Revert "Merge remote-tracking branch 'refs/remotes/cros/upstream/glk-003-drop-stable'"
This reverts commit 2f3a03f1b0ef5b00e8de4fa5079fb2885fcf66c2, reversing
changes made to b3a8ce9a2a63ca4f8dec7500347c711055251f7b.
Revert release so this repo can start tracking upstream
TEST=N/A
BUG=b:132848755
Change-Id: I4c70c18645f1e4763a95dd0395fbf3fce7d1f903
Signed-off-by: Curtis Malainey <cujomalainey@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/third_party/sound-open-firmware/+/1834244
Reviewed-by: Dylan Reid <dgreid@chromium.org>
diff --git a/.gitignore b/.gitignore
deleted file mode 100644
index 3adb154..0000000
--- a/.gitignore
+++ /dev/null
@@ -1,60 +0,0 @@
-*.o
-*.Po
-*~
-*.a
-*.la
-*.lo
-*.Tpo
-*.swp
-*.bin
-*.map
-*.ri
-*.orig
-*.rej
-*.rom
-*.man
-.version
-.tarball-version
-*.x
-.build
-*.dis
-*.lst
-*.log
-.*
-
-Makefile
-Makefile.in
-configure
-depcomp
-aclocal.m4
-install-sh
-missing
-compile
-ar-lib
-stamp-h1
-CHANGELOG
-ltmain.sh
-m4/lt*
-m4/libtool.m4
-libtool
-src/include/version.h
-doc/doxygen
-*.doxygen
-
-autom4te*
-config.*
-*.gz
-*.xz
-src/arch/xtensa/sof
-src/arch/xtensa/boot_ldr
-sof-*
-boot_ldr-*
-boot_module
-module
-rimage/rimage
-
-tap-driver.sh
-test-driver
-test/*.log
-test/*.trs
-
diff --git a/.travis.yml b/.travis.yml
deleted file mode 100644
index b8354f1..0000000
--- a/.travis.yml
+++ /dev/null
@@ -1,12 +0,0 @@
-sudo: required
-
-language: c
-
-services:
- - docker
-
-before_install:
- - docker pull xiulipan/sof
-
-script:
- - docker run -it -v `pwd`:/home/sof/work/sof.git -v `pwd`/../soft.git:/home/sof/work/soft.git --user `id -u` xiulipan/sof ./scripts/xtensa-build-all.sh -l
diff --git a/LICENCE b/LICENCE
deleted file mode 100644
index 8f532c5..0000000
--- a/LICENCE
+++ /dev/null
@@ -1,53 +0,0 @@
-/*
- * BSD 3 Clause
- * Copyright (c) 2016, Intel Corporation
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- *
- * 1. Redistributions of source code must retain the above copyright notice,
- * this list of conditions and the following disclaimer.
- *
- * 2. Redistributions in binary form must reproduce the above copyright notice,
- * this list of conditions and the following disclaimer in the documentation
- * and/or other materials provided with the distribution.
- *
- * 3. Neither the name of the copyright holder nor the names of its
- * contributors may be used to endorse or promote products derived from this
- * software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
- * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
- * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
- * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
- * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
- * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
- * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
- * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
- * POSSIBILITY OF SUCH DAMAGE.
- */
-
-
-// Copyright (c) 2003-2014 Cadence Design Systems, Inc.
-//
-// Permission is hereby granted, free of charge, to any person obtaining
-// a copy of this software and associated documentation files (the
-// "Software"), to deal in the Software without restriction, including
-// without limitation the rights to use, copy, modify, merge, publish,
-// distribute, sublicense, and/or sell copies of the Software, and to
-// permit persons to whom the Software is furnished to do so, subject to
-// the following conditions:
-//
-// The above copyright notice and this permission notice shall be included
-// in all copies or substantial portions of the Software.
-//
-// THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
-// EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
-// MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
-// IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY
-// CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
-// TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
-// SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
diff --git a/Makefile.am b/Makefile.am
deleted file mode 100644
index 6be7c8e..0000000
--- a/Makefile.am
+++ /dev/null
@@ -1,76 +0,0 @@
-if BUILD_RIMAGE
-SUBDIRS = rimage
-else
-SUBDIRS = doc src test
-endif
-
-ACLOCAL_AMFLAGS = -I m4
-
-EXTRA_DIST = version.sh
-
-SRC_DIR = $(abs_top_builddir)/src
-
-if BUILD_HOST
-export ARCH_INCDIR = \
- -I $(SRC_DIR)/arch/$(ARCH)/include
-
-export SOF_INCDIR = \
- -I $(SRC_DIR)/include
-
-if BUILD_LIB
-export PLATFORM_INCDIR = \
- -I $(SRC_DIR)/library/include
-endif
-
-else
-export SOF_INCDIR = \
- -I $(SRC_DIR)/include \
- -I $(ROOT_DIR)/include
-
-ARCH_INCDIR = -I $(SRC_DIR)/arch/$(ARCH)/include
-
-if BUILD_XTENSA_SMP
-ARCH_INCDIR += \
- -I $(SRC_DIR)/arch/$(ARCH)/smp/include \
- -I $(SRC_DIR)/arch/$(ARCH)/smp/xtos
-else
-ARCH_INCDIR += \
- -I $(SRC_DIR)/arch/$(ARCH)/up/include \
- -I $(SRC_DIR)/arch/$(ARCH)/up/xtos
-endif
-
-export ARCH_INCDIR
-
-PLATFORM_INCDIR = -I $(SRC_DIR)/platform/$(PLATFORM)/include
-
-if BUILD_CAVS
-PLATFORM_INCDIR += \
- -I $(SRC_DIR)/platform/intel/include
-endif
-
-if XCC
-PLATFORM_INCDIR += \
- -I $(ROOT_DIR)/arch/include
-else
-PLATFORM_INCDIR += \
- -I $(SRC_DIR)/platform/$(PLATFORM)/include/arch
-endif
-
-export PLATFORM_INCDIR
-
-endif
-
-dist-hook:
- ./version.sh $(top_srcdir)
- cat .version > $(distdir)/.tarball-version
- cat .version > $(distdir)/.version
-
-doc-dummy:
-
-doc: doc-dummy
- $(MAKE) -C doc doc
-
-if !BUILD_RIMAGE
-all-local:
- rm -f $(top_srcdir)/src/include/version.h
-endif
diff --git a/README b/README
deleted file mode 100644
index c2ac1ca..0000000
--- a/README
+++ /dev/null
@@ -1,33 +0,0 @@
-
-Build Instructions
-
-1) Run "autogen.sh"
-
-2) Build and install the rimage ELF image creator and signing tool
-
-./configure --enable-rimage
-make
-sudo make install
-
-3) Run the following configure based on your platform.
-
-Baytrail :-
-
-./configure --with-arch=xtensa --with-platform=baytrail --with-root-dir=$PWD/../xtensa-root/xtensa-byt-elf --host=xtensa-byt-elf
-
-Cherrytrail :-
-
-./configure --with-arch=xtensa --with-platform=cherrytrail --with-root-dir=$PWD/../xtensa-root/xtensa-byt-elf --host=xtensa-byt-elf
-
-Library for Host Platform :-
-If building library for host platform, run the following configure. Please modify
-the --prefix option to choose the directory for installing the library files and
-headers
-
-./configure --with-arch=host --enable-library=yes --host=x86_64-unknown-linux-gnu --prefix=$PWD/../host-root/
-
-4) make
-
-5) make bin
-
-
diff --git a/autogen.sh b/autogen.sh
deleted file mode 100755
index 62683b0..0000000
--- a/autogen.sh
+++ /dev/null
@@ -1,13 +0,0 @@
-#!/bin/bash
-rm -f .build
-if [ ! -f .git/hooks/pre-commit ]; then
- ln -s -f ../../scripts/sof-pre-commit-hook.sh .git/hooks/pre-commit
-fi
-if [ ! -f .git/hooks/post-commit ]; then
- ln -s -f ../../scripts/sof-post-commit-hook.sh .git/hooks/post-commit
-fi
-libtoolize -c --force
-aclocal -I m4 --install
-autoconf -Wall
-autoheader
-automake -a --copy --foreign --add-missing
diff --git a/configure.ac b/configure.ac
deleted file mode 100644
index f7a75fe..0000000
--- a/configure.ac
+++ /dev/null
@@ -1,526 +0,0 @@
-AC_PREREQ([2.69])
-AC_INIT([sof],[m4_esyscmd(./version.sh)],[sound-open-firmware@alsa-project.org])
-AC_CONFIG_SRCDIR([src/init/init.c])
-AC_CONFIG_HEADERS([src/include/config.h])
-AC_CONFIG_MACRO_DIRS([m4])
-AM_INIT_AUTOMAKE([foreign 1.11 -Wall -Wno-portability subdir-objects silent-rules color-tests dist-xz tar-ustar])
-
-# Initialize maintainer mode
-AM_MAINTAINER_MODE([enable])
-
-# get version info from git
-m4_define(sof_major, `cat .version | cut -dv -f2 | cut -d. -f1`)
-m4_define(sof_minor, `cat .version | cut -d. -f2 | cut -d- -f1`)
-m4_define(sof_micro, `cat .version | cut -d. -f3 | cut -d- -f1`)
-AC_DEFINE_UNQUOTED([SOF_MAJOR], sof_major, [Sof major version])
-AC_DEFINE_UNQUOTED([SOF_MINOR], sof_minor, [Sof minor version])
-AC_DEFINE_UNQUOTED([SOF_MICRO], sof_micro, [Sof micro version])
-
-AC_CANONICAL_HOST
-
-# General assembler flags
-ASFLAGS="-DASSEMBLY"
-AC_SUBST(ASFLAGS)
-
-# Cross compiler tool libgcc and headers
-AC_ARG_WITH([root-dir],
- AS_HELP_STRING([--with-root-dir], [Specify location of cross gcc libraries and headers]),
- [], [with_root_dir=no])
-
-# MEU location
-AC_ARG_WITH([meu],
- AS_HELP_STRING([--with-meu], [Specify location of MEU tool]),
- [], [with_meu=no])
-if test "x$with_meu" != "xno"; then
- MEU_PATH="$with_meu"
- AC_SUBST(MEU_PATH)
-
- MEU_VERSION=$($with_meu/meu -ver | grep "Version:" | cut -d" " -f6)
- AX_COMPARE_VERSION([$MEU_VERSION], [ge], [12.0.0.1035], [MEU_OFFSET=1088], [MEU_OFFSET=1152])
- AC_SUBST(MEU_OFFSET)
-fi
-AM_CONDITIONAL(USE_MEU, test "x$with_meu" != "xno")
-
-# Private key location
-AC_ARG_WITH([key],
- AS_HELP_STRING([--with-key], [Specify location of private key]),
- [], [with_key=no])
-if test "x$with_meu" != "xno"; then
- if test "x$with_key" != "xno"; then
- PRIVATE_KEY="$with_key"
- AC_SUBST(PRIVATE_KEY)
- else
- AC_MSG_ERROR([Private key location not specified])
- fi
-fi
-
-# check if we are building FW image or library
-AC_ARG_ENABLE(library, [AS_HELP_STRING([--enable-library],[build library])], have_library=$enableval, have_library=no)
-if test "$have_library" = "yes"; then
- AC_DEFINE([CONFIG_LIB], [1], [Configure for Shared Library])
-fi
-AM_CONDITIONAL(BUILD_LIB, test "$have_library" = "yes")
-
-# check if we are building tools
-AC_ARG_ENABLE(rimage, [AS_HELP_STRING([--enable-rimage],[build rimage tool])], have_rimage=$enableval, have_rimage=no)
-if test "$have_rimage" = "yes"; then
- AC_DEFINE([CONFIG_RIMAGE], [1], [Configure to build rimage])
- AM_CFLAGS="-O2 -g -Wall -Werror -Wl,-EL -Wmissing-prototypes"
-fi
-AM_CONDITIONAL(BUILD_RIMAGE, test "$have_rimage" = "yes")
-
-# check if we are building docs
-AC_ARG_ENABLE(doc, [AS_HELP_STRING([--enable-doc],[build doc])], have_doc=$enableval, have_doc=no)
-if test "$have_doc" = "yes"; then
- AC_DEFINE([CONFIG_DOC], [1], [Configure to build doc])
-fi
-AM_CONDITIONAL(BUILD_DOC, test "$have_doc" = "yes")
-
-# Disable DMIC driver if requested, by default build for supported platforms
-AC_ARG_ENABLE([dmic], AS_HELP_STRING([--disable-dmic], [Disable DMIC driver]))
-AS_IF([test "x$enable_dmic" != "xno"], [
- AC_DEFINE([CONFIG_DMIC], [1], [Configure to build DMIC driver])
-])
-
-# Architecture support
-AC_ARG_WITH([arch],
- AS_HELP_STRING([--with-arch], [Specify DSP architecture]),
- [], [with_arch=no])
-
-case "$with_arch" in
- xtensa*)
-
- ARCH_CFLAGS="-mtext-section-literals"
-
- ARCH_LDFLAGS="-nostdlib -Wl,--no-check-sections -u call_user_start -Wl,-static"
-
- # automake FLAGS defined here
- AM_CFLAGS="-fno-inline-functions -nostdlib -mlongcalls"
- AM_LDFLAGS=""
- AM_CCASFLAGS=""
-
- # GCC needs these additional flags on top of any user flags.
- CFLAGS="${CFLAGS:+$CFLAGS } -O2 -g -Wall -Werror -Wl,-EL -Wmissing-prototypes"
- LDFLAGS="${LDFLAGS:+$LDFLAGS } -nostdlib"
- CCASFLAGS="${CCASFLAGS:+$CCASFLAGS } -fno-inline-functions -nostdlib -mlongcalls"
-
- ARCH="xtensa"
- AC_SUBST(ARCH)
-
- AS_IF([test "x$with_root_dir" = xno],
- AC_MSG_ERROR([Please specify cross compiler root header directory]),
- [ROOT_DIR=$with_root_dir])
- AC_SUBST(ROOT_DIR)
- ;;
- host*)
-
- ARCH_CFLAGS="-g"
-
- # automake FLAGS defined here
- AM_CFLAGS="-O3 -Wall -Werror -Wl,-EL -Wmissing-prototypes"
- AM_LDFLAGS="-lpthread"
- AM_CCASFLAGS="-O3 -Wall -Werror -Wl,-EL -Wmissing-prototypes"
-
- ARCH="host"
- AC_SUBST(ARCH)
- ;;
- *)
- if test "$have_rimage" = "no" && test "$have_doc" = "no" ; then
- AC_MSG_ERROR([DSP architecture not specified])
- fi
- ;;
-esac
-
-AC_SUBST(ARCH_CFLAGS)
-AC_SUBST(ARCH_LDFLAGS)
-
-AC_SUBST(AM_CFLAGS)
-AC_SUBST(AM_LDFLAGS)
-AC_SUBST(AM_CCASFLAGS)
-
-AM_CONDITIONAL(BUILD_XTENSA, test "$ARCH" = "xtensa")
-AM_CONDITIONAL(BUILD_HOST, test "$ARCH" = "host")
-
-# check for xtensa extension
-AM_CONDITIONAL(BUILD_XTENSA_SMP, test "$with_arch" = "xtensa-smp")
-
-# Cmocka tests
-AC_ARG_WITH([cmocka-prefix],
- AS_HELP_STRING([--with-cmocka-prefix], [Path to cmocka]),
- [], [with_cmocka_prefix="no"])
-
-# in case of native build, cmocka may be installed
-HAVE_CMOCKA_PKG=no
-AC_CHECK_LIB(cmocka, _cmocka_run_group_tests, [HAVE_CMOCKA_PKG=yes])
-
-if test "x$with_arch" != "xno"; then
- if test "x$with_cmocka_prefix" = "xno"; then
- if test "$ARCH" = "xtensa"; then
- AC_MSG_WARN([Need cmocka to run unit tests. Path to cmocka not specified. Please use --with-cmocka-prefix option.])
- elif test "x$HAVE_CMOCKA_PKG" = "xno"; then
- AC_MSG_WARN([Need cmocka to run unit tests. No cmocka library found. Please install cmocka or use --with-cmocka-prefix option.])
- fi
- else
- CMOCKA_PREFIX="$with_cmocka_prefix"
- AC_SUBST(CMOCKA_PREFIX)
- fi
-fi
-
-AM_CONDITIONAL(HAVE_CMOCKA_PREFIX, test "x$with_cmocka_prefix" != "xno")
-
-# Platform support
-AC_ARG_WITH([platform],
- AS_HELP_STRING([--with-platform], [Specify Host Platform]),
- [], [with_platform=no])
-
-case "$with_platform" in
- baytrail*)
-
- PLATFORM_LDSCRIPT="baytrail.x"
- AC_SUBST(PLATFORM_LDSCRIPT)
-
- PLATFORM="baytrail"
- AC_SUBST(PLATFORM)
-
- FW_NAME="byt"
- AC_SUBST(FW_NAME)
-
- XTENSA_CORE="hifiep_bd5"
- AC_SUBST(XTENSA_CORE)
-
- AC_DEFINE([CONFIG_BAYTRAIL], [1], [Configure for Baytrail])
- AC_DEFINE([CONFIG_HOST_PTABLE], [1], [Configure handling host page table])
- ;;
- cherrytrail*)
-
- PLATFORM_LDSCRIPT="baytrail.x"
- AC_SUBST(PLATFORM_LDSCRIPT)
-
- PLATFORM="baytrail"
- AC_SUBST(PLATFORM)
-
- FW_NAME="cht"
- AC_SUBST(FW_NAME)
-
- XTENSA_CORE="hifiep_bd5"
- AC_SUBST(XTENSA_CORE)
-
- AC_DEFINE([CONFIG_CHERRYTRAIL], [1], [Configure for Cherrytrail])
- AC_DEFINE([CONFIG_HOST_PTABLE], [1], [Configure handling host page table])
- ;;
- apollolake*)
-
- PLATFORM_LDSCRIPT="apollolake.x"
- AC_SUBST(PLATFORM_LDSCRIPT)
-
- PLATFORM="apollolake"
- AC_SUBST(PLATFORM)
-
- FW_NAME="apl"
- AC_SUBST(FW_NAME)
-
- XTENSA_CORE="hifi3_std"
- AC_SUBST(XTENSA_CORE)
-
- AC_DEFINE([CONFIG_APOLLOLAKE], [1], [Configure for Apololake])
- AC_DEFINE([CONFIG_BOOT_LOADER], [1], [Configure Boot Loader])
- AC_DEFINE([CONFIG_IRQ_MAP], [1], [Configure IRQ maps])
- AC_DEFINE([CONFIG_DMA_GW], [1], [Configure DMA Gateway])
- ;;
- haswell*)
-
- PLATFORM_LDSCRIPT="haswell.x"
- AC_SUBST(PLATFORM_LDSCRIPT)
-
- PLATFORM="haswell"
- AC_SUBST(PLATFORM)
-
- FW_NAME="hsw"
- AC_SUBST(FW_NAME)
-
- XTENSA_CORE="hifiep_bd5"
- AC_SUBST(XTENSA_CORE)
-
- AC_DEFINE([CONFIG_HASWELL], [1], [Configure for Haswell])
- AC_DEFINE([CONFIG_HOST_PTABLE], [1], [Configure handling host page table])
- ;;
- broadwell*)
-
- PLATFORM_LDSCRIPT="broadwell.x"
- AC_SUBST(PLATFORM_LDSCRIPT)
-
- PLATFORM="haswell"
- AC_SUBST(PLATFORM)
-
- FW_NAME="bdw"
- AC_SUBST(FW_NAME)
-
- XTENSA_CORE="hifiep_bd5"
- AC_SUBST(XTENSA_CORE)
-
- AC_DEFINE([CONFIG_BROADWELL], [1], [Configure for Broadwell])
- AC_DEFINE([CONFIG_HOST_PTABLE], [1], [Configure handling host page table])
- ;;
- cannonlake*)
-
- PLATFORM_LDSCRIPT="cannonlake.x"
- AC_SUBST(PLATFORM_LDSCRIPT)
-
- PLATFORM="cannonlake"
- AC_SUBST(PLATFORM)
-
- FW_NAME="cnl"
- AC_SUBST(FW_NAME)
-
- XTENSA_CORE="hifi4_std"
- AC_SUBST(XTENSA_CORE)
-
- AC_DEFINE([CONFIG_CANNONLAKE], [1], [Configure for Cannonlake])
- AC_DEFINE([CONFIG_BOOT_LOADER], [1], [Configure Boot Loader])
- AC_DEFINE([CONFIG_IRQ_MAP], [1], [Configure IRQ maps])
- AC_DEFINE([CONFIG_DMA_GW], [1], [Configure DMA Gateway])
- ;;
- *)
- if test "$have_rimage" = "no" && test "$have_doc" = "no"; then
- if test "$ARCH" = "host"; then
- PLATFORM="host"
- AC_SUBST(PLATFORM)
- else
- AC_MSG_ERROR([Host platform not specified])
- fi
- fi
- ;;
-esac
-
-AM_CONDITIONAL(BUILD_BAYTRAIL, test "$FW_NAME" = "byt")
-AM_CONDITIONAL(BUILD_CHERRYTRAIL, test "$FW_NAME" = "cht")
-AM_CONDITIONAL(BUILD_HASWELL, test "$FW_NAME" = "hsw")
-AM_CONDITIONAL(BUILD_BROADWELL, test "$FW_NAME" = "bdw")
-AM_CONDITIONAL(BUILD_APOLLOLAKE, test "$FW_NAME" = "apl")
-AM_CONDITIONAL(BUILD_CANNONLAKE, test "$FW_NAME" = "cnl")
-AM_CONDITIONAL(BUILD_BOOTLOADER, test "$FW_NAME" = "apl" -o "$FW_NAME" = "cnl")
-AM_CONDITIONAL(BUILD_CAVS, test "$FW_NAME" = "apl" -o "$FW_NAME" = "cnl")
-AM_CONDITIONAL(BUILD_MODULE, test "$FW_NAME" = "apl" -o "$FW_NAME" = "cnl")
-AM_CONDITIONAL(BUILD_APL_SSP, test "$FW_NAME" = "apl" -o "$FW_NAME" = "cnl")
-
-# DSP core support (Optional)
-AC_ARG_WITH([dsp-core],
- AS_HELP_STRING([--with-dsp-core], [Specify DSP Core]),
- [], [with_dsp_core=no])
-
-case "$with_dsp_core" in
- *)
- XTENSA_CORE="$with_dsp_core"
- AC_SUBST(XTENSA_CORE)
- ;;
-
-esac
-
-PLATFORM_BOOT_LDR_LDSCRIPT="boot_ldr.x"
-AC_SUBST(PLATFORM_BOOT_LDR_LDSCRIPT)
-
-# Optimisation settings and checks
-
-# SSE4_2 support
-AC_ARG_ENABLE(sse42, [AS_HELP_STRING([--enable-sse42],[enable SSE42 optimizations])], have_sse42=$enableval, have_sse42=yes)
-AX_CHECK_COMPILE_FLAG(-msse4.2, [SSE42_CFLAGS="-DOPS_SSE42 -msse4.2 -ffast-math -ftree-vectorizer-verbose=0"],
- [have_sse42=no])
-if test "$have_sse42" = "yes"; then
- AC_DEFINE(HAVE_SSE42,1,[Define to enable SSE42 optimizations.])
-fi
-AM_CONDITIONAL(HAVE_SSE42, test "$have_sse42" = "yes")
-AC_SUBST(SSE42_CFLAGS)
-
-# AVX support
-AC_ARG_ENABLE(avx, [AS_HELP_STRING([--enable-avx],[enable AVX optimizations])], have_avx=$enableval, have_avx=yes)
-AX_CHECK_COMPILE_FLAG(-mavx, [AVX_CFLAGS="-DOPS_AVX -mavx -ffast-math -ftree-vectorizer-verbose=0"],
- [have_avx=no])
-if test "$have_avx" = "yes"; then
- AC_DEFINE(HAVE_AVX,1,[Define to enable AVX optimizations.])
-fi
-AM_CONDITIONAL(HAVE_AVX, test "$have_avx" = "yes")
-AC_SUBST(AVX_CFLAGS)
-
-
-# AVX2 support
-AC_ARG_ENABLE(avx2, [AS_HELP_STRING([--enable-avx2],[enable AVX2 optimizations])], have_avx2=$enableval, have_avx2=yes)
-AX_CHECK_COMPILE_FLAG(-mavx2, [AVX2_CFLAGS="-DOPS_AVX2 -mavx2 -ffast-math -ftree-vectorizer-verbose=0"],
- [have_avx2=no])
-if test "$have_avx2" = "yes"; then
- AC_DEFINE(HAVE_AVX2,1,[Define to enable AVX2 optimizations.])
-fi
-AM_CONDITIONAL(HAVE_AVX2, test "$have_avx2" = "yes")
-AC_SUBST(AVX2_CFLAGS)
-
-
-# FMA support
-AC_ARG_ENABLE(fma, [AS_HELP_STRING([--enable-fma],[enable FMA optimizations])], have_fma=$enableval, have_fma=yes)
-AX_CHECK_COMPILE_FLAG(-mfma, [FMA_CFLAGS="-DOPS_FMA -mfma -ffast-math -ftree-vectorizer-verbose=0"],
- [have_fma=no])
-if test "$have_fma" = "yes"; then
- AC_DEFINE(HAVE_FMA,1,[Define to enable FMA optimizations.])
-fi
-AM_CONDITIONAL(HAVE_FMA, test "$have_fma" = "yes")
-AC_SUBST(FMA_CFLAGS)
-
-# Hifi2EP
-AC_ARG_ENABLE(hifi2ep, [AS_HELP_STRING([--enable-hifi2ep],[enable HiFi2EP optimizations])], have_hifi2ep=$enableval, have_hifi2ep=yes)
-AX_CHECK_COMPILE_FLAG(-mhifi2ep, [FMA_CFLAGS="-DOPS_HIFI2EP -mhifi2ep -ffast-math -ftree-vectorizer-verbose=0"],
- [have_hifi2ep=no])
-if test "$have_hifi2ep" = "yes"; then
- AC_DEFINE(HAVE_HIFI2EP,1,[Define to enable Hifi2 EP optimizations.])
-fi
-AM_CONDITIONAL(HAVE_HIFI2EP, test "$have_hifi2ep" = "yes")
-AC_SUBST(HIFI2EP_CFLAGS)
-
-# Hifi3
-AC_ARG_ENABLE(hifi3, [AS_HELP_STRING([--enable-hifi3],[enable HiFi3 optimizations])], have_hifi3=$enableval, have_hifi3=yes)
-AX_CHECK_COMPILE_FLAG(-mhihi3, [FMA_CFLAGS="-DOPS_HIFI3 -mhifi3 -ffast-math -ftree-vectorizer-verbose=0"],
- [have_hifi3=no])
-if test "$have_hifi3" = "yes"; then
- AC_DEFINE(HAVE_HIFI3,1,[Define to enable Hifi3 optimizations.])
-fi
-AM_CONDITIONAL(HAVE_HIFI3, test "$have_hifi3" = "yes")
-AC_SUBST(HIFI3_CFLAGS)
-
-# Test after CFLAGS set othewise test of cross compiler fails.
-AM_PROG_AS
-AM_PROG_AR
-AC_PROG_CC
-LT_INIT
-AC_CHECK_TOOL([OBJCOPY], [objcopy], [])
-AC_CHECK_TOOL([OBJDUMP], [objdump], [])
-
-# Check for openssl - used by rimage
-AC_CHECK_LIB([crypto], [OPENSSL_config], , [have_openssl="no"])
-if test "$have_rimage" = "yes"; then
- if test "$have_openssl" = "no"; then
- AC_MSG_ERROR([Need OpenSSL libcrypto for rimage code signing])
- fi
-fi
-
-if test "x$prefix" == "xNONE"; then
-PEM_KEY_PREFIX="/usr/local/share/rimage"
-else
-PEM_KEY_PREFIX=$prefix"/share/rimage"
-fi
-AC_DEFINE_UNQUOTED([PEM_KEY_PREFIX], ["$PEM_KEY_PREFIX"], ["Path for PEM keys"])
-AC_SUBST(PEM_KEY_PREFIX)
-
-# Check for doxygen and graphviz - used by make doc
-AC_CHECK_PROG(have_doxygen, doxygen, true, false)
-if test "$have_doxygen" = "false"; then
- AC_MSG_WARN([Need doxygen to build documentation])
-fi
-AC_CHECK_PROG(have_graphviz, dot, true, false)
-if test "$have_graphviz" = "false"; then
- AC_MSG_WARN([Need graphviz to build documentation])
-fi
-
-# Check for compiler type
-AM_CONDITIONAL(XCC, test "$CC" = "xt-xcc")
-
-AM_EXTRA_RECURSIVE_TARGETS([bin])
-
-AM_EXTRA_RECURSIVE_TARGETS([vminstall])
-
-AC_CONFIG_FILES([
- Makefile
- rimage/Makefile
- rimage/keys/Makefile
- doc/Makefile
- src/Makefile
- src/tasks/Makefile
- src/init/Makefile
- src/arch/Makefile
- src/arch/xtensa/Makefile
- src/arch/xtensa/include/Makefile
- src/arch/xtensa/include/arch/Makefile
- src/arch/xtensa/include/xtensa/Makefile
- src/arch/xtensa/include/xtensa/config/Makefile
- src/arch/xtensa/smp/Makefile
- src/arch/xtensa/smp/hal/Makefile
- src/arch/xtensa/smp/include/Makefile
- src/arch/xtensa/smp/include/arch/Makefile
- src/arch/xtensa/smp/xtos/Makefile
- src/arch/xtensa/up/Makefile
- src/arch/xtensa/up/hal/Makefile
- src/arch/xtensa/up/include/Makefile
- src/arch/xtensa/up/include/arch/Makefile
- src/arch/xtensa/up/xtos/Makefile
- src/arch/host/Makefile
- src/arch/host/include/Makefile
- src/arch/host/include/arch/Makefile
- src/audio/Makefile
- src/math/Makefile
- src/drivers/Makefile
- src/include/Makefile
- src/include/sof/Makefile
- src/include/sof/audio/Makefile
- src/include/sof/audio/coefficients/Makefile
- src/include/sof/audio/coefficients/src/Makefile
- src/include/sof/math/Makefile
- src/include/uapi/Makefile
- src/ipc/Makefile
- src/library/Makefile
- src/library/include/Makefile
- src/library/include/platform/Makefile
- src/lib/Makefile
- src/host/Makefile
- src/platform/Makefile
- src/platform/baytrail/Makefile
- src/platform/baytrail/include/Makefile
- src/platform/baytrail/include/arch/Makefile
- src/platform/baytrail/include/arch/xtensa/Makefile
- src/platform/baytrail/include/arch/xtensa/config/Makefile
- src/platform/baytrail/include/platform/Makefile
- src/platform/apollolake/Makefile
- src/platform/apollolake/include/Makefile
- src/platform/apollolake/include/arch/Makefile
- src/platform/apollolake/include/arch/xtensa/Makefile
- src/platform/apollolake/include/arch/xtensa/config/Makefile
- src/platform/apollolake/include/platform/Makefile
- src/platform/haswell/Makefile
- src/platform/haswell/include/Makefile
- src/platform/haswell/include/arch/Makefile
- src/platform/haswell/include/arch/xtensa/Makefile
- src/platform/haswell/include/arch/xtensa/config/Makefile
- src/platform/haswell/include/platform/Makefile
- src/platform/cannonlake/Makefile
- src/platform/cannonlake/include/Makefile
- src/platform/cannonlake/include/arch/Makefile
- src/platform/cannonlake/include/arch/xtensa/Makefile
- src/platform/cannonlake/include/arch/xtensa/config/Makefile
- src/platform/cannonlake/include/platform/Makefile
- src/platform/intel/Makefile
- src/platform/intel/cavs/Makefile
- src/platform/intel/include/Makefile
- src/platform/intel/include/platform/Makefile
- src/platform/intel/include/platform/cavs/Makefile
- test/Makefile
- test/cmocka/Makefile
-])
-AC_REQUIRE_AUX_FILE([tap-driver.sh])
-AC_OUTPUT
-
-echo "
----{ $PACKAGE_NAME $VERSION }---
-
-Target Architecture: ${ARCH}
-Target Platform: ${PLATFORM}
-Target Core: ${XTENSA_CORE}
-Install Prefix: ${prefix}
-PEM: ${PEM_KEY_PREFIX}
-
-Compiler: ${CC}
-OBJCOPY: ${OBJCOPY}
-OBJDUMP: ${OBJDUMP}
-CFLAGS: ${CFLAGS}
-LDFLAGS: ${LDFLAGS}
-ARCH_CFLAGS: ${ARCH_CFLAGS}
-ARCH_LDFLAGS: ${ARCH_LDFLAGS}
-A@&t@M_CFLAGS: ${AM_CFLAGS}
-A@&t@M_LDFLAGS: ${AM_LDFLAGS}
-A@&t@M_CCASFLAGS: ${AM_CCASFLAGS}
-"
-
diff --git a/doc/Makefile.am b/doc/Makefile.am
deleted file mode 100644
index f3db658..0000000
--- a/doc/Makefile.am
+++ /dev/null
@@ -1,10 +0,0 @@
-EXTRA_DIST=sof.doxygen.in
-
-AM_CPPFLAGS=-I$(top_srcdir)/include
-
-doc:
- test -e sof.doxygen || sed s:[@]top_srcdir[@]:..:g sof.doxygen.in > sof.doxygen
- doxygen sof.doxygen
-
-doc-clean:
- rm -rf $(top_srcdir)/doc/doxygen/*
diff --git a/doc/README-HOST b/doc/README-HOST
deleted file mode 100644
index 30ad583..0000000
--- a/doc/README-HOST
+++ /dev/null
@@ -1,23 +0,0 @@
-The host testbench is meant to serve as a vehicle to test components for functionality
-and quality of processed samples.
-
-Compilation steps:
-
-Run the host-build-all.sh to build the required libraries for the testbench.
-It should also build the testbench executable.
-
-Running the Testbench:
-
-The test can be invoked by running the "testbench" bin in the src/host directory.
-
-Compile and run using script provided (Recommended):
-
-Set up the input arguments for the test in
-"host-testbench.sh" and invoke it to compile the host libraries
-and execute the testbench.
-
-Known Limitations:
-
-1. Currently, testbench code supports simple volume topologies only.
-
-2. When setting up arguments, please keep the same file format for input and output files
diff --git a/doc/README.host b/doc/README.host
deleted file mode 100644
index 30ad583..0000000
--- a/doc/README.host
+++ /dev/null
@@ -1,23 +0,0 @@
-The host testbench is meant to serve as a vehicle to test components for functionality
-and quality of processed samples.
-
-Compilation steps:
-
-Run the host-build-all.sh to build the required libraries for the testbench.
-It should also build the testbench executable.
-
-Running the Testbench:
-
-The test can be invoked by running the "testbench" bin in the src/host directory.
-
-Compile and run using script provided (Recommended):
-
-Set up the input arguments for the test in
-"host-testbench.sh" and invoke it to compile the host libraries
-and execute the testbench.
-
-Known Limitations:
-
-1. Currently, testbench code supports simple volume topologies only.
-
-2. When setting up arguments, please keep the same file format for input and output files
diff --git a/doc/sof.doxygen.in b/doc/sof.doxygen.in
deleted file mode 100644
index 9751e00..0000000
--- a/doc/sof.doxygen.in
+++ /dev/null
@@ -1,35 +0,0 @@
-PROJECT_NAME = "Sound Open Firmware"
-OUTPUT_DIRECTORY = doxygen
-GENERATE_LATEX = NO
-GENERATE_RTF = NO
-GENERATE_MAN = NO
-GENERATE_XML = YES
-
-CASE_SENSE_NAMES = NO
-INPUT = @top_srcdir@/src/include/uapi \
- @top_srcdir@/src/include/sof
-EXCLUDE =
-RECURSIVE = YES
-FILE_PATTERNS = *.c *.h
-EXAMPLE_PATH = ../test
-IMAGE_PATH =
-QUIET = YES
-
-EXTRACT_ALL = NO
-EXTRACT_STATIC = NO
-WARN_IF_UNDOCUMENTED = NO
-SHOW_INCLUDE_FILES = NO
-JAVADOC_AUTOBRIEF = NO
-INHERIT_DOCS = YES
-ENABLED_SECTIONS = ""
-MACRO_EXPANSION = YES
-EXPAND_ONLY_PREDEF = YES
-PREDEFINED = __attribute__(x)=
-
-OPTIMIZE_OUTPUT_FOR_C = YES
-TYPEDEF_HIDES_STRUCT = YES
-
-#INPUT_FILTER = inputfilter
-#FILTER_SOURCE_FILES = YES
-
-HTML_TIMESTAMP = NO
diff --git a/m4/ax_check_compile_flag.m4 b/m4/ax_check_compile_flag.m4
deleted file mode 100644
index dcabb92..0000000
--- a/m4/ax_check_compile_flag.m4
+++ /dev/null
@@ -1,74 +0,0 @@
-# ===========================================================================
-# https://www.gnu.org/software/autoconf-archive/ax_check_compile_flag.html
-# ===========================================================================
-#
-# SYNOPSIS
-#
-# AX_CHECK_COMPILE_FLAG(FLAG, [ACTION-SUCCESS], [ACTION-FAILURE], [EXTRA-FLAGS], [INPUT])
-#
-# DESCRIPTION
-#
-# Check whether the given FLAG works with the current language's compiler
-# or gives an error. (Warnings, however, are ignored)
-#
-# ACTION-SUCCESS/ACTION-FAILURE are shell commands to execute on
-# success/failure.
-#
-# If EXTRA-FLAGS is defined, it is added to the current language's default
-# flags (e.g. CFLAGS) when the check is done. The check is thus made with
-# the flags: "CFLAGS EXTRA-FLAGS FLAG". This can for example be used to
-# force the compiler to issue an error when a bad flag is given.
-#
-# INPUT gives an alternative input source to AC_COMPILE_IFELSE.
-#
-# NOTE: Implementation based on AX_CFLAGS_GCC_OPTION. Please keep this
-# macro in sync with AX_CHECK_{PREPROC,LINK}_FLAG.
-#
-# LICENSE
-#
-# Copyright (c) 2008 Guido U. Draheim <guidod@gmx.de>
-# Copyright (c) 2011 Maarten Bosmans <mkbosmans@gmail.com>
-#
-# This program is free software: you can redistribute it and/or modify it
-# under the terms of the GNU General Public License as published by the
-# Free Software Foundation, either version 3 of the License, or (at your
-# option) any later version.
-#
-# This program is distributed in the hope that it will be useful, but
-# WITHOUT ANY WARRANTY; without even the implied warranty of
-# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General
-# Public License for more details.
-#
-# You should have received a copy of the GNU General Public License along
-# with this program. If not, see <https://www.gnu.org/licenses/>.
-#
-# As a special exception, the respective Autoconf Macro's copyright owner
-# gives unlimited permission to copy, distribute and modify the configure
-# scripts that are the output of Autoconf when processing the Macro. You
-# need not follow the terms of the GNU General Public License when using
-# or distributing such scripts, even though portions of the text of the
-# Macro appear in them. The GNU General Public License (GPL) does govern
-# all other use of the material that constitutes the Autoconf Macro.
-#
-# This special exception to the GPL applies to versions of the Autoconf
-# Macro released by the Autoconf Archive. When you make and distribute a
-# modified version of the Autoconf Macro, you may extend this special
-# exception to the GPL to apply to your modified version as well.
-
-#serial 5
-
-AC_DEFUN([AX_CHECK_COMPILE_FLAG],
-[AC_PREREQ(2.64)dnl for _AC_LANG_PREFIX and AS_VAR_IF
-AS_VAR_PUSHDEF([CACHEVAR],[ax_cv_check_[]_AC_LANG_ABBREV[]flags_$4_$1])dnl
-AC_CACHE_CHECK([whether _AC_LANG compiler accepts $1], CACHEVAR, [
- ax_check_save_flags=$[]_AC_LANG_PREFIX[]FLAGS
- _AC_LANG_PREFIX[]FLAGS="$[]_AC_LANG_PREFIX[]FLAGS $4 $1"
- AC_COMPILE_IFELSE([m4_default([$5],[AC_LANG_PROGRAM()])],
- [AS_VAR_SET(CACHEVAR,[yes])],
- [AS_VAR_SET(CACHEVAR,[no])])
- _AC_LANG_PREFIX[]FLAGS=$ax_check_save_flags])
-AS_VAR_IF(CACHEVAR,yes,
- [m4_default([$2], :)],
- [m4_default([$3], :)])
-AS_VAR_POPDEF([CACHEVAR])dnl
-])dnl AX_CHECK_COMPILE_FLAGS
diff --git a/m4/ax_compare_version.m4 b/m4/ax_compare_version.m4
deleted file mode 100644
index 6df1c53..0000000
--- a/m4/ax_compare_version.m4
+++ /dev/null
@@ -1,178 +0,0 @@
-# ===========================================================================
-# https://www.gnu.org/software/autoconf-archive/ax_compare_version.html
-# ===========================================================================
-#
-# SYNOPSIS
-#
-# AX_COMPARE_VERSION(VERSION_A, OP, VERSION_B, [ACTION-IF-TRUE], [ACTION-IF-FALSE])
-#
-# DESCRIPTION
-#
-# This macro compares two version strings. Due to the various number of
-# minor-version numbers that can exist, and the fact that string
-# comparisons are not compatible with numeric comparisons, this is not
-# necessarily trivial to do in a autoconf script. This macro makes doing
-# these comparisons easy.
-#
-# The six basic comparisons are available, as well as checking equality
-# limited to a certain number of minor-version levels.
-#
-# The operator OP determines what type of comparison to do, and can be one
-# of:
-#
-# eq - equal (test A == B)
-# ne - not equal (test A != B)
-# le - less than or equal (test A <= B)
-# ge - greater than or equal (test A >= B)
-# lt - less than (test A < B)
-# gt - greater than (test A > B)
-#
-# Additionally, the eq and ne operator can have a number after it to limit
-# the test to that number of minor versions.
-#
-# eq0 - equal up to the length of the shorter version
-# ne0 - not equal up to the length of the shorter version
-# eqN - equal up to N sub-version levels
-# neN - not equal up to N sub-version levels
-#
-# When the condition is true, shell commands ACTION-IF-TRUE are run,
-# otherwise shell commands ACTION-IF-FALSE are run. The environment
-# variable 'ax_compare_version' is always set to either 'true' or 'false'
-# as well.
-#
-# Examples:
-#
-# AX_COMPARE_VERSION([3.15.7],[lt],[3.15.8])
-# AX_COMPARE_VERSION([3.15],[lt],[3.15.8])
-#
-# would both be true.
-#
-# AX_COMPARE_VERSION([3.15.7],[eq],[3.15.8])
-# AX_COMPARE_VERSION([3.15],[gt],[3.15.8])
-#
-# would both be false.
-#
-# AX_COMPARE_VERSION([3.15.7],[eq2],[3.15.8])
-#
-# would be true because it is only comparing two minor versions.
-#
-# AX_COMPARE_VERSION([3.15.7],[eq0],[3.15])
-#
-# would be true because it is only comparing the lesser number of minor
-# versions of the two values.
-#
-# Note: The characters that separate the version numbers do not matter. An
-# empty string is the same as version 0. OP is evaluated by autoconf, not
-# configure, so must be a string, not a variable.
-#
-# The author would like to acknowledge Guido Draheim whose advice about
-# the m4_case and m4_ifvaln functions make this macro only include the
-# portions necessary to perform the specific comparison specified by the
-# OP argument in the final configure script.
-#
-# LICENSE
-#
-# Copyright (c) 2008 Tim Toolan <toolan@ele.uri.edu>
-#
-# Copying and distribution of this file, with or without modification, are
-# permitted in any medium without royalty provided the copyright notice
-# and this notice are preserved. This file is offered as-is, without any
-# warranty.
-
-#serial 13
-
-dnl #########################################################################
-AC_DEFUN([AX_COMPARE_VERSION], [
- AC_REQUIRE([AC_PROG_AWK])
-
- # Used to indicate true or false condition
- ax_compare_version=false
-
- # Convert the two version strings to be compared into a format that
- # allows a simple string comparison. The end result is that a version
- # string of the form 1.12.5-r617 will be converted to the form
- # 0001001200050617. In other words, each number is zero padded to four
- # digits, and non digits are removed.
- AS_VAR_PUSHDEF([A],[ax_compare_version_A])
- A=`echo "$1" | sed -e 's/\([[0-9]]*\)/Z\1Z/g' \
- -e 's/Z\([[0-9]]\)Z/Z0\1Z/g' \
- -e 's/Z\([[0-9]][[0-9]]\)Z/Z0\1Z/g' \
- -e 's/Z\([[0-9]][[0-9]][[0-9]]\)Z/Z0\1Z/g' \
- -e 's/[[^0-9]]//g'`
-
- AS_VAR_PUSHDEF([B],[ax_compare_version_B])
- B=`echo "$3" | sed -e 's/\([[0-9]]*\)/Z\1Z/g' \
- -e 's/Z\([[0-9]]\)Z/Z0\1Z/g' \
- -e 's/Z\([[0-9]][[0-9]]\)Z/Z0\1Z/g' \
- -e 's/Z\([[0-9]][[0-9]][[0-9]]\)Z/Z0\1Z/g' \
- -e 's/[[^0-9]]//g'`
-
- dnl # In the case of le, ge, lt, and gt, the strings are sorted as necessary
- dnl # then the first line is used to determine if the condition is true.
- dnl # The sed right after the echo is to remove any indented white space.
- m4_case(m4_tolower($2),
- [lt],[
- ax_compare_version=`echo "x$A
-x$B" | sed 's/^ *//' | sort -r | sed "s/x${A}/false/;s/x${B}/true/;1q"`
- ],
- [gt],[
- ax_compare_version=`echo "x$A
-x$B" | sed 's/^ *//' | sort | sed "s/x${A}/false/;s/x${B}/true/;1q"`
- ],
- [le],[
- ax_compare_version=`echo "x$A
-x$B" | sed 's/^ *//' | sort | sed "s/x${A}/true/;s/x${B}/false/;1q"`
- ],
- [ge],[
- ax_compare_version=`echo "x$A
-x$B" | sed 's/^ *//' | sort -r | sed "s/x${A}/true/;s/x${B}/false/;1q"`
- ],[
- dnl Split the operator from the subversion count if present.
- m4_bmatch(m4_substr($2,2),
- [0],[
- # A count of zero means use the length of the shorter version.
- # Determine the number of characters in A and B.
- ax_compare_version_len_A=`echo "$A" | $AWK '{print(length)}'`
- ax_compare_version_len_B=`echo "$B" | $AWK '{print(length)}'`
-
- # Set A to no more than B's length and B to no more than A's length.
- A=`echo "$A" | sed "s/\(.\{$ax_compare_version_len_B\}\).*/\1/"`
- B=`echo "$B" | sed "s/\(.\{$ax_compare_version_len_A\}\).*/\1/"`
- ],
- [[0-9]+],[
- # A count greater than zero means use only that many subversions
- A=`echo "$A" | sed "s/\(\([[0-9]]\{4\}\)\{m4_substr($2,2)\}\).*/\1/"`
- B=`echo "$B" | sed "s/\(\([[0-9]]\{4\}\)\{m4_substr($2,2)\}\).*/\1/"`
- ],
- [.+],[
- AC_WARNING(
- [invalid OP numeric parameter: $2])
- ],[])
-
- # Pad zeros at end of numbers to make same length.
- ax_compare_version_tmp_A="$A`echo $B | sed 's/./0/g'`"
- B="$B`echo $A | sed 's/./0/g'`"
- A="$ax_compare_version_tmp_A"
-
- # Check for equality or inequality as necessary.
- m4_case(m4_tolower(m4_substr($2,0,2)),
- [eq],[
- test "x$A" = "x$B" && ax_compare_version=true
- ],
- [ne],[
- test "x$A" != "x$B" && ax_compare_version=true
- ],[
- AC_WARNING([invalid OP parameter: $2])
- ])
- ])
-
- AS_VAR_POPDEF([A])dnl
- AS_VAR_POPDEF([B])dnl
-
- dnl # Execute ACTION-IF-TRUE / ACTION-IF-FALSE.
- if test "$ax_compare_version" = "true" ; then
- m4_ifvaln([$4],[$4],[:])dnl
- m4_ifvaln([$5],[else $5])dnl
- fi
-]) dnl AX_COMPARE_VERSION
-
diff --git a/rimage/Makefile.am b/rimage/Makefile.am
deleted file mode 100644
index 467bfe6..0000000
--- a/rimage/Makefile.am
+++ /dev/null
@@ -1,25 +0,0 @@
-SUBDIRS=keys
-
-bin_PROGRAMS = rimage
-
-noinst_HEADERS = \
- rimage.h \
- css.h \
- cse.h \
- plat_auth.h \
- manifest.h \
- file_format.h
-
-rimage_SOURCES = \
- file_simple.c \
- man_apl.c \
- man_cnl.c \
- cse.c \
- css.c \
- plat_auth.c \
- hash.c \
- pkcs1_5.c \
- manifest.c \
- elf.c \
- rimage.c
-
diff --git a/rimage/cse.c b/rimage/cse.c
deleted file mode 100644
index b560415..0000000
--- a/rimage/cse.c
+++ /dev/null
@@ -1,45 +0,0 @@
-/*
- * Copyright (c) 2017, Intel Corporation.
- *
- * This program is free software; you can redistribute it and/or modify it
- * under the terms and conditions of the GNU General Public License,
- * version 2, as published by the Free Software Foundation.
- *
- * This program is distributed in the hope it will be useful, but WITHOUT
- * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
- * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
- * more details.
- *
- * Author: Liam Girdwood <liam.r.girdwood@linux.intel.com>
- * Keyon Jie <yang.jie@linux.intel.com>
- */
-
-#include <stdio.h>
-#include "rimage.h"
-#include "cse.h"
-#include "manifest.h"
-
-void ri_cse_create(struct image *image)
-{
- struct CsePartitionDirHeader *cse_hdr = image->fw_image;
- struct sof_man_adsp_meta_file_ext *meta = image->fw_image +
- MAN_META_EXT_OFFSET;
- struct CsePartitionDirEntry *cse_entry =
- image->fw_image + sizeof(*cse_hdr);
- uint8_t csum = 0, *val = image->fw_image;
- int i, size;
-
- fprintf(stdout, " cse: completing CSE manifest\n");
-
- cse_entry[2].length = meta->comp_desc[0].limit_offset -
- MAN_DESC_OFFSET;
-
- /* calculate checksum using BSD algo */
- size = sizeof(*cse_hdr) + sizeof(*cse_entry) * MAN_CSE_PARTS;
- for (i = 0; i < size; i++) {
- if (i == 11)
- continue;
- csum += val[i];
- }
- cse_hdr->checksum = 0x100 - csum;
-}
diff --git a/rimage/cse.h b/rimage/cse.h
deleted file mode 100644
index 28650da..0000000
--- a/rimage/cse.h
+++ /dev/null
@@ -1,42 +0,0 @@
-/*
- * Copyright (c) 2017, Intel Corporation.
- *
- * This program is free software; you can redistribute it and/or modify it
- * under the terms and conditions of the GNU General Public License,
- * version 2, as published by the Free Software Foundation.
- *
- * This program is distributed in the hope it will be useful, but WITHOUT
- * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
- * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
- * more details.
- */
-
-#ifndef __CSE_H__
-#define __CSE_H__
-
-#include <stdint.h>
-
-struct image;
-
-#define CSE_HEADER_MAKER 0x44504324 /* "DPC$" */
-
-struct CsePartitionDirHeader {
- uint32_t header_marker;
- uint32_t nb_entries;
- uint8_t header_version;
- uint8_t entry_version;
- uint8_t header_length;
- uint8_t checksum;
- uint8_t partition_name[4];
-} __attribute__((packed));
-
-struct CsePartitionDirEntry {
- uint8_t entry_name[12];
- uint32_t offset;
- uint32_t length;
- uint32_t reserved;
-} __attribute__((packed));
-
-void ri_cse_create(struct image *image);
-
-#endif
diff --git a/rimage/css.c b/rimage/css.c
deleted file mode 100644
index 79b5ace..0000000
--- a/rimage/css.c
+++ /dev/null
@@ -1,76 +0,0 @@
-/*
- * Copyright (c) 2017, Intel Corporation.
- *
- * This program is free software; you can redistribute it and/or modify it
- * under the terms and conditions of the GNU General Public License,
- * version 2, as published by the Free Software Foundation.
- *
- * This program is distributed in the hope it will be useful, but WITHOUT
- * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
- * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
- * more details.
- *
- * Author: Liam Girdwood <liam.r.girdwood@linux.intel.com>
- * Keyon Jie <yang.jie@linux.intel.com>
- */
-
-#include <stdio.h>
-#include <sys/time.h>
-#include "rimage.h"
-#include "css.h"
-#include "manifest.h"
-
-void ri_css_hdr_create(struct image *image)
-{
- struct css_header *css = image->fw_image + MAN_CSS_HDR_OFFSET;
- struct tm *date;
- struct timeval tv;
- int val;
-
- fprintf(stdout, " cse: completing CSS manifest\n");
-
- /* get local time and date */
- gettimeofday(&tv, NULL);
- date = localtime(&tv.tv_sec);
-
- if (!date) {
- fprintf(stderr, "error: cant get localtime %d\n", -errno);
- return;
- }
-
- date->tm_year += 1900;
- fprintf(stdout, " css: set build date to %d:%2.2d:%2.2d\n",
- date->tm_year, date->tm_mon, date->tm_mday);
-
- /* year yYyy */
- val = date->tm_year / 1000;
- css->date |= val << 28;
- date->tm_year -= val * 1000;
- /* year yyYy */
- val = date->tm_year / 100;
- css->date |= val << 24;
- date->tm_year -= val * 100;
- /* year yyyY */
- val = date->tm_year / 10;
- css->date |= val << 20;
- date->tm_year -= val * 10;
- /* year Yyyy */
- val = date->tm_year;
- css->date |= val << 16;
-
- /* month Mm - for some reason month starts at 0 */
- val = ++date->tm_mon / 10;
- css->date |= val << 12;
- date->tm_mon -= (val * 10);
- /* month mM */
- val = date->tm_mon;
- css->date |= val << 8;
-
- /* Day Dd */
- val = date->tm_mday / 10;
- css->date |= val << 4;
- date->tm_mday -= (val * 10);
- /* Day dD */
- val = date->tm_mday;
- css->date |= val << 0;
-}
diff --git a/rimage/css.h b/rimage/css.h
deleted file mode 100644
index 0516f53..0000000
--- a/rimage/css.h
+++ /dev/null
@@ -1,69 +0,0 @@
-/*
- * Copyright (c) 2017, Intel Corporation.
- *
- * This program is free software; you can redistribute it and/or modify it
- * under the terms and conditions of the GNU General Public License,
- * version 2, as published by the Free Software Foundation.
- *
- * This program is distributed in the hope it will be useful, but WITHOUT
- * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
- * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
- * more details.
- */
-
-#ifndef __CSS_H__
-#define __CSS_H__
-
-#include <stdint.h>
-
-struct image;
-
-#define MAN_CSS_MOD_TYPE 4
-#define MAN_CSS_HDR_SIZE 161 /* in words */
-#define MAN_CSS_HDR_VERSION 0x10000
-#define MAN_CSS_MOD_VENDOR 0x8086
-#define MAN_CSS_HDR_ID {'$', 'M', 'N', '2'}
-
-#define MAN_CSS_KEY_SIZE (MAN_RSA_KEY_MODULUS_LEN >> 2)
-#define MAN_CSS_MOD_SIZE (MAN_RSA_KEY_MODULUS_LEN >> 2)
-#define MAN_CSS_EXP_SIZE (MAN_RSA_KEY_EXPONENT_LEN >> 2)
-#define MAN_CSS_MAN_SIZE \
- (sizeof(struct fw_image_manifest) >> 2)
-
-/*
- * RSA Key and Crypto
- */
-#define MAN_RSA_KEY_MODULUS_LEN 256
-#define MAN_RSA_KEY_EXPONENT_LEN 4
-#define MAN_RSA_SIGNATURE_LEN 256
-
-struct fw_version {
- uint16_t major_version;
- uint16_t minor_version;
- uint16_t hotfix_version;
- uint16_t build_version;
-} __attribute__((packed));
-
-struct css_header {
- uint32_t header_type;
- uint32_t header_len;
- uint32_t header_version;
- uint32_t reserved0; /* must be 0x0 */
- uint32_t module_vendor;
- uint32_t date;
- uint32_t size;
- uint8_t header_id[4];
- uint32_t padding; /* must be 0x0 */
- struct fw_version version;
- uint32_t svn;
- uint32_t reserved1[18]; /* must be 0x0 */
- uint32_t modulus_size;
- uint32_t exponent_size;
- uint8_t modulus[MAN_RSA_KEY_MODULUS_LEN];
- uint8_t exponent[MAN_RSA_KEY_EXPONENT_LEN];
- uint8_t signature[MAN_RSA_SIGNATURE_LEN];
-} __attribute__((packed));
-
-void ri_css_hdr_create(struct image *image);
-
-#endif
diff --git a/rimage/elf.c b/rimage/elf.c
deleted file mode 100644
index 4efed7a..0000000
--- a/rimage/elf.c
+++ /dev/null
@@ -1,618 +0,0 @@
-/*
- * Copyright (c) 2017, Intel Corporation.
- *
- * This program is free software; you can redistribute it and/or modify it
- * under the terms and conditions of the GNU General Public License,
- * version 2, as published by the Free Software Foundation.
- *
- * This program is distributed in the hope it will be useful, but WITHOUT
- * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
- * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
- * more details.
- *
- * Author: Liam Girdwood <liam.r.girdwood@linux.intel.com>
- * Keyon Jie <yang.jie@linux.intel.com>
- */
-
-#include <stdio.h>
-#include <string.h>
-#include "rimage.h"
-#include "cse.h"
-#include "manifest.h"
-
-static int elf_read_sections(struct image *image, struct module *module)
-{
- Elf32_Ehdr *hdr = &module->hdr;
- Elf32_Shdr *section = module->section;
- size_t count;
- int i, ret;
- uint32_t valid = (SHF_WRITE | SHF_ALLOC | SHF_EXECINSTR);
- int man_section_idx;
-
- /* read in section header */
- ret = fseek(module->fd, hdr->e_shoff, SEEK_SET);
- if (ret < 0) {
- fprintf(stderr, "error: can't seek to %s section header %d\n",
- module->elf_file, ret);
- return ret;
- }
-
- /* allocate space for each section header */
- section = calloc(sizeof(Elf32_Shdr), hdr->e_shnum);
- if (section == NULL)
- return -ENOMEM;
- module->section = section;
-
- /* read in sections */
- count = fread(section, sizeof(Elf32_Shdr), hdr->e_shnum, module->fd);
- if (count != hdr->e_shnum) {
- fprintf(stderr, "error: failed to read %s section header %d\n",
- module->elf_file, -errno);
- return -errno;
- }
-
- /* read in strings */
- module->strings = calloc(1, section[hdr->e_shstrndx].sh_size);
- if (!module->strings) {
- fprintf(stderr, "error: failed %s to read ELF strings for %d\n",
- module->elf_file, -errno);
- return -errno;
- }
-
- ret = fseek(module->fd, section[hdr->e_shstrndx].sh_offset, SEEK_SET);
- if (ret < 0) {
- fprintf(stderr, "error: can't seek to %s stringss %d\n",
- module->elf_file, ret);
- return ret;
- }
-
- count = fread(module->strings, 1, section[hdr->e_shstrndx].sh_size,
- module->fd);
- if (count != section[hdr->e_shstrndx].sh_size) {
- fprintf(stderr, "error: failed to read %s strings %d\n",
- module->elf_file, -errno);
- return -errno;
- }
-
- /* find manifest module data */
- man_section_idx = elf_find_section(image, module, ".bss");
- if (man_section_idx < 0) {
- /* no bss - it is OK for boot_ldr */
- module->bss_start = 0;
- module->bss_end = 0;
- } else {
- module->bss_index = man_section_idx;
- }
-
- fprintf(stdout, " BSS module metadata section at index %d\n",
- man_section_idx);
-
- /* parse each section */
- for (i = 0; i < hdr->e_shnum; i++) {
-
- /* only write valid sections */
- if (!(section[i].sh_flags & valid))
- continue;
-
- switch (section[i].sh_type) {
- case SHT_NOBITS:
- /* bss */
- module->bss_size += section[i].sh_size;
- module->num_bss++;
- break;
- case SHT_PROGBITS:
- /* text or data */
- module->fw_size += section[i].sh_size;
-
- if (section[i].sh_flags & SHF_EXECINSTR)
- module->text_size += section[i].sh_size;
- else
- module->data_size += section[i].sh_size;
- break;
- default:
- continue;
- }
-
- module->num_sections++;
-
- if (!image->verbose)
- continue;
-
- fprintf(stdout, " %s section-%d: \ttype\t 0x%8.8x\n", module->elf_file,
- i, section[i].sh_type);
- fprintf(stdout, " %s section-%d: \tflags\t 0x%8.8x\n", module->elf_file,
- i, section[i].sh_flags);
- fprintf(stdout, " %s section-%d: \taddr\t 0x%8.8x\n", module->elf_file,
- i, section[i].sh_addr);
- fprintf(stdout, " %s section-%d: \toffset\t 0x%8.8x\n", module->elf_file,
- i, section[i].sh_offset);
- fprintf(stdout, " %s section-%d: \tsize\t 0x%8.8x\n", module->elf_file,
- i, section[i].sh_size);
- fprintf(stdout, " %s section-%d: \tlink\t 0x%8.8x\n", module->elf_file,
- i, section[i].sh_link);
- fprintf(stdout, " %s section-%d: \tinfo\t 0x%8.8x\n\n", module->elf_file,
- i, section[i].sh_info);
- }
-
- return 0;
-}
-
-static int elf_read_programs(struct image *image, struct module *module)
-{
- Elf32_Ehdr *hdr = &module->hdr;
- Elf32_Phdr *prg = module->prg;
- size_t count;
- int i, ret;
-
- /* read in program header */
- ret = fseek(module->fd, hdr->e_phoff, SEEK_SET);
- if (ret < 0) {
- fprintf(stderr, "error: cant seek to %s program header %d\n",
- module->elf_file, ret);
- return ret;
- }
-
- /* allocate space for programs */
- prg = calloc(sizeof(Elf32_Phdr), hdr->e_phnum);
- if (prg == NULL)
- return -ENOMEM;
- module->prg = prg;
-
- /* read in programs */
- count = fread(prg, sizeof(Elf32_Phdr), hdr->e_phnum, module->fd);
- if (count != hdr->e_phnum) {
- fprintf(stderr, "error: failed to read %s program header %d\n",
- module->elf_file, -errno);
- return -errno;
- }
-
- /* check each program */
- for (i = 0; i < hdr->e_phnum; i++) {
-
- if (prg[i].p_filesz == 0)
- continue;
-
- if (!image->verbose)
- continue;
-
- fprintf(stdout, "%s program-%d: \ttype\t 0x%8.8x\n",
- module->elf_file, i, prg[i].p_type);
- fprintf(stdout, "%s program-%d: \toffset\t 0x%8.8x\n",
- module->elf_file, i, prg[i].p_offset);
- fprintf(stdout, "%s program-%d: \tvaddr\t 0x%8.8x\n",
- module->elf_file, i, prg[i].p_vaddr);
- fprintf(stdout, "%s program-%d: \tpaddr\t 0x%8.8x\n",
- module->elf_file, i, prg[i].p_paddr);
- fprintf(stdout, "%s program-%d: \tfsize\t 0x%8.8x\n",
- module->elf_file, i, prg[i].p_filesz);
- fprintf(stdout, "%s program-%d: \tmsize\t 0x%8.8x\n",
- module->elf_file, i, prg[i].p_memsz);
- fprintf(stdout, "%s program-%d: \tflags\t 0x%8.8x\n\n",
- module->elf_file, i, prg[i].p_flags);
- }
-
- return 0;
-}
-
-static int elf_read_hdr(struct image *image, struct module *module)
-{
- Elf32_Ehdr *hdr = &module->hdr;
- size_t count;
-
- /* read in elf header */
- count = fread(hdr, sizeof(*hdr), 1, module->fd);
- if (count != 1) {
- fprintf(stderr, "error: failed to read %s elf header %d\n",
- module->elf_file, -errno);
- return -errno;
- }
-
- if (!image->verbose)
- return 0;
-
- fprintf(stdout, "%s elf: \tentry point\t 0x%8.8x\n",
- module->elf_file, hdr->e_entry);
- fprintf(stdout, "%s elf: \tprogram offset\t 0x%8.8x\n",
- module->elf_file, hdr->e_phoff);
- fprintf(stdout, "%s elf: \tsection offset\t 0x%8.8x\n",
- module->elf_file, hdr->e_shoff);
- fprintf(stdout, "%s elf: \tprogram size\t 0x%8.8x\n",
- module->elf_file, hdr->e_phentsize);
- fprintf(stdout, "%s elf: \tprogram count\t 0x%8.8x\n",
- module->elf_file, hdr->e_phnum);
- fprintf(stdout, "%s elf: \tsection size\t 0x%8.8x\n",
- module->elf_file, hdr->e_shentsize);
- fprintf(stdout, "%s elf: \tsection count\t 0x%8.8x\n",
- module->elf_file, hdr->e_shnum);
- fprintf(stdout, "%s elf: \tstring index\t 0x%8.8x\n\n",
- module->elf_file, hdr->e_shstrndx);
-
- return 0;
-}
-
-int elf_is_rom(struct image *image, Elf32_Shdr *section)
-{
- uint32_t start, end;
-
- start = section->sh_addr;
- end = section->sh_addr + section->sh_size;
-
- if (start < image->adsp->rom_base ||
- start > image->adsp->rom_base + image->adsp->rom_size)
- return 0;
- if (end < image->adsp->rom_base ||
- end > image->adsp->rom_base + image->adsp->rom_size)
- return 0;
- return 1;
-}
-
-static void elf_module_size(struct image *image, struct module *module,
- Elf32_Shdr *section, int index)
-{
- switch (section->sh_type) {
- case SHT_PROGBITS:
- /* text or data */
- if (section->sh_flags & SHF_EXECINSTR) {
- /* text */
- if (module->text_start > section->sh_addr)
- module->text_start = section->sh_addr;
- if (module->text_end < section->sh_addr + section->sh_size)
- module->text_end = section->sh_addr + section->sh_size;
-
- fprintf(stdout, "\tTEXT\t");
- } else {
- /* initialized data, also calc the writable sections */
- if (module->data_start > section->sh_addr)
- module->data_start = section->sh_addr;
- if (module->data_end < section->sh_addr + section->sh_size)
- module->data_end = section->sh_addr + section->sh_size;
-
- fprintf(stdout, "\tDATA\t");
- }
- break;
- case SHT_NOBITS:
- /* bss */
- if (index == module->bss_index) {
- /* updated the .bss segment */
- module->bss_start = section->sh_addr;
- module->bss_end = section->sh_addr + section->sh_size;
- fprintf(stdout, "\tBSS\t");
- } else {
- fprintf(stdout, "\tHEAP\t");
- }
- break;
- default:
- break;
- }
-}
-
-static void elf_module_size_reloc(struct image *image, struct module *module,
- Elf32_Shdr *section, int index)
-{
- switch (section->sh_type) {
- case SHT_PROGBITS:
- /* text or data */
- if (section->sh_flags & SHF_EXECINSTR) {
- /* text */
- module->text_start = 0;
- module->text_end += section->sh_size;
-
- fprintf(stdout, "\tTEXT\t");
- } else {
- /* initialized data, also calc the writable sections */
- module->data_start = 0;
- module->data_end += section->sh_size;
-
- fprintf(stdout, "\tDATA\t");
- }
- break;
- case SHT_NOBITS:
- /* bss */
- if (index == module->bss_index) {
- /* updated the .bss segment */
- module->bss_start = section->sh_addr;
- module->bss_end = section->sh_addr + section->sh_size;
- fprintf(stdout, "\tBSS\t");
- } else {
- fprintf(stdout, "\tHEAP\t");
- }
- break;
- default:
- break;
- }
-}
-
-static void elf_module_limits(struct image *image, struct module *module)
-{
- Elf32_Shdr *section;
- uint32_t valid = (SHF_WRITE | SHF_ALLOC | SHF_EXECINSTR);
- int i;
-
- module->text_start = module->data_start = 0xffffffff;
- module->bss_start = 0;
- module->text_end = module->data_end = module->bss_end = 0;
-
- fprintf(stdout, " Found %d sections, listing valid sections......\n",
- module->hdr.e_shnum);
-
- fprintf(stdout, "\tNo\tStart\t\tEnd\t\tBytes\tType\tName\n");
-
- /* iterate all sections and get size of segments */
- for (i = 0; i < module->hdr.e_shnum; i++) {
-
- section = &module->section[i];
-
- /* module bss can sometimes be missed */
- if (i != module->bss_index) {
-
- /* only check valid sections */
- if (!(section->sh_flags & valid))
- continue;
-
- if (section->sh_size == 0)
- continue;
-
- if (elf_is_rom(image, section))
- continue;
- }
-
- fprintf(stdout, "\t%d\t0x%8.8x\t0x%8.8x\t%d", i,
- section->sh_addr, section->sh_addr + section->sh_size,
- section->sh_size);
-
- /* text or data section */
- if (image->reloc)
- elf_module_size_reloc(image, module, section, i);
- else
- elf_module_size(image, module, section, i);
-
- /* section name */
- fprintf(stdout, "%s\n", module->strings + section->sh_name);
- }
-
- fprintf(stdout, "\n");
-}
-
-/* make sure no section overlap from any modules */
-int elf_validate_section(struct image *image, struct module *module,
- Elf32_Shdr *section, int index)
-{
- struct module *m;
- Elf32_Shdr *s;
- uint32_t valid = (SHF_WRITE | SHF_ALLOC | SHF_EXECINSTR);
- int i, j;
-
- /* for each module */
- for (i = 0; i < image->num_modules; i++) {
- m = &image->module[i];
-
- /* for each section */
- for (j = 0; j < m->hdr.e_shnum; j++) {
- s = &m->section[j];
-
- if (s == section)
- continue;
-
- /* only check valid sections */
- if (!(s->sh_flags & valid))
- continue;
-
- if (s->sh_size == 0)
- continue;
-
- /* is section start non overlapping ? */
- if (section->sh_addr >= s->sh_addr &&
- section->sh_addr <
- s->sh_addr + s->sh_size) {
- goto err;
- }
-
- /* is section end non overlapping ? */
- if (section->sh_addr + section->sh_size > s->sh_addr &&
- section->sh_addr + section->sh_size <=
- s->sh_addr + s->sh_size) {
- goto err;
- }
- }
- }
-
- return 0;
-
-err:
- fprintf(stderr, "error: section overlap between %s:%d and %s:%d\n",
- module->elf_file, index, m->elf_file, j);
- fprintf(stderr, " [0x%x : 0x%x] overlaps with [0x%x :0x%x]\n",
- section->sh_addr, section->sh_addr + section->sh_size,
- s->sh_addr, s->sh_addr + s->sh_size);
- return -EINVAL;
-}
-
-/* make sure no section overlaps from any modules */
-int elf_validate_modules(struct image *image)
-{
- struct module *module;
- Elf32_Shdr *section;
- uint32_t valid = (SHF_WRITE | SHF_ALLOC | SHF_EXECINSTR);
- int i, j, ret;
-
- /* relocatable modules have no physical addresses until runtime */
- if (image->reloc)
- return 0;
-
- /* for each module */
- for (i = 0; i < image->num_modules; i++) {
- module = &image->module[i];
-
- /* for each section */
- for (j = 0; j < module->hdr.e_shnum; j++) {
- section = &module->section[j];
-
- /* only check valid sections */
- if (!(section->sh_flags & valid))
- continue;
-
- if (section->sh_size == 0)
- continue;
-
- /* is section non overlapping ? */
- ret = elf_validate_section(image, module, section, j);
- if (ret < 0)
- return ret;
- }
- }
-
- return 0;
-}
-
-int elf_find_section(struct image *image, struct module *module,
- const char *name)
-{
- Elf32_Ehdr *hdr = &module->hdr;
- Elf32_Shdr *section, *s;
- char *buffer;
- size_t count;
- int ret, i;
-
- section = &module->section[hdr->e_shstrndx];
-
- /* alloc data data */
- buffer = calloc(1, section->sh_size);
- if (buffer == NULL)
- return -ENOMEM;
-
- /* read in section string data */
- ret = fseek(module->fd, section->sh_offset, SEEK_SET);
- if (ret < 0) {
- fprintf(stderr, "error: cant seek to string section %d\n", ret);
- goto out;
- }
-
- count = fread(buffer, 1, section->sh_size, module->fd);
- if (count != section->sh_size) {
- fprintf(stderr, "error: can't read string section %d\n", -errno);
- ret = -errno;
- goto out;
- }
-
- /* find section with name */
- for (i = 0; i < hdr->e_shnum; i++) {
- s = &module->section[i];
- if (!strcmp(name, buffer + s->sh_name)) {
- ret = i;
- goto out;
- }
- }
-
- fprintf(stderr, "error: can't find section %s in module %s\n", name,
- module->elf_file);
- ret = -EINVAL;
-
-out:
- free(buffer);
- return ret;
-}
-
-int elf_parse_module(struct image *image, int module_index, const char *name)
-{
- struct module *module;
- uint32_t rem;
- int ret = 0;
-
- /* validate module index */
- if (module_index >= MAX_MODULES) {
- fprintf(stderr, "error: too any modules\n");
- return -EINVAL;
- }
-
- module = &image->module[module_index];
-
- /* open the elf input file */
- module->fd = fopen(name, "r");
- if (module->fd == NULL) {
- fprintf(stderr, "error: unable to open %s for reading %d\n",
- name, errno);
- return -EINVAL;
- }
- module->elf_file = name;
-
- /* get file size */
- ret = fseek(module->fd, 0, SEEK_END);
- if (ret < 0)
- goto hdr_err;
- module->file_size = ftell(module->fd);
- ret = fseek(module->fd, 0, SEEK_SET);
- if (ret < 0)
- goto hdr_err;
-
- /* read in elf header */
- ret = elf_read_hdr(image, module);
- if (ret < 0)
- goto hdr_err;
-
- /* read in programs */
- ret = elf_read_programs(image, module);
- if (ret < 0) {
- fprintf(stderr, "error: failed to read program sections %d\n",
- ret);
- goto hdr_err;
- }
-
- /* read sections */
- ret = elf_read_sections(image, module);
- if (ret < 0) {
- fprintf(stderr, "error: failed to read base sections %d\n",
- ret);
- goto sec_err;
- }
-
- /* check limits */
- elf_module_limits(image, module);
-
- elf_find_section(image, module, "");
-
- fprintf(stdout, " module: input size %d (0x%x) bytes %d sections\n",
- module->fw_size, module->fw_size, module->num_sections);
- fprintf(stdout, " module: text %d (0x%x) bytes\n"
- " data %d (0x%x) bytes\n"
- " bss %d (0x%x) bytes\n\n",
- module->text_size, module->text_size,
- module->data_size, module->data_size,
- module->bss_size, module->bss_size);
-
- /* file sizes round up to nearest page */
- module->text_file_size = module->text_end - module->text_start;
- rem = module->text_file_size % MAN_PAGE_SIZE;
- if (rem)
- module->text_file_size += MAN_PAGE_SIZE - rem;
-
- /* data section */
- module->data_file_size = module->data_end - module->data_start;
- rem = module->data_file_size % MAN_PAGE_SIZE;
- if (rem)
- module->data_file_size += MAN_PAGE_SIZE - rem;
-
- /* bss section */
- module->bss_file_size = module->bss_end - module->bss_start;
- rem = module->bss_file_size % MAN_PAGE_SIZE;
- if (rem)
- module->bss_file_size += MAN_PAGE_SIZE - rem;
-
- return 0;
-
-sec_err:
- free(module->prg);
-hdr_err:
- fclose(module->fd);
-
- return ret;
-}
-
-void elf_free_module(struct image *image, int module_index)
-{
- struct module *module = &image->module[module_index];
-
- free(module->prg);
- free(module->section);
- free(module->strings);
- fclose(module->fd);
-}
diff --git a/rimage/file_format.h b/rimage/file_format.h
deleted file mode 100644
index 1530258..0000000
--- a/rimage/file_format.h
+++ /dev/null
@@ -1,117 +0,0 @@
-/*
- * This file is provided under a dual BSD/GPLv2 license. When using or
- * redistributing this file, you may do so under either license.
- *
- * GPL LICENSE SUMMARY
- *
- * Copyright(c) 2017 Intel Corporation. All rights reserved.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of version 2 of the GNU General Public License as
- * published by the Free Software Foundation.
- *
- * This program is distributed in the hope that it will be useful, but
- * WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
- * General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
- * The full GNU General Public License is included in this distribution
- * in the file called LICENSE.GPL.
- *
- * BSD LICENSE
- *
- * Copyright(c) 2017 Intel Corporation. All rights reserved.
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions
- * are met:
- *
- * * Redistributions of source code must retain the above copyright
- * notice, this list of conditions and the following disclaimer.
- * * Redistributions in binary form must reproduce the above copyright
- * notice, this list of conditions and the following disclaimer in
- * the documentation and/or other materials provided with the
- * distribution.
- * * Neither the name of Intel Corporation nor the names of its
- * contributors may be used to endorse or promote products derived
- * from this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
- * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
- * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
- * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
- * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
- * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
- * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
- * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
- * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
- * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *
- * Author: Liam Girdwood <liam.r.girdwood@linux.intel.com>
- */
-
-
-/*
- * Firmware file format .
- */
-
-#ifndef __INCLUDE_UAPI_SOF_FW_H__
-#define __INCLUDE_UAPI_SOF_FW_H__
-
-#define SND_SOF_FW_SIG_SIZE 4
-#define SND_SOF_FW_ABI 1
-#define SND_SOF_FW_SIG "Reef"
-
-/*
- * Firmware module is made up of 1 . N blocks of different types. The
- * Block header is used to determine where and how block is to be copied in the
- * DSP/host memory space.
- */
-enum snd_sof_fw_blk_type {
- SOF_BLK_IMAGE = 0, /* whole image - parsed by ROMs */
- SOF_BLK_TEXT = 1,
- SOF_BLK_DATA = 2,
- SOF_BLK_CACHE = 3,
- SOF_BLK_REGS = 4,
- SOF_BLK_SIG = 5,
- SOF_BLK_ROM = 6,
- /* add new block types here */
-};
-
-struct snd_sof_blk_hdr {
- enum snd_sof_fw_blk_type type;
- uint32_t size; /* bytes minus this header */
- uint32_t offset; /* offset from base */
-} __attribute__((packed));
-
-/*
- * Firmware file is made up of 1 .. N different modules types. The module
- * type is used to determine how to load and parse the module.
- */
-enum snd_sof_fw_mod_type {
- SOF_FW_BASE = 0, /* base firmware image */
- SOF_FW_MODULE = 1, /* firmware module */
-};
-
-struct snd_sof_mod_hdr {
- enum snd_sof_fw_mod_type type;
- uint32_t size; /* bytes minus this header */
- uint32_t num_blocks; /* number of blocks */
-} __attribute__((packed));
-
-/*
- * Firmware file header.
- */
-struct snd_sof_fw_header {
- unsigned char sig[SND_SOF_FW_SIG_SIZE]; /* "Reef" */
- uint32_t file_size; /* size of file minus this header */
- uint32_t num_modules; /* number of modules */
- uint32_t abi; /* version of header format */
-} __attribute__((packed));
-
-#endif
diff --git a/rimage/file_simple.c b/rimage/file_simple.c
deleted file mode 100644
index 4068734..0000000
--- a/rimage/file_simple.c
+++ /dev/null
@@ -1,406 +0,0 @@
-/*
- * ELF to firmware image creator.
- *
- * Copyright (c) 2015, Intel Corporation.
- *
- * This program is free software; you can redistribute it and/or modify it
- * under the terms and conditions of the GNU General Public License,
- * version 2, as published by the Free Software Foundation.
- *
- * This program is distributed in the hope it will be useful, but WITHOUT
- * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
- * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
- * more details.
- */
-
-
-#include <stdlib.h>
-#include <stdio.h>
-#include <unistd.h>
-#include <errno.h>
-#include <string.h>
-
-#include "rimage.h"
-#include "file_format.h"
-
-#define BYT_IRAM_BASE 0xff2c0000
-#define BYT_IRAM_HOST_OFFSET 0x0C0000
-#define BYT_IRAM_SIZE (80 * 1024)
-#define BYT_DRAM_BASE 0xff300000
-#define BYT_DRAM_HOST_OFFSET 0x100000
-#define BYT_DRAM_SIZE (160 * 1024)
-
-#define HSW_IRAM_BASE 0x00000000
-#define HSW_IRAM_HOST_OFFSET 0x00080000
-#define HSW_IRAM_SIZE (384 * 1024)
-#define HSW_DRAM_BASE 0x00400000
-#define HSW_DRAM_HOST_OFFSET 0x00000000
-#define HSW_DRAM_SIZE (512 * 1024)
-
-#define BDW_IRAM_BASE 0x00000000
-#define BDW_IRAM_HOST_OFFSET 0x000A0000
-#define BDW_IRAM_SIZE (320 * 1024)
-#define BDW_DRAM_BASE 0x00400000
-#define BDW_DRAM_HOST_OFFSET 0x00000000
-#define BDW_DRAM_SIZE (640 * 1024)
-
-static int is_iram(struct image *image, Elf32_Shdr *section)
-{
- const struct adsp *adsp = image->adsp;
- uint32_t start, end;
-
- start = section->sh_addr;
- end = section->sh_addr + section->sh_size;
-
- if (start < adsp->iram_base)
- return 0;
- if (start >= adsp->iram_base + adsp->iram_size)
- return 0;
- if (end > adsp->iram_base + adsp->iram_size)
- return 0;
- return 1;
-}
-
-static int is_dram(struct image *image, Elf32_Shdr *section)
-{
- const struct adsp *adsp = image->adsp;
- uint32_t start, end;
-
- start = section->sh_addr;
- end = section->sh_addr + section->sh_size;
-
- if (start < adsp->dram_base)
- return 0;
- if (start >= adsp->dram_base + adsp->dram_size)
- return 0;
- if (end > adsp->dram_base + adsp->dram_size)
- return 0;
- return 1;
-}
-
-static int block_idx;
-
-static int write_block(struct image *image, struct module *module,
- Elf32_Shdr *section)
-{
- const struct adsp *adsp = image->adsp;
- struct snd_sof_blk_hdr block;
- size_t count;
- void *buffer;
- int ret;
-
- block.size = section->sh_size;
-
- if (is_iram(image, section)) {
- block.type = SOF_BLK_TEXT;
- block.offset = section->sh_addr - adsp->iram_base
- + adsp->host_iram_offset;
- } else if (is_dram(image, section)) {
- block.type = SOF_BLK_DATA;
- block.offset = section->sh_addr - adsp->dram_base
- + adsp->host_dram_offset;
- } else {
- fprintf(stderr, "error: invalid block address/size 0x%x/0x%x\n",
- section->sh_addr, section->sh_size);
- return -EINVAL;
- }
-
- /* write header */
- count = fwrite(&block, sizeof(block), 1, image->out_fd);
- if (count != 1)
- return -errno;
-
- /* alloc data data */
- buffer = calloc(1, section->sh_size);
- if (buffer == NULL)
- return -ENOMEM;
-
- /* read in section data */
- ret = fseek(module->fd, section->sh_offset, SEEK_SET);
- if (ret < 0) {
- fprintf(stderr, "error: cant seek to section %d\n", ret);
- goto out;
- }
- count = fread(buffer, 1, section->sh_size, module->fd);
- if (count != section->sh_size) {
- fprintf(stderr, "error: cant read section %d\n", -errno);
- ret = -errno;
- goto out;
- }
-
- /* write out section data */
- count = fwrite(buffer, 1, section->sh_size, image->out_fd);
- if (count != section->sh_size) {
- fprintf(stderr, "error: cant write section %d\n", -errno);
- fprintf(stderr, " foffset %d size 0x%x mem addr 0x%x\n",
- section->sh_offset, section->sh_size, section->sh_addr);
- ret = -errno;
- goto out;
- }
-
- fprintf(stdout, "\t%d\t0x%8.8x\t0x%8.8x\t0x%8.8lx\t%s\n", block_idx++,
- section->sh_addr, section->sh_size, ftell(image->out_fd),
- block.type == SOF_BLK_TEXT ? "TEXT" : "DATA");
-
-out:
- free(buffer);
- return ret;
-}
-
-static int simple_write_module(struct image *image, struct module *module)
-{
- struct snd_sof_mod_hdr hdr;
- Elf32_Shdr *section;
- size_t count;
- int i, err;
- uint32_t valid = (SHF_WRITE | SHF_ALLOC | SHF_EXECINSTR);
-
- hdr.num_blocks = module->num_sections - module->num_bss;
- hdr.size = module->text_size + module->data_size +
- sizeof(struct snd_sof_blk_hdr) * hdr.num_blocks;
- hdr.type = SOF_FW_BASE;
-
- count = fwrite(&hdr, sizeof(hdr), 1, image->out_fd);
- if (count != 1) {
- fprintf(stderr, "error: failed to write section header %d\n",
- -errno);
- return -errno;
- }
-
- fprintf(stdout, "\n\tTotals\tStart\t\tEnd\t\tSize");
-
- fprintf(stdout, "\n\tTEXT\t0x%8.8x\t0x%8.8x\t0x%x\n",
- module->text_start, module->text_end,
- module->text_end - module->text_start);
- fprintf(stdout, "\tDATA\t0x%8.8x\t0x%8.8x\t0x%x\n",
- module->data_start, module->data_end,
- module->data_end - module->data_start);
- fprintf(stdout, "\tBSS\t0x%8.8x\t0x%8.8x\t0x%x\n\n ",
- module->bss_start, module->bss_end,
- module->bss_end - module->bss_start);
-
- fprintf(stdout, "\tNo\tAddress\t\tSize\t\tFile\t\tType\n");
-
- for (i = 0; i < module->hdr.e_shnum; i++) {
-
- section = &module->section[i];
-
- /* only write valid sections */
- if (!(module->section[i].sh_flags & valid))
- continue;
-
- /* dont write bss */
- if (section->sh_type == SHT_NOBITS)
- continue;
-
- err = write_block(image, module, section);
- if (err < 0) {
- fprintf(stderr, "error: failed to write section #%d\n", i);
- return err;
- }
- }
-
- fprintf(stdout, "\n");
- return 0;
-}
-
-static int write_block_reloc(struct image *image, struct module *module)
-{
- struct snd_sof_blk_hdr block;
- size_t count;
- void *buffer;
- int ret;
-
- block.size = module->file_size;
- block.type = SOF_BLK_DATA;
- block.offset = 0;
-
- /* write header */
- count = fwrite(&block, sizeof(block), 1, image->out_fd);
- if (count != 1)
- return -errno;
-
- /* alloc data data */
- buffer = calloc(1, module->file_size);
- if (!buffer)
- return -ENOMEM;
-
- /* read in section data */
- ret = fseek(module->fd, 0, SEEK_SET);
- if (ret < 0) {
- fprintf(stderr, "error: can't seek to section %d\n", ret);
- goto out;
- }
- count = fread(buffer, 1, module->file_size, module->fd);
- if (count != module->file_size) {
- fprintf(stderr, "error: can't read section %d\n", -errno);
- ret = -errno;
- goto out;
- }
-
- /* write out section data */
- count = fwrite(buffer, 1, module->file_size, image->out_fd);
- if (count != module->file_size) {
- fprintf(stderr, "error: can't write section %d\n", -errno);
- ret = -errno;
- goto out;
- }
-
- fprintf(stdout, "\t%d\t0x%8.8x\t0x%8.8x\t0x%8.8lx\t%s\n", block_idx++,
- 0, module->file_size, ftell(image->out_fd),
- block.type == SOF_BLK_TEXT ? "TEXT" : "DATA");
-
-out:
- free(buffer);
- return ret;
-}
-
-static int simple_write_module_reloc(struct image *image, struct module *module)
-{
- struct snd_sof_mod_hdr hdr;
- size_t count;
- int err;
-
- hdr.num_blocks = 1;
- hdr.size = module->text_size + module->data_size;
- hdr.type = SOF_FW_BASE; // module
-
- count = fwrite(&hdr, sizeof(hdr), 1, image->out_fd);
- if (count != 1) {
- fprintf(stderr, "error: failed to write section header %d\n",
- -errno);
- return -errno;
- }
-
- fprintf(stdout, "\n\tTotals\tStart\t\tEnd\t\tSize");
-
- fprintf(stdout, "\n\tTEXT\t0x%8.8x\t0x%8.8x\t0x%x\n",
- module->text_start, module->text_end,
- module->text_end - module->text_start);
- fprintf(stdout, "\tDATA\t0x%8.8x\t0x%8.8x\t0x%x\n",
- module->data_start, module->data_end,
- module->data_end - module->data_start);
- fprintf(stdout, "\tBSS\t0x%8.8x\t0x%8.8x\t0x%x\n\n ",
- module->bss_start, module->bss_end,
- module->bss_end - module->bss_start);
-
- fprintf(stdout, "\tNo\tAddress\t\tSize\t\tFile\t\tType\n");
-
- err = write_block_reloc(image, module);
- if (err < 0) {
- fprintf(stderr, "error: failed to write section #%d\n", err);
- return err;
- }
-
- fprintf(stdout, "\n");
- return 0;
-}
-
-/* used by others */
-static int simple_write_firmware(struct image *image)
-{
- struct snd_sof_fw_header hdr;
- struct module *module;
- size_t count;
- int i, ret;
-
- memcpy(hdr.sig, SND_SOF_FW_SIG, SND_SOF_FW_SIG_SIZE);
-
- hdr.num_modules = image->num_modules;
- hdr.abi = SND_SOF_FW_ABI;
- hdr.file_size = 0;
-
- for (i = 0; i < image->num_modules; i++) {
- module = &image->module[i];
- module->fw_size += sizeof(struct snd_sof_blk_hdr) *
- (module->num_sections - module->num_bss);
- module->fw_size += sizeof(struct snd_sof_mod_hdr) * hdr.num_modules;
- hdr.file_size += module->fw_size;
- }
-
- count = fwrite(&hdr, sizeof(hdr), 1, image->out_fd);
- if (count != 1)
- return -errno;
-
- for (i = 0; i < image->num_modules; i++) {
- module = &image->module[i];
-
- fprintf(stdout, "writing module %d %s\n", i, module->elf_file);
-
- if (image->reloc)
- ret = simple_write_module_reloc(image, module);
- else
- ret = simple_write_module(image, module);
- if (ret < 0) {
- fprintf(stderr, "error: failed to write module %d\n",
- i);
- return ret;
- }
- }
-
- fprintf(stdout, "firmware: image size %ld (0x%lx) bytes %d modules\n\n",
- hdr.file_size + sizeof(hdr), hdr.file_size + sizeof(hdr),
- hdr.num_modules);
-
- return 0;
-}
-
-const struct adsp machine_byt = {
- .name = "byt",
- .iram_base = BYT_IRAM_BASE,
- .iram_size = BYT_IRAM_SIZE,
- .host_iram_offset = BYT_IRAM_HOST_OFFSET,
- .dram_base = BYT_DRAM_BASE,
- .dram_size = BYT_DRAM_SIZE,
- .host_dram_offset = BYT_DRAM_HOST_OFFSET,
- .machine_id = MACHINE_BAYTRAIL,
- .write_firmware = simple_write_firmware,
-};
-
-const struct adsp machine_cht = {
- .name = "cht",
- .iram_base = BYT_IRAM_BASE,
- .iram_size = BYT_IRAM_SIZE,
- .host_iram_offset = BYT_IRAM_HOST_OFFSET,
- .dram_base = BYT_DRAM_BASE,
- .dram_size = BYT_DRAM_SIZE,
- .host_dram_offset = BYT_DRAM_HOST_OFFSET,
- .machine_id = MACHINE_CHERRYTRAIL,
- .write_firmware = simple_write_firmware,
-};
-
-const struct adsp machine_bsw = {
- .name = "bsw",
- .iram_base = BYT_IRAM_BASE,
- .iram_size = BYT_IRAM_SIZE,
- .host_iram_offset = BYT_IRAM_HOST_OFFSET,
- .dram_base = BYT_DRAM_BASE,
- .dram_size = BYT_DRAM_SIZE,
- .host_dram_offset = BYT_DRAM_HOST_OFFSET,
- .machine_id = MACHINE_BRASWELL,
- .write_firmware = simple_write_firmware,
-};
-
-const struct adsp machine_hsw = {
- .name = "hsw",
- .iram_base = HSW_IRAM_BASE,
- .iram_size = HSW_IRAM_SIZE,
- .host_iram_offset = HSW_IRAM_HOST_OFFSET,
- .dram_base = HSW_DRAM_BASE,
- .dram_size = HSW_DRAM_SIZE,
- .host_dram_offset = HSW_DRAM_HOST_OFFSET,
- .machine_id = MACHINE_HASWELL,
- .write_firmware = simple_write_firmware,
-};
-
-const struct adsp machine_bdw = {
- .name = "bdw",
- .iram_base = BDW_IRAM_BASE,
- .iram_size = BDW_IRAM_SIZE,
- .host_iram_offset = BDW_IRAM_HOST_OFFSET,
- .dram_base = BDW_DRAM_BASE,
- .dram_size = BDW_DRAM_SIZE,
- .host_dram_offset = BDW_DRAM_HOST_OFFSET,
- .machine_id = MACHINE_BROADWELL,
- .write_firmware = simple_write_firmware,
-};
diff --git a/rimage/hash.c b/rimage/hash.c
deleted file mode 100644
index 73b6d72..0000000
--- a/rimage/hash.c
+++ /dev/null
@@ -1,98 +0,0 @@
-/*
- * Copyright (c) 2017, Intel Corporation.
- *
- * This program is free software; you can redistribute it and/or modify it
- * under the terms and conditions of the GNU General Public License,
- * version 2, as published by the Free Software Foundation.
- *
- * This program is distributed in the hope it will be useful, but WITHOUT
- * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
- * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
- * more details.
- *
- * Author: Liam Girdwood <liam.r.girdwood@linux.intel.com>
- * Keyon Jie <yang.jie@linux.intel.com>
- */
-
-#include <stdlib.h>
-#include <stdio.h>
-#include <unistd.h>
-#include <errno.h>
-#include <string.h>
-#include <time.h>
-#include <sys/time.h>
-
-#include <openssl/conf.h>
-#include <openssl/evp.h>
-#include <openssl/err.h>
-
-#include "rimage.h"
-#include "file_format.h"
-#include "manifest.h"
-
-#if OPENSSL_VERSION_NUMBER < 0x10100000L
-void EVP_MD_CTX_free(EVP_MD_CTX *ctx);
-EVP_MD_CTX *EVP_MD_CTX_new(void);
-
-static void *OPENSSL_zalloc(size_t num)
-{
- void *ret = OPENSSL_malloc(num);
-
- if (ret != NULL)
- memset(ret, 0, num);
- return ret;
-}
-
-EVP_MD_CTX *EVP_MD_CTX_new(void)
-{
- return OPENSSL_zalloc(sizeof(EVP_MD_CTX));
-}
-
-void EVP_MD_CTX_free(EVP_MD_CTX *ctx)
-{
- EVP_MD_CTX_cleanup(ctx);
- OPENSSL_free(ctx);
-}
-#endif
-
-
-#define DEBUG_HASH 0
-
-void module_sha256_create(struct image *image)
-{
- image->md = EVP_sha256();
- image->mdctx = EVP_MD_CTX_new();
-
- EVP_DigestInit_ex(image->mdctx, image->md, NULL);
-}
-
-void module_sha256_update(struct image *image, uint8_t *data, size_t bytes)
-{
- EVP_DigestUpdate(image->mdctx, data, bytes);
-}
-
-void module_sha256_complete(struct image *image, uint8_t *hash)
-{
- unsigned char md_value[EVP_MAX_MD_SIZE];
- unsigned int md_len;
-#if DEBUG_HASH
- int i;
-#endif
- EVP_DigestFinal_ex(image->mdctx, md_value, &md_len);
- EVP_MD_CTX_free(image->mdctx);
-
- memcpy(hash, md_value, md_len);
-#if DEBUG_HASH
- fprintf(stdout, "Module digest is: ");
- for (i = 0; i < md_len; i++)
- fprintf(stdout, "%02x", md_value[i]);
- fprintf(stdout, "\n");
-#endif
-}
-
-void ri_hash(struct image *image, unsigned int offset, unsigned int size, uint8_t *hash)
-{
- module_sha256_create(image);
- module_sha256_update(image, image->fw_image + offset, size);
- module_sha256_complete(image, hash);
-}
diff --git a/rimage/keys/Makefile.am b/rimage/keys/Makefile.am
deleted file mode 100644
index 06fe307..0000000
--- a/rimage/keys/Makefile.am
+++ /dev/null
@@ -1,9 +0,0 @@
-install-data-local:
- @$(NORMAL_INSTALL)
- $(mkinstalldirs) $(PEM_KEY_PREFIX);
- $(INSTALL_DATA) otc_private_key.pem $(PEM_KEY_PREFIX)
- $(INSTALL_DATA) otc_public_key.pem $(PEM_KEY_PREFIX)
-
-EXTRA_DIST = \
- otc_private_key.pem \
- otc_public_key.pem
\ No newline at end of file
diff --git a/rimage/keys/README b/rimage/keys/README
deleted file mode 100644
index 3ece70c..0000000
--- a/rimage/keys/README
+++ /dev/null
@@ -1,34 +0,0 @@
-About
-=====
-
-Firmware binary signing is for audio DSP is mandatory on Intel products from
-Skylake onwards. i.e. no code signing on Baytrail, Cherrytrail, Braswell,
-Haswell and Broadwell but mandatory on Skylake, Kabylake, Apollolake and
-Cannonlake.
-
-rimage can now sign firmware binaries for Apollolake and Cannonlake targets.
-This is done automatically as part of the "make bin" part of the build.
-
-
-Key Pairs
-=========
-
-The key included here is the Intel OTC (Opensource Technology Center) community
-development key. It can be freely used by anyone and is intended for reference
-board makers and firmware developers.
-
-** This key is NOT intended for locking down firmware on end user production
-devices since the "private" key has been published here. A new key pair must
-be genrated for securing firmware ! **
-
-RSA Private and Public keys are generated as follows :-
-
-openssl genpkey -algorithm RSA -out private_key.pem -pkeyopt rsa_keygen_bits:2048
-openssl rsa -pubout -in private_key.pem -out public_key.pem
-
-The public key needs to be programmed into the OEM Key manifest (cavsManifest0)
-within the BIOS in order to verify code signed with the private key.
-Intel supplies tools to board makers to stitch the public key into the BIOS.
-
-The private key is used by rimage to sign the SOF binary. It should be kept
-secret and secure for production signing.
\ No newline at end of file
diff --git a/rimage/keys/otc_private_key.pem b/rimage/keys/otc_private_key.pem
deleted file mode 100644
index 03ad749..0000000
--- a/rimage/keys/otc_private_key.pem
+++ /dev/null
@@ -1,28 +0,0 @@
------BEGIN PRIVATE KEY-----
-MIIEvQIBADANBgkqhkiG9w0BAQEFAASCBKcwggSjAgEAAoIBAQC5Q68ZJyiWWrXb
-TSjlj4I/UmgusmIfv5+MCtinahekLPasIvoBhmEAr/TBizlfhj2/VN4FKNsqy7HR
-QGn+iLhqnVrzpEVug4EQIpkFxTnycKMQPSDvpIqq8VL9pUCvKokSMub0oTCwoxjJ
-V81wJy+NE2AnamjtnuJEXqim9U5CGjsnVNSktv/YPbso/LYFjH658Fz5QGgWfbgi
-BPNFwMvemSFOIXw2J2B91ayP9ZJeI2tLyEP9EMeQqU3Gd8T5LfHIUmibpPFe1JDM
-s4HmIEs7Iay03EfwjEWLVd0P/fxv9I9YNTZAi+7o8IyrTNRHDsH55efW7V58GwfS
-66po4QCFAgMBAAECggEBALf7IlktTR47iRv2/WUz5hnyQWoWVmHHD6+oWc2wCzhM
-Os9pkLOQ+qYPF1ZZZ6mYi5uFsVKYZ0aRsM3oVRqkNdgS2m7YtObyC2q1oRdc7JX6
-C8Wlnx69XcQzEcK4qIsMB8Gd8UQBC3RvE79nxanaEFveYP/jqb5IqdVR19SuCYCU
-EZurwwAnYeLg0VSSdVQHSGVMlHkDwhgVAvp5NryPXhml51pT0gzUwnvJOsUcrc0m
-tqUa2yu7/Qju1/JtFL98RgW4x3mSo4TZO3B/d664pWPOxL72zCt7bD9s06ILZmga
-z1oMLMwTaNaeYIBaRvjmssKOqLXmDvfc415V82SwMYUCgYEA2p2At6acrD8Xx5GO
-GeCeUbZzm0Ke9zql1W+Diq89UroFX/i9XO9Mb/ZfwouC+5n3iLjyCG7jIaIwYAyV
-2qim9sINeieepM54HqYz0235nX5CqLHPDobYLn5tsbNYvXYBWiyjRppG+cnprMBk
-O6vLNXNc4sRemgbcmwT3sEYLLo8CgYEA2PInWZx0JoEXriEgefv/IZeyCjpaS9uH
-OOaPVAJTJPaaZhazA4ANV2bzrQAigiXbOgzPkXyldy7T7d/gHfVYnHbyhGwMEa6u
-WMnj5qFXPI0hYOOrJbqXofbfGkKC996eoQybnvE0WdIwscySIki1zAenE/5nVdCJ
-HLwK9xXMKasCgYA/ZxSQrsqbjgTYhVdgG+vuqOqoac7uxtyXpSrSSvaPCpJKfjp1
-PJW/lwW4x3tqewH2biUL2xUWiRJcmOnRK76YrDj6Z4k0JQljYjJ/rFKLobW1dTQm
-82a5PUOVGP2wnQvRWkbUUCQrh6q0xmuLfsyFqPqUbf090KWkc/Fd90KA8wKBgG6C
-q9jSAbi7ebyR02FQJJ6QD3l2UBjkMvWhPNGmfYQOuofWeEoIKMOlBevSbcGuVwYz
-EGkj/YXArOQ3borUN9c8ID2kbGF1ggpojVcmSLHnkmEwmDYX3rX6c5uE1gI9vMB9
-E6jbZbd7gqKPesFMGI9eNpXQugLUv4OLpmpHCEERAoGAMF5P9jSe3JirlZ7WaH7A
-I1I23L3oZfkmrcxP7B860k1ZLHDtx/MtWLkb609fq1Q2lqRuvdoaur1kW+Rv9IHS
-Db8cznu9jIz3OzmJ735lHDpomylzt0+nxL5rrUnoTyMsDK0kIWs03JhPYc0+S2Ip
-lkkvYQHB1eUUCxMnTgzWRr4=
------END PRIVATE KEY-----
diff --git a/rimage/keys/otc_public_key.pem b/rimage/keys/otc_public_key.pem
deleted file mode 100644
index b8662bd..0000000
--- a/rimage/keys/otc_public_key.pem
+++ /dev/null
@@ -1,9 +0,0 @@
------BEGIN PUBLIC KEY-----
-MIIBIjANBgkqhkiG9w0BAQEFAAOCAQ8AMIIBCgKCAQEAuUOvGScollq1200o5Y+C
-P1JoLrJiH7+fjArYp2oXpCz2rCL6AYZhAK/0wYs5X4Y9v1TeBSjbKsux0UBp/oi4
-ap1a86RFboOBECKZBcU58nCjED0g76SKqvFS/aVAryqJEjLm9KEwsKMYyVfNcCcv
-jRNgJ2po7Z7iRF6opvVOQho7J1TUpLb/2D27KPy2BYx+ufBc+UBoFn24IgTzRcDL
-3pkhTiF8NidgfdWsj/WSXiNrS8hD/RDHkKlNxnfE+S3xyFJom6TxXtSQzLOB5iBL
-OyGstNxH8IxFi1XdD/38b/SPWDU2QIvu6PCMq0zURw7B+eXn1u1efBsH0uuqaOEA
-hQIDAQAB
------END PUBLIC KEY-----
diff --git a/rimage/man_apl.c b/rimage/man_apl.c
deleted file mode 100644
index efe8583..0000000
--- a/rimage/man_apl.c
+++ /dev/null
@@ -1,140 +0,0 @@
-/*
- * Copyright (c) 2017, Intel Corporation.
- *
- * This program is free software; you can redistribute it and/or modify it
- * under the terms and conditions of the GNU General Public License,
- * version 2, as published by the Free Software Foundation.
- *
- * This program is distributed in the hope it will be useful, but WITHOUT
- * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
- * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
- * more details.
- */
-
-#include "css.h"
-#include "cse.h"
-#include "plat_auth.h"
-#include "manifest.h"
-#include <config.h>
-#include <version.h>
-
-/* manifest template */
-struct fw_image_manifest apl_manifest = {
-
- .cse_partition_dir_header = {
- .header_marker = CSE_HEADER_MAKER,
- .nb_entries = MAN_CSE_PARTS,
- .header_version = 1,
- .entry_version = 1,
- .header_length = sizeof(struct CsePartitionDirHeader),
- .checksum = 0,
- .partition_name = "ADSP",
- },
-
- .cse_partition_dir_entry = {
- {
- /* CssHeader + platformFirmwareAuthenticationExtension - padding */
- .entry_name = "ADSP.man",
- .offset = MAN_CSS_HDR_OFFSET,
- .length = sizeof(struct css_header) +
- PLAT_AUTH_SIZE,
- },
- { /* ADSPMetadataFileExtension */
- .entry_name = "cavs0015.met",
- .offset = MAN_META_EXT_OFFSET,
- .length = sizeof(struct sof_man_adsp_meta_file_ext),
- },
- { /* AdspFwBinaryDesc */
- .entry_name = "cavs0015",
- .offset = MAN_FW_DESC_OFFSET,
- .length = 0, /* calculated by rimage - */
- },
-
- },
-
- .css = {
- .header_type = MAN_CSS_MOD_TYPE,
- .header_len = MAN_CSS_HDR_SIZE,
- .header_version = MAN_CSS_HDR_VERSION,
- .module_vendor = MAN_CSS_MOD_VENDOR,
- .size = 222,
- .header_id = MAN_CSS_HDR_ID,
- .padding = 0,
- .version = {
- .major_version = SOF_MAJOR,
- .minor_version = SOF_MINOR,
- .hotfix_version = 0,
- .build_version = SOF_BUILD,
- },
- .modulus_size = MAN_CSS_MOD_SIZE,
- .exponent_size = MAN_CSS_EXP_SIZE,
- },
-
- .signed_pkg = {
- .ext_type = SIGN_PKG_EXT_TYPE,
- .ext_len = sizeof(struct signed_pkg_info_ext),
- .name = "ADSP",
- .vcn = 0,
- .bitmap = {0, 0, 0, 0, 8},
-
- .module[0] = {
- .name = "cavs0015.met",
- .meta_size = 96,
- .type = 0x03,
- .hash_algo = 0x02, /* SHA 256 */
- .hash_size = 0x20,
- },
- },
-
- .partition_info = {
-
- .ext_type = PART_INFO_EXT_TYPE,
- .ext_len = sizeof(struct partition_info_ext),
-
- .name = "ADSP",
- .length = 0, /* calculated by rimage - rounded up to nearest PAGE */
- .part_version = 0x10000000,
- .instance_id = 1,
- .reserved[0 ... 19] = 0xff,
-
- .module[0] = {
- .name = "cavs0015.met",
- .meta_size = 96,
- .type = 0x03,
- .reserved = {0x00, 0xff, 0xff},
- },
-
- },
-
- .cse_padding[0 ... 47] = 0xff,
-
- .adsp_file_ext = {
- .ext_type = 17,
- .ext_len = sizeof(struct sof_man_adsp_meta_file_ext),
- .imr_type = 3,
- .comp_desc[0] = {
- .version = 0,
- .base_offset = MAN_DESC_OFFSET,
- .limit_offset = 0, /* calculated length + MAN_DESC_OFFSET */
- },
-
- },
-
- .reserved[0 ... 31] = 0xff,
-
- .desc = {
- .header = {
- .header_id = SOF_MAN_FW_HDR_ID,
- .header_len = sizeof(struct sof_man_fw_header),
- .name = SOF_MAN_FW_HDR_NAME,
- .preload_page_count = 0, /* size in pages from $CPD */
- .fw_image_flags = SOF_MAN_FW_HDR_FLAGS,
- .feature_mask = SOF_MAN_FW_HDR_FEATURES,
- .major_version = SOF_MAJOR,
- .minor_version = SOF_MINOR,
- .hotfix_version = 0,
- .build_version = SOF_BUILD,
- .load_offset = MAN_DESC_OFFSET,
- },
- },
-};
diff --git a/rimage/man_cnl.c b/rimage/man_cnl.c
deleted file mode 100644
index 5ce8c9d..0000000
--- a/rimage/man_cnl.c
+++ /dev/null
@@ -1,139 +0,0 @@
-/*
- * Copyright (c) 2017, Intel Corporation.
- *
- * This program is free software; you can redistribute it and/or modify it
- * under the terms and conditions of the GNU General Public License,
- * version 2, as published by the Free Software Foundation.
- *
- * This program is distributed in the hope it will be useful, but WITHOUT
- * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
- * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
- * more details.
- */
-
-#include "css.h"
-#include "cse.h"
-#include "plat_auth.h"
-#include "manifest.h"
-#include <config.h>
-#include <version.h>
-
-/* manifest template */
-struct fw_image_manifest cnl_manifest = {
-
- .cse_partition_dir_header = {
- .header_marker = CSE_HEADER_MAKER,
- .nb_entries = MAN_CSE_PARTS,
- .header_version = 1,
- .entry_version = 1,
- .header_length = sizeof(struct CsePartitionDirHeader),
- .partition_name = "ADSP",
- },
-
- .cse_partition_dir_entry = {
- {
- /* CssHeader + platformFirmwareAuthenticationExtension - padding */
- .entry_name = "ADSP.man",
- .offset = MAN_CSS_HDR_OFFSET,
- .length = sizeof(struct css_header) +
- PLAT_AUTH_SIZE,
- },
- { /* ADSPMetadataFileExtension */
- .entry_name = "cavs0015.met",
- .offset = MAN_META_EXT_OFFSET,
- .length = sizeof(struct sof_man_adsp_meta_file_ext),
- },
- { /* AdspFwBinaryDesc */
- .entry_name = "cavs0015",
- .offset = MAN_FW_DESC_OFFSET,
- .length = 0, /* calculated by rimage - */
- },
-
- },
-
- .css = {
- .header_type = MAN_CSS_MOD_TYPE,
- .header_len = MAN_CSS_HDR_SIZE,
- .header_version = MAN_CSS_HDR_VERSION,
- .module_vendor = MAN_CSS_MOD_VENDOR,
- .size = 222,
- .header_id = MAN_CSS_HDR_ID,
- .padding = 0,
- .version = {
- .major_version = SOF_MAJOR,
- .minor_version = SOF_MINOR,
- .hotfix_version = 0,
- .build_version = SOF_BUILD,
- },
- .modulus_size = MAN_CSS_MOD_SIZE,
- .exponent_size = MAN_CSS_EXP_SIZE,
- },
-
- .signed_pkg = {
- .ext_type = SIGN_PKG_EXT_TYPE,
- .ext_len = sizeof(struct signed_pkg_info_ext),
- .name = "ADSP",
- .vcn = 0,
- .bitmap = {0, 0, 0, 0, 8},
-
- .module[0] = {
- .name = "cavs0015.met",
- .meta_size = 96,
- .type = 0x03,
- .hash_algo = 0x02, /* SHA 256 */
- .hash_size = 0x20,
- },
- },
-
- .partition_info = {
-
- .ext_type = PART_INFO_EXT_TYPE,
- .ext_len = sizeof(struct partition_info_ext),
-
- .name = "ADSP",
- .length = 0, /* calculated by rimage - rounded up to nearest PAGE */
- .part_version = 0x10000000,
- .instance_id = 1,
- .reserved[0 ... 19] = 0xff,
-
- .module[0] = {
- .name = "cavs0015.met",
- .meta_size = 96,
- .type = 0x03,
- .reserved = {0x00, 0xff, 0xff},
- },
-
- },
-
- .cse_padding[0 ... 47] = 0xff,
-
- .adsp_file_ext = {
- .ext_type = 17,
- .ext_len = sizeof(struct sof_man_adsp_meta_file_ext),
- .imr_type = 3,
- .comp_desc[0] = {
- .version = 0,
- .base_offset = MAN_DESC_OFFSET,
- .limit_offset = 0, /* calculated length + MAN_DESC_OFFSET */
- },
-
- },
-
- .reserved[0 ... 31] = 0xff,
-
- .desc = {
- .header = {
- .header_id = SOF_MAN_FW_HDR_ID,
- .header_len = sizeof(struct sof_man_fw_header),
- .name = SOF_MAN_FW_HDR_NAME,
- .preload_page_count = 0, /* size in pages from $CPD */
- .fw_image_flags = SOF_MAN_FW_HDR_FLAGS,
- .feature_mask = SOF_MAN_FW_HDR_FEATURES,
- .major_version = SOF_MAJOR,
- .minor_version = SOF_MINOR,
- .hotfix_version = 0,
- .build_version = SOF_BUILD,
- .load_offset = 0x30000,
- },
- },
-};
diff --git a/rimage/manifest.c b/rimage/manifest.c
deleted file mode 100644
index b758717..0000000
--- a/rimage/manifest.c
+++ /dev/null
@@ -1,858 +0,0 @@
-/*
- * Copyright (c) 2017, Intel Corporation.
- *
- * This program is free software; you can redistribute it and/or modify it
- * under the terms and conditions of the GNU General Public License,
- * version 2, as published by the Free Software Foundation.
- *
- * This program is distributed in the hope it will be useful, but WITHOUT
- * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
- * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
- * more details.
- *
- * Author: Liam Girdwood <liam.r.girdwood@linux.intel.com>
- * Keyon Jie <yang.jie@linux.intel.com>
- */
-
-
-#include <stdlib.h>
-#include <stdio.h>
-#include <unistd.h>
-#include <errno.h>
-#include <string.h>
-#include <time.h>
-#include <sys/time.h>
-
-#include "uapi/manifest.h"
-#include "rimage.h"
-#include "file_format.h"
-#include "css.h"
-#include "cse.h"
-#include "plat_auth.h"
-#include "manifest.h"
-
-static int man_open_rom_file(struct image *image)
-{
- sprintf(image->out_rom_file, "%s.rom", image->out_file);
- unlink(image->out_rom_file);
-
- /* allocate ROM image */
- image->rom_image = calloc(image->adsp->rom_size, 1);
- if (image->rom_image == NULL)
- return -ENOMEM;
-
- /* open ROM outfile for writing */
- image->out_rom_fd = fopen(image->out_rom_file, "w");
- if (image->out_rom_fd == NULL) {
- fprintf(stderr, "error: unable to open %s for writing %d\n",
- image->out_rom_file, errno);
- }
-
- return 0;
-}
-
-static int man_open_unsigned_file(struct image *image)
-{
- sprintf(image->out_unsigned_file, "%s.uns", image->out_file);
- unlink(image->out_unsigned_file);
-
- /* open unsigned FW outfile for writing */
- image->out_unsigned_fd = fopen(image->out_unsigned_file, "w");
- if (image->out_unsigned_fd == NULL) {
- fprintf(stderr, "error: unable to open %s for writing %d\n",
- image->out_unsigned_file, errno);
- }
-
- return 0;
-}
-
-static int man_open_manifest_file(struct image *image)
-{
- /* open manifest outfile for writing */
- sprintf(image->out_man_file, "%s.met", image->out_file);
- unlink(image->out_man_file);
-
- image->out_man_fd = fopen(image->out_man_file, "w");
- if (image->out_man_fd == NULL) {
- fprintf(stderr, "error: unable to open %s for writing %d\n",
- image->out_man_file, errno);
- }
-
- return 0;
-}
-
-static int man_init_image(struct image *image)
-{
- /* allocate image and copy template manifest */
- image->fw_image = calloc(image->adsp->image_size, 1);
- if (image->fw_image == NULL)
- return -ENOMEM;
-
- memcpy(image->fw_image, image->adsp->man,
- sizeof(struct fw_image_manifest));
-
- return 0;
-}
-
-/* we should call this after all segments size set up via iterate */
-static uint32_t elf_to_file_offset(struct image *image,
- struct module *module, struct sof_man_module *man_module,
- Elf32_Shdr *section)
-{
- uint32_t elf_addr = section->sh_addr, file_offset = 0;
-
- if (section->sh_type == SHT_PROGBITS) {
- if (section->sh_flags & SHF_EXECINSTR) {
- /* text segment */
- file_offset = elf_addr - module->text_start +
- module->foffset;
- } else {
- /* rodata segment, append to text segment */
- file_offset = elf_addr - module->data_start +
- module->foffset + module->text_fixup_size;
-
- }
- } else if (section->sh_type == SHT_NOBITS) {
- /* bss segment */
- file_offset = 0;
- }
-
- return file_offset;
-}
-
-/* write SRAM sections */
-static int man_copy_sram(struct image *image, Elf32_Shdr *section,
- struct module *module, struct sof_man_module *man_module,
- int section_idx)
-{
- uint32_t offset = elf_to_file_offset(image, module,
- man_module, section);
- uint32_t end = offset + section->sh_size;
- int seg_type = -1;
- void *buffer = image->fw_image + offset;
- size_t count;
-
- switch (section->sh_type) {
- case SHT_PROGBITS:
- /* text or data */
- if (section->sh_flags & SHF_EXECINSTR)
- seg_type = SOF_MAN_SEGMENT_TEXT;
- else
- seg_type = SOF_MAN_SEGMENT_RODATA;
- break;
- case SHT_NOBITS:
- seg_type = SOF_MAN_SEGMENT_BSS;
- default:
- return 0;
- }
-
- /* file_offset for segment should not be 0s, we set it to
- * the smallest offset of its modules ATM.
- */
- if (man_module->segment[seg_type].file_offset > offset ||
- man_module->segment[seg_type].file_offset == 0)
- man_module->segment[seg_type].file_offset = offset;
-
- count = fread(buffer, 1, section->sh_size, module->fd);
- if (count != section->sh_size) {
- fprintf(stderr, "error: cant read section %d\n", -errno);
- return -errno;
- }
-
- /* get module end offset ? */
- if (end > image->image_end)
- image->image_end = end;
-
- fprintf(stdout, "\t%d\t0x%x\t0x%x\t\t0x%x\t%s\n", section_idx,
- section->sh_addr, section->sh_size, offset,
- seg_type == SOF_MAN_SEGMENT_TEXT ? "TEXT" : "DATA");
-
- return 0;
-}
-
-static int man_copy_elf_section(struct image *image, Elf32_Shdr *section,
- struct module *module, struct sof_man_module *man_module, int idx)
-{
- int ret;
-
- /* seek to ELF section */
- ret = fseek(module->fd, section->sh_offset, SEEK_SET);
- if (ret < 0) {
- fprintf(stderr, "error: can't seek to section %d\n", ret);
- return ret;
- }
-
- /* write data to DRAM or ROM image */
- if (!elf_is_rom(image, section))
- return man_copy_sram(image, section, module, man_module, idx);
-
- return 0;
-}
-
-static int man_get_module_manifest(struct image *image, struct module *module,
- struct sof_man_module *man_module)
-{
- Elf32_Shdr *section;
- struct sof_man_segment_desc *segment;
- struct sof_man_module_manifest sof_mod;
- size_t count;
- int ret, man_section_idx;
-
- fprintf(stdout, "Module Write: %s\n", module->elf_file);
-
- /* find manifest module data */
- man_section_idx = elf_find_section(image, module, ".module");
- if (man_section_idx < 0) {
- return -EINVAL;
- }
-
- fprintf(stdout, " Manifest module metadata section at index %d\n",
- man_section_idx);
- section = &module->section[man_section_idx];
-
- /* load in manifest data */
- /* module built using xcc has preceding bytes */
- if (section->sh_size > sizeof(sof_mod))
- ret = fseek(module->fd,
- section->sh_offset + XCC_MOD_OFFSET, SEEK_SET);
- else
- ret = fseek(module->fd, section->sh_offset, SEEK_SET);
-
- if (ret < 0) {
- fprintf(stderr, "error: can't seek to section %d\n", ret);
- return ret;
- }
-
- count = fread(&sof_mod, 1, sizeof(sof_mod), module->fd);
- if (count != sizeof(sof_mod)) {
- fprintf(stderr, "error: can't read section %d\n", -errno);
- return -errno;
- }
-
- /* configure man_module with sofmod data */
- memcpy(man_module->struct_id, "$AME", 4);
- man_module->entry_point = sof_mod.module.entry_point;
- memcpy(man_module->name, sof_mod.module.name, SOF_MAN_MOD_NAME_LEN);
- memcpy(man_module->uuid, sof_mod.module.uuid, 16);
- man_module->affinity_mask = sof_mod.module.affinity_mask;
- man_module->type.auto_start = sof_mod.module.type.auto_start;
- man_module->type.domain_dp = sof_mod.module.type.domain_dp;
- man_module->type.domain_ll = sof_mod.module.type.domain_ll;
- man_module->type.load_type = sof_mod.module.type.load_type;
-
- /* read out text_fixup_size from memory mapping */
- module->text_fixup_size = sof_mod.text_size;
-
- /* text segment */
- segment = &man_module->segment[SOF_MAN_SEGMENT_TEXT];
- segment->flags.r.contents = 1;
- segment->flags.r.alloc = 1;
- segment->flags.r.load = 1;
- segment->flags.r.readonly = 1;
- segment->flags.r.code = 1;
-
- /* data segment */
- segment = &man_module->segment[SOF_MAN_SEGMENT_RODATA];
- segment->flags.r.contents = 1;
- segment->flags.r.alloc = 1;
- segment->flags.r.load = 1;
- segment->flags.r.readonly = 1;
- segment->flags.r.data = 1;
- segment->flags.r.type = 1;
-
- /* bss segment */
- segment = &man_module->segment[SOF_MAN_SEGMENT_BSS];
- segment->flags.r.alloc = 1;
- segment->flags.r.type = 2;
-
- fprintf(stdout, " Entry point 0x%8.8x\n", man_module->entry_point);
-
- return 0;
-}
-
-static inline const char *segment_name(int i)
-{
- switch (i) {
- case SOF_MAN_SEGMENT_TEXT:
- return "TEXT";
- case SOF_MAN_SEGMENT_RODATA:
- return "DATA";
- case SOF_MAN_SEGMENT_BSS:
- return "BSS";
- default:
- return "NONE";
- }
-}
-
-/* make sure no segments collide */
-static int man_module_validate(struct sof_man_module *man_module)
-{
- uint32_t istart, iend;
- uint32_t jstart, jend;
- int i, j;
-
- for (i = 0; i < 3; i++) {
-
- istart = man_module->segment[i].v_base_addr;
- iend = istart + man_module->segment[i].flags.r.length *
- MAN_PAGE_SIZE;
-
- for (j = 0; j < 3; j++) {
-
- /* don't validate segment against itself */
- if (i == j)
- continue;
-
- jstart = man_module->segment[j].v_base_addr;
- jend = jstart + man_module->segment[j].flags.r.length *
- MAN_PAGE_SIZE;
-
- if (jstart > istart && jstart < iend)
- goto err;
-
- if (jend > istart && jend < iend)
- goto err;
- }
- }
-
- /* success, no overlapping segments */
- return 0;
-
-err:
- fprintf(stderr, "error: segment %s [0x%8.8x:0x%8.8x] overlaps",
- segment_name(i), istart, iend);
- fprintf(stderr, " with %s [0x%8.8x:0x%8.8x]\n",
- segment_name(j), jstart, jend);
- return -EINVAL;
-}
-
-static int man_module_create(struct image *image, struct module *module,
- struct sof_man_module *man_module)
-{
- /* create module and segments */
- uint32_t valid = (SHF_WRITE | SHF_ALLOC | SHF_EXECINSTR);
- Elf32_Shdr *section;
- int i, err;
- unsigned int pages;
-
- image->image_end = 0;
-
- err = man_get_module_manifest(image, module, man_module);
- if (err < 0)
- return err;
-
- /* stack size ??? convert sizes to PAGES */
- man_module->instance_bss_size = 1;
-
- /* max number of instances of this module ?? */
- man_module->instance_max_count = 1;
-
- fprintf(stdout, "\n\tTotals\tStart\t\tEnd\t\tSize");
-
- fprintf(stdout, "\n\tTEXT\t0x%8.8x\t0x%8.8x\t0x%x\n",
- module->text_start, module->text_end,
- module->text_end - module->text_start);
- fprintf(stdout, "\tDATA\t0x%8.8x\t0x%8.8x\t0x%x\n",
- module->data_start, module->data_end,
- module->data_end - module->data_start);
- fprintf(stdout, "\tBSS\t0x%8.8x\t0x%8.8x\t0x%x\n\n ",
- module->bss_start, module->bss_end,
- module->bss_end - module->bss_start);
-
- /* main module */
- /* text section is first */
- man_module->segment[SOF_MAN_SEGMENT_TEXT].file_offset =
- module->foffset;
- man_module->segment[SOF_MAN_SEGMENT_TEXT].v_base_addr =
- module->text_start;
-
- /* calculates those padding 0s by the start of next segment */
- pages = module->text_file_size / MAN_PAGE_SIZE;
- if (module->text_file_size % MAN_PAGE_SIZE)
- pages += 1;
-
- if (module->text_fixup_size == 0)
- module->text_fixup_size = module->text_file_size;
-
- /* check if text_file_size is bigger then text_fixup_size */
- if (module->text_file_size > module->text_fixup_size) {
- fprintf(stderr, "error: too small text size assigned!\n");
- return -EINVAL;
- }
-
- man_module->segment[SOF_MAN_SEGMENT_TEXT].flags.r.length = pages;
-
- /* data section */
- man_module->segment[SOF_MAN_SEGMENT_RODATA].v_base_addr =
- module->data_start;
- man_module->segment[SOF_MAN_SEGMENT_RODATA].file_offset =
- module->foffset + module->text_fixup_size;
- pages = module->data_file_size / MAN_PAGE_SIZE;
- if (module->data_file_size % MAN_PAGE_SIZE)
- pages += 1;
-
- man_module->segment[SOF_MAN_SEGMENT_RODATA].flags.r.length = pages;
-
- /* bss is last */
- man_module->segment[SOF_MAN_SEGMENT_BSS].file_offset = 0;
- man_module->segment[SOF_MAN_SEGMENT_BSS].v_base_addr = module->bss_start;
- pages = (module->bss_end - module->bss_start) / MAN_PAGE_SIZE;
- if ((module->bss_end - module->bss_start) % MAN_PAGE_SIZE)
- pages += 1;
- man_module->segment[SOF_MAN_SEGMENT_BSS].flags.r.length = pages;
- if (pages == 0) {
- man_module->segment[SOF_MAN_SEGMENT_BSS].flags.ul = 0;
- man_module->segment[SOF_MAN_SEGMENT_BSS].flags.r.type =
- SOF_MAN_SEGMENT_EMPTY;
- }
-
- fprintf(stdout, "\tNo\tAddress\t\tSize\t\tFile\tType\n");
-
- if (man_module_validate(man_module) < 0)
- return -EINVAL;
-
- /* find all sections and copy to corresponding segments */
- for (i = 0; i < module->hdr.e_shnum; i++) {
-
- section = &module->section[i];
-
- /* only check valid sections */
- if (!(section->sh_flags & valid))
- continue;
-
- if (section->sh_size == 0)
- continue;
-
- /* text or data section */
- if (!elf_is_rom(image, section))
- err = man_copy_elf_section(image, section, module,
- man_module, i);
-
- if (err < 0) {
- fprintf(stderr, "error: failed to write section #%d\n", i);
- return err;
- }
- }
- fprintf(stdout, "\n");
-
- /* round module end upto nearest page */
- if (image->image_end % MAN_PAGE_SIZE) {
- image->image_end = (image->image_end / MAN_PAGE_SIZE) + 1;
- image->image_end *= MAN_PAGE_SIZE;
- }
-
- fprintf(stdout, " Total pages text %d data %d bss %d module file limit: 0x%x\n\n",
- man_module->segment[SOF_MAN_SEGMENT_TEXT].flags.r.length,
- man_module->segment[SOF_MAN_SEGMENT_RODATA].flags.r.length,
- man_module->segment[SOF_MAN_SEGMENT_BSS].flags.r.length,
- image->image_end);
- return 0;
-}
-
-static int man_module_create_reloc(struct image *image, struct module *module,
- struct sof_man_module *man_module)
-{
- /* create module and segments */
- int err;
- unsigned int pages;
- void *buffer = image->fw_image + module->foffset;
- size_t count;
-
- image->image_end = 0;
-
- err = man_get_module_manifest(image, module, man_module);
- if (err < 0)
- return err;
-
- /* stack size ??? convert sizes to PAGES */
- man_module->instance_bss_size = 1;
-
- /* max number of instances of this module ?? */
- man_module->instance_max_count = 1;
-
- fprintf(stdout, "\n\tTotals\tStart\t\tEnd\t\tSize");
-
- fprintf(stdout, "\n\tTEXT\t0x%8.8x\t0x%8.8x\t0x%x\n",
- module->text_start, module->text_end,
- module->text_end - module->text_start);
- fprintf(stdout, "\tDATA\t0x%8.8x\t0x%8.8x\t0x%x\n",
- module->data_start, module->data_end,
- module->data_end - module->data_start);
- fprintf(stdout, "\tBSS\t0x%8.8x\t0x%8.8x\t0x%x\n\n ",
- module->bss_start, module->bss_end,
- module->bss_end - module->bss_start);
-
- /* main module */
- /* text section is first */
- man_module->segment[SOF_MAN_SEGMENT_TEXT].file_offset =
- module->foffset;
- man_module->segment[SOF_MAN_SEGMENT_TEXT].v_base_addr = 0;
- man_module->segment[SOF_MAN_SEGMENT_TEXT].flags.r.length = 0;
-
- /* data section */
- man_module->segment[SOF_MAN_SEGMENT_RODATA].v_base_addr = 0;
- man_module->segment[SOF_MAN_SEGMENT_RODATA].file_offset =
- module->foffset;
- pages = module->data_file_size / MAN_PAGE_SIZE;
- if (module->data_file_size % MAN_PAGE_SIZE)
- pages += 1;
-
- man_module->segment[SOF_MAN_SEGMENT_RODATA].flags.r.length = pages;
-
- /* bss is last */
- man_module->segment[SOF_MAN_SEGMENT_BSS].file_offset = 0;
- man_module->segment[SOF_MAN_SEGMENT_BSS].v_base_addr = 0;
- man_module->segment[SOF_MAN_SEGMENT_BSS].flags.r.length = 0;
-
- fprintf(stdout, "\tNo\tAddress\t\tSize\t\tFile\tType\n");
-
- /* seek to beginning of file */
- err = fseek(module->fd, 0, SEEK_SET);
- if (err < 0) {
- fprintf(stderr, "error: can't seek to section %d\n", err);
- return err;
- }
-
- count = fread(buffer, 1, module->file_size, module->fd);
- if (count != module->file_size) {
- fprintf(stderr, "error: can't read section %d\n", -errno);
- return -errno;
- }
-
- fprintf(stdout, "\t%d\t0x%8.8x\t0x%8.8x\t0x%x\t%s\n", 0,
- 0, module->file_size, 0, "DATA");
-
- fprintf(stdout, "\n");
- image->image_end = module->foffset + module->file_size;
-
- /* round module end up to nearest page */
- if (image->image_end % MAN_PAGE_SIZE) {
- image->image_end = (image->image_end / MAN_PAGE_SIZE) + 1;
- image->image_end *= MAN_PAGE_SIZE;
- }
-
- fprintf(stdout, " Total pages text %d data %d bss %d module file limit: 0x%x\n\n",
- man_module->segment[SOF_MAN_SEGMENT_TEXT].flags.r.length,
- man_module->segment[SOF_MAN_SEGMENT_RODATA].flags.r.length,
- man_module->segment[SOF_MAN_SEGMENT_BSS].flags.r.length,
- image->image_end);
- return 0;
-}
-
-static int man_write_unsigned_mod(struct image *image, int meta_start_offset,
- int meta_end_offset)
-{
- int count;
-
- /* write metadata file for unsigned FW */
- count = fwrite(image->fw_image + meta_start_offset,
- sizeof(struct sof_man_adsp_meta_file_ext), 1,
- image->out_man_fd);
-
- /* did the metadata/manifest write succeed ? */
- if (count != 1) {
- fprintf(stderr, "error: failed to write meta %s %d\n",
- image->out_man_file, -errno);
- return -errno;
- }
- fclose(image->out_man_fd);
-
- /* now prepare the unsigned rimage */
- count = fwrite(image->fw_image + meta_end_offset,
- image->image_end - meta_end_offset,
- 1, image->out_unsigned_fd);
-
- /* did the unsigned FW write succeed ? */
- if (count != 1) {
- fprintf(stderr, "error: failed to write firmware %s %d\n",
- image->out_unsigned_file, -errno);
- return -errno;
- }
- fclose(image->out_unsigned_fd);
-
- return 0;
-}
-
-static int man_write_fw_mod(struct image *image)
-{
- int count;
-
- /* write ROM - for VM use only */
- count = fwrite(image->rom_image, image->adsp->rom_size, 1,
- image->out_rom_fd);
- if (count != 1) {
- fprintf(stderr, "error: failed to write rom %s %d\n",
- image->out_rom_file, -errno);
- return -errno;
- }
- fclose(image->out_rom_fd);
-
- /* write manifest and signed image */
- count = fwrite(image->fw_image,
- image->image_end,
- 1, image->out_fd);
-
- /* did the image write succeed ? */
- if (count != 1) {
- fprintf(stderr, "error: failed to write signed firmware %s %d\n",
- image->out_file, -errno);
- return -errno;
- }
-
- return 0;
-}
-
-static int man_create_modules(struct image *image, struct sof_man_fw_desc *desc)
-{
- struct module *module;
- struct sof_man_module *man_module;
- int err;
- int i;
-
- for (i = 0; i < image->num_modules; i++) {
- man_module = sof_man_get_module(desc, i);
- module = &image->module[i];
-
- /* set module file offset */
- if (i == 0)
- module->foffset = FILE_TEXT_OFFSET;
- else
- module->foffset = image->image_end;
-
- if (image->reloc)
- err = man_module_create_reloc(image, module,
- man_module);
- else
- err = man_module_create(image, module, man_module);
-
- if (err < 0)
- return err;
- }
-
- return 0;
-}
-
-static int man_hash_modules(struct image *image, struct sof_man_fw_desc *desc)
-{
- struct sof_man_module *man_module;
- int i;
-
- for (i = 0; i < image->num_modules; i++) {
- man_module = sof_man_get_module(desc, i);
-
- ri_hash(image,
- man_module->segment[SOF_MAN_SEGMENT_TEXT].file_offset,
- (man_module->segment[SOF_MAN_SEGMENT_TEXT].flags.r.length +
- man_module->segment[SOF_MAN_SEGMENT_RODATA].flags.r.length) *
- MAN_PAGE_SIZE, man_module->hash);
- }
-
- return 0;
-}
-
-/* used by others */
-static int man_write_fw(struct image *image)
-{
- struct sof_man_fw_desc *desc;
- struct fw_image_manifest *m;
- uint8_t hash[SOF_MAN_MOD_SHA256_LEN];
- int ret, i;
-
- /* init image */
- ret = man_init_image(image);
- if (ret < 0)
- goto err;
-
- /* open ROM image */
- ret = man_open_rom_file(image);
- if (ret < 0)
- goto err;
-
- /* open unsigned firmware */
- ret = man_open_unsigned_file(image);
- if (ret < 0)
- goto err;
-
- /* create the manifest */
- ret = man_open_manifest_file(image);
- if (ret < 0)
- goto err;
-
- /* create the module */
- m = image->fw_image;
- desc = image->fw_image + MAN_DESC_OFFSET;
-
- /* create each module */
- m->desc.header.num_module_entries = image->num_modules;
- man_create_modules(image, desc);
-
- fprintf(stdout, "Firmware completing manifest\n");
-
- /* create structures from end of file to start of file */
- ri_adsp_meta_data_create(image, MAN_META_EXT_OFFSET,
- MAN_FW_DESC_OFFSET);
- ri_plat_ext_data_create(image);
- ri_css_hdr_create(image);
- ri_cse_create(image);
-
- fprintf(stdout, "Firmware file size 0x%x page count %d\n",
- FILE_TEXT_OFFSET - MAN_DESC_OFFSET + image->image_end,
- desc->header.preload_page_count);
-
- /* calculate hash for each module */
- man_hash_modules(image, desc);
-
- /* calculate hash for ADSP meta data extension - 0x480 to end */
- ri_hash(image, MAN_FW_DESC_OFFSET, image->image_end
- - MAN_FW_DESC_OFFSET, m->adsp_file_ext.comp_desc[0].hash);
-
- /* calculate hash for platform auth data - repeated in hash 2 and 4 */
- ri_hash(image, MAN_META_EXT_OFFSET,
- sizeof(struct sof_man_adsp_meta_file_ext), hash);
-
- /* hash values in reverse order */
- for (i = 0; i < SOF_MAN_MOD_SHA256_LEN; i++) {
- m->signed_pkg.module[0].hash[i] =
- m->partition_info.module[0].hash[i] =
- hash[SOF_MAN_MOD_SHA256_LEN - 1 - i];
- }
-
- /* sign manifest */
- ret = ri_manifest_sign(image);
- if (ret < 0)
- goto err;
-
- /* write the firmware */
- ret = man_write_fw_mod(image);
- if (ret < 0)
- goto err;
-
- /* write the unsigned files*/
- ret = man_write_unsigned_mod(image, MAN_META_EXT_OFFSET,
- MAN_FW_DESC_OFFSET);
- if (ret < 0)
- goto err;
-
- fprintf(stdout, "Firmware manifest and signing completed !\n");
- return 0;
-
-err:
- free(image->rom_image);
- free(image->fw_image);
- unlink(image->out_file);
- unlink(image->out_rom_file);
- return ret;
-}
-
-/* used to sign with MEU */
-static int man_write_fw_meu(struct image *image)
-{
- const int meta_start_offset = image->meu_offset -
- sizeof(struct sof_man_adsp_meta_file_ext) - MAN_EXT_PADDING;
- struct sof_man_adsp_meta_file_ext *meta;
- struct sof_man_fw_desc *desc;
- uint32_t preload_size;
- int ret;
-
- /* allocate image */
- image->fw_image = calloc(image->adsp->image_size, 1);
- if (image->fw_image == NULL) {
- ret = -ENOMEM;
- goto err;
- }
-
- /* open unsigned firmware */
- ret = man_open_unsigned_file(image);
- if (ret < 0)
- goto err;
-
- /* create the manifest */
- ret = man_open_manifest_file(image);
- if (ret < 0)
- goto err;
-
- /* create the module */
- meta = image->fw_image + meta_start_offset;
- desc = image->fw_image + MAN_DESC_OFFSET;
-
- /* copy data */
- memcpy(meta, &image->adsp->man->adsp_file_ext,
- sizeof(struct sof_man_adsp_meta_file_ext));
- memcpy(desc, &image->adsp->man->desc,
- sizeof(struct sof_man_fw_desc));
-
- /* create each module */
- desc->header.num_module_entries = image->num_modules;
- man_create_modules(image, desc);
-
- fprintf(stdout, "Firmware completing manifest\n");
-
- /* create structures from end of file to start of file */
- ri_adsp_meta_data_create(image, meta_start_offset, image->meu_offset);
-
- /* write preload page count */
- preload_size = meta->comp_desc[0].limit_offset - MAN_DESC_OFFSET;
- preload_size += MAN_PAGE_SIZE - (preload_size % MAN_PAGE_SIZE);
- desc->header.preload_page_count = preload_size / MAN_PAGE_SIZE;
-
- /* calculate hash for each module */
- man_hash_modules(image, desc);
-
- /* calculate hash for ADSP meta data extension */
- ri_hash(image, image->meu_offset, image->image_end -
- image->meu_offset, meta->comp_desc[0].hash);
-
- /* write the unsigned files */
- ret = man_write_unsigned_mod(image, meta_start_offset,
- image->meu_offset);
- if (ret < 0)
- goto err;
-
- fprintf(stdout, "Firmware manifest completed!\n");
- return 0;
-
-err:
- free(image->fw_image);
- unlink(image->out_file);
- return ret;
-}
-
-#define ADSP_APL_DSP_ROM_BASE 0xBEFE0000
-#define ADSP_APL_DSP_ROM_SIZE 0x00002000
-#define APL_DSP_BASE_ENTRY 0xa000a000
-
-#define ADSP_CNL_DSP_ROM_BASE 0xBEFE0000
-#define ADSP_CNL_DSP_ROM_SIZE 0x00002000
-#define CNL_DSP_IMR_BASE_ENTRY 0xb0038000
-#define CNL_DSP_HP_BASE_ENTRY 0xbe040000
-
-/* list of supported adsp */
-const struct adsp machine_apl = {
- .name = "apl",
- .rom_base = ADSP_APL_DSP_ROM_BASE,
- .rom_size = ADSP_APL_DSP_ROM_SIZE,
- .sram_base = APL_DSP_BASE_ENTRY,
- .sram_size = 0x100000,
- .image_size = 0x100000,
- .dram_offset = 0,
- .machine_id = MACHINE_APOLLOLAKE,
- .write_firmware = man_write_fw,
- .write_firmware_meu = man_write_fw_meu,
- .man = &apl_manifest,
-};
-
-const struct adsp machine_cnl = {
- .name = "cnl",
- .rom_base = ADSP_CNL_DSP_ROM_BASE,
- .rom_size = ADSP_CNL_DSP_ROM_SIZE,
- .imr_base = CNL_DSP_IMR_BASE_ENTRY,
- .imr_size = 0x100000,
- .sram_base = CNL_DSP_HP_BASE_ENTRY,
- .sram_size = 0x100000,
- .image_size = 0x100000,
- .dram_offset = 0,
- .machine_id = MACHINE_CANNONLAKE,
- .write_firmware = man_write_fw,
- .write_firmware_meu = man_write_fw_meu,
- .man = &cnl_manifest,
-};
diff --git a/rimage/manifest.h b/rimage/manifest.h
deleted file mode 100644
index 8d1d3d2..0000000
--- a/rimage/manifest.h
+++ /dev/null
@@ -1,93 +0,0 @@
-/*
- * Copyright (c) 2017, Intel Corporation.
- *
- * This program is free software; you can redistribute it and/or modify it
- * under the terms and conditions of the GNU General Public License,
- * version 2, as published by the Free Software Foundation.
- *
- * This program is distributed in the hope it will be useful, but WITHOUT
- * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
- * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
- * more details.
- */
-
-#ifndef __MANIFEST_H__
-#define __MANIFEST_H__
-
-#include <stdint.h>
-#include "uapi/manifest.h"
-#include "css.h"
-#include "cse.h"
-#include "plat_auth.h"
-
-#define MAN_PAGE_SIZE 4096
-
-/* start offset for modules built using xcc */
-#define XCC_MOD_OFFSET 0x8
-
-/* start offset for base FW module */
-#define FILE_TEXT_OFFSET 0x8000
-
-/*
- * CSE values for CNL
- */
-#define MAN_CSE_PARTS 3
-
-
-#define MAN_CSE_HDR_OFFSET 0
-#define MAN_CSE_PADDING_SIZE 0x30
-#define MAN_EXT_PADDING 0x20
-#define MAN_DESC_OFFSET 0x2000
-
-#define MAN_CSS_HDR_OFFSET \
- (MAN_CSE_HDR_OFFSET + \
- sizeof(struct CsePartitionDirHeader) + \
- MAN_CSE_PARTS * sizeof(struct CsePartitionDirEntry))
-
-#define MAN_SIG_PKG_OFFSET \
- (MAN_CSS_HDR_OFFSET + \
- sizeof(struct css_header))
-
-#define MAN_PART_INFO_OFFSET \
- (MAN_SIG_PKG_OFFSET + \
- sizeof(struct signed_pkg_info_ext))
-
-#define MAN_META_EXT_OFFSET \
- (MAN_SIG_PKG_OFFSET + \
- sizeof(struct signed_pkg_info_ext) + \
- sizeof(struct partition_info_ext) + \
- MAN_CSE_PADDING_SIZE)
-
-#define MAN_FW_DESC_OFFSET \
- (MAN_META_EXT_OFFSET + \
- sizeof(struct sof_man_adsp_meta_file_ext) + \
- MAN_EXT_PADDING)
-
-#define MAN_DESC_PADDING_SIZE \
- (MAN_DESC_OFFSET - MAN_FW_DESC_OFFSET)
-
-/*
- * Firmware manifest header.
- */
-struct fw_image_manifest {
- /* MEU tool needs these sections to be 0s */
- struct CsePartitionDirHeader cse_partition_dir_header;
- struct CsePartitionDirEntry cse_partition_dir_entry[MAN_CSE_PARTS];
- struct css_header css;
- struct signed_pkg_info_ext signed_pkg;
- struct partition_info_ext partition_info;
- uint8_t cse_padding[MAN_CSE_PADDING_SIZE];
- struct sof_man_adsp_meta_file_ext adsp_file_ext;
-
- /* reserved / pading at end of ext data - all 0s*/
- uint8_t reserved[MAN_EXT_PADDING];
-
- /* start of the unsigned binary for MEU input must start at MAN_DESC_OFFSET */
- uint8_t padding[MAN_DESC_PADDING_SIZE];
-
- struct sof_man_fw_desc desc; /* at offset MAN_DESC_OFFSET */
-} __attribute__((packed));
-
-extern struct fw_image_manifest apl_manifest;
-extern struct fw_image_manifest cnl_manifest;
-#endif
diff --git a/rimage/pkcs1_5.c b/rimage/pkcs1_5.c
deleted file mode 100644
index 9253594..0000000
--- a/rimage/pkcs1_5.c
+++ /dev/null
@@ -1,163 +0,0 @@
-/*
- * Copyright (c) 2017, Intel Corporation.
- *
- * This program is free software; you can redistribute it and/or modify it
- * under the terms and conditions of the GNU General Public License,
- * version 2, as published by the Free Software Foundation.
- *
- * This program is distributed in the hope it will be useful, but WITHOUT
- * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
- * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
- * more details.
- *
- * Author: Liam Girdwood <liam.r.girdwood@linux.intel.com>
- * Keyon Jie <yang.jie@linux.intel.com>
- */
-
-#include <openssl/pem.h>
-#include <openssl/ssl.h>
-#include <openssl/rsa.h>
-#include <openssl/evp.h>
-#include <openssl/bio.h>
-#include <openssl/sha.h>
-#include <openssl/objects.h>
-#include <openssl/bn.h>
-#include <stdio.h>
-#include <errno.h>
-#include <string.h>
-
-#include "config.h"
-#include "rimage.h"
-#include "css.h"
-#include "manifest.h"
-
-#if OPENSSL_VERSION_NUMBER < 0x10100000L
-void RSA_get0_key(const RSA *r,
- const BIGNUM **n, const BIGNUM **e, const BIGNUM **d);
-
-void RSA_get0_key(const RSA *r,
- const BIGNUM **n, const BIGNUM **e, const BIGNUM **d)
-{
- if (n != NULL)
- *n = r->n;
- if (e != NULL)
- *e = r->e;
- if (d != NULL)
- *d = r->d;
-}
-#endif
-
-#define DEBUG_PKCS 0
-
-static void bytes_swap(uint8_t *ptr, uint32_t size)
-{
- uint8_t tmp;
- uint32_t index;
-
- for (index = 0; index < (size / 2); index++) {
- tmp = ptr[index];
- ptr[index] = ptr[size - 1 - index];
- ptr[size - 1 - index] = tmp;
- }
-}
-
-/*
- * RSA signature of manifest. The signature is an PKCS
- * #1-v1_5 of the entire manifest structure, including all
- * extensions, and excluding the last 3 fields of the
- * manifest header (Public Key, Exponent and Signature).
-*/
-
-int pkcs_sign(struct image *image, struct fw_image_manifest *man,
- void *ptr1, unsigned int size1, void *ptr2, unsigned int size2)
-{
- RSA *priv_rsa = NULL;
- EVP_PKEY *privkey;
- FILE *fp;
- const BIGNUM *n, *e, *d;
- unsigned char digest[SHA256_DIGEST_LENGTH], mod[MAN_RSA_KEY_MODULUS_LEN];
- unsigned int siglen = MAN_RSA_SIGNATURE_LEN;
- char path[256];
- int ret = -EINVAL, i;
-
-#if DEBUG_PKCS
- fprintf(stdout, "offsets 0x%lx size 0x%x offset 0x%lx size 0x%x\n",
- ptr1 - (void *)man, size1, ptr2 - (void *)man, size2);
-#endif
-
- /* create new key */
- privkey = EVP_PKEY_new();
- if (privkey == NULL)
- return -ENOMEM;
-
- /* load in RSA private key from PEM file */
- if (!image->key_name)
- sprintf(path, "%s/otc_private_key.pem", PEM_KEY_PREFIX);
- else
- strcpy(path, image->key_name);
-
- fprintf(stdout, " pkcs: signing with key %s\n", path);
- fp = fopen(path, "r");
- if (fp == NULL) {
- fprintf(stderr, "error: can't open file %s %d\n",
- path, -errno);
- return -errno;
- }
- PEM_read_PrivateKey(fp, &privkey, NULL, NULL);
- fclose(fp);
-
- /* validate RSA private key */
- priv_rsa = EVP_PKEY_get1_RSA(privkey);
- if (RSA_check_key(priv_rsa)) {
- fprintf(stdout, " pkcs: RSA private key is valid.\n");
- } else {
- fprintf(stderr, "error: validating RSA private key.\n");
- return -EINVAL;
- }
-
- /* calculate the digest */
- module_sha256_create(image);
- module_sha256_update(image, ptr1, size1);
- module_sha256_update(image, ptr2, size2);
- module_sha256_complete(image, digest);
-
- fprintf(stdout, " pkcs: digest for manifest is ");
- for (i = 0; i < SHA256_DIGEST_LENGTH; i++)
- fprintf(stdout, "%02x", digest[i]);
- fprintf(stdout, "\n");
-
- /* sign the manifest */
- ret = RSA_sign(NID_sha256, digest, SHA256_DIGEST_LENGTH,
- (unsigned char *)man->css.signature,
- &siglen, priv_rsa);
- if (ret < 0)
- fprintf(stderr, "error: failed to sign manifest\n");
-
- /* copy public key modulus and exponent to manifest */
- RSA_get0_key(priv_rsa, &n, &e, &d);
- BN_bn2bin(n, mod);
- BN_bn2bin(e, (unsigned char *)man->css.exponent);
-
- /* modulus is reveresd */
- for (i = 0; i < MAN_RSA_KEY_MODULUS_LEN; i++)
- man->css.modulus[i] = mod[MAN_RSA_KEY_MODULUS_LEN - (1 + i)];
-
- /* signature is reveresd, swap it */
- bytes_swap(man->css.signature, sizeof(man->css.signature));
-
- EVP_PKEY_free(privkey);
- return ret;
-}
-
-int ri_manifest_sign(struct image *image)
-{
- struct fw_image_manifest *man = image->fw_image;
-
- pkcs_sign(image, man, (void *)man + MAN_CSS_HDR_OFFSET,
- sizeof(struct css_header) -
- (MAN_RSA_KEY_MODULUS_LEN + MAN_RSA_KEY_EXPONENT_LEN +
- MAN_RSA_SIGNATURE_LEN),
- (void *)man + MAN_SIG_PKG_OFFSET,
- (man->css.size - man->css.header_len) * sizeof(uint32_t));
- return 0;
-}
diff --git a/rimage/plat_auth.c b/rimage/plat_auth.c
deleted file mode 100644
index 2fd62aa..0000000
--- a/rimage/plat_auth.c
+++ /dev/null
@@ -1,51 +0,0 @@
-/*
- * Copyright (c) 2017, Intel Corporation.
- *
- * This program is free software; you can redistribute it and/or modify it
- * under the terms and conditions of the GNU General Public License,
- * version 2, as published by the Free Software Foundation.
- *
- * This program is distributed in the hope it will be useful, but WITHOUT
- * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
- * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
- * more details.
- *
- * Author: Liam Girdwood <liam.r.girdwood@linux.intel.com>
- * Keyon Jie <yang.jie@linux.intel.com>
- */
-
-#include "rimage.h"
-#include "manifest.h"
-#include "plat_auth.h"
-
-void ri_adsp_meta_data_create(struct image *image, int meta_start_offset,
- int meta_end_offset)
-{
- struct sof_man_adsp_meta_file_ext *meta =
- image->fw_image + meta_start_offset;
-
- fprintf(stdout, " meta: completing ADSP manifest\n");
-
- meta->comp_desc[0].limit_offset = MAN_DESC_OFFSET + image->image_end
- - meta_end_offset;
-
- fprintf(stdout, " meta: limit is 0x%x\n",
- meta->comp_desc[0].limit_offset);
- /* now hash the AdspFwBinaryDesc -> EOF */
-}
-
-void ri_plat_ext_data_create(struct image *image)
-{
- struct partition_info_ext *part = image->fw_image + MAN_PART_INFO_OFFSET;
- struct sof_man_adsp_meta_file_ext *meta =
- image->fw_image + MAN_META_EXT_OFFSET;
- struct sof_man_fw_desc *desc = image->fw_image + MAN_DESC_OFFSET;
-
- fprintf(stdout, " auth: completing authentication manifest\n");
-
- part->length = meta->comp_desc[0].limit_offset - MAN_DESC_OFFSET;
- part->length += MAN_PAGE_SIZE - (part->length % MAN_PAGE_SIZE);
-
- /* do this here atm */
- desc->header.preload_page_count = part->length / MAN_PAGE_SIZE;
-}
diff --git a/rimage/plat_auth.h b/rimage/plat_auth.h
deleted file mode 100644
index 253a78b..0000000
--- a/rimage/plat_auth.h
+++ /dev/null
@@ -1,93 +0,0 @@
-/*
- * Copyright (c) 2017, Intel Corporation.
- *
- * This program is free software; you can redistribute it and/or modify it
- * under the terms and conditions of the GNU General Public License,
- * version 2, as published by the Free Software Foundation.
- *
- * This program is distributed in the hope it will be useful, but WITHOUT
- * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
- * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
- * more details.
- */
-
-#ifndef __PLAT_AUTH_H__
-#define __PLAT_AUTH_H__
-
-#include <stdint.h>
-
-struct image;
-
-#define PLAT_AUTH_SHA256_LEN 32
-#define PLAT_AUTH_NAME_LEN 12
-#define PLAT_AUTH_PADDING 48 /* pad at end of struct */
-
-#define SIGN_PKG_EXT_TYPE 15
-#define SIGN_PKG_NUM_MODULE 1
-
-struct signed_pkg_info_module {
- uint8_t name[PLAT_AUTH_NAME_LEN]; /* must be padded with 0 */
- uint8_t type;
- uint8_t hash_algo;
- uint16_t hash_size;
- uint32_t meta_size;
- uint8_t hash[PLAT_AUTH_SHA256_LEN];
-} __attribute__((packed));
-
-struct signed_pkg_info_ext {
- uint32_t ext_type;
- uint32_t ext_len;
-
- uint8_t name[4];
- uint32_t vcn;
- uint8_t bitmap[16];
- uint32_t svn;
- uint8_t fw_type;
- uint8_t fw_sub_type;
- uint8_t reserved[14]; /* must be 0 */
-
- /* variable length of modules */
- struct signed_pkg_info_module module[SIGN_PKG_NUM_MODULE];
-} __attribute__((packed));
-
-
-#define PART_INFO_EXT_TYPE 3
-#define PART_INFO_NUM_MODULE 1
-
-struct partition_info_module {
- uint8_t name[PLAT_AUTH_NAME_LEN]; /* must be padded with 0 */
- uint8_t type;
- uint8_t reserved[3];
- uint32_t meta_size;
- uint8_t hash[PLAT_AUTH_SHA256_LEN];
-} __attribute__((packed));
-
-struct partition_info_ext {
- uint32_t ext_type;
- uint32_t ext_len;
-
- uint8_t name[4]; /* "ADSP" */
- uint32_t length;
- uint8_t hash[PLAT_AUTH_SHA256_LEN];
-
- uint32_t vcn;
- uint32_t part_version;
- uint32_t fmt_version;
- uint32_t instance_id;
- uint32_t part_flags;
- uint8_t reserved[20]; /* must be 0 */
-
- /* variable length of modules */
- struct partition_info_module module[PART_INFO_NUM_MODULE];
-} __attribute__((packed));
-
-
-#define PLAT_AUTH_SIZE \
- (sizeof(struct partition_info_ext) + \
- sizeof(struct signed_pkg_info_ext))
-
-void ri_adsp_meta_data_create(struct image *image, int meta_start_offset,
- int meta_end_offset);
-void ri_plat_ext_data_create(struct image *image);
-
-#endif
diff --git a/rimage/rimage.c b/rimage/rimage.c
deleted file mode 100644
index e8b9dc8..0000000
--- a/rimage/rimage.c
+++ /dev/null
@@ -1,145 +0,0 @@
-/*
- * ELF to firmware image creator.
- *
- * Copyright (c) 2015, Intel Corporation.
- *
- * This program is free software; you can redistribute it and/or modify it
- * under the terms and conditions of the GNU General Public License,
- * version 2, as published by the Free Software Foundation.
- *
- * This program is distributed in the hope it will be useful, but WITHOUT
- * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
- * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
- * more details.
- */
-
-#include <stdlib.h>
-#include <stdio.h>
-#include <unistd.h>
-#include <errno.h>
-#include <string.h>
-
-#include "rimage.h"
-#include "file_format.h"
-#include "manifest.h"
-
-static const struct adsp *machine[] = {
- &machine_byt,
- &machine_cht,
- &machine_bsw,
- &machine_hsw,
- &machine_bdw,
- &machine_apl,
- &machine_cnl,
-};
-
-static void usage(char *name)
-{
- fprintf(stdout, "%s:\t -m machine -o outfile -k [key] ELF files\n",
- name);
- fprintf(stdout, "\t -v enable verbose output\n");
- fprintf(stdout, "\t -r enable relocatable ELF files\n");
- fprintf(stdout, "\t -s MEU signing offset\n");
- exit(0);
-}
-
-int main(int argc, char *argv[])
-{
- struct image image;
- const char *mach = NULL;
- int opt, ret, i, elf_argc = 0;
-
- memset(&image, 0, sizeof(image));
-
- while ((opt = getopt(argc, argv, "ho:m:vba:s:k:l:r")) != -1) {
- switch (opt) {
- case 'o':
- image.out_file = optarg;
- break;
- case 'm':
- mach = optarg;
- break;
- case 'v':
- image.verbose = 1;
- break;
- case 's':
- image.meu_offset = atoi(optarg);
- break;
- case 'a':
- image.abi = atoi(optarg);
- break;
- case 'k':
- image.key_name = optarg;
- break;
- case 'r':
- image.reloc = 1;
- break;
- case 'h':
- usage(argv[0]);
- break;
- default:
- break;
- }
- }
-
- elf_argc = optind;
-
- /* make sure we have an outfile and machine */
- if (image.out_file == NULL || mach == NULL)
- usage(argv[0]);
-
-
- /* find machine */
- for (i = 0; i < ARRAY_SIZE(machine); i++) {
- if (!strcmp(mach, machine[i]->name)) {
- image.adsp = machine[i];
- goto found;
- }
- }
- fprintf(stderr, "error: machine %s not found\n", mach);
- fprintf(stderr, "error: available machines ");
- for (i = 0; i < ARRAY_SIZE(machine); i++)
- fprintf(stderr, "%s, ", machine[i]->name);
- fprintf(stderr, "\n");
-
- return -EINVAL;
-
-found:
-
- /* parse input ELF files */
- image.num_modules = argc - elf_argc;
- for (i = elf_argc; i < argc; i++) {
- fprintf(stdout, "\nModule Reading %s\n", argv[i]);
- ret = elf_parse_module(&image, i - elf_argc, argv[i]);
- if (ret < 0)
- goto out;
- }
-
- /* validate all modules */
- ret = elf_validate_modules(&image);
- if (ret < 0)
- goto out;
-
- /* open outfile for writing */
- unlink(image.out_file);
- image.out_fd = fopen(image.out_file, "w");
- if (image.out_fd == NULL) {
- fprintf(stderr, "error: unable to open %s for writing %d\n",
- image.out_file, errno);
- ret = -EINVAL;
- goto out;
- }
-
- /* process and write output */
- if (image.meu_offset)
- ret = image.adsp->write_firmware_meu(&image);
- else
- ret = image.adsp->write_firmware(&image);
-out:
- /* close files */
- if (image.out_fd)
- fclose(image.out_fd);
-
-
- return ret;
-}
diff --git a/rimage/rimage.h b/rimage/rimage.h
deleted file mode 100644
index 3398ece..0000000
--- a/rimage/rimage.h
+++ /dev/null
@@ -1,174 +0,0 @@
-/*
- * ELF to firmware image creator.
- *
- * Copyright (c) 2015-2018 Intel Corporation.
- *
- * This program is free software; you can redistribute it and/or modify it
- * under the terms and conditions of the GNU General Public License,
- * version 2, as published by the Free Software Foundation.
- *
- * This program is distributed in the hope it will be useful, but WITHOUT
- * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
- * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
- * more details.
- */
-
-#ifndef __RIMAGE_H__
-#define __RIMAGE_H__
-
-#include <stdint.h>
-#include <elf.h>
-#include <stdio.h>
-
-#include <openssl/conf.h>
-#include <openssl/evp.h>
-#include <openssl/err.h>
-
-#define ARRAY_SIZE(x) (sizeof(x) / sizeof(x[0]))
-#define MAX_MODULES 32
-
-struct adsp;
-struct manifest;
-struct man_module;
-
-/* list of supported targets */
-enum machine_id {
- MACHINE_BAYTRAIL = 0,
- MACHINE_CHERRYTRAIL,
- MACHINE_BRASWELL,
- MACHINE_HASWELL,
- MACHINE_BROADWELL,
- MACHINE_APOLLOLAKE,
- MACHINE_CANNONLAKE,
- MACHINE_MAX
-};
-
-/*
- * ELF module data
- */
-struct module {
- const char *elf_file;
- FILE *fd;
-
- Elf32_Ehdr hdr;
- Elf32_Shdr *section;
- Elf32_Phdr *prg;
- char *strings;
-
- uint32_t text_start;
- uint32_t text_end;
- uint32_t data_start;
- uint32_t data_end;
- uint32_t bss_start;
- uint32_t bss_end;
- uint32_t foffset;
-
- int num_sections;
- int num_bss;
- int fw_size;
- int bss_index;
-
- /* sizes do not include any gaps */
- int bss_size;
- int text_size;
- int data_size;
-
- /* sizes do include gaps to nearest page */
- int bss_file_size;
- int text_file_size;
- int text_fixup_size;
- int data_file_size;
-
- /* total file size */
- int file_size;
-};
-
-/*
- * Firmware image context.
- */
-struct image {
-
- const char *out_file;
- FILE *out_fd;
- void *pos;
-
- const struct adsp *adsp;
- int abi;
- int verbose;
- int reloc; /* ELF data is relocatable */
- int num_modules;
- struct module module[MAX_MODULES];
- uint32_t image_end;/* module end, equal to output image size */
- int meu_offset;
-
- /* SHA 256 */
- const char *key_name;
- EVP_MD_CTX *mdctx;
- const EVP_MD *md;
-
- /* file IO */
- void *fw_image;
- void *rom_image;
- FILE *out_rom_fd;
- FILE *out_man_fd;
- FILE *out_unsigned_fd;
- char out_rom_file[256];
- char out_man_file[256];
- char out_unsigned_file[256];
-};
-
-/*
- * Audio DSP descriptor and operations.
- */
-struct adsp {
- const char *name;
- uint32_t iram_base;
- uint32_t iram_size;
- uint32_t dram_base;
- uint32_t dram_size;
- uint32_t sram_base;
- uint32_t sram_size;
- uint32_t host_iram_offset;
- uint32_t host_dram_offset;
- uint32_t rom_base;
- uint32_t rom_size;
- uint32_t imr_base;
- uint32_t imr_size;
-
- uint32_t image_size;
- uint32_t dram_offset;
-
- enum machine_id machine_id;
- int (*write_firmware)(struct image *image);
- int (*write_firmware_meu)(struct image *image);
- struct fw_image_manifest *man;
-};
-
-void module_sha256_create(struct image *image);
-void module_sha256_update(struct image *image, uint8_t *data, size_t bytes);
-void module_sha256_complete(struct image *image, uint8_t *hash);
-int ri_manifest_sign(struct image *image);
-void ri_hash(struct image *image, unsigned offset, unsigned size, uint8_t *hash);
-
-int pkcs_sign(struct image *image, struct fw_image_manifest *man,
- void *ptr1, unsigned size1, void *ptr2, unsigned size2);
-
-int elf_parse_module(struct image *image, int module_index, const char *name);
-void elf_free_module(struct image *image, int module_index);
-int elf_is_rom(struct image *image, Elf32_Shdr *section);
-int elf_validate_modules(struct image *image);
-int elf_find_section(struct image *image, struct module *module,
- const char *name);
-int elf_validate_section(struct image *image, struct module *module,
- Elf32_Shdr *section, int index);
-
-/* supported machines */
-extern const struct adsp machine_byt;
-extern const struct adsp machine_cht;
-extern const struct adsp machine_bsw;
-extern const struct adsp machine_hsw;
-extern const struct adsp machine_bdw;
-extern const struct adsp machine_apl;
-extern const struct adsp machine_cnl;
-
-#endif
diff --git a/scripts/README.docker b/scripts/README.docker
deleted file mode 100644
index 468ae25..0000000
--- a/scripts/README.docker
+++ /dev/null
@@ -1,36 +0,0 @@
-The docker container provided in docker_build sets up a build environment for
-building Sound Open Firmware. A working docker installation is needed to run
-the docker build container.
-
-Note: This script assumes the sof.git/ and soft.git/ directories are siblings.
-
-Note2: In order to run docker as non sudo/root user please run.
-
-sudo usermod -aG docker your-user-name
-
-Then logout and login again.
-
-Quick Start:
-
-First, build the docker container. This step needs to be done initially and
-when the toolchain or alsa dependencies are updated.
-
-cd scripts/docker_build
-
-./docker-build.sh
-
-After the container is built, it can be used to run the scripts.
-
-To build for baytrail:
-./scripts/docker-run.sh ./scripts/xtensa-build-all.sh -l byt
-or (may need password test0000 for rimage install)
-./scripts/docker-run.sh ./scripts/xtensa-build-all.sh byt
-
-To rebuild the topology in soft.git:
-./scripts/docker-run.sh ./scripts/build-soft.sh
-
-An incremental sof.git build:
-./scripts/docker-run.sh make
-
-Or enter a shell:
-./scripts/docker-run.sh bash
diff --git a/scripts/build-soft.sh b/scripts/build-soft.sh
deleted file mode 100755
index 0756cc5..0000000
--- a/scripts/build-soft.sh
+++ /dev/null
@@ -1,6 +0,0 @@
-#!/bin/sh
-cd ../soft.git
-./autogen.sh
-./configure
-make -j$(nproc)
-cd ../sof.git
diff --git a/scripts/checkpatch.pl b/scripts/checkpatch.pl
deleted file mode 100755
index 16d035e..0000000
--- a/scripts/checkpatch.pl
+++ /dev/null
@@ -1,6417 +0,0 @@
-#!/usr/bin/env perl
-# (c) 2001, Dave Jones. (the file handling bit)
-# (c) 2005, Joel Schopp <jschopp@austin.ibm.com> (the ugly bit)
-# (c) 2007,2008, Andy Whitcroft <apw@uk.ibm.com> (new conditions, test suite)
-# (c) 2008-2010 Andy Whitcroft <apw@canonical.com>
-# Licensed under the terms of the GNU GPL License version 2
-
-use strict;
-use warnings;
-use POSIX;
-use File::Basename;
-use Cwd 'abs_path';
-use Term::ANSIColor qw(:constants);
-
-my $P = $0;
-my $D = dirname(abs_path($P));
-
-my $V = '0.32';
-
-use Getopt::Long qw(:config no_auto_abbrev);
-
-my $quiet = 0;
-my $tree = 1;
-my $chk_signoff = 1;
-my $chk_patch = 1;
-my $tst_only;
-my $emacs = 0;
-my $terse = 0;
-my $showfile = 0;
-my $file = 0;
-my $git = 0;
-my %git_commits = ();
-my $check = 0;
-my $check_orig = 0;
-my $summary = 1;
-my $mailback = 0;
-my $summary_file = 0;
-my $show_types = 0;
-my $list_types = 0;
-my $fix = 0;
-my $fix_inplace = 0;
-my $root;
-my %debug;
-my %camelcase = ();
-my %use_type = ();
-my @use = ();
-my %ignore_type = ();
-my @ignore = ();
-my $help = 0;
-my $configuration_file = ".checkpatch.conf";
-my $max_line_length = 80;
-my $ignore_perl_version = 0;
-my $minimum_perl_version = 5.10.0;
-my $min_conf_desc_length = 4;
-my $spelling_file = "$D/spelling.txt";
-my $codespell = 0;
-my $codespellfile = "/usr/share/codespell/dictionary.txt";
-my $conststructsfile = "$D/const_structs.checkpatch";
-my $typedefsfile = "";
-my $color = "auto";
-my $allow_c99_comments = 1;
-
-sub help {
- my ($exitcode) = @_;
-
- print << "EOM";
-Usage: $P [OPTION]... [FILE]...
-Version: $V
-
-Options:
- -q, --quiet quiet
- --no-tree run without a kernel tree
- --no-signoff do not check for 'Signed-off-by' line
- --patch treat FILE as patchfile (default)
- --emacs emacs compile window format
- --terse one line per report
- --showfile emit diffed file position, not input file position
- -g, --git treat FILE as a single commit or git revision range
- single git commit with:
- <rev>
- <rev>^
- <rev>~n
- multiple git commits with:
- <rev1>..<rev2>
- <rev1>...<rev2>
- <rev>-<count>
- git merges are ignored
- -f, --file treat FILE as regular source file
- --subjective, --strict enable more subjective tests
- --list-types list the possible message types
- --types TYPE(,TYPE2...) show only these comma separated message types
- --ignore TYPE(,TYPE2...) ignore various comma separated message types
- --show-types show the specific message type in the output
- --max-line-length=n set the maximum line length, if exceeded, warn
- --min-conf-desc-length=n set the min description length, if shorter, warn
- --root=PATH PATH to the kernel tree root
- --no-summary suppress the per-file summary
- --mailback only produce a report in case of warnings/errors
- --summary-file include the filename in summary
- --debug KEY=[0|1] turn on/off debugging of KEY, where KEY is one of
- 'values', 'possible', 'type', and 'attr' (default
- is all off)
- --test-only=WORD report only warnings/errors containing WORD
- literally
- --fix EXPERIMENTAL - may create horrible results
- If correctable single-line errors exist, create
- "<inputfile>.EXPERIMENTAL-checkpatch-fixes"
- with potential errors corrected to the preferred
- checkpatch style
- --fix-inplace EXPERIMENTAL - may create horrible results
- Is the same as --fix, but overwrites the input
- file. It's your fault if there's no backup or git
- --ignore-perl-version override checking of perl version. expect
- runtime errors.
- --codespell Use the codespell dictionary for spelling/typos
- (default:/usr/share/codespell/dictionary.txt)
- --codespellfile Use this codespell dictionary
- --typedefsfile Read additional types from this file
- --color[=WHEN] Use colors 'always', 'never', or only when output
- is a terminal ('auto'). Default is 'auto'.
- -h, --help, --version display this help and exit
-
-When FILE is - read standard input.
-EOM
-
- exit($exitcode);
-}
-
-sub uniq {
- my %seen;
- return grep { !$seen{$_}++ } @_;
-}
-
-sub list_types {
- my ($exitcode) = @_;
-
- my $count = 0;
-
- local $/ = undef;
-
- open(my $script, '<', abs_path($P)) or
- die "$P: Can't read '$P' $!\n";
-
- my $text = <$script>;
- close($script);
-
- my @types = ();
- # Also catch when type or level is passed through a variable
- for ($text =~ /(?:(?:\bCHK|\bWARN|\bERROR|&\{\$msg_level})\s*\(|\$msg_type\s*=)\s*"([^"]+)"/g) {
- push (@types, $_);
- }
- @types = sort(uniq(@types));
- print("#\tMessage type\n\n");
- foreach my $type (@types) {
- print(++$count . "\t" . $type . "\n");
- }
-
- exit($exitcode);
-}
-
-my $conf = which_conf($configuration_file);
-if (-f $conf) {
- my @conf_args;
- open(my $conffile, '<', "$conf")
- or warn "$P: Can't find a readable $configuration_file file $!\n";
-
- while (<$conffile>) {
- my $line = $_;
-
- $line =~ s/\s*\n?$//g;
- $line =~ s/^\s*//g;
- $line =~ s/\s+/ /g;
-
- next if ($line =~ m/^\s*#/);
- next if ($line =~ m/^\s*$/);
-
- my @words = split(" ", $line);
- foreach my $word (@words) {
- last if ($word =~ m/^#/);
- push (@conf_args, $word);
- }
- }
- close($conffile);
- unshift(@ARGV, @conf_args) if @conf_args;
-}
-
-# Perl's Getopt::Long allows options to take optional arguments after a space.
-# Prevent --color by itself from consuming other arguments
-foreach (@ARGV) {
- if ($_ eq "--color" || $_ eq "-color") {
- $_ = "--color=$color";
- }
-}
-
-GetOptions(
- 'q|quiet+' => \$quiet,
- 'tree!' => \$tree,
- 'signoff!' => \$chk_signoff,
- 'patch!' => \$chk_patch,
- 'emacs!' => \$emacs,
- 'terse!' => \$terse,
- 'showfile!' => \$showfile,
- 'f|file!' => \$file,
- 'g|git!' => \$git,
- 'subjective!' => \$check,
- 'strict!' => \$check,
- 'ignore=s' => \@ignore,
- 'types=s' => \@use,
- 'show-types!' => \$show_types,
- 'list-types!' => \$list_types,
- 'max-line-length=i' => \$max_line_length,
- 'min-conf-desc-length=i' => \$min_conf_desc_length,
- 'root=s' => \$root,
- 'summary!' => \$summary,
- 'mailback!' => \$mailback,
- 'summary-file!' => \$summary_file,
- 'fix!' => \$fix,
- 'fix-inplace!' => \$fix_inplace,
- 'ignore-perl-version!' => \$ignore_perl_version,
- 'debug=s' => \%debug,
- 'test-only=s' => \$tst_only,
- 'codespell!' => \$codespell,
- 'codespellfile=s' => \$codespellfile,
- 'typedefsfile=s' => \$typedefsfile,
- 'color=s' => \$color,
- 'no-color' => \$color, #keep old behaviors of -nocolor
- 'nocolor' => \$color, #keep old behaviors of -nocolor
- 'h|help' => \$help,
- 'version' => \$help
-) or help(1);
-
-help(0) if ($help);
-
-list_types(0) if ($list_types);
-
-$fix = 1 if ($fix_inplace);
-$check_orig = $check;
-
-my $exit = 0;
-
-if ($^V && $^V lt $minimum_perl_version) {
- printf "$P: requires at least perl version %vd\n", $minimum_perl_version;
- if (!$ignore_perl_version) {
- exit(1);
- }
-}
-
-#if no filenames are given, push '-' to read patch from stdin
-if ($#ARGV < 0) {
- push(@ARGV, '-');
-}
-
-if ($color =~ /^[01]$/) {
- $color = !$color;
-} elsif ($color =~ /^always$/i) {
- $color = 1;
-} elsif ($color =~ /^never$/i) {
- $color = 0;
-} elsif ($color =~ /^auto$/i) {
- $color = (-t STDOUT);
-} else {
- die "Invalid color mode: $color\n";
-}
-
-sub hash_save_array_words {
- my ($hashRef, $arrayRef) = @_;
-
- my @array = split(/,/, join(',', @$arrayRef));
- foreach my $word (@array) {
- $word =~ s/\s*\n?$//g;
- $word =~ s/^\s*//g;
- $word =~ s/\s+/ /g;
- $word =~ tr/[a-z]/[A-Z]/;
-
- next if ($word =~ m/^\s*#/);
- next if ($word =~ m/^\s*$/);
-
- $hashRef->{$word}++;
- }
-}
-
-sub hash_show_words {
- my ($hashRef, $prefix) = @_;
-
- if (keys %$hashRef) {
- print "\nNOTE: $prefix message types:";
- foreach my $word (sort keys %$hashRef) {
- print " $word";
- }
- print "\n";
- }
-}
-
-hash_save_array_words(\%ignore_type, \@ignore);
-hash_save_array_words(\%use_type, \@use);
-
-my $dbg_values = 0;
-my $dbg_possible = 0;
-my $dbg_type = 0;
-my $dbg_attr = 0;
-for my $key (keys %debug) {
- ## no critic
- eval "\${dbg_$key} = '$debug{$key}';";
- die "$@" if ($@);
-}
-
-my $rpt_cleaners = 0;
-
-if ($terse) {
- $emacs = 1;
- $quiet++;
-}
-
-if ($tree) {
- if (defined $root) {
- if (!top_of_kernel_tree($root)) {
- die "$P: $root: --root does not point at a valid tree\n";
- }
- } else {
- if (top_of_kernel_tree('.')) {
- $root = '.';
- } elsif ($0 =~ m@(.*)/scripts/[^/]*$@ &&
- top_of_kernel_tree($1)) {
- $root = $1;
- }
- }
-
- if (!defined $root) {
- print "Must be run from the top-level dir. of a kernel tree\n";
- exit(2);
- }
-}
-
-my $emitted_corrupt = 0;
-
-our $Ident = qr{
- [A-Za-z_][A-Za-z\d_]*
- (?:\s*\#\#\s*[A-Za-z_][A-Za-z\d_]*)*
- }x;
-our $Storage = qr{extern|static|asmlinkage};
-our $Sparse = qr{
- __user|
- __kernel|
- __force|
- __iomem|
- __must_check|
- __init_refok|
- __kprobes|
- __ref|
- __rcu|
- __private
- }x;
-our $InitAttributePrefix = qr{__(?:mem|cpu|dev|net_|)};
-our $InitAttributeData = qr{$InitAttributePrefix(?:initdata\b)};
-our $InitAttributeConst = qr{$InitAttributePrefix(?:initconst\b)};
-our $InitAttributeInit = qr{$InitAttributePrefix(?:init\b)};
-our $InitAttribute = qr{$InitAttributeData|$InitAttributeConst|$InitAttributeInit};
-
-# Notes to $Attribute:
-# We need \b after 'init' otherwise 'initconst' will cause a false positive in a check
-our $Attribute = qr{
- const|
- __percpu|
- __nocast|
- __safe|
- __bitwise|
- __packed__|
- __packed2__|
- __naked|
- __maybe_unused|
- __always_unused|
- __noreturn|
- __used|
- __cold|
- __pure|
- __noclone|
- __deprecated|
- __read_mostly|
- __kprobes|
- $InitAttribute|
- ____cacheline_aligned|
- ____cacheline_aligned_in_smp|
- ____cacheline_internodealigned_in_smp|
- __weak
- }x;
-our $Modifier;
-our $Inline = qr{inline|__always_inline|noinline|__inline|__inline__};
-our $Member = qr{->$Ident|\.$Ident|\[[^]]*\]};
-our $Lval = qr{$Ident(?:$Member)*};
-
-our $Int_type = qr{(?i)llu|ull|ll|lu|ul|l|u};
-our $Binary = qr{(?i)0b[01]+$Int_type?};
-our $Hex = qr{(?i)0x[0-9a-f]+$Int_type?};
-our $Int = qr{[0-9]+$Int_type?};
-our $Octal = qr{0[0-7]+$Int_type?};
-our $String = qr{"[X\t]*"};
-our $Float_hex = qr{(?i)0x[0-9a-f]+p-?[0-9]+[fl]?};
-our $Float_dec = qr{(?i)(?:[0-9]+\.[0-9]*|[0-9]*\.[0-9]+)(?:e-?[0-9]+)?[fl]?};
-our $Float_int = qr{(?i)[0-9]+e-?[0-9]+[fl]?};
-our $Float = qr{$Float_hex|$Float_dec|$Float_int};
-our $Constant = qr{$Float|$Binary|$Octal|$Hex|$Int};
-our $Assignment = qr{\*\=|/=|%=|\+=|-=|<<=|>>=|&=|\^=|\|=|=};
-our $Compare = qr{<=|>=|==|!=|<|(?<!-)>};
-our $Arithmetic = qr{\+|-|\*|\/|%};
-our $Operators = qr{
- <=|>=|==|!=|
- =>|->|<<|>>|<|>|!|~|
- &&|\|\||,|\^|\+\+|--|&|\||$Arithmetic
- }x;
-
-our $c90_Keywords = qr{do|for|while|if|else|return|goto|continue|switch|default|case|break}x;
-
-our $BasicType;
-our $NonptrType;
-our $NonptrTypeMisordered;
-our $NonptrTypeWithAttr;
-our $Type;
-our $TypeMisordered;
-our $Declare;
-our $DeclareMisordered;
-
-our $NON_ASCII_UTF8 = qr{
- [\xC2-\xDF][\x80-\xBF] # non-overlong 2-byte
- | \xE0[\xA0-\xBF][\x80-\xBF] # excluding overlongs
- | [\xE1-\xEC\xEE\xEF][\x80-\xBF]{2} # straight 3-byte
- | \xED[\x80-\x9F][\x80-\xBF] # excluding surrogates
- | \xF0[\x90-\xBF][\x80-\xBF]{2} # planes 1-3
- | [\xF1-\xF3][\x80-\xBF]{3} # planes 4-15
- | \xF4[\x80-\x8F][\x80-\xBF]{2} # plane 16
-}x;
-
-our $UTF8 = qr{
- [\x09\x0A\x0D\x20-\x7E] # ASCII
- | $NON_ASCII_UTF8
-}x;
-
-our $typeC99Typedefs = qr{(?:__)?(?:[us]_?)?int_?(?:8|16|32|64)_t};
-our $typeOtherOSTypedefs = qr{(?x:
- u_(?:char|short|int|long) | # bsd
- u(?:nchar|short|int|long) # sysv
-)};
-our $typeKernelTypedefs = qr{(?x:
- (?:__)?(?:u|s|be|le)(?:8|16|32|64)|
- atomic_t
-)};
-our $typeTypedefs = qr{(?x:
- $typeC99Typedefs\b|
- $typeOtherOSTypedefs\b|
- $typeKernelTypedefs\b
-)};
-
-our $zero_initializer = qr{(?:(?:0[xX])?0+$Int_type?|NULL|false)\b};
-
-our $logFunctions = qr{(?x:
- printk(?:_ratelimited|_once|_deferred_once|_deferred|)|
- (?:[a-z0-9]+_){1,2}(?:printk|emerg|alert|crit|err|warning|warn|notice|info|debug|dbg|vdbg|devel|cont|WARN)(?:_ratelimited|_once|)|
- TP_printk|
- WARN(?:_RATELIMIT|_ONCE|)|
- panic|
- MODULE_[A-Z_]+|
- seq_vprintf|seq_printf|seq_puts
-)};
-
-our $signature_tags = qr{(?xi:
- Signed-off-by:|
- Acked-by:|
- Tested-by:|
- Reviewed-by:|
- Reported-by:|
- Suggested-by:|
- To:|
- Cc:
-)};
-
-our @typeListMisordered = (
- qr{char\s+(?:un)?signed},
- qr{int\s+(?:(?:un)?signed\s+)?short\s},
- qr{int\s+short(?:\s+(?:un)?signed)},
- qr{short\s+int(?:\s+(?:un)?signed)},
- qr{(?:un)?signed\s+int\s+short},
- qr{short\s+(?:un)?signed},
- qr{long\s+int\s+(?:un)?signed},
- qr{int\s+long\s+(?:un)?signed},
- qr{long\s+(?:un)?signed\s+int},
- qr{int\s+(?:un)?signed\s+long},
- qr{int\s+(?:un)?signed},
- qr{int\s+long\s+long\s+(?:un)?signed},
- qr{long\s+long\s+int\s+(?:un)?signed},
- qr{long\s+long\s+(?:un)?signed\s+int},
- qr{long\s+long\s+(?:un)?signed},
- qr{long\s+(?:un)?signed},
-);
-
-our @typeList = (
- qr{void},
- qr{(?:(?:un)?signed\s+)?char},
- qr{(?:(?:un)?signed\s+)?short\s+int},
- qr{(?:(?:un)?signed\s+)?short},
- qr{(?:(?:un)?signed\s+)?int},
- qr{(?:(?:un)?signed\s+)?long\s+int},
- qr{(?:(?:un)?signed\s+)?long\s+long\s+int},
- qr{(?:(?:un)?signed\s+)?long\s+long},
- qr{(?:(?:un)?signed\s+)?long},
- qr{(?:un)?signed},
- qr{float},
- qr{double},
- qr{bool},
- qr{struct\s+$Ident},
- qr{union\s+$Ident},
- qr{enum\s+$Ident},
- qr{${Ident}_t},
- qr{${Ident}_handler},
- qr{${Ident}_handler_fn},
- @typeListMisordered,
-);
-
-our $C90_int_types = qr{(?x:
- long\s+long\s+int\s+(?:un)?signed|
- long\s+long\s+(?:un)?signed\s+int|
- long\s+long\s+(?:un)?signed|
- (?:(?:un)?signed\s+)?long\s+long\s+int|
- (?:(?:un)?signed\s+)?long\s+long|
- int\s+long\s+long\s+(?:un)?signed|
- int\s+(?:(?:un)?signed\s+)?long\s+long|
-
- long\s+int\s+(?:un)?signed|
- long\s+(?:un)?signed\s+int|
- long\s+(?:un)?signed|
- (?:(?:un)?signed\s+)?long\s+int|
- (?:(?:un)?signed\s+)?long|
- int\s+long\s+(?:un)?signed|
- int\s+(?:(?:un)?signed\s+)?long|
-
- int\s+(?:un)?signed|
- (?:(?:un)?signed\s+)?int
-)};
-
-our @typeListFile = ();
-our @typeListWithAttr = (
- @typeList,
- qr{struct\s+$InitAttribute\s+$Ident},
- qr{union\s+$InitAttribute\s+$Ident},
-);
-
-our @modifierList = (
- qr{fastcall},
-);
-our @modifierListFile = ();
-
-our @mode_permission_funcs = (
- ["module_param", 3],
- ["module_param_(?:array|named|string)", 4],
- ["module_param_array_named", 5],
- ["debugfs_create_(?:file|u8|u16|u32|u64|x8|x16|x32|x64|size_t|atomic_t|bool|blob|regset32|u32_array)", 2],
- ["proc_create(?:_data|)", 2],
- ["(?:CLASS|DEVICE|SENSOR|SENSOR_DEVICE|IIO_DEVICE)_ATTR", 2],
- ["IIO_DEV_ATTR_[A-Z_]+", 1],
- ["SENSOR_(?:DEVICE_|)ATTR_2", 2],
- ["SENSOR_TEMPLATE(?:_2|)", 3],
- ["__ATTR", 2],
-);
-
-#Create a search pattern for all these functions to speed up a loop below
-our $mode_perms_search = "";
-foreach my $entry (@mode_permission_funcs) {
- $mode_perms_search .= '|' if ($mode_perms_search ne "");
- $mode_perms_search .= $entry->[0];
-}
-
-our $mode_perms_world_writable = qr{
- S_IWUGO |
- S_IWOTH |
- S_IRWXUGO |
- S_IALLUGO |
- 0[0-7][0-7][2367]
-}x;
-
-our %mode_permission_string_types = (
- "S_IRWXU" => 0700,
- "S_IRUSR" => 0400,
- "S_IWUSR" => 0200,
- "S_IXUSR" => 0100,
- "S_IRWXG" => 0070,
- "S_IRGRP" => 0040,
- "S_IWGRP" => 0020,
- "S_IXGRP" => 0010,
- "S_IRWXO" => 0007,
- "S_IROTH" => 0004,
- "S_IWOTH" => 0002,
- "S_IXOTH" => 0001,
- "S_IRWXUGO" => 0777,
- "S_IRUGO" => 0444,
- "S_IWUGO" => 0222,
- "S_IXUGO" => 0111,
-);
-
-#Create a search pattern for all these strings to speed up a loop below
-our $mode_perms_string_search = "";
-foreach my $entry (keys %mode_permission_string_types) {
- $mode_perms_string_search .= '|' if ($mode_perms_string_search ne "");
- $mode_perms_string_search .= $entry;
-}
-
-our $allowed_asm_includes = qr{(?x:
- irq|
- memory|
- time|
- reboot
-)};
-# memory.h: ARM has a custom one
-
-# Load common spelling mistakes and build regular expression list.
-my $misspellings;
-my %spelling_fix;
-
-if (open(my $spelling, '<', $spelling_file)) {
- while (<$spelling>) {
- my $line = $_;
-
- $line =~ s/\s*\n?$//g;
- $line =~ s/^\s*//g;
-
- next if ($line =~ m/^\s*#/);
- next if ($line =~ m/^\s*$/);
-
- my ($suspect, $fix) = split(/\|\|/, $line);
-
- $spelling_fix{$suspect} = $fix;
- }
- close($spelling);
-} else {
- warn "No typos will be found - file '$spelling_file': $!\n";
-}
-
-if ($codespell) {
- if (open(my $spelling, '<', $codespellfile)) {
- while (<$spelling>) {
- my $line = $_;
-
- $line =~ s/\s*\n?$//g;
- $line =~ s/^\s*//g;
-
- next if ($line =~ m/^\s*#/);
- next if ($line =~ m/^\s*$/);
- next if ($line =~ m/, disabled/i);
-
- $line =~ s/,.*$//;
-
- my ($suspect, $fix) = split(/->/, $line);
-
- $spelling_fix{$suspect} = $fix;
- }
- close($spelling);
- } else {
- warn "No codespell typos will be found - file '$codespellfile': $!\n";
- }
-}
-
-$misspellings = join("|", sort keys %spelling_fix) if keys %spelling_fix;
-
-sub read_words {
- my ($wordsRef, $file) = @_;
-
- if (open(my $words, '<', $file)) {
- while (<$words>) {
- my $line = $_;
-
- $line =~ s/\s*\n?$//g;
- $line =~ s/^\s*//g;
-
- next if ($line =~ m/^\s*#/);
- next if ($line =~ m/^\s*$/);
- if ($line =~ /\s/) {
- print("$file: '$line' invalid - ignored\n");
- next;
- }
-
- $$wordsRef .= '|' if ($$wordsRef ne "");
- $$wordsRef .= $line;
- }
- close($file);
- return 1;
- }
-
- return 0;
-}
-
-my $const_structs = "";
-read_words(\$const_structs, $conststructsfile)
- or warn "No structs that should be const will be found - file '$conststructsfile': $!\n";
-
-my $typeOtherTypedefs = "";
-if (length($typedefsfile)) {
- read_words(\$typeOtherTypedefs, $typedefsfile)
- or warn "No additional types will be considered - file '$typedefsfile': $!\n";
-}
-$typeTypedefs .= '|' . $typeOtherTypedefs if ($typeOtherTypedefs ne "");
-
-sub build_types {
- my $mods = "(?x: \n" . join("|\n ", (@modifierList, @modifierListFile)) . "\n)";
- my $all = "(?x: \n" . join("|\n ", (@typeList, @typeListFile)) . "\n)";
- my $Misordered = "(?x: \n" . join("|\n ", @typeListMisordered) . "\n)";
- my $allWithAttr = "(?x: \n" . join("|\n ", @typeListWithAttr) . "\n)";
- $Modifier = qr{(?:$Attribute|$Sparse|$mods)};
- $BasicType = qr{
- (?:$typeTypedefs\b)|
- (?:${all}\b)
- }x;
- $NonptrType = qr{
- (?:$Modifier\s+|const\s+)*
- (?:
- (?:typeof|__typeof__)\s*\([^\)]*\)|
- (?:$typeTypedefs\b)|
- (?:${all}\b)
- )
- (?:\s+$Modifier|\s+const)*
- }x;
- $NonptrTypeMisordered = qr{
- (?:$Modifier\s+|const\s+)*
- (?:
- (?:${Misordered}\b)
- )
- (?:\s+$Modifier|\s+const)*
- }x;
- $NonptrTypeWithAttr = qr{
- (?:$Modifier\s+|const\s+)*
- (?:
- (?:typeof|__typeof__)\s*\([^\)]*\)|
- (?:$typeTypedefs\b)|
- (?:${allWithAttr}\b)
- )
- (?:\s+$Modifier|\s+const)*
- }x;
- $Type = qr{
- $NonptrType
- (?:(?:\s|\*|\[\])+\s*const|(?:\s|\*\s*(?:const\s*)?|\[\])+|(?:\s*\[\s*\])+)?
- (?:\s+$Inline|\s+$Modifier)*
- }x;
- $TypeMisordered = qr{
- $NonptrTypeMisordered
- (?:(?:\s|\*|\[\])+\s*const|(?:\s|\*\s*(?:const\s*)?|\[\])+|(?:\s*\[\s*\])+)?
- (?:\s+$Inline|\s+$Modifier)*
- }x;
- $Declare = qr{(?:$Storage\s+(?:$Inline\s+)?)?$Type};
- $DeclareMisordered = qr{(?:$Storage\s+(?:$Inline\s+)?)?$TypeMisordered};
-}
-build_types();
-
-our $Typecast = qr{\s*(\(\s*$NonptrType\s*\)){0,1}\s*};
-
-# Using $balanced_parens, $LvalOrFunc, or $FuncArg
-# requires at least perl version v5.10.0
-# Any use must be runtime checked with $^V
-
-our $balanced_parens = qr/(\((?:[^\(\)]++|(?-1))*\))/;
-our $LvalOrFunc = qr{((?:[\&\*]\s*)?$Lval)\s*($balanced_parens{0,1})\s*};
-our $FuncArg = qr{$Typecast{0,1}($LvalOrFunc|$Constant|$String)};
-
-our $declaration_macros = qr{(?x:
- (?:$Storage\s+)?(?:[A-Z_][A-Z0-9]*_){0,2}(?:DEFINE|DECLARE)(?:_[A-Z0-9]+){1,6}\s*\(|
- (?:$Storage\s+)?[HLP]?LIST_HEAD\s*\(|
- (?:$Storage\s+)?${Type}\s+uninitialized_var\s*\(
-)};
-
-sub deparenthesize {
- my ($string) = @_;
- return "" if (!defined($string));
-
- while ($string =~ /^\s*\(.*\)\s*$/) {
- $string =~ s@^\s*\(\s*@@;
- $string =~ s@\s*\)\s*$@@;
- }
-
- $string =~ s@\s+@ @g;
-
- return $string;
-}
-
-sub seed_camelcase_file {
- my ($file) = @_;
-
- return if (!(-f $file));
-
- local $/;
-
- open(my $include_file, '<', "$file")
- or warn "$P: Can't read '$file' $!\n";
- my $text = <$include_file>;
- close($include_file);
-
- my @lines = split('\n', $text);
-
- foreach my $line (@lines) {
- next if ($line !~ /(?:[A-Z][a-z]|[a-z][A-Z])/);
- if ($line =~ /^[ \t]*(?:#[ \t]*define|typedef\s+$Type)\s+(\w*(?:[A-Z][a-z]|[a-z][A-Z])\w*)/) {
- $camelcase{$1} = 1;
- } elsif ($line =~ /^\s*$Declare\s+(\w*(?:[A-Z][a-z]|[a-z][A-Z])\w*)\s*[\(\[,;]/) {
- $camelcase{$1} = 1;
- } elsif ($line =~ /^\s*(?:union|struct|enum)\s+(\w*(?:[A-Z][a-z]|[a-z][A-Z])\w*)\s*[;\{]/) {
- $camelcase{$1} = 1;
- }
- }
-}
-
-sub is_maintained_obsolete {
- my ($filename) = @_;
-
- return 0 if (!$tree || !(-e "$root/scripts/get_maintainer.pl"));
-
- my $status = `perl $root/scripts/get_maintainer.pl --status --nom --nol --nogit --nogit-fallback -f $filename 2>&1`;
-
- return $status =~ /obsolete/i;
-}
-
-my $camelcase_seeded = 0;
-sub seed_camelcase_includes {
- return if ($camelcase_seeded);
-
- my $files;
- my $camelcase_cache = "";
- my @include_files = ();
-
- $camelcase_seeded = 1;
-
- if (-e ".git") {
- my $git_last_include_commit = `git log --no-merges --pretty=format:"%h%n" -1 -- include`;
- chomp $git_last_include_commit;
- $camelcase_cache = ".checkpatch-camelcase.git.$git_last_include_commit";
- } else {
- my $last_mod_date = 0;
- $files = `find $root/include -name "*.h"`;
- @include_files = split('\n', $files);
- foreach my $file (@include_files) {
- my $date = POSIX::strftime("%Y%m%d%H%M",
- localtime((stat $file)[9]));
- $last_mod_date = $date if ($last_mod_date < $date);
- }
- $camelcase_cache = ".checkpatch-camelcase.date.$last_mod_date";
- }
-
- if ($camelcase_cache ne "" && -f $camelcase_cache) {
- open(my $camelcase_file, '<', "$camelcase_cache")
- or warn "$P: Can't read '$camelcase_cache' $!\n";
- while (<$camelcase_file>) {
- chomp;
- $camelcase{$_} = 1;
- }
- close($camelcase_file);
-
- return;
- }
-
- if (-e ".git") {
- $files = `git ls-files "include/*.h"`;
- @include_files = split('\n', $files);
- }
-
- foreach my $file (@include_files) {
- seed_camelcase_file($file);
- }
-
- if ($camelcase_cache ne "") {
- unlink glob ".checkpatch-camelcase.*";
- open(my $camelcase_file, '>', "$camelcase_cache")
- or warn "$P: Can't write '$camelcase_cache' $!\n";
- foreach (sort { lc($a) cmp lc($b) } keys(%camelcase)) {
- print $camelcase_file ("$_\n");
- }
- close($camelcase_file);
- }
-}
-
-sub git_commit_info {
- my ($commit, $id, $desc) = @_;
-
- return ($id, $desc) if ((which("git") eq "") || !(-e ".git"));
-
- my $output = `git log --no-color --format='%H %s' -1 $commit 2>&1`;
- $output =~ s/^\s*//gm;
- my @lines = split("\n", $output);
-
- return ($id, $desc) if ($#lines < 0);
-
- if ($lines[0] =~ /^error: short SHA1 $commit is ambiguous\./) {
-# Maybe one day convert this block of bash into something that returns
-# all matching commit ids, but it's very slow...
-#
-# echo "checking commits $1..."
-# git rev-list --remotes | grep -i "^$1" |
-# while read line ; do
-# git log --format='%H %s' -1 $line |
-# echo "commit $(cut -c 1-12,41-)"
-# done
- } elsif ($lines[0] =~ /^fatal: ambiguous argument '$commit': unknown revision or path not in the working tree\./) {
- $id = undef;
- } else {
- $id = substr($lines[0], 0, 12);
- $desc = substr($lines[0], 41);
- }
-
- return ($id, $desc);
-}
-
-$chk_signoff = 0 if ($file);
-
-my @rawlines = ();
-my @lines = ();
-my @fixed = ();
-my @fixed_inserted = ();
-my @fixed_deleted = ();
-my $fixlinenr = -1;
-
-# If input is git commits, extract all commits from the commit expressions.
-# For example, HEAD-3 means we need check 'HEAD, HEAD~1, HEAD~2'.
-die "$P: No git repository found\n" if ($git && !-e ".git");
-
-if ($git) {
- my @commits = ();
- foreach my $commit_expr (@ARGV) {
- my $git_range;
- if ($commit_expr =~ m/^(.*)-(\d+)$/) {
- $git_range = "-$2 $1";
- } elsif ($commit_expr =~ m/\.\./) {
- $git_range = "$commit_expr";
- } else {
- $git_range = "-1 $commit_expr";
- }
- my $lines = `git log --no-color --no-merges --pretty=format:'%H %s' $git_range`;
- foreach my $line (split(/\n/, $lines)) {
- $line =~ /^([0-9a-fA-F]{40,40}) (.*)$/;
- next if (!defined($1) || !defined($2));
- my $sha1 = $1;
- my $subject = $2;
- unshift(@commits, $sha1);
- $git_commits{$sha1} = $subject;
- }
- }
- die "$P: no git commits after extraction!\n" if (@commits == 0);
- @ARGV = @commits;
-}
-
-my $vname;
-for my $filename (@ARGV) {
- my $FILE;
- if ($git) {
- open($FILE, '-|', "git format-patch -M --stdout -1 $filename") ||
- die "$P: $filename: git format-patch failed - $!\n";
- } elsif ($file) {
- open($FILE, '-|', "diff -u /dev/null $filename") ||
- die "$P: $filename: diff failed - $!\n";
- } elsif ($filename eq '-') {
- open($FILE, '<&STDIN');
- } else {
- open($FILE, '<', "$filename") ||
- die "$P: $filename: open failed - $!\n";
- }
- if ($filename eq '-') {
- $vname = 'Your patch';
- } elsif ($git) {
- $vname = "Commit " . substr($filename, 0, 12) . ' ("' . $git_commits{$filename} . '")';
- } else {
- $vname = $filename;
- }
- while (<$FILE>) {
- chomp;
- push(@rawlines, $_);
- }
- close($FILE);
-
- if ($#ARGV > 0 && $quiet == 0) {
- print '-' x length($vname) . "\n";
- print "$vname\n";
- print '-' x length($vname) . "\n";
- }
-
- if (!process($filename)) {
- $exit = 1;
- }
- @rawlines = ();
- @lines = ();
- @fixed = ();
- @fixed_inserted = ();
- @fixed_deleted = ();
- $fixlinenr = -1;
- @modifierListFile = ();
- @typeListFile = ();
- build_types();
-}
-
-if (!$quiet) {
- hash_show_words(\%use_type, "Used");
- hash_show_words(\%ignore_type, "Ignored");
-
- if ($^V lt 5.10.0) {
- print << "EOM"
-
-NOTE: perl $^V is not modern enough to detect all possible issues.
- An upgrade to at least perl v5.10.0 is suggested.
-EOM
- }
- if ($exit) {
- print << "EOM"
-
-NOTE: If any of the errors are false positives, please report
- them to the maintainer, see CHECKPATCH in MAINTAINERS.
-EOM
- }
-}
-
-exit($exit);
-
-sub top_of_kernel_tree {
- my ($root) = @_;
-
- my @tree_check = (
- "COPYING", "CREDITS", "Kbuild", "MAINTAINERS", "Makefile",
- "README", "Documentation", "arch", "include", "drivers",
- "fs", "init", "ipc", "kernel", "lib", "scripts",
- );
-
- foreach my $check (@tree_check) {
- if (! -e $root . '/' . $check) {
- return 0;
- }
- }
- return 1;
-}
-
-sub parse_email {
- my ($formatted_email) = @_;
-
- my $name = "";
- my $address = "";
- my $comment = "";
-
- if ($formatted_email =~ /^(.*)<(\S+\@\S+)>(.*)$/) {
- $name = $1;
- $address = $2;
- $comment = $3 if defined $3;
- } elsif ($formatted_email =~ /^\s*<(\S+\@\S+)>(.*)$/) {
- $address = $1;
- $comment = $2 if defined $2;
- } elsif ($formatted_email =~ /(\S+\@\S+)(.*)$/) {
- $address = $1;
- $comment = $2 if defined $2;
- $formatted_email =~ s/$address.*$//;
- $name = $formatted_email;
- $name = trim($name);
- $name =~ s/^\"|\"$//g;
- # If there's a name left after stripping spaces and
- # leading quotes, and the address doesn't have both
- # leading and trailing angle brackets, the address
- # is invalid. ie:
- # "joe smith joe@smith.com" bad
- # "joe smith <joe@smith.com" bad
- if ($name ne "" && $address !~ /^<[^>]+>$/) {
- $name = "";
- $address = "";
- $comment = "";
- }
- }
-
- $name = trim($name);
- $name =~ s/^\"|\"$//g;
- $address = trim($address);
- $address =~ s/^\<|\>$//g;
-
- if ($name =~ /[^\w \-]/i) { ##has "must quote" chars
- $name =~ s/(?<!\\)"/\\"/g; ##escape quotes
- $name = "\"$name\"";
- }
-
- return ($name, $address, $comment);
-}
-
-sub format_email {
- my ($name, $address) = @_;
-
- my $formatted_email;
-
- $name = trim($name);
- $name =~ s/^\"|\"$//g;
- $address = trim($address);
-
- if ($name =~ /[^\w \-]/i) { ##has "must quote" chars
- $name =~ s/(?<!\\)"/\\"/g; ##escape quotes
- $name = "\"$name\"";
- }
-
- if ("$name" eq "") {
- $formatted_email = "$address";
- } else {
- $formatted_email = "$name <$address>";
- }
-
- return $formatted_email;
-}
-
-sub which {
- my ($bin) = @_;
-
- foreach my $path (split(/:/, $ENV{PATH})) {
- if (-e "$path/$bin") {
- return "$path/$bin";
- }
- }
-
- return "";
-}
-
-sub which_conf {
- my ($conf) = @_;
-
- foreach my $path (split(/:/, ".:$ENV{HOME}:.scripts")) {
- if (-e "$path/$conf") {
- return "$path/$conf";
- }
- }
-
- return "";
-}
-
-sub expand_tabs {
- my ($str) = @_;
-
- my $res = '';
- my $n = 0;
- for my $c (split(//, $str)) {
- if ($c eq "\t") {
- $res .= ' ';
- $n++;
- for (; ($n % 8) != 0; $n++) {
- $res .= ' ';
- }
- next;
- }
- $res .= $c;
- $n++;
- }
-
- return $res;
-}
-sub copy_spacing {
- (my $res = shift) =~ tr/\t/ /c;
- return $res;
-}
-
-sub line_stats {
- my ($line) = @_;
-
- # Drop the diff line leader and expand tabs
- $line =~ s/^.//;
- $line = expand_tabs($line);
-
- # Pick the indent from the front of the line.
- my ($white) = ($line =~ /^(\s*)/);
-
- return (length($line), length($white));
-}
-
-my $sanitise_quote = '';
-
-sub sanitise_line_reset {
- my ($in_comment) = @_;
-
- if ($in_comment) {
- $sanitise_quote = '*/';
- } else {
- $sanitise_quote = '';
- }
-}
-sub sanitise_line {
- my ($line) = @_;
-
- my $res = '';
- my $l = '';
-
- my $qlen = 0;
- my $off = 0;
- my $c;
-
- # Always copy over the diff marker.
- $res = substr($line, 0, 1);
-
- for ($off = 1; $off < length($line); $off++) {
- $c = substr($line, $off, 1);
-
- # Comments we are wacking completly including the begin
- # and end, all to $;.
- if ($sanitise_quote eq '' && substr($line, $off, 2) eq '/*') {
- $sanitise_quote = '*/';
-
- substr($res, $off, 2, "$;$;");
- $off++;
- next;
- }
- if ($sanitise_quote eq '*/' && substr($line, $off, 2) eq '*/') {
- $sanitise_quote = '';
- substr($res, $off, 2, "$;$;");
- $off++;
- next;
- }
- if ($sanitise_quote eq '' && substr($line, $off, 2) eq '//') {
- $sanitise_quote = '//';
-
- substr($res, $off, 2, $sanitise_quote);
- $off++;
- next;
- }
-
- # A \ in a string means ignore the next character.
- if (($sanitise_quote eq "'" || $sanitise_quote eq '"') &&
- $c eq "\\") {
- substr($res, $off, 2, 'XX');
- $off++;
- next;
- }
- # Regular quotes.
- if ($c eq "'" || $c eq '"') {
- if ($sanitise_quote eq '') {
- $sanitise_quote = $c;
-
- substr($res, $off, 1, $c);
- next;
- } elsif ($sanitise_quote eq $c) {
- $sanitise_quote = '';
- }
- }
-
- #print "c<$c> SQ<$sanitise_quote>\n";
- if ($off != 0 && $sanitise_quote eq '*/' && $c ne "\t") {
- substr($res, $off, 1, $;);
- } elsif ($off != 0 && $sanitise_quote eq '//' && $c ne "\t") {
- substr($res, $off, 1, $;);
- } elsif ($off != 0 && $sanitise_quote && $c ne "\t") {
- substr($res, $off, 1, 'X');
- } else {
- substr($res, $off, 1, $c);
- }
- }
-
- if ($sanitise_quote eq '//') {
- $sanitise_quote = '';
- }
-
- # The pathname on a #include may be surrounded by '<' and '>'.
- if ($res =~ /^.\s*\#\s*include\s+\<(.*)\>/) {
- my $clean = 'X' x length($1);
- $res =~ s@\<.*\>@<$clean>@;
-
- # The whole of a #error is a string.
- } elsif ($res =~ /^.\s*\#\s*(?:error|warning)\s+(.*)\b/) {
- my $clean = 'X' x length($1);
- $res =~ s@(\#\s*(?:error|warning)\s+).*@$1$clean@;
- }
-
- if ($allow_c99_comments && $res =~ m@(//.*$)@) {
- my $match = $1;
- $res =~ s/\Q$match\E/"$;" x length($match)/e;
- }
-
- return $res;
-}
-
-sub get_quoted_string {
- my ($line, $rawline) = @_;
-
- return "" if ($line !~ m/($String)/g);
- return substr($rawline, $-[0], $+[0] - $-[0]);
-}
-
-sub ctx_statement_block {
- my ($linenr, $remain, $off) = @_;
- my $line = $linenr - 1;
- my $blk = '';
- my $soff = $off;
- my $coff = $off - 1;
- my $coff_set = 0;
-
- my $loff = 0;
-
- my $type = '';
- my $level = 0;
- my @stack = ();
- my $p;
- my $c;
- my $len = 0;
-
- my $remainder;
- while (1) {
- @stack = (['', 0]) if ($#stack == -1);
-
- #warn "CSB: blk<$blk> remain<$remain>\n";
- # If we are about to drop off the end, pull in more
- # context.
- if ($off >= $len) {
- for (; $remain > 0; $line++) {
- last if (!defined $lines[$line]);
- next if ($lines[$line] =~ /^-/);
- $remain--;
- $loff = $len;
- $blk .= $lines[$line] . "\n";
- $len = length($blk);
- $line++;
- last;
- }
- # Bail if there is no further context.
- #warn "CSB: blk<$blk> off<$off> len<$len>\n";
- if ($off >= $len) {
- last;
- }
- if ($level == 0 && substr($blk, $off) =~ /^.\s*#\s*define/) {
- $level++;
- $type = '#';
- }
- }
- $p = $c;
- $c = substr($blk, $off, 1);
- $remainder = substr($blk, $off);
-
- #warn "CSB: c<$c> type<$type> level<$level> remainder<$remainder> coff_set<$coff_set>\n";
-
- # Handle nested #if/#else.
- if ($remainder =~ /^#\s*(?:ifndef|ifdef|if)\s/) {
- push(@stack, [ $type, $level ]);
- } elsif ($remainder =~ /^#\s*(?:else|elif)\b/) {
- ($type, $level) = @{$stack[$#stack - 1]};
- } elsif ($remainder =~ /^#\s*endif\b/) {
- ($type, $level) = @{pop(@stack)};
- }
-
- # Statement ends at the ';' or a close '}' at the
- # outermost level.
- if ($level == 0 && $c eq ';') {
- last;
- }
-
- # An else is really a conditional as long as its not else if
- if ($level == 0 && $coff_set == 0 &&
- (!defined($p) || $p =~ /(?:\s|\}|\+)/) &&
- $remainder =~ /^(else)(?:\s|{)/ &&
- $remainder !~ /^else\s+if\b/) {
- $coff = $off + length($1) - 1;
- $coff_set = 1;
- #warn "CSB: mark coff<$coff> soff<$soff> 1<$1>\n";
- #warn "[" . substr($blk, $soff, $coff - $soff + 1) . "]\n";
- }
-
- if (($type eq '' || $type eq '(') && $c eq '(') {
- $level++;
- $type = '(';
- }
- if ($type eq '(' && $c eq ')') {
- $level--;
- $type = ($level != 0)? '(' : '';
-
- if ($level == 0 && $coff < $soff) {
- $coff = $off;
- $coff_set = 1;
- #warn "CSB: mark coff<$coff>\n";
- }
- }
- if (($type eq '' || $type eq '{') && $c eq '{') {
- $level++;
- $type = '{';
- }
- if ($type eq '{' && $c eq '}') {
- $level--;
- $type = ($level != 0)? '{' : '';
-
- if ($level == 0) {
- if (substr($blk, $off + 1, 1) eq ';') {
- $off++;
- }
- last;
- }
- }
- # Preprocessor commands end at the newline unless escaped.
- if ($type eq '#' && $c eq "\n" && $p ne "\\") {
- $level--;
- $type = '';
- $off++;
- last;
- }
- $off++;
- }
- # We are truly at the end, so shuffle to the next line.
- if ($off == $len) {
- $loff = $len + 1;
- $line++;
- $remain--;
- }
-
- my $statement = substr($blk, $soff, $off - $soff + 1);
- my $condition = substr($blk, $soff, $coff - $soff + 1);
-
- #warn "STATEMENT<$statement>\n";
- #warn "CONDITION<$condition>\n";
-
- #print "coff<$coff> soff<$off> loff<$loff>\n";
-
- return ($statement, $condition,
- $line, $remain + 1, $off - $loff + 1, $level);
-}
-
-sub statement_lines {
- my ($stmt) = @_;
-
- # Strip the diff line prefixes and rip blank lines at start and end.
- $stmt =~ s/(^|\n)./$1/g;
- $stmt =~ s/^\s*//;
- $stmt =~ s/\s*$//;
-
- my @stmt_lines = ($stmt =~ /\n/g);
-
- return $#stmt_lines + 2;
-}
-
-sub statement_rawlines {
- my ($stmt) = @_;
-
- my @stmt_lines = ($stmt =~ /\n/g);
-
- return $#stmt_lines + 2;
-}
-
-sub statement_block_size {
- my ($stmt) = @_;
-
- $stmt =~ s/(^|\n)./$1/g;
- $stmt =~ s/^\s*{//;
- $stmt =~ s/}\s*$//;
- $stmt =~ s/^\s*//;
- $stmt =~ s/\s*$//;
-
- my @stmt_lines = ($stmt =~ /\n/g);
- my @stmt_statements = ($stmt =~ /;/g);
-
- my $stmt_lines = $#stmt_lines + 2;
- my $stmt_statements = $#stmt_statements + 1;
-
- if ($stmt_lines > $stmt_statements) {
- return $stmt_lines;
- } else {
- return $stmt_statements;
- }
-}
-
-sub ctx_statement_full {
- my ($linenr, $remain, $off) = @_;
- my ($statement, $condition, $level);
-
- my (@chunks);
-
- # Grab the first conditional/block pair.
- ($statement, $condition, $linenr, $remain, $off, $level) =
- ctx_statement_block($linenr, $remain, $off);
- #print "F: c<$condition> s<$statement> remain<$remain>\n";
- push(@chunks, [ $condition, $statement ]);
- if (!($remain > 0 && $condition =~ /^\s*(?:\n[+-])?\s*(?:if|else|do)\b/s)) {
- return ($level, $linenr, @chunks);
- }
-
- # Pull in the following conditional/block pairs and see if they
- # could continue the statement.
- for (;;) {
- ($statement, $condition, $linenr, $remain, $off, $level) =
- ctx_statement_block($linenr, $remain, $off);
- #print "C: c<$condition> s<$statement> remain<$remain>\n";
- last if (!($remain > 0 && $condition =~ /^(?:\s*\n[+-])*\s*(?:else|do)\b/s));
- #print "C: push\n";
- push(@chunks, [ $condition, $statement ]);
- }
-
- return ($level, $linenr, @chunks);
-}
-
-sub ctx_block_get {
- my ($linenr, $remain, $outer, $open, $close, $off) = @_;
- my $line;
- my $start = $linenr - 1;
- my $blk = '';
- my @o;
- my @c;
- my @res = ();
-
- my $level = 0;
- my @stack = ($level);
- for ($line = $start; $remain > 0; $line++) {
- next if ($rawlines[$line] =~ /^-/);
- $remain--;
-
- $blk .= $rawlines[$line];
-
- # Handle nested #if/#else.
- if ($lines[$line] =~ /^.\s*#\s*(?:ifndef|ifdef|if)\s/) {
- push(@stack, $level);
- } elsif ($lines[$line] =~ /^.\s*#\s*(?:else|elif)\b/) {
- $level = $stack[$#stack - 1];
- } elsif ($lines[$line] =~ /^.\s*#\s*endif\b/) {
- $level = pop(@stack);
- }
-
- foreach my $c (split(//, $lines[$line])) {
- ##print "C<$c>L<$level><$open$close>O<$off>\n";
- if ($off > 0) {
- $off--;
- next;
- }
-
- if ($c eq $close && $level > 0) {
- $level--;
- last if ($level == 0);
- } elsif ($c eq $open) {
- $level++;
- }
- }
-
- if (!$outer || $level <= 1) {
- push(@res, $rawlines[$line]);
- }
-
- last if ($level == 0);
- }
-
- return ($level, @res);
-}
-sub ctx_block_outer {
- my ($linenr, $remain) = @_;
-
- my ($level, @r) = ctx_block_get($linenr, $remain, 1, '{', '}', 0);
- return @r;
-}
-sub ctx_block {
- my ($linenr, $remain) = @_;
-
- my ($level, @r) = ctx_block_get($linenr, $remain, 0, '{', '}', 0);
- return @r;
-}
-sub ctx_statement {
- my ($linenr, $remain, $off) = @_;
-
- my ($level, @r) = ctx_block_get($linenr, $remain, 0, '(', ')', $off);
- return @r;
-}
-sub ctx_block_level {
- my ($linenr, $remain) = @_;
-
- return ctx_block_get($linenr, $remain, 0, '{', '}', 0);
-}
-sub ctx_statement_level {
- my ($linenr, $remain, $off) = @_;
-
- return ctx_block_get($linenr, $remain, 0, '(', ')', $off);
-}
-
-sub ctx_locate_comment {
- my ($first_line, $end_line) = @_;
-
- # Catch a comment on the end of the line itself.
- my ($current_comment) = ($rawlines[$end_line - 1] =~ m@.*(/\*.*\*/)\s*(?:\\\s*)?$@);
- return $current_comment if (defined $current_comment);
-
- # Look through the context and try and figure out if there is a
- # comment.
- my $in_comment = 0;
- $current_comment = '';
- for (my $linenr = $first_line; $linenr < $end_line; $linenr++) {
- my $line = $rawlines[$linenr - 1];
- #warn " $line\n";
- if ($linenr == $first_line and $line =~ m@^.\s*\*@) {
- $in_comment = 1;
- }
- if ($line =~ m@/\*@) {
- $in_comment = 1;
- }
- if (!$in_comment && $current_comment ne '') {
- $current_comment = '';
- }
- $current_comment .= $line . "\n" if ($in_comment);
- if ($line =~ m@\*/@) {
- $in_comment = 0;
- }
- }
-
- chomp($current_comment);
- return($current_comment);
-}
-sub ctx_has_comment {
- my ($first_line, $end_line) = @_;
- my $cmt = ctx_locate_comment($first_line, $end_line);
-
- ##print "LINE: $rawlines[$end_line - 1 ]\n";
- ##print "CMMT: $cmt\n";
-
- return ($cmt ne '');
-}
-
-sub raw_line {
- my ($linenr, $cnt) = @_;
-
- my $offset = $linenr - 1;
- $cnt++;
-
- my $line;
- while ($cnt) {
- $line = $rawlines[$offset++];
- next if (defined($line) && $line =~ /^-/);
- $cnt--;
- }
-
- return $line;
-}
-
-sub cat_vet {
- my ($vet) = @_;
- my ($res, $coded);
-
- $res = '';
- while ($vet =~ /([^[:cntrl:]]*)([[:cntrl:]]|$)/g) {
- $res .= $1;
- if ($2 ne '') {
- $coded = sprintf("^%c", unpack('C', $2) + 64);
- $res .= $coded;
- }
- }
- $res =~ s/$/\$/;
-
- return $res;
-}
-
-my $av_preprocessor = 0;
-my $av_pending;
-my @av_paren_type;
-my $av_pend_colon;
-
-sub annotate_reset {
- $av_preprocessor = 0;
- $av_pending = '_';
- @av_paren_type = ('E');
- $av_pend_colon = 'O';
-}
-
-sub annotate_values {
- my ($stream, $type) = @_;
-
- my $res;
- my $var = '_' x length($stream);
- my $cur = $stream;
-
- print "$stream\n" if ($dbg_values > 1);
-
- while (length($cur)) {
- @av_paren_type = ('E') if ($#av_paren_type < 0);
- print " <" . join('', @av_paren_type) .
- "> <$type> <$av_pending>" if ($dbg_values > 1);
- if ($cur =~ /^(\s+)/o) {
- print "WS($1)\n" if ($dbg_values > 1);
- if ($1 =~ /\n/ && $av_preprocessor) {
- $type = pop(@av_paren_type);
- $av_preprocessor = 0;
- }
-
- } elsif ($cur =~ /^(\(\s*$Type\s*)\)/ && $av_pending eq '_') {
- print "CAST($1)\n" if ($dbg_values > 1);
- push(@av_paren_type, $type);
- $type = 'c';
-
- } elsif ($cur =~ /^($Type)\s*(?:$Ident|,|\)|\(|\s*$)/) {
- print "DECLARE($1)\n" if ($dbg_values > 1);
- $type = 'T';
-
- } elsif ($cur =~ /^($Modifier)\s*/) {
- print "MODIFIER($1)\n" if ($dbg_values > 1);
- $type = 'T';
-
- } elsif ($cur =~ /^(\#\s*define\s*$Ident)(\(?)/o) {
- print "DEFINE($1,$2)\n" if ($dbg_values > 1);
- $av_preprocessor = 1;
- push(@av_paren_type, $type);
- if ($2 ne '') {
- $av_pending = 'N';
- }
- $type = 'E';
-
- } elsif ($cur =~ /^(\#\s*(?:undef\s*$Ident|include\b))/o) {
- print "UNDEF($1)\n" if ($dbg_values > 1);
- $av_preprocessor = 1;
- push(@av_paren_type, $type);
-
- } elsif ($cur =~ /^(\#\s*(?:ifdef|ifndef|if))/o) {
- print "PRE_START($1)\n" if ($dbg_values > 1);
- $av_preprocessor = 1;
-
- push(@av_paren_type, $type);
- push(@av_paren_type, $type);
- $type = 'E';
-
- } elsif ($cur =~ /^(\#\s*(?:else|elif))/o) {
- print "PRE_RESTART($1)\n" if ($dbg_values > 1);
- $av_preprocessor = 1;
-
- push(@av_paren_type, $av_paren_type[$#av_paren_type]);
-
- $type = 'E';
-
- } elsif ($cur =~ /^(\#\s*(?:endif))/o) {
- print "PRE_END($1)\n" if ($dbg_values > 1);
-
- $av_preprocessor = 1;
-
- # Assume all arms of the conditional end as this
- # one does, and continue as if the #endif was not here.
- pop(@av_paren_type);
- push(@av_paren_type, $type);
- $type = 'E';
-
- } elsif ($cur =~ /^(\\\n)/o) {
- print "PRECONT($1)\n" if ($dbg_values > 1);
-
- } elsif ($cur =~ /^(__attribute__)\s*\(?/o) {
- print "ATTR($1)\n" if ($dbg_values > 1);
- $av_pending = $type;
- $type = 'N';
-
- } elsif ($cur =~ /^(sizeof)\s*(\()?/o) {
- print "SIZEOF($1)\n" if ($dbg_values > 1);
- if (defined $2) {
- $av_pending = 'V';
- }
- $type = 'N';
-
- } elsif ($cur =~ /^(if|while|for)\b/o) {
- print "COND($1)\n" if ($dbg_values > 1);
- $av_pending = 'E';
- $type = 'N';
-
- } elsif ($cur =~/^(case)/o) {
- print "CASE($1)\n" if ($dbg_values > 1);
- $av_pend_colon = 'C';
- $type = 'N';
-
- } elsif ($cur =~/^(return|else|goto|typeof|__typeof__)\b/o) {
- print "KEYWORD($1)\n" if ($dbg_values > 1);
- $type = 'N';
-
- } elsif ($cur =~ /^(\()/o) {
- print "PAREN('$1')\n" if ($dbg_values > 1);
- push(@av_paren_type, $av_pending);
- $av_pending = '_';
- $type = 'N';
-
- } elsif ($cur =~ /^(\))/o) {
- my $new_type = pop(@av_paren_type);
- if ($new_type ne '_') {
- $type = $new_type;
- print "PAREN('$1') -> $type\n"
- if ($dbg_values > 1);
- } else {
- print "PAREN('$1')\n" if ($dbg_values > 1);
- }
-
- } elsif ($cur =~ /^($Ident)\s*\(/o) {
- print "FUNC($1)\n" if ($dbg_values > 1);
- $type = 'V';
- $av_pending = 'V';
-
- } elsif ($cur =~ /^($Ident\s*):(?:\s*\d+\s*(,|=|;))?/) {
- if (defined $2 && $type eq 'C' || $type eq 'T') {
- $av_pend_colon = 'B';
- } elsif ($type eq 'E') {
- $av_pend_colon = 'L';
- }
- print "IDENT_COLON($1,$type>$av_pend_colon)\n" if ($dbg_values > 1);
- $type = 'V';
-
- } elsif ($cur =~ /^($Ident|$Constant)/o) {
- print "IDENT($1)\n" if ($dbg_values > 1);
- $type = 'V';
-
- } elsif ($cur =~ /^($Assignment)/o) {
- print "ASSIGN($1)\n" if ($dbg_values > 1);
- $type = 'N';
-
- } elsif ($cur =~/^(;|{|})/) {
- print "END($1)\n" if ($dbg_values > 1);
- $type = 'E';
- $av_pend_colon = 'O';
-
- } elsif ($cur =~/^(,)/) {
- print "COMMA($1)\n" if ($dbg_values > 1);
- $type = 'C';
-
- } elsif ($cur =~ /^(\?)/o) {
- print "QUESTION($1)\n" if ($dbg_values > 1);
- $type = 'N';
-
- } elsif ($cur =~ /^(:)/o) {
- print "COLON($1,$av_pend_colon)\n" if ($dbg_values > 1);
-
- substr($var, length($res), 1, $av_pend_colon);
- if ($av_pend_colon eq 'C' || $av_pend_colon eq 'L') {
- $type = 'E';
- } else {
- $type = 'N';
- }
- $av_pend_colon = 'O';
-
- } elsif ($cur =~ /^(\[)/o) {
- print "CLOSE($1)\n" if ($dbg_values > 1);
- $type = 'N';
-
- } elsif ($cur =~ /^(-(?![->])|\+(?!\+)|\*|\&\&|\&)/o) {
- my $variant;
-
- print "OPV($1)\n" if ($dbg_values > 1);
- if ($type eq 'V') {
- $variant = 'B';
- } else {
- $variant = 'U';
- }
-
- substr($var, length($res), 1, $variant);
- $type = 'N';
-
- } elsif ($cur =~ /^($Operators)/o) {
- print "OP($1)\n" if ($dbg_values > 1);
- if ($1 ne '++' && $1 ne '--') {
- $type = 'N';
- }
-
- } elsif ($cur =~ /(^.)/o) {
- print "C($1)\n" if ($dbg_values > 1);
- }
- if (defined $1) {
- $cur = substr($cur, length($1));
- $res .= $type x length($1);
- }
- }
-
- return ($res, $var);
-}
-
-sub possible {
- my ($possible, $line) = @_;
- my $notPermitted = qr{(?:
- ^(?:
- $Modifier|
- $Storage|
- $Type|
- DEFINE_\S+
- )$|
- ^(?:
- goto|
- return|
- case|
- else|
- asm|__asm__|
- do|
- \#|
- \#\#|
- )(?:\s|$)|
- ^(?:typedef|struct|enum)\b
- )}x;
- warn "CHECK<$possible> ($line)\n" if ($dbg_possible > 2);
- if ($possible !~ $notPermitted) {
- # Check for modifiers.
- $possible =~ s/\s*$Storage\s*//g;
- $possible =~ s/\s*$Sparse\s*//g;
- if ($possible =~ /^\s*$/) {
-
- } elsif ($possible =~ /\s/) {
- $possible =~ s/\s*$Type\s*//g;
- for my $modifier (split(' ', $possible)) {
- if ($modifier !~ $notPermitted) {
- warn "MODIFIER: $modifier ($possible) ($line)\n" if ($dbg_possible);
- push(@modifierListFile, $modifier);
- }
- }
-
- } else {
- warn "POSSIBLE: $possible ($line)\n" if ($dbg_possible);
- push(@typeListFile, $possible);
- }
- build_types();
- } else {
- warn "NOTPOSS: $possible ($line)\n" if ($dbg_possible > 1);
- }
-}
-
-my $prefix = '';
-
-sub show_type {
- my ($type) = @_;
-
- $type =~ tr/[a-z]/[A-Z]/;
-
- return defined $use_type{$type} if (scalar keys %use_type > 0);
-
- return !defined $ignore_type{$type};
-}
-
-sub report {
- my ($level, $type, $msg) = @_;
-
- if (!show_type($type) ||
- (defined $tst_only && $msg !~ /\Q$tst_only\E/)) {
- return 0;
- }
- my $output = '';
- if ($color) {
- if ($level eq 'ERROR') {
- $output .= RED;
- } elsif ($level eq 'WARNING') {
- $output .= YELLOW;
- } else {
- $output .= GREEN;
- }
- }
- $output .= $prefix . $level . ':';
- if ($show_types) {
- $output .= BLUE if ($color);
- $output .= "$type:";
- }
- $output .= RESET if ($color);
- $output .= ' ' . $msg . "\n";
-
- if ($showfile) {
- my @lines = split("\n", $output, -1);
- splice(@lines, 1, 1);
- $output = join("\n", @lines);
- }
- $output = (split('\n', $output))[0] . "\n" if ($terse);
-
- push(our @report, $output);
-
- return 1;
-}
-
-sub report_dump {
- our @report;
-}
-
-sub fixup_current_range {
- my ($lineRef, $offset, $length) = @_;
-
- if ($$lineRef =~ /^\@\@ -\d+,\d+ \+(\d+),(\d+) \@\@/) {
- my $o = $1;
- my $l = $2;
- my $no = $o + $offset;
- my $nl = $l + $length;
- $$lineRef =~ s/\+$o,$l \@\@/\+$no,$nl \@\@/;
- }
-}
-
-sub fix_inserted_deleted_lines {
- my ($linesRef, $insertedRef, $deletedRef) = @_;
-
- my $range_last_linenr = 0;
- my $delta_offset = 0;
-
- my $old_linenr = 0;
- my $new_linenr = 0;
-
- my $next_insert = 0;
- my $next_delete = 0;
-
- my @lines = ();
-
- my $inserted = @{$insertedRef}[$next_insert++];
- my $deleted = @{$deletedRef}[$next_delete++];
-
- foreach my $old_line (@{$linesRef}) {
- my $save_line = 1;
- my $line = $old_line; #don't modify the array
- if ($line =~ /^(?:\+\+\+|\-\-\-)\s+\S+/) { #new filename
- $delta_offset = 0;
- } elsif ($line =~ /^\@\@ -\d+,\d+ \+\d+,\d+ \@\@/) { #new hunk
- $range_last_linenr = $new_linenr;
- fixup_current_range(\$line, $delta_offset, 0);
- }
-
- while (defined($deleted) && ${$deleted}{'LINENR'} == $old_linenr) {
- $deleted = @{$deletedRef}[$next_delete++];
- $save_line = 0;
- fixup_current_range(\$lines[$range_last_linenr], $delta_offset--, -1);
- }
-
- while (defined($inserted) && ${$inserted}{'LINENR'} == $old_linenr) {
- push(@lines, ${$inserted}{'LINE'});
- $inserted = @{$insertedRef}[$next_insert++];
- $new_linenr++;
- fixup_current_range(\$lines[$range_last_linenr], $delta_offset++, 1);
- }
-
- if ($save_line) {
- push(@lines, $line);
- $new_linenr++;
- }
-
- $old_linenr++;
- }
-
- return @lines;
-}
-
-sub fix_insert_line {
- my ($linenr, $line) = @_;
-
- my $inserted = {
- LINENR => $linenr,
- LINE => $line,
- };
- push(@fixed_inserted, $inserted);
-}
-
-sub fix_delete_line {
- my ($linenr, $line) = @_;
-
- my $deleted = {
- LINENR => $linenr,
- LINE => $line,
- };
-
- push(@fixed_deleted, $deleted);
-}
-
-sub ERROR {
- my ($type, $msg) = @_;
-
- if (report("ERROR", $type, $msg)) {
- our $clean = 0;
- our $cnt_error++;
- return 1;
- }
- return 0;
-}
-sub WARN {
- my ($type, $msg) = @_;
-
- if (report("WARNING", $type, $msg)) {
- our $clean = 0;
- our $cnt_warn++;
- return 1;
- }
- return 0;
-}
-sub CHK {
- my ($type, $msg) = @_;
-
- if ($check && report("CHECK", $type, $msg)) {
- our $clean = 0;
- our $cnt_chk++;
- return 1;
- }
- return 0;
-}
-
-sub check_absolute_file {
- my ($absolute, $herecurr) = @_;
- my $file = $absolute;
-
- ##print "absolute<$absolute>\n";
-
- # See if any suffix of this path is a path within the tree.
- while ($file =~ s@^[^/]*/@@) {
- if (-f "$root/$file") {
- ##print "file<$file>\n";
- last;
- }
- }
- if (! -f _) {
- return 0;
- }
-
- # It is, so see if the prefix is acceptable.
- my $prefix = $absolute;
- substr($prefix, -length($file)) = '';
-
- ##print "prefix<$prefix>\n";
- if ($prefix ne ".../") {
- WARN("USE_RELATIVE_PATH",
- "use relative pathname instead of absolute in changelog text\n" . $herecurr);
- }
-}
-
-sub trim {
- my ($string) = @_;
-
- $string =~ s/^\s+|\s+$//g;
-
- return $string;
-}
-
-sub ltrim {
- my ($string) = @_;
-
- $string =~ s/^\s+//;
-
- return $string;
-}
-
-sub rtrim {
- my ($string) = @_;
-
- $string =~ s/\s+$//;
-
- return $string;
-}
-
-sub string_find_replace {
- my ($string, $find, $replace) = @_;
-
- $string =~ s/$find/$replace/g;
-
- return $string;
-}
-
-sub tabify {
- my ($leading) = @_;
-
- my $source_indent = 8;
- my $max_spaces_before_tab = $source_indent - 1;
- my $spaces_to_tab = " " x $source_indent;
-
- #convert leading spaces to tabs
- 1 while $leading =~ s@^([\t]*)$spaces_to_tab@$1\t@g;
- #Remove spaces before a tab
- 1 while $leading =~ s@^([\t]*)( {1,$max_spaces_before_tab})\t@$1\t@g;
-
- return "$leading";
-}
-
-sub pos_last_openparen {
- my ($line) = @_;
-
- my $pos = 0;
-
- my $opens = $line =~ tr/\(/\(/;
- my $closes = $line =~ tr/\)/\)/;
-
- my $last_openparen = 0;
-
- if (($opens == 0) || ($closes >= $opens)) {
- return -1;
- }
-
- my $len = length($line);
-
- for ($pos = 0; $pos < $len; $pos++) {
- my $string = substr($line, $pos);
- if ($string =~ /^($FuncArg|$balanced_parens)/) {
- $pos += length($1) - 1;
- } elsif (substr($line, $pos, 1) eq '(') {
- $last_openparen = $pos;
- } elsif (index($string, '(') == -1) {
- last;
- }
- }
-
- return length(expand_tabs(substr($line, 0, $last_openparen))) + 1;
-}
-
-sub process {
- my $filename = shift;
-
- my $linenr=0;
- my $prevline="";
- my $prevrawline="";
- my $stashline="";
- my $stashrawline="";
-
- my $length;
- my $indent;
- my $previndent=0;
- my $stashindent=0;
-
- our $clean = 1;
- my $signoff = 0;
- my $is_patch = 0;
- my $in_header_lines = $file ? 0 : 1;
- my $in_commit_log = 0; #Scanning lines before patch
- my $has_commit_log = 0; #Encountered lines before patch
- my $commit_log_possible_stack_dump = 0;
- my $commit_log_long_line = 0;
- my $commit_log_has_diff = 0;
- my $reported_maintainer_file = 0;
- my $non_utf8_charset = 0;
-
- my $last_blank_line = 0;
- my $last_coalesced_string_linenr = -1;
-
- our @report = ();
- our $cnt_lines = 0;
- our $cnt_error = 0;
- our $cnt_warn = 0;
- our $cnt_chk = 0;
-
- # Trace the real file/line as we go.
- my $realfile = '';
- my $realline = 0;
- my $realcnt = 0;
- my $here = '';
- my $context_function; #undef'd unless there's a known function
- my $in_comment = 0;
- my $comment_edge = 0;
- my $first_line = 0;
- my $p1_prefix = '';
-
- my $prev_values = 'E';
-
- # suppression flags
- my %suppress_ifbraces;
- my %suppress_whiletrailers;
- my %suppress_export;
- my $suppress_statement = 0;
-
- my %signatures = ();
-
- # Pre-scan the patch sanitizing the lines.
- # Pre-scan the patch looking for any __setup documentation.
- #
- my @setup_docs = ();
- my $setup_docs = 0;
-
- my $camelcase_file_seeded = 0;
-
- sanitise_line_reset();
- my $line;
- foreach my $rawline (@rawlines) {
- $linenr++;
- $line = $rawline;
-
- push(@fixed, $rawline) if ($fix);
-
- if ($rawline=~/^\+\+\+\s+(\S+)/) {
- $setup_docs = 0;
- if ($1 =~ m@Documentation/admin-guide/kernel-parameters.rst$@) {
- $setup_docs = 1;
- }
- #next;
- }
- if ($rawline =~ /^\@\@ -\d+(?:,\d+)? \+(\d+)(,(\d+))? \@\@/) {
- $realline=$1-1;
- if (defined $2) {
- $realcnt=$3+1;
- } else {
- $realcnt=1+1;
- }
- $in_comment = 0;
-
- # Guestimate if this is a continuing comment. Run
- # the context looking for a comment "edge". If this
- # edge is a close comment then we must be in a comment
- # at context start.
- my $edge;
- my $cnt = $realcnt;
- for (my $ln = $linenr + 1; $cnt > 0; $ln++) {
- next if (defined $rawlines[$ln - 1] &&
- $rawlines[$ln - 1] =~ /^-/);
- $cnt--;
- #print "RAW<$rawlines[$ln - 1]>\n";
- last if (!defined $rawlines[$ln - 1]);
- if ($rawlines[$ln - 1] =~ m@(/\*|\*/)@ &&
- $rawlines[$ln - 1] !~ m@"[^"]*(?:/\*|\*/)[^"]*"@) {
- ($edge) = $1;
- last;
- }
- }
- if (defined $edge && $edge eq '*/') {
- $in_comment = 1;
- }
-
- # Guestimate if this is a continuing comment. If this
- # is the start of a diff block and this line starts
- # ' *' then it is very likely a comment.
- if (!defined $edge &&
- $rawlines[$linenr] =~ m@^.\s*(?:\*\*+| \*)(?:\s|$)@)
- {
- $in_comment = 1;
- }
-
- ##print "COMMENT:$in_comment edge<$edge> $rawline\n";
- sanitise_line_reset($in_comment);
-
- } elsif ($realcnt && $rawline =~ /^(?:\+| |$)/) {
- # Standardise the strings and chars within the input to
- # simplify matching -- only bother with positive lines.
- $line = sanitise_line($rawline);
- }
- push(@lines, $line);
-
- if ($realcnt > 1) {
- $realcnt-- if ($line =~ /^(?:\+| |$)/);
- } else {
- $realcnt = 0;
- }
-
- #print "==>$rawline\n";
- #print "-->$line\n";
-
- if ($setup_docs && $line =~ /^\+/) {
- push(@setup_docs, $line);
- }
- }
-
- $prefix = '';
-
- $realcnt = 0;
- $linenr = 0;
- $fixlinenr = -1;
- foreach my $line (@lines) {
- $linenr++;
- $fixlinenr++;
- my $sline = $line; #copy of $line
- $sline =~ s/$;/ /g; #with comments as spaces
-
- my $rawline = $rawlines[$linenr - 1];
-
-#extract the line range in the file after the patch is applied
- if (!$in_commit_log &&
- $line =~ /^\@\@ -\d+(?:,\d+)? \+(\d+)(,(\d+))? \@\@(.*)/) {
- my $context = $4;
- $is_patch = 1;
- $first_line = $linenr + 1;
- $realline=$1-1;
- if (defined $2) {
- $realcnt=$3+1;
- } else {
- $realcnt=1+1;
- }
- annotate_reset();
- $prev_values = 'E';
-
- %suppress_ifbraces = ();
- %suppress_whiletrailers = ();
- %suppress_export = ();
- $suppress_statement = 0;
- if ($context =~ /\b(\w+)\s*\(/) {
- $context_function = $1;
- } else {
- undef $context_function;
- }
- next;
-
-# track the line number as we move through the hunk, note that
-# new versions of GNU diff omit the leading space on completely
-# blank context lines so we need to count that too.
- } elsif ($line =~ /^( |\+|$)/) {
- $realline++;
- $realcnt-- if ($realcnt != 0);
-
- # Measure the line length and indent.
- ($length, $indent) = line_stats($rawline);
-
- # Track the previous line.
- ($prevline, $stashline) = ($stashline, $line);
- ($previndent, $stashindent) = ($stashindent, $indent);
- ($prevrawline, $stashrawline) = ($stashrawline, $rawline);
-
- #warn "line<$line>\n";
-
- } elsif ($realcnt == 1) {
- $realcnt--;
- }
-
- my $hunk_line = ($realcnt != 0);
-
- $here = "#$linenr: " if (!$file);
- $here = "#$realline: " if ($file);
-
- my $found_file = 0;
- # extract the filename as it passes
- if ($line =~ /^diff --git.*?(\S+)$/) {
- $realfile = $1;
- $realfile =~ s@^([^/]*)/@@ if (!$file);
- $in_commit_log = 0;
- $found_file = 1;
- } elsif ($line =~ /^\+\+\+\s+(\S+)/) {
- $realfile = $1;
- $realfile =~ s@^([^/]*)/@@ if (!$file);
- $in_commit_log = 0;
-
- $p1_prefix = $1;
- if (!$file && $tree && $p1_prefix ne '' &&
- -e "$root/$p1_prefix") {
- WARN("PATCH_PREFIX",
- "patch prefix '$p1_prefix' exists, appears to be a -p0 patch\n");
- }
-
- if ($realfile =~ m@^include/asm/@) {
- ERROR("MODIFIED_INCLUDE_ASM",
- "do not modify files in include/asm, change architecture specific files in include/asm-<architecture>\n" . "$here$rawline\n");
- }
- $found_file = 1;
- }
-
-#make up the handle for any error we report on this line
- if ($showfile) {
- $prefix = "$realfile:$realline: "
- } elsif ($emacs) {
- if ($file) {
- $prefix = "$filename:$realline: ";
- } else {
- $prefix = "$filename:$linenr: ";
- }
- }
-
- if ($found_file) {
- if (is_maintained_obsolete($realfile)) {
- WARN("OBSOLETE",
- "$realfile is marked as 'obsolete' in the MAINTAINERS hierarchy. No unnecessary modifications please.\n");
- }
- if ($realfile =~ m@^(?:drivers/net/|net/|drivers/staging/)@) {
- $check = 1;
- } else {
- $check = $check_orig;
- }
- next;
- }
-
- $here .= "FILE: $realfile:$realline:" if ($realcnt != 0);
-
- my $hereline = "$here\n$rawline\n";
- my $herecurr = "$here\n$rawline\n";
- my $hereprev = "$here\n$prevrawline\n$rawline\n";
-
- $cnt_lines++ if ($realcnt != 0);
-
-# Check if the commit log has what seems like a diff which can confuse patch
- if ($in_commit_log && !$commit_log_has_diff &&
- (($line =~ m@^\s+diff\b.*a/[\w/]+@ &&
- $line =~ m@^\s+diff\b.*a/([\w/]+)\s+b/$1\b@) ||
- $line =~ m@^\s*(?:\-\-\-\s+a/|\+\+\+\s+b/)@ ||
- $line =~ m/^\s*\@\@ \-\d+,\d+ \+\d+,\d+ \@\@/)) {
- ERROR("DIFF_IN_COMMIT_MSG",
- "Avoid using diff content in the commit message - patch(1) might not work\n" . $herecurr);
- $commit_log_has_diff = 1;
- }
-
-# Check for incorrect file permissions
- if ($line =~ /^new (file )?mode.*[7531]\d{0,2}$/) {
- my $permhere = $here . "FILE: $realfile\n";
- if ($realfile !~ m@scripts/@ &&
- $realfile !~ /\.(py|pl|awk|sh)$/) {
- ERROR("EXECUTE_PERMISSIONS",
- "do not set execute permissions for source files\n" . $permhere);
- }
- }
-
-# Check the patch for a signoff:
- if ($line =~ /^\s*signed-off-by:/i) {
- $signoff++;
- $in_commit_log = 0;
- }
-
-# Check if MAINTAINERS is being updated. If so, there's probably no need to
-# emit the "does MAINTAINERS need updating?" message on file add/move/delete
- if ($line =~ /^\s*MAINTAINERS\s*\|/) {
- $reported_maintainer_file = 1;
- }
-
-# Check signature styles
- if (!$in_header_lines &&
- $line =~ /^(\s*)([a-z0-9_-]+by:|$signature_tags)(\s*)(.*)/i) {
- my $space_before = $1;
- my $sign_off = $2;
- my $space_after = $3;
- my $email = $4;
- my $ucfirst_sign_off = ucfirst(lc($sign_off));
-
- if ($sign_off !~ /$signature_tags/) {
- WARN("BAD_SIGN_OFF",
- "Non-standard signature: $sign_off\n" . $herecurr);
- }
- if (defined $space_before && $space_before ne "") {
- if (WARN("BAD_SIGN_OFF",
- "Do not use whitespace before $ucfirst_sign_off\n" . $herecurr) &&
- $fix) {
- $fixed[$fixlinenr] =
- "$ucfirst_sign_off $email";
- }
- }
- if ($sign_off =~ /-by:$/i && $sign_off ne $ucfirst_sign_off) {
- if (WARN("BAD_SIGN_OFF",
- "'$ucfirst_sign_off' is the preferred signature form\n" . $herecurr) &&
- $fix) {
- $fixed[$fixlinenr] =
- "$ucfirst_sign_off $email";
- }
-
- }
- if (!defined $space_after || $space_after ne " ") {
- if (WARN("BAD_SIGN_OFF",
- "Use a single space after $ucfirst_sign_off\n" . $herecurr) &&
- $fix) {
- $fixed[$fixlinenr] =
- "$ucfirst_sign_off $email";
- }
- }
-
- my ($email_name, $email_address, $comment) = parse_email($email);
- my $suggested_email = format_email(($email_name, $email_address));
- if ($suggested_email eq "") {
- ERROR("BAD_SIGN_OFF",
- "Unrecognized email address: '$email'\n" . $herecurr);
- } else {
- my $dequoted = $suggested_email;
- $dequoted =~ s/^"//;
- $dequoted =~ s/" </ </;
- # Don't force email to have quotes
- # Allow just an angle bracketed address
- if ("$dequoted$comment" ne $email &&
- "<$email_address>$comment" ne $email &&
- "$suggested_email$comment" ne $email) {
- WARN("BAD_SIGN_OFF",
- "email address '$email' might be better as '$suggested_email$comment'\n" . $herecurr);
- }
- }
-
-# Check for duplicate signatures
- my $sig_nospace = $line;
- $sig_nospace =~ s/\s//g;
- $sig_nospace = lc($sig_nospace);
- if (defined $signatures{$sig_nospace}) {
- WARN("BAD_SIGN_OFF",
- "Duplicate signature\n" . $herecurr);
- } else {
- $signatures{$sig_nospace} = 1;
- }
- }
-
-# Check email subject for common tools that don't need to be mentioned
- if ($in_header_lines &&
- $line =~ /^Subject:.*\b(?:checkpatch|sparse|smatch)\b[^:]/i) {
- WARN("EMAIL_SUBJECT",
- "A patch subject line should describe the change not the tool that found it\n" . $herecurr);
- }
-
-# Check for old stable address
- if ($line =~ /^\s*cc:\s*.*<?\bstable\@kernel\.org\b>?.*$/i) {
- ERROR("STABLE_ADDRESS",
- "The 'stable' address should be 'stable\@vger.kernel.org'\n" . $herecurr);
- }
-
-# Check for unwanted Gerrit info
- if ($in_commit_log && $line =~ /^\s*change-id:/i) {
- ERROR("GERRIT_CHANGE_ID",
- "Remove Gerrit Change-Id's before submitting upstream.\n" . $herecurr);
- }
-
-# Check if the commit log is in a possible stack dump
- if ($in_commit_log && !$commit_log_possible_stack_dump &&
- ($line =~ /^\s*(?:WARNING:|BUG:)/ ||
- $line =~ /^\s*\[\s*\d+\.\d{6,6}\s*\]/ ||
- # timestamp
- $line =~ /^\s*\[\<[0-9a-fA-F]{8,}\>\]/)) {
- # stack dump address
- $commit_log_possible_stack_dump = 1;
- }
-
-# Check for line lengths > 75 in commit log, warn once
- if ($in_commit_log && !$commit_log_long_line &&
- length($line) > 75 &&
- !($line =~ /^\s*[a-zA-Z0-9_\/\.]+\s+\|\s+\d+/ ||
- # file delta changes
- $line =~ /^\s*(?:[\w\.\-]+\/)++[\w\.\-]+:/ ||
- # filename then :
- $line =~ /^\s*(?:Fixes:|Link:)/i ||
- # A Fixes: or Link: line
- $commit_log_possible_stack_dump)) {
- WARN("COMMIT_LOG_LONG_LINE",
- "Possible unwrapped commit description (prefer a maximum 75 chars per line)\n" . $herecurr);
- $commit_log_long_line = 1;
- }
-
-# Reset possible stack dump if a blank line is found
- if ($in_commit_log && $commit_log_possible_stack_dump &&
- $line =~ /^\s*$/) {
- $commit_log_possible_stack_dump = 0;
- }
-
-# Check for git id commit length and improperly formed commit descriptions
- if ($in_commit_log && !$commit_log_possible_stack_dump &&
- $line !~ /^\s*(?:Link|Patchwork|http|https|BugLink):/i &&
- $line !~ /^This reverts commit [0-9a-f]{7,40}/ &&
- ($line =~ /\bcommit\s+[0-9a-f]{5,}\b/i ||
- ($line =~ /(?:\s|^)[0-9a-f]{12,40}(?:[\s"'\(\[]|$)/i &&
- $line !~ /[\<\[][0-9a-f]{12,40}[\>\]]/i &&
- $line !~ /\bfixes:\s*[0-9a-f]{12,40}/i))) {
- my $init_char = "c";
- my $orig_commit = "";
- my $short = 1;
- my $long = 0;
- my $case = 1;
- my $space = 1;
- my $hasdesc = 0;
- my $hasparens = 0;
- my $id = '0123456789ab';
- my $orig_desc = "commit description";
- my $description = "";
-
- if ($line =~ /\b(c)ommit\s+([0-9a-f]{5,})\b/i) {
- $init_char = $1;
- $orig_commit = lc($2);
- } elsif ($line =~ /\b([0-9a-f]{12,40})\b/i) {
- $orig_commit = lc($1);
- }
-
- $short = 0 if ($line =~ /\bcommit\s+[0-9a-f]{12,40}/i);
- $long = 1 if ($line =~ /\bcommit\s+[0-9a-f]{41,}/i);
- $space = 0 if ($line =~ /\bcommit [0-9a-f]/i);
- $case = 0 if ($line =~ /\b[Cc]ommit\s+[0-9a-f]{5,40}[^A-F]/);
- if ($line =~ /\bcommit\s+[0-9a-f]{5,}\s+\("([^"]+)"\)/i) {
- $orig_desc = $1;
- $hasparens = 1;
- } elsif ($line =~ /\bcommit\s+[0-9a-f]{5,}\s*$/i &&
- defined $rawlines[$linenr] &&
- $rawlines[$linenr] =~ /^\s*\("([^"]+)"\)/) {
- $orig_desc = $1;
- $hasparens = 1;
- } elsif ($line =~ /\bcommit\s+[0-9a-f]{5,}\s+\("[^"]+$/i &&
- defined $rawlines[$linenr] &&
- $rawlines[$linenr] =~ /^\s*[^"]+"\)/) {
- $line =~ /\bcommit\s+[0-9a-f]{5,}\s+\("([^"]+)$/i;
- $orig_desc = $1;
- $rawlines[$linenr] =~ /^\s*([^"]+)"\)/;
- $orig_desc .= " " . $1;
- $hasparens = 1;
- }
-
- ($id, $description) = git_commit_info($orig_commit,
- $id, $orig_desc);
-
- if (defined($id) &&
- ($short || $long || $space || $case || ($orig_desc ne $description) || !$hasparens)) {
- ERROR("GIT_COMMIT_ID",
- "Please use git commit description style 'commit <12+ chars of sha1> (\"<title line>\")' - ie: '${init_char}ommit $id (\"$description\")'\n" . $herecurr);
- }
- }
-
-# Check for wrappage within a valid hunk of the file
- if ($realcnt != 0 && $line !~ m{^(?:\+|-| |\\ No newline|$)}) {
- ERROR("CORRUPTED_PATCH",
- "patch seems to be corrupt (line wrapped?)\n" .
- $herecurr) if (!$emitted_corrupt++);
- }
-
-# UTF-8 regex found at http://www.w3.org/International/questions/qa-forms-utf-8.en.php
- if (($realfile =~ /^$/ || $line =~ /^\+/) &&
- $rawline !~ m/^$UTF8*$/) {
- my ($utf8_prefix) = ($rawline =~ /^($UTF8*)/);
-
- my $blank = copy_spacing($rawline);
- my $ptr = substr($blank, 0, length($utf8_prefix)) . "^";
- my $hereptr = "$hereline$ptr\n";
-
- CHK("INVALID_UTF8",
- "Invalid UTF-8, patch and commit message should be encoded in UTF-8\n" . $hereptr);
- }
-
-# Check if it's the start of a commit log
-# (not a header line and we haven't seen the patch filename)
- if ($in_header_lines && $realfile =~ /^$/ &&
- !($rawline =~ /^\s+(?:\S|$)/ ||
- $rawline =~ /^(?:commit\b|from\b|[\w-]+:)/i)) {
- $in_header_lines = 0;
- $in_commit_log = 1;
- $has_commit_log = 1;
- }
-
-# Check if there is UTF-8 in a commit log when a mail header has explicitly
-# declined it, i.e defined some charset where it is missing.
- if ($in_header_lines &&
- $rawline =~ /^Content-Type:.+charset="(.+)".*$/ &&
- $1 !~ /utf-8/i) {
- $non_utf8_charset = 1;
- }
-
- if ($in_commit_log && $non_utf8_charset && $realfile =~ /^$/ &&
- $rawline =~ /$NON_ASCII_UTF8/) {
- WARN("UTF8_BEFORE_PATCH",
- "8-bit UTF-8 used in possible commit log\n" . $herecurr);
- }
-
-# Check for absolute kernel paths in commit message
- if ($tree && $in_commit_log) {
- while ($line =~ m{(?:^|\s)(/\S*)}g) {
- my $file = $1;
-
- if ($file =~ m{^(.*?)(?::\d+)+:?$} &&
- check_absolute_file($1, $herecurr)) {
- #
- } else {
- check_absolute_file($file, $herecurr);
- }
- }
- }
-
-# Check for various typo / spelling mistakes
- if (defined($misspellings) &&
- ($in_commit_log || $line =~ /^(?:\+|Subject:)/i)) {
- while ($rawline =~ /(?:^|[^a-z@])($misspellings)(?:\b|$|[^a-z@])/gi) {
- my $typo = $1;
- my $typo_fix = $spelling_fix{lc($typo)};
- $typo_fix = ucfirst($typo_fix) if ($typo =~ /^[A-Z]/);
- $typo_fix = uc($typo_fix) if ($typo =~ /^[A-Z]+$/);
- my $msg_level = \&WARN;
- $msg_level = \&CHK if ($file);
- if (&{$msg_level}("TYPO_SPELLING",
- "'$typo' may be misspelled - perhaps '$typo_fix'?\n" . $herecurr) &&
- $fix) {
- $fixed[$fixlinenr] =~ s/(^|[^A-Za-z@])($typo)($|[^A-Za-z@])/$1$typo_fix$3/;
- }
- }
- }
-
-# ignore non-hunk lines and lines being removed
- next if (!$hunk_line || $line =~ /^-/);
-
-#trailing whitespace
- if ($line =~ /^\+.*\015/) {
- my $herevet = "$here\n" . cat_vet($rawline) . "\n";
- if (ERROR("DOS_LINE_ENDINGS",
- "DOS line endings\n" . $herevet) &&
- $fix) {
- $fixed[$fixlinenr] =~ s/[\s\015]+$//;
- }
- } elsif ($rawline =~ /^\+.*\S\s+$/ || $rawline =~ /^\+\s+$/) {
- my $herevet = "$here\n" . cat_vet($rawline) . "\n";
- if (ERROR("TRAILING_WHITESPACE",
- "trailing whitespace\n" . $herevet) &&
- $fix) {
- $fixed[$fixlinenr] =~ s/\s+$//;
- }
-
- $rpt_cleaners = 1;
- }
-
-# Check for FSF mailing addresses.
- if ($rawline =~ /\bwrite to the Free/i ||
- $rawline =~ /\b675\s+Mass\s+Ave/i ||
- $rawline =~ /\b59\s+Temple\s+Pl/i ||
- $rawline =~ /\b51\s+Franklin\s+St/i) {
- my $herevet = "$here\n" . cat_vet($rawline) . "\n";
- my $msg_level = \&ERROR;
- $msg_level = \&CHK if ($file);
- &{$msg_level}("FSF_MAILING_ADDRESS",
- "Do not include the paragraph about writing to the Free Software Foundation's mailing address from the sample GPL notice. The FSF has changed addresses in the past, and may do so again. Linux already includes a copy of the GPL.\n" . $herevet)
- }
-
-# check for Kconfig help text having a real description
-# Only applies when adding the entry originally, after that we do not have
-# sufficient context to determine whether it is indeed long enough.
- if ($realfile =~ /Kconfig/ &&
- $line =~ /^\+\s*config\s+/) {
- my $length = 0;
- my $cnt = $realcnt;
- my $ln = $linenr + 1;
- my $f;
- my $is_start = 0;
- my $is_end = 0;
- for (; $cnt > 0 && defined $lines[$ln - 1]; $ln++) {
- $f = $lines[$ln - 1];
- $cnt-- if ($lines[$ln - 1] !~ /^-/);
- $is_end = $lines[$ln - 1] =~ /^\+/;
-
- next if ($f =~ /^-/);
- last if (!$file && $f =~ /^\@\@/);
-
- if ($lines[$ln - 1] =~ /^\+\s*(?:bool|tristate)\s*\"/) {
- $is_start = 1;
- } elsif ($lines[$ln - 1] =~ /^\+\s*(?:---)?help(?:---)?$/) {
- $length = -1;
- }
-
- $f =~ s/^.//;
- $f =~ s/#.*//;
- $f =~ s/^\s+//;
- next if ($f =~ /^$/);
- if ($f =~ /^\s*config\s/) {
- $is_end = 1;
- last;
- }
- $length++;
- }
- if ($is_start && $is_end && $length < $min_conf_desc_length) {
- WARN("CONFIG_DESCRIPTION",
- "please write a paragraph that describes the config symbol fully\n" . $herecurr);
- }
- #print "is_start<$is_start> is_end<$is_end> length<$length>\n";
- }
-
-# check for MAINTAINERS entries that don't have the right form
- if ($realfile =~ /^MAINTAINERS$/ &&
- $rawline =~ /^\+[A-Z]:/ &&
- $rawline !~ /^\+[A-Z]:\t\S/) {
- if (WARN("MAINTAINERS_STYLE",
- "MAINTAINERS entries use one tab after TYPE:\n" . $herecurr) &&
- $fix) {
- $fixed[$fixlinenr] =~ s/^(\+[A-Z]):\s*/$1:\t/;
- }
- }
-
-# discourage the use of boolean for type definition attributes of Kconfig options
- if ($realfile =~ /Kconfig/ &&
- $line =~ /^\+\s*\bboolean\b/) {
- WARN("CONFIG_TYPE_BOOLEAN",
- "Use of boolean is deprecated, please use bool instead.\n" . $herecurr);
- }
-
- if (($realfile =~ /Makefile.*/ || $realfile =~ /Kbuild.*/) &&
- ($line =~ /\+(EXTRA_[A-Z]+FLAGS).*/)) {
- my $flag = $1;
- my $replacement = {
- 'EXTRA_AFLAGS' => 'asflags-y',
- 'EXTRA_CFLAGS' => 'ccflags-y',
- 'EXTRA_CPPFLAGS' => 'cppflags-y',
- 'EXTRA_LDFLAGS' => 'ldflags-y',
- };
-
- WARN("DEPRECATED_VARIABLE",
- "Use of $flag is deprecated, please use \`$replacement->{$flag} instead.\n" . $herecurr) if ($replacement->{$flag});
- }
-
-# check for DT compatible documentation
- if (defined $root &&
- (($realfile =~ /\.dtsi?$/ && $line =~ /^\+\s*compatible\s*=\s*\"/) ||
- ($realfile =~ /\.[ch]$/ && $line =~ /^\+.*\.compatible\s*=\s*\"/))) {
-
- my @compats = $rawline =~ /\"([a-zA-Z0-9\-\,\.\+_]+)\"/g;
-
- my $dt_path = $root . "/Documentation/devicetree/bindings/";
- my $vp_file = $dt_path . "vendor-prefixes.txt";
-
- foreach my $compat (@compats) {
- my $compat2 = $compat;
- $compat2 =~ s/\,[a-zA-Z0-9]*\-/\,<\.\*>\-/;
- my $compat3 = $compat;
- $compat3 =~ s/\,([a-z]*)[0-9]*\-/\,$1<\.\*>\-/;
- `grep -Erq "$compat|$compat2|$compat3" $dt_path`;
- if ( $? >> 8 ) {
- WARN("UNDOCUMENTED_DT_STRING",
- "DT compatible string \"$compat\" appears un-documented -- check $dt_path\n" . $herecurr);
- }
-
- next if $compat !~ /^([a-zA-Z0-9\-]+)\,/;
- my $vendor = $1;
- `grep -Eq "^$vendor\\b" $vp_file`;
- if ( $? >> 8 ) {
- WARN("UNDOCUMENTED_DT_STRING",
- "DT compatible string vendor \"$vendor\" appears un-documented -- check $vp_file\n" . $herecurr);
- }
- }
- }
-
-# check we are in a valid source file if not then ignore this hunk
- next if ($realfile !~ /\.(h|c|s|S|sh|dtsi|dts)$/);
-
-# line length limit (with some exclusions)
-#
-# There are a few types of lines that may extend beyond $max_line_length:
-# logging functions like pr_info that end in a string
-# lines with a single string
-# #defines that are a single string
-#
-# There are 3 different line length message types:
-# LONG_LINE_COMMENT a comment starts before but extends beyond $max_line_length
-# LONG_LINE_STRING a string starts before but extends beyond $max_line_length
-# LONG_LINE all other lines longer than $max_line_length
-#
-# if LONG_LINE is ignored, the other 2 types are also ignored
-#
-
- if ($line =~ /^\+/ && $length > $max_line_length) {
- my $msg_type = "LONG_LINE";
-
- # Check the allowed long line types first
-
- # logging functions that end in a string that starts
- # before $max_line_length
- if ($line =~ /^\+\s*$logFunctions\s*\(\s*(?:(?:KERN_\S+\s*|[^"]*))?($String\s*(?:|,|\)\s*;)\s*)$/ &&
- length(expand_tabs(substr($line, 1, length($line) - length($1) - 1))) <= $max_line_length) {
- $msg_type = "";
-
- # lines with only strings (w/ possible termination)
- # #defines with only strings
- } elsif ($line =~ /^\+\s*$String\s*(?:\s*|,|\)\s*;)\s*$/ ||
- $line =~ /^\+\s*#\s*define\s+\w+\s+$String$/) {
- $msg_type = "";
-
- # More special cases
- } elsif ($line =~ /^\+.*\bEFI_GUID\s*\(/ ||
- $line =~ /^\+\s*(?:\w+)?\s*DEFINE_PER_CPU/) {
- $msg_type = "";
-
- # Otherwise set the alternate message types
-
- # a comment starts before $max_line_length
- } elsif ($line =~ /($;[\s$;]*)$/ &&
- length(expand_tabs(substr($line, 1, length($line) - length($1) - 1))) <= $max_line_length) {
- $msg_type = "LONG_LINE_COMMENT"
-
- # a quoted string starts before $max_line_length
- } elsif ($sline =~ /\s*($String(?:\s*(?:\\|,\s*|\)\s*;\s*))?)$/ &&
- length(expand_tabs(substr($line, 1, length($line) - length($1) - 1))) <= $max_line_length) {
- $msg_type = "LONG_LINE_STRING"
- }
-
- if ($msg_type ne "" &&
- (show_type("LONG_LINE") || show_type($msg_type))) {
- WARN($msg_type,
- "line over $max_line_length characters\n" . $herecurr);
- }
- }
-
-# check for adding lines without a newline.
- if ($line =~ /^\+/ && defined $lines[$linenr] && $lines[$linenr] =~ /^\\ No newline at end of file/) {
- WARN("MISSING_EOF_NEWLINE",
- "adding a line without newline at end of file\n" . $herecurr);
- }
-
-# Blackfin: use hi/lo macros
- if ($realfile =~ m@arch/blackfin/.*\.S$@) {
- if ($line =~ /\.[lL][[:space:]]*=.*&[[:space:]]*0x[fF][fF][fF][fF]/) {
- my $herevet = "$here\n" . cat_vet($line) . "\n";
- ERROR("LO_MACRO",
- "use the LO() macro, not (... & 0xFFFF)\n" . $herevet);
- }
- if ($line =~ /\.[hH][[:space:]]*=.*>>[[:space:]]*16/) {
- my $herevet = "$here\n" . cat_vet($line) . "\n";
- ERROR("HI_MACRO",
- "use the HI() macro, not (... >> 16)\n" . $herevet);
- }
- }
-
-# check we are in a valid source file C or perl if not then ignore this hunk
- next if ($realfile !~ /\.(h|c|pl|dtsi|dts)$/);
-
-# at the beginning of a line any tabs must come first and anything
-# more than 8 must use tabs.
- if ($rawline =~ /^\+\s* \t\s*\S/ ||
- $rawline =~ /^\+\s* \s*/) {
- my $herevet = "$here\n" . cat_vet($rawline) . "\n";
- $rpt_cleaners = 1;
- if (ERROR("CODE_INDENT",
- "code indent should use tabs where possible\n" . $herevet) &&
- $fix) {
- $fixed[$fixlinenr] =~ s/^\+([ \t]+)/"\+" . tabify($1)/e;
- }
- }
-
-# check for space before tabs.
- if ($rawline =~ /^\+/ && $rawline =~ / \t/) {
- my $herevet = "$here\n" . cat_vet($rawline) . "\n";
- if (WARN("SPACE_BEFORE_TAB",
- "please, no space before tabs\n" . $herevet) &&
- $fix) {
- while ($fixed[$fixlinenr] =~
- s/(^\+.*) {8,8}\t/$1\t\t/) {}
- while ($fixed[$fixlinenr] =~
- s/(^\+.*) +\t/$1\t/) {}
- }
- }
-
-# check for && or || at the start of a line
- if ($rawline =~ /^\+\s*(&&|\|\|)/) {
- CHK("LOGICAL_CONTINUATIONS",
- "Logical continuations should be on the previous line\n" . $hereprev);
- }
-
-# check indentation starts on a tab stop
- if ($^V && $^V ge 5.10.0 &&
- $sline =~ /^\+\t+( +)(?:$c90_Keywords\b|\{\s*$|\}\s*(?:else\b|while\b|\s*$))/) {
- my $indent = length($1);
- if ($indent % 8) {
- if (WARN("TABSTOP",
- "Statements should start on a tabstop\n" . $herecurr) &&
- $fix) {
- $fixed[$fixlinenr] =~ s@(^\+\t+) +@$1 . "\t" x ($indent/8)@e;
- }
- }
- }
-
-# check multi-line statement indentation matches previous line
- if ($^V && $^V ge 5.10.0 &&
- $prevline =~ /^\+([ \t]*)((?:$c90_Keywords(?:\s+if)\s*)|(?:$Declare\s*)?(?:$Ident|\(\s*\*\s*$Ident\s*\))\s*|(?:\*\s*)*$Lval\s*=\s*$Ident\s*)\(.*(\&\&|\|\||,)\s*$/) {
- $prevline =~ /^\+(\t*)(.*)$/;
- my $oldindent = $1;
- my $rest = $2;
-
- my $pos = pos_last_openparen($rest);
- if ($pos >= 0) {
- $line =~ /^(\+| )([ \t]*)/;
- my $newindent = $2;
-
- my $goodtabindent = $oldindent .
- "\t" x ($pos / 8) .
- " " x ($pos % 8);
- my $goodspaceindent = $oldindent . " " x $pos;
-
- if ($newindent ne $goodtabindent &&
- $newindent ne $goodspaceindent) {
-
- if (CHK("PARENTHESIS_ALIGNMENT",
- "Alignment should match open parenthesis\n" . $hereprev) &&
- $fix && $line =~ /^\+/) {
- $fixed[$fixlinenr] =~
- s/^\+[ \t]*/\+$goodtabindent/;
- }
- }
- }
- }
-
-# check for space after cast like "(int) foo" or "(struct foo) bar"
-# avoid checking a few false positives:
-# "sizeof(<type>)" or "__alignof__(<type>)"
-# function pointer declarations like "(*foo)(int) = bar;"
-# structure definitions like "(struct foo) { 0 };"
-# multiline macros that define functions
-# known attributes or the __attribute__ keyword
- if ($line =~ /^\+(.*)\(\s*$Type\s*\)([ \t]++)((?![={]|\\$|$Attribute|__attribute__))/ &&
- (!defined($1) || $1 !~ /\b(?:sizeof|__alignof__)\s*$/)) {
- if (CHK("SPACING",
- "No space is necessary after a cast\n" . $herecurr) &&
- $fix) {
- $fixed[$fixlinenr] =~
- s/(\(\s*$Type\s*\))[ \t]+/$1/;
- }
- }
-
-# Block comment styles
-# Networking with an initial /*
- if ($realfile =~ m@^(drivers/net/|net/)@ &&
- $prevrawline =~ /^\+[ \t]*\/\*[ \t]*$/ &&
- $rawline =~ /^\+[ \t]*\*/ &&
- $realline > 2) {
- WARN("NETWORKING_BLOCK_COMMENT_STYLE",
- "networking block comments don't use an empty /* line, use /* Comment...\n" . $hereprev);
- }
-
-# Block comments use * on subsequent lines
- if ($prevline =~ /$;[ \t]*$/ && #ends in comment
- $prevrawline =~ /^\+.*?\/\*/ && #starting /*
- $prevrawline !~ /\*\/[ \t]*$/ && #no trailing */
- $rawline =~ /^\+/ && #line is new
- $rawline !~ /^\+[ \t]*\*/) { #no leading *
- WARN("BLOCK_COMMENT_STYLE",
- "Block comments use * on subsequent lines\n" . $hereprev);
- }
-
-# Block comments use */ on trailing lines
- if ($rawline !~ m@^\+[ \t]*\*/[ \t]*$@ && #trailing */
- $rawline !~ m@^\+.*/\*.*\*/[ \t]*$@ && #inline /*...*/
- $rawline !~ m@^\+.*\*{2,}/[ \t]*$@ && #trailing **/
- $rawline =~ m@^\+[ \t]*.+\*\/[ \t]*$@) { #non blank */
- WARN("BLOCK_COMMENT_STYLE",
- "Block comments use a trailing */ on a separate line\n" . $herecurr);
- }
-
-# Block comment * alignment
- if ($prevline =~ /$;[ \t]*$/ && #ends in comment
- $line =~ /^\+[ \t]*$;/ && #leading comment
- $rawline =~ /^\+[ \t]*\*/ && #leading *
- (($prevrawline =~ /^\+.*?\/\*/ && #leading /*
- $prevrawline !~ /\*\/[ \t]*$/) || #no trailing */
- $prevrawline =~ /^\+[ \t]*\*/)) { #leading *
- my $oldindent;
- $prevrawline =~ m@^\+([ \t]*/?)\*@;
- if (defined($1)) {
- $oldindent = expand_tabs($1);
- } else {
- $prevrawline =~ m@^\+(.*/?)\*@;
- $oldindent = expand_tabs($1);
- }
- $rawline =~ m@^\+([ \t]*)\*@;
- my $newindent = $1;
- $newindent = expand_tabs($newindent);
- if (length($oldindent) ne length($newindent)) {
- WARN("BLOCK_COMMENT_STYLE",
- "Block comments should align the * on each line\n" . $hereprev);
- }
- }
-
-# check for missing blank lines after struct/union declarations
-# with exceptions for various attributes and macros
- if ($prevline =~ /^[\+ ]};?\s*$/ &&
- $line =~ /^\+/ &&
- !($line =~ /^\+\s*$/ ||
- $line =~ /^\+\s*EXPORT_SYMBOL/ ||
- $line =~ /^\+\s*MODULE_/i ||
- $line =~ /^\+\s*\#\s*(?:end|elif|else)/ ||
- $line =~ /^\+[a-z_]*init/ ||
- $line =~ /^\+\s*(?:static\s+)?[A-Z_]*ATTR/ ||
- $line =~ /^\+\s*DECLARE/ ||
- $line =~ /^\+\s*builtin_[\w_]*driver/ ||
- $line =~ /^\+\s*__setup/)) {
- if (CHK("LINE_SPACING",
- "Please use a blank line after function/struct/union/enum declarations\n" . $hereprev) &&
- $fix) {
- fix_insert_line($fixlinenr, "\+");
- }
- }
-
-# check for multiple consecutive blank lines
- if ($prevline =~ /^[\+ ]\s*$/ &&
- $line =~ /^\+\s*$/ &&
- $last_blank_line != ($linenr - 1)) {
- if (CHK("LINE_SPACING",
- "Please don't use multiple blank lines\n" . $hereprev) &&
- $fix) {
- fix_delete_line($fixlinenr, $rawline);
- }
-
- $last_blank_line = $linenr;
- }
-
-# check for missing blank lines after declarations
- if ($sline =~ /^\+\s+\S/ && #Not at char 1
- # actual declarations
- ($prevline =~ /^\+\s+$Declare\s*$Ident\s*[=,;:\[]/ ||
- # function pointer declarations
- $prevline =~ /^\+\s+$Declare\s*\(\s*\*\s*$Ident\s*\)\s*[=,;:\[\(]/ ||
- # foo bar; where foo is some local typedef or #define
- $prevline =~ /^\+\s+$Ident(?:\s+|\s*\*\s*)$Ident\s*[=,;\[]/ ||
- # known declaration macros
- $prevline =~ /^\+\s+$declaration_macros/) &&
- # for "else if" which can look like "$Ident $Ident"
- !($prevline =~ /^\+\s+$c90_Keywords\b/ ||
- # other possible extensions of declaration lines
- $prevline =~ /(?:$Compare|$Assignment|$Operators)\s*$/ ||
- # not starting a section or a macro "\" extended line
- $prevline =~ /(?:\{\s*|\\)$/) &&
- # looks like a declaration
- !($sline =~ /^\+\s+$Declare\s*$Ident\s*[=,;:\[]/ ||
- # function pointer declarations
- $sline =~ /^\+\s+$Declare\s*\(\s*\*\s*$Ident\s*\)\s*[=,;:\[\(]/ ||
- # foo bar; where foo is some local typedef or #define
- $sline =~ /^\+\s+$Ident(?:\s+|\s*\*\s*)$Ident\s*[=,;\[]/ ||
- # known declaration macros
- $sline =~ /^\+\s+$declaration_macros/ ||
- # start of struct or union or enum
- $sline =~ /^\+\s+(?:union|struct|enum|typedef)\b/ ||
- # start or end of block or continuation of declaration
- $sline =~ /^\+\s+(?:$|[\{\}\.\#\"\?\:\(\[])/ ||
- # bitfield continuation
- $sline =~ /^\+\s+$Ident\s*:\s*\d+\s*[,;]/ ||
- # other possible extensions of declaration lines
- $sline =~ /^\+\s+\(?\s*(?:$Compare|$Assignment|$Operators)/) &&
- # indentation of previous and current line are the same
- (($prevline =~ /\+(\s+)\S/) && $sline =~ /^\+$1\S/)) {
- if (WARN("LINE_SPACING",
- "Missing a blank line after declarations\n" . $hereprev) &&
- $fix) {
- fix_insert_line($fixlinenr, "\+");
- }
- }
-
-# check for spaces at the beginning of a line.
-# Exceptions:
-# 1) within comments
-# 2) indented preprocessor commands
-# 3) hanging labels
- if ($rawline =~ /^\+ / && $line !~ /^\+ *(?:$;|#|$Ident:)/) {
- my $herevet = "$here\n" . cat_vet($rawline) . "\n";
- if (WARN("LEADING_SPACE",
- "please, no spaces at the start of a line\n" . $herevet) &&
- $fix) {
- $fixed[$fixlinenr] =~ s/^\+([ \t]+)/"\+" . tabify($1)/e;
- }
- }
-
-# check we are in a valid C source file if not then ignore this hunk
- next if ($realfile !~ /\.(h|c)$/);
-
-# check for unusual line ending [ or (
- if ($line =~ /^\+.*([\[\(])\s*$/) {
- CHK("OPEN_ENDED_LINE",
- "Lines should not end with a '$1'\n" . $herecurr);
- }
-
-# check if this appears to be the start function declaration, save the name
- if ($sline =~ /^\+\{\s*$/ &&
- $prevline =~ /^\+(?:(?:(?:$Storage|$Inline)\s*)*\s*$Type\s*)?($Ident)\(/) {
- $context_function = $1;
- }
-
-# check if this appears to be the end of function declaration
- if ($sline =~ /^\+\}\s*$/) {
- undef $context_function;
- }
-
-# check indentation of any line with a bare else
-# (but not if it is a multiple line "if (foo) return bar; else return baz;")
-# if the previous line is a break or return and is indented 1 tab more...
- if ($sline =~ /^\+([\t]+)(?:}[ \t]*)?else(?:[ \t]*{)?\s*$/) {
- my $tabs = length($1) + 1;
- if ($prevline =~ /^\+\t{$tabs,$tabs}break\b/ ||
- ($prevline =~ /^\+\t{$tabs,$tabs}return\b/ &&
- defined $lines[$linenr] &&
- $lines[$linenr] !~ /^[ \+]\t{$tabs,$tabs}return/)) {
- WARN("UNNECESSARY_ELSE",
- "else is not generally useful after a break or return\n" . $hereprev);
- }
- }
-
-# check indentation of a line with a break;
-# if the previous line is a goto or return and is indented the same # of tabs
- if ($sline =~ /^\+([\t]+)break\s*;\s*$/) {
- my $tabs = $1;
- if ($prevline =~ /^\+$tabs(?:goto|return)\b/) {
- WARN("UNNECESSARY_BREAK",
- "break is not useful after a goto or return\n" . $hereprev);
- }
- }
-
-# check for RCS/CVS revision markers
- if ($rawline =~ /^\+.*\$(Revision|Log|Id)(?:\$|)/) {
- WARN("CVS_KEYWORD",
- "CVS style keyword markers, these will _not_ be updated\n". $herecurr);
- }
-
-# Blackfin: don't use __builtin_bfin_[cs]sync
- if ($line =~ /__builtin_bfin_csync/) {
- my $herevet = "$here\n" . cat_vet($line) . "\n";
- ERROR("CSYNC",
- "use the CSYNC() macro in asm/blackfin.h\n" . $herevet);
- }
- if ($line =~ /__builtin_bfin_ssync/) {
- my $herevet = "$here\n" . cat_vet($line) . "\n";
- ERROR("SSYNC",
- "use the SSYNC() macro in asm/blackfin.h\n" . $herevet);
- }
-
-# check for old HOTPLUG __dev<foo> section markings
- if ($line =~ /\b(__dev(init|exit)(data|const|))\b/) {
- WARN("HOTPLUG_SECTION",
- "Using $1 is unnecessary\n" . $herecurr);
- }
-
-# Check for potential 'bare' types
- my ($stat, $cond, $line_nr_next, $remain_next, $off_next,
- $realline_next);
-#print "LINE<$line>\n";
- if ($linenr > $suppress_statement &&
- $realcnt && $sline =~ /.\s*\S/) {
- ($stat, $cond, $line_nr_next, $remain_next, $off_next) =
- ctx_statement_block($linenr, $realcnt, 0);
- $stat =~ s/\n./\n /g;
- $cond =~ s/\n./\n /g;
-
-#print "linenr<$linenr> <$stat>\n";
- # If this statement has no statement boundaries within
- # it there is no point in retrying a statement scan
- # until we hit end of it.
- my $frag = $stat; $frag =~ s/;+\s*$//;
- if ($frag !~ /(?:{|;)/) {
-#print "skip<$line_nr_next>\n";
- $suppress_statement = $line_nr_next;
- }
-
- # Find the real next line.
- $realline_next = $line_nr_next;
- if (defined $realline_next &&
- (!defined $lines[$realline_next - 1] ||
- substr($lines[$realline_next - 1], $off_next) =~ /^\s*$/)) {
- $realline_next++;
- }
-
- my $s = $stat;
- $s =~ s/{.*$//s;
-
- # Ignore goto labels.
- if ($s =~ /$Ident:\*$/s) {
-
- # Ignore functions being called
- } elsif ($s =~ /^.\s*$Ident\s*\(/s) {
-
- } elsif ($s =~ /^.\s*else\b/s) {
-
- # declarations always start with types
- } elsif ($prev_values eq 'E' && $s =~ /^.\s*(?:$Storage\s+)?(?:$Inline\s+)?(?:const\s+)?((?:\s*$Ident)+?)\b(?:\s+$Sparse)?\s*\**\s*(?:$Ident|\(\*[^\)]*\))(?:\s*$Modifier)?\s*(?:;|=|,|\()/s) {
- my $type = $1;
- $type =~ s/\s+/ /g;
- possible($type, "A:" . $s);
-
- # definitions in global scope can only start with types
- } elsif ($s =~ /^.(?:$Storage\s+)?(?:$Inline\s+)?(?:const\s+)?($Ident)\b\s*(?!:)/s) {
- possible($1, "B:" . $s);
- }
-
- # any (foo ... *) is a pointer cast, and foo is a type
- while ($s =~ /\(($Ident)(?:\s+$Sparse)*[\s\*]+\s*\)/sg) {
- possible($1, "C:" . $s);
- }
-
- # Check for any sort of function declaration.
- # int foo(something bar, other baz);
- # void (*store_gdt)(x86_descr_ptr *);
- if ($prev_values eq 'E' && $s =~ /^(.(?:typedef\s*)?(?:(?:$Storage|$Inline)\s*)*\s*$Type\s*(?:\b$Ident|\(\*\s*$Ident\))\s*)\(/s) {
- my ($name_len) = length($1);
-
- my $ctx = $s;
- substr($ctx, 0, $name_len + 1, '');
- $ctx =~ s/\)[^\)]*$//;
-
- for my $arg (split(/\s*,\s*/, $ctx)) {
- if ($arg =~ /^(?:const\s+)?($Ident)(?:\s+$Sparse)*\s*\**\s*(:?\b$Ident)?$/s || $arg =~ /^($Ident)$/s) {
-
- possible($1, "D:" . $s);
- }
- }
- }
-
- }
-
-#
-# Checks which may be anchored in the context.
-#
-
-# Check for switch () and associated case and default
-# statements should be at the same indent.
- if ($line=~/\bswitch\s*\(.*\)/) {
- my $err = '';
- my $sep = '';
- my @ctx = ctx_block_outer($linenr, $realcnt);
- shift(@ctx);
- for my $ctx (@ctx) {
- my ($clen, $cindent) = line_stats($ctx);
- if ($ctx =~ /^\+\s*(case\s+|default:)/ &&
- $indent != $cindent) {
- $err .= "$sep$ctx\n";
- $sep = '';
- } else {
- $sep = "[...]\n";
- }
- }
- if ($err ne '') {
- ERROR("SWITCH_CASE_INDENT_LEVEL",
- "switch and case should be at the same indent\n$hereline$err");
- }
- }
-
-# if/while/etc brace do not go on next line, unless defining a do while loop,
-# or if that brace on the next line is for something else
- if ($line =~ /(.*)\b((?:if|while|for|switch|(?:[a-z_]+|)for_each[a-z_]+)\s*\(|do\b|else\b)/ && $line !~ /^.\s*\#/) {
- my $pre_ctx = "$1$2";
-
- my ($level, @ctx) = ctx_statement_level($linenr, $realcnt, 0);
-
- if ($line =~ /^\+\t{6,}/) {
- WARN("DEEP_INDENTATION",
- "Too many leading tabs - consider code refactoring\n" . $herecurr);
- }
-
- my $ctx_cnt = $realcnt - $#ctx - 1;
- my $ctx = join("\n", @ctx);
-
- my $ctx_ln = $linenr;
- my $ctx_skip = $realcnt;
-
- while ($ctx_skip > $ctx_cnt || ($ctx_skip == $ctx_cnt &&
- defined $lines[$ctx_ln - 1] &&
- $lines[$ctx_ln - 1] =~ /^-/)) {
- ##print "SKIP<$ctx_skip> CNT<$ctx_cnt>\n";
- $ctx_skip-- if (!defined $lines[$ctx_ln - 1] || $lines[$ctx_ln - 1] !~ /^-/);
- $ctx_ln++;
- }
-
- #print "realcnt<$realcnt> ctx_cnt<$ctx_cnt>\n";
- #print "pre<$pre_ctx>\nline<$line>\nctx<$ctx>\nnext<$lines[$ctx_ln - 1]>\n";
-
- if ($ctx !~ /{\s*/ && defined($lines[$ctx_ln - 1]) && $lines[$ctx_ln - 1] =~ /^\+\s*{/) {
- ERROR("OPEN_BRACE",
- "that open brace { should be on the previous line\n" .
- "$here\n$ctx\n$rawlines[$ctx_ln - 1]\n");
- }
- if ($level == 0 && $pre_ctx !~ /}\s*while\s*\($/ &&
- $ctx =~ /\)\s*\;\s*$/ &&
- defined $lines[$ctx_ln - 1])
- {
- my ($nlength, $nindent) = line_stats($lines[$ctx_ln - 1]);
- if ($nindent > $indent) {
- WARN("TRAILING_SEMICOLON",
- "trailing semicolon indicates no statements, indent implies otherwise\n" .
- "$here\n$ctx\n$rawlines[$ctx_ln - 1]\n");
- }
- }
- }
-
-# Check relative indent for conditionals and blocks.
- if ($line =~ /\b(?:(?:if|while|for|(?:[a-z_]+|)for_each[a-z_]+)\s*\(|(?:do|else)\b)/ && $line !~ /^.\s*#/ && $line !~ /\}\s*while\s*/) {
- ($stat, $cond, $line_nr_next, $remain_next, $off_next) =
- ctx_statement_block($linenr, $realcnt, 0)
- if (!defined $stat);
- my ($s, $c) = ($stat, $cond);
-
- substr($s, 0, length($c), '');
-
- # remove inline comments
- $s =~ s/$;/ /g;
- $c =~ s/$;/ /g;
-
- # Find out how long the conditional actually is.
- my @newlines = ($c =~ /\n/gs);
- my $cond_lines = 1 + $#newlines;
-
- # Make sure we remove the line prefixes as we have
- # none on the first line, and are going to readd them
- # where necessary.
- $s =~ s/\n./\n/gs;
- while ($s =~ /\n\s+\\\n/) {
- $cond_lines += $s =~ s/\n\s+\\\n/\n/g;
- }
-
- # We want to check the first line inside the block
- # starting at the end of the conditional, so remove:
- # 1) any blank line termination
- # 2) any opening brace { on end of the line
- # 3) any do (...) {
- my $continuation = 0;
- my $check = 0;
- $s =~ s/^.*\bdo\b//;
- $s =~ s/^\s*{//;
- if ($s =~ s/^\s*\\//) {
- $continuation = 1;
- }
- if ($s =~ s/^\s*?\n//) {
- $check = 1;
- $cond_lines++;
- }
-
- # Also ignore a loop construct at the end of a
- # preprocessor statement.
- if (($prevline =~ /^.\s*#\s*define\s/ ||
- $prevline =~ /\\\s*$/) && $continuation == 0) {
- $check = 0;
- }
-
- my $cond_ptr = -1;
- $continuation = 0;
- while ($cond_ptr != $cond_lines) {
- $cond_ptr = $cond_lines;
-
- # If we see an #else/#elif then the code
- # is not linear.
- if ($s =~ /^\s*\#\s*(?:else|elif)/) {
- $check = 0;
- }
-
- # Ignore:
- # 1) blank lines, they should be at 0,
- # 2) preprocessor lines, and
- # 3) labels.
- if ($continuation ||
- $s =~ /^\s*?\n/ ||
- $s =~ /^\s*#\s*?/ ||
- $s =~ /^\s*$Ident\s*:/) {
- $continuation = ($s =~ /^.*?\\\n/) ? 1 : 0;
- if ($s =~ s/^.*?\n//) {
- $cond_lines++;
- }
- }
- }
-
- my (undef, $sindent) = line_stats("+" . $s);
- my $stat_real = raw_line($linenr, $cond_lines);
-
- # Check if either of these lines are modified, else
- # this is not this patch's fault.
- if (!defined($stat_real) ||
- $stat !~ /^\+/ && $stat_real !~ /^\+/) {
- $check = 0;
- }
- if (defined($stat_real) && $cond_lines > 1) {
- $stat_real = "[...]\n$stat_real";
- }
-
- #print "line<$line> prevline<$prevline> indent<$indent> sindent<$sindent> check<$check> continuation<$continuation> s<$s> cond_lines<$cond_lines> stat_real<$stat_real> stat<$stat>\n";
-
- if ($check && $s ne '' &&
- (($sindent % 8) != 0 ||
- ($sindent < $indent) ||
- ($sindent == $indent &&
- ($s !~ /^\s*(?:\}|\{|else\b)/)) ||
- ($sindent > $indent + 8))) {
- WARN("SUSPECT_CODE_INDENT",
- "suspect code indent for conditional statements ($indent, $sindent)\n" . $herecurr . "$stat_real\n");
- }
- }
-
- # Track the 'values' across context and added lines.
- my $opline = $line; $opline =~ s/^./ /;
- my ($curr_values, $curr_vars) =
- annotate_values($opline . "\n", $prev_values);
- $curr_values = $prev_values . $curr_values;
- if ($dbg_values) {
- my $outline = $opline; $outline =~ s/\t/ /g;
- print "$linenr > .$outline\n";
- print "$linenr > $curr_values\n";
- print "$linenr > $curr_vars\n";
- }
- $prev_values = substr($curr_values, -1);
-
-#ignore lines not being added
- next if ($line =~ /^[^\+]/);
-
-# check for dereferences that span multiple lines
- if ($prevline =~ /^\+.*$Lval\s*(?:\.|->)\s*$/ &&
- $line =~ /^\+\s*(?!\#\s*(?!define\s+|if))\s*$Lval/) {
- $prevline =~ /($Lval\s*(?:\.|->))\s*$/;
- my $ref = $1;
- $line =~ /^.\s*($Lval)/;
- $ref .= $1;
- $ref =~ s/\s//g;
- WARN("MULTILINE_DEREFERENCE",
- "Avoid multiple line dereference - prefer '$ref'\n" . $hereprev);
- }
-
-# check for declarations of signed or unsigned without int
- while ($line =~ m{\b($Declare)\s*(?!char\b|short\b|int\b|long\b)\s*($Ident)?\s*[=,;\[\)\(]}g) {
- my $type = $1;
- my $var = $2;
- $var = "" if (!defined $var);
- if ($type =~ /^(?:(?:$Storage|$Inline|$Attribute)\s+)*((?:un)?signed)((?:\s*\*)*)\s*$/) {
- my $sign = $1;
- my $pointer = $2;
-
- $pointer = "" if (!defined $pointer);
-
- if (WARN("UNSPECIFIED_INT",
- "Prefer '" . trim($sign) . " int" . rtrim($pointer) . "' to bare use of '$sign" . rtrim($pointer) . "'\n" . $herecurr) &&
- $fix) {
- my $decl = trim($sign) . " int ";
- my $comp_pointer = $pointer;
- $comp_pointer =~ s/\s//g;
- $decl .= $comp_pointer;
- $decl = rtrim($decl) if ($var eq "");
- $fixed[$fixlinenr] =~ s@\b$sign\s*\Q$pointer\E\s*$var\b@$decl$var@;
- }
- }
- }
-
-# TEST: allow direct testing of the type matcher.
- if ($dbg_type) {
- if ($line =~ /^.\s*$Declare\s*$/) {
- ERROR("TEST_TYPE",
- "TEST: is type\n" . $herecurr);
- } elsif ($dbg_type > 1 && $line =~ /^.+($Declare)/) {
- ERROR("TEST_NOT_TYPE",
- "TEST: is not type ($1 is)\n". $herecurr);
- }
- next;
- }
-# TEST: allow direct testing of the attribute matcher.
- if ($dbg_attr) {
- if ($line =~ /^.\s*$Modifier\s*$/) {
- ERROR("TEST_ATTR",
- "TEST: is attr\n" . $herecurr);
- } elsif ($dbg_attr > 1 && $line =~ /^.+($Modifier)/) {
- ERROR("TEST_NOT_ATTR",
- "TEST: is not attr ($1 is)\n". $herecurr);
- }
- next;
- }
-
-# check for initialisation to aggregates open brace on the next line
- if ($line =~ /^.\s*{/ &&
- $prevline =~ /(?:^|[^=])=\s*$/) {
- if (ERROR("OPEN_BRACE",
- "that open brace { should be on the previous line\n" . $hereprev) &&
- $fix && $prevline =~ /^\+/ && $line =~ /^\+/) {
- fix_delete_line($fixlinenr - 1, $prevrawline);
- fix_delete_line($fixlinenr, $rawline);
- my $fixedline = $prevrawline;
- $fixedline =~ s/\s*=\s*$/ = {/;
- fix_insert_line($fixlinenr, $fixedline);
- $fixedline = $line;
- $fixedline =~ s/^(.\s*)\{\s*/$1/;
- fix_insert_line($fixlinenr, $fixedline);
- }
- }
-
-#
-# Checks which are anchored on the added line.
-#
-
-# check for malformed paths in #include statements (uses RAW line)
- if ($rawline =~ m{^.\s*\#\s*include\s+[<"](.*)[">]}) {
- my $path = $1;
- if ($path =~ m{//}) {
- ERROR("MALFORMED_INCLUDE",
- "malformed #include filename\n" . $herecurr);
- }
- if ($path =~ "^uapi/" && $realfile =~ m@\binclude/uapi/@) {
- ERROR("UAPI_INCLUDE",
- "No #include in ...include/uapi/... should use a uapi/ path prefix\n" . $herecurr);
- }
- }
-
-# no C99 // comments
- if ($line =~ m{//}) {
- if (ERROR("C99_COMMENTS",
- "do not use C99 // comments\n" . $herecurr) &&
- $fix) {
- my $line = $fixed[$fixlinenr];
- if ($line =~ /\/\/(.*)$/) {
- my $comment = trim($1);
- $fixed[$fixlinenr] =~ s@\/\/(.*)$@/\* $comment \*/@;
- }
- }
- }
- # Remove C99 comments.
- $line =~ s@//.*@@;
- $opline =~ s@//.*@@;
-
-# EXPORT_SYMBOL should immediately follow the thing it is exporting, consider
-# the whole statement.
-#print "APW <$lines[$realline_next - 1]>\n";
- if (defined $realline_next &&
- exists $lines[$realline_next - 1] &&
- !defined $suppress_export{$realline_next} &&
- ($lines[$realline_next - 1] =~ /EXPORT_SYMBOL.*\((.*)\)/ ||
- $lines[$realline_next - 1] =~ /EXPORT_UNUSED_SYMBOL.*\((.*)\)/)) {
- # Handle definitions which produce identifiers with
- # a prefix:
- # XXX(foo);
- # EXPORT_SYMBOL(something_foo);
- my $name = $1;
- if ($stat =~ /^(?:.\s*}\s*\n)?.([A-Z_]+)\s*\(\s*($Ident)/ &&
- $name =~ /^${Ident}_$2/) {
-#print "FOO C name<$name>\n";
- $suppress_export{$realline_next} = 1;
-
- } elsif ($stat !~ /(?:
- \n.}\s*$|
- ^.DEFINE_$Ident\(\Q$name\E\)|
- ^.DECLARE_$Ident\(\Q$name\E\)|
- ^.LIST_HEAD\(\Q$name\E\)|
- ^.(?:$Storage\s+)?$Type\s*\(\s*\*\s*\Q$name\E\s*\)\s*\(|
- \b\Q$name\E(?:\s+$Attribute)*\s*(?:;|=|\[|\()
- )/x) {
-#print "FOO A<$lines[$realline_next - 1]> stat<$stat> name<$name>\n";
- $suppress_export{$realline_next} = 2;
- } else {
- $suppress_export{$realline_next} = 1;
- }
- }
- if (!defined $suppress_export{$linenr} &&
- $prevline =~ /^.\s*$/ &&
- ($line =~ /EXPORT_SYMBOL.*\((.*)\)/ ||
- $line =~ /EXPORT_UNUSED_SYMBOL.*\((.*)\)/)) {
-#print "FOO B <$lines[$linenr - 1]>\n";
- $suppress_export{$linenr} = 2;
- }
- if (defined $suppress_export{$linenr} &&
- $suppress_export{$linenr} == 2) {
- WARN("EXPORT_SYMBOL",
- "EXPORT_SYMBOL(foo); should immediately follow its function/variable\n" . $herecurr);
- }
-
-# check for global initialisers.
- if ($line =~ /^\+$Type\s*$Ident(?:\s+$Modifier)*\s*=\s*($zero_initializer)\s*;/) {
- if (ERROR("GLOBAL_INITIALISERS",
- "do not initialise globals to $1\n" . $herecurr) &&
- $fix) {
- $fixed[$fixlinenr] =~ s/(^.$Type\s*$Ident(?:\s+$Modifier)*)\s*=\s*$zero_initializer\s*;/$1;/;
- }
- }
-# check for static initialisers.
- if ($line =~ /^\+.*\bstatic\s.*=\s*($zero_initializer)\s*;/) {
- if (ERROR("INITIALISED_STATIC",
- "do not initialise statics to $1\n" .
- $herecurr) &&
- $fix) {
- $fixed[$fixlinenr] =~ s/(\bstatic\s.*?)\s*=\s*$zero_initializer\s*;/$1;/;
- }
- }
-
-# check for misordered declarations of char/short/int/long with signed/unsigned
- while ($sline =~ m{(\b$TypeMisordered\b)}g) {
- my $tmp = trim($1);
- WARN("MISORDERED_TYPE",
- "type '$tmp' should be specified in [[un]signed] [short|int|long|long long] order\n" . $herecurr);
- }
-
-# check for static const char * arrays.
- if ($line =~ /\bstatic\s+const\s+char\s*\*\s*(\w+)\s*\[\s*\]\s*=\s*/) {
- WARN("STATIC_CONST_CHAR_ARRAY",
- "static const char * array should probably be static const char * const\n" .
- $herecurr);
- }
-
-# check for static char foo[] = "bar" declarations.
- if ($line =~ /\bstatic\s+char\s+(\w+)\s*\[\s*\]\s*=\s*"/) {
- WARN("STATIC_CONST_CHAR_ARRAY",
- "static char array declaration should probably be static const char\n" .
- $herecurr);
- }
-
-# check for const <foo> const where <foo> is not a pointer or array type
- if ($sline =~ /\bconst\s+($BasicType)\s+const\b/) {
- my $found = $1;
- if ($sline =~ /\bconst\s+\Q$found\E\s+const\b\s*\*/) {
- WARN("CONST_CONST",
- "'const $found const *' should probably be 'const $found * const'\n" . $herecurr);
- } elsif ($sline !~ /\bconst\s+\Q$found\E\s+const\s+\w+\s*\[/) {
- WARN("CONST_CONST",
- "'const $found const' should probably be 'const $found'\n" . $herecurr);
- }
- }
-
-# check for non-global char *foo[] = {"bar", ...} declarations.
- if ($line =~ /^.\s+(?:static\s+|const\s+)?char\s+\*\s*\w+\s*\[\s*\]\s*=\s*\{/) {
- WARN("STATIC_CONST_CHAR_ARRAY",
- "char * array declaration might be better as static const\n" .
- $herecurr);
- }
-
-# check for sizeof(foo)/sizeof(foo[0]) that could be ARRAY_SIZE(foo)
- if ($line =~ m@\bsizeof\s*\(\s*($Lval)\s*\)@) {
- my $array = $1;
- if ($line =~ m@\b(sizeof\s*\(\s*\Q$array\E\s*\)\s*/\s*sizeof\s*\(\s*\Q$array\E\s*\[\s*0\s*\]\s*\))@) {
- my $array_div = $1;
- if (WARN("ARRAY_SIZE",
- "Prefer ARRAY_SIZE($array)\n" . $herecurr) &&
- $fix) {
- $fixed[$fixlinenr] =~ s/\Q$array_div\E/ARRAY_SIZE($array)/;
- }
- }
- }
-
-# check for function declarations without arguments like "int foo()"
- if ($line =~ /(\b$Type\s+$Ident)\s*\(\s*\)/) {
- if (ERROR("FUNCTION_WITHOUT_ARGS",
- "Bad function definition - $1() should probably be $1(void)\n" . $herecurr) &&
- $fix) {
- $fixed[$fixlinenr] =~ s/(\b($Type)\s+($Ident))\s*\(\s*\)/$2 $3(void)/;
- }
- }
-
-# check for new typedefs, only function parameters and sparse annotations
-# make sense.
- if ($line =~ /\btypedef\s/ &&
- $line !~ /\btypedef\s+$Type\s*\(\s*\*?$Ident\s*\)\s*\(/ &&
- $line !~ /\btypedef\s+$Type\s+$Ident\s*\(/ &&
- $line !~ /\b$typeTypedefs\b/ &&
- $line !~ /\b__bitwise\b/) {
- WARN("NEW_TYPEDEFS",
- "do not add new typedefs\n" . $herecurr);
- }
-
-# * goes on variable not on type
- # (char*[ const])
- while ($line =~ m{(\($NonptrType(\s*(?:$Modifier\b\s*|\*\s*)+)\))}g) {
- #print "AA<$1>\n";
- my ($ident, $from, $to) = ($1, $2, $2);
-
- # Should start with a space.
- $to =~ s/^(\S)/ $1/;
- # Should not end with a space.
- $to =~ s/\s+$//;
- # '*'s should not have spaces between.
- while ($to =~ s/\*\s+\*/\*\*/) {
- }
-
-## print "1: from<$from> to<$to> ident<$ident>\n";
- if ($from ne $to) {
- if (ERROR("POINTER_LOCATION",
- "\"(foo$from)\" should be \"(foo$to)\"\n" . $herecurr) &&
- $fix) {
- my $sub_from = $ident;
- my $sub_to = $ident;
- $sub_to =~ s/\Q$from\E/$to/;
- $fixed[$fixlinenr] =~
- s@\Q$sub_from\E@$sub_to@;
- }
- }
- }
- while ($line =~ m{(\b$NonptrType(\s*(?:$Modifier\b\s*|\*\s*)+)($Ident))}g) {
- #print "BB<$1>\n";
- my ($match, $from, $to, $ident) = ($1, $2, $2, $3);
-
- # Should start with a space.
- $to =~ s/^(\S)/ $1/;
- # Should not end with a space.
- $to =~ s/\s+$//;
- # '*'s should not have spaces between.
- while ($to =~ s/\*\s+\*/\*\*/) {
- }
- # Modifiers should have spaces.
- $to =~ s/(\b$Modifier$)/$1 /;
-
-## print "2: from<$from> to<$to> ident<$ident>\n";
- if ($from ne $to && $ident !~ /^$Modifier$/) {
- if (ERROR("POINTER_LOCATION",
- "\"foo${from}bar\" should be \"foo${to}bar\"\n" . $herecurr) &&
- $fix) {
-
- my $sub_from = $match;
- my $sub_to = $match;
- $sub_to =~ s/\Q$from\E/$to/;
- $fixed[$fixlinenr] =~
- s@\Q$sub_from\E@$sub_to@;
- }
- }
- }
-
-# avoid BUG() or BUG_ON()
- if ($line =~ /\b(?:BUG|BUG_ON)\b/) {
- my $msg_level = \&WARN;
- $msg_level = \&CHK if ($file);
- &{$msg_level}("AVOID_BUG",
- "Avoid crashing the kernel - try using WARN_ON & recovery code rather than BUG() or BUG_ON()\n" . $herecurr);
- }
-
-# avoid LINUX_VERSION_CODE
- if ($line =~ /\bLINUX_VERSION_CODE\b/) {
- WARN("LINUX_VERSION_CODE",
- "LINUX_VERSION_CODE should be avoided, code should be for the version to which it is merged\n" . $herecurr);
- }
-
-# check for uses of printk_ratelimit
- if ($line =~ /\bprintk_ratelimit\s*\(/) {
- WARN("PRINTK_RATELIMITED",
- "Prefer printk_ratelimited or pr_<level>_ratelimited to printk_ratelimit\n" . $herecurr);
- }
-
-# printk should use KERN_* levels
- if ($line =~ /\bprintk\s*\(\s*(?!KERN_[A-Z]+\b)/) {
- WARN("PRINTK_WITHOUT_KERN_LEVEL",
- "printk() should include KERN_<LEVEL> facility level\n" . $herecurr);
- }
-
- if ($line =~ /\bprintk\s*\(\s*KERN_([A-Z]+)/) {
- my $orig = $1;
- my $level = lc($orig);
- $level = "warn" if ($level eq "warning");
- my $level2 = $level;
- $level2 = "dbg" if ($level eq "debug");
- WARN("PREFER_PR_LEVEL",
- "Prefer [subsystem eg: netdev]_$level2([subsystem]dev, ... then dev_$level2(dev, ... then pr_$level(... to printk(KERN_$orig ...\n" . $herecurr);
- }
-
- if ($line =~ /\bpr_warning\s*\(/) {
- if (WARN("PREFER_PR_LEVEL",
- "Prefer pr_warn(... to pr_warning(...\n" . $herecurr) &&
- $fix) {
- $fixed[$fixlinenr] =~
- s/\bpr_warning\b/pr_warn/;
- }
- }
-
- if ($line =~ /\bdev_printk\s*\(\s*KERN_([A-Z]+)/) {
- my $orig = $1;
- my $level = lc($orig);
- $level = "warn" if ($level eq "warning");
- $level = "dbg" if ($level eq "debug");
- WARN("PREFER_DEV_LEVEL",
- "Prefer dev_$level(... to dev_printk(KERN_$orig, ...\n" . $herecurr);
- }
-
-# ENOSYS means "bad syscall nr" and nothing else. This will have a small
-# number of false positives, but assembly files are not checked, so at
-# least the arch entry code will not trigger this warning.
- if ($line =~ /\bENOSYS\b/) {
- WARN("ENOSYS",
- "ENOSYS means 'invalid syscall nr' and nothing else\n" . $herecurr);
- }
-
-# function brace can't be on same line, except for #defines of do while,
-# or if closed on same line
- if (($line=~/$Type\s*$Ident\(.*\).*\s*{/) and
- !($line=~/\#\s*define.*do\s\{/) and !($line=~/}/)) {
- if (ERROR("OPEN_BRACE",
- "open brace '{' following function declarations go on the next line\n" . $herecurr) &&
- $fix) {
- fix_delete_line($fixlinenr, $rawline);
- my $fixed_line = $rawline;
- $fixed_line =~ /(^..*$Type\s*$Ident\(.*\)\s*){(.*)$/;
- my $line1 = $1;
- my $line2 = $2;
- fix_insert_line($fixlinenr, ltrim($line1));
- fix_insert_line($fixlinenr, "\+{");
- if ($line2 !~ /^\s*$/) {
- fix_insert_line($fixlinenr, "\+\t" . trim($line2));
- }
- }
- }
-
-# open braces for enum, union and struct go on the same line.
- if ($line =~ /^.\s*{/ &&
- $prevline =~ /^.\s*(?:typedef\s+)?(enum|union|struct)(?:\s+$Ident)?\s*$/) {
- if (ERROR("OPEN_BRACE",
- "open brace '{' following $1 go on the same line\n" . $hereprev) &&
- $fix && $prevline =~ /^\+/ && $line =~ /^\+/) {
- fix_delete_line($fixlinenr - 1, $prevrawline);
- fix_delete_line($fixlinenr, $rawline);
- my $fixedline = rtrim($prevrawline) . " {";
- fix_insert_line($fixlinenr, $fixedline);
- $fixedline = $rawline;
- $fixedline =~ s/^(.\s*)\{\s*/$1\t/;
- if ($fixedline !~ /^\+\s*$/) {
- fix_insert_line($fixlinenr, $fixedline);
- }
- }
- }
-
-# missing space after union, struct or enum definition
- if ($line =~ /^.\s*(?:typedef\s+)?(enum|union|struct)(?:\s+$Ident){1,2}[=\{]/) {
- if (WARN("SPACING",
- "missing space after $1 definition\n" . $herecurr) &&
- $fix) {
- $fixed[$fixlinenr] =~
- s/^(.\s*(?:typedef\s+)?(?:enum|union|struct)(?:\s+$Ident){1,2})([=\{])/$1 $2/;
- }
- }
-
-# Function pointer declarations
-# check spacing between type, funcptr, and args
-# canonical declaration is "type (*funcptr)(args...)"
- if ($line =~ /^.\s*($Declare)\((\s*)\*(\s*)($Ident)(\s*)\)(\s*)\(/) {
- my $declare = $1;
- my $pre_pointer_space = $2;
- my $post_pointer_space = $3;
- my $funcname = $4;
- my $post_funcname_space = $5;
- my $pre_args_space = $6;
-
-# the $Declare variable will capture all spaces after the type
-# so check it for a missing trailing missing space but pointer return types
-# don't need a space so don't warn for those.
- my $post_declare_space = "";
- if ($declare =~ /(\s+)$/) {
- $post_declare_space = $1;
- $declare = rtrim($declare);
- }
- if ($declare !~ /\*$/ && $post_declare_space =~ /^$/) {
- WARN("SPACING",
- "missing space after return type\n" . $herecurr);
- $post_declare_space = " ";
- }
-
-# unnecessary space "type (*funcptr)(args...)"
-# This test is not currently implemented because these declarations are
-# equivalent to
-# int foo(int bar, ...)
-# and this is form shouldn't/doesn't generate a checkpatch warning.
-#
-# elsif ($declare =~ /\s{2,}$/) {
-# WARN("SPACING",
-# "Multiple spaces after return type\n" . $herecurr);
-# }
-
-# unnecessary space "type ( *funcptr)(args...)"
- if (defined $pre_pointer_space &&
- $pre_pointer_space =~ /^\s/) {
- WARN("SPACING",
- "Unnecessary space after function pointer open parenthesis\n" . $herecurr);
- }
-
-# unnecessary space "type (* funcptr)(args...)"
- if (defined $post_pointer_space &&
- $post_pointer_space =~ /^\s/) {
- WARN("SPACING",
- "Unnecessary space before function pointer name\n" . $herecurr);
- }
-
-# unnecessary space "type (*funcptr )(args...)"
- if (defined $post_funcname_space &&
- $post_funcname_space =~ /^\s/) {
- WARN("SPACING",
- "Unnecessary space after function pointer name\n" . $herecurr);
- }
-
-# unnecessary space "type (*funcptr) (args...)"
- if (defined $pre_args_space &&
- $pre_args_space =~ /^\s/) {
- WARN("SPACING",
- "Unnecessary space before function pointer arguments\n" . $herecurr);
- }
-
- if (show_type("SPACING") && $fix) {
- $fixed[$fixlinenr] =~
- s/^(.\s*)$Declare\s*\(\s*\*\s*$Ident\s*\)\s*\(/$1 . $declare . $post_declare_space . '(*' . $funcname . ')('/ex;
- }
- }
-
-# check for spacing round square brackets; allowed:
-# 1. with a type on the left -- int [] a;
-# 2. at the beginning of a line for slice initialisers -- [0...10] = 5,
-# 3. inside a curly brace -- = { [0...10] = 5 }
- while ($line =~ /(.*?\s)\[/g) {
- my ($where, $prefix) = ($-[1], $1);
- if ($prefix !~ /$Type\s+$/ &&
- ($where != 0 || $prefix !~ /^.\s+$/) &&
- $prefix !~ /[{,]\s+$/) {
- if (ERROR("BRACKET_SPACE",
- "space prohibited before open square bracket '['\n" . $herecurr) &&
- $fix) {
- $fixed[$fixlinenr] =~
- s/^(\+.*?)\s+\[/$1\[/;
- }
- }
- }
-
-# check for spaces between functions and their parentheses.
- while ($line =~ /($Ident)\s+\(/g) {
- my $name = $1;
- my $ctx_before = substr($line, 0, $-[1]);
- my $ctx = "$ctx_before$name";
-
- # Ignore those directives where spaces _are_ permitted.
- if ($name =~ /^(?:
- if|for|while|switch|return|case|
- volatile|__volatile__|
- __attribute__|format|__extension__|
- asm|__asm__)$/x)
- {
- # cpp #define statements have non-optional spaces, ie
- # if there is a space between the name and the open
- # parenthesis it is simply not a parameter group.
- } elsif ($ctx_before =~ /^.\s*\#\s*define\s*$/) {
-
- # cpp #elif statement condition may start with a (
- } elsif ($ctx =~ /^.\s*\#\s*elif\s*$/) {
-
- # If this whole things ends with a type its most
- # likely a typedef for a function.
- } elsif ($ctx =~ /$Type$/) {
-
- } else {
- if (WARN("SPACING",
- "space prohibited between function name and open parenthesis '('\n" . $herecurr) &&
- $fix) {
- $fixed[$fixlinenr] =~
- s/\b$name\s+\(/$name\(/;
- }
- }
- }
-
-# Check operator spacing.
- if (!($line=~/\#\s*include/)) {
- my $fixed_line = "";
- my $line_fixed = 0;
-
- my $ops = qr{
- <<=|>>=|<=|>=|==|!=|
- \+=|-=|\*=|\/=|%=|\^=|\|=|&=|
- =>|->|<<|>>|<|>|=|!|~|
- &&|\|\||,|\^|\+\+|--|&|\||\+|-|\*|\/|%|
- \?:|\?|:
- }x;
- my @elements = split(/($ops|;)/, $opline);
-
-## print("element count: <" . $#elements . ">\n");
-## foreach my $el (@elements) {
-## print("el: <$el>\n");
-## }
-
- my @fix_elements = ();
- my $off = 0;
-
- foreach my $el (@elements) {
- push(@fix_elements, substr($rawline, $off, length($el)));
- $off += length($el);
- }
-
- $off = 0;
-
- my $blank = copy_spacing($opline);
- my $last_after = -1;
-
- for (my $n = 0; $n < $#elements; $n += 2) {
-
- my $good = $fix_elements[$n] . $fix_elements[$n + 1];
-
-## print("n: <$n> good: <$good>\n");
-
- $off += length($elements[$n]);
-
- # Pick up the preceding and succeeding characters.
- my $ca = substr($opline, 0, $off);
- my $cc = '';
- if (length($opline) >= ($off + length($elements[$n + 1]))) {
- $cc = substr($opline, $off + length($elements[$n + 1]));
- }
- my $cb = "$ca$;$cc";
-
- my $a = '';
- $a = 'V' if ($elements[$n] ne '');
- $a = 'W' if ($elements[$n] =~ /\s$/);
- $a = 'C' if ($elements[$n] =~ /$;$/);
- $a = 'B' if ($elements[$n] =~ /(\[|\()$/);
- $a = 'O' if ($elements[$n] eq '');
- $a = 'E' if ($ca =~ /^\s*$/);
-
- my $op = $elements[$n + 1];
-
- my $c = '';
- if (defined $elements[$n + 2]) {
- $c = 'V' if ($elements[$n + 2] ne '');
- $c = 'W' if ($elements[$n + 2] =~ /^\s/);
- $c = 'C' if ($elements[$n + 2] =~ /^$;/);
- $c = 'B' if ($elements[$n + 2] =~ /^(\)|\]|;)/);
- $c = 'O' if ($elements[$n + 2] eq '');
- $c = 'E' if ($elements[$n + 2] =~ /^\s*\\$/);
- } else {
- $c = 'E';
- }
-
- my $ctx = "${a}x${c}";
-
- my $at = "(ctx:$ctx)";
-
- my $ptr = substr($blank, 0, $off) . "^";
- my $hereptr = "$hereline$ptr\n";
-
- # Pull out the value of this operator.
- my $op_type = substr($curr_values, $off + 1, 1);
-
- # Get the full operator variant.
- my $opv = $op . substr($curr_vars, $off, 1);
-
- # Ignore operators passed as parameters.
- if ($op_type ne 'V' &&
- $ca =~ /\s$/ && $cc =~ /^\s*[,\)]/) {
-
-# # Ignore comments
-# } elsif ($op =~ /^$;+$/) {
-
- # ; should have either the end of line or a space or \ after it
- } elsif ($op eq ';') {
- if ($ctx !~ /.x[WEBC]/ &&
- $cc !~ /^\\/ && $cc !~ /^;/) {
- if (ERROR("SPACING",
- "space required after that '$op' $at\n" . $hereptr)) {
- $good = $fix_elements[$n] . trim($fix_elements[$n + 1]) . " ";
- $line_fixed = 1;
- }
- }
-
- # // is a comment
- } elsif ($op eq '//') {
-
- # : when part of a bitfield
- } elsif ($opv eq ':B') {
- # skip the bitfield test for now
-
- # No spaces for:
- # ->
- } elsif ($op eq '->') {
- if ($ctx =~ /Wx.|.xW/) {
- if (ERROR("SPACING",
- "spaces prohibited around that '$op' $at\n" . $hereptr)) {
- $good = rtrim($fix_elements[$n]) . trim($fix_elements[$n + 1]);
- if (defined $fix_elements[$n + 2]) {
- $fix_elements[$n + 2] =~ s/^\s+//;
- }
- $line_fixed = 1;
- }
- }
-
- # , must not have a space before and must have a space on the right.
- } elsif ($op eq ',') {
- my $rtrim_before = 0;
- my $space_after = 0;
- if ($ctx =~ /Wx./) {
- if (ERROR("SPACING",
- "space prohibited before that '$op' $at\n" . $hereptr)) {
- $line_fixed = 1;
- $rtrim_before = 1;
- }
- }
- if ($ctx !~ /.x[WEC]/ && $cc !~ /^}/) {
- if (ERROR("SPACING",
- "space required after that '$op' $at\n" . $hereptr)) {
- $line_fixed = 1;
- $last_after = $n;
- $space_after = 1;
- }
- }
- if ($rtrim_before || $space_after) {
- if ($rtrim_before) {
- $good = rtrim($fix_elements[$n]) . trim($fix_elements[$n + 1]);
- } else {
- $good = $fix_elements[$n] . trim($fix_elements[$n + 1]);
- }
- if ($space_after) {
- $good .= " ";
- }
- }
-
- # '*' as part of a type definition -- reported already.
- } elsif ($opv eq '*_') {
- #warn "'*' is part of type\n";
-
- # unary operators should have a space before and
- # none after. May be left adjacent to another
- # unary operator, or a cast
- } elsif ($op eq '!' || $op eq '~' ||
- $opv eq '*U' || $opv eq '-U' ||
- $opv eq '&U' || $opv eq '&&U') {
- if ($ctx !~ /[WEBC]x./ && $ca !~ /(?:\)|!|~|\*|-|\&|\||\+\+|\-\-|\{)$/) {
- if (ERROR("SPACING",
- "space required before that '$op' $at\n" . $hereptr)) {
- if ($n != $last_after + 2) {
- $good = $fix_elements[$n] . " " . ltrim($fix_elements[$n + 1]);
- $line_fixed = 1;
- }
- }
- }
- if ($op eq '*' && $cc =~/\s*$Modifier\b/) {
- # A unary '*' may be const
-
- } elsif ($ctx =~ /.xW/) {
- if (ERROR("SPACING",
- "space prohibited after that '$op' $at\n" . $hereptr)) {
- $good = $fix_elements[$n] . rtrim($fix_elements[$n + 1]);
- if (defined $fix_elements[$n + 2]) {
- $fix_elements[$n + 2] =~ s/^\s+//;
- }
- $line_fixed = 1;
- }
- }
-
- # unary ++ and unary -- are allowed no space on one side.
- } elsif ($op eq '++' or $op eq '--') {
- if ($ctx !~ /[WEOBC]x[^W]/ && $ctx !~ /[^W]x[WOBEC]/) {
- if (ERROR("SPACING",
- "space required one side of that '$op' $at\n" . $hereptr)) {
- $good = $fix_elements[$n] . trim($fix_elements[$n + 1]) . " ";
- $line_fixed = 1;
- }
- }
- if ($ctx =~ /Wx[BE]/ ||
- ($ctx =~ /Wx./ && $cc =~ /^;/)) {
- if (ERROR("SPACING",
- "space prohibited before that '$op' $at\n" . $hereptr)) {
- $good = rtrim($fix_elements[$n]) . trim($fix_elements[$n + 1]);
- $line_fixed = 1;
- }
- }
- if ($ctx =~ /ExW/) {
- if (ERROR("SPACING",
- "space prohibited after that '$op' $at\n" . $hereptr)) {
- $good = $fix_elements[$n] . trim($fix_elements[$n + 1]);
- if (defined $fix_elements[$n + 2]) {
- $fix_elements[$n + 2] =~ s/^\s+//;
- }
- $line_fixed = 1;
- }
- }
-
- # << and >> may either have or not have spaces both sides
- } elsif ($op eq '<<' or $op eq '>>' or
- $op eq '&' or $op eq '^' or $op eq '|' or
- $op eq '+' or $op eq '-' or
- $op eq '*' or $op eq '/' or
- $op eq '%')
- {
- if ($check) {
- if (defined $fix_elements[$n + 2] && $ctx !~ /[EW]x[EW]/) {
- if (CHK("SPACING",
- "spaces preferred around that '$op' $at\n" . $hereptr)) {
- $good = rtrim($fix_elements[$n]) . " " . trim($fix_elements[$n + 1]) . " ";
- $fix_elements[$n + 2] =~ s/^\s+//;
- $line_fixed = 1;
- }
- } elsif (!defined $fix_elements[$n + 2] && $ctx !~ /Wx[OE]/) {
- if (CHK("SPACING",
- "space preferred before that '$op' $at\n" . $hereptr)) {
- $good = rtrim($fix_elements[$n]) . " " . trim($fix_elements[$n + 1]);
- $line_fixed = 1;
- }
- }
- } elsif ($ctx =~ /Wx[^WCE]|[^WCE]xW/) {
- if (ERROR("SPACING",
- "need consistent spacing around '$op' $at\n" . $hereptr)) {
- $good = rtrim($fix_elements[$n]) . " " . trim($fix_elements[$n + 1]) . " ";
- if (defined $fix_elements[$n + 2]) {
- $fix_elements[$n + 2] =~ s/^\s+//;
- }
- $line_fixed = 1;
- }
- }
-
- # A colon needs no spaces before when it is
- # terminating a case value or a label.
- } elsif ($opv eq ':C' || $opv eq ':L') {
- if ($ctx =~ /Wx./) {
- if (ERROR("SPACING",
- "space prohibited before that '$op' $at\n" . $hereptr)) {
- $good = rtrim($fix_elements[$n]) . trim($fix_elements[$n + 1]);
- $line_fixed = 1;
- }
- }
-
- # All the others need spaces both sides.
- } elsif ($ctx !~ /[EWC]x[CWE]/) {
- my $ok = 0;
-
- # Ignore email addresses <foo@bar>
- if (($op eq '<' &&
- $cc =~ /^\S+\@\S+>/) ||
- ($op eq '>' &&
- $ca =~ /<\S+\@\S+$/))
- {
- $ok = 1;
- }
-
- # for asm volatile statements
- # ignore a colon with another
- # colon immediately before or after
- if (($op eq ':') &&
- ($ca =~ /:$/ || $cc =~ /^:/)) {
- $ok = 1;
- }
-
- # messages are ERROR, but ?: are CHK
- if ($ok == 0) {
- my $msg_level = \&ERROR;
- $msg_level = \&CHK if (($op eq '?:' || $op eq '?' || $op eq ':') && $ctx =~ /VxV/);
-
- if (&{$msg_level}("SPACING",
- "spaces required around that '$op' $at\n" . $hereptr)) {
- $good = rtrim($fix_elements[$n]) . " " . trim($fix_elements[$n + 1]) . " ";
- if (defined $fix_elements[$n + 2]) {
- $fix_elements[$n + 2] =~ s/^\s+//;
- }
- $line_fixed = 1;
- }
- }
- }
- $off += length($elements[$n + 1]);
-
-## print("n: <$n> GOOD: <$good>\n");
-
- $fixed_line = $fixed_line . $good;
- }
-
- if (($#elements % 2) == 0) {
- $fixed_line = $fixed_line . $fix_elements[$#elements];
- }
-
- if ($fix && $line_fixed && $fixed_line ne $fixed[$fixlinenr]) {
- $fixed[$fixlinenr] = $fixed_line;
- }
-
-
- }
-
-# check for whitespace before a non-naked semicolon
- if ($line =~ /^\+.*\S\s+;\s*$/) {
- if (WARN("SPACING",
- "space prohibited before semicolon\n" . $herecurr) &&
- $fix) {
- 1 while $fixed[$fixlinenr] =~
- s/^(\+.*\S)\s+;/$1;/;
- }
- }
-
-# check for multiple assignments
- if ($line =~ /^.\s*$Lval\s*=\s*$Lval\s*=(?!=)/) {
- CHK("MULTIPLE_ASSIGNMENTS",
- "multiple assignments should be avoided\n" . $herecurr);
- }
-
-## # check for multiple declarations, allowing for a function declaration
-## # continuation.
-## if ($line =~ /^.\s*$Type\s+$Ident(?:\s*=[^,{]*)?\s*,\s*$Ident.*/ &&
-## $line !~ /^.\s*$Type\s+$Ident(?:\s*=[^,{]*)?\s*,\s*$Type\s*$Ident.*/) {
-##
-## # Remove any bracketed sections to ensure we do not
-## # falsly report the parameters of functions.
-## my $ln = $line;
-## while ($ln =~ s/\([^\(\)]*\)//g) {
-## }
-## if ($ln =~ /,/) {
-## WARN("MULTIPLE_DECLARATION",
-## "declaring multiple variables together should be avoided\n" . $herecurr);
-## }
-## }
-
-#need space before brace following if, while, etc
- if (($line =~ /\(.*\)\{/ && $line !~ /\($Type\)\{/) ||
- $line =~ /do\{/) {
- if (ERROR("SPACING",
- "space required before the open brace '{'\n" . $herecurr) &&
- $fix) {
- $fixed[$fixlinenr] =~ s/^(\+.*(?:do|\)))\{/$1 {/;
- }
- }
-
-## # check for blank lines before declarations
-## if ($line =~ /^.\t+$Type\s+$Ident(?:\s*=.*)?;/ &&
-## $prevrawline =~ /^.\s*$/) {
-## WARN("SPACING",
-## "No blank lines before declarations\n" . $hereprev);
-## }
-##
-
-# closing brace should have a space following it when it has anything
-# on the line
- if ($line =~ /}(?!(?:,|;|\)))\S/) {
- if (ERROR("SPACING",
- "space required after that close brace '}'\n" . $herecurr) &&
- $fix) {
- $fixed[$fixlinenr] =~
- s/}((?!(?:,|;|\)))\S)/} $1/;
- }
- }
-
-# check spacing on square brackets
- if ($line =~ /\[\s/ && $line !~ /\[\s*$/) {
- if (ERROR("SPACING",
- "space prohibited after that open square bracket '['\n" . $herecurr) &&
- $fix) {
- $fixed[$fixlinenr] =~
- s/\[\s+/\[/;
- }
- }
- if ($line =~ /\s\]/) {
- if (ERROR("SPACING",
- "space prohibited before that close square bracket ']'\n" . $herecurr) &&
- $fix) {
- $fixed[$fixlinenr] =~
- s/\s+\]/\]/;
- }
- }
-
-# check spacing on parentheses
- if ($line =~ /\(\s/ && $line !~ /\(\s*(?:\\)?$/ &&
- $line !~ /for\s*\(\s+;/) {
- if (ERROR("SPACING",
- "space prohibited after that open parenthesis '('\n" . $herecurr) &&
- $fix) {
- $fixed[$fixlinenr] =~
- s/\(\s+/\(/;
- }
- }
- if ($line =~ /(\s+)\)/ && $line !~ /^.\s*\)/ &&
- $line !~ /for\s*\(.*;\s+\)/ &&
- $line !~ /:\s+\)/) {
- if (ERROR("SPACING",
- "space prohibited before that close parenthesis ')'\n" . $herecurr) &&
- $fix) {
- $fixed[$fixlinenr] =~
- s/\s+\)/\)/;
- }
- }
-
-# check unnecessary parentheses around addressof/dereference single $Lvals
-# ie: &(foo->bar) should be &foo->bar and *(foo->bar) should be *foo->bar
-
- while ($line =~ /(?:[^&]&\s*|\*)\(\s*($Ident\s*(?:$Member\s*)+)\s*\)/g) {
- my $var = $1;
- if (CHK("UNNECESSARY_PARENTHESES",
- "Unnecessary parentheses around $var\n" . $herecurr) &&
- $fix) {
- $fixed[$fixlinenr] =~ s/\(\s*\Q$var\E\s*\)/$var/;
- }
- }
-
-# check for unnecessary parentheses around function pointer uses
-# ie: (foo->bar)(); should be foo->bar();
-# but not "if (foo->bar) (" to avoid some false positives
- if ($line =~ /(\bif\s*|)(\(\s*$Ident\s*(?:$Member\s*)+\))[ \t]*\(/ && $1 !~ /^if/) {
- my $var = $2;
- if (CHK("UNNECESSARY_PARENTHESES",
- "Unnecessary parentheses around function pointer $var\n" . $herecurr) &&
- $fix) {
- my $var2 = deparenthesize($var);
- $var2 =~ s/\s//g;
- $fixed[$fixlinenr] =~ s/\Q$var\E/$var2/;
- }
- }
-
-# check for unnecessary parentheses around comparisons in if uses
- if ($^V && $^V ge 5.10.0 && defined($stat) &&
- $stat =~ /(^.\s*if\s*($balanced_parens))/) {
- my $if_stat = $1;
- my $test = substr($2, 1, -1);
- my $herectx;
- while ($test =~ /(?:^|[^\w\&\!\~])+\s*\(\s*([\&\!\~]?\s*$Lval\s*(?:$Compare\s*$FuncArg)?)\s*\)/g) {
- my $match = $1;
- # avoid parentheses around potential macro args
- next if ($match =~ /^\s*\w+\s*$/);
- if (!defined($herectx)) {
- $herectx = $here . "\n";
- my $cnt = statement_rawlines($if_stat);
- for (my $n = 0; $n < $cnt; $n++) {
- my $rl = raw_line($linenr, $n);
- $herectx .= $rl . "\n";
- last if $rl =~ /^[ \+].*\{/;
- }
- }
- CHK("UNNECESSARY_PARENTHESES",
- "Unnecessary parentheses around '$match'\n" . $herectx);
- }
- }
-
-#goto labels aren't indented, allow a single space however
- if ($line=~/^.\s+[A-Za-z\d_]+:(?![0-9]+)/ and
- !($line=~/^. [A-Za-z\d_]+:/) and !($line=~/^.\s+default:/)) {
- if (WARN("INDENTED_LABEL",
- "labels should not be indented\n" . $herecurr) &&
- $fix) {
- $fixed[$fixlinenr] =~
- s/^(.)\s+/$1/;
- }
- }
-
-# return is not a function
- if (defined($stat) && $stat =~ /^.\s*return(\s*)\(/s) {
- my $spacing = $1;
- if ($^V && $^V ge 5.10.0 &&
- $stat =~ /^.\s*return\s*($balanced_parens)\s*;\s*$/) {
- my $value = $1;
- $value = deparenthesize($value);
- if ($value =~ m/^\s*$FuncArg\s*(?:\?|$)/) {
- ERROR("RETURN_PARENTHESES",
- "return is not a function, parentheses are not required\n" . $herecurr);
- }
- } elsif ($spacing !~ /\s+/) {
- ERROR("SPACING",
- "space required before the open parenthesis '('\n" . $herecurr);
- }
- }
-
-# unnecessary return in a void function
-# at end-of-function, with the previous line a single leading tab, then return;
-# and the line before that not a goto label target like "out:"
- if ($sline =~ /^[ \+]}\s*$/ &&
- $prevline =~ /^\+\treturn\s*;\s*$/ &&
- $linenr >= 3 &&
- $lines[$linenr - 3] =~ /^[ +]/ &&
- $lines[$linenr - 3] !~ /^[ +]\s*$Ident\s*:/) {
- WARN("RETURN_VOID",
- "void function return statements are not generally useful\n" . $hereprev);
- }
-
-# if statements using unnecessary parentheses - ie: if ((foo == bar))
- if ($^V && $^V ge 5.10.0 &&
- $line =~ /\bif\s*((?:\(\s*){2,})/) {
- my $openparens = $1;
- my $count = $openparens =~ tr@\(@\(@;
- my $msg = "";
- if ($line =~ /\bif\s*(?:\(\s*){$count,$count}$LvalOrFunc\s*($Compare)\s*$LvalOrFunc(?:\s*\)){$count,$count}/) {
- my $comp = $4; #Not $1 because of $LvalOrFunc
- $msg = " - maybe == should be = ?" if ($comp eq "==");
- WARN("UNNECESSARY_PARENTHESES",
- "Unnecessary parentheses$msg\n" . $herecurr);
- }
- }
-
-# comparisons with a constant or upper case identifier on the left
-# avoid cases like "foo + BAR < baz"
-# only fix matches surrounded by parentheses to avoid incorrect
-# conversions like "FOO < baz() + 5" being "misfixed" to "baz() > FOO + 5"
- if ($^V && $^V ge 5.10.0 &&
- $line =~ /^\+(.*)\b($Constant|[A-Z_][A-Z0-9_]*)\s*($Compare)\s*($LvalOrFunc)/) {
- my $lead = $1;
- my $const = $2;
- my $comp = $3;
- my $to = $4;
- my $newcomp = $comp;
- if ($lead !~ /(?:$Operators|\.)\s*$/ &&
- $to !~ /^(?:Constant|[A-Z_][A-Z0-9_]*)$/ &&
- WARN("CONSTANT_COMPARISON",
- "Comparisons should place the constant on the right side of the test\n" . $herecurr) &&
- $fix) {
- if ($comp eq "<") {
- $newcomp = ">";
- } elsif ($comp eq "<=") {
- $newcomp = ">=";
- } elsif ($comp eq ">") {
- $newcomp = "<";
- } elsif ($comp eq ">=") {
- $newcomp = "<=";
- }
- $fixed[$fixlinenr] =~ s/\(\s*\Q$const\E\s*$Compare\s*\Q$to\E\s*\)/($to $newcomp $const)/;
- }
- }
-
-# Return of what appears to be an errno should normally be negative
- if ($sline =~ /\breturn(?:\s*\(+\s*|\s+)(E[A-Z]+)(?:\s*\)+\s*|\s*)[;:,]/) {
- my $name = $1;
- if ($name ne 'EOF' && $name ne 'ERROR') {
- WARN("USE_NEGATIVE_ERRNO",
- "return of an errno should typically be negative (ie: return -$1)\n" . $herecurr);
- }
- }
-
-# Need a space before open parenthesis after if, while etc
- if ($line =~ /\b(if|while|for|switch)\(/) {
- if (ERROR("SPACING",
- "space required before the open parenthesis '('\n" . $herecurr) &&
- $fix) {
- $fixed[$fixlinenr] =~
- s/\b(if|while|for|switch)\(/$1 \(/;
- }
- }
-
-# Check for illegal assignment in if conditional -- and check for trailing
-# statements after the conditional.
- if ($line =~ /do\s*(?!{)/) {
- ($stat, $cond, $line_nr_next, $remain_next, $off_next) =
- ctx_statement_block($linenr, $realcnt, 0)
- if (!defined $stat);
- my ($stat_next) = ctx_statement_block($line_nr_next,
- $remain_next, $off_next);
- $stat_next =~ s/\n./\n /g;
- ##print "stat<$stat> stat_next<$stat_next>\n";
-
- if ($stat_next =~ /^\s*while\b/) {
- # If the statement carries leading newlines,
- # then count those as offsets.
- my ($whitespace) =
- ($stat_next =~ /^((?:\s*\n[+-])*\s*)/s);
- my $offset =
- statement_rawlines($whitespace) - 1;
-
- $suppress_whiletrailers{$line_nr_next +
- $offset} = 1;
- }
- }
- if (!defined $suppress_whiletrailers{$linenr} &&
- defined($stat) && defined($cond) &&
- $line =~ /\b(?:if|while|for)\s*\(/ && $line !~ /^.\s*#/) {
- my ($s, $c) = ($stat, $cond);
-
- if ($c =~ /\bif\s*\(.*[^<>!=]=[^=].*/s) {
- ERROR("ASSIGN_IN_IF",
- "do not use assignment in if condition\n" . $herecurr);
- }
-
- # Find out what is on the end of the line after the
- # conditional.
- substr($s, 0, length($c), '');
- $s =~ s/\n.*//g;
- $s =~ s/$;//g; # Remove any comments
- if (length($c) && $s !~ /^\s*{?\s*\\*\s*$/ &&
- $c !~ /}\s*while\s*/)
- {
- # Find out how long the conditional actually is.
- my @newlines = ($c =~ /\n/gs);
- my $cond_lines = 1 + $#newlines;
- my $stat_real = '';
-
- $stat_real = raw_line($linenr, $cond_lines)
- . "\n" if ($cond_lines);
- if (defined($stat_real) && $cond_lines > 1) {
- $stat_real = "[...]\n$stat_real";
- }
-
- ERROR("TRAILING_STATEMENTS",
- "trailing statements should be on next line\n" . $herecurr . $stat_real);
- }
- }
-
-# Check for bitwise tests written as boolean
- if ($line =~ /
- (?:
- (?:\[|\(|\&\&|\|\|)
- \s*0[xX][0-9]+\s*
- (?:\&\&|\|\|)
- |
- (?:\&\&|\|\|)
- \s*0[xX][0-9]+\s*
- (?:\&\&|\|\||\)|\])
- )/x)
- {
- WARN("HEXADECIMAL_BOOLEAN_TEST",
- "boolean test with hexadecimal, perhaps just 1 \& or \|?\n" . $herecurr);
- }
-
-# if and else should not have general statements after it
- if ($line =~ /^.\s*(?:}\s*)?else\b(.*)/) {
- my $s = $1;
- $s =~ s/$;//g; # Remove any comments
- if ($s !~ /^\s*(?:\sif|(?:{|)\s*\\?\s*$)/) {
- ERROR("TRAILING_STATEMENTS",
- "trailing statements should be on next line\n" . $herecurr);
- }
- }
-# if should not continue a brace
- if ($line =~ /}\s*if\b/) {
- ERROR("TRAILING_STATEMENTS",
- "trailing statements should be on next line (or did you mean 'else if'?)\n" .
- $herecurr);
- }
-# case and default should not have general statements after them
- if ($line =~ /^.\s*(?:case\s*.*|default\s*):/g &&
- $line !~ /\G(?:
- (?:\s*$;*)(?:\s*{)?(?:\s*$;*)(?:\s*\\)?\s*$|
- \s*return\s+
- )/xg)
- {
- ERROR("TRAILING_STATEMENTS",
- "trailing statements should be on next line\n" . $herecurr);
- }
-
- # Check for }<nl>else {, these must be at the same
- # indent level to be relevant to each other.
- if ($prevline=~/}\s*$/ and $line=~/^.\s*else\s*/ &&
- $previndent == $indent) {
- if (ERROR("ELSE_AFTER_BRACE",
- "else should follow close brace '}'\n" . $hereprev) &&
- $fix && $prevline =~ /^\+/ && $line =~ /^\+/) {
- fix_delete_line($fixlinenr - 1, $prevrawline);
- fix_delete_line($fixlinenr, $rawline);
- my $fixedline = $prevrawline;
- $fixedline =~ s/}\s*$//;
- if ($fixedline !~ /^\+\s*$/) {
- fix_insert_line($fixlinenr, $fixedline);
- }
- $fixedline = $rawline;
- $fixedline =~ s/^(.\s*)else/$1} else/;
- fix_insert_line($fixlinenr, $fixedline);
- }
- }
-
- if ($prevline=~/}\s*$/ and $line=~/^.\s*while\s*/ &&
- $previndent == $indent) {
- my ($s, $c) = ctx_statement_block($linenr, $realcnt, 0);
-
- # Find out what is on the end of the line after the
- # conditional.
- substr($s, 0, length($c), '');
- $s =~ s/\n.*//g;
-
- if ($s =~ /^\s*;/) {
- if (ERROR("WHILE_AFTER_BRACE",
- "while should follow close brace '}'\n" . $hereprev) &&
- $fix && $prevline =~ /^\+/ && $line =~ /^\+/) {
- fix_delete_line($fixlinenr - 1, $prevrawline);
- fix_delete_line($fixlinenr, $rawline);
- my $fixedline = $prevrawline;
- my $trailing = $rawline;
- $trailing =~ s/^\+//;
- $trailing = trim($trailing);
- $fixedline =~ s/}\s*$/} $trailing/;
- fix_insert_line($fixlinenr, $fixedline);
- }
- }
- }
-
-#Specific variable tests
- while ($line =~ m{($Constant|$Lval)}g) {
- my $var = $1;
-
-#gcc binary extension
- if ($var =~ /^$Binary$/) {
- if (WARN("GCC_BINARY_CONSTANT",
- "Avoid gcc v4.3+ binary constant extension: <$var>\n" . $herecurr) &&
- $fix) {
- my $hexval = sprintf("0x%x", oct($var));
- $fixed[$fixlinenr] =~
- s/\b$var\b/$hexval/;
- }
- }
-
-#CamelCase
- if ($var !~ /^$Constant$/ &&
- $var =~ /[A-Z][a-z]|[a-z][A-Z]/ &&
-#Ignore Page<foo> variants
- $var !~ /^(?:Clear|Set|TestClear|TestSet|)Page[A-Z]/ &&
-#Ignore SI style variants like nS, mV and dB (ie: max_uV, regulator_min_uA_show)
- $var !~ /^(?:[a-z_]*?)_?[a-z][A-Z](?:_[a-z_]+)?$/ &&
-#Ignore some three character SI units explicitly, like MiB and KHz
- $var !~ /^(?:[a-z_]*?)_?(?:[KMGT]iB|[KMGT]?Hz)(?:_[a-z_]+)?$/) {
- while ($var =~ m{($Ident)}g) {
- my $word = $1;
- next if ($word !~ /[A-Z][a-z]|[a-z][A-Z]/);
- if ($check) {
- seed_camelcase_includes();
- if (!$file && !$camelcase_file_seeded) {
- seed_camelcase_file($realfile);
- $camelcase_file_seeded = 1;
- }
- }
- if (!defined $camelcase{$word}) {
- $camelcase{$word} = 1;
- CHK("CAMELCASE",
- "Avoid CamelCase: <$word>\n" . $herecurr);
- }
- }
- }
- }
-
-#no spaces allowed after \ in define
- if ($line =~ /\#\s*define.*\\\s+$/) {
- if (WARN("WHITESPACE_AFTER_LINE_CONTINUATION",
- "Whitespace after \\ makes next lines useless\n" . $herecurr) &&
- $fix) {
- $fixed[$fixlinenr] =~ s/\s+$//;
- }
- }
-
-# warn if <asm/foo.h> is #included and <linux/foo.h> is available and includes
-# itself <asm/foo.h> (uses RAW line)
- if ($tree && $rawline =~ m{^.\s*\#\s*include\s*\<asm\/(.*)\.h\>}) {
- my $file = "$1.h";
- my $checkfile = "include/linux/$file";
- if (-f "$root/$checkfile" &&
- $realfile ne $checkfile &&
- $1 !~ /$allowed_asm_includes/)
- {
- my $asminclude = `grep -Ec "#include\\s+<asm/$file>" $root/$checkfile`;
- if ($asminclude > 0) {
- if ($realfile =~ m{^arch/}) {
- CHK("ARCH_INCLUDE_LINUX",
- "Consider using #include <linux/$file> instead of <asm/$file>\n" . $herecurr);
- } else {
- WARN("INCLUDE_LINUX",
- "Use #include <linux/$file> instead of <asm/$file>\n" . $herecurr);
- }
- }
- }
- }
-
-# multi-statement macros should be enclosed in a do while loop, grab the
-# first statement and ensure its the whole macro if its not enclosed
-# in a known good container
- if ($realfile !~ m@/vmlinux.lds.h$@ &&
- $line =~ /^.\s*\#\s*define\s*$Ident(\()?/) {
- my $ln = $linenr;
- my $cnt = $realcnt;
- my ($off, $dstat, $dcond, $rest);
- my $ctx = '';
- my $has_flow_statement = 0;
- my $has_arg_concat = 0;
- ($dstat, $dcond, $ln, $cnt, $off) =
- ctx_statement_block($linenr, $realcnt, 0);
- $ctx = $dstat;
- #print "dstat<$dstat> dcond<$dcond> cnt<$cnt> off<$off>\n";
- #print "LINE<$lines[$ln-1]> len<" . length($lines[$ln-1]) . "\n";
-
- $has_flow_statement = 1 if ($ctx =~ /\b(goto|return)\b/);
- $has_arg_concat = 1 if ($ctx =~ /\#\#/ && $ctx !~ /\#\#\s*(?:__VA_ARGS__|args)\b/);
-
- $dstat =~ s/^.\s*\#\s*define\s+$Ident(\([^\)]*\))?\s*//;
- my $define_args = $1;
- my $define_stmt = $dstat;
- my @def_args = ();
-
- if (defined $define_args && $define_args ne "") {
- $define_args = substr($define_args, 1, length($define_args) - 2);
- $define_args =~ s/\s*//g;
- @def_args = split(",", $define_args);
- }
-
- $dstat =~ s/$;//g;
- $dstat =~ s/\\\n.//g;
- $dstat =~ s/^\s*//s;
- $dstat =~ s/\s*$//s;
-
- # Flatten any parentheses and braces
- while ($dstat =~ s/\([^\(\)]*\)/1/ ||
- $dstat =~ s/\{[^\{\}]*\}/1/ ||
- $dstat =~ s/.\[[^\[\]]*\]/1/)
- {
- }
-
- # Flatten any obvious string concatentation.
- while ($dstat =~ s/($String)\s*$Ident/$1/ ||
- $dstat =~ s/$Ident\s*($String)/$1/)
- {
- }
-
- # Make asm volatile uses seem like a generic function
- $dstat =~ s/\b_*asm_*\s+_*volatile_*\b/asm_volatile/g;
-
- my $exceptions = qr{
- $Declare|
- module_param_named|
- MODULE_PARM_DESC|
- DECLARE_PER_CPU|
- DEFINE_PER_CPU|
- __typeof__\(|
- union|
- struct|
- \.$Ident\s*=\s*|
- ^\"|\"$|
- ^\[
- }x;
- #print "REST<$rest> dstat<$dstat> ctx<$ctx>\n";
-
- $ctx =~ s/\n*$//;
- my $herectx = $here . "\n";
- my $stmt_cnt = statement_rawlines($ctx);
-
- for (my $n = 0; $n < $stmt_cnt; $n++) {
- $herectx .= raw_line($linenr, $n) . "\n";
- }
-
- if ($dstat ne '' &&
- $dstat !~ /^(?:$Ident|-?$Constant),$/ && # 10, // foo(),
- $dstat !~ /^(?:$Ident|-?$Constant);$/ && # foo();
- $dstat !~ /^[!~-]?(?:$Lval|$Constant)$/ && # 10 // foo() // !foo // ~foo // -foo // foo->bar // foo.bar->baz
- $dstat !~ /^'X'$/ && $dstat !~ /^'XX'$/ && # character constants
- $dstat !~ /$exceptions/ &&
- $dstat !~ /^\.$Ident\s*=/ && # .foo =
- $dstat !~ /^(?:\#\s*$Ident|\#\s*$Constant)\s*$/ && # stringification #foo
- $dstat !~ /^do\s*$Constant\s*while\s*$Constant;?$/ && # do {...} while (...); // do {...} while (...)
- $dstat !~ /^for\s*$Constant$/ && # for (...)
- $dstat !~ /^for\s*$Constant\s+(?:$Ident|-?$Constant)$/ && # for (...) bar()
- $dstat !~ /^do\s*{/ && # do {...
- $dstat !~ /^\(\{/ && # ({...
- $ctx !~ /^.\s*#\s*define\s+TRACE_(?:SYSTEM|INCLUDE_FILE|INCLUDE_PATH)\b/)
- {
- if ($dstat =~ /^\s*if\b/) {
- ERROR("MULTISTATEMENT_MACRO_USE_DO_WHILE",
- "Macros starting with if should be enclosed by a do - while loop to avoid possible if/else logic defects\n" . "$herectx");
- } elsif ($dstat =~ /;/) {
- ERROR("MULTISTATEMENT_MACRO_USE_DO_WHILE",
- "Macros with multiple statements should be enclosed in a do - while loop\n" . "$herectx");
- } else {
- ERROR("COMPLEX_MACRO",
- "Macros with complex values should be enclosed in parentheses\n" . "$herectx");
- }
-
- }
-
- # Make $define_stmt single line, comment-free, etc
- my @stmt_array = split('\n', $define_stmt);
- my $first = 1;
- $define_stmt = "";
- foreach my $l (@stmt_array) {
- $l =~ s/\\$//;
- if ($first) {
- $define_stmt = $l;
- $first = 0;
- } elsif ($l =~ /^[\+ ]/) {
- $define_stmt .= substr($l, 1);
- }
- }
- $define_stmt =~ s/$;//g;
- $define_stmt =~ s/\s+/ /g;
- $define_stmt = trim($define_stmt);
-
-# check if any macro arguments are reused (ignore '...' and 'type')
- foreach my $arg (@def_args) {
- next if ($arg =~ /\.\.\./);
- next if ($arg =~ /^type$/i);
- my $tmp_stmt = $define_stmt;
- $tmp_stmt =~ s/\b(typeof|__typeof__|__builtin\w+|typecheck\s*\(\s*$Type\s*,|\#+)\s*\(*\s*$arg\s*\)*\b//g;
- $tmp_stmt =~ s/\#+\s*$arg\b//g;
- $tmp_stmt =~ s/\b$arg\s*\#\#//g;
- my $use_cnt = $tmp_stmt =~ s/\b$arg\b//g;
- if ($use_cnt > 1) {
- CHK("MACRO_ARG_REUSE",
- "Macro argument reuse '$arg' - possible side-effects?\n" . "$herectx");
- }
-# check if any macro arguments may have other precedence issues
- if ($tmp_stmt =~ m/($Operators)?\s*\b$arg\b\s*($Operators)?/m &&
- ((defined($1) && $1 ne ',') ||
- (defined($2) && $2 ne ','))) {
- CHK("MACRO_ARG_PRECEDENCE",
- "Macro argument '$arg' may be better as '($arg)' to avoid precedence issues\n" . "$herectx");
- }
- }
-
-# check for macros with flow control, but without ## concatenation
-# ## concatenation is commonly a macro that defines a function so ignore those
- if ($has_flow_statement && !$has_arg_concat) {
- my $herectx = $here . "\n";
- my $cnt = statement_rawlines($ctx);
-
- for (my $n = 0; $n < $cnt; $n++) {
- $herectx .= raw_line($linenr, $n) . "\n";
- }
- WARN("MACRO_WITH_FLOW_CONTROL",
- "Macros with flow control statements should be avoided\n" . "$herectx");
- }
-
-# check for line continuations outside of #defines, preprocessor #, and asm
-
- } else {
- if ($prevline !~ /^..*\\$/ &&
- $line !~ /^\+\s*\#.*\\$/ && # preprocessor
- $line !~ /^\+.*\b(__asm__|asm)\b.*\\$/ && # asm
- $line =~ /^\+.*\\$/) {
- WARN("LINE_CONTINUATIONS",
- "Avoid unnecessary line continuations\n" . $herecurr);
- }
- }
-
-# do {} while (0) macro tests:
-# single-statement macros do not need to be enclosed in do while (0) loop,
-# macro should not end with a semicolon
- if ($^V && $^V ge 5.10.0 &&
- $realfile !~ m@/vmlinux.lds.h$@ &&
- $line =~ /^.\s*\#\s*define\s+$Ident(\()?/) {
- my $ln = $linenr;
- my $cnt = $realcnt;
- my ($off, $dstat, $dcond, $rest);
- my $ctx = '';
- ($dstat, $dcond, $ln, $cnt, $off) =
- ctx_statement_block($linenr, $realcnt, 0);
- $ctx = $dstat;
-
- $dstat =~ s/\\\n.//g;
- $dstat =~ s/$;/ /g;
-
- if ($dstat =~ /^\+\s*#\s*define\s+$Ident\s*${balanced_parens}\s*do\s*{(.*)\s*}\s*while\s*\(\s*0\s*\)\s*([;\s]*)\s*$/) {
- my $stmts = $2;
- my $semis = $3;
-
- $ctx =~ s/\n*$//;
- my $cnt = statement_rawlines($ctx);
- my $herectx = $here . "\n";
-
- for (my $n = 0; $n < $cnt; $n++) {
- $herectx .= raw_line($linenr, $n) . "\n";
- }
-
- if (($stmts =~ tr/;/;/) == 1 &&
- $stmts !~ /^\s*(if|while|for|switch)\b/) {
- WARN("SINGLE_STATEMENT_DO_WHILE_MACRO",
- "Single statement macros should not use a do {} while (0) loop\n" . "$herectx");
- }
- if (defined $semis && $semis ne "") {
- WARN("DO_WHILE_MACRO_WITH_TRAILING_SEMICOLON",
- "do {} while (0) macros should not be semicolon terminated\n" . "$herectx");
- }
- } elsif ($dstat =~ /^\+\s*#\s*define\s+$Ident.*;\s*$/) {
- $ctx =~ s/\n*$//;
- my $cnt = statement_rawlines($ctx);
- my $herectx = $here . "\n";
-
- for (my $n = 0; $n < $cnt; $n++) {
- $herectx .= raw_line($linenr, $n) . "\n";
- }
-
- WARN("TRAILING_SEMICOLON",
- "macros should not use a trailing semicolon\n" . "$herectx");
- }
- }
-
-# make sure symbols are always wrapped with VMLINUX_SYMBOL() ...
-# all assignments may have only one of the following with an assignment:
-# .
-# ALIGN(...)
-# VMLINUX_SYMBOL(...)
- if ($realfile eq 'vmlinux.lds.h' && $line =~ /(?:(?:^|\s)$Ident\s*=|=\s*$Ident(?:\s|$))/) {
- WARN("MISSING_VMLINUX_SYMBOL",
- "vmlinux.lds.h needs VMLINUX_SYMBOL() around C-visible symbols\n" . $herecurr);
- }
-
-# check for redundant bracing round if etc
- if ($line =~ /(^.*)\bif\b/ && $1 !~ /else\s*$/) {
- my ($level, $endln, @chunks) =
- ctx_statement_full($linenr, $realcnt, 1);
- #print "chunks<$#chunks> linenr<$linenr> endln<$endln> level<$level>\n";
- #print "APW: <<$chunks[1][0]>><<$chunks[1][1]>>\n";
- if ($#chunks > 0 && $level == 0) {
- my @allowed = ();
- my $allow = 0;
- my $seen = 0;
- my $herectx = $here . "\n";
- my $ln = $linenr - 1;
- for my $chunk (@chunks) {
- my ($cond, $block) = @{$chunk};
-
- # If the condition carries leading newlines, then count those as offsets.
- my ($whitespace) = ($cond =~ /^((?:\s*\n[+-])*\s*)/s);
- my $offset = statement_rawlines($whitespace) - 1;
-
- $allowed[$allow] = 0;
- #print "COND<$cond> whitespace<$whitespace> offset<$offset>\n";
-
- # We have looked at and allowed this specific line.
- $suppress_ifbraces{$ln + $offset} = 1;
-
- $herectx .= "$rawlines[$ln + $offset]\n[...]\n";
- $ln += statement_rawlines($block) - 1;
-
- substr($block, 0, length($cond), '');
-
- $seen++ if ($block =~ /^\s*{/);
-
- #print "cond<$cond> block<$block> allowed<$allowed[$allow]>\n";
- if (statement_lines($cond) > 1) {
- #print "APW: ALLOWED: cond<$cond>\n";
- $allowed[$allow] = 1;
- }
- if ($block =~/\b(?:if|for|while)\b/) {
- #print "APW: ALLOWED: block<$block>\n";
- $allowed[$allow] = 1;
- }
- if (statement_block_size($block) > 1) {
- #print "APW: ALLOWED: lines block<$block>\n";
- $allowed[$allow] = 1;
- }
- $allow++;
- }
- if ($seen) {
- my $sum_allowed = 0;
- foreach (@allowed) {
- $sum_allowed += $_;
- }
- if ($sum_allowed == 0) {
- WARN("BRACES",
- "braces {} are not necessary for any arm of this statement\n" . $herectx);
- } elsif ($sum_allowed != $allow &&
- $seen != $allow) {
- CHK("BRACES",
- "braces {} should be used on all arms of this statement\n" . $herectx);
- }
- }
- }
- }
- if (!defined $suppress_ifbraces{$linenr - 1} &&
- $line =~ /\b(if|while|for|else)\b/) {
- my $allowed = 0;
-
- # Check the pre-context.
- if (substr($line, 0, $-[0]) =~ /(\}\s*)$/) {
- #print "APW: ALLOWED: pre<$1>\n";
- $allowed = 1;
- }
-
- my ($level, $endln, @chunks) =
- ctx_statement_full($linenr, $realcnt, $-[0]);
-
- # Check the condition.
- my ($cond, $block) = @{$chunks[0]};
- #print "CHECKING<$linenr> cond<$cond> block<$block>\n";
- if (defined $cond) {
- substr($block, 0, length($cond), '');
- }
- if (statement_lines($cond) > 1) {
- #print "APW: ALLOWED: cond<$cond>\n";
- $allowed = 1;
- }
- if ($block =~/\b(?:if|for|while)\b/) {
- #print "APW: ALLOWED: block<$block>\n";
- $allowed = 1;
- }
- if (statement_block_size($block) > 1) {
- #print "APW: ALLOWED: lines block<$block>\n";
- $allowed = 1;
- }
- # Check the post-context.
- if (defined $chunks[1]) {
- my ($cond, $block) = @{$chunks[1]};
- if (defined $cond) {
- substr($block, 0, length($cond), '');
- }
- if ($block =~ /^\s*\{/) {
- #print "APW: ALLOWED: chunk-1 block<$block>\n";
- $allowed = 1;
- }
- }
- if ($level == 0 && $block =~ /^\s*\{/ && !$allowed) {
- my $herectx = $here . "\n";
- my $cnt = statement_rawlines($block);
-
- for (my $n = 0; $n < $cnt; $n++) {
- $herectx .= raw_line($linenr, $n) . "\n";
- }
-
- WARN("BRACES",
- "braces {} are not necessary for single statement blocks\n" . $herectx);
- }
- }
-
-# check for single line unbalanced braces
- if ($sline =~ /^.\s*\}\s*else\s*$/ ||
- $sline =~ /^.\s*else\s*\{\s*$/) {
- CHK("BRACES", "Unbalanced braces around else statement\n" . $herecurr);
- }
-
-# check for unnecessary blank lines around braces
- if (($line =~ /^.\s*}\s*$/ && $prevrawline =~ /^.\s*$/)) {
- if (CHK("BRACES",
- "Blank lines aren't necessary before a close brace '}'\n" . $hereprev) &&
- $fix && $prevrawline =~ /^\+/) {
- fix_delete_line($fixlinenr - 1, $prevrawline);
- }
- }
- if (($rawline =~ /^.\s*$/ && $prevline =~ /^..*{\s*$/)) {
- if (CHK("BRACES",
- "Blank lines aren't necessary after an open brace '{'\n" . $hereprev) &&
- $fix) {
- fix_delete_line($fixlinenr, $rawline);
- }
- }
-
-# no volatiles please
- my $asm_volatile = qr{\b(__asm__|asm)\s+(__volatile__|volatile)\b};
- if ($line =~ /\bvolatile\b/ && $line !~ /$asm_volatile/) {
- WARN("VOLATILE",
- "Use of volatile is usually wrong: see Documentation/process/volatile-considered-harmful.rst\n" . $herecurr);
- }
-
-# Check for user-visible strings broken across lines, which breaks the ability
-# to grep for the string. Make exceptions when the previous string ends in a
-# newline (multiple lines in one string constant) or '\t', '\r', ';', or '{'
-# (common in inline assembly) or is a octal \123 or hexadecimal \xaf value
- if ($line =~ /^\+\s*$String/ &&
- $prevline =~ /"\s*$/ &&
- $prevrawline !~ /(?:\\(?:[ntr]|[0-7]{1,3}|x[0-9a-fA-F]{1,2})|;\s*|\{\s*)"\s*$/) {
- if (WARN("SPLIT_STRING",
- "quoted string split across lines\n" . $hereprev) &&
- $fix &&
- $prevrawline =~ /^\+.*"\s*$/ &&
- $last_coalesced_string_linenr != $linenr - 1) {
- my $extracted_string = get_quoted_string($line, $rawline);
- my $comma_close = "";
- if ($rawline =~ /\Q$extracted_string\E(\s*\)\s*;\s*$|\s*,\s*)/) {
- $comma_close = $1;
- }
-
- fix_delete_line($fixlinenr - 1, $prevrawline);
- fix_delete_line($fixlinenr, $rawline);
- my $fixedline = $prevrawline;
- $fixedline =~ s/"\s*$//;
- $fixedline .= substr($extracted_string, 1) . trim($comma_close);
- fix_insert_line($fixlinenr - 1, $fixedline);
- $fixedline = $rawline;
- $fixedline =~ s/\Q$extracted_string\E\Q$comma_close\E//;
- if ($fixedline !~ /\+\s*$/) {
- fix_insert_line($fixlinenr, $fixedline);
- }
- $last_coalesced_string_linenr = $linenr;
- }
- }
-
-# check for missing a space in a string concatenation
- if ($prevrawline =~ /[^\\]\w"$/ && $rawline =~ /^\+[\t ]+"\w/) {
- WARN('MISSING_SPACE',
- "break quoted strings at a space character\n" . $hereprev);
- }
-
-# check for an embedded function name in a string when the function is known
-# This does not work very well for -f --file checking as it depends on patch
-# context providing the function name or a single line form for in-file
-# function declarations
- if ($line =~ /^\+.*$String/ &&
- defined($context_function) &&
- get_quoted_string($line, $rawline) =~ /\b$context_function\b/ &&
- length(get_quoted_string($line, $rawline)) != (length($context_function) + 2)) {
- WARN("EMBEDDED_FUNCTION_NAME",
- "Prefer using '\"%s...\", __func__' to using '$context_function', this function's name, in a string\n" . $herecurr);
- }
-
-# check for spaces before a quoted newline
- if ($rawline =~ /^.*\".*\s\\n/) {
- if (WARN("QUOTED_WHITESPACE_BEFORE_NEWLINE",
- "unnecessary whitespace before a quoted newline\n" . $herecurr) &&
- $fix) {
- $fixed[$fixlinenr] =~ s/^(\+.*\".*)\s+\\n/$1\\n/;
- }
-
- }
-
-# concatenated string without spaces between elements
- if ($line =~ /$String[A-Z_]/ || $line =~ /[A-Za-z0-9_]$String/) {
- CHK("CONCATENATED_STRING",
- "Concatenated strings should use spaces between elements\n" . $herecurr);
- }
-
-# uncoalesced string fragments
- if ($line =~ /$String\s*"/) {
- WARN("STRING_FRAGMENTS",
- "Consecutive strings are generally better as a single string\n" . $herecurr);
- }
-
-# check for non-standard and hex prefixed decimal printf formats
- my $show_L = 1; #don't show the same defect twice
- my $show_Z = 1;
- while ($line =~ /(?:^|")([X\t]*)(?:"|$)/g) {
- my $string = substr($rawline, $-[1], $+[1] - $-[1]);
- $string =~ s/%%/__/g;
- # check for %L
- if ($show_L && $string =~ /%[\*\d\.\$]*L([diouxX])/) {
- WARN("PRINTF_L",
- "\%L$1 is non-standard C, use %ll$1\n" . $herecurr);
- $show_L = 0;
- }
- # check for %Z
- if ($show_Z && $string =~ /%[\*\d\.\$]*Z([diouxX])/) {
- WARN("PRINTF_Z",
- "%Z$1 is non-standard C, use %z$1\n" . $herecurr);
- $show_Z = 0;
- }
- # check for 0x<decimal>
- if ($string =~ /0x%[\*\d\.\$\Llzth]*[diou]/) {
- ERROR("PRINTF_0XDECIMAL",
- "Prefixing 0x with decimal output is defective\n" . $herecurr);
- }
- }
-
-# check for line continuations in quoted strings with odd counts of "
- if ($rawline =~ /\\$/ && $rawline =~ tr/"/"/ % 2) {
- WARN("LINE_CONTINUATIONS",
- "Avoid line continuations in quoted strings\n" . $herecurr);
- }
-
-# warn about #if 0
- if ($line =~ /^.\s*\#\s*if\s+0\b/) {
- CHK("REDUNDANT_CODE",
- "if this code is redundant consider removing it\n" .
- $herecurr);
- }
-
-# check for needless "if (<foo>) fn(<foo>)" uses
- if ($prevline =~ /\bif\s*\(\s*($Lval)\s*\)/) {
- my $tested = quotemeta($1);
- my $expr = '\s*\(\s*' . $tested . '\s*\)\s*;';
- if ($line =~ /\b(kfree|usb_free_urb|debugfs_remove(?:_recursive)?|(?:kmem_cache|mempool|dma_pool)_destroy)$expr/) {
- my $func = $1;
- if (WARN('NEEDLESS_IF',
- "$func(NULL) is safe and this check is probably not required\n" . $hereprev) &&
- $fix) {
- my $do_fix = 1;
- my $leading_tabs = "";
- my $new_leading_tabs = "";
- if ($lines[$linenr - 2] =~ /^\+(\t*)if\s*\(\s*$tested\s*\)\s*$/) {
- $leading_tabs = $1;
- } else {
- $do_fix = 0;
- }
- if ($lines[$linenr - 1] =~ /^\+(\t+)$func\s*\(\s*$tested\s*\)\s*;\s*$/) {
- $new_leading_tabs = $1;
- if (length($leading_tabs) + 1 ne length($new_leading_tabs)) {
- $do_fix = 0;
- }
- } else {
- $do_fix = 0;
- }
- if ($do_fix) {
- fix_delete_line($fixlinenr - 1, $prevrawline);
- $fixed[$fixlinenr] =~ s/^\+$new_leading_tabs/\+$leading_tabs/;
- }
- }
- }
- }
-
-# check for unnecessary "Out of Memory" messages
- if ($line =~ /^\+.*\b$logFunctions\s*\(/ &&
- $prevline =~ /^[ \+]\s*if\s*\(\s*(\!\s*|NULL\s*==\s*)?($Lval)(\s*==\s*NULL\s*)?\s*\)/ &&
- (defined $1 || defined $3) &&
- $linenr > 3) {
- my $testval = $2;
- my $testline = $lines[$linenr - 3];
-
- my ($s, $c) = ctx_statement_block($linenr - 3, $realcnt, 0);
-# print("line: <$line>\nprevline: <$prevline>\ns: <$s>\nc: <$c>\n\n\n");
-
- if ($s =~ /(?:^|\n)[ \+]\s*(?:$Type\s*)?\Q$testval\E\s*=\s*(?:\([^\)]*\)\s*)?\s*(?:devm_)?(?:[kv][czm]alloc(?:_node|_array)?\b|kstrdup|kmemdup|(?:dev_)?alloc_skb)/) {
- WARN("OOM_MESSAGE",
- "Possible unnecessary 'out of memory' message\n" . $hereprev);
- }
- }
-
-# check for logging functions with KERN_<LEVEL>
- if ($line !~ /printk(?:_ratelimited|_once)?\s*\(/ &&
- $line =~ /\b$logFunctions\s*\(.*\b(KERN_[A-Z]+)\b/) {
- my $level = $1;
- if (WARN("UNNECESSARY_KERN_LEVEL",
- "Possible unnecessary $level\n" . $herecurr) &&
- $fix) {
- $fixed[$fixlinenr] =~ s/\s*$level\s*//;
- }
- }
-
-# check for logging continuations
- if ($line =~ /\bprintk\s*\(\s*KERN_CONT\b|\bpr_cont\s*\(/) {
- WARN("LOGGING_CONTINUATION",
- "Avoid logging continuation uses where feasible\n" . $herecurr);
- }
-
-# check for mask then right shift without a parentheses
- if ($^V && $^V ge 5.10.0 &&
- $line =~ /$LvalOrFunc\s*\&\s*($LvalOrFunc)\s*>>/ &&
- $4 !~ /^\&/) { # $LvalOrFunc may be &foo, ignore if so
- WARN("MASK_THEN_SHIFT",
- "Possible precedence defect with mask then right shift - may need parentheses\n" . $herecurr);
- }
-
-# check for pointer comparisons to NULL
- if ($^V && $^V ge 5.10.0) {
- while ($line =~ /\b$LvalOrFunc\s*(==|\!=)\s*NULL\b/g) {
- my $val = $1;
- my $equal = "!";
- $equal = "" if ($4 eq "!=");
- if (CHK("COMPARISON_TO_NULL",
- "Comparison to NULL could be written \"${equal}${val}\"\n" . $herecurr) &&
- $fix) {
- $fixed[$fixlinenr] =~ s/\b\Q$val\E\s*(?:==|\!=)\s*NULL\b/$equal$val/;
- }
- }
- }
-
-# check for bad placement of section $InitAttribute (e.g.: __initdata)
- if ($line =~ /(\b$InitAttribute\b)/) {
- my $attr = $1;
- if ($line =~ /^\+\s*static\s+(?:const\s+)?(?:$attr\s+)?($NonptrTypeWithAttr)\s+(?:$attr\s+)?($Ident(?:\[[^]]*\])?)\s*[=;]/) {
- my $ptr = $1;
- my $var = $2;
- if ((($ptr =~ /\b(union|struct)\s+$attr\b/ &&
- ERROR("MISPLACED_INIT",
- "$attr should be placed after $var\n" . $herecurr)) ||
- ($ptr !~ /\b(union|struct)\s+$attr\b/ &&
- WARN("MISPLACED_INIT",
- "$attr should be placed after $var\n" . $herecurr))) &&
- $fix) {
- $fixed[$fixlinenr] =~ s/(\bstatic\s+(?:const\s+)?)(?:$attr\s+)?($NonptrTypeWithAttr)\s+(?:$attr\s+)?($Ident(?:\[[^]]*\])?)\s*([=;])\s*/"$1" . trim(string_find_replace($2, "\\s*$attr\\s*", " ")) . " " . trim(string_find_replace($3, "\\s*$attr\\s*", "")) . " $attr" . ("$4" eq ";" ? ";" : " = ")/e;
- }
- }
- }
-
-# check for $InitAttributeData (ie: __initdata) with const
- if ($line =~ /\bconst\b/ && $line =~ /($InitAttributeData)/) {
- my $attr = $1;
- $attr =~ /($InitAttributePrefix)(.*)/;
- my $attr_prefix = $1;
- my $attr_type = $2;
- if (ERROR("INIT_ATTRIBUTE",
- "Use of const init definition must use ${attr_prefix}initconst\n" . $herecurr) &&
- $fix) {
- $fixed[$fixlinenr] =~
- s/$InitAttributeData/${attr_prefix}initconst/;
- }
- }
-
-# check for $InitAttributeConst (ie: __initconst) without const
- if ($line !~ /\bconst\b/ && $line =~ /($InitAttributeConst)/) {
- my $attr = $1;
- if (ERROR("INIT_ATTRIBUTE",
- "Use of $attr requires a separate use of const\n" . $herecurr) &&
- $fix) {
- my $lead = $fixed[$fixlinenr] =~
- /(^\+\s*(?:static\s+))/;
- $lead = rtrim($1);
- $lead = "$lead " if ($lead !~ /^\+$/);
- $lead = "${lead}const ";
- $fixed[$fixlinenr] =~ s/(^\+\s*(?:static\s+))/$lead/;
- }
- }
-
-# check for __read_mostly with const non-pointer (should just be const)
- if ($line =~ /\b__read_mostly\b/ &&
- $line =~ /($Type)\s*$Ident/ && $1 !~ /\*\s*$/ && $1 =~ /\bconst\b/) {
- if (ERROR("CONST_READ_MOSTLY",
- "Invalid use of __read_mostly with const type\n" . $herecurr) &&
- $fix) {
- $fixed[$fixlinenr] =~ s/\s+__read_mostly\b//;
- }
- }
-
-# don't use __constant_<foo> functions outside of include/uapi/
- if ($realfile !~ m@^include/uapi/@ &&
- $line =~ /(__constant_(?:htons|ntohs|[bl]e(?:16|32|64)_to_cpu|cpu_to_[bl]e(?:16|32|64)))\s*\(/) {
- my $constant_func = $1;
- my $func = $constant_func;
- $func =~ s/^__constant_//;
- if (WARN("CONSTANT_CONVERSION",
- "$constant_func should be $func\n" . $herecurr) &&
- $fix) {
- $fixed[$fixlinenr] =~ s/\b$constant_func\b/$func/g;
- }
- }
-
-# prefer usleep_range over udelay
- if ($line =~ /\budelay\s*\(\s*(\d+)\s*\)/) {
- my $delay = $1;
- # ignore udelay's < 10, however
- if (! ($delay < 10) ) {
- CHK("USLEEP_RANGE",
- "usleep_range is preferred over udelay; see Documentation/timers/timers-howto.txt\n" . $herecurr);
- }
- if ($delay > 2000) {
- WARN("LONG_UDELAY",
- "long udelay - prefer mdelay; see arch/arm/include/asm/delay.h\n" . $herecurr);
- }
- }
-
-# warn about unexpectedly long msleep's
- if ($line =~ /\bmsleep\s*\((\d+)\);/) {
- if ($1 < 20) {
- WARN("MSLEEP",
- "msleep < 20ms can sleep for up to 20ms; see Documentation/timers/timers-howto.txt\n" . $herecurr);
- }
- }
-
-# check for comparisons of jiffies
- if ($line =~ /\bjiffies\s*$Compare|$Compare\s*jiffies\b/) {
- WARN("JIFFIES_COMPARISON",
- "Comparing jiffies is almost always wrong; prefer time_after, time_before and friends\n" . $herecurr);
- }
-
-# check for comparisons of get_jiffies_64()
- if ($line =~ /\bget_jiffies_64\s*\(\s*\)\s*$Compare|$Compare\s*get_jiffies_64\s*\(\s*\)/) {
- WARN("JIFFIES_COMPARISON",
- "Comparing get_jiffies_64() is almost always wrong; prefer time_after64, time_before64 and friends\n" . $herecurr);
- }
-
-# warn about #ifdefs in C files
-# if ($line =~ /^.\s*\#\s*if(|n)def/ && ($realfile =~ /\.c$/)) {
-# print "#ifdef in C files should be avoided\n";
-# print "$herecurr";
-# $clean = 0;
-# }
-
-# warn about spacing in #ifdefs
- if ($line =~ /^.\s*\#\s*(ifdef|ifndef|elif)\s\s+/) {
- if (ERROR("SPACING",
- "exactly one space required after that #$1\n" . $herecurr) &&
- $fix) {
- $fixed[$fixlinenr] =~
- s/^(.\s*\#\s*(ifdef|ifndef|elif))\s{2,}/$1 /;
- }
-
- }
-
-# check for spinlock_t definitions without a comment.
- if ($line =~ /^.\s*(struct\s+mutex|spinlock_t)\s+\S+;/ ||
- $line =~ /^.\s*(DEFINE_MUTEX)\s*\(/) {
- my $which = $1;
- if (!ctx_has_comment($first_line, $linenr)) {
- CHK("UNCOMMENTED_DEFINITION",
- "$1 definition without comment\n" . $herecurr);
- }
- }
-# check for memory barriers without a comment.
-
- my $barriers = qr{
- mb|
- rmb|
- wmb|
- read_barrier_depends
- }x;
- my $barrier_stems = qr{
- mb__before_atomic|
- mb__after_atomic|
- store_release|
- load_acquire|
- store_mb|
- (?:$barriers)
- }x;
- my $all_barriers = qr{
- (?:$barriers)|
- smp_(?:$barrier_stems)|
- virt_(?:$barrier_stems)
- }x;
-
- if ($line =~ /\b(?:$all_barriers)\s*\(/) {
- if (!ctx_has_comment($first_line, $linenr)) {
- WARN("MEMORY_BARRIER",
- "memory barrier without comment\n" . $herecurr);
- }
- }
-
- my $underscore_smp_barriers = qr{__smp_(?:$barrier_stems)}x;
-
- if ($realfile !~ m@^include/asm-generic/@ &&
- $realfile !~ m@/barrier\.h$@ &&
- $line =~ m/\b(?:$underscore_smp_barriers)\s*\(/ &&
- $line !~ m/^.\s*\#\s*define\s+(?:$underscore_smp_barriers)\s*\(/) {
- WARN("MEMORY_BARRIER",
- "__smp memory barriers shouldn't be used outside barrier.h and asm-generic\n" . $herecurr);
- }
-
-# check for waitqueue_active without a comment.
- if ($line =~ /\bwaitqueue_active\s*\(/) {
- if (!ctx_has_comment($first_line, $linenr)) {
- WARN("WAITQUEUE_ACTIVE",
- "waitqueue_active without comment\n" . $herecurr);
- }
- }
-
-# check of hardware specific defines
- if ($line =~ m@^.\s*\#\s*if.*\b(__i386__|__powerpc64__|__sun__|__s390x__)\b@ && $realfile !~ m@include/asm-@) {
- CHK("ARCH_DEFINES",
- "architecture specific defines should be avoided\n" . $herecurr);
- }
-
-# check that the storage class is not after a type
- if ($line =~ /\b($Type)\s+($Storage)\b/) {
- WARN("STORAGE_CLASS",
- "storage class '$2' should be located before type '$1'\n" . $herecurr);
- }
-# Check that the storage class is at the beginning of a declaration
- if ($line =~ /\b$Storage\b/ &&
- $line !~ /^.\s*$Storage/ &&
- $line =~ /^.\s*(.+?)\$Storage\s/ &&
- $1 !~ /[\,\)]\s*$/) {
- WARN("STORAGE_CLASS",
- "storage class should be at the beginning of the declaration\n" . $herecurr);
- }
-
-# check the location of the inline attribute, that it is between
-# storage class and type.
- if ($line =~ /\b$Type\s+$Inline\b/ ||
- $line =~ /\b$Inline\s+$Storage\b/) {
- ERROR("INLINE_LOCATION",
- "inline keyword should sit between storage class and type\n" . $herecurr);
- }
-
-# Check for __inline__ and __inline, prefer inline
- if ($realfile !~ m@\binclude/uapi/@ &&
- $line =~ /\b(__inline__|__inline)\b/) {
- if (WARN("INLINE",
- "plain inline is preferred over $1\n" . $herecurr) &&
- $fix) {
- $fixed[$fixlinenr] =~ s/\b(__inline__|__inline)\b/inline/;
-
- }
- }
-
-# Check for __attribute__ packed, prefer __packed
- if ($realfile !~ m@\binclude/uapi/@ &&
- $line =~ /\b__attribute__\s*\(\s*\(.*\bpacked\b/) {
- WARN("PREFER_PACKED",
- "__packed is preferred over __attribute__((packed))\n" . $herecurr);
- }
-
-# Check for __attribute__ aligned, prefer __aligned
- if ($realfile !~ m@\binclude/uapi/@ &&
- $line =~ /\b__attribute__\s*\(\s*\(.*aligned/) {
- WARN("PREFER_ALIGNED",
- "__aligned(size) is preferred over __attribute__((aligned(size)))\n" . $herecurr);
- }
-
-# Check for __attribute__ format(printf, prefer __printf
- if ($realfile !~ m@\binclude/uapi/@ &&
- $line =~ /\b__attribute__\s*\(\s*\(\s*format\s*\(\s*printf/) {
- if (WARN("PREFER_PRINTF",
- "__printf(string-index, first-to-check) is preferred over __attribute__((format(printf, string-index, first-to-check)))\n" . $herecurr) &&
- $fix) {
- $fixed[$fixlinenr] =~ s/\b__attribute__\s*\(\s*\(\s*format\s*\(\s*printf\s*,\s*(.*)\)\s*\)\s*\)/"__printf(" . trim($1) . ")"/ex;
-
- }
- }
-
-# Check for __attribute__ format(scanf, prefer __scanf
- if ($realfile !~ m@\binclude/uapi/@ &&
- $line =~ /\b__attribute__\s*\(\s*\(\s*format\s*\(\s*scanf\b/) {
- if (WARN("PREFER_SCANF",
- "__scanf(string-index, first-to-check) is preferred over __attribute__((format(scanf, string-index, first-to-check)))\n" . $herecurr) &&
- $fix) {
- $fixed[$fixlinenr] =~ s/\b__attribute__\s*\(\s*\(\s*format\s*\(\s*scanf\s*,\s*(.*)\)\s*\)\s*\)/"__scanf(" . trim($1) . ")"/ex;
- }
- }
-
-# Check for __attribute__ weak, or __weak declarations (may have link issues)
- if ($^V && $^V ge 5.10.0 &&
- $line =~ /(?:$Declare|$DeclareMisordered)\s*$Ident\s*$balanced_parens\s*(?:$Attribute)?\s*;/ &&
- ($line =~ /\b__attribute__\s*\(\s*\(.*\bweak\b/ ||
- $line =~ /\b__weak\b/)) {
- ERROR("WEAK_DECLARATION",
- "Using weak declarations can have unintended link defects\n" . $herecurr);
- }
-
-# check for cast of C90 native int or longer types constants
- if ($line =~ /(\(\s*$C90_int_types\s*\)\s*)($Constant)\b/) {
- my $cast = $1;
- my $const = $2;
- if (WARN("TYPECAST_INT_CONSTANT",
- "Unnecessary typecast of c90 int constant\n" . $herecurr) &&
- $fix) {
- my $suffix = "";
- my $newconst = $const;
- $newconst =~ s/${Int_type}$//;
- $suffix .= 'U' if ($cast =~ /\bunsigned\b/);
- if ($cast =~ /\blong\s+long\b/) {
- $suffix .= 'LL';
- } elsif ($cast =~ /\blong\b/) {
- $suffix .= 'L';
- }
- $fixed[$fixlinenr] =~ s/\Q$cast\E$const\b/$newconst$suffix/;
- }
- }
-
-# check for sizeof(&)
- if ($line =~ /\bsizeof\s*\(\s*\&/) {
- WARN("SIZEOF_ADDRESS",
- "sizeof(& should be avoided\n" . $herecurr);
- }
-
-# check for sizeof without parenthesis
- if ($line =~ /\bsizeof\s+((?:\*\s*|)$Lval|$Type(?:\s+$Lval|))/) {
- if (WARN("SIZEOF_PARENTHESIS",
- "sizeof $1 should be sizeof($1)\n" . $herecurr) &&
- $fix) {
- $fixed[$fixlinenr] =~ s/\bsizeof\s+((?:\*\s*|)$Lval|$Type(?:\s+$Lval|))/"sizeof(" . trim($1) . ")"/ex;
- }
- }
-
-# check for struct spinlock declarations
- if ($line =~ /^.\s*\bstruct\s+spinlock\s+\w+\s*;/) {
- WARN("USE_SPINLOCK_T",
- "struct spinlock should be spinlock_t\n" . $herecurr);
- }
-
-# check for seq_printf uses that could be seq_puts
- if ($sline =~ /\bseq_printf\s*\(.*"\s*\)\s*;\s*$/) {
- my $fmt = get_quoted_string($line, $rawline);
- $fmt =~ s/%%//g;
- if ($fmt !~ /%/) {
- if (WARN("PREFER_SEQ_PUTS",
- "Prefer seq_puts to seq_printf\n" . $herecurr) &&
- $fix) {
- $fixed[$fixlinenr] =~ s/\bseq_printf\b/seq_puts/;
- }
- }
- }
-
- # check for vsprintf extension %p<foo> misuses
- if ($^V && $^V ge 5.10.0 &&
- defined $stat &&
- $stat =~ /^\+(?![^\{]*\{\s*).*\b(\w+)\s*\(.*$String\s*,/s &&
- $1 !~ /^_*volatile_*$/) {
- my $bad_extension = "";
- my $lc = $stat =~ tr@\n@@;
- $lc = $lc + $linenr;
- for (my $count = $linenr; $count <= $lc; $count++) {
- my $fmt = get_quoted_string($lines[$count - 1], raw_line($count, 0));
- $fmt =~ s/%%//g;
- if ($fmt =~ /(\%[\*\d\.]*p(?![\WFfSsBKRraEhMmIiUDdgVCbGNOx]).)/) {
- $bad_extension = $1;
- last;
- }
- }
- if ($bad_extension ne "") {
- my $stat_real = raw_line($linenr, 0);
- for (my $count = $linenr + 1; $count <= $lc; $count++) {
- $stat_real = $stat_real . "\n" . raw_line($count, 0);
- }
- WARN("VSPRINTF_POINTER_EXTENSION",
- "Invalid vsprintf pointer extension '$bad_extension'\n" . "$here\n$stat_real\n");
- }
- }
-
-# Check for misused memsets
- if ($^V && $^V ge 5.10.0 &&
- defined $stat &&
- $stat =~ /^\+(?:.*?)\bmemset\s*\(\s*$FuncArg\s*,\s*$FuncArg\s*\,\s*$FuncArg\s*\)/) {
-
- my $ms_addr = $2;
- my $ms_val = $7;
- my $ms_size = $12;
-
- if ($ms_size =~ /^(0x|)0$/i) {
- ERROR("MEMSET",
- "memset to 0's uses 0 as the 2nd argument, not the 3rd\n" . "$here\n$stat\n");
- } elsif ($ms_size =~ /^(0x|)1$/i) {
- WARN("MEMSET",
- "single byte memset is suspicious. Swapped 2nd/3rd argument?\n" . "$here\n$stat\n");
- }
- }
-
-# Check for memcpy(foo, bar, ETH_ALEN) that could be ether_addr_copy(foo, bar)
-# if ($^V && $^V ge 5.10.0 &&
-# defined $stat &&
-# $stat =~ /^\+(?:.*?)\bmemcpy\s*\(\s*$FuncArg\s*,\s*$FuncArg\s*\,\s*ETH_ALEN\s*\)/) {
-# if (WARN("PREFER_ETHER_ADDR_COPY",
-# "Prefer ether_addr_copy() over memcpy() if the Ethernet addresses are __aligned(2)\n" . "$here\n$stat\n") &&
-# $fix) {
-# $fixed[$fixlinenr] =~ s/\bmemcpy\s*\(\s*$FuncArg\s*,\s*$FuncArg\s*\,\s*ETH_ALEN\s*\)/ether_addr_copy($2, $7)/;
-# }
-# }
-
-# Check for memcmp(foo, bar, ETH_ALEN) that could be ether_addr_equal*(foo, bar)
-# if ($^V && $^V ge 5.10.0 &&
-# defined $stat &&
-# $stat =~ /^\+(?:.*?)\bmemcmp\s*\(\s*$FuncArg\s*,\s*$FuncArg\s*\,\s*ETH_ALEN\s*\)/) {
-# WARN("PREFER_ETHER_ADDR_EQUAL",
-# "Prefer ether_addr_equal() or ether_addr_equal_unaligned() over memcmp()\n" . "$here\n$stat\n")
-# }
-
-# check for memset(foo, 0x0, ETH_ALEN) that could be eth_zero_addr
-# check for memset(foo, 0xFF, ETH_ALEN) that could be eth_broadcast_addr
-# if ($^V && $^V ge 5.10.0 &&
-# defined $stat &&
-# $stat =~ /^\+(?:.*?)\bmemset\s*\(\s*$FuncArg\s*,\s*$FuncArg\s*\,\s*ETH_ALEN\s*\)/) {
-#
-# my $ms_val = $7;
-#
-# if ($ms_val =~ /^(?:0x|)0+$/i) {
-# if (WARN("PREFER_ETH_ZERO_ADDR",
-# "Prefer eth_zero_addr over memset()\n" . "$here\n$stat\n") &&
-# $fix) {
-# $fixed[$fixlinenr] =~ s/\bmemset\s*\(\s*$FuncArg\s*,\s*$FuncArg\s*,\s*ETH_ALEN\s*\)/eth_zero_addr($2)/;
-# }
-# } elsif ($ms_val =~ /^(?:0xff|255)$/i) {
-# if (WARN("PREFER_ETH_BROADCAST_ADDR",
-# "Prefer eth_broadcast_addr() over memset()\n" . "$here\n$stat\n") &&
-# $fix) {
-# $fixed[$fixlinenr] =~ s/\bmemset\s*\(\s*$FuncArg\s*,\s*$FuncArg\s*,\s*ETH_ALEN\s*\)/eth_broadcast_addr($2)/;
-# }
-# }
-# }
-
-# typecasts on min/max could be min_t/max_t
- if ($^V && $^V ge 5.10.0 &&
- defined $stat &&
- $stat =~ /^\+(?:.*?)\b(min|max)\s*\(\s*$FuncArg\s*,\s*$FuncArg\s*\)/) {
- if (defined $2 || defined $7) {
- my $call = $1;
- my $cast1 = deparenthesize($2);
- my $arg1 = $3;
- my $cast2 = deparenthesize($7);
- my $arg2 = $8;
- my $cast;
-
- if ($cast1 ne "" && $cast2 ne "" && $cast1 ne $cast2) {
- $cast = "$cast1 or $cast2";
- } elsif ($cast1 ne "") {
- $cast = $cast1;
- } else {
- $cast = $cast2;
- }
- WARN("MINMAX",
- "$call() should probably be ${call}_t($cast, $arg1, $arg2)\n" . "$here\n$stat\n");
- }
- }
-
-# check usleep_range arguments
- if ($^V && $^V ge 5.10.0 &&
- defined $stat &&
- $stat =~ /^\+(?:.*?)\busleep_range\s*\(\s*($FuncArg)\s*,\s*($FuncArg)\s*\)/) {
- my $min = $1;
- my $max = $7;
- if ($min eq $max) {
- WARN("USLEEP_RANGE",
- "usleep_range should not use min == max args; see Documentation/timers/timers-howto.txt\n" . "$here\n$stat\n");
- } elsif ($min =~ /^\d+$/ && $max =~ /^\d+$/ &&
- $min > $max) {
- WARN("USLEEP_RANGE",
- "usleep_range args reversed, use min then max; see Documentation/timers/timers-howto.txt\n" . "$here\n$stat\n");
- }
- }
-
-# check for naked sscanf
- if ($^V && $^V ge 5.10.0 &&
- defined $stat &&
- $line =~ /\bsscanf\b/ &&
- ($stat !~ /$Ident\s*=\s*sscanf\s*$balanced_parens/ &&
- $stat !~ /\bsscanf\s*$balanced_parens\s*(?:$Compare)/ &&
- $stat !~ /(?:$Compare)\s*\bsscanf\s*$balanced_parens/)) {
- my $lc = $stat =~ tr@\n@@;
- $lc = $lc + $linenr;
- my $stat_real = raw_line($linenr, 0);
- for (my $count = $linenr + 1; $count <= $lc; $count++) {
- $stat_real = $stat_real . "\n" . raw_line($count, 0);
- }
- WARN("NAKED_SSCANF",
- "unchecked sscanf return value\n" . "$here\n$stat_real\n");
- }
-
-# check for simple sscanf that should be kstrto<foo>
- if ($^V && $^V ge 5.10.0 &&
- defined $stat &&
- $line =~ /\bsscanf\b/) {
- my $lc = $stat =~ tr@\n@@;
- $lc = $lc + $linenr;
- my $stat_real = raw_line($linenr, 0);
- for (my $count = $linenr + 1; $count <= $lc; $count++) {
- $stat_real = $stat_real . "\n" . raw_line($count, 0);
- }
- if ($stat_real =~ /\bsscanf\b\s*\(\s*$FuncArg\s*,\s*("[^"]+")/) {
- my $format = $6;
- my $count = $format =~ tr@%@%@;
- if ($count == 1 &&
- $format =~ /^"\%(?i:ll[udxi]|[udxi]ll|ll|[hl]h?[udxi]|[udxi][hl]h?|[hl]h?|[udxi])"$/) {
- WARN("SSCANF_TO_KSTRTO",
- "Prefer kstrto<type> to single variable sscanf\n" . "$here\n$stat_real\n");
- }
- }
- }
-
-# check for new externs in .h files.
- if ($realfile =~ /\.h$/ &&
- $line =~ /^\+\s*(extern\s+)$Type\s*$Ident\s*\(/s) {
- if (CHK("AVOID_EXTERNS",
- "extern prototypes should be avoided in .h files\n" . $herecurr) &&
- $fix) {
- $fixed[$fixlinenr] =~ s/(.*)\bextern\b\s*(.*)/$1$2/;
- }
- }
-
-# check for new externs in .c files.
- if ($realfile =~ /\.c$/ && defined $stat &&
- $stat =~ /^.\s*(?:extern\s+)?$Type\s+($Ident)(\s*)\(/s)
- {
- my $function_name = $1;
- my $paren_space = $2;
-
- my $s = $stat;
- if (defined $cond) {
- substr($s, 0, length($cond), '');
- }
- if ($s =~ /^\s*;/ &&
- $function_name ne 'uninitialized_var')
- {
- WARN("AVOID_EXTERNS",
- "externs should be avoided in .c files\n" . $herecurr);
- }
-
- if ($paren_space =~ /\n/) {
- WARN("FUNCTION_ARGUMENTS",
- "arguments for function declarations should follow identifier\n" . $herecurr);
- }
-
- } elsif ($realfile =~ /\.c$/ && defined $stat &&
- $stat =~ /^.\s*extern\s+/)
- {
- WARN("AVOID_EXTERNS",
- "externs should be avoided in .c files\n" . $herecurr);
- }
-
-# check for function declarations that have arguments without identifier names
- if (defined $stat &&
- $stat =~ /^.\s*(?:extern\s+)?$Type\s*(?:$Ident|\(\s*\*\s*$Ident\s*\))\s*\(\s*([^{]+)\s*\)\s*;/s &&
- $1 ne "void") {
- my $args = trim($1);
- while ($args =~ m/\s*($Type\s*(?:$Ident|\(\s*\*\s*$Ident?\s*\)\s*$balanced_parens)?)/g) {
- my $arg = trim($1);
- if ($arg =~ /^$Type$/ && $arg !~ /enum\s+$Ident$/) {
- WARN("FUNCTION_ARGUMENTS",
- "function definition argument '$arg' should also have an identifier name\n" . $herecurr);
- }
- }
- }
-
-# check for function definitions
- if ($^V && $^V ge 5.10.0 &&
- defined $stat &&
- $stat =~ /^.\s*(?:$Storage\s+)?$Type\s*($Ident)\s*$balanced_parens\s*{/s) {
- $context_function = $1;
-
-# check for multiline function definition with misplaced open brace
- my $ok = 0;
- my $cnt = statement_rawlines($stat);
- my $herectx = $here . "\n";
- for (my $n = 0; $n < $cnt; $n++) {
- my $rl = raw_line($linenr, $n);
- $herectx .= $rl . "\n";
- $ok = 1 if ($rl =~ /^[ \+]\{/);
- $ok = 1 if ($rl =~ /\{/ && $n == 0);
- last if $rl =~ /^[ \+].*\{/;
- }
- if (!$ok) {
- ERROR("OPEN_BRACE",
- "open brace '{' following function definitions go on the next line\n" . $herectx);
- }
- }
-
-# checks for new __setup's
- if ($rawline =~ /\b__setup\("([^"]*)"/) {
- my $name = $1;
-
- if (!grep(/$name/, @setup_docs)) {
- CHK("UNDOCUMENTED_SETUP",
- "__setup appears un-documented -- check Documentation/admin-guide/kernel-parameters.rst\n" . $herecurr);
- }
- }
-
-# check for pointless casting of kmalloc return
- if ($line =~ /\*\s*\)\s*[kv][czm]alloc(_node){0,1}\b/) {
- WARN("UNNECESSARY_CASTS",
- "unnecessary cast may hide bugs, see http://c-faq.com/malloc/mallocnocast.html\n" . $herecurr);
- }
-
-# alloc style
-# p = alloc(sizeof(struct foo), ...) should be p = alloc(sizeof(*p), ...)
- if ($^V && $^V ge 5.10.0 &&
- $line =~ /\b($Lval)\s*\=\s*(?:$balanced_parens)?\s*([kv][mz]alloc(?:_node)?)\s*\(\s*(sizeof\s*\(\s*struct\s+$Lval\s*\))/) {
- CHK("ALLOC_SIZEOF_STRUCT",
- "Prefer $3(sizeof(*$1)...) over $3($4...)\n" . $herecurr);
- }
-
-# check for k[mz]alloc with multiplies that could be kmalloc_array/kcalloc
- if ($^V && $^V ge 5.10.0 &&
- defined $stat &&
- $stat =~ /^\+\s*($Lval)\s*\=\s*(?:$balanced_parens)?\s*(k[mz]alloc)\s*\(\s*($FuncArg)\s*\*\s*($FuncArg)\s*,/) {
- my $oldfunc = $3;
- my $a1 = $4;
- my $a2 = $10;
- my $newfunc = "kmalloc_array";
- $newfunc = "kcalloc" if ($oldfunc eq "kzalloc");
- my $r1 = $a1;
- my $r2 = $a2;
- if ($a1 =~ /^sizeof\s*\S/) {
- $r1 = $a2;
- $r2 = $a1;
- }
- if ($r1 !~ /^sizeof\b/ && $r2 =~ /^sizeof\s*\S/ &&
- !($r1 =~ /^$Constant$/ || $r1 =~ /^[A-Z_][A-Z0-9_]*$/)) {
- my $ctx = '';
- my $herectx = $here . "\n";
- my $cnt = statement_rawlines($stat);
- for (my $n = 0; $n < $cnt; $n++) {
- $herectx .= raw_line($linenr, $n) . "\n";
- }
- if (WARN("ALLOC_WITH_MULTIPLY",
- "Prefer $newfunc over $oldfunc with multiply\n" . $herectx) &&
- $cnt == 1 &&
- $fix) {
- $fixed[$fixlinenr] =~ s/\b($Lval)\s*\=\s*(?:$balanced_parens)?\s*(k[mz]alloc)\s*\(\s*($FuncArg)\s*\*\s*($FuncArg)/$1 . ' = ' . "$newfunc(" . trim($r1) . ', ' . trim($r2)/e;
- }
- }
- }
-
-# check for krealloc arg reuse
- if ($^V && $^V ge 5.10.0 &&
- $line =~ /\b($Lval)\s*\=\s*(?:$balanced_parens)?\s*krealloc\s*\(\s*\1\s*,/) {
- WARN("KREALLOC_ARG_REUSE",
- "Reusing the krealloc arg is almost always a bug\n" . $herecurr);
- }
-
-# check for alloc argument mismatch
- if ($line =~ /\b(kcalloc|kmalloc_array)\s*\(\s*sizeof\b/) {
- WARN("ALLOC_ARRAY_ARGS",
- "$1 uses number as first arg, sizeof is generally wrong\n" . $herecurr);
- }
-
-# check for multiple semicolons
- if ($line =~ /;\s*;\s*$/) {
- if (WARN("ONE_SEMICOLON",
- "Statements terminations use 1 semicolon\n" . $herecurr) &&
- $fix) {
- $fixed[$fixlinenr] =~ s/(\s*;\s*){2,}$/;/g;
- }
- }
-
-# check for #defines like: 1 << <digit> that could be BIT(digit), it is not exported to uapi
- if ($realfile !~ m@^include/uapi/@ &&
- $line =~ /#\s*define\s+\w+\s+\(?\s*1\s*([ulUL]*)\s*\<\<\s*(?:\d+|$Ident)\s*\)?/) {
- my $ull = "";
- $ull = "_ULL" if (defined($1) && $1 =~ /ll/i);
- if (CHK("BIT_MACRO",
- "Prefer using the BIT$ull macro\n" . $herecurr) &&
- $fix) {
- $fixed[$fixlinenr] =~ s/\(?\s*1\s*[ulUL]*\s*<<\s*(\d+|$Ident)\s*\)?/BIT${ull}($1)/;
- }
- }
-
-# check for #if defined CONFIG_<FOO> || defined CONFIG_<FOO>_MODULE
- if ($line =~ /^\+\s*#\s*if\s+defined(?:\s*\(?\s*|\s+)(CONFIG_[A-Z_]+)\s*\)?\s*\|\|\s*defined(?:\s*\(?\s*|\s+)\1_MODULE\s*\)?\s*$/) {
- my $config = $1;
- if (WARN("PREFER_IS_ENABLED",
- "Prefer IS_ENABLED(<FOO>) to CONFIG_<FOO> || CONFIG_<FOO>_MODULE\n" . $herecurr) &&
- $fix) {
- $fixed[$fixlinenr] = "\+#if IS_ENABLED($config)";
- }
- }
-
-# check for case / default statements not preceded by break/fallthrough/switch
- if ($line =~ /^.\s*(?:case\s+(?:$Ident|$Constant)\s*|default):/) {
- my $has_break = 0;
- my $has_statement = 0;
- my $count = 0;
- my $prevline = $linenr;
- while ($prevline > 1 && ($file || $count < 3) && !$has_break) {
- $prevline--;
- my $rline = $rawlines[$prevline - 1];
- my $fline = $lines[$prevline - 1];
- last if ($fline =~ /^\@\@/);
- next if ($fline =~ /^\-/);
- next if ($fline =~ /^.(?:\s*(?:case\s+(?:$Ident|$Constant)[\s$;]*|default):[\s$;]*)*$/);
- $has_break = 1 if ($rline =~ /fall[\s_-]*(through|thru)/i);
- next if ($fline =~ /^.[\s$;]*$/);
- $has_statement = 1;
- $count++;
- $has_break = 1 if ($fline =~ /\bswitch\b|\b(?:break\s*;[\s$;]*$|exit\s*\(\b|return\b|goto\b|continue\b)/);
- }
- if (!$has_break && $has_statement) {
- WARN("MISSING_BREAK",
- "Possible switch case/default not preceded by break or fallthrough comment\n" . $herecurr);
- }
- }
-
-# check for switch/default statements without a break;
- if ($^V && $^V ge 5.10.0 &&
- defined $stat &&
- $stat =~ /^\+[$;\s]*(?:case[$;\s]+\w+[$;\s]*:[$;\s]*|)*[$;\s]*\bdefault[$;\s]*:[$;\s]*;/g) {
- my $ctx = '';
- my $herectx = $here . "\n";
- my $cnt = statement_rawlines($stat);
- for (my $n = 0; $n < $cnt; $n++) {
- $herectx .= raw_line($linenr, $n) . "\n";
- }
- WARN("DEFAULT_NO_BREAK",
- "switch default: should use break\n" . $herectx);
- }
-
-# check for gcc specific __FUNCTION__
- if ($line =~ /\b__FUNCTION__\b/) {
- if (WARN("USE_FUNC",
- "__func__ should be used instead of gcc specific __FUNCTION__\n" . $herecurr) &&
- $fix) {
- $fixed[$fixlinenr] =~ s/\b__FUNCTION__\b/__func__/g;
- }
- }
-
-# check for uses of __DATE__, __TIME__, __TIMESTAMP__
- while ($line =~ /\b(__(?:DATE|TIME|TIMESTAMP)__)\b/g) {
- ERROR("DATE_TIME",
- "Use of the '$1' macro makes the build non-deterministic\n" . $herecurr);
- }
-
-# check for use of yield()
- if ($line =~ /\byield\s*\(\s*\)/) {
- WARN("YIELD",
- "Using yield() is generally wrong. See yield() kernel-doc (sched/core.c)\n" . $herecurr);
- }
-
-# check for comparisons against true and false
- if ($line =~ /\+\s*(.*?)\b(true|false|$Lval)\s*(==|\!=)\s*(true|false|$Lval)\b(.*)$/i) {
- my $lead = $1;
- my $arg = $2;
- my $test = $3;
- my $otype = $4;
- my $trail = $5;
- my $op = "!";
-
- ($arg, $otype) = ($otype, $arg) if ($arg =~ /^(?:true|false)$/i);
-
- my $type = lc($otype);
- if ($type =~ /^(?:true|false)$/) {
- if (("$test" eq "==" && "$type" eq "true") ||
- ("$test" eq "!=" && "$type" eq "false")) {
- $op = "";
- }
-
- CHK("BOOL_COMPARISON",
- "Using comparison to $otype is error prone\n" . $herecurr);
-
-## maybe suggesting a correct construct would better
-## "Using comparison to $otype is error prone. Perhaps use '${lead}${op}${arg}${trail}'\n" . $herecurr);
-
- }
- }
-
-# check for semaphores initialized locked
- if ($line =~ /^.\s*sema_init.+,\W?0\W?\)/) {
- WARN("CONSIDER_COMPLETION",
- "consider using a completion\n" . $herecurr);
- }
-
-# recommend kstrto* over simple_strto* and strict_strto*
- if ($line =~ /\b((simple|strict)_(strto(l|ll|ul|ull)))\s*\(/) {
- WARN("CONSIDER_KSTRTO",
- "$1 is obsolete, use k$3 instead\n" . $herecurr);
- }
-
-# check for __initcall(), use device_initcall() explicitly or more appropriate function please
- if ($line =~ /^.\s*__initcall\s*\(/) {
- WARN("USE_DEVICE_INITCALL",
- "please use device_initcall() or more appropriate function instead of __initcall() (see include/linux/init.h)\n" . $herecurr);
- }
-
-# check for various structs that are normally const (ops, kgdb, device_tree)
-# and avoid what seem like struct definitions 'struct foo {'
- if ($line !~ /\bconst\b/ &&
- $line =~ /\bstruct\s+($const_structs)\b(?!\s*\{)/) {
- WARN("CONST_STRUCT",
- "struct $1 should normally be const\n" . $herecurr);
- }
-
-# use of NR_CPUS is usually wrong
-# ignore definitions of NR_CPUS and usage to define arrays as likely right
- if ($line =~ /\bNR_CPUS\b/ &&
- $line !~ /^.\s*\s*#\s*if\b.*\bNR_CPUS\b/ &&
- $line !~ /^.\s*\s*#\s*define\b.*\bNR_CPUS\b/ &&
- $line !~ /^.\s*$Declare\s.*\[[^\]]*NR_CPUS[^\]]*\]/ &&
- $line !~ /\[[^\]]*\.\.\.[^\]]*NR_CPUS[^\]]*\]/ &&
- $line !~ /\[[^\]]*NR_CPUS[^\]]*\.\.\.[^\]]*\]/)
- {
- WARN("NR_CPUS",
- "usage of NR_CPUS is often wrong - consider using cpu_possible(), num_possible_cpus(), for_each_possible_cpu(), etc\n" . $herecurr);
- }
-
-# Use of __ARCH_HAS_<FOO> or ARCH_HAVE_<BAR> is wrong.
- if ($line =~ /\+\s*#\s*define\s+((?:__)?ARCH_(?:HAS|HAVE)\w*)\b/) {
- ERROR("DEFINE_ARCH_HAS",
- "#define of '$1' is wrong - use Kconfig variables or standard guards instead\n" . $herecurr);
- }
-
-# likely/unlikely comparisons similar to "(likely(foo) > 0)"
- if ($^V && $^V ge 5.10.0 &&
- $line =~ /\b((?:un)?likely)\s*\(\s*$FuncArg\s*\)\s*$Compare/) {
- WARN("LIKELY_MISUSE",
- "Using $1 should generally have parentheses around the comparison\n" . $herecurr);
- }
-
-# whine mightly about in_atomic
- if ($line =~ /\bin_atomic\s*\(/) {
- if ($realfile =~ m@^drivers/@) {
- ERROR("IN_ATOMIC",
- "do not use in_atomic in drivers\n" . $herecurr);
- } elsif ($realfile !~ m@^kernel/@) {
- WARN("IN_ATOMIC",
- "use of in_atomic() is incorrect outside core kernel code\n" . $herecurr);
- }
- }
-
-# check for mutex_trylock_recursive usage
- if ($line =~ /mutex_trylock_recursive/) {
- ERROR("LOCKING",
- "recursive locking is bad, do not use this ever.\n" . $herecurr);
- }
-
-# check for lockdep_set_novalidate_class
- if ($line =~ /^.\s*lockdep_set_novalidate_class\s*\(/ ||
- $line =~ /__lockdep_no_validate__\s*\)/ ) {
- if ($realfile !~ m@^kernel/lockdep@ &&
- $realfile !~ m@^include/linux/lockdep@ &&
- $realfile !~ m@^drivers/base/core@) {
- ERROR("LOCKDEP",
- "lockdep_no_validate class is reserved for device->mutex.\n" . $herecurr);
- }
- }
-
- if ($line =~ /debugfs_create_\w+.*\b$mode_perms_world_writable\b/ ||
- $line =~ /DEVICE_ATTR.*\b$mode_perms_world_writable\b/) {
- WARN("EXPORTED_WORLD_WRITABLE",
- "Exporting world writable files is usually an error. Consider more restrictive permissions.\n" . $herecurr);
- }
-
-# Mode permission misuses where it seems decimal should be octal
-# This uses a shortcut match to avoid unnecessary uses of a slow foreach loop
- if ($^V && $^V ge 5.10.0 &&
- defined $stat &&
- $line =~ /$mode_perms_search/) {
- foreach my $entry (@mode_permission_funcs) {
- my $func = $entry->[0];
- my $arg_pos = $entry->[1];
-
- my $lc = $stat =~ tr@\n@@;
- $lc = $lc + $linenr;
- my $stat_real = raw_line($linenr, 0);
- for (my $count = $linenr + 1; $count <= $lc; $count++) {
- $stat_real = $stat_real . "\n" . raw_line($count, 0);
- }
-
- my $skip_args = "";
- if ($arg_pos > 1) {
- $arg_pos--;
- $skip_args = "(?:\\s*$FuncArg\\s*,\\s*){$arg_pos,$arg_pos}";
- }
- my $test = "\\b$func\\s*\\(${skip_args}($FuncArg(?:\\|\\s*$FuncArg)*)\\s*[,\\)]";
- if ($stat =~ /$test/) {
- my $val = $1;
- $val = $6 if ($skip_args ne "");
- if (($val =~ /^$Int$/ && $val !~ /^$Octal$/) ||
- ($val =~ /^$Octal$/ && length($val) ne 4)) {
- ERROR("NON_OCTAL_PERMISSIONS",
- "Use 4 digit octal (0777) not decimal permissions\n" . "$here\n" . $stat_real);
- }
- if ($val =~ /^$Octal$/ && (oct($val) & 02)) {
- ERROR("EXPORTED_WORLD_WRITABLE",
- "Exporting writable files is usually an error. Consider more restrictive permissions.\n" . "$here\n" . $stat_real);
- }
- }
- }
- }
-
-# check for uses of S_<PERMS> that could be octal for readability
- if ($line =~ /\b$mode_perms_string_search\b/) {
- my $val = "";
- my $oval = "";
- my $to = 0;
- my $curpos = 0;
- my $lastpos = 0;
- while ($line =~ /\b(($mode_perms_string_search)\b(?:\s*\|\s*)?\s*)/g) {
- $curpos = pos($line);
- my $match = $2;
- my $omatch = $1;
- last if ($lastpos > 0 && ($curpos - length($omatch) != $lastpos));
- $lastpos = $curpos;
- $to |= $mode_permission_string_types{$match};
- $val .= '\s*\|\s*' if ($val ne "");
- $val .= $match;
- $oval .= $omatch;
- }
- $oval =~ s/^\s*\|\s*//;
- $oval =~ s/\s*\|\s*$//;
- my $octal = sprintf("%04o", $to);
- if (WARN("SYMBOLIC_PERMS",
- "Symbolic permissions '$oval' are not preferred. Consider using octal permissions '$octal'.\n" . $herecurr) &&
- $fix) {
- $fixed[$fixlinenr] =~ s/$val/$octal/;
- }
- }
-
-# validate content of MODULE_LICENSE against list from include/linux/module.h
- if ($line =~ /\bMODULE_LICENSE\s*\(\s*($String)\s*\)/) {
- my $extracted_string = get_quoted_string($line, $rawline);
- my $valid_licenses = qr{
- GPL|
- GPL\ v2|
- GPL\ and\ additional\ rights|
- Dual\ BSD/GPL|
- Dual\ MIT/GPL|
- Dual\ MPL/GPL|
- Proprietary
- }x;
- if ($extracted_string !~ /^"(?:$valid_licenses)"$/x) {
- WARN("MODULE_LICENSE",
- "unknown module license " . $extracted_string . "\n" . $herecurr);
- }
- }
- }
-
- # If we have no input at all, then there is nothing to report on
- # so just keep quiet.
- if ($#rawlines == -1) {
- exit(0);
- }
-
- # In mailback mode only produce a report in the negative, for
- # things that appear to be patches.
- if ($mailback && ($clean == 1 || !$is_patch)) {
- exit(0);
- }
-
- # This is not a patch, and we are are in 'no-patch' mode so
- # just keep quiet.
- if (!$chk_patch && !$is_patch) {
- exit(0);
- }
-
- if (!$is_patch && $filename !~ /cover-letter\.patch$/) {
- ERROR("NOT_UNIFIED_DIFF",
- "Does not appear to be a unified-diff format patch\n");
- }
- if ($is_patch && $has_commit_log && $chk_signoff && $signoff == 0) {
- ERROR("MISSING_SIGN_OFF",
- "Missing Signed-off-by: line(s)\n");
- }
-
- print report_dump();
- if ($summary && !($clean == 1 && $quiet == 1)) {
- print "$filename " if ($summary_file);
- print "total: $cnt_error errors, $cnt_warn warnings, " .
- (($check)? "$cnt_chk checks, " : "") .
- "$cnt_lines lines checked\n";
- }
-
- if ($quiet == 0) {
- # If there were any defects found and not already fixing them
- if (!$clean and !$fix) {
- print << "EOM"
-
-NOTE: For some of the reported defects, checkpatch may be able to
- mechanically convert to the typical style using --fix or --fix-inplace.
-EOM
- }
- # If there were whitespace errors which cleanpatch can fix
- # then suggest that.
- if ($rpt_cleaners) {
- $rpt_cleaners = 0;
- print << "EOM"
-
-NOTE: Whitespace errors detected.
- You may wish to use scripts/cleanpatch or scripts/cleanfile
-EOM
- }
- }
-
- if ($clean == 0 && $fix &&
- ("@rawlines" ne "@fixed" ||
- $#fixed_inserted >= 0 || $#fixed_deleted >= 0)) {
- my $newfile = $filename;
- $newfile .= ".EXPERIMENTAL-checkpatch-fixes" if (!$fix_inplace);
- my $linecount = 0;
- my $f;
-
- @fixed = fix_inserted_deleted_lines(\@fixed, \@fixed_inserted, \@fixed_deleted);
-
- open($f, '>', $newfile)
- or die "$P: Can't open $newfile for write\n";
- foreach my $fixed_line (@fixed) {
- $linecount++;
- if ($file) {
- if ($linecount > 3) {
- $fixed_line =~ s/^\+//;
- print $f $fixed_line . "\n";
- }
- } else {
- print $f $fixed_line . "\n";
- }
- }
- close($f);
-
- if (!$quiet) {
- print << "EOM";
-
-Wrote EXPERIMENTAL --fix correction(s) to '$newfile'
-
-Do _NOT_ trust the results written to this file.
-Do _NOT_ submit these changes without inspecting them for correctness.
-
-This EXPERIMENTAL file is simply a convenience to help rewrite patches.
-No warranties, expressed or implied...
-EOM
- }
- }
-
- if ($quiet == 0) {
- print "\n";
- if ($clean == 1) {
- print "$vname has no obvious style problems and is ready for submission.\n";
- } else {
- print "$vname has style problems, please review.\n";
- }
- }
- return $clean;
-}
diff --git a/scripts/const_structs.checkpatch b/scripts/const_structs.checkpatch
deleted file mode 100644
index 25fb13c..0000000
--- a/scripts/const_structs.checkpatch
+++ /dev/null
@@ -1,4 +0,0 @@
-comp_func_map
-dma_ops
-dai_ops
-freq_table
\ No newline at end of file
diff --git a/scripts/docker-run.sh b/scripts/docker-run.sh
deleted file mode 100755
index b1e989c..0000000
--- a/scripts/docker-run.sh
+++ /dev/null
@@ -1,13 +0,0 @@
-#!/bin/sh
-
-# Runs a given script in the docker container you can generate from the
-# docker_build directory.
-# Example:
-# To build sof for baytrail:
-# ./scripts/docker-run.sh ./scripts/xtensa-build-all.sh byt
-# To build topology:
-# ./scripts/docker-run.sh ./scripts/build_soft.sh
-
-docker run -it -v `pwd`:/home/sof/work/sof.git \
- -v `pwd`/../soft.git:/home/sof/work/soft.git \
- --user `id -u` sof $@
diff --git a/scripts/docker_build/Dockerfile b/scripts/docker_build/Dockerfile
deleted file mode 100644
index ffc68aa..0000000
--- a/scripts/docker_build/Dockerfile
+++ /dev/null
@@ -1,110 +0,0 @@
-# Copyright 2018 The Chromium Authors. All rights reserved.
-# Use of this source code is governed by a BSD-style license that can be
-# found in the LICENSE file.
-#
-# Defines a docker image that can build sound open firmware
-#
-# Usage:
-# check out sof
-# build docker image:
-# docker build --build-arg UID=$(id -u) -t sof .
-# docker run -it -v <insert sof dir here>:/home/sof/workdir -v <soft git dir>:/home/sof/work/soft.git --user `id -u` sof
-#
-# For incremental builds:
-# docker run -it -v <insert sof dir here>:/home/sof/work/sof.git -v <soft git dir>:/home/sof/work/soft.git --user `id -u` sof ./incremental.sh
-#
-
-FROM ubuntu:18.04
-ARG UID=1000
-
-# Set up proxy from host
-COPY apt.conf /etc/apt/
-ARG host_http_proxy
-ARG host_https_proxy
-ENV http_proxy $host_http_proxy
-ENV https_proxy $host_https_proxy
-
-RUN apt-get -y update && \
- apt-get install -y \
- autoconf \
- bison \
- build-essential \
- flex \
- gawk \
- gettext \
- git \
- gperf \
- help2man \
- libncurses5-dev \
- libssl-dev \
- libtool \
- libtool-bin \
- pkg-config \
- software-properties-common \
- sudo \
- texinfo \
- udev \
- wget \
- unzip
-
-
-# Use ToT alsa utils for the latest topology patches.
-RUN mkdir -p /root/alsa-build && cd /root/alsa-build && \
- if [ "x$http_proxy" = "x" ]; then \
- git clone git://git.alsa-project.org/alsa-lib.git && \
- git clone git://git.alsa-project.org/alsa-utils.git ; \
- else \
- git clone http://git.alsa-project.org/http/alsa-lib.git && \
- git clone http://git.alsa-project.org/http/alsa-utils.git; \
- fi && \
-cd /root/alsa-build/alsa-lib && ./gitcompile && make install && \
-cd /root/alsa-build/alsa-utils && ./gitcompile && make install && \
-cd /root/ && rm -rf alsa-build
-
-# Set up sof user
-RUN useradd --create-home -d /home/sof -u $UID -G sudo sof && \
-echo "sof:test0000" | chpasswd && adduser sof sudo
-ENV HOME /home/sof
-
-# build cross compiler
-USER sof
-RUN cd /home/sof && git clone https://github.com/thesofproject/xtensa-overlay.git && \
- cd xtensa-overlay && git checkout sof-gcc8.1 && cd ../ && \
- git clone https://github.com/thesofproject/crosstool-ng.git && \
- mkdir -p /home/sof/work/ && \
- cd crosstool-ng && git checkout sof-gcc8.1 && \
- ./bootstrap && ./configure --prefix=`pwd` && make && make install && \
- for arch in byt hsw apl cnl; do \
- cp config-${arch}-gcc8.1-gdb8.1 .config && \
-# replace the build dist to save space
- sed -i 's#${CT_TOP_DIR}\/builds#\/home\/sof\/work#g' .config && \
-# gl_cv_func_getcwd_path_max=yes is used to avoid too-long confdir3/confdir3/...
- gl_cv_func_getcwd_path_max=yes ./ct-ng build && \
- ./ct-ng distclean ; \
- done && \
- cd /home/sof/ && rm -rf xtensa-overlay && rm -rf crosstool-ng
-
-ENV PATH="/home/sof/work/xtensa-byt-elf/bin:${PATH}"
-ENV PATH="/home/sof/work/xtensa-hsw-elf/bin:${PATH}"
-ENV PATH="/home/sof/work/xtensa-apl-elf/bin:${PATH}"
-ENV PATH="/home/sof/work/xtensa-cnl-elf/bin:${PATH}"
-
-RUN cd /home/sof && git clone https://github.com/jcmvbkbc/newlib-xtensa.git newlib-xtensa.git && \
- cd newlib-xtensa.git && git checkout -b xtensa origin/xtensa && \
- for arch in byt hsw apl cnl; do \
- ./configure --target=xtensa-${arch}-elf \
- --prefix=/home/sof/work/xtensa-root && \
- make && \
- make install && \
- make distclean; \
- done && \
- cd /home/sof/ && rm -rf newlib-xtensa.git
-
-
-# Create direcroties for the host machines sof/soft directories to be mounted.
-RUN mkdir -p /home/sof/work/sof.git && \
- mkdir -p /home/sof/work/soft.git
-
-
-USER sof
-WORKDIR /home/sof/work/sof.git/
diff --git a/scripts/docker_build/docker-build.sh b/scripts/docker_build/docker-build.sh
deleted file mode 100755
index 1090f15..0000000
--- a/scripts/docker_build/docker-build.sh
+++ /dev/null
@@ -1,7 +0,0 @@
-#!/bin/bash
-if [ -f "/etc/apt/apt.conf" ]; then
- cp /etc/apt/apt.conf ./
-else
- touch apt.conf
-fi
-docker build --build-arg UID=$(id -u) --build-arg host_http_proxy=$http_proxy --build-arg host_https_proxy=$https_proxy -t sof .
diff --git a/scripts/host-build-all.sh b/scripts/host-build-all.sh
deleted file mode 100755
index 4c316da..0000000
--- a/scripts/host-build-all.sh
+++ /dev/null
@@ -1,15 +0,0 @@
-#!/bin/sh
-
-# fail on any errors
-set -e
-
-# run autogen.sh
-./autogen.sh
-
-# build all images for all targets.
-pwd=`pwd`
-
-# Build library for host platform architecture
-./configure --with-arch=host --enable-library=yes --host=x86_64-unknown-linux-gnu
-make
-make install
diff --git a/scripts/host-testbench.sh b/scripts/host-testbench.sh
deleted file mode 100755
index 6e77b4b..0000000
--- a/scripts/host-testbench.sh
+++ /dev/null
@@ -1,40 +0,0 @@
-#!/bin/sh
-
-#build host library
-sudo ./scripts/host-build-all.sh
-
-#input file
-input_file="48000Hz_stereo_16bit.raw"
-
-#output_file
-output_file="out.raw"
-
-#input bit format
-bits_in="S16_LE"
-
-#input sample rate (this is an optional argument for SRC based pipelines)
-#should be used with -r option
-fs_in="48000"
-
-#output sample rate (this is an optional argument for SRC based pipelines)
-#should be used with -R option
-fs_out="96000"
-
-# topology file
-# please use simple volume/src topologies for now
-
-topology_file="../soft.git/topology/test/test-playback-ssp2-I2S-volume-s16le-s32le-48k-24576k-codec.tplg"
-
-#example src topology
-#topology_file="../soft.git/topology/test/test-playback-ssp5-LEFT_J-src-s24le-s24le-48k-19200k-codec.tplg"
-
-#optional libraries to override
-libraries="vol=libsof_volume.so,src=libsof_src.so"
-
-# Use -d to enable debug prints
-
-# run volume testbench
-./src/host/testbench -i $input_file -o $output_file -b $bits_in -t $topology_file -a $libraries -d
-
-# run src testbench
-#./src/host/testbench -i $input_file -o $output_file -b $bits_in -t $topology_file -a $libraries -r $fs_in -R $fs_out -d
diff --git a/scripts/rimage-build.sh b/scripts/rimage-build.sh
deleted file mode 100755
index af7997d..0000000
--- a/scripts/rimage-build.sh
+++ /dev/null
@@ -1,6 +0,0 @@
-#!/bin/sh
-
-./autogen.sh
-./configure --enable-rimage
-make
-
diff --git a/scripts/sof-post-commit-hook.sh b/scripts/sof-post-commit-hook.sh
deleted file mode 100755
index 0df8012..0000000
--- a/scripts/sof-post-commit-hook.sh
+++ /dev/null
@@ -1,4 +0,0 @@
-#!/bin/sh
-
-set -e
-exec git show --format=email HEAD | ./scripts/checkpatch.pl --no-tree --strict --codespell
diff --git a/scripts/sof-pre-commit-hook.sh b/scripts/sof-pre-commit-hook.sh
deleted file mode 100755
index 182fed4..0000000
--- a/scripts/sof-pre-commit-hook.sh
+++ /dev/null
@@ -1,4 +0,0 @@
-#!/bin/bash
-
-exec git diff --cached | scripts/checkpatch.pl --no-tree --codespell --no-signoff -q -
-
diff --git a/scripts/spelling.txt b/scripts/spelling.txt
deleted file mode 100644
index 9a058cf..0000000
--- a/scripts/spelling.txt
+++ /dev/null
@@ -1,1254 +0,0 @@
-# Originally from Debian's Lintian tool. Various false positives have been
-# removed, and various additions have been made as they've been discovered
-# in the kernel source.
-#
-# License: GPLv2
-#
-# The format of each line is:
-# mistake||correction
-#
-abandonning||abandoning
-abigious||ambiguous
-abitrate||arbitrate
-abov||above
-abreviated||abbreviated
-absense||absence
-absolut||absolute
-absoulte||absolute
-acccess||access
-acceess||access
-acceleratoin||acceleration
-accelleration||acceleration
-accesing||accessing
-accesnt||accent
-accessable||accessible
-accesss||access
-accidentaly||accidentally
-accidentually||accidentally
-accoding||according
-accomodate||accommodate
-accomodates||accommodates
-accordign||according
-accoring||according
-accout||account
-accquire||acquire
-accquired||acquired
-accross||across
-acessable||accessible
-acess||access
-achitecture||architecture
-acient||ancient
-acitions||actions
-acitve||active
-acknowldegement||acknowledgment
-acknowledgement||acknowledgment
-ackowledge||acknowledge
-ackowledged||acknowledged
-acording||according
-activete||activate
-actived||activated
-actualy||actually
-acumulating||accumulating
-acumulator||accumulator
-adapater||adapter
-addional||additional
-additionaly||additionally
-additonal||additional
-addres||address
-adddress||address
-addreses||addresses
-addresss||address
-aditional||additional
-aditionally||additionally
-aditionaly||additionally
-adminstrative||administrative
-adress||address
-adresses||addresses
-adviced||advised
-afecting||affecting
-againt||against
-agaist||against
-aggreataon||aggregation
-aggreation||aggregation
-albumns||albums
-alegorical||allegorical
-algined||aligned
-algorith||algorithm
-algorithmical||algorithmically
-algoritm||algorithm
-algoritms||algorithms
-algorrithm||algorithm
-algorritm||algorithm
-aligment||alignment
-alignement||alignment
-allign||align
-alligned||aligned
-alllocate||allocate
-alloated||allocated
-allocatote||allocate
-allocatrd||allocated
-allocte||allocate
-allpication||application
-alocate||allocate
-alogirhtms||algorithms
-alogrithm||algorithm
-alot||a lot
-alow||allow
-alows||allows
-altough||although
-alue||value
-ambigious||ambiguous
-amoung||among
-amout||amount
-an union||a union
-an user||a user
-an userspace||a userspace
-an one||a one
-analysator||analyzer
-ang||and
-anniversery||anniversary
-annoucement||announcement
-anomolies||anomalies
-anomoly||anomaly
-anway||anyway
-aplication||application
-appearence||appearance
-applicaion||application
-appliction||application
-applictions||applications
-applys||applies
-appplications||applications
-appropiate||appropriate
-appropriatly||appropriately
-approriate||appropriate
-approriately||appropriately
-apropriate||appropriate
-aquainted||acquainted
-aquired||acquired
-aquisition||acquisition
-arbitary||arbitrary
-architechture||architecture
-arguement||argument
-arguements||arguments
-aritmetic||arithmetic
-arne't||aren't
-arraival||arrival
-artifical||artificial
-artillary||artillery
-asign||assign
-asser||assert
-assertation||assertion
-assiged||assigned
-assigment||assignment
-assigments||assignments
-assistent||assistant
-assocation||association
-associcated||associated
-assotiated||associated
-assum||assume
-assumtpion||assumption
-asuming||assuming
-asycronous||asynchronous
-asynchnous||asynchronous
-atomatically||automatically
-atomicly||atomically
-atempt||attempt
-attachement||attachment
-attched||attached
-attemps||attempts
-attemping||attempting
-attruibutes||attributes
-authentification||authentication
-automaticaly||automatically
-automaticly||automatically
-automatize||automate
-automatized||automated
-automatizes||automates
-autonymous||autonomous
-auxillary||auxiliary
-auxilliary||auxiliary
-avaiable||available
-avaible||available
-availabe||available
-availabled||available
-availablity||availability
-availale||available
-availavility||availability
-availble||available
-availiable||available
-availible||available
-avalable||available
-avaliable||available
-aysnc||async
-backgroud||background
-backword||backward
-backwords||backwards
-bahavior||behavior
-bakup||backup
-baloon||balloon
-baloons||balloons
-bandwith||bandwidth
-banlance||balance
-batery||battery
-beacuse||because
-becasue||because
-becomming||becoming
-becuase||because
-beeing||being
-befor||before
-begining||beginning
-beter||better
-betweeen||between
-bianries||binaries
-bitmast||bitmask
-boardcast||broadcast
-borad||board
-boundry||boundary
-brievely||briefly
-broadcat||broadcast
-cacluated||calculated
-caculation||calculation
-calender||calendar
-calescing||coalescing
-calle||called
-callibration||calibration
-calucate||calculate
-calulate||calculate
-cancelation||cancellation
-cancle||cancel
-capabilites||capabilities
-capabilty||capability
-capabitilies||capabilities
-capatibilities||capabilities
-capapbilities||capabilities
-carefuly||carefully
-cariage||carriage
-catagory||category
-cehck||check
-challange||challenge
-challanges||challenges
-chanell||channel
-changable||changeable
-chanined||chained
-channle||channel
-channnel||channel
-charachter||character
-charachters||characters
-charactor||character
-charater||character
-charaters||characters
-charcter||character
-chcek||check
-chck||check
-checksuming||checksumming
-childern||children
-childs||children
-chiled||child
-chked||checked
-chnage||change
-chnages||changes
-chnnel||channel
-choosen||chosen
-chouse||chose
-circumvernt||circumvent
-claread||cleared
-clared||cleared
-closeing||closing
-clustred||clustered
-coexistance||coexistence
-collapsable||collapsible
-colorfull||colorful
-comand||command
-comit||commit
-commerical||commercial
-comming||coming
-comminucation||communication
-commited||committed
-commiting||committing
-committ||commit
-commoditiy||commodity
-comsume||consume
-comsumer||consumer
-comsuming||consuming
-compability||compatibility
-compaibility||compatibility
-compatability||compatibility
-compatable||compatible
-compatibiliy||compatibility
-compatibilty||compatibility
-compatiblity||compatibility
-competion||completion
-compilant||compliant
-compleatly||completely
-completition||completion
-completly||completely
-complient||compliant
-componnents||components
-compoment||component
-compres||compress
-compresion||compression
-comression||compression
-comunication||communication
-conbination||combination
-conditionaly||conditionally
-conected||connected
-connecetd||connected
-configuartion||configuration
-configuratoin||configuration
-configuraton||configuration
-configuretion||configuration
-configutation||configuration
-conider||consider
-conjuction||conjunction
-connectinos||connections
-connnection||connection
-connnections||connections
-consistancy||consistency
-consistant||consistent
-containes||contains
-containts||contains
-contaisn||contains
-contant||contact
-contence||contents
-continious||continuous
-continous||continuous
-continously||continuously
-continueing||continuing
-contraints||constraints
-contol||control
-contoller||controller
-controled||controlled
-controler||controller
-controll||control
-contruction||construction
-contry||country
-conuntry||country
-convertion||conversion
-convertor||converter
-convienient||convenient
-convinient||convenient
-corected||corrected
-correponding||corresponding
-correponds||corresponds
-correspoding||corresponding
-cotrol||control
-cound||could
-couter||counter
-coutner||counter
-cryptocraphic||cryptographic
-cunter||counter
-curently||currently
-cylic||cyclic
-dafault||default
-deafult||default
-deamon||daemon
-decompres||decompress
-decription||description
-dectected||detected
-defailt||default
-defferred||deferred
-definate||definite
-definately||definitely
-defintion||definition
-defintions||definitions
-defualt||default
-defult||default
-deintializing||deinitializing
-deintialize||deinitialize
-deintialized||deinitialized
-deivce||device
-delared||declared
-delare||declare
-delares||declares
-delaring||declaring
-delemiter||delimiter
-demodualtor||demodulator
-demension||dimension
-dependancies||dependencies
-dependancy||dependency
-dependant||dependent
-depreacted||deprecated
-depreacte||deprecate
-desactivate||deactivate
-desciptor||descriptor
-desciptors||descriptors
-descripton||description
-descrition||description
-descritptor||descriptor
-desctiptor||descriptor
-desriptor||descriptor
-desriptors||descriptors
-destionation||destination
-destory||destroy
-destoryed||destroyed
-destorys||destroys
-destroied||destroyed
-detabase||database
-deteced||detected
-develope||develop
-developement||development
-developped||developed
-developpement||development
-developper||developer
-developpment||development
-deveolpment||development
-devided||divided
-deviece||device
-diable||disable
-dictionnary||dictionary
-didnt||didn't
-diferent||different
-differrence||difference
-diffrent||different
-diffrentiate||differentiate
-difinition||definition
-dimesions||dimensions
-diplay||display
-direectly||directly
-disassocation||disassociation
-disapear||disappear
-disapeared||disappeared
-disappared||disappeared
-disble||disable
-disbled||disabled
-disconnet||disconnect
-discontinous||discontinuous
-dispertion||dispersion
-dissapears||disappears
-distiction||distinction
-docuentation||documentation
-documantation||documentation
-documentaion||documentation
-documment||document
-doesnt||doesn't
-dorp||drop
-dosen||doesn
-downlad||download
-downlads||downloads
-druing||during
-dynmaic||dynamic
-easilly||easily
-ecspecially||especially
-edditable||editable
-editting||editing
-efective||effective
-efficently||efficiently
-ehther||ether
-eigth||eight
-elementry||elementary
-eletronic||electronic
-embeded||embedded
-enabledi||enabled
-enchanced||enhanced
-encorporating||incorporating
-encrupted||encrypted
-encrypiton||encryption
-encryptio||encryption
-endianess||endianness
-enhaced||enhanced
-enlightnment||enlightenment
-entrys||entries
-enocded||encoded
-enterily||entirely
-enviroiment||environment
-enviroment||environment
-environement||environment
-environent||environment
-eqivalent||equivalent
-equiped||equipped
-equivelant||equivalent
-equivilant||equivalent
-eror||error
-errorr||error
-estbalishment||establishment
-etsablishment||establishment
-etsbalishment||establishment
-excecutable||executable
-exceded||exceeded
-excellant||excellent
-exeed||exceed
-existance||existence
-existant||existent
-exixt||exist
-exlcude||exclude
-exlcusive||exclusive
-exmaple||example
-expecially||especially
-explicite||explicit
-explicitely||explicitly
-explict||explicit
-explictely||explicitly
-explictly||explicitly
-expresion||expression
-exprimental||experimental
-extened||extended
-extensability||extensibility
-extention||extension
-extracter||extractor
-falied||failed
-faild||failed
-faill||fail
-failied||failed
-faillure||failure
-failue||failure
-failuer||failure
-failng||failing
-faireness||fairness
-falied||failed
-faliure||failure
-fallbck||fallback
-familar||familiar
-fatser||faster
-feauture||feature
-feautures||features
-fetaure||feature
-fetaures||features
-fileystem||filesystem
-fimware||firmware
-firware||firmware
-finanize||finalize
-findn||find
-finilizes||finalizes
-finsih||finish
-flusing||flushing
-folloing||following
-followign||following
-followings||following
-follwing||following
-fonud||found
-forseeable||foreseeable
-forse||force
-fortan||fortran
-forwardig||forwarding
-framming||framing
-framwork||framework
-frequncy||frequency
-frome||from
-fucntion||function
-fuction||function
-fuctions||functions
-funcion||function
-functionallity||functionality
-functionaly||functionally
-functionnality||functionality
-functonality||functionality
-funtion||function
-funtions||functions
-furthur||further
-futhermore||furthermore
-futrue||future
-gaurenteed||guaranteed
-generiously||generously
-genereate||generate
-genric||generic
-globel||global
-grabing||grabbing
-grahical||graphical
-grahpical||graphical
-grapic||graphic
-grranted||granted
-guage||gauge
-guarenteed||guaranteed
-guarentee||guarantee
-halfs||halves
-hander||handler
-handfull||handful
-hanled||handled
-happend||happened
-harware||hardware
-heirarchically||hierarchically
-helpfull||helpful
-hybernate||hibernate
-hierachy||hierarchy
-hierarchie||hierarchy
-howver||however
-hsould||should
-hypervior||hypervisor
-hypter||hyper
-identidier||identifier
-iligal||illegal
-illigal||illegal
-imblance||imbalance
-immeadiately||immediately
-immedaite||immediate
-immediatelly||immediately
-immediatly||immediately
-immidiate||immediate
-impelentation||implementation
-impementated||implemented
-implemantation||implementation
-implemenation||implementation
-implementaiton||implementation
-implementated||implemented
-implemention||implementation
-implementd||implemented
-implemetation||implementation
-implemntation||implementation
-implentation||implementation
-implmentation||implementation
-implmenting||implementing
-incative||inactive
-incomming||incoming
-incompatabilities||incompatibilities
-incompatable||incompatible
-inconsistant||inconsistent
-increas||increase
-incremeted||incremented
-incrment||increment
-indendation||indentation
-indended||intended
-independant||independent
-independantly||independently
-independed||independent
-indiate||indicate
-indicat||indicate
-inexpect||inexpected
-infomation||information
-informatiom||information
-informations||information
-informtion||information
-infromation||information
-ingore||ignore
-inital||initial
-initalized||initialized
-initalised||initialized
-initalise||initialize
-initalize||initialize
-initation||initiation
-initators||initiators
-initialiazation||initialization
-initializiation||initialization
-initialzed||initialized
-initilization||initialization
-initilize||initialize
-inofficial||unofficial
-insititute||institute
-instal||install
-instanciated||instantiated
-inteface||interface
-integreated||integrated
-integrety||integrity
-integrey||integrity
-intendet||intended
-intented||intended
-interanl||internal
-interchangable||interchangeable
-interferring||interfering
-interger||integer
-intermittant||intermittent
-internel||internal
-interoprability||interoperability
-interuupt||interrupt
-interrface||interface
-interrrupt||interrupt
-interrup||interrupt
-interrups||interrupts
-interruptted||interrupted
-interupted||interrupted
-interupt||interrupt
-intial||initial
-intialisation||initialisation
-intialised||initialised
-intialise||initialise
-intialization||initialization
-intialized||initialized
-intialize||initialize
-intregral||integral
-intrrupt||interrupt
-intterrupt||interrupt
-intuative||intuitive
-invaid||invalid
-invald||invalid
-invalde||invalid
-invalide||invalid
-invalidiate||invalidate
-invalud||invalid
-invididual||individual
-invokation||invocation
-invokations||invocations
-irrelevent||irrelevant
-isnt||isn't
-isssue||issue
-iternations||iterations
-itertation||iteration
-itslef||itself
-jave||java
-jeffies||jiffies
-juse||just
-jus||just
-kown||known
-langage||language
-langauage||language
-langauge||language
-langugage||language
-lauch||launch
-layed||laid
-leightweight||lightweight
-lengh||length
-lenght||length
-lenth||length
-lesstiff||lesstif
-libaries||libraries
-libary||library
-librairies||libraries
-libraris||libraries
-licenceing||licencing
-loggging||logging
-loggin||login
-logile||logfile
-loosing||losing
-losted||lost
-machinary||machinery
-maintainance||maintenance
-maintainence||maintenance
-maintan||maintain
-makeing||making
-malplaced||misplaced
-malplace||misplace
-managable||manageable
-managment||management
-mangement||management
-manoeuvering||maneuvering
-mappping||mapping
-mathimatical||mathematical
-mathimatic||mathematic
-mathimatics||mathematics
-maxium||maximum
-mechamism||mechanism
-meetign||meeting
-ment||meant
-mergable||mergeable
-mesage||message
-messags||messages
-messgaes||messages
-messsage||message
-messsages||messages
-micropone||microphone
-microprocesspr||microprocessor
-milliseonds||milliseconds
-minium||minimum
-minimam||minimum
-minumum||minimum
-misalinged||misaligned
-miscelleneous||miscellaneous
-misformed||malformed
-mispelled||misspelled
-mispelt||misspelt
-mising||missing
-mismactch||mismatch
-missmanaged||mismanaged
-missmatch||mismatch
-miximum||maximum
-mmnemonic||mnemonic
-mnay||many
-modulues||modules
-momery||memory
-memomry||memory
-monochorome||monochrome
-monochromo||monochrome
-monocrome||monochrome
-mopdule||module
-mroe||more
-mulitplied||multiplied
-multidimensionnal||multidimensional
-multple||multiple
-mumber||number
-muticast||multicast
-mutilcast||multicast
-mutiple||multiple
-mutli||multi
-nams||names
-navagating||navigating
-nead||need
-neccecary||necessary
-neccesary||necessary
-neccessary||necessary
-necesary||necessary
-neded||needed
-negaive||negative
-negoitation||negotiation
-negotation||negotiation
-nerver||never
-nescessary||necessary
-nessessary||necessary
-noticable||noticeable
-notications||notifications
-notifed||notified
-numebr||number
-numner||number
-obtaion||obtain
-occassionally||occasionally
-occationally||occasionally
-occurance||occurrence
-occurances||occurrences
-occured||occurred
-occurence||occurrence
-occure||occurred
-occured||occurred
-occuring||occurring
-offet||offset
-omited||omitted
-omiting||omitting
-omitt||omit
-ommiting||omitting
-ommitted||omitted
-onself||oneself
-ony||only
-operatione||operation
-opertaions||operations
-optionnal||optional
-optmizations||optimizations
-orientatied||orientated
-orientied||oriented
-orignal||original
-otherise||otherwise
-ouput||output
-oustanding||outstanding
-overaall||overall
-overhread||overhead
-overlaping||overlapping
-overide||override
-overrided||overridden
-overriden||overridden
-overun||overrun
-overwritting||overwriting
-overwriten||overwritten
-pacakge||package
-pachage||package
-packacge||package
-packege||package
-packge||package
-packtes||packets
-pakage||package
-pallette||palette
-paln||plan
-paramameters||parameters
-paramaters||parameters
-paramater||parameter
-parametes||parameters
-parametised||parametrised
-paramter||parameter
-paramters||parameters
-particuarly||particularly
-particularily||particularly
-partiton||partition
-pased||passed
-passin||passing
-pathes||paths
-pecularities||peculiarities
-peformance||performance
-peice||piece
-pendantic||pedantic
-peprocessor||preprocessor
-perfoming||performing
-permissons||permissions
-peroid||period
-persistance||persistence
-persistant||persistent
-plalform||platform
-platfrom||platform
-plattform||platform
-pleaes||please
-ploting||plotting
-plugable||pluggable
-poinnter||pointer
-pointeur||pointer
-poiter||pointer
-posible||possible
-positon||position
-possibilites||possibilities
-powerfull||powerful
-preample||preamble
-preapre||prepare
-preceeded||preceded
-preceeding||preceding
-preceed||precede
-precendence||precedence
-precission||precision
-preemptable||preemptible
-prefered||preferred
-prefferably||preferably
-premption||preemption
-prepaired||prepared
-pressre||pressure
-primative||primitive
-princliple||principle
-priorty||priority
-privilaged||privileged
-privilage||privilege
-priviledge||privilege
-priviledges||privileges
-probaly||probably
-procceed||proceed
-proccesors||processors
-procesed||processed
-proces||process
-procesing||processing
-processessing||processing
-processess||processes
-processpr||processor
-processsed||processed
-processsing||processing
-procteted||protected
-prodecure||procedure
-progams||programs
-progess||progress
-programers||programmers
-programm||program
-programms||programs
-progresss||progress
-promiscous||promiscuous
-promps||prompts
-pronnounced||pronounced
-prononciation||pronunciation
-pronouce||pronounce
-pronunce||pronounce
-propery||property
-propigate||propagate
-propigation||propagation
-propogate||propagate
-prosess||process
-protable||portable
-protcol||protocol
-protecion||protection
-protocoll||protocol
-promixity||proximity
-psudo||pseudo
-psuedo||pseudo
-psychadelic||psychedelic
-pwoer||power
-quering||querying
-randomally||randomly
-raoming||roaming
-reasearcher||researcher
-reasearchers||researchers
-reasearch||research
-recepient||recipient
-receving||receiving
-recieved||received
-recieve||receive
-reciever||receiver
-recieves||receives
-recogniced||recognised
-recognizeable||recognizable
-recommanded||recommended
-recyle||recycle
-redircet||redirect
-redirectrion||redirection
-reename||rename
-refcounf||refcount
-refence||reference
-refered||referred
-referenace||reference
-refering||referring
-refernces||references
-refernnce||reference
-refrence||reference
-registerd||registered
-registeresd||registered
-registerred||registered
-registes||registers
-registraration||registration
-regsiter||register
-regster||register
-regualar||regular
-reguator||regulator
-regulamentations||regulations
-reigstration||registration
-releated||related
-relevent||relevant
-remoote||remote
-remore||remote
-removeable||removable
-repectively||respectively
-replacable||replaceable
-replacments||replacements
-replys||replies
-reponse||response
-representaion||representation
-reqeust||request
-requestied||requested
-requiere||require
-requirment||requirement
-requred||required
-requried||required
-requst||request
-reseting||resetting
-resizeable||resizable
-resouce||resource
-resouces||resources
-resoures||resources
-responce||response
-ressizes||resizes
-ressource||resource
-ressources||resources
-retransmited||retransmitted
-retreived||retrieved
-retreive||retrieve
-retrive||retrieve
-retuned||returned
-reudce||reduce
-reuest||request
-reuqest||request
-reutnred||returned
-revsion||revision
-rmeoved||removed
-rmeove||remove
-rmeoves||removes
-rountine||routine
-routins||routines
-rquest||request
-runing||running
-runned||ran
-runnning||running
-runtine||runtime
-sacrifying||sacrificing
-safly||safely
-safty||safety
-savable||saveable
-scaned||scanned
-scaning||scanning
-scarch||search
-seach||search
-searchs||searches
-secquence||sequence
-secund||second
-segement||segment
-senarios||scenarios
-sentivite||sensitive
-separatly||separately
-sepcify||specify
-sepc||spec
-seperated||separated
-seperately||separately
-seperate||separate
-seperatly||separately
-seperator||separator
-sepperate||separate
-sequece||sequence
-sequencial||sequential
-serveral||several
-setts||sets
-settting||setting
-shotdown||shutdown
-shoud||should
-shouldnt||shouldn't
-shoule||should
-shrinked||shrunk
-siginificantly||significantly
-signabl||signal
-similary||similarly
-similiar||similar
-simlar||similar
-simliar||similar
-simpified||simplified
-singaled||signaled
-singal||signal
-singed||signed
-sleeped||slept
-softwares||software
-speach||speech
-specfic||specific
-speciefied||specified
-specifc||specific
-specifed||specified
-specificatin||specification
-specificaton||specification
-specifing||specifying
-specifiying||specifying
-speficied||specified
-speicify||specify
-speling||spelling
-spinlcok||spinlock
-spinock||spinlock
-splitted||split
-spreaded||spread
-spurrious||spurious
-sructure||structure
-stablilization||stabilization
-staically||statically
-staion||station
-standardss||standards
-standartization||standardization
-standart||standard
-staticly||statically
-stoped||stopped
-stoppped||stopped
-straming||streaming
-struc||struct
-structres||structures
-stuct||struct
-strucuture||structure
-stucture||structure
-sturcture||structure
-subdirectoires||subdirectories
-suble||subtle
-substract||subtract
-submition||submission
-succesfully||successfully
-succesful||successful
-successed||succeeded
-successfull||successful
-successfuly||successfully
-sucessfully||successfully
-sucess||success
-superflous||superfluous
-superseeded||superseded
-suplied||supplied
-suported||supported
-suport||support
-supportet||supported
-suppored||supported
-supportin||supporting
-suppoted||supported
-suppported||supported
-suppport||support
-supress||suppress
-surpressed||suppressed
-surpresses||suppresses
-susbsystem||subsystem
-suspeneded||suspended
-suspicously||suspiciously
-swaping||swapping
-switchs||switches
-swith||switch
-swithable||switchable
-swithc||switch
-swithced||switched
-swithcing||switching
-swithed||switched
-swithing||switching
-swtich||switch
-symetric||symmetric
-synax||syntax
-synchonized||synchronized
-syncronize||synchronize
-syncronized||synchronized
-syncronizing||synchronizing
-syncronus||synchronous
-syste||system
-sytem||system
-sythesis||synthesis
-taht||that
-targetted||targeted
-targetting||targeting
-teh||the
-temorary||temporary
-temproarily||temporarily
-therfore||therefore
-thier||their
-threds||threads
-threshhold||threshold
-thresold||threshold
-throught||through
-troughput||throughput
-thses||these
-tiggered||triggered
-tipically||typically
-timout||timeout
-tmis||this
-torerable||tolerable
-tramsmitted||transmitted
-tramsmit||transmit
-tranasction||transaction
-tranfer||transfer
-transciever||transceiver
-transferd||transferred
-transfered||transferred
-transfering||transferring
-transision||transition
-transmittd||transmitted
-transormed||transformed
-trasfer||transfer
-trasmission||transmission
-treshold||threshold
-trigerring||triggering
-trun||turn
-tunning||tuning
-ture||true
-tyep||type
-udpate||update
-uesd||used
-uncommited||uncommitted
-unconditionaly||unconditionally
-underun||underrun
-unecessary||unnecessary
-unexecpted||unexpected
-unexepected||unexpected
-unexpcted||unexpected
-unexpectd||unexpected
-unexpeted||unexpected
-unexpexted||unexpected
-unfortunatelly||unfortunately
-unifiy||unify
-unintialized||uninitialized
-unkmown||unknown
-unknonw||unknown
-unknow||unknown
-unkown||unknown
-unneded||unneeded
-unneccecary||unnecessary
-unneccesary||unnecessary
-unneccessary||unnecessary
-unnecesary||unnecessary
-unneedingly||unnecessarily
-unnsupported||unsupported
-unmached||unmatched
-unregester||unregister
-unresgister||unregister
-unrgesiter||unregister
-unsinged||unsigned
-unstabel||unstable
-unsolicitied||unsolicited
-unsuccessfull||unsuccessful
-unsuported||unsupported
-untill||until
-unuseful||useless
-upate||update
-usefule||useful
-usefull||useful
-usege||usage
-usera||users
-usualy||usually
-utilites||utilities
-utillities||utilities
-utilties||utilities
-utiltity||utility
-utitity||utility
-utitlty||utility
-vaid||valid
-vaild||valid
-valide||valid
-variantions||variations
-varible||variable
-varient||variant
-vaule||value
-verbse||verbose
-verisons||versions
-verison||version
-verson||version
-vicefersa||vice-versa
-virtal||virtual
-virtaul||virtual
-virtiual||virtual
-visiters||visitors
-vitual||virtual
-wakeus||wakeups
-wating||waiting
-wiat||wait
-wether||whether
-whataver||whatever
-whcih||which
-whenver||whenever
-wheter||whether
-whe||when
-wierd||weird
-wiil||will
-wirte||write
-withing||within
-wnat||want
-workarould||workaround
-writeing||writing
-writting||writing
-zombe||zombie
-zomebie||zombie
diff --git a/scripts/xtensa-build-all.sh b/scripts/xtensa-build-all.sh
deleted file mode 100755
index abf4e87..0000000
--- a/scripts/xtensa-build-all.sh
+++ /dev/null
@@ -1,156 +0,0 @@
-#!/bin/bash
-
-SUPPORTED_PLATFORMS=(byt cht bdw hsw apl cnl)
-if [ "$#" -eq 0 ]
-then
- PLATFORMS=${SUPPORTED_PLATFORMS[@]}
-else
- # parse the args
- for args in $@
- do
- if [[ "$args" == "-l" ]]
- then
- BUILD_LOCAL=1
-
- # build all images for chosen targets
- if [ "$#" -eq 1 ]
- then
- PLATFORMS=${SUPPORTED_PLATFORMS[@]}
- break
- fi
- else
- for i in ${SUPPORTED_PLATFORMS[@]}
- do
- if [ $i == $args ]
- then
- PLATFORMS+=$i" "
- fi
- done
- fi
- done
-fi
-
-
-# now build the firmware (depends on rimage)
-rm -fr src/arch/xtensa/*.ri
-
-# fail on any errors
-set -e
-
-# run autogen.sh
-./autogen.sh
-
-pwd=`pwd`
-
-
-# make sure rimage is built and aligned with code
-if [[ "x$BUILD_LOCAL" == "x" ]]
-then
- ./configure --enable-rimage
- make
- sudo make install
-else
- echo "BUILD in local folder!"
- rm -rf $pwd/local/
- ./configure --enable-rimage --prefix=$pwd/local
- make
- make install
- PATH=$pwd/local/bin:$PATH
-fi
-
-OLDPATH=$PATH
-
-# build platform
-for j in ${PLATFORMS[@]}
-do
- if [ $j == "byt" ]
- then
- PLATFORM="baytrail"
- XTENSA_CORE="Intel_HiFiEP"
- ROOT="$pwd/../xtensa-root/xtensa-byt-elf"
- HOST="xtensa-byt-elf"
- XTENSA_TOOLS_VERSION="RD-2012.5-linux"
- fi
- if [ $j == "cht" ]
- then
- PLATFORM="cherrytrail"
- XTENSA_CORE="CHT_audio_hifiep"
- ROOT="$pwd/../xtensa-root/xtensa-byt-elf"
- HOST="xtensa-byt-elf"
- XTENSA_TOOLS_VERSION="RD-2012.5-linux"
- fi
- if [ $j == "bdw" ]
- then
- PLATFORM="broadwell"
- ROOT="$pwd/../xtensa-root/xtensa-hsw-elf"
- HOST="xtensa-hsw-elf"
- fi
- if [ $j == "hsw" ]
- then
- PLATFORM="haswell"
- ROOT="$pwd/../xtensa-root/xtensa-hsw-elf"
- HOST="xtensa-hsw-elf"
- fi
- if [ $j == "apl" ]
- then
- PLATFORM="apollolake"
- XTENSA_CORE="X4H3I16w2D48w3a_2017_8"
-
- # test APL compiler aliases and ignore set -e here
- type xtensa-bxt-elf-gcc > /dev/null 2>&1 && true
- if [ $? == 0 ]
- then
- HOST="xtensa-bxt-elf"
- else
- HOST="xtensa-apl-elf"
- fi
-
- ROOT="$pwd/../xtensa-root/$HOST"
- XTENSA_TOOLS_VERSION="RG-2017.8-linux"
- fi
- if [ $j == "cnl" ]
- then
- PLATFORM="cannonlake"
- XTENSA_CORE="X6H3CNL_2016_4_linux"
- ROOT="$pwd/../xtensa-root/xtensa-cnl-elf"
- HOST="xtensa-cnl-elf"
- XTENSA_TOOLS_VERSION="RF-2016.4-linux"
- fi
- if [ $XTENSA_TOOLS_ROOT ]
- then
- XTENSA_TOOLS_DIR="$XTENSA_TOOLS_ROOT/install/tools/$XTENSA_TOOLS_VERSION"
- XTENSA_BUILDS_DIR="$XTENSA_TOOLS_ROOT/install/builds/$XTENSA_TOOLS_VERSION"
-
- # make sure the required version of xtensa tools is installed
- if [ -d $XTENSA_TOOLS_DIR ]
- then
- XCC="xt-xcc"
- XTOBJCOPY="xt-objcopy"
- XTOBJDUMP="xt-objdump"
- else
- XCC="none"
- XTOBJCOPY="none"
- XTOBJDUMP="none"
- fi
- fi
-
- # update ROOT directory for xt-xcc
- if [ $XCC == "xt-xcc" ]
- then
- ROOT="$XTENSA_BUILDS_DIR/$XTENSA_CORE/xtensa-elf"
- export XTENSA_SYSTEM=$XTENSA_BUILDS_DIR/$XTENSA_CORE/config
- PATH=$XTENSA_TOOLS_DIR/XtensaTools/bin:$OLDPATH
- else
- PATH=$pwd/../$HOST/bin:$OLDPATH
- fi
-
- ./configure --with-arch=xtensa --with-platform=$PLATFORM --with-root-dir=$ROOT --host=$HOST \
- CC=$XCC OBJCOPY=$XTOBJCOPY OBJDUMP=$XTOBJDUMP --with-dsp-core=$XTENSA_CORE
-
- make clean
- make
- make bin
-done
-
-# list all the images
-ls -l src/arch/xtensa/*.ri
diff --git a/src/Makefile.am b/src/Makefile.am
deleted file mode 100644
index d864b36..0000000
--- a/src/Makefile.am
+++ /dev/null
@@ -1,12 +0,0 @@
-export COMMON_INCDIR = \
- $(PLATFORM_INCDIR) \
- $(SOF_INCDIR) \
- $(ARCH_INCDIR)
-
-if BUILD_LIB
-SUBDIRS = ipc math audio arch include library host
-endif
-
-if BUILD_XTENSA
-SUBDIRS = include init math audio platform tasks drivers ipc lib arch
-endif
diff --git a/src/arch/Makefile.am b/src/arch/Makefile.am
deleted file mode 100644
index 0662ebf..0000000
--- a/src/arch/Makefile.am
+++ /dev/null
@@ -1 +0,0 @@
-SUBDIRS = $(ARCH)
diff --git a/src/arch/host/Makefile.am b/src/arch/host/Makefile.am
deleted file mode 100644
index 7b92e00..0000000
--- a/src/arch/host/Makefile.am
+++ /dev/null
@@ -1 +0,0 @@
-SUBDIRS = include
diff --git a/src/arch/host/include/Makefile.am b/src/arch/host/include/Makefile.am
deleted file mode 100644
index f0ac9b7..0000000
--- a/src/arch/host/include/Makefile.am
+++ /dev/null
@@ -1 +0,0 @@
-SUBDIRS = arch
diff --git a/src/arch/host/include/arch/Makefile.am b/src/arch/host/include/arch/Makefile.am
deleted file mode 100644
index 08d859b..0000000
--- a/src/arch/host/include/arch/Makefile.am
+++ /dev/null
@@ -1,10 +0,0 @@
-includedir = $(prefix)/include/sof/arch
-
-include_HEADERS = \
- cache.h \
- interrupt.h \
- sof.h \
- spinlock.h \
- timer.h \
- string.h \
- wait.h
diff --git a/src/arch/host/include/arch/atomic.h b/src/arch/host/include/arch/atomic.h
deleted file mode 100644
index d9e9fad..0000000
--- a/src/arch/host/include/arch/atomic.h
+++ /dev/null
@@ -1,69 +0,0 @@
-/*
- * Copyright (c) 2018, Intel Corporation
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- * * Redistributions of source code must retain the above copyright
- * notice, this list of conditions and the following disclaimer.
- * * Redistributions in binary form must reproduce the above copyright
- * notice, this list of conditions and the following disclaimer in the
- * documentation and/or other materials provided with the distribution.
- * * Neither the name of the Intel Corporation nor the
- * names of its contributors may be used to endorse or promote products
- * derived from this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
- * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
- * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
- * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
- * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
- * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
- * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
- * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
- * POSSIBILITY OF SUCH DAMAGE.
- *
- * Author: Liam Girdwood <liam.r.girdwood@linux.intel.com>
- * Ranjani Sridharan <ranjani.sridharan@linux.intel.com>
- *
- */
-
-#ifndef __ARCH_ATOMIC_H_
-#define __ARCH_ATOMIC_H_
-
-#include <stdint.h>
-#include <errno.h>
-
-typedef struct {
- volatile int32_t value;
-} atomic_t;
-
-static inline int32_t arch_atomic_read(const atomic_t *a)
-{
- return (*(volatile int32_t *)&a->value);
-}
-
-static inline void arch_atomic_set(atomic_t *a, int32_t value)
-{
- a->value = value;
-}
-
-static inline void arch_atomic_init(atomic_t *a, int32_t value)
-{
- arch_atomic_set(a, value);
-}
-
-/* use gcc atomic built-ins for host library */
-static inline void arch_atomic_add(atomic_t *a, int32_t value)
-{
- __sync_fetch_and_add(&a->value, value);
-}
-
-static inline void arch_atomic_sub(atomic_t *a, int32_t value)
-{
- __sync_fetch_and_sub(&a->value, value);
-}
-
-#endif
diff --git a/src/arch/host/include/arch/cache.h b/src/arch/host/include/arch/cache.h
deleted file mode 100644
index e64a6c5..0000000
--- a/src/arch/host/include/arch/cache.h
+++ /dev/null
@@ -1,43 +0,0 @@
-/*
- * Copyright (c) 2017, Intel Corporation
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- * * Redistributions of source code must retain the above copyright
- * notice, this list of conditions and the following disclaimer.
- * * Redistributions in binary form must reproduce the above copyright
- * notice, this list of conditions and the following disclaimer in the
- * documentation and/or other materials provided with the distribution.
- * * Neither the name of the Intel Corporation nor the
- * names of its contributors may be used to endorse or promote products
- * derived from this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
- * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
- * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
- * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
- * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
- * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
- * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
- * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
- * POSSIBILITY OF SUCH DAMAGE.
- *
- * Author: Liam Girdwood <liam.r.girdwood@linux.intel.com>
- */
-
-#ifndef __INCLUDE_ARCH_CACHE__
-#define __INCLUDE_ARCH_CACHE__
-
-#include <stdint.h>
-#include <stddef.h>
-
-static inline void dcache_writeback_region(void *addr, size_t size) {}
-static inline void dcache_invalidate_region(void *addr, size_t size) {}
-static inline void icache_invalidate_region(void *addr, size_t size) {}
-static inline void dcache_writeback_invalidate_region(void *addr,
- size_t size) {}
-
-#endif
diff --git a/src/arch/host/include/arch/interrupt.h b/src/arch/host/include/arch/interrupt.h
deleted file mode 100644
index 15632aa..0000000
--- a/src/arch/host/include/arch/interrupt.h
+++ /dev/null
@@ -1,57 +0,0 @@
-/*
- * Copyright (c) 2016, Intel Corporation
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- * * Redistributions of source code must retain the above copyright
- * notice, this list of conditions and the following disclaimer.
- * * Redistributions in binary form must reproduce the above copyright
- * notice, this list of conditions and the following disclaimer in the
- * documentation and/or other materials provided with the distribution.
- * * Neither the name of the Intel Corporation nor the
- * names of its contributors may be used to endorse or promote products
- * derived from this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
- * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
- * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
- * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
- * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
- * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
- * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
- * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
- * POSSIBILITY OF SUCH DAMAGE.
- *
- * Author: Liam Girdwood <liam.r.girdwood@linux.intel.com>
- *
- */
-
-#ifndef __ARCH_INTERRUPT_H
-#define __ARCH_INTERRUPT_H
-
-#include <sof/interrupt-map.h>
-#include <stdint.h>
-#include <stdlib.h>
-#include <unistd.h>
-#include <pthread.h>
-
-#define PLATFORM_IRQ_CHILDREN 0
-
-static inline int arch_interrupt_register(int irq,
- void (*handler)(void *arg), void *arg) {return 0; }
-static inline void arch_interrupt_unregister(int irq) {}
-static inline uint32_t arch_interrupt_enable_mask(uint32_t mask) {return 0; }
-static inline uint32_t arch_interrupt_disable_mask(uint32_t mask) {return 0; }
-static inline uint32_t arch_interrupt_get_level(void) { return 0; }
-static inline void arch_interrupt_set(int irq) {}
-static inline void arch_interrupt_clear(int irq) {}
-static inline uint32_t arch_interrupt_get_enabled(void) {return 0; }
-static inline uint32_t arch_interrupt_get_status(void) {return 0; }
-static inline uint32_t arch_interrupt_global_disable(void) {return 0; }
-static inline void arch_interrupt_global_enable(uint32_t flags) {}
-static inline int arch_interrupt_init(void) {return 0; }
-
-#endif
diff --git a/src/arch/host/include/arch/sof.h b/src/arch/host/include/arch/sof.h
deleted file mode 100644
index ce2bd69..0000000
--- a/src/arch/host/include/arch/sof.h
+++ /dev/null
@@ -1,70 +0,0 @@
-/*
- * Copyright (c) 2016, Intel Corporation
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- * * Redistributions of source code must retain the above copyright
- * notice, this list of conditions and the following disclaimer.
- * * Redistributions in binary form must reproduce the above copyright
- * notice, this list of conditions and the following disclaimer in the
- * documentation and/or other materials provided with the distribution.
- * * Neither the name of the Intel Corporation nor the
- * names of its contributors may be used to endorse or promote products
- * derived from this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
- * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
- * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
- * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
- * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
- * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
- * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
- * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
- * POSSIBILITY OF SUCH DAMAGE.
- *
- * Author: Liam Girdwood <liam.r.girdwood@linux.intel.com>
- *
- */
-
-#ifndef __INCLUDE_ARCH_SOF__
-#define __INCLUDE_ARCH_SOF__
-
-#include <stdint.h>
-#include <stdlib.h>
-#include <stddef.h>
-#include <string.h>
-#include <stdio.h>
-#include <execinfo.h>
-
-/* architecture specific stack frames to dump */
-#define ARCH_STACK_DUMP_FRAMES 32
-
-static inline void *arch_get_stack_ptr(void)
-{
- void *frames[ARCH_STACK_DUMP_FRAMES];
- size_t frame_count;
- size_t i;
- char **symbols;
-
- frame_count = backtrace(frames, ARCH_STACK_DUMP_FRAMES);
- symbols = backtrace_symbols(frames, frame_count);
-
- fprintf(stderr, "Dumping %zd stack frames.\n", frame_count);
-
- for (i = 0; i < frame_count; i++)
- fprintf(stderr, "\t%s\n", symbols[i]);
-
- free(symbols);
-
- return NULL;
-}
-
-static inline void *arch_dump_regs(void)
-{
- return NULL;
-}
-
-#endif
diff --git a/src/arch/host/include/arch/spinlock.h b/src/arch/host/include/arch/spinlock.h
deleted file mode 100644
index ea59769..0000000
--- a/src/arch/host/include/arch/spinlock.h
+++ /dev/null
@@ -1,46 +0,0 @@
-/*
- * Copyright (c) 2016, Intel Corporation
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- * * Redistributions of source code must retain the above copyright
- * notice, this list of conditions and the following disclaimer.
- * * Redistributions in binary form must reproduce the above copyright
- * notice, this list of conditions and the following disclaimer in the
- * documentation and/or other materials provided with the distribution.
- * * Neither the name of the Intel Corporation nor the
- * names of its contributors may be used to endorse or promote products
- * derived from this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
- * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
- * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
- * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
- * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
- * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
- * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
- * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
- * POSSIBILITY OF SUCH DAMAGE.
- *
- * Author: Liam Girdwood <liam.r.girdwood@linux.intel.com>
- *
- */
-
-#ifndef __ARCH_SPINLOCK_H_
-#define __ARCH_SPINLOCK_H_
-
-#include <stdint.h>
-#include <errno.h>
-#include <pthread.h>
-
-typedef struct {
-} spinlock_t;
-
-static inline void arch_spinlock_init(spinlock_t *lock) {}
-static inline void arch_spin_lock(spinlock_t *lock) {}
-static inline void arch_spin_unlock(spinlock_t *lock) {}
-
-#endif
diff --git a/src/arch/host/include/arch/string.h b/src/arch/host/include/arch/string.h
deleted file mode 100644
index 6b2755d..0000000
--- a/src/arch/host/include/arch/string.h
+++ /dev/null
@@ -1,38 +0,0 @@
-/*
- * Copyright (c) 2018, Intel Corporation
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- * * Redistributions of source code must retain the above copyright
- * notice, this list of conditions and the following disclaimer.
- * * Redistributions in binary form must reproduce the above copyright
- * notice, this list of conditions and the following disclaimer in the
- * documentation and/or other materials provided with the distribution.
- * * Neither the name of the Intel Corporation nor the
- * names of its contributors may be used to endorse or promote products
- * derived from this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
- * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
- * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
- * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
- * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
- * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
- * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
- * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
- * POSSIBILITY OF SUCH DAMAGE.
- *
- * Author: Liam Girdwood <liam.r.girdwood@linux.intel.com>
- *
- */
-
-#ifndef __INCLUDE_ARCH_STRING_SOF__
-#define __INCLUDE_ARCH_STRING_SOF__
-
-#define arch_memcpy(dest, src, size) \
- memcpy(dest, src, size)
-
-#endif
diff --git a/src/arch/host/include/arch/timer.h b/src/arch/host/include/arch/timer.h
deleted file mode 100644
index c650da3..0000000
--- a/src/arch/host/include/arch/timer.h
+++ /dev/null
@@ -1,52 +0,0 @@
-/*
- * Copyright (c) 2016, Intel Corporation
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- * * Redistributions of source code must retain the above copyright
- * notice, this list of conditions and the following disclaimer.
- * * Redistributions in binary form must reproduce the above copyright
- * notice, this list of conditions and the following disclaimer in the
- * documentation and/or other materials provided with the distribution.
- * * Neither the name of the Intel Corporation nor the
- * names of its contributors may be used to endorse or promote products
- * derived from this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
- * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
- * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
- * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
- * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
- * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
- * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
- * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
- * POSSIBILITY OF SUCH DAMAGE.
- *
- * Author: Liam Girdwood <liam.r.girdwood@linux.intel.com>
- *
- */
-
-#ifndef __ARCH_TIMER_H_
-#define __ARCH_TIMER_H_
-
-#include <arch/interrupt.h>
-#include <stdint.h>
-#include <errno.h>
-
-struct timer {
-};
-
-static inline int arch_timer_register(struct timer *timer,
- void (*handler)(void *arg), void *arg) {return 0; }
-static inline void arch_timer_unregister(struct timer *timer) {}
-static inline void arch_timer_enable(struct timer *timer) {}
-static inline void arch_timer_disable(struct timer *timer) {}
-static inline uint32_t arch_timer_get_system(struct timer *timer) {return 0; }
-static inline int arch_timer_set(struct timer *timer,
- uint64_t ticks) {return 0; }
-static inline void arch_timer_clear(struct timer *timer) {}
-
-#endif
diff --git a/src/arch/host/include/arch/wait.h b/src/arch/host/include/arch/wait.h
deleted file mode 100644
index e1e23a1..0000000
--- a/src/arch/host/include/arch/wait.h
+++ /dev/null
@@ -1,34 +0,0 @@
-/*
- * Copyright (c) 2017, Intel Corporation
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- * * Redistributions of source code must retain the above copyright
- * notice, this list of conditions and the following disclaimer.
- * * Redistributions in binary form must reproduce the above copyright
- * notice, this list of conditions and the following disclaimer in the
- * documentation and/or other materials provided with the distribution.
- * * Neither the name of the Intel Corporation nor the
- * names of its contributors may be used to endorse or promote products
- * derived from this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
- * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
- * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
- * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
- * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
- * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
- * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
- * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
- * POSSIBILITY OF SUCH DAMAGE.
- *
- * Author: Liam Girdwood <liam.r.girdwood@linux.intel.com>
- */
-
-static inline void arch_wait_for_interrupt(int level) {}
-
-static inline void idelay(int n) {}
-
diff --git a/src/arch/xtensa/Makefile.am b/src/arch/xtensa/Makefile.am
deleted file mode 100644
index c119f14..0000000
--- a/src/arch/xtensa/Makefile.am
+++ /dev/null
@@ -1,235 +0,0 @@
-if BUILD_XTENSA_SMP
-SUBDIRS = smp include
-else
-SUBDIRS = up include
-endif
-
-noinst_PROGRAMS = \
- sof
-
-# generate linker script from platform headers
-LINK_SCRIPT = ../../platform/$(PLATFORM)/$(PLATFORM_LDSCRIPT)
-
-LINK_DEPS = ../../platform/$(PLATFORM)/include/platform/memory.h
-
-if XCC
-LINK_DEPS += \
- $(ROOT_DIR)/arch/include/xtensa/config/core-isa*
-else
-LINK_DEPS += \
- ../../platform/$(PLATFORM)/include/arch/xtensa/config/core-isa*
-endif
-
-nodist_sof_SOURCES = $(LINK_SCRIPT).in
-BUILT_SOURCES = $(LINK_SCRIPT)
-CLEANFILES = $(LINK_SCRIPT)
-$(LINK_SCRIPT): Makefile $(LINK_SCRIPT).in $(LINK_DEPS)
- cat $(LINK_SCRIPT).in | $(CPP) -P $(PLATFORM_INCDIR) $(SOF_INCDIR) - >$@
-
-noinst_LIBRARIES = \
- libreset.a
-
-if BUILD_XTENSA_SMP
-libreset_a_SOURCES = \
- smp/xtos/memctl_default.S \
- smp/xtos/reset-vector.S
-else
-libreset_a_SOURCES = \
- up/xtos/reset-vector.S
-endif
-
-libreset_a_CCASFLAGS = \
- $(ARCH_INCDIR) \
- $(ASFLAGS) \
- $(AM_CCASFLAGS) \
- $(PLATFORM_INCDIR) \
- -mtext-section-literals
-
-sof_SOURCES = \
- timer.c
-
-if BUILD_XTENSA_SMP
-sof_SOURCES += \
- smp/xtos/crt1-boards.S \
- smp/xtos/_vectors.S \
- smp/cpu.c \
- smp/init.c \
- smp/schedule.c \
- smp/task.c
-else
-sof_SOURCES += \
- up/xtos/crt1-boards.S \
- up/xtos/_vectors.S \
- up/cpu.c \
- up/init.c \
- up/schedule.c \
- up/task.c
-endif
-
-if BUILD_BOOTLOADER
-sof_SOURCES += \
- main-entry.S
-endif
-
-sof_CFLAGS = \
- $(ARCH_INCDIR) \
- $(AM_CFLAGS) \
- $(ARCH_CFLAGS) \
- $(PLATFORM_INCDIR) \
- $(SOF_INCDIR)
-
-sof_CCASFLAGS = \
- $(ARCH_INCDIR) \
- $(ASFLAGS) \
- $(AM_CCASFLAGS) \
- $(PLATFORM_INCDIR)
-
-sof_LDADD = \
- ../../init/libinit.a \
- ../../tasks/libtasks.a \
- ../../lib/libcore.a \
- ../../platform/$(PLATFORM)/libplatform.la \
- ../../ipc/libsof_ipc.a \
- ../../lib/libdma.a \
- ../../audio/libaudio.a \
- ../../drivers/libdrivers.a \
- ../../math/libsof_math.a \
- -lgcc
-
-if BUILD_XTENSA_SMP
-sof_LDADD += \
- smp/xtos/libxtos.a \
- smp/xtos/libxlevel2.a \
- smp/xtos/libxlevel3.a \
- smp/xtos/libxlevel4.a \
- smp/xtos/libxlevel5.a \
- smp/hal/libhal.a
-else
-sof_LDADD += \
- up/xtos/libxtos.a \
- up/xtos/libxlevel2.a \
- up/xtos/libxlevel3.a \
- up/xtos/libxlevel4.a \
- up/xtos/libxlevel5.a \
- up/hal/libhal.a
-endif
-
-if !BUILD_BOOTLOADER
-sof_LDADD += \
- libreset.a
-endif
-
-sof_LDFLAGS = \
- $(AM_LDFLAGS) \
- $(ARCH_LDFLAGS) -Wl,-Map=sof-$(FW_NAME).map \
- -T ../../platform/$(PLATFORM)/$(PLATFORM_LDSCRIPT)
-
-RIMAGE_FLAGS = sof-$(FW_NAME)
-RIMAGE_BOOT_FLAGS =
-BIN_FLAGS = sof
-
-if BUILD_BOOTLOADER
-
-noinst_PROGRAMS += \
- boot_ldr
-
-LINK_BOOT_LDR_SCRIPT = ../../platform/$(PLATFORM)/$(PLATFORM_BOOT_LDR_LDSCRIPT)
-BUILT_SOURCES += $(LINK_BOOT_LDR_SCRIPT)
-CLEANFILES += $(LINK_BOOT_LDR_SCRIPT)
-
-nodist_boot_ldr_SOURCES = $(LINK_BOOT_LDR_SCRIPT).in
-$(LINK_BOOT_LDR_SCRIPT): Makefile $(LINK_BOOT_LDR_SCRIPT).in $(LINK_DEPS)
- cat $(LINK_BOOT_LDR_SCRIPT).in | $(CPP) -P $(PLATFORM_INCDIR) $(SOF_INCDIR) - >$@
-
-boot_ldr_SOURCES = \
- boot_entry.S \
- boot_loader.c
-
-if BUILD_XTENSA_SMP
-boot_ldr_SOURCES += \
- smp/xtos/_vectors.S
-else
-boot_ldr_SOURCES += \
- up/xtos/_vectors.S
-endif
-
-boot_ldr_CFLAGS = \
- $(ARCH_INCDIR) \
- $(AM_CFLAGS) \
- $(ARCH_CFLAGS) \
- $(PLATFORM_INCDIR) \
- $(SOF_INCDIR)
-
-boot_ldr_CCASFLAGS = \
- $(ARCH_INCDIR) \
- $(ASFLAGS) \
- $(AM_CCASFLAGS) \
- $(PLATFORM_INCDIR)
-
-boot_ldr_LDADD = \
- libreset.a \
- -lgcc
-
-if BUILD_XTENSA_SMP
-boot_ldr_LDADD += \
- smp/hal/libhal.a
-else
-boot_ldr_LDADD += \
- up/hal/libhal.a
-endif
-
-boot_ldr_LDFLAGS = \
- $(AM_LDFLAGS) \
- $(ARCH_LDFLAGS) \
- -T ../../platform/$(PLATFORM)/$(PLATFORM_BOOT_LDR_LDSCRIPT)
-
-boot_ldr-local:
- cp boot_ldr boot_ldr-$(FW_NAME)
- $(OBJCOPY) -O binary ../../platform/$(PLATFORM)/boot_module mod-boot-$(FW_NAME).bin
- $(OBJCOPY) --add-section .module=mod-boot-$(FW_NAME).bin \
- --set-section-flags .module=load,readonly boot_ldr-$(FW_NAME)
- $(OBJCOPY) -O binary boot_ldr boot_ldr-$(FW_NAME).bin
- $(OBJDUMP) -h -D boot_ldr > boot_ldr-$(FW_NAME).map
- $(OBJDUMP) -S boot_ldr > boot_ldr-$(FW_NAME).lst
- $(OBJDUMP) -D boot_ldr > boot_ldr-$(FW_NAME).dis
-
-RIMAGE_BOOT_FLAGS += boot_ldr-$(FW_NAME)
-BIN_FLAGS +=boot_ldr-local
-endif
-
-if BUILD_MODULE
-MODULE_COPY=$(OBJCOPY) -O binary ../../platform/$(PLATFORM)/module mod-$(FW_NAME).bin
-MODULE_INSERT=$(OBJCOPY) --add-section .module=mod-$(FW_NAME).bin \
- --set-section-flags .module=load,readonly sof-$(FW_NAME)
-else
-MODULE_COPY=
-MODULE_INSERT=
-endif
-
-if USE_MEU
-RIMAGE=rimage -o sof-$(FW_NAME).ri -m $(FW_NAME) $(RIMAGE_BOOT_FLAGS) $(RIMAGE_FLAGS) -s $(MEU_OFFSET)
-MEU=$(MEU_PATH)/meu -w ./ -s sof-$(FW_NAME) -key $(PRIVATE_KEY) -stp /usr/bin/openssl -f $(MEU_PATH)/generic_meu_conf.xml \
- -mnver 0.0.0.0 -o sof-$(FW_NAME).ri
-else
-RIMAGE=rimage -o sof-$(FW_NAME).ri -m $(FW_NAME) $(RIMAGE_BOOT_FLAGS) $(RIMAGE_FLAGS)
-MEU=
-endif
-
-bin-local: $(BIN_FLAGS)
- cp sof sof-$(FW_NAME)
- $(MODULE_COPY)
- $(MODULE_INSERT)
- $(OBJDUMP) -S sof-$(FW_NAME) > sof-$(FW_NAME).lst
- $(OBJDUMP) -D sof-$(FW_NAME) > sof-$(FW_NAME).dis
- $(RIMAGE)
- $(MEU)
-
-vminstall-local:
- scp -P 5555 sof-*.ri root@localhost:/lib/firmware/intel/
-
-clean-local:
- rm -fr mod-*
- rm -fr *.bin
- rm -fr *.lst
- rm -fr *.map
- rm -fr *.dis
diff --git a/src/arch/xtensa/boot_entry.S b/src/arch/xtensa/boot_entry.S
deleted file mode 100644
index f00155c..0000000
--- a/src/arch/xtensa/boot_entry.S
+++ /dev/null
@@ -1,164 +0,0 @@
-/*
- * Copyright (c) 2016, Intel Corporation
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- * * Redistributions of source code must retain the above copyright
- * notice, this list of conditions and the following disclaimer.
- * * Redistributions in binary form must reproduce the above copyright
- * notice, this list of conditions and the following disclaimer in the
- * documentation and/or other materials provided with the distribution.
- * * Neither the name of the Intel Corporation nor the
- * names of its contributors may be used to endorse or promote products
- * derived from this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
- * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
- * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
- * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
- * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
- * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
- * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
- * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
- * POSSIBILITY OF SUCH DAMAGE.
- *
- * Author: Liam Girdwood <liam.r.girdwood@linux.intel.com>
- */
-
-/*
- * Entry point from ROM - assumes :-
- *
- * 1) C runtime environment is initalised by ROM.
- * 2) Stack is in first HPSRAM bank.
- */
-
-#include <config.h>
-#include <platform/shim.h>
-#include <platform/platcfg.h>
-#include <xtensa/corebits.h>
-#include <xtensa/config/core-isa.h>
-
- .type boot_master_core, @function
-
- .begin literal_prefix .boot_entry
- .section .boot_entry.text, "ax"
-
- .align 4
- .global boot_entry
-
-boot_entry:
- entry a1, 48
- j boot_init
-
- .align 4
- .literal_position
-#if defined(PLATFORM_RESET_MHE_AT_BOOT)
-l2_mecs:
- .word SHIM_L2_MECS
-#endif
-
-#if defined(PLATFORM_DISABLE_L2CACHE_AT_BOOT)
-l2_cache_pref:
- .word SHIM_L2_PREF_CFG
-#endif
-
-sof_stack_base:
- .word SOF_STACK_BASE
-
-wnd0_base:
- .word DMWBA(0)
-
-wnd0_size:
- .word DMWLO(0)
-
-wnd0_base_val:
- .word HP_SRAM_WIN0_BASE | DMWBA_READONLY | DMWBA_ENABLE
-
-wnd0_size_val:
- .word HP_SRAM_WIN0_SIZE | 0x7
-
-wnd0_status_address:
- .word HP_SRAM_WIN0_BASE
-
-wnd0_error_address:
- .word HP_SRAM_WIN0_BASE | 0x4
-
-fw_loaded_status_value:
- .word 0x00000005
-
-fw_no_errors_value:
- .word 0x00000000
-
-boot_init:
- .align 4
-#if defined(PLATFORM_DISABLE_L2CACHE_AT_BOOT)
- l32r a3, l2_cache_pref
- movi a5, 0
- s32i a5, a3, 0
- memw
-#endif
-
-#if defined(PLATFORM_RESET_MHE_AT_BOOT)
- /* reset memory hole */
- l32r a3, l2_mecs
- movi a5, 0
- s32i a5, a3, 0
-#endif
-
- /* reprogram stack to the area defined by main FW */
- l32r a3, sof_stack_base
- mov sp, a3
-
- /* set status register to 0x00000005 in wnd0 */
- l32r a3, fw_loaded_status_value
- l32r a5, wnd0_status_address
- s32i a3, a5, 0
-
- /* set error register to 0x00 in wnd0 */
- l32r a3, fw_no_errors_value
- l32r a5, wnd0_error_address
- s32i a3, a5, 0
-
- /* realloc memory window0 to
- continue reporting boot progress */
- l32r a3, wnd0_size
- l32r a5, wnd0_size_val
- s32i a5, a3, 0
- memw
- l32r a3, wnd0_base
- l32r a5, wnd0_base_val
- s32i a5, a3, 0
- memw
-
-#if (XCHAL_DCACHE_IS_COHERENT || XCHAL_LOOP_BUFFER_SIZE) && \
- XCHAL_HW_MIN_VERSION >= XTENSA_HWVERSION_RE_2012_0
- /* Enable zero-overhead loop instr buffer,
- and snoop responses, if configured. */
- movi a3, (MEMCTL_SNOOP_EN | MEMCTL_L0IBUF_EN)
- rsr a2, MEMCTL
- or a2, a2, a3
- wsr a2, MEMCTL
-#endif
-
- /* determine core we are running on */
- rsr.prid a2
- movi a3, PLATFORM_MASTER_CORE_ID
- beq a2, a3, 1f
-
- /* no core should get here */
- j dead
-
-1:
- /* we are primary core so boot it */
- call8 boot_master_core
-
-dead:
- /* should never get here - we are dead */
- j dead
-
- .size boot_entry, . - boot_entry
-
- .end literal_prefix
diff --git a/src/arch/xtensa/boot_loader.c b/src/arch/xtensa/boot_loader.c
deleted file mode 100644
index 448f51b..0000000
--- a/src/arch/xtensa/boot_loader.c
+++ /dev/null
@@ -1,198 +0,0 @@
-/*
- * Copyright (c) 2016, Intel Corporation
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- * * Redistributions of source code must retain the above copyright
- * notice, this list of conditions and the following disclaimer.
- * * Redistributions in binary form must reproduce the above copyright
- * notice, this list of conditions and the following disclaimer in the
- * documentation and/or other materials provided with the distribution.
- * * Neither the name of the Intel Corporation nor the
- * names of its contributors may be used to endorse or promote products
- * derived from this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
- * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
- * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
- * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
- * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
- * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
- * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
- * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
- * POSSIBILITY OF SUCH DAMAGE.
- *
- * Author: Liam Girdwood <liam.r.girdwood@linux.intel.com>
- */
-
-#include <arch/cache.h>
-#include <arch/wait.h>
-#include <sof/trace.h>
-#include <sof/io.h>
-#include <uapi/manifest.h>
-#include <platform/platform.h>
-#include <platform/memory.h>
-
-/* entry point to main firmware */
-extern void _ResetVector(void);
-
-void boot_master_core(void);
-
-#if defined(CONFIG_BOOT_LOADER)
-
-/* memcopy used by boot loader */
-static inline void bmemcpy(void *dest, void *src, size_t bytes)
-{
- uint32_t *d = dest;
- uint32_t *s = src;
- int i;
-
- for (i = 0; i < (bytes >> 2); i++)
- d[i] = s[i];
-
- dcache_writeback_region(dest, bytes);
-}
-
-/* bzero used by bootloader */
-static inline void bbzero(void *dest, size_t bytes)
-{
- uint32_t *d = dest;
- int i;
-
- for (i = 0; i < (bytes >> 2); i++)
- d[i] = 0;
-
- dcache_writeback_region(dest, bytes);
-}
-
-static void parse_module(struct sof_man_fw_header *hdr,
- struct sof_man_module *mod)
-{
- int i;
- uint32_t bias;
-
- /* each module has 3 segments */
- for (i = 0; i < 3; i++) {
-
- platform_trace_point(TRACE_BOOT_LDR_PARSE_SEGMENT + i);
- switch (mod->segment[i].flags.r.type) {
- case SOF_MAN_SEGMENT_TEXT:
- case SOF_MAN_SEGMENT_DATA:
- bias = (mod->segment[i].file_offset -
- SOF_MAN_ELF_TEXT_OFFSET);
-
- /* copy from IMR to SRAM */
- bmemcpy((void *)mod->segment[i].v_base_addr,
- (void *)((int)hdr + bias),
- mod->segment[i].flags.r.length * HOST_PAGE_SIZE);
- break;
- case SOF_MAN_SEGMENT_BSS:
- /* copy from IMR to SRAM */
- bbzero((void*)mod->segment[i].v_base_addr,
- mod->segment[i].flags.r.length * HOST_PAGE_SIZE);
- break;
- default:
- /* ignore */
- break;
- }
- }
-}
-
-/* parse FW manifest and copy modules */
-static void parse_manifest(void)
-{
- struct sof_man_fw_desc *desc =
- (struct sof_man_fw_desc *)IMR_BOOT_LDR_MANIFEST_BASE;
- struct sof_man_fw_header *hdr = &desc->header;
- struct sof_man_module *mod;
- int i;
-
- /* copy module to SRAM - skip bootloader module */
- for (i = 1; i < hdr->num_module_entries; i++) {
-
- platform_trace_point(TRACE_BOOT_LDR_PARSE_MODULE + i);
- mod = sof_man_get_module(desc, i);
- parse_module(hdr, mod);
- }
-}
-#endif
-
-/* power on HPSRAM */
-#if defined(CONFIG_CANNONLAKE)
-static int32_t hp_sram_init(void)
-{
- int delay_count = 256;
- uint32_t status;
-
- shim_write(SHIM_LDOCTL, SHIM_HPMEM_POWER_ON);
-
- /* add some delay before touch power register */
- idelay(delay_count);
-
- /* now all the memory bank has been powered up */
- io_reg_write(HSPGCTL0, 0);
- io_reg_write(HSRMCTL0, 0);
- io_reg_write(HSPGCTL1, 0);
- io_reg_write(HSRMCTL1, 0);
-
- /* query the power status of first part of HP memory */
- /* to check whether it has been powered up. A few */
- /* cycles are needed for it to be powered up */
- status = io_reg_read(HSPGISTS0);
- while (status) {
- idelay(delay_count);
- status = io_reg_read(HSPGISTS0);
- }
-
- /* query the power status of second part of HP memory */
- /* and do as above code */
- status = io_reg_read(HSPGISTS1);
- while (status) {
- idelay(delay_count);
- status = io_reg_read(HSPGISTS1);
- }
-
- /* add some delay before touch power register */
- idelay(delay_count);
- shim_write(SHIM_LDOCTL, SHIM_LPMEM_POWER_BYPASS);
-
- return 0;
-}
-#endif
-
-#if defined(CONFIG_APOLLOLAKE)
-static uint32_t hp_sram_init(void)
-{
- return 0;
-}
-#endif
-
-/* boot master core */
-void boot_master_core(void)
-{
- int32_t result;
-
- /* TODO: platform trace should write to HW IPC regs on CNL */
- platform_trace_point(TRACE_BOOT_LDR_ENTRY);
-
- /* init the HPSRAM */
- platform_trace_point(TRACE_BOOT_LDR_HPSRAM);
- result = hp_sram_init();
- if (result < 0) {
- platform_panic(SOF_IPC_PANIC_MEM);
- return;
- }
-
-#if defined(CONFIG_BOOT_LOADER)
- /* parse manifest and copy modules */
- platform_trace_point(TRACE_BOOT_LDR_MANIFEST);
- parse_manifest();
-#endif
-
- /* now call SOF entry */
- platform_trace_point(TRACE_BOOT_LDR_JUMP);
- _ResetVector();
-}
diff --git a/src/arch/xtensa/include/Makefile.am b/src/arch/xtensa/include/Makefile.am
deleted file mode 100644
index b2e07bf..0000000
--- a/src/arch/xtensa/include/Makefile.am
+++ /dev/null
@@ -1 +0,0 @@
-SUBDIRS = arch xtensa
diff --git a/src/arch/xtensa/include/arch/Makefile.am b/src/arch/xtensa/include/arch/Makefile.am
deleted file mode 100644
index 0d969cc..0000000
--- a/src/arch/xtensa/include/arch/Makefile.am
+++ /dev/null
@@ -1,11 +0,0 @@
-noinst_HEADERS = \
- atomic.h \
- cache.h \
- init.h \
- interrupt.h \
- sof.h \
- spinlock.h \
- task.h \
- timer.h \
- string.h \
- wait.h
diff --git a/src/arch/xtensa/include/arch/atomic.h b/src/arch/xtensa/include/arch/atomic.h
deleted file mode 100644
index aadc6db..0000000
--- a/src/arch/xtensa/include/arch/atomic.h
+++ /dev/null
@@ -1,87 +0,0 @@
-/*
- * Copyright (c) 2018, Intel Corporation
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- * * Redistributions of source code must retain the above copyright
- * notice, this list of conditions and the following disclaimer.
- * * Redistributions in binary form must reproduce the above copyright
- * notice, this list of conditions and the following disclaimer in the
- * documentation and/or other materials provided with the distribution.
- * * Neither the name of the Intel Corporation nor the
- * names of its contributors may be used to endorse or promote products
- * derived from this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
- * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
- * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
- * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
- * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
- * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
- * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
- * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
- * POSSIBILITY OF SUCH DAMAGE.
- *
- * Author: Liam Girdwood <liam.r.girdwood@linux.intel.com>
- *
- */
-
-#ifndef __ARCH_ATOMIC_H_
-#define __ARCH_ATOMIC_H_
-
-#include <stdint.h>
-#include <errno.h>
-
-typedef struct {
- volatile int32_t value;
-} atomic_t;
-
-static inline int32_t arch_atomic_read(const atomic_t *a)
-{
- return (*(volatile int32_t *)&a->value);
-}
-
-static inline void arch_atomic_set(atomic_t *a, int32_t value)
-{
- a->value = value;
-}
-
-static inline void arch_atomic_init(atomic_t *a, int32_t value)
-{
- arch_atomic_set(a, value);
-}
-
-static inline void arch_atomic_add(atomic_t *a, int32_t value)
-{
- int32_t result, current;
-
- __asm__ __volatile__(
- "1: l32i %1, %2, 0\n"
- " wsr %1, scompare1\n"
- " add %0, %1, %3\n"
- " s32c1i %0, %2, 0\n"
- " bne %0, %1, 1b\n"
- : "=&a" (result), "=&a" (current)
- : "a" (&a->value), "a" (value)
- : "memory");
-}
-
-static inline void arch_atomic_sub(atomic_t *a, int32_t value)
-{
- int32_t result, current;
-
- __asm__ __volatile__(
- "1: l32i %1, %2, 0\n"
- " wsr %1, scompare1\n"
- " sub %0, %1, %3\n"
- " s32c1i %0, %2, 0\n"
- " bne %0, %1, 1b\n"
- : "=&a" (result), "=&a" (current)
- : "a" (&a->value), "a" (value)
- : "memory");
-}
-
-#endif
diff --git a/src/arch/xtensa/include/arch/cache.h b/src/arch/xtensa/include/arch/cache.h
deleted file mode 100644
index a0f02b0..0000000
--- a/src/arch/xtensa/include/arch/cache.h
+++ /dev/null
@@ -1,96 +0,0 @@
-/*
- * Copyright (c) 2017, Intel Corporation
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- * * Redistributions of source code must retain the above copyright
- * notice, this list of conditions and the following disclaimer.
- * * Redistributions in binary form must reproduce the above copyright
- * notice, this list of conditions and the following disclaimer in the
- * documentation and/or other materials provided with the distribution.
- * * Neither the name of the Intel Corporation nor the
- * names of its contributors may be used to endorse or promote products
- * derived from this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
- * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
- * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
- * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
- * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
- * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
- * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
- * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
- * POSSIBILITY OF SUCH DAMAGE.
- *
- * Author: Liam Girdwood <liam.r.girdwood@linux.intel.com>
- */
-
-#ifndef __INCLUDE_ARCH_CACHE__
-#define __INCLUDE_ARCH_CACHE__
-
-#include <stdint.h>
-#include <stddef.h>
-#include <xtensa/config/core.h>
-#include <xtensa/hal.h>
-
-static inline void dcache_writeback_region(void *addr, size_t size)
-{
-#if XCHAL_DCACHE_SIZE > 0
- xthal_dcache_region_writeback(addr, size);
-#endif
-}
-
-static inline void dcache_writeback_all()
-{
-#if XCHAL_DCACHE_SIZE > 0
- xthal_dcache_all_writeback();
-#endif
-}
-
-static inline void dcache_invalidate_region(void *addr, size_t size)
-{
-#if XCHAL_DCACHE_SIZE > 0
- xthal_dcache_region_invalidate(addr, size);
-#endif
-}
-
-static inline void dcache_invalidate_all()
-{
-#if XCHAL_DCACHE_SIZE > 0
- xthal_dcache_all_invalidate();
-#endif
-}
-
-static inline void icache_invalidate_region(void *addr, size_t size)
-{
-#if XCHAL_ICACHE_SIZE > 0
- xthal_icache_region_invalidate(addr, size);
-#endif
-}
-
-static inline void icache_invalidate_all()
-{
-#if XCHAL_ICACHE_SIZE > 0
- xthal_icache_all_invalidate();
-#endif
-}
-
-static inline void dcache_writeback_invalidate_region(void *addr, size_t size)
-{
-#if XCHAL_DCACHE_SIZE > 0
- xthal_dcache_region_writeback_inv(addr, size);
-#endif
-}
-
-static inline void dcache_writeback_invalidate_all()
-{
-#if XCHAL_DCACHE_SIZE > 0
- xthal_dcache_all_writeback_inv();
-#endif
-}
-
-#endif
-
diff --git a/src/arch/xtensa/include/arch/cpu.h b/src/arch/xtensa/include/arch/cpu.h
deleted file mode 100644
index 982c14d..0000000
--- a/src/arch/xtensa/include/arch/cpu.h
+++ /dev/null
@@ -1,77 +0,0 @@
-/*
- * Copyright (c) 2018, Intel Corporation
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- * * Redistributions of source code must retain the above copyright
- * notice, this list of conditions and the following disclaimer.
- * * Redistributions in binary form must reproduce the above copyright
- * notice, this list of conditions and the following disclaimer in the
- * documentation and/or other materials provided with the distribution.
- * * Neither the name of the Intel Corporation nor the
- * names of its contributors may be used to endorse or promote products
- * derived from this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
- * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
- * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
- * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
- * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
- * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
- * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
- * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
- * POSSIBILITY OF SUCH DAMAGE.
- *
- * Author: Rander Wang <rander.wang@linux.intel.com>
- *
- */
-
-#ifndef __INCLUDE_ARCH_CPU__
-#define __INCLUDE_ARCH_CPU__
-
-#include <xtensa/config/core.h>
-#include <platform/platcfg.h>
-
-void arch_cpu_enable_core(int id);
-
-void arch_cpu_disable_core(int id);
-
-int arch_cpu_is_core_enabled(int id);
-
-static inline int arch_cpu_get_id(void)
-{
- int prid;
-#if XCHAL_HAVE_PRID
- __asm__("rsr.prid %0" : "=a"(prid));
-#else
- prid = PLATFORM_MASTER_CORE_ID;
-#endif
- return prid;
-}
-
-static inline void cpu_write_threadptr(int threadptr)
-{
-#if XCHAL_HAVE_THREADPTR
- __asm__ __volatile__(
- "wur.threadptr %0" : : "a" (threadptr) : "memory");
-#else
-#error "Core support for XCHAL_HAVE_THREADPTR is required"
-#endif
-}
-
-static inline int cpu_read_threadptr(void)
-{
- int threadptr;
-#if XCHAL_HAVE_THREADPTR
- __asm__ __volatile__(
- "rur.threadptr %0" : "=a"(threadptr));
-#else
-#error "Core support for XCHAL_HAVE_THREADPTR is required"
-#endif
- return threadptr;
-}
-
-#endif
diff --git a/src/arch/xtensa/include/arch/init.h b/src/arch/xtensa/include/arch/init.h
deleted file mode 100644
index 3e018de..0000000
--- a/src/arch/xtensa/include/arch/init.h
+++ /dev/null
@@ -1,142 +0,0 @@
-/*
- * Copyright (c) 2016, Intel Corporation
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- * * Redistributions of source code must retain the above copyright
- * notice, this list of conditions and the following disclaimer.
- * * Redistributions in binary form must reproduce the above copyright
- * notice, this list of conditions and the following disclaimer in the
- * documentation and/or other materials provided with the distribution.
- * * Neither the name of the Intel Corporation nor the
- * names of its contributors may be used to endorse or promote products
- * derived from this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
- * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
- * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
- * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
- * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
- * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
- * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
- * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
- * POSSIBILITY OF SUCH DAMAGE.
- *
- * Author: Liam Girdwood <liam.r.girdwood@linux.intel.com>
- */
-
-/**
- * \file arch/xtensa/include/arch/init.h
- * \brief Arch init header file
- * \authors Liam Girdwood <liam.r.girdwood@linux.intel.com>
- */
-
-#ifndef __ARCH_INIT_H__
-#define __ARCH_INIT_H__
-
-#include <xtensa/hal.h>
-#include <xtensa/xtruntime.h>
-#include <sof/panic.h>
-
-/**
- * \brief Called in the case of exception.
- */
-static inline void exception(void)
-{
- /* now panic and rewind 8 stack frames. */
- /* TODO: we could invoke a GDB stub here */
- panic_rewind(SOF_IPC_PANIC_EXCEPTION, 8 * sizeof(uint32_t));
-}
-
-/**
- * \brief Registers exception handlers.
- */
-static inline void register_exceptions(void)
-{
-
- /* 0 - 9 */
- _xtos_set_exception_handler(
- EXCCAUSE_ILLEGAL, (void *)&exception);
- _xtos_set_exception_handler(
- EXCCAUSE_SYSCALL, (void *)&exception);
- _xtos_set_exception_handler(
- EXCCAUSE_INSTR_ERROR, (void *)&exception);
- _xtos_set_exception_handler(
- EXCCAUSE_LOAD_STORE_ERROR, (void *)&exception);
- _xtos_set_exception_handler(
- EXCCAUSE_ALLOCA, (void *)&exception);
- _xtos_set_exception_handler(
- EXCCAUSE_DIVIDE_BY_ZERO, (void *)&exception);
- _xtos_set_exception_handler(
- EXCCAUSE_SPECULATION, (void *)&exception);
- _xtos_set_exception_handler(
- EXCCAUSE_PRIVILEGED, (void *)&exception);
- _xtos_set_exception_handler(
- EXCCAUSE_UNALIGNED, (void *)&exception);
-
- /* Reserved 10..11 */
-
- _xtos_set_exception_handler(
- EXCCAUSE_INSTR_DATA_ERROR, (void *)&exception);
- _xtos_set_exception_handler(
- EXCCAUSE_LOAD_STORE_DATA_ERROR, (void *)&exception);
- _xtos_set_exception_handler(
- EXCCAUSE_INSTR_ADDR_ERROR, (void *)&exception);
- _xtos_set_exception_handler(
- EXCCAUSE_LOAD_STORE_ADDR_ERROR, (void *)&exception);
- _xtos_set_exception_handler(
- EXCCAUSE_ITLB_MISS, (void *)&exception);
- _xtos_set_exception_handler(
- EXCCAUSE_ITLB_MULTIHIT, (void *)&exception);
- _xtos_set_exception_handler(
- EXCCAUSE_INSTR_RING, (void *)&exception);
-
- /* Reserved 19 */
-
- _xtos_set_exception_handler(
- EXCCAUSE_INSTR_PROHIBITED, (void *)&exception);
-
- /* Reserved 21..23 */
- _xtos_set_exception_handler(
- EXCCAUSE_DTLB_MISS, (void *)&exception);
- _xtos_set_exception_handler(
- EXCCAUSE_DTLB_MULTIHIT, (void *)&exception);
- _xtos_set_exception_handler(
- EXCCAUSE_LOAD_STORE_RING, (void *)&exception);
-
- /* Reserved 27 */
- _xtos_set_exception_handler(
- EXCCAUSE_LOAD_PROHIBITED, (void *)&exception);
- _xtos_set_exception_handler(
- EXCCAUSE_STORE_PROHIBITED, (void *)&exception);
-
- /* Reserved 30..31 */
- _xtos_set_exception_handler(
- EXCCAUSE_CP0_DISABLED, (void *)&exception);
- _xtos_set_exception_handler(
- EXCCAUSE_CP1_DISABLED, (void *)&exception);
- _xtos_set_exception_handler(
- EXCCAUSE_CP2_DISABLED, (void *)&exception);
- _xtos_set_exception_handler(
- EXCCAUSE_CP3_DISABLED, (void *)&exception);
- _xtos_set_exception_handler(
- EXCCAUSE_CP4_DISABLED, (void *)&exception);
- _xtos_set_exception_handler(
- EXCCAUSE_CP5_DISABLED, (void *)&exception);
- _xtos_set_exception_handler(
- EXCCAUSE_CP6_DISABLED, (void *)&exception);
- _xtos_set_exception_handler(
- EXCCAUSE_CP7_DISABLED, (void *)&exception);
-
- /* Reserved 40..63 */
-}
-
-/**
- * \brief Called from assembler context with no return or parameters.
- */
-static inline void __memmap_init(void) { }
-
-#endif
diff --git a/src/arch/xtensa/include/arch/interrupt.h b/src/arch/xtensa/include/arch/interrupt.h
deleted file mode 100644
index d2f7360..0000000
--- a/src/arch/xtensa/include/arch/interrupt.h
+++ /dev/null
@@ -1,113 +0,0 @@
-/*
- * Copyright (c) 2016, Intel Corporation
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- * * Redistributions of source code must retain the above copyright
- * notice, this list of conditions and the following disclaimer.
- * * Redistributions in binary form must reproduce the above copyright
- * notice, this list of conditions and the following disclaimer in the
- * documentation and/or other materials provided with the distribution.
- * * Neither the name of the Intel Corporation nor the
- * names of its contributors may be used to endorse or promote products
- * derived from this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
- * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
- * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
- * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
- * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
- * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
- * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
- * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
- * POSSIBILITY OF SUCH DAMAGE.
- *
- * Author: Liam Girdwood <liam.r.girdwood@linux.intel.com>
- *
- */
-
-#ifndef __ARCH_INTERRUPT_H
-#define __ARCH_INTERRUPT_H
-
-#include <xtensa/xtruntime.h>
-#include <xtensa/hal.h>
-#include <sof/interrupt-map.h>
-#include <stdint.h>
-#include <stdlib.h>
-
-static inline int arch_interrupt_register(int irq,
- void(*handler)(void *arg), void *arg)
-{
- irq = SOF_IRQ_NUMBER(irq);
- xthal_set_intclear(0x1 << irq);
- _xtos_set_interrupt_handler_arg(irq, handler, arg);
- return 0;
-}
-
-static inline void arch_interrupt_unregister(int irq)
-{
- irq = SOF_IRQ_NUMBER(irq);
- _xtos_set_interrupt_handler_arg(irq, NULL, NULL);
-}
-
-/* returns previous mask */
-#define arch_interrupt_enable_mask(mask) \
- _xtos_ints_on(mask)
-
-/* returns previous mask */
-#define arch_interrupt_disable_mask(mask) \
- _xtos_ints_off(mask)
-
-static inline uint32_t arch_interrupt_get_level(void)
-{
- uint32_t level;
-
- __asm__ __volatile__(
- " rsr.ps %0\n"
- " extui %0, %0, 0, 4\n"
- : "=&a" (level) :: "memory");
-
- return level;
-}
-
-static inline void arch_interrupt_set(int irq)
-{
- irq = SOF_IRQ_NUMBER(irq);
- xthal_set_intset(0x1 << irq);
-}
-
-static inline void arch_interrupt_clear(int irq)
-{
- irq = SOF_IRQ_NUMBER(irq);
- xthal_set_intclear(0x1 << irq);
-}
-
-static inline uint32_t arch_interrupt_get_enabled(void)
-{
- return xthal_get_intenable();
-}
-
-static inline uint32_t arch_interrupt_get_status(void)
-{
- return xthal_get_interrupt();
-}
-
-static inline uint32_t arch_interrupt_global_disable(void)
-{
- uint32_t flags;
-
- asm volatile("rsil %0, 5"
- : "=a" (flags) :: "memory");
- return flags;
-}
-
-static inline void arch_interrupt_global_enable(uint32_t flags)
-{
- asm volatile("wsr %0, ps; rsync"
- :: "a" (flags) : "memory");
-}
-
-#endif
diff --git a/src/arch/xtensa/include/arch/sof.h b/src/arch/xtensa/include/arch/sof.h
deleted file mode 100644
index abace8f..0000000
--- a/src/arch/xtensa/include/arch/sof.h
+++ /dev/null
@@ -1,109 +0,0 @@
-/*
- * Copyright (c) 2016, Intel Corporation
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- * * Redistributions of source code must retain the above copyright
- * notice, this list of conditions and the following disclaimer.
- * * Redistributions in binary form must reproduce the above copyright
- * notice, this list of conditions and the following disclaimer in the
- * documentation and/or other materials provided with the distribution.
- * * Neither the name of the Intel Corporation nor the
- * names of its contributors may be used to endorse or promote products
- * derived from this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
- * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
- * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
- * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
- * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
- * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
- * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
- * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
- * POSSIBILITY OF SUCH DAMAGE.
- *
- * Author: Liam Girdwood <liam.r.girdwood@linux.intel.com>
- *
- */
-
-#ifndef __INCLUDE_ARCH_SOF__
-#define __INCLUDE_ARCH_SOF__
-
-#include <stdint.h>
-#include <stddef.h>
-#include <sof/mailbox.h>
-#include <uapi/ipc.h>
-
-/* architecture specific stack frames to dump */
-#define ARCH_STACK_DUMP_FRAMES 32
-
-static inline void *arch_get_stack_ptr(void)
-{
- void *ptr;
-
- /* stack pointer is in a1 */
- __asm__ __volatile__ ("mov %0, a1"
- : "=a" (ptr)
- :
- : "memory");
- return ptr;
-}
-
-static inline void *arch_dump_regs(void)
-{
- struct sof_ipc_dsp_oops_xtensa *x =
- (struct sof_ipc_dsp_oops_xtensa *) mailbox_get_exception_base();
-
- /* Exception Vector number - 0x0 */
- __asm__ __volatile__ ("rsr %0, EXCCAUSE" : "=a" (x->exccause) : : "memory");
- /* Exception Vector address - 0x4 */
- __asm__ __volatile__ ("rsr %0, EXCVADDR" : "=a" (x->excvaddr) : : "memory");
- /* Exception Processor State - 0x8 */
- __asm__ __volatile__ ("rsr %0, PS" : "=a" (x->ps) : : "memory");
- /* Level 1 Exception PC - 0xc */
- __asm__ __volatile__ ("rsr %0, EPC1" : "=a" (x->epc1) : : "memory");
- /* Level 2 Exception PC - 0x10 */
- __asm__ __volatile__ ("rsr %0, EPC2" : "=a" (x->epc2) : : "memory");
- /* Level 3 Exception PC - 0x14 */
- __asm__ __volatile__ ("rsr %0, EPC3" : "=a" (x->epc3) : : "memory");
- /* Level 4 Exception PC - 0x18 */
- __asm__ __volatile__ ("rsr %0, EPC4" : "=a" (x->epc4) : : "memory");
- /* Level 5 Exception PC - 0x1c */
- __asm__ __volatile__ ("rsr %0, EPC5" : "=a" (x->epc5) : : "memory");
- /* Level 6 Exception PC - 0x20 */
- __asm__ __volatile__ ("rsr %0, EPC6" : "=a" (x->epc6) : : "memory");
- /* Level 7 Exception PC - 0x24 */
- __asm__ __volatile__ ("rsr %0, EPC7" : "=a" (x->epc7) : : "memory");
- /* Level 2 Exception PS - 0x28 */
- __asm__ __volatile__ ("rsr %0, EPS2" : "=a" (x->eps2) : : "memory");
- /* Level 3 Exception PS - 0x2c */
- __asm__ __volatile__ ("rsr %0, EPS3" : "=a" (x->eps3) : : "memory");
- /* Level 4 Exception PS - 0x30 */
- __asm__ __volatile__ ("rsr %0, EPS4" : "=a" (x->eps4) : : "memory");
- /* Level 5 Exception PS - 0x34 */
- __asm__ __volatile__ ("rsr %0, EPS5" : "=a" (x->eps5) : : "memory");
- /* Level 6 Exception PS - 0x38 */
- __asm__ __volatile__ ("rsr %0, EPS6" : "=a" (x->eps6) : : "memory");
- /* Level 7 Exception PS - 0x3c */
- __asm__ __volatile__ ("rsr %0, EPS7" : "=a" (x->eps7) : : "memory");
- /* Double Exception program counter - 0x40 */
- __asm__ __volatile__ ("rsr %0, DEPC" : "=a" (x->depc) : : "memory");
- /* Interrupts Enabled - 0x44 */
- __asm__ __volatile__ ("rsr %0, INTENABLE" : "=a" (x->intenable) : : "memory");
- /* Interrupts Status - 0x48 */
- __asm__ __volatile__ ("rsr %0, INTERRUPT" : "=a" (x->interrupt) : : "memory");
- /* Shift register - 0x4c */
- __asm__ __volatile__ ("rsr %0, SAR" : "=a" (x->sar) : : "memory");
- /* Register A1 (stack) - 0x50 */
- __asm__ __volatile__ ("mov %0, a1" : "=a" (x->stack) : : "memory");
-
- dcache_writeback_region((void *)x, sizeof(*x));
-
- /* tell caller extended data can be placed hereafter */
- return (void *)(x + 1);
-}
-
-#endif
diff --git a/src/arch/xtensa/include/arch/spinlock.h b/src/arch/xtensa/include/arch/spinlock.h
deleted file mode 100644
index 3bb6b15..0000000
--- a/src/arch/xtensa/include/arch/spinlock.h
+++ /dev/null
@@ -1,95 +0,0 @@
-/*
- * Copyright (c) 2016, Intel Corporation
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- * * Redistributions of source code must retain the above copyright
- * notice, this list of conditions and the following disclaimer.
- * * Redistributions in binary form must reproduce the above copyright
- * notice, this list of conditions and the following disclaimer in the
- * documentation and/or other materials provided with the distribution.
- * * Neither the name of the Intel Corporation nor the
- * names of its contributors may be used to endorse or promote products
- * derived from this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
- * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
- * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
- * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
- * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
- * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
- * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
- * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
- * POSSIBILITY OF SUCH DAMAGE.
- *
- * Author: Liam Girdwood <liam.r.girdwood@linux.intel.com>
- *
- */
-
-#ifndef __ARCH_SPINLOCK_H_
-#define __ARCH_SPINLOCK_H_
-
-#include <stdint.h>
-#include <errno.h>
-
-typedef struct {
- volatile uint32_t lock;
-#if DEBUG_LOCKS
- uint32_t user;
-#endif
-} spinlock_t;
-
-static inline void arch_spinlock_init(spinlock_t *lock)
-{
- lock->lock = 0;
-}
-
-static inline void arch_spin_lock(spinlock_t *lock)
-{
- uint32_t result, current;
-
- __asm__ __volatile__(
- "1: l32i %1, %2, 0\n"
- " wsr %1, scompare1\n"
- " movi %0, 1\n"
- " s32c1i %0, %2, 0\n"
- " bne %0, %1, 1b\n"
- : "=&a" (result), "=&a" (current)
- : "a" (&lock->lock)
- : "memory");
-}
-
-static inline int arch_try_lock(spinlock_t *lock)
-{
- uint32_t result, current;
-
- __asm__ __volatile__(
- " l32i %1, %2, 0\n"
- " wsr %1, scompare1\n"
- " movi %0, 1\n"
- " s32c1i %0, %2, 0\n"
- : "=&a" (result), "=&a" (current)
- : "a" (&lock->lock)
- : "memory");
-
- if (result)
- return 0; /* lock failed */
- return 1; /* lock acquired */
-}
-
-static inline void arch_spin_unlock(spinlock_t *lock)
-{
- uint32_t result;
-
- __asm__ __volatile__(
- " movi %0, 0\n"
- " s32ri %0, %1, 0\n"
- : "=&a" (result)
- : "a" (&lock->lock)
- : "memory");
-}
-
-#endif
diff --git a/src/arch/xtensa/include/arch/string.h b/src/arch/xtensa/include/arch/string.h
deleted file mode 100644
index 56258b3..0000000
--- a/src/arch/xtensa/include/arch/string.h
+++ /dev/null
@@ -1,40 +0,0 @@
-/*
- * Copyright (c) 2018, Intel Corporation
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- * * Redistributions of source code must retain the above copyright
- * notice, this list of conditions and the following disclaimer.
- * * Redistributions in binary form must reproduce the above copyright
- * notice, this list of conditions and the following disclaimer in the
- * documentation and/or other materials provided with the distribution.
- * * Neither the name of the Intel Corporation nor the
- * names of its contributors may be used to endorse or promote products
- * derived from this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
- * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
- * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
- * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
- * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
- * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
- * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
- * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
- * POSSIBILITY OF SUCH DAMAGE.
- *
- * Author: Liam Girdwood <liam.r.girdwood@linux.intel.com>
- *
- */
-
-#ifndef __INCLUDE_ARCH_STRING_SOF__
-#define __INCLUDE_ARCH_STRING_SOF__
-
-void *xthal_memcpy(void *dst, const void *src, size_t len);
-
-#define arch_memcpy(dest, src, size) \
- xthal_memcpy(dest, src, size)
-
-#endif
diff --git a/src/arch/xtensa/include/arch/task.h b/src/arch/xtensa/include/arch/task.h
deleted file mode 100644
index fa5a372..0000000
--- a/src/arch/xtensa/include/arch/task.h
+++ /dev/null
@@ -1,272 +0,0 @@
-/*
- * Copyright (c) 2017, Intel Corporation
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- * * Redistributions of source code must retain the above copyright
- * notice, this list of conditions and the following disclaimer.
- * * Redistributions in binary form must reproduce the above copyright
- * notice, this list of conditions and the following disclaimer in the
- * documentation and/or other materials provided with the distribution.
- * * Neither the name of the Intel Corporation nor the
- * names of its contributors may be used to endorse or promote products
- * derived from this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
- * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
- * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
- * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
- * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
- * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
- * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
- * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
- * POSSIBILITY OF SUCH DAMAGE.
- *
- * Author: Liam Girdwood <liam.r.girdwood@linux.intel.com>
- *
- */
-
-/**
- * \file arch/xtensa/include/arch/task.h
- * \brief Arch task header file
- * \authors Liam Girdwood <liam.r.girdwood@linux.intel.com>
- */
-
-#ifndef __ARCH_TASK_H_
-#define __ARCH_TASK_H_
-
-#include <sof/schedule.h>
-#include <sof/interrupt.h>
-#include <platform/platform.h>
-#include <sof/debug.h>
-#include <sof/alloc.h>
-
-/** \brief IRQ task data. */
-struct irq_task {
- spinlock_t lock; /**< lock */
- struct list_item list; /**< list of tasks */
- uint32_t irq; /**< IRQ level */
-};
-
-/**
- * \brief Returns IRQ low task data.
- * \return Pointer to pointer of IRQ low task data.
- */
-struct irq_task **task_irq_low_get(void);
-
-/**
- * \brief Returns IRQ medium task data.
- * \return Pointer to pointer of IRQ medium task data.
- */
-struct irq_task **task_irq_med_get(void);
-
-/**
- * \brief Returns IRQ high task data.
- * \return Pointer to pointer of IRQ high task data.
- */
-struct irq_task **task_irq_high_get(void);
-
-/**
- * \brief Retrieves task IRQ level.
- * \param[in,out] task Task data.
- * \return IRQ level.
- */
-static inline uint32_t task_get_irq(struct task *task)
-{
- uint32_t irq;
-
- switch (task->priority) {
- case TASK_PRI_MED + 1 ... TASK_PRI_LOW:
- irq = PLATFORM_IRQ_TASK_LOW;
- break;
- case TASK_PRI_HIGH ... TASK_PRI_MED - 1:
- irq = PLATFORM_IRQ_TASK_HIGH;
- break;
- case TASK_PRI_MED:
- default:
- irq = PLATFORM_IRQ_TASK_MED;
- break;
- }
-
- return irq;
-}
-
-/**
- * \brief Adds task to the list per IRQ level.
- * \param[in,out] task Task data.
- */
-static inline void task_set_data(struct task *task)
-{
- struct list_item *dst = NULL;
-
- switch (task->priority) {
- case TASK_PRI_MED + 1 ... TASK_PRI_LOW:
- dst = &((*task_irq_low_get())->list);
- break;
- case TASK_PRI_HIGH ... TASK_PRI_MED - 1:
- dst = &((*task_irq_high_get())->list);
- break;
- case TASK_PRI_MED:
- default:
- dst = &((*task_irq_med_get())->list);
- break;
- }
- list_item_append(&task->irq_list, dst);
-}
-
-/**
- * \brief Interrupt handler for the IRQ task.
- * \param[in,out] arg IRQ task data.
- */
-static void _irq_task(void *arg)
-{
- struct irq_task *irq_task = *(struct irq_task **)arg;
- struct list_item *tlist;
- struct list_item *clist;
- struct task *task;
- uint32_t flags;
-
- /* intentionally don't lock list to have task added from schedule irq */
- list_for_item(tlist, &irq_task->list) {
- task = container_of(tlist, struct task, irq_list);
-
- if (task->func)
- task->func(task->data);
-
- schedule_task_complete(task);
- }
-
- spin_lock_irq(&irq_task->lock, flags);
-
- list_for_item_safe(clist, tlist, &irq_task->list) {
- task = container_of(clist, struct task, irq_list);
- list_item_del(&task->irq_list);
- }
-
- interrupt_clear(irq_task->irq);
-
- spin_unlock_irq(&irq_task->lock, flags);
-}
-
-/**
- * \brief Runs task.
- * \param[in,out] task Task data.
- */
-static inline void arch_run_task(struct task *task)
-{
- uint32_t irq;
-
- task_set_data(task);
- irq = task_get_irq(task);
- interrupt_set(irq);
-}
-
-/**
- * \brief Allocates IRQ tasks.
- */
-static inline int arch_allocate_tasks(void)
-{
- /* irq low */
- struct irq_task **low = task_irq_low_get();
- *low = rzalloc(RZONE_RUNTIME, SOF_MEM_CAPS_RAM, sizeof(**low));
-
- if (!*low)
- return -ENOMEM;
-
- list_init(&((*low)->list));
- spinlock_init(&((*low)->lock));
- (*low)->irq = PLATFORM_IRQ_TASK_LOW;
-
- /* irq medium */
- struct irq_task **med = task_irq_med_get();
- *med = rzalloc(RZONE_RUNTIME, SOF_MEM_CAPS_RAM, sizeof(**med));
-
- if (!*med)
- return -ENOMEM;
-
- list_init(&((*med)->list));
- spinlock_init(&((*med)->lock));
- (*med)->irq = PLATFORM_IRQ_TASK_MED;
-
- /* irq high */
- struct irq_task **high = task_irq_high_get();
- *high = rzalloc(RZONE_RUNTIME, SOF_MEM_CAPS_RAM, sizeof(**high));
-
- if (!*high)
- return -ENOMEM;
-
- list_init(&((*high)->list));
- spinlock_init(&((*high)->lock));
- (*high)->irq = PLATFORM_IRQ_TASK_HIGH;
-
- return 0;
-}
-
-/**
- * \brief Frees IRQ tasks.
- */
-static inline void arch_free_tasks(void)
-{
- uint32_t flags;
-
- /* free IRQ low task */
- struct irq_task **low = task_irq_low_get();
-
- spin_lock_irq(&(*low)->lock, flags);
- interrupt_disable(PLATFORM_IRQ_TASK_LOW);
- interrupt_unregister(PLATFORM_IRQ_TASK_LOW);
- list_item_del(&(*low)->list);
- spin_unlock_irq(&(*low)->lock, flags);
-
- rfree(*low);
-
- /* free IRQ medium task */
- struct irq_task **med = task_irq_med_get();
-
- spin_lock_irq(&(*med)->lock, flags);
- interrupt_disable(PLATFORM_IRQ_TASK_MED);
- interrupt_unregister(PLATFORM_IRQ_TASK_MED);
- list_item_del(&(*med)->list);
- spin_unlock_irq(&(*med)->lock, flags);
-
- rfree(*med);
-
- /* free IRQ high task */
- struct irq_task **high = task_irq_high_get();
-
- spin_lock_irq(&(*high)->lock, flags);
- interrupt_disable(PLATFORM_IRQ_TASK_HIGH);
- interrupt_unregister(PLATFORM_IRQ_TASK_HIGH);
- list_item_del(&(*high)->list);
- spin_unlock_irq(&(*high)->lock, flags);
-
- rfree(*high);
-}
-
-/**
- * \brief Assigns IRQ tasks to interrupts.
- */
-static inline int arch_assign_tasks(void)
-{
- /* irq low */
- interrupt_register(PLATFORM_IRQ_TASK_LOW, _irq_task,
- task_irq_low_get());
- interrupt_enable(PLATFORM_IRQ_TASK_LOW);
-
- /* irq medium */
- interrupt_register(PLATFORM_IRQ_TASK_MED, _irq_task,
- task_irq_med_get());
- interrupt_enable(PLATFORM_IRQ_TASK_MED);
-
- /* irq high */
- interrupt_register(PLATFORM_IRQ_TASK_HIGH, _irq_task,
- task_irq_high_get());
- interrupt_enable(PLATFORM_IRQ_TASK_HIGH);
-
- return 0;
-}
-
-#endif
diff --git a/src/arch/xtensa/include/arch/timer.h b/src/arch/xtensa/include/arch/timer.h
deleted file mode 100644
index e36df6b..0000000
--- a/src/arch/xtensa/include/arch/timer.h
+++ /dev/null
@@ -1,90 +0,0 @@
-/*
- * Copyright (c) 2016, Intel Corporation
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- * * Redistributions of source code must retain the above copyright
- * notice, this list of conditions and the following disclaimer.
- * * Redistributions in binary form must reproduce the above copyright
- * notice, this list of conditions and the following disclaimer in the
- * documentation and/or other materials provided with the distribution.
- * * Neither the name of the Intel Corporation nor the
- * names of its contributors may be used to endorse or promote products
- * derived from this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
- * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
- * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
- * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
- * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
- * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
- * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
- * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
- * POSSIBILITY OF SUCH DAMAGE.
- *
- * Author: Liam Girdwood <liam.r.girdwood@linux.intel.com>
- *
- */
-
-#ifndef __ARCH_TIMER_H_
-#define __ARCH_TIMER_H_
-
-#include <arch/interrupt.h>
-#include <stdint.h>
-#include <errno.h>
-
-struct timer {
- uint32_t id;
- uint32_t irq;
- void *timer_data; /* used by core */
- uint32_t hitime; /* high end of 64bit timer */
- uint32_t hitimeout;
- uint32_t lowtimeout;
-};
-
-/* internal API calls */
-int timer64_register(struct timer *timer, void(*handler)(void *arg), void *arg);
-void timer_64_handler(void *arg);
-
-static inline int arch_timer_register(struct timer *timer,
- void(*handler)(void *arg), void *arg)
-{
- uint32_t flags;
- int ret;
-
- flags = arch_interrupt_global_disable();
- timer64_register(timer, handler, arg);
- ret = arch_interrupt_register(timer->id, timer_64_handler, timer);
- arch_interrupt_global_enable(flags);
-
- return ret;
-}
-
-static inline void arch_timer_unregister(struct timer *timer)
-{
- arch_interrupt_unregister(timer->id);
-}
-
-static inline void arch_timer_enable(struct timer *timer)
-{
- arch_interrupt_enable_mask(1 << timer->irq);
-}
-
-static inline void arch_timer_disable(struct timer *timer)
-{
- arch_interrupt_disable_mask(1 << timer->irq);
-}
-
-uint64_t arch_timer_get_system(struct timer *timer);
-
-int arch_timer_set(struct timer *timer, uint64_t ticks);
-
-static inline void arch_timer_clear(struct timer *timer)
-{
- arch_interrupt_clear(timer->irq);
-}
-
-#endif
diff --git a/src/arch/xtensa/include/arch/wait.h b/src/arch/xtensa/include/arch/wait.h
deleted file mode 100644
index e1cca01..0000000
--- a/src/arch/xtensa/include/arch/wait.h
+++ /dev/null
@@ -1,69 +0,0 @@
-/*
- * Copyright (c) 2017, Intel Corporation
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- * * Redistributions of source code must retain the above copyright
- * notice, this list of conditions and the following disclaimer.
- * * Redistributions in binary form must reproduce the above copyright
- * notice, this list of conditions and the following disclaimer in the
- * documentation and/or other materials provided with the distribution.
- * * Neither the name of the Intel Corporation nor the
- * names of its contributors may be used to endorse or promote products
- * derived from this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
- * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
- * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
- * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
- * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
- * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
- * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
- * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
- * POSSIBILITY OF SUCH DAMAGE.
- *
- * Author: Liam Girdwood <liam.r.girdwood@linux.intel.com>
- */
-
-#include <xtensa/xtruntime.h>
-
-#if defined(PLATFORM_WAITI_DELAY)
-
-static inline void arch_wait_for_interrupt(int level)
-{
- int i;
-
- /* this sequnce must be atomic on LX6 */
- XTOS_SET_INTLEVEL(5);
-
- /* LX6 needs a delay */
- for (i = 0; i < 128; i++)
- asm volatile("nop");
-
- /* and to flush all loads/stores prior to wait */
- asm volatile("isync");
- asm volatile("extw");
-
- /* now wait */
- asm volatile("waiti 0");
-}
-
-#else
-
-static inline void arch_wait_for_interrupt(int level)
-{
- asm volatile("waiti 0");
-}
-
-#endif
-
-static inline void idelay(int n)
-{
- while (n--) {
- asm volatile("nop");
- }
-}
-
diff --git a/src/arch/xtensa/include/xtensa/Makefile.am b/src/arch/xtensa/include/xtensa/Makefile.am
deleted file mode 100644
index c4c0f20..0000000
--- a/src/arch/xtensa/include/xtensa/Makefile.am
+++ /dev/null
@@ -1,35 +0,0 @@
-noinst_HEADERS = \
- board.h \
- config \
- hal.h \
- overlay.h \
- trax-api.h \
- trax-proto.h \
- xdm-regs.h \
- xtensa-versions.h \
- xtruntime.h \
- c6x-compat.h \
- coreasm.h \
- overlay_os_asm.h \
- trax-core-config.h \
- traxreg.h \
- xmon.h \
- xtensa-xer.h \
- cacheasm.h \
- corebits.h \
- simboard.h \
- traxfile.h \
- trax-util.h \
- xtbsp.h \
- xtruntime-core-state.h \
- cacheattrasm.h \
- core-macros.h \
- specreg.h \
- trax.h \
- uart-16550.h \
- xtensa-libdb-macros.h \
- xtruntime-frames.h \
- mpuasm.h \
- idmaasm.h
-
-SUBDIRS = config
diff --git a/src/arch/xtensa/include/xtensa/board.h b/src/arch/xtensa/include/xtensa/board.h
deleted file mode 100644
index c6b04a2..0000000
--- a/src/arch/xtensa/include/xtensa/board.h
+++ /dev/null
@@ -1,28 +0,0 @@
-/* This header is supposed to be obtained from <board>/xtensa/board.h
- using a -I directive passed to the compiler. */
-
-#error "Unspecified board. Missing -I directive to select supported Xtensa board, usually -I XTENSA_TOOLS_ROOT/xtensa-elf/include/xtensa/<BOARD> (XTENSA_TOOLS_ROOT is root of Xtensa Tools install, see xt-run --show-config=xttools)"
-
-/*
- * Copyright (c) 2013 Tensilica Inc.
- *
- * Permission is hereby granted, free of charge, to any person obtaining
- * a copy of this software and associated documentation files (the
- * "Software"), to deal in the Software without restriction, including
- * without limitation the rights to use, copy, modify, merge, publish,
- * distribute, sublicense, and/or sell copies of the Software, and to
- * permit persons to whom the Software is furnished to do so, subject to
- * the following conditions:
- *
- * The above copyright notice and this permission notice shall be included
- * in all copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
- * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
- * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
- * IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY
- * CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
- * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
- * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
- */
-
diff --git a/src/arch/xtensa/include/xtensa/c6x-compat.h b/src/arch/xtensa/include/xtensa/c6x-compat.h
deleted file mode 100755
index 4b17987..0000000
--- a/src/arch/xtensa/include/xtensa/c6x-compat.h
+++ /dev/null
@@ -1,1758 +0,0 @@
-/*
- * Copyright (c) 2006-2010 Tensilica Inc. ALL RIGHTS RESERVED.
- *
- * Permission is hereby granted, free of charge, to any person obtaining a copy
- * of this software and associated documentation files (the "Software"), to deal
- * in the Software without restriction, including without limitation the rights
- * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
- * copies of the Software, and to permit persons to whom the Software is
- * furnished to do so, subject to the following conditions:
- *
- * The above copyright notice and this permission notice shall be included in
- * all copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
- * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
- * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
- * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
- * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
- * THE SOFTWARE.
- */
-
-#ifndef __C6X_COMPAT__H
-#define __C6X_COMPAT__H
-
-/* Unimplemented functions _gmpy, _gmpy4, _xormpy, _lssub, _cmpy, _cmpyr,
- _cmpyr1, _ddotpl2r, _ddotph2r */
-
-
-typedef long long C6X_COMPAT_LONG40;
-
-
-#define _memd8(a) (*((double*)(a)))
-#define _memd8_const(a) (*((const double*)(a)))
-
-#define _amemd8(a) (*((double*)(a)))
-#define _amemd8_const(a) (*((const double*)(a)))
-
-#define _mem8(a) (*((unsigned long long*)(a)))
-#define _mem8_const(a) (*((const unsigned long long*)(a)))
-
-#define _mem4(a) (*((unsigned*)(a)))
-#define _mem4_const(a) (*((const unsigned*)(a)))
-#define _amem4_const(a) (*((const unsigned*)(a)))
-
-/* NOTE: To emulate a C6X properly you should define global variables
- for your Xtensa with these names. Some of the emulation routines
- will set these values. */
-
-extern int _carry;
-extern int _overflow;
-
-// Utility routines
-
-
-#define TESTBIT(x,n) (((x) >> (n)) & 1)
-
-#define NSA_BITS 32
-
-static inline unsigned int norm_shift_amt_U_and_non_U(int is_signed, int inp) {
-int j=0, k=0;
-int x=inp;
-if (is_signed) {
- /* Invert signed val if negative */
- x= TESTBIT(x,(NSA_BITS-1))? ~x: x;
- x= (x&1)|(x<<1); /* Shift up to return count-1 */
- if (x ==0)
- return NSA_BITS-1;
- }
- if (x ==0)
- return NSA_BITS;
- /* Now count leading zeros */
- for (j=0, k=NSA_BITS-1; k>=0; j++, k--) {
- if (TESTBIT(x,k))
- return j;
- }
- return NSA_BITS;
-}
-
-
-
-static inline long long
-orig_L40_set( long long L40_var1) {
- long long L40_var_out;
-
- L40_var_out = L40_var1 & 0x000000ffffffffffLL;
-
- if( L40_var1 & 0x8000000000LL)
- L40_var_out = L40_var_out | 0xffffff0000000000LL;
-
- return( L40_var_out);
-}
-
-
-
-static inline signed long long
-util_saturate_n_no_state(signed long long t, int n)
-{
- signed long long maxv, minv;
- maxv = (1LL << (n-1)) - 1;
- minv = (-1LL << (n-1));
- if (t > maxv) {
- t = maxv;
- } else if (t < minv) {
- t = minv;
- }
- return t;
-}
-
-
-static inline signed long long
-util_saturate_n_sgn(signed long long t, int n)
-{
- signed long long result;
- signed long long maxv, minv;
- maxv = (1LL << (n-1)) - 1;
- minv = (-1LL << (n-1));
- if (t > 0) {
- result = maxv;
- _overflow = 1;
- } else if (t < 0) {
- result = minv;
- _overflow = 1;
- } else {
- result = 0;
- }
- return result;
-}
-
-
-
-
-/* well-behaved signed shift right (left on negative) with
- saturation */
-static inline signed long long
-util_shift_right_saturate_n(signed long long t, int shval, int n)
-{
- /* n should be <= 62 */
- long long result;
-
- signed long long mask;
- int actual_shift = shval;
- long long shft = actual_shift > 0 ? actual_shift : -actual_shift;
-
- if (t == 0 || actual_shift == 0)
- return t;
-
- if (actual_shift >= n) {
- return (t < 0) ? -1 : 0;
- }
- if (actual_shift <= -n) {
- return util_saturate_n_sgn(t, n);
- }
- if (actual_shift > 0) {
- return t >> actual_shift;
- }
- /* actual_shift < 0. Check for saturation after shift. */
- mask = (-1LL << (n-shft-1));
- if (t > 0 && ((mask & t) != 0)) {
- return util_saturate_n_sgn(t, n);
- }
- if (t < 0 && ((mask & t) != mask)) {
- return util_saturate_n_sgn(t, n);
- }
- result = t << shft;
-
- return result;
-}
-
-
-/* Implemented c6x standard C compatibility functions (alphabetical
- order) */
-
-
-static inline int _abs(int src1) {
- if ((unsigned) src1 == (unsigned) 0x80000000) {
- return 0x7fffffff;
- }
- return abs(src1);
-}
-
-
-static inline int _abs2(int src1) {
- short s1[2],r[2];
- int result;
- *((int*)s1) = src1;
- if ((unsigned short) s1[1] == (unsigned short) 0x8000) r[1] = 0x7fff;
- else r[1] = abs(s1[1]);
- if ((unsigned short) s1[0] == (unsigned short) 0x8000) r[0] = 0x7fff;
- else r[0] = abs(s1[0]);
- result = *(int*)r;
- return result;
- }
-
-
-
-
-static inline int _add2(int src1, int src2) {
- short s1[2], s2[2], r[2];
- int result;
- *((int*)s1) = src1;
- *((int*)s2) = src2;
- r[0] = s1[0] + s2[0];
- r[1] = s1[1] + s2[1];
- result = *(int*)r;
- return result;
-}
-
-static inline int _add4(int src1, int src2) {
- char c1[4], c2[4], r[4];
- int result;
- *((int*)c1) = src1;
- *((int*)c2) = src2;
- r[0] = c1[0] + c2[0];
- r[1] = c1[1] + c2[1];
- r[2] = c1[2] + c2[2];
- r[3] = c1[3] + c2[3];
- result = *(int*)r;
- return result;
-}
-
-
-
-static inline long long _addsub(unsigned int src1, unsigned int src2)
-{
-
- int res_lo;
- int res_hi;
-
- res_hi = src1+src2;
- res_lo = src1-src2;
- return (((unsigned long long) res_hi) << 32) | ((unsigned int) res_lo) ;
-}
-
-
-static inline long long _addsub2(unsigned int src1, unsigned int src2)
-{
- short s1[2], s2[2], ra[2], rs[2];
- int res_lo;
- int res_hi;
-
- *((int*)s1) = src1;
- *((int*)s2) = src2;
- ra[0] = s1[0] + s2[0];
- ra[1] = s1[1] + s2[1];
- rs[0] = s1[0] - s2[0];
- rs[1] = s1[1] - s2[1];
-
- res_hi = *(int*)ra;
- res_lo = *(int*)rs;
- return (((unsigned long long) res_hi) << 32) | ((unsigned int) res_lo) ;
-}
-
-
-static inline int _avg2(int src1, int src2) {
- int low = (((int)1 + (short) src1 + (short) src2) >> 1) & 0XFFFF;
- int high1 = src1 >> 16;
- int high2 = src2 >> 16;
- int high = ((high1 + high2 + 1) >> 1)<< 16;
- return high | low;
-}
-
-
-
-static inline unsigned int _avgu4(unsigned int src1, unsigned int src2) {
-unsigned int res0 = ((src1 & 0xFF) + (src2 & 0xFF) + 1) >> 1;
- unsigned int res1 = (((src1 & 0xFF00) >> 8) + ((src2 & 0xFF00) >> 8) + 1) >> 1;
- unsigned int res2 = (((src1 & 0xFF0000) >> 16) + ((src2 & 0xFF0000) >> 16) + 1) >> 1;
- unsigned int res3 = (((src1 & 0xFF000000) >> 24) + ((src2 & 0xFF000000) >> 24) + 1) >> 1;
- return (res3 << 24) | (res2 << 16) | (res1 << 8) | res0;
-}
-
-
-static inline int TEN_popc (unsigned char b)
-{
- int i, result = 0;
- for (i = 0; i < 8; i++){
- if (b & 0x1)
- result++;
- b >>= 1;
- }
- return result;
-}
-
-static inline unsigned int _bitc4(unsigned int src1)
-{
- unsigned int res0 = TEN_popc(src1 & 0xFF);
- unsigned int res1 = TEN_popc((src1 & 0xFF00) >> 8);
- unsigned int res2 = TEN_popc((src1 & 0xFF0000) >> 16);
- unsigned int res3 = TEN_popc((src1 & 0xFF000000) >> 24);
- return (res3 << 24) | (res2 << 16) | (res1 << 8) | res0;
-}
-
-static inline unsigned int _bitr(unsigned int src) {
- int i;
- unsigned r = 0;
- for (i = 0; i< 32; ++i) {
- r = r | (((src >> i) & 1)<<(31-i));
- }
- return r;
-}
-
-
-static inline unsigned int _clr(unsigned int src2, int csta, int cstb)
-{
- csta &= 0x1f;
- cstb &= 0x1f;
- if (csta > cstb)
- return src2;
- else {
- unsigned int mask = (((1 << (cstb - csta)) << 1) - 1) << csta;
- return src2 & (~mask);
- }
-}
-
-static inline unsigned int _clrr(unsigned int src2, int src1)
-{
- unsigned int csta = (src1 >> 5) & 0x1f;
- unsigned int cstb = src1 & 0x1f;
- if (csta > cstb)
- return src2;
- else {
- unsigned int mask = (((1 << (cstb - csta)) << 1) - 1) << csta;
- return src2 & (~mask);
- }
-}
-
-
-
-
-static inline int _cmpeq2(int src1, int src2) {
- short s1[2], s2[2];
- int r0, r1;
- int result;
- *((int*)s1) = src1;
- *((int*)s2) = src2;
- r0 = s1[0] == s2[0] ? 1 : 0;
- r1 = s1[1] == s2[1] ? 1 : 0;
- result = (r1 << 1) | r0;
- return result;
-}
-
-static inline int _cmpeq4(int src1, int src2) {
- char s1[4], s2[4];
- int r0, r1, r2, r3;
- int result;
- *((int*)s1) = src1;
- *((int*)s2) = src2;
- r0 = s1[0] == s2[0] ? 1 : 0;
- r1 = s1[1] == s2[1] ? 1 : 0;
- r2 = s1[2] == s2[2] ? 1 : 0;
- r3 = s1[3] == s2[3] ? 1 : 0;
- result = (r3 << 3) | (r2 << 2) | (r1 << 1) | r0;
- return result;
-}
-
-
-static inline int _cmpgt2(int src1, int src2) {
- short s1[2], s2[2];
- int r1, r0;
- int result;
- *((int*)s1) = src1;
- *((int*)s2) = src2;
- r0 = s1[0] > s2[0] ? 1 : 0;
- r1 = s1[1] > s2[1] ? 1 : 0;
- result = (r1<<1) | r0;
- return result;
-}
-
-
-static inline unsigned int _cmpgtu4(unsigned int src1, unsigned int src2) {
- unsigned int s1_0 = (src1 & 0xFF);
- unsigned int s1_1 = (src1 & 0xFF00) >> 8;
- unsigned int s1_2 = (src1 & 0xFF0000) >> 16;
- unsigned int s1_3 = (src1 & 0xFF000000) >> 24;
-
- unsigned int s2_0 = (src2 & 0xFF);
- unsigned int s2_1 = (src2 & 0xFF00) >> 8;
- unsigned int s2_2 = (src2 & 0xFF0000) >> 16;
- unsigned int s2_3 = (src2 & 0xFF000000) >> 24;
-
- unsigned int result = 0;
-
- if (s1_0 > s2_0)
- result |= 0x1;
-
- if (s1_1 > s2_1)
- result |= 0x2;
-
- if (s1_2 > s2_2)
- result |= 0x4;
-
- if (s1_3 > s2_3)
- result |= 0x8;
-
- return result;
-}
-
-
-
-
-static inline long long _ddotp4(unsigned int src1, unsigned int src2) {
- unsigned int res0, res1;
- short s1_0 = (src1 & 0xffff);
- short s1_1 = (src1 & 0xfff0000) >> 16;
-
- unsigned short s2_0 = (src2 & 0xff);
- unsigned short s2_1 = (src2 & 0xff00) >> 8;
- unsigned short s2_2 = (src2 & 0xff0000) >> 16;
- unsigned short s2_3 = (src2 & 0xff000000) >> 24;
-
- res0 = ((int)s1_0) * s2_0 + ((int)s1_1) * s2_1;
- res1 = ((int)s1_0) * s2_2 + ((int)s1_1) * s2_3;
-
- return (res1 << 16) | res0;
-}
-
-
-static inline long long _ddotph2(long long src1_o_src1_e, unsigned int src2)
-{
-
- unsigned int src1_o = src1_o_src1_e >> 32;
- unsigned int src1_e = src1_o_src1_e & 0xFFFFFFFF;
- short ls1_o = src1_o & 0XFFFF;
- short hs1_o = src1_o >> 16;
-// short ls1_e = src1_e & 0XFFFF;
- short hs1_e = src1_e >> 16;
- short ls2 = src2 & 0XFFFF;
- short hs2 = src2 >> 16;
-
- unsigned long long res_hi = ls2 * ls1_o + hs2 * hs1_o;
- unsigned int res_lo = ls1_o * hs2 + hs1_e * ls2;
- return (res_hi << 32) | res_lo;
-}
-
-
-static inline long long _ddotpl2(long long src1_o_src1_e, unsigned int src2)
-{
- unsigned int src1_o = src1_o_src1_e >> 32;
- unsigned int src1_e = src1_o_src1_e & 0xFFFFFFFF;
- short ls1_o = src1_o & 0XFFFF;
-// short hs1_o = src1_o >> 16;
- short ls1_e = src1_e & 0XFFFF;
- short hs1_e = src1_e >> 16;
- short ls2 = src2 & 0XFFFF;
- short hs2 = src2 >> 16;
-
- unsigned long long res_hi = ls2 * hs1_e + hs2 * ls1_o;
- unsigned res_lo = hs1_e * hs2 + ls1_e * ls2;
- return (res_hi << 32) | res_lo;
-}
-
-
-static inline unsigned int _deal(unsigned int src)
-{
- int i;
- unsigned short lo = 0, hi = 0;
- for (i = 0; i < 32; i+= 2) {
- lo >>= 1;
- lo |= (src & 0x1) << 15;
- src >>= 1;
- hi >>= 1;
- hi |= (src & 0x1) << 15;
- src >>= 1;
- }
- return (hi << 16) | lo;
-}
-
-
-static inline long long _dmv(unsigned int src1, unsigned int src2)
-{
- return (((long long) src1) << 32) | src2;
-}
-
-
-static inline int _dotpn2(int src1, int src2) {
-short int s1_h = src1>>16;
- short int s1_l = src1;
- short int s2_h = src2>>16;
- short int s2_l = src2;
- return s1_h * s2_h - s1_l * s2_l;
-}
-
-
-static inline int _dotp2(int src1, int src2) {
- short int s1_h = src1>>16;
- short int s1_l = src1;
- short int s2_h = src2>>16;
- short int s2_l = src2;
- return s1_h * s2_h + s1_l * s2_l;
-}
-
-
-
-static inline int _dotpnrsu2(int src1, unsigned int src2)
-{
- short ls1 = src1 & 0XFFFF;
- unsigned short ls2 = src2 & 0XFFFF;
- short hs1 = src1 >> 16;
- unsigned short hs2 = src2 >> 16;
-
- int result = (((long long) (int)(hs1 * hs2)) - ((long long) (int)(ls1 * ls2)) + (1 << 15)) >> 16;
- return result;
-}
-
-
-
-static inline int _dotprsu2(int src1, unsigned int src2) {
- short ls1 = src1 & 0XFFFF;
- unsigned short ls2 = (src2 & 0XFFFF);
- short hs1 = src1 >> 16;
- unsigned short hs2 = (src2 >> 16);
-
- int result = (((long long) (int) (ls1 * ls2)) + ((long long) (int) (hs1 * hs2)) + (1LL << 15)) >> 16;
- return result;
-}
-
-
-
-
-
-
-
-static inline int _dotpsu4(int src1, unsigned int src2) {
- int result;
- signed char s1_0 = (src1 & 0xff);
- signed char s1_1 = (src1 & 0xff00) >> 8;
- signed char s1_2 = (src1 & 0xff0000) >> 16;
- signed char s1_3 = (src1 & 0xff000000) >> 24;
-
- unsigned int s2_0 = (src2 & 0xff);
- unsigned int s2_1 = (src2 & 0xff00) >> 8;
- unsigned int s2_2 = (src2 & 0xff0000) >> 16;
- unsigned int s2_3 = (src2 & 0xff000000) >> 24;
-
- result = s1_0 * s2_0 + s1_1 * s2_1 + s1_2 * s2_2 + s1_3 * s2_3;
- return result;
-}
-
-
-static inline unsigned int _dotpu4(unsigned int src1, unsigned int src2) {
- unsigned char v1_0 = src1 & 0xff;
- unsigned char v1_1 = (src1>>8) & 0xff;
- unsigned char v1_2 = (src1>>16) & 0xff;
- unsigned char v1_3 = (src1>>24) & 0xff;
-
- unsigned char v2_0 = src2 & 0xff;
- unsigned char v2_1 = (src2>>8) & 0xff;
- unsigned char v2_2 = (src2>>16) & 0xff;
- unsigned char v2_3 = (src2>>24) & 0xff;
-
- unsigned v = v1_0 * v2_0 + v1_1 * v2_1 + v1_2 * v2_2 + v1_3 * v2_3;
- return v;
-}
-
-
-static inline long long _dpack2(unsigned int src1, unsigned int src2){
-unsigned short s1[2], s2[2];
-*((int*)s1) = src1;
-*((int*)s2) = src2;
-return ((unsigned long long) s1[1] << 48) | ((unsigned long long) s2[1] << 32) | ((unsigned long long) s1[0] << 16) | ((unsigned long long) s2[0]);
-}
-
-
-static inline long long _dpackx2(unsigned int src1, unsigned int src2){
-unsigned short s1[2], s2[2];
-*((int*)s1) = src1;
-*((int*)s2) = src2;
-return ((unsigned long long) s2[0] << 48) | ((unsigned long long) s1[1] << 32) | ((unsigned long long) s1[0] << 16) | ((unsigned long long) s2[1]);
-}
-
-static inline int _ext(int src2, unsigned int csta, unsigned int cstb)
-{
- return (src2 << csta) >> cstb;
-}
-
-static inline int _extr(int src2, int src1)
-{
- unsigned int csta = (src1 >> 5) & 0x1f;
- unsigned int cstb = src1 & 0x1f;
- return (src2 << csta) >> cstb;
-}
-
-static inline unsigned int _extu(unsigned int src2, unsigned int csta, unsigned int cstb)
-{
- return (src2 << csta) >> cstb;
-}
-
-static inline unsigned int _extur(unsigned int src2, int src1)
-{
- unsigned int csta = (src1 >> 5) & 0x1f;
- unsigned int cstb = src1 & 0x1f;
- return (src2 << csta) >> cstb;
-}
-
-
-static inline unsigned long long _hi(double src) {
- unsigned long long v;
- *(double*)&v = src;
- return v>>32;
-}
-
-static inline unsigned int _hill (long long src)
-{
- return (unsigned int) (src >> 32);
-}
-
-
-
-static inline double _itod(unsigned hi, unsigned lo) {
- double v;
- unsigned long long ll = ((((unsigned long long)(hi))<<32) | (unsigned long long)((unsigned)lo));
- *((unsigned long long *)&v) = ll;
- return v;
-}
-
-
-static inline long long _itoll(unsigned int src2, unsigned int src1)
-{
- return (((long long) src2) << 32) | src1;
-}
-
-
-static inline C6X_COMPAT_LONG40 _labs(C6X_COMPAT_LONG40 src2)
-{
- long long maxv = (1LL << (40 -1)) - 1;
- long long minv = (-1LL << (40 - 1));
- C6X_COMPAT_LONG40 lres = orig_L40_set(src2);
-
- lres = lres < 0 ? -lres : lres;
- if (lres > maxv) lres = maxv;
- else if (lres < minv) lres = minv;
-
- return lres;
-}
-
-
-static inline C6X_COMPAT_LONG40 _ldotp2(int src1, int src2) {
-return (C6X_COMPAT_LONG40) _dotp2(src1, src2);
-}
-
-
-static inline unsigned int _lmbd(unsigned int src1, unsigned int src2)
-{
- return norm_shift_amt_U_and_non_U(0,(((int) (src1 << 31)) >> 31) ^ (~src2));
-}
-
-
-static inline unsigned int _lnorm(C6X_COMPAT_LONG40 src2) {
-if (src2 == 0)
- return 39;
- else {
- int hi = (int)(src2 >> 32);
- int lo = (int)src2;
-
-
- long long temp = (unsigned long long)(unsigned)lo | (unsigned long long)hi << 32;
- temp = orig_L40_set(temp);
-
- if (temp == 0) return 0;
- int cnt = 0;
- while (((temp >> 39) & 1) == ((temp >> 38) & 1)) {
- temp <<= 1;
- cnt++;
- }
- return cnt;
- }
-}
-
-
-static inline unsigned long long _lo(double src) {
- unsigned long long v;
- *(double*)&v = src;
- return v;
-}
-
-
-static inline unsigned int _loll (long long src)
-{
- return (unsigned int) src;
-}
-
-
-static inline C6X_COMPAT_LONG40 _lsadd(int src1, C6X_COMPAT_LONG40 src2)
-{
- long long maxv = (1LL << (40 -1)) - 1;
- long long minv = (-1LL << (40 - 1));
- int hi = (int)(src2 >> 32);
- int lo = (int)src2;
- long long src2_int = (unsigned long long)(unsigned)lo | (unsigned long long)hi << 32;
-
-
- long long src2_int2 = orig_L40_set(src2_int);
-
- long long res = src1 + src2_int2;
-
- if (res > maxv) {
- res = maxv;
- _overflow = 1;
- }
- else if (res < minv) {
- res = minv;
- _overflow = 1;
- }
-
- long long res2 = orig_L40_set(res);
-
- res2 = (signed char)(res2 >> 32);
-
- C6X_COMPAT_LONG40 lres = (((C6X_COMPAT_LONG40) res2) << 32) | ((unsigned int)res);
- return lres;
-}
-
-
-
-static inline int _max2 (int src1, int src2) {
- short s1[2], s2[2], r[2];
- int result;
- *((int*)s1) = src1;
- *((int*)s2) = src2;
- r[0] = s1[0] > s2[0] ? s1[0] : s2[0];
- r[1] = s1[1] > s2[1] ? s1[1] : s2[1];
- result = *(int*)r;
- return result;
-}
-
-
-
-
-
-
-static inline unsigned int _maxu4(unsigned int src1, unsigned int src2) {
- unsigned int res0, res1, res2, res3;
- unsigned int s1_0 = res0 = (src1 & 0xFF);
- unsigned int s1_1 = res1 = (src1 & 0xFF00) >> 8;
- unsigned int s1_2 = res2 = (src1 & 0xFF0000) >> 16;
- unsigned int s1_3 = res3 = (src1 & 0xFF000000) >> 24;
-
- unsigned int s2_0 = (src2 & 0xFF);
- unsigned int s2_1 = (src2 & 0xFF00) >> 8;
- unsigned int s2_2 = (src2 & 0xFF0000) >> 16;
- unsigned int s2_3 = (src2 & 0xFF000000) >> 24;
-
-// unsigned int res = 0;
-
- if (s1_0 < s2_0)
- res0 = s2_0;
-
- if (s1_1 < s2_1)
- res1 = s2_1;
-
- if (s1_2 < s2_2)
- res2 = s2_2;
-
- if (s1_3 < s2_3)
- res3 = s2_3;
-
- return (res3 << 24) | (res2 << 16) | (res1 << 8) | res0;
-
-
-}
-
-static inline int _min2(int src1, int src2) {
- short s1[2], s2[2], r[2];
- int result;
- *((int*)s1) = src1;
- *((int*)s2) = src2;
- r[0] = s1[0] < s2[0] ? s1[0] : s2[0];
- r[1] = s1[1] < s2[1] ? s1[1] : s2[1];
- result = *(int*)r;
- return result;
-}
-
-
-static inline unsigned int _minu4(unsigned int src1, unsigned int src2) {
-unsigned int res0, res1, res2, res3;
- unsigned int s1_0 = res0 = (src1 & 0xFF);
- unsigned int s1_1 = res1 = (src1 & 0xFF00) >> 8;
- unsigned int s1_2 = res2 = (src1 & 0xFF0000) >> 16;
- unsigned int s1_3 = res3 = (src1 & 0xFF000000) >> 24;
-
- unsigned int s2_0 = (src2 & 0xFF);
- unsigned int s2_1 = (src2 & 0xFF00) >> 8;
- unsigned int s2_2 = (src2 & 0xFF0000) >> 16;
- unsigned int s2_3 = (src2 & 0xFF000000) >> 24;
-
-// unsigned int res = 0;
-
- if (s1_0 > s2_0)
- res0 = s2_0;
-
- if (s1_1 > s2_1)
- res1 = s2_1;
-
- if (s1_2 > s2_2)
- res2 = s2_2;
-
- if (s1_3 > s2_3)
- res3 = s2_3;
-
- return (res3 << 24) | (res2 << 16) | (res1 << 8) | res0;
-}
-
-
-static inline int _mpy(int src1, int src2) {
-return (short) src1 * (short) src2;
-}
-
-
-static inline int _mpyh(int src1, int src2) {
-return (short) (src1 >> 16) * (short) (src2 >> 16);
-}
-
-
-static inline long long _mpyhill (int src1, int src2)
-{
- short s1 = src1 >> 16;
- return ((long long) src2) * s1;
-}
-
-static inline int _mpyhir(int src1, int src2)
-{
- short s1 = src1 >> 16;
- long long result = ((long long) src2) * s1 + (1 << 14);
- result >>= 15;
- return result;
-}
-
-
-static inline int _mpyhl(int src1, int src2) {
-return (short) (src1 >> 16) * (short) (src2);
-}
-
-static inline unsigned int _mpyhlu(unsigned int src1, unsigned int src2) {
-return (unsigned short) (src1 >> 16) * (unsigned short) (src2);
-}
-
-static inline int _mpyhslu(int src1, unsigned int src2) {
-return (short) (src1 >> 16) * (unsigned short) src2;
-}
-
-
-static inline int _mpyhsu(int src1, unsigned int src2) {
-return (short) (src1 >>16) * (unsigned short) (src2 >>16);
-}
-
-
-static inline unsigned int _mpyhu(unsigned int src1, unsigned int src2) {
-return (unsigned short) (src1 >>16) * (unsigned short) (src2 >> 16);
-}
-
-
-static inline int _mpyhuls(unsigned int src1, int src2) {
-return (unsigned short) (src1 >>16) * (signed short) (src2);
-}
-
-
-static inline int _mpyhus(unsigned int src1, int src2) {
-return (unsigned short) (src1 >> 16) * (short) (src2 >>16);
-}
-
-
-
-static inline long long _mpyidll (int src1, int src2)
-{
- return (long long) src1 * src2;
-}
-
-
-static inline int _mpylh(int src1, int src2) {
-return (signed short) (src1 & 0xffff) * (signed short) (src2 >> 16);
-}
-
-static inline unsigned int _mpylhu(unsigned int src1, unsigned int src2) {
-return (unsigned short) src1 * (unsigned short) (src2 >> 16);
-}
-
-
-static inline long long _mpylill (int src1, int src2)
-{
- return ((long long) src2) * ((short)src1);
-}
-
-
-
-static inline int _mpylir(int src1, int src2)
-{
- short s1 = src1;
- long long result = ((long long) src2) * s1 + (1 << 14);
- result >>= 15;
- return result;
-}
-
-
-static inline int _mpylshu(int src1, unsigned int src2) {
-return (short) src1 * (unsigned short) (src2 >> 16);
-}
-
-
-static inline int _mpyluhs(unsigned int src1, int src2) {
-return (unsigned short) src1 * (short) (src2 >> 16);
-}
-
-
-
-static inline int _mpysu(int src1, unsigned int src2) {
-return (short) src1 * (unsigned short) src2;
-}
-
-
-
-static inline long long _mpysu4ll (int src1, unsigned int src2) {
- unsigned short res0, res1, res2, res3;
- signed char s1_0 = (src1 & 0xff);
- signed char s1_1 = (src1 & 0xff00) >> 8;
- signed char s1_2 = (src1 & 0xff0000) >> 16;
- signed char s1_3 = (src1 & 0xff000000) >> 24;
-
- unsigned short s2_0 = (src2 & 0xff);
- unsigned short s2_1 = (src2 & 0xff00) >> 8;
- unsigned short s2_2 = (src2 & 0xff0000) >> 16;
- unsigned short s2_3 = (src2 & 0xff000000) >> 24;
-
- res0 = s1_0 * s2_0;
- res1 = s1_1 * s2_1;
- res2 = s1_2 * s2_2;
- res3 = s1_3 * s2_3;
-
- return (((unsigned long long) res3) << 48)
- | (((unsigned long long) res2) << 32)
- | (((unsigned long long) res1) << 16)
- | res0;
-}
-
-static inline unsigned int _mpyu(unsigned int src1, unsigned int src2) {
- unsigned v = (unsigned short)src1 * (unsigned short)src2;
- return v;
-}
-
-static inline int _mpyus(unsigned int src1, int src2) {
-return (unsigned short) src1 * (short) src2;
-}
-
-static inline long long _mpyu4ll (unsigned int src1, unsigned int src2) {
- unsigned short res0, res1, res2, res3;
- unsigned char s1_0 = (src1 & 0xff);
- unsigned char s1_1 = (src1 & 0xff00) >> 8;
- unsigned char s1_2 = (src1 & 0xff0000) >> 16;
- unsigned char s1_3 = (src1 & 0xff000000) >> 24;
-
- unsigned short s2_0 = (src2 & 0xff);
- unsigned short s2_1 = (src2 & 0xff00) >> 8;
- unsigned short s2_2 = (src2 & 0xff0000) >> 16;
- unsigned short s2_3 = (src2 & 0xff000000) >> 24;
-
- res0 = s1_0 * s2_0;
- res1 = s1_1 * s2_1;
- res2 = s1_2 * s2_2;
- res3 = s1_3 * s2_3;
-
- return (((unsigned long long) res3) << 48)
- | (((unsigned long long) res2) << 32)
- | (((unsigned long long) res1) << 16)
- | res0;
-}
-
-
-static inline long long _mpy2ir(unsigned int src1, unsigned int src2)
-{
- if ((src1 == 0x8000) && (src2 == 0x80000000)) {
- _overflow = 1;
- return 0;
- }
- else {
- short ls1 = src1 & 0xffff;
- short hs1 = src1 >> 16;
- unsigned long long hi = (((long long) hs1) * (int) src2 + (1 << 14)) >> 15;
- unsigned long long lo = ((((long long) ls1) * (int) src2 + (1 << 14)) >> 15) & 0xFFFFFFFF;
- return (hi << 32) | lo;
- }
-}
-
-
-static inline long long _mpy2ll (int src1, int src2) {
- short ls1 = src1 & 0xffff;
- short hs1 = src1 >> 16;
- short ls2 = src2 & 0xffff;
- short hs2 = src2 >> 16;
-
- unsigned long long hi = hs1 * hs2;
- unsigned long long lo = (ls1 * ls2) & 0xFFFFFFFF;
-
- return (hi << 32) | lo;
-
-}
-
-
-static inline int _mpy32(int src1, int src2)
-{
- return src1 * src2;
-}
-
-
-static inline long long _mpy32ll(int src1, int src2)
-{
- return ((long long) src1) * src2;
-}
-
-static inline long long _mpy32su(int src1, unsigned int src2)
-{
- return ((long long) src1) * ((int) src2);
-}
-
-static inline long long _mpy32u(unsigned int src1, unsigned int src2)
-{
- return ((long long) ((int) src1)) * ((long long) ((int) src2));
-}
-
-static inline long long _mpy32us(unsigned int src1, int src2)
-{
- return ((int) src1) * ((long long) src2);
-}
-
-static inline int _mvd (int src2)
-{
- return src2;
-}
-
-
-static inline unsigned int _norm(int src2)
-{
- return norm_shift_amt_U_and_non_U(1,src2);
-}
-
-
-static inline unsigned int _pack2 (unsigned int src1, unsigned int src2) {
- short s1[2], s2[2], r[2];
- int result;
- *((int*)s1) = src1;
- *((int*)s2) = src2;
- r[0] = s2[0];
- r[1] = s1[0];
- result = *(int*)r;
- return result;
-}
-
-
-static inline int _packh2 (unsigned int src1, unsigned int src2) {
- unsigned v0 = src1 & 0xffff0000;
- unsigned v1 = src2 >> 16;
- unsigned v = v0|v1;
- return v;
-
-}
-
-static inline unsigned int _packh4 (unsigned int src1, unsigned int src2) {
- unsigned v3 = (src1 >> 24) & 0xff;
- unsigned v2 = (src1 >> 8) & 0xff;
- unsigned v1 = (src2 >> 24) & 0xff;
- unsigned v0 = (src2 >> 8) & 0xff;
- unsigned v = (v3<<24) | (v2<<16) | (v1 << 8) | v0;
- return v;
-}
-
-static inline unsigned int _packhl2 (unsigned int src1, unsigned int src2) {
- unsigned v0 = src1 & 0xffff0000;
- unsigned v1 = src2 & 0x0000ffff;
- unsigned v = v0|v1;
- return v;
-}
-
-static inline unsigned int _packlh2 (unsigned int src1, unsigned int src2) {
- unsigned v0 = src1 << 16;
- unsigned v1 = (src2 >> 16) & 0xffff;
- unsigned v = v0|v1;
- return v;
-}
-
-
-
-
-static inline unsigned int _packl4 (unsigned int src1, unsigned int src2) {
- unsigned v3 = (src1 >> 16) & 0xff;
- unsigned v2 = (src1) & 0xff;
- unsigned v1 = (src2 >> 16) & 0xff;
- unsigned v0 = (src2) & 0xff;
- unsigned v = (v3<<24) | (v2<<16) | (v1 << 8) | v0;
- return v;
-}
-
-
-
-
-static inline unsigned int _rpack2 (unsigned int src1, unsigned int src2) {
-int s1 = (int) src1;
-int s2 = (int) src2;
-s1 = util_shift_right_saturate_n (s1, -1, 32);
-s2 = util_shift_right_saturate_n (s2, -1, 32);
-return (unsigned int) (s1 & 0xffff0000) | (unsigned int) ((s2 & 0xffff0000) >>16);
-}
-
-
-static inline unsigned int _rotl (unsigned int src1, unsigned int src2)
-{
- src2 &= 0x1f;
- return (src1 << src2) | (src1 >> (32 - src2));
-}
-
-
-static inline int _sadd(int src1, int src2) {
-signed long long res;
-signed long long maxv, minv;
-maxv = (1LL << (32-1)) - 1;
-minv = (-1LL << (32-1));
-res = (long long) src1 + (long long) src2;
-if (res > maxv) {
- res = maxv;
- _overflow = 1;
- }
-else if (res < minv ) {
- res = minv;
- _overflow = 1;
- }
-return (int) res;
-}
-
-static inline long long _saddsub(unsigned int src1, unsigned int src2) {
-int radd;
-signed long long rsub;
-
-signed long long maxv, minv;
-maxv = (1LL << (32-1)) - 1;
-minv = (-1LL << (32-1));
-
-radd = (int) src1 + (int) src2;
-
-// saturate on subtract, not add
-
-
-rsub = (long long) ((int) src1) - (long long) ((int) src2);
-if (rsub > maxv) {
- rsub = maxv;
- /* NOTE: TI c6x does NOT set the overflow register even if results saturate */
- /* _overflow = 1; */
- }
-else if (rsub < minv ) {
- rsub = minv;
- /* NOTE: TI c6x does NOT set the overflow register even if results saturate */
- /* _overflow = 1; */
- }
-
-return (((unsigned long long) radd) << 32) | ( rsub & 0x00000000ffffffff ) ;
-}
-
-
-
-static inline long long _saddsub2(unsigned int src1, unsigned int src2) {
-signed int radd[2];
-signed int rsub[2];
-signed short s1[2], s2[2];
-
-signed int maxv, minv;
-maxv = (1L << (16-1)) - 1;
-minv = (-1L << (16-1));
-
-*((int*)s1) = src1;
-*((int*)s2) = src2;
-
-radd[0] = (int) s1[0] + (int) s2[0];
-radd[1] = (int) s1[1] + (int) s2[1];
-
-rsub[0] = (int) s1[0] - (int) s2[0];
-rsub[1] = (int) s1[1] - (int) s2[1];
-
-if (radd[0] > maxv) {
- radd[0] = maxv;
- /* NOTE: TI c6x does NOT set the overflow register even if results saturate */
- /* _overflow = 1; */
- }
-else if (radd[0] < minv ) {
- radd[0] = minv;
- /* NOTE: TI c6x does NOT set the overflow register even if results saturate */
- /* _overflow = 1; */
- }
-
-if (radd[1] > maxv) {
- radd[1] = maxv;
- /* NOTE: TI c6x does NOT set the overflow register even if results saturate */
- /* _overflow = 1; */
- }
-else if (radd[1] < minv ) {
- radd[1] = minv;
- /* NOTE: TI c6x does NOT set the overflow register even if results saturate */
- /* _overflow = 1; */
- }
-
-
-if (rsub[0] > maxv) {
- rsub[0] = maxv;
- /* NOTE: TI c6x does NOT set the overflow register even if results saturate */
- /* _overflow = 1; */
- }
-else if (rsub[0] < minv ) {
- rsub[0] = minv;
- /* NOTE: TI c6x does NOT set the overflow register even if results saturate */
- /* _overflow = 1; */
- }
-
-if (rsub[1] > maxv) {
- rsub[1] = maxv;
- /* NOTE: TI c6x does NOT set the overflow register even if results saturate */
- /* _overflow = 1; */
- }
-else if (rsub[1] < minv ) {
- rsub[1] = minv;
- /* NOTE: TI c6x does NOT set the overflow register even if results saturate */
- /* _overflow = 1; */
- }
-
-
-return ((((unsigned long long) radd[1]) & 0x000000000000ffff) << 48) |
- ((((unsigned long long) radd[0]) & 0x000000000000ffff) << 32) |
- ((((unsigned long long) rsub[1]) & 0x000000000000ffff) << 16) |
- ((((unsigned long long) rsub[0]) & 0x000000000000ffff));
-}
-
-
-
-static inline int _sadd2(int src1, int src2) {
-signed short s1[2], s2[2];
-signed int r[2], maxv, minv;
-
-maxv = (1L << (16-1)) - 1;
-minv = (-1L << (16-1));
-
-
-*((int*)s1) = src1;
-*((int*)s2) = src2;
-
-r[0] = (int) s1[0] + (int) s2[0];
-r[1] = (int) s1[1] + (int) s2[1];
-
-if (r[0] > maxv) {
- r[0] = maxv;
- /* NOTE: TI c6x does NOT set the overflow register even if results saturate */
- /* _overflow = 1; */
- }
-else if (r[0] < minv ) {
- r[0] = minv;
- /* NOTE: TI c6x does NOT set the overflow register even if results saturate */
- /* _overflow = 1; */
- }
-if (r[1] > maxv) {
- r[1] = maxv;
- /* NOTE: TI c6x does NOT set the overflow register even if results saturate */
- /* _overflow = 1; */
- }
-else if (r[1] < minv ) {
- r[1] = minv;
- /* NOTE: TI c6x does NOT set the overflow register even if results saturate */
- /* _overflow = 1; */
- }
-
-return ((r[1] & 0xffff) << 16 ) | (r[0] & 0xffff) ;
-}
-
-
-static inline int _saddus2(unsigned int src1, int src2) {
-int res0, res1;
- unsigned int s1_0 = (src1 & 0xffff);
- unsigned int s1_1 = (src1 & 0xffff0000) >> 16;
-
- short s2_0 = (src2 & 0xffff);
- short s2_1 = (src2 & 0xffff0000) >> 16;
-
- res0 = s1_0 + s2_0;
- res1 = s1_1 + s2_1;
-
- if (res0 >= 0x10000)
- res0 = 0xffff;
- else if (res0 < 0)
- res0 = 0;
-
- if (res1 >= 0x10000)
- res1 = 0xffff;
- else if (res1 < 0)
- res1 = 0;
-
- return (res1 << 16) | res0;
-}
-
-
-static inline unsigned int _saddu4(unsigned int src1, unsigned int src2) {
-unsigned int res0, res1, res2, res3;
- unsigned int s1_0 = (src1 & 0xff);
- unsigned int s1_1 = (src1 & 0xff00) >> 8;
- unsigned int s1_2 = (src1 & 0xff0000) >> 16;
- unsigned int s1_3 = (src1 & 0xff000000) >> 24;
-
- unsigned int s2_0 = (src2 & 0xff);
- unsigned int s2_1 = (src2 & 0xff00) >> 8;
- unsigned int s2_2 = (src2 & 0xff0000) >> 16;
- unsigned int s2_3 = (src2 & 0xff000000) >> 24;
-
- res0 = s1_0 + s2_0;
- res1 = s1_1 + s2_1;
- res2 = s1_2 + s2_2;
- res3 = s1_3 + s2_3;
-
- if (res0 >= 0x100)
- res0 = 0xff;
-
- if (res1 >= 0x100)
- res1 = 0xff;
-
- if (res2 >= 0x100)
- res2 = 0xff;
-
- if (res3 >= 0x100)
- res3 = 0xff;
-
- return (res3 << 24) | (res2 << 16) | (res1 << 8) | res0;
-
-}
-
-
-
-static inline int _sat(C6X_COMPAT_LONG40 src2)
-{
- long long maxv = (1LL << (32-1)) - 1;
- long long minv = (-1LL << (32-1));
-
- int hi = (int)(src2 >> 32);
- int lo = (int)src2;
- long long temp = (unsigned long long)(unsigned)lo | (unsigned long long)hi << 32;
- temp = orig_L40_set(temp);
-
- if (temp > maxv) {
- temp = maxv;
- _overflow = 1;
- }
- else if (temp < minv) {
- temp = minv;
- _overflow = 1;
- }
- return (int) temp;
-}
-
-static inline unsigned int _set(unsigned int src2, unsigned int csta, unsigned int cstb)
-{
- csta &= 0x1f;
- cstb &= 0x1f;
- if (csta > cstb)
- return src2;
- else {
- unsigned int mask = (((1 << (cstb - csta)) << 1) - 1) << csta;
- return src2 | mask;
- }
-}
-
-static inline unsigned int _setr(unsigned int src2, int src1)
-{
- unsigned int csta = (src1 >> 5) & 0x1f;
- unsigned int cstb = src1 & 0x1f;
- if (csta > cstb)
- return src2;
- else {
- unsigned int mask = (((1 << (cstb - csta)) << 1) - 1) << csta;
- return src2 | mask;
- }
-}
-
-
-static inline unsigned int _shfl (unsigned int src2)
-{
- unsigned short lo = src2;
- unsigned short hi = src2 >> 16;
- unsigned int result = 0;
- int i;
- for (i = 0; i < 32; i+= 2) {
- result >>= 1;
- result |= (lo & 0x1) << 31;
- lo >>= 1;
- result >>= 1;
- result |= (hi & 0x1) << 31;
- hi >>= 1;
- }
- return result;
-}
-
-static inline long long _shfl3 (unsigned int src1, unsigned int src2)
-{
- unsigned short lo = src2;
- unsigned short hi = src1 >> 16;
- unsigned short mid = src1;
- unsigned long long result = 0;
- int i;
- for (i = 0; i < 32; i+= 2) {
- result >>= 1;
- result |= ((unsigned long long) (lo & 0x1)) << 47;
- lo >>= 1;
- result >>= 1;
- result |= ((unsigned long long) (mid & 0x1)) << 47;
- mid >>= 1;
- result >>= 1;
- result |= ((unsigned long long) (hi & 0x1)) << 47;
- hi >>= 1;
- }
- return result;
-}
-
-
-
-static inline unsigned int _shlmb (unsigned int src1, unsigned int src2)
-{
- return (src2 << 8) | (src1 >> 24);
-}
-
-static inline unsigned int _shrmb (unsigned int src1, unsigned int src2)
-{
- return (src2 >> 8) | (src1 << 24);
-}
-
-
-static inline unsigned int _shru2 (unsigned int src1, unsigned int src2) {
-unsigned short hs1 = src1 >> 16;
- unsigned short ls1 = src1 & 0xFFFF;
- hs1 >>= src2;
- ls1 >>= src2;
- return (hs1 << 16) | ls1;
-}
-
-
-static inline int _shr2 (int src1, unsigned int src2) {
- short s1[2], result[2];
- *((int*)s1) = src1;
- src2 = src2 & 31;
- result[0] = (int)s1[0] >> src2;
- result[1] = (int)s1[1] >> src2;
-
- return *(int*)result;
-}
-
-
-static inline int _smpy (int src1, int src2) {
-unsigned long long result;
-result = (((short) src1 * (short) src2) << 1);
-
-if ((result & 0xffffffff) == 0x80000000){
- result = 0x7fffffff;
- _overflow = 1;
- }
-return (int) (result);
-}
-
-static inline int _smpyh (int src1, int src2) {
-unsigned long long result;
-result = ((short) (src1 >> 16) * (short) (src2 >> 16)) << 1;
-if ((result & 0xffffffff) == 0x80000000){
- result = 0x7fffffff;
- _overflow = 1;
- }
-return (int) (result);
-}
-
-static inline int _smpyhl (int src1, int src2) {
-unsigned long long result;
-result = ((short) (src1 >> 16) * (short) (src2)) << 1;
-if ((result & 0xffffffff) == 0x80000000){
- result = 0x7fffffff;
- _overflow = 1;
- }
-return (int) (result);
-}
-
-static inline int _smpylh (int src1, int src2) {
-unsigned long long result;
-result = ((short) (src1) * (short) (src2 >> 16)) << 1;
-if ((result & 0xffffffff) == 0x80000000){
- result = 0x7fffffff;
- _overflow = 1;
- }
-return (int) (result);
-}
-
-static inline long long _smpy2ll (int src1, int src2) {
- short ls1 = src1 & 0XFFFF;
- short hs1 = src1 >> 16;
- short ls2 = src2 & 0XFFFF;
- short hs2 = src2 >> 16;
-
- unsigned long long hi = (hs1 * hs2) << 1;
- unsigned long long lo = ((ls1 * ls2) << 1) & 0xFFFFFFFF;
- if ((hi & 0xffffffff) == 0x80000000){
- hi = 0x7fffffff;
- _overflow = 1;
- }
-
- if ((lo & 0xffffffff) == 0x80000000){
- lo = 0x7fffffff;
- _overflow = 1;
- }
-
- return (hi << 32) | lo;
-}
-
-
-
-
-static inline int _smpy32(int src1, int src2)
-{
- long long res = (long long) src1 * src2;
- res <<= 1;
- res >>= 32;
- return res;
-}
-
-static inline unsigned char TEN_satu8 (short src)
-{
- if (src > 0xff)
- return 0xff;
- else if (src < 0)
- return 0;
- else
- return src;
-}
-
-static inline int _spack2 (int src1, int src2) {
-short s1 = (short) util_saturate_n_no_state(src1,16);
-short s2 = (short) util_saturate_n_no_state(src2,16);
-return ( (unsigned int) s1 << 16) | (((int) s2) & 0xFFFF);
-}
-
-
-static inline unsigned int _spacku4 (int src1, int src2) {
- short lolo = src2;
- short lohi = src2 >> 16;
- short hilo = src1;
- short hihi = src1 >> 16;
-
- lolo = TEN_satu8(lolo);
- lohi = TEN_satu8(lohi);
- hilo = TEN_satu8(hilo);
- hihi = TEN_satu8(hihi);
-
- return (((unsigned int) hihi) << 24) | (((unsigned int) hilo) << 16) | (lohi << 8) | lolo;
-}
-
-
-
-static inline int _sshl (int src1, unsigned int src2) {
-short local2 = (short)(src2 & 0x7FFF);
-return (int) util_shift_right_saturate_n(src1, -local2, 32);
-}
-
-
-
-
-static inline int _sshvl (int src2, int src1) {
- short s1;
- if (src1 > 31)
- s1 = 31;
- else if (src1 < -31)
- s1 = -31;
- else
- s1 = src1;
-
- return (int) util_shift_right_saturate_n(src2, -s1, 32);
-}
-
-
-
-
-
-static inline int _sshvr (int src2, int src1) {
-short s1;
- if (src1 > 31)
- s1 = 31;
- else if (src1 < -31)
- s1 = -31;
- else
- s1 = src1;
- return (int) util_shift_right_saturate_n(src2, s1, 32);
-}
-
-
-
-
-static inline int _ssub(int src1, int src2) {
-signed long long res;
-signed long long maxv, minv;
-maxv = (1LL << (32-1)) - 1;
-minv = (-1LL << (32-1));
-res = (long long) src1 - (long long) src2;
-if (res > maxv) {
- res = maxv;
- _overflow = 1;
- }
-else if (res < minv ) {
- res = minv;
- _overflow = 1;
- }
-return (int) res;
-}
-
-static inline int _ssub2(int src1, int src2) {
-signed short s1[2], s2[2];
-signed int r[2], maxv, minv;
-
-maxv = (1L << (16-1)) - 1;
-minv = (-1L << (16-1));
-
-
-*((int*)s1) = src1;
-*((int*)s2) = src2;
-
-r[0] = (int) s1[0] - (int) s2[0];
-r[1] = (int) s1[1] - (int) s2[1];
-
-if (r[0] > maxv) {
- r[0] = maxv;
- /* NOTE: TI c6x does NOT set the overflow register even if results saturate */
- /* _overflow = 1; */
- }
-else if (r[0] < minv ) {
- r[0] = minv;
- /* NOTE: TI c6x does NOT set the overflow register even if results saturate */
- /* _overflow = 1; */
- }
-if (r[1] > maxv) {
- r[1] = maxv;
- /* NOTE: TI c6x does NOT set the overflow register even if results saturate */
- /* _overflow = 1; */
- }
-else if (r[1] < minv ) {
- r[1] = minv;
- /* NOTE: TI c6x does NOT set the overflow register even if results saturate */
- /* _overflow = 1; */
- }
-
-return ((r[1] & 0xffff) << 16 ) | (r[0] & 0xffff) ;
-}
-
-
-static inline int _subabs4 (int src1, int src2) {
- int res0, res1, res2, res3;
- unsigned int s1_0 = (src1 & 0xff);
- unsigned int s1_1 = (src1 & 0xff00) >> 8;
- unsigned int s1_2 = (src1 & 0xff0000) >> 16;
- unsigned int s1_3 = (src1 & 0xff000000) >> 24;
-
- unsigned int s2_0 = (src2 & 0xff);
- unsigned int s2_1 = (src2 & 0xff00) >> 8;
- unsigned int s2_2 = (src2 & 0xff0000) >> 16;
- unsigned int s2_3 = (src2 & 0xff000000) >> 24;
-
- res0 = s1_0 - s2_0;
- res1 = s1_1 - s2_1;
- res2 = s1_2 - s2_2;
- res3 = s1_3 - s2_3;
-
- if (res0 < 0)
- res0 = -res0;
-
- if (res1 < 0)
- res1 = -res1;
-
- if (res2 < 0)
- res2 = -res2;
-
- if (res3 < 0)
- res3 = -res3;
-
- return (res3 << 24) | (res2 << 16) | (res1 << 8) | res0;
-}
-
-
-static inline unsigned int _subc (unsigned int src1, unsigned int src2)
-{
- if ( src1 >= src2)
- return ((src1 - src2) << 1) + 1;
- else
- return src1 << 1;
-}
-
-
-
-static inline int _sub2(int src1, int src2) {
- short s1[2], s2[2], r[2];
- int result;
- *((int*)s1) = src1;
- *((int*)s2) = src2;
- r[0] = s1[0] - s2[0];
- r[1] = s1[1] - s2[1];
- result = *(int*)r;
- return result;
-}
-
-
-static inline int _sub4(int src1, int src2) {
- char c1[4], c2[4], r[4];
- int result;
- *((int*)c1) = src1;
- *((int*)c2) = src2;
- r[0] = c1[0] - c2[0];
- r[1] = c1[1] - c2[1];
- r[2] = c1[2] - c2[2];
- r[3] = c1[3] - c2[3];
- result = *(int*)r;
- return result;
-}
-
-
-static inline int _swap4 (unsigned int src1) {
- unsigned char v0 = src1;
- unsigned char v1 = src1 >> 8;
- unsigned char v2 = src1 >> 16;
- unsigned char v3 = src1 >> 24;
- unsigned v = v0<<8 | v1 | v2<<24 | v3<<16;
- return v;
-}
-
-static inline unsigned int _unpkhu4 (unsigned int src1) {
- unsigned v0 = src1>>24;
- unsigned v1 = (src1>>16) & 0xff;
- return (v0<<16) | v1;
-}
-
-static inline unsigned int _unpklu4 (unsigned int src1) {
- unsigned v1 = (src1>>8) & 0xff;
- unsigned v0 = (src1) & 0xff;
- return (v1<<16) | v0;
-}
-
-
-
-
-static inline unsigned int _xpnd2 (unsigned int src1) {
- int v0 = (src1 & 0x1) ? 0x0000ffff : 0x00000000;
- int v1 = (src1 & 0x2) ? 0xffff0000 : 0x00000000;
- return v0|v1;
-}
-
-static inline unsigned int _xpnd4 (unsigned int src1) {
- int v0 = (src1 & 0x1) ? 0x000000ff : 0x00000000;
- int v1 = (src1 & 0x2) ? 0x0000ff00 : 0x00000000;
- int v2 = (src1 & 0x4) ? 0x00ff0000 : 0x00000000;
- int v3 = (src1 & 0x8) ? 0xff000000 : 0x00000000;
- int r = v0|v1|v2|v3;
- return r;
-}
-
-
-
-// end of Implemented in alphabetical order
-
-
-#endif /* __C6X_COMPAT__H */
diff --git a/src/arch/xtensa/include/xtensa/cacheasm.h b/src/arch/xtensa/include/xtensa/cacheasm.h
deleted file mode 100644
index 9cb2c8f..0000000
--- a/src/arch/xtensa/include/xtensa/cacheasm.h
+++ /dev/null
@@ -1,962 +0,0 @@
-/*
- * xtensa/cacheasm.h -- assembler-specific cache related definitions
- * that depend on CORE configuration
- *
- * This file is logically part of xtensa/coreasm.h ,
- * but is kept separate for modularity / compilation-performance.
- */
-
-/*
- * Copyright (c) 2001-2014 Cadence Design Systems, Inc.
- *
- * Permission is hereby granted, free of charge, to any person obtaining
- * a copy of this software and associated documentation files (the
- * "Software"), to deal in the Software without restriction, including
- * without limitation the rights to use, copy, modify, merge, publish,
- * distribute, sublicense, and/or sell copies of the Software, and to
- * permit persons to whom the Software is furnished to do so, subject to
- * the following conditions:
- *
- * The above copyright notice and this permission notice shall be included
- * in all copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
- * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
- * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
- * IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY
- * CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
- * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
- * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
- */
-
-#ifndef XTENSA_CACHEASM_H
-#define XTENSA_CACHEASM_H
-
-#include <xtensa/coreasm.h>
-#include <xtensa/corebits.h>
-#include <xtensa/xtensa-xer.h>
-#include <xtensa/xtensa-versions.h>
-
-/*
- * This header file defines assembler macros of the form:
- * <x>cache_<func>
- * where <x> is 'i' or 'd' for instruction and data caches,
- * and <func> indicates the function of the macro.
- *
- * The following functions <func> are defined,
- * and apply only to the specified cache (I or D):
- *
- * reset
- * Resets the cache.
- *
- * sync
- * Makes sure any previous cache instructions have been completed;
- * ie. makes sure any previous cache control operations
- * have had full effect and been synchronized to memory.
- * Eg. any invalidate completed [so as not to generate a hit],
- * any writebacks or other pipelined writes written to memory, etc.
- *
- * invalidate_line (single cache line)
- * invalidate_region (specified memory range)
- * invalidate_all (entire cache)
- * Invalidates all cache entries that cache
- * data from the specified memory range.
- * NOTE: locked entries are not invalidated.
- *
- * writeback_line (single cache line)
- * writeback_region (specified memory range)
- * writeback_all (entire cache)
- * Writes back to memory all dirty cache entries
- * that cache data from the specified memory range,
- * and marks these entries as clean.
- * NOTE: on some future implementations, this might
- * also invalidate.
- * NOTE: locked entries are written back, but never invalidated.
- * NOTE: instruction caches never implement writeback.
- *
- * writeback_inv_line (single cache line)
- * writeback_inv_region (specified memory range)
- * writeback_inv_all (entire cache)
- * Writes back to memory all dirty cache entries
- * that cache data from the specified memory range,
- * and invalidates these entries (including all clean
- * cache entries that cache data from that range).
- * NOTE: locked entries are written back but not invalidated.
- * NOTE: instruction caches never implement writeback.
- *
- * lock_line (single cache line)
- * lock_region (specified memory range)
- * Prefetch and lock the specified memory range into cache.
- * NOTE: if any part of the specified memory range cannot
- * be locked, a Load/Store Error (for dcache) or Instruction
- * Fetch Error (for icache) exception occurs. These macros don't
- * do anything special (yet anyway) to handle this situation.
- *
- * unlock_line (single cache line)
- * unlock_region (specified memory range)
- * unlock_all (entire cache)
- * Unlock cache entries that cache the specified memory range.
- * Entries not already locked are unaffected.
- *
- * coherence_on
- * coherence_off
- * Turn off and on cache coherence
- *
- */
-
-
-
-/*************************** GENERIC -- ALL CACHES ***************************/
-
-
-/*
- * The following macros assume the following cache size/parameter limits
- * in the current Xtensa core implementation:
- * cache size: 1024 bytes minimum
- * line size: 16 - 64 bytes
- * way count: 1 - 4
- *
- * Minimum entries per way (ie. per associativity) = 1024 / 64 / 4 = 4
- * Hence the assumption that each loop can execute four cache instructions.
- *
- * Correspondingly, the offset range of instructions is assumed able to cover
- * four lines, ie. offsets {0,1,2,3} * line_size are assumed valid for
- * both hit and indexed cache instructions. Ie. these offsets are all
- * valid: 0, 16, 32, 48, 64, 96, 128, 192 (for line sizes 16, 32, 64).
- * This is true of all original cache instructions
- * (dhi, ihi, dhwb, dhwbi, dii, iii) which have offsets
- * of 0 to 1020 in multiples of 4 (ie. 8 bits shifted by 2).
- * This is also true of subsequent cache instructions
- * (dhu, ihu, diu, iiu, diwb, diwbi, dpfl, ipfl) which have offsets
- * of 0 to 240 in multiples of 16 (ie. 4 bits shifted by 4).
- *
- * (Maximum cache size, currently 32k, doesn't affect the following macros.
- * Cache ways > MMU min page size cause aliasing but that's another matter.)
- */
-
-
-
-/*
- * Macro to apply an 'indexed' cache instruction to the entire cache.
- *
- * Parameters:
- * cainst instruction/ that takes an address register parameter
- * and an offset parameter (in range 0 .. 3*linesize).
- * size size of cache in bytes
- * linesize size of cache line in bytes (always power-of-2)
- * assoc_or1 number of associativities (ways/sets) in cache
- * if all sets affected by cainst,
- * or 1 if only one set (or not all sets) of the cache
- * is affected by cainst (eg. DIWB or DIWBI [not yet ISA defined]).
- * aa, ab unique address registers (temporaries).
- * awb set to other than a0 if wb type of instruction
- * loopokay 1 allows use of zero-overhead loops, 0 does not
- * immrange range (max value) of cainst's immediate offset parameter, in bytes
- * (NOTE: macro assumes immrange allows power-of-2 number of lines)
- */
-
- .macro cache_index_all cainst, size, linesize, assoc_or1, aa, ab, loopokay, maxofs, awb=a0
-
- // Number of indices in cache (lines per way):
- .set .Lindices, (\size / (\linesize * \assoc_or1))
- // Number of indices processed per loop iteration (max 4):
- .set .Lperloop, .Lindices
- .ifgt .Lperloop - 4
- .set .Lperloop, 4
- .endif
- // Also limit instructions per loop if cache line size exceeds immediate range:
- .set .Lmaxperloop, (\maxofs / \linesize) + 1
- .ifgt .Lperloop - .Lmaxperloop
- .set .Lperloop, .Lmaxperloop
- .endif
- // Avoid addi of 128 which takes two instructions (addmi,addi):
- .ifeq .Lperloop*\linesize - 128
- .ifgt .Lperloop - 1
- .set .Lperloop, .Lperloop / 2
- .endif
- .endif
-
- // \size byte cache, \linesize byte lines, \assoc_or1 way(s) affected by each \cainst.
- // XCHAL_ERRATUM_497 - don't execute using loop, to reduce the amount of added code
- .ifne (\loopokay & XCHAL_HAVE_LOOPS && !XCHAL_ERRATUM_497)
-
- movi \aa, .Lindices / .Lperloop // number of loop iterations
- // Possible improvement: need only loop if \aa > 1 ;
- // however \aa == 1 is highly unlikely.
- movi \ab, 0 // to iterate over cache
- loop \aa, .Lend_cachex\@
- .set .Li, 0 ; .rept .Lperloop
- \cainst \ab, .Li*\linesize
- .set .Li, .Li+1 ; .endr
- addi \ab, \ab, .Lperloop*\linesize // move to next line
-.Lend_cachex\@:
-
- .else
-
- movi \aa, (\size / \assoc_or1)
- // Possible improvement: need only loop if \aa > 1 ;
- // however \aa == 1 is highly unlikely.
- movi \ab, 0 // to iterate over cache
- .ifne ((\awb !=a0) & XCHAL_ERRATUM_497) // don't use awb if set to a0
- movi \awb, 0
- .endif
-.Lstart_cachex\@:
- .set .Li, 0 ; .rept .Lperloop
- \cainst \ab, .Li*\linesize
- .set .Li, .Li+1 ; .endr
- .ifne ((\awb !=a0) & XCHAL_ERRATUM_497) // do memw after 8 cainst wb instructions
- addi \awb, \awb, .Lperloop
- blti \awb, 8, .Lstart_memw\@
- memw
- movi \awb, 0
-.Lstart_memw\@:
- .endif
- addi \ab, \ab, .Lperloop*\linesize // move to next line
- bltu \ab, \aa, .Lstart_cachex\@
- .endif
-
- .endm
-
-
-/*
- * Macro to apply a 'hit' cache instruction to a memory region,
- * ie. to any cache entries that cache a specified portion (region) of memory.
- * Takes care of the unaligned cases, ie. may apply to one
- * more cache line than $asize / lineSize if $aaddr is not aligned.
- *
- *
- * Parameters are:
- * cainst instruction/macro that takes an address register parameter
- * and an offset parameter (currently always zero)
- * and generates a cache instruction (eg. "dhi", "dhwb", "ihi", etc.)
- * linesize_log2 log2(size of cache line in bytes)
- * addr register containing start address of region (clobbered)
- * asize register containing size of the region in bytes (clobbered)
- * askew unique register used as temporary
- * awb unique register used as temporary for erratum 497.
- *
- * Note: A possible optimization to this macro is to apply the operation
- * to the entire cache if the region exceeds the size of the cache
- * by some empirically determined amount or factor. Some experimentation
- * is required to determine the appropriate factors, which also need
- * to be tunable if required.
- */
-
- .macro cache_hit_region cainst, linesize_log2, addr, asize, askew, awb=a0
-
- // Make \asize the number of iterations:
- extui \askew, \addr, 0, \linesize_log2 // get unalignment amount of \addr
- add \asize, \asize, \askew // ... and add it to \asize
- addi \asize, \asize, (1 << \linesize_log2) - 1 // round up!
- srli \asize, \asize, \linesize_log2
-
- // Iterate over region:
- .ifne ((\awb !=a0) & XCHAL_ERRATUM_497) // don't use awb if set to a0
- movi \awb, 0
- .endif
- floopnez \asize, cacheh\@
- \cainst \addr, 0
- .ifne ((\awb !=a0) & XCHAL_ERRATUM_497) // do memw after 8 cainst wb instructions
- addi \awb, \awb, 1
- blti \awb, 8, .Lstart_memw\@
- memw
- movi \awb, 0
-.Lstart_memw\@:
- .endif
- addi \addr, \addr, (1 << \linesize_log2) // move to next line
- floopend \asize, cacheh\@
- .endm
-
-
-
-
-
-/*************************** INSTRUCTION CACHE ***************************/
-
-
-/*
- * Reset/initialize the instruction cache by simply invalidating it:
- * (need to unlock first also, if cache locking implemented):
- *
- * Parameters:
- * aa, ab unique address registers (temporaries)
- */
- .macro icache_reset aa, ab, loopokay=0
- icache_unlock_all \aa, \ab, \loopokay
- icache_invalidate_all \aa, \ab, \loopokay
- .endm
-
-
-/*
- * Synchronize after an instruction cache operation,
- * to be sure everything is in sync with memory as to be
- * expected following any previous instruction cache control operations.
- *
- * Even if a config doesn't have caches, an isync is still needed
- * when instructions in any memory are modified, whether by a loader
- * or self-modifying code. Therefore, this macro always produces
- * an isync, whether or not an icache is present.
- *
- * Parameters are:
- * ar an address register (temporary) (currently unused, but may be used in future)
- */
- .macro icache_sync ar
- isync
- .endm
-
-
-
-/*
- * Invalidate a single line of the instruction cache.
- * Parameters are:
- * ar address register that contains (virtual) address to invalidate
- * (may get clobbered in a future implementation, but not currently)
- * offset (optional) offset to add to \ar to compute effective address to invalidate
- * (note: some number of lsbits are ignored)
- */
- .macro icache_invalidate_line ar, offset
-#if XCHAL_ICACHE_SIZE > 0
- ihi \ar, \offset // invalidate icache line
- icache_sync \ar
-#endif
- .endm
-
-
-
-
-/*
- * Invalidate instruction cache entries that cache a specified portion of memory.
- * Parameters are:
- * astart start address (register gets clobbered)
- * asize size of the region in bytes (register gets clobbered)
- * ac unique register used as temporary
- */
- .macro icache_invalidate_region astart, asize, ac
-#if XCHAL_ICACHE_SIZE > 0
- // Instruction cache region invalidation:
- cache_hit_region ihi, XCHAL_ICACHE_LINEWIDTH, \astart, \asize, \ac
- icache_sync \ac
- // End of instruction cache region invalidation
-#endif
- .endm
-
-
-
-/*
- * Invalidate entire instruction cache.
- *
- * Parameters:
- * aa, ab unique address registers (temporaries)
- */
- .macro icache_invalidate_all aa, ab, loopokay=1
-#if XCHAL_ICACHE_SIZE > 0
- // Instruction cache invalidation:
- cache_index_all iii, XCHAL_ICACHE_SIZE, XCHAL_ICACHE_LINESIZE, XCHAL_ICACHE_WAYS, \aa, \ab, \loopokay, 1020
- icache_sync \aa
- // End of instruction cache invalidation
-#endif
- .endm
-
-
-
-/*
- * Lock (prefetch & lock) a single line of the instruction cache.
- *
- * Parameters are:
- * ar address register that contains (virtual) address to lock
- * (may get clobbered in a future implementation, but not currently)
- * offset offset to add to \ar to compute effective address to lock
- * (note: some number of lsbits are ignored)
- */
- .macro icache_lock_line ar, offset
-#if XCHAL_ICACHE_SIZE > 0 && XCHAL_ICACHE_LINE_LOCKABLE
- ipfl \ar, \offset /* prefetch and lock icache line */
- icache_sync \ar
-#endif
- .endm
-
-
-
-/*
- * Lock (prefetch & lock) a specified portion of memory into the instruction cache.
- * Parameters are:
- * astart start address (register gets clobbered)
- * asize size of the region in bytes (register gets clobbered)
- * ac unique register used as temporary
- */
- .macro icache_lock_region astart, asize, ac
-#if XCHAL_ICACHE_SIZE > 0 && XCHAL_ICACHE_LINE_LOCKABLE
- // Instruction cache region lock:
- cache_hit_region ipfl, XCHAL_ICACHE_LINEWIDTH, \astart, \asize, \ac
- icache_sync \ac
- // End of instruction cache region lock
-#endif
- .endm
-
-
-
-/*
- * Unlock a single line of the instruction cache.
- *
- * Parameters are:
- * ar address register that contains (virtual) address to unlock
- * (may get clobbered in a future implementation, but not currently)
- * offset offset to add to \ar to compute effective address to unlock
- * (note: some number of lsbits are ignored)
- */
- .macro icache_unlock_line ar, offset
-#if XCHAL_ICACHE_SIZE > 0 && XCHAL_ICACHE_LINE_LOCKABLE
- ihu \ar, \offset /* unlock icache line */
- icache_sync \ar
-#endif
- .endm
-
-
-
-/*
- * Unlock a specified portion of memory from the instruction cache.
- * Parameters are:
- * astart start address (register gets clobbered)
- * asize size of the region in bytes (register gets clobbered)
- * ac unique register used as temporary
- */
- .macro icache_unlock_region astart, asize, ac
-#if XCHAL_ICACHE_SIZE > 0 && XCHAL_ICACHE_LINE_LOCKABLE
- // Instruction cache region unlock:
- cache_hit_region ihu, XCHAL_ICACHE_LINEWIDTH, \astart, \asize, \ac
- icache_sync \ac
- // End of instruction cache region unlock
-#endif
- .endm
-
-
-
-/*
- * Unlock entire instruction cache.
- *
- * Parameters:
- * aa, ab unique address registers (temporaries)
- */
- .macro icache_unlock_all aa, ab, loopokay=1
-#if XCHAL_ICACHE_SIZE > 0 && XCHAL_ICACHE_LINE_LOCKABLE
- // Instruction cache unlock:
- cache_index_all iiu, XCHAL_ICACHE_SIZE, XCHAL_ICACHE_LINESIZE, 1, \aa, \ab, \loopokay, 240
- icache_sync \aa
- // End of instruction cache unlock
-#endif
- .endm
-
-
-
-
-
-/*************************** DATA CACHE ***************************/
-
-
-
-/*
- * Reset/initialize the data cache by simply invalidating it
- * (need to unlock first also, if cache locking implemented):
- *
- * Parameters:
- * aa, ab unique address registers (temporaries)
- */
- .macro dcache_reset aa, ab, loopokay=0
- dcache_unlock_all \aa, \ab, \loopokay
- dcache_invalidate_all \aa, \ab, \loopokay
- .endm
-
-
-
-
-/*
- * Synchronize after a data cache operation,
- * to be sure everything is in sync with memory as to be
- * expected following any previous data cache control operations.
- *
- * Parameters are:
- * ar an address register (temporary) (currently unused, but may be used in future)
- */
- .macro dcache_sync ar, wbtype=0
-#if XCHAL_DCACHE_SIZE > 0
- // No synchronization is needed.
- // (memw may be desired e.g. after writeback operation to help ensure subsequent
- // external accesses are seen to follow that writeback, however that's outside
- // the scope of this macro)
-
- //dsync
- .ifne (\wbtype & XCHAL_ERRATUM_497)
- memw
- .endif
-#endif
- .endm
-
-
-
-/*
- * Turn on cache coherence.
- *
- * WARNING: for RE-201x.x and later hardware, any interrupt that tries
- * to change MEMCTL will see its changes dropped if the interrupt comes
- * in the middle of this routine. If this might be an issue, call this
- * routine with interrupts disabled.
- *
- * Parameters are:
- * ar,at two scratch address registers (both clobbered)
- */
- .macro cache_coherence_on ar at
-#if XCHAL_DCACHE_IS_COHERENT
-# if XCHAL_HW_MIN_VERSION >= XTENSA_HWVERSION_RE_2012_0
- /* Have MEMCTL. Enable snoop responses. */
- rsr.memctl \ar
- movi \at, MEMCTL_SNOOP_EN
- or \ar, \ar, \at
- wsr.memctl \ar
-# elif XCHAL_HAVE_EXTERN_REGS && XCHAL_HAVE_MX
- /* Opt into coherence for MX (for backward compatibility / testing). */
- movi \ar, 1
- movi \at, XER_CCON
- wer \ar, \at
- extw
-# endif
-#endif
- .endm
-
-
-
-/*
- * Turn off cache coherence.
- *
- * NOTE: this is generally preceded by emptying the cache;
- * see xthal_cache_coherence_optout() in hal/coherence.c for details.
- *
- * WARNING: for RE-201x.x and later hardware, any interrupt that tries
- * to change MEMCTL will see its changes dropped if the interrupt comes
- * in the middle of this routine. If this might be an issue, call this
- * routine with interrupts disabled.
- *
- * Parameters are:
- * ar,at two scratch address registers (both clobbered)
- */
- .macro cache_coherence_off ar at
-#if XCHAL_DCACHE_IS_COHERENT
-# if XCHAL_HW_MIN_VERSION >= XTENSA_HWVERSION_RE_2012_0
- /* Have MEMCTL. Disable snoop responses. */
- rsr.memctl \ar
- movi \at, ~MEMCTL_SNOOP_EN
- and \ar, \ar, \at
- wsr.memctl \ar
-# elif XCHAL_HAVE_EXTERN_REGS && XCHAL_HAVE_MX
- /* Opt out of coherence, for MX (for backward compatibility / testing). */
- extw
- movi \at, 0
- movi \ar, XER_CCON
- wer \at, \ar
- extw
-# endif
-#endif
- .endm
-
-
-
-/*
- * Synchronize after a data store operation,
- * to be sure the stored data is completely off the processor
- * (and assuming there is no buffering outside the processor,
- * that the data is in memory). This may be required to
- * ensure that the processor's write buffers are emptied.
- * A MEMW followed by a read guarantees this, by definition.
- * We also try to make sure the read itself completes.
- *
- * Parameters are:
- * ar an address register (temporary)
- */
- .macro write_sync ar
- memw // ensure previous memory accesses are complete prior to subsequent memory accesses
- l32i \ar, sp, 0 // completing this read ensures any previous write has completed, because of MEMW
- //slot
- add \ar, \ar, \ar // use the result of the read to help ensure the read completes (in future architectures)
- .endm
-
-
-/*
- * Invalidate a single line of the data cache.
- * Parameters are:
- * ar address register that contains (virtual) address to invalidate
- * (may get clobbered in a future implementation, but not currently)
- * offset (optional) offset to add to \ar to compute effective address to invalidate
- * (note: some number of lsbits are ignored)
- */
- .macro dcache_invalidate_line ar, offset
-#if XCHAL_DCACHE_SIZE > 0
- dhi \ar, \offset
- dcache_sync \ar
-#endif
- .endm
-
-
-
-
-
-/*
- * Invalidate data cache entries that cache a specified portion of memory.
- * Parameters are:
- * astart start address (register gets clobbered)
- * asize size of the region in bytes (register gets clobbered)
- * ac unique register used as temporary
- */
- .macro dcache_invalidate_region astart, asize, ac
-#if XCHAL_DCACHE_SIZE > 0
- // Data cache region invalidation:
- cache_hit_region dhi, XCHAL_DCACHE_LINEWIDTH, \astart, \asize, \ac
- dcache_sync \ac
- // End of data cache region invalidation
-#endif
- .endm
-
-
-
-/*
- * Invalidate entire data cache.
- *
- * Parameters:
- * aa, ab unique address registers (temporaries)
- */
- .macro dcache_invalidate_all aa, ab, loopokay=1
-#if XCHAL_DCACHE_SIZE > 0
- // Data cache invalidation:
- cache_index_all dii, XCHAL_DCACHE_SIZE, XCHAL_DCACHE_LINESIZE, XCHAL_DCACHE_WAYS, \aa, \ab, \loopokay, 1020
- dcache_sync \aa
- // End of data cache invalidation
-#endif
- .endm
-
-
-
-/*
- * Writeback a single line of the data cache.
- * Parameters are:
- * ar address register that contains (virtual) address to writeback
- * (may get clobbered in a future implementation, but not currently)
- * offset offset to add to \ar to compute effective address to writeback
- * (note: some number of lsbits are ignored)
- */
- .macro dcache_writeback_line ar, offset
-#if XCHAL_DCACHE_SIZE > 0 && XCHAL_DCACHE_IS_WRITEBACK
- dhwb \ar, \offset
- dcache_sync \ar, wbtype=1
-#endif
- .endm
-
-
-
-/*
- * Writeback dirty data cache entries that cache a specified portion of memory.
- * Parameters are:
- * astart start address (register gets clobbered)
- * asize size of the region in bytes (register gets clobbered)
- * ac unique register used as temporary
- */
- .macro dcache_writeback_region astart, asize, ac, awb
-#if XCHAL_DCACHE_SIZE > 0 && XCHAL_DCACHE_IS_WRITEBACK
- // Data cache region writeback:
- cache_hit_region dhwb, XCHAL_DCACHE_LINEWIDTH, \astart, \asize, \ac, \awb
- dcache_sync \ac, wbtype=1
- // End of data cache region writeback
-#endif
- .endm
-
-
-
-/*
- * Writeback entire data cache.
- * Parameters:
- * aa, ab unique address registers (temporaries)
- */
- .macro dcache_writeback_all aa, ab, awb, loopokay=1
-#if XCHAL_DCACHE_SIZE > 0 && XCHAL_DCACHE_IS_WRITEBACK
- // Data cache writeback:
- cache_index_all diwb, XCHAL_DCACHE_SIZE, XCHAL_DCACHE_LINESIZE, 1, \aa, \ab, \loopokay, 240, \awb,
- dcache_sync \aa, wbtype=1
- // End of data cache writeback
-#endif
- .endm
-
-
-
-/*
- * Writeback and invalidate a single line of the data cache.
- * Parameters are:
- * ar address register that contains (virtual) address to writeback and invalidate
- * (may get clobbered in a future implementation, but not currently)
- * offset offset to add to \ar to compute effective address to writeback and invalidate
- * (note: some number of lsbits are ignored)
- */
- .macro dcache_writeback_inv_line ar, offset
-#if XCHAL_DCACHE_SIZE > 0
- dhwbi \ar, \offset /* writeback and invalidate dcache line */
- dcache_sync \ar, wbtype=1
-#endif
- .endm
-
-
-
-/*
- * Writeback and invalidate data cache entries that cache a specified portion of memory.
- * Parameters are:
- * astart start address (register gets clobbered)
- * asize size of the region in bytes (register gets clobbered)
- * ac unique register used as temporary
- */
- .macro dcache_writeback_inv_region astart, asize, ac, awb
-#if XCHAL_DCACHE_SIZE > 0
- // Data cache region writeback and invalidate:
- cache_hit_region dhwbi, XCHAL_DCACHE_LINEWIDTH, \astart, \asize, \ac, \awb
- dcache_sync \ac, wbtype=1
- // End of data cache region writeback and invalidate
-#endif
- .endm
-
-
-
-/*
- * Writeback and invalidate entire data cache.
- * Parameters:
- * aa, ab unique address registers (temporaries)
- */
- .macro dcache_writeback_inv_all aa, ab, awb, loopokay=1
-#if XCHAL_DCACHE_SIZE > 0
- // Data cache writeback and invalidate:
-#if XCHAL_DCACHE_IS_WRITEBACK
- cache_index_all diwbi, XCHAL_DCACHE_SIZE, XCHAL_DCACHE_LINESIZE, 1, \aa, \ab, \loopokay, 240, \awb
- dcache_sync \aa, wbtype=1
-#else /*writeback*/
- // Data cache does not support writeback, so just invalidate: */
- dcache_invalidate_all \aa, \ab, \loopokay
-#endif /*writeback*/
- // End of data cache writeback and invalidate
-#endif
- .endm
-
-
-
-
-/*
- * Lock (prefetch & lock) a single line of the data cache.
- *
- * Parameters are:
- * ar address register that contains (virtual) address to lock
- * (may get clobbered in a future implementation, but not currently)
- * offset offset to add to \ar to compute effective address to lock
- * (note: some number of lsbits are ignored)
- */
- .macro dcache_lock_line ar, offset
-#if XCHAL_DCACHE_SIZE > 0 && XCHAL_DCACHE_LINE_LOCKABLE
- dpfl \ar, \offset /* prefetch and lock dcache line */
- dcache_sync \ar
-#endif
- .endm
-
-
-
-/*
- * Lock (prefetch & lock) a specified portion of memory into the data cache.
- * Parameters are:
- * astart start address (register gets clobbered)
- * asize size of the region in bytes (register gets clobbered)
- * ac unique register used as temporary
- */
- .macro dcache_lock_region astart, asize, ac
-#if XCHAL_DCACHE_SIZE > 0 && XCHAL_DCACHE_LINE_LOCKABLE
- // Data cache region lock:
- cache_hit_region dpfl, XCHAL_DCACHE_LINEWIDTH, \astart, \asize, \ac
- dcache_sync \ac
- // End of data cache region lock
-#endif
- .endm
-
-
-
-/*
- * Unlock a single line of the data cache.
- *
- * Parameters are:
- * ar address register that contains (virtual) address to unlock
- * (may get clobbered in a future implementation, but not currently)
- * offset offset to add to \ar to compute effective address to unlock
- * (note: some number of lsbits are ignored)
- */
- .macro dcache_unlock_line ar, offset
-#if XCHAL_DCACHE_SIZE > 0 && XCHAL_DCACHE_LINE_LOCKABLE
- dhu \ar, \offset /* unlock dcache line */
- dcache_sync \ar
-#endif
- .endm
-
-
-
-/*
- * Unlock a specified portion of memory from the data cache.
- * Parameters are:
- * astart start address (register gets clobbered)
- * asize size of the region in bytes (register gets clobbered)
- * ac unique register used as temporary
- */
- .macro dcache_unlock_region astart, asize, ac
-#if XCHAL_DCACHE_SIZE > 0 && XCHAL_DCACHE_LINE_LOCKABLE
- // Data cache region unlock:
- cache_hit_region dhu, XCHAL_DCACHE_LINEWIDTH, \astart, \asize, \ac
- dcache_sync \ac
- // End of data cache region unlock
-#endif
- .endm
-
-
-
-/*
- * Unlock entire data cache.
- *
- * Parameters:
- * aa, ab unique address registers (temporaries)
- */
- .macro dcache_unlock_all aa, ab, loopokay=1
-#if XCHAL_DCACHE_SIZE > 0 && XCHAL_DCACHE_LINE_LOCKABLE
- // Data cache unlock:
- cache_index_all diu, XCHAL_DCACHE_SIZE, XCHAL_DCACHE_LINESIZE, 1, \aa, \ab, \loopokay, 240
- dcache_sync \aa
- // End of data cache unlock
-#endif
- .endm
-
-
-
-/*
- * Get the number of enabled icache ways. Note that this may
- * be different from the value read from the MEMCTL register.
- *
- * Parameters:
- * aa address register where value is returned
- */
- .macro icache_get_ways aa
-#if XCHAL_ICACHE_SIZE > 0
-#if XCHAL_HAVE_ICACHE_DYN_WAYS
- // Read from MEMCTL and shift/mask
- rsr.memctl \aa
- extui \aa, \aa, MEMCTL_ICWU_SHIFT, MEMCTL_ICWU_BITS
- blti \aa, XCHAL_ICACHE_WAYS, .Licgw
- movi \aa, XCHAL_ICACHE_WAYS
-.Licgw:
-#else
- // All ways are always enabled
- movi \aa, XCHAL_ICACHE_WAYS
-#endif
-#else
- // No icache
- movi \aa, 0
-#endif
- .endm
-
-
-
-/*
- * Set the number of enabled icache ways.
- *
- * Parameters:
- * aa address register specifying number of ways (trashed)
- * ab,ac address register for scratch use (trashed)
- */
- .macro icache_set_ways aa, ab, ac
-#if XCHAL_ICACHE_SIZE > 0
-#if XCHAL_HAVE_ICACHE_DYN_WAYS
- movi \ac, MEMCTL_ICWU_CLR_MASK // set up to clear bits 18-22
- rsr.memctl \ab
- and \ab, \ab, \ac
- movi \ac, MEMCTL_INV_EN // set bit 23
- slli \aa, \aa, MEMCTL_ICWU_SHIFT // move to right spot
- or \ab, \ab, \aa
- or \ab, \ab, \ac
- wsr.memctl \ab
- isync
-#else
- // All ways are always enabled
-#endif
-#else
- // No icache
-#endif
- .endm
-
-
-
-/*
- * Get the number of enabled dcache ways. Note that this may
- * be different from the value read from the MEMCTL register.
- *
- * Parameters:
- * aa address register where value is returned
- */
- .macro dcache_get_ways aa
-#if XCHAL_DCACHE_SIZE > 0
-#if XCHAL_HAVE_DCACHE_DYN_WAYS
- // Read from MEMCTL and shift/mask
- rsr.memctl \aa
- extui \aa, \aa, MEMCTL_DCWU_SHIFT, MEMCTL_DCWU_BITS
- blti \aa, XCHAL_DCACHE_WAYS, .Ldcgw
- movi \aa, XCHAL_DCACHE_WAYS
-.Ldcgw:
-#else
- // All ways are always enabled
- movi \aa, XCHAL_DCACHE_WAYS
-#endif
-#else
- // No dcache
- movi \aa, 0
-#endif
- .endm
-
-
-
-/*
- * Set the number of enabled dcache ways.
- *
- * Parameters:
- * aa address register specifying number of ways (trashed)
- * ab,ac address register for scratch use (trashed)
- */
- .macro dcache_set_ways aa, ab, ac
-#if (XCHAL_DCACHE_SIZE > 0) && XCHAL_HAVE_DCACHE_DYN_WAYS
- movi \ac, MEMCTL_DCWA_CLR_MASK // set up to clear bits 13-17
- rsr.memctl \ab
- and \ab, \ab, \ac // clear ways allocatable
- slli \ac, \aa, MEMCTL_DCWA_SHIFT
- or \ab, \ab, \ac // set ways allocatable
- wsr.memctl \ab
-#if XCHAL_DCACHE_IS_WRITEBACK
- // Check if the way count is increasing or decreasing
- extui \ac, \ab, MEMCTL_DCWU_SHIFT, MEMCTL_DCWU_BITS // bits 8-12 - ways in use
- bge \aa, \ac, .Ldsw3 // equal or increasing
- slli \ab, \aa, XCHAL_DCACHE_LINEWIDTH + XCHAL_DCACHE_SETWIDTH // start way number
- slli \ac, \ac, XCHAL_DCACHE_LINEWIDTH + XCHAL_DCACHE_SETWIDTH // end way number
-.Ldsw1:
- diwbui.p \ab // auto-increments ab
- bge \ab, \ac, .Ldsw2
- beqz \ab, .Ldsw2
- j .Ldsw1
-.Ldsw2:
- rsr.memctl \ab
-#endif
-.Ldsw3:
- // No dirty data to write back, just set the new number of ways
- movi \ac, MEMCTL_DCWU_CLR_MASK // set up to clear bits 8-12
- and \ab, \ab, \ac // clear ways in use
- movi \ac, MEMCTL_INV_EN
- or \ab, \ab, \ac // set bit 23
- slli \aa, \aa, MEMCTL_DCWU_SHIFT
- or \ab, \ab, \aa // set ways in use
- wsr.memctl \ab
-#else
- // No dcache or no way disable support
-#endif
- .endm
-
-#endif /*XTENSA_CACHEASM_H*/
-
diff --git a/src/arch/xtensa/include/xtensa/cacheattrasm.h b/src/arch/xtensa/include/xtensa/cacheattrasm.h
deleted file mode 100644
index 211803a..0000000
--- a/src/arch/xtensa/include/xtensa/cacheattrasm.h
+++ /dev/null
@@ -1,436 +0,0 @@
-/*
- * xtensa/cacheattrasm.h -- assembler-specific CACHEATTR register related definitions
- * that depend on CORE configuration
- *
- * This file is logically part of xtensa/coreasm.h (or perhaps xtensa/cacheasm.h),
- * but is kept separate for modularity / compilation-performance.
- */
-
-/*
- * Copyright (c) 2001-2009 Tensilica Inc.
- *
- * Permission is hereby granted, free of charge, to any person obtaining
- * a copy of this software and associated documentation files (the
- * "Software"), to deal in the Software without restriction, including
- * without limitation the rights to use, copy, modify, merge, publish,
- * distribute, sublicense, and/or sell copies of the Software, and to
- * permit persons to whom the Software is furnished to do so, subject to
- * the following conditions:
- *
- * The above copyright notice and this permission notice shall be included
- * in all copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
- * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
- * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
- * IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY
- * CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
- * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
- * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
- */
-
-#ifndef XTENSA_CACHEATTRASM_H
-#define XTENSA_CACHEATTRASM_H
-
-#include <xtensa/coreasm.h>
-
-/* Determine whether cache attributes are controlled using eight 512MB entries: */
-#define XCHAL_CA_8X512 (XCHAL_HAVE_CACHEATTR || XCHAL_HAVE_MIMIC_CACHEATTR || XCHAL_HAVE_XLT_CACHEATTR \
- || (XCHAL_HAVE_PTP_MMU && XCHAL_HAVE_SPANNING_WAY))
-
-
-/*
- * This header file defines assembler macros of the form:
- * <x>cacheattr_<func>
- * where:
- * <x> is 'i', 'd' or absent for instruction, data
- * or both caches; and
- * <func> indicates the function of the macro.
- *
- * The following functions are defined:
- *
- * icacheattr_get
- * Reads I-cache CACHEATTR into a2 (clobbers a3-a5).
- *
- * dcacheattr_get
- * Reads D-cache CACHEATTR into a2 (clobbers a3-a5).
- * (Note: for configs with a real CACHEATTR register, the
- * above two macros are identical.)
- *
- * cacheattr_set
- * Writes both I-cache and D-cache CACHEATTRs from a2 (a3-a8 clobbered).
- * Works even when changing one's own code's attributes.
- *
- * icacheattr_is_enabled label
- * Branches to \label if I-cache appears to have been enabled
- * (eg. if CACHEATTR contains a cache-enabled attribute).
- * (clobbers a2-a5,SAR)
- *
- * dcacheattr_is_enabled label
- * Branches to \label if D-cache appears to have been enabled
- * (eg. if CACHEATTR contains a cache-enabled attribute).
- * (clobbers a2-a5,SAR)
- *
- * cacheattr_is_enabled label
- * Branches to \label if either I-cache or D-cache appears to have been enabled
- * (eg. if CACHEATTR contains a cache-enabled attribute).
- * (clobbers a2-a5,SAR)
- *
- * The following macros are only defined under certain conditions:
- *
- * icacheattr_set (if XCHAL_HAVE_MIMIC_CACHEATTR || XCHAL_HAVE_XLT_CACHEATTR)
- * Writes I-cache CACHEATTR from a2 (a3-a8 clobbered).
- *
- * dcacheattr_set (if XCHAL_HAVE_MIMIC_CACHEATTR || XCHAL_HAVE_XLT_CACHEATTR)
- * Writes D-cache CACHEATTR from a2 (a3-a8 clobbered).
- */
-
-
-
-/*************************** GENERIC -- ALL CACHES ***************************/
-
-/*
- * _cacheattr_get
- *
- * (Internal macro.)
- * Returns value of CACHEATTR register (or closest equivalent) in a2.
- *
- * Entry:
- * (none)
- * Exit:
- * a2 value read from CACHEATTR
- * a3-a5 clobbered (temporaries)
- */
- .macro _cacheattr_get tlb
-#if XCHAL_HAVE_CACHEATTR
- rsr.cacheattr a2
-#elif XCHAL_CA_8X512
- // We have a config that "mimics" CACHEATTR using a simplified
- // "MMU" composed of a single statically-mapped way.
- // DTLB and ITLB are independent, so there's no single
- // cache attribute that can describe both. So for now
- // just return the DTLB state.
- movi a5, 0xE0000000
- movi a2, 0
- movi a3, XCHAL_SPANNING_WAY
-1: add a3, a3, a5 // next segment
- r&tlb&1 a4, a3 // get PPN+CA of segment at 0xE0000000, 0xC0000000, ..., 0
- dsync // interlock???
- slli a2, a2, 4
- extui a4, a4, 0, 4 // extract CA
- or a2, a2, a4
- bgeui a3, 16, 1b
-#else
- // This macro isn't applicable to arbitrary MMU configurations.
- // Just return zero.
- movi a2, 0
-#endif
- .endm
-
- .macro icacheattr_get
- _cacheattr_get itlb
- .endm
-
- .macro dcacheattr_get
- _cacheattr_get dtlb
- .endm
-
-
-/* Default (powerup/reset) value of CACHEATTR,
- all BYPASS mode (ie. disabled/bypassed caches): */
-#if XCHAL_HAVE_PTP_MMU
-# define XCHAL_CACHEATTR_ALL_BYPASS 0x33333333
-#else
-# define XCHAL_CACHEATTR_ALL_BYPASS 0x22222222
-#endif
-
-#if XCHAL_CA_8X512
-
-#if XCHAL_HAVE_PTP_MMU
-# define XCHAL_FCA_ENAMASK 0x0AA0 /* bitmap of fetch attributes that require enabled icache */
-# define XCHAL_LCA_ENAMASK 0x0FF0 /* bitmap of load attributes that require enabled dcache */
-# define XCHAL_SCA_ENAMASK 0x0CC0 /* bitmap of store attributes that require enabled dcache */
-#else
-# define XCHAL_FCA_ENAMASK 0x003A /* bitmap of fetch attributes that require enabled icache */
-# define XCHAL_LCA_ENAMASK 0x0033 /* bitmap of load attributes that require enabled dcache */
-# define XCHAL_SCA_ENAMASK 0x0033 /* bitmap of store attributes that require enabled dcache */
-#endif
-#define XCHAL_LSCA_ENAMASK (XCHAL_LCA_ENAMASK|XCHAL_SCA_ENAMASK) /* l/s attrs requiring enabled dcache */
-#define XCHAL_ALLCA_ENAMASK (XCHAL_FCA_ENAMASK|XCHAL_LSCA_ENAMASK) /* all attrs requiring enabled caches */
-
-/*
- * _cacheattr_is_enabled
- *
- * (Internal macro.)
- * Branches to \label if CACHEATTR in a2 indicates an enabled
- * cache, using mask in a3.
- *
- * Parameters:
- * label where to branch to if cache is enabled
- * Entry:
- * a2 contains CACHEATTR value used to determine whether
- * caches are enabled
- * a3 16-bit constant where each bit correspond to
- * one of the 16 possible CA values (in a CACHEATTR mask);
- * CA values that indicate the cache is enabled
- * have their corresponding bit set in this mask
- * (eg. use XCHAL_xCA_ENAMASK , above)
- * Exit:
- * a2,a4,a5 clobbered
- * SAR clobbered
- */
- .macro _cacheattr_is_enabled label
- movi a4, 8 // loop 8 times
-.Lcaife\@:
- extui a5, a2, 0, 4 // get CA nibble
- ssr a5 // index into mask according to CA...
- srl a5, a3 // ...and get CA's mask bit in a5 bit 0
- bbsi.l a5, 0, \label // if CA indicates cache enabled, jump to label
- srli a2, a2, 4 // next nibble
- addi a4, a4, -1
- bnez a4, .Lcaife\@ // loop for each nibble
- .endm
-
-#else /* XCHAL_CA_8X512 */
- .macro _cacheattr_is_enabled label
- j \label // macro not applicable, assume caches always enabled
- .endm
-#endif /* XCHAL_CA_8X512 */
-
-
-
-/*
- * icacheattr_is_enabled
- *
- * Branches to \label if I-cache is enabled.
- *
- * Parameters:
- * label where to branch to if icache is enabled
- * Entry:
- * (none)
- * Exit:
- * a2-a5, SAR clobbered (temporaries)
- */
- .macro icacheattr_is_enabled label
-#if XCHAL_CA_8X512
- icacheattr_get
- movi a3, XCHAL_FCA_ENAMASK
-#endif
- _cacheattr_is_enabled \label
- .endm
-
-/*
- * dcacheattr_is_enabled
- *
- * Branches to \label if D-cache is enabled.
- *
- * Parameters:
- * label where to branch to if dcache is enabled
- * Entry:
- * (none)
- * Exit:
- * a2-a5, SAR clobbered (temporaries)
- */
- .macro dcacheattr_is_enabled label
-#if XCHAL_CA_8X512
- dcacheattr_get
- movi a3, XCHAL_LSCA_ENAMASK
-#endif
- _cacheattr_is_enabled \label
- .endm
-
-/*
- * cacheattr_is_enabled
- *
- * Branches to \label if either I-cache or D-cache is enabled.
- *
- * Parameters:
- * label where to branch to if a cache is enabled
- * Entry:
- * (none)
- * Exit:
- * a2-a5, SAR clobbered (temporaries)
- */
- .macro cacheattr_is_enabled label
-#if XCHAL_HAVE_CACHEATTR
- rsr.cacheattr a2
- movi a3, XCHAL_ALLCA_ENAMASK
-#elif XCHAL_CA_8X512
- icacheattr_get
- movi a3, XCHAL_FCA_ENAMASK
- _cacheattr_is_enabled \label
- dcacheattr_get
- movi a3, XCHAL_LSCA_ENAMASK
-#endif
- _cacheattr_is_enabled \label
- .endm
-
-
-
-/*
- * The ISA does not have a defined way to change the
- * instruction cache attributes of the running code,
- * ie. of the memory area that encloses the current PC.
- * However, each micro-architecture (or class of
- * configurations within a micro-architecture)
- * provides a way to deal with this issue.
- *
- * Here are a few macros used to implement the relevant
- * approach taken.
- */
-
-#if XCHAL_CA_8X512 && !XCHAL_HAVE_CACHEATTR
- // We have a config that "mimics" CACHEATTR using a simplified
- // "MMU" composed of a single statically-mapped way.
-
-/*
- * icacheattr_set
- *
- * Entry:
- * a2 cacheattr value to set
- * Exit:
- * a2 unchanged
- * a3-a8 clobbered (temporaries)
- */
- .macro icacheattr_set
-
- movi a5, 0xE0000000 // mask of upper 3 bits
- movi a6, 3f // PC where ITLB is set
- movi a3, XCHAL_SPANNING_WAY // start at region 0 (0 .. 7)
- mov a7, a2 // copy a2 so it doesn't get clobbered
- and a6, a6, a5 // upper 3 bits of local PC area
- j 3f
-
- // Use micro-architecture specific method.
- // The following 4-instruction sequence is aligned such that
- // it all fits within a single I-cache line. Sixteen byte
- // alignment is sufficient for this (using XCHAL_ICACHE_LINESIZE
- // actually causes problems because that can be greater than
- // the alignment of the reset vector, where this macro is often
- // invoked, which would cause the linker to align the reset
- // vector code away from the reset vector!!).
- .begin no-transform
- .align 16 /*XCHAL_ICACHE_LINESIZE*/
-1: witlb a4, a3 // write wired PTE (CA, no PPN) of 512MB segment to ITLB
- isync
- .end no-transform
- nop
- nop
-
- sub a3, a3, a5 // next segment (add 0x20000000)
- bltui a3, 16, 4f // done?
-
- // Note that in the WITLB loop, we don't do any load/stores
- // (may not be an issue here, but it is important in the DTLB case).
-2: srli a7, a7, 4 // next CA
-3:
-# if XCHAL_HAVE_MIMIC_CACHEATTR
- extui a4, a7, 0, 4 // extract CA to set
-# else /* have translation, preserve it: */
- ritlb1 a8, a3 // get current PPN+CA of segment
- //dsync // interlock???
- extui a4, a7, 0, 4 // extract CA to set
- srli a8, a8, 4 // clear CA but keep PPN ...
- slli a8, a8, 4 // ...
- add a4, a4, a8 // combine new CA with PPN to preserve
-# endif
- beq a3, a6, 1b // current PC's region? if so, do it in a safe way
- witlb a4, a3 // write wired PTE (CA [+PPN]) of 512MB segment to ITLB
- sub a3, a3, a5 // next segment (add 0x20000000)
- bgeui a3, 16, 2b
- isync // make sure all ifetch changes take effect
-4:
- .endm // icacheattr_set
-
-
-/*
- * dcacheattr_set
- *
- * Entry:
- * a2 cacheattr value to set
- * Exit:
- * a2 unchanged
- * a3-a8 clobbered (temporaries)
- */
-
- .macro dcacheattr_set
-
- movi a5, 0xE0000000 // mask of upper 3 bits
- movi a3, XCHAL_SPANNING_WAY // start at region 0 (0 .. 7)
- mov a7, a2 // copy a2 so it doesn't get clobbered
- // Note that in the WDTLB loop, we don't do any load/stores
-2: // (including implicit l32r via movi) because it isn't safe.
-# if XCHAL_HAVE_MIMIC_CACHEATTR
- extui a4, a7, 0, 4 // extract CA to set
-# else /* have translation, preserve it: */
- rdtlb1 a8, a3 // get current PPN+CA of segment
- //dsync // interlock???
- extui a4, a7, 0, 4 // extract CA to set
- srli a8, a8, 4 // clear CA but keep PPN ...
- slli a8, a8, 4 // ...
- add a4, a4, a8 // combine new CA with PPN to preserve
-# endif
- wdtlb a4, a3 // write wired PTE (CA [+PPN]) of 512MB segment to DTLB
- sub a3, a3, a5 // next segment (add 0x20000000)
- srli a7, a7, 4 // next CA
- bgeui a3, 16, 2b
- dsync // make sure all data path changes take effect
- .endm // dcacheattr_set
-
-#endif /* XCHAL_CA_8X512 && !XCHAL_HAVE_CACHEATTR */
-
-
-
-/*
- * cacheattr_set
- *
- * Macro that sets the current CACHEATTR safely
- * (both i and d) according to the current contents of a2.
- * It works even when changing the cache attributes of
- * the currently running code.
- *
- * Entry:
- * a2 cacheattr value to set
- * Exit:
- * a2 unchanged
- * a3-a8 clobbered (temporaries)
- */
- .macro cacheattr_set
-
-#if XCHAL_HAVE_CACHEATTR
-# if XCHAL_ICACHE_LINESIZE < 4
- // No i-cache, so can always safely write to CACHEATTR:
- wsr.cacheattr a2
-# else
- // The Athens micro-architecture, when using the old
- // exception architecture option (ie. with the CACHEATTR register)
- // allows changing the cache attributes of the running code
- // using the following exact sequence aligned to be within
- // an instruction cache line. (NOTE: using XCHAL_ICACHE_LINESIZE
- // alignment actually causes problems because that can be greater
- // than the alignment of the reset vector, where this macro is often
- // invoked, which would cause the linker to align the reset
- // vector code away from the reset vector!!).
- j 1f
- .begin no-transform
- .align 16 /*XCHAL_ICACHE_LINESIZE*/ // align to within an I-cache line
-1: wsr.cacheattr a2
- isync
- .end no-transform
- nop
- nop
-# endif
-#elif XCHAL_CA_8X512
- // DTLB and ITLB are independent, but to keep semantics
- // of this macro we simply write to both.
- icacheattr_set
- dcacheattr_set
-#else
- // This macro isn't applicable to arbitrary MMU configurations.
- // Do nothing in this case.
-#endif
- .endm
-
-
-#endif /*XTENSA_CACHEATTRASM_H*/
-
diff --git a/src/arch/xtensa/include/xtensa/config/Makefile.am b/src/arch/xtensa/include/xtensa/config/Makefile.am
deleted file mode 100644
index 69f1b8a..0000000
--- a/src/arch/xtensa/include/xtensa/config/Makefile.am
+++ /dev/null
@@ -1,2 +0,0 @@
-noinst_HEADERS = \
- core.h
diff --git a/src/arch/xtensa/include/xtensa/config/core.h b/src/arch/xtensa/include/xtensa/config/core.h
deleted file mode 100644
index f5bb44f..0000000
--- a/src/arch/xtensa/include/xtensa/config/core.h
+++ /dev/null
@@ -1,1408 +0,0 @@
-/*
- * xtensa/config/core.h -- HAL definitions dependent on CORE configuration
- *
- * This header file is sometimes referred to as the "compile-time HAL" or CHAL.
- * It pulls definitions tailored for a specific Xtensa processor configuration.
- *
- * Sources for binaries meant to be configuration-independent generally avoid
- * including this file (they may use the configuration-specific HAL library).
- * It is normal for the HAL library source itself to include this file.
- */
-
-/*
- * Copyright (c) 2005-2015 Cadence Design Systems, Inc.
- *
- * Permission is hereby granted, free of charge, to any person obtaining
- * a copy of this software and associated documentation files (the
- * "Software"), to deal in the Software without restriction, including
- * without limitation the rights to use, copy, modify, merge, publish,
- * distribute, sublicense, and/or sell copies of the Software, and to
- * permit persons to whom the Software is furnished to do so, subject to
- * the following conditions:
- *
- * The above copyright notice and this permission notice shall be included
- * in all copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
- * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
- * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
- * IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY
- * CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
- * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
- * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
- */
-
-
-#ifndef XTENSA_CONFIG_CORE_H
-#define XTENSA_CONFIG_CORE_H
-
-/* CONFIGURATION INDEPENDENT DEFINITIONS: */
-#ifdef __XTENSA__
-#include <xtensa/hal.h>
-#include <xtensa/xtensa-versions.h>
-#else
-#include "../hal.h"
-#include "../xtensa-versions.h"
-#endif
-
-/* CONFIGURATION SPECIFIC DEFINITIONS: */
-#ifdef __XTENSA__
-#include <xtensa/config/core-isa.h>
-#include <xtensa/config/core-matmap.h>
-#include <xtensa/config/tie.h>
-#else
-#include "core-isa.h"
-#include "core-matmap.h"
-#include "tie.h"
-#endif
-
-#if defined (_ASMLANGUAGE) || defined (__ASSEMBLER__)
-#ifdef __XTENSA__
-#include <xtensa/config/tie-asm.h>
-#else
-#include "tie-asm.h"
-#endif
-#endif /*_ASMLANGUAGE or __ASSEMBLER__*/
-
-
-/*----------------------------------------------------------------------
- GENERAL
- ----------------------------------------------------------------------*/
-
-/*
- * Separators for macros that expand into arrays.
- * These can be predefined by files that #include this one,
- * when different separators are required.
- */
-/* Element separator for macros that expand into 1-dimensional arrays: */
-#ifndef XCHAL_SEP
-#define XCHAL_SEP ,
-#endif
-/* Array separator for macros that expand into 2-dimensional arrays: */
-#ifndef XCHAL_SEP2
-#define XCHAL_SEP2 },{
-#endif
-
-
-/*----------------------------------------------------------------------
- ERRATA
- ----------------------------------------------------------------------*/
-
-/*
- * Erratum T1020.H13, T1030.H7, T1040.H10, T1050.H4 (fixed in T1040.3 and T1050.1;
- * relevant only in XEA1, kernel-vector mode, level-one interrupts and overflows enabled):
- */
-#define XCHAL_MAYHAVE_ERRATUM_XEA1KWIN (XCHAL_HAVE_XEA1 && \
- (XCHAL_HW_RELEASE_AT_OR_BELOW(1040,2) != 0 \
- || XCHAL_HW_RELEASE_AT(1050,0)))
-/*
- * Erratum 453 present in RE-2013.2 up to RF-2014.0, fixed in RF-2014.1.
- * Applies to specific set of configuration options.
- * Part of the workaround is to add ISYNC at certain points in the code.
- * The workaround gated by this macro can be disabled if not needed, e.g. if
- * zero-overhead loop buffer will be disabled, by defining _NO_ERRATUM_453.
- */
-#if ( XCHAL_HW_MAX_VERSION >= XTENSA_HWVERSION_RE_2013_2 && \
- XCHAL_HW_MIN_VERSION <= XTENSA_HWVERSION_RF_2014_0 && \
- XCHAL_ICACHE_SIZE != 0 && XCHAL_HAVE_PIF /*covers also AXI/AHB*/ && \
- XCHAL_HAVE_LOOPS && XCHAL_LOOP_BUFFER_SIZE != 0 && \
- XCHAL_CLOCK_GATING_GLOBAL && !defined(_NO_ERRATUM_453) )
-#define XCHAL_ERRATUM_453 1
-#else
-#define XCHAL_ERRATUM_453 0
-#endif
-
-/*
- * Erratum 497 present in RE-2012.2 up to RG/RF-2015.2
- * Applies to specific set of configuration options.
- * Workaround is to add MEMWs after at most 8 cache WB instructions
- */
-#if ( ((XCHAL_HW_MAX_VERSION >= XTENSA_HWVERSION_RE_2012_0 && \
- XCHAL_HW_MIN_VERSION <= XTENSA_HWVERSION_RF_2015_2) || \
- (XCHAL_HW_MAX_VERSION >= XTENSA_HWVERSION_RG_2015_0 && \
- XCHAL_HW_MIN_VERSION <= XTENSA_HWVERSION_RG_2015_2) \
- ) && \
- XCHAL_DCACHE_IS_WRITEBACK && \
- XCHAL_HAVE_AXI && \
- XCHAL_HAVE_PIF_WR_RESP && \
- XCHAL_HAVE_PIF_REQ_ATTR && !defined(_NO_ERRATUM_497) \
- )
-#define XCHAL_ERRATUM_497 1
-#else
-#define XCHAL_ERRATUM_497 0
-#endif
-
-
-/*----------------------------------------------------------------------
- ISA
- ----------------------------------------------------------------------*/
-
-#if XCHAL_HAVE_BE
-# define XCHAL_HAVE_LE 0
-# define XCHAL_MEMORY_ORDER XTHAL_BIGENDIAN
-#else
-# define XCHAL_HAVE_LE 1
-# define XCHAL_MEMORY_ORDER XTHAL_LITTLEENDIAN
-#endif
-
-
-
-/*----------------------------------------------------------------------
- INTERRUPTS
- ----------------------------------------------------------------------*/
-
-/* Indexing macros: */
-#define _XCHAL_INTLEVEL_MASK(n) XCHAL_INTLEVEL ## n ## _MASK
-#define XCHAL_INTLEVEL_MASK(n) _XCHAL_INTLEVEL_MASK(n) /* n = 0 .. 15 */
-#define _XCHAL_INTLEVEL_ANDBELOWMASK(n) XCHAL_INTLEVEL ## n ## _ANDBELOW_MASK
-#define XCHAL_INTLEVEL_ANDBELOW_MASK(n) _XCHAL_INTLEVEL_ANDBELOWMASK(n) /* n = 0 .. 15 */
-#define _XCHAL_INTLEVEL_NUM(n) XCHAL_INTLEVEL ## n ## _NUM
-#define XCHAL_INTLEVEL_NUM(n) _XCHAL_INTLEVEL_NUM(n) /* n = 0 .. 15 */
-#define _XCHAL_INT_LEVEL(n) XCHAL_INT ## n ## _LEVEL
-#define XCHAL_INT_LEVEL(n) _XCHAL_INT_LEVEL(n) /* n = 0 .. 31 */
-#define _XCHAL_INT_TYPE(n) XCHAL_INT ## n ## _TYPE
-#define XCHAL_INT_TYPE(n) _XCHAL_INT_TYPE(n) /* n = 0 .. 31 */
-#define _XCHAL_TIMER_INTERRUPT(n) XCHAL_TIMER ## n ## _INTERRUPT
-#define XCHAL_TIMER_INTERRUPT(n) _XCHAL_TIMER_INTERRUPT(n) /* n = 0 .. 3 */
-
-
-#define XCHAL_HAVE_HIGHLEVEL_INTERRUPTS XCHAL_HAVE_HIGHPRI_INTERRUPTS
-#define XCHAL_NUM_LOWPRI_LEVELS 1 /* number of low-priority interrupt levels (always 1) */
-#define XCHAL_FIRST_HIGHPRI_LEVEL (XCHAL_NUM_LOWPRI_LEVELS+1) /* level of first high-priority interrupt (always 2) */
-/* Note: 1 <= LOWPRI_LEVELS <= EXCM_LEVEL < DEBUGLEVEL <= NUM_INTLEVELS < NMILEVEL <= 15 */
-
-/* These values are constant for existing Xtensa processor implementations: */
-#define XCHAL_INTLEVEL0_MASK 0x00000000
-#define XCHAL_INTLEVEL8_MASK 0x00000000
-#define XCHAL_INTLEVEL9_MASK 0x00000000
-#define XCHAL_INTLEVEL10_MASK 0x00000000
-#define XCHAL_INTLEVEL11_MASK 0x00000000
-#define XCHAL_INTLEVEL12_MASK 0x00000000
-#define XCHAL_INTLEVEL13_MASK 0x00000000
-#define XCHAL_INTLEVEL14_MASK 0x00000000
-#define XCHAL_INTLEVEL15_MASK 0x00000000
-
-/* Array of masks of interrupts at each interrupt level: */
-#define XCHAL_INTLEVEL_MASKS XCHAL_INTLEVEL0_MASK \
- XCHAL_SEP XCHAL_INTLEVEL1_MASK \
- XCHAL_SEP XCHAL_INTLEVEL2_MASK \
- XCHAL_SEP XCHAL_INTLEVEL3_MASK \
- XCHAL_SEP XCHAL_INTLEVEL4_MASK \
- XCHAL_SEP XCHAL_INTLEVEL5_MASK \
- XCHAL_SEP XCHAL_INTLEVEL6_MASK \
- XCHAL_SEP XCHAL_INTLEVEL7_MASK \
- XCHAL_SEP XCHAL_INTLEVEL8_MASK \
- XCHAL_SEP XCHAL_INTLEVEL9_MASK \
- XCHAL_SEP XCHAL_INTLEVEL10_MASK \
- XCHAL_SEP XCHAL_INTLEVEL11_MASK \
- XCHAL_SEP XCHAL_INTLEVEL12_MASK \
- XCHAL_SEP XCHAL_INTLEVEL13_MASK \
- XCHAL_SEP XCHAL_INTLEVEL14_MASK \
- XCHAL_SEP XCHAL_INTLEVEL15_MASK
-
-/* These values are constant for existing Xtensa processor implementations: */
-#define XCHAL_INTLEVEL0_ANDBELOW_MASK 0x00000000
-#define XCHAL_INTLEVEL8_ANDBELOW_MASK XCHAL_INTLEVEL7_ANDBELOW_MASK
-#define XCHAL_INTLEVEL9_ANDBELOW_MASK XCHAL_INTLEVEL7_ANDBELOW_MASK
-#define XCHAL_INTLEVEL10_ANDBELOW_MASK XCHAL_INTLEVEL7_ANDBELOW_MASK
-#define XCHAL_INTLEVEL11_ANDBELOW_MASK XCHAL_INTLEVEL7_ANDBELOW_MASK
-#define XCHAL_INTLEVEL12_ANDBELOW_MASK XCHAL_INTLEVEL7_ANDBELOW_MASK
-#define XCHAL_INTLEVEL13_ANDBELOW_MASK XCHAL_INTLEVEL7_ANDBELOW_MASK
-#define XCHAL_INTLEVEL14_ANDBELOW_MASK XCHAL_INTLEVEL7_ANDBELOW_MASK
-#define XCHAL_INTLEVEL15_ANDBELOW_MASK XCHAL_INTLEVEL7_ANDBELOW_MASK
-
-/* Mask of all low-priority interrupts: */
-#define XCHAL_LOWPRI_MASK XCHAL_INTLEVEL1_ANDBELOW_MASK
-
-/* Mask of all interrupts masked by PS.EXCM (or CEXCM): */
-#define XCHAL_EXCM_MASK XCHAL_INTLEVEL_ANDBELOW_MASK(XCHAL_EXCM_LEVEL)
-
-/* Array of masks of interrupts at each range 1..n of interrupt levels: */
-#define XCHAL_INTLEVEL_ANDBELOW_MASKS XCHAL_INTLEVEL0_ANDBELOW_MASK \
- XCHAL_SEP XCHAL_INTLEVEL1_ANDBELOW_MASK \
- XCHAL_SEP XCHAL_INTLEVEL2_ANDBELOW_MASK \
- XCHAL_SEP XCHAL_INTLEVEL3_ANDBELOW_MASK \
- XCHAL_SEP XCHAL_INTLEVEL4_ANDBELOW_MASK \
- XCHAL_SEP XCHAL_INTLEVEL5_ANDBELOW_MASK \
- XCHAL_SEP XCHAL_INTLEVEL6_ANDBELOW_MASK \
- XCHAL_SEP XCHAL_INTLEVEL7_ANDBELOW_MASK \
- XCHAL_SEP XCHAL_INTLEVEL8_ANDBELOW_MASK \
- XCHAL_SEP XCHAL_INTLEVEL9_ANDBELOW_MASK \
- XCHAL_SEP XCHAL_INTLEVEL10_ANDBELOW_MASK \
- XCHAL_SEP XCHAL_INTLEVEL11_ANDBELOW_MASK \
- XCHAL_SEP XCHAL_INTLEVEL12_ANDBELOW_MASK \
- XCHAL_SEP XCHAL_INTLEVEL13_ANDBELOW_MASK \
- XCHAL_SEP XCHAL_INTLEVEL14_ANDBELOW_MASK \
- XCHAL_SEP XCHAL_INTLEVEL15_ANDBELOW_MASK
-
-#if 0 /*XCHAL_HAVE_NMI*/
-/* NMI "interrupt level" (for use with EXCSAVE_n, EPS_n, EPC_n, RFI n): */
-# define XCHAL_NMILEVEL (XCHAL_NUM_INTLEVELS+1)
-#endif
-
-/* Array of levels of each possible interrupt: */
-#define XCHAL_INT_LEVELS XCHAL_INT0_LEVEL \
- XCHAL_SEP XCHAL_INT1_LEVEL \
- XCHAL_SEP XCHAL_INT2_LEVEL \
- XCHAL_SEP XCHAL_INT3_LEVEL \
- XCHAL_SEP XCHAL_INT4_LEVEL \
- XCHAL_SEP XCHAL_INT5_LEVEL \
- XCHAL_SEP XCHAL_INT6_LEVEL \
- XCHAL_SEP XCHAL_INT7_LEVEL \
- XCHAL_SEP XCHAL_INT8_LEVEL \
- XCHAL_SEP XCHAL_INT9_LEVEL \
- XCHAL_SEP XCHAL_INT10_LEVEL \
- XCHAL_SEP XCHAL_INT11_LEVEL \
- XCHAL_SEP XCHAL_INT12_LEVEL \
- XCHAL_SEP XCHAL_INT13_LEVEL \
- XCHAL_SEP XCHAL_INT14_LEVEL \
- XCHAL_SEP XCHAL_INT15_LEVEL \
- XCHAL_SEP XCHAL_INT16_LEVEL \
- XCHAL_SEP XCHAL_INT17_LEVEL \
- XCHAL_SEP XCHAL_INT18_LEVEL \
- XCHAL_SEP XCHAL_INT19_LEVEL \
- XCHAL_SEP XCHAL_INT20_LEVEL \
- XCHAL_SEP XCHAL_INT21_LEVEL \
- XCHAL_SEP XCHAL_INT22_LEVEL \
- XCHAL_SEP XCHAL_INT23_LEVEL \
- XCHAL_SEP XCHAL_INT24_LEVEL \
- XCHAL_SEP XCHAL_INT25_LEVEL \
- XCHAL_SEP XCHAL_INT26_LEVEL \
- XCHAL_SEP XCHAL_INT27_LEVEL \
- XCHAL_SEP XCHAL_INT28_LEVEL \
- XCHAL_SEP XCHAL_INT29_LEVEL \
- XCHAL_SEP XCHAL_INT30_LEVEL \
- XCHAL_SEP XCHAL_INT31_LEVEL
-
-/* Array of types of each possible interrupt: */
-#define XCHAL_INT_TYPES XCHAL_INT0_TYPE \
- XCHAL_SEP XCHAL_INT1_TYPE \
- XCHAL_SEP XCHAL_INT2_TYPE \
- XCHAL_SEP XCHAL_INT3_TYPE \
- XCHAL_SEP XCHAL_INT4_TYPE \
- XCHAL_SEP XCHAL_INT5_TYPE \
- XCHAL_SEP XCHAL_INT6_TYPE \
- XCHAL_SEP XCHAL_INT7_TYPE \
- XCHAL_SEP XCHAL_INT8_TYPE \
- XCHAL_SEP XCHAL_INT9_TYPE \
- XCHAL_SEP XCHAL_INT10_TYPE \
- XCHAL_SEP XCHAL_INT11_TYPE \
- XCHAL_SEP XCHAL_INT12_TYPE \
- XCHAL_SEP XCHAL_INT13_TYPE \
- XCHAL_SEP XCHAL_INT14_TYPE \
- XCHAL_SEP XCHAL_INT15_TYPE \
- XCHAL_SEP XCHAL_INT16_TYPE \
- XCHAL_SEP XCHAL_INT17_TYPE \
- XCHAL_SEP XCHAL_INT18_TYPE \
- XCHAL_SEP XCHAL_INT19_TYPE \
- XCHAL_SEP XCHAL_INT20_TYPE \
- XCHAL_SEP XCHAL_INT21_TYPE \
- XCHAL_SEP XCHAL_INT22_TYPE \
- XCHAL_SEP XCHAL_INT23_TYPE \
- XCHAL_SEP XCHAL_INT24_TYPE \
- XCHAL_SEP XCHAL_INT25_TYPE \
- XCHAL_SEP XCHAL_INT26_TYPE \
- XCHAL_SEP XCHAL_INT27_TYPE \
- XCHAL_SEP XCHAL_INT28_TYPE \
- XCHAL_SEP XCHAL_INT29_TYPE \
- XCHAL_SEP XCHAL_INT30_TYPE \
- XCHAL_SEP XCHAL_INT31_TYPE
-
-/* Array of masks of interrupts for each type of interrupt: */
-#define XCHAL_INTTYPE_MASKS XCHAL_INTTYPE_MASK_UNCONFIGURED \
- XCHAL_SEP XCHAL_INTTYPE_MASK_SOFTWARE \
- XCHAL_SEP XCHAL_INTTYPE_MASK_EXTERN_EDGE \
- XCHAL_SEP XCHAL_INTTYPE_MASK_EXTERN_LEVEL \
- XCHAL_SEP XCHAL_INTTYPE_MASK_TIMER \
- XCHAL_SEP XCHAL_INTTYPE_MASK_NMI \
- XCHAL_SEP XCHAL_INTTYPE_MASK_WRITE_ERROR \
- XCHAL_SEP XCHAL_INTTYPE_MASK_IDMA_DONE \
- XCHAL_SEP XCHAL_INTTYPE_MASK_IDMA_ERR \
- XCHAL_SEP XCHAL_INTTYPE_MASK_GS_ERR
-
-/* Interrupts that can be cleared using the INTCLEAR special register: */
-#define XCHAL_INTCLEARABLE_MASK (XCHAL_INTTYPE_MASK_SOFTWARE+XCHAL_INTTYPE_MASK_EXTERN_EDGE+XCHAL_INTTYPE_MASK_WRITE_ERROR)
-/* Interrupts that can be triggered using the INTSET special register: */
-#define XCHAL_INTSETTABLE_MASK XCHAL_INTTYPE_MASK_SOFTWARE
-
-/* Array of interrupts assigned to each timer (CCOMPARE0 to CCOMPARE3): */
-#define XCHAL_TIMER_INTERRUPTS XCHAL_TIMER0_INTERRUPT \
- XCHAL_SEP XCHAL_TIMER1_INTERRUPT \
- XCHAL_SEP XCHAL_TIMER2_INTERRUPT \
- XCHAL_SEP XCHAL_TIMER3_INTERRUPT
-
-
-
-/* For backward compatibility and for the array macros, define macros for
- * each unconfigured interrupt number (unfortunately, the value of
- * XTHAL_INTTYPE_UNCONFIGURED is not zero): */
-#if XCHAL_NUM_INTERRUPTS == 0
-# define XCHAL_INT0_LEVEL 0
-# define XCHAL_INT0_TYPE XTHAL_INTTYPE_UNCONFIGURED
-#endif
-#if XCHAL_NUM_INTERRUPTS <= 1
-# define XCHAL_INT1_LEVEL 0
-# define XCHAL_INT1_TYPE XTHAL_INTTYPE_UNCONFIGURED
-#endif
-#if XCHAL_NUM_INTERRUPTS <= 2
-# define XCHAL_INT2_LEVEL 0
-# define XCHAL_INT2_TYPE XTHAL_INTTYPE_UNCONFIGURED
-#endif
-#if XCHAL_NUM_INTERRUPTS <= 3
-# define XCHAL_INT3_LEVEL 0
-# define XCHAL_INT3_TYPE XTHAL_INTTYPE_UNCONFIGURED
-#endif
-#if XCHAL_NUM_INTERRUPTS <= 4
-# define XCHAL_INT4_LEVEL 0
-# define XCHAL_INT4_TYPE XTHAL_INTTYPE_UNCONFIGURED
-#endif
-#if XCHAL_NUM_INTERRUPTS <= 5
-# define XCHAL_INT5_LEVEL 0
-# define XCHAL_INT5_TYPE XTHAL_INTTYPE_UNCONFIGURED
-#endif
-#if XCHAL_NUM_INTERRUPTS <= 6
-# define XCHAL_INT6_LEVEL 0
-# define XCHAL_INT6_TYPE XTHAL_INTTYPE_UNCONFIGURED
-#endif
-#if XCHAL_NUM_INTERRUPTS <= 7
-# define XCHAL_INT7_LEVEL 0
-# define XCHAL_INT7_TYPE XTHAL_INTTYPE_UNCONFIGURED
-#endif
-#if XCHAL_NUM_INTERRUPTS <= 8
-# define XCHAL_INT8_LEVEL 0
-# define XCHAL_INT8_TYPE XTHAL_INTTYPE_UNCONFIGURED
-#endif
-#if XCHAL_NUM_INTERRUPTS <= 9
-# define XCHAL_INT9_LEVEL 0
-# define XCHAL_INT9_TYPE XTHAL_INTTYPE_UNCONFIGURED
-#endif
-#if XCHAL_NUM_INTERRUPTS <= 10
-# define XCHAL_INT10_LEVEL 0
-# define XCHAL_INT10_TYPE XTHAL_INTTYPE_UNCONFIGURED
-#endif
-#if XCHAL_NUM_INTERRUPTS <= 11
-# define XCHAL_INT11_LEVEL 0
-# define XCHAL_INT11_TYPE XTHAL_INTTYPE_UNCONFIGURED
-#endif
-#if XCHAL_NUM_INTERRUPTS <= 12
-# define XCHAL_INT12_LEVEL 0
-# define XCHAL_INT12_TYPE XTHAL_INTTYPE_UNCONFIGURED
-#endif
-#if XCHAL_NUM_INTERRUPTS <= 13
-# define XCHAL_INT13_LEVEL 0
-# define XCHAL_INT13_TYPE XTHAL_INTTYPE_UNCONFIGURED
-#endif
-#if XCHAL_NUM_INTERRUPTS <= 14
-# define XCHAL_INT14_LEVEL 0
-# define XCHAL_INT14_TYPE XTHAL_INTTYPE_UNCONFIGURED
-#endif
-#if XCHAL_NUM_INTERRUPTS <= 15
-# define XCHAL_INT15_LEVEL 0
-# define XCHAL_INT15_TYPE XTHAL_INTTYPE_UNCONFIGURED
-#endif
-#if XCHAL_NUM_INTERRUPTS <= 16
-# define XCHAL_INT16_LEVEL 0
-# define XCHAL_INT16_TYPE XTHAL_INTTYPE_UNCONFIGURED
-#endif
-#if XCHAL_NUM_INTERRUPTS <= 17
-# define XCHAL_INT17_LEVEL 0
-# define XCHAL_INT17_TYPE XTHAL_INTTYPE_UNCONFIGURED
-#endif
-#if XCHAL_NUM_INTERRUPTS <= 18
-# define XCHAL_INT18_LEVEL 0
-# define XCHAL_INT18_TYPE XTHAL_INTTYPE_UNCONFIGURED
-#endif
-#if XCHAL_NUM_INTERRUPTS <= 19
-# define XCHAL_INT19_LEVEL 0
-# define XCHAL_INT19_TYPE XTHAL_INTTYPE_UNCONFIGURED
-#endif
-#if XCHAL_NUM_INTERRUPTS <= 20
-# define XCHAL_INT20_LEVEL 0
-# define XCHAL_INT20_TYPE XTHAL_INTTYPE_UNCONFIGURED
-#endif
-#if XCHAL_NUM_INTERRUPTS <= 21
-# define XCHAL_INT21_LEVEL 0
-# define XCHAL_INT21_TYPE XTHAL_INTTYPE_UNCONFIGURED
-#endif
-#if XCHAL_NUM_INTERRUPTS <= 22
-# define XCHAL_INT22_LEVEL 0
-# define XCHAL_INT22_TYPE XTHAL_INTTYPE_UNCONFIGURED
-#endif
-#if XCHAL_NUM_INTERRUPTS <= 23
-# define XCHAL_INT23_LEVEL 0
-# define XCHAL_INT23_TYPE XTHAL_INTTYPE_UNCONFIGURED
-#endif
-#if XCHAL_NUM_INTERRUPTS <= 24
-# define XCHAL_INT24_LEVEL 0
-# define XCHAL_INT24_TYPE XTHAL_INTTYPE_UNCONFIGURED
-#endif
-#if XCHAL_NUM_INTERRUPTS <= 25
-# define XCHAL_INT25_LEVEL 0
-# define XCHAL_INT25_TYPE XTHAL_INTTYPE_UNCONFIGURED
-#endif
-#if XCHAL_NUM_INTERRUPTS <= 26
-# define XCHAL_INT26_LEVEL 0
-# define XCHAL_INT26_TYPE XTHAL_INTTYPE_UNCONFIGURED
-#endif
-#if XCHAL_NUM_INTERRUPTS <= 27
-# define XCHAL_INT27_LEVEL 0
-# define XCHAL_INT27_TYPE XTHAL_INTTYPE_UNCONFIGURED
-#endif
-#if XCHAL_NUM_INTERRUPTS <= 28
-# define XCHAL_INT28_LEVEL 0
-# define XCHAL_INT28_TYPE XTHAL_INTTYPE_UNCONFIGURED
-#endif
-#if XCHAL_NUM_INTERRUPTS <= 29
-# define XCHAL_INT29_LEVEL 0
-# define XCHAL_INT29_TYPE XTHAL_INTTYPE_UNCONFIGURED
-#endif
-#if XCHAL_NUM_INTERRUPTS <= 30
-# define XCHAL_INT30_LEVEL 0
-# define XCHAL_INT30_TYPE XTHAL_INTTYPE_UNCONFIGURED
-#endif
-#if XCHAL_NUM_INTERRUPTS <= 31
-# define XCHAL_INT31_LEVEL 0
-# define XCHAL_INT31_TYPE XTHAL_INTTYPE_UNCONFIGURED
-#endif
-
-
-/*
- * Masks and levels corresponding to each *external* interrupt.
- */
-
-#define XCHAL_EXTINT0_MASK (1 << XCHAL_EXTINT0_NUM)
-#define XCHAL_EXTINT0_LEVEL XCHAL_INT_LEVEL(XCHAL_EXTINT0_NUM)
-#define XCHAL_EXTINT1_MASK (1 << XCHAL_EXTINT1_NUM)
-#define XCHAL_EXTINT1_LEVEL XCHAL_INT_LEVEL(XCHAL_EXTINT1_NUM)
-#define XCHAL_EXTINT2_MASK (1 << XCHAL_EXTINT2_NUM)
-#define XCHAL_EXTINT2_LEVEL XCHAL_INT_LEVEL(XCHAL_EXTINT2_NUM)
-#define XCHAL_EXTINT3_MASK (1 << XCHAL_EXTINT3_NUM)
-#define XCHAL_EXTINT3_LEVEL XCHAL_INT_LEVEL(XCHAL_EXTINT3_NUM)
-#define XCHAL_EXTINT4_MASK (1 << XCHAL_EXTINT4_NUM)
-#define XCHAL_EXTINT4_LEVEL XCHAL_INT_LEVEL(XCHAL_EXTINT4_NUM)
-#define XCHAL_EXTINT5_MASK (1 << XCHAL_EXTINT5_NUM)
-#define XCHAL_EXTINT5_LEVEL XCHAL_INT_LEVEL(XCHAL_EXTINT5_NUM)
-#define XCHAL_EXTINT6_MASK (1 << XCHAL_EXTINT6_NUM)
-#define XCHAL_EXTINT6_LEVEL XCHAL_INT_LEVEL(XCHAL_EXTINT6_NUM)
-#define XCHAL_EXTINT7_MASK (1 << XCHAL_EXTINT7_NUM)
-#define XCHAL_EXTINT7_LEVEL XCHAL_INT_LEVEL(XCHAL_EXTINT7_NUM)
-#define XCHAL_EXTINT8_MASK (1 << XCHAL_EXTINT8_NUM)
-#define XCHAL_EXTINT8_LEVEL XCHAL_INT_LEVEL(XCHAL_EXTINT8_NUM)
-#define XCHAL_EXTINT9_MASK (1 << XCHAL_EXTINT9_NUM)
-#define XCHAL_EXTINT9_LEVEL XCHAL_INT_LEVEL(XCHAL_EXTINT9_NUM)
-#define XCHAL_EXTINT10_MASK (1 << XCHAL_EXTINT10_NUM)
-#define XCHAL_EXTINT10_LEVEL XCHAL_INT_LEVEL(XCHAL_EXTINT10_NUM)
-#define XCHAL_EXTINT11_MASK (1 << XCHAL_EXTINT11_NUM)
-#define XCHAL_EXTINT11_LEVEL XCHAL_INT_LEVEL(XCHAL_EXTINT11_NUM)
-#define XCHAL_EXTINT12_MASK (1 << XCHAL_EXTINT12_NUM)
-#define XCHAL_EXTINT12_LEVEL XCHAL_INT_LEVEL(XCHAL_EXTINT12_NUM)
-#define XCHAL_EXTINT13_MASK (1 << XCHAL_EXTINT13_NUM)
-#define XCHAL_EXTINT13_LEVEL XCHAL_INT_LEVEL(XCHAL_EXTINT13_NUM)
-#define XCHAL_EXTINT14_MASK (1 << XCHAL_EXTINT14_NUM)
-#define XCHAL_EXTINT14_LEVEL XCHAL_INT_LEVEL(XCHAL_EXTINT14_NUM)
-#define XCHAL_EXTINT15_MASK (1 << XCHAL_EXTINT15_NUM)
-#define XCHAL_EXTINT15_LEVEL XCHAL_INT_LEVEL(XCHAL_EXTINT15_NUM)
-#define XCHAL_EXTINT16_MASK (1 << XCHAL_EXTINT16_NUM)
-#define XCHAL_EXTINT16_LEVEL XCHAL_INT_LEVEL(XCHAL_EXTINT16_NUM)
-#define XCHAL_EXTINT17_MASK (1 << XCHAL_EXTINT17_NUM)
-#define XCHAL_EXTINT17_LEVEL XCHAL_INT_LEVEL(XCHAL_EXTINT17_NUM)
-#define XCHAL_EXTINT18_MASK (1 << XCHAL_EXTINT18_NUM)
-#define XCHAL_EXTINT18_LEVEL XCHAL_INT_LEVEL(XCHAL_EXTINT18_NUM)
-#define XCHAL_EXTINT19_MASK (1 << XCHAL_EXTINT19_NUM)
-#define XCHAL_EXTINT19_LEVEL XCHAL_INT_LEVEL(XCHAL_EXTINT19_NUM)
-#define XCHAL_EXTINT20_MASK (1 << XCHAL_EXTINT20_NUM)
-#define XCHAL_EXTINT20_LEVEL XCHAL_INT_LEVEL(XCHAL_EXTINT20_NUM)
-#define XCHAL_EXTINT21_MASK (1 << XCHAL_EXTINT21_NUM)
-#define XCHAL_EXTINT21_LEVEL XCHAL_INT_LEVEL(XCHAL_EXTINT21_NUM)
-#define XCHAL_EXTINT22_MASK (1 << XCHAL_EXTINT22_NUM)
-#define XCHAL_EXTINT22_LEVEL XCHAL_INT_LEVEL(XCHAL_EXTINT22_NUM)
-#define XCHAL_EXTINT23_MASK (1 << XCHAL_EXTINT23_NUM)
-#define XCHAL_EXTINT23_LEVEL XCHAL_INT_LEVEL(XCHAL_EXTINT23_NUM)
-#define XCHAL_EXTINT24_MASK (1 << XCHAL_EXTINT24_NUM)
-#define XCHAL_EXTINT24_LEVEL XCHAL_INT_LEVEL(XCHAL_EXTINT24_NUM)
-#define XCHAL_EXTINT25_MASK (1 << XCHAL_EXTINT25_NUM)
-#define XCHAL_EXTINT25_LEVEL XCHAL_INT_LEVEL(XCHAL_EXTINT25_NUM)
-#define XCHAL_EXTINT26_MASK (1 << XCHAL_EXTINT26_NUM)
-#define XCHAL_EXTINT26_LEVEL XCHAL_INT_LEVEL(XCHAL_EXTINT26_NUM)
-#define XCHAL_EXTINT27_MASK (1 << XCHAL_EXTINT27_NUM)
-#define XCHAL_EXTINT27_LEVEL XCHAL_INT_LEVEL(XCHAL_EXTINT27_NUM)
-#define XCHAL_EXTINT28_MASK (1 << XCHAL_EXTINT28_NUM)
-#define XCHAL_EXTINT28_LEVEL XCHAL_INT_LEVEL(XCHAL_EXTINT28_NUM)
-#define XCHAL_EXTINT29_MASK (1 << XCHAL_EXTINT29_NUM)
-#define XCHAL_EXTINT29_LEVEL XCHAL_INT_LEVEL(XCHAL_EXTINT29_NUM)
-#define XCHAL_EXTINT30_MASK (1 << XCHAL_EXTINT30_NUM)
-#define XCHAL_EXTINT30_LEVEL XCHAL_INT_LEVEL(XCHAL_EXTINT30_NUM)
-#define XCHAL_EXTINT31_MASK (1 << XCHAL_EXTINT31_NUM)
-#define XCHAL_EXTINT31_LEVEL XCHAL_INT_LEVEL(XCHAL_EXTINT31_NUM)
-
-
-/*----------------------------------------------------------------------
- EXCEPTIONS and VECTORS
- ----------------------------------------------------------------------*/
-
-/* For backward compatibility ONLY -- DO NOT USE (will be removed in future release): */
-#define XCHAL_HAVE_OLD_EXC_ARCH XCHAL_HAVE_XEA1 /* (DEPRECATED) 1 if old exception architecture (XEA1), 0 otherwise (eg. XEA2) */
-#define XCHAL_HAVE_EXCM XCHAL_HAVE_XEA2 /* (DEPRECATED) 1 if PS.EXCM bit exists (currently equals XCHAL_HAVE_TLBS) */
-#ifdef XCHAL_USER_VECTOR_VADDR
-#define XCHAL_PROGRAMEXC_VECTOR_VADDR XCHAL_USER_VECTOR_VADDR
-#define XCHAL_USEREXC_VECTOR_VADDR XCHAL_USER_VECTOR_VADDR
-#endif
-#ifdef XCHAL_USER_VECTOR_PADDR
-# define XCHAL_PROGRAMEXC_VECTOR_PADDR XCHAL_USER_VECTOR_PADDR
-# define XCHAL_USEREXC_VECTOR_PADDR XCHAL_USER_VECTOR_PADDR
-#endif
-#ifdef XCHAL_KERNEL_VECTOR_VADDR
-# define XCHAL_STACKEDEXC_VECTOR_VADDR XCHAL_KERNEL_VECTOR_VADDR
-# define XCHAL_KERNELEXC_VECTOR_VADDR XCHAL_KERNEL_VECTOR_VADDR
-#endif
-#ifdef XCHAL_KERNEL_VECTOR_PADDR
-# define XCHAL_STACKEDEXC_VECTOR_PADDR XCHAL_KERNEL_VECTOR_PADDR
-# define XCHAL_KERNELEXC_VECTOR_PADDR XCHAL_KERNEL_VECTOR_PADDR
-#endif
-
-#if 0
-#if XCHAL_HAVE_DEBUG
-# define XCHAL_DEBUG_VECTOR_VADDR XCHAL_INTLEVEL_VECTOR_VADDR(XCHAL_DEBUGLEVEL)
-/* This one should only get defined if the corresponding intlevel paddr macro exists: */
-# define XCHAL_DEBUG_VECTOR_PADDR XCHAL_INTLEVEL_VECTOR_PADDR(XCHAL_DEBUGLEVEL)
-#endif
-#endif
-
-/* Indexing macros: */
-#define _XCHAL_INTLEVEL_VECTOR_VADDR(n) XCHAL_INTLEVEL ## n ## _VECTOR_VADDR
-#define XCHAL_INTLEVEL_VECTOR_VADDR(n) _XCHAL_INTLEVEL_VECTOR_VADDR(n) /* n = 0 .. 15 */
-
-/*
- * General Exception Causes
- * (values of EXCCAUSE special register set by general exceptions,
- * which vector to the user, kernel, or double-exception vectors).
- *
- * DEPRECATED. Please use the equivalent EXCCAUSE_xxx macros
- * defined in <xtensa/corebits.h>. (Note that these have slightly
- * different names, they don't just have the XCHAL_ prefix removed.)
- */
-#define XCHAL_EXCCAUSE_ILLEGAL_INSTRUCTION 0 /* Illegal Instruction */
-#define XCHAL_EXCCAUSE_SYSTEM_CALL 1 /* System Call */
-#define XCHAL_EXCCAUSE_INSTRUCTION_FETCH_ERROR 2 /* Instruction Fetch Error */
-#define XCHAL_EXCCAUSE_LOAD_STORE_ERROR 3 /* Load Store Error */
-#define XCHAL_EXCCAUSE_LEVEL1_INTERRUPT 4 /* Level 1 Interrupt */
-#define XCHAL_EXCCAUSE_ALLOCA 5 /* Stack Extension Assist */
-#define XCHAL_EXCCAUSE_INTEGER_DIVIDE_BY_ZERO 6 /* Integer Divide by Zero */
-#define XCHAL_EXCCAUSE_SPECULATION 7 /* Speculation */
-#define XCHAL_EXCCAUSE_PRIVILEGED 8 /* Privileged Instruction */
-#define XCHAL_EXCCAUSE_UNALIGNED 9 /* Unaligned Load Store */
-/*10..15 reserved*/
-#define XCHAL_EXCCAUSE_ITLB_MISS 16 /* ITlb Miss Exception */
-#define XCHAL_EXCCAUSE_ITLB_MULTIHIT 17 /* ITlb Mutltihit Exception */
-#define XCHAL_EXCCAUSE_ITLB_PRIVILEGE 18 /* ITlb Privilege Exception */
-#define XCHAL_EXCCAUSE_ITLB_SIZE_RESTRICTION 19 /* ITlb Size Restriction Exception */
-#define XCHAL_EXCCAUSE_FETCH_CACHE_ATTRIBUTE 20 /* Fetch Cache Attribute Exception */
-/*21..23 reserved*/
-#define XCHAL_EXCCAUSE_DTLB_MISS 24 /* DTlb Miss Exception */
-#define XCHAL_EXCCAUSE_DTLB_MULTIHIT 25 /* DTlb Multihit Exception */
-#define XCHAL_EXCCAUSE_DTLB_PRIVILEGE 26 /* DTlb Privilege Exception */
-#define XCHAL_EXCCAUSE_DTLB_SIZE_RESTRICTION 27 /* DTlb Size Restriction Exception */
-#define XCHAL_EXCCAUSE_LOAD_CACHE_ATTRIBUTE 28 /* Load Cache Attribute Exception */
-#define XCHAL_EXCCAUSE_STORE_CACHE_ATTRIBUTE 29 /* Store Cache Attribute Exception */
-/*30..31 reserved*/
-#define XCHAL_EXCCAUSE_COPROCESSOR0_DISABLED 32 /* Coprocessor 0 disabled */
-#define XCHAL_EXCCAUSE_COPROCESSOR1_DISABLED 33 /* Coprocessor 1 disabled */
-#define XCHAL_EXCCAUSE_COPROCESSOR2_DISABLED 34 /* Coprocessor 2 disabled */
-#define XCHAL_EXCCAUSE_COPROCESSOR3_DISABLED 35 /* Coprocessor 3 disabled */
-#define XCHAL_EXCCAUSE_COPROCESSOR4_DISABLED 36 /* Coprocessor 4 disabled */
-#define XCHAL_EXCCAUSE_COPROCESSOR5_DISABLED 37 /* Coprocessor 5 disabled */
-#define XCHAL_EXCCAUSE_COPROCESSOR6_DISABLED 38 /* Coprocessor 6 disabled */
-#define XCHAL_EXCCAUSE_COPROCESSOR7_DISABLED 39 /* Coprocessor 7 disabled */
-/*40..63 reserved*/
-
-
-/*
- * Miscellaneous special register fields.
- *
- * For each special register, and each field within each register:
- * XCHAL_<regname>_VALIDMASK is the set of bits defined in the register.
- * XCHAL_<regname>_<field>_BITS is the number of bits in the field.
- * XCHAL_<regname>_<field>_NUM is 2^bits, the number of possible values
- * of the field.
- * XCHAL_<regname>_<field>_SHIFT is the position of the field within
- * the register, starting from the least significant bit.
- *
- * DEPRECATED. Please use the equivalent macros defined in
- * <xtensa/corebits.h>. (Note that these have different names.)
- */
-
-/* DBREAKC (special register number 160): */
-#define XCHAL_DBREAKC_VALIDMASK 0xC000003F
-#define XCHAL_DBREAKC_MASK_BITS 6
-#define XCHAL_DBREAKC_MASK_NUM 64
-#define XCHAL_DBREAKC_MASK_SHIFT 0
-#define XCHAL_DBREAKC_MASK_MASK 0x0000003F
-#define XCHAL_DBREAKC_LOADBREAK_BITS 1
-#define XCHAL_DBREAKC_LOADBREAK_NUM 2
-#define XCHAL_DBREAKC_LOADBREAK_SHIFT 30
-#define XCHAL_DBREAKC_LOADBREAK_MASK 0x40000000
-#define XCHAL_DBREAKC_STOREBREAK_BITS 1
-#define XCHAL_DBREAKC_STOREBREAK_NUM 2
-#define XCHAL_DBREAKC_STOREBREAK_SHIFT 31
-#define XCHAL_DBREAKC_STOREBREAK_MASK 0x80000000
-/* PS (special register number 230): */
-#define XCHAL_PS_VALIDMASK 0x00070F3F
-#define XCHAL_PS_INTLEVEL_BITS 4
-#define XCHAL_PS_INTLEVEL_NUM 16
-#define XCHAL_PS_INTLEVEL_SHIFT 0
-#define XCHAL_PS_INTLEVEL_MASK 0x0000000F
-#define XCHAL_PS_EXCM_BITS 1
-#define XCHAL_PS_EXCM_NUM 2
-#define XCHAL_PS_EXCM_SHIFT 4
-#define XCHAL_PS_EXCM_MASK 0x00000010
-#define XCHAL_PS_UM_BITS 1
-#define XCHAL_PS_UM_NUM 2
-#define XCHAL_PS_UM_SHIFT 5
-#define XCHAL_PS_UM_MASK 0x00000020
-#define XCHAL_PS_RING_BITS 2
-#define XCHAL_PS_RING_NUM 4
-#define XCHAL_PS_RING_SHIFT 6
-#define XCHAL_PS_RING_MASK 0x000000C0
-#define XCHAL_PS_OWB_BITS 4
-#define XCHAL_PS_OWB_NUM 16
-#define XCHAL_PS_OWB_SHIFT 8
-#define XCHAL_PS_OWB_MASK 0x00000F00
-#define XCHAL_PS_CALLINC_BITS 2
-#define XCHAL_PS_CALLINC_NUM 4
-#define XCHAL_PS_CALLINC_SHIFT 16
-#define XCHAL_PS_CALLINC_MASK 0x00030000
-#define XCHAL_PS_WOE_BITS 1
-#define XCHAL_PS_WOE_NUM 2
-#define XCHAL_PS_WOE_SHIFT 18
-#define XCHAL_PS_WOE_MASK 0x00040000
-/* EXCCAUSE (special register number 232): */
-#define XCHAL_EXCCAUSE_VALIDMASK 0x0000003F
-#define XCHAL_EXCCAUSE_BITS 6
-#define XCHAL_EXCCAUSE_NUM 64
-#define XCHAL_EXCCAUSE_SHIFT 0
-#define XCHAL_EXCCAUSE_MASK 0x0000003F
-/* DEBUGCAUSE (special register number 233): */
-#define XCHAL_DEBUGCAUSE_VALIDMASK 0x0000003F
-#define XCHAL_DEBUGCAUSE_ICOUNT_BITS 1
-#define XCHAL_DEBUGCAUSE_ICOUNT_NUM 2
-#define XCHAL_DEBUGCAUSE_ICOUNT_SHIFT 0
-#define XCHAL_DEBUGCAUSE_ICOUNT_MASK 0x00000001
-#define XCHAL_DEBUGCAUSE_IBREAK_BITS 1
-#define XCHAL_DEBUGCAUSE_IBREAK_NUM 2
-#define XCHAL_DEBUGCAUSE_IBREAK_SHIFT 1
-#define XCHAL_DEBUGCAUSE_IBREAK_MASK 0x00000002
-#define XCHAL_DEBUGCAUSE_DBREAK_BITS 1
-#define XCHAL_DEBUGCAUSE_DBREAK_NUM 2
-#define XCHAL_DEBUGCAUSE_DBREAK_SHIFT 2
-#define XCHAL_DEBUGCAUSE_DBREAK_MASK 0x00000004
-#define XCHAL_DEBUGCAUSE_BREAK_BITS 1
-#define XCHAL_DEBUGCAUSE_BREAK_NUM 2
-#define XCHAL_DEBUGCAUSE_BREAK_SHIFT 3
-#define XCHAL_DEBUGCAUSE_BREAK_MASK 0x00000008
-#define XCHAL_DEBUGCAUSE_BREAKN_BITS 1
-#define XCHAL_DEBUGCAUSE_BREAKN_NUM 2
-#define XCHAL_DEBUGCAUSE_BREAKN_SHIFT 4
-#define XCHAL_DEBUGCAUSE_BREAKN_MASK 0x00000010
-#define XCHAL_DEBUGCAUSE_DEBUGINT_BITS 1
-#define XCHAL_DEBUGCAUSE_DEBUGINT_NUM 2
-#define XCHAL_DEBUGCAUSE_DEBUGINT_SHIFT 5
-#define XCHAL_DEBUGCAUSE_DEBUGINT_MASK 0x00000020
-
-
-
-
-/*----------------------------------------------------------------------
- TIMERS
- ----------------------------------------------------------------------*/
-
-/*#define XCHAL_HAVE_TIMERS XCHAL_HAVE_CCOUNT*/
-
-
-
-/*----------------------------------------------------------------------
- INTERNAL I/D RAM/ROMs and XLMI
- ----------------------------------------------------------------------*/
-
-#define XCHAL_NUM_IROM XCHAL_NUM_INSTROM /* (DEPRECATED) */
-#define XCHAL_NUM_IRAM XCHAL_NUM_INSTRAM /* (DEPRECATED) */
-#define XCHAL_NUM_DROM XCHAL_NUM_DATAROM /* (DEPRECATED) */
-#define XCHAL_NUM_DRAM XCHAL_NUM_DATARAM /* (DEPRECATED) */
-
-#define XCHAL_IROM0_VADDR XCHAL_INSTROM0_VADDR /* (DEPRECATED) */
-#define XCHAL_IROM0_PADDR XCHAL_INSTROM0_PADDR /* (DEPRECATED) */
-#define XCHAL_IROM0_SIZE XCHAL_INSTROM0_SIZE /* (DEPRECATED) */
-#define XCHAL_IROM1_VADDR XCHAL_INSTROM1_VADDR /* (DEPRECATED) */
-#define XCHAL_IROM1_PADDR XCHAL_INSTROM1_PADDR /* (DEPRECATED) */
-#define XCHAL_IROM1_SIZE XCHAL_INSTROM1_SIZE /* (DEPRECATED) */
-#define XCHAL_IRAM0_VADDR XCHAL_INSTRAM0_VADDR /* (DEPRECATED) */
-#define XCHAL_IRAM0_PADDR XCHAL_INSTRAM0_PADDR /* (DEPRECATED) */
-#define XCHAL_IRAM0_SIZE XCHAL_INSTRAM0_SIZE /* (DEPRECATED) */
-#define XCHAL_IRAM1_VADDR XCHAL_INSTRAM1_VADDR /* (DEPRECATED) */
-#define XCHAL_IRAM1_PADDR XCHAL_INSTRAM1_PADDR /* (DEPRECATED) */
-#define XCHAL_IRAM1_SIZE XCHAL_INSTRAM1_SIZE /* (DEPRECATED) */
-#define XCHAL_DROM0_VADDR XCHAL_DATAROM0_VADDR /* (DEPRECATED) */
-#define XCHAL_DROM0_PADDR XCHAL_DATAROM0_PADDR /* (DEPRECATED) */
-#define XCHAL_DROM0_SIZE XCHAL_DATAROM0_SIZE /* (DEPRECATED) */
-#define XCHAL_DROM1_VADDR XCHAL_DATAROM1_VADDR /* (DEPRECATED) */
-#define XCHAL_DROM1_PADDR XCHAL_DATAROM1_PADDR /* (DEPRECATED) */
-#define XCHAL_DROM1_SIZE XCHAL_DATAROM1_SIZE /* (DEPRECATED) */
-#define XCHAL_DRAM0_VADDR XCHAL_DATARAM0_VADDR /* (DEPRECATED) */
-#define XCHAL_DRAM0_PADDR XCHAL_DATARAM0_PADDR /* (DEPRECATED) */
-#define XCHAL_DRAM0_SIZE XCHAL_DATARAM0_SIZE /* (DEPRECATED) */
-#define XCHAL_DRAM1_VADDR XCHAL_DATARAM1_VADDR /* (DEPRECATED) */
-#define XCHAL_DRAM1_PADDR XCHAL_DATARAM1_PADDR /* (DEPRECATED) */
-#define XCHAL_DRAM1_SIZE XCHAL_DATARAM1_SIZE /* (DEPRECATED) */
-
-
-
-/*----------------------------------------------------------------------
- CACHE
- ----------------------------------------------------------------------*/
-
-
-/* Default PREFCTL value to enable prefetch. */
-#if XCHAL_HW_MIN_VERSION < XTENSA_HWVERSION_RE_2012_0
-#define XCHAL_CACHE_PREFCTL_DEFAULT 0x00044 /* enabled, not aggressive */
-#elif XCHAL_HW_MIN_VERSION < XTENSA_HWVERSION_RF_2014_0
-#define XCHAL_CACHE_PREFCTL_DEFAULT 0x01044 /* + enable prefetch to L1 */
-#elif ((XCHAL_PREFETCH_ENTRIES >= 16) && XCHAL_HAVE_CACHE_BLOCKOPS)
-#define XCHAL_CACHE_PREFCTL_DEFAULT 0x81044 /* 12 entries for block ops */
-#elif ((XCHAL_PREFETCH_ENTRIES >= 8) && XCHAL_HAVE_CACHE_BLOCKOPS)
-#define XCHAL_CACHE_PREFCTL_DEFAULT 0x51044 /* 5 entries for block ops */
-#else
-#define XCHAL_CACHE_PREFCTL_DEFAULT 0x01044 /* 0 entries for block ops */
-#endif
-
-
-/* Max for both I-cache and D-cache (used for general alignment): */
-#if XCHAL_ICACHE_LINESIZE > XCHAL_DCACHE_LINESIZE
-# define XCHAL_CACHE_LINEWIDTH_MAX XCHAL_ICACHE_LINEWIDTH
-# define XCHAL_CACHE_LINESIZE_MAX XCHAL_ICACHE_LINESIZE
-#else
-# define XCHAL_CACHE_LINEWIDTH_MAX XCHAL_DCACHE_LINEWIDTH
-# define XCHAL_CACHE_LINESIZE_MAX XCHAL_DCACHE_LINESIZE
-#endif
-
-#define XCHAL_ICACHE_SETSIZE (1<<XCHAL_ICACHE_SETWIDTH)
-#define XCHAL_DCACHE_SETSIZE (1<<XCHAL_DCACHE_SETWIDTH)
-/* Max for both I and D caches (used for cache-coherency page alignment): */
-#if XCHAL_ICACHE_SETWIDTH > XCHAL_DCACHE_SETWIDTH
-# define XCHAL_CACHE_SETWIDTH_MAX XCHAL_ICACHE_SETWIDTH
-# define XCHAL_CACHE_SETSIZE_MAX XCHAL_ICACHE_SETSIZE
-#else
-# define XCHAL_CACHE_SETWIDTH_MAX XCHAL_DCACHE_SETWIDTH
-# define XCHAL_CACHE_SETSIZE_MAX XCHAL_DCACHE_SETSIZE
-#endif
-
-/* Instruction cache tag bits: */
-#define XCHAL_ICACHE_TAG_V_SHIFT 0
-#define XCHAL_ICACHE_TAG_V 0x1 /* valid bit */
-#if XCHAL_ICACHE_WAYS > 1
-# define XCHAL_ICACHE_TAG_F_SHIFT 1
-# define XCHAL_ICACHE_TAG_F 0x2 /* fill (LRU) bit */
-#else
-# define XCHAL_ICACHE_TAG_F_SHIFT 0
-# define XCHAL_ICACHE_TAG_F 0 /* no fill (LRU) bit */
-#endif
-#if XCHAL_ICACHE_LINE_LOCKABLE
-# define XCHAL_ICACHE_TAG_L_SHIFT (XCHAL_ICACHE_TAG_F_SHIFT+1)
-# define XCHAL_ICACHE_TAG_L (1 << XCHAL_ICACHE_TAG_L_SHIFT) /* lock bit */
-#else
-# define XCHAL_ICACHE_TAG_L_SHIFT XCHAL_ICACHE_TAG_F_SHIFT
-# define XCHAL_ICACHE_TAG_L 0 /* no lock bit */
-#endif
-/* Data cache tag bits: */
-#define XCHAL_DCACHE_TAG_V_SHIFT 0
-#define XCHAL_DCACHE_TAG_V 0x1 /* valid bit */
-#if XCHAL_DCACHE_WAYS > 1
-# define XCHAL_DCACHE_TAG_F_SHIFT 1
-# define XCHAL_DCACHE_TAG_F 0x2 /* fill (LRU) bit */
-#else
-# define XCHAL_DCACHE_TAG_F_SHIFT 0
-# define XCHAL_DCACHE_TAG_F 0 /* no fill (LRU) bit */
-#endif
-#if XCHAL_DCACHE_IS_WRITEBACK
-# define XCHAL_DCACHE_TAG_D_SHIFT (XCHAL_DCACHE_TAG_F_SHIFT+1)
-# define XCHAL_DCACHE_TAG_D (1 << XCHAL_DCACHE_TAG_D_SHIFT) /* dirty bit */
-#else
-# define XCHAL_DCACHE_TAG_D_SHIFT XCHAL_DCACHE_TAG_F_SHIFT
-# define XCHAL_DCACHE_TAG_D 0 /* no dirty bit */
-#endif
-#if XCHAL_DCACHE_LINE_LOCKABLE
-# define XCHAL_DCACHE_TAG_L_SHIFT (XCHAL_DCACHE_TAG_D_SHIFT+1)
-# define XCHAL_DCACHE_TAG_L (1 << XCHAL_DCACHE_TAG_L_SHIFT) /* lock bit */
-#else
-# define XCHAL_DCACHE_TAG_L_SHIFT XCHAL_DCACHE_TAG_D_SHIFT
-# define XCHAL_DCACHE_TAG_L 0 /* no lock bit */
-#endif
-
-/* Whether MEMCTL register has anything useful */
-#define XCHAL_USE_MEMCTL (((XCHAL_LOOP_BUFFER_SIZE > 0) || \
- XCHAL_DCACHE_IS_COHERENT || \
- XCHAL_HAVE_ICACHE_DYN_WAYS || \
- XCHAL_HAVE_DCACHE_DYN_WAYS) && \
- (XCHAL_HW_MIN_VERSION >= XTENSA_HWVERSION_RE_2012_0))
-
-#if XCHAL_DCACHE_IS_COHERENT
-#define _MEMCTL_SNOOP_EN 0x02 /* Enable snoop */
-#else
-#define _MEMCTL_SNOOP_EN 0x00 /* Don't enable snoop */
-#endif
-
-#if (XCHAL_LOOP_BUFFER_SIZE == 0) || XCHAL_ERRATUM_453
-#define _MEMCTL_L0IBUF_EN 0x00 /* No loop buffer or don't enable */
-#else
-#define _MEMCTL_L0IBUF_EN 0x01 /* Enable loop buffer */
-#endif
-
-/* Default MEMCTL values: */
-#if XCHAL_HAVE_ICACHE_DYN_WAYS || XCHAL_HAVE_DCACHE_DYN_WAYS
-#define XCHAL_CACHE_MEMCTL_DEFAULT (0xFFFFFF00 | _MEMCTL_L0IBUF_EN)
-#else
-#define XCHAL_CACHE_MEMCTL_DEFAULT (0x00000000 | _MEMCTL_L0IBUF_EN)
-#endif
-
-#define XCHAL_SNOOP_LB_MEMCTL_DEFAULT (_MEMCTL_SNOOP_EN | _MEMCTL_L0IBUF_EN)
-
-
-/*----------------------------------------------------------------------
- MMU
- ----------------------------------------------------------------------*/
-
-/* See <xtensa/config/core-matmap.h> for more details. */
-
-/* Has different semantic in open source headers (where it means HAVE_PTP_MMU),
- so comment out starting with RB-2008.3 release; later, might get
- get reintroduced as a synonym for XCHAL_HAVE_PTP_MMU instead: */
-/*#define XCHAL_HAVE_MMU XCHAL_HAVE_TLBS*/ /* (DEPRECATED; use XCHAL_HAVE_TLBS instead) */
-
-/* Indexing macros: */
-#define _XCHAL_ITLB_SET(n,_what) XCHAL_ITLB_SET ## n ## _what
-#define XCHAL_ITLB_SET(n,what) _XCHAL_ITLB_SET(n, _ ## what )
-#define _XCHAL_ITLB_SET_E(n,i,_what) XCHAL_ITLB_SET ## n ## _E ## i ## _what
-#define XCHAL_ITLB_SET_E(n,i,what) _XCHAL_ITLB_SET_E(n,i, _ ## what )
-#define _XCHAL_DTLB_SET(n,_what) XCHAL_DTLB_SET ## n ## _what
-#define XCHAL_DTLB_SET(n,what) _XCHAL_DTLB_SET(n, _ ## what )
-#define _XCHAL_DTLB_SET_E(n,i,_what) XCHAL_DTLB_SET ## n ## _E ## i ## _what
-#define XCHAL_DTLB_SET_E(n,i,what) _XCHAL_DTLB_SET_E(n,i, _ ## what )
-/*
- * Example use: XCHAL_ITLB_SET(XCHAL_ITLB_ARF_SET0,ENTRIES)
- * to get the value of XCHAL_ITLB_SET<n>_ENTRIES where <n> is the first auto-refill set.
- */
-
-/* Number of entries per autorefill way: */
-#define XCHAL_ITLB_ARF_ENTRIES (1<<XCHAL_ITLB_ARF_ENTRIES_LOG2)
-#define XCHAL_DTLB_ARF_ENTRIES (1<<XCHAL_DTLB_ARF_ENTRIES_LOG2)
-
-/*
- * Determine whether we have a full MMU (with Page Table and Protection)
- * usable for an MMU-based OS:
- */
-#if 0
-#if XCHAL_HAVE_TLBS && !XCHAL_HAVE_SPANNING_WAY && XCHAL_ITLB_ARF_WAYS > 0 && XCHAL_DTLB_ARF_WAYS > 0 && XCHAL_MMU_RINGS >= 2
-# define XCHAL_HAVE_PTP_MMU 1 /* have full MMU (with page table [autorefill] and protection) */
-#else
-# define XCHAL_HAVE_PTP_MMU 0 /* don't have full MMU */
-#endif
-#endif
-
-/*
- * For full MMUs, report kernel RAM segment and kernel I/O segment static page mappings:
- */
-#if XCHAL_HAVE_PTP_MMU && !XCHAL_HAVE_SPANNING_WAY
-#define XCHAL_KSEG_CACHED_VADDR 0xD0000000 /* virt.addr of kernel RAM cached static map */
-#define XCHAL_KSEG_CACHED_PADDR 0x00000000 /* phys.addr of kseg_cached */
-#define XCHAL_KSEG_CACHED_SIZE 0x08000000 /* size in bytes of kseg_cached (assumed power of 2!!!) */
-#define XCHAL_KSEG_BYPASS_VADDR 0xD8000000 /* virt.addr of kernel RAM bypass (uncached) static map */
-#define XCHAL_KSEG_BYPASS_PADDR 0x00000000 /* phys.addr of kseg_bypass */
-#define XCHAL_KSEG_BYPASS_SIZE 0x08000000 /* size in bytes of kseg_bypass (assumed power of 2!!!) */
-
-#define XCHAL_KIO_CACHED_VADDR 0xE0000000 /* virt.addr of kernel I/O cached static map */
-#define XCHAL_KIO_CACHED_PADDR 0xF0000000 /* phys.addr of kio_cached */
-#define XCHAL_KIO_CACHED_SIZE 0x10000000 /* size in bytes of kio_cached (assumed power of 2!!!) */
-#define XCHAL_KIO_BYPASS_VADDR 0xF0000000 /* virt.addr of kernel I/O bypass (uncached) static map */
-#define XCHAL_KIO_BYPASS_PADDR 0xF0000000 /* phys.addr of kio_bypass */
-#define XCHAL_KIO_BYPASS_SIZE 0x10000000 /* size in bytes of kio_bypass (assumed power of 2!!!) */
-
-#define XCHAL_SEG_MAPPABLE_VADDR 0x00000000 /* start of largest non-static-mapped virtual addr area */
-#define XCHAL_SEG_MAPPABLE_SIZE 0xD0000000 /* size in bytes of " */
-/* define XCHAL_SEG_MAPPABLE2_xxx if more areas present, sorted in order of descending size. */
-#endif
-
-
-/*----------------------------------------------------------------------
- MISC
- ----------------------------------------------------------------------*/
-
-/* Data alignment required if used for instructions: */
-#if XCHAL_INST_FETCH_WIDTH > XCHAL_DATA_WIDTH
-# define XCHAL_ALIGN_MAX XCHAL_INST_FETCH_WIDTH
-#else
-# define XCHAL_ALIGN_MAX XCHAL_DATA_WIDTH
-#endif
-
-/*
- * Names kept for backward compatibility.
- * (Here "RELEASE" is now a misnomer; these are product *versions*, not the releases
- * under which they are released. In the T10##.# era there was no distinction.)
- */
-#define XCHAL_HW_RELEASE_MAJOR XCHAL_HW_VERSION_MAJOR
-#define XCHAL_HW_RELEASE_MINOR XCHAL_HW_VERSION_MINOR
-#define XCHAL_HW_RELEASE_NAME XCHAL_HW_VERSION_NAME
-
-
-
-
-/*----------------------------------------------------------------------
- COPROCESSORS and EXTRA STATE
- ----------------------------------------------------------------------*/
-
-#define XCHAL_EXTRA_SA_SIZE XCHAL_NCP_SA_SIZE
-#define XCHAL_EXTRA_SA_ALIGN XCHAL_NCP_SA_ALIGN
-#define XCHAL_CPEXTRA_SA_SIZE XCHAL_TOTAL_SA_SIZE
-#define XCHAL_CPEXTRA_SA_ALIGN XCHAL_TOTAL_SA_ALIGN
-
-#if defined (_ASMLANGUAGE) || defined (__ASSEMBLER__)
-
- /* Invoked at start of save area load/store sequence macro to setup macro
- * internal offsets. Not usually invoked directly.
- * continue 0 for 1st sequence, 1 for subsequent consecutive ones.
- * totofs offset from original ptr to next load/store location.
- */
- .macro xchal_sa_start continue totofs
- .ifeq \continue
- .set .Lxchal_pofs_, 0 /* offset from original ptr to current \ptr */
- .set .Lxchal_ofs_, 0 /* offset from current \ptr to next load/store location */
- .endif
- .if \totofs + 1 /* if totofs specified (not -1) */
- .set .Lxchal_ofs_, \totofs - .Lxchal_pofs_ /* specific offset from original ptr */
- .endif
- .endm
-
- /* Align portion of save area and bring ptr in range if necessary.
- * Used by save area load/store sequences. Not usually invoked directly.
- * Allows combining multiple (sub-)sequences arbitrarily.
- * ptr pointer to save area (may be off, see .Lxchal_pofs_)
- * minofs,maxofs range of offset from cur ptr to next load/store loc;
- * minofs <= 0 <= maxofs (0 must always be valid offset)
- * range must be within +/- 30kB or so.
- * ofsalign alignment granularity of minofs .. maxofs (pow of 2)
- * (restriction on offset from ptr to next load/store loc)
- * totalign align from orig ptr to next load/store loc (pow of 2)
- */
- .macro xchal_sa_align ptr minofs maxofs ofsalign totalign
- /* First align where we start accessing the next register
- * per \totalign relative to original ptr (i.e. start of the save area):
- */
- .set .Lxchal_ofs_, ((.Lxchal_pofs_ + .Lxchal_ofs_ + \totalign - 1) & -\totalign) - .Lxchal_pofs_
- /* If necessary, adjust \ptr to bring .Lxchal_ofs_ in acceptable range: */
- .if (((\maxofs) - .Lxchal_ofs_) & 0xC0000000) | ((.Lxchal_ofs_ - (\minofs)) & 0xC0000000) | (.Lxchal_ofs_ & (\ofsalign-1))
- .set .Ligmask, 0xFFFFFFFF /* TODO: optimize to addmi, per aligns and .Lxchal_ofs_ */
- addi \ptr, \ptr, (.Lxchal_ofs_ & .Ligmask)
- .set .Lxchal_pofs_, .Lxchal_pofs_ + (.Lxchal_ofs_ & .Ligmask)
- .set .Lxchal_ofs_, (.Lxchal_ofs_ & ~.Ligmask)
- .endif
- .endm
- /*
- * We could optimize for addi to expand to only addmi instead of
- * "addmi;addi", where possible. Here's a partial example how:
- * .set .Lmaxmask, -(\ofsalign) & -(\totalign)
- * .if (((\maxofs) + ~.Lmaxmask + 1) & 0xFFFFFF00) && ((.Lxchal_ofs_ & ~.Lmaxmask) == 0)
- * .set .Ligmask, 0xFFFFFF00
- * .elif ... ditto for negative ofs range ...
- * .set .Ligmask, 0xFFFFFF00
- * .set ... adjust per offset ...
- * .else
- * .set .Ligmask, 0xFFFFFFFF
- * .endif
- */
-
- /* Invoke this after xchal_XXX_{load,store} macros to restore \ptr. */
- .macro xchal_sa_ptr_restore ptr
- .if .Lxchal_pofs_
- addi \ptr, \ptr, - .Lxchal_pofs_
- .set .Lxchal_ofs_, .Lxchal_ofs_ + .Lxchal_pofs_
- .set .Lxchal_pofs_, 0
- .endif
- .endm
-
- /*
- * Use as eg:
- * xchal_atmps_store a1, SOMEOFS, XCHAL_SA_NUM_ATMPS, a4, a5
- * xchal_ncp_load a2, a0,a3,a4,a5
- * xchal_atmps_load a1, SOMEOFS, XCHAL_SA_NUM_ATMPS, a4, a5
- *
- * Specify only the ARs you *haven't* saved/restored already, up to 4.
- * They *must* be the *last* ARs (in same order) specified to save area
- * load/store sequences. In the example above, a0 and a3 were already
- * saved/restored and unused (thus available) but a4 and a5 were not.
- */
-#define xchal_atmps_store xchal_atmps_loadstore s32i,
-#define xchal_atmps_load xchal_atmps_loadstore l32i,
- .macro xchal_atmps_loadstore inst ptr offset nreq aa=0 ab=0 ac=0 ad=0
- .set .Lnsaved_, 0
- .irp reg,\aa,\ab,\ac,\ad
- .ifeq 0x\reg ; .set .Lnsaved_,.Lnsaved_+1 ; .endif
- .endr
- .set .Laofs_, 0
- .irp reg,\aa,\ab,\ac,\ad
- .ifgt (\nreq)-.Lnsaved_
- \inst \reg, \ptr, .Laofs_+\offset
- .set .Laofs_,.Laofs_+4
- .set .Lnsaved_,.Lnsaved_+1
- .endif
- .endr
- .endm
-
-/*#define xchal_ncp_load_a2 xchal_ncp_load a2,a3,a4,a5,a6*/
-/*#define xchal_ncp_store_a2 xchal_ncp_store a2,a3,a4,a5,a6*/
-#define xchal_extratie_load xchal_ncptie_load
-#define xchal_extratie_store xchal_ncptie_store
-#define xchal_extratie_load_a2 xchal_ncptie_load a2,a3,a4,a5,a6
-#define xchal_extratie_store_a2 xchal_ncptie_store a2,a3,a4,a5,a6
-#define xchal_extra_load xchal_ncp_load
-#define xchal_extra_store xchal_ncp_store
-#define xchal_extra_load_a2 xchal_ncp_load a2,a3,a4,a5,a6
-#define xchal_extra_store_a2 xchal_ncp_store a2,a3,a4,a5,a6
-#define xchal_extra_load_funcbody xchal_ncp_load a2,a3,a4,a5,a6
-#define xchal_extra_store_funcbody xchal_ncp_store a2,a3,a4,a5,a6
-#define xchal_cp0_store_a2 xchal_cp0_store a2,a3,a4,a5,a6
-#define xchal_cp0_load_a2 xchal_cp0_load a2,a3,a4,a5,a6
-#define xchal_cp1_store_a2 xchal_cp1_store a2,a3,a4,a5,a6
-#define xchal_cp1_load_a2 xchal_cp1_load a2,a3,a4,a5,a6
-#define xchal_cp2_store_a2 xchal_cp2_store a2,a3,a4,a5,a6
-#define xchal_cp2_load_a2 xchal_cp2_load a2,a3,a4,a5,a6
-#define xchal_cp3_store_a2 xchal_cp3_store a2,a3,a4,a5,a6
-#define xchal_cp3_load_a2 xchal_cp3_load a2,a3,a4,a5,a6
-#define xchal_cp4_store_a2 xchal_cp4_store a2,a3,a4,a5,a6
-#define xchal_cp4_load_a2 xchal_cp4_load a2,a3,a4,a5,a6
-#define xchal_cp5_store_a2 xchal_cp5_store a2,a3,a4,a5,a6
-#define xchal_cp5_load_a2 xchal_cp5_load a2,a3,a4,a5,a6
-#define xchal_cp6_store_a2 xchal_cp6_store a2,a3,a4,a5,a6
-#define xchal_cp6_load_a2 xchal_cp6_load a2,a3,a4,a5,a6
-#define xchal_cp7_store_a2 xchal_cp7_store a2,a3,a4,a5,a6
-#define xchal_cp7_load_a2 xchal_cp7_load a2,a3,a4,a5,a6
-
-/* Empty placeholder macros for undefined coprocessors: */
-#if (XCHAL_CP_MASK & ~XCHAL_CP_PORT_MASK) == 0
-# if XCHAL_CP0_SA_SIZE == 0
- .macro xchal_cp0_store p a b c d continue=0 ofs=-1 select=-1 ; .endm
- .macro xchal_cp0_load p a b c d continue=0 ofs=-1 select=-1 ; .endm
-# endif
-# if XCHAL_CP1_SA_SIZE == 0
- .macro xchal_cp1_store p a b c d continue=0 ofs=-1 select=-1 ; .endm
- .macro xchal_cp1_load p a b c d continue=0 ofs=-1 select=-1 ; .endm
-# endif
-# if XCHAL_CP2_SA_SIZE == 0
- .macro xchal_cp2_store p a b c d continue=0 ofs=-1 select=-1 ; .endm
- .macro xchal_cp2_load p a b c d continue=0 ofs=-1 select=-1 ; .endm
-# endif
-# if XCHAL_CP3_SA_SIZE == 0
- .macro xchal_cp3_store p a b c d continue=0 ofs=-1 select=-1 ; .endm
- .macro xchal_cp3_load p a b c d continue=0 ofs=-1 select=-1 ; .endm
-# endif
-# if XCHAL_CP4_SA_SIZE == 0
- .macro xchal_cp4_store p a b c d continue=0 ofs=-1 select=-1 ; .endm
- .macro xchal_cp4_load p a b c d continue=0 ofs=-1 select=-1 ; .endm
-# endif
-# if XCHAL_CP5_SA_SIZE == 0
- .macro xchal_cp5_store p a b c d continue=0 ofs=-1 select=-1 ; .endm
- .macro xchal_cp5_load p a b c d continue=0 ofs=-1 select=-1 ; .endm
-# endif
-# if XCHAL_CP6_SA_SIZE == 0
- .macro xchal_cp6_store p a b c d continue=0 ofs=-1 select=-1 ; .endm
- .macro xchal_cp6_load p a b c d continue=0 ofs=-1 select=-1 ; .endm
-# endif
-# if XCHAL_CP7_SA_SIZE == 0
- .macro xchal_cp7_store p a b c d continue=0 ofs=-1 select=-1 ; .endm
- .macro xchal_cp7_load p a b c d continue=0 ofs=-1 select=-1 ; .endm
-# endif
-#endif
-
- /********************
- * Macros to create functions that save and restore the state of *any* TIE
- * coprocessor (by dynamic index).
- */
-
- /*
- * Macro that expands to the body of a function
- * that stores the selected coprocessor's state (registers etc).
- * Entry: a2 = ptr to save area in which to save cp state
- * a3 = coprocessor number
- * Exit: any register a2-a15 (?) may have been clobbered.
- */
- .macro xchal_cpi_store_funcbody
-#if (XCHAL_CP_MASK & ~XCHAL_CP_PORT_MASK)
-# if XCHAL_CP0_SA_SIZE
- bnez a3, 99f
- xchal_cp0_store_a2
- j 90f
-99:
-# endif
-# if XCHAL_CP1_SA_SIZE
- bnei a3, 1, 99f
- xchal_cp1_store_a2
- j 90f
-99:
-# endif
-# if XCHAL_CP2_SA_SIZE
- bnei a3, 2, 99f
- xchal_cp2_store_a2
- j 90f
-99:
-# endif
-# if XCHAL_CP3_SA_SIZE
- bnei a3, 3, 99f
- xchal_cp3_store_a2
- j 90f
-99:
-# endif
-# if XCHAL_CP4_SA_SIZE
- bnei a3, 4, 99f
- xchal_cp4_store_a2
- j 90f
-99:
-# endif
-# if XCHAL_CP5_SA_SIZE
- bnei a3, 5, 99f
- xchal_cp5_store_a2
- j 90f
-99:
-# endif
-# if XCHAL_CP6_SA_SIZE
- bnei a3, 6, 99f
- xchal_cp6_store_a2
- j 90f
-99:
-# endif
-# if XCHAL_CP7_SA_SIZE
- bnei a3, 7, 99f
- xchal_cp7_store_a2
- j 90f
-99:
-# endif
-90:
-#endif
- .endm
-
- /*
- * Macro that expands to the body of a function
- * that loads the selected coprocessor's state (registers etc).
- * Entry: a2 = ptr to save area from which to restore cp state
- * a3 = coprocessor number
- * Exit: any register a2-a15 (?) may have been clobbered.
- */
- .macro xchal_cpi_load_funcbody
-#if (XCHAL_CP_MASK & ~XCHAL_CP_PORT_MASK)
-# if XCHAL_CP0_SA_SIZE
- bnez a3, 99f
- xchal_cp0_load_a2
- j 90f
-99:
-# endif
-# if XCHAL_CP1_SA_SIZE
- bnei a3, 1, 99f
- xchal_cp1_load_a2
- j 90f
-99:
-# endif
-# if XCHAL_CP2_SA_SIZE
- bnei a3, 2, 99f
- xchal_cp2_load_a2
- j 90f
-99:
-# endif
-# if XCHAL_CP3_SA_SIZE
- bnei a3, 3, 99f
- xchal_cp3_load_a2
- j 90f
-99:
-# endif
-# if XCHAL_CP4_SA_SIZE
- bnei a3, 4, 99f
- xchal_cp4_load_a2
- j 90f
-99:
-# endif
-# if XCHAL_CP5_SA_SIZE
- bnei a3, 5, 99f
- xchal_cp5_load_a2
- j 90f
-99:
-# endif
-# if XCHAL_CP6_SA_SIZE
- bnei a3, 6, 99f
- xchal_cp6_load_a2
- j 90f
-99:
-# endif
-# if XCHAL_CP7_SA_SIZE
- bnei a3, 7, 99f
- xchal_cp7_load_a2
- j 90f
-99:
-# endif
-90:
-#endif
- .endm
-
-#endif /*_ASMLANGUAGE or __ASSEMBLER__*/
-
-
-/* Other default macros for undefined coprocessors: */
-#ifndef XCHAL_CP0_NAME
-# define XCHAL_CP0_NAME 0
-# define XCHAL_CP0_SA_CONTENTS_LIBDB_NUM 0
-# define XCHAL_CP0_SA_CONTENTS_LIBDB /* empty */
-#endif
-#ifndef XCHAL_CP1_NAME
-# define XCHAL_CP1_NAME 0
-# define XCHAL_CP1_SA_CONTENTS_LIBDB_NUM 0
-# define XCHAL_CP1_SA_CONTENTS_LIBDB /* empty */
-#endif
-#ifndef XCHAL_CP2_NAME
-# define XCHAL_CP2_NAME 0
-# define XCHAL_CP2_SA_CONTENTS_LIBDB_NUM 0
-# define XCHAL_CP2_SA_CONTENTS_LIBDB /* empty */
-#endif
-#ifndef XCHAL_CP3_NAME
-# define XCHAL_CP3_NAME 0
-# define XCHAL_CP3_SA_CONTENTS_LIBDB_NUM 0
-# define XCHAL_CP3_SA_CONTENTS_LIBDB /* empty */
-#endif
-#ifndef XCHAL_CP4_NAME
-# define XCHAL_CP4_NAME 0
-# define XCHAL_CP4_SA_CONTENTS_LIBDB_NUM 0
-# define XCHAL_CP4_SA_CONTENTS_LIBDB /* empty */
-#endif
-#ifndef XCHAL_CP5_NAME
-# define XCHAL_CP5_NAME 0
-# define XCHAL_CP5_SA_CONTENTS_LIBDB_NUM 0
-# define XCHAL_CP5_SA_CONTENTS_LIBDB /* empty */
-#endif
-#ifndef XCHAL_CP6_NAME
-# define XCHAL_CP6_NAME 0
-# define XCHAL_CP6_SA_CONTENTS_LIBDB_NUM 0
-# define XCHAL_CP6_SA_CONTENTS_LIBDB /* empty */
-#endif
-#ifndef XCHAL_CP7_NAME
-# define XCHAL_CP7_NAME 0
-# define XCHAL_CP7_SA_CONTENTS_LIBDB_NUM 0
-# define XCHAL_CP7_SA_CONTENTS_LIBDB /* empty */
-#endif
-
-#if XCHAL_CP_MASK == 0
-/* Filler info for unassigned coprocessors, to simplify arrays etc: */
-#define XCHAL_CP0_SA_SIZE 0
-#define XCHAL_CP0_SA_ALIGN 1
-#define XCHAL_CP1_SA_SIZE 0
-#define XCHAL_CP1_SA_ALIGN 1
-#define XCHAL_CP2_SA_SIZE 0
-#define XCHAL_CP2_SA_ALIGN 1
-#define XCHAL_CP3_SA_SIZE 0
-#define XCHAL_CP3_SA_ALIGN 1
-#define XCHAL_CP4_SA_SIZE 0
-#define XCHAL_CP4_SA_ALIGN 1
-#define XCHAL_CP5_SA_SIZE 0
-#define XCHAL_CP5_SA_ALIGN 1
-#define XCHAL_CP6_SA_SIZE 0
-#define XCHAL_CP6_SA_ALIGN 1
-#define XCHAL_CP7_SA_SIZE 0
-#define XCHAL_CP7_SA_ALIGN 1
-#endif
-
-
-/* Indexing macros: */
-#define _XCHAL_CP_SA_SIZE(n) XCHAL_CP ## n ## _SA_SIZE
-#define XCHAL_CP_SA_SIZE(n) _XCHAL_CP_SA_SIZE(n) /* n = 0 .. 7 */
-#define _XCHAL_CP_SA_ALIGN(n) XCHAL_CP ## n ## _SA_ALIGN
-#define XCHAL_CP_SA_ALIGN(n) _XCHAL_CP_SA_ALIGN(n) /* n = 0 .. 7 */
-
-#define XCHAL_CPEXTRA_SA_SIZE_TOR2 XCHAL_CPEXTRA_SA_SIZE /* Tor2Beta only - do not use */
-
-/* Link-time HAL global variables that report coprocessor numbers by name
- (names are case-preserved from the original TIE): */
-#if !defined(_ASMLANGUAGE) && !defined(_NOCLANGUAGE) && !defined(__ASSEMBLER__)
-# define _XCJOIN(a,b) a ## b
-# define XCJOIN(a,b) _XCJOIN(a,b)
-# ifdef XCHAL_CP0_NAME
-extern const unsigned char XCJOIN(Xthal_cp_id_,XCHAL_CP0_IDENT);
-extern const unsigned int XCJOIN(Xthal_cp_mask_,XCHAL_CP0_IDENT);
-# endif
-# ifdef XCHAL_CP1_NAME
-extern const unsigned char XCJOIN(Xthal_cp_id_,XCHAL_CP1_IDENT);
-extern const unsigned int XCJOIN(Xthal_cp_mask_,XCHAL_CP1_IDENT);
-# endif
-# ifdef XCHAL_CP2_NAME
-extern const unsigned char XCJOIN(Xthal_cp_id_,XCHAL_CP2_IDENT);
-extern const unsigned int XCJOIN(Xthal_cp_mask_,XCHAL_CP2_IDENT);
-# endif
-# ifdef XCHAL_CP3_NAME
-extern const unsigned char XCJOIN(Xthal_cp_id_,XCHAL_CP3_IDENT);
-extern const unsigned int XCJOIN(Xthal_cp_mask_,XCHAL_CP3_IDENT);
-# endif
-# ifdef XCHAL_CP4_NAME
-extern const unsigned char XCJOIN(Xthal_cp_id_,XCHAL_CP4_IDENT);
-extern const unsigned int XCJOIN(Xthal_cp_mask_,XCHAL_CP4_IDENT);
-# endif
-# ifdef XCHAL_CP5_NAME
-extern const unsigned char XCJOIN(Xthal_cp_id_,XCHAL_CP5_IDENT);
-extern const unsigned int XCJOIN(Xthal_cp_mask_,XCHAL_CP5_IDENT);
-# endif
-# ifdef XCHAL_CP6_NAME
-extern const unsigned char XCJOIN(Xthal_cp_id_,XCHAL_CP6_IDENT);
-extern const unsigned int XCJOIN(Xthal_cp_mask_,XCHAL_CP6_IDENT);
-# endif
-# ifdef XCHAL_CP7_NAME
-extern const unsigned char XCJOIN(Xthal_cp_id_,XCHAL_CP7_IDENT);
-extern const unsigned int XCJOIN(Xthal_cp_mask_,XCHAL_CP7_IDENT);
-# endif
-#endif
-
-
-
-
-/*----------------------------------------------------------------------
- DERIVED
- ----------------------------------------------------------------------*/
-
-#if XCHAL_HAVE_BE
-#define XCHAL_INST_ILLN 0xD60F /* 2-byte illegal instruction, msb-first */
-#define XCHAL_INST_ILLN_BYTE0 0xD6 /* 2-byte illegal instruction, 1st byte */
-#define XCHAL_INST_ILLN_BYTE1 0x0F /* 2-byte illegal instruction, 2nd byte */
-#else
-#define XCHAL_INST_ILLN 0xF06D /* 2-byte illegal instruction, lsb-first */
-#define XCHAL_INST_ILLN_BYTE0 0x6D /* 2-byte illegal instruction, 1st byte */
-#define XCHAL_INST_ILLN_BYTE1 0xF0 /* 2-byte illegal instruction, 2nd byte */
-#endif
-/* Belongs in xtensa/hal.h: */
-#define XTHAL_INST_ILL 0x000000 /* 3-byte illegal instruction */
-
-
-/*
- * Because information as to exactly which hardware version is targeted
- * by a given software build is not always available, compile-time HAL
- * Hardware-Release "_AT" macros are fuzzy (return 0, 1, or XCHAL_MAYBE):
- * (Here "RELEASE" is now a misnomer; these are product *versions*, not the releases
- * under which they are released. In the T10##.# era there was no distinction.)
- */
-#if XCHAL_HW_CONFIGID_RELIABLE
-# define XCHAL_HW_RELEASE_AT_OR_BELOW(major,minor) (XTHAL_REL_LE( XCHAL_HW_VERSION_MAJOR,XCHAL_HW_VERSION_MINOR, major,minor ) ? 1 : 0)
-# define XCHAL_HW_RELEASE_AT_OR_ABOVE(major,minor) (XTHAL_REL_GE( XCHAL_HW_VERSION_MAJOR,XCHAL_HW_VERSION_MINOR, major,minor ) ? 1 : 0)
-# define XCHAL_HW_RELEASE_AT(major,minor) (XTHAL_REL_EQ( XCHAL_HW_VERSION_MAJOR,XCHAL_HW_VERSION_MINOR, major,minor ) ? 1 : 0)
-# define XCHAL_HW_RELEASE_MAJOR_AT(major) ((XCHAL_HW_VERSION_MAJOR == (major)) ? 1 : 0)
-#else
-# define XCHAL_HW_RELEASE_AT_OR_BELOW(major,minor) ( ((major) < 1040 && XCHAL_HAVE_XEA2) ? 0 \
- : ((major) > 1050 && XCHAL_HAVE_XEA1) ? 1 \
- : XTHAL_MAYBE )
-# define XCHAL_HW_RELEASE_AT_OR_ABOVE(major,minor) ( ((major) >= 2000 && XCHAL_HAVE_XEA1) ? 0 \
- : (XTHAL_REL_LE(major,minor, 1040,0) && XCHAL_HAVE_XEA2) ? 1 \
- : XTHAL_MAYBE )
-# define XCHAL_HW_RELEASE_AT(major,minor) ( (((major) < 1040 && XCHAL_HAVE_XEA2) || \
- ((major) >= 2000 && XCHAL_HAVE_XEA1)) ? 0 : XTHAL_MAYBE)
-# define XCHAL_HW_RELEASE_MAJOR_AT(major) XCHAL_HW_RELEASE_AT(major,0)
-#endif
-
-
-#endif /*XTENSA_CONFIG_CORE_H*/
-
diff --git a/src/arch/xtensa/include/xtensa/core-macros.h b/src/arch/xtensa/include/xtensa/core-macros.h
deleted file mode 100644
index 8b8a16b..0000000
--- a/src/arch/xtensa/include/xtensa/core-macros.h
+++ /dev/null
@@ -1,506 +0,0 @@
-/*
- * xtensa/core-macros.h -- C specific definitions
- * that depend on CORE configuration
- */
-
-/*
- * Copyright (c) 2012 Tensilica Inc.
- *
- * Permission is hereby granted, free of charge, to any person obtaining
- * a copy of this software and associated documentation files (the
- * "Software"), to deal in the Software without restriction, including
- * without limitation the rights to use, copy, modify, merge, publish,
- * distribute, sublicense, and/or sell copies of the Software, and to
- * permit persons to whom the Software is furnished to do so, subject to
- * the following conditions:
- *
- * The above copyright notice and this permission notice shall be included
- * in all copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
- * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
- * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
- * IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY
- * CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
- * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
- * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
- */
-
-#ifndef XTENSA_CACHE_H
-#define XTENSA_CACHE_H
-
-#include <xtensa/config/core.h>
-
-/* Only define things for C code. */
-#if !defined(_ASMLANGUAGE) && !defined(_NOCLANGUAGE) && !defined(__ASSEMBLER__)
-
-
-
-/*************************** CACHE ***************************/
-
-/* All the macros are in the lower case now and some of them
- * share the name with the existing functions from hal.h.
- * Including this header file will define XTHAL_USE_CACHE_MACROS
- * which directs hal.h not to use the functions.
- */
-
-/*
- * Single-cache-line operations in C-callable inline assembly.
- * Essentially macro versions (uppercase) of:
- *
- * xthal_icache_line_invalidate(void *addr);
- * xthal_icache_line_lock(void *addr);
- * xthal_icache_line_unlock(void *addr);
- * xthal_icache_sync(void);
- *
- * NOTE: unlike the above functions, the following macros do NOT
- * execute the xthal_icache_sync() as part of each line operation.
- * This sync must be called explicitly by the caller. This is to
- * allow better optimization when operating on more than one line.
- *
- * xthal_dcache_line_invalidate(void *addr);
- * xthal_dcache_line_writeback(void *addr);
- * xthal_dcache_line_writeback_inv(void *addr);
- * xthal_dcache_line_lock(void *addr);
- * xthal_dcache_line_unlock(void *addr);
- * xthal_dcache_sync(void);
- * xthal_dcache_line_prefetch_for_write(void *addr);
- * xthal_dcache_line_prefetch_for_read(void *addr);
- *
- * All are made memory-barriers, given that's how they're typically used
- * (ops operate on a whole line, so clobbers all memory not just *addr).
- *
- * NOTE: All the block block cache ops and line prefetches are implemented
- * using intrinsics so they are better optimized regarding memory barriers etc.
- *
- * All block downgrade functions exist in two forms: with and without
- * the 'max' parameter: This parameter allows compiler to optimize
- * the functions whenever the parameter is smaller than the cache size.
- *
- * xthal_dcache_block_invalidate(void *addr, unsigned size);
- * xthal_dcache_block_writeback(void *addr, unsigned size);
- * xthal_dcache_block_writeback_inv(void *addr, unsigned size);
- * xthal_dcache_block_invalidate_max(void *addr, unsigned size, unsigned max);
- * xthal_dcache_block_writeback_max(void *addr, unsigned size, unsigned max);
- * xthal_dcache_block_writeback_inv_max(void *addr, unsigned size, unsigned max);
- *
- * xthal_dcache_block_prefetch_for_read(void *addr, unsigned size);
- * xthal_dcache_block_prefetch_for_write(void *addr, unsigned size);
- * xthal_dcache_block_prefetch_modify(void *addr, unsigned size);
- * xthal_dcache_block_prefetch_read_write(void *addr, unsigned size);
- * xthal_dcache_block_prefetch_for_read_grp(void *addr, unsigned size);
- * xthal_dcache_block_prefetch_for_write_grp(void *addr, unsigned size);
- * xthal_dcache_block_prefetch_modify_grp(void *addr, unsigned size);
- * xthal_dcache_block_prefetch_read_write_grp(void *addr, unsigned size)
- *
- * xthal_dcache_block_wait();
- * xthal_dcache_block_required_wait();
- * xthal_dcache_block_abort();
- * xthal_dcache_block_prefetch_end();
- * xthal_dcache_block_newgrp();
- */
-
-/*** INSTRUCTION CACHE ***/
-
-#define XTHAL_USE_CACHE_MACROS
-
-#if XCHAL_ICACHE_SIZE > 0
-# define xthal_icache_line_invalidate(addr) do { void *__a = (void*)(addr); \
- __asm__ __volatile__("ihi %0, 0" :: "a"(__a) : "memory"); \
- } while(0)
-#else
-# define xthal_icache_line_invalidate(addr) do {/*nothing*/} while(0)
-#endif
-
-#if XCHAL_ICACHE_SIZE > 0 && XCHAL_ICACHE_LINE_LOCKABLE
-# define xthal_icache_line_lock(addr) do { void *__a = (void*)(addr); \
- __asm__ __volatile__("ipfl %0, 0" :: "a"(__a) : "memory"); \
- } while(0)
-# define xthal_icache_line_unlock(addr) do { void *__a = (void*)(addr); \
- __asm__ __volatile__("ihu %0, 0" :: "a"(__a) : "memory"); \
- } while(0)
-#else
-# define xthal_icache_line_lock(addr) do {/*nothing*/} while(0)
-# define xthal_icache_line_unlock(addr) do {/*nothing*/} while(0)
-#endif
-
-/*
- * Even if a config doesn't have caches, an isync is still needed
- * when instructions in any memory are modified, whether by a loader
- * or self-modifying code. Therefore, this macro always produces
- * an isync, whether or not an icache is present.
- */
-#define xthal_icache_sync() \
- __asm__ __volatile__("isync":::"memory")
-
-
-/*** DATA CACHE ***/
-
-#if XCHAL_DCACHE_SIZE > 0
-
-# include <xtensa/tie/xt_datacache.h>
-
-# define xthal_dcache_line_invalidate(addr) do { void *__a = (void*)(addr); \
- __asm__ __volatile__("dhi %0, 0" :: "a"(__a) : "memory"); \
- } while(0)
-# define xthal_dcache_line_writeback(addr) do { void *__a = (void*)(addr); \
- __asm__ __volatile__("dhwb %0, 0" :: "a"(__a) : "memory"); \
- } while(0)
-# define xthal_dcache_line_writeback_inv(addr) do { void *__a = (void*)(addr); \
- __asm__ __volatile__("dhwbi %0, 0" :: "a"(__a) : "memory"); \
- } while(0)
-# define xthal_dcache_sync() \
- __asm__ __volatile__("" /*"dsync"?*/:::"memory")
-# define xthal_dcache_line_prefetch_for_read(addr) do { \
- XT_DPFR((const int*)addr, 0); \
- } while(0)
-#else
-# define xthal_dcache_line_invalidate(addr) do {/*nothing*/} while(0)
-# define xthal_dcache_line_writeback(addr) do {/*nothing*/} while(0)
-# define xthal_dcache_line_writeback_inv(addr) do {/*nothing*/} while(0)
-# define xthal_dcache_sync() __asm__ __volatile__("":::"memory")
-# define xthal_dcache_line_prefetch_for_read(addr) do {/*nothing*/} while(0)
-#endif
-
-#if XCHAL_DCACHE_SIZE > 0 && XCHAL_DCACHE_LINE_LOCKABLE
-# define xthal_dcache_line_lock(addr) do { void *__a = (void*)(addr); \
- __asm__ __volatile__("dpfl %0, 0" :: "a"(__a) : "memory"); \
- } while(0)
-# define xthal_dcache_line_unlock(addr) do { void *__a = (void*)(addr); \
- __asm__ __volatile__("dhu %0, 0" :: "a"(__a) : "memory"); \
- } while(0)
-#else
-# define xthal_dcache_line_lock(addr) do {/*nothing*/} while(0)
-# define xthal_dcache_line_unlock(addr) do {/*nothing*/} while(0)
-#endif
-
-#if XCHAL_DCACHE_SIZE > 0 && XCHAL_DCACHE_IS_WRITEBACK
-
-# define xthal_dcache_line_prefetch_for_write(addr) do { \
- XT_DPFW((const int*)addr, 0); \
- } while(0)
-#else
-# define xthal_dcache_line_prefetch_for_write(addr) do {/*nothing*/} while(0)
-#endif
-
-
-/***** Block Operations *****/
-
-#if XCHAL_DCACHE_SIZE > 0 && XCHAL_HAVE_CACHE_BLOCKOPS
-
-/* upgrades */
-
-# define _XTHAL_DCACHE_BLOCK_UPGRADE(addr, size, type) \
- { \
- type((const int*)addr, size); \
- }
-
-/*downgrades */
-
-# define _XTHAL_DCACHE_BLOCK_DOWNGRADE(addr, size, type) \
- unsigned _s = size; \
- unsigned _a = (unsigned) addr; \
- do { \
- unsigned __s = (_s > XCHAL_DCACHE_SIZE) ? \
- XCHAL_DCACHE_SIZE : _s; \
- type((const int*)_a, __s); \
- _s -= __s; \
- _a += __s; \
- } while(_s > 0);
-
-# define _XTHAL_DCACHE_BLOCK_DOWNGRADE_MAX(addr, size, type, max) \
- if (max <= XCHAL_DCACHE_SIZE) { \
- unsigned _s = size; \
- unsigned _a = (unsigned) addr; \
- type((const int*)_a, _s); \
- } \
- else { \
- _XTHAL_DCACHE_BLOCK_DOWNGRADE(addr, size, type); \
- }
-
-# define xthal_dcache_block_invalidate(addr, size) do { \
- _XTHAL_DCACHE_BLOCK_DOWNGRADE(addr, size, XT_DHI_B); \
- } while(0)
-# define xthal_dcache_block_writeback(addr, size) do { \
- _XTHAL_DCACHE_BLOCK_DOWNGRADE(addr, size, XT_DHWB_B); \
- } while(0)
-# define xthal_dcache_block_writeback_inv(addr, size) do { \
- _XTHAL_DCACHE_BLOCK_DOWNGRADE(addr, size, XT_DHWBI_B); \
- } while(0)
-
-# define xthal_dcache_block_invalidate_max(addr, size, max) do { \
- _XTHAL_DCACHE_BLOCK_DOWNGRADE_MAX(addr, size, XT_DHI_B, max); \
- } while(0)
-# define xthal_dcache_block_writeback_max(addr, size, max) do { \
- _XTHAL_DCACHE_BLOCK_DOWNGRADE_MAX(addr, size, XT_DHWB_B, max); \
- } while(0)
-# define xthal_dcache_block_writeback_inv_max(addr, size, max) do { \
- _XTHAL_DCACHE_BLOCK_DOWNGRADE_MAX(addr, size, XT_DHWBI_B, max); \
- } while(0)
-
-/* upgrades that are performed even with write-thru caches */
-
-# define xthal_dcache_block_prefetch_read_write(addr, size) do { \
- _XTHAL_DCACHE_BLOCK_UPGRADE(addr, size, XT_DPFW_B); \
- } while(0)
-# define xthal_dcache_block_prefetch_read_write_grp(addr, size) do { \
- _XTHAL_DCACHE_BLOCK_UPGRADE(addr, size, XT_DPFW_BF); \
- } while(0)
-# define xthal_dcache_block_prefetch_for_read(addr, size) do { \
- _XTHAL_DCACHE_BLOCK_UPGRADE(addr, size, XT_DPFR_B); \
- } while(0)
-# define xthal_dcache_block_prefetch_for_read_grp(addr, size) do { \
- _XTHAL_DCACHE_BLOCK_UPGRADE(addr, size, XT_DPFR_BF); \
- } while(0)
-
-/* abort all or end optional block cache operations */
-# define xthal_dcache_block_abort() do { \
- XT_PFEND_A(); \
- } while(0)
-# define xthal_dcache_block_end() do { \
- XT_PFEND_O(); \
- } while(0)
-
-/* wait for all/required block cache operations to finish */
-# define xthal_dcache_block_wait() do { \
- XT_PFWAIT_A(); \
- } while(0)
-# define xthal_dcache_block_required_wait() do { \
- XT_PFWAIT_R(); \
- } while(0)
-/* Start a new group */
-# define xthal_dcache_block_newgrp() do { \
- XT_PFNXT_F(); \
- } while(0)
-#else
-# define xthal_dcache_block_invalidate(addr, size) do {/*nothing*/} while(0)
-# define xthal_dcache_block_writeback(addr, size) do {/*nothing*/} while(0)
-# define xthal_dcache_block_writeback_inv(addr, size) do {/*nothing*/} while(0)
-# define xthal_dcache_block_invalidate_max(addr, size, max) do {/*nothing*/} while(0)
-# define xthal_dcache_block_writeback_max(addr, size, max) do {/*nothing*/} while(0)
-# define xthal_dcache_block_writeback_inv_max(addr, size, max) do {/*nothing*/} while(0)
-# define xthal_dcache_block_prefetch_read_write(addr, size) do {/*nothing*/} while(0)
-# define xthal_dcache_block_prefetch_read_write_grp(addr, size) do {/*nothing*/} while(0)
-# define xthal_dcache_block_prefetch_for_read(addr, size) do {/*nothing*/} while(0)
-# define xthal_dcache_block_prefetch_for_read_grp(addr, size) do {/*nothing*/} while(0)
-# define xthal_dcache_block_end() do {/*nothing*/} while(0)
-# define xthal_dcache_block_abort() do {/*nothing*/} while(0)
-# define xthal_dcache_block_wait() do {/*nothing*/} while(0)
-# define xthal_dcache_block_required_wait() do {/*nothing*/} while(0)
-# define xthal_dcache_block_newgrp() do {/*nothing*/} while(0)
-#endif
-
-#if XCHAL_DCACHE_SIZE > 0 && XCHAL_HAVE_CACHE_BLOCKOPS && XCHAL_DCACHE_IS_WRITEBACK
-
-# define xthal_dcache_block_prefetch_for_write(addr, size) do { \
- _XTHAL_DCACHE_BLOCK_UPGRADE(addr, size, XT_DPFW_B); \
- } while(0)
-# define xthal_dcache_block_prefetch_modify(addr, size) do { \
- _XTHAL_DCACHE_BLOCK_UPGRADE(addr, size, XT_DPFM_B); \
- } while(0)
-# define xthal_dcache_block_prefetch_for_write_grp(addr, size) do { \
- _XTHAL_DCACHE_BLOCK_UPGRADE(addr, size, XT_DPFW_BF); \
- } while(0)
-# define xthal_dcache_block_prefetch_modify_grp(addr, size) do { \
- _XTHAL_DCACHE_BLOCK_UPGRADE(addr, size, XT_DPFM_BF); \
- } while(0)
-#else
-# define xthal_dcache_block_prefetch_for_write(addr, size) do {/*nothing*/} while(0)
-# define xthal_dcache_block_prefetch_modify(addr, size) do {/*nothing*/} while(0)
-# define xthal_dcache_block_prefetch_for_write_grp(addr, size) do {/*nothing*/} while(0)
-# define xthal_dcache_block_prefetch_modify_grp(addr, size) do {/*nothing*/} while(0)
-#endif
-
-/*************************** INTERRUPTS ***************************/
-
-/*
- * Macro versions of:
- * unsigned xthal_get_intenable( void );
- * void xthal_set_intenable( unsigned );
- * unsigned xthal_get_interrupt( void );
- * void xthal_set_intset( unsigned );
- * void xthal_set_intclear( unsigned );
- * unsigned xthal_get_ccount(void);
- * void xthal_set_ccompare(int, unsigned);
- * unsigned xthal_get_ccompare(int);
- *
- * NOTE: for {set,get}_ccompare, the first argument MUST be a decimal constant.
- */
-
-#if XCHAL_HAVE_INTERRUPTS
-# define XTHAL_GET_INTENABLE() ({ int __intenable; \
- __asm__("rsr.intenable %0" : "=a"(__intenable)); \
- __intenable; })
-# define XTHAL_SET_INTENABLE(v) do { int __intenable = (int)(v); \
- __asm__ __volatile__("wsr.intenable %0" :: "a"(__intenable):"memory"); \
- } while(0)
-# define XTHAL_GET_INTERRUPT() ({ int __interrupt; \
- __asm__("rsr.interrupt %0" : "=a"(__interrupt)); \
- __interrupt; })
-# define XTHAL_SET_INTSET(v) do { int __interrupt = (int)(v); \
- __asm__ __volatile__("wsr.intset %0" :: "a"(__interrupt):"memory"); \
- } while(0)
-# define XTHAL_SET_INTCLEAR(v) do { int __interrupt = (int)(v); \
- __asm__ __volatile__("wsr.intclear %0" :: "a"(__interrupt):"memory"); \
- } while(0)
-# define XTHAL_GET_CCOUNT() ({ int __ccount; \
- __asm__("rsr.ccount %0" : "=a"(__ccount)); \
- __ccount; })
-# define XTHAL_SET_CCOUNT(v) do { int __ccount = (int)(v); \
- __asm__ __volatile__("wsr.ccount %0" :: "a"(__ccount):"memory"); \
- } while(0)
-# define _XTHAL_GET_CCOMPARE(n) ({ int __ccompare; \
- __asm__("rsr.ccompare" #n " %0" : "=a"(__ccompare)); \
- __ccompare; })
-# define XTHAL_GET_CCOMPARE(n) _XTHAL_GET_CCOMPARE(n)
-# define _XTHAL_SET_CCOMPARE(n,v) do { int __ccompare = (int)(v); \
- __asm__ __volatile__("wsr.ccompare" #n " %0 ; esync" :: "a"(__ccompare):"memory"); \
- } while(0)
-# define XTHAL_SET_CCOMPARE(n,v) _XTHAL_SET_CCOMPARE(n,v)
-#else
-# define XTHAL_GET_INTENABLE() 0
-# define XTHAL_SET_INTENABLE(v) do {/*nothing*/} while(0)
-# define XTHAL_GET_INTERRUPT() 0
-# define XTHAL_SET_INTSET(v) do {/*nothing*/} while(0)
-# define XTHAL_SET_INTCLEAR(v) do {/*nothing*/} while(0)
-# define XTHAL_GET_CCOUNT() 0
-# define XTHAL_SET_CCOUNT(v) do {/*nothing*/} while(0)
-# define XTHAL_GET_CCOMPARE(n) 0
-# define XTHAL_SET_CCOMPARE(n,v) do {/*nothing*/} while(0)
-#endif
-
-/* New functions added to accomodate XEA3 and allow deprecation of older
- functions. For this release they just map to the older ones. */
-
-/* Enables the specified interrupt. */
-static inline void xthal_interrupt_enable(unsigned intnum)
-{
- xthal_int_enable(1 << intnum);
-}
-
-/* Disables the specified interrupt. */
-static inline void xthal_interrupt_disable(unsigned intnum)
-{
- xthal_int_disable(1 << intnum);
-}
-
-/* Triggers the specified interrupt. */
-static inline void xthal_interrupt_trigger(unsigned intnum)
-{
- xthal_set_intset(1 << intnum);
-}
-
-/* Clears the specified interrupt. */
-static inline void xthal_interrupt_clear(unsigned intnum)
-{
- xthal_set_intclear(1 << intnum);
-}
-
-
-/*************************** MISC ***************************/
-
-/*
- * Macro or inline versions of:
- * void xthal_clear_regcached_code( void );
- * unsigned xthal_get_prid( void );
- * unsigned xthal_compare_and_set( int *addr, int testval, int setval );
- */
-
-#if XCHAL_HAVE_LOOPS
-# define XTHAL_CLEAR_REGCACHED_CODE() \
- __asm__ __volatile__("wsr.lcount %0" :: "a"(0) : "memory")
-#else
-# define XTHAL_CLEAR_REGCACHED_CODE() do {/*nothing*/} while(0)
-#endif
-
-#if XCHAL_HAVE_PRID
-# define XTHAL_GET_PRID() ({ int __prid; \
- __asm__("rsr.prid %0" : "=a"(__prid)); \
- __prid; })
-#else
-# define XTHAL_GET_PRID() 0
-#endif
-
-
-static inline unsigned XTHAL_COMPARE_AND_SET( int *addr, int testval, int setval )
-{
- int result;
-
-#if XCHAL_HAVE_S32C1I && XCHAL_HW_MIN_VERSION_MAJOR >= 2200
- __asm__ __volatile__ (
- " wsr.scompare1 %2 \n"
- " s32c1i %0, %3, 0 \n"
- : "=a"(result) : "0" (setval), "a" (testval), "a" (addr)
- : "memory");
-#elif XCHAL_HAVE_INTERRUPTS
- int tmp;
- __asm__ __volatile__ (
- " rsil %4, 15 \n" // %4 == saved ps
- " l32i %0, %3, 0 \n" // %0 == value to test, return val
- " bne %2, %0, 9f \n" // test
- " s32i %1, %3, 0 \n" // write the new value
- "9: wsr.ps %4 ; rsync \n" // restore the PS
- : "=a"(result)
- : "0" (setval), "a" (testval), "a" (addr), "a" (tmp)
- : "memory");
-#else
- __asm__ __volatile__ (
- " l32i %0, %3, 0 \n" // %0 == value to test, return val
- " bne %2, %0, 9f \n" // test
- " s32i %1, %3, 0 \n" // write the new value
- "9: \n"
- : "=a"(result) : "0" (setval), "a" (testval), "a" (addr)
- : "memory");
-#endif
- return result;
-}
-
-#if XCHAL_HAVE_EXTERN_REGS
-
-static inline unsigned XTHAL_RER (unsigned int reg)
-{
- unsigned result;
-
- __asm__ __volatile__ (
- " rer %0, %1"
- : "=a" (result) : "a" (reg) : "memory");
-
- return result;
-}
-
-static inline void XTHAL_WER (unsigned reg, unsigned value)
-{
- __asm__ __volatile__ (
- " wer %0, %1"
- : : "a" (value), "a" (reg) : "memory");
-}
-
-#endif /* XCHAL_HAVE_EXTERN_REGS */
-
-/*
- * Sets a single entry at 'index' within the MPU
- *
- * The caller must ensure that the resulting MPU map is ordered.
- */
-static inline void xthal_mpu_set_entry (xthal_MPU_entry entry)
-{
-#if XCHAL_HAVE_MPU
- __asm__ __volatile__("j 1f\n\t.align 8\n\t1: memw\n\twptlb %0, %1\n\t" : : "a" (entry.at), "a"(entry.as));
-#endif
-}
-
-/* Same as xthal_mpu_set_entry except that this function must not be used to change the MPU entry
- * for the currently executing instruction ... use xthal_mpu_set_entry instead. */
-static inline void xthal_mpu_set_entry_ (xthal_MPU_entry entry)
-{
-#if XCHAL_HAVE_MPU
- __asm__ __volatile__("wptlb %0, %1\n\t" : : "a" (entry.at), "a"(entry.as));
-#endif
-}
-
-
-
-#endif /* C code */
-
-#endif /*XTENSA_CACHE_H*/
-
diff --git a/src/arch/xtensa/include/xtensa/coreasm.h b/src/arch/xtensa/include/xtensa/coreasm.h
deleted file mode 100644
index 335c0c3..0000000
--- a/src/arch/xtensa/include/xtensa/coreasm.h
+++ /dev/null
@@ -1,1059 +0,0 @@
-/*
- * xtensa/coreasm.h -- assembler-specific definitions that depend on CORE configuration
- *
- * Source for configuration-independent binaries (which link in a
- * configuration-specific HAL library) must NEVER include this file.
- * It is perfectly normal, however, for the HAL itself to include this file.
- *
- * This file must NOT include xtensa/config/system.h. Any assembler
- * header file that depends on system information should likely go
- * in a new systemasm.h (or sysasm.h) header file.
- *
- * NOTE: macro beqi32 is NOT configuration-dependent, and is placed
- * here until we have a proper configuration-independent header file.
- */
-
-/* $Id: //depot/rel/Foxhill/dot.8/Xtensa/OS/include/xtensa/coreasm.h#1 $ */
-
-/*
- * Copyright (c) 2000-2014 Tensilica Inc.
- *
- * Permission is hereby granted, free of charge, to any person obtaining
- * a copy of this software and associated documentation files (the
- * "Software"), to deal in the Software without restriction, including
- * without limitation the rights to use, copy, modify, merge, publish,
- * distribute, sublicense, and/or sell copies of the Software, and to
- * permit persons to whom the Software is furnished to do so, subject to
- * the following conditions:
- *
- * The above copyright notice and this permission notice shall be included
- * in all copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
- * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
- * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
- * IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY
- * CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
- * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
- * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
- */
-
-#ifndef XTENSA_COREASM_H
-#define XTENSA_COREASM_H
-
-/*
- * Tell header files this is assembly source, so they can avoid non-assembler
- * definitions (eg. C types etc):
- */
-#ifndef _ASMLANGUAGE /* conditionalize to avoid cpp warnings (3rd parties might use same macro) */
-#define _ASMLANGUAGE
-#endif
-
-#include <xtensa/config/core.h>
-#include <xtensa/config/specreg.h>
-#include <xtensa/config/system.h>
-
-/*
- * Assembly-language specific definitions (assembly macros, etc.).
- */
-
-/*----------------------------------------------------------------------
- * find_ms_setbit
- *
- * This macro finds the most significant bit that is set in <as>
- * and return its index + <base> in <ad>, or <base> - 1 if <as> is zero.
- * The index counts starting at zero for the lsbit, so the return
- * value ranges from <base>-1 (no bit set) to <base>+31 (msbit set).
- *
- * Parameters:
- * <ad> destination address register (any register)
- * <as> source address register
- * <at> temporary address register (must be different than <as>)
- * <base> constant value added to result (usually 0 or 1)
- * On entry:
- * <ad> = undefined if different than <as>
- * <as> = value whose most significant set bit is to be found
- * <at> = undefined
- * no other registers are used by this macro.
- * On exit:
- * <ad> = <base> + index of msbit set in original <as>,
- * = <base> - 1 if original <as> was zero.
- * <as> clobbered (if not <ad>)
- * <at> clobbered (if not <ad>)
- * Example:
- * find_ms_setbit a0, a4, a0, 0 -- return in a0 index of msbit set in a4
- */
-
- .macro find_ms_setbit ad, as, at, base
-#if XCHAL_HAVE_NSA
- movi \at, 31+\base
- nsau \as, \as // get index of \as, numbered from msbit (32 if absent)
- sub \ad, \at, \as // get numbering from lsbit (0..31, -1 if absent)
-#else /* XCHAL_HAVE_NSA */
- movi \at, \base // start with result of 0 (point to lsbit of 32)
-
- beqz \as, 2f // special case for zero argument: return -1
- bltui \as, 0x10000, 1f // is it one of the 16 lsbits? (if so, check lower 16 bits)
- addi \at, \at, 16 // no, increment result to upper 16 bits (of 32)
- //srli \as, \as, 16 // check upper half (shift right 16 bits)
- extui \as, \as, 16, 16 // check upper half (shift right 16 bits)
-1: bltui \as, 0x100, 1f // is it one of the 8 lsbits? (if so, check lower 8 bits)
- addi \at, \at, 8 // no, increment result to upper 8 bits (of 16)
- srli \as, \as, 8 // shift right to check upper 8 bits
-1: bltui \as, 0x10, 1f // is it one of the 4 lsbits? (if so, check lower 4 bits)
- addi \at, \at, 4 // no, increment result to upper 4 bits (of 8)
- srli \as, \as, 4 // shift right 4 bits to check upper half
-1: bltui \as, 0x4, 1f // is it one of the 2 lsbits? (if so, check lower 2 bits)
- addi \at, \at, 2 // no, increment result to upper 2 bits (of 4)
- srli \as, \as, 2 // shift right 2 bits to check upper half
-1: bltui \as, 0x2, 1f // is it the lsbit?
- addi \at, \at, 2 // no, increment result to upper bit (of 2)
-2: addi \at, \at, -1 // (from just above: add 1; from beqz: return -1)
- //srli \as, \as, 1
-1: // done! \at contains index of msbit set (or -1 if none set)
- .if 0x\ad - 0x\at // destination different than \at ? (works because regs are a0-a15)
- mov \ad, \at // then move result to \ad
- .endif
-#endif /* XCHAL_HAVE_NSA */
- .endm // find_ms_setbit
-
-/*----------------------------------------------------------------------
- * find_ls_setbit
- *
- * This macro finds the least significant bit that is set in <as>,
- * and return its index in <ad>.
- * Usage is the same as for the find_ms_setbit macro.
- * Example:
- * find_ls_setbit a0, a4, a0, 0 -- return in a0 index of lsbit set in a4
- */
-
- .macro find_ls_setbit ad, as, at, base
- neg \at, \as // keep only the least-significant bit that is set...
- and \as, \at, \as // ... in \as
- find_ms_setbit \ad, \as, \at, \base
- .endm // find_ls_setbit
-
-/*----------------------------------------------------------------------
- * find_ls_one
- *
- * Same as find_ls_setbit with base zero.
- * Source (as) and destination (ad) registers must be different.
- * Provided for backward compatibility.
- */
-
- .macro find_ls_one ad, as
- find_ls_setbit \ad, \as, \ad, 0
- .endm // find_ls_one
-
-/*----------------------------------------------------------------------
- * floop, floopnez, floopgtz, floopend
- *
- * These macros are used for fast inner loops that
- * work whether or not the Loops options is configured.
- * If the Loops option is configured, they simply use
- * the zero-overhead LOOP instructions; otherwise
- * they use explicit decrement and branch instructions.
- *
- * They are used in pairs, with floop, floopnez or floopgtz
- * at the beginning of the loop, and floopend at the end.
- *
- * Each pair of loop macro calls must be given the loop count
- * address register and a unique label for that loop.
- *
- * Example:
- *
- * movi a3, 16 // loop 16 times
- * floop a3, myloop1
- * :
- * bnez a7, end1 // exit loop if a7 != 0
- * :
- * floopend a3, myloop1
- * end1:
- *
- * Like the LOOP instructions, these macros cannot be
- * nested, must include at least one instruction,
- * cannot call functions inside the loop, etc.
- * The loop can be exited by jumping to the instruction
- * following floopend (or elsewhere outside the loop),
- * or continued by jumping to a NOP instruction placed
- * immediately before floopend.
- *
- * Unlike LOOP instructions, the register passed to floop*
- * cannot be used inside the loop, because it is used as
- * the loop counter if the Loops option is not configured.
- * And its value is undefined after exiting the loop.
- * And because the loop counter register is active inside
- * the loop, you can't easily use this construct to loop
- * across a register file using ROTW as you might with LOOP
- * instructions, unless you copy the loop register along.
- */
-
- /* Named label version of the macros: */
-
- .macro floop ar, endlabel
- floop_ \ar, .Lfloopstart_\endlabel, .Lfloopend_\endlabel
- .endm
-
- .macro floopnez ar, endlabel
- floopnez_ \ar, .Lfloopstart_\endlabel, .Lfloopend_\endlabel
- .endm
-
- .macro floopgtz ar, endlabel
- floopgtz_ \ar, .Lfloopstart_\endlabel, .Lfloopend_\endlabel
- .endm
-
- .macro floopend ar, endlabel
- floopend_ \ar, .Lfloopstart_\endlabel, .Lfloopend_\endlabel
- .endm
-
- /* Numbered local label version of the macros: */
-#if 0 /*UNTESTED*/
- .macro floop89 ar
- floop_ \ar, 8, 9f
- .endm
-
- .macro floopnez89 ar
- floopnez_ \ar, 8, 9f
- .endm
-
- .macro floopgtz89 ar
- floopgtz_ \ar, 8, 9f
- .endm
-
- .macro floopend89 ar
- floopend_ \ar, 8b, 9
- .endm
-#endif /*0*/
-
- /* Underlying version of the macros: */
-
- .macro floop_ ar, startlabel, endlabelref
- .ifdef _infloop_
- .if _infloop_
- .err // Error: floop cannot be nested
- .endif
- .endif
- .set _infloop_, 1
-#if XCHAL_HAVE_LOOPS
- loop \ar, \endlabelref
-#else /* XCHAL_HAVE_LOOPS */
-\startlabel:
- addi \ar, \ar, -1
-#endif /* XCHAL_HAVE_LOOPS */
- .endm // floop_
-
- .macro floopnez_ ar, startlabel, endlabelref
- .ifdef _infloop_
- .if _infloop_
- .err // Error: floopnez cannot be nested
- .endif
- .endif
- .set _infloop_, 1
-#if XCHAL_HAVE_LOOPS
- loopnez \ar, \endlabelref
-#else /* XCHAL_HAVE_LOOPS */
- beqz \ar, \endlabelref
-\startlabel:
- addi \ar, \ar, -1
-#endif /* XCHAL_HAVE_LOOPS */
- .endm // floopnez_
-
- .macro floopgtz_ ar, startlabel, endlabelref
- .ifdef _infloop_
- .if _infloop_
- .err // Error: floopgtz cannot be nested
- .endif
- .endif
- .set _infloop_, 1
-#if XCHAL_HAVE_LOOPS
- loopgtz \ar, \endlabelref
-#else /* XCHAL_HAVE_LOOPS */
- bltz \ar, \endlabelref
- beqz \ar, \endlabelref
-\startlabel:
- addi \ar, \ar, -1
-#endif /* XCHAL_HAVE_LOOPS */
- .endm // floopgtz_
-
-
- .macro floopend_ ar, startlabelref, endlabel
- .ifndef _infloop_
- .err // Error: floopend without matching floopXXX
- .endif
- .ifeq _infloop_
- .err // Error: floopend without matching floopXXX
- .endif
- .set _infloop_, 0
-#if ! XCHAL_HAVE_LOOPS
- bnez \ar, \startlabelref
-#endif /* XCHAL_HAVE_LOOPS */
-\endlabel:
- .endm // floopend_
-
-/*----------------------------------------------------------------------
- * crsil -- conditional RSIL (read/set interrupt level)
- *
- * Executes the RSIL instruction if it exists, else just reads PS.
- * The RSIL instruction does not exist in the new exception architecture
- * if the interrupt option is not selected.
- */
-
- .macro crsil ar, newlevel
-#if XCHAL_HAVE_OLD_EXC_ARCH || XCHAL_HAVE_INTERRUPTS
- rsil \ar, \newlevel
-#else
- rsr.ps \ar
-#endif
- .endm // crsil
-
-/*----------------------------------------------------------------------
- * safe_movi_a0 -- move constant into a0 when L32R is not safe
- *
- * This macro is typically used by interrupt/exception handlers.
- * Loads a 32-bit constant in a0, without using any other register,
- * and without corrupting the LITBASE register, even when the
- * value of the LITBASE register is unknown (eg. when application
- * code and interrupt/exception handling code are built independently,
- * and thus with independent values of the LITBASE register;
- * debug monitors are one example of this).
- *
- * Worst-case size of resulting code: 17 bytes.
- */
-
- .macro safe_movi_a0 constant
-#if XCHAL_HAVE_ABSOLUTE_LITERALS
- /* Contort a PC-relative literal load even though we may be in litbase-relative mode: */
- j 1f
- .begin no-transform // ensure what follows is assembled exactly as-is
- .align 4 // ensure constant and call0 target ...
- .byte 0 // ... are 4-byte aligned (call0 instruction is 3 bytes long)
-1: call0 2f // read PC (that follows call0) in a0
- .long \constant // 32-bit constant to load into a0
-2:
- .end no-transform
- l32i a0, a0, 0 // load constant
-#else
- movi a0, \constant // no LITBASE, can assume PC-relative L32R
-#endif
- .endm
-
-
-
-
-/*----------------------------------------------------------------------
- * window_spill{4,8,12}
- *
- * These macros spill callers' register windows to the stack.
- * They work for both privileged and non-privileged tasks.
- * Must be called from a windowed ABI context, eg. within
- * a windowed ABI function (ie. valid stack frame, window
- * exceptions enabled, not in exception mode, etc).
- *
- * This macro requires a single invocation of the window_spill_common
- * macro in the same assembly unit and section.
- *
- * Note that using window_spill{4,8,12} macros is more efficient
- * than calling a function implemented using window_spill_function,
- * because the latter needs extra code to figure out the size of
- * the call to the spilling function.
- *
- * Example usage:
- *
- * .text
- * .align 4
- * .global some_function
- * .type some_function,@function
- * some_function:
- * entry a1, 16
- * :
- * :
- *
- * window_spill4 // Spill windows of some_function's callers; preserves a0..a3 only;
- * // to use window_spill{8,12} in this example function we'd have
- * // to increase space allocated by the entry instruction, because
- * // 16 bytes only allows call4; 32 or 48 bytes (+locals) are needed
- * // for call8/window_spill8 or call12/window_spill12 respectively.
- *
- * :
- *
- * retw
- *
- * window_spill_common // instantiates code used by window_spill4
- *
- *
- * On entry:
- * none (if window_spill4)
- * stack frame has enough space allocated for call8 (if window_spill8)
- * stack frame has enough space allocated for call12 (if window_spill12)
- * On exit:
- * a4..a15 clobbered (if window_spill4)
- * a8..a15 clobbered (if window_spill8)
- * a12..a15 clobbered (if window_spill12)
- * no caller windows are in live registers
- */
-
- .macro window_spill4
-#if XCHAL_HAVE_WINDOWED
-# if XCHAL_NUM_AREGS == 16
- movi a15, 0 // for 16-register files, no need to call to reach the end
-# elif XCHAL_NUM_AREGS == 32
- call4 .L__wdwspill_assist28 // call deep enough to clear out any live callers
-# elif XCHAL_NUM_AREGS == 64
- call4 .L__wdwspill_assist60 // call deep enough to clear out any live callers
-# endif
-#endif
- .endm // window_spill4
-
- .macro window_spill8
-#if XCHAL_HAVE_WINDOWED
-# if XCHAL_NUM_AREGS == 16
- movi a15, 0 // for 16-register files, no need to call to reach the end
-# elif XCHAL_NUM_AREGS == 32
- call8 .L__wdwspill_assist24 // call deep enough to clear out any live callers
-# elif XCHAL_NUM_AREGS == 64
- call8 .L__wdwspill_assist56 // call deep enough to clear out any live callers
-# endif
-#endif
- .endm // window_spill8
-
- .macro window_spill12
-#if XCHAL_HAVE_WINDOWED
-# if XCHAL_NUM_AREGS == 16
- movi a15, 0 // for 16-register files, no need to call to reach the end
-# elif XCHAL_NUM_AREGS == 32
- call12 .L__wdwspill_assist20 // call deep enough to clear out any live callers
-# elif XCHAL_NUM_AREGS == 64
- call12 .L__wdwspill_assist52 // call deep enough to clear out any live callers
-# endif
-#endif
- .endm // window_spill12
-
-
-/*----------------------------------------------------------------------
- * window_spill_function
- *
- * This macro outputs a function that will spill its caller's callers'
- * register windows to the stack. Eg. it could be used to implement
- * a version of xthal_window_spill() that works in non-privileged tasks.
- * This works for both privileged and non-privileged tasks.
- *
- * Typical usage:
- *
- * .text
- * .align 4
- * .global my_spill_function
- * .type my_spill_function,@function
- * my_spill_function:
- * window_spill_function
- *
- * On entry to resulting function:
- * none
- * On exit from resulting function:
- * none (no caller windows are in live registers)
- */
-
- .macro window_spill_function
-#if XCHAL_HAVE_WINDOWED
-# if XCHAL_NUM_AREGS == 32
- entry sp, 48
- bbci.l a0, 31, 1f // branch if called with call4
- bbsi.l a0, 30, 2f // branch if called with call12
- call8 .L__wdwspill_assist16 // called with call8, only need another 8
- retw
-1: call12 .L__wdwspill_assist16 // called with call4, only need another 12
- retw
-2: call4 .L__wdwspill_assist16 // called with call12, only need another 4
- retw
-# elif XCHAL_NUM_AREGS == 64
- entry sp, 48
- bbci.l a0, 31, 1f // branch if called with call4
- bbsi.l a0, 30, 2f // branch if called with call12
- call4 .L__wdwspill_assist52 // called with call8, only need a call4
- retw
-1: call8 .L__wdwspill_assist52 // called with call4, only need a call8
- retw
-2: call12 .L__wdwspill_assist40 // called with call12, can skip a call12
- retw
-# elif XCHAL_NUM_AREGS == 16
- entry sp, 16
- bbci.l a0, 31, 1f // branch if called with call4
- bbsi.l a0, 30, 2f // branch if called with call12
- movi a7, 0 // called with call8
- retw
-1: movi a11, 0 // called with call4
-2: retw // if called with call12, everything already spilled
-
-// movi a15, 0 // trick to spill all but the direct caller
-// j 1f
-// // The entry instruction is magical in the assembler (gets auto-aligned)
-// // so we have to jump to it to avoid falling through the padding.
-// // We need entry/retw to know where to return.
-//1: entry sp, 16
-// retw
-# else
-# error "unrecognized address register file size"
-# endif
-
-#endif /* XCHAL_HAVE_WINDOWED */
- window_spill_common
- .endm // window_spill_function
-
-/*----------------------------------------------------------------------
- * window_spill_common
- *
- * Common code used by any number of invocations of the window_spill##
- * and window_spill_function macros.
- *
- * Must be instantiated exactly once within a given assembly unit,
- * within call/j range of and same section as window_spill##
- * macro invocations for that assembly unit.
- * (Is automatically instantiated by the window_spill_function macro.)
- */
-
- .macro window_spill_common
-#if XCHAL_HAVE_WINDOWED && (XCHAL_NUM_AREGS == 32 || XCHAL_NUM_AREGS == 64)
- .ifndef .L__wdwspill_defined
-# if XCHAL_NUM_AREGS >= 64
-.L__wdwspill_assist60:
- entry sp, 32
- call8 .L__wdwspill_assist52
- retw
-.L__wdwspill_assist56:
- entry sp, 16
- call4 .L__wdwspill_assist52
- retw
-.L__wdwspill_assist52:
- entry sp, 48
- call12 .L__wdwspill_assist40
- retw
-.L__wdwspill_assist40:
- entry sp, 48
- call12 .L__wdwspill_assist28
- retw
-# endif
-.L__wdwspill_assist28:
- entry sp, 48
- call12 .L__wdwspill_assist16
- retw
-.L__wdwspill_assist24:
- entry sp, 32
- call8 .L__wdwspill_assist16
- retw
-.L__wdwspill_assist20:
- entry sp, 16
- call4 .L__wdwspill_assist16
- retw
-.L__wdwspill_assist16:
- entry sp, 16
- movi a15, 0
- retw
- .set .L__wdwspill_defined, 1
- .endif
-#endif /* XCHAL_HAVE_WINDOWED with 32 or 64 aregs */
- .endm // window_spill_common
-
-/*----------------------------------------------------------------------
- * beqi32
- *
- * macro implements version of beqi for arbitrary 32-bit immediate value
- *
- * beqi32 ax, ay, imm32, label
- *
- * Compares value in register ax with imm32 value and jumps to label if
- * equal. Clobbers register ay if needed
- *
- */
- .macro beqi32 ax, ay, imm, label
- .ifeq ((\imm-1) & ~7) // 1..8 ?
- beqi \ax, \imm, \label
- .else
- .ifeq (\imm+1) // -1 ?
- beqi \ax, \imm, \label
- .else
- .ifeq (\imm) // 0 ?
- beqz \ax, \label
- .else
- // We could also handle immediates 10,12,16,32,64,128,256
- // but it would be a long macro...
- movi \ay, \imm
- beq \ax, \ay, \label
- .endif
- .endif
- .endif
- .endm // beqi32
-
-/*----------------------------------------------------------------------
- * isync_retw_nop
- *
- * This macro must be invoked immediately after ISYNC if ISYNC
- * would otherwise be immediately followed by RETW (or other instruction
- * modifying WindowBase or WindowStart), in a context where
- * kernel vector mode may be selected, and level-one interrupts
- * and window overflows may be enabled, on an XEA1 configuration.
- *
- * On hardware with erratum "XEA1KWIN" (see <xtensa/core.h> for details),
- * XEA1 code must have at least one instruction between ISYNC and RETW if
- * run in kernel vector mode with interrupts and window overflows enabled.
- */
- .macro isync_retw_nop
-#if XCHAL_MAYHAVE_ERRATUM_XEA1KWIN
- nop
-#endif
- .endm
-
-/*----------------------------------------------------------------------
- * isync_return_nop
- *
- * This macro should be used instead of isync_retw_nop in code that is
- * intended to run on both the windowed and call0 ABIs
- */
- .macro isync_return_nop
-#ifdef __XTENSA_WINDOWED_ABI__
- isync_retw_nop
-#endif
- .endm
-
-/*----------------------------------------------------------------------
- * isync_erratum453
- *
- * This macro must be invoked at certain points in the code,
- * such as in exception and interrupt vectors in particular,
- * to work around erratum 453.
- */
- .macro isync_erratum453
-#if XCHAL_ERRATUM_453
- isync
-#endif
- .endm
-
-
-/*----------------------------------------------------------------------
- * readsr
- *
- * wrapper for 'rsr' that constructs register names that involve levels
- * e.g. EPCn etc. Use like so:
- * readsr epc XCHAL_DEBUGLEVEL a2
- */
- .macro readsr reg suf ar
- rsr.\reg\suf \ar
- .endm
-
-/*----------------------------------------------------------------------
- * writesr
- *
- * wrapper for 'wsr' that constructs register names that involve levels
- * e.g. EPCn etc. Use like so:
- * writesr epc XCHAL_DEBUGLEVEL a2
- */
- .macro writesr reg suf ar
- wsr.\reg\suf \ar
- .endm
-
-/*----------------------------------------------------------------------
- * xchgsr
- *
- * wrapper for 'xsr' that constructs register names that involve levels
- * e.g. EPCn etc. Use like so:
- * xchgsr epc XCHAL_DEBUGLEVEL a2
- */
- .macro xchgsr reg suf ar
- xsr.\reg\suf \ar
- .endm
-
-/*----------------------------------------------------------------------
- * INDEX_SR
- *
- * indexing wrapper for rsr/wsr/xsr that constructs register names from
- * the provided base name and the current index. Use like so:
- * .set _idx, 0
- * INDEX_SR rsr.ccompare a2
- *
- * this yields: rsr.ccompare0 a2
- */
- .macro INDEX_SR instr ar
-.ifeq (_idx)
- &instr&0 \ar
-.endif
-.ifeq (_idx-1)
- &instr&1 \ar
-.endif
-.ifeq (_idx-2)
- &instr&2 \ar
-.endif
-.ifeq (_idx-3)
- &instr&3 \ar
-.endif
-.ifeq (_idx-4)
- &instr&4 \ar
-.endif
-.ifeq (_idx-5)
- &instr&5 \ar
-.endif
-.ifeq (_idx-6)
- &instr&6 \ar
-.endif
-.ifeq (_idx-7)
- &instr&7 \ar
-.endif
- .endm
-
-
-/*----------------------------------------------------------------------
- * abs
- *
- * implements abs on machines that do not have it configured
- */
-
-#if !XCHAL_HAVE_ABS
- .macro abs arr, ars
- .ifc \arr, \ars
- //src equal dest is less efficient
- bgez \arr, 1f
- neg \arr, \arr
-1:
- .else
- neg \arr, \ars
- movgez \arr, \ars, \ars
- .endif
- .endm
-#endif /* !XCHAL_HAVE_ABS */
-
-
-/*----------------------------------------------------------------------
- * addx2
- *
- * implements addx2 on machines that do not have it configured
- *
- */
-
-#if !XCHAL_HAVE_ADDX
- .macro addx2 arr, ars, art
- .ifc \arr, \art
- .ifc \arr, \ars
- // addx2 a, a, a (not common)
- .err
- .else
- add \arr, \ars, \art
- add \arr, \ars, \art
- .endif
- .else
- //addx2 a, b, c
- //addx2 a, a, b
- //addx2 a, b, b
- slli \arr, \ars, 1
- add \arr, \arr, \art
- .endif
- .endm
-#endif /* !XCHAL_HAVE_ADDX */
-
-/*----------------------------------------------------------------------
- * addx4
- *
- * implements addx4 on machines that do not have it configured
- *
- */
-
-#if !XCHAL_HAVE_ADDX
- .macro addx4 arr, ars, art
- .ifc \arr, \art
- .ifc \arr, \ars
- // addx4 a, a, a (not common)
- .err
- .else
- //# addx4 a, b, a
- add \arr, \ars, \art
- add \arr, \ars, \art
- add \arr, \ars, \art
- add \arr, \ars, \art
- .endif
- .else
- //addx4 a, b, c
- //addx4 a, a, b
- //addx4 a, b, b
- slli \arr, \ars, 2
- add \arr, \arr, \art
- .endif
- .endm
-#endif /* !XCHAL_HAVE_ADDX */
-
-/*----------------------------------------------------------------------
- * addx8
- *
- * implements addx8 on machines that do not have it configured
- *
- */
-
-#if !XCHAL_HAVE_ADDX
- .macro addx8 arr, ars, art
- .ifc \arr, \art
- .ifc \arr, \ars
- //addx8 a, a, a (not common)
- .err
- .else
- //addx8 a, b, a
- add \arr, \ars, \art
- add \arr, \ars, \art
- add \arr, \ars, \art
- add \arr, \ars, \art
- add \arr, \ars, \art
- add \arr, \ars, \art
- add \arr, \ars, \art
- add \arr, \ars, \art
- .endif
- .else
- //addx8 a, b, c
- //addx8 a, a, b
- //addx8 a, b, b
- slli \arr, \ars, 3
- add \arr, \arr, \art
- .endif
- .endm
-#endif /* !XCHAL_HAVE_ADDX */
-
-
-/*----------------------------------------------------------------------
- * rfe_rfue
- *
- * Maps to RFUE on XEA1, and RFE on XEA2. No mapping on XEAX.
- */
-
-#if XCHAL_HAVE_XEA1
- .macro rfe_rfue
- rfue
- .endm
-#elif XCHAL_HAVE_XEA2
- .macro rfe_rfue
- rfe
- .endm
-#endif
-
-
-/*----------------------------------------------------------------------
- * abi_entry
- *
- * Generate proper function entry sequence for the current ABI
- * (windowed or call0). Takes care of allocating stack space (up to 1kB)
- * and saving the return PC, if necessary. The corresponding abi_return
- * macro does the corresponding stack deallocation and restoring return PC.
- *
- * Parameters are:
- *
- * locsize Number of bytes to allocate on the stack
- * for local variables (and for args to pass to
- * callees, if any calls are made). Defaults to zero.
- * The macro rounds this up to a multiple of 16.
- * NOTE: large values are allowed (e.g. up to 1 GB).
- *
- * callsize Maximum call size made by this function.
- * Leave zero (default) for leaf functions, i.e. if
- * this function makes no calls to other functions.
- * Otherwise must be set to 4, 8, or 12 according
- * to whether the "largest" call made is a call[x]4,
- * call[x]8, or call[x]12 (for call0 ABI, it makes
- * no difference whether this is set to 4, 8 or 12,
- * but it must be set to one of these values).
- *
- * NOTE: It is up to the caller to align the entry point, declare the
- * function symbol, make it global, etc.
- *
- * NOTE: This macro relies on assembler relaxation for large values
- * of locsize. It might not work with the no-transform directive.
- * NOTE: For the call0 ABI, this macro ensures SP is allocated or
- * de-allocated cleanly, i.e. without temporarily allocating too much
- * (or allocating negatively!) due to addi relaxation.
- *
- * NOTE: Generating the proper sequence and register allocation for
- * making calls in an ABI independent manner is a separate topic not
- * covered by this macro.
- *
- * NOTE: To access arguments, you can't use a fixed offset from SP.
- * The offset depends on the ABI, whether the function is leaf, etc.
- * The simplest method is probably to use the .locsz symbol, which
- * is set by this macro to the actual number of bytes allocated on
- * the stack, in other words, to the offset from SP to the arguments.
- * E.g. for a function whose arguments are all 32-bit integers, you
- * can get the 7th and 8th arguments (1st and 2nd args stored on stack)
- * using:
- * l32i a2, sp, .locsz
- * l32i a3, sp, .locsz+4
- * (this example works as long as locsize is under L32I's offset limit
- * of 1020 minus up to 48 bytes of ABI-specific stack usage;
- * otherwise you might first need to do "addi a?, sp, .locsz"
- * or similar sequence).
- *
- * NOTE: For call0 ABI, this macro (and abi_return) may clobber a9
- * (a caller-saved register).
- *
- * Examples:
- * abi_entry
- * abi_entry 5
- * abi_entry 22, 8
- * abi_entry 0, 4
- */
-
- /*
- * Compute .locsz and .callsz without emitting any instructions.
- * Used by both abi_entry and abi_return.
- * Assumes locsize >= 0.
- */
- .macro abi_entry_size locsize=0, callsize=0
-#if XCHAL_HAVE_WINDOWED && !__XTENSA_CALL0_ABI__
- .ifeq \callsize
- .set .callsz, 16
- .else
- .ifeq \callsize-4
- .set .callsz, 16
- .else
- .ifeq \callsize-8
- .set .callsz, 32
- .else
- .ifeq \callsize-12
- .set .callsz, 48
- .else
- .error "abi_entry: invalid call size \callsize"
- .endif
- .endif
- .endif
- .endif
- .set .locsz, .callsz + ((\locsize + 15) & -16)
-#else
- .set .callsz, \callsize
- .if .callsz /* if calls, need space for return PC */
- .set .locsz, (\locsize + 4 + 15) & -16
- .else
- .set .locsz, (\locsize + 15) & -16
- .endif
-#endif
- .endm
-
- .macro abi_entry locsize=0, callsize=0
- .iflt \locsize
- .error "abi_entry: invalid negative size of locals (\locsize)"
- .endif
- abi_entry_size \locsize, \callsize
-#if XCHAL_HAVE_WINDOWED && !__XTENSA_CALL0_ABI__
-# define ABI_ENTRY_MINSIZE 3 /* size of abi_entry (no arguments) instructions in bytes */
- .ifgt .locsz - 32760 /* .locsz > 32760 (ENTRY's max range)? */
- /* Funky computation to try to have assembler use addmi efficiently if possible: */
- entry sp, 0x7F00 + (.locsz & 0xF0)
- addi a12, sp, - ((.locsz & -0x100) - 0x7F00)
- movsp sp, a12
- .else
- entry sp, .locsz
- .endif
-#else
-# define ABI_ENTRY_MINSIZE 0 /* size of abi_entry (no arguments) instructions in bytes */
- .if .locsz
- .ifle .locsz - 128 /* if locsz <= 128 */
- addi sp, sp, -.locsz
- .if .callsz
- s32i a0, sp, .locsz - 4
- .endif
- .elseif .callsz /* locsz > 128, with calls: */
- movi a9, .locsz - 16 /* note: a9 is caller-saved */
- addi sp, sp, -16
- s32i a0, sp, 12
- sub sp, sp, a9
- .else /* locsz > 128, no calls: */
- movi a9, .locsz
- sub sp, sp, a9
- .endif /* end */
- .endif
-#endif
- .endm
-
-
-
-/*----------------------------------------------------------------------
- * abi_return
- *
- * Generate proper function exit sequence for the current ABI
- * (windowed or call0). Takes care of freeing stack space and
- * restoring the return PC, if necessary.
- * NOTE: This macro MUST be invoked following a corresponding
- * abi_entry macro invocation. For call0 ABI in particular,
- * all stack and PC restoration are done according to the last
- * abi_entry macro invoked before this macro in the assembly file.
- *
- * Normally this macro takes no arguments. However to allow
- * for placing abi_return *before* abi_entry (as must be done
- * for some highly optimized assembly), it optionally takes
- * exactly the same arguments as abi_entry.
- */
-
- .macro abi_return locsize=-1, callsize=0
- .ifge \locsize
- abi_entry_size \locsize, \callsize
- .endif
-#if XCHAL_HAVE_WINDOWED && !__XTENSA_CALL0_ABI__
- retw
-#else
- .if .locsz
- .iflt .locsz - 128 /* if locsz < 128 */
- .if .callsz
- l32i a0, sp, .locsz - 4
- .endif
- addi sp, sp, .locsz
- .elseif .callsz /* locsz >= 128, with calls: */
- addi a9, sp, .locsz - 16
- l32i a0, a9, 12
- addi sp, a9, 16
- .else /* locsz >= 128, no calls: */
- movi a9, .locsz
- add sp, sp, a9
- .endif /* end */
- .endif
- ret
-#endif
- .endm
-
-
-/*
- * HW erratum fixes.
- */
-
- .macro hw_erratum_487_fix
-#if defined XSHAL_ERRATUM_487_FIX
- isync
-#endif
- .endm
-
-/*
- * These macros are internal, subject to change, and should not be used in
- * any new code.
- */
-
-#define _GBL(x) .global x
-#define _TYP(x) .type x,@function
-#define _ALN(x) .align x
-#define _SIZ(x) .size x, . - x
-#define _MKEND(x) .purgem endfunc ; .macro endfunc ; _SIZ(x) ; .purgem endfunc ; .macro endfunc ; .endm ; .endm
-#define _SYMT(x) _GBL(x); _MKEND(x); _TYP(x); _ALN(4); x:
-#define _SYM2(x) _GBL(x); _TYP(x); x:
-#define _SYM(x) _GBL(x); _MKEND(x); _ALN(4); x:
-.macro endfunc ; .endm
-
-/*
- * the DECLFUNC() macro provides a mechanism for implementing both the
- * standard and _nw interface with a single copy of the code.
- *
- * For Call0 ABI there is one function definition which is labeled with
- * both the xthal_..._nw and xthal_... symbols.
- *
- * For windowed ABI, two compilations are involved (one with the __NW_FUNCTION__
- * symbol defined) resulting in two separate functions (the _nw one without
- * the window adjustments).
-*/
-
-#if defined(__NW_FUNCTION__)
-# define DECLFUNC(x) _SYMT(x ## _nw)
-#else
-# if defined (__XTENSA_CALL0_ABI__)
-# define DECLFUNC(x) _SYMT(x); _SYM2(x ## _nw)
-# else
-# define DECLFUNC(x) _SYMT(x)
-# endif
-#endif
-
-#endif /*XTENSA_COREASM_H*/
-
diff --git a/src/arch/xtensa/include/xtensa/corebits.h b/src/arch/xtensa/include/xtensa/corebits.h
deleted file mode 100644
index c14dabc..0000000
--- a/src/arch/xtensa/include/xtensa/corebits.h
+++ /dev/null
@@ -1,193 +0,0 @@
-/*
- * xtensa/corebits.h - Xtensa Special Register field positions, masks, values.
- *
- * (In previous releases, these were defined in specreg.h, a generated file.
- * This file is not generated, ie. it is processor configuration independent.)
- */
-
-/* $Id: //depot/rel/Foxhill/dot.8/Xtensa/OS/include/xtensa/corebits.h#1 $ */
-
-/*
- * Copyright (c) 2005-2011 Tensilica Inc.
- *
- * Permission is hereby granted, free of charge, to any person obtaining
- * a copy of this software and associated documentation files (the
- * "Software"), to deal in the Software without restriction, including
- * without limitation the rights to use, copy, modify, merge, publish,
- * distribute, sublicense, and/or sell copies of the Software, and to
- * permit persons to whom the Software is furnished to do so, subject to
- * the following conditions:
- *
- * The above copyright notice and this permission notice shall be included
- * in all copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
- * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
- * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
- * IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY
- * CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
- * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
- * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
- */
-
-#ifndef XTENSA_COREBITS_H
-#define XTENSA_COREBITS_H
-
-/* EXCCAUSE register fields: */
-#define EXCCAUSE_EXCCAUSE_SHIFT 0
-#define EXCCAUSE_EXCCAUSE_MASK 0x3F
-/* EXCCAUSE register values: */
-/*
- * General Exception Causes
- * (values of EXCCAUSE special register set by general exceptions,
- * which vector to the user, kernel, or double-exception vectors).
- */
-#define EXCCAUSE_ILLEGAL 0 /* Illegal Instruction */
-#define EXCCAUSE_SYSCALL 1 /* System Call (SYSCALL instruction) */
-#define EXCCAUSE_INSTR_ERROR 2 /* Instruction Fetch Error */
-# define EXCCAUSE_IFETCHERROR 2 /* (backward compatibility macro, deprecated, avoid) */
-#define EXCCAUSE_LOAD_STORE_ERROR 3 /* Load Store Error */
-# define EXCCAUSE_LOADSTOREERROR 3 /* (backward compatibility macro, deprecated, avoid) */
-#define EXCCAUSE_LEVEL1_INTERRUPT 4 /* Level 1 Interrupt */
-# define EXCCAUSE_LEVEL1INTERRUPT 4 /* (backward compatibility macro, deprecated, avoid) */
-#define EXCCAUSE_ALLOCA 5 /* Stack Extension Assist (MOVSP instruction) for alloca */
-#define EXCCAUSE_DIVIDE_BY_ZERO 6 /* Integer Divide by Zero */
-#define EXCCAUSE_SPECULATION 7 /* Use of Failed Speculative Access (not implemented) */
-#define EXCCAUSE_PRIVILEGED 8 /* Privileged Instruction */
-#define EXCCAUSE_UNALIGNED 9 /* Unaligned Load or Store */
-/* Reserved 10..11 */
-#define EXCCAUSE_INSTR_DATA_ERROR 12 /* PIF Data Error on Instruction Fetch (RB-200x and later) */
-#define EXCCAUSE_LOAD_STORE_DATA_ERROR 13 /* PIF Data Error on Load or Store (RB-200x and later) */
-#define EXCCAUSE_INSTR_ADDR_ERROR 14 /* PIF Address Error on Instruction Fetch (RB-200x and later) */
-#define EXCCAUSE_LOAD_STORE_ADDR_ERROR 15 /* PIF Address Error on Load or Store (RB-200x and later) */
-#define EXCCAUSE_ITLB_MISS 16 /* ITLB Miss (no ITLB entry matches, hw refill also missed) */
-#define EXCCAUSE_ITLB_MULTIHIT 17 /* ITLB Multihit (multiple ITLB entries match) */
-#define EXCCAUSE_INSTR_RING 18 /* Ring Privilege Violation on Instruction Fetch */
-/* Reserved 19 */ /* Size Restriction on IFetch (not implemented) */
-#define EXCCAUSE_INSTR_PROHIBITED 20 /* Cache Attribute does not allow Instruction Fetch */
-/* Reserved 21..23 */
-#define EXCCAUSE_DTLB_MISS 24 /* DTLB Miss (no DTLB entry matches, hw refill also missed) */
-#define EXCCAUSE_DTLB_MULTIHIT 25 /* DTLB Multihit (multiple DTLB entries match) */
-#define EXCCAUSE_LOAD_STORE_RING 26 /* Ring Privilege Violation on Load or Store */
-/* Reserved 27 */ /* Size Restriction on Load/Store (not implemented) */
-#define EXCCAUSE_LOAD_PROHIBITED 28 /* Cache Attribute does not allow Load */
-#define EXCCAUSE_STORE_PROHIBITED 29 /* Cache Attribute does not allow Store */
-/* Reserved 30..31 */
-#define EXCCAUSE_CP_DISABLED(n) (32+(n)) /* Access to Coprocessor 'n' when disabled */
-#define EXCCAUSE_CP0_DISABLED 32 /* Access to Coprocessor 0 when disabled */
-#define EXCCAUSE_CP1_DISABLED 33 /* Access to Coprocessor 1 when disabled */
-#define EXCCAUSE_CP2_DISABLED 34 /* Access to Coprocessor 2 when disabled */
-#define EXCCAUSE_CP3_DISABLED 35 /* Access to Coprocessor 3 when disabled */
-#define EXCCAUSE_CP4_DISABLED 36 /* Access to Coprocessor 4 when disabled */
-#define EXCCAUSE_CP5_DISABLED 37 /* Access to Coprocessor 5 when disabled */
-#define EXCCAUSE_CP6_DISABLED 38 /* Access to Coprocessor 6 when disabled */
-#define EXCCAUSE_CP7_DISABLED 39 /* Access to Coprocessor 7 when disabled */
-/* Reserved 40..63 */
-
-/* PS register fields: */
-#define PS_WOE_SHIFT 18
-#define PS_WOE_MASK 0x00040000
-#define PS_WOE PS_WOE_MASK
-#define PS_CALLINC_SHIFT 16
-#define PS_CALLINC_MASK 0x00030000
-#define PS_CALLINC(n) (((n)&3)<<PS_CALLINC_SHIFT) /* n = 0..3 */
-#define PS_OWB_SHIFT 8
-#define PS_OWB_MASK 0x00000F00
-#define PS_OWB(n) (((n)&15)<<PS_OWB_SHIFT) /* n = 0..15 (or 0..7) */
-#define PS_RING_SHIFT 6
-#define PS_RING_MASK 0x000000C0
-#define PS_RING(n) (((n)&3)<<PS_RING_SHIFT) /* n = 0..3 */
-#define PS_UM_SHIFT 5
-#define PS_UM_MASK 0x00000020
-#define PS_UM PS_UM_MASK
-#define PS_EXCM_SHIFT 4
-#define PS_EXCM_MASK 0x00000010
-#define PS_EXCM PS_EXCM_MASK
-#define PS_INTLEVEL_SHIFT 0
-#define PS_INTLEVEL_MASK 0x0000000F
-#define PS_INTLEVEL(n) ((n)&PS_INTLEVEL_MASK) /* n = 0..15 */
-/* ABI-derived field values: */
-#ifdef __XTENSA_CALL0_ABI__
-#define PS_WOE_ABI 0
-#define PS_WOECALL4_ABI 0
-#else
-#define PS_WOE_ABI PS_WOE /* 0x40000 */
-#define PS_WOECALL4_ABI (PS_WOE | PS_CALLINC(1)) /* 0x50000, per call4 */
-#endif
-/* Backward compatibility (deprecated): */
-#define PS_PROGSTACK_SHIFT PS_UM_SHIFT
-#define PS_PROGSTACK_MASK PS_UM_MASK
-#define PS_PROG_SHIFT PS_UM_SHIFT
-#define PS_PROG_MASK PS_UM_MASK
-#define PS_PROG PS_UM
-
-/* DBREAKCn register fields: */
-#define DBREAKC_MASK_SHIFT 0
-#define DBREAKC_MASK_MASK 0x0000003F
-#define DBREAKC_LOADBREAK_SHIFT 30
-#define DBREAKC_LOADBREAK_MASK 0x40000000
-#define DBREAKC_STOREBREAK_SHIFT 31
-#define DBREAKC_STOREBREAK_MASK 0x80000000
-
-/* DEBUGCAUSE register fields: */
-#define DEBUGCAUSE_DEBUGINT_SHIFT 5
-#define DEBUGCAUSE_DEBUGINT_MASK 0x20 /* debug interrupt */
-#define DEBUGCAUSE_BREAKN_SHIFT 4
-#define DEBUGCAUSE_BREAKN_MASK 0x10 /* BREAK.N instruction */
-#define DEBUGCAUSE_BREAK_SHIFT 3
-#define DEBUGCAUSE_BREAK_MASK 0x08 /* BREAK instruction */
-#define DEBUGCAUSE_DBREAK_SHIFT 2
-#define DEBUGCAUSE_DBREAK_MASK 0x04 /* DBREAK match */
-#define DEBUGCAUSE_IBREAK_SHIFT 1
-#define DEBUGCAUSE_IBREAK_MASK 0x02 /* IBREAK match */
-#define DEBUGCAUSE_ICOUNT_SHIFT 0
-#define DEBUGCAUSE_ICOUNT_MASK 0x01 /* ICOUNT would increment to zero */
-
-/* MESR register fields: */
-#define MESR_MEME 0x00000001 /* memory error */
-#define MESR_MEME_SHIFT 0
-#define MESR_DME 0x00000002 /* double memory error */
-#define MESR_DME_SHIFT 1
-#define MESR_RCE 0x00000010 /* recorded memory error */
-#define MESR_RCE_SHIFT 4
-#define MESR_LCE
-#define MESR_LCE_SHIFT ?
-#define MESR_LCE_L
-#define MESR_ERRENAB 0x00000100
-#define MESR_ERRENAB_SHIFT 8
-#define MESR_ERRTEST 0x00000200
-#define MESR_ERRTEST_SHIFT 9
-#define MESR_DATEXC 0x00000400
-#define MESR_DATEXC_SHIFT 10
-#define MESR_INSEXC 0x00000800
-#define MESR_INSEXC_SHIFT 11
-#define MESR_WAYNUM_SHIFT 16
-#define MESR_ACCTYPE_SHIFT 20
-#define MESR_MEMTYPE_SHIFT 24
-#define MESR_ERRTYPE_SHIFT 30
-
-/* MEMCTL register fields: */
-#define MEMCTL_SNOOP_EN_SHIFT 1
-#define MEMCTL_SNOOP_EN 0x02 /* enable snoop responses (default 0) */
-#define MEMCTL_L0IBUF_EN_SHIFT 0
-#define MEMCTL_L0IBUF_EN 0x01 /* enable loop instr. buffer (default 1) */
-#define MEMCTL_INV_EN_SHIFT 23
-#define MEMCTL_INV_EN 0x00800000 /* invalidate cache ways being increased */
-#define MEMCTL_DCWU_SHIFT 8
-#define MEMCTL_DCWU_BITS 5
-#define MEMCTL_DCWA_SHIFT 13
-#define MEMCTL_DCWA_BITS 5
-#define MEMCTL_ICWU_SHIFT 18
-#define MEMCTL_ICWU_BITS 5
-#define MEMCTL_DCWU_MASK 0x00001F00 /* Bits 8-12 dcache ways in use */
-#define MEMCTL_DCWA_MASK 0x0003E000 /* Bits 13-17 dcache ways allocatable */
-#define MEMCTL_ICWU_MASK 0x007C0000 /* Bits 18-22 icache ways in use */
-#define MEMCTL_DCWU_CLR_MASK ~(MEMCTL_DCWU_MASK)
-#define MEMCTL_DCWA_CLR_MASK ~(MEMCTL_DCWA_MASK)
-#define MEMCTL_ICWU_CLR_MASK ~(MEMCTL_ICWU_MASK)
-#define MEMCTL_DCW_CLR_MASK (MEMCTL_DCWU_CLR_MASK | MEMCTL_DCWA_CLR_MASK)
-#define MEMCTL_IDCW_CLR_MASK (MEMCTL_DCW_CLR_MASK | MEMCTL_ICWU_CLR_MASK)
-
-
-#endif /*XTENSA_COREBITS_H*/
-
diff --git a/src/arch/xtensa/include/xtensa/hal.h b/src/arch/xtensa/include/xtensa/hal.h
deleted file mode 100644
index 9db5df3..0000000
--- a/src/arch/xtensa/include/xtensa/hal.h
+++ /dev/null
@@ -1,1518 +0,0 @@
-/*
- xtensa/hal.h -- contains a definition of the Core HAL interface
-
- All definitions in this header file are independent of any specific
- Xtensa processor configuration. Thus software (eg. OS, application,
- etc) can include this header file and be compiled into configuration-
- independent objects that can be distributed and eventually linked
- to the HAL library (libhal.a) to create a configuration-specific
- final executable.
-
- Certain definitions, however, are release/version-specific -- such as
- the XTHAL_RELEASE_xxx macros (or additions made in later versions).
-
-
- $Id: //depot/rel/Foxhill/dot.8/Xtensa/OS/target-os-src/hal.h.tpp#1 $
-
- Copyright (c) 1999-2015 Cadence Design Systems, Inc.
-
- Permission is hereby granted, free of charge, to any person obtaining
- a copy of this software and associated documentation files (the
- "Software"), to deal in the Software without restriction, including
- without limitation the rights to use, copy, modify, merge, publish,
- distribute, sublicense, and/or sell copies of the Software, and to
- permit persons to whom the Software is furnished to do so, subject to
- the following conditions:
-
- The above copyright notice and this permission notice shall be included
- in all copies or substantial portions of the Software.
-
- THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
- EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
- MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
- IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY
- CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
- TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
- SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
-*/
-
-#ifndef XTENSA_HAL_H
-#define XTENSA_HAL_H
-
-
-/****************************************************************************
- Definitions Useful for Any Code, USER or PRIVILEGED
- ****************************************************************************/
-
-
-/*----------------------------------------------------------------------
- Constant Definitions (shared with assembly)
- ----------------------------------------------------------------------*/
-
-/*
- * Software (Xtensa Tools) version information. Not configuration-specific!
- *
- * NOTE: "release" is a misnomer here, these are really product "version"
- * numbers. A "release" is a collection of product versions
- * made available at once (together) to customers.
- * In the past, release and version names all matched in T####.# form,
- * making the distinction irrelevant. This is no longer the case.
- */
-#define XTHAL_RELEASE_MAJOR 12000
-#define XTHAL_RELEASE_MINOR 8
-#define XTHAL_RELEASE_NAME "12.0.8"
-#define XTHAL_REL_12 1
-#define XTHAL_REL_12_0 1
-#define XTHAL_REL_12_0_8 1
-
-/* HAL version numbers (these names are for backward compatibility): */
-#define XTHAL_MAJOR_REV XTHAL_RELEASE_MAJOR
-#define XTHAL_MINOR_REV XTHAL_RELEASE_MINOR
-/*
- * A bit of software release/version history on values of XTHAL_{MAJOR,MINOR}_REV:
- *
- * SW Version MAJOR MINOR Comment
- * ======= ===== ===== =======
- * T1015.n n/a n/a (HAL not yet available)
- * T1020.{0,1,2} 0 1 (HAL beta)
- * T1020.{3,4} 0 2 First release.
- * T1020.n (n>4) 0 2 or >3 (TBD)
- * T1030.0 0 1 (HAL beta)
- * T1030.{1,2} 0 3 Equivalent to first release.
- * T1030.n (n>=3) 0 >= 3 (TBD)
- * T1040.n 1040 n Full CHAL available from T1040.2
- * T1050.n 1050 n .
- * 6.0.n 6000 n Xtensa Tools v6 (RA-200x.n)
- * 7.0.n 7000 n Xtensa Tools v7 (RB-200x.n)
- * 7.1.n 7010 n Xtensa Tools v7.1 (RB-200x.(n+2))
- * 8.0.n 8000 n Xtensa Tools v8 (RC-20xx.n)
- * 9.0.n 9000 n Xtensa Tools v9 (RD-201x.n)
- * 10.0.n 10000 n Xtensa Tools v10 (RE-201x.n)
- *
- *
- * Note: there is a distinction between the software version with
- * which something is compiled (accessible using XTHAL_RELEASE_* macros)
- * and the software version with which the HAL library was compiled
- * (accessible using Xthal_release_* global variables). This
- * distinction is particularly relevant for vendors that distribute
- * configuration-independent binaries (eg. an OS), where their customer
- * might link it with a HAL of a different Xtensa software version.
- * In this case, it may be appropriate for the OS to verify at run-time
- * whether XTHAL_RELEASE_* and Xthal_release_* are compatible.
- * [Guidelines as to which version is compatible with which are not
- * currently provided explicitly, but might be inferred from reading
- * OSKit documentation for all releases -- compatibility is also highly
- * dependent on which HAL features are used. Each version is usually
- * backward compatible, with very few exceptions if any.]
- */
-
-/* Version comparison operators (among major/minor pairs): */
-#define XTHAL_REL_GE(maja,mina, majb,minb) ((maja) > (majb) || \
- ((maja) == (majb) && (mina) >= (minb)))
-#define XTHAL_REL_GT(maja,mina, majb,minb) ((maja) > (majb) || \
- ((maja) == (majb) && (mina) > (minb)))
-#define XTHAL_REL_LE(maja,mina, majb,minb) ((maja) < (majb) || \
- ((maja) == (majb) && (mina) <= (minb)))
-#define XTHAL_REL_LT(maja,mina, majb,minb) ((maja) < (majb) || \
- ((maja) == (majb) && (mina) < (minb)))
-#define XTHAL_REL_EQ(maja,mina, majb,minb) ((maja) == (majb) && (mina) == (minb))
-
-/* Fuzzy (3-way) logic operators: */
-#define XTHAL_MAYBE -1 /* 0=NO, 1=YES, -1=MAYBE */
-#define XTHAL_FUZZY_AND(a,b) (((a)==0 || (b)==0) ? 0 : ((a)==1 && (b)==1) ? 1 : XTHAL_MAYBE)
-#define XTHAL_FUZZY_OR(a,b) (((a)==1 || (b)==1) ? 1 : ((a)==0 && (b)==0) ? 0 : XTHAL_MAYBE)
-#define XTHAL_FUZZY_NOT(a) (((a)==0 || (a)==1) ? (1-(a)) : XTHAL_MAYBE)
-
-
-/*
- * Architectural limit, independent of configuration:
- */
-#define XTHAL_MAX_CPS 8 /* max number of coprocessors (0..7) */
-
-/* Misc: */
-#define XTHAL_LITTLEENDIAN 0
-#define XTHAL_BIGENDIAN 1
-
-
-
-#if !defined(_ASMLANGUAGE) && !defined(_NOCLANGUAGE) && !defined(__ASSEMBLER__)
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-/*----------------------------------------------------------------------
- HAL
- ----------------------------------------------------------------------*/
-
-/* Constant to be checked in build = (XTHAL_MAJOR_REV<<16)|XTHAL_MINOR_REV */
-extern const unsigned int Xthal_rev_no;
-
-
-/*----------------------------------------------------------------------
- Optional/Custom Processor State
- ----------------------------------------------------------------------*/
-
-/* save & restore the extra processor state */
-extern void xthal_save_extra(void *base);
-extern void xthal_restore_extra(void *base);
-
-extern void xthal_save_cpregs(void *base, int);
-extern void xthal_restore_cpregs(void *base, int);
-/* versions specific to each coprocessor id */
-extern void xthal_save_cp0(void *base);
-extern void xthal_save_cp1(void *base);
-extern void xthal_save_cp2(void *base);
-extern void xthal_save_cp3(void *base);
-extern void xthal_save_cp4(void *base);
-extern void xthal_save_cp5(void *base);
-extern void xthal_save_cp6(void *base);
-extern void xthal_save_cp7(void *base);
-extern void xthal_restore_cp0(void *base);
-extern void xthal_restore_cp1(void *base);
-extern void xthal_restore_cp2(void *base);
-extern void xthal_restore_cp3(void *base);
-extern void xthal_restore_cp4(void *base);
-extern void xthal_restore_cp5(void *base);
-extern void xthal_restore_cp6(void *base);
-extern void xthal_restore_cp7(void *base);
-/* pointers to each of the functions above */
-extern void* Xthal_cpregs_save_fn[XTHAL_MAX_CPS];
-extern void* Xthal_cpregs_restore_fn[XTHAL_MAX_CPS];
-/* similarly for non-windowed ABI (may be same or different) */
-extern void* Xthal_cpregs_save_nw_fn[XTHAL_MAX_CPS];
-extern void* Xthal_cpregs_restore_nw_fn[XTHAL_MAX_CPS];
-
-/*extern void xthal_save_all_extra(void *base);*/
-/*extern void xthal_restore_all_extra(void *base);*/
-
-/* space for processor state */
-extern const unsigned int Xthal_extra_size;
-extern const unsigned int Xthal_extra_align;
-extern const unsigned int Xthal_cpregs_size[XTHAL_MAX_CPS];
-extern const unsigned int Xthal_cpregs_align[XTHAL_MAX_CPS];
-extern const unsigned int Xthal_all_extra_size;
-extern const unsigned int Xthal_all_extra_align;
-/* coprocessor names */
-extern const char * const Xthal_cp_names[XTHAL_MAX_CPS];
-
-/* initialize the extra processor */
-/*extern void xthal_init_extra(void);*/
-/* initialize the TIE coprocessor */
-/*extern void xthal_init_cp(int);*/
-
-/* initialize the extra processor */
-extern void xthal_init_mem_extra(void *);
-/* initialize the TIE coprocessor */
-extern void xthal_init_mem_cp(void *, int);
-
-/* the number of TIE coprocessors contiguous from zero (for Tor2) */
-extern const unsigned int Xthal_num_coprocessors;
-
-/* actual number of coprocessors */
-extern const unsigned char Xthal_cp_num;
-/* index of highest numbered coprocessor, plus one */
-extern const unsigned char Xthal_cp_max;
-/* index of highest allowed coprocessor number, per cfg, plus one */
-/*extern const unsigned char Xthal_cp_maxcfg;*/
-/* bitmask of which coprocessors are present */
-extern const unsigned int Xthal_cp_mask;
-
-/* read & write extra state register */
-/*extern int xthal_read_extra(void *base, unsigned reg, unsigned *value);*/
-/*extern int xthal_write_extra(void *base, unsigned reg, unsigned value);*/
-
-/* read & write a TIE coprocessor register */
-/*extern int xthal_read_cpreg(void *base, int cp, unsigned reg, unsigned *value);*/
-/*extern int xthal_write_cpreg(void *base, int cp, unsigned reg, unsigned value);*/
-
-/* return coprocessor number based on register */
-/*extern int xthal_which_cp(unsigned reg);*/
-
-
-/*----------------------------------------------------------------------
- Register Windows
- ----------------------------------------------------------------------*/
-
-/* number of registers in register window */
-extern const unsigned int Xthal_num_aregs;
-extern const unsigned char Xthal_num_aregs_log2;
-
-
-/*----------------------------------------------------------------------
- Cache
- ----------------------------------------------------------------------*/
-
-/* size of the cache lines in log2(bytes) */
-extern const unsigned char Xthal_icache_linewidth;
-extern const unsigned char Xthal_dcache_linewidth;
-/* size of the cache lines in bytes (2^linewidth) */
-extern const unsigned short Xthal_icache_linesize;
-extern const unsigned short Xthal_dcache_linesize;
-
-/* size of the caches in bytes (ways * 2^(linewidth + setwidth)) */
-extern const unsigned int Xthal_icache_size;
-extern const unsigned int Xthal_dcache_size;
-/* cache features */
-extern const unsigned char Xthal_dcache_is_writeback;
-
-/* cache region operations*/
-extern void xthal_icache_region_invalidate( void *addr, unsigned size );
-extern void xthal_dcache_region_invalidate( void *addr, unsigned size );
-extern void xthal_dcache_region_writeback( void *addr, unsigned size );
-extern void xthal_dcache_region_writeback_inv( void *addr, unsigned size );
-
-#ifndef XTHAL_USE_CACHE_MACROS
-/* cache line operations*/
-extern void xthal_icache_line_invalidate(void *addr);
-extern void xthal_dcache_line_invalidate(void *addr);
-extern void xthal_dcache_line_writeback(void *addr);
-extern void xthal_dcache_line_writeback_inv(void *addr);
-/* sync icache and memory */
-extern void xthal_icache_sync( void );
-/* sync dcache and memory */
-extern void xthal_dcache_sync( void );
-#endif
-
-/* get/set number of icache ways enabled */
-extern unsigned int xthal_icache_get_ways(void);
-extern void xthal_icache_set_ways(unsigned int ways);
-/* get/set number of dcache ways enabled */
-extern unsigned int xthal_dcache_get_ways(void);
-extern void xthal_dcache_set_ways(unsigned int ways);
-
-/* coherency (low-level -- not normally called directly) */
-extern void xthal_cache_coherence_on( void );
-extern void xthal_cache_coherence_off( void );
-/* coherency (high-level) */
-extern void xthal_cache_coherence_optin( void );
-extern void xthal_cache_coherence_optout( void );
-
-/*
- * Cache prefetch control.
- * The parameter to xthal_set_cache_prefetch() contains both
- * a PREFCTL register value and a mask of which bits to actually modify.
- * This allows easily combining field macros (below) by ORing,
- * leaving unspecified fields unmodified.
- *
- * For backward compatibility with the older version of this routine
- * (that took 15-bit value and mask in a 32-bit parameter, for pre-RF
- * cores with only the lower 15 bits of PREFCTL defined), the 32-bit
- * value and mask are staggered as follows in a 64-bit parameter:
- * param[63:48] are PREFCTL[31:16] if param[31] is set
- * param[47:32] are mask[31:16] if param[31] is set
- * param[31] is set if mask is used, 0 if not
- * param[31:16] are mask[15:0] if param[31] is set
- * param[31:16] are PREFCTL[31:16] if param[31] is clear
- * param[15:0] are PREFCTL[15:0]
- *
- * Limitation: PREFCTL register bit 31 cannot be set without masking,
- * and bit 15 must always be set when using masking, so it is hoped that
- * these two bits will remain reserved, read-as-zero in PREFCTL.
- */
-#define XTHAL_PREFETCH_ENABLE -1 /* enable inst+data prefetch */
-#define XTHAL_PREFETCH_DISABLE 0xFFFF0000 /* disab inst+data prefetch*/
-#define XTHAL_DCACHE_PREFETCH(n) (0x800F0000+((n)&0xF)) /* data-side */
-#define XTHAL_DCACHE_PREFETCH_OFF XTHAL_DCACHE_PREFETCH(0) /* disable */
-#define XTHAL_DCACHE_PREFETCH_LOW XTHAL_DCACHE_PREFETCH(4) /* less aggr.*/
-#define XTHAL_DCACHE_PREFETCH_MEDIUM XTHAL_DCACHE_PREFETCH(5) /* mid aggr. */
-#define XTHAL_DCACHE_PREFETCH_HIGH XTHAL_DCACHE_PREFETCH(8) /* more aggr.*/
-#define XTHAL_DCACHE_PREFETCH_L1_OFF 0x90000000 /* to prefetch buffers*/
-#define XTHAL_DCACHE_PREFETCH_L1 0x90001000 /* direct to L1 dcache*/
-#define XTHAL_ICACHE_PREFETCH(n) (0x80F00000+(((n)&0xF)<<4)) /* i-side */
-#define XTHAL_ICACHE_PREFETCH_OFF XTHAL_ICACHE_PREFETCH(0) /* disable */
-#define XTHAL_ICACHE_PREFETCH_LOW XTHAL_ICACHE_PREFETCH(4) /* less aggr.*/
-#define XTHAL_ICACHE_PREFETCH_MEDIUM XTHAL_ICACHE_PREFETCH(5) /* mid aggr. */
-#define XTHAL_ICACHE_PREFETCH_HIGH XTHAL_ICACHE_PREFETCH(8) /* more aggr.*/
-#define XTHAL_ICACHE_PREFETCH_L1_OFF 0xA0000000 /* (not implemented) */
-#define XTHAL_ICACHE_PREFETCH_L1 0xA0002000 /* (not implemented) */
-#define _XTHAL_PREFETCH_BLOCKS(n) ((n)<0?0:(n)<5?(n):(n)<15?((n)>>1)+2:9)
-#define XTHAL_PREFETCH_BLOCKS(n) (0x0000000F80000000ULL + \
- (((unsigned long long)_XTHAL_PREFETCH_BLOCKS(n))<<48))
-
-extern int xthal_get_cache_prefetch( void );
-extern int xthal_set_cache_prefetch( int );
-extern int xthal_set_cache_prefetch_long( unsigned long long );
-/* Only use the new extended function from now on: */
-#define xthal_set_cache_prefetch xthal_set_cache_prefetch_long
-#define xthal_set_cache_prefetch_nw xthal_set_cache_prefetch_long_nw
-
-
-/*----------------------------------------------------------------------
- Debug
- ----------------------------------------------------------------------*/
-
-/* 1 if debug option configured, 0 if not: */
-extern const int Xthal_debug_configured;
-
-/* Set (plant) and remove software breakpoint, both synchronizing cache: */
-extern unsigned int xthal_set_soft_break(void *addr);
-extern void xthal_remove_soft_break(void *addr, unsigned int);
-
-
-/*----------------------------------------------------------------------
- Disassembler
- ----------------------------------------------------------------------*/
-
-/* Max expected size of the return buffer for a disassembled instruction (hint only): */
-#define XTHAL_DISASM_BUFSIZE 80
-
-/* Disassembly option bits for selecting what to return: */
-#define XTHAL_DISASM_OPT_ADDR 0x0001 /* display address */
-#define XTHAL_DISASM_OPT_OPHEX 0x0002 /* display opcode bytes in hex */
-#define XTHAL_DISASM_OPT_OPCODE 0x0004 /* display opcode name (mnemonic) */
-#define XTHAL_DISASM_OPT_PARMS 0x0008 /* display parameters */
-#define XTHAL_DISASM_OPT_ALL 0x0FFF /* display everything */
-
-/* routine to get a string for the disassembled instruction */
-extern int xthal_disassemble( unsigned char *instr_buf, void *tgt_addr,
- char *buffer, unsigned buflen, unsigned options );
-
-/* routine to get the size of the next instruction. Returns 0 for
- illegal instruction */
-extern int xthal_disassemble_size( unsigned char *instr_buf );
-
-
-/*----------------------------------------------------------------------
- Instruction/Data RAM/ROM Access
- ----------------------------------------------------------------------*/
-
-extern void* xthal_memcpy(void *dst, const void *src, unsigned len);
-extern void* xthal_bcopy(const void *src, void *dst, unsigned len);
-
-
-/*----------------------------------------------------------------------
- MP Synchronization
- ----------------------------------------------------------------------*/
-
-extern int xthal_compare_and_set( int *addr, int test_val, int compare_val );
-
-/*extern const char Xthal_have_s32c1i;*/
-
-
-/*----------------------------------------------------------------------
- Miscellaneous
- ----------------------------------------------------------------------*/
-
-extern const unsigned int Xthal_release_major;
-extern const unsigned int Xthal_release_minor;
-extern const char * const Xthal_release_name;
-extern const char * const Xthal_release_internal;
-
-extern const unsigned char Xthal_memory_order;
-extern const unsigned char Xthal_have_windowed;
-extern const unsigned char Xthal_have_density;
-extern const unsigned char Xthal_have_booleans;
-extern const unsigned char Xthal_have_loops;
-extern const unsigned char Xthal_have_nsa;
-extern const unsigned char Xthal_have_minmax;
-extern const unsigned char Xthal_have_sext;
-extern const unsigned char Xthal_have_clamps;
-extern const unsigned char Xthal_have_mac16;
-extern const unsigned char Xthal_have_mul16;
-extern const unsigned char Xthal_have_fp;
-extern const unsigned char Xthal_have_speculation;
-extern const unsigned char Xthal_have_threadptr;
-
-extern const unsigned char Xthal_have_pif;
-extern const unsigned short Xthal_num_writebuffer_entries;
-
-extern const unsigned int Xthal_build_unique_id;
-/* Version info for hardware targeted by software upgrades: */
-extern const unsigned int Xthal_hw_configid0;
-extern const unsigned int Xthal_hw_configid1;
-extern const unsigned int Xthal_hw_release_major;
-extern const unsigned int Xthal_hw_release_minor;
-extern const char * const Xthal_hw_release_name;
-extern const char * const Xthal_hw_release_internal;
-
-/* Clear any remnant code-dependent state (i.e. clear loop count regs). */
-extern void xthal_clear_regcached_code( void );
-
-#ifdef __cplusplus
-}
-#endif
-#endif /*!_ASMLANGUAGE && !_NOCLANGUAGE && !__ASSEMBLER__ */
-
-
-
-
-
-/****************************************************************************
- Definitions Useful for PRIVILEGED (Supervisory or Non-Virtualized) Code
- ****************************************************************************/
-
-
-#ifndef XTENSA_HAL_NON_PRIVILEGED_ONLY
-
-/*----------------------------------------------------------------------
- Constant Definitions (shared with assembly)
- ----------------------------------------------------------------------*/
-
-/*
- * Architectural limits, independent of configuration.
- * Note that these are ISA-defined limits, not micro-architecture implementation
- * limits enforced by the Xtensa Processor Generator (which may be stricter than
- * these below).
- */
-#define XTHAL_MAX_INTERRUPTS 32 /* max number of interrupts (0..31) */
-#define XTHAL_MAX_INTLEVELS 16 /* max number of interrupt levels (0..15) */
- /* (as of T1040, implementation limit is 7: 0..6) */
-#define XTHAL_MAX_TIMERS 4 /* max number of timers (CCOMPARE0..CCOMPARE3) */
- /* (as of T1040, implementation limit is 3: 0..2) */
-
-/* Interrupt types: */
-#define XTHAL_INTTYPE_UNCONFIGURED 0
-#define XTHAL_INTTYPE_SOFTWARE 1
-#define XTHAL_INTTYPE_EXTERN_EDGE 2
-#define XTHAL_INTTYPE_EXTERN_LEVEL 3
-#define XTHAL_INTTYPE_TIMER 4
-#define XTHAL_INTTYPE_NMI 5
-#define XTHAL_INTTYPE_WRITE_ERROR 6
-#define XTHAL_INTTYPE_PROFILING 7
-#define XTHAL_INTTYPE_IDMA_DONE 8
-#define XTHAL_INTTYPE_IDMA_ERR 9
-#define XTHAL_INTTYPE_GS_ERR 10
-#define XTHAL_INTTYPE_SG_ERR 10 /* backward compatibility name - deprecated */
-#define XTHAL_MAX_INTTYPES 11 /* number of interrupt types */
-
-/* Timer related: */
-#define XTHAL_TIMER_UNCONFIGURED -1 /* Xthal_timer_interrupt[] value for non-existent timers */
-#define XTHAL_TIMER_UNASSIGNED XTHAL_TIMER_UNCONFIGURED /* (for backwards compatibility only) */
-
-/* Local Memory ECC/Parity: */
-#define XTHAL_MEMEP_PARITY 1
-#define XTHAL_MEMEP_ECC 2
-/* Flags parameter to xthal_memep_inject_error(): */
-#define XTHAL_MEMEP_F_LOCAL 0 /* local memory (default) */
-#define XTHAL_MEMEP_F_DCACHE_DATA 4 /* data cache data */
-#define XTHAL_MEMEP_F_DCACHE_TAG 5 /* data cache tag */
-#define XTHAL_MEMEP_F_ICACHE_DATA 6 /* instruction cache data */
-#define XTHAL_MEMEP_F_ICACHE_TAG 7 /* instruction cache tag */
-#define XTHAL_MEMEP_F_CORRECTABLE 16 /* inject correctable error
- (default is non-corr.) */
-
-
-/* Access Mode bits (tentative): */ /* bit abbr unit short_name PPC equ - Description */
-#define XTHAL_AMB_EXCEPTION 0 /* 001 E EX fls: EXception none
- exception on any access (aka "illegal") */
-#define XTHAL_AMB_HITCACHE 1 /* 002 C CH fls: use Cache on Hit ~(I CI)
- [or H HC] way from tag match;
- [or U UC] (ISA: same except Isolate case) */
-#define XTHAL_AMB_ALLOCATE 2 /* 004 A AL fl?: ALlocate none
- [or F FI fill] refill cache on miss, way from LRU
- (ISA: Read/Write Miss Refill) */
-#define XTHAL_AMB_WRITETHRU 3 /* 008 W WT --s: WriteThrough W WT
- store immediately to memory (ISA: same) */
-#define XTHAL_AMB_ISOLATE 4 /* 010 I IS fls: ISolate none
- use cache regardless of hit-vs-miss,
- way from vaddr (ISA: use-cache-on-miss+hit) */
-#define XTHAL_AMB_GUARD 5 /* 020 G GU ?l?: GUard G *
- non-speculative; spec/replay refs not permitted */
-#define XTHAL_AMB_COHERENT 6 /* 040 M MC ?ls: Mem/MP Coherent M
- on read, other CPU/bus-master may need to supply data;
- on write, maybe redirect to or flush other CPU dirty line; etc */
-#if 0
-#define XTHAL_AMB_BUFFERABLE x /* 000 B BU --s: BUfferable ?
- write response may return earlier than from final destination */
-#define XTHAL_AMB_ORDERED x /* 000 O OR fls: ORdered G *
- mem accesses cannot be out of order */
-#define XTHAL_AMB_FUSEWRITES x /* 000 F FW --s: FuseWrites none
- allow combining/merging/coalescing multiple writes
- (to same datapath data unit) into one
- (implied by writeback) */
-#define XTHAL_AMB_TRUSTED x /* 000 T TR ?l?: TRusted none
- memory will not bus error (if it does,
- handle as fatal imprecise interrupt) */
-#define XTHAL_AMB_PREFETCH x /* 000 P PR fl?: PRefetch none
- on refill, read line+1 into prefetch buffers */
-#define XTHAL_AMB_STREAM x /* 000 S ST ???: STreaming none
- access one of N stream buffers */
-#endif /*0*/
-
-#define XTHAL_AM_EXCEPTION (1<<XTHAL_AMB_EXCEPTION)
-#define XTHAL_AM_HITCACHE (1<<XTHAL_AMB_HITCACHE)
-#define XTHAL_AM_ALLOCATE (1<<XTHAL_AMB_ALLOCATE)
-#define XTHAL_AM_WRITETHRU (1<<XTHAL_AMB_WRITETHRU)
-#define XTHAL_AM_ISOLATE (1<<XTHAL_AMB_ISOLATE)
-#define XTHAL_AM_GUARD (1<<XTHAL_AMB_GUARD)
-#define XTHAL_AM_COHERENT (1<<XTHAL_AMB_COHERENT)
-#if 0
-#define XTHAL_AM_BUFFERABLE (1<<XTHAL_AMB_BUFFERABLE)
-#define XTHAL_AM_ORDERED (1<<XTHAL_AMB_ORDERED)
-#define XTHAL_AM_FUSEWRITES (1<<XTHAL_AMB_FUSEWRITES)
-#define XTHAL_AM_TRUSTED (1<<XTHAL_AMB_TRUSTED)
-#define XTHAL_AM_PREFETCH (1<<XTHAL_AMB_PREFETCH)
-#define XTHAL_AM_STREAM (1<<XTHAL_AMB_STREAM)
-#endif /*0*/
-
-/*
- * Allowed Access Modes (bit combinations).
- *
- * Columns are:
- * "FOGIWACE"
- * Access mode bits (see XTHAL_AMB_xxx above).
- * <letter> = bit is set
- * '-' = bit is clear
- * '.' = bit is irrelevant / don't care, as follows:
- * E=1 makes all others irrelevant
- * W,F relevant only for stores
- * "2345"
- * Indicates which Xtensa releases support the corresponding
- * access mode. Releases for each character column are:
- * 2 = prior to T1020.2: T1015 (V1.5), T1020.0, T1020.1
- * 3 = T1020.2 and later: T1020.2+, T1030
- * 4 = T1040
- * 5 = T1050 (maybe), LX1, LX2, LX2.1
- * 7 = LX2.2
- * 8 = LX3, LX4
- * 9 = LX5
- * And the character column contents are:
- * <number> = supported by release(s)
- * "." = unsupported by release(s)
- * "?" = support unknown
- */
- /* foMGIWACE 2345789 */
-/* For instruction fetch: */
-#define XTHAL_FAM_EXCEPTION 0x001 /* ........E 2345789 exception */
-/*efine XTHAL_FAM_ISOLATE*/ /*0x012*/ /* .---I.-C- ....... isolate */
-#define XTHAL_FAM_BYPASS 0x000 /* .----.--- 2345789 bypass */
-/*efine XTHAL_FAM_NACACHED*/ /*0x002*/ /* .----.-C- ....... cached no-allocate (frozen) */
-#define XTHAL_FAM_CACHED 0x006 /* .----.AC- 2345789 cached */
-/* For data load: */
-#define XTHAL_LAM_EXCEPTION 0x001 /* ........E 2345789 exception */
-#define XTHAL_LAM_ISOLATE 0x012 /* .---I.-C- 2345789 isolate */
-#define XTHAL_LAM_BYPASS 0x000 /* .O---.--- 2...... bypass speculative */
-#define XTHAL_LAM_BYPASSG 0x020 /* .O-G-.--- .345789 bypass guarded */
-#define XTHAL_LAM_CACHED_NOALLOC 0x002 /* .O---.-C- 2345789 cached no-allocate speculative */
-#define XTHAL_LAM_NACACHED XTHAL_LAM_CACHED_NOALLOC
-#define XTHAL_LAM_NACACHEDG 0x022 /* .O-G-.-C- .?..... cached no-allocate guarded */
-#define XTHAL_LAM_CACHED 0x006 /* .----.AC- 2345789 cached speculative */
-#define XTHAL_LAM_COHCACHED 0x046 /* .-M--.AC- ....*89 cached speculative MP-coherent */
-/* For data store: */
-#define XTHAL_SAM_EXCEPTION 0x001 /* ........E 2345789 exception */
-#define XTHAL_SAM_ISOLATE 0x032 /* .--GI--C- 2345789 isolate */
-#define XTHAL_SAM_BYPASS 0x028 /* -O-G-W--- 2345789 bypass */
-#define XTHAL_SAM_WRITETHRU 0x02A /* -O-G-W-C- 2345789 writethrough */
-/*efine XTHAL_SAM_WRITETHRU_ALLOC*/ /*0x02E*/ /* -O-G-WAC- ....... writethrough allocate */
-#define XTHAL_SAM_WRITEBACK 0x026 /* F--G--AC- ...5789 writeback */
-#define XTHAL_SAM_WRITEBACK_NOALLOC 0x022 /* ?--G---C- .....89 writeback no-allocate */
-#define XTHAL_SAM_COHWRITEBACK 0x066 /* F-MG--AC- ....*89 writeback MP-coherent */
-/* For PIF attributes: */ /* -PIwrWCBUUUU ...9 */
-#define XTHAL_PAM_BYPASS 0x000 /* xxx00000xxxx ...9 bypass non-bufferable */
-#define XTHAL_PAM_BYPASS_BUF 0x010 /* xxx0000bxxxx ...9 bypass */
-#define XTHAL_PAM_CACHED_NOALLOC 0x030 /* xxx0001bxxxx ...9 cached no-allocate */
-#define XTHAL_PAM_WRITETHRU 0x0B0 /* xxx0101bxxxx ...9 writethrough (WT) */
-#define XTHAL_PAM_WRITEBACK_NOALLOC 0x0F0 /* xxx0111bxxxx ...9 writeback no-alloc (WBNA) */
-#define XTHAL_PAM_WRITEBACK 0x1F0 /* xxx1111bxxxx ...9 writeback (WB) */
-/*efine XTHAL_PAM_NORMAL*/ /*0x050*/ /* xxx0010bxxxx .... (unimplemented) */
-/*efine XTHAL_PAM_WRITETHRU_WA*/ /*0x130*/ /* xxx1001bxxxx .... (unimplemented, less likely) */
-/*efine XTHAL_PAM_WRITETHRU_RWA*/ /*0x1B0*/ /* xxx1101bxxxx .... (unimplemented, less likely) */
-/*efine XTHAL_PAM_WRITEBACK_WA*/ /*0x170*/ /* xxx1011bxxxx .... (unimplemented, less likely) */
-
-
-#if 0
-/*
- Cache attribute encoding for CACHEATTR (per ISA):
- (Note: if this differs from ISA Ref Manual, ISA has precedence)
-
- Inst-fetches Loads Stores
- ------------- ------------ -------------
-0x0 FCA_EXCEPTION LCA_NACACHED SCA_WRITETHRU cached no-allocate (previously misnamed "uncached")
-0x1 FCA_CACHED LCA_CACHED SCA_WRITETHRU cached
-0x2 FCA_BYPASS LCA_BYPASS_G* SCA_BYPASS bypass cache (what most people call uncached)
-0x3 FCA_CACHED LCA_CACHED SCA_WRITEALLOCF write-allocate
- or LCA_EXCEPTION SCA_EXCEPTION (if unimplemented)
-0x4 FCA_CACHED LCA_CACHED SCA_WRITEBACK[M] write-back [MP-coherent]
- or LCA_EXCEPTION SCA_EXCEPTION (if unimplemented)
-0x5 FCA_CACHED LCA_CACHED SCA_WRITEBACK_NOALLOC write-back no-allocate
- or FCA_EXCEPTION LCA_EXCEPTION SCA_EXCEPTION (if unimplemented)
-0x6..D FCA_EXCEPTION LCA_EXCEPTION SCA_EXCEPTION (reserved)
-0xE FCA_EXCEPTION LCA_ISOLATE SCA_ISOLATE isolate
-0xF FCA_EXCEPTION LCA_EXCEPTION SCA_EXCEPTION illegal
- * Prior to T1020.2?, guard feature not supported, this defaulted to speculative (no _G)
-*/
-#endif /*0*/
-
-
-#if !defined(_ASMLANGUAGE) && !defined(_NOCLANGUAGE) && !defined(__ASSEMBLER__)
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-
-/*----------------------------------------------------------------------
- Register Windows
- ----------------------------------------------------------------------*/
-
-/* This spill any live register windows (other than the caller's):
- * (NOTE: current implementation require privileged code, but
- * a user-callable implementation is possible.) */
-extern void xthal_window_spill( void );
-
-
-/*----------------------------------------------------------------------
- Optional/Custom Processor State
- ----------------------------------------------------------------------*/
-
-/* validate & invalidate the TIE register file */
-extern void xthal_validate_cp(int);
-extern void xthal_invalidate_cp(int);
-
-/* read and write cpenable register */
-extern void xthal_set_cpenable(unsigned);
-extern unsigned xthal_get_cpenable(void);
-
-
-/*----------------------------------------------------------------------
- Interrupts
- ----------------------------------------------------------------------*/
-
-/* the number of interrupt levels */
-extern const unsigned char Xthal_num_intlevels;
-/* the number of interrupts */
-extern const unsigned char Xthal_num_interrupts;
-/* the highest level of interrupts masked by PS.EXCM */
-extern const unsigned char Xthal_excm_level;
-
-/* mask for level of interrupts */
-extern const unsigned int Xthal_intlevel_mask[XTHAL_MAX_INTLEVELS];
-/* mask for level 0 to N interrupts */
-extern const unsigned int Xthal_intlevel_andbelow_mask[XTHAL_MAX_INTLEVELS];
-
-/* level of each interrupt */
-extern const unsigned char Xthal_intlevel[XTHAL_MAX_INTERRUPTS];
-
-/* type per interrupt */
-extern const unsigned char Xthal_inttype[XTHAL_MAX_INTERRUPTS];
-
-/* masks of each type of interrupt */
-extern const unsigned int Xthal_inttype_mask[XTHAL_MAX_INTTYPES];
-
-/* interrupt numbers assigned to each timer interrupt */
-extern const int Xthal_timer_interrupt[XTHAL_MAX_TIMERS];
-
-/* INTENABLE,INTERRUPT,INTSET,INTCLEAR register access functions: */
-extern unsigned xthal_get_intenable( void );
-extern void xthal_set_intenable( unsigned );
-extern unsigned xthal_get_interrupt( void );
-#define xthal_get_intread xthal_get_interrupt /* backward compatibility */
-
-/* These two functions are deprecated. Use the newer functions
- xthal_interrupt_trigger and xthal_interrupt_clear instead. */
-extern void xthal_set_intset( unsigned );
-extern void xthal_set_intclear( unsigned );
-
-
-/*----------------------------------------------------------------------
- Debug
- ----------------------------------------------------------------------*/
-
-/* Number of instruction and data break registers: */
-extern const int Xthal_num_ibreak;
-extern const int Xthal_num_dbreak;
-
-
-/*----------------------------------------------------------------------
- Core Counter
- ----------------------------------------------------------------------*/
-
-/* counter info */
-extern const unsigned char Xthal_have_ccount; /* set if CCOUNT register present */
-extern const unsigned char Xthal_num_ccompare; /* number of CCOMPAREn registers */
-
-/* get CCOUNT register (if not present return 0) */
-extern unsigned xthal_get_ccount(void);
-
-/* set and get CCOMPAREn registers (if not present, get returns 0) */
-extern void xthal_set_ccompare(int, unsigned);
-extern unsigned xthal_get_ccompare(int);
-
-
-/*----------------------------------------------------------------------
- Miscellaneous
- ----------------------------------------------------------------------*/
-
-extern const unsigned char Xthal_have_prid;
-extern const unsigned char Xthal_have_exceptions;
-extern const unsigned char Xthal_xea_version;
-extern const unsigned char Xthal_have_interrupts;
-extern const unsigned char Xthal_have_highlevel_interrupts;
-extern const unsigned char Xthal_have_nmi;
-
-extern unsigned xthal_get_prid( void );
-
-
-/*----------------------------------------------------------------------
- Virtual interrupt prioritization (DEPRECATED)
- ----------------------------------------------------------------------*/
-
-/* Convert between interrupt levels (as per PS.INTLEVEL) and virtual interrupt priorities: */
-extern unsigned xthal_vpri_to_intlevel(unsigned vpri);
-extern unsigned xthal_intlevel_to_vpri(unsigned intlevel);
-
-/* Enables/disables given set (mask) of interrupts; returns previous enabled-mask of all ints: */
-/* These functions are deprecated. Use xthal_interrupt_enable and xthal_interrupt_disable instead. */
-extern unsigned xthal_int_enable(unsigned);
-extern unsigned xthal_int_disable(unsigned);
-
-/* Set/get virtual priority of an interrupt: */
-extern int xthal_set_int_vpri(int intnum, int vpri);
-extern int xthal_get_int_vpri(int intnum);
-
-/* Set/get interrupt lockout level for exclusive access to virtual priority data structures: */
-extern void xthal_set_vpri_locklevel(unsigned intlevel);
-extern unsigned xthal_get_vpri_locklevel(void);
-
-/* Set/get current virtual interrupt priority: */
-extern unsigned xthal_set_vpri(unsigned vpri);
-extern unsigned xthal_get_vpri(void);
-extern unsigned xthal_set_vpri_intlevel(unsigned intlevel);
-extern unsigned xthal_set_vpri_lock(void);
-
-
-/*----------------------------------------------------------------------
- Generic Interrupt Trampolining Support (DEPRECATED)
- ----------------------------------------------------------------------*/
-
-typedef void (XtHalVoidFunc)(void);
-
-/* Bitmask of interrupts currently trampolining down: */
-extern unsigned Xthal_tram_pending;
-
-/*
- * Bitmask of which interrupts currently trampolining down synchronously are
- * actually enabled; this bitmask is necessary because INTENABLE cannot hold
- * that state (sync-trampolining interrupts must be kept disabled while
- * trampolining); in the current implementation, any bit set here is not set
- * in INTENABLE, and vice-versa; once a sync-trampoline is handled (at level
- * one), its enable bit must be moved from here to INTENABLE:
- */
-extern unsigned Xthal_tram_enabled;
-
-/* Bitmask of interrupts configured for sync trampolining: */
-extern unsigned Xthal_tram_sync;
-
-/* Trampoline support functions: */
-extern unsigned xthal_tram_pending_to_service( void );
-extern void xthal_tram_done( unsigned serviced_mask );
-extern int xthal_tram_set_sync( int intnum, int sync );
-extern XtHalVoidFunc* xthal_set_tram_trigger_func( XtHalVoidFunc *trigger_fn );
-
-
-/*----------------------------------------------------------------------
- Internal Memories
- ----------------------------------------------------------------------*/
-
-extern const unsigned char Xthal_num_instrom;
-extern const unsigned char Xthal_num_instram;
-extern const unsigned char Xthal_num_datarom;
-extern const unsigned char Xthal_num_dataram;
-extern const unsigned char Xthal_num_xlmi;
-
-/* Each of the following arrays contains at least one entry,
- * or as many entries as needed if more than one: */
-extern const unsigned int Xthal_instrom_vaddr[];
-extern const unsigned int Xthal_instrom_paddr[];
-extern const unsigned int Xthal_instrom_size [];
-extern const unsigned int Xthal_instram_vaddr[];
-extern const unsigned int Xthal_instram_paddr[];
-extern const unsigned int Xthal_instram_size [];
-extern const unsigned int Xthal_datarom_vaddr[];
-extern const unsigned int Xthal_datarom_paddr[];
-extern const unsigned int Xthal_datarom_size [];
-extern const unsigned int Xthal_dataram_vaddr[];
-extern const unsigned int Xthal_dataram_paddr[];
-extern const unsigned int Xthal_dataram_size [];
-extern const unsigned int Xthal_xlmi_vaddr[];
-extern const unsigned int Xthal_xlmi_paddr[];
-extern const unsigned int Xthal_xlmi_size [];
-
-
-/*----------------------------------------------------------------------
- Cache
- ----------------------------------------------------------------------*/
-
-/* number of cache sets in log2(lines per way) */
-extern const unsigned char Xthal_icache_setwidth;
-extern const unsigned char Xthal_dcache_setwidth;
-/* cache set associativity (number of ways) */
-extern const unsigned int Xthal_icache_ways;
-extern const unsigned int Xthal_dcache_ways;
-/* cache features */
-extern const unsigned char Xthal_icache_line_lockable;
-extern const unsigned char Xthal_dcache_line_lockable;
-
-/* cache attribute register control (used by other HAL routines) */
-extern unsigned xthal_get_cacheattr( void );
-extern unsigned xthal_get_icacheattr( void );
-extern unsigned xthal_get_dcacheattr( void );
-extern void xthal_set_cacheattr( unsigned );
-extern void xthal_set_icacheattr( unsigned );
-extern void xthal_set_dcacheattr( unsigned );
-/* set cache attribute (access modes) for a range of memory */
-extern int xthal_set_region_attribute( void *addr, unsigned size,
- unsigned cattr, unsigned flags );
-/* Bits of flags parameter to xthal_set_region_attribute(): */
-#define XTHAL_CAFLAG_EXPAND 0x000100 /* only expand allowed access to range, don't reduce it */
-#define XTHAL_CAFLAG_EXACT 0x000200 /* return error if can't apply change to exact range specified */
-#define XTHAL_CAFLAG_NO_PARTIAL 0x000400 /* don't apply change to regions partially covered by range */
-#define XTHAL_CAFLAG_NO_AUTO_WB 0x000800 /* don't writeback data after leaving writeback attribute */
-#define XTHAL_CAFLAG_NO_AUTO_INV 0x001000 /* don't invalidate after disabling cache (entering bypass) */
-
-/* enable caches */
-extern void xthal_icache_enable( void ); /* DEPRECATED */
-extern void xthal_dcache_enable( void ); /* DEPRECATED */
-/* disable caches */
-extern void xthal_icache_disable( void ); /* DEPRECATED */
-extern void xthal_dcache_disable( void ); /* DEPRECATED */
-
-/* whole cache operations (privileged) */
-extern void xthal_icache_all_invalidate( void );
-extern void xthal_dcache_all_invalidate( void );
-extern void xthal_dcache_all_writeback( void );
-extern void xthal_dcache_all_writeback_inv( void );
-extern void xthal_icache_all_unlock( void );
-extern void xthal_dcache_all_unlock( void );
-
-/* address-range cache operations (privileged) */
-/* prefetch and lock specified memory range into cache */
-extern void xthal_icache_region_lock( void *addr, unsigned size );
-extern void xthal_dcache_region_lock( void *addr, unsigned size );
-/* unlock from cache */
-extern void xthal_icache_region_unlock( void *addr, unsigned size );
-extern void xthal_dcache_region_unlock( void *addr, unsigned size );
-
-/* huge-range cache operations (privileged) (EXPERIMENTAL) */
-extern void xthal_icache_hugerange_invalidate( void *addr, unsigned size );
-extern void xthal_icache_hugerange_unlock( void *addr, unsigned size );
-extern void xthal_dcache_hugerange_invalidate( void *addr, unsigned size );
-extern void xthal_dcache_hugerange_unlock( void *addr, unsigned size );
-extern void xthal_dcache_hugerange_writeback( void *addr, unsigned size );
-extern void xthal_dcache_hugerange_writeback_inv( void *addr, unsigned size );
-
-# ifndef XTHAL_USE_CACHE_MACROS
-/* cache line operations (privileged) */
-extern void xthal_icache_line_lock(void *addr);
-extern void xthal_dcache_line_lock(void *addr);
-extern void xthal_icache_line_unlock(void *addr);
-extern void xthal_dcache_line_unlock(void *addr);
-# endif
-
-
-
-/*----------------------------------------------------------------------
- Local Memory ECC/Parity
- ----------------------------------------------------------------------*/
-
-/* Inject memory errors; flags is bit combination of XTHAL_MEMEP_F_xxx: */
-extern void xthal_memep_inject_error(void *addr, int size, int flags);
-
-
-
-/*----------------------------------------------------------------------
- Memory Management Unit
- ----------------------------------------------------------------------*/
-
-extern const unsigned char Xthal_have_spanning_way;
-extern const unsigned char Xthal_have_identity_map;
-extern const unsigned char Xthal_have_mimic_cacheattr;
-extern const unsigned char Xthal_have_xlt_cacheattr;
-extern const unsigned char Xthal_have_cacheattr;
-extern const unsigned char Xthal_have_tlbs;
-
-extern const unsigned char Xthal_mmu_asid_bits; /* 0 .. 8 */
-extern const unsigned char Xthal_mmu_asid_kernel;
-extern const unsigned char Xthal_mmu_rings; /* 1 .. 4 (perhaps 0 if no MMU and/or no protection?) */
-extern const unsigned char Xthal_mmu_ring_bits;
-extern const unsigned char Xthal_mmu_sr_bits;
-extern const unsigned char Xthal_mmu_ca_bits;
-extern const unsigned int Xthal_mmu_max_pte_page_size;
-extern const unsigned int Xthal_mmu_min_pte_page_size;
-
-extern const unsigned char Xthal_itlb_way_bits;
-extern const unsigned char Xthal_itlb_ways;
-extern const unsigned char Xthal_itlb_arf_ways;
-extern const unsigned char Xthal_dtlb_way_bits;
-extern const unsigned char Xthal_dtlb_ways;
-extern const unsigned char Xthal_dtlb_arf_ways;
-
-/* Return error codes for hal functions */
-
-/* function sucessful, operation completed as expected */
-#define XTHAL_SUCCESS 0
-/* XTHAL_CAFLAGS_NO_PARTIAL was specified, and no full region is
- * covered by the address range. */
-#define XTHAL_NO_REGIONS_COVERED -1
-/* The XTHAL_CAFLAGS_EXACT flag was given, but no exact mapping is possible. */
-#define XTHAL_INEXACT -2
-/* The supplied address doesn't correspond to the start of a region. */
-#define XTHAL_INVALID_ADDRESS -3
-/* This functionality is not available on this architecture. */
-#define XTHAL_UNSUPPORTED -4
-/* Translation failed because vaddr and paddr were not aligned. */
-#define XTHAL_ADDRESS_MISALIGNED -5
-/* There is mapping for the supplied address. */
-#define XTHAL_NO_MAPPING -6
-/* The requested access rights are not supported */
-#define XTHAL_BAD_ACCESS_RIGHTS -7
-/* The requested memory type is not supported */
-#define XTHAL_BAD_MEMORY_TYPE -8
-/* The entries supplied are not properly aligned to the MPU's background map. */
-#define XTHAL_MAP_NOT_ALIGNED -9
-/* There are not enough MPU entries available to do the requeste mapping. */
-#define XTHAL_OUT_OF_ENTRIES -10
-/* The entries supplied are not properly ordered for the MPU. */
-#define XTHAL_OUT_OF_ORDER_MAP -11
-/* an invalid argument such as a null pointer was supplied to the function */
-#define XTHAL_INVALID -12
-/* specified region is of zero size, therefore no mapping is done. */
-#define XTHAL_ZERO_SIZED_REGION -13
-/* specified range wraps around '0' */
-#define XTHAL_INVALID_ADDRESS_RANGE -14
-
-/*
- For backward compatibility we retain the following inconsistenly named
- constants. Do not use them as they may be removed in a future release.
- */
-#define XCHAL_SUCCESS XTHAL_SUCCESS
-#define XCHAL_ADDRESS_MISALIGNED XTHAL_ADDRESS_MISALIGNED
-#define XCHAL_INEXACT XTHAL_INEXACT
-#define XCHAL_INVALID_ADDRESS XTHAL_INVALID_ADDRESS
-#define XCHAL_UNSUPPORTED_ON_THIS_ARCH XTHAL_UNSUPPORTED
-#define XCHAL_NO_PAGES_MAPPED XTHAL_NO_REGIONS_COVERED
-
-
-/* Convert between virtual and physical addresses (through static maps only)
- * WARNING: these two functions may go away in a future release;
- * don't depend on them!
-*/
-extern int xthal_static_v2p( unsigned vaddr, unsigned *paddrp );
-extern int xthal_static_p2v( unsigned paddr, unsigned *vaddrp, unsigned cached );
-
-extern int xthal_set_region_translation(void* vaddr, void* paddr,
- unsigned size, unsigned cache_atr, unsigned flags);
-extern int xthal_v2p(void*, void**, unsigned*, unsigned*);
-extern int xthal_invalidate_region(void* addr);
-extern int xthal_set_region_translation_raw(void *vaddr, void *paddr, unsigned cattr);
-
-/*------------------------------------------------------------------------
- MPU (Memory Protection Unit)
--------------------------------------------------------------------------*/
-
-/*
- * General notes on MPU (Memory Protection Unit):
- *
- * The MPU supports setting the access rights (read, write, execute) as
- * well as the memory type (cacheablity, ...)
- * for regions of memory. The granularity can be as small as 32 bytes.
- * (XCHAL_MPU_ALIGN specifies the granularity for any specific MPU config)
- *
- * The MPU doesn't support mapping between virtual and physical addresses.
- *
- * The MPU contains a fixed number of map changeable forground map entries,
- * and a background map which is fixed at configuration time.
- *
- * Each entry has a start address (up to 27 bits), valid flag,
- * access rights (4 bits), and memory type (9 bits);
- *
- */
-
-
-/*
- MPU access rights constants:
- Only the combinations listed below are supported by the MPU.
-*/
-
-#define XTHAL_AR_NONE 0 /* no access */
-#define XTHAL_AR_R 4 /* Kernel read, User no access*/
-#define XTHAL_AR_RX 5 /* Kernel read/execute, User no access */
-#define XTHAL_AR_RW 6 /* Kernel read/write, User no access */
-#define XTHAL_AR_RWX 7 /* Kernel read/write/execute, User no access */
-#define XTHAL_AR_Ww 8 /* Kernel write, User write */
-#define XTHAL_AR_RWrwx 9 /* Kernel read/write , User read/write/execute */
-#define XTHAL_AR_RWr 10 /* Kernel read/write, User read */
-#define XTHAL_AR_RWXrx 11 /* Kernel read/write/execute, User read/execute */
-#define XTHAL_AR_Rr 12 /* Kernel read, User read */
-#define XTHAL_AR_RXrx 13 /* Kernel read/execute, User read/execute */
-#define XTHAL_AR_RWrw 14 /* Kernel read/write, User read/write */
-#define XTHAL_AR_RWXrwx 15 /* Kernel read/write/execute,
- User read/write/execute */
-
-#define XTHAL_AR_WIDTH 4 /* # bits used to encode access rights */
-
-/* If the bit XTHAL_MPU_USE_EXISTING_ACCESS_RIGHTS is set in the accessRights
- * argument to xthal_mpu_set_region_attribute(), or to the cattr argument of
- * xthal_set_region_attribute() then the existing access rights for the first
- * byte of the region will be used as the access rights of the new region.
- */
-#define XTHAL_MPU_USE_EXISTING_ACCESS_RIGHTS 0x00002000
-
-/* If the bit XTHAL_MPU_USE_EXISTING_MEMORY_TYPE is set in the memoryType
- * argument to xthal_mpu_set_region_attribute(), or to the cattr argument of
- * xthal_set_region_attribute() then the existing memory type for the first
- * byte of the region will be used as the memory type of the new region.
- */
-#define XTHAL_MPU_USE_EXISTING_MEMORY_TYPE 0x00004000
-
-/* The following groups of constants are bit-wise or'd together to specify
- * the memory type as input to the macros and functions that accept an
- * unencoded memory type specifier:
- * XTHAL_ENCODE_MEMORY_TYPE, xthal_encode_memory_type,
- * xthal_mpu_set_region_attribute(), and xthal_set_region_attribute().
- *
- * example:
- * XTHAL_MEM_DEVICE | XTHAL_MEM_INTERRUPTIBLE | XTHAL_MEM_SYSTEM_SHARABLE
- *
- * or
- * XTHAL_MEM_WRITEBACK | XTHAL_MEM_INNER_SHAREABLE
- *
- * If it is desired to specify different attributes for the system and
- * local cache, then macro XTHAL_MEM_PROC_CACHE is used:
- *
- * XTHAL_MEM_PROC_CACHE(XTHAL_MEM_WRITEBACK, XTHAL_MEM_WRITETHRU)
- *
- * indicates the shared cache is writeback, but the processor's local cache
- * is writethrough.
- *
- */
-
-/* The following group of constants are used to specify cache attributes of
- * an MPU entry. If the processors local cache and the system's shared cache
- * have the same attributes (or if there aren't distinct local and shared
- * caches) then the constant can be used directly. If different attributes
- * for the shared and local caches, then use these constants as the parameters
- * to the XTHAL_MEM_PROC_CACHE() macro.
- */
-#define XTHAL_MEM_DEVICE 0x00008000
-#define XTHAL_MEM_NON_CACHEABLE 0x00090000
-#define XTHAL_MEM_WRITETHRU_NOALLOC 0x00080000
-#define XTHAL_MEM_WRITETHRU 0x00040000
-#define XTHAL_MEM_WRITETHRU_WRITEALLOC 0x00060000
-#define XTHAL_MEM_WRITEBACK_NOALLOC 0x00050000
-#define XTHAL_MEM_WRITEBACK 0x00070000
-
-/* Indicates a read is interruptible. Only applicable to devices */
-#define XTHAL_MEM_INTERRUPTIBLE 0x08000000
-
-/* Indicates if writes to this memory are bufferable ... only applicable
- * to devices, and non-cacheable memory.
- */
-#define XTHAL_MEM_BUFFERABLE 0x01000000
-
-/* The following group of constants indicates the scope of the sharing of
- * the memory region. XTHAL_MEM_INNER_SHAREABLE and XTHAL_MEM_OUTER_SHARABLE are
- * only applicable to cacheable regions. XTHAL_MEM_SYSTEM_SHAREABLE is only
- * applicable to devices and non-cacheable regions.
- */
-#define XTHAL_MEM_NON_SHAREABLE 0x00000000
-#define XTHAL_MEM_INNER_SHAREABLE 0x02000000
-#define XTHAL_MEM_OUTER_SHAREABLE 0x04000000
-#define XTHAL_MEM_SYSTEM_SHAREABLE 0x06000000
-
-
-/*
- * This macro is needed when the cache attributes are different for the shared
- * and processor's local caches. For example:
- *
- * XTHAL_MEM_PROC_CACHE(XTHAL_MEM_WRITEBACK, XTHAL_MEM_NON_CACHEABLE)
- * creates a memory type that is writeback cacheable in the system cache, and not
- * cacheable in the processor's local cache.
- */
-#define XTHAL_MEM_PROC_CACHE(system, processor) \
- (((system) & 0x000f0000) | (((processor) & 0x000f0000 ) << 4) | \
- (((system) & XTHAL_MEM_DEVICE) | ((processor) & XTHAL_MEM_DEVICE)))
-
-/*
- * This macro converts a bit-wise combination of the XTHAL_MEM_... constants
- * to the corresponding MPU memory type (9-bits).
- *
- * Unsupported combinations are mapped to the best available substitute.
- *
- * The same functionality plus error checking is available from
- * xthal_encode_memory_type().
- */
-#define XTHAL_ENCODE_MEMORY_TYPE(x) \
- (((x) & 0xffffe000) ? \
- (_XTHAL_MEM_IS_DEVICE((x)) ? _XTHAL_ENCODE_DEVICE((x)) : \
- (_XTHAL_IS_SYSTEM_NONCACHEABLE((x)) ? \
- _XTHAL_ENCODE_SYSTEM_NONCACHEABLE((x)) : \
- _XTHAL_ENCODE_SYSTEM_CACHEABLE((x)))) : (x))
-
-/*
- * This structure is used to represent each MPU entry (both foreground and
- * background). The internal representation of the structure is subject to
- * change, so it should only be accessed by the XTHAL_MPU_ENTRY_... macros
- * below.
- */
-typedef struct xthal_MPU_entry
-{
- unsigned as; /* virtual start address, and valid bit */
- unsigned at; /* access rights, and memory type (and space for entry index) */
-} xthal_MPU_entry;
-
-extern const xthal_MPU_entry Xthal_mpu_bgmap[];
-
-
-
-
-/*
- * XTHAL_MPU_ENTRY creates an MPU entry from its component values. It is
- * intended for initializing an MPU map. Example:
- * const struct xthal_MPU_entry mpumap[] =
- { XTHAL_MPU_ENTRY( 0x00000000, 1, XTHAL_AR_RWXrwx, XTHAL_MEM_WRITEBACK),
- XTHAL_MPU_ENTRY( 0xE0000000, 1, XTHAL_AR_RWXrwx,
- XTHAL_MEM_NON_CACHEABLE | XTHAL_MEM_BUFFERABLE),
- XTHAL_MPU_ENTRY( 0xF0000000, 1, XTHAL_AR_RWX,
- XTHAL_MEM_NON_CACHEABLE | XTHAL_MEM_BUFFERABLE) };
- xthal_write_map(mpumap, sizeof(mpumap) / sizeof(struct xthal_MPU_entry));
- *
- */
-#define XTHAL_MPU_ENTRY(vaddr, valid, access, memtype) \
- { (((vaddr) & 0xffffffe0) | ((valid & 0x1))), \
- (((XTHAL_ENCODE_MEMORY_TYPE(memtype)) << 12) | (((access) & 0xf) << 8)) }
-
-/*
- * These macros get (or set) the specified field of the MPU entry.
- */
-#define XTHAL_MPU_ENTRY_GET_VSTARTADDR(x) ((x).as & 0xffffffe0)
-
-#define XTHAL_MPU_ENTRY_SET_VSTARTADDR(x, vaddr) (x).as = \
- (((x).as) & 0x1) | ((vaddr) & 0xffffffe0)
-
-#define XTHAL_MPU_ENTRY_GET_VALID(x) (((x).as & 0x1))
-
-#define XTHAL_MPU_ENTRY_SET_VALID(x, valid) (x).as = \
- (((x).as & 0xfffffffe) | ((valid) & 0x1))
-#define XTHAL_MPU_ENTRY_GET_ACCESS(x) ((((x).at) >> 8) & 0xf)
-
-#define XTHAL_MPU_ENTRY_SET_ACCESS(x, accessRights) ((x).at = \
- ((x).at & 0xfffff0ff) | (((accessRights) & 0xf) << 8))
-
-#define XTHAL_MPU_ENTRY_GET_MEMORY_TYPE(x) ((((x).at) >> 12) & 0x1ff)
-
-#define XTHAL_MPU_ENTRY_SET_MEMORY_TYPE(x, memtype) ((x).at = \
- ((x).at & 0xffe00fff) | (((XTHAL_ENCODE_MEMORY_TYPE(memtype)) & 0x1ff) << 12))
-
-/*
- * These functions accept encoded access rights, and return 1 if the
- * supplied memory type has the property specified by the function name,
- * otherwise they return 0.
- */
-extern int xthal_is_kernel_readable(int accessRights);
-extern int xthal_is_kernel_writeable(int accessRights);
-extern int xthal_is_kernel_executable(int accessRights);
-extern int xthal_is_user_readable(int accessRights);
-extern int xthal_is_user_writeable (int accessRights);
-extern int xthal_is_user_executable(int accessRights);
-
-
-/*
- * This function converts a bit-wise combination of the XTHAL_MEM_.. constants
- * to the corresponding MPU memory type (9-bits).
- *
- * If none of the XTHAL_MEM_.. bits are present in the argument, then
- * bits 4-12 (9-bits) are returned ... this supports using an already encoded
- * memoryType (perhaps obtained from an xthal_MPU_entry structure) as input
- * to xthal_set_region_attribute().
- *
- * This function first checks that the supplied constants are a valid and
- * supported combination. If not, it returns XTHAL_BAD_MEMORY_TYPE.
- */
-extern int xthal_encode_memory_type(unsigned int x);
-
-/*
- * This function accepts a 9-bit memory type value (such as returned by
- * XTHAL_MEM_ENTRY_GET_MEMORY_TYPE() or xthal_encode_memory_type(). They
- * return 1 if the memoryType has the property specified in the function
- * name and 0 otherwise.
- */
-extern int xthal_is_cacheable(unsigned int memoryType);
-extern int xthal_is_writeback(unsigned int memoryType);
-extern int xthal_is_device(unsigned int memoryType);
-
-/*
- * Copies the current MPU entry list into 'entries' which
- * must point to available memory of at least
- * sizeof(struct xthal_MPU_entry) * XCHAL_MPU_ENTRIES.
- *
- * This function returns XTHAL_SUCCESS.
- * XTHAL_INVALID, or
- * XTHAL_UNSUPPORTED.
- */
-extern int xthal_read_map(struct xthal_MPU_entry* entries);
-
-/*
- * Writes the map pointed to by 'entries' to the MPU. Before updating
- * the map, it commits any uncommitted
- * cache writes, and invalidates the cache if necessary.
- *
- * This function does not check for the correctness of the map. Generally
- * xthal_check_map() should be called first to check the map.
- *
- * If n == 0 then the existing map is cleared, and no new map is written
- * (useful for returning to reset state)
- *
- * If (n > 0 && n < XCHAL_MPU_ENTRIES) then a new map is written with
- * (XCHAL_MPU_ENTRIES-n) padding entries added to ensure a properly ordered
- * map. The resulting foreground map will be equivalent to the map vector
- * fg, but the position of the padding entries should not be relied upon.
- *
- * If n == XCHAL_MPU_ENTRIES then the complete map as specified by fg is
- * written.
- *
- * The CACHEADRDIS register will be set to enable caching any 512MB region
- * that is overlapped by an MPU region with a cacheable memory type.
- * Caching will be disabled if none of the 512 MB region is cacheable.
- *
- * xthal_write_map() disables the MPU foreground map during the MPU
- * update and relies on the background map.
- *
- * As a result any interrupt that does not meet the following conditions
- * must be disabled before calling xthal_write_map():
- * 1) All code and data needed for the interrupt must be
- * mapped by the background map with sufficient access rights.
- * 2) The interrupt code must not access the MPU.
- *
- */
-extern void xthal_write_map(const struct xthal_MPU_entry* entries, unsigned n);
-
-/*
- * Checks if entry vector 'entries' of length 'n' is a valid MPU access map.
- * Returns:
- * XTHAL_SUCCESS if valid,
- * XTHAL_OUT_OF_ENTRIES
- * XTHAL_MAP_NOT_ALIGNED,
- * XTHAL_BAD_ACCESS_RIGHTS,
- * XTHAL_OUT_OF_ORDER_MAP, or
- * XTHAL_UNSUPPORTED if config doesn't have an MPU.
- */
-extern int xthal_check_map(const struct xthal_MPU_entry* entries, unsigned n);
-
-/*
- * Returns the MPU entry that maps 'vaddr'. If 'infgmap' is non-NULL then
- * *infgmap is set to 1 if 'vaddr' is mapped by the foreground map, and
- * *infgmap is set to 0 if 'vaddr' is mapped by the background map.
- */
-extern struct xthal_MPU_entry xthal_get_entry_for_address(void* vaddr,
- int* infgmap);
-
-/*
- * Scans the supplied MPU map and returns a value suitable for writing to
- * the CACHEADRDIS register:
- * Bits 0-7 -> 1 if there are no cacheable areas in the corresponding 512MB
- * region and 0 otherwise.
- * Bits 8-31 -> undefined.
- * This function can accept a partial memory map in the same manner
- * xthal_write_map() does, */
-extern unsigned int
-xthal_calc_cacheadrdis(const struct xthal_MPU_entry* e, unsigned n);
-
-/*
- * This function is intended as an MPU specific version of
- * xthal_set_region_attributes(). xthal_set_region_attributes() calls
- * this function for MPU configurations.
- *
- * This function sets the attributes for the region [vaddr, vaddr+size)
- * in the MPU.
- *
- * Depending on the state of the MPU this function will require from
- * 0 to 3 unused MPU entries.
- *
- * This function typically will move, add, and subtract entries from
- * the MPU map during execution, so that the resulting map may
- * be quite different than when the function was called.
- *
- * This function does make the following guarantees:
- * 1) The MPU access map remains in a valid state at all times
- * during its execution.
- * 2) At all points during (and after) completion the memoryType
- * and accessRights remain the same for all addresses
- * that are not in the range [vaddr, vaddr+size).
- * 3) If XTHAL_SUCCESS is returned, then the range
- * [vaddr, vaddr+size) will have the accessRights and memoryType
- * specified.
- * 4) The CACHEADRDIS register will be set to enable caching any 512MB region
- * that is overlapped by an MPU region with a cacheable memory type.
- * Caching will be disabled if none of the 512 MB region is cacheable.
- *
- * The accessRights parameter should be either a 4-bit value corresponding
- * to an MPU access mode (as defined by the XTHAL_AR_.. constants), or
- * XTHAL_MPU_USE_EXISTING_ACCESS_RIGHTS.
- *
- * The memoryType parameter should be either a bit-wise or-ing of XTHAL_MEM_..
- * constants that represent a valid MPU memoryType, a 9-bit MPU memoryType
- * value, or XTHAL_MPU_USE_EXISTING_MEMORY_TYPE.
- *
- * In addition to the error codes that xthal_set_region_attribute()
- * returns, this function can also return: XTHAL_BAD_ACCESS_RIGHTS
- * (if the access rights bits map to an unsupported combination), or
- * XTHAL_OUT_OF_MAP_ENTRIES (if there are not enough unused MPU entries)
- *
- * If this function is called with an invalid MPU map, then this function
- * will return one of the codes that is returned by xthal_check_map().
- *
- * The flag, XTHAL_CAFLAG_EXPAND, is not supported
- *
- */
-
-extern int xthal_mpu_set_region_attribute(void* vaddr, unsigned size,
- int accessRights, int memoryType, unsigned flags);
-
-/* The following are internal implementation macros. These should not
- * be directly used except by the hal code and headers.
-*/
-
-/*
- * Layout of the MPU specifier for: XTHAL_ENCODE_MEMORY_TYPE(),
- * xthal_encode_memory_type(), xthal_set_region_attribute(),
- * and xthal_mpu_set_region_attribute(). THIS IS SUBJECT TO CHANGE:
- *
- * Bits 0-3 - reserved for pass through of accessRights
- * Bits 4-12 - reserved for pass through of memoryType bits
- * Bit 13 - indicates to use existing access rights of region
- * Bit 14 - indicates to use existing memory type of region
- * Bit 15 - indicates device
- * Bit 16-19- system cache properties
- * Bit 20-23- local cache properties
- * Bit 24 - indicates bufferable
- * Bit 25-26- encodes shareability (1=inner, 2=outer, 3=system)
- * Bit 27 - indicates interruptible
- * Bits 28-31- reserved for future use
- */
-#define _XTHAL_SYSTEM_CACHE_BITS 0x000f0000
-#define _XTHAL_LOCAL_CACHE_BITS 0x00f00000
-#define _XTHAL_MEM_SYSTEM_RWC_MASK 0x00070000
-#define _XTHAL_MEM_LOCAL_RWC_MASK 0x00700000
-#define _XTHAL_SHIFT_RWC 16
-
-#define _XTHAL_MEM_ANY_SHAREABLE(x) (((x) & XTHAL_MEM_SYSTEM_SHAREABLE) ? 1 : 0)
-
-#define _XTHAL_MEM_INNER_SHAREABLE(x) ((((x) & XTHAL_MEM_SYSTEM_SHAREABLE) \
- == XTHAL_MEM_INNER_SHAREABLE) ? 1 : 0)
-
-#define _XTHAL_MEM_IS_BUFFERABLE(x) (((x) & XTHAL_MEM_BUFFERABLE) ? 1 : 0)
-
-#define _XTHAL_MEM_IS_DEVICE(x) (((x) & XTHAL_MEM_DEVICE) ? 1 : 0)
-
-#define _XTHAL_NON_CACHEABLE_DOMAIN(x) \
- (_XTHAL_MEM_IS_DEVICE(x) || _XTHAL_MEM_ANY_SHAREABLE(x)? 0x3 : 0)
-
-#define _XTHAL_CACHEABLE_DOMAIN(x) (_XTHAL_MEM_ANY_SHAREABLE(x) ? \
- 0x3 : 0x1)
-
-#define _XTHAL_MEM_CACHE_MASK(x) ((x) & _XTHAL_SYSTEM_CACHE_BITS)
-
-#define _XTHAL_IS_SYSTEM_NONCACHEABLE(x) \
- (((_XTHAL_MEM_CACHE_MASK(x) & XTHAL_MEM_NON_CACHEABLE) == \
- XTHAL_MEM_NON_CACHEABLE) ? 1 : 0)
-
-#define _XTHAL_ENCODE_DEVICE(x) \
- (((((x) & XTHAL_MEM_INTERRUPTIBLE) ? 1 : 0) << 3) | \
- (_XTHAL_NON_CACHEABLE_DOMAIN(x) << 1) | _XTHAL_MEM_IS_BUFFERABLE(x))
-
-#define _XTHAL_ENCODE_SYSTEM_NONCACHEABLE(x) \
- (0x18 | (_XTHAL_NON_CACHEABLE_DOMAIN(x) << 1) \
- | _XTHAL_MEM_IS_BUFFERABLE(x))
-
-#define _XTHAL_ENCODE_SYSTEM_CACHEABLE(x) \
- (((((((x) & _XTHAL_LOCAL_CACHE_BITS) >> 4) & XTHAL_MEM_NON_CACHEABLE) == \
- XTHAL_MEM_NON_CACHEABLE) ? 1 : 0) ? \
- (_XTHAL_CACHEABLE_DOMAIN(x) << 4) : \
- _XTHAL_ENCODE_SYSTEM_CACHEABLE_LOCAL_CACHEABLE(x)) | \
- ((_XTHAL_MEM_INNER_SHAREABLE(x) << 3) | \
- (_XTHAL_MEM_CACHE_MASK(x) & _XTHAL_MEM_SYSTEM_RWC_MASK) \
- >> _XTHAL_SHIFT_RWC)
-
-#define _XTHAL_ENCODE_SYSTEM_CACHEABLE_LOCAL_CACHEABLE(x) \
- ((_XTHAL_CACHEABLE_DOMAIN(x) << 7) | (((((x) & _XTHAL_LOCAL_CACHE_BITS) ? \
- ((x) & _XTHAL_LOCAL_CACHE_BITS) : \
- (_XTHAL_MEM_CACHE_MASK(x) << 4)) \
- & (_XTHAL_MEM_LOCAL_RWC_MASK)) >> _XTHAL_SHIFT_RWC ))
-
-/* End of internal macros */
-
-/* The functions and constants below here have been deprecated.*/
-#define XTHAL_MEM_NON_CACHED XTHAL_MEM_NON_CACHEABLE
-#define XTHAL_MEM_NON_SHARED XTHAL_MEM_NON_SHAREABLE
-#define XTHAL_MEM_INNER_SHARED XTHAL_MEM_INNER_SHAREABLE
-#define XTHAL_MEM_OUTER_SHARED XTHAL_MEM_OUTER_SHAREABLE
-#define XTHAL_MEM_SYSTEM_SHARED XTHAL_MEM_SYSTEM_SHAREABLE
-#define XTHAL_MEM_SW_SHAREABLE 0
-
-#define xthal_is_cached(memoryType) (xthal_is_cacheable((memoryType)))
-extern int xthal_read_background_map(struct xthal_MPU_entry* entries);
-
-/* end deprecated functions and constants */
-
-#ifdef __cplusplus
-}
-#endif
-#endif /*!_ASMLANGUAGE && !_NOCLANGUAGE && !__ASSEMBLER__ */
-
-#endif /* !XTENSA_HAL_NON_PRIVILEGED_ONLY */
-
-
-
-
-/****************************************************************************
- EXPERIMENTAL and DEPRECATED Definitions
- ****************************************************************************/
-
-
-#if !defined(_ASMLANGUAGE) && !defined(_NOCLANGUAGE) && !defined(__ASSEMBLER__)
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-#ifdef INCLUDE_DEPRECATED_HAL_CODE
-extern const unsigned char Xthal_have_old_exc_arch;
-extern const unsigned char Xthal_have_mmu;
-extern const unsigned int Xthal_num_regs;
-extern const unsigned char Xthal_num_iroms;
-extern const unsigned char Xthal_num_irams;
-extern const unsigned char Xthal_num_droms;
-extern const unsigned char Xthal_num_drams;
-extern const unsigned int Xthal_configid0;
-extern const unsigned int Xthal_configid1;
-#endif
-
-#ifdef INCLUDE_DEPRECATED_HAL_DEBUG_CODE
-#define XTHAL_24_BIT_BREAK 0x80000000
-#define XTHAL_16_BIT_BREAK 0x40000000
-extern const unsigned short Xthal_ill_inst_16[16];
-#define XTHAL_DEST_REG 0xf0000000 /* Mask for destination register */
-#define XTHAL_DEST_REG_INST 0x08000000 /* Branch address is in register */
-#define XTHAL_DEST_REL_INST 0x04000000 /* Branch address is relative */
-#define XTHAL_RFW_INST 0x00000800
-#define XTHAL_RFUE_INST 0x00000400
-#define XTHAL_RFI_INST 0x00000200
-#define XTHAL_RFE_INST 0x00000100
-#define XTHAL_RET_INST 0x00000080
-#define XTHAL_BREAK_INST 0x00000040
-#define XTHAL_SYSCALL_INST 0x00000020
-#define XTHAL_LOOP_END 0x00000010 /* Not set by xthal_inst_type */
-#define XTHAL_JUMP_INST 0x00000008 /* Call or jump instruction */
-#define XTHAL_BRANCH_INST 0x00000004 /* Branch instruction */
-#define XTHAL_24_BIT_INST 0x00000002
-#define XTHAL_16_BIT_INST 0x00000001
-typedef struct xthal_state {
- unsigned pc;
- unsigned ar[16];
- unsigned lbeg;
- unsigned lend;
- unsigned lcount;
- unsigned extra_ptr;
- unsigned cpregs_ptr[XTHAL_MAX_CPS];
-} XTHAL_STATE;
-extern unsigned int xthal_inst_type(void *addr);
-extern unsigned int xthal_branch_addr(void *addr);
-extern unsigned int xthal_get_npc(XTHAL_STATE *user_state);
-#endif /* INCLUDE_DEPRECATED_HAL_DEBUG_CODE */
-
-#ifdef __cplusplus
-}
-#endif
-#endif /*!_ASMLANGUAGE && !_NOCLANGUAGE && !__ASSEMBLER__ */
-
-#endif /*XTENSA_HAL_H*/
-
diff --git a/src/arch/xtensa/include/xtensa/idmaasm.h b/src/arch/xtensa/include/xtensa/idmaasm.h
deleted file mode 100755
index 2669ff0..0000000
--- a/src/arch/xtensa/include/xtensa/idmaasm.h
+++ /dev/null
@@ -1,72 +0,0 @@
-/* $Id: //depot/dev/Foxhill/Xtensa/OS/include/xtensa/mpuasm.h#5 $ */
-
-/*
- * Copyright (c) 2016 Cadence Design Systems, Inc.
- *
- * Permission is hereby granted, free of charge, to any person obtaining
- * a copy of this software and associated documentation files (the
- * "Software"), to deal in the Software without restriction, including
- * without limitation the rights to use, copy, modify, merge, publish,
- * distribute, sublicense, and/or sell copies of the Software, and to
- * permit persons to whom the Software is furnished to do so, subject to
- * the following conditions:
- *
- * The above copyright notice and this permission notice shall be included
- * in all copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
- * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
- * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
- * IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY
- * CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
- * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
- * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
- */
-
-#ifndef _IDMAASM_H_
-#define _IDMAASM_H_
-
-#if XCHAL_HAVE_IDMA
-#include <xtensa/idma.h>
-#endif
-
-/*
- * Macro for restore IDMA regs
- *
- * Parameters:
- * a_save => address register containing pointer to IDMA save area
- * a_temp1, a_temp2, a_temp3. => address register temporaries
- */
-// IDMA_REG_SETTINGS,
-// IDMA_REG_TIMEOUT,
-// IDMA_REG_DESC_START,
-// IDMA_REG_CONTROL,
-// IDMA_REG_USERPRIV,
-
-.macro _idma_restore a_save, a_temp1, a_temp2, a_temp3
-#if XCHAL_HAVE_IDMA
- l32i \a_temp1, \a_save, 0
- movi \a_temp3, idmareg_base
- movi \a_temp2, IDMA_REG_SETTINGS
- add \a_temp2, \a_temp2, \a_temp3
- wer \a_temp1, \a_temp2
- l32i \a_temp1, \a_save, 4
- movi \a_temp2, IDMA_REG_TIMEOUT
- add \a_temp2, \a_temp2, \a_temp3
- wer \a_temp1, \a_temp2
- l32i \a_temp1, \a_save, 8
- movi \a_temp2, IDMA_REG_DESC_START
- add \a_temp2, \a_temp2, \a_temp3
- wer \a_temp1, \a_temp2
- l32i \a_temp1, \a_save, 12
- movi \a_temp2, IDMA_REG_CONTROL
- add \a_temp2, \a_temp2, \a_temp3
- wer \a_temp1, \a_temp2
- l32i \a_temp1, \a_save, 16
- movi \a_temp2, IDMA_REG_USERPRIV
- add \a_temp2, \a_temp2, \a_temp3
- wer \a_temp1, \a_temp2
-#endif
-.endm
-
-#endif //_IDMAASM_H_
diff --git a/src/arch/xtensa/include/xtensa/mpuasm.h b/src/arch/xtensa/include/xtensa/mpuasm.h
deleted file mode 100644
index f14dacc..0000000
--- a/src/arch/xtensa/include/xtensa/mpuasm.h
+++ /dev/null
@@ -1,111 +0,0 @@
-/* $Id: //depot/dev/Foxhill/Xtensa/OS/include/xtensa/mpuasm.h#5 $ */
-
-/*
- * Copyright (c) 2016 Cadence Design Systems, Inc.
- *
- * Permission is hereby granted, free of charge, to any person obtaining
- * a copy of this software and associated documentation files (the
- * "Software"), to deal in the Software without restriction, including
- * without limitation the rights to use, copy, modify, merge, publish,
- * distribute, sublicense, and/or sell copies of the Software, and to
- * permit persons to whom the Software is furnished to do so, subject to
- * the following conditions:
- *
- * The above copyright notice and this permission notice shall be included
- * in all copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
- * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
- * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
- * IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY
- * CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
- * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
- * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
- */
-
-#ifndef _MPUASM_H_
-#define _MPUASM_H_
-#include <xtensa/config/core.h>
-
-/*
- * Macro for writing MPU map.
- *
- * Parameters:
- * a_map => address register containing pointer to MPU map
- * a_num_entries => number of entries in the forementioned map
- * a_temp1, a_temp2. => address register temporaries
- * a_temp3, a_temp4
- */
-
-.macro mpu_write_map a_map, a_num_entries, a_temp1, a_temp2, a_temp3, a_temp4
-#if XCHAL_HAVE_MPU
- movi \a_temp1, 0
- wsr.cacheadrdis \a_temp1 // enable the cache in all regions
- wsr.mpuenb \a_temp1 // disable all foreground entries
-
- // Clear out the unused entries.
- //
- // Currently we are clearing out all the entries because currently
- // the entries must be ordered even if they are all disabled.
- // If out of order entries were permitted when all are disabled,
- // performance could be improved by clearing XCHAL_MPU_ENTRIES - n
- // (n = number of entries) rather than XCHAL_MPU_ENTRIES - 1 entries.
- //
- movi \a_temp2, 0
- movi \a_temp3, XCHAL_MPU_ENTRIES - 1
- j 1f
- .align 16 // this alignment is done to ensure that
-1:
- memw // todo currently wptlb must be preceeded by a memw. The instructions must
- // be aligned to ensure that both are in the same cache line. These statements should be
- // properly conditionalized when that restriction is removed from the HW
- wptlb \a_temp2, \a_temp1
- addi \a_temp2, \a_temp2, 1
- bltu \a_temp2, \a_temp3, 1b
-
- // Write the new entries.
- //
- beqz \a_num_entries, 4f // if no entries, skip loop
- addx8 \a_map, \a_num_entries, \a_map // compute end of provided map
- j 3f
- .align 16
-2: memw // todo currently wptlb must be preceeded by a memw. The instructions must
- // be aligned to ensure that both are in the same cache line. These statements should be
- // properly conditionalized when that restriction is removed from the HW
- wptlb \a_temp2, \a_temp4
- addi \a_temp3, \a_temp3, -1
- beqz \a_num_entries, 4f // loop until done
-3: addi \a_map, \a_map, -8
- l32i \a_temp2, \a_map, 4 // get at (acc.rights, memtype)
- l32i \a_temp4, \a_map, 0 // get as (vstart, valid)
- addi \a_num_entries, \a_num_entries, -1
- extui \a_temp1, \a_temp2, 0, 5 // entry index portion
- xor \a_temp2, \a_temp2, \a_temp1 // zero it
- or \a_temp2, \a_temp2, \a_temp3 // set index = \a_temp3
- j 2b
-4:
-#endif
-.endm
-
-/*
- * Macro for reading MPU map
- *
- * Parameters:
- * a_map_ptr => address register pointing to memory where map is written
- * a_temp1, a_temp2 => address register temporaries
- */
-.macro mpu_read_map a_map_ptr, a_temp1, a_temp2
-#if XCHAL_HAVE_MPU
- movi \a_temp1, XCHAL_MPU_ENTRIES // set index to last entry + 1
- addx8 \a_map_ptr, \a_temp1, \a_map_ptr // set map ptr to last entry + 1
-1: addi \a_temp1, \a_temp1, -1 // decrement index
- addi \a_map_ptr, \a_map_ptr, -8 // decrement index
- rptlb0 \a_temp2, \a_temp1 // read 1/2 of entry
- s32i \a_temp2, \a_map_ptr, 0 // write 1/2 of entry
- rptlb1 \a_temp2, \a_temp1
- s32i \a_temp2, \a_map_ptr, 4
- bnez \a_temp1, 1b // loop until done
-#endif
- .endm
-
-#endif
diff --git a/src/arch/xtensa/include/xtensa/overlay.h b/src/arch/xtensa/include/xtensa/overlay.h
deleted file mode 100644
index 9e41cd2..0000000
--- a/src/arch/xtensa/include/xtensa/overlay.h
+++ /dev/null
@@ -1,190 +0,0 @@
-// overlay.h -- Overlay manager header file
-// $Id$
-
-// Copyright (c) 2013 Tensilica Inc.
-//
-// Permission is hereby granted, free of charge, to any person obtaining
-// a copy of this software and associated documentation files (the
-// "Software"), to deal in the Software without restriction, including
-// without limitation the rights to use, copy, modify, merge, publish,
-// distribute, sublicense, and/or sell copies of the Software, and to
-// permit persons to whom the Software is furnished to do so, subject to
-// the following conditions:
-//
-// The above copyright notice and this permission notice shall be included
-// in all copies or substantial portions of the Software.
-//
-// THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
-// EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
-// MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
-// IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY
-// CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
-// TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
-// SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
-
-
-#ifndef OVERLAY_H
-#define OVERLAY_H
-
-
-#include <xtensa/xtruntime.h>
-
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-
-// Overlays not supported for CALL0 ABI
-#if defined (__XTENSA_CALL0_ABI__)
-#undef XT_DISABLE_OVERLAYS
-#define XT_DISABLE_OVERLAYS 1
-#endif
-
-// Define this to turn off overlay support
-#ifdef XT_DISABLE_OVERLAYS
-
-#define OVERLAY(n)
-#define DECLARE_OVERLAY(n)
-
-#define xt_overlay_map(ov_id)
-#define xt_overlay_map_async(ov_id) 0
-#define xt_overlay_map_in_progress() 0
-#define xt_overlay_get_id() 0
-#define xt_overlay_get_state(pc) 0
-#define xt_overlay_check_map(pc,ps,ovstate,sp) 0
-
-#else
-
-// Shorthand for convenience and portability.
-#define OVERLAY(n) __attribute__((overlay(n)))
-
-// Structure of the overlay table required by gdb and the overlay
-// manager. Should not be accessed by user code unless overriding
-// the load process.
-struct ovly_table {
- void * vma; // The overlay's mapped address.
- unsigned int size; // The size of the overlay, in bytes.
- void * lma; // The overlay's load address.
- unsigned int mapped; // Non-zero if overlay is currently mapped; zero otherwise.
-};
-
-// Constructed by the linker. Required for gdb and for the overlay
-// manager. Should not be accessed by user code unless overriding
-// the load process.
-extern struct ovly_table _ovly_table[];
-
-// Functions.
-void xt_overlay_map(int ov_id);
-int xt_overlay_map_async(int ov_id);
-int xt_overlay_map_in_progress(void);
-unsigned int xt_overlay_get_state(unsigned int pc);
-unsigned int xt_overlay_check_map(unsigned int * pc, unsigned int * ps,
- unsigned int ovstate, unsigned int sp);
-int xt_overlay_start_map(void * dst, void * src, unsigned int len, int ov_id);
-int xt_overlay_is_mapping(int ov_id);
-void xt_overlay_fatal_error(int ov_id);
-
-
-// Returns the current overlay ID. If no overlay is mapped or an overlay
-// is in the middle of being mapped, returns -1. Inlined to avoid calling
-// out of overlay (wastes cycles, can end up reading wrong ID on interrupt
-// activity).
-//
-static inline int __attribute__((always_inline)) xt_overlay_get_id(void)
-{
-extern short _mapping_id;
-extern short _ovly_id;
-
- int ret;
- unsigned int flags = XTOS_SET_INTLEVEL(15);
-
- if (_mapping_id >= 0) {
- ret = -1;
- }
- else {
- ret = _ovly_id;
- }
-
- XTOS_RESTORE_INTLEVEL(flags);
- return ret;
-}
-
-
-// The following macros are used to declare numbered overlays and generate
-// the corresponding call stubs. Use as follows:
-//
-// DECLARE_OVERLAY(n)
-//
-// See documentation for more details.
-
-//#include <xtensa/config/core-isa.h>
-
-// At this time overlays are not supported without windowing.
-#if defined(__XTENSA_WINDOWED_ABI__)
-
-#define xstr(x) str(x)
-#define str(x) #x
-
-// At entry, register a8 holds the return address and a9 holds the target
-// function address. This stub saves a8 on the stack at (SP - 20) which
-// is the only location that is safe for us to use. Then it allocates 32
-// bytes on the stack for working storage, loads the overlay number into
-// a8, and jumps to the common handler. The common handler will make sure
-// that the called function is loaded into memory before calling it.
-// NOTE: we are using the stack area normally reserved for nested functions.
-// This means nested functions cannot be used when overlays are in use.
-
-#define CALL_IN(num) \
- asm(".section .gnu.linkonce.t.overlay.call." xstr(num) ".text, \"ax\"\n" \
- ".global _overlay_call_in_" xstr(num) "_\n" \
- ".align 4\n" \
- "_overlay_call_in_" xstr(num) "_:\n" \
- "s32e a8, a1, -20\n" \
- "addi a8, a1, -32\n" \
- "movsp a1, a8\n" \
- "movi a8, " xstr(num) "\n" \
- "j _overlay_call_in_common\n" \
- ".size _overlay_call_in_" xstr(num) "_, . - _overlay_call_in_" xstr(num) "_\n");
-
-// The call-out stub first calls the target function, then loads the overlay
-// number into register a14 and jumps to the common handler. The handler will
-// make sure that the caller function is present in memory before returning.
-// Note that registers a10-a13 may contain return values so must be preserved.
-//
-// Because we came here via a call4, the return address is in a4, and the top
-// 2 bits are set to the window increment. We'll restore the top 2 bits of
-// the return address from the called function's address, assuming that both
-// are in the same 1 GB segment. For now this is always true.
-
-#define CALL_OUT(num) \
- asm(".section .gnu.linkonce.t.overlay.call." xstr(num) ".text, \"ax\"\n" \
- ".global _overlay_call_out_" xstr(num) "_\n" \
- ".align 4\n" \
- "_overlay_call_out_" xstr(num) "_:\n" \
- "slli a4, a4, 2\n" \
- "srli a4, a4, 2\n" \
- "extui a8, a9, 30, 2\n" \
- "slli a8, a8, 30\n" \
- "or a4, a4, a8\n" \
- "callx8 a9\n" \
- "movi a14, " xstr(num) "\n" \
- "j _overlay_call_out_common\n" \
- ".size _overlay_call_out_" xstr(num) "_, . - _overlay_call_out_" xstr(num) "_\n");
-
-// Generate a call-in and a call-out stub for each overlay.
-
-#define DECLARE_OVERLAY(num) \
- CALL_IN(num) \
- CALL_OUT(num)
-
-#endif // defined(__XTENSA_WINDOWED_ABI__)
-
-#endif // XT_DISABLE_OVERLAYS
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif // OVERLAY_H
-
diff --git a/src/arch/xtensa/include/xtensa/overlay_os_asm.h b/src/arch/xtensa/include/xtensa/overlay_os_asm.h
deleted file mode 100644
index 4adc044..0000000
--- a/src/arch/xtensa/include/xtensa/overlay_os_asm.h
+++ /dev/null
@@ -1,140 +0,0 @@
-// overlay_os_asm.h -- Overlay manager assembly macros for OS use.
-// $Id$
-
-// Copyright (c) 2013 Tensilica Inc.
-//
-// Permission is hereby granted, free of charge, to any person obtaining
-// a copy of this software and associated documentation files (the
-// "Software"), to deal in the Software without restriction, including
-// without limitation the rights to use, copy, modify, merge, publish,
-// distribute, sublicense, and/or sell copies of the Software, and to
-// permit persons to whom the Software is furnished to do so, subject to
-// the following conditions:
-//
-// The above copyright notice and this permission notice shall be included
-// in all copies or substantial portions of the Software.
-//
-// THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
-// EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
-// MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
-// IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY
-// CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
-// TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
-// SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
-
-
-#ifndef OVERLAY_OS_ASM_H
-#define OVERLAY_OS_ASM_H
-
-// The macros in here are intended to be used by RTOS task switch code
-// to check overlay status. Such code is usually in assembly and cannot
-// call C code without penalty. For C code usage, it is best to use the
-// corresponding C functions from the library.
-
-
-// Inline assembly version of xt_overlay_get_state(). The arguments are
-// three AR registers (a0-a15):
-//
-// "pcreg" - should contain the outgoing task's PC, i.e. the point at
-// which the task got interrupted. The return value is also
-// returned in this register.
-// "sr1/2" - Scratch registers. These must be distinct from "pcreg".
-//
-// The return value is a 32-bit result that should be saved with the
-// task context and passed as-is to xt_overlay_check_map.
-
- .macro _xt_overlay_get_state pcreg sr1 sr2
-
- movi \sr1, _mapping_id
- movi \sr2, _ovly_id
- l16si \sr1, \sr1, 0
- l16ui \sr2, \sr2, 0
- slli \sr1, \sr1, 16
- or \pcreg, \sr1, \sr2
-
- .endm
-
-
-// Inline assembly version of xt_overlay_check_map(). It requires 5 AR
-// registers (a0-a15) as arguments.
-//
-// "pcreg" - should contain the interrupted task's PC, i.e. the point
-// at which the task got interrupted. This will be adjusted
-// if required.
-// "psreg" - should contain the interrupted task's PS. This will be
-// adjusted if required.
-// "ovreg" - should contain the overlay state on entry. Contents may
-// be clobbered.
-// "spreg" - should contain the tasks stack pointer on entry.
-// "sr1" - Scratch register. Must be distinct from any of the above.
-//
-// The return values are "pcreg" and "psreg" and these must be used
-// to update the task's PC and PS.
-// Note that this macro may store data below the "spreg" pointer. If
-// it does, then it will also disable interrupts via the PS, so that
-// the task resumes with all interrupts disabled (to avoid corrupting
-// this data).
-//
-// (SP - 24) Overlay ID to restore
-// (SP - 28) Task PC
-// (SP - 32) Task PS
-
- .macro _xt_overlay_check_map pcreg psreg ovreg spreg sr1
-
-// There are four cases to deal with:
-//
-// _ovly_id = -1, _mapping_id = -1
-// No overlay is mapped or mapping, nothing to do.
-//
-// _ovly_id >= 0, _mapping_id = -1
-// An overlay was mapped, check PC to see if we need a restore.
-//
-// _ovly_id = -1, _mapping_id >= 0
-// An overlay is being mapped. Either it belongs to this task, which
-// implies that the PC is in the mapping function, or it does not
-// belong to this task. Either way there is nothing to do.
-//
-// _ovly_id >= 0, _mapping_id >= 0
-// Illegal, cannot happen by design. Don't need to handle this.
-//
-// So, the logic is to check _ovly_id first. If this is >= 0, then
-// we check the task PC. If the PC is in the regions of interest then
-// we'll patch the return PC to invoke xt_overlay_restore.
-
-.L1:
- extui \sr1, \ovreg, 0, 16 // Extract _ovly_id
- bbsi.l \sr1, 15, .Lno // If -1 then we're done
- mov \ovreg, \sr1 // Restore this one
-
-// Next check the PC to see if it falls within the ranges of interest.
-
-.L2:
- movi \sr1, _overlay_vma // Is PC < VMA range ?
- bltu \pcreg, \sr1, .L3
- movi \sr1, _overlay_vma_end // Is PC > VMA range ?
- bgeu \pcreg, \sr1, .L3
- j .L4 // PC is in VMA range
-.L3:
- movi \sr1, _overlay_call_stubs_start // Is PC < call stubs range ?
- bltu \pcreg, \sr1, .Lno
- movi \sr1, _overlay_call_stubs_end // Is PC > call stubs range ?
- bgeu \pcreg, \sr1, .Lno
-
-// If we get here then a restore is needed. Save the overlay ID, PC and PS.
-// Return modified PC and PS so that xt_overlay_restore() will execute in
-// the context of the task when resumed. Note that the OS resumption code
-// may expect PS.EXCM to be set so we leave it as is in the return value.
-
-.L4:
- s32e \ovreg, \spreg, -24 // Save overlay ID
- s32e \pcreg, \spreg, -28 // Save task PC
- s32e \psreg, \spreg, -32 // Save task PS
- movi \pcreg, xt_overlay_restore // Adjust resumption PC
- movi \sr1, 15
- or \psreg, \psreg, \sr1 // Set intlevel to highest
-.Lno:
-
- .endm
-
-#endif // OVERLAY_OS_ASM_H
-
diff --git a/src/arch/xtensa/include/xtensa/simboard.h b/src/arch/xtensa/include/xtensa/simboard.h
deleted file mode 100644
index 980b0b7..0000000
--- a/src/arch/xtensa/include/xtensa/simboard.h
+++ /dev/null
@@ -1,71 +0,0 @@
-/*
- * Copyright (c) 2001 Tensilica Inc.
- *
- * Permission is hereby granted, free of charge, to any person obtaining
- * a copy of this software and associated documentation files (the
- * "Software"), to deal in the Software without restriction, including
- * without limitation the rights to use, copy, modify, merge, publish,
- * distribute, sublicense, and/or sell copies of the Software, and to
- * permit persons to whom the Software is furnished to do so, subject to
- * the following conditions:
- *
- * The above copyright notice and this permission notice shall be included
- * in all copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
- * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
- * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
- * IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY
- * CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
- * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
- * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
- */
-
-/* simboard.h - Xtensa ISS "Board" specific definitions */
-
-#ifndef _INC_SIMBOARD_H_
-#define _INC_SIMBOARD_H_
-
-#include <xtensa/config/core.h>
-#include <xtensa/config/system.h>
-
-
-/*
- * Device addresses.
- */
-
-/* System ROM: */
-#define XTBOARD_ROM_SIZE XSHAL_ROM_SIZE
-#ifdef XSHAL_ROM_VADDR
-#define XTBOARD_ROM_VADDR XSHAL_ROM_VADDR
-#endif
-#ifdef XSHAL_ROM_PADDR
-#define XTBOARD_ROM_PADDR XSHAL_ROM_PADDR
-#endif
-
-/* System RAM: */
-#define XTBOARD_RAM_SIZE XSHAL_RAM_SIZE
-#ifdef XSHAL_RAM_VADDR
-#define XTBOARD_RAM_VADDR XSHAL_RAM_VADDR
-#endif
-#ifdef XSHAL_RAM_PADDR
-#define XTBOARD_RAM_PADDR XSHAL_RAM_PADDR
-#endif
-
-
-/*
- * Things that depend on device addresses.
- */
-
-#define XTBOARD_CACHEATTR_WRITEBACK XSHAL_ISS_CACHEATTR_WRITEBACK
-#define XTBOARD_CACHEATTR_WRITEALLOC XSHAL_ISS_CACHEATTR_WRITEALLOC
-#define XTBOARD_CACHEATTR_WRITETHRU XSHAL_ISS_CACHEATTR_WRITETHRU
-#define XTBOARD_CACHEATTR_BYPASS XSHAL_ISS_CACHEATTR_BYPASS
-#define XTBOARD_CACHEATTR_DEFAULT XSHAL_ISS_CACHEATTR_DEFAULT
-
-#define XTBOARD_BUSINT_PIPE_REGIONS 0
-#define XTBOARD_BUSINT_SDRAM_REGIONS 0
-
-
-#endif /*_INC_SIMBOARD_H_*/
-
diff --git a/src/arch/xtensa/include/xtensa/specreg.h b/src/arch/xtensa/include/xtensa/specreg.h
deleted file mode 100644
index 1805811..0000000
--- a/src/arch/xtensa/include/xtensa/specreg.h
+++ /dev/null
@@ -1,144 +0,0 @@
-/*
- * Xtensa Special Register symbolic names
- */
-
-/* $Id: //depot/rel/Foxhill/dot.8/Xtensa/OS/include/xtensa/specreg.h#1 $ */
-
-/*
- * Copyright (c) 2005-2011 Tensilica Inc.
- *
- * Permission is hereby granted, free of charge, to any person obtaining
- * a copy of this software and associated documentation files (the
- * "Software"), to deal in the Software without restriction, including
- * without limitation the rights to use, copy, modify, merge, publish,
- * distribute, sublicense, and/or sell copies of the Software, and to
- * permit persons to whom the Software is furnished to do so, subject to
- * the following conditions:
- *
- * The above copyright notice and this permission notice shall be included
- * in all copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
- * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
- * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
- * IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY
- * CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
- * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
- * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
- */
-
-#ifndef XTENSA_SPECREG_H
-#define XTENSA_SPECREG_H
-
-/* Special registers: */
-#define LBEG 0
-#define LEND 1
-#define LCOUNT 2
-#define SAR 3
-#define BR 4
-#define LITBASE 5
-#define SCOMPARE1 12
-#define ACCLO 16
-#define ACCHI 17
-#define MR_0 32
-#define MR_1 33
-#define MR_2 34
-#define MR_3 35
-#define PREFCTL 40
-#define WINDOWBASE 72
-#define WINDOWSTART 73
-#define PTEVADDR 83
-#define RASID 90
-#define ITLBCFG 91
-#define DTLBCFG 92
-#define IBREAKENABLE 96
-#define MEMCTL 97
-#define CACHEATTR 98 /* until T1050, XEA1 */
-#define CACHEADRDIS 98 /* LX7+ */
-#define ATOMCTL 99
-#define DDR 104
-#define MECR 110
-#define IBREAKA_0 128
-#define IBREAKA_1 129
-#define DBREAKA_0 144
-#define DBREAKA_1 145
-#define DBREAKC_0 160
-#define DBREAKC_1 161
-#define CONFIGID0 176
-#define EPC_1 177
-#define EPC_2 178
-#define EPC_3 179
-#define EPC_4 180
-#define EPC_5 181
-#define EPC_6 182
-#define EPC_7 183
-#define DEPC 192
-#define EPS_2 194
-#define EPS_3 195
-#define EPS_4 196
-#define EPS_5 197
-#define EPS_6 198
-#define EPS_7 199
-#define CONFIGID1 208
-#define EXCSAVE_1 209
-#define EXCSAVE_2 210
-#define EXCSAVE_3 211
-#define EXCSAVE_4 212
-#define EXCSAVE_5 213
-#define EXCSAVE_6 214
-#define EXCSAVE_7 215
-#define CPENABLE 224
-#define INTERRUPT 226
-#define INTREAD INTERRUPT /* alternate name for backward compatibility */
-#define INTSET INTERRUPT /* alternate name for backward compatibility */
-#define INTCLEAR 227
-#define INTENABLE 228
-#define PS 230
-#define VECBASE 231
-#define EXCCAUSE 232
-#define DEBUGCAUSE 233
-#define CCOUNT 234
-#define PRID 235
-#define ICOUNT 236
-#define ICOUNTLEVEL 237
-#define EXCVADDR 238
-#define CCOMPARE_0 240
-#define CCOMPARE_1 241
-#define CCOMPARE_2 242
-#define MISC_REG_0 244
-#define MISC_REG_1 245
-#define MISC_REG_2 246
-#define MISC_REG_3 247
-
-/* Special cases (bases of special register series): */
-#define MR 32
-#define IBREAKA 128
-#define DBREAKA 144
-#define DBREAKC 160
-#define EPC 176
-#define EPS 192
-#define EXCSAVE 208
-#define CCOMPARE 240
-#define MISC_REG 244
-
-/* Tensilica-defined user registers: */
-#if 0
-/*#define ... 21..24 */ /* (545CK) */
-/*#define ... 140..143 */ /* (545CK) */
-#define EXPSTATE 230 /* Diamond */
-#define THREADPTR 231 /* threadptr option */
-#define FCR 232 /* FPU */
-#define FSR 233 /* FPU */
-#define AE_OVF_SAR 240 /* HiFi2 */
-#define AE_BITHEAD 241 /* HiFi2 */
-#define AE_TS_FTS_BU_BP 242 /* HiFi2 */
-#define AE_SD_NO 243 /* HiFi2 */
-#define VSAR 240 /* VectraLX */
-#define ROUND_LO 242 /* VectraLX */
-#define ROUND_HI 243 /* VectraLX */
-#define CBEGIN 246 /* VectraLX */
-#define CEND 247 /* VectraLX */
-#endif
-
-#endif /* XTENSA_SPECREG_H */
-
diff --git a/src/arch/xtensa/include/xtensa/trax-api.h b/src/arch/xtensa/include/xtensa/trax-api.h
deleted file mode 100644
index aa15843..0000000
--- a/src/arch/xtensa/include/xtensa/trax-api.h
+++ /dev/null
@@ -1,93 +0,0 @@
-/* Misc TRAX API function definitions.
-
- Copyright (c) 2007-2012 Tensilica Inc.
-
- Permission is hereby granted, free of charge, to any person obtaining
- a copy of this software and associated documentation files (the
- "Software"), to deal in the Software without restriction, including
- without limitation the rights to use, copy, modify, merge, publish,
- distribute, sublicense, and/or sell copies of the Software, and to
- permit persons to whom the Software is furnished to do so, subject to
- the following conditions:
-
- The above copyright notice and this permission notice shall be included
- in all copies or substantial portions of the Software.
-
- THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
- EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
- MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
- IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY
- CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
- TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
- SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. */
-
-#ifndef _TRAX_API_H_
-#define _TRAX_API_H_
-
-#include <xtensa-isa.h>
-#include <xtensa-params.h>
-#include "tpack.h"
-#include "traxreg.h"
-
-#include "xdm-regs.h"
-
-/* Flags for trax_stop(): */
-#define TRAX_STOP_HALT 0x0001 /* halt immediately, don't wait for post-stop-trigger capture */
-#define TRAX_STOP_QUIET 0x0002 /* don't display informative messages */
-
-
-/*
- * Describes a TRAX channel (based on tpack).
- */
-typedef struct {
- tpack_channel chan; /* channel structure header */
- /* Per TRAX unit information: */
- int trax_version; /* TRAX_ID_VER(id), one of TRAX_VER_xxx macros */
- unsigned long trax_tram_size; /* size of trace RAM in bytes */
- int trax_erratum10; /* set if TRAX 1.0 erratum workarounds needed */
- int trax_erratum20; /* set if TRAX 2.0 erratum workaround needed (PR 22161)*/
- int trax_erratum20_size;
- int trax_has_busy; /* has trace-busy feature */
- int trax_has_atb; /* has ATB feature */
- /*FIXME: add various features: coresight regs (don't call it that), APB, ATB, TRAM, ... */
-} trax_channel;
-
-
-/* Prototypes: */
-
-/* TRAX Protocol API: */
-extern int trax_read_register(tpack_channel *tchan, int regno, unsigned *value);
-extern int trax_write_register(tpack_channel *tchan, int regno, unsigned value);
-extern int trax_read_memory(tpack_channel *tchan, int address, int size, unsigned char *pdata);
-extern int trax_fill_memory(tpack_channel *tchan, int address, int size, tpack_u32 pattern);
-extern int trax_enumerate_devices(tpack_channel *tchan, int * buf, int * size);
-
-/* TRAX Network API: */
-extern unsigned long trax_ram_size(tpack_channel *traxchan);
-extern unsigned long trax_ram_size_addr(tpack_channel *traxchan);
-extern int trax_create_tracefile(tpack_channel *traxchan, int size, unsigned char * data,
- char *filename, int hflags, const char *toolver);
-extern int trax_memaccess_safe(tpack_channel *traxchan, const char *what);
-extern int trax_start(tpack_channel *traxchan, int flags);
-extern int trax_stop(tpack_channel *traxchan, int flags);
-extern int trax_halt(tpack_channel *traxchan, int flags);
-extern int trax_save(tpack_channel *traxchan, char *filename, int flags, const char *toolver, int erratum);
-
-/* TRAX Misc API (no network dependencies): */
-int trax_fixed_hw(unsigned * regs);
-extern int trax_display_id(unsigned id, const char *prefix);
-extern int trax_display_summary(unsigned id,
- unsigned status,
- unsigned control,
- unsigned address,
- unsigned delay,
- unsigned trigger,
- unsigned match,
- unsigned startaddr,
- unsigned endaddr,
- const char *prefix);
-
-/* Other: */
-
-#endif /* _TRAX_API_H_ */
-
diff --git a/src/arch/xtensa/include/xtensa/trax-core-config.h b/src/arch/xtensa/include/xtensa/trax-core-config.h
deleted file mode 100644
index 42a0333..0000000
--- a/src/arch/xtensa/include/xtensa/trax-core-config.h
+++ /dev/null
@@ -1,144 +0,0 @@
-/* Definitions for Xtensa processor config info needed for TRAX.
-
- Copyright (c) 2005-2011 Tensilica Inc.
-
- Permission is hereby granted, free of charge, to any person obtaining
- a copy of this software and associated documentation files (the
- "Software"), to deal in the Software without restriction, including
- without limitation the rights to use, copy, modify, merge, publish,
- distribute, sublicense, and/or sell copies of the Software, and to
- permit persons to whom the Software is furnished to do so, subject to
- the following conditions:
-
- The above copyright notice and this permission notice shall be included
- in all copies or substantial portions of the Software.
-
- THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
- EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
- MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
- IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY
- CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
- TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
- SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. */
-
-#ifndef TRAX_CORE_CONFIG_H
-#define TRAX_CORE_CONFIG_H
-
-#include "xtensa-params.h"
-
-/*
- * Vector Enumerations.
- */
-
-/* These must match the LX2.0 and later traceport spec: */
-#define VEC_NO_VECTOR 0
-#define VEC_FIRST VEC_RESET /* first valid vector */
-#define VEC_RESET 1
-#define VEC_DEBUG 2
-#define VEC_NMI 3
-#define VEC_USER 4
-#define VEC_KERNEL 5
-#define VEC_DOUBLE 6
-#define VEC_MEMERR 7
-#define VEC_RESERVED8 8
-#define VEC_RESERVED9 9
-#define VEC_WINO4 10
-#define VEC_WINU4 11
-#define VEC_WINO8 12
-#define VEC_WINU8 13
-#define VEC_WINO12 14
-#define VEC_WINU12 15
-#define VEC_INTLEVEL2 16
-#define VEC_INTLEVEL3 17
-#define VEC_INTLEVEL4 18
-#define VEC_INTLEVEL5 19
-#define VEC_INTLEVEL6 20
-/* These are internal, i.e. don't appear like this on traceport: */
-#define VEC_DEBUG_OCD 21
-#define VEC_UNKNOWN 22
-/* Enumerations 23 through 31 are also reserved, but putting */
-/* placeholders here seems wasteful and unnecessary. */
-#define VEC_COUNT 23
-
-/* Other branch (change-of-PC-flow) type encodings;
- * if PC changes due to an exception or interrupt vector,
- * one of the VEC_* values above is used, otherwise
- * (or if it's unknown whether it's due to an exception/interrupt)
- * one of the following is used: */
-
-#define BRANCH_IS_VEC(n) ((n) < VEC_COUNT) /* is known to be except/interrupt? */
-#define BRANCH_OR_VEC 24 /* unknown type of branch (branch/exception/interrupt/etc) */
-#define BRANCH_UNKNOWN 25 /* unknown type of branch (anything but except/interrupt) */
-#define BRANCH_UNKNOWN_ERR 26 /* like BRANCH_UNKNOWN with known error (non-branch instr) */
-#define BRANCH_LOOPBACK 28 /* zero-overhead loopback (from LEND to LBEG) */
-#define BRANCH_CONDTAKEN 29 /* conditional branch taken (or LOOP{NEZ,GTZ} loop skip) */
-#define BRANCH_JUMP 30 /* jump (unconditional branch, i.e. J or JX) */
-#define BRANCH_IS_CALL(n) (((n) & ~3) == 32) /* is a function call? */
-#define BRANCH_CALL0 32 /* non-windowed function call (CALL0, CALLX0) */
-#define BRANCH_CALL4 33 /* windowed function call (CALL4, CALLX4) */
-#define BRANCH_CALL8 34 /* windowed function call (CALL8, CALLX8) */
-#define BRANCH_CALL12 35 /* windowed function call (CALL12, CALLX12) */
-#define BRANCH_IS_RETURN(n) ((n) >= 36) /* is any kind of return? */
-#define BRANCH_IS_CALLRETURN(n) (((n) & ~1) == 36) /* is a function return? */
-#define BRANCH_RET 36 /* non-windowed function return (RET or RET.N) */
-#define BRANCH_RETW 37 /* windowed function return (RETW or RETW.N) */
-#define BRANCH_IS_EIRETURN(n) ((n) >= 38) /* is an except/inter. return? */
-#define BRANCH_RFE 38 /* RFE or RFUE */
-#define BRANCH_RFDE 39 /* RFDE */
-#define BRANCH_RFWO 40 /* RFWO */
-#define BRANCH_RFWU 41 /* RFWU */
-#define BRANCH_RFI_2 42 /* RFI 2 */
-#define BRANCH_RFI_3 43 /* RFI 3 */
-#define BRANCH_RFI_4 44 /* RFI 4 */
-#define BRANCH_RFI_5 45 /* RFI 5 */
-#define BRANCH_RFI_6 46 /* RFI 6 */
-#define BRANCH_RFI_NMI 47 /* RFI NMILEVEL */
-#define BRANCH_RFI_DEBUG 48 /* RFI DEBUGLEVEL */
-#define BRANCH_RFME 49 /* RFME */
-#define BRANCH_COUNT 50 /* (number of defined BRANCH_xxx values) */
-
-
-
-typedef struct {
- unsigned vaddr;
- unsigned vaddr2; /* for static vectors only (reloc vectors option) */
- int is_configured;
-} trax_vector_t;
-
-
-/*
- * This structure describes those portion of a Tensilica processor's
- * configuration that are useful for trace.
- */
-typedef struct {
- char ** isa_dlls;
- char * core_name; /* (XPG core name, not necessarily same as XTENSA_CORE) */
- int big_endian; /* 0 = little-endian, 1 = big-endian */
- int has_loops; /* 1 = zero overhead loops configured */
- int has_autorefill; /* 1 = TLB autorefill (MMU) configured */
- unsigned max_instr_size; /* in bytes (eg. 3, 4, 8, ...) */
- unsigned int_level_max; /* number of interrupt levels configured (without NMI) */
- int debug_level; /* debug intlevel, 0 if debug not configured */
- int nmi_level; /* NMI intlevel, 0 if NMI not configured */
- unsigned targethw_min; /* min. targeted hardware version (XTENSA_HWVERSION_<rel>) */
- unsigned targethw_max; /* max. targeted hardware version (XTENSA_HWVERSION_<rel>) */
- int reloc_vectors; /* 0 = fixed vectors, 1 = relocatable vectors */
- int statvec_select; /* 0 = stat vec base 0, 1 = stat vec base 1 (SW default) */
- int vecbase_align; /* number of bits to align VECBASE (32 - bits in VECBASE) */
- unsigned statvec_base0; /* static vector base 0 */
- unsigned statvec_base1; /* static vector base 1 */
- unsigned vecbase_reset; /* reset value of VECBASE */
- trax_vector_t vectors[VEC_COUNT]; /* all vectors... */
-} trax_core_config_t;
-
-
-/* Globals: */
-//extern const char * const trax_vector_short_names[/*VEC_COUNT*/]; // nobody uses this one
-extern const char * const trax_vector_names[/*VEC_COUNT*/];
-
-/* Prototypes: */
-extern int trax_read_params (trax_core_config_t *c, xtensa_params p);
-extern int trax_vector_from_address(trax_core_config_t *config, unsigned long vaddr, unsigned long *vecbases);
-
-#endif /* TRAX_CORE_CONFIG_H */
-
diff --git a/src/arch/xtensa/include/xtensa/trax-proto.h b/src/arch/xtensa/include/xtensa/trax-proto.h
deleted file mode 100644
index 41d5c9f..0000000
--- a/src/arch/xtensa/include/xtensa/trax-proto.h
+++ /dev/null
@@ -1,91 +0,0 @@
-/* This file contains functions that are hidden from the user. These are
- * protocol specific functions used to read and write TRAX registers
- * and the trace memory
- */
-
-/*
- * Copyright (c) 2012-2013 Tensilica Inc.
- *
- * Permission is hereby granted, free of charge, to any person obtaining
- * a copy of this software and associated documentation files (the
- * "Software"), to deal in the Software without restriction, including
- * without limitation the rights to use, copy, modify, merge, publish,
- * distribute, sublicense, and/or sell copies of the Software, and to
- * permit persons to whom the Software is furnished to do so, subject to
- * the following conditions:
- *
- * The above copyright notice and this permission notice shall be included
- * in all copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
- * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
- * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
- * IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY
- * CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
- * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
- * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
- */
-#ifndef _TRAX_PROTO_H
-#define _TRAX_PROTO_H
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-/* Function to read register
- *
- * regno : The register number to be read (not ERI addressed)
- * data : Location where the read value is kept
- *
- * returns : 0 if successful, -1 if unsuccessful
- */
-int trax_read_register_eri (int regno, unsigned *data);
-
-/* Function to write a value into a register
- *
- * regno : The register number to be written (not ERI addressed)
- * value : The value to be written at that register location
- *
- * returns : 0 if successful, -1 if unsuccessful
- */
-int trax_write_register_eri (int regno, unsigned value);
-
-/* Function to read memory
- *
- * address : Address of the TraceRAM memory, each location has a word
- * len : Amount of memory in bytes, to be read
- * data : buffer in which the read memory is stored
- * final_address: Next address to be read in the following call to this
- * function (trace save mechanism)
- *
- * returns : 0 if successful, -1 if unsuccessful
- */
-int trax_read_memory_eri (unsigned address, int len, int *data,
- unsigned *final_address);
-
-/* Function to write a value to the memory address
- *
- * address : Address of the TraceRAM memory
- * value : The value to be written inside that location
- *
- * returns : 0 if successful, -1 if unsuccessful
- */
-int trax_write_memory_eri (int address, unsigned value);
-
-/* Function to write to a subfield of the register.
- * Called by set and show parameter functions.
- *
- * regno : Register number
- * regmask : Mask in order to toggle appropriate bits
- * value : Value to be written in the masked location
- *
- * returns : 0 if successful, -1 if unsuccessful
- */
-int trax_write_register_field_eri (int regno, unsigned regmask,
- unsigned value);
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif
diff --git a/src/arch/xtensa/include/xtensa/trax-util.h b/src/arch/xtensa/include/xtensa/trax-util.h
deleted file mode 100644
index 123ac36..0000000
--- a/src/arch/xtensa/include/xtensa/trax-util.h
+++ /dev/null
@@ -1,63 +0,0 @@
-/* This file contains utility functions that can be used for polling TRAX
- * or executing higher level save functionality
- * It assumes that print subroutines and file I/O routines are available
- * on the system
- */
-
-/*
- * Copyright (c) 2012-2013 Tensilica Inc.
- *
- * Permission is hereby granted, free of charge, to any person obtaining
- * a copy of this software and associated documentation files (the
- * "Software"), to deal in the Software without restriction, including
- * without limitation the rights to use, copy, modify, merge, publish,
- * distribute, sublicense, and/or sell copies of the Software, and to
- * permit persons to whom the Software is furnished to do so, subject to
- * the following conditions:
- *
- * The above copyright notice and this permission notice shall be included
- * in all copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
- * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
- * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
- * IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY
- * CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
- * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
- * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
- */
-
-#ifndef _TRAX_UTIL_H
-#define _TRAX_UTIL_H
-
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-/* User can use this function if he wants to generate a tracefile output.
- * Internally it calls trax_get_trace in a loop until it realizes that
- * the entire trace has been read.
- *
- * context : pointer to structure which contains information about the
- * current TRAX session
- * filename : user specified output trace file name. If the file does not
- * exist, it would create the new file, else would append to it
- *
- * returns : 0 if successful, -1 if unsuccessful
- */
-int trax_save (trax_context *context, char *filename);
-
-/* Displays a brief machine readable status.
- *
- * context : pointer to structure which contains information about the
- * current TRAX session
- * returns : 0 if successful, -1 if unsuccessful
- */
-int trax_poll (trax_context *context);
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif
diff --git a/src/arch/xtensa/include/xtensa/trax.h b/src/arch/xtensa/include/xtensa/trax.h
deleted file mode 100644
index 47049c5..0000000
--- a/src/arch/xtensa/include/xtensa/trax.h
+++ /dev/null
@@ -1,409 +0,0 @@
-/* Header file for TRAX control Library */
-
-/*
- * Copyright (c) 2012-2013 Tensilica Inc.
- *
- * Permission is hereby granted, free of charge, to any person obtaining
- * a copy of this software and associated documentation files (the
- * "Software"), to deal in the Software without restriction, including
- * without limitation the rights to use, copy, modify, merge, publish,
- * distribute, sublicense, and/or sell copies of the Software, and to
- * permit persons to whom the Software is furnished to do so, subject to
- * the following conditions:
- *
- * The above copyright notice and this permission notice shall be included
- * in all copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
- * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
- * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
- * IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY
- * CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
- * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
- * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
- */
-
-#ifndef _TRAX_H
-#define _TRAX_H
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-#define TRAX_STOP_HALT 0x0001
-#define TRAX_STOP_QUIET 0x0002
-
-/* Flag values to indicate if the user wanted to reverse the pcstop
- * parameters */
-#define TRAX_PCSTOP_REVERSE 0x0001
-#define TRAX_PCSTOP_NO_REVERSE 0x0000
-
-/* Indicating whether postsize should be in terms of bytes, instructions
- * or percentage of trace size captured */
-#define TRAX_POSTSIZE_BYTES 0x0000
-#define TRAX_POSTSIZE_INSTR 0x0001
-#define TRAX_POSTSIZE_PERCENT 0x0002
-
-/* Size of the header inside the trace file */
-#define TRAX_HEADER_SIZE 256
-
-/* Minimum size between start and end addresses */
-#define TRAX_MIN_TRACEMEM 64
-
-/* For basic debugging */
-#define DEBUG 0
-
-#include <stdbool.h>
-
-#define ffs(i) __builtin_ffs(i)
-
-/* Data structures */
-
-/* Represents the context of the TRAX unit and the current TRAX session.
- * To be used by set and show function calls to set and show appropriate
- * parameters of appropriate TRAX unit.
- */
-
-typedef struct {
- int trax_version; /* TRAX PC version information */
- unsigned long trax_tram_size; /* If trace RAM is present,size of it */
- int hflags; /* Flags that can be used to debug,
- print info, etc. */
- int address_read_last; /* During saving of the trace, this
- indicates the address from which
- the current trace reading must
- resume */
- unsigned long bytes_read; /* bytes read uptil now */
- unsigned long total_memlen; /* Total bytes to be read based on the
- trace collected in the trace RAM */
- bool get_trace_started; /* indicates that the first chunk of
- bytes (which include the header) has
- been read */
-} trax_context;
-
-
-/* -----------------------TRAX Initialization ------------------------------*/
-
-/* Initializing the trax context. Reads registers and sets values for version,
- * trace RAM size, total memory length, etc. Most of the other values are
- * initialized to their default case.
- *
- * context : pointer to structure which contains information about the
- * current TRAX session
- *
- * returns : 0 if successful, -1 if unsuccessful, -2 if ram_size if
- * incorrect
- */
-int trax_context_init_eri (trax_context *context);
-
-/* -----------------Starting/Stopping TRAX session -------------------------*/
-
-/* Start tracing with current parameter setting. If tracing is already in
- * progress, an error is reported. Otherwise, tracing starts and any unsaved
- * contents of the TraceRAM is discarded
- *
- * context : pointer to structure which contains information about the
- * current TRAX session
- * returns : 0 if successful, 1 if trace is already active,
- * -1 if unsuccessful
- */
-int trax_start (trax_context *context);
-
-/* This command initiates a stop trigger or halts a trace session based of the
- * value of the flag parameter passed. In case stop trigger is initiated, any
- * selected post-stop-trigger capture proceeds normally.
- * If trace capture was not in progress, or a stop was already triggered, the
- * return value indicates appropriately.
- *
- * context : pointer to structure which contains information about the
- * current TRAX session
- * flags : To differentiate between stopping trace without any
- * post-size-trigger capture (trax_halt) or with that.
- * A zero value would stop the trace based on trigger and a
- * value of one would halt it
- *
- * returns : 0 if successful, 1 if already stopped, -1 if unsuccessful
- */
-int trax_stop_halt (trax_context *context, int flags);
-
-/* Resets the TRAX parameters to their default values which would internally
- * involve resetting the TRAX registers. To invoke another trace session or
- * reset the current tracing mechanism, this function needs to be called as
- * it resets parameters of the context that deal with tracing information
- *
- * context : pointer to structure which contains information about the
- * current TRAX session
- *
- * returns : 0 if successful, -1 if unsuccessful
- */
-int trax_reset (trax_context *context);
-
-/* ---------------Set/Get several TRAX parameters --------------------------*/
-
-/* Sets the start address and end address (word aligned) of the trace in the
- * TraceRAM. Care must be taken to ensure that the difference between the
- * start and the end addresses is atleast TRAX_MIN_TRACEMEM bytes. If not,
- * the values are reset to default, which is 0 for startaddr and
- * traceRAM_words -1 for endaddr
- *
- * context : pointer to structure which contains information about the
- * current TRAX session
- * startaddr : value to which the start address must be set. Can be
- * any value between 0 - (traceRAM_words - 1)
- * endaddr : value to which the end address must be set. Can be any value
- * between 0 - (traceRAM_words - 1)
- *
- * returns : 0 if successful, -1 if unsuccessful, -2 if the difference
- * between the start and end addresses is less than
- * TRAX_MIN_TRACEMEM bytes or if they are passed incorrect
- * values, -3 if memory shared option is not configured, in
- * which case, start and end addresses are set to default
- * values instead of those passed by the user
- */
-int trax_set_ram_boundaries (trax_context *context, unsigned startaddr,
- unsigned endaddr);
-
-/* Shows the start address and end address(word aligned) of the trace in the
- * TraceRAM. If incorrect, the startaddress and the endaddress values are
- * set to default, i.e. 0 for startaddr and traceRAM_words - 1 for endaddr
- *
- * context : pointer to structure which contains information about the
- * current TRAX session
- * startaddr : pointer to value which will contain the start address
- * endaddr : pointer to value which will contain the end address
- *
- * returns : 0 if successful, -1 if unsuccessful
- *
- */
-int trax_get_ram_boundaries (trax_context *context, unsigned *startaddr,
- unsigned *endaddr);
-
-/* Selects stop trigger via cross-trigger input
- *
- * context : pointer to structure which contains information about the
- * current TRAX session
- * value : 0 = off (reset value), 1 = on
- *
- * returns : 0 if successful, -1 if unsuccessful
- */
-int trax_set_ctistop (trax_context *context, unsigned value);
-
-/* Shows if stop-trigger via cross-trigger input is off or on
- *
- * context : pointer to structure which contains information about the
- * current TRAX session
- * returns : 0 if off, 1 if on, -1 if unsuccessful
- */
-int trax_get_ctistop (trax_context *context);
-
-/* Selects stop trigger via processor-trigger input
- *
- * context : pointer to structure which contains information about the
- * current TRAX session
- * value : 0 = off (reset value), 1 = on
- *
- * returns : 0 if successful, -1 if unsuccessful
- */
-int trax_set_ptistop (trax_context *context, unsigned value);
-
-/* Shows if stop trigger visa processor-trigger input is off or on
- *
- * context : pointer to structure which contains information about the
- * current TRAX session
- * returns : 0 if off, 1 if on, -1 if unsuccessful
- */
-int trax_get_ptistop (trax_context *context);
-
-/* Reports cross trigger output state
- *
- * context : pointer to structure which contains information about the
- * current TRAX session
- * returns : 0 if CTO bit is reset, 1 if CTO bit is set
- */
-int trax_get_cto (trax_context *context);
-
-/* Reports processor trigger output state
- *
- * context : pointer to structure which contains information about the
- * current TRAX session
- * returns : 0 if PTO bit is reset, 1 if PTO bit is set
- */
-int trax_get_pto (trax_context *context);
-
-/* Selects condition that asserts cross trigger output
- *
- * context : pointer to structure which contains information about the
- * current TRAX session
- * option : 0 = off(reset value)/1 = ontrig/2 = onhalt
- *
- * returns : 0 if successful, -1 if unsuccessful
- */
-int trax_set_ctowhen (trax_context *context, int option);
-
-/* Shows condition that asserted cross trigger output. It can be
- * any of: ontrig or onhalt or even off
- *
- * context : pointer to structure which contains information about the
- * current TRAX session
- *
- * returns : 0 if off, 1 if ontrig, 2 if onhalt, -1 if unsuccessful
- */
-int trax_get_ctowhen (trax_context *context);
-
-/* Selects condition that asserts processor trigger output
- *
- * context : pointer to structure which contains information about the
- * current TRAX session
- * option : 0 = off(reset value)/1 = ontrig/2 = onhalt
- *
- * returns : 0 if successful, -1 if unsuccessful
- */
-int trax_set_ptowhen (trax_context *context, int option);
-
-
-/* Shows condition that asserted processor trigger output. It can be
- * any of: ontrig or onhalt or even off
- *
- * context : pointer to structure which contains information about the
- * current TRAX session
- * returns : 0 if off, 1 if ontrig, 2 if onhalt, -1 if unsuccessful
- */
-int trax_get_ptowhen (trax_context *context);
-
-/* Selects the trace synchronization message period.
- * If ATEN enabled, we cannot allow syncper to be off, set it to reset value.
- * Also, if no trace RAM, and ATEN enabled, set syncper to be reset value
- * i.e. 256. A value of 1 i.e. on indicates that internally the message
- * frequency is set to an optimal value. This option should be preferred
- * if the user is not sure what message frequency option to set for the
- * trace session.
- *
- * context : pointer to structure which contains information about the
- * current TRAX session
- * option : 0 = off, 1 = on, -1 = auto, 8, 16, 32, 64, 128,
- * 256 (reset value)
- *
- * returns : 0 if successful, -1 if unsuccessful, -2 if incorrect
- * arguments
- */
-int trax_set_syncper (trax_context *context, int option);
-
-/* Shows trace synchronization message period. Can be one of:
- * off, on, auto, 8, 16, 32, 64, 128, 256 (reset value)
- *
- * context : pointer to structure which contains information about the
- * current TRAX session
- * returns : value of sync period, 0 if off, -1 if unsuccessful
- */
-int trax_get_syncper (trax_context *context);
-
-/* Selects stop trigger via PC match. Specifies the address or
- * address range to match against program counter. Trace stops when the
- * processor executes an instruction matching the specified address
- * or range.
- *
- * context : pointer to structure which contains information about the
- * current TRAX session
- * index : indicates the number of stop trigger (currently there is
- * only one i.e. index = 0)
- * startaddress : start range of the address at which the stop trigger
- * should be activated
- * enaddress : end range of the address at which the stop trigger should
- * be activated
- * flags : If non-zero, this inverts the range. i.e. trace stops
- * when the processor executes an instruction that does not
- * match the specified address or range
- *
- * returns : 0 if successful, -1 if unsuccessful, -2 if incorrect
- * arguments (unaligned)
- *
- * Note : For the current version of TRAX library, the endaddress and
- * startaddress can differ by at most 31 bytes and the total
- * range i.e. (endaddress - startaddress + 1) has to be a power
- * of two
- */
-int trax_set_pcstop (trax_context *context, int index, unsigned long startaddress,
- unsigned long endaddress, int flags);
-
-/* Shows the stop trigger via PC match
- *
- * context : pointer to structure which contains information about the
- * current TRAX session
- * index : container of information about the number of stop triggers
- * startaddress : container of start range of stop trigger
- * endaddress : container of end range of stop trigger
- * flags : container of information whcih indicates whether the
- * pc stop range is inverted or not.
- *
- * returns : 0 if successful, -1 if unsuccessful
- */
-int trax_get_pcstop (trax_context *context, int *index,
- unsigned long *startaddress,
- unsigned long *endaddress, int *flags);
-
-/* This function is used to set the amount of trace to be captured past
- * the stop trigger.
- *
- * context : pointer to structure which contains information about the
- * current TRAX session
- * count_unit : contains the count of units (instructions or bytes) to be
- * captured post trigger. If 0, it implies that this is off
- * unit : unit of measuring the count. 0 is bytes, 1 is instructions
- * 2 is percentage of trace
- *
- * returns : 0 if successful, -1 if unsuccessful, -2 if incorrect
- * arguments
- *
- */
-int trax_set_postsize (trax_context *context, int count_unit, int unit);
-
-/* This function shows the amount of TraceRAM in terms of the number of
- * instructions or bytes, captured post the stop trigger
- *
- * context : pointer to structure which contains information about the
- * current TRAX session
- * count_unit : will contain the count of units(instructions or bytes) post
- * trigger
- * unit : will contain information about the events that are counted
- * 0 implies that the traceRAM words consumed are counted and
- * 1 implies that the target processor instructions executed and
- * excpetions/interrupts taken are counted
- *
- * returns : 0 if postsize was got successfully, -1 if unsuccessful
- */
-int trax_get_postsize (trax_context *context, int *count_unit, int *unit);
-
-/* -------------------------- TRAX save routines ---------------------------*/
-
-/* This function should be called by the user to return a chunk of
- * bytes in buf. It can be a lower layer function of save, or can be
- * called by the user explicitly. If bytes_actually_read contains a 0
- * after a call to this function has been made, it implies that the entire
- * trace has been read successfully.
- *
- * context : pointer to structure which contains information about
- * the current TRAX session
- * buf : Buffer that is allocated by the user, all the trace
- * data read would be put in this buffer, which can then
- * be used to generate a tracefile.
- * The first TRAX_HEADER_SIZE of the buffer will always
- * contain the header information.
- * bytes_to_be_read : Indicates the bytes the user wants to read. The first
- * invocation would need this parameter to be
- * TRAX_HEADER_SIZE at least.
- *
- * returns : bytes actually read during the call to this function.
- * 0 implies that all the bytes in the trace have been
- * read, -1 if unsuccessful read/write of
- * registers or memory, -2 if trace was active while
- * this function was called, -3 if user enters
- * bytes_to_be_read < TRAX_HEADER_SIZE in the first
- * pass
- */
-int trax_get_trace (trax_context *context, void *buf,
- int bytes_to_be_read);
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* _TRAX_H */
diff --git a/src/arch/xtensa/include/xtensa/traxfile.h b/src/arch/xtensa/include/xtensa/traxfile.h
deleted file mode 100644
index 4afc926..0000000
--- a/src/arch/xtensa/include/xtensa/traxfile.h
+++ /dev/null
@@ -1,62 +0,0 @@
-/* TRAX file header definition.
-
- Copyright (c) 2007-2012 Tensilica Inc.
-
- Permission is hereby granted, free of charge, to any person obtaining
- a copy of this software and associated documentation files (the
- "Software"), to deal in the Software without restriction, including
- without limitation the rights to use, copy, modify, merge, publish,
- distribute, sublicense, and/or sell copies of the Software, and to
- permit persons to whom the Software is furnished to do so, subject to
- the following conditions:
-
- The above copyright notice and this permission notice shall be included
- in all copies or substantial portions of the Software.
-
- THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
- EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
- MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
- IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY
- CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
- TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
- SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. */
-
-
-#define TRAX_FHEAD_MAGIC "TRAXdmp"
-#define TRAX_FHEAD_VERSION 1
-
-/* Header flags: */
-#define TRAX_FHEADF_OCD_ENABLED 0x00000001 /* set if OCD was enabled while capturing trace */
-#define TRAX_FHEADF_TESTDUMP 0x00000002 /* set if is a test file
- (from 'memsave' instead of 'save') */
-#define TRAX_FHEADF_OCD_ENABLED_WHILE_EXIT 0x00000004 /* set if OCD was enabled while capturing trace and
- we were exiting the OCD mode */
-
-/* Header at the start of a TRAX dump file. */
-typedef struct {
- char magic[8]; /* 00: "TRAXdmp\0" (TRAX_FHEAD_MAGIC) */
- char endianness; /* 08: 0=little-endian, 1=big-endian */
- char version; /* 09: TRAX_FHEAD_VERSION */
- char reserved0[2]; /* 0A: ... */
- unsigned filesize; /* 0C: size of the trace file, including this header */
- unsigned trace_ofs; /* 10: start of trace output, byte offset from start of header */
- unsigned trace_size; /* 14: size of trace output in bytes */
- unsigned dumptime; /* 18: date/time of capture save (secs since 1970-01-01), 0 if unknown */
- unsigned flags; /* 1C: misc flags (TRAX_FHEAD_F_xxx) */
- char username[16]; /* 20: user doing the capture/save (up to 15 chars) */
- char toolver[24]; /* 30: tool + version used for capture/save (up to 23 chars) */
- char reserved2[40]; /* 48: (reserved - could be hostname used for dump (up to 39 chars)) */
- unsigned configid[2]; /* 70: processor ConfigID values, 0 if unknown */
- unsigned ts_freq; /* 78: timestamp frequency, 0 if not specified */
- unsigned reserved3; /* 7C: (reserved) */
- unsigned id; /* 80: TRAX registers at time of save (0 if not read) */
- unsigned control;
- unsigned status;
- unsigned reserved4; /* Data register (should not be read) */
- unsigned address;
- unsigned trigger;
- unsigned match;
- unsigned delay;
- unsigned trax_regs[24]; /*100: (total size) -- dummy allocation (FIXME) */
-} trax_file_header;
-
diff --git a/src/arch/xtensa/include/xtensa/traxreg.h b/src/arch/xtensa/include/xtensa/traxreg.h
deleted file mode 100644
index 282ba1f..0000000
--- a/src/arch/xtensa/include/xtensa/traxreg.h
+++ /dev/null
@@ -1,199 +0,0 @@
-/* TRAX register definitions
-
- Copyright (c) 2006-2012 Tensilica Inc.
-
- Permission is hereby granted, free of charge, to any person obtaining
- a copy of this software and associated documentation files (the
- "Software"), to deal in the Software without restriction, including
- without limitation the rights to use, copy, modify, merge, publish,
- distribute, sublicense, and/or sell copies of the Software, and to
- permit persons to whom the Software is furnished to do so, subject to
- the following conditions:
-
- The above copyright notice and this permission notice shall be included
- in all copies or substantial portions of the Software.
-
- THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
- EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
- MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
- IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY
- CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
- TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
- SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. */
-
-#ifndef _TRAX_REGISTERS_H_
-#define _TRAX_REGISTERS_H_
-
-#define SHOW 1
-#define HIDE 0
-
-#define RO 0
-#define RW 1
-
-/* TRAX Register Numbers (from possible range of 0..127) */
-#if 0
-#define TRAXREG_ID 0
-#define TRAXREG_CONTROL 1
-#define TRAXREG_STATUS 2
-#define TRAXREG_DATA 3
-#define TRAXREG_ADDRESS 4
-#define TRAXREG_TRIGGER 5
-#define TRAXREG_MATCH 6
-#define TRAXREG_DELAY 7
-#define TRAXREG_STARTADDR 8
-#define TRAXREG_ENDADDR 9
-/* Internal use only (unpublished): */
-#define TRAXREG_P4CHANGE 16
-#define TRAXREG_P4REV 17
-#define TRAXREG_P4DATE 18
-#define TRAXREG_P4TIME 19
-#define TRAXREG_PDSTATUS 20
-#define TRAXREG_PDDATA 21
-#define TRAXREG_STOP_PC 22
-#define TRAXREG_STOP_ICNT 23
-#define TRAXREG_MSG_STATUS 24
-#define TRAXREG_FSM_STATUS 25
-#define TRAXREG_IB_STATUS 26
-#define TRAXREG_MAX 27
-#define TRAXREG_ITCTRL 96
-#endif
-/* The registers above match the NAR addresses. So, their values are used for NAR access */
-
-/* TRAX Register Fields */
-
-/* TRAX ID register fields: */
-#define TRAX_ID_PRODNO 0xf0000000 /* product number (0=TRAX) */
-#define TRAX_ID_PRODOPT 0x0f000000 /* product options */
-#define TRAX_ID_MIW64 0x08000000 /* opt: instruction width */
-#define TRAX_ID_AMTRAX 0x04000000 /* opt: collection of options,
- internal (VER_2_0 or later)*/
-#define TRAX_ID_MAJVER(id) (((id) >> 20) & 0x0f)
-#define TRAX_ID_MINVER(id) (((id) >> 17) & 0x07)
-#define TRAX_ID_VER(id) ((TRAX_ID_MAJVER(id)<<4)|TRAX_ID_MINVER(id))
-#define TRAX_ID_STDCFG 0x00010000 /* standard config */
-#define TRAX_ID_CFGID 0x0000ffff /* TRAX configuration ID */
-#define TRAX_ID_MEMSHARED 0x00001000 /* Memshared option in TRAX */
-#define TRAX_ID_FROM_VER(ver) ((((ver) & 0xf0) << 16) | (((ver) & 0x7) << 17))
-/* Other TRAX ID register macros: */
-/* TRAX versions of interest (TRAX_ID_VER(), ie. MAJVER*16 + MINVER): */
-#define TRAX_VER_1_0 0x10 /* RA */
-#define TRAX_VER_1_1 0x11 /* RB thru RC-2010.1 */
-#define TRAX_VER_2_0 0x20 /* RC-2010.2, RD-2010.0,
- RD-2011.1 */
-#define TRAX_VER_2_1 0x21 /* RC-2011.3 / RD-2011.2 and
- later */
-#define TRAX_VER_3_0 0x30 /* RE-2012.0 */
-#define TRAX_VER_3_1 0x31 /* RE-2012.1 */
-#define TRAX_VER_HUAWEI_3 TRAX_VER_3_0 /* For Huawei, PRs: 25223, 25224
- , 24880 */
-
-
-/* TRAX version 1.0 requires a couple software workarounds: */
-#define TRAX_ID_1_0_ERRATUM(id) (TRAX_ID_VER(id) == TRAX_VER_1_0)
-/* TRAX version 2.0 requires software workaround for PR 22161: */
-#define TRAX_ID_MEMSZ_ERRATUM(id) (TRAX_ID_VER(id) == TRAX_VER_2_0)
-
-/* TRAX Control register fields: */
-#define TRAX_CONTROL_TREN 0x00000001
-#define TRAX_CONTROL_TRSTP 0x00000002
-#define TRAX_CONTROL_PCMEN 0x00000004
-#define TRAX_CONTROL_PTIEN 0x00000010
-#define TRAX_CONTROL_CTIEN 0x00000020
-#define TRAX_CONTROL_TMEN 0x00000080 /* 2.0+ */
-#define TRAX_CONTROL_CNTU 0x00000200
-#define TRAX_CONTROL_BIEN 0x00000400
-#define TRAX_CONTROL_BOEN 0x00000800
-#define TRAX_CONTROL_TSEN 0x00000800
-#define TRAX_CONTROL_SMPER 0x00007000
-#define TRAX_CONTROL_SMPER_SHIFT 12
-#define TRAX_CONTROL_PTOWT 0x00010000
-#define TRAX_CONTROL_CTOWT 0x00020000
-#define TRAX_CONTROL_PTOWS 0x00100000
-#define TRAX_CONTROL_CTOWS 0x00200000
-#define TRAX_CONTROL_ATID 0x7F000000 /* 2.0+, amtrax */
-#define TRAX_CONTROL_ATID_SHIFT 24
-#define TRAX_CONTROL_ATEN 0x80000000 /* 2.0+, amtrax */
-
-#define TRAX_CONTROL_PTOWS_ER 0x00020000 /* For 3.0 */
-#define TRAX_CONTROL_CTOWT_ER 0x00100000 /* For 3.0 */
-
-#define TRAX_CONTROL_ITCTO 0x00400000 /* For 3.0 */
-#define TRAX_CONTROL_ITCTIA 0x00800000 /* For 3.0 */
-#define TRAX_CONTROL_ITATV 0x01000000 /* For 3.0 */
-
-
-/* TRAX Status register fields: */
-#define TRAX_STATUS_TRACT 0x00000001
-#define TRAX_STATUS_TRIG 0x00000002
-#define TRAX_STATUS_PCMTG 0x00000004
-#define TRAX_STATUS_BUSY 0x00000008 /* ER ??? */
-#define TRAX_STATUS_PTITG 0x00000010
-#define TRAX_STATUS_CTITG 0x00000020
-#define TRAX_STATUS_MEMSZ 0x00001F00
-#define TRAX_STATUS_MEMSZ_SHIFT 8
-#define TRAX_STATUS_PTO 0x00010000
-#define TRAX_STATUS_CTO 0x00020000
-
-#define TRAX_STATUS_ITCTOA 0x00400000 /* For 3.0 */
-#define TRAX_STATUS_ITCTI 0x00800000 /* For 3.0 */
-#define TRAX_STATUS_ITATR 0x01000000 /* For 3.0 */
-
-
-/* TRAX Address register fields: */
-#define TRAX_ADDRESS_TWSAT 0x80000000
-#define TRAX_ADDRESS_TWSAT_SHIFT 31
-#define TRAX_ADDRESS_TOTALMASK 0x00FFFFFF
-// !!! VUakiVU. added for new TRAX:
-#define TRAX_ADDRESS_WRAPCNT 0x7FE00000 /* version ???... */
-#define TRAX_ADDRESS_WRAP_SHIFT 21
-
-/* TRAX PCMatch register fields: */
-#define TRAX_PCMATCH_PCML 0x0000001F
-#define TRAX_PCMATCH_PCML_SHIFT 0
-#define TRAX_PCMATCH_PCMS 0x80000000
-
-/* Compute trace ram buffer size (in bytes) from status register: */
-#define TRAX_MEM_SIZE(status) (1L << (((status) & TRAX_STATUS_MEMSZ) >> TRAX_STATUS_MEMSZ_SHIFT))
-
-#if 0
-/* Describes a field within a register: */
-typedef struct {
- const char* name;
-// unsigned width;
-// unsigned shift;
- char width;
- char shift;
- char visible; /* 0 = internal use only, 1 = shown */
- char reserved;
-} trax_regfield_t;
-#endif
-
-/* Describes a TRAX register: */
-typedef struct {
- const char* name;
- unsigned id;
- char width;
- char visible;
- char writable;
- char reserved;
- //const trax_regfield_t * fieldset;
-} trax_regdef_t;
-
-
-extern const trax_regdef_t trax_reglist[];
-extern const signed char trax_readable_regs[];
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-/* Prototypes: */
-extern int trax_find_reg(char * regname, char **errmsg);
-extern const char * trax_regname(int regno);
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* _TRAX_REGISTERS_H_ */
-
diff --git a/src/arch/xtensa/include/xtensa/uart-16550.h b/src/arch/xtensa/include/xtensa/uart-16550.h
deleted file mode 100644
index c551c64..0000000
--- a/src/arch/xtensa/include/xtensa/uart-16550.h
+++ /dev/null
@@ -1,152 +0,0 @@
-/*******************************************************************************
-
- Copyright (c) 2006-2007 Tensilica Inc.
-
- Permission is hereby granted, free of charge, to any person obtaining
- a copy of this software and associated documentation files (the
- "Software"), to deal in the Software without restriction, including
- without limitation the rights to use, copy, modify, merge, publish,
- distribute, sublicense, and/or sell copies of the Software, and to
- permit persons to whom the Software is furnished to do so, subject to
- the following conditions:
-
- The above copyright notice and this permission notice shall be included
- in all copies or substantial portions of the Software.
-
- THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
- EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
- MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
- IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY
- CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
- TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
- SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
-
---------------------------------------------------------------------------------
-
-uart-16550.h Generic definitions for National Semiconductor 16550 UART
-
-This is used by board-support-packages with one or more 16550 compatible UARTs.
-A BSP provides a base address for each instance of a 16550 UART on the board.
-
-Note that a 16552 DUART (Dual UART) is simply two instances of a 16550 UART.
-
-*******************************************************************************/
-
-#ifndef _UART_16550_H_
-#define _UART_16550_H_
-
-/* C interface to UART registers. */
-struct uart_dev_s {
- union {
- uart16550_reg_t rxb; /* DLAB=0: receive buffer, read-only */
- uart16550_reg_t txb; /* DLAB=0: transmit buffer, write-only */
- uart16550_reg_t dll; /* DLAB=1: divisor, LS byte latch */
- } w0;
- union {
- uart16550_reg_t ier; /* DLAB=0: interrupt-enable register */
- uart16550_reg_t dlm; /* DLAB=1: divisor, MS byte latch */
- } w1;
-
- union {
- uart16550_reg_t isr; /* DLAB=0: interrupt status register, read-only */
- uart16550_reg_t fcr; /* DLAB=0: FIFO control register, write-only */
- uart16550_reg_t afr; /* DLAB=1: alternate function register */
- } w2;
-
- uart16550_reg_t lcr; /* line control-register, write-only */
- uart16550_reg_t mcr; /* modem control-regsiter, write-only */
- uart16550_reg_t lsr; /* line status register, read-only */
- uart16550_reg_t msr; /* modem status register, read-only */
- uart16550_reg_t scr; /* scratch regsiter, read/write */
-};
-
-
-#define _RXB(u) ((u)->w0.rxb)
-#define _TXB(u) ((u)->w0.txb)
-#define _DLL(u) ((u)->w0.dll)
-#define _IER(u) ((u)->w1.ier)
-#define _DLM(u) ((u)->w1.dlm)
-#define _ISR(u) ((u)->w2.isr)
-#define _FCR(u) ((u)->w2.fcr)
-#define _AFR(u) ((u)->w2.afr)
-#define _LCR(u) ((u)->lcr)
-#define _MCR(u) ((u)->mcr)
-#define _LSR(u) ((u)->lsr)
-#define _MSR(u) ((u)->msr)
-#define _SCR(u) ((u)->scr)
-
-typedef volatile struct uart_dev_s uart_dev_t;
-
-/* IER bits */
-#define RCVR_DATA_REG_INTENABLE 0x01
-#define XMIT_HOLD_REG_INTENABLE 0x02
-#define RCVR_STATUS_INTENABLE 0x04
-#define MODEM_STATUS_INTENABLE 0x08
-
-/* FCR bits */
-#define _FIFO_ENABLE 0x01
-#define RCVR_FIFO_RESET 0x02
-#define XMIT_FIFO_RESET 0x04
-#define DMA_MODE_SELECT 0x08
-#define RCVR_TRIGGER_LSB 0x40
-#define RCVR_TRIGGER_MSB 0x80
-
-/* AFR bits */
-#define AFR_CONC_WRITE 0x01
-#define AFR_BAUDOUT_SEL 0x02
-#define AFR_RXRDY_SEL 0x04
-
-/* ISR bits */
-#define INT_STATUS(r) ((r)&1)
-#define INT_PRIORITY(r) (((r)>>1)&0x7)
-
-/* LCR bits */
-#define WORD_LENGTH(n) (((n)-5)&0x3)
-#define STOP_BIT_ENABLE 0x04
-#define PARITY_ENABLE 0x08
-#define EVEN_PARITY 0x10
-#define FORCE_PARITY 0x20
-#define XMIT_BREAK 0x40
-#define DLAB_ENABLE 0x80
-
-/* MCR bits */
-#define _DTR 0x01
-#define _RTS 0x02
-#define _OP1 0x04
-#define _OP2 0x08
-#define LOOP_BACK 0x10
-
-/* LSR Bits */
-#define RCVR_DATA_READY 0x01
-#define OVERRUN_ERROR 0x02
-#define PARITY_ERROR 0x04
-#define FRAMING_ERROR 0x08
-#define BREAK_INTERRUPT 0x10
-#define XMIT_HOLD_EMPTY 0x20
-#define XMIT_EMPTY 0x40
-#define FIFO_ERROR 0x80
-#define RCVR_READY(u) (_LSR(u)&RCVR_DATA_READY)
-#define XMIT_READY(u) (_LSR(u)&XMIT_HOLD_EMPTY)
-
-/* MSR bits */
-#define _RDR 0x01
-#define DELTA_DSR 0x02
-#define DELTA_RI 0x04
-#define DELTA_CD 0x08
-#define _CTS 0x10
-#define _DSR 0x20
-#define _RI 0x40
-#define _CD 0x80
-
-
-/* Compute 16-bit divisor for baudrate generator, with rounding: */
-#define UART_DIVISOR(clock,baud) (((clock)/16 + (baud)/2)/(baud))
-
-/* Prototypes of driver functions */
-extern void uart16550_init( uart_dev_t *u, unsigned baud, unsigned ndata,
- unsigned parity, unsigned nstop );
-extern void uart16550_out( uart_dev_t *u, char c );
-extern char uart16550_in( uart_dev_t *u );
-extern unsigned uart16550_measure_sys_clk( uart_dev_t *u );
-
-#endif /* _UART_16550_H_ */
diff --git a/src/arch/xtensa/include/xtensa/xdm-regs.h b/src/arch/xtensa/include/xtensa/xdm-regs.h
deleted file mode 100644
index c220bc9..0000000
--- a/src/arch/xtensa/include/xtensa/xdm-regs.h
+++ /dev/null
@@ -1,534 +0,0 @@
-/* xdm-regs.h - Common register and related definitions for the XDM
- (Xtensa Debug Module) */
-
-/* Copyright (c) 2016 Cadence Design Systems Inc.
-
- Permission is hereby granted, free of charge, to any person obtaining
- a copy of this software and associated documentation files (the
- "Software"), to deal in the Software without restriction, including
- without limitation the rights to use, copy, modify, merge, publish,
- distribute, sublicense, and/or sell copies of the Software, and to
- permit persons to whom the Software is furnished to do so, subject to
- the following conditions:
-
- The above copyright notice and this permission notice shall be included
- in all copies or substantial portions of the Software.
-
- THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
- EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
- MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
- IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY
- CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
- TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
- SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. */
-
-
-#ifndef _XDM_REGS_H_
-#define _XDM_REGS_H_
-
-/* NOTE: This header file is included by C, assembler, and other sources.
- So any C-specific or asm-specific content must be appropriately #ifdef'd. */
-
-
-/*
- * XDM registers can be accessed using APB, ERI, or JTAG (via NAR).
- * Address offsets for APB and ERI are the same, and for JTAG
- * is different (due to the limited 7-bit NAR addressing).
- *
- * Here, we first provide the constants as APB / ERI address offsets.
- * This is necessary for assembler code (which accesses XDM via ERI),
- * because complex conversion macros between the two address maps
- * don't work in the assembler.
- * Conversion macros are used to convert these to/from JTAG (NAR),
- * addresses, for software using JTAG.
- */
-/* FIXME: maybe provide only MISC+CS registers here, and leave specific
- subsystem registers in separate headers? eg. for TRAX, PERF, OCD */
-
-/* XDM_.... ERI addr [NAR addr] Description...... */
-
-/* TRAX */
-#define XDM_TRAX_ID 0x100000 /*[0x00] ID */
-#define XDM_TRAX_CONTROL 0x100004 /*[0x01] Control */
-#define XDM_TRAX_STATUS 0x100008 /*[0x02] Status */
-#define XDM_TRAX_DATA 0x10000C /*[0x03] Data */
-#define XDM_TRAX_ADDRESS 0x100010 /*[0x04] Address */
-#define XDM_TRAX_TRIGGER 0x100014 /*[0x05] Stop PC */
-#define XDM_TRAX_MATCH 0x100018 /*[0x06] Stop PC Range */
-#define XDM_TRAX_DELAY 0x10001C /*[0x07] Post Stop Trigger Capture Size */
-#define XDM_TRAX_STARTADDR 0x100020 /*[0x08] Trace Memory Start */
-#define XDM_TRAX_ENDADDR 0x100024 /*[0x09] Trace Memory End */
-#define XDM_TRAX_DEBUGPC 0x10003C /*[0x0F] Debug PC */
-#define XDM_TRAX_P4CHANGE 0x100040 /*[0x10] X */
-#define XDM_TRAX_TIME0 0x100040 /*[0x10] First Time Register */
-#define XDM_TRAX_P4REV 0x100044 /*[0x11] X */
-#define XDM_TRAX_TIME1 0x100044 /*[0x11] Second Time Register */
-#define XDM_TRAX_P4DATE 0x100048 /*[0x12] X */
-#define XDM_TRAX_INTTIME_MAX 0x100048 /*[0x12] maximal Value of Timestamp IntTime */
-#define XDM_TRAX_P4TIME 0x10004C /*[0x13] X */
-#define XDM_TRAX_PDSTATUS 0x100050 /*[0x14] Sample of PDebugStatus */
-#define XDM_TRAX_PDDATA 0x100054 /*[0x15] Sample of PDebugData */
-#define XDM_TRAX_STOP_PC 0x100058 /*[0x16] X */
-#define XDM_TRAX_STOP_ICNT 0x10005C /*[0x16] X */
-#define XDM_TRAX_MSG_STATUS 0x100060 /*[0x17] X */
-#define XDM_TRAX_FSM_STATUS 0x100064 /*[0x18] X */
-#define XDM_TRAX_IB_STATUS 0x100068 /*[0x19] X */
-#define XDM_TRAX_STOPCNT 0x10006C /*[0x1A] X */
-
-/* Performance Monitoring Counters */
-#define XDM_PERF_PMG 0x101000 /*[0x20] perf. mon. global control register */
-#define XDM_PERF_INTPC 0x101010 /*[0x24] perf. mon. interrupt PC */
-#define XDM_PERF_PM0 0x101080 /*[0x28] perf. mon. counter 0 value */
-#define XDM_PERF_PM1 0x101084 /*[0x29] perf. mon. counter 1 value */
-#define XDM_PERF_PM2 0x101088 /*[0x2A] perf. mon. counter 2 value */
-#define XDM_PERF_PM3 0x10108C /*[0x2B] perf. mon. counter 3 value */
-#define XDM_PERF_PM4 0x101090 /*[0x2C] perf. mon. counter 4 value */
-#define XDM_PERF_PM5 0x101094 /*[0x2D] perf. mon. counter 5 value */
-#define XDM_PERF_PM6 0x101098 /*[0x2E] perf. mon. counter 6 value */
-#define XDM_PERF_PM7 0x10109C /*[0x2F] perf. mon. counter 7 value */
-#define XDM_PERF_PM(n) (0x101080+((n)<<2)) /* perfmon cnt n=0..7 value */
-#define XDM_PERF_PMCTRL0 0x101100 /*[0x30] perf. mon. counter 0 control */
-#define XDM_PERF_PMCTRL1 0x101104 /*[0x31] perf. mon. counter 1 control */
-#define XDM_PERF_PMCTRL2 0x101108 /*[0x32] perf. mon. counter 2 control */
-#define XDM_PERF_PMCTRL3 0x10110C /*[0x33] perf. mon. counter 3 control */
-#define XDM_PERF_PMCTRL4 0x101110 /*[0x34] perf. mon. counter 4 control */
-#define XDM_PERF_PMCTRL5 0x101114 /*[0x35] perf. mon. counter 5 control */
-#define XDM_PERF_PMCTRL6 0x101118 /*[0x36] perf. mon. counter 6 control */
-#define XDM_PERF_PMCTRL7 0x10111C /*[0x37] perf. mon. counter 7 control */
-#define XDM_PERF_PMCTRL(n) (0x101100+((n)<<2)) /* perfmon cnt n=0..7 control */
-#define XDM_PERF_PMSTAT0 0x101180 /*[0x38] perf. mon. counter 0 status */
-#define XDM_PERF_PMSTAT1 0x101184 /*[0x39] perf. mon. counter 1 status */
-#define XDM_PERF_PMSTAT2 0x101188 /*[0x3A] perf. mon. counter 2 status */
-#define XDM_PERF_PMSTAT3 0x10118C /*[0x3B] perf. mon. counter 3 status */
-#define XDM_PERF_PMSTAT4 0x101190 /*[0x3C] perf. mon. counter 4 status */
-#define XDM_PERF_PMSTAT5 0x101194 /*[0x3D] perf. mon. counter 5 status */
-#define XDM_PERF_PMSTAT6 0x101198 /*[0x3E] perf. mon. counter 6 status */
-#define XDM_PERF_PMSTAT7 0x10119C /*[0x3F] perf. mon. counter 7 status */
-#define XDM_PERF_PMSTAT(n) (0x101180+((n)<<2)) /* perfmon cnt n=0..7 status */
-
-/* On-Chip-Debug (OCD) */
-#define XDM_OCD_ID 0x102000 /*[0x40] ID register */
-#define XDM_OCD_DCR_CLR 0x102008 /*[0x42] Debug Control reg clear */
-#define XDM_OCD_DCR_SET 0x10200C /*[0x43] Debug Control reg set */
-#define XDM_OCD_DSR 0x102010 /*[0x44] Debug Status reg */
-#define XDM_OCD_DDR 0x102014 /*[0x45] Debug Data reg */
-#define XDM_OCD_DDREXEC 0x102018 /*[0x46] Debug Data reg + execute-DIR */
-#define XDM_OCD_DIR0EXEC 0x10201C /*[0x47] Debug Instruction reg, word 0 + execute-DIR */
-#define XDM_OCD_DIR0 0x102020 /*[0x48] Debug Instruction reg, word 1 */
-#define XDM_OCD_DIR1 0x102024 /*[0x49] Debug Instruction reg, word 2 */
-#define XDM_OCD_DIR2 0x102028 /*[0x4A] Debug Instruction reg, word 3 */
-#define XDM_OCD_DIR3 0x10202C /*[0x49] Debug Instruction reg, word 4 */
-#define XDM_OCD_DIR4 0x102030 /*[0x4C] Debug Instruction reg, word 5 */
-#define XDM_OCD_DIR5 0x102034 /*[0x4D] Debug Instruction reg, word 5 */
-#define XDM_OCD_DIR6 0x102038 /*[0x4E] Debug Instruction reg, word 6 */
-#define XDM_OCD_DIR7 0x10203C /*[0x4F] Debug Instruction reg, word 7 */
-
-/* Miscellaneous Registers */
-#define XDM_MISC_PWRCTL 0x103020 /*[0x58] Power and Reset Control */
-#define XDM_MISC_PWRSTAT 0x103024 /*[0x59] Power and Reset Status */
-#define XDM_MISC_ERISTAT 0x103028 /*[0x5A] ERI Transaction Status */
-#define XDM_MISC_DATETIME 0x103034
-#define XDM_MISC_CONFIGID1_V0 0x103034 /*[0x5D] [INTERNAL] ConfigID1 in XDM v0/1 */
-#define XDM_MISC_CONFIGID1_V2 0x10007c /*[0x1F] [INTERNAL] ConfigID1 since XDM v2 */
-#define XDM_MISC_CONFIGID0_V2 0x100078 /*[0x1E] [INTERNAL] ConfigID0 since XDM v2 */
-#define XDM_MISC_UBID 0x103038 /*[0x5E] [INTERNAL] Build Unique ID */
-#define XDM_MISC_CID 0x10303C /*[0x5F] [INTERNAL] Customer ID */
-
-/* CoreSight compatibility */
-#define XDM_CS_ITCTRL 0x103F00 /*[0x60] InTegration Mode control reg */
-#define XDM_CS_CLAIMSET 0x103FA0 /*[0x68] Claim Tag Set reg */
-#define XDM_CS_CLAIMCLR 0x103FA4 /*[0x69] Claim Tag Clear reg */
-#define XDM_CS_LOCK_ACCESS 0x103FB0 /*[0x6B] Lock Access (writing 0xC5ACCE55 unlocks) */
-#define XDM_CS_LOCK_STATUS 0x103FB4 /*[0x6D] Lock Status */
-#define XDM_CS_AUTH_STATUS 0x103FB8 /*[0x6E] Authentication Status */
-#define XDM_CS_DEV_ID 0x103FC8 /*[0x72] Device ID */
-#define XDM_CS_DEV_TYPE 0x103FCC /*[0x73] Device Type */
-#define XDM_CS_PER_ID4 0x103FD0 /*[0x74] Peripheral ID reg byte 4 */
-#define XDM_CS_PER_ID5 0x103FD4 /*[0x75] Peripheral ID reg byte 5 */
-#define XDM_CS_PER_ID6 0x103FD8 /*[0x76] Peripheral ID reg byte 6 */
-#define XDM_CS_PER_ID7 0x103FDC /*[0x77] Peripheral ID reg byte 7 */
-#define XDM_CS_PER_ID0 0x103FE0 /*[0x78] Peripheral ID reg byte 0 */
-#define XDM_CS_PER_ID1 0x103FE4 /*[0x79] Peripheral ID reg byte 1 */
-#define XDM_CS_PER_ID2 0x103FE8 /*[0x7A] Peripheral ID reg byte 2 */
-#define XDM_CS_PER_ID3 0x103FEC /*[0x7B] Peripheral ID reg byte 3 */
-#define XDM_CS_COMP_ID0 0x103FF0 /*[0x7C] Component ID reg byte 0 */
-#define XDM_CS_COMP_ID1 0x103FF4 /*[0x7D] Component ID reg byte 1 */
-#define XDM_CS_COMP_ID2 0x103FF8 /*[0x7E] Component ID reg byte 2 */
-#define XDM_CS_COMP_ID3 0x103FFC /*[0x7F] Component ID reg byte 3 */
-
-#define CS_PER_ID0 0x00000003
-#define CS_PER_ID1 0x00000021
-#define CS_PER_ID2 0x0000000f
-#define CS_PER_ID3 0x00000000
-#define CS_PER_ID4 0x00000024
-
-#define CS_COMP_ID0 0x0000000d
-#define CS_COMP_ID1 0x00000090
-#define CS_COMP_ID2 0x00000005
-#define CS_COMP_ID3 0x000000b1
-
-#define CS_DEV_TYPE 0x00000015
-
-#define XTENSA_IDCODE 0x120034e5 // FIXME (upper bits not spec. out but BE is !)
-#define XTENSA_MFC_ID (XTENSA_IDCODE & 0xFFF)
-#define CS_DEV_ID XTENSA_IDCODE //FIXME - for XDM v0 only, for v2 is the new ID, that includes vars like PRID but also can be custom
-#define CS_DEV_ID_v0_MASK 0x00000FFF // can compare only the lower 12 bits
-#define CS_DEV_ID_v2_MASK 0xF0000000 // can compare only the upper 4 bits
-
-#define NXS_OCD_REG(val) ((val >= 0x40) && (val <= 0x5F))
-#define NXS_TRAX_REG(val) val <= 0x3F
-
-#define ERI_TRAX_REG(val) ((val & 0xFFFF) < 0x1000)
-#define ERI_OCD_REG(val) ((val & 0xFFFF) >= 0x2000) && ((val & 0xFFFF) < 0x4000))
-
-/* Convert above 14-bit ERI/APB address/offset to 7-bit NAR address: */
-#define _XDM_ERI_TO_NAR(a) ( ((a)&0x3F80)==0x0000 ? (((a)>>2) & 0x1F) \
- : ((a)&0x3E00)==0x1000 ? (0x20 | (((a)>>2) & 7) | (((a)>>4) & 0x18)) \
- : ((a)&0x3FC0)==0x2000 ? (0x40 | (((a)>>2) & 0xF)) \
- : ((a)&0x3FE0)==0x3020 ? (0x50 | (((a)>>2) & 0xF)) \
- : ((a)&0x3FFC)==0x3F00 ? 0x60 \
- : ((a)&0x3F80)==0x3F80 ? (0x60 | (((a)>>2) & 0x1F)) \
- : -1 )
-
-#define XDM_ERI_TO_NAR(a) _XDM_ERI_TO_NAR(a & 0xFFFF)
-
-/* Convert 7-bit NAR address back to ERI/APB address/offset: */
-#define _XDM_NAR_TO_APB(a) ((a) <= 0x1f ? ((a) << 2) \
- :(a) >= 0x20 && (a) <= 0x3F ? (0x1000 | (((a)& 7) << 2) | (((a)&0x18)<<4)) \
- :(a) >= 0x40 && (a) <= 0x4F ? (0x2000 | (((a)&0xF) << 2)) \
- :(a) >= 0x58 && (a) <= 0x5F ? (0x3000 | (((a)&0xF) << 2)) \
- :(a) == 0x60 ? (0x3F00) \
- :(a) >= 0x68 && (a) <= 0x7F ? (0x3F80 | (((a)&0x1F) << 2)) \
- : -1)
-
-#define XDM_NAR_TO_APB(a) _XDM_NAR_TO_APB((a & 0xFFFF))
-#define XDM_NAR_TO_ERI(a) _XDM_NAR_TO_APB((a & 0xFFFF)) | 0x100000
-
-/* Convert APB to ERI address */
-#define XDM_APB_TO_ERI(a) ((a) | (0x100000))
-#define XDM_ERI_TO_APB(a) ((a) & (0x0FFFFF))
-
-/*********** Bit definitions within some of the above registers ***********/
-#define OCD_ID_LSDDRP 0x01000000
-#define OCD_ID_LSDDRP_SHIFT 24
-#define OCD_ID_ENDIANESS 0x00000001
-#define OCD_ID_ENDIANESS_SHIFT 0
-#define OCD_ID_PSO 0x0000000C
-#define OCD_ID_PSO_SHIFT 2
-#define OCD_ID_TRACEPORT 0x00000080
-#define OCD_ID_TRACEPORT_SHIFT 7
-
-#define OCD_ID_LSDDRP_XEA3 0x00000400
-
-/* Power Status register. NOTE: different bit positions in JTAG vs. ERI/APB !! */
-/* ERI/APB: */
-#define PWRSTAT_CORE_DOMAIN_ON 0x00000001 /* set if core is powered on */
-#define PWRSTAT_CORE_DOMAIN_ON_SHIFT 0
-#define PWRSTAT_WAKEUP_RESET 0x00000002 /* [ERI only] 0=cold start, 1=PSO wakeup */
-#define PWRSTAT_WAKEUP_RESET_SHIFT 1
-#define PWRSTAT_CACHES_LOST_POWER 0x00000004 /* [ERI only] set if caches (/localmems?) lost power */
- /* FIXME: does this include local memories? */
-#define PWRSTAT_CACHES_LOST_POWER_SHIFT 2
-#define PWRSTAT_CORE_STILL_NEEDED 0x00000010 /* set if others keeping core awake */
-#define PWRSTAT_CORE_STILL_NEEDED_SHIFT 4
-#define PWRSTAT_MEM_DOMAIN_ON 0x00000100 /* set if memory domain is powered on */
-#define PWRSTAT_MEM_DOMAIN_ON_SHIFT 8
-#define PWRSTAT_DEBUG_DOMAIN_ON 0x00001000 /* set if debug domain is powered on */
-#define PWRSTAT_DEBUG_DOMAIN_ON_SHIFT 12
-#define PWRSTAT_ALL_ON (PWRSTAT_CORE_DOMAIN_ON | PWRSTAT_MEM_DOMAIN_ON | PWRSTAT_DEBUG_DOMAIN_ON)
-#define PWRSTAT_CORE_WAS_RESET 0x00010000 /* [APB only] set if core got reset */
-#define PWRSTAT_CORE_WAS_RESET_SHIFT 16
-#define PWRSTAT_DEBUG_WAS_RESET 0x10000000 /* set if debug module got reset */
-#define PWRSTAT_DEBUG_WAS_RESET_SHIFT 28
-/* JTAG: */
-#define J_PWRSTAT_CORE_DOMAIN_ON 0x01 /* set if core is powered on */
-#define J_PWRSTAT_MEM_DOMAIN_ON 0x02 /* set if memory domain is powered on */
-#define J_PWRSTAT_DEBUG_DOMAIN_ON 0x04 /* set if debug domain is powered on */
-#define J_PWRSTAT_ALL_ON (J_PWRSTAT_CORE_DOMAIN_ON | J_PWRSTAT_MEM_DOMAIN_ON | J_PWRSTAT_DEBUG_DOMAIN_ON)
-#define J_PWRSTAT_CORE_STILL_NEEDED 0x08 /* set if others keeping core awake */
-#define J_PWRSTAT_CORE_WAS_RESET 0x10 /* set if core got reset */
-#define J_PWRSTAT_DEBUG_WAS_RESET 0x40 /* set if debug module got reset */
-
-/* Power Control register. NOTE: different bit positions in JTAG vs. ERI/APB !! */
-/* ERI/APB: */
-#define PWRCTL_CORE_SHUTOFF 0x00000001 /* [ERI only] core wants to shut off on WAITI */
-#define PWRCTL_CORE_SHUTOFF_SHIFT 0
-#define PWRCTL_CORE_WAKEUP 0x00000001 /* [APB only] set to force core to stay powered on */
-#define PWRCTL_CORE_WAKEUP_SHIFT 0
-#define PWRCTL_MEM_WAKEUP 0x00000100 /* set to force memory domain to stay powered on */
-#define PWRCTL_MEM_WAKEUP_SHIFT 8
-#define PWRCTL_DEBUG_WAKEUP 0x00001000 /* set to force debug domain to stay powered on */
-#define PWRCTL_DEBUG_WAKEUP_SHIFT 12
-#define PWRCTL_ALL_ON (PWRCTL_CORE_WAKEUP | PWRCTL_MEM_WAKEUP | PWRCTL_DEBUG_WAKEUP)
-#define PWRCTL_CORE_RESET 0x00010000 /* [APB only] set to assert core reset */
-#define PWRCTL_CORE_RESET_SHIFT 16
-#define PWRCTL_DEBUG_RESET 0x10000000 /* set to assert debug module reset */
-#define PWRCTL_DEBUG_RESET_SHIFT 28
-/* JTAG: */
-#define J_PWRCTL_CORE_WAKEUP 0x01 /* set to force core to stay powered on */
-#define J_PWRCTL_MEM_WAKEUP 0x02 /* set to force memory domain to stay powered on */
-#define J_PWRCTL_DEBUG_WAKEUP 0x04 /* set to force debug domain to stay powered on */
-#define J_DEBUG_USE 0x80 /* */
-#define J_PWRCTL_ALL_ON (J_DEBUG_USE | J_PWRCTL_CORE_WAKEUP | J_PWRCTL_MEM_WAKEUP | J_PWRCTL_DEBUG_WAKEUP)
-#define J_PWRCTL_DEBUG_ON J_DEBUG_USE | J_PWRCTL_DEBUG_WAKEUP
-#define J_PWRCTL_CORE_RESET 0x10 /* set to assert core reset */
-#define J_PWRCTL_DEBUG_RESET 0x40 /* set to assert debug module reset */
-
-#define J_PWRCTL_WRITE_MASK 0xFF
-#define J_PWRSTAT_WRITE_MASK 0xFF
-
-#define PWRCTL_WRITE_MASK ~0
-#define PWRSTAT_WRITE_MASK ~0
-
-/************ The following are only relevant for JTAG, so perhaps belong in OCD only **************/
-
-/* XDM 5-bit JTAG Instruction Register (IR) values: */
-#define XDM_IR_PWRCTL 0x08 /* select 8-bit Power/Reset Control (PRC) */
-#define XDM_IR_PWRSTAT 0x09 /* select 8-bit Power/Reset Status (PRS) */
-#define XDM_IR_NAR_SEL 0x1c /* select altern. 8-bit NAR / 32-bit NDR (Nexus-style) */
-#define XDM_IR_NDR_SEL 0x1d /* select altern. 32-bit NDR / 8-bit NAR
- (FIXME - functionality not yet in HW) */
-#define XDM_IR_IDCODE 0x1e /* select 32-bit JTAG IDCODE */
-#define XDM_IR_BYPASS 0x1f /* select 1-bit bypass */
-
-#define XDM_IR_WIDTH 5 /* width of IR for Xtensa TAP */
-
-/* NAR register bits: */
-#define XDM_NAR_WRITE 0x01
-#define XDM_NAR_ADDR_MASK 0xFE
-#define XDM_NAR_ADDR_SHIFT 1
-
-#define XDM_NAR_BUSY 0x02
-#define XDM_NAR_ERROR 0x01
-
-#define NEXUS_DIR_READ 0x00
-#define NEXUS_DIR_WRITE 0x01
-
-/************ Define DCR register bits **************/
-
-#define DCR_ENABLEOCD 0x0000001
-#define DCR_ENABLEOCD_SHIFT 0
-#define DCR_DEBUG_INT 0x0000002
-#define DCR_DEBUG_INT_SHIFT 1
-#define DCR_DEBUG_OVERRIDE 0x0000004
-#define DCR_DEBUG_OVERRIDE_SHIFT 2
-#define DCR_DEBUG_SS_REQ 0x0000008
-#define DCR_DEBUG_SS_REQ_SHIFT 3
-#define DCR_MASK_NMI 0x0000020
-#define DCR_MASK_NMI_SHIFT 5
-#define DCR_STEP_ENABLE 0x0000040
-#define DCR_STEP_ENABLE_SHIFT 6
-#define DCR_BREAK_IN_EN 0x0010000
-#define DCR_BREAK_IN_EN_SHIFT 16
-#define DCR_BREAK_OUT_EN 0x0020000
-#define DCR_BREAK_OUT_EN_SHIFT 17
-#define DCR_DEBUG_INT_EN 0x0040000
-#define DCR_DEBUG_INT_EN_SHIFT 18
-#define DCR_DBG_SW_ACTIVE 0x0100000
-#define DCR_DBG_SW_ACTIVE_SHIFT 20
-#define DCR_STALL_IN_EN 0x0200000
-#define DCR_STALL_IN_EN_SHIFT 21
-#define DCR_DEBUG_OUT_EN 0x0400000
-#define DCR_DEBUG_OUT_EN_SHIFT 22
-#define DCR_BREAK_OUT_ITO 0x1000000
-#define DCR_STALL_OUT_ITO 0x2000000
-#define DCR_STALL_OUT_ITO_SHIFT 25
-
-/************ Define DSR register bits **************/
-
-#define DOSR_STOP_CAUSE_SHIFT 5
-#define DOSR_STOP_CAUSE_MASK 0xF
-
-#define DOSR_EXECDONE_SHIFT 0
-#define DOSR_EXECDONE_ER 0x01
-#define DOSR_EXECDONE_SHIFT 0
-#define DOSR_EXCEPTION_ER 0x02
-#define DOSR_EXCEPTION_SHIFT 1
-#define DOSR_BUSY 0x04
-#define DOSR_BUSY_SHIFT 2
-#define DOSR_OVERRUN 0x08
-#define DOSR_OVERRUN_SHIFT 3
-#define DOSR_INOCDMODE_ER 0x10
-#define DOSR_INOCDMODE_SHIFT 4
-#define DOSR_CORE_WROTE_DDR_ER 0x400
-#define DOSR_CORE_WROTE_DDR_SHIFT 10
-#define DOSR_CORE_READ_DDR_ER 0x800
-#define DOSR_CORE_READ_DDR_SHIFT 11
-#define DOSR_HOST_WROTE_DDR_ER 0x4000
-#define DOSR_HOST_WROTE_DDR_SHIFT 14
-#define DOSR_HOST_READ_DDR_ER 0x8000
-#define DOSR_HOST_READ_DDR_SHIFT 15
-
-#define DOSR_DEBUG_PEND_BIN 0x10000
-#define DOSR_DEBUG_PEND_HOST 0x20000
-#define DOSR_DEBUG_PEND_TRAX 0x40000
-#define DOSR_DEBUG_BIN 0x100000
-#define DOSR_DEBUG_HOST 0x200000
-#define DOSR_DEBUG_TRAX 0x400000
-#define DOSR_DEBUG_PEND_BIN_SHIFT 16
-#define DOSR_DEBUG_PEND_HOST_SHIFT 17
-#define DOSR_DEBUG_PEND_TRAX_SHIFT 18
-#define DOSR_DEBUG_BREAKIN 0x0100000
-#define DOSR_DEBUG_BREAKIN_SHIFT 20
-#define DOSR_DEBUG_HOST_SHIFT 21
-#define DOSR_DEBUG_TRAX_SHIFT 22
-
-#define DOSR_DEBUG_STALL 0x1000000
-#define DOSR_DEBUG_STALL_SHIFT 24
-
-#define DOSR_CORE_ON 0x40000000
-#define DOSR_CORE_ON_SHIFT 30
-#define DOSR_DEBUG_ON 0x80000000
-#define DOSR_DEBUG_ON_SHIFT 31
-
-/********** Performance monitor registers bits **********/
-
-#define PERF_PMG_ENABLE 0x00000001 /* global enable bit */
-#define PERF_PMG_ENABLE_SHIFT 0
-
-#define PERF_PMCTRL_INT_ENABLE 0x00000001 /* assert interrupt on overflow */
-#define PERF_PMCTRL_INT_ENABLE_SHIFT 0
-#define PERF_PMCTRL_KRNLCNT 0x00000008 /* ignore TRACELEVEL */
-#define PERF_PMCTRL_KRNLCNT_SHIFT 3
-#define PERF_PMCTRL_TRACELEVEL 0x000000F0 /* count when CINTLEVEL <= TRACELEVEL */
-#define PERF_PMCTRL_TRACELEVEL_SHIFT 4
-#define PERF_PMCTRL_SELECT 0x00001F00 /* events group selector */
-#define PERF_PMCTRL_SELECT_SHIFT 8
-#define PERF_PMCTRL_MASK 0xFFFF0000 /* events mask */
-#define PERF_PMCTRL_MASK_SHIFT 16
-
-#define PERF_PMSTAT_OVERFLOW 0x00000001 /* counter overflowed */
-#define PERF_PMSTAT_OVERFLOW_SHIFT 0
-#define PERF_PMSTAT_INT 0x00000010 /* interrupt asserted */
-#define PERF_PMSTAT_INT_SHIFT 4
-
-#if defined (USE_XDM_REGNAME) || defined (USE_DAP_REGNAME)
-/* Describes XDM register: */
-typedef struct {
- int reg;
- char* name;
-} regdef_t;
-
-/*
- * Returns the name of the specified XDM register number,
- * or simply "???" if the register number is not recognized.
- * FIXME - requires -1 as the last entry - change to compare the name to ???
- * or even better, make the code above to work.
- */
-static char*
-regname(regdef_t* list, int reg)
-{
- int i = 0;
- while (list[i].reg != -1) {
- if (list[i].reg == reg)
- break;
- i++;
- }
- return list[i].name;
-}
-
-#if defined (USE_XDM_REGNAME)
-static regdef_t xdm_reglist[] =
-{
- {XDM_OCD_DSR ,"DOSR" },
- {XDM_OCD_DDR ,"DDR" },
- {XDM_OCD_DDREXEC ,"DDREXEC" },
- {XDM_OCD_DIR0EXEC ,"DIR0EXEC"},
- {XDM_OCD_DCR_CLR ,"DCR_CLR" },
- {XDM_OCD_DCR_SET ,"DCR_SET" },
- {XDM_TRAX_CONTROL ,"CONTROL" },
- {XDM_TRAX_STATUS ,"STATUS" },
- {XDM_TRAX_DATA ,"DATA" },
- {XDM_TRAX_ADDRESS ,"ADDRESS" },
-
- {XDM_TRAX_ID ,"TRAX_ID" },
-
- {XDM_TRAX_TRIGGER ,"TRIGGER PC" },
- {XDM_TRAX_MATCH ,"PC MATCH" },
- {XDM_TRAX_DELAY ,"DELAY CNT." },
- {XDM_TRAX_STARTADDR ,"START ADDRESS"},
- {XDM_TRAX_ENDADDR ,"END ADDRESS" },
- {XDM_TRAX_DEBUGPC ,"DEBUG PC" },
- {XDM_TRAX_P4CHANGE ,"P4 CHANGE" },
- {XDM_TRAX_P4REV ,"P4 REV." },
- {XDM_TRAX_P4DATE ,"P4 DATE" },
- {XDM_TRAX_P4TIME ,"P4 TIME" },
- {XDM_TRAX_PDSTATUS ,"PD STATUS" },
- {XDM_TRAX_PDDATA ,"PD DATA" },
- {XDM_TRAX_STOP_PC ,"STOP PC" },
- {XDM_TRAX_STOP_ICNT ,"STOP ICNT" },
- {XDM_TRAX_MSG_STATUS,"MSG STAT." },
- {XDM_TRAX_FSM_STATUS,"FSM STAT." },
- {XDM_TRAX_IB_STATUS ,"IB STAT." },
-
- {XDM_OCD_ID ,"OCD_ID" },
- {XDM_OCD_DIR0 ,"DIR0" },
- {XDM_OCD_DIR1 ,"DIR1" },
- {XDM_OCD_DIR2 ,"DIR2" },
- {XDM_OCD_DIR3 ,"DIR3" },
- {XDM_OCD_DIR4 ,"DIR4" },
- {XDM_OCD_DIR5 ,"DIR5" },
- {XDM_OCD_DIR6 ,"DIR6" },
- {XDM_OCD_DIR7 ,"DIR7" },
-
- {XDM_PERF_PMG ,"PMG" },
- {XDM_PERF_INTPC ,"INTPC" },
- {XDM_PERF_PM0 ,"PM0 " },
- {XDM_PERF_PM1 ,"PM1 " },
- {XDM_PERF_PM2 ,"PM2 " },
- {XDM_PERF_PM3 ,"PM3 " },
- {XDM_PERF_PM4 ,"PM4 " },
- {XDM_PERF_PM5 ,"PM5 " },
- {XDM_PERF_PM6 ,"PM6 " },
- {XDM_PERF_PM7 ,"PM7 " },
- {XDM_PERF_PMCTRL0 ,"PMCTRL0"},
- {XDM_PERF_PMCTRL1 ,"PMCTRL1"},
- {XDM_PERF_PMCTRL2 ,"PMCTRL2"},
- {XDM_PERF_PMCTRL3 ,"PMCTRL3"},
- {XDM_PERF_PMCTRL4 ,"PMCTRL4"},
- {XDM_PERF_PMCTRL5 ,"PMCTRL5"},
- {XDM_PERF_PMCTRL6 ,"PMCTRL6"},
- {XDM_PERF_PMCTRL7 ,"PMCTRL7"},
- {XDM_PERF_PMSTAT0 ,"PMSTAT0"},
- {XDM_PERF_PMSTAT1 ,"PMSTAT1"},
- {XDM_PERF_PMSTAT2 ,"PMSTAT2"},
- {XDM_PERF_PMSTAT3 ,"PMSTAT3"},
- {XDM_PERF_PMSTAT4 ,"PMSTAT4"},
- {XDM_PERF_PMSTAT5 ,"PMSTAT5"},
- {XDM_PERF_PMSTAT6 ,"PMSTAT6"},
- {XDM_PERF_PMSTAT7 ,"PMSTAT7"},
-
- {XDM_MISC_PWRCTL ,"PWRCTL" },
- {XDM_MISC_PWRSTAT ,"PWRSTAT" },
- {XDM_MISC_ERISTAT ,"ERISTAT" },
- {XDM_MISC_DATETIME ,"DATETIME"},
- {XDM_MISC_UBID ,"UBID" },
- {XDM_MISC_CID ,"CID" },
-
- {XDM_CS_ITCTRL ,"ITCTRL" },
- {XDM_CS_CLAIMSET ,"CLAIMSET" },
- {XDM_CS_CLAIMCLR ,"CLAIMCLR" },
- {XDM_CS_LOCK_ACCESS ,"LOCK_ACCESS"},
- {XDM_CS_LOCK_STATUS ,"LOCK_STATUS"},
- {XDM_CS_AUTH_STATUS ,"AUTH_STATUS"},
- {XDM_CS_DEV_ID ,"DEV_ID" },
- {XDM_CS_DEV_TYPE ,"DEV_TYPE" },
- {XDM_CS_PER_ID4 ,"PER_ID4" },
- {XDM_CS_PER_ID5 ,"PER_ID5" },
- {XDM_CS_PER_ID6 ,"PER_ID6" },
- {XDM_CS_PER_ID7 ,"PER_ID7" },
- {XDM_CS_PER_ID0 ,"PER_ID0" },
- {XDM_CS_PER_ID1 ,"PER_ID1" },
- {XDM_CS_PER_ID2 ,"PER_ID2" },
- {XDM_CS_PER_ID3 ,"PER_ID3" },
- {XDM_CS_COMP_ID0 ,"COMP_ID0" },
- {XDM_CS_COMP_ID1 ,"COMP_ID1" },
- {XDM_CS_COMP_ID2 ,"COMP_ID2" },
- {XDM_CS_COMP_ID3 ,"COMP_ID3" },
- {-1 ,"???" },
-};
-#endif
-
-#endif
-
-#endif /* _XDM_REGS_H_ */
diff --git a/src/arch/xtensa/include/xtensa/xmon.h b/src/arch/xtensa/include/xtensa/xmon.h
deleted file mode 100644
index 34c90dc..0000000
--- a/src/arch/xtensa/include/xtensa/xmon.h
+++ /dev/null
@@ -1,156 +0,0 @@
-/* xmon.h - XMON definitions
- *
- * $Id: //depot/rel/Foxhill/dot.8/Xtensa/OS/xmon/xmon.h#1 $
- *
- * Copyright (c) 2001-2013 Tensilica Inc.
- *
- * Permission is hereby granted, free of charge, to any person obtaining
- * a copy of this software and associated documentation files (the
- * "Software"), to deal in the Software without restriction, including
- * without limitation the rights to use, copy, modify, merge, publish,
- * distribute, sublicense, and/or sell copies of the Software, and to
- * permit persons to whom the Software is furnished to do so, subject to
- * the following conditions:
- *
- * The above copyright notice and this permission notice shall be included
- * in all copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
- * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
- * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
- * IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY
- * CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
- * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
- * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
- */
-
-#ifndef __H_XMON
-#define __H_XMON
-
-#ifndef UCHAR
-# define UCHAR unsigned char
-#endif
-
-#ifndef C_UCHAR
-# define C_UCHAR const unsigned char
-#endif
-
-#ifndef UINT32
-# define UINT32 unsigned int
-#endif
-
-/* Default GDB packet size */
-#define GDB_PKT_SIZE 4096
-
-/*XMON signals */
-#define XMON_SIGINT 2 /*target was interrupted */
-#define XMON_SIGILL 4 /*illegal instruction */
-#define XMON_SIGTRAP 5 /*general exception */
-#define XMON_SIGSEGV 11 /*page faults */
-
-
-/* Type of log message from XMON to the application */
-typedef enum {
- XMON_LOG,
- XMON_TRACE,
- XMON_ERR,
-} xmon_log_t;
-
-
-#ifdef _cplusplus
-extern "C" {
-#endif
-
-/*
- * THE FOLLOWING ROUTINES ARE USED BY THE USER
- */
-
-/**
- * Initialize XMON so GDB can attach.
- * gdbBuf - pointer to a buffer XMON uses to comm. with GDB
- * gdbPktSize - Size of the allocated buffer for GDB communication.
- * xlog - log handler for XMON produced errors/logs/traces
-
- */
-extern int
-_xmon_init(char* gdbBuf, int gdbPktSize,
- void(*xlog)(xmon_log_t type, const char* str));
-
-/**
- * Detach from XMON. Can execute at any time
- */
-extern void
-_xmon_close(void);
-
-/**
- * Print message to GDB
- */
-extern void
-_xmon_consoleString(const char* str);
-
-/**
- * XMON version
- */
-extern const char*
-_xmon_version();
-
-/**
- * Enable disable various logging and tracing chains
- * app_log_en - enable/disable logging to the app log handler.
- * ENABLED BY DEFAULT.
- * app_trace_en - enable/disable tracing to the app log handler.
- * DISABLED BY DEFAULT.
- * gdb_log_en - enable/disable log notifications to the GDB.
- * ENABLED BY DEFAULT.
- * gdb_trace_en - enable/disable tracing notifications to the GDB.
- * DISABLED BY DEFAULT.
- */
-extern void
-_xmon_log(char app_log_en, char app_trace_en,
- char gdb_log_en, char gdb_trace_en);
-
-//extern int
-//_xmon_process_packet (int len, char* buf);
-
-//extern int
-//_xmon_process_packet2 (void);
-
-/*
- * THE FOLLOWING ROUTINES NEED TO BE PROVIDED BY USER
- */
-
-/*
- * Receive remote packet bytes from GDB
- * wait: If the function would block waiting for more
- * characters from gdb, wait=0 instructs it to
- * return 0 immediatelly. Otherwise, if wait=1,
- * the function may or may not wait for GDB.
- * NOTE: Current XMON version supports single char
- * input only (return value is 1 always)
- * buf: Pointer to the buffer for the received data.
- * Returns: 0 - no data avaiable,
- >0 - length of received array in buf.
- */
-extern int
-_xmon_in(int wait, UCHAR* buf);
-
-/*
- * Output an array of chars to GDB
- * len - number of chars in the array
- */
-extern void
-_xmon_out(int len, UCHAR*);
-
-/*
- * Flush output characthers
- * XMON invokes this one when a full response is ready
- */
-extern int
-_xmon_flush(void); // flush output characters
-
-#ifdef _cplusplus
-}
-#endif
-
-
-#endif
diff --git a/src/arch/xtensa/include/xtensa/xtbsp.h b/src/arch/xtensa/include/xtensa/xtbsp.h
deleted file mode 100644
index 0781e41..0000000
--- a/src/arch/xtensa/include/xtensa/xtbsp.h
+++ /dev/null
@@ -1,287 +0,0 @@
-/*******************************************************************************
-
- Copyright (c) 2006-2009 Tensilica Inc.
-
- Permission is hereby granted, free of charge, to any person obtaining
- a copy of this software and associated documentation files (the
- "Software"), to deal in the Software without restriction, including
- without limitation the rights to use, copy, modify, merge, publish,
- distribute, sublicense, and/or sell copies of the Software, and to
- permit persons to whom the Software is furnished to do so, subject to
- the following conditions:
-
- The above copyright notice and this permission notice shall be included
- in all copies or substantial portions of the Software.
-
- THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
- EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
- MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
- IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY
- CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
- TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
- SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
-
---------------------------------------------------------------------------------
-
-xtbsp.h Xtensa Board Support Package API
-
-This API defines a minimal set of board-support functions that every supported
-Xtensa board is expected to provide in the board-support-package (BSP) library
-associated with the board-specific LSP. Only basic board functions are provided
-in this board-independent API. API functions not applicable to a board must be
-stubbed in its BSP library. More complex operations must use a board-specific
-interface. Functions are grouped by type of peripheral device.
-
-*******************************************************************************/
-
-#ifndef _XTBSP_H_
-#define _XTBSP_H_
-
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-
-/*******************************************************************************
-BOARD INITIALIZATION.
-The board with all its devices is initialized by xtbsp_board_init().
-Individual devices represented by this API can be reinitialized at any
-time by calling their inidividual device init functions (grouped with
-other device functions). This might be useful to (say) change the baud
-rate of the UART.
-*/
-
-
-/*
-Initialize the board. Must call before any other API function.
-Iniitializes BSP, board in general, and all devices on the board.
-*/
-extern void xtbsp_board_init(void);
-
-
-/*******************************************************************************
-BOARD CHARACTERISTICS and CONVENIENCE FUNCTIONS.
-Board support functions not associated with a particular peripheral device.
-*/
-
-/*
-Return a short string representing the type of board.
-If the board has a display, the string must fit on a single line.
-*/
-extern const char * xtbsp_board_name(void);
-
-/*
-Hardware reset the entire board (if possible). Does not return if successful.
-If this function returns, it is stubbed out or not possible with this board.
-*/
-extern void xtbsp_board_reset(void);
-
-/*
-Return the clock frequency in Hertz. May be constant or computed.
-*/
-extern unsigned xtbsp_clock_freq_hz(void);
-
-/*
-Return the clock period in picoseconds. May be constant or computed.
-*/
-extern unsigned xtbsp_clock_period_ps(void);
-
-/*
-Spin (at least) a number of cycles per the processor's CCOUNT register.
-Unlike a s/w delay loop, the duration is not affected by compiler
-optimization or interrupts completed within the delay period.
-If the processor doesn't have CCOUNT, a s/w delay loop is used to obtain
-a rough approximation of the cycle count.
-*/
-extern void xtbsp_delay_cycles(unsigned cycles);
-
-/*
-Spin at least a number of nanoseconds (approximate and err in the high side).
-BSP implementation should do this efficiently, avoiding integer overflow or
-excessive loss of precision, run-time division or floating point.
-Function implementation (vs. macro) allows BSP to optimize for the clock
-frequency by pre-computing (or using constant) scale factors.
-*/
-extern void xtbsp_delay_ns(unsigned ns);
-
-
-/*******************************************************************************
-C LIBRARY SUPPORT.
-These functions are called by the C library libgloss interface.
-Their names are predetermined apart from this BSP API.
-*/
-
-/*
-Initialize the board. Called by C library initialization code.
-Usually simply calls xtbsp_board_init().
-*/
-extern void board_init(void);
-
-/*
-(Wait for and) Input a single byte from the default character I/O
-device. Return -1 if there is no input device.
-This device is usually a UART and this function calls xtbsp_uart_getchar().
-On some boards (eg.) it might be a directly connected keyboard.
-*/
-extern int inbyte(void);
-
-/*
-Output a single char to the default character I/O device (and wait
-until it's been taken).
-This device is usually a UART and this function calls xtbsp_uart_putchar().
-On some boards (eg.) it might be a directly connected bit-mapped screen.
-*/
-extern void outbyte(int c);
-
-
-/*******************************************************************************
-UART (SERIAL I/O).
-Supports a single UART in a simple polling mode and provides control of
-receiver and transmitter data interrupts (client must provide handler).
-Provides a mapping to processor interrupt number which can be used with
-the HAL to control processor interrupt enable (INTENABLE) etc.
-*/
-
-/* Bitmasks to identify UART interrupts. */
-typedef enum xtbsp_uart_int {
- xtbsp_uart_int_rx = 1<<0,
- xtbsp_uart_int_tx = 1<<1,
- /* mask of all valid interrupt bits */
- xtbsp_uart_int_all = (1<<2)-1
-} xtbsp_uart_int;
-
-/*
-Return non-zero if the board has a UART.
-*/
-extern int xtbsp_uart_exists(void);
-
-/*
-Initialize the UART:
- parity = 0 (none), 1 (odd), or 2 (even).
- nstop = 1 or 2 (stop bits).
- ndata = 7 or 8 (data bits).
-Disables all UART interrupts.
-Returns non-zero if failed (perhaps due to unsupported parameter values).
-Must call before any of the following functions.
-*/
-extern int xtbsp_uart_init(unsigned baud, unsigned ndata,
- unsigned parity, unsigned nstop);
-#define xtbsp_uart_init_default() xtbsp_uart_init(38400, 8, 0, 1)
-
-/*
- Extended init routine for 'portable' UART. Allows specifying the UART
- base address and interrupt number (if interrupt operation desired).
- Meant for use on platforms other than the FPGA boards (e.g. XTSC sim
- or Palladium).
-
- NOTE: Using the 'portable' UART may require that you implement function
- xtbsp_clock_freq_hz() if your target platform does not provide it.
- We recommend you implement it as a weak function so that it can be
- overridden by the target platform implementation if available.
- */
-extern int xtbsp_uart_init_ex(unsigned uart_baseaddr,
- unsigned uart_intnum,
- unsigned baud,
- unsigned ndata,
- unsigned parity,
- unsigned nstop);
-
-/*
-(Wait for and) Input a single char from the UART.
-Any pending xtbsp_uart_int_rx interrupt is cleared.
-*/
-extern char xtbsp_uart_getchar(void);
-
-/*
-(Wait for transmitter ready and) Output a single char to the UART.
-Any pending xtbsp_uart_int_tx interrupt is cleared.
-*/
-extern void xtbsp_uart_putchar(const char c);
-
-/*
-Return true (non-zero) if a character has been received and is ready
-to be input by xtbsp_uart_getchar() without waiting, else return 0.
-*/
-extern int xtbsp_uart_get_isready(void);
-
-/*
-Return non-zero if a character may be output by xtbsp_uart_putchar()
-without waiting, else return 0.
-Any pending xtbsp_uart_int_tx interrupt is cleared.
-*/
-extern int xtbsp_uart_put_isready(void);
-
-/*
-Return the enable status of all UART interrupts represented by this API,
-that is those with bits defined in type xtbsp_uart_int (1 bit = enabled).
-This is the enable status at the device, not the processor's INTENABLE.
-*/
-extern xtbsp_uart_int xtbsp_uart_int_enable_status(void);
-
-/*
-Enable selected UART interrupts at the device.
-*/
-extern void xtbsp_uart_int_enable(const xtbsp_uart_int mask);
-
-/*
-Disable selected UART interrupts at the device.
-*/
-extern void xtbsp_uart_int_disable(const xtbsp_uart_int mask);
-
-/*
-Return the interrupt number (0..31) to which the selected UART interrupt
-is connected. May be used with the link-time HAL to obtain more information,
-eg. Xthal_intlevel_mask[xtbsp_uart_int_number(xtbsp_uart_int_rx)]
-This information can be used to control the processor's INTENABLE, etc.
-Result is -1 if not connected, undefined if mask has more than 1 bit set.
-*/
-extern int xtbsp_uart_int_number(const xtbsp_uart_int mask);
-
-
-/*******************************************************************************
-DISPLAY.
-Supports a single display that can render a series of ASCII characters.
-Functions are provided to perform generic display tasks such as display
-a string, display character by character, or blank the display.
-Chars are 7-bit printable ASCII. Strings are C style NUL \0 terminated.
-These functions busy-wait for any required timing delays so the caller does
-not have to deal with timing. Some displays require long delays which in
-some client applications warrant a board and RTOS specific approach to
-driving the display, however that is beyond the scope of this API.
-*/
-
-/*
-Return non-zero if board has a display.
-*/
-extern int xtbsp_display_exists(void);
-
-/*
-Initialize the display. Must call before any of the following functions.
-*/
-extern void xtbsp_display_init(void);
-
-/*
-Display a single char at position pos (0 is leftmost). Other positions are
-left untouched. Positions beyond the width of the display are ignored.
-*/
-extern void xtbsp_display_char(unsigned pos, const char c);
-
-/*
-Display a string. Blank-pad to or truncate at the end of the display
-(overwrites any previous string so don't need to blank display first).
-*/
-extern void xtbsp_display_string(const char *s);
-
-/*
-Blank (clear) the entire display.
-*/
-extern void xtbsp_display_blank(void);
-
-
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* _XTBSP_H_ */
diff --git a/src/arch/xtensa/include/xtensa/xtensa-libdb-macros.h b/src/arch/xtensa/include/xtensa/xtensa-libdb-macros.h
deleted file mode 100644
index 8f67184..0000000
--- a/src/arch/xtensa/include/xtensa/xtensa-libdb-macros.h
+++ /dev/null
@@ -1,161 +0,0 @@
-/*
- * xtensa-libdb-macros.h
- */
-
-/* $Id: //depot/rel/Foxhill/dot.8/Xtensa/Software/libdb/xtensa-libdb-macros.h#1 $ */
-
-/* Copyright (c) 2004-2008 Tensilica Inc.
-
- Permission is hereby granted, free of charge, to any person obtaining
- a copy of this software and associated documentation files (the
- "Software"), to deal in the Software without restriction, including
- without limitation the rights to use, copy, modify, merge, publish,
- distribute, sublicense, and/or sell copies of the Software, and to
- permit persons to whom the Software is furnished to do so, subject to
- the following conditions:
-
- The above copyright notice and this permission notice shall be included
- in all copies or substantial portions of the Software.
-
- THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
- EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
- MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
- IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY
- CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
- TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
- SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. */
-
-#ifndef __H_LIBDB_MACROS
-#define __H_LIBDB_MACROS
-
-/*
- * This header file provides macros used to construct, identify and use
- * "target numbers" that are assigned to various types of Xtensa processor
- * registers and states. These target numbers are used by GDB in the remote
- * protocol, and are thus used by all GDB debugger agents (targets).
- * They are also used in ELF debugger information sections (stabs, dwarf, etc).
- *
- * These macros are separated from xtensa-libdb.h because they are needed
- * by certain debugger agents that do not use or have access to libdb,
- * e.g. the OCD daemon, RedBoot, XMON, etc.
- *
- * For the time being, for compatibility with certain 3rd party debugger
- * software vendors, target numbers are limited to 16 bits. It is
- * conceivable that this will be extended in the future to 32 bits.
- */
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-#ifndef uint32
- #define uint32 unsigned int
-#endif
-#ifndef int32
- #define int32 int
-#endif
-
-
-/*
- * Macros to form register "target numbers" for various standard registers/states:
- */
-#define XTENSA_DBREGN_INVALID -1 /* not a valid target number */
-#define XTENSA_DBREGN_A(n) (0x0000+(n)) /* address registers a0..a15 */
-#define XTENSA_DBREGN_B(n) (0x0010+(n)) /* boolean bits b0..b15 */
-#define XTENSA_DBREGN_PC 0x0020 /* program counter */
- /* 0x0021 RESERVED for use by Tensilica */
-#define XTENSA_DBREGN_BO(n) (0x0022+(n)) /* boolean octuple-bits bo0..bo1 */
-#define XTENSA_DBREGN_BQ(n) (0x0024+(n)) /* boolean quadruple-bits bq0..bq3 */
-#define XTENSA_DBREGN_BD(n) (0x0028+(n)) /* boolean double-bits bd0..bd7 */
-#define XTENSA_DBREGN_F(n) (0x0030+(n)) /* floating point registers f0..f15 */
-#define XTENSA_DBREGN_VEC(n) (0x0040+(n)) /* Vectra vec regs v0..v15 */
-#define XTENSA_DBREGN_VSEL(n) (0x0050+(n)) /* Vectra sel s0..s3 (V1) ..s7 (V2) */
-#define XTENSA_DBREGN_VALIGN(n) (0x0058+(n)) /* Vectra valign regs u0..u3 */
-#define XTENSA_DBREGN_VCOEFF(n) (0x005C+(n)) /* Vectra I vcoeff regs c0..c1 */
- /* 0x005E..0x005F RESERVED for use by Tensilica */
-#define XTENSA_DBREGN_AEP(n) (0x0060+(n)) /* HiFi2 Audio Engine regs aep0..aep7 */
-#define XTENSA_DBREGN_AEQ(n) (0x0068+(n)) /* HiFi2 Audio Engine regs aeq0..aeq3 */
- /* 0x006C..0x00FF RESERVED for use by Tensilica */
-#define XTENSA_DBREGN_AR(n) (0x0100+(n)) /* physical address regs ar0..ar63
- (note: only with window option) */
- /* 0x0140..0x01FF RESERVED for use by Tensilica */
-#define XTENSA_DBREGN_SREG(n) (0x0200+(n)) /* special registers 0..255 (core) */
-#define XTENSA_DBREGN_BR XTENSA_DBREGN_SREG(0x04) /* all 16 boolean bits, BR */
-#define XTENSA_DBREGN_MR(n) XTENSA_DBREGN_SREG(0x20+(n)) /* MAC16 registers m0..m3 */
-#define XTENSA_DBREGN_UREG(n) (0x0300+(n)) /* user registers 0..255 (TIE) */
- /* 0x0400..0x0FFF RESERVED for use by Tensilica */
- /* 0x1000..0x1FFF user-defined regfiles */
- /* 0x2000..0xEFFF other states (and regfiles) */
-#define XTENSA_DBREGN_DBAGENT(n) (0xF000+(n)) /* non-processor "registers" 0..4095 for
- 3rd-party debugger agent defined use */
- /* > 0xFFFF (32-bit) RESERVED for use by Tensilica */
-/*#define XTENSA_DBREGN_CONTEXT(n) (0x02000000+((n)<<20))*/ /* add this macro's value to a target
- number to identify a specific context 0..31
- for context-replicated registers */
-#define XTENSA_DBREGN_MASK 0xFFFF /* mask of valid target_number bits */
-#define XTENSA_DBREGN_WRITE_SIDE 0x04000000 /* flag to request write half of a register
- split into distinct read and write entries
- with the same target number (currently only
- valid in a couple of libdb API functions;
- see xtensa-libdb.h for details) */
-
-/*
- * Macros to identify specific ranges of target numbers (formed above):
- * NOTE: any context number (or other upper 12 bits) are considered
- * modifiers and are thus stripped out for identification purposes.
- */
-#define XTENSA_DBREGN_IS_VALID(tn) (((tn) & ~0xFFFF) == 0) /* just tests it's 16-bit unsigned */
-#define XTENSA_DBREGN_IS_A(tn) (((tn) & 0xFFF0)==0x0000) /* is a0..a15 */
-#define XTENSA_DBREGN_IS_B(tn) (((tn) & 0xFFF0)==0x0010) /* is b0..b15 */
-#define XTENSA_DBREGN_IS_PC(tn) (((tn) & 0xFFFF)==0x0020) /* is program counter */
-#define XTENSA_DBREGN_IS_BO(tn) (((tn) & 0xFFFE)==0x0022) /* is bo0..bo1 */
-#define XTENSA_DBREGN_IS_BQ(tn) (((tn) & 0xFFFC)==0x0024) /* is bq0..bq3 */
-#define XTENSA_DBREGN_IS_BD(tn) (((tn) & 0xFFF8)==0x0028) /* is bd0..bd7 */
-#define XTENSA_DBREGN_IS_F(tn) (((tn) & 0xFFF0)==0x0030) /* is f0..f15 */
-#define XTENSA_DBREGN_IS_VEC(tn) (((tn) & 0xFFF0)==0x0040) /* is v0..v15 */
-#define XTENSA_DBREGN_IS_VSEL(tn) (((tn) & 0xFFF8)==0x0050) /* is s0..s7 (s0..s3 in V1) */
-#define XTENSA_DBREGN_IS_VALIGN(tn) (((tn) & 0xFFFC)==0x0058) /* is u0..u3 */
-#define XTENSA_DBREGN_IS_VCOEFF(tn) (((tn) & 0xFFFE)==0x005C) /* is c0..c1 */
-#define XTENSA_DBREGN_IS_AEP(tn) (((tn) & 0xFFF8)==0x0060) /* is aep0..aep7 */
-#define XTENSA_DBREGN_IS_AEQ(tn) (((tn) & 0xFFFC)==0x0068) /* is aeq0..aeq3 */
-#define XTENSA_DBREGN_IS_AR(tn) (((tn) & 0xFFC0)==0x0100) /* is ar0..ar63 */
-#define XTENSA_DBREGN_IS_SREG(tn) (((tn) & 0xFF00)==0x0200) /* is special register */
-#define XTENSA_DBREGN_IS_BR(tn) (((tn) & 0xFFFF)==XTENSA_DBREGN_SREG(0x04)) /* is BR */
-#define XTENSA_DBREGN_IS_MR(tn) (((tn) & 0xFFFC)==XTENSA_DBREGN_SREG(0x20)) /* m0..m3 */
-#define XTENSA_DBREGN_IS_UREG(tn) (((tn) & 0xFF00)==0x0300) /* is user register */
-#define XTENSA_DBREGN_IS_DBAGENT(tn) (((tn) & 0xF000)==0xF000) /* is non-processor */
-/*#define XTENSA_DBREGN_IS_CONTEXT(tn) (((tn) & 0x02000000) != 0)*/ /* specifies context # */
-
-/*
- * Macros to extract register index from a register "target number"
- * when a specific range has been identified using one of the _IS_ macros above.
- * These macros only return a useful value if the corresponding _IS_ macro returns true.
- */
-#define XTENSA_DBREGN_A_INDEX(tn) ((tn) & 0x0F) /* 0..15 for a0..a15 */
-#define XTENSA_DBREGN_B_INDEX(tn) ((tn) & 0x0F) /* 0..15 for b0..b15 */
-#define XTENSA_DBREGN_BO_INDEX(tn) ((tn) & 0x01) /* 0..1 for bo0..bo1 */
-#define XTENSA_DBREGN_BQ_INDEX(tn) ((tn) & 0x03) /* 0..3 for bq0..bq3 */
-#define XTENSA_DBREGN_BD_INDEX(tn) ((tn) & 0x07) /* 0..7 for bd0..bd7 */
-#define XTENSA_DBREGN_F_INDEX(tn) ((tn) & 0x0F) /* 0..15 for f0..f15 */
-#define XTENSA_DBREGN_VEC_INDEX(tn) ((tn) & 0x0F) /* 0..15 for v0..v15 */
-#define XTENSA_DBREGN_VSEL_INDEX(tn) ((tn) & 0x07) /* 0..7 for s0..s7 */
-#define XTENSA_DBREGN_VALIGN_INDEX(tn) ((tn) & 0x03) /* 0..3 for u0..u3 */
-#define XTENSA_DBREGN_VCOEFF_INDEX(tn) ((tn) & 0x01) /* 0..1 for c0..c1 */
-#define XTENSA_DBREGN_AEP_INDEX(tn) ((tn) & 0x07) /* 0..7 for aep0..aep7 */
-#define XTENSA_DBREGN_AEQ_INDEX(tn) ((tn) & 0x03) /* 0..3 for aeq0..aeq3 */
-#define XTENSA_DBREGN_AR_INDEX(tn) ((tn) & 0x3F) /* 0..63 for ar0..ar63 */
-#define XTENSA_DBREGN_SREG_INDEX(tn) ((tn) & 0xFF) /* 0..255 for special registers */
-#define XTENSA_DBREGN_MR_INDEX(tn) ((tn) & 0x03) /* 0..3 for m0..m3 */
-#define XTENSA_DBREGN_UREG_INDEX(tn) ((tn) & 0xFF) /* 0..255 for user registers */
-#define XTENSA_DBREGN_DBAGENT_INDEX(tn) ((tn) & 0xFFF) /* 0..4095 for non-processor */
-/*#define XTENSA_DBREGN_CONTEXT_INDEX(tn) (((tn) >> 20) & 0x1F)*/ /* 0..31 context numbers */
-
-
-
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* __H_LIBDB_MACROS */
-
diff --git a/src/arch/xtensa/include/xtensa/xtensa-versions.h b/src/arch/xtensa/include/xtensa/xtensa-versions.h
deleted file mode 100644
index 30f318e..0000000
--- a/src/arch/xtensa/include/xtensa/xtensa-versions.h
+++ /dev/null
@@ -1,398 +0,0 @@
-/*
- xtensa-versions.h -- definitions of Xtensa version and release numbers
-
- This file defines most Xtensa-related product versions and releases
- that exist so far.
- It also provides a bit of information about which ones are current.
- This file changes every release, as versions/releases get added.
-
-
- $Id: //depot/rel/Foxhill/dot.8/Xtensa/Software/misc/xtensa-versions.h.tpp#1 $
-
- Copyright (c) 2006-2010 Tensilica Inc.
-
- Permission is hereby granted, free of charge, to any person obtaining
- a copy of this software and associated documentation files (the
- "Software"), to deal in the Software without restriction, including
- without limitation the rights to use, copy, modify, merge, publish,
- distribute, sublicense, and/or sell copies of the Software, and to
- permit persons to whom the Software is furnished to do so, subject to
- the following conditions:
-
- The above copyright notice and this permission notice shall be included
- in all copies or substantial portions of the Software.
-
- THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
- EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
- MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
- IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY
- CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
- TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
- SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
-*/
-
-#ifndef XTENSA_VERSIONS_H
-#define XTENSA_VERSIONS_H
-
-
-/*
- * NOTE: A "release" is a collection of product versions
- * made available at once (together) to customers.
- * In the past, release and version names all matched in T####.# form,
- * making the distinction irrelevant.
- * Starting with the RA-2004.1 release, this is no longer the case.
- */
-
-
-/* Hardware (Xtensa/Diamond processor) versions: */
-#define XTENSA_HWVERSION_T1020_0 102000 /* versions T1020.0 */
-#define XTENSA_HWCIDSCHEME_T1020_0 10
-#define XTENSA_HWCIDVERS_T1020_0 2
-#define XTENSA_HWVERSION_T1020_1 102001 /* versions T1020.1 */
-#define XTENSA_HWCIDSCHEME_T1020_1 10
-#define XTENSA_HWCIDVERS_T1020_1 3
-#define XTENSA_HWVERSION_T1020_2 102002 /* versions T1020.2 */
-#define XTENSA_HWCIDSCHEME_T1020_2 10
-#define XTENSA_HWCIDVERS_T1020_2 4
-#define XTENSA_HWVERSION_T1020_2B 102002 /* versions T1020.2b */
-#define XTENSA_HWCIDSCHEME_T1020_2B 10
-#define XTENSA_HWCIDVERS_T1020_2B 5
-#define XTENSA_HWVERSION_T1020_3 102003 /* versions T1020.3 */
-#define XTENSA_HWCIDSCHEME_T1020_3 10
-#define XTENSA_HWCIDVERS_T1020_3 6
-#define XTENSA_HWVERSION_T1020_4 102004 /* versions T1020.4 */
-#define XTENSA_HWCIDSCHEME_T1020_4 10
-#define XTENSA_HWCIDVERS_T1020_4 7
-#define XTENSA_HWVERSION_T1030_0 103000 /* versions T1030.0 */
-#define XTENSA_HWCIDSCHEME_T1030_0 10
-#define XTENSA_HWCIDVERS_T1030_0 9
-#define XTENSA_HWVERSION_T1030_1 103001 /* versions T1030.1 */
-#define XTENSA_HWCIDSCHEME_T1030_1 10
-#define XTENSA_HWCIDVERS_T1030_1 10
-#define XTENSA_HWVERSION_T1030_2 103002 /* versions T1030.2 */
-#define XTENSA_HWCIDSCHEME_T1030_2 10
-#define XTENSA_HWCIDVERS_T1030_2 11
-#define XTENSA_HWVERSION_T1030_3 103003 /* versions T1030.3 */
-#define XTENSA_HWCIDSCHEME_T1030_3 10
-#define XTENSA_HWCIDVERS_T1030_3 12
-#define XTENSA_HWVERSION_T1040_0 104000 /* versions T1040.0 */
-#define XTENSA_HWCIDSCHEME_T1040_0 10
-#define XTENSA_HWCIDVERS_T1040_0 15
-#define XTENSA_HWVERSION_T1040_1 104001 /* versions T1040.1 */
-#define XTENSA_HWCIDSCHEME_T1040_1 01
-#define XTENSA_HWCIDVERS_T1040_1 32
-#define XTENSA_HWVERSION_T1040_1P 104001 /* versions T1040.1-prehotfix */
-#define XTENSA_HWCIDSCHEME_T1040_1P 10
-#define XTENSA_HWCIDVERS_T1040_1P 16
-#define XTENSA_HWVERSION_T1040_2 104002 /* versions T1040.2 */
-#define XTENSA_HWCIDSCHEME_T1040_2 01
-#define XTENSA_HWCIDVERS_T1040_2 33
-#define XTENSA_HWVERSION_T1040_3 104003 /* versions T1040.3 */
-#define XTENSA_HWCIDSCHEME_T1040_3 01
-#define XTENSA_HWCIDVERS_T1040_3 34
-#define XTENSA_HWVERSION_T1050_0 105000 /* versions T1050.0 */
-#define XTENSA_HWCIDSCHEME_T1050_0 1100
-#define XTENSA_HWCIDVERS_T1050_0 1
-#define XTENSA_HWVERSION_T1050_1 105001 /* versions T1050.1 */
-#define XTENSA_HWCIDSCHEME_T1050_1 1100
-#define XTENSA_HWCIDVERS_T1050_1 2
-#define XTENSA_HWVERSION_T1050_2 105002 /* versions T1050.2 */
-#define XTENSA_HWCIDSCHEME_T1050_2 1100
-#define XTENSA_HWCIDVERS_T1050_2 4
-#define XTENSA_HWVERSION_T1050_3 105003 /* versions T1050.3 */
-#define XTENSA_HWCIDSCHEME_T1050_3 1100
-#define XTENSA_HWCIDVERS_T1050_3 6
-#define XTENSA_HWVERSION_T1050_4 105004 /* versions T1050.4 */
-#define XTENSA_HWCIDSCHEME_T1050_4 1100
-#define XTENSA_HWCIDVERS_T1050_4 7
-#define XTENSA_HWVERSION_T1050_5 105005 /* versions T1050.5 */
-#define XTENSA_HWCIDSCHEME_T1050_5 1100
-#define XTENSA_HWCIDVERS_T1050_5 8
-#define XTENSA_HWVERSION_RA_2004_1 210000 /* versions LX1.0.0 */
-#define XTENSA_HWCIDSCHEME_RA_2004_1 1100
-#define XTENSA_HWCIDVERS_RA_2004_1 3
-#define XTENSA_HWVERSION_RA_2005_1 210001 /* versions LX1.0.1 */
-#define XTENSA_HWCIDSCHEME_RA_2005_1 1100
-#define XTENSA_HWCIDVERS_RA_2005_1 20
-#define XTENSA_HWVERSION_RA_2005_2 210002 /* versions LX1.0.2 */
-#define XTENSA_HWCIDSCHEME_RA_2005_2 1100
-#define XTENSA_HWCIDVERS_RA_2005_2 21
-#define XTENSA_HWVERSION_RA_2005_3 210003 /* versions LX1.0.3, X6.0.3 */
-#define XTENSA_HWCIDSCHEME_RA_2005_3 1100
-#define XTENSA_HWCIDVERS_RA_2005_3 22
-#define XTENSA_HWVERSION_RA_2006_4 210004 /* versions LX1.0.4, X6.0.4 */
-#define XTENSA_HWCIDSCHEME_RA_2006_4 1100
-#define XTENSA_HWCIDVERS_RA_2006_4 23
-#define XTENSA_HWVERSION_RA_2006_5 210005 /* versions LX1.0.5, X6.0.5 */
-#define XTENSA_HWCIDSCHEME_RA_2006_5 1100
-#define XTENSA_HWCIDVERS_RA_2006_5 24
-#define XTENSA_HWVERSION_RA_2006_6 210006 /* versions LX1.0.6, X6.0.6 */
-#define XTENSA_HWCIDSCHEME_RA_2006_6 1100
-#define XTENSA_HWCIDVERS_RA_2006_6 25
-#define XTENSA_HWVERSION_RA_2007_7 210007 /* versions LX1.0.7, X6.0.7 */
-#define XTENSA_HWCIDSCHEME_RA_2007_7 1100
-#define XTENSA_HWCIDVERS_RA_2007_7 26
-#define XTENSA_HWVERSION_RA_2008_8 210008 /* versions LX1.0.8, X6.0.8 */
-#define XTENSA_HWCIDSCHEME_RA_2008_8 1100
-#define XTENSA_HWCIDVERS_RA_2008_8 27
-#define XTENSA_HWVERSION_RB_2006_0 220000 /* versions LX2.0.0, X7.0.0 */
-#define XTENSA_HWCIDSCHEME_RB_2006_0 1100
-#define XTENSA_HWCIDVERS_RB_2006_0 48
-#define XTENSA_HWVERSION_RB_2007_1 220001 /* versions LX2.0.1, X7.0.1 */
-#define XTENSA_HWCIDSCHEME_RB_2007_1 1100
-#define XTENSA_HWCIDVERS_RB_2007_1 49
-#define XTENSA_HWVERSION_RB_2007_2 221000 /* versions LX2.1.0, X7.1.0 */
-#define XTENSA_HWCIDSCHEME_RB_2007_2 1100
-#define XTENSA_HWCIDVERS_RB_2007_2 52
-#define XTENSA_HWVERSION_RB_2008_3 221001 /* versions LX2.1.1, X7.1.1 */
-#define XTENSA_HWCIDSCHEME_RB_2008_3 1100
-#define XTENSA_HWCIDVERS_RB_2008_3 53
-#define XTENSA_HWVERSION_RB_2008_4 221002 /* versions LX2.1.2, X7.1.2 */
-#define XTENSA_HWCIDSCHEME_RB_2008_4 1100
-#define XTENSA_HWCIDVERS_RB_2008_4 54
-#define XTENSA_HWVERSION_RB_2009_5 221003 /* versions LX2.1.3, X7.1.3 */
-#define XTENSA_HWCIDSCHEME_RB_2009_5 1100
-#define XTENSA_HWCIDVERS_RB_2009_5 55
-#define XTENSA_HWVERSION_RB_2007_2_MP 221100 /* versions LX2.1.8-MP, X7.1.8-MP */
-#define XTENSA_HWCIDSCHEME_RB_2007_2_MP 1100
-#define XTENSA_HWCIDVERS_RB_2007_2_MP 64
-#define XTENSA_HWVERSION_RC_2009_0 230000 /* versions LX3.0.0, X8.0.0, MX1.0.0 */
-#define XTENSA_HWCIDSCHEME_RC_2009_0 1100
-#define XTENSA_HWCIDVERS_RC_2009_0 65
-#define XTENSA_HWVERSION_RC_2010_1 230001 /* versions LX3.0.1, X8.0.1, MX1.0.1 */
-#define XTENSA_HWCIDSCHEME_RC_2010_1 1100
-#define XTENSA_HWCIDVERS_RC_2010_1 66
-#define XTENSA_HWVERSION_RC_2010_2 230002 /* versions LX3.0.2, X8.0.2, MX1.0.2 */
-#define XTENSA_HWCIDSCHEME_RC_2010_2 1100
-#define XTENSA_HWCIDVERS_RC_2010_2 67
-#define XTENSA_HWVERSION_RC_2011_3 230003 /* versions LX3.0.3, X8.0.3, MX1.0.3 */
-#define XTENSA_HWCIDSCHEME_RC_2011_3 1100
-#define XTENSA_HWCIDVERS_RC_2011_3 68
-#define XTENSA_HWVERSION_RD_2010_0 240000 /* versions LX4.0.0, X9.0.0, MX1.1.0, TX1.0.0 */
-#define XTENSA_HWCIDSCHEME_RD_2010_0 1100
-#define XTENSA_HWCIDVERS_RD_2010_0 80
-#define XTENSA_HWVERSION_RD_2011_1 240001 /* versions LX4.0.1, X9.0.1, MX1.1.1, TX1.0.1 */
-#define XTENSA_HWCIDSCHEME_RD_2011_1 1100
-#define XTENSA_HWCIDVERS_RD_2011_1 81
-#define XTENSA_HWVERSION_RD_2011_2 240002 /* versions LX4.0.2, X9.0.2, MX1.1.2, TX1.0.2 */
-#define XTENSA_HWCIDSCHEME_RD_2011_2 1100
-#define XTENSA_HWCIDVERS_RD_2011_2 82
-#define XTENSA_HWVERSION_RD_2011_3 240003 /* versions LX4.0.3, X9.0.3, MX1.1.3, TX1.0.3 */
-#define XTENSA_HWCIDSCHEME_RD_2011_3 1100
-#define XTENSA_HWCIDVERS_RD_2011_3 83
-#define XTENSA_HWVERSION_RD_2012_4 240004 /* versions LX4.0.4, X9.0.4, MX1.1.4, TX1.0.4 */
-#define XTENSA_HWCIDSCHEME_RD_2012_4 1100
-#define XTENSA_HWCIDVERS_RD_2012_4 84
-#define XTENSA_HWVERSION_RD_2012_5 240005 /* versions LX4.0.5, X9.0.5, MX1.1.5, TX1.0.5 */
-#define XTENSA_HWCIDSCHEME_RD_2012_5 1100
-#define XTENSA_HWCIDVERS_RD_2012_5 85
-#define XTENSA_HWVERSION_RE_2012_0 250000 /* versions LX5.0.0, X10.0.0, MX1.2.0 */
-#define XTENSA_HWCIDSCHEME_RE_2012_0 1100
-#define XTENSA_HWCIDVERS_RE_2012_0 96
-#define XTENSA_HWVERSION_RE_2012_1 250001 /* versions LX5.0.1, X10.0.1, MX1.2.1 */
-#define XTENSA_HWCIDSCHEME_RE_2012_1 1100
-#define XTENSA_HWCIDVERS_RE_2012_1 97
-#define XTENSA_HWVERSION_RE_2013_2 250002 /* versions LX5.0.2, X10.0.2, MX1.2.2 */
-#define XTENSA_HWCIDSCHEME_RE_2013_2 1100
-#define XTENSA_HWCIDVERS_RE_2013_2 98
-#define XTENSA_HWVERSION_RE_2013_3 250003 /* versions LX5.0.3, X10.0.3, MX1.2.3 */
-#define XTENSA_HWCIDSCHEME_RE_2013_3 1100
-#define XTENSA_HWCIDVERS_RE_2013_3 99
-#define XTENSA_HWVERSION_RE_2013_4 250004 /* versions LX5.0.4, X10.0.4, MX1.2.4 */
-#define XTENSA_HWCIDSCHEME_RE_2013_4 1100
-#define XTENSA_HWCIDVERS_RE_2013_4 100
-#define XTENSA_HWVERSION_RE_2014_5 250005 /* versions LX5.0.5, X10.0.5, MX1.2.5 */
-#define XTENSA_HWCIDSCHEME_RE_2014_5 1100
-#define XTENSA_HWCIDVERS_RE_2014_5 101
-#define XTENSA_HWVERSION_RE_2015_6 250006 /* versions LX5.0.6, X10.0.6, MX1.2.6 */
-#define XTENSA_HWCIDSCHEME_RE_2015_6 1100
-#define XTENSA_HWCIDVERS_RE_2015_6 102
-#define XTENSA_HWVERSION_RF_2014_0 260000 /* versions LX6.0.0, X11.0.0, MX1.3.0 */
-#define XTENSA_HWCIDSCHEME_RF_2014_0 1100
-#define XTENSA_HWCIDVERS_RF_2014_0 112
-#define XTENSA_HWVERSION_RF_2014_1 260001 /* versions LX6.0.1, X11.0.1 */
-#define XTENSA_HWCIDSCHEME_RF_2014_1 1100
-#define XTENSA_HWCIDVERS_RF_2014_1 113
-#define XTENSA_HWVERSION_RF_2015_2 260002 /* versions LX6.0.2, X11.0.2 */
-#define XTENSA_HWCIDSCHEME_RF_2015_2 1100
-#define XTENSA_HWCIDVERS_RF_2015_2 114
-#define XTENSA_HWVERSION_RF_2015_3 260003 /* versions LX6.0.3, X11.0.3 */
-#define XTENSA_HWCIDSCHEME_RF_2015_3 1100
-#define XTENSA_HWCIDVERS_RF_2015_3 115
-#define XTENSA_HWVERSION_RF_2016_4 260004 /* versions LX6.0.4, X11.0.4 */
-#define XTENSA_HWCIDSCHEME_RF_2016_4 1100
-#define XTENSA_HWCIDVERS_RF_2016_4 116
-#define XTENSA_HWVERSION_RG_2015_0 270000 /* versions LX7.0.0 */
-#define XTENSA_HWCIDSCHEME_RG_2015_0 1100
-#define XTENSA_HWCIDVERS_RG_2015_0 128
-#define XTENSA_HWVERSION_RG_2015_1 270001 /* versions LX7.0.1 */
-#define XTENSA_HWCIDSCHEME_RG_2015_1 1100
-#define XTENSA_HWCIDVERS_RG_2015_1 129
-#define XTENSA_HWVERSION_RG_2015_2 270002 /* versions LX7.0.2 */
-#define XTENSA_HWCIDSCHEME_RG_2015_2 1100
-#define XTENSA_HWCIDVERS_RG_2015_2 130
-#define XTENSA_HWVERSION_RG_2016_3 270003 /* versions LX7.0.3 */
-#define XTENSA_HWCIDSCHEME_RG_2016_3 1100
-#define XTENSA_HWCIDVERS_RG_2016_3 131
-#define XTENSA_HWVERSION_RG_2016_4 270004 /* versions LX7.0.4 */
-#define XTENSA_HWCIDSCHEME_RG_2016_4 1100
-#define XTENSA_HWCIDVERS_RG_2016_4 132
-#define XTENSA_HWVERSION_RG_2017_5 270005 /* versions LX7.0.5 */
-#define XTENSA_HWCIDSCHEME_RG_2017_5 1100
-#define XTENSA_HWCIDVERS_RG_2017_5 133
-#define XTENSA_HWVERSION_RG_2017_6 270006 /* versions LX7.0.6 */
-#define XTENSA_HWCIDSCHEME_RG_2017_6 1100
-#define XTENSA_HWCIDVERS_RG_2017_6 134
-#define XTENSA_HWVERSION_RG_2017_7 270007 /* versions LX7.0.7 */
-#define XTENSA_HWCIDSCHEME_RG_2017_7 1100
-#define XTENSA_HWCIDVERS_RG_2017_7 135
-#define XTENSA_HWVERSION_RG_2017_8 270008 /* versions LX7.0.8 */
-#define XTENSA_HWCIDSCHEME_RG_2017_8 1100
-#define XTENSA_HWCIDVERS_RG_2017_8 136
-#define XTENSA_HWVERSION_RH_2016_0 280000 /* versions LX8.0.0, NX1.0.0, SX1.0.0 */
-#define XTENSA_HWCIDSCHEME_RH_2016_0 1100
-#define XTENSA_HWCIDVERS_RH_2016_0 144
-
-/* Software (Xtensa Tools) versions: */
-#define XTENSA_SWVERSION_T1020_0 102000 /* versions T1020.0 */
-#define XTENSA_SWVERSION_T1020_1 102001 /* versions T1020.1 */
-#define XTENSA_SWVERSION_T1020_2 102002 /* versions T1020.2 */
-#define XTENSA_SWVERSION_T1020_2B 102002 /* versions T1020.2b */
-#define XTENSA_SWVERSION_T1020_3 102003 /* versions T1020.3 */
-#define XTENSA_SWVERSION_T1020_4 102004 /* versions T1020.4 */
-#define XTENSA_SWVERSION_T1030_0 103000 /* versions T1030.0 */
-#define XTENSA_SWVERSION_T1030_1 103001 /* versions T1030.1 */
-#define XTENSA_SWVERSION_T1030_2 103002 /* versions T1030.2 */
-#define XTENSA_SWVERSION_T1030_3 103003 /* versions T1030.3 */
-#define XTENSA_SWVERSION_T1040_0 104000 /* versions T1040.0 */
-#define XTENSA_SWVERSION_T1040_1 104001 /* versions T1040.1 */
-#define XTENSA_SWVERSION_T1040_1P 104001 /* versions T1040.1-prehotfix */
-#define XTENSA_SWVERSION_T1040_2 104002 /* versions T1040.2 */
-#define XTENSA_SWVERSION_T1040_3 104003 /* versions T1040.3 */
-#define XTENSA_SWVERSION_T1050_0 105000 /* versions T1050.0 */
-#define XTENSA_SWVERSION_T1050_1 105001 /* versions T1050.1 */
-#define XTENSA_SWVERSION_T1050_2 105002 /* versions T1050.2 */
-#define XTENSA_SWVERSION_T1050_3 105003 /* versions T1050.3 */
-#define XTENSA_SWVERSION_T1050_4 105004 /* versions T1050.4 */
-#define XTENSA_SWVERSION_T1050_5 105005 /* versions T1050.5 */
-#define XTENSA_SWVERSION_RA_2004_1 600000 /* versions 6.0.0 */
-#define XTENSA_SWVERSION_RA_2005_1 600001 /* versions 6.0.1 */
-#define XTENSA_SWVERSION_RA_2005_2 600002 /* versions 6.0.2 */
-#define XTENSA_SWVERSION_RA_2005_3 600003 /* versions 6.0.3 */
-#define XTENSA_SWVERSION_RA_2006_4 600004 /* versions 6.0.4 */
-#define XTENSA_SWVERSION_RA_2006_5 600005 /* versions 6.0.5 */
-#define XTENSA_SWVERSION_RA_2006_6 600006 /* versions 6.0.6 */
-#define XTENSA_SWVERSION_RA_2007_7 600007 /* versions 6.0.7 */
-#define XTENSA_SWVERSION_RA_2008_8 600008 /* versions 6.0.8 */
-#define XTENSA_SWVERSION_RB_2006_0 700000 /* versions 7.0.0 */
-#define XTENSA_SWVERSION_RB_2007_1 700001 /* versions 7.0.1 */
-#define XTENSA_SWVERSION_RB_2007_2 701000 /* versions 7.1.0 */
-#define XTENSA_SWVERSION_RB_2008_3 701001 /* versions 7.1.1 */
-#define XTENSA_SWVERSION_RB_2008_4 701002 /* versions 7.1.2 */
-#define XTENSA_SWVERSION_RB_2009_5 701003 /* versions 7.1.3 */
-#define XTENSA_SWVERSION_RB_2007_2_MP 701100 /* versions 7.1.8-MP */
-#define XTENSA_SWVERSION_RC_2009_0 800000 /* versions 8.0.0 */
-#define XTENSA_SWVERSION_RC_2010_1 800001 /* versions 8.0.1 */
-#define XTENSA_SWVERSION_RC_2010_2 800002 /* versions 8.0.2 */
-#define XTENSA_SWVERSION_RC_2011_3 800003 /* versions 8.0.3 */
-#define XTENSA_SWVERSION_RD_2010_0 900000 /* versions 9.0.0 */
-#define XTENSA_SWVERSION_RD_2011_1 900001 /* versions 9.0.1 */
-#define XTENSA_SWVERSION_RD_2011_2 900002 /* versions 9.0.2 */
-#define XTENSA_SWVERSION_RD_2011_3 900003 /* versions 9.0.3 */
-#define XTENSA_SWVERSION_RD_2012_4 900004 /* versions 9.0.4 */
-#define XTENSA_SWVERSION_RD_2012_5 900005 /* versions 9.0.5 */
-#define XTENSA_SWVERSION_RE_2012_0 1000000 /* versions 10.0.0 */
-#define XTENSA_SWVERSION_RE_2012_1 1000001 /* versions 10.0.1 */
-#define XTENSA_SWVERSION_RE_2013_2 1000002 /* versions 10.0.2 */
-#define XTENSA_SWVERSION_RE_2013_3 1000003 /* versions 10.0.3 */
-#define XTENSA_SWVERSION_RE_2013_4 1000004 /* versions 10.0.4 */
-#define XTENSA_SWVERSION_RE_2014_5 1000005 /* versions 10.0.5 */
-#define XTENSA_SWVERSION_RE_2015_6 1000006 /* versions 10.0.6 */
-#define XTENSA_SWVERSION_RF_2014_0 1100000 /* versions 11.0.0 */
-#define XTENSA_SWVERSION_RF_2014_1 1100001 /* versions 11.0.1 */
-#define XTENSA_SWVERSION_RF_2015_2 1100002 /* versions 11.0.2 */
-#define XTENSA_SWVERSION_RF_2015_3 1100003 /* versions 11.0.3 */
-#define XTENSA_SWVERSION_RF_2016_4 1100004 /* versions 11.0.4 */
-#define XTENSA_SWVERSION_RG_2015_0 1200000 /* versions 12.0.0 */
-#define XTENSA_SWVERSION_RG_2015_1 1200001 /* versions 12.0.1 */
-#define XTENSA_SWVERSION_RG_2015_2 1200002 /* versions 12.0.2 */
-#define XTENSA_SWVERSION_RG_2016_3 1200003 /* versions 12.0.3 */
-#define XTENSA_SWVERSION_RG_2016_4 1200004 /* versions 12.0.4 */
-#define XTENSA_SWVERSION_RG_2017_5 1200005 /* versions 12.0.5 */
-#define XTENSA_SWVERSION_RG_2017_6 1200006 /* versions 12.0.6 */
-#define XTENSA_SWVERSION_RG_2017_7 1200007 /* versions 12.0.7 */
-#define XTENSA_SWVERSION_RG_2017_8 1200008 /* versions 12.0.8 */
-#define XTENSA_SWVERSION_RH_2016_0 1300000 /* versions 13.0.0 */
-#define XTENSA_SWVERSION_T1040_1_PREHOTFIX XTENSA_SWVERSION_T1040_1P /* T1040.1-prehotfix */
-#define XTENSA_SWVERSION_6_0_0 XTENSA_SWVERSION_RA_2004_1 /* 6.0.0 */
-#define XTENSA_SWVERSION_6_0_1 XTENSA_SWVERSION_RA_2005_1 /* 6.0.1 */
-#define XTENSA_SWVERSION_6_0_2 XTENSA_SWVERSION_RA_2005_2 /* 6.0.2 */
-#define XTENSA_SWVERSION_6_0_3 XTENSA_SWVERSION_RA_2005_3 /* 6.0.3 */
-#define XTENSA_SWVERSION_6_0_4 XTENSA_SWVERSION_RA_2006_4 /* 6.0.4 */
-#define XTENSA_SWVERSION_6_0_5 XTENSA_SWVERSION_RA_2006_5 /* 6.0.5 */
-#define XTENSA_SWVERSION_6_0_6 XTENSA_SWVERSION_RA_2006_6 /* 6.0.6 */
-#define XTENSA_SWVERSION_6_0_7 XTENSA_SWVERSION_RA_2007_7 /* 6.0.7 */
-#define XTENSA_SWVERSION_6_0_8 XTENSA_SWVERSION_RA_2008_8 /* 6.0.8 */
-#define XTENSA_SWVERSION_7_0_0 XTENSA_SWVERSION_RB_2006_0 /* 7.0.0 */
-#define XTENSA_SWVERSION_7_0_1 XTENSA_SWVERSION_RB_2007_1 /* 7.0.1 */
-#define XTENSA_SWVERSION_7_1_0 XTENSA_SWVERSION_RB_2007_2 /* 7.1.0 */
-#define XTENSA_SWVERSION_7_1_1 XTENSA_SWVERSION_RB_2008_3 /* 7.1.1 */
-#define XTENSA_SWVERSION_7_1_2 XTENSA_SWVERSION_RB_2008_4 /* 7.1.2 */
-#define XTENSA_SWVERSION_7_1_3 XTENSA_SWVERSION_RB_2009_5 /* 7.1.3 */
-#define XTENSA_SWVERSION_7_1_8_MP XTENSA_SWVERSION_RB_2007_2_MP /* 7.1.8-MP */
-#define XTENSA_SWVERSION_8_0_0 XTENSA_SWVERSION_RC_2009_0 /* 8.0.0 */
-#define XTENSA_SWVERSION_8_0_1 XTENSA_SWVERSION_RC_2010_1 /* 8.0.1 */
-#define XTENSA_SWVERSION_8_0_2 XTENSA_SWVERSION_RC_2010_2 /* 8.0.2 */
-#define XTENSA_SWVERSION_8_0_3 XTENSA_SWVERSION_RC_2011_3 /* 8.0.3 */
-#define XTENSA_SWVERSION_9_0_0 XTENSA_SWVERSION_RD_2010_0 /* 9.0.0 */
-#define XTENSA_SWVERSION_9_0_1 XTENSA_SWVERSION_RD_2011_1 /* 9.0.1 */
-#define XTENSA_SWVERSION_9_0_2 XTENSA_SWVERSION_RD_2011_2 /* 9.0.2 */
-#define XTENSA_SWVERSION_9_0_3 XTENSA_SWVERSION_RD_2011_3 /* 9.0.3 */
-#define XTENSA_SWVERSION_9_0_4 XTENSA_SWVERSION_RD_2012_4 /* 9.0.4 */
-#define XTENSA_SWVERSION_9_0_5 XTENSA_SWVERSION_RD_2012_5 /* 9.0.5 */
-#define XTENSA_SWVERSION_10_0_0 XTENSA_SWVERSION_RE_2012_0 /* 10.0.0 */
-#define XTENSA_SWVERSION_10_0_1 XTENSA_SWVERSION_RE_2012_1 /* 10.0.1 */
-#define XTENSA_SWVERSION_10_0_2 XTENSA_SWVERSION_RE_2013_2 /* 10.0.2 */
-#define XTENSA_SWVERSION_10_0_3 XTENSA_SWVERSION_RE_2013_3 /* 10.0.3 */
-#define XTENSA_SWVERSION_10_0_4 XTENSA_SWVERSION_RE_2013_4 /* 10.0.4 */
-#define XTENSA_SWVERSION_10_0_5 XTENSA_SWVERSION_RE_2014_5 /* 10.0.5 */
-#define XTENSA_SWVERSION_10_0_6 XTENSA_SWVERSION_RE_2015_6 /* 10.0.6 */
-#define XTENSA_SWVERSION_11_0_0 XTENSA_SWVERSION_RF_2014_0 /* 11.0.0 */
-#define XTENSA_SWVERSION_11_0_1 XTENSA_SWVERSION_RF_2014_1 /* 11.0.1 */
-#define XTENSA_SWVERSION_11_0_2 XTENSA_SWVERSION_RF_2015_2 /* 11.0.2 */
-#define XTENSA_SWVERSION_11_0_3 XTENSA_SWVERSION_RF_2015_3 /* 11.0.3 */
-#define XTENSA_SWVERSION_11_0_4 XTENSA_SWVERSION_RF_2016_4 /* 11.0.4 */
-#define XTENSA_SWVERSION_12_0_0 XTENSA_SWVERSION_RG_2015_0 /* 12.0.0 */
-#define XTENSA_SWVERSION_12_0_1 XTENSA_SWVERSION_RG_2015_1 /* 12.0.1 */
-#define XTENSA_SWVERSION_12_0_2 XTENSA_SWVERSION_RG_2015_2 /* 12.0.2 */
-#define XTENSA_SWVERSION_12_0_3 XTENSA_SWVERSION_RG_2016_3 /* 12.0.3 */
-#define XTENSA_SWVERSION_12_0_4 XTENSA_SWVERSION_RG_2016_4 /* 12.0.4 */
-#define XTENSA_SWVERSION_12_0_5 XTENSA_SWVERSION_RG_2017_5 /* 12.0.5 */
-#define XTENSA_SWVERSION_12_0_6 XTENSA_SWVERSION_RG_2017_6 /* 12.0.6 */
-#define XTENSA_SWVERSION_12_0_7 XTENSA_SWVERSION_RG_2017_7 /* 12.0.7 */
-#define XTENSA_SWVERSION_12_0_8 XTENSA_SWVERSION_RG_2017_8 /* 12.0.8 */
-#define XTENSA_SWVERSION_13_0_0 XTENSA_SWVERSION_RH_2016_0 /* 13.0.0 */
-
-
-/* The current release: */
-#define XTENSA_RELEASE_NAME "RG-2017.8"
-#define XTENSA_RELEASE_CANONICAL_NAME "RG-2017.8"
-
-/* The product versions within the current release: */
-#define XTENSA_SWVERSION XTENSA_SWVERSION_RG_2017_8
-#define XTENSA_SWVERSION_NAME "12.0.8"
-#define XTENSA_SWVERSION_NAME_IDENT 12_0_8
-#define XTENSA_SWVERSION_CANONICAL_NAME "12.0.8"
-#define XTENSA_SWVERSION_MAJORMID_NAME "12.0"
-#define XTENSA_SWVERSION_MAJOR_NAME "12"
-/* For product licensing (not necessarily same as *_MAJORMID_NAME): */
-#define XTENSA_SWVERSION_LICENSE_NAME "12.0"
-
-/* Note: there may be multiple hardware products in one release,
- and software can target older hardware, so the notion of
- "current" hardware versions is partially configuration dependent.
- For now, "current" hardware product version info is left out
- to avoid confusion. */
-
-#endif /*XTENSA_VERSIONS_H*/
-
diff --git a/src/arch/xtensa/include/xtensa/xtensa-xer.h b/src/arch/xtensa/include/xtensa/xtensa-xer.h
deleted file mode 100644
index 900bda3..0000000
--- a/src/arch/xtensa/include/xtensa/xtensa-xer.h
+++ /dev/null
@@ -1,149 +0,0 @@
-/* xer-constants.h -- various constants describing external registers accessed
- via wer and rer.
-
- TODO: find a better prefix. Also conditionalize certain constants based
- on number of cores and interrupts actually present.
-*/
-
-/*
- * Copyright (c) 1999-2008 Tensilica Inc.
- *
- * Permission is hereby granted, free of charge, to any person obtaining
- * a copy of this software and associated documentation files (the
- * "Software"), to deal in the Software without restriction, including
- * without limitation the rights to use, copy, modify, merge, publish,
- * distribute, sublicense, and/or sell copies of the Software, and to
- * permit persons to whom the Software is furnished to do so, subject to
- * the following conditions:
- *
- * The above copyright notice and this permission notice shall be included
- * in all copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
- * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
- * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
- * IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY
- * CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
- * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
- * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
- */
-
-#include <xtensa/config/core.h>
-
-#define NUM_INTERRUPTS 27
-#define NUM_CORES 4
-
-/* Routing of NMI (BInterrupt2) and interrupts 0..n-1 (BInterrupt3+)
- RER reads
- WER writes
- */
-
-#define XER_MIROUT 0x0000
-#define XER_MIROUT_LAST (XER_MIROUT + NUM_INTERRUPTS)
-
-
-/* IPI to core M (all 16 causes).
-
- RER reads
- WER clears
- */
-#define XER_MIPICAUSE 0x0100
-#define XER_MIPICAUSE_FIELD_A_FIRST 0x0
-#define XER_MIPICAUSE_FIELD_A_LAST 0x0
-#define XER_MIPICAUSE_FIELD_B_FIRST 0x1
-#define XER_MIPICAUSE_FIELD_B_LAST 0x3
-#define XER_MIPICAUSE_FIELD_C_FIRST 0x4
-#define XER_MIPICAUSE_FIELD_C_LAST 0x7
-#define XER_MIPICAUSE_FIELD_D_FIRST 0x8
-#define XER_MIPICAUSE_FIELD_D_LAST 0xF
-
-
-/* IPI from cause bit 0..15
-
- RER invalid
- WER sets
-*/
-#define XER_MIPISET 0x0140
-#define XER_MIPISET_LAST 0x014F
-
-
-/* Global enable
-
- RER read
- WER clear
-*/
-#define XER_MIENG 0x0180
-
-
-/* Global enable
-
- RER invalid
- WER set
-*/
-#define XER_MIENG_SET 0x0184
-
-/* Global assert
-
- RER read
- WER clear
-*/
-#define XER_MIASG 0x0188
-
-
-/* Global enable
-
- RER invalid
- WER set
-*/
-#define XER_MIASG_SET 0x018C
-
-
-/* IPI partition register
-
- RER read
- WER write
-*/
-#define XER_PART 0x0190
-#define XER_IPI0 0x0
-#define XER_IPI1 0x1
-#define XER_IPI2 0x2
-#define XER_IPI3 0x3
-
-#define XER_PART_ROUTE_IPI(NUM, FIELD) ((NUM) << ((FIELD) << 2))
-
-#define XER_PART_ROUTE_IPI_CAUSE(TO_A, TO_B, TO_C, TO_D) \
- (XER_PART_ROUTE_IPI(TO_A, XER_IPI0) | \
- XER_PART_ROUTE_IPI(TO_B, XER_IPI1) | \
- XER_PART_ROUTE_IPI(TO_C, XER_IPI2) | \
- XER_PART_ROUTE_IPI(TO_D, XER_IPI3))
-
-#define XER_IPI_WAKE_EXT_INTERRUPT XCHAL_EXTINT0_NUM
-#define XER_IPI_WAKE_CAUSE XER_MIPICAUSE_FIELD_C_FIRST
-#define XER_IPI_WAKE_ADDRESS (XER_MIPISET + XER_IPI_WAKE_CAUSE)
-#define XER_DEFAULT_IPI_ROUTING XER_PART_ROUTE_IPI_CAUSE(XER_IPI1, XER_IPI0, XER_IPI2, XER_IPI3)
-
-
-/* System configuration ID
-
- RER read
- WER invalid
-*/
-#define XER_SYSCFGID 0x01A0
-
-
-/* RunStall to slave processors
-
- RER read
- WER write
-*/
-#define XER_MPSCORE 0x0200
-
-
-/* Cache coherency ON
-
- RER read
- WER write
-*/
-#define XER_CCON 0x0220
-
-
diff --git a/src/arch/xtensa/include/xtensa/xtruntime-core-state.h b/src/arch/xtensa/include/xtensa/xtruntime-core-state.h
deleted file mode 100644
index 94cc719..0000000
--- a/src/arch/xtensa/include/xtensa/xtruntime-core-state.h
+++ /dev/null
@@ -1,240 +0,0 @@
-/* xtruntime-core-state.h - core state save area (used eg. by PSO) */
-/* $Id: //depot/rel/Foxhill/dot.8/Xtensa/OS/include/xtensa/xtruntime-core-state.h#1 $ */
-
-/*
- * Copyright (c) 2012-2013 Tensilica Inc.
- *
- * Permission is hereby granted, free of charge, to any person obtaining
- * a copy of this software and associated documentation files (the
- * "Software"), to deal in the Software without restriction, including
- * without limitation the rights to use, copy, modify, merge, publish,
- * distribute, sublicense, and/or sell copies of the Software, and to
- * permit persons to whom the Software is furnished to do so, subject to
- * the following conditions:
- *
- * The above copyright notice and this permission notice shall be included
- * in all copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
- * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
- * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
- * IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY
- * CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
- * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
- * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
- */
-
-#ifndef _XTOS_CORE_STATE_H_
-#define _XTOS_CORE_STATE_H_
-
-/* Import STRUCT_xxx macros for defining structures: */
-#include <xtensa/xtruntime-frames.h>
-#include <xtensa/config/core.h>
-#include <xtensa/config/tie.h>
-#if XCHAL_HAVE_IDMA
-#include <xtensa/idma.h>
-#endif
-
-//#define XTOS_PSO_TEST 1 // uncommented for internal PSO testing only
-
-#define CORE_STATE_SIGNATURE 0xB1C5AFED // pattern that indicates state was saved
-
-
-/*
- * Save area for saving entire core state, such as across Power Shut-Off (PSO).
- */
-
-STRUCT_BEGIN
-STRUCT_FIELD (long,4,CS_SA_,signature) // for checking whether state was saved
-STRUCT_FIELD (long,4,CS_SA_,restore_label)
-STRUCT_FIELD (long,4,CS_SA_,aftersave_label)
-STRUCT_AFIELD(long,4,CS_SA_,areg,XCHAL_NUM_AREGS)
-#if XCHAL_HAVE_WINDOWED
-STRUCT_AFIELD(long,4,CS_SA_,caller_regs,16) // save a max of 16 caller regs
-STRUCT_FIELD (long,4,CS_SA_,caller_regs_saved) // flag to show if caller regs saved
-#endif
-#if XCHAL_HAVE_PSO_CDM
-STRUCT_FIELD (long,4,CS_SA_,pwrctl)
-#endif
-#if XCHAL_HAVE_WINDOWED
-STRUCT_FIELD (long,4,CS_SA_,windowbase)
-STRUCT_FIELD (long,4,CS_SA_,windowstart)
-#endif
-STRUCT_FIELD (long,4,CS_SA_,sar)
-#if XCHAL_HAVE_EXCEPTIONS
-STRUCT_FIELD (long,4,CS_SA_,epc1)
-STRUCT_FIELD (long,4,CS_SA_,ps)
-STRUCT_FIELD (long,4,CS_SA_,excsave1)
-# ifdef XCHAL_DOUBLEEXC_VECTOR_VADDR
-STRUCT_FIELD (long,4,CS_SA_,depc)
-# endif
-#endif
-#if XCHAL_NUM_INTLEVELS + XCHAL_HAVE_NMI >= 2
-STRUCT_AFIELD(long,4,CS_SA_,epc, XCHAL_NUM_INTLEVELS + XCHAL_HAVE_NMI - 1)
-STRUCT_AFIELD(long,4,CS_SA_,eps, XCHAL_NUM_INTLEVELS + XCHAL_HAVE_NMI - 1)
-STRUCT_AFIELD(long,4,CS_SA_,excsave,XCHAL_NUM_INTLEVELS + XCHAL_HAVE_NMI - 1)
-#endif
-#if XCHAL_HAVE_LOOPS
-STRUCT_FIELD (long,4,CS_SA_,lcount)
-STRUCT_FIELD (long,4,CS_SA_,lbeg)
-STRUCT_FIELD (long,4,CS_SA_,lend)
-#endif
-#if XCHAL_HAVE_ABSOLUTE_LITERALS
-STRUCT_FIELD (long,4,CS_SA_,litbase)
-#endif
-#if XCHAL_HAVE_VECBASE
-STRUCT_FIELD (long,4,CS_SA_,vecbase)
-#endif
-#if XCHAL_HAVE_S32C1I && (XCHAL_HW_MIN_VERSION >= XTENSA_HWVERSION_RC_2009_0) /* have ATOMCTL ? */
-STRUCT_FIELD (long,4,CS_SA_,atomctl)
-#endif
-#if XCHAL_HAVE_PREFETCH
-STRUCT_FIELD (long,4,CS_SA_,prefctl)
-#endif
-#if XCHAL_USE_MEMCTL
-STRUCT_FIELD (long,4,CS_SA_,memctl)
-#endif
-#if XCHAL_HAVE_CCOUNT
-STRUCT_FIELD (long,4,CS_SA_,ccount)
-STRUCT_AFIELD(long,4,CS_SA_,ccompare, XCHAL_NUM_TIMERS)
-#endif
-#if XCHAL_HAVE_INTERRUPTS
-STRUCT_FIELD (long,4,CS_SA_,intenable)
-STRUCT_FIELD (long,4,CS_SA_,interrupt)
-#endif
-#if XCHAL_HAVE_DEBUG
-STRUCT_FIELD (long,4,CS_SA_,icount)
-STRUCT_FIELD (long,4,CS_SA_,icountlevel)
-STRUCT_FIELD (long,4,CS_SA_,debugcause)
-// DDR not saved
-# if XCHAL_NUM_DBREAK
-STRUCT_AFIELD(long,4,CS_SA_,dbreakc, XCHAL_NUM_DBREAK)
-STRUCT_AFIELD(long,4,CS_SA_,dbreaka, XCHAL_NUM_DBREAK)
-# endif
-# if XCHAL_NUM_IBREAK
-STRUCT_AFIELD(long,4,CS_SA_,ibreaka, XCHAL_NUM_IBREAK)
-STRUCT_FIELD (long,4,CS_SA_,ibreakenable)
-# endif
-#endif
-#if XCHAL_NUM_MISC_REGS
-STRUCT_AFIELD(long,4,CS_SA_,misc,XCHAL_NUM_MISC_REGS)
-#endif
-#if XCHAL_HAVE_MEM_ECC_PARITY
-STRUCT_FIELD (long,4,CS_SA_,mepc)
-STRUCT_FIELD (long,4,CS_SA_,meps)
-STRUCT_FIELD (long,4,CS_SA_,mesave)
-STRUCT_FIELD (long,4,CS_SA_,mesr)
-STRUCT_FIELD (long,4,CS_SA_,mecr)
-STRUCT_FIELD (long,4,CS_SA_,mevaddr)
-#endif
-
-/* We put this ahead of TLB and other TIE state,
- to keep it within S32I/L32I offset range. */
-#if XCHAL_HAVE_CP
-STRUCT_FIELD (long,4,CS_SA_,cpenable)
-#endif
-
-/* TLB state */
-#if XCHAL_HAVE_MIMIC_CACHEATTR || XCHAL_HAVE_XLT_CACHEATTR
-STRUCT_AFIELD(long,4,CS_SA_,tlbs,8*2)
-#endif
-#if XCHAL_HAVE_PTP_MMU
-/* Compute number of auto-refill (ARF) entries as max of I and D,
- to simplify TLB save logic. On the unusual configs with
- ITLB ARF != DTLB ARF entries, we'll just end up
- saving/restoring some extra entries redundantly. */
-# if XCHAL_DTLB_ARF_ENTRIES_LOG2 + XCHAL_ITLB_ARF_ENTRIES_LOG2 > 4
-# define ARF_ENTRIES 8
-# else
-# define ARF_ENTRIES 4
-# endif
-STRUCT_FIELD (long,4,CS_SA_,ptevaddr)
-STRUCT_FIELD (long,4,CS_SA_,rasid)
-STRUCT_FIELD (long,4,CS_SA_,dtlbcfg)
-STRUCT_FIELD (long,4,CS_SA_,itlbcfg)
-/*** WARNING: past this point, field offsets may be larger than S32I/L32I range ***/
-STRUCT_AFIELD(long,4,CS_SA_,tlbs,((4*ARF_ENTRIES+4)*2+3)*2)
-# if XCHAL_HAVE_SPANNING_WAY /* MMU v3 */
-STRUCT_AFIELD(long,4,CS_SA_,tlbs_ways56,(4+8)*2*2)
-# endif
-#endif
-/* MPU state */
-#if XCHAL_HAVE_MPU
-STRUCT_AFIELD(long,4,CS_SA_,mpuentry,8*XCHAL_MPU_ENTRIES)
-STRUCT_FIELD (long,4,CS_SA_,cacheadrdis)
-#endif
-
-#if XCHAL_HAVE_IDMA
-STRUCT_AFIELD(long,4,CS_SA_,idmaregs, IDMA_PSO_SAVE_SIZE)
-#endif
-
-/* TIE state */
-/* NOTE: NCP area is aligned to XCHAL_TOTAL_SA_ALIGN not XCHAL_NCP_SA_ALIGN,
- because the offsets of all subsequent coprocessor save areas are relative
- to the NCP save area. */
-STRUCT_AFIELD_A(char,1,XCHAL_TOTAL_SA_ALIGN,CS_SA_,ncp,XCHAL_NCP_SA_SIZE)
-#if XCHAL_HAVE_CP
-#if XCHAL_CP0_SA_SIZE > 0
-STRUCT_AFIELD_A(char,1,XCHAL_CP0_SA_ALIGN,CS_SA_,cp0,XCHAL_CP0_SA_SIZE)
-#endif
-#if XCHAL_CP1_SA_SIZE > 0
-STRUCT_AFIELD_A(char,1,XCHAL_CP1_SA_ALIGN,CS_SA_,cp1,XCHAL_CP1_SA_SIZE)
-#endif
-#if XCHAL_CP2_SA_SIZE > 0
-STRUCT_AFIELD_A(char,1,XCHAL_CP2_SA_ALIGN,CS_SA_,cp2,XCHAL_CP2_SA_SIZE)
-#endif
-#if XCHAL_CP3_SA_SIZE > 0
-STRUCT_AFIELD_A(char,1,XCHAL_CP3_SA_ALIGN,CS_SA_,cp3,XCHAL_CP3_SA_SIZE)
-#endif
-#if XCHAL_CP4_SA_SIZE > 0
-STRUCT_AFIELD_A(char,1,XCHAL_CP4_SA_ALIGN,CS_SA_,cp4,XCHAL_CP4_SA_SIZE)
-#endif
-#if XCHAL_CP5_SA_SIZE > 0
-STRUCT_AFIELD_A(char,1,XCHAL_CP5_SA_ALIGN,CS_SA_,cp5,XCHAL_CP5_SA_SIZE)
-#endif
-#if XCHAL_CP6_SA_SIZE > 0
-STRUCT_AFIELD_A(char,1,XCHAL_CP6_SA_ALIGN,CS_SA_,cp6,XCHAL_CP6_SA_SIZE)
-#endif
-#if XCHAL_CP7_SA_SIZE > 0
-STRUCT_AFIELD_A(char,1,XCHAL_CP7_SA_ALIGN,CS_SA_,cp7,XCHAL_CP7_SA_SIZE)
-#endif
-//STRUCT_AFIELD_A(char,1,XCHAL_CP8_SA_ALIGN,CS_SA_,cp8,XCHAL_CP8_SA_SIZE)
-//STRUCT_AFIELD_A(char,1,XCHAL_CP9_SA_ALIGN,CS_SA_,cp9,XCHAL_CP9_SA_SIZE)
-//STRUCT_AFIELD_A(char,1,XCHAL_CP10_SA_ALIGN,CS_SA_,cp10,XCHAL_CP10_SA_SIZE)
-//STRUCT_AFIELD_A(char,1,XCHAL_CP11_SA_ALIGN,CS_SA_,cp11,XCHAL_CP11_SA_SIZE)
-//STRUCT_AFIELD_A(char,1,XCHAL_CP12_SA_ALIGN,CS_SA_,cp12,XCHAL_CP12_SA_SIZE)
-//STRUCT_AFIELD_A(char,1,XCHAL_CP13_SA_ALIGN,CS_SA_,cp13,XCHAL_CP13_SA_SIZE)
-//STRUCT_AFIELD_A(char,1,XCHAL_CP14_SA_ALIGN,CS_SA_,cp14,XCHAL_CP14_SA_SIZE)
-//STRUCT_AFIELD_A(char,1,XCHAL_CP15_SA_ALIGN,CS_SA_,cp15,XCHAL_CP15_SA_SIZE)
-#endif
-
-STRUCT_END(XtosCoreState)
-
-
-
-// These are part of non-coprocessor state (ncp):
-#if XCHAL_HAVE_MAC16
-//STRUCT_FIELD (long,4,CS_SA_,acclo)
-//STRUCT_FIELD (long,4,CS_SA_,acchi)
-//STRUCT_AFIELD(long,4,CS_SA_,mr, 4)
-#endif
-#if XCHAL_HAVE_THREADPTR
-//STRUCT_FIELD (long,4,CS_SA_,threadptr)
-#endif
-#if XCHAL_HAVE_S32C1I
-//STRUCT_FIELD (long,4,CS_SA_,scompare1)
-#endif
-#if XCHAL_HAVE_BOOLEANS
-//STRUCT_FIELD (long,4,CS_SA_,br)
-#endif
-
-// Not saved:
-// EXCCAUSE ??
-// DEBUGCAUSE ??
-// EXCVADDR ??
-// DDR
-// INTERRUPT
-// ... locked cache lines ...
-
-#endif /* _XTOS_CORE_STATE_H_ */
-
diff --git a/src/arch/xtensa/include/xtensa/xtruntime-frames.h b/src/arch/xtensa/include/xtensa/xtruntime-frames.h
deleted file mode 100644
index ede375a..0000000
--- a/src/arch/xtensa/include/xtensa/xtruntime-frames.h
+++ /dev/null
@@ -1,181 +0,0 @@
-/* xtruntime-frames.h - exception stack frames for single-threaded run-time */
-/* $Id: //depot/rel/Foxhill/dot.8/Xtensa/OS/include/xtensa/xtruntime-frames.h#1 $ */
-
-/*
- * Copyright (c) 2002-2012 Tensilica Inc.
- *
- * Permission is hereby granted, free of charge, to any person obtaining
- * a copy of this software and associated documentation files (the
- * "Software"), to deal in the Software without restriction, including
- * without limitation the rights to use, copy, modify, merge, publish,
- * distribute, sublicense, and/or sell copies of the Software, and to
- * permit persons to whom the Software is furnished to do so, subject to
- * the following conditions:
- *
- * The above copyright notice and this permission notice shall be included
- * in all copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
- * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
- * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
- * IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY
- * CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
- * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
- * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
- */
-
-#ifndef _XTRUNTIME_FRAMES_H_
-#define _XTRUNTIME_FRAMES_H_
-
-#include <xtensa/config/core.h>
-
-/* Macros that help define structures for both C and assembler: */
-#if defined(_ASMLANGUAGE) || defined(__ASSEMBLER__)
-#define STRUCT_BEGIN .pushsection .text; .struct 0
-#define STRUCT_FIELD(ctype,size,pre,name) pre##name: .space size
-#define STRUCT_AFIELD(ctype,size,pre,name,n) pre##name: .if n ; .space (size)*(n) ; .endif
-#define STRUCT_AFIELD_A(ctype,size,align,pre,name,n) .balign align ; pre##name: .if n ; .space (size)*(n) ; .endif
-#define STRUCT_END(sname) sname##Size:; .popsection
-#else /*_ASMLANGUAGE||__ASSEMBLER__*/
-#define STRUCT_BEGIN typedef struct {
-#define STRUCT_FIELD(ctype,size,pre,name) ctype name;
-#define STRUCT_AFIELD(ctype,size,pre,name,n) ctype name[n];
-#define STRUCT_AFIELD_A(ctype,size,align,pre,name,n) ctype name[n] __attribute__((aligned(align)));
-#define STRUCT_END(sname) } sname;
-#endif /*_ASMLANGUAGE||__ASSEMBLER__*/
-
-
-/*
- * Kernel vector mode exception stack frame.
- *
- * NOTE: due to the limited range of addi used in the current
- * kernel exception vector, and the fact that historically
- * the vector is limited to 12 bytes, the size of this
- * stack frame is limited to 128 bytes (currently at 64).
- */
-STRUCT_BEGIN
-STRUCT_FIELD (long,4,KEXC_,pc) /* "parm" */
-STRUCT_FIELD (long,4,KEXC_,ps)
-STRUCT_AFIELD(long,4,KEXC_,areg, 4) /* a12 .. a15 */
-STRUCT_FIELD (long,4,KEXC_,sar) /* "save" */
-#if XCHAL_HAVE_LOOPS
-STRUCT_FIELD (long,4,KEXC_,lcount)
-STRUCT_FIELD (long,4,KEXC_,lbeg)
-STRUCT_FIELD (long,4,KEXC_,lend)
-#endif
-#if XCHAL_HAVE_MAC16
-STRUCT_FIELD (long,4,KEXC_,acclo)
-STRUCT_FIELD (long,4,KEXC_,acchi)
-STRUCT_AFIELD(long,4,KEXC_,mr, 4)
-#endif
-STRUCT_END(KernelFrame)
-
-
-/*
- * User vector mode exception stack frame:
- *
- * WARNING: if you modify this structure, you MUST modify the
- * computation of the pad size (ALIGNPAD) accordingly.
- */
-STRUCT_BEGIN
-STRUCT_FIELD (long,4,UEXC_,pc)
-STRUCT_FIELD (long,4,UEXC_,ps)
-STRUCT_FIELD (long,4,UEXC_,sar)
-STRUCT_FIELD (long,4,UEXC_,vpri)
-#ifdef __XTENSA_CALL0_ABI__
-STRUCT_FIELD (long,4,UEXC_,a0)
-#endif
-STRUCT_FIELD (long,4,UEXC_,a2)
-STRUCT_FIELD (long,4,UEXC_,a3)
-STRUCT_FIELD (long,4,UEXC_,a4)
-STRUCT_FIELD (long,4,UEXC_,a5)
-#ifdef __XTENSA_CALL0_ABI__
-STRUCT_FIELD (long,4,UEXC_,a6)
-STRUCT_FIELD (long,4,UEXC_,a7)
-STRUCT_FIELD (long,4,UEXC_,a8)
-STRUCT_FIELD (long,4,UEXC_,a9)
-STRUCT_FIELD (long,4,UEXC_,a10)
-STRUCT_FIELD (long,4,UEXC_,a11)
-STRUCT_FIELD (long,4,UEXC_,a12)
-STRUCT_FIELD (long,4,UEXC_,a13)
-STRUCT_FIELD (long,4,UEXC_,a14)
-STRUCT_FIELD (long,4,UEXC_,a15)
-#endif
-STRUCT_FIELD (long,4,UEXC_,exccause) /* NOTE: can probably rid of this one (pass direct) */
-#if XCHAL_HAVE_LOOPS
-STRUCT_FIELD (long,4,UEXC_,lcount)
-STRUCT_FIELD (long,4,UEXC_,lbeg)
-STRUCT_FIELD (long,4,UEXC_,lend)
-#endif
-#if XCHAL_HAVE_MAC16
-STRUCT_FIELD (long,4,UEXC_,acclo)
-STRUCT_FIELD (long,4,UEXC_,acchi)
-STRUCT_AFIELD(long,4,UEXC_,mr, 4)
-#endif
-/* ALIGNPAD is the 16-byte alignment padding. */
-#ifdef __XTENSA_CALL0_ABI__
-# define CALL0_ABI 1
-#else
-# define CALL0_ABI 0
-#endif
-#define ALIGNPAD ((3 + XCHAL_HAVE_LOOPS*1 + XCHAL_HAVE_MAC16*2 + CALL0_ABI*1) & 3)
-#if ALIGNPAD
-STRUCT_AFIELD(long,4,UEXC_,pad, ALIGNPAD) /* 16-byte alignment padding */
-#endif
-/*STRUCT_AFIELD_A(char,1,XCHAL_CPEXTRA_SA_ALIGN,UEXC_,ureg, (XCHAL_CPEXTRA_SA_SIZE+3)&-4)*/ /* not used */
-STRUCT_END(UserFrame)
-
-/*
- * xtos_structures_pointers contains ptrs to all structures created for
- * each processor individually.
- *
- * To access the core specific structure from ASM (after threadptr is set):
- * xtos_addr_percore a13, _xtos_interrupt_table
- *
- * Access to the core specific structure from C is not supported!
- */
-STRUCT_BEGIN
-STRUCT_FIELD(void*,4,XTOS_PTR_TO_,xtos_enabled)
-STRUCT_FIELD(void*,4,XTOS_PTR_TO_,xtos_intstruct)
-STRUCT_FIELD(void*,4,XTOS_PTR_TO_,xtos_interrupt_table)
-STRUCT_FIELD(void*,4,XTOS_PTR_TO_,xtos_interrupt_mask_table)
-STRUCT_FIELD(void*,4,XTOS_PTR_TO_,xtos_stack_for_interrupt_2)
-STRUCT_FIELD(void*,4,XTOS_PTR_TO_,xtos_stack_for_interrupt_3)
-STRUCT_FIELD(void*,4,XTOS_PTR_TO_,xtos_stack_for_interrupt_4)
-STRUCT_FIELD(void*,4,XTOS_PTR_TO_,xtos_stack_for_interrupt_5)
-STRUCT_END(xtos_structures_pointers)
-
-#if defined(_ASMLANGUAGE) || defined(__ASSEMBLER__)
-
-
-/* Check for UserFrameSize small enough not to require rounding...: */
- /* Skip 16-byte save area, then 32-byte space for 8 regs of call12
- * (which overlaps with 16-byte GCC nested func chaining area),
- * then exception stack frame: */
- .set UserFrameTotalSize, 16+32+UserFrameSize
- /* Greater than 112 bytes? (max range of ADDI, both signs, when aligned to 16 bytes): */
- .ifgt UserFrameTotalSize-112
- /* Round up to 256-byte multiple to accelerate immediate adds: */
- .set UserFrameTotalSize, ((UserFrameTotalSize+255) & 0xFFFFFF00)
- .endif
-# define ESF_TOTALSIZE UserFrameTotalSize
-
-#endif /* _ASMLANGUAGE || __ASSEMBLER__ */
-
-
-#if XCHAL_NUM_CONTEXTS > 1
-/* Structure of info stored on new context's stack for setup: */
-STRUCT_BEGIN
-STRUCT_FIELD (long,4,INFO_,sp)
-STRUCT_FIELD (long,4,INFO_,arg1)
-STRUCT_FIELD (long,4,INFO_,funcpc)
-STRUCT_FIELD (long,4,INFO_,prevps)
-STRUCT_END(SetupInfo)
-#endif
-
-
-#define KERNELSTACKSIZE 1024
-
-
-#endif /* _XTRUNTIME_FRAMES_H_ */
-
diff --git a/src/arch/xtensa/include/xtensa/xtruntime.h b/src/arch/xtensa/include/xtensa/xtruntime.h
deleted file mode 100644
index d5d1f1d..0000000
--- a/src/arch/xtensa/include/xtensa/xtruntime.h
+++ /dev/null
@@ -1,237 +0,0 @@
-/*
- * xtruntime.h -- general C definitions for single-threaded run-time
- *
- * Copyright (c) 2002-2013 Tensilica Inc.
- *
- * Permission is hereby granted, free of charge, to any person obtaining
- * a copy of this software and associated documentation files (the
- * "Software"), to deal in the Software without restriction, including
- * without limitation the rights to use, copy, modify, merge, publish,
- * distribute, sublicense, and/or sell copies of the Software, and to
- * permit persons to whom the Software is furnished to do so, subject to
- * the following conditions:
- *
- * The above copyright notice and this permission notice shall be included
- * in all copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
- * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
- * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
- * IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY
- * CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
- * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
- * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
- */
-
-#ifndef XTRUNTIME_H
-#define XTRUNTIME_H
-
-#include <xtensa/config/core.h>
-#include <xtensa/config/specreg.h>
-#include <xtensa/xtruntime-core-state.h>
-
-#ifndef XTSTR
-#define _XTSTR(x) # x
-#define XTSTR(x) _XTSTR(x)
-#endif
-
-/* _xtos_core_shutoff() flags parameter values: */
-#define XTOS_KEEPON_MEM 0x00000100 /* ==PWRCTL_MEM_WAKEUP */
-#define XTOS_KEEPON_MEM_SHIFT 8
-#define XTOS_KEEPON_DEBUG 0x00001000 /* ==PWRCTL_DEBUG_WAKEUP */
-#define XTOS_KEEPON_DEBUG_SHIFT 12
-
-#define XTOS_IDMA_NO_WAIT 0x00010000 /* Do not wait for idma to finish. Disable if necessary */
-#define XTOS_IDMA_WAIT_STANDBY 0x00020000 /* Also treat standby state as the end of wait */
-
-#define XTOS_COREF_PSO 0x00000001 /* do power shutoff */
-#define XTOS_COREF_PSO_SHIFT 0
-
-#define _xtos_set_execption_handler _xtos_set_exception_handler /* backward compatibility */
-#define _xtos_set_saved_intenable _xtos_ints_on /* backward compatibility */
-#define _xtos_clear_saved_intenable _xtos_ints_off /* backward compatibility */
-
-#if !defined(_ASMLANGUAGE) && !defined(__ASSEMBLER__)
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-#if defined(XTOS_MISRA)
-typedef void (_xtos_handler_func)(void *);
-#elif defined(__cplusplus)
-typedef void (_xtos_handler_func)(...);
-#else
-typedef void (_xtos_handler_func)();
-#endif
-typedef _xtos_handler_func *_xtos_handler;
-
-/*
- * unsigned XTOS_SET_INTLEVEL(int intlevel);
- * This macro sets the current interrupt level.
- * The 'intlevel' parameter must be a constant.
- * This macro returns a 32-bit value that must be passed to
- * XTOS_RESTORE_INTLEVEL() to restore the previous interrupt level.
- * XTOS_RESTORE_JUST_INTLEVEL() also does this, but in XEA2 configs
- * it restores only PS.INTLEVEL rather than the entire PS register
- * and thus is slower.
- */
-#if !XCHAL_HAVE_INTERRUPTS
-# define XTOS_SET_INTLEVEL(intlevel) 0
-# define XTOS_SET_MIN_INTLEVEL(intlevel) 0
-# define XTOS_RESTORE_INTLEVEL(restoreval)
-# define XTOS_RESTORE_JUST_INTLEVEL(restoreval)
-#elif XCHAL_HAVE_XEA2
-/* In XEA2, we can simply safely set PS.INTLEVEL directly: */
-/* NOTE: these asm macros don't modify memory, but they are marked
- * as such to act as memory access barriers to the compiler because
- * these macros are sometimes used to delineate critical sections;
- * function calls are natural barriers (the compiler does not know
- * whether a function modifies memory) unless declared to be inlined. */
-# define XTOS_SET_INTLEVEL(intlevel) ({ unsigned __tmp; \
- __asm__ __volatile__( "rsil %0, " XTSTR(intlevel) "\n" \
- : "=a" (__tmp) : : "memory" ); \
- __tmp;})
-# define XTOS_SET_MIN_INTLEVEL(intlevel) ({ unsigned __tmp, __tmp2, __tmp3; \
- __asm__ __volatile__( "rsr.ps %0\n" /* get old (current) PS.INTLEVEL */ \
- "movi %2, " XTSTR(intlevel) "\n" \
- "extui %1, %0, 0, 4\n" /* keep only INTLEVEL bits of parameter */ \
- "blt %2, %1, 1f\n" \
- "rsil %0, " XTSTR(intlevel) "\n" \
- "1:\n" \
- : "=a" (__tmp), "=&a" (__tmp2), "=&a" (__tmp3) : : "memory" ); \
- __tmp;})
-# define XTOS_RESTORE_INTLEVEL(restoreval) do{ unsigned __tmp = (restoreval); \
- __asm__ __volatile__( "wsr.ps %0 ; rsync\n" \
- : : "a" (__tmp) : "memory" ); \
- }while(0)
-# define XTOS_RESTORE_JUST_INTLEVEL(restoreval) _xtos_set_intlevel(restoreval)
-#else
-/* In XEA1, we have to rely on INTENABLE register virtualization: */
-extern unsigned _xtos_set_vpri( unsigned vpri );
-extern unsigned _xtos_vpri_enabled; /* current virtual priority */
-# define XTOS_SET_INTLEVEL(intlevel) _xtos_set_vpri(~XCHAL_INTLEVEL_ANDBELOW_MASK(intlevel))
-# define XTOS_SET_MIN_INTLEVEL(intlevel) _xtos_set_vpri(_xtos_vpri_enabled & ~XCHAL_INTLEVEL_ANDBELOW_MASK(intlevel))
-# define XTOS_RESTORE_INTLEVEL(restoreval) _xtos_set_vpri(restoreval)
-# define XTOS_RESTORE_JUST_INTLEVEL(restoreval) _xtos_set_vpri(restoreval)
-#endif
-
-/*
- * The following macros build upon the above. They are generally used
- * instead of invoking the SET_INTLEVEL and SET_MIN_INTLEVEL macros directly.
- * They all return a value that can be used with XTOS_RESTORE_INTLEVEL()
- * or _xtos_restore_intlevel() or _xtos_restore_just_intlevel() to restore
- * the effective interrupt level to what it was before the macro was invoked.
- * In XEA2, the DISABLE macros are much faster than the MASK macros
- * (in all configs, DISABLE sets the effective interrupt level, whereas MASK
- * makes ensures the effective interrupt level is at least the level given
- * without lowering it; in XEA2 with INTENABLE virtualization, these macros
- * affect PS.INTLEVEL only, not the virtual priority, so DISABLE has partial
- * MASK semantics).
- *
- * A typical critical section sequence might be:
- * unsigned rval = XTOS_DISABLE_EXCM_INTERRUPTS;
- * ... critical section ...
- * XTOS_RESTORE_INTLEVEL(rval);
- */
-/* Enable all interrupts (those activated with _xtos_ints_on()): */
-#define XTOS_ENABLE_INTERRUPTS XTOS_SET_INTLEVEL(0)
-/* Disable low priority level interrupts (they can interact with the OS): */
-#define XTOS_DISABLE_LOWPRI_INTERRUPTS XTOS_SET_INTLEVEL(XCHAL_NUM_LOWPRI_LEVELS)
-#define XTOS_MASK_LOWPRI_INTERRUPTS XTOS_SET_MIN_INTLEVEL(XCHAL_NUM_LOWPRI_LEVELS)
-/* Disable interrupts that can interact with the OS: */
-#define XTOS_DISABLE_EXCM_INTERRUPTS XTOS_SET_INTLEVEL(XCHAL_EXCM_LEVEL)
-#define XTOS_MASK_EXCM_INTERRUPTS XTOS_SET_MIN_INTLEVEL(XCHAL_EXCM_LEVEL)
-#if 0 /* XTOS_LOCK_LEVEL is not exported to applications */
-/* Disable interrupts that can interact with the OS, or manipulate virtual INTENABLE: */
-#define XTOS_DISABLE_LOCK_INTERRUPTS XTOS_SET_INTLEVEL(XTOS_LOCK_LEVEL)
-#define XTOS_MASK_LOCK_INTERRUPTS XTOS_SET_MIN_INTLEVEL(XTOS_LOCK_LEVEL)
-#endif
-/* Disable ALL interrupts (not for common use, particularly if one's processor
- * configuration has high-level interrupts and one cares about their latency): */
-#define XTOS_DISABLE_ALL_INTERRUPTS XTOS_SET_INTLEVEL(15)
-
-/* These two are deprecated. Use the newer functions below. */
-extern unsigned int _xtos_ints_off( unsigned int mask );
-extern unsigned int _xtos_ints_on( unsigned int mask );
-
-/* Newer functions to enable/disable the specified interrupt. */
-static inline void _xtos_interrupt_enable(unsigned int intnum)
-{
- _xtos_ints_on(1 << intnum);
-}
-
-static inline void _xtos_interrupt_disable(unsigned int intnum)
-{
- _xtos_ints_off(1 << intnum);
-}
-
-extern unsigned _xtos_set_intlevel( int intlevel );
-extern unsigned _xtos_set_min_intlevel( int intlevel );
-extern unsigned _xtos_restore_intlevel( unsigned restoreval );
-extern unsigned _xtos_restore_just_intlevel( unsigned restoreval );
-extern _xtos_handler _xtos_set_interrupt_handler( int n, _xtos_handler f );
-extern _xtos_handler _xtos_set_interrupt_handler_arg( int n, _xtos_handler f, void *arg );
-extern _xtos_handler _xtos_set_exception_handler( int n, _xtos_handler f );
-
-extern void _xtos_memep_initrams( void );
-extern void _xtos_memep_enable( int flags );
-
-/* For use with the tiny LSP (see LSP reference manual). */
-#if XCHAL_NUM_INTLEVELS >= 1
-extern void _xtos_dispatch_level1_interrupts( void );
-#endif
-#if XCHAL_NUM_INTLEVELS >= 2
-extern void _xtos_dispatch_level2_interrupts( void );
-#endif
-#if XCHAL_NUM_INTLEVELS >= 3
-extern void _xtos_dispatch_level3_interrupts( void );
-#endif
-#if XCHAL_NUM_INTLEVELS >= 4
-extern void _xtos_dispatch_level4_interrupts( void );
-#endif
-#if XCHAL_NUM_INTLEVELS >= 5
-extern void _xtos_dispatch_level5_interrupts( void );
-#endif
-#if XCHAL_NUM_INTLEVELS >= 6
-extern void _xtos_dispatch_level6_interrupts( void );
-#endif
-
-/* Deprecated (but kept because they were documented): */
-extern unsigned int _xtos_read_ints( void );
-extern void _xtos_clear_ints( unsigned int mask );
-
-
-/* Power shut-off related routines. */
-extern int _xtos_core_shutoff(unsigned flags);
-extern int _xtos_core_save(unsigned flags, XtosCoreState *savearea, void *code);
-extern void _xtos_core_restore(unsigned retvalue, XtosCoreState *savearea);
-
-
-#if XCHAL_NUM_CONTEXTS > 1
-extern unsigned _xtos_init_context(int context_num, int stack_size,
- _xtos_handler_func *start_func, int arg1);
-#endif
-
-/* Deprecated: */
-#if XCHAL_NUM_TIMERS > 0
-extern void _xtos_timer_0_delta( int cycles );
-#endif
-#if XCHAL_NUM_TIMERS > 1
-extern void _xtos_timer_1_delta( int cycles );
-#endif
-#if XCHAL_NUM_TIMERS > 2
-extern void _xtos_timer_2_delta( int cycles );
-#endif
-#if XCHAL_NUM_TIMERS > 3
-extern void _xtos_timer_3_delta( int cycles );
-#endif
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* !_ASMLANGUAGE && !__ASSEMBLER__ */
-
-#endif /* XTRUNTIME_H */
-
diff --git a/src/arch/xtensa/main-entry.S b/src/arch/xtensa/main-entry.S
deleted file mode 100644
index c77a74a..0000000
--- a/src/arch/xtensa/main-entry.S
+++ /dev/null
@@ -1,57 +0,0 @@
-/*
- * Copyright (c) 2017, Intel Corporation
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- * * Redistributions of source code must retain the above copyright
- * notice, this list of conditions and the following disclaimer.
- * * Redistributions in binary form must reproduce the above copyright
- * notice, this list of conditions and the following disclaimer in the
- * documentation and/or other materials provided with the distribution.
- * * Neither the name of the Intel Corporation nor the
- * names of its contributors may be used to endorse or promote products
- * derived from this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
- * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
- * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
- * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
- * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
- * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
- * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
- * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
- * POSSIBILITY OF SUCH DAMAGE.
- *
- * Author: Rander Wang <rander.wang@intel.com>
- */
-
-/*
- * Entry point from boot loader.
- * Fix link address of this entry to SOF_TEXT_START so that
- * it is easy for boot loader to jump to the baseFW becasue
- * the boot loader and baseFW are in different elf file.
- */
-
-
-// Exports
-.global _MainEntry
-
-
-/**************************************************************************/
-
- .begin literal_prefix .MainEntry
- .section .MainEntry.text, "ax"
-
- .align 4
- .global _MainEntry
-
-_MainEntry:
-
- call0 _start
-
- .size _MainEntry, . - _MainEntry
-
- .end literal_prefix
diff --git a/src/arch/xtensa/smp/Makefile.am b/src/arch/xtensa/smp/Makefile.am
deleted file mode 100644
index a937680..0000000
--- a/src/arch/xtensa/smp/Makefile.am
+++ /dev/null
@@ -1 +0,0 @@
-SUBDIRS = hal include xtos
diff --git a/src/arch/xtensa/smp/cpu.c b/src/arch/xtensa/smp/cpu.c
deleted file mode 100644
index 411725f..0000000
--- a/src/arch/xtensa/smp/cpu.c
+++ /dev/null
@@ -1,108 +0,0 @@
-/*
- * Copyright (c) 2018, Intel Corporation
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- * * Redistributions of source code must retain the above copyright
- * notice, this list of conditions and the following disclaimer.
- * * Redistributions in binary form must reproduce the above copyright
- * notice, this list of conditions and the following disclaimer in the
- * documentation and/or other materials provided with the distribution.
- * * Neither the name of the Intel Corporation nor the
- * names of its contributors may be used to endorse or promote products
- * derived from this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
- * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
- * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
- * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
- * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
- * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
- * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
- * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
- * POSSIBILITY OF SUCH DAMAGE.
- *
- * Author: Tomasz Lauda <tomasz.lauda@linux.intel.com>
- *
- */
-
-/**
- * \file arch/xtensa/smp/cpu.c
- * \brief Xtensa SMP CPU implementation file
- * \authors Tomasz Lauda <tomasz.lauda@linux.intel.com>
- */
-
-#include <arch/alloc.h>
-#include <arch/atomic.h>
-#include <arch/cpu.h>
-#include <arch/idc.h>
-#include <platform/platform.h>
-#include <sof/lock.h>
-#include <sof/schedule.h>
-
-static uint32_t active_cores_mask = 0x1;
-static spinlock_t lock = { 0 };
-
-void arch_cpu_enable_core(int id)
-{
- struct idc_msg power_up = {
- IDC_POWER_UP_MESSAGE, IDC_POWER_UP_EXTENSION, id };
- uint32_t flags;
-
- spin_lock_irq(&lock, flags);
-
- if (!(active_cores_mask & (1 << id))) {
- /* allocate resources for core */
- alloc_core_context(id);
-
- /* enable IDC interrupt for the the slave core */
- idc_enable_interrupts(id, arch_cpu_get_id());
-
- /* send IDC power up message */
- arch_idc_send_msg(&power_up, IDC_NON_BLOCKING);
-
- active_cores_mask |= (1 << id);
- }
-
- spin_unlock_irq(&lock, flags);
-}
-
-void arch_cpu_disable_core(int id)
-{
- struct idc_msg power_down = { IDC_POWER_DOWN_MESSAGE, 0, id };
- uint32_t flags;
-
- spin_lock_irq(&lock, flags);
-
- if (active_cores_mask & (1 << id)) {
- arch_idc_send_msg(&power_down, IDC_NON_BLOCKING);
-
- active_cores_mask ^= (1 << id);
- }
-
- spin_unlock_irq(&lock, flags);
-}
-
-int arch_cpu_is_core_enabled(int id)
-{
- return active_cores_mask & (1 << id);
-}
-
-void cpu_power_down_core(void)
-{
- arch_interrupt_global_disable();
-
- idc_free();
-
- scheduler_free();
-
- free_core_context(arch_cpu_get_id());
-
- dcache_writeback_invalidate_all();
-
- while (1)
- arch_wait_for_interrupt(0);
-}
diff --git a/src/arch/xtensa/smp/hal/Makefile.am b/src/arch/xtensa/smp/hal/Makefile.am
deleted file mode 100644
index 368ab56..0000000
--- a/src/arch/xtensa/smp/hal/Makefile.am
+++ /dev/null
@@ -1,235 +0,0 @@
-STATE_DEFS = \
- -D__SPLIT__extra_size \
- -D__SPLIT__extra_align \
- -D__SPLIT__cpregs_size \
- -D__SPLIT__cpregs_align \
- -D__SPLIT__cp_names \
- -D__SPLIT__all_extra_size \
- -D__SPLIT__all_extra_align \
- -D__SPLIT__num_coprocessors \
- -D__SPLIT__cp_num \
- -D__SPLIT__cp_max \
- -D__SPLIT__cp_mask \
- -D__SPLIT__cp_id_mappings \
- -D__SPLIT__cp_mask_mappings \
- -D__SPLIT__init_mem_extra \
- -D__SPLIT__init_mem_cp \
- -D__SPLIT__save_extra \
- -D__SPLIT__restore_extra \
- -D__SPLIT__save_cpregs \
- -D__SPLIT__save_cp0 \
- -D__SPLIT__save_cp1 \
- -D__SPLIT__save_cp2 \
- -D__SPLIT__save_cp3 \
- -D__SPLIT__save_cp4 \
- -D__SPLIT__save_cp5 \
- -D__SPLIT__save_cp6 \
- -D__SPLIT__save_cp7 \
- -D__SPLIT__restore_cpregs \
- -D__SPLIT__restore_cp0 \
- -D__SPLIT__restore_cp1 \
- -D__SPLIT__restore_cp2 \
- -D__SPLIT__restore_cp3 \
- -D__SPLIT__restore_cp4 \
- -D__SPLIT__restore_cp5 \
- -D__SPLIT__restore_cp6 \
- -D__SPLIT__restore_cp7 \
- -D__SPLIT__cpregs_save_fn \
- -D__SPLIT__cpregs_restore_fn \
- -D__SPLIT__validate_cp \
- -D__SPLIT__invalidate_cp \
- -D__SPLIT__get_cpenable \
- -D__SPLIT__set_cpenable
-
-STATE_DEFS_CNL = \
- -D__SPLIT__extra_size \
- -D__SPLIT__extra_align \
- -D__SPLIT__cpregs_size \
- -D__SPLIT__cpregs_align \
- -D__SPLIT__cp_names \
- -D__SPLIT__all_extra_size \
- -D__SPLIT__all_extra_align \
- -D__SPLIT__num_coprocessors \
- -D__SPLIT__cp_num \
- -D__SPLIT__cp_max \
- -D__SPLIT__cp_mask \
- -D__SPLIT__cp_id_mappings \
- -D__SPLIT__cp_mask_mappings \
- -D__SPLIT__init_mem_extra \
- -D__SPLIT__init_mem_cp \
- -D__SPLIT__save_extra \
- -D__SPLIT__restore_extra \
- -D__SPLIT__cpregs_save_fn \
- -D__SPLIT__cpregs_restore_fn \
- -D__SPLIT__validate_cp \
- -D__SPLIT__invalidate_cp \
- -D__SPLIT__get_cpenable \
- -D__SPLIT__set_cpenable
-
-DISASS_DEFS = \
- -D__SPLIT__op0_format_lengths \
- -D__SPLIT__byte0_format_lengths \
- -D__SPLIT__disassemble_size \
- -D__SPLIT__disassemble
-
-MISC_DEFS = \
- -D__SPLIT__clear_regcached_code
-
-# Call0 ABI means the xthal... and xthal..._nw functions are
-# identical. If we're building for Call0 ABI, omit the ..._nw
-# functions (except for xthal_get_intpending_nw, an interrupt handler
-# helper function for which there is no duplicate and which does not
-# obey _any_ calling conventions).
-INTERRUPTS_DEFS = \
- -D__SPLIT__num_intlevels \
- -D__SPLIT__num_interrupts \
- -D__SPLIT__excm_level \
- -D__SPLIT__intlevel \
- -D__SPLIT__get_intenable \
- -D__SPLIT__set_intenable \
- -D__SPLIT__get_interrupt \
- -D__SPLIT__set_intset \
- -D__SPLIT__set_intclear
-
-CACHE_DEFS = \
- -D__SPLIT__get_cacheattr \
- -D__SPLIT__get_icacheattr \
- -D__SPLIT__set_cacheattr \
- -D__SPLIT__set_icacheattr \
- -D__SPLIT__set_dcacheattr \
- -D__SPLIT__set_idcacheattr \
- -D__SPLIT__idcache_is_enabled \
- -D__SPLIT__icache_is_enabled \
- -D__SPLIT__dcache_is_enabled \
- -D__SPLIT__idcache_is_enabled \
- -D__SPLIT__icache_all_invalidate \
- -D__SPLIT__dcache_all_invalidate \
- -D__SPLIT__dcache_all_writeback \
- -D__SPLIT__dcache_all_writeback_inv \
- -D__SPLIT__icache_all_unlock \
- -D__SPLIT__dcache_all_unlock \
- -D__SPLIT__icache_region_invalidate \
- -D__SPLIT__dcache_region_invalidate \
- -D__SPLIT__dcache_region_writeback \
- -D__SPLIT__dcache_region_writeback_inv \
- -D__SPLIT__icache_region_lock \
- -D__SPLIT__dcache_region_lock \
- -D__SPLIT__icache_region_unlock \
- -D__SPLIT__dcache_region_unlock \
- -D__SPLIT__icache_line_invalidate \
- -D__SPLIT__dcache_line_invalidate \
- -D__SPLIT__dcache_line_writeback \
- -D__SPLIT__dcache_line_writeback_inv \
- -D__SPLIT__icache_line_lock \
- -D__SPLIT__dcache_line_lock \
- -D__SPLIT__icache_line_unlock \
- -D__SPLIT__dcache_line_unlock \
- -D__SPLIT__icache_sync \
- -D__SPLIT__dcache_sync \
- -D__SPLIT__icache_get_ways \
- -D__SPLIT__icache_set_ways \
- -D__SPLIT__dcache_get_ways \
- -D__SPLIT__dcache_set_ways \
- -D__SPLIT__cache_coherence_on \
- -D__SPLIT__cache_coherence_off \
- -D__SPLIT__set_cache_prefetch_long \
- -D__SPLIT__set_cache_prefetch \
- -D__SPLIT__get_cache_prefetch \
- -D__SPLIT__hw_configid0 \
- -D__SPLIT__hw_configid1 \
- -D__SPLIT__release_major \
- -D__SPLIT__release_minor
-
-
-if BUILD_BAYTRAIL
-PLATFORM_DEFS = \
- $(STATE_DEFS) \
- $(DISASS_DEFS) \
- $(MISC_DEFS) \
- $(INTERRUPTS_DEFS) \
- $(CACHE_DEFS)
-endif
-
-if BUILD_CHERRYTRAIL
-PLATFORM_DEFS = \
- $(STATE_DEFS) \
- $(DISASS_DEFS) \
- $(MISC_DEFS) \
- $(INTERRUPTS_DEFS) \
- $(CACHE_DEFS)
-endif
-
-if BUILD_BROADWELL
-PLATFORM_DEFS = \
- $(STATE_DEFS) \
- $(DISASS_DEFS) \
- $(MISC_DEFS) \
- $(INTERRUPTS_DEFS) \
- $(CACHE_DEFS)
-endif
-
-if BUILD_HASWELL
-PLATFORM_DEFS = \
- $(STATE_DEFS) \
- $(DISASS_DEFS) \
- $(MISC_DEFS) \
- $(INTERRUPTS_DEFS) \
- $(CACHE_DEFS)
-endif
-
-if BUILD_APOLLOLAKE
-PLATFORM_DEFS = \
- $(STATE_DEFS) \
- $(DISASS_DEFS) \
- $(MISC_DEFS) \
- $(INTERRUPTS_DEFS) \
- $(CACHE_DEFS)
-endif
-
-if BUILD_CANNONLAKE
-PLATFORM_DEFS = \
- $(STATE_DEFS_CNL) \
- $(DISASS_DEFS) \
- $(MISC_DEFS) \
- $(INTERRUPTS_DEFS) \
- $(CACHE_DEFS)
-endif
-
-noinst_LIBRARIES = libhal.a
-
-libhal_a_SOURCES = \
- attribute.c \
- cache.c \
- cache_asm.S \
- clock.S \
- coherence.c \
- debug.c \
- debug_hndlr.S \
- disass.c \
- int_asm.S \
- interrupts.c \
- memcopy.S \
- mem_ecc_parity.S \
- misc.c \
- miscellaneous.S \
- mmu.c \
- mp_asm.S \
- mpu_asm.S \
- mpu.c \
- set_region_translate.c \
- state_asm.S \
- state.c \
- syscache_asm.S \
- windowspill_asm.S
-
-libhal_a_CFLAGS = \
- $(ARCH_INCDIR) \
- $(ARCH_CFLAGS) \
- $(PLATFORM_INCDIR) \
- $(PLATFORM_DEFS)
-
-libhal_a_CCASFLAGS = \
- $(ARCH_INCDIR) \
- $(ARCH_ASFLAGS) \
- $(PLATFORM_INCDIR) \
- $(PLATFORM_DEFS)
diff --git a/src/arch/xtensa/smp/hal/attribute.c b/src/arch/xtensa/smp/hal/attribute.c
deleted file mode 100644
index 7d663b2..0000000
--- a/src/arch/xtensa/smp/hal/attribute.c
+++ /dev/null
@@ -1,282 +0,0 @@
-/* attribute.c - Cache attribute (memory access mode) related functions */
-
-/* $Id: //depot/rel/Foxhill/dot.8/Xtensa/OS/hal/attribute.c#1 $ */
-
-/*
- * Copyright (c) 2004-2009 Tensilica Inc.
- *
- * Permission is hereby granted, free of charge, to any person obtaining
- * a copy of this software and associated documentation files (the
- * "Software"), to deal in the Software without restriction, including
- * without limitation the rights to use, copy, modify, merge, publish,
- * distribute, sublicense, and/or sell copies of the Software, and to
- * permit persons to whom the Software is furnished to do so, subject to
- * the following conditions:
- *
- * The above copyright notice and this permission notice shall be included
- * in all copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
- * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
- * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
- * IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY
- * CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
- * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
- * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
- */
-
-#include <xtensa/config/core.h>
-
-
-
-/*
- * Set the "cache attribute" (encoded memory access modes)
- * of the region of memory specified by <vaddr> and <size>.
- *
- * This function is only supported on processor configurations
- * with region protection (or XEA1). It has no effect on
- * a processor configured with an MMU (with autorefill).
- *
- * SPECIFYING THE MEMORY REGION
- * The full (4 GB) address space may be specified with an
- * address of zero and a size of 0xFFFFFFFF (or -1);
- * in fact whenever <vaddr>+<size> equal 0xFFFFFFFF, <size>
- * is interpreted as one byte greater than that specified.
- *
- * If the specified memory range exactly covers a series
- * of consecutive 512 MB regions, the cache attributes of
- * these regions are updated with the requested attribute.
- * If this is not the case, e.g. if either or both the
- * start and end of the range only partially cover a 512 MB
- * region, one of three results are possible:
- *
- * 1. By default, the cache attribute of all regions
- * covered, even just partially, is changed to
- * the requested attribute.
- *
- * 2. If the XTHAL_CAFLAG_EXACT flag is specified,
- * a non-zero error code is returned.
- *
- * 3. If the XTHAL_CAFLAG_NO_PARTIAL flag is specified
- * (but not the EXACT flag), only regions fully
- * covered by the specified range are updated with
- * the requested attribute.
- *
- * WRITEBACK CACHE HANDLING
- * This function automatically writes back dirty data when
- * switching a region from writeback mode to a non-writeback mode.
- * This writeback is done safely, ie. by first switching to writethrough
- * mode, then invoking xthal_dcache_all_writeback(), then switching to
- * the selected <cattr> mode. Such a sequence is necessary to ensure
- * there is no longer any dirty data in the memory region by the time
- * this function returns, even in the presence of interrupts, speculation, etc.
- * This avoids memory coherency problems when switching from writeback
- * to bypass mode (in bypass mode, loads go directly to memory, ignoring
- * any dirty data in the cache; also, such dirty data can still be castout
- * due to seemingly unrelated stores).
- * This automatic write-back can be disabled using the XTHAL_CAFLAG_NO_AUTO_WB flag.
- *
- * CACHE DISABLE THEN ENABLE HANDLING
- * To avoid cache coherency issues when the cache is disabled, then
- * memory is modified, then then cache is re-enabled (thus making
- * visible stale cache entries), this function automatically
- * invalidates the cache when any region switches to bypass mode.
- * For efficiency, the entire cache is invalidated -- this is done
- * using writeback-invalidate operations to ensure coherency even
- * when other regions still have write-back caches enabled.
- * This automatic invalidate can be disabled using the XTHAL_CAFLAG_NO_AUTO_INV flag.
- *
- * Parameters:
- * vaddr starting virtual address of region of memory
- *
- * size number of bytes in region of memory
- * (see above, SPECIFYING THE MEMORY REGION)
- *
- * cattr cache attribute (encoded);
- * typically taken from compile-time HAL constants
- * XCHAL_CA_{BYPASS[BUF], WRITETHRU, WRITEBACK[_NOALLOC], ILLEGAL}
- * (defined in <xtensa/config/core.h>);
- * in XEA1, this corresponds to the value of a nibble
- * in the CACHEATTR register;
- * in XEA2, this corresponds to the value of the
- * cache attribute (CA) field of each TLB entry
- *
- * On MPU configurations, the cattr is composed of accessRights
- * and memoryType. The accessRights occupy bits 0..3 and are
- * typically taken from the XTHAL_AR constants. The memory type
- * is specified by either a bitwise or-ing of the XTHAL_MEM_...
- * constants or if none of the XTHAL_MEM_... constants are
- * specified, bits 4..12 are used for the memory type (that
- * allows a cattr obtained by xthal_v2p() to be passed directly.
- *
- * In addition on MPU configurations if the
- * XTHAL_MPU_USE_EXISTING_MEMORY_TYPE bit is set then the existing
- * memoryType at the first address in the region is used for the
- * memoryType of the new region.
- *
- * Likewise, if the XTHAL_MPU_USE_EXISTING_ACCESS_RIGHTS bit is set
- * in cattr, then the existing accessRights at the first address
- * in the region are used for the accessRights of the new region.
- *
- * flags bitwise combination of flags XTHAL_CAFLAG_*
- * (see xtensa/hal.h for brief description of each flag);
- * (see also various descriptions above);
- *
- * The XTHAL_CAFLAG_EXPAND flag prevents attribute changes
- * to regions whose current cache attribute already provide
- * greater access than the requested attribute.
- * This ensures access to each region can only "expand",
- * and thus continue to work correctly in most instances,
- * possibly at the expense of performance. This helps
- * make this flag safer to use in a variety of situations.
- * For the purposes of this flag, cache attributes are
- * ordered (in "expansion" order, from least to greatest
- * access) as follows:
- * XCHAL_CA_ILLEGAL no access allowed
- * (various special and reserved attributes)
- * XCHAL_CA_WRITEBACK writeback cached
- * XCHAL_CA_WRITEBACK_NOALLOC writeback no-write-alloc
- * XCHAL_CA_WRITETHRU writethrough cached
- * XCHAL_CA_BYPASSBUF bypass with write buffering
- * XCHAL_CA_BYPASS bypass (uncached)
- * This is consistent with requirements of certain
- * devices that no caches be used, or in certain cases
- * that writethrough caching is allowed but not writeback.
- * Thus, bypass mode is assumed to work for most/all types
- * of devices and memories (albeit at reduced performance
- * compared to cached modes), and is ordered as providing
- * greatest access (to most devices).
- * Thus, this XTHAL_CAFLAG_EXPAND flag has no effect when
- * requesting the XCHAL_CA_BYPASS attribute (one can always
- * expand to bypass mode). And at the other extreme,
- * no action is ever taken by this function when specifying
- * both the XTHAL_CAFLAG_EXPAND flag and the XCHAL_CA_ILLEGAL
- * cache attribute.
- *
- * The XTHAL_CAFLAG_EXPAND is not supported on MPU configurations.
- *
- * Returns:
- * 0 successful, or size is zero
- * -1 XTHAL_CAFLAG_NO_PARTIAL flag specified and address range
- * is valid with a non-zero size, however no 512 MB region (or page)
- * is completely covered by the range
- * -2 XTHAL_CAFLAG_EXACT flag specified, and address range does
- * not exactly specify a 512 MB region (or page)
- * -3 invalid address range specified (wraps around the end of memory)
- * -4 function not supported in this processor configuration
- */
-int xthal_set_region_attribute( void *vaddr, unsigned size, unsigned cattr, unsigned flags )
-{
-#if XCHAL_HAVE_MPU
- if (cattr & 0xffffe000) // check if XTHAL mem flags were supplied
- // in this case just pass cattr as the memType paramenter
- return xthal_mpu_set_region_attribute(vaddr, size, cattr, cattr, flags);
- else
- // otherwise we take the bits 0-3 for accessRights and bits 4-13 as the memoryType
- return xthal_mpu_set_region_attribute(vaddr, size, cattr & 0xf, (cattr & 0x1ff0) >> 4, flags);
-#elif XCHAL_HAVE_PTP_MMU && !XCHAL_HAVE_SPANNING_WAY
- return -4; /* full MMU not supported */
-#else
-/* These cache attribute encodings are valid for XEA1 and region protection only: */
-# if XCHAL_HAVE_PTP_MMU
-# define CA_BYPASS XCHAL_CA_BYPASS
-# ifdef XCHAL_CA_BYPASSBUF
-# define CA_BYPASSBUF XCHAL_CA_BYPASSBUF
-# else
-# define CA_BYPASSBUF XCHAL_CA_BYPASS
-# endif
-# define CA_WRITETHRU XCHAL_CA_WRITETHRU
-# define CA_WRITEBACK XCHAL_CA_WRITEBACK
-# define CA_WRITEBACK_NOALLOC XCHAL_CA_WRITEBACK_NOALLOC
-# define CA_ILLEGAL XCHAL_CA_ILLEGAL
-# else
-/* Hardcode these, because they get remapped when caches or writeback not configured: */
-# define CA_BYPASS 2
-# define CA_BYPASSBUF 6
-# define CA_WRITETHRU 1
-# define CA_WRITEBACK 4
-# define CA_WRITEBACK_NOALLOC 5
-# define CA_ILLEGAL 15
-# endif
-# define CA_MASK 0xF /*((1L<<XCHAL_CA_BITS)-1)*/ /* mask of cache attribute bits */
-# define IS_CACHED(attr) ((attr == CA_BYPASS) || (attr == CA_BYPASSBUF))
-
- unsigned start_region, start_offset, end_vaddr, end_region, end_offset;
- unsigned cacheattr, cachewrtr, i, disabled_cache = 0;
-
- if (size == 0)
- return 0;
- end_vaddr = (unsigned)vaddr + size - 1;
- if (end_vaddr < (unsigned)vaddr)
- return -3; /* address overflow/wraparound error */
- if (end_vaddr == 0xFFFFFFFE /*&& (unsigned)vaddr == 0*/ )
- end_vaddr = 0xFFFFFFFF; /* allow specifying 4 GB */
- start_region = ((unsigned)vaddr >> 29);
- start_offset = ((unsigned)vaddr & 0x1FFFFFFF);
- end_region = (end_vaddr >> 29);
- end_offset = ((end_vaddr+1) & 0x1FFFFFFF);
- if (flags & XTHAL_CAFLAG_EXACT) {
- if (start_offset != 0 || end_offset != 0)
- return -2; /* not an exact-sized range */
- } else if (flags & XTHAL_CAFLAG_NO_PARTIAL) {
- if (start_offset != 0)
- start_region++;
- if (end_offset != 0)
- end_region--;
- if (start_region > end_region)
- return -1; /* nothing fully covered by specified range */
- }
- cacheattr = cachewrtr = xthal_get_cacheattr();
- cattr &= CA_MASK;
-# if XCHAL_ICACHE_SIZE == 0 && XCHAL_DCACHE_SIZE == 0
- if (cattr == CA_WRITETHRU || cattr == CA_WRITEBACK || cattr == CA_WRITEBACK_NOALLOC)
- cattr = CA_BYPASS; /* no caches configured, only do protection */
-# elif XCHAL_DCACHE_IS_WRITEBACK == 0
- if (cattr == CA_WRITEBACK || cattr == CA_WRITEBACK_NOALLOC)
- cattr = CA_WRITETHRU; /* no writeback configured for data cache */
-# endif
- for (i = start_region; i <= end_region; i++) {
- unsigned sh = (i << 2); /* bit offset of nibble for region i */
- unsigned oldattr = ((cacheattr >> sh) & CA_MASK);
- unsigned newattr = cattr;
- if (flags & XTHAL_CAFLAG_EXPAND) {
- /* This array determines whether a cache attribute can be changed
- * from <a> to <b> with the EXPAND flag; an attribute's "pri"
- * value (from this array) can only monotonically increase: */
- const static signed char _Xthal_ca_pri[16] = {[CA_ILLEGAL] = -1,
- [CA_WRITEBACK] = 3, [CA_WRITEBACK_NOALLOC] = 3, [CA_WRITETHRU] = 4, [CA_BYPASSBUF] = 8, [CA_BYPASS] = 9 };
- if (_Xthal_ca_pri[newattr] < _Xthal_ca_pri[oldattr])
- newattr = oldattr; /* avoid going to lesser access */
- }
- if (IS_CACHED(newattr) && !IS_CACHED(oldattr))
- disabled_cache = 1; /* we're disabling the cache for some region */
-# if XCHAL_DCACHE_IS_WRITEBACK
- {
- unsigned tmpattr = newattr;
- if ((oldattr == CA_WRITEBACK || oldattr == CA_WRITEBACK_NOALLOC)
- && newattr != CA_WRITEBACK && newattr != CA_WRITEBACK_NOALLOC) /* leaving writeback mode? */
- tmpattr = CA_WRITETHRU; /* leave it safely! */
- cachewrtr = ((cachewrtr & ~(CA_MASK << sh)) | (tmpattr << sh));
- }
-# endif
- cacheattr = ((cacheattr & ~(CA_MASK << sh)) | (newattr << sh));
- }
-# if XCHAL_DCACHE_IS_WRITEBACK
- if (cacheattr != cachewrtr /* need to leave writeback safely? */
- && (flags & XTHAL_CAFLAG_NO_AUTO_WB) == 0) {
- xthal_set_cacheattr(cachewrtr); /* set to writethru first, to safely writeback any dirty data */
- xthal_dcache_all_writeback(); /* much quicker than scanning entire 512MB region(s) */
- }
-# endif
- xthal_set_cacheattr(cacheattr);
- /* After disabling the cache, invalidate cache entries
- * to avoid coherency issues when later re-enabling it: */
- if (disabled_cache && (flags & XTHAL_CAFLAG_NO_AUTO_INV) == 0) {
- xthal_dcache_all_writeback_inv(); /* we might touch regions of memory still enabled write-back,
- so must use writeback-invalidate, not just invalidate */
- xthal_icache_all_invalidate();
- }
- return( 0 );
-#endif /* !(XCHAL_HAVE_PTP_MMU && !XCHAL_HAVE_SPANNING_WAY) */
-}
-
diff --git a/src/arch/xtensa/smp/hal/cache.c b/src/arch/xtensa/smp/hal/cache.c
deleted file mode 100644
index 4f6e292..0000000
--- a/src/arch/xtensa/smp/hal/cache.c
+++ /dev/null
@@ -1,53 +0,0 @@
-//
-// cache.c -- cache management routines
-//
-// $Id: //depot/rel/Foxhill/dot.8/Xtensa/OS/hal/cache.c#1 $
-
-// Copyright (c) 2002 Tensilica Inc.
-//
-// Permission is hereby granted, free of charge, to any person obtaining
-// a copy of this software and associated documentation files (the
-// "Software"), to deal in the Software without restriction, including
-// without limitation the rights to use, copy, modify, merge, publish,
-// distribute, sublicense, and/or sell copies of the Software, and to
-// permit persons to whom the Software is furnished to do so, subject to
-// the following conditions:
-//
-// The above copyright notice and this permission notice shall be included
-// in all copies or substantial portions of the Software.
-//
-// THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
-// EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
-// MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
-// IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY
-// CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
-// TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
-// SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
-
-#include <xtensa/config/core.h>
-
-// size of the cache lines in log2(bytes)
-const unsigned char Xthal_icache_linewidth = XCHAL_ICACHE_LINEWIDTH;
-const unsigned char Xthal_dcache_linewidth = XCHAL_DCACHE_LINEWIDTH;
-
-// size of the cache lines in bytes
-const unsigned short Xthal_icache_linesize = XCHAL_ICACHE_LINESIZE;
-const unsigned short Xthal_dcache_linesize = XCHAL_DCACHE_LINESIZE;
-
-// number of cache sets in log2(lines per way)
-const unsigned char Xthal_icache_setwidth = XCHAL_ICACHE_SETWIDTH;
-const unsigned char Xthal_dcache_setwidth = XCHAL_DCACHE_SETWIDTH;
-
-// cache set associativity (number of ways)
-const unsigned int Xthal_icache_ways = XCHAL_ICACHE_WAYS;
-const unsigned int Xthal_dcache_ways = XCHAL_DCACHE_WAYS;
-
-// size of the caches in bytes (ways * 2^(linewidth + setwidth))
-const unsigned int Xthal_icache_size = XCHAL_ICACHE_SIZE;
-const unsigned int Xthal_dcache_size = XCHAL_DCACHE_SIZE;
-
-// cache features
-const unsigned char Xthal_dcache_is_writeback = XCHAL_DCACHE_IS_WRITEBACK;
-const unsigned char Xthal_icache_line_lockable = XCHAL_ICACHE_LINE_LOCKABLE;
-const unsigned char Xthal_dcache_line_lockable = XCHAL_DCACHE_LINE_LOCKABLE;
-
diff --git a/src/arch/xtensa/smp/hal/cache_asm.S b/src/arch/xtensa/smp/hal/cache_asm.S
deleted file mode 100644
index 9bb1043..0000000
--- a/src/arch/xtensa/smp/hal/cache_asm.S
+++ /dev/null
@@ -1,1073 +0,0 @@
-//
-// cache_asm.S - assembly language cache management routines
-//
-// $Id: //depot/rel/Foxhill/dot.8/Xtensa/OS/hal/cache_asm.S#1 $
-
-// Copyright (c) 1999-2015 Cadence Design Systems, Inc.
-//
-// Permission is hereby granted, free of charge, to any person obtaining
-// a copy of this software and associated documentation files (the
-// "Software"), to deal in the Software without restriction, including
-// without limitation the rights to use, copy, modify, merge, publish,
-// distribute, sublicense, and/or sell copies of the Software, and to
-// permit persons to whom the Software is furnished to do so, subject to
-// the following conditions:
-//
-// The above copyright notice and this permission notice shall be included
-// in all copies or substantial portions of the Software.
-//
-// THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
-// EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
-// MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
-// IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY
-// CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
-// TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
-// SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
-
-#include <xtensa/cacheasm.h>
-#include <xtensa/cacheattrasm.h>
-#include <xtensa/xtensa-versions.h>
-
-
-
-
-//----------------------------------------------------------------------
-// Huge Range cache routines
-//----------------------------------------------------------------------
-
- // void xthal_dcache_hugerange_<name>(void *addr, unsigned size);
- //
- // Invalidate and/or writeback dcache entries for an arbitrary large
- // virtual address range with a single scan of the dcache.
- // Assumes no address translation, i.e. virtual = physical.
- //
- // a2 = ptr to range
- // a3 = size of range
- //
- // Note: -128 is a valid immediate for ADDI, but +128 is not,
- // and ADDI can relax to ADDMI for multiples of 256. So scanning
- // cache backwards (from end to start) allows all cache line sizes
- // without creating an extra instruction for the ADDI.
- //
- .macro dcache_hugefunc name, instruction
- .text
- .align 4
- .type xthal_dcache_hugerange_\name,@function
- .global xthal_dcache_hugerange_\name
-xthal_dcache_hugerange_\name:
- abi_entry
-#if (!defined(XCHAL_HAVE_NX) || XCHAL_HAVE_NX == 0) && XCHAL_DCACHE_SIZE > 0 \
- && XCHAL_HAVE_DCACHE_TEST && XCHAL_HAVE_MINMAX && XCHAL_HAVE_LOOPS
- movi a4, XCHAL_DCACHE_SIZE*2 // size at which to use huge algorithm
- movi a7, -XCHAL_DCACHE_LINESIZE // for rounding to cache line size
- bltu a3, a4, 7f // use normal (line-by-line hit) function
-#if XCHAL_HAVE_PREFETCH
- movi a11, 0
- xsr.prefctl a11 // temporarily disable prefetch (invalidates prefetch bufs!)
-#endif
- add a5, a3, a2 // a5 = end of range
- and a4, a2, a7 // a4 = low end, rounded to containing cache line
- addi a5, a5, /*XCHAL_DCACHE_LINESIZE*/-1
- and a5, a5, a7 // a5 = high end, rounded to containing cache line
- movi a7, XCHAL_DCACHE_SIZE/XCHAL_DCACHE_LINESIZE // a7 = number of lines in dcache
- movi a3, XCHAL_DCACHE_SIZE-XCHAL_DCACHE_LINESIZE // way index
- mov a6, a5
- //movi a8, -XCHAL_DCACHE_SETSIZE // use if LDCT gives non-zero index bits
- movi a10, (XCHAL_DCACHE_SIZE/XCHAL_DCACHE_WAYS) - 1
-
- loopgtz a7, 1f
- ldct a7, a3 // a3 = cache tag for cache entry [a7]
- \instruction a2, 0
- .begin schedule
- //extui a9, a3, 0, XCHAL_DCACHE_SETWIDTH+XCHAL_DCACHE_LINEWIDTH
- and a9, a3, a10
- addi a3, a3, -XCHAL_DCACHE_LINESIZE
- .end schedule
- .begin schedule
- //and a7, a7, a8 // uncomment if LDCT reports non-zero index bits
- maxu a6, a6, a4 // a4 = low end of range
- minu a2, a6, a5 // a5 = high end of range
- or a6, a7, a9
- .end schedule
-1:
-
- \instruction a2, 0
- maxu a6, a6, a4
- minu a2, a6, a5
- \instruction a2, 0
-#if XCHAL_HAVE_PREFETCH
- wsr.prefctl a11 // restore prefetch
-#endif
- isync_return_nop
- abi_return
-#endif /* dcache supports hugerange */
-// Jump to non-huge routine
-7: j.l xthal_dcache_region_\name + ABI_ENTRY_MINSIZE, a4
- .size xthal_dcache_hugerange_\name, . - xthal_dcache_hugerange_\name
- .endm
-
-
-
- // void xthal_icache_hugerange_<name>(void *addr, unsigned size);
- //
- // Invalidate icache entries for an arbitrary large
- // virtual address range with a single scan of the icache.
- // Assumes no address translation, i.e. virtual = physical.
- //
- // a2 = ptr to range
- // a3 = size of range
- //
- // Note: -128 is a valid immediate for ADDI, but +128 is not,
- // and ADDI can relax to ADDMI for multiples of 256. So scanning
- // cache backwards (from end to start) allows all cache line sizes
- // without creating an extra instruction for the ADDI.
- //
- .macro icache_hugefunc name, instruction
- .text
- .align 4
- .type xthal_icache_hugerange_\name,@function
- .global xthal_icache_hugerange_\name
-xthal_icache_hugerange_\name:
- abi_entry
-#if (!defined(XCHAL_HAVE_NX) || XCHAL_HAVE_NX == 0) &&XCHAL_ICACHE_SIZE > 0 && \
- XCHAL_HAVE_ICACHE_TEST && XCHAL_HAVE_MINMAX && XCHAL_HAVE_LOOPS
- movi a4, XCHAL_ICACHE_SIZE*2 // size at which to use huge algorithm
- movi a7, -XCHAL_ICACHE_LINESIZE // for rounding to cache line size
- bltu a3, a4, 7f // use normal (line-by-line hit) function
- add a5, a3, a2 // a5 = end of range
- and a4, a2, a7 // a4 = low end, rounded to containing cache line
- addi a5, a5, XCHAL_ICACHE_LINESIZE-1
- and a5, a5, a7 // a5 = high end, rounded to containing cache line
- movi a7, XCHAL_ICACHE_SIZE/XCHAL_ICACHE_LINESIZE // a7 = number of lines in dcache
- movi a3, XCHAL_ICACHE_SIZE-XCHAL_ICACHE_LINESIZE // way index
- mov a6, a5
- //movi a8, -XCHAL_ICACHE_SETSIZE // use if LICT gives non-zero index bits
- movi a10, (XCHAL_ICACHE_SIZE/XCHAL_ICACHE_WAYS) - 1
-
- loopgtz a7, 1f
- lict a7, a3 // a3 = cache tag for cache entry [a7]
- \instruction a2, 0
- .begin schedule
- //extui a9, a3, 0, XCHAL_ICACHE_SETWIDTH+XCHAL_ICACHE_LINEWIDTH
- and a9, a3, a10
- addi a3, a3, -XCHAL_ICACHE_LINESIZE
- .end schedule
- .begin schedule
- //and a7, a7, a8 // uncomment if LDCT reports non-zero index bits
- maxu a6, a6, a4 // a4 = low end of range
- minu a2, a6, a5 // a5 = high end of range
- or a6, a7, a9
- .end schedule
-1:
-
- \instruction a2, 0
- maxu a6, a6, a4
- minu a2, a6, a5
- \instruction a2, 0
- isync_return_nop
- abi_return
-#endif /* icache supports hugerange */
-7: j.l xthal_icache_region_\name + ABI_ENTRY_MINSIZE, a4
- .size xthal_icache_hugerange_\name, . - xthal_icache_hugerange_\name
- .endm
-
-
-
-
- .text
-
-//----------------------------------------------------------------------
-// Read CACHEATTR register
-//----------------------------------------------------------------------
-
-#if defined(__SPLIT__get_cacheattr) ||\
- defined(__SPLIT__get_cacheattr_nw)
-
-// unsigned xthal_get_cacheattr(void);
-
-DECLFUNC(xthal_get_cacheattr)
-DECLFUNC(xthal_get_dcacheattr)
-# if XCHAL_HAVE_CACHEATTR /* single CACHEATTR register used for both I and D */
-DECLFUNC(xthal_get_icacheattr)
-# endif
- abi_entry
- dcacheattr_get
- abi_return
- endfunc
-
-#endif
-
-#if defined(__SPLIT__get_icacheattr) ||\
- defined(__SPLIT__get_icacheattr_nw)
-
-// unsigned xthal_get_icacheattr(void);
-
-# if !XCHAL_HAVE_CACHEATTR /* possibly independent CACHEATTR states used for I and D */
-DECLFUNC(xthal_get_icacheattr)
- abi_entry
- icacheattr_get
- abi_return
- endfunc
-# endif
-
-#endif /*split*/
-
-
-//----------------------------------------------------------------------
-// Write CACHEATTR register, or equivalent.
-//----------------------------------------------------------------------
-
-/*
- * Set CACHEATTR register in a safe manner.
- *
- * void xthal_set_cacheattr( unsigned new_cacheattr );
- * void xthal_set_icacheattr( unsigned new_cacheattr );
- * void xthal_set_dcacheattr( unsigned new_cacheattr );
- */
-
-#if defined(__SPLIT__set_cacheattr) ||\
- defined(__SPLIT__set_cacheattr_nw)
-
-# if XCHAL_HAVE_CACHEATTR /* single CACHEATTR register used for both I and D accesses */
-DECLFUNC(xthal_set_icacheattr)
-DECLFUNC(xthal_set_dcacheattr)
-# endif
-DECLFUNC(xthal_set_cacheattr)
- abi_entry
- cacheattr_set
- abi_return
- endfunc
-
-#endif /*split*/
-
-
-#if XCHAL_HAVE_CACHEATTR
-
- /*
- * Already done above.
- *
- * Since we can't enable/disable the icache and dcache independently,
- * and don't have a nice place to store a state which would enable
- * us to only enable them both when both have been requested to be
- * enabled, we simply enable both for any request to enable either,
- * and disable both for any request to disable either cache.
- */
-
-#elif XCHAL_HAVE_MIMIC_CACHEATTR || XCHAL_HAVE_XLT_CACHEATTR || (XCHAL_HAVE_PTP_MMU && XCHAL_HAVE_SPANNING_WAY)
-
-# if defined(__SPLIT__set_icacheattr) \
- || defined(__SPLIT__set_icacheattr_nw)
-
-DECLFUNC(xthal_set_icacheattr)
- abi_entry
- icacheattr_set
- isync_return_nop
- abi_return
- endfunc
-
-# endif
-
-# if defined(__SPLIT__set_dcacheattr) \
- || defined(__SPLIT__set_dcacheattr_nw)
-
-DECLFUNC(xthal_set_dcacheattr)
- abi_entry
- dcacheattr_set
- abi_return
- endfunc
-
-# endif /*split*/
-
-#else /* full MMU (pre-v3): */
-
-# if defined(__SPLIT__set_idcacheattr) \
- || defined(__SPLIT__set_idcacheattr_nw)
-
-// These functions aren't applicable to arbitrary MMU configurations.
-// Do nothing in this case.
-
-DECLFUNC(xthal_set_icacheattr)
-DECLFUNC(xthal_set_dcacheattr)
- abi_entry
- abi_return
- endfunc
-
-# endif /*split*/
-
-#endif /* cacheattr/MMU type */
-
-
-//----------------------------------------------------------------------
-// Determine (guess) whether caches are "enabled"
-//----------------------------------------------------------------------
-
-/*
- * There is no "cache enable" bit in the Xtensa architecture,
- * but we can use CACHEATTR (if it or its equivalent exists)
- * as an indication that caches have been enabled.
- */
-
-#if XCHAL_HAVE_CACHEATTR
-
-# if defined(__SPLIT__idcache_is_enabled) || \
- defined(__SPLIT__idcache_is_enabled_nw)
-
-DECLFUNC(xthal_icache_is_enabled)
-DECLFUNC(xthal_dcache_is_enabled)
- abi_entry
- cacheattr_is_enabled 2f
- movi a2, 0
- abi_return
-2: movi a2, 1
- abi_return
- endfunc
-
-# endif /*split*/
-
-#elif XCHAL_HAVE_MIMIC_CACHEATTR || XCHAL_HAVE_XLT_CACHEATTR
-
-# if defined(__SPLIT__icache_is_enabled) || \
- defined(__SPLIT__icache_is_enabled_nw)
-
-DECLFUNC(xthal_icache_is_enabled)
- abi_entry
- icacheattr_is_enabled 2f
- movi a2, 0
- abi_return
-2: movi a2, 1
- abi_return
- endfunc
-
-# endif
-
-# if defined(__SPLIT__dcache_is_enabled) || \
- defined(__SPLIT__dcache_is_enabled_nw)
-
-DECLFUNC(xthal_dcache_is_enabled)
- abi_entry
- dcacheattr_is_enabled 2f
- movi a2, 0
- abi_return
-2: movi a2, 1
- abi_return
- endfunc
-
-# endif /*split*/
-
-#else
-
-// These functions aren't applicable to arbitrary MMU configurations.
-// Assume caches are enabled in this case (!).
-
-# if defined(__SPLIT__idcache_is_enabled) || \
- defined(__SPLIT__idcache_is_enabled_nw)
-
-DECLFUNC(xthal_icache_is_enabled)
-DECLFUNC(xthal_dcache_is_enabled)
- abi_entry
- movi a2, 1
- abi_return
- endfunc
-# endif /*split*/
-
-#endif
-
-
-
-//----------------------------------------------------------------------
-// invalidate the icache
-//----------------------------------------------------------------------
-
-#if defined(__SPLIT__icache_all_invalidate) || \
- defined(__SPLIT__icache_all_invalidate_nw)
-
-// void xthal_icache_all_invalidate(void);
-
-DECLFUNC(xthal_icache_all_invalidate)
- abi_entry
- icache_invalidate_all a2, a3
- isync_return_nop
- abi_return
- endfunc
-
-//----------------------------------------------------------------------
-// invalidate the dcache
-//----------------------------------------------------------------------
-
-#endif
-
-#if defined(__SPLIT__dcache_all_invalidate) || \
- defined(__SPLIT__dcache_all_invalidate_nw)
-
-// void xthal_dcache_all_invalidate(void);
-
-DECLFUNC(xthal_dcache_all_invalidate)
- abi_entry
- dcache_invalidate_all a2, a3
- abi_return
- endfunc
-
-//----------------------------------------------------------------------
-// write dcache dirty data
-//----------------------------------------------------------------------
-
-#endif
-
-#if defined(__SPLIT__dcache_all_writeback) || \
- defined(__SPLIT__dcache_all_writeback_nw)
-
-// void xthal_dcache_all_writeback(void);
-
-DECLFUNC(xthal_dcache_all_writeback)
- abi_entry
- dcache_writeback_all a2, a3, a4
- abi_return
- endfunc
-
-//----------------------------------------------------------------------
-// write dcache dirty data and invalidate
-//----------------------------------------------------------------------
-
-#endif
-
-#if defined(__SPLIT__dcache_all_writeback_inv) || \
- defined(__SPLIT__dcache_all_writeback_inv_nw)
-
-// void xthal_dcache_all_writeback_inv(void);
-
-DECLFUNC(xthal_dcache_all_writeback_inv)
- abi_entry
- dcache_writeback_inv_all a2, a3, a4
- abi_return
- endfunc
-
-//----------------------------------------------------------------------
-// unlock instructions from icache
-//----------------------------------------------------------------------
-
-#endif
-
-#if defined(__SPLIT__icache_all_unlock) || \
- defined(__SPLIT__icache_all_unlock_nw)
-
-// void xthal_icache_all_unlock(void);
-
-DECLFUNC(xthal_icache_all_unlock)
- abi_entry
- icache_unlock_all a2, a3
- abi_return
- endfunc
-
-//----------------------------------------------------------------------
-// unlock data from dcache
-//----------------------------------------------------------------------
-
-#endif
-
-#if defined(__SPLIT__dcache_all_unlock) || \
- defined(__SPLIT__dcache_all_unlock_nw)
-
-// void xthal_dcache_all_unlock(void);
-
-DECLFUNC(xthal_dcache_all_unlock)
- abi_entry
- dcache_unlock_all a2, a3
- abi_return
- endfunc
-
-//----------------------------------------------------------------------
-// invalidate the address range in the icache
-//----------------------------------------------------------------------
-
-#endif
-
-#if defined(__SPLIT__icache_region_invalidate) || \
- defined(__SPLIT__icache_region_invalidate_nw)
-
-// void xthal_icache_region_invalidate( void *addr, unsigned size );
-
-DECLFUNC(xthal_icache_region_invalidate)
- abi_entry
- icache_invalidate_region a2, a3, a4
- isync_return_nop
- abi_return
- endfunc
-
-#endif
-
-#if defined(__SPLIT__icache_hugerange_invalidate)
-
-// void xthal_icache_hugerange_invalidate( void *addr, unsigned size );
-icache_hugefunc invalidate, ihi
-
-#endif
-
-#if defined(__SPLIT__icache_hugerange_unlock)
-
-# if XCHAL_ICACHE_LINE_LOCKABLE
-// void xthal_icache_hugerange_unlock( void *addr, unsigned size );
-icache_hugefunc unlock, ihu
-# endif
-
-#endif
-
-#if defined(__SPLIT__dcache_hugerange_invalidate)
-
-// void xthal_dcache_hugerange_invalidate( void *addr, unsigned size );
-dcache_hugefunc invalidate, dhi
-
-#endif
-
-#if defined(__SPLIT__dcache_hugerange_unlock)
-
-# if XCHAL_DCACHE_LINE_LOCKABLE
-// void xthal_dcache_hugerange_unlock( void *addr, unsigned size );
-dcache_hugefunc unlock, dhu
-# endif
-
-#endif
-
-#if defined(__SPLIT__dcache_hugerange_writeback)
-
-// void xthal_dcache_hugerange_writeback( void *addr, unsigned size );
-dcache_hugefunc writeback, dhwb
-
-#endif
-
-#if defined(__SPLIT__dcache_hugerange_writeback_inv)
-
-// void xthal_dcache_hugerange_writeback_inv( void *addr, unsigned size );
-dcache_hugefunc writeback_inv, dhwbi
-
-
-
-//----------------------------------------------------------------------
-// invalidate the address range in the dcache
-//----------------------------------------------------------------------
-
-#endif
-
-#if defined(__SPLIT__dcache_region_invalidate) || \
- defined(__SPLIT__dcache_region_invalidate_nw)
-
-// void xthal_dcache_region_invalidate( void *addr, unsigned size );
-
-DECLFUNC(xthal_dcache_region_invalidate)
- abi_entry
- dcache_invalidate_region a2, a3, a4
- abi_return
- endfunc
-
-//----------------------------------------------------------------------
-// write dcache region dirty data
-//----------------------------------------------------------------------
-
-#endif
-
-#if defined(__SPLIT__dcache_region_writeback) || \
- defined(__SPLIT__dcache_region_writeback_nw)
-
-// void xthal_dcache_region_writeback( void *addr, unsigned size );
-
-DECLFUNC(xthal_dcache_region_writeback)
- abi_entry
- dcache_writeback_region a2, a3, a4, a5
- abi_return
- endfunc
-
-//----------------------------------------------------------------------
-// write dcache region dirty data and invalidate
-//----------------------------------------------------------------------
-
-#endif
-
-#if defined(__SPLIT__dcache_region_writeback_inv) || \
- defined(__SPLIT__dcache_region_writeback_inv_nw)
-
-// void xthal_dcache_region_writeback_inv( void *addr, unsigned size );
-
-DECLFUNC(xthal_dcache_region_writeback_inv)
- abi_entry
- dcache_writeback_inv_region a2, a3, a4, a5
- abi_return
- endfunc
-
-//----------------------------------------------------------------------
-// lock instructions in icache region
-//----------------------------------------------------------------------
-
-#endif
-
-#if defined(__SPLIT__icache_region_lock) || \
- defined(__SPLIT__icache_region_lock_nw)
-
-// void xthal_icache_region_lock(void);
-
-DECLFUNC(xthal_icache_region_lock)
- abi_entry
- icache_lock_region a2, a3, a4
- abi_return
- endfunc
-
-//----------------------------------------------------------------------
-// lock data in dcache region
-//----------------------------------------------------------------------
-
-#endif
-
-#if defined(__SPLIT__dcache_region_lock) || \
- defined(__SPLIT__dcache_region_lock_nw)
-
-// void xthal_dcache_region_lock(void);
-
-DECLFUNC(xthal_dcache_region_lock)
- abi_entry
- dcache_lock_region a2, a3, a4
- abi_return
- endfunc
-
-//----------------------------------------------------------------------
-// unlock instructions from icache region
-//----------------------------------------------------------------------
-
-#endif
-
-#if defined(__SPLIT__icache_region_unlock) || \
- defined(__SPLIT__icache_region_unlock_nw)
-
-// void xthal_icache_region_unlock(void);
-
-DECLFUNC(xthal_icache_region_unlock)
- abi_entry
- icache_unlock_region a2, a3, a4
- abi_return
- endfunc
-
-//----------------------------------------------------------------------
-// unlock data from dcache region
-//----------------------------------------------------------------------
-
-#endif
-
-#if defined(__SPLIT__dcache_region_unlock) || \
- defined(__SPLIT__dcache_region_unlock_nw)
-
-// void xthal_dcache_region_unlock(void);
-
-DECLFUNC(xthal_dcache_region_unlock)
- abi_entry
- dcache_unlock_region a2, a3, a4
- abi_return
- endfunc
-
-
-//----------------------------------------------------------------------
-// invalidate single icache line
-//----------------------------------------------------------------------
-
-#endif
-
-#if defined(__SPLIT__icache_line_invalidate) || \
- defined(__SPLIT__icache_line_invalidate_nw)
-
-// void xthal_icache_line_invalidate(void *addr);
-
-DECLFUNC(xthal_icache_line_invalidate)
- abi_entry
- icache_invalidate_line a2, 0
- isync_return_nop
- abi_return
- endfunc
-
-
-//----------------------------------------------------------------------
-// invalidate single dcache line
-//----------------------------------------------------------------------
-
-#endif
-
-#if defined(__SPLIT__dcache_line_invalidate) || \
- defined(__SPLIT__dcache_line_invalidate_nw)
-
-// void xthal_dcache_line_invalidate(void *addr);
-
-DECLFUNC(xthal_dcache_line_invalidate)
- abi_entry
- dcache_invalidate_line a2, 0
- abi_return
- endfunc
-
-//----------------------------------------------------------------------
-// write single dcache line dirty data
-//----------------------------------------------------------------------
-
-#endif
-
-#if defined(__SPLIT__dcache_line_writeback) || \
- defined(__SPLIT__dcache_line_writeback_nw)
-
-// void xthal_dcache_line_writeback(void *addr);
-
-DECLFUNC(xthal_dcache_line_writeback)
- abi_entry
- dcache_writeback_line a2, 0
- abi_return
- endfunc
-
-//----------------------------------------------------------------------
-// write single dcache line dirty data and invalidate
-//----------------------------------------------------------------------
-
-#endif
-
-#if defined(__SPLIT__dcache_line_writeback_inv) || \
- defined(__SPLIT__dcache_line_writeback_inv_nw)
-
-// void xthal_dcache_line_writeback_inv(void *addr);
-
-DECLFUNC(xthal_dcache_line_writeback_inv)
- abi_entry
- dcache_writeback_inv_line a2, 0
- abi_return
- endfunc
-
-//----------------------------------------------------------------------
-// lock instructions in icache line
-//----------------------------------------------------------------------
-
-#endif
-
-#if defined(__SPLIT__icache_line_lock) || \
- defined(__SPLIT__icache_line_lock_nw)
-
-// void xthal_icache_line_lock(void);
-
-DECLFUNC(xthal_icache_line_lock)
- abi_entry
- icache_lock_line a2, 0
- abi_return
- endfunc
-
-//----------------------------------------------------------------------
-// lock data in dcache line
-//----------------------------------------------------------------------
-
-#endif
-
-#if defined(__SPLIT__dcache_line_lock) || \
- defined(__SPLIT__dcache_line_lock_nw)
-
-// void xthal_dcache_line_lock(void);
-
-DECLFUNC(xthal_dcache_line_lock)
- abi_entry
- dcache_lock_line a2, 0
- abi_return
- endfunc
-
-//----------------------------------------------------------------------
-// unlock instructions from icache line
-//----------------------------------------------------------------------
-
-#endif
-
-#if defined(__SPLIT__icache_line_unlock) || \
- defined(__SPLIT__icache_line_unlock_nw)
-
-// void xthal_icache_line_unlock(void);
-
-DECLFUNC(xthal_icache_line_unlock)
- abi_entry
- icache_unlock_line a2, 0
- abi_return
- endfunc
-
-//----------------------------------------------------------------------
-// unlock data from dcache line
-//----------------------------------------------------------------------
-
-#endif
-
-#if defined(__SPLIT__dcache_line_unlock) || \
- defined(__SPLIT__dcache_line_unlock_nw)
-
-// void xthal_dcache_line_unlock(void);
-
-DECLFUNC(xthal_dcache_line_unlock)
- abi_entry
- dcache_unlock_line a2, 0
- abi_return
- endfunc
-
-//----------------------------------------------------------------------
-// sync icache and memory (???)
-//----------------------------------------------------------------------
-
-#endif
-
-#if defined(__SPLIT__icache_sync) || \
- defined(__SPLIT__icache_sync_nw)
-
-// void xthal_icache_sync(void);
-
-DECLFUNC(xthal_icache_sync)
- abi_entry
- icache_sync a2
- isync_return_nop
- abi_return
- endfunc
-
-//----------------------------------------------------------------------
-// sync dcache and memory (???)
-//----------------------------------------------------------------------
-
-#endif
-
-#if defined(__SPLIT__dcache_sync) || \
- defined(__SPLIT__dcache_sync_nw)
-
-// void xthal_dcache_sync(void);
-
-DECLFUNC(xthal_dcache_sync)
- abi_entry
- dcache_sync a2
- abi_return
- endfunc
-
-//----------------------------------------------------------------------
-// Get/Set icache number of ways enabled
-//----------------------------------------------------------------------
-
-#endif
-
-#if defined (__SPLIT__icache_get_ways) || \
- defined (__SPLIT__icache_get_ways_nw)
-
-// unsigned int xthal_icache_get_ways(void);
-
-DECLFUNC(xthal_icache_get_ways)
- abi_entry
- icache_get_ways a2
- abi_return
- endfunc
-
-#endif
-
-#if defined (__SPLIT__icache_set_ways) || \
- defined(__SPLIT__icache_set_ways_nw)
-
-/// void xthal_icache_set_ways(unsigned int ways);
-
-DECLFUNC(xthal_icache_set_ways)
- abi_entry
- icache_set_ways a2 a3 a4
- abi_return
- endfunc
-
-//----------------------------------------------------------------------
-// Get/Set dcache number of ways enabled
-//----------------------------------------------------------------------
-
-#endif
-
-#if defined (__SPLIT__dcache_get_ways) || \
- defined (__SPLIT__dcache_get_ways_nw)
-
-// unsigned int xthal_dcache_get_ways(void);
-
-DECLFUNC(xthal_dcache_get_ways)
- abi_entry
- dcache_get_ways a2
- abi_return
- endfunc
-
-#endif
-
-#if defined (__SPLIT__dcache_set_ways) || \
- defined (__SPLIT__dcache_set_ways_nw)
-
-// void xthal_dcache_set_ways(unsigned int ways);
-
-DECLFUNC(xthal_dcache_set_ways)
- abi_entry
- dcache_set_ways a2 a3 a4
- abi_return
- endfunc
-
-//----------------------------------------------------------------------
-// opt into and out of coherence
-//----------------------------------------------------------------------
-
-#endif
-
-#if defined(__SPLIT__cache_coherence_on) || \
- defined(__SPLIT__cache_coherence_on_nw)
-
-// The opt-in routine assumes cache was initialized at reset,
-// so it's equivalent to the low-level coherence_on routine.
-
-// void xthal_cache_coherence_optin(void)
-// void xthal_cache_coherence_on(void)
-
-DECLFUNC(xthal_cache_coherence_optin)
-DECLFUNC(xthal_cache_coherence_on)
- abi_entry
- cache_coherence_on a2, a3
- abi_return
- endfunc
-
-#endif
-
-#if defined(__SPLIT__cache_coherence_off) || \
- defined(__SPLIT__cache_coherence_off_nw)
-
-// The coherence_off routines should not normally be called directly.
-// Use the xthal_cache_coherence_optout() C routine instead
-// (which first empties the cache).
-
-// void xthal_cache_coherence_off
-
-DECLFUNC(xthal_cache_coherence_off)
- abi_entry
- cache_coherence_off a2, a3
- abi_return
- endfunc
-
-
-//----------------------------------------------------------------------
-// Control cache prefetch
-//----------------------------------------------------------------------
-
-#endif
-
-#if defined(__SPLIT__set_cache_prefetch_long) || \
- defined(__SPLIT__set_cache_prefetch_long_nw)
-
-# if XCHAL_HAVE_BE
-# define aH a2 /* msb word = prefctl mask */
-# define aL a3 /* lsb word = prefctl value */
-# else
-# define aH a3 /* msb word = prefctl mask */
-# define aL a2 /* lsb word = prefctl value */
-# endif
-
-// Set cache prefetch state (-1=enable, 0=disable, and see XTHAL_*PREFETCH_*),
-// and return previous one.
-//
-// int xthal_set_cache_prefetch_long( unsigned long long );
-//
-DECLFUNC(xthal_set_cache_prefetch_long)
- abi_entry
-# if XCHAL_HAVE_PREFETCH
- movi a5, XCHAL_CACHE_PREFCTL_DEFAULT
- addi a4, aL, 1 // does prefctl value aL == -1 ?
- moveqz aL, a5, a4 // if yes (XTHAL_PREFETCH_ENABLE), set it to default
- movgez a2, aL, aL // if the high bit is not set, then we want to transfer the contents of aL to prefctl
- // so we move it to a2
- bgez aL, 1f // high bit set indicates masked update
- ssai 16 // 16-bit right shifts
- src a5, aL, aH // get 16-bit-swapped 32-bit value
- src a5, a5, a5 // get 32-bit value (rotate by 16)
- rsr.prefctl a4
- src a3, aH, aL // get 32-bit mask
- or a4, a4, a3 // set masked bits
- xor a4, a4, a3 // clear masked bits
- and a5, a5, a3 // only use masked bits
- or a2, a4, a5 // combine masked bits
-1:
-# if XCHAL_HW_MIN_VERSION <= XTENSA_HWVERSION_RC_2010_1 /* for erratum #325 */
- j 1f ; .align 8 ; 1: xsr.prefctl a2 ; isync // ensure XSR.PREFCTL;ISYNC wholly within an icache line
-# else
- xsr.prefctl a2
-# endif
-# else
- movi a2, 0
-# endif
- abi_return
- endfunc
-
-//----------------------------------------------------------------------
-
-#endif
-
-#if defined(__SPLIT__set_cache_prefetch) || \
- defined(__SPLIT__set_cache_prefetch_nw)
-
-// FOR BACKWARD COMPATIBILITY WITH PRE-RF RELEASE OBJECT CODE ONLY.
-// Set cache prefetch state (-1=enable, 0=disable, and see the
-// definitions of XTHAL_*PREFETCH_* with only the lower 32 bits set),
-// and return previous one.
-// int xthal_set_cache_prefetch( int )
-//
-DECLFUNC(xthal_set_cache_prefetch)
- abi_entry
-# if XCHAL_HAVE_PREFETCH
- movi a3, XCHAL_CACHE_PREFCTL_DEFAULT
- addi a4, a2, 1 // does a2 == -1 ?
- moveqz a2, a3, a4 // if yes (XTHAL_PREFETCH_ENABLE), set it to default
- bbci.l a2, 31, 1f // high bit set indicates masked update
- rsr.prefctl a4
- extui a5, a2, 16, 15
- or a4, a4, a5 // set masked bits
- xor a4, a4, a5 // clear masked bits
- and a2, a2, a5 // only use masked bits
- or a2, a4, a2 // combine masked bits
-1:
-# if XCHAL_HW_MIN_VERSION <= XTENSA_HWVERSION_RC_2010_1 /* for erratum #325 */
- j 1f ; .align 8 ; 1: xsr.prefctl a2 ; isync // ensure XSR.PREFCTL;ISYNC wholly within an icache line
-# else
- xsr.prefctl a2
-# endif
-# else
- movi a2, 0
-# endif
- abi_return
- endfunc
-
-//----------------------------------------------------------------------
-
-#endif
-
-#if defined(__SPLIT__get_cache_prefetch) ||\
- defined(__SPLIT__get_cache_prefetch_nw)
-
-// Return current cache prefetch state.
-// int xthal_get_cache_prefetch( void )
-DECLFUNC(xthal_get_cache_prefetch)
- abi_entry
-# if XCHAL_HAVE_PREFETCH
- rsr.prefctl a2
-# else
- movi a2, 0
-# endif
- abi_return
- endfunc
-
-//----------------------------------------------------------------------
-// Misc configuration info
-//----------------------------------------------------------------------
-#endif
-
-// Eventually these will move to their own file:
-#if defined(__SPLIT__hw_configid0)
- .set xthals_hw_configid0, XCHAL_HW_CONFIGID0
-#endif
-
-#if defined(__SPLIT__hw_configid1)
- .set xthals_hw_configid1, XCHAL_HW_CONFIGID1
-#endif
-
-#if defined(__SPLIT__release_major)
- .set xthals_release_major, XTHAL_RELEASE_MAJOR
-#endif
-
-#if defined(__SPLIT__release_minor)
- .set xthals_release_minor, XTHAL_RELEASE_MINOR
-
-#endif /*split*/
-
- .global xthals_hw_configid0, xthals_hw_configid1
- .global xthals_release_major, xthals_release_minor
-
-//----------------------------------------------------------------------
-
diff --git a/src/arch/xtensa/smp/hal/clock.S b/src/arch/xtensa/smp/hal/clock.S
deleted file mode 100644
index 7ea86d3..0000000
--- a/src/arch/xtensa/smp/hal/clock.S
+++ /dev/null
@@ -1,138 +0,0 @@
-//
-// clock.S - assembly language clock routines
-//
-// $Id: //depot/rel/Foxhill/dot.8/Xtensa/OS/hal/clock.S#1 $
-
-// Copyright (c) 2003-2010 Tensilica Inc.
-//
-// Permission is hereby granted, free of charge, to any person obtaining
-// a copy of this software and associated documentation files (the
-// "Software"), to deal in the Software without restriction, including
-// without limitation the rights to use, copy, modify, merge, publish,
-// distribute, sublicense, and/or sell copies of the Software, and to
-// permit persons to whom the Software is furnished to do so, subject to
-// the following conditions:
-//
-// The above copyright notice and this permission notice shall be included
-// in all copies or substantial portions of the Software.
-//
-// THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
-// EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
-// MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
-// IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY
-// CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
-// TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
-// SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
-
-#include <xtensa/coreasm.h>
-
-
-// A useful looping macro:
-// 'iterate' invokes 'what' (an instruction, pseudo-op or other macro)
-// multiple times, passing it a numbered parameter from 'from' to 'to'
-// inclusively. Does not invoke 'what' at all if from > to.
-// Maximum difference between 'from' and 'to' is 99 minus nesting depth
-// (GNU 'as' doesn't allow nesting deeper than 100).
-//
- .macro iterate from, to, what
- .ifeq ((\to-\from) & ~0xFFF)
- \what \from
- iterate "(\from+1)", \to, \what
- .endif
- .endm // iterate
-
-
-//----------------------------------------------------------------------
-// Read CCOUNT register
-//----------------------------------------------------------------------
-
-// unsigned xthal_get_ccount(void)
-//
- .global xthal_get_ccount
- .type xthal_get_ccount,@function
- .align 4
-xthal_get_ccount:
- abi_entry
-#if XCHAL_HAVE_CCOUNT
- rsr.ccount a2
-/*
- * The following alternative (in absence of CCOUNT) doesn't work well,
- * because ICOUNT is often used for debugging. (And when it isn't,
- * one would have to ensure that ICOUNTLEVEL is high enough and that
- * ICOUNT is incremented to zero in the debug exception handler upon
- * ICOUNT exceptions.)
- *
- * #elif XCHAL_HAVE_DEBUG
- * rsr.icount a2 // no CCOUNT, return ICOUNT if available
- */
-#else
- movi a2, 0 // else no counter at all, just return zero
-#endif
- abi_return
- .size xthal_get_ccount, . - xthal_get_ccount
-
-
-//----------------------------------------------------------------------
-// Access CCOMPAREn registers
-//----------------------------------------------------------------------
-
-// void xthal_set_ccompare(int, unsigned)
-//
- .global xthal_set_ccompare
- .type xthal_set_ccompare,@function
- .align 4
-xthal_set_ccompare:
- abi_entry
-#if XCHAL_NUM_TIMERS > 0
- bnez a2, 1f
- wsr.ccompare0 a3
- rsync
- abi_return
-#endif
-1:
-#if XCHAL_NUM_TIMERS > 1
- bnei a2, 1, 2f
- wsr.ccompare1 a3
- rsync
- abi_return
-#endif
-2:
-#if XCHAL_NUM_TIMERS > 2
- bnei a2, 2, 3f
- wsr.ccompare2 a3
- rsync
-#endif
-3:
- abi_return
- .size xthal_set_ccompare, . - xthal_set_ccompare
-
-
-// unsigned xthal_get_ccompare(int)
-//
- .global xthal_get_ccompare
- .type xthal_get_ccompare,@function
- .align 4
-xthal_get_ccompare:
- abi_entry
-#if XCHAL_NUM_TIMERS > 0
- bnez a2, 1f
- rsr.ccompare0 a2
- abi_return
-#endif
-1:
-#if XCHAL_NUM_TIMERS > 1
- bnei a2, 1, 2f
- rsr.ccompare1 a2
- abi_return
-#endif
-2:
-#if XCHAL_NUM_TIMERS > 2
- bnei a2, 2, 3f
- rsr.ccompare2 a2
- abi_return
-#endif
-3:
- movi a2, 0
- abi_return
- .size xthal_get_ccompare, . - xthal_get_ccompare
-
diff --git a/src/arch/xtensa/smp/hal/coherence.c b/src/arch/xtensa/smp/hal/coherence.c
deleted file mode 100644
index 0665573..0000000
--- a/src/arch/xtensa/smp/hal/coherence.c
+++ /dev/null
@@ -1,59 +0,0 @@
-/* coherence.c - Cache coherence opt-in / opt-out functions */
-
-/* $Id: //depot/rel/Foxhill/dot.8/Xtensa/OS/hal/coherence.c#1 $ */
-
-/*
- * Copyright (c) 2008 Tensilica Inc.
- *
- * Permission is hereby granted, free of charge, to any person obtaining
- * a copy of this software and associated documentation files (the
- * "Software"), to deal in the Software without restriction, including
- * without limitation the rights to use, copy, modify, merge, publish,
- * distribute, sublicense, and/or sell copies of the Software, and to
- * permit persons to whom the Software is furnished to do so, subject to
- * the following conditions:
- *
- * The above copyright notice and this permission notice shall be included
- * in all copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
- * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
- * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
- * IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY
- * CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
- * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
- * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
- */
-
-#include <xtensa/config/core.h>
-
-
-/*
- * Opt-out of cache coherence.
- *
- * Caveat: on a core with full MMU, cache attribute handling done here only
- * works well with the default (reset) TLB mapping of eight 512MB regions.
- * It likely won't work correctly when other page sizes are in use (it may
- * appear to work but be open to race conditions, depending on situation).
- */
-void xthal_cache_coherence_optout( void )
-{
-#if XCHAL_HAVE_EXTERN_REGS && XCHAL_DCACHE_IS_COHERENT
- unsigned ca = xthal_get_cacheattr();
- /* Writeback all dirty entries. Writethru mode avoids new dirty entries. */
- xthal_set_region_attribute(0,0xFFFFFFFF, XCHAL_CA_WRITETHRU, XTHAL_CAFLAG_EXPAND);
- xthal_dcache_all_writeback();
- /* Invalidate all cache entries. Cache-bypass mode avoids new entries. */
- xthal_set_region_attribute(0,0xFFFFFFFF, XCHAL_CA_BYPASS, XTHAL_CAFLAG_EXPAND);
- xthal_dcache_all_writeback_inv();
- /* Wait for everything to settle. */
- asm("memw");
- xthal_dcache_sync();
- xthal_icache_sync();
- /* Opt-out of cache coherency protocol. */
- xthal_cache_coherence_off();
- /* Restore cache attributes, as of entry to this function. */
- xthal_set_cacheattr(ca);
-#endif
-}
-
diff --git a/src/arch/xtensa/smp/hal/debug.c b/src/arch/xtensa/smp/hal/debug.c
deleted file mode 100644
index 9e2b265..0000000
--- a/src/arch/xtensa/smp/hal/debug.c
+++ /dev/null
@@ -1,525 +0,0 @@
-//
-// debug.c - debug related constants and functions
-//
-// $Id: //depot/rel/Foxhill/dot.8/Xtensa/OS/hal/debug.c#1 $
-
-// Copyright (c) 2002 Tensilica Inc.
-//
-// Permission is hereby granted, free of charge, to any person obtaining
-// a copy of this software and associated documentation files (the
-// "Software"), to deal in the Software without restriction, including
-// without limitation the rights to use, copy, modify, merge, publish,
-// distribute, sublicense, and/or sell copies of the Software, and to
-// permit persons to whom the Software is furnished to do so, subject to
-// the following conditions:
-//
-// The above copyright notice and this permission notice shall be included
-// in all copies or substantial portions of the Software.
-//
-// THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
-// EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
-// MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
-// IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY
-// CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
-// TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
-// SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
-
-#include <xtensa/hal.h>
-#include <xtensa/config/core.h>
-
-
-/* 1 if debug option configured, 0 if not: */
-const int Xthal_debug_configured = XCHAL_HAVE_DEBUG;
-
-/* Number of instruction and data break registers: */
-const int Xthal_num_ibreak = XCHAL_NUM_IBREAK;
-const int Xthal_num_dbreak = XCHAL_NUM_DBREAK;
-
-
-#ifdef INCLUDE_DEPRECATED_HAL_DEBUG_CODE
-/* This array is incorrect: */
-const unsigned short Xthal_ill_inst_16[16] =
-{
-#if XCHAL_HAVE_BE
- 0xfd0f, 0xfd1f, 0xfd2f, 0xfd3f,
- 0xfd4f, 0xfd5f, 0xfd6f, 0xfd7f,
- 0xfd8f, 0xfd9f, 0xfdaf, 0xfdbf,
- 0xfdcf, 0xfddf, 0xfdef, 0xfdff
-#else
- 0xf0fd, 0xf1fd, 0xf2fd, 0xf3fd,
- 0xf4fd, 0xf5fd, 0xf6fd, 0xf7fd,
- 0xf8fd, 0xf9fd, 0xfafd, 0xfbfd,
- 0xfcfd, 0xfdfd, 0xfefd, 0xfffd
-#endif
-};
-#endif /* INCLUDE_DEPRECATED_HAL_DEBUG_CODE */
-
-
-#undef XTHAL_24_BIT_BREAK
-#undef XTHAL_16_BIT_BREAK
-#define XTHAL_24_BIT_BREAK 0x80000000
-#define XTHAL_16_BIT_BREAK 0x40000000
-
-
-
-// set software breakpoint and synchronize cache
-unsigned int
-xthal_set_soft_break(void *addr)
-{
- unsigned inst;
- int is24bit = (xthal_disassemble_size( (unsigned char *)addr ) == 3);
- unsigned int ret_val;
-
-#if XCHAL_HAVE_BE
- inst = ((((char *)addr)[0])<<24) +
- ((((char *)addr)[1])<<16) +
- ((((char *)addr)[2])<<8);
-#else
- inst = ((((char *)addr)[0])) +
- ((((char *)addr)[1])<<8) +
- ((((char *)addr)[2])<<16);
-#endif
-#if XCHAL_HAVE_BE
- if (is24bit) {
- ret_val = XTHAL_24_BIT_BREAK & ((inst>>8)&0xffffff);
- ((unsigned char *)addr)[0] = 0x00;
- ((unsigned char *)addr)[1] = 0x04;
- ((unsigned char *)addr)[2] = 0x00;
- } else {
- ret_val = XTHAL_16_BIT_BREAK & ((inst>>16)&0xffff);
- ((unsigned char *)addr)[0] = 0xD2;
- ((unsigned char *)addr)[1] = 0x0f;
- }
-#else
- if (is24bit) {
- ret_val = XTHAL_24_BIT_BREAK & (inst&0xffffff);
- ((unsigned char *)addr)[0] = 0x00;
- ((unsigned char *)addr)[1] = 0x40;
- ((unsigned char *)addr)[2] = 0x00;
- } else {
- ret_val = XTHAL_16_BIT_BREAK & (inst&0xffff);
- ((unsigned char *)addr)[0] = 0x2D;
- ((unsigned char *)addr)[1] = 0xf0;
- }
-#endif
- *((unsigned int *)addr) = inst;
-#if XCHAL_DCACHE_IS_WRITEBACK
- xthal_dcache_region_writeback((void*)addr, 3);
-#endif
-#if XCHAL_ICACHE_SIZE > 0
- xthal_icache_region_invalidate((void*)addr, 3);
-#endif
- return ret_val;
-}
-
-
-// remove software breakpoint and synchronize cache
-void
-xthal_remove_soft_break(void *addr, unsigned int inst)
-{
-#if XCHAL_HAVE_BE
- if (inst&XTHAL_24_BIT_BREAK) {
- ((unsigned char *)addr)[0] = (inst>>16)&0xff;
- ((unsigned char *)addr)[1] = (inst>>8)&0xff;
- ((unsigned char *)addr)[2] = inst&0xff;
- } else {
- ((unsigned char *)addr)[0] = (inst>>8)&0xff;
- ((unsigned char *)addr)[1] = inst&0xff;
- }
-#else
- ((unsigned char *)addr)[0] = inst&0xff;
- ((unsigned char *)addr)[1] = (inst>>8)&0xff;
- if (inst&XTHAL_24_BIT_BREAK)
- ((unsigned char *)addr)[2] = (inst>>16)&0xff;
-#endif
-#if XCHAL_DCACHE_IS_WRITEBACK
- xthal_dcache_region_writeback((void*)addr, 3);
-#endif
-#if XCHAL_ICACHE_SIZE > 0
- xthal_icache_region_invalidate((void*)addr, 3);
-#endif
-}
-
-
-
-
-#ifdef INCLUDE_DEPRECATED_HAL_DEBUG_CODE
-
-// return instruction type
-unsigned int
-xthal_inst_type(void *addr)
-{
- unsigned int inst_type = 0;
- unsigned inst;
-// unsigned int inst = *((unsigned int *)addr);
- unsigned char op0, op1, op2;
- unsigned char i, m, n, r, s, t, z;
-
-#if XCHAL_HAVE_BE
- inst = ((((char *)addr)[0])<<24) +
- ((((char *)addr)[1])<<16) +
- ((((char *)addr)[2])<<8);
- op0 = inst>>28;
- op1 = (inst>>12)&0xf;
- op2 = (inst>>16)&0xf;
- i = (inst>>27)&0x1;
- z = (inst>>26)&0x1;
- m = (inst>>24)&0x3;
- n = (inst>>26)&0x3;
- r = (inst>>16)&0xf;
- s = (inst>>20)&0xf;
- t = (inst>>24)&0xf;
-#else
- inst = ((((char *)addr)[0])) +
- ((((char *)addr)[1])<<8) +
- ((((char *)addr)[2])<<16);
- op0 = inst&0xf;
- op1 = (inst&0xf0000)>>16;
- op2 = (inst&0xf00000)>>20;
- i = (inst&0x80)>>7;
- z = (inst&0x40)>>6;
- m = (inst&0xc0)>>6;
- n = (inst&0x30)>>4;
- r = (inst&0xf000)>>12;
- s = (inst&0xf00)>>8;
- t = (inst&0xf0)>4;
-#endif
- switch (op0) {
- case 0x0:
- inst_type |= XTHAL_24_BIT_INST;
- if ((op1==0)&&(op2==0))
- switch (r) {
- case 0:
- if (m==0x2) {
- if (!(n&0x2)) // RET, RETW
- inst_type |= XTHAL_RET_INST;
- else if (n==0x2) // JX
- inst_type |= (XTHAL_JUMP_INST|XTHAL_DEST_REG_INST);
- inst_type |= (s<<28);
- } else if (m==3) // CALLX
- inst_type |= (XTHAL_JUMP_INST|XTHAL_DEST_REG_INST);
- inst_type |= (s<<28);
- break;
- case 0x3:
- if (t==0)
- switch (s) {
- case 0x0: // RFE
- inst_type |= XTHAL_RFE_INST;
- break;
- case 0x1: // RFUE
- inst_type |= XTHAL_RFUE_INST;
- break;
- case 0x4: // RFW
- case 0x5:
- inst_type |= XTHAL_RFW_INST;
- break;
- }
- else if (t==1) // RFI
- inst_type |= XTHAL_RFI_INST;
- break;
- case 0x4: // BREAK
- inst_type |= XTHAL_BREAK_INST;
- break;
- case 0x5: // SYSCALL
- inst_type |= XTHAL_SYSCALL_INST;
- break;
- }
- break;
- case 0x5: // CALL
- inst_type |= XTHAL_24_BIT_INST;
- inst_type |= (XTHAL_JUMP_INST|XTHAL_DEST_REL_INST);
- break;
- case 0x6: // B
- inst_type |= XTHAL_24_BIT_INST;
- if (n==0) // J
- inst_type |= (XTHAL_JUMP_INST|XTHAL_DEST_REL_INST);
- else if ((n==0x1)||(n==0x2))
- inst_type |= (XTHAL_BRANCH_INST|XTHAL_DEST_REL_INST);
- else {
- if (m&0x2)
- inst_type |= (XTHAL_BRANCH_INST|XTHAL_DEST_REL_INST);
- else if ((m==0x1)&&((r==0x0)||(r==0x1)))
- inst_type |= (XTHAL_BRANCH_INST|XTHAL_DEST_REL_INST);
- }
- break;
- case 0x7: // B
- inst_type |= XTHAL_24_BIT_INST;
- inst_type |= (XTHAL_BRANCH_INST|XTHAL_DEST_REL_INST);
- break;
-#if XCHAL_HAVE_DENSITY
- case 0x8: // L32I.N
- case 0x9: // S32I.N
- case 0xA: // ADD.N
- case 0xb: // ADDI.N
- inst_type |= XTHAL_16_BIT_INST;
- break;
- case 0xc:
- inst_type |= XTHAL_16_BIT_INST; // MOVI.N BEQZ.N, BNEZ.N
- if (i)
- inst_type |= (XTHAL_BRANCH_INST|XTHAL_DEST_REL_INST);
- break;
- case 0xd: // MOV.N NOP.N
- inst_type |= XTHAL_16_BIT_INST;
- if (r==0xf)
- switch(t) {
- case 0x0:
- case 0x1:
- inst_type |= XTHAL_RET_INST; // RET.N, RETW.N
- break;
- case 0x2:
- inst_type |= XTHAL_BREAK_INST; // BREAK.N
- break;
- }
- break;
-#endif /* XCHAL_HAVE_DENSITY */
- default:
- inst_type |= XTHAL_24_BIT_INST;
- }
- return inst_type;
-}
-
-// returns branch address
-unsigned int
-xthal_branch_addr(void *addr)
-{
- unsigned int b_addr = (unsigned int) addr;
- unsigned inst;
-// unsigned int inst = *((unsigned int *)addr);
- int offset;
- unsigned int inst_type = xthal_inst_type(addr);
- unsigned int inst_type_mask;
-#if XCHAL_HAVE_BE
- inst = ((((char *)addr)[0])<<24) +
- ((((char *)addr)[1])<<16) +
- ((((char *)addr)[2])<<8);
-#else
- inst = ((((char *)addr)[0])) +
- ((((char *)addr)[1])<<8) +
- ((((char *)addr)[2])<<16);
-#endif
-#if XCHAL_HAVE_DENSITY
- inst_type_mask = XTHAL_16_BIT_INST|XTHAL_BRANCH_INST|XTHAL_DEST_REL_INST;
- if ((inst_type&inst_type_mask)==inst_type_mask) {
-# if XCHAL_HAVE_BE
- b_addr += (4+((inst&0x3000000)>>20)+((inst&0xf0000)>>16));
-# else
- b_addr += (4+(inst&0x30)+((inst&0xf000)>>12));
-# endif
- }
-#endif /* XCHAL_HAVE_DENSITY */
- inst_type_mask = XTHAL_24_BIT_INST|XTHAL_BRANCH_INST|XTHAL_DEST_REL_INST;
- if ((inst_type&inst_type_mask)==inst_type_mask) {
-#if XCHAL_HAVE_BE
- if ((inst&0xf0000000)==0x70000000)
- offset = ((int)(inst<<16))>>24;
- else if ((inst&0xf2000000)==0x62000000)
- offset = ((int)(inst<<16))>>24;
- else
- offset = ((int)(inst<<12))>>20;
-#else
- if ((inst&0xf)==0x7)
- offset = ((int)(inst<<8))>>24;
- else if ((inst&0x2f)==0x26)
- offset = ((int)(inst<<8))>>24;
- else
- offset = ((int)(inst<<8))>>20;
-#endif
- b_addr += 4 + offset;
- }
- inst_type_mask = XTHAL_24_BIT_INST|XTHAL_JUMP_INST|XTHAL_DEST_REL_INST;
- if ((inst_type&inst_type_mask)==inst_type_mask) {
-#if XCHAL_HAVE_BE
- if ((inst&0xfc000000)==0x60000000)
- offset = ((int)(inst<<6))>>14;
- else
- {
- b_addr &= 0xfffffffc;
- offset = ((int)(inst<<6))>>12;
- }
-#else
- if ((inst&0x3f)==0x6)
- offset = ((int)(inst<<8))>>14;
- else
- {
- b_addr &= 0xfffffffc;
- offset = ((int)(inst<<8))>>12;
- }
-#endif
- b_addr += 4 + offset;
- }
- return b_addr;
-}
-
-// return pc of next instruction for a given state
-unsigned int xthal_get_npc(XTHAL_STATE *user_state)
-{
- unsigned inst_type;
- unsigned npc;
- inst_type = xthal_inst_type((void *)user_state->pc);
- if (inst_type & XTHAL_24_BIT_INST)
- npc = user_state->pc + 3;
- else
- npc = user_state->pc + 2;
- if (inst_type & XTHAL_RFW_INST) {
- /* Can not debug level 1 interrupts */
- // xt_panic();
- } else if (inst_type & XTHAL_RFUE_INST) {
- /* Can not debug level 1 interrupts */
- // xt_panic();
- } else if (inst_type & XTHAL_RFI_INST) {
- /* Can not debug level 1 interrupts */
- // xt_panic();
- } else if (inst_type & XTHAL_RFE_INST) {
- /* Can not debug level 1 interrupts */
- // xt_panic();
- } else if (inst_type & XTHAL_RET_INST) {
- npc = (user_state->pc&0xc0000000)+(user_state->ar[0]&0x3fffffff);
- } else if (inst_type & XTHAL_BREAK_INST) {
- /* Can not debug break */
- // xt_panic();
- } else if (inst_type & XTHAL_SYSCALL_INST) {
- /* Can not debug exceptions */
- // xt_panic();
- } else if (inst_type & XTHAL_LOOP_END) {
- // xt_panic();
- } else if (inst_type & XTHAL_JUMP_INST) {
- if (inst_type & XTHAL_DEST_REG_INST) {
- return user_state->ar[inst_type>>28];
- } else if (inst_type & XTHAL_DEST_REL_INST) {
- return xthal_branch_addr((void *)user_state->pc);
- }
- } else if (inst_type & XTHAL_BRANCH_INST) {
- int branch_taken = 0;
- unsigned short inst;
- unsigned char op0, t, s, r, m, n;
- memcpy(&inst, (void *)user_state->pc, 2);
-#if XCHAL_HAVE_BE
- op0 = (inst&0xf000)>>12;
- t = (inst&0x0f00)>>8;
- s = (inst&0x00f0)>>4;
- r = (inst&0x000f);
- m = t&3;
- n = t>>2;
-#else
- op0 = (inst&0x000f);
- t = (inst&0x00f0)>>4;
- s = (inst&0x0f00)>>8;
- r = (inst&0xf000)>>12;
- m = t>>2;
- n = t&3;
-#endif
- if (inst_type &XTHAL_16_BIT_INST) {
-#if XCHAL_HAVE_BE
- if (inst&0x400) /* BNEZ.N */
- branch_taken = (user_state->ar[(inst>>4)&0xf]!=0);
- else /* BEQZ.N */
- branch_taken = (user_state->ar[(inst>>4)&0xf]==0);
-#else
- if (inst&0x40) /* BNEZ.N */
- branch_taken = (user_state->ar[(inst>>8)&0xf]!=0);
- else /* BEQZ.N */
- branch_taken = (user_state->ar[(inst>>8)&0xf]==0);
-#endif
- }
- if (op0==0x6) {
- if (n==1) {
- if (m==0) { /* BEQZ */
- branch_taken = (user_state->ar[s]==0);
- } else if (m==1) { /* BNEZ */
- branch_taken = (user_state->ar[s]!=0);
- } else if (m==2) { /* BLTZ */
- branch_taken = (((int)user_state->ar[s])<0);
- } else if (m==3) { /* BGEZ */
- branch_taken = (((int)user_state->ar[s])>=0);
- }
- } else if (n==2) {
- int b4const[16] =
- { -1, 1, 2, 3, 4, 5, 6, 7,
- 8, 10, 12, 16, 32, 62, 128, 256 };
- if (m==0) { /* BEQI */
- branch_taken = (user_state->ar[s]==b4const[r]);
- } else if (m==1) { /* BNEI */
- branch_taken = (user_state->ar[s]!=b4const[r]);
- } else if (m==2) { /* BLTI */
- branch_taken = (((int)user_state->ar[s])<b4const[r]);
- } else if (m==3) { /* BGEI */
- branch_taken = (((int)user_state->ar[s])>=b4const[r]);
- }
- } else if (n==3) {
- int b4constu[16] =
- { 32768, 65536, 2, 3, 4, 5, 6, 7,
- 8, 10, 12, 16, 32, 62, 128, 256 };
- if (m==2) { /* BLTUI */
- branch_taken = (user_state->ar[s]<b4constu[r]);
- } else if (m==3) { /* BGEUI */
- branch_taken = (user_state->ar[s]>=b4constu[r]);
- }
- }
- } else if (op0==0x7) {
- if (r==0) { /* BNONE */
- branch_taken = ((user_state->ar[s]&user_state->ar[t])==0);
- } else if (r==1) { /* BEQ */
- branch_taken = (user_state->ar[s]==user_state->ar[t]);
- } else if (r==2) { /* BLT */
- branch_taken = ((int)user_state->ar[s]<(int)user_state->ar[t]);
- } else if (r==3) { /* BLTU */
- branch_taken = (user_state->ar[s]<user_state->ar[t]);
- } else if (r==4) { /* BALL */
- branch_taken = (((~user_state->ar[s])&user_state->ar[t])==0);
- } else if (r==5) { /* BBC */
-#if XCHAL_HAVE_BE
- branch_taken = ((user_state->ar[s]&(0x80000000>>user_state->ar[t]))==0);
- } else if (r==6) { /* BBCI */
- branch_taken = ((user_state->ar[s]&(0x80000000>>t))==0);
- } else if (r==7) { /* BBCI */
- branch_taken = ((user_state->ar[s]&(0x80000000>>(t+16)))==0);
-#else
- branch_taken = ((user_state->ar[s]&(1<<user_state->ar[t]))==0);
- } else if (r==6) { /* BBCI */
- branch_taken = ((user_state->ar[s]&(1<<t))==0);
- } else if (r==7) { /* BBCI */
- branch_taken = ((user_state->ar[s]&(1<<(t+16)))==0);
-#endif
- } else if (r==8) { /* BANY */
- branch_taken = ((user_state->ar[s]&user_state->ar[t])!=0);
- } else if (r==9) { /* BNE */
- branch_taken = (user_state->ar[s]!=user_state->ar[t]);
- } else if (r==10) { /* BGE */
- branch_taken = ((int)user_state->ar[s]>=(int)user_state->ar[t]);
- } else if (r==11) { /* BGEU */
- branch_taken = (user_state->ar[s]>=user_state->ar[t]);
- } else if (r==12) { /* BNALL */
- branch_taken = (((~user_state->ar[s])&user_state->ar[t])!=0);
- } else if (r==13) { /* BBS */
-#if XCHAL_HAVE_BE
- branch_taken = ((user_state->ar[s]&(0x80000000>>user_state->ar[t]))!=0);
- } else if (r==14) { /* BBSI */
- branch_taken = ((user_state->ar[s]&(0x80000000>>t))!=0);
- } else if (r==15) { /* BBSI */
- branch_taken = ((user_state->ar[s]&(0x80000000>>(t+16)))!=0);
-#else
- branch_taken = ((user_state->ar[s]&(1<<user_state->ar[t]))!=0);
- } else if (r==14) { /* BBSI */
- branch_taken = ((user_state->ar[s]&(1<<t))!=0);
- } else if (r==15) { /* BBSI */
- branch_taken = ((user_state->ar[s]&(1<<(t+16)))!=0);
-#endif
- }
- }
- if (branch_taken) {
- if (inst_type & XTHAL_DEST_REG_INST) {
- return user_state->ar[inst_type>>24];
- } else if (inst_type & XTHAL_DEST_REL_INST) {
- return xthal_branch_addr((void *)user_state->pc);
- }
- }
-#if XCHAL_HAVE_LOOPS
- else if (user_state->lcount && (npc==user_state->lend))
- return user_state->lbeg;
-#endif
- }
- return npc;
-}
-
-#endif /* INCLUDE_DEPRECATED_HAL_DEBUG_CODE */
-
diff --git a/src/arch/xtensa/smp/hal/debug_hndlr.S b/src/arch/xtensa/smp/hal/debug_hndlr.S
deleted file mode 100644
index 172f61c..0000000
--- a/src/arch/xtensa/smp/hal/debug_hndlr.S
+++ /dev/null
@@ -1,146 +0,0 @@
-//
-// debug_hndlr.S -- default Xtensa debug exception handler
-//
-// $Id: //depot/rel/Foxhill/dot.8/Xtensa/OS/hal/debug_hndlr.S#1 $
-
-// Copyright (c) 2003-2010 Tensilica Inc.
-//
-// Permission is hereby granted, free of charge, to any person obtaining
-// a copy of this software and associated documentation files (the
-// "Software"), to deal in the Software without restriction, including
-// without limitation the rights to use, copy, modify, merge, publish,
-// distribute, sublicense, and/or sell copies of the Software, and to
-// permit persons to whom the Software is furnished to do so, subject to
-// the following conditions:
-//
-// The above copyright notice and this permission notice shall be included
-// in all copies or substantial portions of the Software.
-//
-// THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
-// EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
-// MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
-// IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY
-// CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
-// TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
-// SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
-
-#include <xtensa/coreasm.h>
-#include <xtensa/config/system.h>
-
-#if XCHAL_HAVE_DEBUG && XCHAL_HAVE_EXCEPTIONS
-
- /*
- * Default debug exception handler.
- *
- * Note that the debug exception vector must save a3
- * in EXCSAVE+XCHAL_DEBUGLEVEL before jumping here.
- *
- * This handler is used when no debugger is present.
- * The end result of executing this default handler
- * is as if no debug exception had occurred, eg. as if
- * the core was running at PS.INTLEVEL >= DEBUGLEVEL.
- *
- * Because the debug exception vector might get
- * placed in ROM, and be expected to work regardless
- * of what executable image or OS is running in RAM,
- * we're very careful not to use any RAM here.
- * We don't know what RAM we can safely use.
- * This tricky part to accomplishing this feat
- * is to use only *one* register (a3, which was
- * saved in EXCSAVE+XCHAL_DEBUGLEVEL), because we don't
- * have RAM in which to safely store other regs.
- *
- * A real debugger application would normally
- * have some kind of conventions, or special
- * hardware support, to have its own RAM workspace
- * in which to save context and do real work
- * in this handler.
- */
-
-
-#if XSHAL_DEBUG_VECTOR_ISROM
- // Debug exception vector is in ROM, so place the handler
- // in ROM also. Otherwise running different executables
- // with that ROM will not work because the handler would
- // likely not be there or be at the wrong address.
- //
- .section .srom.text, "ax"
-#else
- // Debug exception vector is in RAM, so we can safely
- // place the handler in RAM as well.
- //
- .text
-#endif
-
- .global xthal_debugexc_defhndlr_nw
- .align 4
-xthal_debugexc_defhndlr_nw:
- rsr.debugcause a3 // get cause of debug exception
-
- // Check for possible debug causes, in priority order.
- // We only handle the highest priority condition present.
- // (If there are multiple conditions, the lower priority
- // condition(s) will normally trigger upon return from
- // this exception handler.)
-
- bbci.l a3, DEBUGCAUSE_ICOUNT_SHIFT, 1f // ICOUNT trap?
- movi a3, 0
- wsr.icount a3 // clear ICOUNT
- j 3f
-
-/*
- * Ensure that we have IBREAKs, otherwise the IBREAKENABLE
- * special register is not there:
- */
-#if XCHAL_NUM_IBREAK > 0
-1: bbci.l a3, DEBUGCAUSE_IBREAK_SHIFT, 1f // IBREAK match?
- movi a3, 0
- wsr.ibreakenable a3 // disable IBREAK traps
- j 3f
-#endif
-
-/* Also check for DBREAK registers: */
-#if XCHAL_NUM_DBREAK > 0
-1: bbci.l a3, DEBUGCAUSE_DBREAK_SHIFT, 1f // DBREAK match?
- movi a3, 0
- wsr.dbreakc0 a3 // disable DBREAK register 0
-# if XCHAL_NUM_DBREAK > 1
- wsr.dbreakc1 a3 // disable DBREAK register 1
-# endif
- j 3f
-#endif
-
-1: bbci.l a3, DEBUGCAUSE_BREAK_SHIFT, 1f // BREAK instruction?
- //readsr epc XCHAL_DEBUGLEVEL a3 // get PC pointing to BREAK
- //l8ui a3, a3, 1 // get first 4-bit operand of BREAK (in 2nd byte)
- //extui a3, a3, (XCHAL_HAVE_BE*4), 4 // pos depends on endianness
- //bnei a3, 1, 3f // is it a BREAK 1,x instruction?
- readsr epc XCHAL_DEBUGLEVEL a3 // get PC pointing to BREAK
- addi a3, a3, 3 // skip BREAK instruction
- writesr epc XCHAL_DEBUGLEVEL a3 // update PC
- j 3f
-
-1: bbci.l a3, DEBUGCAUSE_BREAKN_SHIFT, 1f // BREAK.N instruction?
- readsr epc XCHAL_DEBUGLEVEL a3 // get PC pointing to BREAK
- addi a3, a3, 2 // skip BREAK.N instruction
- writesr epc XCHAL_DEBUGLEVEL a3 // update PC
- j 3f
-
-1: bbci.l a3, DEBUGCAUSE_DEBUGINT_SHIFT, 1f // debug interrupt?
- // Nothing to do...
- j 3f
-
-1: // Unknown debug case? ignore
-
-3: readsr excsave XCHAL_DEBUGLEVEL a3 // restore a3
- rfi XCHAL_DEBUGLEVEL // return from debug exception
-
- .size xthal_debugexc_defhndlr_nw, . - xthal_debugexc_defhndlr_nw
-
-
-#if XSHAL_DEBUG_VECTOR_ISROM
- .text // in case this gets included by something else
-#endif
-
-#endif /* XCHAL_HAVE_DEBUG */
-
diff --git a/src/arch/xtensa/smp/hal/disass.c b/src/arch/xtensa/smp/hal/disass.c
deleted file mode 100644
index 5f8d851..0000000
--- a/src/arch/xtensa/smp/hal/disass.c
+++ /dev/null
@@ -1,153 +0,0 @@
-//
-// disass.c - disassembly routines for Xtensa
-//
-// $Id: //depot/rel/Foxhill/dot.8/Xtensa/OS/hal/disass.c#1 $
-
-// Copyright (c) 2004-2013 Tensilica Inc.
-//
-// Permission is hereby granted, free of charge, to any person obtaining
-// a copy of this software and associated documentation files (the
-// "Software"), to deal in the Software without restriction, including
-// without limitation the rights to use, copy, modify, merge, publish,
-// distribute, sublicense, and/or sell copies of the Software, and to
-// permit persons to whom the Software is furnished to do so, subject to
-// the following conditions:
-//
-// The above copyright notice and this permission notice shall be included
-// in all copies or substantial portions of the Software.
-//
-// THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
-// EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
-// MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
-// IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY
-// CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
-// TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
-// SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
-
-#include <xtensa/hal.h>
-#include <xtensa/config/core.h>
-
-#ifdef XCHAL_OP0_FORMAT_LENGTHS
-extern const unsigned char Xthal_op0_format_lengths[16];
-#endif
-extern const unsigned char Xthal_byte0_format_lengths[256];
-
-
-#if defined(__SPLIT__op0_format_lengths)
-
-/* Instruction length in bytes as function of its op0 field (first nibble): */
-#ifdef XCHAL_OP0_FORMAT_LENGTHS
-const unsigned char Xthal_op0_format_lengths[16] = {
- XCHAL_OP0_FORMAT_LENGTHS
-};
-#endif
-
-
-#elif defined(__SPLIT__byte0_format_lengths)
-
-/* Instruction length in bytes as function of its first byte: */
-const unsigned char Xthal_byte0_format_lengths[256] = {
- XCHAL_BYTE0_FORMAT_LENGTHS
-};
-
-
-#elif defined(__SPLIT__disassemble_size)
-
-//
-// Disassembly is currently not supported in xtensa hal.
-//
-
-int xthal_disassemble_size( unsigned char *instr_buf )
-{
-#ifdef XCHAL_OP0_FORMAT_LENGTHS
- /* Extract op0 field of instruction (first nibble used for decoding): */
-# if XCHAL_HAVE_BE
- int op0 = ((*instr_buf >> 4) & 0xF);
-# else
- int op0 = (*instr_buf & 0xF);
-# endif
- /*return (op0 & 8) ? 2 : 3;*/ /* simple case only works consistently on older hardware */
- return Xthal_op0_format_lengths[op0];
-#else
- return Xthal_byte0_format_lengths[*instr_buf];
-#endif
-}
-
-
-#elif defined(__SPLIT__disassemble)
-
-/*
- * Note: we make sure to avoid the use of library functions,
- * to minimize dependencies.
- */
-int xthal_disassemble(
- unsigned char *instr_buffer, /* the address of the instructions */
- void *tgt_address, /* where the instruction is to be */
- char *buffer, /* where the result goes */
- unsigned buflen, /* size of buffer */
- unsigned options /* what to display */
- )
-{
-#define OUTC(c) do{ if( p < endp ) *p = c; p++; }while(0)
- int i, n;
- char *p = buffer, *endp = buffer + buflen - 1;
- /*static char *ret = " decoding not supported";*/
- static const char _hexc[16] = "0123456789ABCDEF";
-
- n = xthal_disassemble_size( instr_buffer );
-
- if( options & XTHAL_DISASM_OPT_ADDR ) {
- unsigned addr = (unsigned)tgt_address;
- for( i = 0; i < 8; i++ ) {
- OUTC( _hexc[(addr >> 28) & 0xF] );
- addr <<= 4;
- }
- }
-
- if( options & XTHAL_DISASM_OPT_OPHEX ) {
- if( p > buffer )
- OUTC( ' ' );
- for( i = 0; i < 3; i++ ) {
- if( i < n ) {
- OUTC( _hexc[(*instr_buffer >> 4) & 0xF] );
- OUTC( _hexc[*instr_buffer++ & 0xF] );
- } else {
- OUTC( ' ' );
- OUTC( ' ' );
- }
- OUTC( ' ' );
- }
- }
-
- if( options & XTHAL_DISASM_OPT_OPCODE ) {
- if( p > buffer )
- OUTC( ' ' );
- OUTC( '?' );
- OUTC( '?' );
- OUTC( '?' );
- OUTC( ' ' );
- OUTC( ' ' );
- OUTC( ' ' );
- OUTC( ' ' );
- }
-
- if( options & XTHAL_DISASM_OPT_PARMS ) {
- if( p > buffer )
- OUTC( ' ' );
- OUTC( '?' );
- OUTC( '?' );
- OUTC( '?' );
- }
-
- if( p < endp )
- *p = 0;
- else if( buflen > 0 )
- *endp = 0;
-
- return p - buffer; /* return length needed, even if longer than buflen */
-}
-
-#undef OUTC
-
-
-#endif /*split*/
diff --git a/src/arch/xtensa/smp/hal/int_asm.S b/src/arch/xtensa/smp/hal/int_asm.S
deleted file mode 100644
index 4ce36da..0000000
--- a/src/arch/xtensa/smp/hal/int_asm.S
+++ /dev/null
@@ -1,643 +0,0 @@
-//
-// int_asm.S - assembly language interrupt utility routines
-//
-// $Id: //depot/rel/Foxhill/dot.8/Xtensa/OS/hal/int_asm.S#1 $
-
-// Copyright (c) 2003-2010 Tensilica Inc.
-//
-// Permission is hereby granted, free of charge, to any person obtaining
-// a copy of this software and associated documentation files (the
-// "Software"), to deal in the Software without restriction, including
-// without limitation the rights to use, copy, modify, merge, publish,
-// distribute, sublicense, and/or sell copies of the Software, and to
-// permit persons to whom the Software is furnished to do so, subject to
-// the following conditions:
-//
-// The above copyright notice and this permission notice shall be included
-// in all copies or substantial portions of the Software.
-//
-// THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
-// EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
-// MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
-// IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY
-// CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
-// TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
-// SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
-
-#include <xtensa/coreasm.h>
-
-
-#if XCHAL_HAVE_INTERRUPTS
-/* Offsets of XtHalVPriState structure members (Xthal_vpri_state variable): */
-#define XTHAL_VPRI_VPRI_OFS 0x00
-#define XTHAL_VPRI_LOCKLEVEL_OFS 0x01
-#define XTHAL_VPRI_LOCKVPRI_OFS 0x02
-#define XTHAL_VPRI_PAD0_OFS 0x03
-#define XTHAL_VPRI_ENABLED_OFS 0x04
-#define XTHAL_VPRI_LOCKMASK_OFS 0x08
-#define XTHAL_VPRI_PAD1_OFS 0x0C
-#define XTHAL_VPRI_ENABLEMAP_OFS 0x10
-#define XTHAL_VPRI_RESOLVEMAP_OFS (0x10+0x40*(XCHAL_NUM_INTLEVELS+1))
-#define XTHAL_VPRI_END_OFS (0x10+0x40*(XCHAL_NUM_INTLEVELS*2+1))
-#endif /* XCHAL_HAVE_INTERRUPTS */
-
-
-#if defined(__SPLIT__get_intenable) || \
- defined(__SPLIT__get_intenable_nw)
-
-//----------------------------------------------------------------------
-// Access INTENABLE register from C
-//----------------------------------------------------------------------
-
-// unsigned xthal_get_intenable(void)
-//
-DECLFUNC(xthal_get_intenable)
- abi_entry
-# if XCHAL_HAVE_INTERRUPTS
- rsr.intenable a2
-# else
- movi a2, 0 // if no INTENABLE (no interrupts), tell caller nothing is enabled
-# endif
- abi_return
- endfunc
-
-#endif
-
-#if defined(__SPLIT__set_intenable) || \
- defined(__SPLIT__set_intenable_nw)
-
-// void xthal_set_intenable(unsigned)
-//
-DECLFUNC(xthal_set_intenable)
- abi_entry
-# if XCHAL_HAVE_INTERRUPTS
- wsr.intenable a2
-# endif
- abi_return
- endfunc
-
-
-//----------------------------------------------------------------------
-// Access INTERRUPT, INTSET, INTCLEAR register from C
-//----------------------------------------------------------------------
-
-#endif
-
-#if defined(__SPLIT__get_interrupt) || \
- defined (__SPLIT__get_interrupt_nw)
-
-// unsigned xthal_get_interrupt(void)
-//
-DECLFUNC (xthal_get_interrupt)
- abi_entry
-# if XCHAL_HAVE_INTERRUPTS
- rsr.interrupt a2
-# else
- movi a2, 0 // if no INTERRUPT (no interrupts), tell caller nothing is pending
-# endif
- abi_return
- endfunc
-
-#endif
-
-#if defined(__SPLIT__get_intread) || \
- defined(__SPLIT__get_intread_nw)
-
-DECLFUNC (xthal_get_intread)
- abi_entry
-# if XCHAL_HAVE_INTERRUPTS
- rsr.interrupt a2
-# else
- movi a2, 0 // if no INTERRUPT (no interrupts), tell caller nothing is pending
-# endif
- abi_return
- endfunc
-
-#endif
-
-#if defined(__SPLIT__set_intset) || \
- defined(__SPLIT__set_intset_nw)
-
-// void xthal_set_intset(unsigned)
-//
-DECLFUNC(xthal_set_intset)
- abi_entry
-# if XCHAL_HAVE_INTERRUPTS
- wsr.intset a2
-# endif
- abi_return
- endfunc
-
-#endif
-
-#if defined(__SPLIT__set_intclear) || \
- defined(__SPLIT__set_intclear_nw)
-
-// void xthal_set_intclear(unsigned)
-//
-DECLFUNC(xthal_set_intclear)
- abi_entry
-# if XCHAL_HAVE_INTERRUPTS
- wsr.intclear a2
-# endif
- abi_return
- endfunc
-
-
-
-//----------------------------------------------------------------------
-// Virtual PS.INTLEVEL support:
-// allows running C code at virtual PS.INTLEVEL > 0
-// using INTENABLE to simulate the masking that PS.INTLEVEL would do.
-//----------------------------------------------------------------------
-
-#endif
-
-#if defined(__SPLIT__get_vpri) ||\
- defined(__SPLIT__get_vpri_nw)
-
-// unsigned xthal_get_vpri(void);
-
-DECLFUNC(xthal_get_vpri)
- abi_entry
-# if XCHAL_HAVE_INTERRUPTS
- movi a2, Xthal_vpri_state
- l8ui a2, a2, XTHAL_VPRI_VPRI_OFS
-# else
- movi a2, 0 // no interrupts, report we're always at level 0
-# endif
- abi_return
- endfunc
-
-#endif
-
-#if defined(__SPLIT__set_vpri_nw)
-
-// unsigned xthal_set_vpri_nw(unsigned)
-//
-// Must be called at PS.INTLEVEL <= 1.
-// Doesn't touch the stack (doesn't reference a1 at all).
-// Normally, PS should be restored with a6 after return from this call
-// (it isn't restored automatically because some exception handlers
-// want to keep ints locked for a while).
-//
-// On entry:
-// a2 = new virtual interrupt priority (0x00 .. 0x1F)
-// a3-a6 = undefined
-// PS.INTLEVEL <= 1
-// On exit:
-// a2 = previous virtual interrupt priority (0x0F .. 0x1F, or 0 if no interrupts)
-// a3-a5 = clobbered
-// a6 = PS as it was on entry
-// PS.INTLEVEL = 1
-// !!!!!!!!! PS.WOE = 0 (but not if there are no interrupts; is this really needed???)
-// INTENABLE = updated according to new vpri
-
-_SYM(xthal_set_vpri_nw)
-
-# if XCHAL_HAVE_INTERRUPTS
- /* Make sure a2 is in the range 0x0F .. 0x1F: */
- movi a3, 0x1F // highest legal virtual interrupt priority
- sub a4, a2, a3 // (a4 = newlevel - maxlevel)
- movgez a2, a3, a4 // newlevel = maxlevel if (newlevel - maxlevel) >= 0
- movi a3, 15 // lowest legal virtual interrupt priority
- sub a4, a2, a3 // (a4 = newlevel - 15)
- movltz a2, a3, a4 // newlevel = 15 if newlevel < 15
-
-xthal_set_vpri_nw_common:
- movi a4, Xthal_vpri_state // address of vpri state structure
-
- /*
- * Lockout interrupts for exclusive access to virtual priority structure
- * while we examine and modify it.
- * Note that we accessed a4 and don't access any further than a6,
- * so we won't cause any spills, so we could leave WOE enabled (if it is),
- * but we clear it because that might be what the caller wants,
- * and is cleaner.
- */
- // Get PS and mask off INTLEVEL:
- rsil a6, 1 // save a6 = PS, set PS.INTLEVEL = 1
-
- // Clear PS.WOE. (Can we get rid of this?!!!!!):
- movi a3, ~0x00040000 // mask to...
- rsr.ps a5 // get and save a6 = PS
-//a2,a3,a4,a5,a6
- and a5, a5, a3 // ... clear a5.WOE
- wsr.ps a5 // clear PS.WOE
- rsync
-
-//a2,a4,a6
- /* Get mask of interrupts to be turned off at requested level: */
- l32i a5, a4, XTHAL_VPRI_ENABLED_OFS // get the global mask
- addx4 a3, a2, a4 // a3 = a4 + a2*4 (index into enablemap[] array)
-//a2,a3,a4,a5,a6
- l32i a3, a3, XTHAL_VPRI_ENABLEMAP_OFS // get the per-level mask
- and a3, a5, a3 // new INTENABLE value according to new intlevel
- wsr.intenable a3 // set it!
-//a2,a4,a6
-
- l8ui a5, a4, XTHAL_VPRI_VPRI_OFS // previous virtual priority
- s8i a2, a4, XTHAL_VPRI_VPRI_OFS // new virtual priority
-
- // Let the caller restore PS:
- //wsr.ps a6 // restore PS.INTLEVEL
- //rsync
-
- mov a2, a5 // return previous virtual intlevel
-
-# else /* ! XCHAL_HAVE_INTERRUPTS */
-xthal_set_vpri_nw_common:
-# if XCHAL_HAVE_EXCEPTIONS
- rsr.ps a6 // return PS for caller to restore
-# else
- movi a6, 0
-# endif
- movi a2, 0 // no interrupts, report we're always at virtual priority 0
-# endif /* XCHAL_HAVE_INTERRUPTS */
- ret
- endfunc
-
-
-
-// unsigned xthal_set_vpri_intlevel_nw(unsigned);
-//
-// Same as xthal_set_vpri_nw() except that it accepts
-// an interrupt level rather than a virtual interrupt priority.
-// This just converts intlevel to vpri and jumps to xthal_set_vpri_nw.
-
-_SYM(xthal_set_vpri_intlevel_nw)
-# if XCHAL_HAVE_INTERRUPTS
- movi a3, 0x10
- movnez a2, a3, a2 // a2 = (a2 ? 0x10 : 0)
- addi a2, a2, 0x0F // a2 += 0x0F
-# endif
- j xthal_set_vpri_nw_common // set vpri to a2
- endfunc
-
-
-
-#endif
-
-#if defined(__SPLIT__set_vpri)
-
-// unsigned xthal_set_vpri (unsigned newvpri);
-//
-// Normal windowed call (PS.INTLEVEL=0 and PS.WOE=1 on entry and exit).
-// (PS.UM = 0 or 1)
-//
-// Returns previous virtual interrupt priority
-// (0x0F .. 0x1F, or 0 if no interrupts).
-//
-// On entry:
-// a2 = new virtual interrupt priority (0x00 .. 0x1F)
-// On exit:
-// a2 = previous vpri
-// INTENABLE = updated according to new vpri
-
-DECLFUNC(xthal_set_vpri)
- abi_entry
-# if XCHAL_HAVE_INTERRUPTS
- /* Make sure a2 is in the range 0x0F .. 0x1F: */
- movi a3, 0x1F // highest legal virtual interrupt priority
- sub a4, a2, a3 // (a4 = newlevel - maxlevel)
- movgez a2, a3, a4 // newlevel = maxlevel if (newlevel - maxlevel) >= 0
- movi a3, 15 // lowest legal virtual interrupt priority
- sub a4, a2, a3 // (a4 = newlevel - 15)
- movltz a2, a3, a4 // newlevel = 15 if newlevel < 15
-
-xthal_set_vpri_common1:
- movi a4, Xthal_vpri_state // address of vpri state structure
-
- /*
- * Lockout interrupts for exclusive access to virtual priority structure
- * while we examine and modify it.
- * Note that we accessed a4 and don't access any further than a6,
- * so we won't cause any spills, so we can leave WOE enabled.
- */
- // Get PS and mask off INTLEVEL:
- rsil a6, 1 // save a6 = PS, set PS.INTLEVEL = 1
-
- l8ui a7, a4, XTHAL_VPRI_VPRI_OFS // previous virtual priority (vpri)
-
- /* Get mask of interrupts to be turned off at requested level: */
- l32i a5, a4, XTHAL_VPRI_ENABLED_OFS // get the global mask
- addx4 a3, a2, a4 // a3 = a4 + a2*4 (index into enablemap[] array)
- l32i a3, a3, XTHAL_VPRI_ENABLEMAP_OFS // get the per-level mask
- s8i a2, a4, XTHAL_VPRI_VPRI_OFS // new virtual priority (in load-slot)
- and a3, a5, a3 // new INTENABLE value according to new intlevel
- wsr.intenable a3 // set it!
-
- wsr.ps a6 // restore PS.INTLEVEL
- rsync
-
- mov a2, a7 // return previous vpri
-
-# else /* ! XCHAL_HAVE_INTERRUPTS */
- movi a2, 0 // no interrupts, report we're always at virtual priority 0
-# endif /* XCHAL_HAVE_INTERRUPTS */
- abi_return
- endfunc
-
-
-
-// unsigned xthal_set_vpri_intlevel (unsigned intlevel);
-//
-// Equivalent to xthal_set_vpri(XTHAL_VPRI(intlevel,0xF)).
-// This just converts intlevel to vpri and jumps inside xthal_set_vpri.
-
-DECLFUNC(xthal_set_vpri_intlevel)
- abi_entry
-# if XCHAL_HAVE_INTERRUPTS
- movi a3, 0x10
- movnez a2, a3, a2 // a2 = (a2 ? 0x10 : 0)
- addi a2, a2, 0x0F // a2 += 0x0F
- j xthal_set_vpri_common1 // set vpri to a2
-# else
- movi a2, 0 // no interrupts, report we're always at virtual priority 0
- abi_return
-# endif
- endfunc
-
-
-
-// unsigned xthal_set_vpri_lock (void);
-//
-// Equivalent to xthal_set_vpri(0x1F);
-// Returns previous virtual interrupt priority.
-//
-DECLFUNC(xthal_set_vpri_lock)
- abi_entry
-# if XCHAL_HAVE_INTERRUPTS
- movi a2, 0x1F // lock at intlevel 1
- j xthal_set_vpri_common1
-# else
- movi a2, 0 // no interrupts, report we're always at virtual priority 0
- abi_return
-# endif
- endfunc
-
-
-#endif
-
-#if defined(__SPLIT__get_intpending_nw)
-
-// unsigned xthal_get_intpending_nw(void)
-//
-// Of the pending level-1 interrupts, returns
-// the bitmask of interrupts at the highest software priority,
-// and the index of the first of these.
-// It also disables interrupts of that software priority and lower
-// via INTENABLE.
-//
-// On entry:
-// a0 = return PC
-// a1 = sp
-// a2-a6 = (available) (undefined)
-// PS.INTLEVEL = 1
-// PS.WOE = 0
-// On exit:
-// a0 = return PC
-// a1 = sp (NOTE: stack is untouched, a1 is never referenced)
-// a2 = index of first highest-soft-pri pending l1 interrupt (0..31), or -1 if none
-// a3 = bitmask of highest-soft-pri pending l1 interrupts (0 if none) (may be deprecated)
-// a4 = (clobbered)
-// a5 = new vpri (not typically used by caller? so might get deprecated...?)
-// a6 = old vpri (eg. to be saved as part of interrupt context's state)
-// INTENABLE = updated according to new vpri
-// INTERRUPT bit cleared for interrupt returned in a2 (if any), if software or edge-triggered or write-error
-// all others = preserved
-
-_SYM(xthal_get_intpending_nw)
-# if XCHAL_HAVE_INTERRUPTS
- // Give us one more register to play with
- //wsr.excsave1 a4
-
- // Figure out which interrupt to process
-
- /*
- Perform a binary search to find a mask of the interrupts that are
- ready at the highest virtual priority level.
- Xthal_vpri_resolvemap is a binary tree implemented within an array,
- sorted by priority: each node contains the set of interrupts in
- the range of priorities corresponding to the right half of its branch.
- The mask of enabled & pending interrupts is compared with each node to
- determine in which subbranch (left or right) the highest priority one is
- present. After 4 such masks and comparisons (for 16 priorities), we have
- determined the priority of the highest priority enabled&pending interrupt.
-
- Table entries for intlevel 'i' are bitmasks defined as follows (map=Xthal_vpri_resolvemap[i-1]):
- map[8+(x=0)] = ints at pri x + 8..15 (8-15)
- map[4+(x=0,8)] = ints at pri x + 4..7 (4-7,12-15)
- map[2+(x=0,4,8,12)] = ints at pri x + 2..3 (2-3,6-7,10-11,14-15)
- map[1+(x=0,2..12,14)] = ints at pri x + 1 (1,3,5,7,9,11,13,15)
- map[0] = 0 (unused; for alignment)
- */
-
- rsr.interrupt a4 // a4 = mask of interrupts pending, including those disabled
- rsr.intenable a2 // a2 = mask of interrupts enabled
- movi a3, Xthal_vpri_state
- and a4, a2, a4 // a4 = mask of enabled interrupts pending
- beqz a4, gipfail // if none (can happen for spurious level-triggered interrupts,
- // or ???), we're done
-
- mov a5, a3
- l32i a2, a5, XTHAL_VPRI_RESOLVEMAP_OFS+8*4
- bnone a2, a4, 1f
- addi a5, a5, 8*4
-1: l32i a2, a5, XTHAL_VPRI_RESOLVEMAP_OFS+4*4
- bnone a2, a4, 1f
- addi a5, a5, 4*4
-1: l32i a2, a5, XTHAL_VPRI_RESOLVEMAP_OFS+2*4
- bnone a2, a4, 1f
- addi a5, a5, 2*4
-1: l32i a2, a5, XTHAL_VPRI_RESOLVEMAP_OFS+1*4
- bnone a2, a4, 1f
- addi a5, a5, 1*4
-1:
-
-# if 0
- a5 = address of map ...
- l32i a2, a5, XTHAL_VPRI_RESOLVEMAP_OFS+8*4
- addi a?, a5, 8*4
- and a2, a2, a4
- movnez a5, a?, a2
- l32i a2, a5, XTHAL_VPRI_RESOLVEMAP_OFS+4*4
- addi a?, a5, 4*4
- and a2, a2, a4
- movnez a5, a?, a2
- l32i a2, a5, XTHAL_VPRI_RESOLVEMAP_OFS+2*4
- addi a?, a5, 2*4
- and a2, a2, a4
- movnez a5, a?, a2
- l32i a2, a5, XTHAL_VPRI_RESOLVEMAP_OFS+1*4
- addi a?, a5, 1*4
- and a2, a2, a4
- movnez a5, a?, a2
-# endif
-
- // Here:
- // a3 = Xthal_vpri_state
- // a5 = Xthal_vpri_state + softpri*4
- // a4 = mask of enabled interrupts pending
- // a2,a6 = available
-
- // Lock interrupts during virtual priority data structure transaction:
- //rsil a6, 1 // set PS.INTLEVEL = 1 (a6 ignored)
- // a2,a6 = available
-
- // The highest priority interrupt(s) in a4 is at softpri = (a5-a3) / 4.
- // So interrupts in enablemap[1][softpri] are not in a4 (they are higher priority).
- // The set of interrupts at softpri are:
- // enablemap[1][softpri-1] - enablemap[1][softpri]
- // So and'ing a4 with enablemap[1][softpri - 1] will give us
- // the set of interrupts pending at the highest soft priority.
- //
- l32i a2, a5, XTHAL_VPRI_ENABLEMAP_OFS + 16*4 - 4 // get enablemap[1][softpri-1]
- and a4, a2, a4 // only keep interrupts of highest pri (softpri)
-
- // a4 now has mask of pending interrupts at highest ready level (new vpri)
-
- // Update INTENABLE for this new virtual priority
- l32i a2, a5, XTHAL_VPRI_ENABLEMAP_OFS + 16*4 // get vpri-specific mask = enablemap[1][softpri]
- l32i a6, a3, XTHAL_VPRI_ENABLED_OFS // get global mask
- sub a5, a5, a3 // a5 = softpri * 4 (for below; here for efficiency)
- and a2, a2, a6 // and together
- wsr.intenable a2 // disable interrupts at or below new vpri
- // a2,a6 = available
-
- // Update new virtual priority:
- l8ui a6, a3, XTHAL_VPRI_VPRI_OFS // get old vpri (returned)
- srli a5, a5, 2 // a5 = softpri (0..15)
- addi a5, a5, 0x10 // a5 = 0x10 + softpri = new virtual priority
- s8i a5, a3, XTHAL_VPRI_VPRI_OFS // store new vpri (returned)
-
- // Undo the temporary lock (if was at PS.INTLEVEL > 1):
- //rsil a2, 1
-
- mov a3, a4 // save for the caller (in case it wants it?)
-
- // Choose one of the set of highest-vpri pending interrupts to process.
- // For speed (and simplicity), use this simple two-instruction sequence
- // to select the least significant bit set in a4. This implies that
- // interrupts with a lower interrupt number take precedence over those
- // with a higher interrupt number (!!).
- //
- neg a2, a4 // keep only the least-significant bit that is set...
- and a4, a2, a4 // ... in a4
-
- // Software, edge-triggered, and write-error interrupts are cleared by writing to the
- // INTCLEAR pseudo-reg (to clear relevant bits of the INTERRUPT register).
- // To simplify interrupt handlers (so they avoid tracking which type of
- // interrupt they handle and act accordingly), clear such interrupts here.
- // To avoid race conditions, the clearing must occur *after* we undertake
- // to process the interrupt, and *before* actually handling the interrupt.
- // Interrupt handlers may additionally clear the interrupt themselves
- // at appropriate points if needed to avoid unnecessary interrupts.
- //
-#define CLEARABLE_INTLEVEL1_MASK (XCHAL_INTLEVEL1_MASK & XCHAL_INTCLEARABLE_MASK)
-# if CLEARABLE_INTLEVEL1_MASK != 0
- //movi a2, CLEARABLE_INTLEVEL1_MASK
- //and a2, a2, a4
- //wsr.intclear a2
- wsr.intclear a4 // no effect if a4 not a software or edge-triggered or write-error interrupt
-# endif
-
- // Convert the single-bit interrupt mask to an interrupt number.
- // (ie. compute log2 using either the NSAU instruction or a binary search)
-
- find_ms_setbit a2, a4, a2, 0 // set a2 to index of lsbit set in a4 (0..31)
- // NOTE: assumes a4 != 0 (otherwise a2 is undefined[?])
-
- // a2 has vector number (0..31)
-
- //rsr.excsave1 a4
- ret
-
-gipfail:
- l8ui a6, a3, XTHAL_VPRI_VPRI_OFS // get old vpri
- mov a5, a6 // is also new vpri (unchanged)
-# else /* XCHAL_HAVE_INTERRUPTS */
- // No interrupts configured!
- movi a5, 0 // return zero new vpri
- movi a6, 0 // return zero old vpri
-# endif /* XCHAL_HAVE_INTERRUPTS */
- movi a2, -1 // return bogus vector number (eg. can be quickly tested for negative)
- movi a3, 0 // return zero bitmask of interrupts pending
- ret
- endfunc
-
-// -----------------------------------------------------------------
-
-#endif
-
-#if defined(__SPLIT__vpri_lock) || \
- defined(__SPLIT__vpri_lock_nw)
-
-// void xthal_vpri_lock()
-//
-// Used internally by the Core HAL to block interrupts of higher or equal
-// priority than Xthal_vpri_locklevel during virtual interrupt operations.
-//
-DECLFUNC(xthal_vpri_lock)
- abi_entry
-# if XCHAL_HAVE_INTERRUPTS
- rsil a6, 1 // save a6 = PS, set PS.INTLEVEL = 1
-
- // if( Xthal_vpri_level < Xthal_vpri_locklevel )
- //
- movi a2, Xthal_vpri_state // a2 := address of global var. Xthal_vpri_state
- //interlock
- l8ui a3, a2, XTHAL_VPRI_VPRI_OFS // a3 := Xthal_vpri_level == Xthal_vpri_state.vpri
- l8ui a5, a2, XTHAL_VPRI_LOCKLEVEL_OFS // a5 := Xthal_vpri_locklevel
- l32i a4, a2, XTHAL_VPRI_ENABLED_OFS // a4 := Xthal_vpri_enabled
- bgeu a3, a5, xthal_vpri_lock_done
-
- // xthal_set_intenable( Xthal_vpri_enablemap[0][Xthal_vpri_locklevel] & Xthal_vpri_enabled );
- //
- addx4 a3, a5, a2 // a3 := a2 + a5*4 (index into enablemap[] array)
- l32i a3, a3, XTHAL_VPRI_ENABLEMAP_OFS // a3 := Xthal_vpri_enablemap[0][Xthal_vpri_locklevel]
- //interlock
- and a2, a4, a3
- wsr.intenable a2
-
-xthal_vpri_lock_done:
- wsr.ps a6 // restore PS.INTLEVEL
- rsync
-# endif
- abi_return
- endfunc
-
-#endif
-
-#if defined(__SPLIT__vpri_unlock) || \
- defined(__SPLIT__vpri_unlock_nw)
-
-// void xthal_vpri_unlock(void)
-//
-// Enable interrupts according to the current virtual interrupt priority.
-// This effectively "unlocks" interrupts disabled by xthal_vpri_lock()
-// (assuming the virtual interrupt priority hasn't changed).
-//
-DECLFUNC(xthal_vpri_unlock)
- abi_entry
-# if XCHAL_HAVE_INTERRUPTS
- //
- // This should be free of race-conditions.
- //
- // xthal_set_intenable( Xthal_vpri_enablemap[0][Xthal_vpri_level] & Xthal_vpri_enabled );
- //
- movi a2, Xthal_vpri_state // a2 := address of global var. Xthal_vpri_state
- //interlock
- l8ui a3, a2, XTHAL_VPRI_VPRI_OFS // a3 := Xthal_vpri_level == Xthal_vpri_state.vpri
- l32i a4, a2, XTHAL_VPRI_ENABLED_OFS // a4 := Xthal_vpri_enabled
- addx4 a3, a3, a2 // a3 := a2 + a3*4 (index into enablemap[] array)
- l32i a3, a3, XTHAL_VPRI_ENABLEMAP_OFS // a3 := Xthal_vpri_enablemap[0][Xthal_vpri_level]
- //interlock
- and a2, a4, a3
- wsr.intenable a2
-# endif
- abi_return
- endfunc
-
-#endif /*SPLIT*/
-
diff --git a/src/arch/xtensa/smp/hal/interrupts.c b/src/arch/xtensa/smp/hal/interrupts.c
deleted file mode 100644
index 1bf8bd9..0000000
--- a/src/arch/xtensa/smp/hal/interrupts.c
+++ /dev/null
@@ -1,850 +0,0 @@
-//
-// interrupts.c - interrupts related constants and functions
-//
-// $Id: //depot/rel/Foxhill/dot.8/Xtensa/OS/hal/interrupts.c#1 $
-
-// Copyright (c) 2002-2004 Tensilica Inc.
-//
-// Permission is hereby granted, free of charge, to any person obtaining
-// a copy of this software and associated documentation files (the
-// "Software"), to deal in the Software without restriction, including
-// without limitation the rights to use, copy, modify, merge, publish,
-// distribute, sublicense, and/or sell copies of the Software, and to
-// permit persons to whom the Software is furnished to do so, subject to
-// the following conditions:
-//
-// The above copyright notice and this permission notice shall be included
-// in all copies or substantial portions of the Software.
-//
-// THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
-// EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
-// MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
-// IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY
-// CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
-// TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
-// SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
-
-#include <xtensa/config/core.h>
-
-#if XCHAL_HAVE_INTERRUPTS
-
-/* For internal use by the HAL: */
-// static void xthal_vpri_lock(void);
-// static void xthal_vpri_unlock(void);
-extern void xthal_vpri_lock(void);
-extern void xthal_vpri_unlock(void);
-
-
-/*
- * Definitions:
- *
- * Virtual interrupt level = 0 .. 0xFF
- *
- * ...
- */
-
-#define XTHAL_DEFAULT_SOFTPRI 4 /* default software priority (range 0..15) */
- /* IMPORTANT: if you change this, you also
- need to update the initial resolvemap[]
- value below... */
-
-/*
- * Macros to convert between:
- * intlevel (0..15) and software priority within an intlevel (0..15)
- * and
- * virtual interrupt priority (0..0xFF), which is a combination of the above two.
- */
-#define XTHAL_VPRI_INTLEVEL(vpri) (((vpri) >> 4) & 0xF)
-#define XTHAL_VPRI_SOFTPRI(vpri) ((vpri) & 0xF)
-#define XTHAL_VPRI(intlevel,softpri) ((((intlevel)&0xF)<<4)|((softpri)&0xF))
-
-
-/*
- * Virtual priority management data structures.
- * This structure is instantiated as Xthal_vpri_state (below).
- *
- * IMPORTANT: if you change anything in this structure,
- * you must accordingly change structure offsets
- * defined in int_asm.S .
- *
- * IMPORTANT: the worst-case offset of the resolvemap[] field is 976 bytes
- * (0x10 + 0x40*15), which is accessed in int_asm.S at a further
- * offset of 8*4==32 for a total offset of 1008, very close
- * to l32i's offset limit of 1020. So you can't push it much
- * further.
- *
- * [INTERNAL NOTE: There might be a trick that will save 64 bytes,
- * if really needed, by trimming 15 word entries from the start
- * of enablemap[] ... -MG]
- */
-typedef struct XtHalVPriState {
- /*
- * Current virtual interrupt priority (0x0F .. 0xFF)
- * (or actually, 0x0F .. XCHAL_NUM_INTLEVELS*0x10+0x0F).
- * Virtual priorities 0x00 to 0x0E are mapped to 0x0F (they're all
- * equivalent, because there's no such thing as a level 0 interrupt),
- * which may help optimize the size of enablemap[] in the future.
- * Virtual priorities above XCHAL_NUM_INTLEVELS*0x10+0x0F are
- * mapped to XCHAL_NUM_INTLEVELS*0x10+0x0F, which is equivalent.
- *
- * NOTE: this variable is actually part of the processor context,
- * which means (for most OSes) that it must be saved
- * in the task control block along with other register state.
- */
- unsigned char vpri; // current virtual interrupt priority (0x0F..0xFF)
- unsigned char locklevel; // real interrupt level used to get exclusive
- // access to this structure; MUST be at least one (1)
- unsigned char lockvpri; // virtual interrupt level used to get exclusive
- // access to this structure; MUST be XTHAL_VPRI(locklevel,15)
- // (so it's at least 0x1F); placed here for efficiency
- unsigned char pad0; // (alignment padding, unused)
-
- unsigned enabled; // mask of which interrupts are enabled, regardless of level
- // (level masking is applied on top of this)
-
- unsigned lockmask; // (unused?) INTENABLE value used to lock out
- // interrupts for exclusive access to this structure
-
- unsigned pad1; // (alignment padding, unused)
-
- /*
- * For each virtual interrupt priority, this array provides the
- * bitmask of interrupts of greater virtual priority
- * (ie. the set of interrupts to enable at that virtual priority,
- * if all interrupts were enabled in field 'enabled').
- */
- unsigned enablemap[XCHAL_NUM_INTLEVELS+1][16];
-
- /*
- * Table entries for intlevel 'i' are bitmasks defined as follows,
- * with map == Xthal_vpri_resolvemap[i-1]:
- * map[8+(x=0)] = ints at pri x + 8..15 (8-15)
- * map[4+(x=0,8)] = ints at pri x + 4..7 (4-7,12-15)
- * map[2+(x=0,4,8,12)] = ints at pri x + 2..3 (2-3,6-7,10-11,14-15)
- * map[1+(x=0,2..12,14)] = ints at pri x + 1 (1,3,5,7,9,11,13,15)
- * map[0] = 0 (unused; for alignment)
- */
- unsigned resolvemap[XCHAL_NUM_INTLEVELS][16];
-
-} XtHalVPriState;
-
-
-extern XtHalVPriState Xthal_vpri_state;
-extern unsigned char Xthal_int_vpri[32];
-extern XtHalVoidFunc * Xthal_tram_trigger_fn;
-
-extern void xthal_null_func(void);
-
-/* Shorthand for structure members: */
-#define Xthal_vpri_level Xthal_vpri_state.vpri
-#define Xthal_vpri_locklevel Xthal_vpri_state.locklevel
-#define Xthal_vpri_lockvpri Xthal_vpri_state.lockvpri
-#define Xthal_vpri_enabled Xthal_vpri_state.enabled
-#define Xthal_vpri_lockmask Xthal_vpri_state.lockmask // unused?
-#define Xthal_vpri_enablemap Xthal_vpri_state.enablemap
-#define Xthal_vpri_resolvemap Xthal_vpri_state.resolvemap
-#if 0
-Combined refs:
- - enablemap, vpri, enabled (xthal_set_vpri[_nw])
- - enablemap, vpri, enabled, resolvemap (xthal_get_intpending_nw)
- - enablemap, vpri, enabled, locklevel (xthal_vpri_lock)
- - enablemap, vpri, enabled (xthal_vpri_unlock)
-#endif
-
-#endif /* XCHAL_HAVE_INTERRUPTS */
-
-
-
-#if defined(__SPLIT__num_intlevels)
-
-// the number of interrupt levels
-const unsigned char Xthal_num_intlevels = XCHAL_NUM_INTLEVELS;
-
-#endif
-
-#if defined(__SPLIT__num_interrupts)
-
-// the number of interrupts
-const unsigned char Xthal_num_interrupts = XCHAL_NUM_INTERRUPTS;
-
-#endif
-
-#if defined(__SPLIT__excm_level)
-
-// the highest level of interrupts masked by PS.EXCM (if XEA2)
-const unsigned char Xthal_excm_level = XCHAL_EXCM_LEVEL;
-
-#endif
-
-#if defined(__SPLIT__intlevel_mask)
-
-// mask of interrupts at each intlevel
-const unsigned Xthal_intlevel_mask[16] = {
- XCHAL_INTLEVEL_MASKS
-};
-
-#endif
-
-#if defined(__SPLIT__intlevel_andbelow_mask)
-
-// mask for level 1 to N interrupts
-const unsigned Xthal_intlevel_andbelow_mask[16] = {
- XCHAL_INTLEVEL_ANDBELOW_MASKS
-};
-
-#endif
-
-#if defined(__SPLIT__intlevel)
-
-// level per interrupt
-const unsigned char Xthal_intlevel[32] = {
- XCHAL_INT_LEVELS
-};
-
-#endif
-
-#if defined(__SPLIT__inttype)
-
-// type of each interrupt
-const unsigned char Xthal_inttype[32] = {
- XCHAL_INT_TYPES
-};
-
-#endif
-
-#if defined(__SPLIT__inttype_mask)
-
-const unsigned Xthal_inttype_mask[XTHAL_MAX_INTTYPES] = {
- XCHAL_INTTYPE_MASKS
-};
-
-#endif
-
-#if defined(__SPLIT__timer_interrupt)
-
-// interrupts assigned to each timer (CCOMPARE0 to CCOMPARE3), -1 if unassigned
-const int Xthal_timer_interrupt[XTHAL_MAX_TIMERS] = {
- XCHAL_TIMER_INTERRUPTS
-};
-
-#endif
-
-#if defined(__SPLIT__vpri)
-
-#if XCHAL_HAVE_INTERRUPTS
-
-/*
- * Note: this structure changes dynamically at run-time,
- * but is initialized here for efficiency and simplicity,
- * according to configuration.
- */
-XtHalVPriState Xthal_vpri_state = {
- 0x00, /* vpri */
- 1, /* locklevel */
- 0x1F, /* lockvpri */
- 0, /* pad0 */
- 0x00000000, /* enabled */
- 0x00000000, /* lockmask (unused?) */
- 0, /* pad1 */
-
-#define DEFAULT_ENABLEMAP(levela,levelb) \
- { (XCHAL_INTLEVEL15_ANDBELOW_MASK & ~(XTHAL_DEFAULT_SOFTPRI > 0 ? levela : levelb)), \
- (XCHAL_INTLEVEL15_ANDBELOW_MASK & ~(XTHAL_DEFAULT_SOFTPRI > 1 ? levela : levelb)), \
- (XCHAL_INTLEVEL15_ANDBELOW_MASK & ~(XTHAL_DEFAULT_SOFTPRI > 2 ? levela : levelb)), \
- (XCHAL_INTLEVEL15_ANDBELOW_MASK & ~(XTHAL_DEFAULT_SOFTPRI > 3 ? levela : levelb)), \
- (XCHAL_INTLEVEL15_ANDBELOW_MASK & ~(XTHAL_DEFAULT_SOFTPRI > 4 ? levela : levelb)), \
- (XCHAL_INTLEVEL15_ANDBELOW_MASK & ~(XTHAL_DEFAULT_SOFTPRI > 5 ? levela : levelb)), \
- (XCHAL_INTLEVEL15_ANDBELOW_MASK & ~(XTHAL_DEFAULT_SOFTPRI > 6 ? levela : levelb)), \
- (XCHAL_INTLEVEL15_ANDBELOW_MASK & ~(XTHAL_DEFAULT_SOFTPRI > 7 ? levela : levelb)), \
- (XCHAL_INTLEVEL15_ANDBELOW_MASK & ~(XTHAL_DEFAULT_SOFTPRI > 8 ? levela : levelb)), \
- (XCHAL_INTLEVEL15_ANDBELOW_MASK & ~(XTHAL_DEFAULT_SOFTPRI > 9 ? levela : levelb)), \
- (XCHAL_INTLEVEL15_ANDBELOW_MASK & ~(XTHAL_DEFAULT_SOFTPRI >10 ? levela : levelb)), \
- (XCHAL_INTLEVEL15_ANDBELOW_MASK & ~(XTHAL_DEFAULT_SOFTPRI >11 ? levela : levelb)), \
- (XCHAL_INTLEVEL15_ANDBELOW_MASK & ~(XTHAL_DEFAULT_SOFTPRI >12 ? levela : levelb)), \
- (XCHAL_INTLEVEL15_ANDBELOW_MASK & ~(XTHAL_DEFAULT_SOFTPRI >13 ? levela : levelb)), \
- (XCHAL_INTLEVEL15_ANDBELOW_MASK & ~(XTHAL_DEFAULT_SOFTPRI >14 ? levela : levelb)), \
- (XCHAL_INTLEVEL15_ANDBELOW_MASK & ~(XTHAL_DEFAULT_SOFTPRI >15 ? levela : levelb)) }
-
- /* Xthal_vpri_enablemap[XCHAL_NUM_INTLEVELS+1][16]: */
- {
- DEFAULT_ENABLEMAP(XCHAL_INTLEVEL0_ANDBELOW_MASK,XCHAL_INTLEVEL0_ANDBELOW_MASK),
-#if XCHAL_NUM_INTLEVELS >= 1
- DEFAULT_ENABLEMAP(XCHAL_INTLEVEL0_ANDBELOW_MASK,XCHAL_INTLEVEL1_ANDBELOW_MASK),
-#endif
-#if XCHAL_NUM_INTLEVELS >= 2
- DEFAULT_ENABLEMAP(XCHAL_INTLEVEL1_ANDBELOW_MASK,XCHAL_INTLEVEL2_ANDBELOW_MASK),
-#endif
-#if XCHAL_NUM_INTLEVELS >= 3
- DEFAULT_ENABLEMAP(XCHAL_INTLEVEL2_ANDBELOW_MASK,XCHAL_INTLEVEL3_ANDBELOW_MASK),
-#endif
-#if XCHAL_NUM_INTLEVELS >= 4
- DEFAULT_ENABLEMAP(XCHAL_INTLEVEL3_ANDBELOW_MASK,XCHAL_INTLEVEL4_ANDBELOW_MASK),
-#endif
-#if XCHAL_NUM_INTLEVELS >= 5
- DEFAULT_ENABLEMAP(XCHAL_INTLEVEL4_ANDBELOW_MASK,XCHAL_INTLEVEL5_ANDBELOW_MASK),
-#endif
-#if XCHAL_NUM_INTLEVELS >= 6
- DEFAULT_ENABLEMAP(XCHAL_INTLEVEL5_ANDBELOW_MASK,XCHAL_INTLEVEL6_ANDBELOW_MASK),
-#endif
-#if XCHAL_NUM_INTLEVELS >= 7
-# error Interrupt levels greater than 6 not currently supported in the HAL interrupt routines.
-#endif
- },
-
- /* Xthal_vpri_resolvemap[XCHAL_NUM_INTLEVELS][16]: */
- {
-#if XCHAL_NUM_INTLEVELS >= 1 /* set for default soft priority of 4: */
- {0,0,0,0, XCHAL_INTLEVEL1_MASK,0,0,0, 0,0,0,0, 0,0,0,0},
-#endif
-#if XCHAL_NUM_INTLEVELS >= 2 /* set for default soft priority of 4: */
- {0,0,0,0, XCHAL_INTLEVEL2_MASK,0,0,0, 0,0,0,0, 0,0,0,0},
-#endif
-#if XCHAL_NUM_INTLEVELS >= 3 /* set for default soft priority of 4: */
- {0,0,0,0, XCHAL_INTLEVEL3_MASK,0,0,0, 0,0,0,0, 0,0,0,0},
-#endif
-#if XCHAL_NUM_INTLEVELS >= 4 /* set for default soft priority of 4: */
- {0,0,0,0, XCHAL_INTLEVEL4_MASK,0,0,0, 0,0,0,0, 0,0,0,0},
-#endif
-#if XCHAL_NUM_INTLEVELS >= 5 /* set for default soft priority of 4: */
- {0,0,0,0, XCHAL_INTLEVEL5_MASK,0,0,0, 0,0,0,0, 0,0,0,0},
-#endif
-#if XCHAL_NUM_INTLEVELS >= 6 /* set for default soft priority of 4: */
- {0,0,0,0, XCHAL_INTLEVEL6_MASK,0,0,0, 0,0,0,0, 0,0,0,0},
-#endif
-#if XCHAL_NUM_INTLEVELS >= 7 /* set for default soft priority of 4: */
-# error Interrupt levels greater than 6 not currently supported in the HAL interrupt routines.
-#endif
- }
-
-};
-
-
-/*
- * Virtual (software) priority (0x00..0xFF) of each interrupt.
- * This isn't referenced by assembler.
- */
-unsigned char Xthal_int_vpri[32] = {
-#define DEFAULT_INTVPRI(level) (level ? ((level << 4) | XTHAL_DEFAULT_SOFTPRI) : 0)
- DEFAULT_INTVPRI( XCHAL_INT0_LEVEL ),
- DEFAULT_INTVPRI( XCHAL_INT1_LEVEL ),
- DEFAULT_INTVPRI( XCHAL_INT2_LEVEL ),
- DEFAULT_INTVPRI( XCHAL_INT3_LEVEL ),
- DEFAULT_INTVPRI( XCHAL_INT4_LEVEL ),
- DEFAULT_INTVPRI( XCHAL_INT5_LEVEL ),
- DEFAULT_INTVPRI( XCHAL_INT6_LEVEL ),
- DEFAULT_INTVPRI( XCHAL_INT7_LEVEL ),
- DEFAULT_INTVPRI( XCHAL_INT8_LEVEL ),
- DEFAULT_INTVPRI( XCHAL_INT9_LEVEL ),
- DEFAULT_INTVPRI( XCHAL_INT10_LEVEL ),
- DEFAULT_INTVPRI( XCHAL_INT11_LEVEL ),
- DEFAULT_INTVPRI( XCHAL_INT12_LEVEL ),
- DEFAULT_INTVPRI( XCHAL_INT13_LEVEL ),
- DEFAULT_INTVPRI( XCHAL_INT14_LEVEL ),
- DEFAULT_INTVPRI( XCHAL_INT15_LEVEL ),
- DEFAULT_INTVPRI( XCHAL_INT16_LEVEL ),
- DEFAULT_INTVPRI( XCHAL_INT17_LEVEL ),
- DEFAULT_INTVPRI( XCHAL_INT18_LEVEL ),
- DEFAULT_INTVPRI( XCHAL_INT19_LEVEL ),
- DEFAULT_INTVPRI( XCHAL_INT20_LEVEL ),
- DEFAULT_INTVPRI( XCHAL_INT21_LEVEL ),
- DEFAULT_INTVPRI( XCHAL_INT22_LEVEL ),
- DEFAULT_INTVPRI( XCHAL_INT23_LEVEL ),
- DEFAULT_INTVPRI( XCHAL_INT24_LEVEL ),
- DEFAULT_INTVPRI( XCHAL_INT25_LEVEL ),
- DEFAULT_INTVPRI( XCHAL_INT26_LEVEL ),
- DEFAULT_INTVPRI( XCHAL_INT27_LEVEL ),
- DEFAULT_INTVPRI( XCHAL_INT28_LEVEL ),
- DEFAULT_INTVPRI( XCHAL_INT29_LEVEL ),
- DEFAULT_INTVPRI( XCHAL_INT30_LEVEL ),
- DEFAULT_INTVPRI( XCHAL_INT31_LEVEL )
-};
-
-
-#if 0
-/*
- * A number of things may have already been written not calling
- * this function, so it isn't straightforward to start requiring it:
- */
-void xthal_vpri_init( int default_vpri )
-{
- int i, j;
-
- Xthal_vpri_level = 0; /* vpri */
- Xthal_vpri_locklevel = 1; /* locklevel */
- Xthal_vpri_lockvpri = 0x1F; /* lockvpri */
- Xthal_vpri_enabled = 0x00000000; /* enabled */
- Xthal_vpri_lockmask = 0x00000000; /* lockmask (unused?) */
- for( i = 0; i < XCHAL_NUM_INTLEVELS; i++ ) {
- for( j = 0; j < 16; j++ )
- Xthal_vpri_enablemap[i][j] = XCHAL_INTLEVEL15_ANDBELOW_MASK
- & ~Xthal_intlevel_andbelow_mask[i - (j < default_vpri && i > 0)];
- }
- for( i = 1; i < XCHAL_NUM_INTLEVELS; i++ ) {
- for( j = 0; j < 16; j++ )
- Xthal_vpri_resolvemap[i-1][j] = 0;
- if( (default_vpri & 1) != 0 )
- Xthal_vpri_resolvemap[i-1][default_vpri & 0xF] |= Xthal_intlevel_mask[i];
- if( (default_vpri & 2) != 0 )
- Xthal_vpri_resolvemap[i-1][default_vpri & 0xE] |= Xthal_intlevel_mask[i];
- if( (default_vpri & 4) != 0 )
- Xthal_vpri_resolvemap[i-1][default_vpri & 0xC] |= Xthal_intlevel_mask[i];
- if( (default_vpri & 8) != 0 )
- Xthal_vpri_resolvemap[i-1][default_vpri & 0x8] |= Xthal_intlevel_mask[i];
- }
- for( i = 0; i < 32; i++ )
- Xthal_int_vpri[i] = (Xthal_intlevel[i] << 4) | (default_vpri & 0xF);
-}
-#endif /*0*/
-
-void xthal_null_func(void) { }
-XtHalVoidFunc *Xthal_tram_trigger_fn = xthal_null_func;
-
-
-#endif /* XCHAL_HAVE_INTERRUPTS */
-
-#endif
-
-#if defined(__SPLIT__vpri_to_intlevel)
-
-/*
- * xthal_vpri_to_intlevel
- *
- * Converts a virtual interrupt priority to the closest equivalent
- * (equal or higher) interrupt level.
- */
-unsigned xthal_vpri_to_intlevel(unsigned vpri)
-{
-#if XCHAL_HAVE_INTERRUPTS
- return( XTHAL_VPRI_INTLEVEL( vpri ) );
-#else
- return( vpri );
-#endif
-}
-
-#endif
-
-#if defined(__SPLIT__intlevel_to_vpri)
-
-/*
- * xthal_intlevel_to_vpri
- *
- * Converts an interrupt level to a virtual interrupt priority.
- */
-unsigned xthal_intlevel_to_vpri(unsigned intlevel)
-{
-#if XCHAL_HAVE_INTERRUPTS
- return( XTHAL_VPRI( intlevel, 0xF ) );
-#else
- return( intlevel );
-#endif
-}
-
-#endif
-
-#if defined(__SPLIT__vpri_int_enable)
-
-/*
- * xthal_int_enable
- *
- * Enables given set of interrupts, and returns previous enabled-state of these interrupts.
- */
-unsigned xthal_int_enable(unsigned mask)
-{
-#if XCHAL_HAVE_INTERRUPTS
- unsigned prev_enabled, syncmask;
-
- xthal_vpri_lock();
- prev_enabled = Xthal_vpri_enabled | Xthal_tram_enabled;
-
- /* Figure out which bits must go in Xthal_tram_enabled: */
- syncmask = (mask & Xthal_tram_pending & Xthal_tram_sync);
- if( syncmask != 0 ) {
- Xthal_tram_enabled |= syncmask;
- mask &= ~syncmask;
- /*
- * If we are re-enabling a pending trampolined interrupt,
- * there is a possibility that the level-1 software interrupt
- * is no longer pending, having already occurred (without processing
- * the trampoline because it was disabled). So we have to
- * ensure that the level-1 software interrupt used for trampolining
- * is pending.
- * We let the BSP do this rather than the HAL, because it could
- * potentially use an external level-1 interrupt to trampoline
- * (if proper hardware was available) rather than a software interrupt.
- */
- (*Xthal_tram_trigger_fn)();
- }
- /* The rest go in the global enabled mask: */
- Xthal_vpri_enabled |= mask;
-
- xthal_vpri_unlock(); /* update INTENABLE as per current vpri */
- return( prev_enabled );
-
-#else /* XCHAL_HAVE_INTERRUPTS */
- return( 0 );
-#endif /* XCHAL_HAVE_INTERRUPTS */
-}
-
-#endif
-
-#if defined(__SPLIT__vpri_int_disable)
-
-/*
- * xthal_int_disable
- *
- * Disables given set of interrupts, and returns previous enabled-state of these interrupts.
- */
-unsigned xthal_int_disable(unsigned mask)
-{
-#if XCHAL_HAVE_INTERRUPTS
- unsigned prev_enabled;
-
- xthal_vpri_lock();
- prev_enabled = Xthal_vpri_enabled | Xthal_tram_enabled;
- Xthal_vpri_enabled &= ~mask;
- Xthal_tram_enabled &= ~mask;
- xthal_vpri_unlock(); /* update INTENABLE as per current vpri */
- return( prev_enabled );
-#else
- return( 0 );
-#endif
-}
-
-#endif
-
-#if defined(__SPLIT__set_vpri_locklevel)
-
-void xthal_set_vpri_locklevel(unsigned intlevel)
-{
-#if XCHAL_HAVE_INTERRUPTS
- if( intlevel < 1 )
- intlevel = 1;
- else if( intlevel > XCHAL_NUM_INTLEVELS )
- intlevel = XCHAL_NUM_INTLEVELS;
- Xthal_vpri_state.locklevel = intlevel;
- Xthal_vpri_state.lockvpri = XTHAL_VPRI(intlevel, 15);
-#endif
-}
-
-#endif
-
-#if defined(__SPLIT__get_vpri_locklevel)
-
-unsigned xthal_get_vpri_locklevel(void)
-{
-#if XCHAL_HAVE_INTERRUPTS
- return( Xthal_vpri_state.locklevel );
-#else
- return( 1 ); /* must return at least 1, some OSes assume this */
-#endif
-}
-
-#endif
-
-#if defined(__SPLIT__set_int_vpri)
-
-/*
- * xthal_set_int_vpri (was intSetL1Pri)
- *
- * Set the virtual (software) priority of an interrupt.
- * Note: the intlevel of an interrupt CANNOT be changed -- this is
- * set in hardware according to the core configuration file.
- *
- * intnum interrupt number (0..31)
- * vpri virtual interrupt priority (0..15, or intlevel*16+(0..15) )
- */
-int xthal_set_int_vpri(int intnum, int vpri)
-{
-#if XCHAL_HAVE_INTERRUPTS
- unsigned mask, maskoff, basepri, prevpri, intlevel, *maskp, i;
-
- /*
- * Verify parameters:
- */
- if( (unsigned)intnum >= XCHAL_NUM_INTERRUPTS || (unsigned)vpri > 0xFF )
- return( 0 ); /* error: bad parameter(s) */
- /*
- * If requested priority specifies an intlevel, it must match that
- * of the interrupt specified; otherwise (0..15) the proper intlevel of
- * the specified interrupt is assumed, and added to the parameter:
- */
- intlevel = Xthal_intlevel[intnum]; /* intnum's intlevel */
- if( intlevel == 0 || intlevel > XCHAL_NUM_INTLEVELS )
- return( 0 ); /* error: no support for setting priority of NMI etc. */
- basepri = intlevel << 4; /* intnum's base soft-pri. */
- if( vpri > 0x0F ) { /* intlevel portion given? */
- if( (vpri & 0xF0) != basepri ) /* then it must be correct */
- return( 0 ); /* error: intlevel mismatch */
- vpri &= 0x0F; /* remove it */
- }
-
- mask = 1L << intnum;
-
- /*
- * Lock interrupts during virtual priority data structure updates:
- */
- xthal_vpri_lock();
-
- /*
- * Update virtual priority of 'intnum':
- */
- prevpri = Xthal_int_vpri[intnum]; /* save for return value */
- Xthal_int_vpri[intnum] = basepri | vpri;
- /* This interrupt must only be enabled at virtual priorities lower than its own: */
- for( i = 0; i < vpri; i++ )
- Xthal_vpri_enablemap[0][basepri++] |= mask;
- maskoff = ~mask;
- for( ; i <= 0x0F; i++ )
- Xthal_vpri_enablemap[0][basepri++] &= maskoff;
-
- /*
- * Update the prioritization table used to resolve priorities by binary search:
- */
- /* Remove interrupt <intnum> from prioritization table: */
- maskp = Xthal_vpri_resolvemap[intlevel-1];
- for (i=0; i<16; i++)
- maskp[i] &= maskoff;
- /* Add interrupt <intnum> to prioritization table at its (new) given priority: */
- if( vpri & 0x1 )
- maskp[vpri] |= mask;
- if( vpri & 0x2 )
- maskp[vpri & 0xE] |= mask;
- if( vpri & 0x4 )
- maskp[vpri & 0xC] |= mask;
- if( vpri & 0x8 )
- maskp[vpri & 0x8] |= mask;
-
- /*
- * Unlock interrupts (back to current level) and update INTENABLE:
- */
- xthal_vpri_unlock();
-
- return( prevpri );
-#else /* XCHAL_HAVE_INTERRUPTS */
- return( 0 );
-#endif /* XCHAL_HAVE_INTERRUPTS */
-} /* xthal_set_int_vpri */
-
-#endif
-
-#if defined(__SPLIT__get_int_vpri)
-
-int xthal_get_int_vpri(int intnum)
-{
-#if XCHAL_HAVE_INTERRUPTS
- if( (unsigned)intnum >= XCHAL_NUM_INTERRUPTS )
- return( 0 ); /* error: bad parameter */
- return( Xthal_int_vpri[intnum] );
-#else
- return( 0 );
-#endif
-}
-
-
-#endif
-
-#if defined(__SPLIT__trampolines)
-
-
- /*
- SUPPORT FOR TRAMPOLINES
-
- NOTE: trampolining is a special case.
- There are two ways (defined here) to trampoline down
- from a high-level interrupt to a level-one interrupt.
-
- a) Synchronous (restrained) trampolining.
- Trampolining without clearing the high-level interrupt,
- letting the level-one interrupt handler clear the
- source of the interrupt.
- Here the high-level interrupt must be kept disabled
- while trampolining down, and re-enabled after the
- level-one interrupt handler completes.
- This is what one might do to "convert" a high-level
- interrupt into a level-one interrupt.
- The high-level interrupt handler code can be generic.
- [One could argue this type of trampolining isn't required,
- which may? be true...]
- b) Asynchronous (free) trampolining.
- Trampolining when clearing the high-level interrupt
- right away in the high-level interrupt handler.
- Here the high-level interrupt is allowed to remain
- enabled while trampolining occurs. This is very
- useful when some processing must occur with low
- latency, but the rest of the processing can occur
- at lower (eg. level-one) priority. It is particularly
- useful when the lower-priority processing occurs
- for only some of the high-level interrupts.
- Of course this requires custom assembler code to
- handle the high-level interrupt and clear the source
- of the interrupt, so the high-level interrupt handler
- cannot be generic (as opposed to synchronous trampolining).
-
- In both cases, a level-one software interrupt is used
- for trampolining (one could also trampoline from level
- m to n, m > n, n > 1, but that isn't nearly as useful;
- it's generally the ability to execute C code and
- to process exceptions that is sought after).
-
- Default trampolining support is currently implemented as follows.
-
- Trampoline handler:
-
- A high-level interrupt is considered enabled if *either*
- its INTENABLE bit or its xt_tram_ints bit is set
- (note that both should never be set at the same time).
-
- */
-
-
-/* These are described in xtensa/hal.h (assumed initialized to zero, in BSS): */
-unsigned Xthal_tram_pending;
-unsigned Xthal_tram_enabled;
-unsigned Xthal_tram_sync;
-
-
-
-XtHalVoidFunc* xthal_set_tram_trigger_func( XtHalVoidFunc *trigger_fn )
-{
-#if XCHAL_HAVE_INTERRUPTS
- XtHalVoidFunc *fn;
-
- fn = Xthal_tram_trigger_fn;
- Xthal_tram_trigger_fn = trigger_fn;
- return( fn );
-#else
- (void)trigger_fn;
- return( 0 );
-#endif
-}
-
-
-/*
- * xthal_tram_set_sync
- *
- * Configure type of trampoline for a high-level interrupt.
- * By default any trampoline is asynchronous, this need only
- * be called to tell the Core HAL that a high-level interrupt
- * will be using synchronous trampolining (down to a level-1 interrupt).
- *
- * intnum interrupt number (0 .. 31)
- * sync 0 = async, 1 = synchronous
- *
- * Returns previous sync state of interrupt (0 or 1)
- * or -1 if invalid interrupt number provided.
- */
-int xthal_tram_set_sync( int intnum, int sync )
-{
-#if XCHAL_HAVE_INTERRUPTS
- unsigned mask;
- int prev;
-
- if( (unsigned)intnum >= XCHAL_NUM_INTERRUPTS )
- return( -1 );
- mask = 1L << intnum;
- prev = ((Xthal_tram_sync & mask) != 0);
- if( sync )
- Xthal_tram_sync |= mask;
- else
- Xthal_tram_sync &= ~mask;
- return( prev );
-#else /* XCHAL_HAVE_INTERRUPTS */
- return( 0 );
-#endif /* XCHAL_HAVE_INTERRUPTS */
-}
-
-
-/*
- * xthal_tram_pending_to_service
- *
- * This is called by the trampoline interrupt handler
- * (eg. by a level-one software interrupt handler)
- * to obtain the bitmask of high-level interrupts
- * that it must service.
- * Returns that bitmask (note: this can sometimes be zero,
- * eg. if currently executing level-one code disables the high-level
- * interrupt before the trampoline handler has a chance to run).
- *
- * This call automatically clears the trampoline pending
- * bits for the interrupts in the returned mask.
- * So the caller *must* process all interrupts that have
- * a corresponding bit set if the value returned by this function
- * (otherwise those interrupts may likely be lost).
- *
- * This function should be called with level-one interrupts disabled
- * (via INTENABLE; can't be via PS.INTLEVEL because this is C code).
- */
-unsigned xthal_tram_pending_to_service( void )
-{
-#if XCHAL_HAVE_INTERRUPTS
- unsigned service_mask;
-
- service_mask = ( Xthal_tram_pending
- & (Xthal_vpri_enabled | Xthal_tram_enabled) ) ;
-
- /*
- * Clear trampoline pending bits.
- * Each bit must be cleared *before* processing of the corresponding
- * interrupt occurs, to avoid missing interrupts.
- * Here we just clear all bits for simplicity and convenience.
- */
- Xthal_tram_pending &= ~service_mask;
-
- return( service_mask );
-#else /* XCHAL_HAVE_INTERRUPTS */
- return( 0 );
-#endif /* XCHAL_HAVE_INTERRUPTS */
-}
-
-/*
- * xthal_tram_done
- *
- * This is called by the trampoline interrupt handler
- * (eg. by a level-one software interrupt handler)
- * to indicate that processing of a trampolined interrupt
- * (eg. one or more of the bits it received from
- * xthal_tram_acknowledge()) has completed.
- *
- * For asynchronously trampolined interrupt(s), there is nothing to do.
- * For synchronously trampolined interrupt(s), the high-level
- * interrupt(s) must be re-enabled (presumably the level-one
- * interrupt handler that just completed has cleared the source
- * of the high-level interrupt).
- *
- * This function should be called with level-one interrupts disabled
- * (via INTENABLE; can't be via PS.INTLEVEL because this is C code).
- */
-void xthal_tram_done( unsigned serviced_mask )
-{
-#if XCHAL_HAVE_INTERRUPTS
- serviced_mask &= Xthal_tram_enabled; /* sync. trampolined interrupts that completed */
- Xthal_tram_enabled &= ~serviced_mask;
- xthal_int_enable( serviced_mask );
-#endif
-}
-
-#endif
-
-#if defined(__SPLIT__deprecated)
-
-
-/**********************************************************************/
-
-#ifdef INCLUDE_DEPRECATED_HAL_CODE
-/* These definitions were present in an early beta version of the HAL and should not be used: */
-const unsigned Xthal_num_int_levels = XCHAL_NUM_INTLEVELS;
-const unsigned Xthal_num_ints = XCHAL_NUM_INTERRUPTS;
-__asm__(".global Xthal_int_level_mask\n" ".set Xthal_int_level_mask, Xthal_intlevel_mask+4");
-__asm__(".global Xthal_int_level1_to_n_mask\n" ".set Xthal_int_level1_to_n_mask, Xthal_intlevel_andbelow_mask+8");
-/*const unsigned Xthal_int_level_mask[15] = { XCHAL_INTLEVEL_MASKS }; ... minus the first entry ...*/
-/*const unsigned Xthal_int_level1_to_n_mask[14] = { XCHAL_INTLEVEL_ANDBELOW_MASKS }; ... minus the first two entries ...*/
-const unsigned Xthal_int_level[32] = { XCHAL_INT_LEVELS };
-const unsigned Xthal_int_type_edge = XCHAL_INTTYPE_MASK_EXTERN_EDGE;
-const unsigned Xthal_int_type_level = XCHAL_INTTYPE_MASK_EXTERN_LEVEL;
-const unsigned Xthal_int_type_timer = XCHAL_INTTYPE_MASK_TIMER;
-const unsigned Xthal_int_type_software = XCHAL_INTTYPE_MASK_SOFTWARE;
-#endif /* INCLUDE_DEPRECATED_HAL_CODE */
-
-
-#endif /* SPLITs */
-
diff --git a/src/arch/xtensa/smp/hal/mem_ecc_parity.S b/src/arch/xtensa/smp/hal/mem_ecc_parity.S
deleted file mode 100644
index 2a85a3e..0000000
--- a/src/arch/xtensa/smp/hal/mem_ecc_parity.S
+++ /dev/null
@@ -1,285 +0,0 @@
-//
-// mem_ecc_parity.S - utility routines for the local memory ECC/parity option
-// (memory error checking and exceptions)
-//
-// $Id: //depot/rel/Foxhill/dot.8/Xtensa/OS/hal/mem_ecc_parity.S#1 $
-
-// Copyright (c) 2006-2010 Tensilica Inc.
-//
-// Permission is hereby granted, free of charge, to any person obtaining
-// a copy of this software and associated documentation files (the
-// "Software"), to deal in the Software without restriction, including
-// without limitation the rights to use, copy, modify, merge, publish,
-// distribute, sublicense, and/or sell copies of the Software, and to
-// permit persons to whom the Software is furnished to do so, subject to
-// the following conditions:
-//
-// The above copyright notice and this permission notice shall be included
-// in all copies or substantial portions of the Software.
-//
-// THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
-// EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
-// MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
-// IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY
-// CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
-// TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
-// SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
-
-#include <xtensa/coreasm.h>
-
-
-/*
- * For most functions, the link-time HAL defines two entry points:
- * xthal_...() and xthal_..._nw(). The former is the main entry point
- * invoked from C code, or assembly code that follows the C ABI.
- * The latter is for use in assembly code that cannot easily follow
- * all the requirements of the windowed ABI, e.g. in exception handlers;
- * these use the call0 ABI instead (in most cases; some use their own conventions).
- *
- * When software tools are configured to use the call0 ABI, both variants
- * are identical (with some exceptions as noted). To avoid duplicating
- * code, we define both labels for the same function body. The Makefile
- * defines __SPLIT__..._nw macros with windowed ABI but not with Call0 ABI.
- * Use SYM_NW() for the _nw variants defined with the __SPLIT_..._nw macros,
- * i.e. for call0 ABI variants when windowed ABI is in use; these are not
- * C callable so SYM_NW() does not specify .type information.
- * Use SYMBOL() otherwise, which defines both symbols if call0 ABI is selected.
- */
-
-#if defined (__XTENSA_CALL0_ABI__)
-# define SYMBOL(x) .global x ; .type x,@function ; \
- .global x ## _nw ; .type x ## _nw,@function ; \
- .align 4 ; x: ; x ## _nw:
-#else
-# define SYMBOL(x) .global x ; .type x,@function ; .align 4 ; x:
-#endif
-#define SYM_NW(x) .global x ; .align 4 ; x:
-
-
-/* Compute smaller of I and D cache line sizes: */
-#if XCHAL_ICACHE_LINEWIDTH < XCHAL_DCACHE_LINEWIDTH && XCHAL_ICACHE_SIZE > 0
-# define CACHE_LINEWIDTH_MIN XCHAL_ICACHE_LINEWIDTH
-# define CACHE_LINESIZE_MIN XCHAL_ICACHE_LINESIZE
-#else
-# define CACHE_LINEWIDTH_MIN XCHAL_DCACHE_LINEWIDTH
-# define CACHE_LINESIZE_MIN XCHAL_DCACHE_LINESIZE
-#endif
-
-
- .text
-
-//------------------------------------------------------------------------
-// Inject errors into instruction and/or data RAMs, or cache data or tags
-//------------------------------------------------------------------------
-
-#if defined(__SPLIT__memep_inject_error)
-
-// void xthal_memep_inject_error(void *addr, int size, int flags);
-// where:
-// addr (a2) pointer to local memory, or cache address
-// size (a3) size in bytes (gets aligned to words or lines)
-// flags (a4) is a combination of the following bits:
-// bit 31-5: (reserved)
-// bit 4: 0 = inject non-correctable error,
-// 16 = inject correctable error (if ECC)
-// bit 3: (reserved)
-// bit 2: 0 = local memory, 4 = cache
-// bit 1: 0 = data cache, 2 = instruction cache
-// bit 0: 0 = cache data, 1 = cache tag
-//
-// (note: data cache data is handled same as local memories;
-// to access specific dcache data entries, you have to setup
-// a region or page in cache-isolate mode yourself)
-
-SYMBOL(xthal_memep_inject_error)
- abi_entry
-
-#if XCHAL_HAVE_MEM_ECC_PARITY
-
- // These MOVIs may be L32Rs, load them before enabling test mode:
- movi a6, 0x02020202 // XOR'ing this creates a correctable error
- bbsi.l a4, 4, 1f // branch if correctable error requested
- movi a6, 0x03030303 // XOR'ing this creates a non-correctable error
-1:
-
- // Lock out all interrupts, to avoid interrupt handlers running with
- // test mode enabled (corrupting their stores, likely leading to
- // non-correctable memory errors).
- //
- // If NMI is possible, you're toast
- // (no stores during NMI handler will have properly computed ECC/parity bits)
- // although you might make the NMI handler check MESR.ERRTEST and save/clear
- // it if it's set on entry, so that its stores work correctly.
- //
- // If memory exceptions are possible, might be okay as long as the
- // handler checks whether test mode is on, and turns it off temporarily
- // to do its work.
- //
-# if XCHAL_HAVE_INTERRUPTS
- rsil a11, 15
-# endif
-
- // Save current MESR and set test mode:
-
- rsr.mesr a8
- bbsi.l a8, MESR_ERRTEST_SHIFT, .Lproceed // already in test mode?
- addmi a9, a8, MESR_ERRTEST // enable test mode
- bbci.l a8, MESR_ERRENAB_SHIFT, 1f
- addmi a9, a9, - MESR_ERRENAB // disable error checks
-1: xsr.mesr a9
- beq a8, a9, .Lproceed // clean update, continue
- bbci.l a9, MESR_RCE_SHIFT, .Lproceed // we likely restored a lost RCE, just keep it
- // At this point, either we:
- // a) cleared an RCE record that got created between RSR and XSR
- // b) cleared LCE bits that got set between RSR and XSR
- // c) more eclectic, and presumably much less likely, cases of
- // RCE/LCE bits being cleared and set again between RSR and XSR
- // due to multiple memory errors and memory error exceptions
- // in that period; for now, we ignore this possibility
- // (decreasing returns on addressing these arbitrarily complex cases)
- // Assuming (a) or (b), restore the bits we took away.
- //addmi a8, a8, MESR_ERRTEST
- addmi a9, a9, MESR_ERRTEST
- bbci.l a9, MESR_ERRENAB_SHIFT, 1f
- addmi a9, a9, - MESR_ERRENAB // disable error checks
-1: wsr.mesr a9
- //xsr.mesr a9
- //beq a8, a9, .Lproceed // updated fine, continue
- //
- // Above we could have used XSR instead of WSR.
- // However, it's not clear at this point what's the cleanest thing
- // to do if what we read back doesn't match what we expected,
- // because at that point we have multiple errors to deal with.
- // Unless we have code here to handle (fix and/or log) these errors,
- // we have to chuck something away or write a bunch more code to
- // handle another LCE bit getting set etc (also starting to be
- // a low probability occurrence).
-.Lproceed:
- // Test mode enabled. From this point until we restore MESR,
- // the only loads and stores done are for injecting errors.
-
-# if XCHAL_ICACHE_SIZE || XCHAL_DCACHE_SIZE
- bbci.l a4, 2, .L_inject_local // branch if injecting to local memory
- bbsi.l a4, 1, .L_inject_icache // branch if injecting to icache
- // Inject errors in dcache:
- bbci.l a4, 0, .L_inject_local // branch if injecting to dcache data
-# if XCHAL_DCACHE_SIZE && XCHAL_HAVE_DCACHE_TEST
- // Inject errors in dcache tags:
-
- // Round addr/size to fully rather than partially cover
- // all aligned cache lines:
- extui a9, a2, 0, XCHAL_DCACHE_LINEWIDTH
- sub a2, a2, a9
- add a3, a3, a9
- addi a3, a3, XCHAL_DCACHE_LINESIZE-1
- srli a3, a3, XCHAL_DCACHE_LINEWIDTH // size in cache lines
-
- floopgtz a3, .Ldctagloop
- ldct a9, a2 // load dcache line tag
- rsr.mecr a7 // get check bits
- xor a7, a7, a6 // ECC: single-bit error; Parity: NO-OP
- wsr.mecr a7 // setup modified check bits
- sdct a9, a2 // store tag with modified check bits
- addi a2, a2, XCHAL_DCACHE_LINESIZE // increment to next line
- floopend a3, .Ldctagloop
-# endif /* have dcache */
- j .L_inject_done
-
- // Inject errors in icache:
-.L_inject_icache:
-# if XCHAL_ICACHE_SIZE && XCHAL_HAVE_ICACHE_TEST
- bbci.l a4, 0, .L_inject_icw // branch if injecting to icache data
-
- // Inject errors in icache tags:
- // Round addr/size to fully rather than partially cover
- // all aligned cache lines:
- extui a9, a2, 0, XCHAL_ICACHE_LINEWIDTH
- sub a2, a2, a9
- add a3, a3, a9
- addi a3, a3, XCHAL_ICACHE_LINESIZE-1
- srli a3, a3, XCHAL_ICACHE_LINEWIDTH // size in cache lines
-
- floopgtz a3, .Lictagloop
- lict a9, a2 // load icache line tag
- rsr.mecr a7 // get check bits
- xor a7, a7, a6 // ECC: single-bit error; Parity: NO-OP
- wsr.mecr a7 // setup modified check bits
- sict a9, a2 // store tag with modified check bits
- addi a2, a2, XCHAL_ICACHE_LINESIZE // increment to next line
- floopend a3, .Lictagloop
- j .L_inject_done
-
-.L_inject_icw:
-# if XCHAL_ICACHE_ACCESS_SIZE <= 4 /* SICW does not work usefully (replicates data) if accessWidth > 32 bits */
- // Inject errors in icache data words:
- // Round addr/size to fully rather than partially cover
- // all aligned 32-bit words:
- extui a9, a2, 0, 2
- sub a2, a2, a9
- add a3, a3, a9
- addi a3, a3, 3
- srli a3, a3, 2 // size in words
-
- floopgtz a3, .Licwloop
- licw a9, a2 // load word of icache line data
- rsr.mecr a7 // get check bits
- xor a7, a7, a6 // ECC: single-bit error; Parity: NO-OP
- wsr.mecr a7 // setup modified check bits
- sicw a9, a2 // store data with modified check bits
- addi a2, a2, 4 // increment to next word
- floopend a3, .Licwloop
-# endif
-# endif /* have icache */
- j .L_inject_done
-# endif /* have icache or dcache */
-
-.L_inject_local:
- // Round addr/size to fully rather than partially cover
- // all aligned 32-bit words:
- extui a9, a2, 0, 2
- sub a2, a2, a9
- add a3, a3, a9
- addi a3, a3, 3
- srli a3, a3, 2 // size in words
-
- floopgtz a3, .Lendloop
- l32i a9, a2, 0 // load data
- rsr.mecr a7 // get check bits
- xor a7, a7, a6 // ECC: single-bit error; Parity: NO-OP
- wsr.mecr a7 // setup modified check bits
- s32i a9, a2, 0 // store data with modified check bits
- addi a2, a2, 4 // increment to next word
- floopend a3, .Lendloop
-
-.L_inject_done:
- // Restore MESR (a8 is the saved original MESR):
- bbsi.l a8, MESR_ERRTEST_SHIFT, 2f // was already in test mode
- rsr.mesr a6
- addmi a9, a6, - MESR_ERRTEST // disable test mode
- bbci.l a8, MESR_ERRENAB_SHIFT, 1f
- addmi a9, a9, MESR_ERRENAB // enable error checks
-1: xsr.mesr a9
- beq a6, a9, 2f // clean update, done
- bbci.l a9, MESR_RCE_SHIFT, 2f // we likely restored a lost RCE, just keep it
- addmi a9, a9, - MESR_ERRTEST
- bbci.l a8, MESR_ERRENAB_SHIFT, 1f
- addmi a9, a9, MESR_ERRENAB // disable error checks
-1: wsr.mesr a9
-2:
-
- // Restore PS.INTLEVEL:
-# if XCHAL_HAVE_INTERRUPTS
- wsr.ps a11
- rsync
-# endif
-#endif /* XCHAL_HAVE_MEM_ECC_PARITY */
-
- abi_return
-
- .size xthal_memep_inject_error, . - xthal_memep_inject_error
-
-
-#endif /*split*/
-
-//----------------------------------------------------------------------
-
diff --git a/src/arch/xtensa/smp/hal/memcopy.S b/src/arch/xtensa/smp/hal/memcopy.S
deleted file mode 100644
index 5cabcf1..0000000
--- a/src/arch/xtensa/smp/hal/memcopy.S
+++ /dev/null
@@ -1,409 +0,0 @@
-/*
- * Core HAL library functions xthal_memcpy and xthal_bcopy
- */
-
-/*
- * Copyright (c) 2003, 2006, 2010 Tensilica Inc.
- *
- * Permission is hereby granted, free of charge, to any person obtaining
- * a copy of this software and associated documentation files (the
- * "Software"), to deal in the Software without restriction, including
- * without limitation the rights to use, copy, modify, merge, publish,
- * distribute, sublicense, and/or sell copies of the Software, and to
- * permit persons to whom the Software is furnished to do so, subject to
- * the following conditions:
- *
- * The above copyright notice and this permission notice shall be included
- * in all copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
- * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
- * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
- * IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY
- * CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
- * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
- * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
- */
-
-#include <xtensa/coreasm.h>
-
-
-#ifdef __XTENSA_EB__
-# define BL(b,l) b
-#else
-# define BL(b,l) l
-#endif
-
- .macro srcel r, early, late // combine early and late words, shift into \r
- src \r, BL(\early,\late), BL(\late,\early)
- .endm
-
- .macro ssa8f r // set shift-amount for shift *from* given 2-bit alignment
- BL(ssa8b,ssa8l) \r
- .endm
-
- .macro ssa8t r // set shift-amount for shift *to* given 2-bit alignment
- BL(ssa8l,ssa8b) \r // (reverse of ssa8f)
- .endm
-
- .macro s2ll r, s // shift-to-later logical (away from zero-addressed byte)
- BL(srl,sll) \r, \s
- .endm
-
- .macro s2el r, s // shift-to-early logical (towards zero-addressed byte)
- BL(sll,srl) \r, \s
- .endm
-
-/*
- * void *xthal_memcpy(void *dst, const void *src, size_t len);
- * void *xthal_bcopy(const void *src, void *dst, size_t len);
- *
- * This function is intended to do the same thing as the standard
- * library function memcpy() (or bcopy()) for most cases.
- * However, it uses strictly 32-bit load and store instructions
- * to copy data. This ensures this function will work
- * where the source and/or destination references an
- * instruction RAM or ROM, which can only be accessed
- * using l32i (IRAM+IROM) and s32i (IRAM).
- *
- * The bcopy version is provided here to avoid the overhead
- * of an extra call, for callers that require this convention.
- *
- * The (general case) algorithm is as follows:
- * If destination is unaligned, align it by copying 1 to 3 bytes.
- * If source is aligned,
- * do 16 bytes with a loop, and then finish up with
- * 8, 4, and 0-3 byte copies conditional on the length;
- * else (if source is unaligned),
- * do the same, but use SRC to align the source data.
- * This code tries to use fall-through branches for the common
- * case of aligned source and destination and multiple
- * of 4 length.
- *
- * Register use:
- * a0/ return address
- * a1/ stack pointer
- * a2/ return value
- * a3/ src
- * a4/ length
- * a5/ dst
- * a6/ tmp
- * a7/ tmp
- * a8/ tmp
- * a9/ tmp
- * a10/ tmp
- * a11/ tmp
- * a12/ tmp
- */
-
-/* xthal_bcopy and xthal_memcpy need to allocate the same stack size
- * on entry since they share the same function-return code. Also,
- * there is more than one return point. */
-
-#define SAVE_A0 0
-#define SAVE_A3 4
-#define SAVE_A4 8
-#define SAVE_A5 12
-#define SAVE_A12 16
-#define STKSIZE 32
-
-
- .text
- .align 4
- .global xthal_bcopy
- .type xthal_bcopy,@function
-xthal_bcopy:
-#ifdef __XTENSA_CALL0_ABI__
- addi sp, sp, -STKSIZE
- s32i a12, a1, SAVE_A12
-#else
- entry sp, 32 // allow for call8 below
-#endif
- // a2=src, a3=dst, a4=len
- mov a5, a3 // copy dst so that a2 is return value
- mov a3, a2
- mov a2, a5
- j .Lcommon // go to common code for memcpy+bcopy
-
- .size xthal_bcopy, . - xthal_bcopy
-
-
-
-/*
- * Destination is unaligned
- */
-
- .align 4
-xthal_memcpy.prefixcode: // purely for purpose of .size
-.Ldstunaligned:
- mov a10, a5
- mov a11, a3
- movi a12, 4
- sub a6, a12, a6 // number of bytes to copy for dst alignment
- mov a12, a6
-#ifdef __XTENSA_CALL0_ABI__
- s32i a0, a1, SAVE_A0 // preserve live registers
- s32i a3, a1, SAVE_A3
- s32i a4, a1, SAVE_A4
- s32i a5, a1, SAVE_A5
- call0 xthal_copy123
- l32i a0, a1, SAVE_A0 // restore live registers
- l32i a3, a1, SAVE_A3
- l32i a4, a1, SAVE_A4
- l32i a5, a1, SAVE_A5
- mov a6, a12 // restore a6 from callee-saved register
-#else
- call8 xthal_copy123
-#endif
- add a5, a5, a6
- add a3, a3, a6
- sub a4, a4, a6
- j .Ldstaligned
-
- // Not sure how else to count code that precedes a function, in .size:
- .size xthal_memcpy.prefixcode, . - xthal_memcpy.prefixcode
-
-
- .align 4
- .global xthal_memcpy
- .type xthal_memcpy,@function
-xthal_memcpy:
-#ifdef __XTENSA_CALL0_ABI__
- addi sp, sp, -STKSIZE
- s32i a12, a1, SAVE_A12
-#else
- entry sp, 32 // allow for call8 below
-#endif
- // a2=dst, a3=src, a4=len
- mov a5, a2 // copy dst so that a2 is return value
-.Lcommon:
-#ifdef __XTENSA_CALL0_ABI__
- /*
- * have to restore the stack
- */
- _bgeui a4, 4, 1f
- mov a12, a0 // preserve return address
- call0 xthal_copy123
- mov a0, a12 // restore return address
- l32i a12, a1, SAVE_A12
- addi sp, sp, STKSIZE
- ret
-1:
-#else
- bltui a4, 4, xthal_copy123_pastentry // NOTE: sometimes relaxes
-#endif
-
- extui a6, a2, 0, 2 // destination unalignment offset
- bnez a6, .Ldstunaligned // align the destination
-.Ldstaligned: // return here once dst is aligned
- srli a7, a4, 4 // number of loop iterations of 16-bytes each
- extui a11, a3, 0, 2 // source unalignment offset
- _bnez a11, .Lsrcunaligned // if source not aligned, use shifting copy
- /*
- * Destination and source are 32-bit aligned, use 32-bit copy.
- */
-#if XCHAL_HAVE_LOOPS
- loopnez a7, .Loop1done
-#else /* !XCHAL_HAVE_LOOPS */
- beqz a7, .Loop1done
- slli a8, a7, 4
- add a8, a8, a3 // a8 = end of last 16B source chunk
-#endif /* !XCHAL_HAVE_LOOPS */
-.Loop1:
- l32i a6, a3, 0
- l32i a7, a3, 4
- s32i a6, a5, 0
- l32i a6, a3, 8
- s32i a7, a5, 4
- l32i a7, a3, 12
- s32i a6, a5, 8
- addi a3, a3, 16
- s32i a7, a5, 12
- addi a5, a5, 16
-#if !XCHAL_HAVE_LOOPS
- blt a3, a8, .Loop1
-#endif /* !XCHAL_HAVE_LOOPS */
-.Loop1done:
- bbci.l a4, 3, .L2
- // copy 8 bytes
- l32i a6, a3, 0
- l32i a7, a3, 4
- addi a3, a3, 8
- s32i a6, a5, 0
- s32i a7, a5, 4
- addi a5, a5, 8
-.L2:
- bbci.l a4, 2, .L3
- // copy 4 bytes
- l32i a6, a3, 0
- addi a3, a3, 4
- s32i a6, a5, 0
- addi a5, a5, 4
-.L3:
- // Copy last 0 to 3 bytes using 32-bit accesses (aligned source and destination):
- extui a4, a4, 0, 2 // any bytes to copy?
- beqz a4, 1f // if not, skip this to avoid extraneous loads/stores
- l32i a6, a3, 0 // get source word
- l32i a7, a5, 0 // get destination word
- ssa8f a4 // shift from length (end of source)
- s2ll a6, a6 // align source to last byte
- s2el a7, a7 // align parts of a7 following modified bytes, to early byte
- ssa8t a4 // shift to end of modified destination (length)
- srcel a7, a6, a7 // combine source with late-dst to form last word
- s32i a7, a5, 0 // update last word
-1:
-
-#ifdef __XTENSA_CALL0_ABI__
- l32i a12, a1, SAVE_A12
- addi sp, sp, STKSIZE
- ret
-#else
- retw
-#endif
-
- .size xthal_memcpy, . - xthal_memcpy
-
-
- // void xthal_copy123(dst, src, len);
- //
- // Copy from 0 to 3 bytes, using only 32-bit loads and stores,
- // with arbitrarily aligned source and destination.
- //
- // arg1 = a2 = dst
- // arg2 = a3 = src
- // arg3 = a4 = len
-
- .global xthal_copy123
- .type xthal_copy123,@function
- .align 4
-xthal_copy123:
- abi_entry
-
-xthal_copy123_pastentry:
- _beqz a4, cdone // don't load or store if zero bytes
- // First get the bytes:
- movi a5, ~3
- and a5, a3, a5 // align src address
- l32i a6, a5, 0
- l32i a7, a5, 4
- ssa8f a3
- srcel a3, a6, a7
- // a3 now contains source bytes, aligned to 1st byte (memory order)
- // (source address is no longer needed at this point)
-
- // Does destination span two words?:
- extui a10, a2, 0, 2 // destination alignment
- sub a5, a2, a10 // align destination address
- l32i a8, a5, 0 // get first destination word regardless
- add a6, a10, a4 // dst_align + len
- ssa8f a2 // shift from dst_align (to 1st or last byte)
- s2ll a10, a8 // a10 = first part of destination, aligned to last byte
- bltui a6, 4, oneword // branch if destination contained in single word
-
- // Two-word destination case:
- l32i a8, a5, 4 // get second word
- ssa8t a2 // shift to dst_align
- srcel a10, a10, a3 // with a10 in early bytes, a3 in later bytes
- s32i a10, a5, 0 // update first word
- addi a5, a5, 4 // advance to last word for common code below
- //movi a10, 0 // not needed, gets dropped
-
-oneword:
- // One-word (and two-word) destination case:
- // a8 = contents of last destination word
- // a10 = early part of a8 preceding modified bytes, shifted towards last byte
- //
- ssa8f a4 // shift from length (end of source)
- srcel a3, a10, a3 // combine early-destination with source, aligned to last byte
-
- ssa8f a6 // shift from end of modified destination (dst_align+len)
- s2el a8, a8 // align parts of a8 following modified bytes, to early byte
- ssa8t a6 // shift to end of modified destination (dst_align+len)
- srcel a8, a3, a8 // combine early-dst+source with late-dst to form last word
- s32i a8, a5, 0 // update last word
-cdone: abi_return // return dst
-
-/*
- * Destination is aligned, Source is unaligned
- */
-
- .align 4
-.Lsrcunaligned:
- // Copy 16 bytes per iteration for word-aligned dst and unaligned src
- ssa8f a3 // set shift amount from byte offset
-#define SIM_CHECKS_ALIGNMENT 1 /* set to 1 when running on ISS (simulator) with the
- lint or ferret client, or 0 to save a few cycles */
-#if XCHAL_UNALIGNED_LOAD_EXCEPTION || SIM_CHECKS_ALIGNMENT
- extui a11, a3, 0, 2 // save unalignment offset for below
- sub a3, a3, a11 // align a3
-#endif
- l32i a6, a3, 0 // load first word
-#if XCHAL_HAVE_LOOPS
- loopnez a7, .Loop2done
-#else /* !XCHAL_HAVE_LOOPS */
- beqz a7, .Loop2done
- slli a10, a7, 4
- add a10, a10, a3 // a10 = end of last 16B source chunk
-#endif /* !XCHAL_HAVE_LOOPS */
-.Loop2:
- l32i a7, a3, 4
- l32i a8, a3, 8
- srcel a6, a6, a7
- s32i a6, a5, 0
- l32i a9, a3, 12
- srcel a7, a7, a8
- s32i a7, a5, 4
- l32i a6, a3, 16
- srcel a8, a8, a9
- s32i a8, a5, 8
- addi a3, a3, 16
- srcel a9, a9, a6
- s32i a9, a5, 12
- addi a5, a5, 16
-#if !XCHAL_HAVE_LOOPS
- blt a3, a10, .Loop2
-#endif /* !XCHAL_HAVE_LOOPS */
-.Loop2done:
- bbci.l a4, 3, .L12
- // copy 8 bytes
- l32i a7, a3, 4
- l32i a8, a3, 8
- srcel a6, a6, a7
- s32i a6, a5, 0
- addi a3, a3, 8
- srcel a7, a7, a8
- s32i a7, a5, 4
- addi a5, a5, 8
- mov a6, a8
-.L12:
- bbci.l a4, 2, .L13
- // copy 4 bytes
- l32i a7, a3, 4
- addi a3, a3, 4
- srcel a6, a6, a7
- s32i a6, a5, 0
- addi a5, a5, 4
- mov a6, a7
-.L13:
- // Copy last 0 to 3 bytes using 32-bit accesses (shifting source, aligned destination):
- //_beqz a4[1:0], cdone // don't load or store if zero bytes
- l32i a7, a3, 4 // get source word
- l32i a3, a5, 0 // get destination word
- srcel a6, a6, a7 // source bytes, aligned to early (1st) byte
- ssa8f a4 // shift from length (end of source)
- s2ll a6, a6 // combine early-destination with source, aligned to last byte
- s2el a3, a3 // align parts of a3 following modified bytes, to early byte
- ssa8t a4 // shift to end of modified destination (length)
- srcel a3, a6, a3 // combine early-dst+source with late-dst to form last word
- s32i a3, a5, 0 // update last word
-.Ldone:
-#ifdef __XTENSA_CALL0_ABI__
- l32i a12, a1, SAVE_A12
- addi sp, sp, STKSIZE
- ret
-#else
- retw
-#endif
-
- .size xthal_copy123, . - xthal_copy123
-
diff --git a/src/arch/xtensa/smp/hal/misc.c b/src/arch/xtensa/smp/hal/misc.c
deleted file mode 100644
index 7742851..0000000
--- a/src/arch/xtensa/smp/hal/misc.c
+++ /dev/null
@@ -1,178 +0,0 @@
-//
-// misc.c - miscellaneous constants
-//
-// $Id: //depot/rel/Foxhill/dot.8/Xtensa/OS/hal/misc.c#1 $
-
-// Copyright (c) 2004-2005 Tensilica Inc.
-//
-// Permission is hereby granted, free of charge, to any person obtaining
-// a copy of this software and associated documentation files (the
-// "Software"), to deal in the Software without restriction, including
-// without limitation the rights to use, copy, modify, merge, publish,
-// distribute, sublicense, and/or sell copies of the Software, and to
-// permit persons to whom the Software is furnished to do so, subject to
-// the following conditions:
-//
-// The above copyright notice and this permission notice shall be included
-// in all copies or substantial portions of the Software.
-//
-// THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
-// EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
-// MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
-// IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY
-// CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
-// TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
-// SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
-
-#include <xtensa/config/core.h>
-
-
-// Software release info (not configuration-specific!):
-const unsigned int Xthal_release_major = XTHAL_RELEASE_MAJOR;
-const unsigned int Xthal_release_minor = XTHAL_RELEASE_MINOR;
-const char * const Xthal_release_name = XTHAL_RELEASE_NAME;
-#ifdef XTHAL_RELEASE_INTERNAL
-const char * const Xthal_release_internal = XTHAL_RELEASE_INTERNAL;
-#else
-const char * const Xthal_release_internal = 0;
-#endif
-/* Old format, for backward compatibility: */
-const unsigned int Xthal_rev_no = (XTHAL_MAJOR_REV<<16)|XTHAL_MINOR_REV;
-
-// number of registers in register window, or number of registers if not windowed
-const unsigned int Xthal_num_aregs = XCHAL_NUM_AREGS;
-const unsigned char Xthal_num_aregs_log2 = XCHAL_NUM_AREGS_LOG2;
-
-const unsigned char Xthal_memory_order = XCHAL_MEMORY_ORDER;
-const unsigned char Xthal_have_windowed = XCHAL_HAVE_WINDOWED;
-const unsigned char Xthal_have_density = XCHAL_HAVE_DENSITY;
-const unsigned char Xthal_have_booleans = XCHAL_HAVE_BOOLEANS;
-const unsigned char Xthal_have_loops = XCHAL_HAVE_LOOPS;
-const unsigned char Xthal_have_nsa = XCHAL_HAVE_NSA;
-const unsigned char Xthal_have_minmax = XCHAL_HAVE_MINMAX;
-const unsigned char Xthal_have_sext = XCHAL_HAVE_SEXT;
-const unsigned char Xthal_have_clamps = XCHAL_HAVE_CLAMPS;
-const unsigned char Xthal_have_mac16 = XCHAL_HAVE_MAC16;
-const unsigned char Xthal_have_mul16 = XCHAL_HAVE_MUL16;
-const unsigned char Xthal_have_fp = XCHAL_HAVE_FP;
-const unsigned char Xthal_have_speculation = XCHAL_HAVE_SPECULATION;
-const unsigned char Xthal_have_exceptions = XCHAL_HAVE_EXCEPTIONS;
-const unsigned char Xthal_xea_version = XCHAL_XEA_VERSION;
-const unsigned char Xthal_have_interrupts = XCHAL_HAVE_INTERRUPTS;
-const unsigned char Xthal_have_highlevel_interrupts = XCHAL_HAVE_HIGHLEVEL_INTERRUPTS;
-const unsigned char Xthal_have_nmi = XCHAL_HAVE_NMI;
-const unsigned char Xthal_have_prid = XCHAL_HAVE_PRID;
-const unsigned char Xthal_have_release_sync = XCHAL_HAVE_RELEASE_SYNC;
-const unsigned char Xthal_have_s32c1i = XCHAL_HAVE_S32C1I;
-const unsigned char Xthal_have_threadptr = XCHAL_HAVE_THREADPTR;
-
-const unsigned char Xthal_have_pif = XCHAL_HAVE_PIF;
-const unsigned short Xthal_num_writebuffer_entries = XCHAL_NUM_WRITEBUFFER_ENTRIES;
-
-const unsigned int Xthal_build_unique_id = XCHAL_BUILD_UNIQUE_ID;
-// Release info for hardware targeted by software upgrades:
-const unsigned int Xthal_hw_configid0 = XCHAL_HW_CONFIGID0;
-const unsigned int Xthal_hw_configid1 = XCHAL_HW_CONFIGID1;
-const unsigned int Xthal_hw_release_major = XCHAL_HW_VERSION_MAJOR;
-const unsigned int Xthal_hw_release_minor = XCHAL_HW_VERSION_MINOR;
-const char * const Xthal_hw_release_name = XCHAL_HW_VERSION_NAME;
-const unsigned int Xthal_hw_min_version_major = XCHAL_HW_MIN_VERSION_MAJOR;
-const unsigned int Xthal_hw_min_version_minor = XCHAL_HW_MIN_VERSION_MINOR;
-const unsigned int Xthal_hw_max_version_major = XCHAL_HW_MAX_VERSION_MAJOR;
-const unsigned int Xthal_hw_max_version_minor = XCHAL_HW_MAX_VERSION_MINOR;
-#ifdef XCHAL_HW_RELEASE_INTERNAL
-const char * const Xthal_hw_release_internal = XCHAL_HW_RELEASE_INTERNAL;
-#else
-const char * const Xthal_hw_release_internal = 0;
-#endif
-
-/* MMU related info... */
-
-const unsigned char Xthal_have_spanning_way = XCHAL_HAVE_SPANNING_WAY;
-const unsigned char Xthal_have_identity_map = XCHAL_HAVE_IDENTITY_MAP;
-const unsigned char Xthal_have_mimic_cacheattr = XCHAL_HAVE_MIMIC_CACHEATTR;
-const unsigned char Xthal_have_xlt_cacheattr = XCHAL_HAVE_XLT_CACHEATTR;
-const unsigned char Xthal_have_cacheattr = XCHAL_HAVE_CACHEATTR;
-const unsigned char Xthal_have_tlbs = XCHAL_HAVE_TLBS;
-#if XCHAL_HAVE_MPU
-const unsigned char Xthal_mmu_asid_bits = 0;
-const unsigned char Xthal_mmu_asid_kernel = 0;
-const unsigned char Xthal_mmu_rings = 0;
-const unsigned char Xthal_mmu_ring_bits = 0;
-const unsigned char Xthal_mmu_sr_bits = 0;
-const unsigned char Xthal_mmu_ca_bits = 0;
-#else
-const unsigned char Xthal_mmu_asid_bits = XCHAL_MMU_ASID_BITS;
-const unsigned char Xthal_mmu_asid_kernel = XCHAL_MMU_ASID_KERNEL;
-const unsigned char Xthal_mmu_rings = XCHAL_MMU_RINGS;
-const unsigned char Xthal_mmu_ring_bits = XCHAL_MMU_RING_BITS;
-const unsigned char Xthal_mmu_sr_bits = XCHAL_MMU_SR_BITS;
-const unsigned char Xthal_mmu_ca_bits = XCHAL_MMU_CA_BITS;
-#endif
-#if XCHAL_HAVE_TLBS
-const unsigned int Xthal_mmu_max_pte_page_size = XCHAL_MMU_MAX_PTE_PAGE_SIZE;
-const unsigned int Xthal_mmu_min_pte_page_size = XCHAL_MMU_MIN_PTE_PAGE_SIZE;
-const unsigned char Xthal_itlb_way_bits = XCHAL_ITLB_WAY_BITS;
-const unsigned char Xthal_itlb_ways = XCHAL_ITLB_WAYS;
-const unsigned char Xthal_itlb_arf_ways = XCHAL_ITLB_ARF_WAYS;
-const unsigned char Xthal_dtlb_way_bits = XCHAL_DTLB_WAY_BITS;
-const unsigned char Xthal_dtlb_ways = XCHAL_DTLB_WAYS;
-const unsigned char Xthal_dtlb_arf_ways = XCHAL_DTLB_ARF_WAYS;
-#else
-const unsigned int Xthal_mmu_max_pte_page_size = 0;
-const unsigned int Xthal_mmu_min_pte_page_size = 0;
-const unsigned char Xthal_itlb_way_bits = 0;
-const unsigned char Xthal_itlb_ways = 0;
-const unsigned char Xthal_itlb_arf_ways = 0;
-const unsigned char Xthal_dtlb_way_bits = 0;
-const unsigned char Xthal_dtlb_ways = 0;
-const unsigned char Xthal_dtlb_arf_ways = 0;
-#endif
-
-
-/* Internal memories... */
-
-const unsigned char Xthal_num_instrom = XCHAL_NUM_INSTROM;
-const unsigned char Xthal_num_instram = XCHAL_NUM_INSTRAM;
-const unsigned char Xthal_num_datarom = XCHAL_NUM_DATAROM;
-const unsigned char Xthal_num_dataram = XCHAL_NUM_DATARAM;
-const unsigned char Xthal_num_xlmi = XCHAL_NUM_XLMI;
-
-/* Define arrays of internal memories' addresses and sizes: */
-#define MEMTRIPLET(n,mem,memcap) _MEMTRIPLET(n,mem,memcap)
-#define _MEMTRIPLET(n,mem,memcap) MEMTRIPLET##n(mem,memcap)
-#define MEMTRIPLET0(mem,memcap) \
- const unsigned int Xthal_##mem##_vaddr[1] = { 0 }; \
- const unsigned int Xthal_##mem##_paddr[1] = { 0 }; \
- const unsigned int Xthal_##mem##_size [1] = { 0 };
-#define MEMTRIPLET1(mem,memcap) \
- const unsigned int Xthal_##mem##_vaddr[1] = { XCHAL_##memcap##0_VADDR }; \
- const unsigned int Xthal_##mem##_paddr[1] = { XCHAL_##memcap##0_PADDR }; \
- const unsigned int Xthal_##mem##_size [1] = { XCHAL_##memcap##0_SIZE };
-#define MEMTRIPLET2(mem,memcap) \
- const unsigned int Xthal_##mem##_vaddr[2] = { XCHAL_##memcap##0_VADDR, XCHAL_##memcap##1_VADDR }; \
- const unsigned int Xthal_##mem##_paddr[2] = { XCHAL_##memcap##0_PADDR, XCHAL_##memcap##1_PADDR }; \
- const unsigned int Xthal_##mem##_size [2] = { XCHAL_##memcap##0_SIZE, XCHAL_##memcap##1_SIZE };
-MEMTRIPLET(XCHAL_NUM_INSTROM, instrom, INSTROM)
-MEMTRIPLET(XCHAL_NUM_INSTRAM, instram, INSTRAM)
-MEMTRIPLET(XCHAL_NUM_DATAROM, datarom, DATAROM)
-MEMTRIPLET(XCHAL_NUM_DATARAM, dataram, DATARAM)
-MEMTRIPLET(XCHAL_NUM_XLMI, xlmi, XLMI)
-
-/* Timer info... */
-
-const unsigned char Xthal_have_ccount = XCHAL_HAVE_CCOUNT;
-const unsigned char Xthal_num_ccompare = XCHAL_NUM_TIMERS;
-
-#ifdef INCLUDE_DEPRECATED_HAL_CODE
-const unsigned char Xthal_have_old_exc_arch = XCHAL_HAVE_XEA1;
-const unsigned char Xthal_have_mmu = XCHAL_HAVE_TLBS;
-const unsigned int Xthal_num_regs = XCHAL_NUM_AREGS; /*DEPRECATED*/
-const unsigned char Xthal_num_irom = XCHAL_NUM_INSTROM; /*DEPRECATED*/
-const unsigned char Xthal_num_iram = XCHAL_NUM_INSTRAM; /*DEPRECATED*/
-const unsigned char Xthal_num_drom = XCHAL_NUM_DATAROM; /*DEPRECATED*/
-const unsigned char Xthal_num_dram = XCHAL_NUM_DATARAM; /*DEPRECATED*/
-const unsigned int Xthal_configid0 = XCHAL_HW_CONFIGID0;
-const unsigned int Xthal_configid1 = XCHAL_HW_CONFIGID1;
-#endif
-
diff --git a/src/arch/xtensa/smp/hal/miscellaneous.S b/src/arch/xtensa/smp/hal/miscellaneous.S
deleted file mode 100644
index 1a3ebf4..0000000
--- a/src/arch/xtensa/smp/hal/miscellaneous.S
+++ /dev/null
@@ -1,56 +0,0 @@
-//
-// miscellaneous.S - miscellaneous assembly language routines
-//
-// $Id: //depot/rel/Foxhill/dot.8/Xtensa/OS/hal/miscellaneous.S#1 $
-
-// Copyright (c) 2011 Tensilica Inc.
-//
-// Permission is hereby granted, free of charge, to any person obtaining
-// a copy of this software and associated documentation files (the
-// "Software"), to deal in the Software without restriction, including
-// without limitation the rights to use, copy, modify, merge, publish,
-// distribute, sublicense, and/or sell copies of the Software, and to
-// permit persons to whom the Software is furnished to do so, subject to
-// the following conditions:
-//
-// The above copyright notice and this permission notice shall be included
-// in all copies or substantial portions of the Software.
-//
-// THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
-// EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
-// MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
-// IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY
-// CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
-// TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
-// SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
-
-#include <xtensa/cacheasm.h>
-#include <xtensa/cacheattrasm.h>
-#include <xtensa/xtensa-versions.h>
-
-
- .text
-
-//----------------------------------------------------------------------
-// Clear any remnant register state pointing to (or containing) code.
-// Specifically, clear loop registers (LCOUNT) to avoid hardware loopback
-// from LEND to LBEGIN when new code is loaded where code containing a
-// zero-overhead loop was located. See the HAL chapter of the Tensilica
-// System Software Reference Manual for details on the use of this function.
-//----------------------------------------------------------------------
-
-#if defined(__SPLIT__clear_regcached_code) || \
- defined(__SPLIT__clear_regcached_code_nw)
-
-DECLFUNC(xthal_clear_regcached_code)
- abi_entry
-# if XCHAL_HAVE_LOOPS
- movi a2, 0
- wsr.lcount a2
-# endif
- isync_retw_nop
- abi_return
- endfunc
-
-#endif
-
diff --git a/src/arch/xtensa/smp/hal/mmu.c b/src/arch/xtensa/smp/hal/mmu.c
deleted file mode 100644
index ef41652..0000000
--- a/src/arch/xtensa/smp/hal/mmu.c
+++ /dev/null
@@ -1,93 +0,0 @@
-//
-// mmu.c - MMU related functions
-//
-// $Id: //depot/rel/Foxhill/dot.8/Xtensa/OS/hal/mmu.c#1 $
-
-// Copyright (c) 2002, 2008 Tensilica Inc.
-//
-// Permission is hereby granted, free of charge, to any person obtaining
-// a copy of this software and associated documentation files (the
-// "Software"), to deal in the Software without restriction, including
-// without limitation the rights to use, copy, modify, merge, publish,
-// distribute, sublicense, and/or sell copies of the Software, and to
-// permit persons to whom the Software is furnished to do so, subject to
-// the following conditions:
-//
-// The above copyright notice and this permission notice shall be included
-// in all copies or substantial portions of the Software.
-//
-// THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
-// EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
-// MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
-// IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY
-// CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
-// TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
-// SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
-
-#include <xtensa/config/core.h>
-
-/*
- * Convert a virtual address to a physical address
- * (through static maps only).
- * Returns 0 if successful (*paddrp is set), -1 if not (no mapping).
- */
-int xthal_static_v2p( unsigned vaddr, unsigned *paddrp /*, unsigned len, unsigned rasid*/ )
-{
-#if XCHAL_HAVE_PTP_MMU && !XCHAL_HAVE_SPANNING_WAY
- if( vaddr >= XCHAL_KSEG_CACHED_VADDR
- && vaddr <= XCHAL_KSEG_CACHED_VADDR + XCHAL_KSEG_CACHED_SIZE )
- vaddr += XCHAL_KSEG_CACHED_PADDR - XCHAL_KSEG_CACHED_VADDR;
- else if( vaddr >= XCHAL_KSEG_BYPASS_VADDR
- && vaddr <= XCHAL_KSEG_BYPASS_VADDR + XCHAL_KSEG_BYPASS_SIZE )
- vaddr += XCHAL_KSEG_BYPASS_PADDR - XCHAL_KSEG_BYPASS_VADDR;
- else if( vaddr >= XCHAL_KIO_CACHED_VADDR
- && vaddr <= XCHAL_KIO_CACHED_VADDR + XCHAL_KIO_CACHED_SIZE )
- vaddr += XCHAL_KIO_CACHED_PADDR - XCHAL_KIO_CACHED_VADDR;
- else if( vaddr >= XCHAL_KIO_BYPASS_VADDR
- && vaddr <= XCHAL_KIO_BYPASS_VADDR + XCHAL_KIO_BYPASS_SIZE )
- vaddr += XCHAL_KIO_BYPASS_PADDR - XCHAL_KIO_BYPASS_VADDR;
- else
- return( -1 ); /* no known mapping */
-#endif /* XCHAL_HAVE_PTP_MMU && !XCHAL_HAVE_SPANNING_WAY */
- *paddrp = vaddr; /* virtual == physical */
- return( 0 );
-}
-
-/*
- * Convert a physical address to a virtual address
- * (through static maps only).
- * Returns 0 if successful (*vaddrp is set), -1 if not (no mapping).
- *
- * NOTE: A physical address can be mapped from multiple virtual addresses
- * (or one or none).
- * There should be better parameter(s) to help select the mapping returned
- * (eg. cache mode, address, asid, etc), or somehow return them all.
- * Mappings returned currently assume the current RASID setting.
- */
-int xthal_static_p2v( unsigned paddr, unsigned *vaddrp, /*unsigned len, unsigned rasid,*/ unsigned cached )
-{
-#if XCHAL_HAVE_PTP_MMU && !XCHAL_HAVE_SPANNING_WAY
- if( cached ) {
- if( paddr >= XCHAL_KSEG_CACHED_PADDR
- && paddr <= XCHAL_KSEG_CACHED_PADDR + XCHAL_KSEG_CACHED_SIZE )
- paddr += XCHAL_KSEG_CACHED_VADDR - XCHAL_KSEG_CACHED_PADDR;
- else if( paddr >= XCHAL_KIO_BYPASS_PADDR
- && paddr <= XCHAL_KIO_BYPASS_PADDR + XCHAL_KIO_BYPASS_SIZE )
- paddr += XCHAL_KIO_BYPASS_VADDR - XCHAL_KIO_BYPASS_PADDR;
- else
- return -1; /* no known mapping */
- } else {
- if( paddr >= XCHAL_KSEG_BYPASS_PADDR
- && paddr <= XCHAL_KSEG_BYPASS_PADDR + XCHAL_KSEG_BYPASS_SIZE )
- paddr += XCHAL_KSEG_BYPASS_VADDR - XCHAL_KSEG_BYPASS_PADDR;
- else if( paddr >= XCHAL_KIO_CACHED_PADDR
- && paddr <= XCHAL_KIO_CACHED_PADDR + XCHAL_KIO_CACHED_SIZE )
- paddr += XCHAL_KIO_CACHED_VADDR - XCHAL_KIO_CACHED_PADDR;
- else
- return -1; /* no known mapping */
- }
-#endif /* XCHAL_HAVE_PTP_MMU && !XCHAL_HAVE_SPANNING_WAY */
- *vaddrp = paddr; /* virtual == physical */
- return( 0 );
-}
-
diff --git a/src/arch/xtensa/smp/hal/mp_asm.S b/src/arch/xtensa/smp/hal/mp_asm.S
deleted file mode 100644
index cc20343..0000000
--- a/src/arch/xtensa/smp/hal/mp_asm.S
+++ /dev/null
@@ -1,123 +0,0 @@
-//
-// mp_asm.S - multi-processor synchronization routines
-//
-// $Id$
-
-// Copyright (c) 2003, 2005, 2010 Tensilica Inc.
-//
-// Permission is hereby granted, free of charge, to any person obtaining
-// a copy of this software and associated documentation files (the
-// "Software"), to deal in the Software without restriction, including
-// without limitation the rights to use, copy, modify, merge, publish,
-// distribute, sublicense, and/or sell copies of the Software, and to
-// permit persons to whom the Software is furnished to do so, subject to
-// the following conditions:
-//
-// The above copyright notice and this permission notice shall be included
-// in all copies or substantial portions of the Software.
-//
-// THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
-// EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
-// MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
-// IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY
-// CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
-// TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
-// SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
-
-#include <xtensa/coreasm.h>
-
-
-/*
- int xthal_compare_and_set( int *address, int test_value, int set_value )
-
- Atomically sets *address to set_value if *address equals test_value.
- Returns the previous value of *address (the one compared with test_value).
-
- Uses the S32C1I instruction if available.
- S32C1I requires special support from the memory controller for
- memory accessed via the PIF interface. For this and other reasons,
- S32C1I might not work on the entire 4GB address range. This function
- does not test address validity. That is the responsibility of the
- software invoking this function.
-*/
- .text
- .align 4
- .global xthal_compare_and_set
- .type xthal_compare_and_set,@function
-
-xthal_compare_and_set:
- abi_entry
- // a2 == address
- // a3 == test value
- // a4 == set value
-
-#if XCHAL_HAVE_EXCLUSIVE
- mov a6, a4 // a6 = copy of set_value
-1:
- l32ex a5, a2 // a5 = *address, set monitor
- bne a5, a3, 2f // skip write if *address != test_value
- mov a4, a6 // a4 = set_value
- s32ex a4, a2 // *address = set_value
- getex a4 // get result of store
- beqz a4, 1b
-2:
- mov a2, a5 // a2 = *address, return value
- clrex // in case we skipped write
-#elif XCHAL_HAVE_S32C1I && XCHAL_HW_MIN_VERSION_MAJOR >= 2200
- mov a6, a4 // a6 = copy of set_value
- movi a5, -1
- xor a5, a5, a3 // a5 = ~a3
- wsr.scompare1 a3 // set test_value
-1:
- mov a4, a6 // a4 = set_value
- s32c1i a4, a2, 0
- bne a4, a5, 2f // if a4 != ~SCOMPARE1 then done
- l32i a4, a2, 0 // a4 = *address
- bne a4, a5, 1b // retry if *address != ~SCOMPARE1
-2:
- mov a2, a4
-#else
- mov a7, a2 // a7 == address, a2 is return val
-# if XCHAL_HAVE_INTERRUPTS
- rsil a5, 15 // a5 == new ps
-# endif
- l32i a2, a7, 0 // a2 == value to test, return val
- bne a3, a2, done // test
-
- s32i a4, a7, 0 // write the new value
-
-done:
-# if XCHAL_HAVE_INTERRUPTS
- wsr.ps a5 // restore the PS
- rsync
-# endif
-#endif
- abi_return
-
- .size xthal_compare_and_set, . - xthal_compare_and_set
-
-
-/*
- unsigned xthal_get_prid( void );
-
- Returns the value of the PRID register (processor ID),
- or 0 if not configured.
- (Note: this register, when present, cannot / must-not
- change value during runtime; on certain processors,
- its value may get sampled only at reset.
- It can never be written to, hence
- there is no xthal_set_prid() function.)
-*/
- .align 4
- .global xthal_get_prid
- .type xthal_get_prid,@function
-xthal_get_prid:
- abi_entry
-#if XCHAL_HAVE_PRID
- rsr.prid a2
-#else
- movi a2, 0
-#endif
- abi_return
- .size xthal_get_prid, . - xthal_get_prid
-
diff --git a/src/arch/xtensa/smp/hal/mpu.c b/src/arch/xtensa/smp/hal/mpu.c
deleted file mode 100644
index bacbfc6..0000000
--- a/src/arch/xtensa/smp/hal/mpu.c
+++ /dev/null
@@ -1,1830 +0,0 @@
-/*
- * Copyright (c) 2004-2015 Cadence Design Systems Inc.
- *
- * Permission is hereby granted, free of charge, to any person obtaining
- * a copy of this software and associated documentation files (the
- * "Software"), to deal in the Software without restriction, including
- * without limitation the rights to use, copy, modify, merge, publish,
- * distribute, sublicense, and/or sell copies of the Software, and to
- * permit persons to whom the Software is furnished to do so, subject to
- * the following conditions:
- *
- * The above copyright notice and this permission notice shall be included
- * in all copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
- * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
- * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
- * IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY
- * CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
- * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
- * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
- */
-#include <xtensa/config/core.h>
-
-#if XCHAL_HAVE_MPU
-#include <xtensa/core-macros.h>
-#include <xtensa/hal.h>
-#include <string.h>
-#include <stdlib.h>
-
-/*
- * General notes:
- * Wherever an address is represented as an unsigned, it has only the 27 most significant bits. This is how
- * the addresses are represented in the MPU. It has the benefit that we don't need to worry about overflow.
- *
- * The asserts in the code are ignored unless an assert handler is set (as it is during testing).
- *
- * If an assert handler is set, then the MPU map is checked for correctness after every update.
- *
- * On some configs (actually all configs right now), the MPU entries must be aligned to the background map.
- * The constant: XCHAL_MPU_ALIGN_REQ indicates if alignment is required:
- *
- * The rules for a valid map are:
- *
- * 1) The entries' vStartAddress fields must always be in non-descending order.
- * 2) The entries' memoryType and accessRights must contain valid values
- *
- * If XCHAL_MPU_ALIGN_REQ == 1 then the following additional rules are enforced:
- * 3) If entry0's Virtual Address Start field is nonzero, then that field must equal one of the
- * Background Map's Virtual Address Start field values if software ever intends to assert entry0's MPUENB bit.
- * 4) If entryN's MPUENB bit will ever be negated while at the same time entryN+1's MPUENB bit is asserted,
- * then entryN+1's Virtual Address Start field must equal one of the Background Map's Virtual Address Start field values.
- *
- * The internal function are first, and the external 'xthal_' functions are at the end.
- *
- */
-extern void (*_xthal_assert_handler)();
-extern void xthal_write_map_raw(const xthal_MPU_entry* fg, unsigned int n);
-extern void xthal_read_map_raw(const xthal_MPU_entry* fg);
-extern xthal_MPU_entry _xthal_get_entry(const xthal_MPU_entry* fg, const xthal_MPU_entry* bg,
- unsigned int addr, int* infgmap);
-
-#define MPU_ADDRESS_MASK (0xffffffff << XCHAL_MPU_ALIGN_BITS)
-#define MPU_ALIGNMENT_MASK (0xffffffff - MPU_ADDRESS_MASK)
-
-#define MPU_VSTART_CORRECTNESS_MASK ((0x1 << (XCHAL_MPU_ALIGN_BITS)) - 1)
-// Set this to 1 for more extensive internal checking / 0 for production
-#define MPU_DEVELOPMENT_MODE 0
-
-#if XCHAL_MPU_ALIGN_REQ
-#define XCHAL_MPU_WORST_CASE_ENTRIES_FOR_REGION 3
-#else
-#define XCHAL_MPU_WORST_CASE_ENTRIES_FOR_REGION 2
-#endif
-
-/*
- * At some point it is faster to commit/invalidate the entire cache rather than going on line at a time.
- * If a region is bigger than 'CACHE_REGION_THRESHOLD' we operate on the entire cache.
- */
-#if XCHAL_DCACHE_LINESIZE
-#define CACHE_REGION_THRESHOLD (32 * XCHAL_DCACHE_LINESIZE / XCHAL_MPU_ALIGN)
-#else
-#define CACHE_REGION_THRESHOLD 0
-#endif
-
-
-/*
- * Normally these functions are no-ops, but the MPU test harness sets an assert handler to detect any inconsistencies in MPU
- * entries or any other unexpected internal condition.
- */
-#if MPU_DEVELOPMENT_MODE
-static void my_assert(int arg)
-{
- if (_xthal_assert_handler && !arg)
- _xthal_assert_handler();
-}
-
-static void assert_map_valid()
-{
-
- if (_xthal_assert_handler)
- {
- xthal_MPU_entry fg[XCHAL_MPU_ENTRIES];
- xthal_read_map(fg);
- if (xthal_check_map(fg, XCHAL_MPU_ENTRIES))
- _xthal_assert_handler();
- }
-}
-
-static void assert_attributes_equivalent(unsigned addr, const xthal_MPU_entry* initial,
- const xthal_MPU_entry* fg, const xthal_MPU_entry* bg)
-{
-
- xthal_MPU_entry e1 = _xthal_get_entry(initial, bg, addr, 0);
- xthal_MPU_entry e2 = _xthal_get_entry(fg, bg, addr, 0);
- my_assert((XTHAL_MPU_ENTRY_GET_ACCESS(e1) == XTHAL_MPU_ENTRY_GET_ACCESS(e2)) && (XTHAL_MPU_ENTRY_GET_MEMORY_TYPE(e1) == XTHAL_MPU_ENTRY_GET_MEMORY_TYPE(e2)));
-}
-
-static void assert_maps_equivalent(const xthal_MPU_entry* initial, const xthal_MPU_entry* fg,
- const xthal_MPU_entry* bg)
-{
- /* this function checks that for every address the MPU entries 'initial' result in the same attributes as the entries in 'fg'.
- * We only need to check at the addresses that appear in 'initial', 'fg', or 'bg'.
- */
- int i;
- for (i = 0; i < XCHAL_MPU_ENTRIES; i++)
- {
- assert_attributes_equivalent(XTHAL_MPU_ENTRY_GET_VSTARTADDR(initial[i]), initial, fg, bg);
- assert_attributes_equivalent(XTHAL_MPU_ENTRY_GET_VSTARTADDR(fg[i]), initial, fg, bg);
- }
- for (i = 0; i < XCHAL_MPU_BACKGROUND_ENTRIES; i++)
- assert_attributes_equivalent(XTHAL_MPU_ENTRY_GET_VSTARTADDR(bg[i]), initial, fg, bg);
-}
-#else
-#define my_assert(x)
-#define assert_map_valid(x)
-#endif
-
-#if 0
-// These functions aren't used, but am leaving the definitions in place
-// for possible future use.
-static inline unsigned read_mpucfg()
-{
- unsigned long tmp;
- __asm__ __volatile__("rsr.mpucfg %0\n\t"
- : "=a" (tmp));
- return tmp;
-}
-
-static inline unsigned read_mpuenb()
-{
- unsigned long tmp;
- __asm__ __volatile__("rsr.mpuenb %0\n\t"
- : "=a" (tmp));
- return tmp;
-}
-
-/* This function writes the enable for the MPU entries */
-static inline void write_mpuenb(unsigned v)
-{
- __asm__ __volatile__("wsr.mpuenb %0\n\t"
- : : "a" (v));
-}
-
-#endif
-
-static inline void isync()
-{
- __asm__ __volatile__("isync\n\t");
-}
-
-/* This function writes the cache disable register which
- * disables the cache by 512MB registers to save power*/
-static inline void write_cacheadrdis(unsigned v)
-{
- __asm__ __volatile__("wsr.cacheadrdis %0\n\t"
- : : "a" (v));
-}
-
-inline static int is_cacheable(unsigned int mt);
-
-#if 0
-static inline void read_map_entry(unsigned en_num, xthal_MPU_entry* en)
-{
- unsigned as;
- unsigned at0;
- unsigned at1;
- as = en_num;
- __asm__ __volatile__("RPTLB0 %0, %1\n\t" : "+a" (at0) : "a" (as));
- __asm__ __volatile__("RPTLB1 %0, %1\n\t" : "+a" (at1) : "a" (as));
- en->as = at0;
- en->at = at1;
-}
-#endif
-
-inline static int is_cacheable(unsigned int mt)
-{
- return (0x180 & mt) || ((mt & 0x18) == 0x10) || ((mt & 0x30) == 0x30);
-}
-
-inline static int is_writeback(unsigned int mt)
-{
- return (((0x180 & mt) && (mt & 0x11)) ||
- ((((mt & 0x18) == 0x10) || ((mt & 0x30) == 0x30)) & 0x1));
-}
-
-inline static int is_device(unsigned int mt)
-{
- return ((mt & 0x1f0) == 0);
-}
-
-inline static int is_kernel_readable(int accessRights)
-{
- switch (accessRights)
- {
- case XTHAL_AR_R:
- case XTHAL_AR_Rr:
- case XTHAL_AR_RX:
- case XTHAL_AR_RXrx:
- case XTHAL_AR_RW:
- case XTHAL_AR_RWX:
- case XTHAL_AR_RWr:
- case XTHAL_AR_RWrw:
- case XTHAL_AR_RWrwx:
- case XTHAL_AR_RWXrx:
- case XTHAL_AR_RWXrwx:
- return 1;
- case XTHAL_AR_NONE:
- case XTHAL_AR_Ww:
- return 0;
- default:
- return XTHAL_BAD_ACCESS_RIGHTS;
- }
-}
-
-inline static int is_kernel_writeable(int accessRights)
-{
- switch (accessRights)
- {
- case XTHAL_AR_RW:
- case XTHAL_AR_RWX:
- case XTHAL_AR_RWr:
- case XTHAL_AR_RWrw:
- case XTHAL_AR_RWrwx:
- case XTHAL_AR_RWXrx:
- case XTHAL_AR_RWXrwx:
- case XTHAL_AR_Ww:
- return 1;
- case XTHAL_AR_NONE:
- case XTHAL_AR_R:
- case XTHAL_AR_Rr:
- case XTHAL_AR_RX:
- case XTHAL_AR_RXrx:
- return 0;
- default:
- return XTHAL_BAD_ACCESS_RIGHTS;
- }
-}
-
-inline static int is_kernel_executable(int accessRights)
-{
- switch (accessRights)
- {
- case XTHAL_AR_RX:
- case XTHAL_AR_RXrx:
- case XTHAL_AR_RWX:
- case XTHAL_AR_RWXrx:
- case XTHAL_AR_RWXrwx:
- return 1;
- case XTHAL_AR_NONE:
- case XTHAL_AR_Ww:
- case XTHAL_AR_R:
- case XTHAL_AR_Rr:
- case XTHAL_AR_RW:
- case XTHAL_AR_RWr:
- case XTHAL_AR_RWrw:
- case XTHAL_AR_RWrwx:
- return 0;
- default:
- return XTHAL_BAD_ACCESS_RIGHTS;
- }
-}
-
-inline static int is_user_readable(int accessRights)
-{
- switch (accessRights)
- {
- case XTHAL_AR_Rr:
- case XTHAL_AR_RXrx:
- case XTHAL_AR_RWr:
- case XTHAL_AR_RWrw:
- case XTHAL_AR_RWrwx:
- case XTHAL_AR_RWXrx:
- case XTHAL_AR_RWXrwx:
- return 1;
- case XTHAL_AR_R:
- case XTHAL_AR_RX:
- case XTHAL_AR_RW:
- case XTHAL_AR_RWX:
- case XTHAL_AR_NONE:
- case XTHAL_AR_Ww:
- return 0;
- default:
- return XTHAL_BAD_ACCESS_RIGHTS;
- }
-}
-
-inline static int is_user_writeable(int accessRights)
-{
- switch (accessRights)
- {
- case XTHAL_AR_Ww:
- case XTHAL_AR_RWrw:
- case XTHAL_AR_RWrwx:
- case XTHAL_AR_RWXrwx:
- return 1;
- case XTHAL_AR_NONE:
- case XTHAL_AR_R:
- case XTHAL_AR_Rr:
- case XTHAL_AR_RX:
- case XTHAL_AR_RXrx:
- case XTHAL_AR_RW:
- case XTHAL_AR_RWX:
- case XTHAL_AR_RWr:
- case XTHAL_AR_RWXrx:
- return 0;
- default:
- return XTHAL_BAD_ACCESS_RIGHTS;
- }
-}
-
-inline static int is_user_executable(int accessRights)
-{
- switch (accessRights)
- {
- case XTHAL_AR_RXrx:
- case XTHAL_AR_RWrwx:
- case XTHAL_AR_RWXrx:
- case XTHAL_AR_RWXrwx:
- return 1;
- case XTHAL_AR_RW:
- case XTHAL_AR_RWX:
- case XTHAL_AR_RWr:
- case XTHAL_AR_RWrw:
- case XTHAL_AR_R:
- case XTHAL_AR_Rr:
- case XTHAL_AR_RX:
- case XTHAL_AR_NONE:
- case XTHAL_AR_Ww:
- return 0;
- default:
- return XTHAL_BAD_ACCESS_RIGHTS;
- }
-}
-
-/* This function returns the map entry that is used for the address 'addr' (27msb).
- *
- */
-#if defined(__SPLIT__mpu_basic)
-
-xthal_MPU_entry _xthal_get_entry(const xthal_MPU_entry* fg, const xthal_MPU_entry* bg,
- unsigned int addr, int* infgmap)
-{
- int i;
- for (i = XCHAL_MPU_ENTRIES - 1; i >= 0; i--)
- {
- if (XTHAL_MPU_ENTRY_GET_VSTARTADDR(fg[i]) <= addr)
- {
- if (XTHAL_MPU_ENTRY_GET_VALID(fg[i]))
- {
- if (infgmap)
- *infgmap = 1;
- return fg[i];
- }
- else
- break;
- }
- }
- for (i = XCHAL_MPU_BACKGROUND_ENTRIES - 1; i >= 0; i--)
- {
- if (XTHAL_MPU_ENTRY_GET_VSTARTADDR(bg[i]) <= addr)
- {
- if (infgmap)
- *infgmap = 0;
- return bg[i];
- }
- }
- return bg[0]; // never reached ... just to get rid of compilation warning
-}
-
-/* returns true if the supplied address (27msb) is in the background map. */
-int _xthal_in_bgmap(unsigned int address, const xthal_MPU_entry* bg)
-{
- int i;
- for (i = 0; i < XCHAL_MPU_BACKGROUND_ENTRIES; i++)
- if (XTHAL_MPU_ENTRY_GET_VSTARTADDR(bg[i]) == address)
- return 1;
- return 0;
-}
-
-#endif
-
-#if defined(__SPLIT__mpu_attributes)
-
-/* This function updates the map entry as well as internal duplicate of the map
- * state in fg. The assumption is that reading map entries could be somewhat
- * expensive in some situations so we are keeping a copy of the map in memory when
- * doing extensive map manipulations.
- */
-static void write_map_entry(xthal_MPU_entry* fg, unsigned en_num, xthal_MPU_entry en)
-{
- en.at = (en.at & 0xffffffe0) | (en_num & 0x1f);
- xthal_mpu_set_entry(en);
- assert_map_valid();
- fg[en_num] = en;
-}
-
-static void move_map_down(xthal_MPU_entry* fg, int dup, int idx)
-{
- /* moves the map entry list down one (leaving duplicate entries at idx and idx+1. This function assumes that the last
- * entry is invalid ... call MUST check this
- */
- unsigned int i;
- for (i = dup; i > idx; i--)
- {
- write_map_entry(fg, i, fg[i - 1]);
- }
-}
-
-static void move_map_up(xthal_MPU_entry* fg, int dup, int idx)
-{
- /* moves the map entry list up one (leaving duplicate entries at idx and idx-1, removing the entry at dup
- */
- int i;
- for (i = dup; i < idx - 1; i++)
- {
- write_map_entry(fg, i, fg[i + 1]);
- }
-}
-
-static int bubble_free_to_ip(xthal_MPU_entry* fg, int ip, int required)
-{
- /* This function shuffles the entries in the MPU to get at least 'required' free entries at
- * the insertion point 'ip'. This function returns the new insertion point (after all the shuffling).
- */
- int i;
- int rv = ip;
- if (required < 1)
- return ip;
- my_assert(required <= XCHAL_MPU_ENTRIES);
- /* first we search for duplicate or unused entries at an index less than 'ip'. We start looking at ip-1
- * (rather than 0) to minimize the number of shuffles required.
- */
- for (i = ip - 2; i >= 0 && required;)
- {
- if (XTHAL_MPU_ENTRY_GET_VSTARTADDR(fg[i]) == XTHAL_MPU_ENTRY_GET_VSTARTADDR(fg[i + 1]))
- {
- move_map_up(fg, i, ip);
- rv--;
- required--;
- }
- i--;
- }
- // if there are any invalid entries at top of the map, we can remove them to make space
- while (required)
- {
- if (!XTHAL_MPU_ENTRY_GET_VALID(fg[0]))
- {
- move_map_up(fg, 0, ip);
- rv--;
- required--;
- }
- else
- break;
- }
- /* If there are not enough unneeded entries at indexes less than ip, then we search at indexes > ip.
- * We start the search at ip+1 and move down, again to minimize the number of shuffles required.
- */
-
- for (i = ip + 1; i < XCHAL_MPU_ENTRIES && required;)
- {
- if (XTHAL_MPU_ENTRY_GET_VSTARTADDR(fg[i]) == XTHAL_MPU_ENTRY_GET_VSTARTADDR(fg[i - 1]))
- {
- move_map_down(fg, i, ip);
- required--;
- }
- else
- i++;
- }
- my_assert(required == 0);
- return rv;
-}
-
-
-/* This function removes 'inaccessible' entries from the MPU map (those that are hidden by previous entries
- * in the map). It leaves any entries that match background entries in place.
- */
-static void remove_inaccessible_entries(xthal_MPU_entry* fg, const xthal_MPU_entry* bg)
-{
- int i;
- for (i = 1; i < XCHAL_MPU_ENTRIES; i++)
- {
- if (((XTHAL_MPU_ENTRY_GET_VALID(fg[i]) == XTHAL_MPU_ENTRY_GET_VALID(fg[i - 1])) && (XTHAL_MPU_ENTRY_GET_VSTARTADDR(fg[i]) > XTHAL_MPU_ENTRY_GET_VSTARTADDR(fg[i - 1]))
- && (XTHAL_MPU_ENTRY_GET_MEMORY_TYPE(fg[i]) == XTHAL_MPU_ENTRY_GET_MEMORY_TYPE(fg[i - 1])) && (XTHAL_MPU_ENTRY_GET_ACCESS(fg[i]) == XTHAL_MPU_ENTRY_GET_ACCESS(fg[i - 1])) &&
- /* we can only remove the background map entry if either background alignment is not required, or
- * if the previous entry is enabled.
- */
- (!_xthal_in_bgmap(XTHAL_MPU_ENTRY_GET_VSTARTADDR(fg[i]), bg)))
- || ((!XTHAL_MPU_ENTRY_GET_VALID(fg[i]) && (!XTHAL_MPU_ENTRY_GET_VALID(fg[i - 1])) && (!_xthal_in_bgmap(XTHAL_MPU_ENTRY_GET_VSTARTADDR(fg[i]), bg)))))
- {
- write_map_entry(fg, i, fg[i - 1]);
- }
- }
-}
-
-/* This function takes bitwise or'd combination of access rights and memory type, and extracts
- * the access rights. It returns the access rights, or -1.
- */
-static int encode_access_rights(int cattr)
-{
- cattr = cattr & 0xF;
- if ((cattr) > 0 && (cattr < 4))
- return -1;
- else
- return cattr;
-}
-
-/*
- * returns the largest value rv, such that for every index < rv,
- * entrys[index].vStartAddress < first.
- *
- * Assumes an ordered entry array (even disabled entries must be ordered).
- * value returned is in the range [0, XCHAL_MPU_ENTRIES].
- *
- */
-static int find_entry(xthal_MPU_entry* fg, unsigned first)
-{
- int i;
- for (i = XCHAL_MPU_ENTRIES - 1; i >= 0; i--)
- {
- if (XTHAL_MPU_ENTRY_GET_VSTARTADDR(fg[i]) <= first)
- return i + 1;
- }
- return 0; // if it is less than all existing entries return 0
-}
-
-/*
- * This function returns 1 if there is an exact match for first and first+size
- * so that no manipulations are necessary before safing and updating the attributes
- * for [first, first+size). The the first and end entries
- * must be valid, as well as all the entries in between. Otherwise the memory
- * type might change across the region and we wouldn't be able to safe the caches.
- *
- * An alternative would be to require alignment regions in this case, but that seems
- * more wasteful.
- */
-static int needed_entries_exist(xthal_MPU_entry* fg, unsigned first, unsigned last)
-{
- int i;
- for (i = 0; i < XCHAL_MPU_ENTRIES; i++)
- {
- if (XTHAL_MPU_ENTRY_GET_VSTARTADDR(fg[i]) == first)
- {
- int j;
- /* special case ... is last at the end of the address space
- * ... if so there is no end entry needed.
- */
- if (last == 0xFFFFFFFF)
- {
- int k;
- for (k = i; k < XCHAL_MPU_ENTRIES; k++)
- if (!XTHAL_MPU_ENTRY_GET_VALID(fg[k]))
- return 0;
- return 1;
- }
- /* otherwise search for the end entry */
- for (j = i; j < XCHAL_MPU_ENTRIES; j++)
- if (last == XTHAL_MPU_ENTRY_GET_VSTARTADDR(fg[j]))
- {
- int k;
- for (k = i; k <= j; k++)
- if (!XTHAL_MPU_ENTRY_GET_VALID(fg[k]))
- return 0;
- return 1;
- }
- return 0;
- }
- }
- return 0;
-}
-
-/* This function computes the number of MPU entries that are available for use in creating a new
- * region.
- */
-static int number_available(xthal_MPU_entry* fg)
-{
- int i;
- int rv = 0;
- int valid_seen = 0;
- for (i = 0; i < XCHAL_MPU_ENTRIES; i++)
- {
- if (!valid_seen)
- {
- if (XTHAL_MPU_ENTRY_GET_VALID(fg[i]))
- valid_seen = 1;
- else
- {
- rv++;
- continue;
- }
- }
- else
- {
- if (i && (XTHAL_MPU_ENTRY_GET_VSTARTADDR(fg[i]) == XTHAL_MPU_ENTRY_GET_VSTARTADDR(fg[i - 1])))
- rv++;
- }
- }
- return rv;
-}
-
-/*
- * This function returns index of the background map entry that maps the address 'first' if there are no
- * enabled/applicable foreground map entries.
- */
-static int get_bg_map_index(const xthal_MPU_entry* bg, unsigned first)
-{
- int i;
- for (i = XCHAL_MPU_BACKGROUND_ENTRIES - 1; i >= 0; i--)
- if (first > XTHAL_MPU_ENTRY_GET_VSTARTADDR(bg[i]))
- return i;
- return 0;
-}
-
-inline static unsigned int covert_to_writethru_memtype(unsigned int wb_memtype)
-{
- unsigned int prefix = wb_memtype & 0x1f0;
- if (prefix == 0x10)
- return wb_memtype & 0xfffffffe;
- else
- return wb_memtype & 0xffffffee;
-}
-
-/*
- * This function takes the region pointed to by ip, and makes it safe from the aspect of cache coherency, before
- * changing the memory type and possibly corrupting the cache. If wb is 0, then that indicates
- * that we should ignore uncommitted entries. If the inv argument is 0 that indicates that we shouldn't invalidate
- * the cache before switching to bypass.
- */
-static void safe_region(xthal_MPU_entry* fg, int ip, unsigned end_of_segment, int memoryType, int wb, int inv,
- unsigned int* post_inv_all)
-{
- unsigned length = end_of_segment - XTHAL_MPU_ENTRY_GET_VSTARTADDR(fg[ip]); // initially keep length 27msb to avoid possibility of overflow
- if (!length)
- return; // if the region is empty, there is no need to safe it
-
- int cmemType = XTHAL_MPU_ENTRY_GET_MEMORY_TYPE(fg[ip]);
-
- if (memoryType == cmemType)
- return; // not changing memory types ... we don't need to do anything
-
- int mt_is_wb = is_writeback(memoryType);
- int mt_is_ch = is_cacheable(memoryType);
-
- // nothing needs to be done in these cases
- if (mt_is_wb || (!wb && (!inv || mt_is_ch)))
- return;
-
- int need_flush = wb && (is_writeback(cmemType) && !is_writeback(memoryType));
- int need_invalidate = inv && (is_cacheable(cmemType) && !is_cacheable(memoryType));
-
- void* addr = (void*) XTHAL_MPU_ENTRY_GET_VSTARTADDR(fg[ip]);
-
- int write_by_region = length < CACHE_REGION_THRESHOLD;
-
- if (need_flush)
- {
- XTHAL_MPU_ENTRY_SET_MEMORY_TYPE(fg[ip], covert_to_writethru_memtype(XTHAL_MPU_ENTRY_GET_MEMORY_TYPE(fg[ip])));
- // If the AR == NONE, the writing back the cache may generate exception. Temporarily open up the protections ...
- // ...
- if (XTHAL_MPU_ENTRY_GET_ACCESS(fg[ip]) == XTHAL_AR_NONE)
- XTHAL_MPU_ENTRY_SET_ACCESS(fg[ip], XTHAL_AR_RWXrwx);
- // bit 0 determines if it wb/wt
- write_map_entry(fg, ip, fg[ip]);
- if (!write_by_region)
- {
- /* unfortunately there is no straight forward way to avoid the possibility of doing
- * multiple xthal_dcache_all_writeback() calls during a region update. The reason for this
- * is that:
- *
- * 1) The writeback must be done before the memory type is changed to non-cacheable before
- * an invalidate (see below)
- *
- * 2) it isn't possible to reorganize the loop so that all the writebacks are done before
- * any of the invalidates because if part of the region of interest is (initially) mapped
- * by the background map, then a single foreground entry is reused to 'safe' across
- * each background map entry that is overlapped.
- */
- xthal_dcache_all_writeback();
- }
- else if (length)
- xthal_dcache_region_writeback(addr, length);
- }
-
- if (need_invalidate)
- {
- XTHAL_MPU_ENTRY_SET_MEMORY_TYPE(fg[ip],
- XTHAL_ENCODE_MEMORY_TYPE(XCHAL_CA_BYPASS));
- write_map_entry(fg, ip, fg[ip]);
- /* only need to call all_invalidate once ... check
- * if it has already been done.
- */
- if (!*post_inv_all)
- {
- if (!write_by_region)
- {
- *post_inv_all = 1;
- }
- else if (length)
- {
- xthal_icache_region_invalidate(addr, length);
- xthal_dcache_region_writeback_inv(addr, length);
- }
- }
- }
-}
-
-static unsigned max(unsigned a, unsigned b, unsigned c)
-{
- if (a > b && a > c)
- return a;
- else if (b > c)
- return b;
- else
- return c;
-}
-
-/* This function returns the next address to commit which will be the greatest of the following:
- * 1) The start of the region we are creating
- * 2) The vStartAddress of the previous entry
- * 3) The background map entry that precedes the current address (last address committed).
- */
-static unsigned next_address_to_commit(xthal_MPU_entry* fg, const xthal_MPU_entry* bg, unsigned first,
- int current_index)
-{
- unsigned current = XTHAL_MPU_ENTRY_GET_VSTARTADDR(fg[current_index]);
- return max(first, XTHAL_MPU_ENTRY_GET_VSTARTADDR(fg[current_index - 1]), XTHAL_MPU_ENTRY_GET_VSTARTADDR(bg[get_bg_map_index(bg, current)]));
-}
-
-/*
- * This function does a series of calls to safe_region() to ensure that no data will be corrupted when changing the memory type
- * of an MPU entry. These calls are made for every entry address in the range[first,end), as well as at any background region boundary
- * in the range[first,end). In general it is necessary to safe at the background region boundaries, because the memory type could
- * change at that address.
- *
- * This function is written to reuse already needed entries for the background map 'safes' which complicates things somewhat.
- *
- * After the calls to safe region are complete, then the entry attributes are updated for every entry in the range [first,end).
- */
-static void safe_and_commit_overlaped_regions(xthal_MPU_entry* fg, const xthal_MPU_entry*bg, unsigned first,
- unsigned last, int memoryType, int accessRights, int wb, int inv)
-{
- int i;
- unsigned int next;
- unsigned end_of_segment = last;
- unsigned post_inv_all = 0;
- unsigned int cachedisadr;
- write_cacheadrdis(0);
- for (i = XCHAL_MPU_ENTRIES - 1; i >= 0; i--)
- if (XTHAL_MPU_ENTRY_GET_VSTARTADDR(fg[i]) < last)
- {
- // first we want to commit the first entry
- safe_region(fg, i, end_of_segment, memoryType, wb, inv, &post_inv_all);
- end_of_segment = XTHAL_MPU_ENTRY_GET_VSTARTADDR(fg[i]);
- do
- {
- next = next_address_to_commit(fg, bg, first, i);
- if (next == XTHAL_MPU_ENTRY_GET_VSTARTADDR(fg[i - 1]))
- i--;
- XTHAL_MPU_ENTRY_SET_VSTARTADDR(fg[i], next);
- safe_region(fg, i, last, memoryType, wb, inv, &post_inv_all);
- end_of_segment = XTHAL_MPU_ENTRY_GET_VSTARTADDR(fg[i]);
- } while (next > first);
- if (post_inv_all)
- {
- xthal_icache_all_invalidate();
- xthal_dcache_all_writeback_inv();
- }
- for (; i < XCHAL_MPU_ENTRIES && XTHAL_MPU_ENTRY_GET_VSTARTADDR(fg[i]) < last; i++)
- {
- XTHAL_MPU_ENTRY_SET_MEMORY_TYPE(fg[i], memoryType);
- XTHAL_MPU_ENTRY_SET_ACCESS(fg[i], accessRights);
- XTHAL_MPU_ENTRY_SET_VALID(fg[i], 1);
- write_map_entry(fg, i, fg[i]);
- }
- break;
- }
- cachedisadr = xthal_calc_cacheadrdis(fg, XCHAL_MPU_ENTRIES);
- write_cacheadrdis(cachedisadr);
-}
-
-static void handle_invalid_pred(xthal_MPU_entry* fg, const xthal_MPU_entry* bg, unsigned first, int ip)
-{
- /* Handle the case where there is an invalid entry immediately preceding the entry we
- * are creating. If the entries addresses correspond to the same bg map, then we
- * make the previous entry valid with same attributes as the background map entry.
- *
- * The case where an invalid entry exists immediately preceding whose address corresponds to a different
- * background map entry is handled by create_aligning_entries_if_required(), so nothing is done here.
- */
- /* todo ... optimization opportunity, the following block loops through the background map up to 4 times,
- *
- */
- if (!ip || XTHAL_MPU_ENTRY_GET_VALID(fg[ip - 1]))
- return;
- {
- int i;
- unsigned fgipm1_addr = XTHAL_MPU_ENTRY_GET_VSTARTADDR(fg[ip - 1]);
- int first_in_bg_map = 0;
- int first_bg_map_index = -1;
- int fgipm1_bg_map_index = -1;
-#if MPU_DEVELOPMENT_MODE
- unsigned fgip_addr = XTHAL_MPU_ENTRY_GET_VSTARTADDR(fg[ip]);
- int fgip_bg_map_index = -1;
-#endif
- for (i = XCHAL_MPU_BACKGROUND_ENTRIES - 1; i >= 0; i--)
- {
- unsigned addr = XTHAL_MPU_ENTRY_GET_VSTARTADDR(bg[i]);
- if (addr == first)
- first_in_bg_map = 1;
- if (addr < fgipm1_addr && fgipm1_bg_map_index == -1)
- fgipm1_bg_map_index = i;
-#if MPU_DEVELOPMENT_MODE
- if (addr < fgip_addr && fgip_bg_map_index == -1)
- fgip_bg_map_index = i;
-#endif
- if (addr < first && first_bg_map_index == -1)
- first_bg_map_index = i;
- }
- if (!first_in_bg_map && (first_bg_map_index == fgipm1_bg_map_index))
- {
- // There should be a subsequent entry that falls in the address range of same
- // background map entry ... if not, we have a problem because the following
- // will corrupt the memory map
-#if MPU_DEVELOPMENT_MODE
- {
- my_assert(fgip_bg_map_index == fgipm1_bg_map_index);
- }
-#endif
- xthal_MPU_entry temp = _xthal_get_entry(fg, bg, XTHAL_MPU_ENTRY_GET_VSTARTADDR(fg[ip - 1]), 0);
- XTHAL_MPU_ENTRY_SET_VSTARTADDR(temp, XTHAL_MPU_ENTRY_GET_VSTARTADDR(fg[ip - 1]));
- write_map_entry(fg, ip - 1, temp);
- }
- }
-}
-
-/* This function inserts a entry (unless it already exists) with vStartAddress of first. The new entry has
- * the same accessRights and memoryType as the address first had before the call.
- *
- * If 'invalid' is specified, then insert an invalid region if no foreground entry exists for the address 'first'.
- */
-static int insert_entry_if_needed_with_existing_attr(xthal_MPU_entry* fg, const xthal_MPU_entry* bg,
- unsigned first, int invalid)
-{
- int i;
- int ip;
- int infg;
- int found = 0;
-
- for (i = XCHAL_MPU_ENTRIES - 1; i >= 0; i--)
- if (XTHAL_MPU_ENTRY_GET_VSTARTADDR(fg[i]) == first)
- {
- if (XTHAL_MPU_ENTRY_GET_VALID(fg[i]) || invalid)
- return XTHAL_SUCCESS;
- else
- {
- found = 1;
- ip = i;
- break;
- }
- }
-
- if (!found)
- {
- if (!number_available(fg))
- return XTHAL_OUT_OF_ENTRIES;
-
- ip = find_entry(fg, first);
- ip = bubble_free_to_ip(fg, ip, 1);
- }
- if (!invalid)
- handle_invalid_pred(fg, bg, first, ip);
- xthal_MPU_entry n;
- memset(&n, 0, sizeof(n));
- n = _xthal_get_entry(fg, bg, first, &infg);
-
- if (invalid && !infg) // If the entry mapping is currently in the foreground we can't make
- // the entry invalid without corrupting the attributes of the following entry.
- XTHAL_MPU_ENTRY_SET_VALID(n, 0);
- XTHAL_MPU_ENTRY_SET_VSTARTADDR(n,first);
- write_map_entry(fg, ip, n);
- return XTHAL_SUCCESS;
-}
-
-static unsigned int smallest_entry_greater_than_equal(xthal_MPU_entry* fg, unsigned x)
-{
- int i;
- for (i = 0; i < XCHAL_MPU_ENTRIES; i++)
- if (XTHAL_MPU_ENTRY_GET_VSTARTADDR(fg[i]) >= x)
- return XTHAL_MPU_ENTRY_GET_VSTARTADDR(fg[i]);
- return 0;
-}
-
-/* This function creates background map aligning entries if required.*/
-static unsigned int create_aligning_entries_if_required(xthal_MPU_entry* fg, const xthal_MPU_entry* bg,
- unsigned x)
-{
-#if XCHAL_MPU_ALIGN_REQ
- int i;
- int rv;
- unsigned next_entry_address = 0;
- unsigned next_entry_valid = 0;
- int preceding_bg_entry_index_x = get_bg_map_index(bg, x);
- unsigned preceding_bg_entry_x_addr = XTHAL_MPU_ENTRY_GET_VSTARTADDR(bg[preceding_bg_entry_index_x]);
- for (i = XCHAL_MPU_ENTRIES - 1; i >= 0; i--)
- {
- if (XTHAL_MPU_ENTRY_GET_VSTARTADDR(fg[i]) < x)
- {
- if (XTHAL_MPU_ENTRY_GET_VALID(fg[i]))
- return XTHAL_SUCCESS; // If there is a valid entry immediately before the proposed new entry
- // ... then no aligning entries are required
- break;
- }
- else
- {
- next_entry_address = XTHAL_MPU_ENTRY_GET_VSTARTADDR(fg[i]);
- next_entry_valid = XTHAL_MPU_ENTRY_GET_VALID(fg[i]);
- }
- }
-
- /*
- * before creating the aligning entry, we may need to create an entry or entries a higher
- * addresses to limit the scope of the aligning entry.
- */
- if ((!next_entry_address) || (!next_entry_valid) || (_xthal_in_bgmap(next_entry_address, bg)))
- {
- /* in this case, we can just create an invalid entry at the start of the new region because
- * a valid entry could have an alignment problem. An invalid entry is safe because we know that
- * the next entry is either invalid, or is on a bg map entry
- */
- if ((rv = insert_entry_if_needed_with_existing_attr(fg, bg, x, 1)) != XTHAL_SUCCESS)
- {
- return rv;
- }
- }
- else
- {
- unsigned next_bg_entry_index;
- for (next_bg_entry_index = 0; next_bg_entry_index < XCHAL_MPU_BACKGROUND_ENTRIES; next_bg_entry_index++)
- if (XTHAL_MPU_ENTRY_GET_VSTARTADDR(bg[next_bg_entry_index]) > x)
- break;
- if (next_entry_address == XTHAL_MPU_ENTRY_GET_VSTARTADDR(bg[next_bg_entry_index])) // In this case there is no intervening bg entry
- // between the new entry x, and the next existing entry so, we don't need any limiting entry
- // (the existing next_entry serves as the limiting entry)
- { /* intentionally empty */
- }
- else
- {
- // In this case we need to create a valid region at the background entry that immediately precedes
- // next_entry_address, and then create an invalid entry at the background entry immediately after
- // x
- if ((rv = insert_entry_if_needed_with_existing_attr(fg, bg, XTHAL_MPU_ENTRY_GET_VSTARTADDR(_xthal_get_entry(fg, bg, x, 0)), 0))
- != XTHAL_SUCCESS)
- {
- return rv;
- }
- if ((rv = insert_entry_if_needed_with_existing_attr(fg, bg,
- XTHAL_MPU_ENTRY_GET_VSTARTADDR(_xthal_get_entry(fg, bg, XTHAL_MPU_ENTRY_GET_VSTARTADDR(bg[next_bg_entry_index]), 0)), 1)) != XTHAL_SUCCESS)
- {
- return rv;
- }
- }
- }
-
- /* now we are finally ready to create the aligning entry.*/
- if (!(x == preceding_bg_entry_x_addr))
- if ((rv = insert_entry_if_needed_with_existing_attr(fg, bg, preceding_bg_entry_x_addr, 0)) != XTHAL_SUCCESS)
- {
- return rv;
- }
-
- return XTHAL_SUCCESS;
-
-#else
- return XTHAL_SUCCESS;
-#endif
-}
-
-static unsigned start_initial_region(xthal_MPU_entry* fg, const xthal_MPU_entry* bg, unsigned first,
- unsigned end)
-{
- int i;
- unsigned addr;
- for (i = XCHAL_MPU_BACKGROUND_ENTRIES - 1; i >= 0; i--)
- {
- addr = XTHAL_MPU_ENTRY_GET_VSTARTADDR(bg[i]);
- if (addr <= first)
- break;
- if (addr < end)
- return addr;
- }
- return first;
-}
-
-static int safe_add_region(unsigned first, unsigned last, unsigned accessRights, unsigned memoryType,
- unsigned writeback, unsigned invalidate)
-{
- /* This function sets the memoryType and accessRights on a region of memory. If necessary additional MPU entries
- * are created so that the attributes of any memory outside the specified region are not changed.
- *
- * This function has 2 stages:
- * 1) The map is updated one entry at a time to create (if necessary) new entries to mark the beginning and end of the
- * region as well as addition alignment entries if needed. During this stage the map is always correct, and the memoryType
- * and accessRights for every address remain the same.
- * 2) The entries inside the update region are then safed for cache consistency (if necessary) and then written with
- * the new accessRights, and memoryType.
- *
- * If the function fails (by running out of available map entries) during stage 1 then everything is still consistent and
- * it is safe to return an error code.
- *
- * If XCHAL_MPU_ALIGN_REQ is provided then extra entries are create if needed
- * to satisfy these alignment conditions:
- *
- * 1) If entry0's Virtual Address Start field is nonzero, then that field must equal one of the Background Map's
- * Virtual Address Start field values if software ever intends to assert entry0's MPUENB bit.
- * 2) If entryN's MPUENB bit will ever be negated while at the same time entryN+1's MPUENB bit is
- * asserted, then entryN+1's Virtual Address Start field must equal one of the Background Map's Virtual Address Start field values.
- *
- * Between 0 and 2 available entries will be used by this function. In addition, if XCHAL_MPU_ALIGN_REQ == 1 up to ???
- * additional entries will be needed to meet background map alignment requirements.
- *
- * This function keeps a copy of the current map in 'fg'. This is kept in sync with contents of the MPU at all times.
- *
- */
-
- int rv;
-
- xthal_MPU_entry fg[XCHAL_MPU_ENTRIES];
-#if MPU_DEVELOPMENT_MODE
- xthal_MPU_entry on_entry[XCHAL_MPU_ENTRIES];
- xthal_read_map(on_entry);
-#endif
- xthal_read_map(fg);
- assert_map_valid();
-
- /* First we check and see if consecutive entries at first, and first + size already exist.
- * in this important special case we don't need to do anything but safe and update the entries [first, first+size).
- *
- */
-
- if (!needed_entries_exist(fg, first, last))
- {
- unsigned x;
- unsigned pbg;
-
- /*
- * If we are tight on entries, the first step is to remove any redundant entries in the MPU
- * to make room to ensure that there is room for the new entries we need.
- *
- * We need to call it here ... once we have started transforming the map it is too late
- * (the process involves creating inaccessible entries that could potentially get removed).
- */
- if (number_available(fg) < XCHAL_MPU_WORST_CASE_ENTRIES_FOR_REGION)
- remove_inaccessible_entries(fg, Xthal_mpu_bgmap);
-#if MPU_DEVELOPMENT_MODE
- assert_maps_equivalent(on_entry, fg, Xthal_mpu_bgmap);
-#endif
- // First we create foreground entries that 'duplicate' background entries to aide in
- // maintaining proper alignment.
- if ((rv = create_aligning_entries_if_required(fg, Xthal_mpu_bgmap, first)) != XTHAL_SUCCESS)
- return rv;
-
- // First we write the terminating entry for our region
- // 5 cases:
- // 1) end is at the end of the address space, then we don't need to do anything ... takes 0 entries
- // 2) There is an existing entry at end ... another nop ... 0 entries
- // 3) end > than any existing entry ... in this case we just create a new invalid entry at end to mark
- // end of the region. No problem with alignment ... this takes 1 entry
- // 4) otherwise if there is a background map boundary between end and x ,the smallest existing entry that is
- // greater than end, then we first create an equivalent foreground map entry for the background map entry that immediately
- // precedes x, and then we write an invalid entry for end. Takes 2 entries
- // 5) otherwise x is in the same background map entry as end, in this case we write a new foreground entry with the existing
- // attributes at end
-
- if (last == 0xFFFFFFFF)
- { /* the end is the end of the address space ... do nothing */
- }
- else
- {
- x = smallest_entry_greater_than_equal(fg, last);
- if (last == x)
- { /* another nop */
- }
- else if (last > x)
- { /* there is no entry that has a start after the new region ends
- ... we handle this by creating an invalid entry at the end point */
- if ((rv = insert_entry_if_needed_with_existing_attr(fg, Xthal_mpu_bgmap, last, 1)) != XTHAL_SUCCESS)
- {
-#if MPU_DEVELOPMENT_MODE
- assert_maps_equivalent(on_entry, fg, Xthal_mpu_bgmap);
-#endif
- return rv;
- }
-#if MPU_DEVELOPMENT_MODE
- assert_maps_equivalent(on_entry, fg, Xthal_mpu_bgmap);
-#endif
- }
- else
- {
- pbg = XTHAL_MPU_ENTRY_GET_VSTARTADDR(fg[get_bg_map_index(Xthal_mpu_bgmap, x)]);
- /* so there is an existing entry we must deal with. We next need to find
- * if there is an existing background entry in between the end of
- * the new region and beginning of the next.
- */
- if ((pbg != x) && (pbg > last))
- {
- /* okay ... there is an intervening background map entry. We need
- * to handle this by inserting an aligning entry (if the architecture requires it)
- * and then placing writing an invalid entry at end.
- */
- if (XCHAL_MPU_ALIGN_REQ)
- {
- if ((rv = insert_entry_if_needed_with_existing_attr(fg, Xthal_mpu_bgmap, pbg, 0)) != XTHAL_SUCCESS)
- {
-#if MPU_DEVELOPMENT_MODE
- assert_maps_equivalent(on_entry, fg, Xthal_mpu_bgmap);
-#endif
- return rv;
- }
-#if MPU_DEVELOPMENT_MODE
- assert_maps_equivalent(on_entry, fg, Xthal_mpu_bgmap);
-#endif
- }
- if ((rv = insert_entry_if_needed_with_existing_attr(fg, Xthal_mpu_bgmap, last, 1)) != XTHAL_SUCCESS)
- {
-#if MPU_DEVELOPMENT_MODE
- assert_maps_equivalent(on_entry, fg, Xthal_mpu_bgmap);
-#endif
- return rv;
- }
-#if MPU_DEVELOPMENT_MODE
- assert_maps_equivalent(on_entry, fg, Xthal_mpu_bgmap);
-#endif
- }
- else
- /* ok so there are no background map entry in between end and x, in this case
- * we just need to create a new entry at end writing the existing attributes.
- */
- if ((rv = insert_entry_if_needed_with_existing_attr(fg, Xthal_mpu_bgmap, last, 1)) != XTHAL_SUCCESS)
- {
-#if MPU_DEVELOPMENT_MODE
- assert_maps_equivalent(on_entry, fg, Xthal_mpu_bgmap);
-#endif
- return rv;
- }
-#if MPU_DEVELOPMENT_MODE
- assert_maps_equivalent(on_entry, fg, Xthal_mpu_bgmap);
-#endif
- }
- }
-
- /* last, but not least we need to insert a entry at the starting address for our new region */
- if ((rv = insert_entry_if_needed_with_existing_attr(fg, Xthal_mpu_bgmap, start_initial_region(fg, Xthal_mpu_bgmap, first, last), 0))
- != XTHAL_SUCCESS)
- {
-#if MPU_DEVELOPMENT_MODE
- assert_maps_equivalent(on_entry, fg, Xthal_mpu_bgmap);
-#endif
- return rv;
- }
-#if MPU_DEVELOPMENT_MODE
- assert_maps_equivalent(on_entry, fg, Xthal_mpu_bgmap);
-#endif
- }
- // up to this point, the attributes of every byte in the address space should be the same as when this function
- // was called.
- safe_and_commit_overlaped_regions(fg, Xthal_mpu_bgmap, first, last, memoryType, accessRights, writeback, invalidate);
-
- assert_map_valid();
- return XTHAL_SUCCESS;
-}
-
-// checks if x (full 32bit) is mpu_aligned for MPU
-static unsigned int mpu_aligned(unsigned x)
-{
- return !(x & MPU_ALIGNMENT_MASK);
-}
-
-static unsigned int mpu_align(unsigned int x, unsigned int roundUp)
-{
- if (roundUp)
- return (x + MPU_ALIGNMENT_MASK) & MPU_ADDRESS_MASK;
- else
- return (x & MPU_ADDRESS_MASK);
-}
-
-#endif
-
-#if defined(__SPLIT__mpu_check)
-static int bad_accessRights(unsigned ar)
-{
- if (ar == 0 || (ar >= 4 && ar <= 15))
- return 0;
- else
- return 1;
-}
-
-/* this function checks if the supplied map 'fg' is a valid MPU map using 3 criteria:
- * 1) if an entry is valid, then that entries accessRights must be defined (0 or 4-15).
- * 2) The map entries' 'vStartAddress's must be in increasing order.
- * 3) If the architecture requires background map alignment then:
- * a) If entry0's 'vStartAddress' field is nonzero, then that field must equal
- * one of the Background Map's 'vStartAddress' field values if the entry 0's valid bit is set.
- * b) If entryN's 'valid' bit is 0 and entry[N+1]'s 'valid' bit is 1, then
- * entry[N+1]'s 'vStartAddress' field must equal one of the Background Map's 'vStartAddress' field values.
- *
- * This function returns XTHAL_SUCCESS if the map satisfies the condition, otherwise it returns
- * XTHAL_BAD_ACCESS_RIGHTS, XTHAL_OUT_OF_ORDER_MAP, or XTHAL_MAP_NOT_ALIGNED.
- *
- */
-static int check_map(const xthal_MPU_entry* fg, unsigned int n, const xthal_MPU_entry* bg)
-{
- int i;
- unsigned current = 0;
- if (!n)
- return XTHAL_SUCCESS;
- if (n > XCHAL_MPU_ENTRIES)
- return XTHAL_OUT_OF_ENTRIES;
- for (i = 0; i < n; i++)
- {
- if (XTHAL_MPU_ENTRY_GET_VALID(fg[i]) && bad_accessRights(XTHAL_MPU_ENTRY_GET_ACCESS(fg[i])))
- return XTHAL_BAD_ACCESS_RIGHTS;
- if ((XTHAL_MPU_ENTRY_GET_VSTARTADDR(fg[i]) < current))
- return XTHAL_OUT_OF_ORDER_MAP;
- if (XTHAL_MPU_ENTRY_GET_VSTARTADDR(fg[i]) & MPU_VSTART_CORRECTNESS_MASK)
- return XTHAL_MAP_NOT_ALIGNED;
- current = XTHAL_MPU_ENTRY_GET_VSTARTADDR(fg[i]);
- }
- if (XCHAL_MPU_ALIGN_REQ && XTHAL_MPU_ENTRY_GET_VALID(fg[0]) && XTHAL_MPU_ENTRY_GET_VSTARTADDR(fg[0])
- && !_xthal_in_bgmap(XTHAL_MPU_ENTRY_GET_VSTARTADDR(fg[0]), bg))
- return XTHAL_MAP_NOT_ALIGNED;
- for (i = 0; i < n- 1; i++)
- if (XCHAL_MPU_ALIGN_REQ && !XTHAL_MPU_ENTRY_GET_VALID(fg[i]) && XTHAL_MPU_ENTRY_GET_VALID(fg[i + 1])
- && !_xthal_in_bgmap(XTHAL_MPU_ENTRY_GET_VSTARTADDR(fg[i + 1]), bg))
- return XTHAL_MAP_NOT_ALIGNED;
- return XTHAL_SUCCESS;
-}
-
-
-
-/*
- * this function checks that the bit-wise or-ed XTHAL_MEM_... bits in x correspond to a valid
- * MPU memoryType. If x is valid, then 0 is returned, otherwise XTHAL_BAD_MEMORY_TYPE is
- * returned.
- */
-static int check_memory_type(unsigned x)
-{
- unsigned system_cache_type = _XTHAL_MEM_CACHE_MASK(x);
- unsigned processor_cache_type = (((x) & _XTHAL_LOCAL_CACHE_BITS) >> 4);
- if ((system_cache_type > XTHAL_MEM_NON_CACHEABLE) || (processor_cache_type > XTHAL_MEM_NON_CACHEABLE))
- return XTHAL_BAD_MEMORY_TYPE;
- int processor_cache_type_set = 1;
- if (!processor_cache_type)
- {
- processor_cache_type = system_cache_type << 4;
- processor_cache_type_set = 0;
- }
- unsigned device = _XTHAL_MEM_IS_DEVICE(x);
- unsigned system_noncacheable = _XTHAL_IS_SYSTEM_NONCACHEABLE(x);
-
- if (device | system_noncacheable)
- {
- if ((system_cache_type || processor_cache_type_set) && device)
- return XTHAL_BAD_MEMORY_TYPE;
- if (processor_cache_type_set)
- return XTHAL_BAD_MEMORY_TYPE; // if memory is device or non cacheable, then processor cache type should not be set
- if (system_noncacheable && (x & XTHAL_MEM_INTERRUPTIBLE))
- return XTHAL_BAD_MEMORY_TYPE;
- {
- unsigned z = x & XTHAL_MEM_SYSTEM_SHAREABLE;
- if ((z == XTHAL_MEM_INNER_SHAREABLE) || (z == XTHAL_MEM_OUTER_SHAREABLE))
- return XTHAL_BAD_MEMORY_TYPE;
- }
- }
- else
- {
- if ((x & XTHAL_MEM_SYSTEM_SHAREABLE) == XTHAL_MEM_SYSTEM_SHAREABLE)
- return XTHAL_BAD_MEMORY_TYPE;
- if ((x & (XTHAL_MEM_BUFFERABLE | XTHAL_MEM_INTERRUPTIBLE)))
- return XTHAL_BAD_MEMORY_TYPE;
- }
-
- return 0;
-}
-#endif
-
-#endif // is MPU
-
-#if defined(__SPLIT__mpu_basic)
-/*
- * These functions accept encoded access rights, and return 1 if the supplied memory type has the property specified by the function name.
- */
-extern int xthal_is_kernel_readable(int accessRights)
-{
-#if XCHAL_HAVE_MPU
- return is_kernel_readable(accessRights);
-#else
- return XTHAL_UNSUPPORTED;
-#endif
-}
-
-extern int xthal_is_kernel_writeable(int accessRights)
-{
-#if XCHAL_HAVE_MPU
- return is_kernel_writeable(accessRights);
-#else
- return XTHAL_UNSUPPORTED;
-#endif
-}
-
-extern int xthal_is_kernel_executable(int accessRights)
-{
-#if XCHAL_HAVE_MPU
- return is_kernel_executable(accessRights);
-#else
- return XTHAL_UNSUPPORTED;
-#endif
-}
-
-extern int xthal_is_user_readable(int accessRights)
-{
-#if XCHAL_HAVE_MPU
- return is_user_readable(accessRights);
-#else
- return XTHAL_UNSUPPORTED;
-#endif
-}
-
-extern int xthal_is_user_writeable(int accessRights)
-{
-#if XCHAL_HAVE_MPU
- return is_user_writeable(accessRights);
-#else
- return XTHAL_UNSUPPORTED;
-#endif
-}
-
-extern int xthal_is_user_executable(int accessRights)
-{
-#if XCHAL_HAVE_MPU
- return is_user_executable(accessRights);
-#else
- return XTHAL_UNSUPPORTED;
-#endif
-}
-
-/*
- * These functions accept either an encoded or unencoded memory type, and
- * return 1 if the supplied memory type has property specified by the
- * function name.
- */
-int xthal_is_cacheable(unsigned int mt)
-{
-#if XCHAL_HAVE_MPU
- return is_cacheable(mt);
-#else
- return XTHAL_UNSUPPORTED;
-#endif
-}
-
-int xthal_is_writeback(unsigned int mt)
-{
-#if XCHAL_HAVE_MPU
- return is_writeback(mt);
-#else
- return XTHAL_UNSUPPORTED;
-#endif
-}
-
-int xthal_is_device(unsigned int mt)
-{
-#if XCHAL_HAVE_MPU
- return is_device(mt);
-#else
- return XTHAL_UNSUPPORTED;
-#endif
-}
-#endif
-
-/*
- * This function converts a bit-wise combination of the XTHAL_MEM_.. constants
- * to the corresponding MPU memory type (9-bits).
- *
- * If none of the XTHAL_MEM_.. bits are present in the argument, then
- * bits 4-12 (9-bits) are returned ... this supports using an already encoded
- * memoryType (perhaps obtained from an xthal_MPU_entry structure) as input
- * to xthal_set_region_attribute().
- *
- * This function first checks that the supplied constants are a valid and
- * supported combination. If not, it returns XTHAL_BAD_MEMORY_TYPE.
- */
-#if defined(__SPLIT__mpu_check)
-int xthal_encode_memory_type(unsigned int x)
-{
-#if XCHAL_HAVE_MPU
- const unsigned int MemoryTypeMask = 0x1ff0;
- const unsigned int MemoryFlagMask = 0xffffe000;
- /*
- * Encodes the memory type bits supplied in an | format (XCHAL_CA_PROCESSOR_CACHE_WRITEALLOC | XCHAL_CA_PROCESSOR_CACHE_WRITEBACK)
- */
- unsigned memoryFlags = x & MemoryFlagMask;
- if (!memoryFlags)
- return (x & MemoryTypeMask) >> XTHAL_AR_WIDTH;
- else
- {
- int chk = check_memory_type(memoryFlags);
- if (chk < 0)
- return chk;
- else
- return XTHAL_ENCODE_MEMORY_TYPE(memoryFlags);
- }
-#else
- return XTHAL_UNSUPPORTED;
-#endif
-}
-#endif
-
-#if defined(__SPLIT__mpu_rmap)
-
-/*
- * Copies the current MPU entry list into 'entries' which
- * must point to available memory of at least
- * sizeof(xthal_MPU_entry) * XCHAL_MPU_ENTRIES.
- *
- * This function returns XTHAL_SUCCESS.
- * XTHAL_INVALID, or
- * XTHAL_UNSUPPORTED.
- */
-int xthal_read_map(xthal_MPU_entry* fg_map)
-{
-#if XCHAL_HAVE_MPU
- unsigned i;
- if (!fg_map)
- return XTHAL_INVALID;
- xthal_read_map_raw(fg_map);
- return XTHAL_SUCCESS;
-#else
- return XTHAL_UNSUPPORTED;
-#endif
-}
-
-#if XCHAL_HAVE_MPU
- #undef XCHAL_MPU_BGMAP
- #define XCHAL_MPU_BGMAP(s,vstart,vend,rights,mtype,x...) XTHAL_MPU_ENTRY(vstart,1,rights,mtype),
-const xthal_MPU_entry Xthal_mpu_bgmap[] = { XCHAL_MPU_BACKGROUND_MAP(0) };
-#endif
-
-
-/*
- * Copies the MPU background map into 'entries' which must point
- * to available memory of at least
- * sizeof(xthal_MPU_entry) * XCHAL_MPU_BACKGROUND_ENTRIES.
- *
- * This function returns XTHAL_SUCCESS.
- * XTHAL_INVALID, or
- * XTHAL_UNSUPPORTED.
- */
-int xthal_read_background_map(xthal_MPU_entry* bg_map)
-{
-#if XCHAL_HAVE_MPU
- if (!bg_map)
- return XTHAL_INVALID;
- memcpy(bg_map, Xthal_mpu_bgmap, sizeof(Xthal_mpu_bgmap));
- return XTHAL_SUCCESS;
-#else
- return XTHAL_UNSUPPORTED;
-#endif
-}
-#endif
-/*
- * Writes the map pointed to by 'entries' to the MPU. Before updating
- * the map, it commits any uncommitted
- * cache writes, and invalidates the cache if necessary.
- *
- * This function does not check for the correctness of the map. Generally
- * xthal_check_map() should be called first to check the map.
- *
- * If n == 0 then the existing map is cleared, and no new map is written
- * (useful for returning to reset state)
- *
- * If (n > 0 && n < XCHAL_MPU_ENTRIES) then a new map is written with
- * (XCHAL_MPU_ENTRIES-n) padding entries added to ensure a properly ordered
- * map. The resulting foreground map will be equivalent to the map vector
- * fg, but the position of the padding entries should not be relied upon.
- *
- * If n == XCHAL_MPU_ENTRIES then the complete map as specified by fg is
- * written.
- *
- * xthal_write_map() disables the MPU foreground map during the MPU
- * update and relies on the background map.
- *
- * As a result any interrupt that does not meet the following conditions
- * must be disabled before calling xthal_write_map():
- * 1) All code and data needed for the interrupt must be
- * mapped by the background map with sufficient access rights.
- * 2) The interrupt code must not access the MPU.
- *
- */
-#if defined(__SPLIT__mpu_wmap)
-void xthal_write_map(const xthal_MPU_entry* fg, unsigned int n)
-{
-#if XCHAL_HAVE_MPU
- unsigned int cacheadrdis = xthal_calc_cacheadrdis(fg, n);
- xthal_dcache_all_writeback_inv();
- xthal_icache_all_invalidate();
- xthal_write_map_raw(fg, n);
- write_cacheadrdis(cacheadrdis);
- isync(); // ditto
-#endif
-}
-#endif
-
-#if defined(__SPLIT__mpu_check)
-/*
- * Checks if entry vector 'fg' of length 'n' is a valid MPU access map.
- * Returns:
- * XTHAL_SUCCESS if valid,
- * XTHAL_OUT_OF_ENTRIES
- * XTHAL_MAP_NOT_ALIGNED,
- * XTHAL_BAD_ACCESS_RIGHTS,
- * XTHAL_OUT_OF_ORDER_MAP, or
- * XTHAL_UNSUPPORTED if config doesn't have an MPU.
- */
-int xthal_check_map(const xthal_MPU_entry* fg, unsigned int n)
-{
-#if XCHAL_HAVE_MPU
- return check_map(fg, XCHAL_MPU_ENTRIES, Xthal_mpu_bgmap);
-#else
- return XTHAL_UNSUPPORTED;
-#endif
-}
-#endif
-
-#if defined(__SPLIT__mpu_basic)
-/*
- * Returns the MPU entry that maps 'vaddr'. If 'infgmap' is non-NULL then it is
- * set to 1 if 'vaddr' is mapped by the foreground map, or 0 if 'vaddr'
- * is mapped by the background map.
- */
-extern xthal_MPU_entry xthal_get_entry_for_address(void* paddr, int* infgmap)
- {
-#if XCHAL_HAVE_MPU
- xthal_MPU_entry e;
- unsigned int p;
- __asm__ __volatile__("PPTLB %0, %1\n\t" : "=a" (p) : "a" (paddr));
- if ((p & 0x80000000))
- {
- if (infgmap)
- *infgmap = 1;
- e.at = (p & 0x1fffff);
- __asm__ __volatile__("RPTLB0 %0, %1\n\t" : "=a" (e.as) : "a" (p & 0x1f));
- return e;
- }
- else
- {
- int i;
- if (infgmap)
- *infgmap = 0;
- for (i = XCHAL_MPU_BACKGROUND_ENTRIES - 1; i > 0; i--)
- {
- if (XTHAL_MPU_ENTRY_GET_VSTARTADDR(Xthal_mpu_bgmap[i]) <= (unsigned) paddr)
- {
- return Xthal_mpu_bgmap[i];
- }
- } // in background map
- return Xthal_mpu_bgmap[0];
- }
-#else
- xthal_MPU_entry e;
- return e;
-#endif
- }
-#endif
-/*
- * This function is intended as an MPU specific version of
- * xthal_set_region_attributes(). xthal_set_region_attributes() calls
- * this function for MPU configurations.
- *
- * This function sets the attributes for the region [vaddr, vaddr+size)
- * in the MPU.
- *
- * Depending on the state of the MPU this function will require from
- * 0 to 3 unused MPU entries.
- *
- * This function typically will move, add, and subtract entries from
- * the MPU map during execution, so that the resulting map may
- * be quite different than when the function was called.
- *
- * This function does make the following guarantees:
- * 1) The MPU access map remains in a valid state at all times
- * during its execution.
- * 2) At all points during (and after) completion the memoryType
- * and accessRights remain the same for all addresses
- * that are not in the range [vaddr, vaddr+size).
- * 3) If XTHAL_SUCCESS is returned, then the range
- * [vaddr, vaddr+size) will have the accessRights and memoryType
- * specified.
- *
- * The accessRights parameter should be either a 4-bit value corresponding
- * to an MPU access mode (as defined by the XTHAL_AR_.. constants), or
- * XTHAL_MPU_USE_EXISTING_ACCESS_RIGHTS.
- *
- * The memoryType parameter should be either a bit-wise or-ing of XTHAL_MEM_..
- * constants that represent a valid MPU memoryType, a 9-bit MPU memoryType
- * value, or XTHAL_MPU_USE_EXISTING_MEMORY_TYPE.
- *
- * In addition to the error codes that xthal_set_region_attribute()
- * returns, this function can also return: XTHAL_BAD_ACCESS_RIGHTS
- * (if the access rights bits map to an unsupported combination), or
- * XTHAL_OUT_OF_ENTRIES (if there are not enough unused MPU entries).
- *
- * If this function is called with an invalid MPU map, then this function
- * will return one of the codes that is returned by xthal_check_map().
- *
- * The flag, XTHAL_CAFLAG_EXPAND, is not supported.
- *
- */
-#if defined(__SPLIT__mpu_attributes)
-int xthal_mpu_set_region_attribute(void* vaddr, unsigned size, int accessRights, int memoryType, unsigned flags)
-{
-#if XCHAL_HAVE_MPU
- unsigned int first;
- unsigned int last;
- int rv;
-
- if (flags & XTHAL_CAFLAG_EXPAND)
- return XTHAL_UNSUPPORTED;
- if (size == 0)
- return XTHAL_ZERO_SIZED_REGION;
- first = (unsigned) vaddr;
- last = first + size;
- if (last != 0xFFFFFFFF)
- last--;
- if (first >= last)
- return XTHAL_INVALID_ADDRESS_RANGE; // Wraps around
-
- if (accessRights & XTHAL_MPU_USE_EXISTING_ACCESS_RIGHTS)
- {
- accessRights = XTHAL_MPU_ENTRY_GET_ACCESS(xthal_get_entry_for_address(vaddr, 0));
- }
- else
- {
- accessRights = encode_access_rights(accessRights);
- if (accessRights < 0)
- return XTHAL_BAD_ACCESS_RIGHTS;
- }
- if (memoryType & XTHAL_MPU_USE_EXISTING_MEMORY_TYPE)
- {
- memoryType = XTHAL_MPU_ENTRY_GET_MEMORY_TYPE(xthal_get_entry_for_address(vaddr, 0));
- }
- else
- {
- if (memoryType & 0xffffe000) // Tests if any of the XTHAL MEM flags are present
- memoryType = xthal_encode_memory_type(memoryType);
- else
- if (memoryType & 0xfffffe00) // Tests if any of bits from 9 to 13 are set indicating
- // that the memoryType was improperly shifted
- // we flag this as an error
- return XTHAL_BAD_MEMORY_TYPE;
- if (memoryType < 0)
- return XTHAL_BAD_MEMORY_TYPE;
- }
- if (flags & XTHAL_CAFLAG_EXACT)
- if (!mpu_aligned(first) || !mpu_aligned(last + 1))
- return XTHAL_INEXACT;
-
- first = mpu_align(first, (flags & XTHAL_CAFLAG_NO_PARTIAL));
- if (last != 0xffffffff)
- {
- last = mpu_align(last + 1, !(flags & XTHAL_CAFLAG_NO_PARTIAL));
- if (first >= last)
- return ((flags & XTHAL_CAFLAG_NO_PARTIAL) ? XTHAL_ZERO_SIZED_REGION : 0);
- }
- rv = safe_add_region(first, last, accessRights, memoryType, !(flags & XTHAL_CAFLAG_NO_AUTO_WB),
- !(flags & XTHAL_CAFLAG_NO_AUTO_INV));
- isync();
- return rv;
-#else
- return XTHAL_UNSUPPORTED;
-#endif
-}
-#endif
-
-
-#if defined(__SPLIT__mpu_cachedis)
-
-inline static unsigned int max2(unsigned int a, unsigned int b)
- {
- if (a>b)
- return a;
- else
- return b;
- }
-
-inline static unsigned int mask_cachedis(unsigned int current, int first_region,
- int last_region)
- {
- unsigned int x;
- x = ((1 << (last_region - first_region + 1)) - 1) << first_region;
- current &= ~x;
- return current;
- }
-
-/*
- * xthal_calc_cacheadrdis() computes the value that should be written
- * to the CACHEADRDIS register. The return value has bits 0-7 set according as:
- * bit n: is zero if any part of the region [512MB * n, 512MB* (n-1)) is cacheable.
- * is one if NO part of the region [512MB * n, 512MB* (n-1)) is cacheable.
- *
- * This function looks at both the loops through both the foreground and background maps
- * to find cacheable area. Once one cacheable area is found in a 512MB region, then we
- * skip to the next 512MB region.
- */
-unsigned int xthal_calc_cacheadrdis(const xthal_MPU_entry* fg, unsigned int num_entries)
- {
-#if XCHAL_HAVE_MPU
- unsigned int cachedis = 0xff;
- int fg_index = num_entries - 1;
- int bg_index = XCHAL_MPU_BACKGROUND_ENTRIES - 1;
- int working_region = 7;
- int ending_region;
- unsigned int vaddr = 0xffffffff;
- while (bg_index >= 0 || fg_index >= 0)
- {
- if ((fg_index >= 0 && XTHAL_MPU_ENTRY_GET_VALID(fg[fg_index])))
- {
- vaddr = XTHAL_MPU_ENTRY_GET_VSTARTADDR(fg[fg_index]);
- ending_region = vaddr >> 29;
- if (ending_region <= working_region)
- {
- unsigned int mt = XTHAL_MPU_ENTRY_GET_MEMORY_TYPE(fg[fg_index]);
- if (is_cacheable(mt))
- {
- cachedis = mask_cachedis(cachedis, ending_region,
- working_region);
- /* Optimize since we have found one cacheable entry in the region ... no need to look for more */
- if (ending_region == 0)
- return cachedis;
- else
- working_region = ending_region - 1;
- }
- else
- if (vaddr & 0x1fffffff) // If vaddr is on a 512MB region we want to move to the next region
- working_region = ending_region;
- else
- working_region = ending_region - 1;
- }
- }
- else if ((bg_index >= 0)
- && ((fg_index <= 0)
- || XTHAL_MPU_ENTRY_GET_VALID(fg[fg_index-1]))&& vaddr)
- {
- unsigned int caddr;
- unsigned int low_addr = (
- (fg_index >= 0) ?
- (XTHAL_MPU_ENTRY_GET_VSTARTADDR(fg[fg_index])) :
- 0);
- /* First skip any background entries that start after the address of interest */
- while ((caddr = XTHAL_MPU_ENTRY_GET_VSTARTADDR(Xthal_mpu_bgmap[bg_index])) >= vaddr)
- bg_index--;
- do
- {
- caddr = max2(XTHAL_MPU_ENTRY_GET_VSTARTADDR(Xthal_mpu_bgmap[bg_index]),
- low_addr);
- ending_region = caddr >> 29;
- if (ending_region <= working_region)
- {
- unsigned int mt = XTHAL_MPU_ENTRY_GET_MEMORY_TYPE(
- Xthal_mpu_bgmap[bg_index]);
- if (is_cacheable(mt))
- {
- cachedis = mask_cachedis(cachedis, ending_region,
- working_region);
- /* Optimize since we have found one cacheable entry in the region ...
- * no need to look for more */
- if (ending_region == 0)
- return cachedis; // we are done
- else
- working_region = ending_region - 1;
- }
- else
- if (caddr & 0x1fffffff)
- working_region = ending_region;
- else
- working_region = ending_region - 1;
- }
- bg_index--;
- }while (caddr > low_addr);
- vaddr = caddr;
- }
- fg_index--;
- if (!vaddr)
- break;
- }
- return cachedis;
-#else
- return 0;
-#endif
- }
-#endif
-
-#if defined(__SPLIT__mpu_basic)
-void (*_xthal_assert_handler)();
-/* Undocumented internal testing function */
-extern void _xthal_set_assert_handler(void (*handler)())
-{
-#if XCHAL_HAVE_MPU
- _xthal_assert_handler = handler;
-#endif
-}
-#endif
diff --git a/src/arch/xtensa/smp/hal/mpu_asm.S b/src/arch/xtensa/smp/hal/mpu_asm.S
deleted file mode 100644
index a2a544b..0000000
--- a/src/arch/xtensa/smp/hal/mpu_asm.S
+++ /dev/null
@@ -1,78 +0,0 @@
-//
-// mpu_asm.S - Assembler routine(s) for the MPU
-//
-// $Id$
-
-// Copyright (c) 2015 Tensilica Inc.
-//
-// Permission is hereby granted, free of charge, to any person obtaining
-// a copy of this software and associated documentation files (the
-// "Software"), to deal in the Software without restriction, including
-// without limitation the rights to use, copy, modify, merge, publish,
-// distribute, sublicense, and/or sell copies of the Software, and to
-// permit persons to whom the Software is furnished to do so, subject to
-// the following conditions:
-//
-// The above copyright notice and this permission notice shall be included
-// in all copies or substantial portions of the Software.
-//
-// THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
-// EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
-// MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
-// IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY
-// CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
-// TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
-// SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
-
-#include <xtensa/coreasm.h>
-#include <xtensa/mpuasm.h>
-
-#if defined(__SPLIT__write_map_raw) ||\
- defined(__SPLIT__write_map_raw_nw)
-
-/*
- void xthal_write_map_raw( const struct xthal_MPU_entry* map, unsigned n);
-
- Updates the MPU with the MPU entries provided:
- map pointer to array of MPU entries
- n number of entries in array (0 <= n <= XCHAL_MPU_ENTRIES)
-
- The entries provided must have monotonically increasing addresses.
- This function otherwise orders its updates to ensure the MPU always has
- all its entries in monotonically increasing sequence.
-
- on entry
- a2 => vector of MPU entries to write
- a3 => number of entries to write
- a4-a7 => destroyed
-*/
-
-DECLFUNC (xthal_write_map_raw)
- abi_entry
- mpu_write_map a2, a3, a4, a5, a6, a7
- abi_return
- endfunc
-
-#endif
-
-/*
- void xthal_read_map_raw(struct xthal_MPU_entry* map);
-
- Reads the current map from the MPU and puts it the vector
- pointed to by map.
-
- a2 => vector of MPU entries where the current MPU state is copied
- a3-a4 => destroyed
-*/
-
-#if defined(__SPLIT__read_map_raw) ||\
- defined(__SPLIT__read_map_raw_nw)
-
-DECLFUNC (xthal_read_map_raw)
- abi_entry
- mpu_read_map a2, a3, a4
- abi_return
- endfunc
-
-#endif
-
diff --git a/src/arch/xtensa/smp/hal/set_region_translate.c b/src/arch/xtensa/smp/hal/set_region_translate.c
deleted file mode 100644
index b1b53ed..0000000
--- a/src/arch/xtensa/smp/hal/set_region_translate.c
+++ /dev/null
@@ -1,534 +0,0 @@
-/*
- * Copyright (c) 2004-2014 Tensilica Inc.
- *
- * Permission is hereby granted, free of charge, to any person obtaining
- * a copy of this software and associated documentation files (the
- * "Software"), to deal in the Software without restriction, including
- * without limitation the rights to use, copy, modify, merge, publish,
- * distribute, sublicense, and/or sell copies of the Software, and to
- * permit persons to whom the Software is furnished to do so, subject to
- * the following conditions:
- *
- * The above copyright notice and this permission notice shall be included
- * in all copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
- * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
- * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
- * IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY
- * CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
- * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
- * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
- */
-#include <xtensa/config/core.h>
-
-#if XCHAL_HAVE_XEA2 && (!XCHAL_HAVE_MPU)
-/*
- * C-stubs to issue the tlb related instructions (with dsync and isync's if needed).
- *
- */
-static inline void write_dtlb_entry(unsigned vpn_way, unsigned ppn_ca) {
- __asm__ __volatile__("wdtlb %1, %0; dsync\n\t"
- : : "r" (vpn_way), "r" (ppn_ca) );
-}
-
-static inline void write_itlb_entry(unsigned vpn_way, unsigned ppn_ca) {
- __asm__ __volatile__("witlb %1, %0; isync\n\t"
- : : "r" (vpn_way), "r" (ppn_ca) );
-}
-
-static inline unsigned read_dtlb1_entry(unsigned addr) {
- unsigned long tmp;
- __asm__ __volatile__("rdtlb1 %0, %1\n\t"
- : "=a" (tmp)
- : "a" (addr));
- return tmp;
-}
-
-static inline unsigned read_itlb1_entry(unsigned addr) {
- unsigned long tmp;
- __asm__ __volatile__("ritlb1 %0, %1\n\t"
- : "=a" (tmp)
- : "a" (addr));
- return tmp;
-}
-
-static inline unsigned probe_dtlb(unsigned addr) {
- unsigned long tmp;
- __asm__ __volatile__("pdtlb %0, %1\n\t"
- : "=a" (tmp)
- : "a" (addr));
- return tmp;
-}
-
-static inline unsigned probe_itlb(unsigned addr) {
- unsigned long tmp;
- __asm__ __volatile__("pitlb %0, %1\n\t"
- : "=a" (tmp)
- : "a" (addr));
- return tmp;
-}
-
-static inline void invalidate_dtlb_entry(unsigned addr) {
- __asm__ __volatile__("idtlb %0; dsync \n\t"
- : : "a" (addr));
-}
-
-static inline void invalidate_itlb_entry(unsigned addr) {
- __asm__ __volatile__("iitlb %0 ; isync\n\t"
- : : "a" (addr));
-}
-
-static inline unsigned read_dtlbcfg() {
- unsigned long tmp;
- __asm__ __volatile__("rsr.dtlbcfg %0\n\t"
- : "=a" (tmp));
- return tmp;
-}
-
-static inline unsigned read_itlbcfg() {
- unsigned long tmp;
- __asm__ __volatile__("rsr.itlbcfg %0\n\t"
- : "=a" (tmp));
- return tmp;
-}
-
-#endif
-
-/*
- * xthal_set_region_translation_raw is a quick and simple function
- * to set both physical address <paddr> and cache attribute <cattr> for
- * a 512MB region at <vaddr>.
- *
- * Parameters:
- * void* vaddr 512MB aligned pointer representing the start of virtual address region
- * void* paddr 512MB aligned pointer representing the start of physical address region
- * unsigned cattr 4 bit value encoding the caching properties and rights (MMU only).
- *
- * returns 0 (XCHAL_SUCCESS) if successful
- * returns non zero (XCHAL_UNSUPPORTED) on failure
- *
- * This function has the following limitations:
- *
- * 1) Requires either the Region Translation Option or a v3 MMU running in the default mode (with spanning way)
- * 2) It does no error checking.
- * 3) Deals with one 512MB region (vaddr and paddr are required to be 512MB aligned although that is not explicitly checked)
- * 4) It requires the caller to do any cache flushing that is needed
- * 5) Doesn't support mnemonically setting the 'rights' (rwx, rw, ... ) bit on the MMU
- * 6) It is illegal to change the mapping of the region containing the current PC (not checked)
- *
- */
-int xthal_set_region_translation_raw(void *vaddr, void *paddr, unsigned cattr) {
-#if XCHAL_HAVE_MPU
- return XTHAL_UNSUPPORTED;
-#else
-#if XCHAL_HAVE_XEA2
-#if XCHAL_HAVE_XLT_CACHEATTR || (XCHAL_HAVE_PTP_MMU && XCHAL_HAVE_SPANNING_WAY)
-# if XCHAL_HAVE_XLT_CACHEATTR
- unsigned vpn_way = (unsigned)vaddr;
-# else
- unsigned vpn_way = ((unsigned) vaddr & 0xFFFFFFF0) + XCHAL_SPANNING_WAY;
-# endif
- unsigned ppn_ca = ((unsigned) paddr & 0xFFFFFFF0) + (cattr & 0xF);
- write_dtlb_entry(vpn_way, ppn_ca);
- write_itlb_entry(vpn_way, ppn_ca);
- return XTHAL_SUCCESS;
-#else
- return XTHAL_UNSUPPORTED;
-#endif
-#else
- return XTHAL_UNSUPPORTED;
-#endif
-#endif
-}
-
-/*
- * xthal_v2p() takes a virtual address as input, and if that virtual address is mapped to a physical address
- * by the MMU, it returns the:
- * a) corresponding physical address
- * b) the tlb way that is used to translate the address
- * c) cache attribute for translation
- *
- * Parameters:
- * void* vaddr A pointer representing the virtual address (there are no alignment requirements for this address)
- * void** paddr This value can be 0, or can point to a pointer variable which will be updated to contain the physical address
- * unsigned* way This value can be 0, or can point to an unsigned variable which will be updated to contain the TLB way.
- * unsigned* cattr This value can be 0, or can point to an unsigned variable which will be updated to contain the cache attr
- * For MPU configurations bits 0..3 hold the access rights and bits 4..8 hold the encoded memory type
- *
- * Returns 0 (XCHAL_SUCCESS) if successful
- * XTHAL_NO_MAPPING if there is no current mapping for the virtual address
- * XCHAL_UNSUPPORTED if unsupported
- *
- * Limitations:
- * Assumes that architecture variable DVARWAY56 is "Variable"
- * Uses the D-TLBS for the translation ... assumption is that ITLB's have same mappings
- */
-int xthal_v2p(void* vaddr, void** paddr, unsigned *way, unsigned* cattr) {
-#if XCHAL_HAVE_XEA2
-#if XCHAL_HAVE_MPU
- if (paddr)
- *paddr = vaddr;
- if (way)
- *way = 0;
- if (cattr)
- {
- struct xthal_MPU_entry x = xthal_get_entry_for_address(vaddr, 0);
- *cattr = XTHAL_MPU_ENTRY_GET_ACCESS(x) | XTHAL_MPU_ENTRY_GET_MEMORY_TYPE(x) << XTHAL_AR_WIDTH;
- }
- return XTHAL_SUCCESS;
-#else
- unsigned long probe = probe_dtlb((unsigned) vaddr);
-#if !XCHAL_HAVE_PTP_MMU
- if (!(0x1 & probe))
- return XTHAL_NO_MAPPING;
- if (way)
- *way = 1;
- if (paddr || cattr) {
- unsigned long temp;
- temp = read_dtlb1_entry(probe);
- unsigned ppn = 0xe0000000 & temp;
- unsigned att = 0xf & temp;
- if (paddr)
- *paddr = ((void*) (ppn + (((unsigned) vaddr) & 0x1fffffff)));
- if (cattr)
- *cattr = att;
- }
-#else
- {
- unsigned iway;
- if (!(0x10 & probe))
- return XTHAL_NO_MAPPING;
- iway = 0xf & probe;
- if (way)
- *way = iway;
- if (paddr || cattr) {
- unsigned temp;
- unsigned ppn;
- unsigned ppn1;
- unsigned dtlbcfg = read_dtlbcfg();
- temp = read_dtlb1_entry(probe);
- unsigned att = 0xf & temp;
- if (cattr)
- *cattr = att;
- if (paddr)
- switch (iway) // followin code derived from fig 4-40 from ISA MMU Option Data (at) Format for RxTLB1
- { /* 4k pages */
- case 0:
- case 1:
- case 2:
- case 3:
- case 7:
- case 8:
- case 9:
- ppn = 0xfffff000; // 4k pages
- break;
- case 4: {
- switch ((dtlbcfg & (0x3 << 16)) >> 16) // bits 16 & 17
- {
- case 0: // 1MB pages
- ppn = 0xfff00000;
- break;
- case 1: // 4MB pages
- ppn = 0xffc00000;
- break;
- case 2: // 16MB pages
- ppn = 0xff000000;
- break;
- case 3: // 64MB pages
- ppn = 0xfc000000;
- break;
- default:
- return XTHAL_UNSUPPORTED;
- }
- }
- break;
- case 5:
- if ((dtlbcfg & (1 << 20)))
- ppn = 0xf8000000; // 128MB pages
- else
- ppn = 0xf0000000; // 256MB pages
- break;
- case 6:
- if ((dtlbcfg & (1 << 24)))
- ppn = 0xe0000000; // 512MB pages
- else
- ppn = 0xf0000000; // 256MB pages
- break;
- default:
- return XTHAL_UNSUPPORTED;
- break;
- }
- ppn1 = ppn & temp;
- *paddr = ((void*) (ppn1 + (((unsigned) vaddr) & (~ppn))));
- }
- }
-#endif
- return XTHAL_SUCCESS;
-#endif
-#else
- return XTHAL_UNSUPPORTED;
-#endif
-}
-
-/* these constants borrowed from xthal_set_region_attribute */
-# if XCHAL_HAVE_PTP_MMU
-# define CA_BYPASS XCHAL_CA_BYPASS
-# define CA_WRITETHRU XCHAL_CA_WRITETHRU
-# define CA_WRITEBACK XCHAL_CA_WRITEBACK
-# define CA_WRITEBACK_NOALLOC XCHAL_CA_WRITEBACK_NOALLOC
-# define CA_ILLEGAL XCHAL_CA_ILLEGAL
-# else
-/* Hardcode these, because they get remapped when caches or writeback not configured: */
-# define CA_BYPASS 2
-# define CA_WRITETHRU 1
-# define CA_WRITEBACK 4
-# define CA_WRITEBACK_NOALLOC 5
-# define CA_ILLEGAL 15
-# endif
-
-/* internal function that returns 1 if the supplied attr indicates the
- * cache is in writeback mode.
- */
-static inline int is_writeback(unsigned attr) {
-#if XCHAL_HAVE_XLT_CACHEATTR
- return attr == CA_WRITEBACK || attr == CA_WRITEBACK_NOALLOC;
-#endif
-#if XCHAL_HAVE_PTP_MMU && XCHAL_HAVE_SPANNING_WAY
- return (attr | 0x3) == CA_WRITEBACK;
-#endif
- return -1; /* unsupported */
-}
-
-/*
- * xthal_set_region_translation()
- *
- * Establishes a new mapping (with the supplied cache attributes)
- * between a virtual address region, and a physical address region.
- *
- * This function is only supported with following processor configurations:
- * a) Region Translation
- * b) v3 MMU with a spanning way running in the default mode
- *
- * If the specified memory range exactly covers a series
- * of consecutive 512 MB regions, the address mapping and cache
- * attributes of these regions are updated.
- *
- * If this is not the case, e.g. if either or both the
- * start and end of the range only partially cover a 512 MB
- * region, one of three results are possible:
- *
- * 1. By default, the cache attribute of all regions
- * covered, even just partially, is changed to
- * the requested attribute.
- *
- * 2. If the XTHAL_CAFLAG_EXACT flag is specified,
- * a non-zero error code is returned.
- *
- * 3. If the XTHAL_CAFLAG_NO_PARTIAL flag is specified
- * (but not the EXACT flag), only regions fully
- * covered by the specified range are updated with
- * the requested attribute.
- *
- * CACHE HANDLING
- *
- * This function automatically writes back dirty data before remapping a
- * virtual address region.
- *
- * This writeback is done safely, ie. by first switching to writethrough
- * mode, and then invoking xthal_dcache_all_writeback(). Such a sequence is
- * necessary to ensure there is no longer any dirty data in the memory region by the time
- * this function returns, even in the presence of interrupts, speculation, etc.
- * This automatic write-back can be disabled using the XTHAL_CAFLAG_NO_AUTO_WB flag.
- *
- * This function also invalidates the caches after remapping a region because the
- * cache could contain (now invalid) data from the previous mapping.
- * This automatic invalidate can be disabled using the XTHAL_CAFLAG_NO_AUTO_INV flag.
- *
- * Parameters:
- * vaddr starting virtual address of region of memory
- *
- * paddr starting physical address for the mapping (this should be 512MB aligned to vaddr such that ((vaddr ^ paddr) & 0x10000000 == 0)
- *
- * size number of bytes in region of memory
- * (see above, SPECIFYING THE MEMORY REGION)
- *
- * cattr cache attribute (encoded);
- * typically taken from compile-time HAL constants
- * XCHAL_CA_{BYPASS, WRITETHRU, WRITEBACK[_NOALLOC], ILLEGAL}
- * (defined in <xtensa/config/core.h>);
- * in XEA1, this corresponds to the value of a nibble
- * in the CACHEATTR register;
- * in XEA2, this corresponds to the value of the
- * cache attribute (CA) field of each TLB entry
- *
- * flags bitwise combination of flags XTHAL_CAFLAG_*
- *
- * XTHAL_CAFLAG_EXACT - If this flag is present,
- * the mapping will only be done if the specified
- * region exactly matches on or more 512MB pages otherwise
- * XCHAL_INEXACT is returned (and no mapping is done).
- *
- * XTHAL_CAFLAG_NO_PARTIAL - If this flag is specified, then
- * only pages that are completely covered by the specified region
- * are affected. If this flag is specified, and no pages are completely
- * covered by the region, then no pages are affected and XCHAL_NO_REGIONS_COVERED
- * is returned.
- *
- *
- *
- * Returns:
- * XCHAL_SUCCESS - successful, or size is zero
- *
- * XCHAL_NO_REGIONS_COVERED - XTHAL_CAFLAG_NO_PARTIAL flag specified and address range
- * is valid with a non-zero size, however no 512 MB region (or page)
- * is completely covered by the range
- *
- * XCHAL_INEXACT XTHAL_CAFLAG_EXACT flag specified, and address range does
- * not exactly specify a 512 MB region (or page)
- *
- * XCHAL_INVALID_ADDRESS invalid address range specified (wraps around the end of memory)
- *
- * XCHAL_ADDRESS_MISALIGNED virtual and physical addresses are not aligned (512MB)
- *
- *
- * XCHAL_UNSUPPORTED_ON_THIS_ARCH function not supported in this processor configuration
- */
-int xthal_set_region_translation(void* vaddr, void* paddr, unsigned size,
- unsigned cattr, unsigned flags) {
-#if XCHAL_HAVE_XEA2 & !XCHAL_HAVE_MPU
-#if XCHAL_HAVE_XLT_CACHEATTR || (XCHAL_HAVE_PTP_MMU && XCHAL_HAVE_SPANNING_WAY)
- const unsigned CA_MASK = 0xF;
- const unsigned addr_mask = 0x1fffffff;
- const unsigned addr_shift = 29;
- unsigned vaddr_a = (unsigned) vaddr;
- unsigned paddr_a = (unsigned) paddr;
- unsigned end_vaddr;
- unsigned end_paddr;
- unsigned start_va_reg;
- unsigned end_va_reg;
- unsigned start_pa_reg;
- unsigned icache_attr = 0;
- int rv;
- int i;
- if (size == 0)
- return XTHAL_SUCCESS;
- if ((vaddr_a & addr_mask) ^ (paddr_a & addr_mask))
- return XTHAL_ADDRESS_MISALIGNED;
- icache_attr = cattr & CA_MASK;
-#if (XCHAL_HAVE_PTP_MMU && XCHAL_HAVE_SPANNING_WAY)
- // if using the mmu in spanning way mode then 'and in' the R, RX, RW, RWX bits
- if ((cattr & 0x40000000) && (icache_attr < 12))
- icache_attr = icache_attr & ((cattr & 0xF0) >> 4);
-#endif
- end_vaddr = vaddr_a + size - 1;
- end_paddr = paddr_a + size - 1;
-
- if ((end_vaddr < vaddr_a) || (end_paddr < paddr_a))
- return XTHAL_INVALID_ADDRESS;
- start_va_reg = vaddr_a >> addr_shift;
- end_va_reg = end_vaddr >> addr_shift;
- start_pa_reg = paddr_a >> addr_shift;
- if ((flags & XTHAL_CAFLAG_EXACT)
- && ((size & addr_mask) || (vaddr_a & addr_mask)
- || (paddr_a & addr_mask)))
- return XTHAL_INEXACT;
- if (flags & XTHAL_CAFLAG_NO_PARTIAL) {
- if (vaddr_a & addr_mask) {
- start_va_reg++;
- start_pa_reg++;
- }
- if ((end_vaddr & addr_mask) != addr_mask)
- end_va_reg--;
- }
- if (end_va_reg < start_va_reg)
- return XTHAL_NO_REGIONS_COVERED;
- /*
- * Now we need to take care of any uncommitted cache writes in the affected regions
- * 1) first determine if any regions are in write back mode
- * 2) change those pages to write through
- * 3) force the writeback of d-cache by calling xthal_dcach_all_writeback()
- */
-#if ((XCHAL_DCACHE_SIZE >0) && XCHAL_DCACHE_IS_WRITEBACK)
- if (!(flags & XTHAL_CAFLAG_NO_AUTO_WB)) {
- unsigned old_cache_attr = xthal_get_cacheattr();
- unsigned cachewrtr = old_cache_attr;
- unsigned need_safe_writeback = 0;
- for (i = start_va_reg; i <= end_va_reg; i++) {
- unsigned sh = i << 2;
- unsigned old_attr = (old_cache_attr >> sh) & CA_MASK;
- if (is_writeback(old_attr)) {
- need_safe_writeback = 1;
- cachewrtr = (cachewrtr & ~(CA_MASK << sh))
- | (CA_WRITETHRU << sh);
- }
- }
-
- if (need_safe_writeback) {
- xthal_set_cacheattr(cachewrtr); /* set to writethru first, to safely writeback any dirty data */
- xthal_dcache_all_writeback(); /* much quicker than scanning entire 512MB region(s) */
- }
- }
-#endif
- /* Now we set the affected region translations */
- for (i = start_va_reg; i <= end_va_reg; i++) {
- if ((rv = xthal_set_region_translation_raw(
- (void*) ((start_va_reg++) << addr_shift),
- (void*) ((start_pa_reg++) << addr_shift), icache_attr)))
- return rv;
- }
-
- /*
- * Now we need to invalidate the cache in the affected regions. For now invalidate entire cache,
- * but investigate if there are faster alternatives on some architectures.
- */
- if (!(flags & XTHAL_CAFLAG_NO_AUTO_INV)) {
-# if XCHAL_DCACHE_SIZE > 0
- xthal_dcache_all_writeback_inv(); /* some areas in memory (outside the intended region) may have uncommitted
- data so we need the writeback_inv(). */
-#endif
-#if XCHAL_ICACHE_SIZE >0
- xthal_icache_all_invalidate();
-#endif
- }
- return XTHAL_SUCCESS;
-#else
- return XTHAL_UNSUPPORTED;
-#endif
-#else
- return XTHAL_UNSUPPORTED;
-#endif
-}
-
-/* xthal_invalidate_region()
- * invalidates the tlb entry for the specified region.
- *
- * This function is only supported on processor configurations
- * with a v3 MMU with a spanning way.
- *
- * Parameter
- * vaddr - virtual address of region to invalidate (512MB aligned)
- *
- * returns:
- * XCHAL_SUCCESS - Success
- * XCHAL_UNSUPPORTED_ON_THIS_ARCH - Unsupported
- *
- */
-int xthal_invalidate_region(void* vaddr) {
-#if XCHAL_HAVE_XEA2 & !XCHAL_HAVE_MPU
-#if (XCHAL_HAVE_PTP_MMU && XCHAL_HAVE_SPANNING_WAY)
- unsigned addr = (unsigned) vaddr;
- if (addr & 0x1fffffff)
- return XTHAL_INVALID_ADDRESS;
- addr += XCHAL_SPANNING_WAY;
- invalidate_dtlb_entry(addr);
- invalidate_itlb_entry(addr);
- return XTHAL_SUCCESS;
-#else
- return XTHAL_UNSUPPORTED;
-#endif
-#else
- return XTHAL_UNSUPPORTED;
-#endif
-}
-
diff --git a/src/arch/xtensa/smp/hal/state.c b/src/arch/xtensa/smp/hal/state.c
deleted file mode 100644
index 316ddb4..0000000
--- a/src/arch/xtensa/smp/hal/state.c
+++ /dev/null
@@ -1,321 +0,0 @@
-//
-// processor_state.c - processor state management routines
-//
-
-// Copyright (c) 2005-2010 Tensilica Inc.
-//
-// Permission is hereby granted, free of charge, to any person obtaining
-// a copy of this software and associated documentation files (the
-// "Software"), to deal in the Software without restriction, including
-// without limitation the rights to use, copy, modify, merge, publish,
-// distribute, sublicense, and/or sell copies of the Software, and to
-// permit persons to whom the Software is furnished to do so, subject to
-// the following conditions:
-//
-// The above copyright notice and this permission notice shall be included
-// in all copies or substantial portions of the Software.
-//
-// THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
-// EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
-// MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
-// IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY
-// CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
-// TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
-// SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
-
-#include <xtensa/hal.h>
-#include <xtensa/config/core.h>
-
-
-//----------------------------------------------------------------------
-
-#if defined(__SPLIT__extra_size)
-// space for "extra" (user special registers and non-coprocessor TIE) state:
-const unsigned int Xthal_extra_size = XCHAL_NCP_SA_SIZE;
-
-#elif defined(__SPLIT__extra_align)
-const unsigned int Xthal_extra_align = XCHAL_NCP_SA_ALIGN;
-
-#elif defined(__SPLIT__cpregs_size)
-// space for state of TIE coprocessors:
-const unsigned int Xthal_cpregs_size[8] =
- {
- XCHAL_CP0_SA_SIZE,
- XCHAL_CP1_SA_SIZE,
- XCHAL_CP2_SA_SIZE,
- XCHAL_CP3_SA_SIZE,
- XCHAL_CP4_SA_SIZE,
- XCHAL_CP5_SA_SIZE,
- XCHAL_CP6_SA_SIZE,
- XCHAL_CP7_SA_SIZE
- };
-
-#elif defined(__SPLIT__cpregs_align)
-const unsigned int Xthal_cpregs_align[8] =
- {
- XCHAL_CP0_SA_ALIGN,
- XCHAL_CP1_SA_ALIGN,
- XCHAL_CP2_SA_ALIGN,
- XCHAL_CP3_SA_ALIGN,
- XCHAL_CP4_SA_ALIGN,
- XCHAL_CP5_SA_ALIGN,
- XCHAL_CP6_SA_ALIGN,
- XCHAL_CP7_SA_ALIGN
- };
-
-#elif defined(__SPLIT__cp_names)
-const char * const Xthal_cp_names[8] =
- {
- XCHAL_CP0_NAME,
- XCHAL_CP1_NAME,
- XCHAL_CP2_NAME,
- XCHAL_CP3_NAME,
- XCHAL_CP4_NAME,
- XCHAL_CP5_NAME,
- XCHAL_CP6_NAME,
- XCHAL_CP7_NAME
- };
-
-#elif defined(__SPLIT__all_extra_size)
-// total save area size (extra + all coprocessors + min 16-byte alignment everywhere)
-const unsigned int Xthal_all_extra_size = XCHAL_TOTAL_SA_SIZE;
-
-#elif defined(__SPLIT__all_extra_align)
-// maximum required alignment for the total save area (this might be useful):
-const unsigned int Xthal_all_extra_align = XCHAL_TOTAL_SA_ALIGN;
-
-#elif defined(__SPLIT__num_coprocessors)
-// number of coprocessors starting contiguously from zero
-// (same as Xthal_cp_max, but included for Tornado2):
-const unsigned int Xthal_num_coprocessors = XCHAL_CP_MAX;
-
-#elif defined(__SPLIT__cp_num)
-// actual number of coprocessors:
-const unsigned char Xthal_cp_num = XCHAL_CP_NUM;
-
-#elif defined(__SPLIT__cp_max)
-// index of highest numbered coprocessor, plus one:
-const unsigned char Xthal_cp_max = XCHAL_CP_MAX;
-
-// index of highest allowed coprocessor number, per cfg, plus one:
-//const unsigned char Xthal_cp_maxcfg = XCHAL_CP_MAXCFG;
-
-#elif defined(__SPLIT__cp_mask)
-// bitmask of which coprocessors are present:
-const unsigned int Xthal_cp_mask = XCHAL_CP_MASK;
-
-#elif defined(__SPLIT__cp_id_mappings)
-// Coprocessor ID from its name
-
-# ifdef XCHAL_CP0_IDENT
-const unsigned char XCJOIN(Xthal_cp_id_,XCHAL_CP0_IDENT) = 0;
-# endif
-# ifdef XCHAL_CP1_IDENT
-const unsigned char XCJOIN(Xthal_cp_id_,XCHAL_CP1_IDENT) = 1;
-# endif
-# ifdef XCHAL_CP2_IDENT
-const unsigned char XCJOIN(Xthal_cp_id_,XCHAL_CP2_IDENT) = 2;
-# endif
-# ifdef XCHAL_CP3_IDENT
-const unsigned char XCJOIN(Xthal_cp_id_,XCHAL_CP3_IDENT) = 3;
-# endif
-# ifdef XCHAL_CP4_IDENT
-const unsigned char XCJOIN(Xthal_cp_id_,XCHAL_CP4_IDENT) = 4;
-# endif
-# ifdef XCHAL_CP5_IDENT
-const unsigned char XCJOIN(Xthal_cp_id_,XCHAL_CP5_IDENT) = 5;
-# endif
-# ifdef XCHAL_CP6_IDENT
-const unsigned char XCJOIN(Xthal_cp_id_,XCHAL_CP6_IDENT) = 6;
-# endif
-# ifdef XCHAL_CP7_IDENT
-const unsigned char XCJOIN(Xthal_cp_id_,XCHAL_CP7_IDENT) = 7;
-# endif
-
-#elif defined(__SPLIT__cp_mask_mappings)
-// Coprocessor "mask" (1 << ID) from its name
-
-# ifdef XCHAL_CP0_IDENT
-const unsigned int XCJOIN(Xthal_cp_mask_,XCHAL_CP0_IDENT) = (1 << 0);
-# endif
-# ifdef XCHAL_CP1_IDENT
-const unsigned int XCJOIN(Xthal_cp_mask_,XCHAL_CP1_IDENT) = (1 << 1);
-# endif
-# ifdef XCHAL_CP2_IDENT
-const unsigned int XCJOIN(Xthal_cp_mask_,XCHAL_CP2_IDENT) = (1 << 2);
-# endif
-# ifdef XCHAL_CP3_IDENT
-const unsigned int XCJOIN(Xthal_cp_mask_,XCHAL_CP3_IDENT) = (1 << 3);
-# endif
-# ifdef XCHAL_CP4_IDENT
-const unsigned int XCJOIN(Xthal_cp_mask_,XCHAL_CP4_IDENT) = (1 << 4);
-# endif
-# ifdef XCHAL_CP5_IDENT
-const unsigned int XCJOIN(Xthal_cp_mask_,XCHAL_CP5_IDENT) = (1 << 5);
-# endif
-# ifdef XCHAL_CP6_IDENT
-const unsigned int XCJOIN(Xthal_cp_mask_,XCHAL_CP6_IDENT) = (1 << 6);
-# endif
-# ifdef XCHAL_CP7_IDENT
-const unsigned int XCJOIN(Xthal_cp_mask_,XCHAL_CP7_IDENT) = (1 << 7);
-# endif
-
-//----------------------------------------------------------------------
-
-#elif defined(__SPLIT__init_mem_extra)
-// CMS: I have made the assumptions that 0's are safe initial
-// values. That may be wrong at some point.
-//
-// initialize the extra processor
-void
-xthal_init_mem_extra(void *address)
-/* not clear that it is safe to call memcpy and also not clear
- that performance is important. */
-{
- unsigned int *ptr;
- unsigned int *end;
-
- ptr = (unsigned int *)address;
- end = (unsigned int *)((int)address + XCHAL_NCP_SA_SIZE);
- while( ptr < end )
- {
- *ptr++ = 0;
- }
-}
-
-#elif defined(__SPLIT__init_mem_cp)
-// initialize the TIE coprocessor
-void
-xthal_init_mem_cp(void *address, int cp)
-{
- unsigned int *ptr;
- unsigned int *end;
-
- if( cp <= 7 )
- {
- end = (unsigned int *)((int)address + Xthal_cpregs_size[cp]);
- ptr = (unsigned int *)address;
- while( ptr < end )
- {
- *ptr++ = 0;
- }
- }
-}
-
-#endif /*splitting*/
-
-
-/* Nothing implemented below this point. */
-/************************************************************************/
-
-// save all extra+cp processor state (NOT IMPLEMENTED)
-/*void xthal_save_all_extra(void *base)
-{
- xthal_save_extra(base);
- ... here we need to iterate over configured coprocessor register files ...
-// xthal_save_cpregs(base+XCHAL_NCP_SA_SIZE, 0);
-}*/
-
-// restore all extra+cp processor state (NOT IMPLEMENTED)
-/*void xthal_restore_all_extra(void *base)
-{
- xthal_restore_extra(base);
- ... here we need to iterate over configured coprocessor register files ...
-// xthal_restore_cpregs(base+XCHAL_NCP_SA_SIZE, 0);
-}*/
-
-
-// initialize the extra processor (NOT IMPLEMENTED)
-/*void xthal_init_extra()
-{
-}*/
-
-// initialize the TIE coprocessor (NOT IMPLEMENTED)
-/*void xthal_init_cp(int cp)
-{
-}*/
-
-
-#if 0
-
-/* read extra state register (NOT IMPLEMENTED) */
-int xthal_read_extra(void *base, unsigned reg, unsigned *value)
-{
- if (reg&0x1000) {
- switch(reg) {
-#if XCHAL_HAVE_MAC16
- case 16:
- *value = ((unsigned *)base)[0];
- return reg;
- case 17:
- *value = ((unsigned *)base)[1];
- return reg;
- case 32:
- *value = ((unsigned *)base)[2];
- return reg;
- case 33:
- *value = ((unsigned *)base)[3];
- return reg;
- case 34:
- *value = ((unsigned *)base)[4];
- return reg;
- case 35:
- *value = ((unsigned *)base)[5];
- return reg;
-#endif /* XCHAL_HAVE_MAC16 */
- }
- }
- return -1;
-}
-
-/* write extra state register (NOT IMPLEMENTED) */
-int xthal_write_extra(void *base, unsigned reg, unsigned value)
-{
- if (reg&0x1000) {
- switch(reg) {
-#if XCHAL_HAVE_MAC16
- case 16:
- ((unsigned *)base)[0] = value;
- return reg;
- case 17:
- ((unsigned *)base)[1] = value;
- return reg;
- case 32:
- ((unsigned *)base)[2] = value;
- return reg;
- case 33:
- ((unsigned *)base)[3] = value;
- return reg;
- case 34:
- ((unsigned *)base)[4] = value;
- return reg;
- case 35:
- ((unsigned *)base)[5] = value;
- return reg;
-#endif /* XCHAL_HAVE_MAC16 */
- }
- }
- return -1;
-}
-
-#endif /*0*/
-
-
-/* read TIE coprocessor register (NOT IMPLEMENTED) */
-/*int xthal_read_cpreg(void *base, int cp, unsigned reg, unsigned *value)
-{
- return -1;
-}*/
-
-/* write TIE coproessor register (NOT IMPLEMENTED) */
-/*int xthal_write_cpreg(void *base, int cp, unsigned reg, unsigned value)
-{
- return -1;
-}*/
-
-/* return coprocessor number based on register (NOT IMPLEMENTED) */
-/*int xthal_which_cp(unsigned reg)
-{
- return -1;
-}*/
-
diff --git a/src/arch/xtensa/smp/hal/state_asm.S b/src/arch/xtensa/smp/hal/state_asm.S
deleted file mode 100644
index 1089862..0000000
--- a/src/arch/xtensa/smp/hal/state_asm.S
+++ /dev/null
@@ -1,433 +0,0 @@
-/*
- * state_asm.S - assembly language processor management routines
- */
-
-/*
- * Copyright (c) 2005-2010 Tensilica Inc.
- *
- * Permission is hereby granted, free of charge, to any person obtaining
- * a copy of this software and associated documentation files (the
- * "Software"), to deal in the Software without restriction, including
- * without limitation the rights to use, copy, modify, merge, publish,
- * distribute, sublicense, and/or sell copies of the Software, and to
- * permit persons to whom the Software is furnished to do so, subject to
- * the following conditions:
- *
- * The above copyright notice and this permission notice shall be included
- * in all copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
- * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
- * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
- * IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY
- * CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
- * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
- * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
- */
-
-#include <xtensa/coreasm.h>
-
- .text
-
-//----------------------------------------------------------------------
-// save the extra processor state.
-//----------------------------------------------------------------------
-
-#if defined(__SPLIT__save_extra) ||\
- defined(__SPLIT__save_extra_nw)
-
-// void xthal_save_extra(void *base)
-
-DECLFUNC(xthal_save_extra)
- abi_entry
- xchal_extra_store_funcbody
- abi_return
- endfunc
-
-
-//----------------------------------------------------------------------
-// restore the extra processor state.
-//----------------------------------------------------------------------
-
-#elif defined(__SPLIT__restore_extra) ||\
- defined(__SPLIT__restore_extra_nw)
-
-// void xthal_restore_extra(void *base)
-
-DECLFUNC(xthal_restore_extra)
- abi_entry
- xchal_extra_load_funcbody
- abi_return
- endfunc
-
-//----------------------------------------------------------------------
-// save the TIE COPROCESSORS state
-//----------------------------------------------------------------------
-
-#elif defined(__SPLIT__save_cpregs) ||\
- defined(__SPLIT__save_cpregs_nw)
-
-// void xthal_save_cpregs(void *base, int)
-DECLFUNC(xthal_save_cpregs)
- abi_entry
- xchal_cpi_store_funcbody
- abi_return
- endfunc
-#elif defined(__SPLIT__save_cp0) ||\
- defined(__SPLIT__save_cp0_nw)
-// void xthal_save_cp0(void *base)
-DECLFUNC(xthal_save_cp0)
- abi_entry
- xchal_cp0_store_a2
- abi_return
- endfunc
-#elif defined(__SPLIT__save_cp1) ||\
- defined(__SPLIT__save_cp1_nw)
-// void xthal_save_cp1(void *base)
-DECLFUNC(xthal_save_cp1)
- abi_entry
- xchal_cp1_store_a2
- abi_return
- endfunc
-#elif defined(__SPLIT__save_cp2) ||\
- defined(__SPLIT__save_cp2_nw)
-// void xthal_save_cp2(void *base)
-DECLFUNC(xthal_save_cp2)
- abi_entry
- xchal_cp2_store_a2
- abi_return
- endfunc
-#elif defined(__SPLIT__save_cp3) ||\
- defined(__SPLIT__save_cp3_nw)
-// void xthal_save_cp3(void *base)
-DECLFUNC(xthal_save_cp3)
- abi_entry
- xchal_cp3_store_a2
- abi_return
- endfunc
-#elif defined(__SPLIT__save_cp4) ||\
- defined(__SPLIT__save_cp4_nw)
-// void xthal_save_cp4(void *base)
-DECLFUNC(xthal_save_cp4)
- abi_entry
- xchal_cp4_store_a2
- abi_return
- endfunc
-#elif defined(__SPLIT__save_cp5) ||\
- defined(__SPLIT__save_cp5_nw)
-// void xthal_save_cp5(void *base)
-DECLFUNC(xthal_save_cp5)
- abi_entry
- xchal_cp5_store_a2
- abi_return
- endfunc
-#elif defined(__SPLIT__save_cp6) || \
- defined(__SPLIT__save_cp6_nw)
-// void xthal_save_cp6(void *base)
-DECLFUNC(xthal_save_cp6)
- abi_entry
- xchal_cp6_store_a2
- abi_return
- endfunc
-#elif defined(__SPLIT__save_cp7) ||\
- defined(__SPLIT__save_cp7_nw)
-// void xthal_save_cp7(void *base)
-DECLFUNC(xthal_save_cp7)
- abi_entry
- xchal_cp7_store_a2
- abi_return
- endfunc
-
-//----------------------------------------------------------------------
-// restore the TIE coprocessor state
-//----------------------------------------------------------------------
-
-#elif defined(__SPLIT__restore_cpregs) ||\
- defined(__SPLIT__restore_cpregs_nw)
-
-// void xthal_restore_cpregs(void *base, int)
-
-DECLFUNC(xthal_restore_cpregs)
- abi_entry
- xchal_cpi_load_funcbody
- abi_return
- endfunc
-#elif defined(__SPLIT__restore_cp0) ||\
- defined(__SPLIT__restore_cp0_nw)
-// void xthal_restore_cp0(void *base)
-DECLFUNC(xthal_restore_cp0)
- abi_entry
- xchal_cp0_load_a2
- abi_return
- endfunc
-#elif defined(__SPLIT__restore_cp1) ||\
- defined(__SPLIT__restore_cp1_nw)
-// void xthal_restore_cp1(void *base)
-DECLFUNC(xthal_restore_cp1)
- abi_entry
- xchal_cp1_load_a2
- abi_return
- endfunc
-#elif defined(__SPLIT__restore_cp2) ||\
- defined(__SPLIT__restore_cp2_nw)
-// void xthal_restore_cp2(void *base)
-DECLFUNC(xthal_restore_cp2)
- abi_entry
- xchal_cp2_load_a2
- abi_return
- endfunc
-#elif defined(__SPLIT__restore_cp3) || \
- defined(__SPLIT__restore_cp3_nw)
-// void xthal_restore_cp3(void *base)
-DECLFUNC(xthal_restore_cp3)
- abi_entry
- xchal_cp3_load_a2
- abi_return
- endfunc
-#elif defined(__SPLIT__restore_cp4) || \
- defined(__SPLIT__restore_cp4_nw)
-// void xthal_restore_cp4(void *base)
-DECLFUNC(xthal_restore_cp4)
- abi_entry
- xchal_cp4_load_a2
- abi_return
- endfunc
-#elif defined(__SPLIT__restore_cp5) || \
- defined(__SPLIT__restore_cp5_nw)
-// void xthal_restore_cp5(void *base)
-DECLFUNC(xthal_restore_cp5)
- abi_entry
- xchal_cp5_load_a2
- abi_return
- endfunc
-#elif defined(__SPLIT__restore_cp6) || \
- defined(__SPLIT__restore_cp6_nw)
-// void xthal_restore_cp6(void *base)
-DECLFUNC(xthal_restore_cp6)
- abi_entry
- xchal_cp6_load_a2
- abi_return
- endfunc
-#elif defined(__SPLIT__restore_cp7) || \
- defined(__SPLIT__restore_cp7_nw)
-// void xthal_restore_cp7(void *base)
-DECLFUNC(xthal_restore_cp7)
- abi_entry
- xchal_cp7_load_a2
- abi_return
- endfunc
-
-#elif defined(__SPLIT__cpregs_save_fn)
- .section .rodata, "a"
-_SYM(Xthal_cpregs_save_fn)
-# ifdef __XTENSA_CALL0_ABI__
-_SYM(Xthal_cpregs_save_nw_fn)
-# endif
- .long xthal_save_cp0
- .long xthal_save_cp1
- .long xthal_save_cp2
- .long xthal_save_cp3
- .long xthal_save_cp4
- .long xthal_save_cp5
- .long xthal_save_cp6
- .long xthal_save_cp7
- endfunc
- .text
-
-#elif defined(__SPLIT__cpregs_save_nw_fn)
-# ifndef __XTENSA_CALL0_ABI__
- .section .rodata, "a"
-_SYM(Xthal_cpregs_save_nw_fn)
- .long xthal_save_cp0_nw
- .long xthal_save_cp1_nw
- .long xthal_save_cp2_nw
- .long xthal_save_cp3_nw
- .long xthal_save_cp4_nw
- .long xthal_save_cp5_nw
- .long xthal_save_cp6_nw
- .long xthal_save_cp7_nw
- endfunc
- .text
-# endif
-
-#elif defined(__SPLIT__cpregs_restore_fn)
- .section .rodata, "a"
-_SYM(Xthal_cpregs_restore_fn)
-# ifdef __XTENSA_CALL0_ABI__
-_SYM(Xthal_cpregs_restore_nw_fn)
-# endif
- .long xthal_restore_cp0
- .long xthal_restore_cp1
- .long xthal_restore_cp2
- .long xthal_restore_cp3
- .long xthal_restore_cp4
- .long xthal_restore_cp5
- .long xthal_restore_cp6
- .long xthal_restore_cp7
- endfunc
- .text
-
-#elif defined(__SPLIT__cpregs_restore_nw_fn)
-# ifndef __XTENSA_CALL0_ABI__
- .section .rodata, "a"
-_SYM(Xthal_cpregs_restore_nw_fn)
- .long xthal_restore_cp0_nw
- .long xthal_restore_cp1_nw
- .long xthal_restore_cp2_nw
- .long xthal_restore_cp3_nw
- .long xthal_restore_cp4_nw
- .long xthal_restore_cp5_nw
- .long xthal_restore_cp6_nw
- .long xthal_restore_cp7_nw
- endfunc
- .text
-# endif
-
-
-//----------------------------------------------------------------------
-// coprocessor enable/disable
-//----------------------------------------------------------------------
-
-#elif defined(__SPLIT__validate_cp) ||\
- defined(__SPLIT__validate_cp_nw)
-
-// validate the register file.
-// void xthal_validate_cp(int)
-
-DECLFUNC(xthal_validate_cp)
- abi_entry
-#if XCHAL_HAVE_CP
- rsr.cpenable a3
- movi a4, 1
- ssl a2
- sll a4, a4
- or a3, a3, a4
- wsr.cpenable a3
-#endif
- abi_return
- endfunc
-
-#elif defined(__SPLIT__invalidate_cp) || \
- defined(__SPLIT__invalidate_cp_nw)
-
-// invalidate the register file.
-// void xthal_invalidate_cp(int)
-
-DECLFUNC(xthal_invalidate_cp)
- abi_entry
-#if XCHAL_HAVE_CP
- rsr.cpenable a3
- movi a4, 1
- ssl a2
- sll a4, a4
- and a4, a3, a4
- xor a3, a3, a4
- wsr.cpenable a3
-#endif
- abi_return
- endfunc
-
-
-//----------------------------------------------------------------------
-// Access the CPENABLE register
-//----------------------------------------------------------------------
-
-#elif defined(__SPLIT__get_cpenable) || \
- defined(__SPLIT__get_cpenable_nw)
-
-// unsigned xthal_get_cpenable(void);
-
-DECLFUNC(xthal_get_cpenable)
- abi_entry
-#if XCHAL_HAVE_CP
- rsr.cpenable a2
-#else
- movi a2, 0 // if no CPENABLE (no coprocessors), none is ever enabled
-#endif
- abi_return
- endfunc
-
-#elif defined(__SPLIT__set_cpenable) ||\
- defined(__SPLIT__set_cpenable_nw)
-
-// void xthal_set_cpenable(unsigned);
-//
-// Note: to help asm code performance (eg. OS task switch),
-// this routine returns the previous value of CPENABLE in a3
-// (not a2, because that could require an extra mov instruction).
-// This return value is not shown in the prototype, because
-// C code won't see it.
-// [Perhaps this should go in an RTOS-specific Core HAL or BSP. TBD.]
-
-DECLFUNC(xthal_set_cpenable)
- abi_entry
-#if XCHAL_HAVE_CP
- //rsr.cpenable a3 // return previous CPENABLE
- movi a3, 0 // for now, always return 0 (VxWorks currently done that way)
-
- wsr.cpenable a2
-#else
- movi a3, 0 // if no CPENABLE (no coprocessors), none is ever enabled
-#endif
- abi_return
- endfunc
-#endif
-
-
-/* Nothing implemented below this point. */
-/************************************************************************/
-
-#if 0
-
-//----------------------------------------------------------------------
-// initialize the processor state
-//----------------------------------------------------------------------
-
-// void xthal_init_extra_nw()
- .global xthal_init_extra_nw
- .align 4
-xthal_init_extra_nw:
- //addi sp, sp, 0
- ... NOT IMPLEMENTED ...
- ret
-
-//----------------------------------------------------------------------
-// initialize the TIE coprocessor
-//----------------------------------------------------------------------
-
-// void xthal_init_cp_nw(int)
- .global xthal_init_cp_nw
- .align 4
-xthal_init_cp_nw:
- //addi sp, sp, 0
- ... NOT IMPLEMENTED ...
- ret
-
-//----------------------------------------------------------------------
-//
-//----------------------------------------------------------------------
-
-// initialize the extra processor
-// void xthal_init_mem_extra_nw()
- .global xthal_init_mem_extra_nw
- .align 4
-xthal_init_mem_extra_nw:
- //addi sp, sp, 0
- ... NOT IMPLEMENTED ...
- ret
-
-//----------------------------------------------------------------------
-//
-//----------------------------------------------------------------------
-
-// initialize the TIE coprocessor
-// void xthal_init_mem_cp_nw(int)
- .global xthal_init_mem_cp_nw
- .align 4
-xthal_init_mem_cp_nw:
- //addi sp, sp, 0
- ... NOT IMPLEMENTED ...
- ret
-
-#endif /*0*/
-
diff --git a/src/arch/xtensa/smp/hal/syscache_asm.S b/src/arch/xtensa/smp/hal/syscache_asm.S
deleted file mode 100644
index 0716ddc..0000000
--- a/src/arch/xtensa/smp/hal/syscache_asm.S
+++ /dev/null
@@ -1,141 +0,0 @@
-//
-// syscache_asm.S - system-dependent assembly language cache management routines
-//
-// These functions are now obsolete. They cannot be properly implemented
-// in the HAL, because the required settings of CACHEATTR are entirely
-// system- or board-dependent. The HAL is not board specific; it is merely
-// processor-configuration specific. These cache enable and disable
-// functions do a "best-guess" of what values may be appropriate.
-// They should be avoided. (Instead, use xthal_set_[id]cacheattr()
-// and provide specific CACHEATTR values for the board or system.
-// See the LSP ref manual for info on how to obtain such a value as
-// computed by xt-genldscripts for a specific LSP, e.g. by using the
-// address of the _memmap_cacheattr_reset symbol.)
-//
-// $Id: //depot/rel/Foxhill/dot.8/Xtensa/OS/hal/syscache_asm.S#1 $
-
-// Copyright (c) 2003-2013 Tensilica Inc.
-//
-// Permission is hereby granted, free of charge, to any person obtaining
-// a copy of this software and associated documentation files (the
-// "Software"), to deal in the Software without restriction, including
-// without limitation the rights to use, copy, modify, merge, publish,
-// distribute, sublicense, and/or sell copies of the Software, and to
-// permit persons to whom the Software is furnished to do so, subject to
-// the following conditions:
-//
-// The above copyright notice and this permission notice shall be included
-// in all copies or substantial portions of the Software.
-//
-// THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
-// EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
-// MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
-// IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY
-// CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
-// TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
-// SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
-
-#ifdef INCLUDE_DEPRECATED_HAL_CACHE_CODE
-
-#include <xtensa/cacheasm.h>
-#include <xtensa/cacheattrasm.h>
-#include <xtensa/config/system.h>
-
-/*** Modify this for your particular board or system: ***/
-#define CACHEATTR_DEFAULT XSHAL_ISS_CACHEATTR_DEFAULT
-#define CACHEATTR_BYPASS XSHAL_ISS_CACHEATTR_BYPASS
-
-//----------------------------------------------------------------------
-// Enable and disable the caches
-//----------------------------------------------------------------------
-
- .text
-
- .global xthal_icache_enable
- .global xthal_dcache_enable
- .global xthal_icache_enable_nw
- .global xthal_dcache_enable_nw
-
- .global xthal_icache_disable
- .global xthal_dcache_disable
- .global xthal_icache_disable_nw
- .global xthal_dcache_disable_nw
-
- /*
- * Since we can't enable/disable the icache and dcache independently,
- * and don't have a nice place to store a state which would enable
- * us to only enable them both when both have been requested to be
- * enabled, we simply enable both for any request to enable either,
- * and disable both for any request to disable either cache.
- */
-
- .align 4
-xthal_icache_enable:
- abi_entry
- movi a3, xthal_set_icacheattr
- movi a6, CACHEATTR_DEFAULT // get cache-enabled attributes
- callx4 a3 // enable i-cache
- mov a2, a6 // (in case future version has a return value)
- abi_return
- .size xthal_icache_enable, . - xthal_icache_enable
-
- .align 4
-xthal_dcache_enable:
- abi_entry
- movi a3, xthal_set_dcacheattr
- movi a6, CACHEATTR_DEFAULT // get cache-enabled attributes
- callx4 a3 // enable d-cache
- mov a2, a6 // (in case future version has a return value)
- abi_return
- .size xthal_dcache_enable, . - xthal_dcache_enable
-
- .align 4
-xthal_icache_disable:
- abi_entry
- movi a3, xthal_set_icacheattr
- movi a6, CACHEATTR_BYPASS // get cache-disabled attributes
- callx4 a3 // disable i-cache
- mov a2, a6 // (in case future version has a return value)
- abi_return
- .size xthal_icache_disable, . - xthal_icache_disable
-
- .align 4
-xthal_dcache_disable:
- abi_entry
- movi a3, xthal_set_dcacheattr
- movi a6, CACHEATTR_BYPASS // get cache-disabled attributes
- callx4 a3 // disable d-cache
- mov a2, a6 // (in case future version has a return value)
- abi_return
- .size xthal_dcache_disable, . - xthal_dcache_disable
-
- .align 4
-xthal_icache_enable_nw:
- movi a3, xthal_set_icacheattr_nw
- movi a2, CACHEATTR_DEFAULT // get cache-enabled attributes
- jx a3 // enable i-cache
- .size xthal_icache_enable_nw, . - xthal_icache_enable_nw
-
- .align 4
-xthal_dcache_enable_nw:
- movi a3, xthal_set_dcacheattr_nw
- movi a2, CACHEATTR_DEFAULT // get cache-enabled attributes
- jx a3 // enable d-cache
- .size xthal_dcache_enable_nw, . - xthal_dcache_enable_nw
-
- .align 4
-xthal_icache_disable_nw:
- movi a3, xthal_set_icacheattr_nw
- movi a2, CACHEATTR_BYPASS // get cache-disabled attributes
- jx a3 // disable i-cache
- .size xthal_icache_disable_nw, . - xthal_icache_disable_nw
-
- .align 4
-xthal_dcache_disable_nw:
- movi a3, xthal_set_dcacheattr_nw
- movi a2, CACHEATTR_BYPASS // get cache-disabled attributes
- jx a3 // disable d-cache
- .size xthal_dcache_disable_nw, . - xthal_dcache_disable_nw
-
-#endif /* INCLUDE_DEPRECATED_HAL_CACHE_CODE */
-
diff --git a/src/arch/xtensa/smp/hal/windowspill_asm.S b/src/arch/xtensa/smp/hal/windowspill_asm.S
deleted file mode 100644
index 4568a41..0000000
--- a/src/arch/xtensa/smp/hal/windowspill_asm.S
+++ /dev/null
@@ -1,386 +0,0 @@
-//
-// windowspill.S -- register window spill routine
-//
-// $Id: //depot/rel/Foxhill/dot.8/Xtensa/OS/hal/windowspill_asm.S#1 $
-
-// Copyright (c) 1999-2010 Tensilica Inc.
-//
-// Permission is hereby granted, free of charge, to any person obtaining
-// a copy of this software and associated documentation files (the
-// "Software"), to deal in the Software without restriction, including
-// without limitation the rights to use, copy, modify, merge, publish,
-// distribute, sublicense, and/or sell copies of the Software, and to
-// permit persons to whom the Software is furnished to do so, subject to
-// the following conditions:
-//
-// The above copyright notice and this permission notice shall be included
-// in all copies or substantial portions of the Software.
-//
-// THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
-// EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
-// MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
-// IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY
-// CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
-// TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
-// SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
-
-#include <xtensa/coreasm.h>
-
-
-// xthal_window_spill_nw
-//
-// Spill live register windows to the stack.
-//
-// Required entry conditions:
-// PS.WOE = 0
-// PS.INTLEVEL >= XCHAL_EXCM_LEVEL
-// a1 = valid stack pointer (note: some regs may be spilled at a1-16)
-// a0 = return PC (usually set by call0 or callx0 when calling this function)
-// a2,a3 undefined
-// a4 thru a15 valid, if they are part of window(s) to be spilled
-// (Current window a0..a15 saved if necessary.)
-// WINDOWSTART[WINDOWBASE] = 1
-//
-// Exit conditions:
-// PS.WOE, PS.INTLEVEL = same as on entry
-// WINDOWBASE = same as on entry
-// WINDOWSTART updated to reflect spilled windows
-// (equals 1<<WINDOWBASE if successful return)
-// a0 = return PC
-// a1 = same as on entry
-// a2 = error code:
-// 0 --> successful
-// (WINDOWSTART = 1<<WINDOWBASE)
-// 1 --> invalid WINDOWSTART (WINDOWBASE bit not set)
-// (WINDOWSTART unchanged)
-// 2 --> invalid window size (not 4, 8 or 12 regs)
-// (WINDOWSTART bits of successfully spilled
-// windows are cleared, others left intact)
-// a3 clobbered
-// a4,a5,a8,a9,a12,a13 = same as on entry
-// a6,a7,a10,a11,a14,a15 clobbered if they were part of window(s)
-// to be spilled, otherwise they are the same as on entry
-// loop registers (LCOUNT,LBEG,LEND) are NOT affected (they were in earlier versions)
-// SAR clobbered
-//
-// All non-spilled register windows will be spilled.
-// Beware that this may include a4..a15 of the current window,
-// so generally these should not have been clobbered by the
-// caller if it is at all possible that these registers
-// are part of an unspilled window (it often is possible)
-// (otherwise the spilled stack would be invalid).
-//
-// THIS MEANS: the caller is responsible for saving a0-a15 but
-// the caller must leave a4-a15 intact when control is transferred
-// here.
-//
-// It may be reentrant (but stack pointer is invalid during
-// execution due to window rotations, so can't take interrupts
-// and exceptions in the usual manner, so ... what does
-// reentrancy really mean here?).
-
-
- // The xthal_spill_registers_into_stack_nw entry point
- // is kept here only for backwards compatibility.
- // It will be removed in the very near future.
- .global xthal_spill_registers_into_stack_nw
-
- .text
- .align 4
- .global xthal_window_spill_nw
-xthal_window_spill_nw:
-xthal_spill_registers_into_stack_nw: // BACKWARD COMPATIBILITY ONLY - see above
-
-#if ! XCHAL_HAVE_WINDOWED
- // Nothing to do -- window option was not selected.
- movi a2, 0 // always report success
- ret
-#else /* XCHAL_HAVE_WINDOWED */
-#define WSBITS (XCHAL_NUM_AREGS / 4) /* width of WINDOWSTART register in bits */
-#define WBBITS (XCHAL_NUM_AREGS_LOG2 - 2) /* width of WINDOWBASE register in bits */
- /*
- * Rearrange (rotate) window start bits relative to the current
- * window (WINDOWBASE). WINDOWSTART currently looks like this:
- *
- * a15-a0
- * NAREG-1 | | 0
- * | vvvv |
- * xxxxxxxxxx1yyyyy
- * ^
- * |
- * WINDOWBASE
- *
- * The start bit pointed to by WINDOWBASE must be set
- * (we return an error if it isn't), as it corresponds
- * to the start of the current window (shown as a0-a15).
- *
- * We want the window start bits rotated to look like this:
- * 1yyyyyxxxxxxxxxx
- *
- * Note that there is one start bit for every four registers;
- * and the total number of registers (NAREG) can be 32 or 64;
- * so the number of start bits in WINDOWSTART is NAREG/4,
- * and the size of WINDOWSTART can be 8 or 16.
- */
-
- rsr.windowbase a2
- addi a2, a2, 1
- ssr a2 // sar = WINDOWBASE + 1
- rsr.windowstart a3
- srl a2, a3 // a2 is 0... | 000000xxxxxxxxxx = WINDOWSTART >> sar
- sll a3, a3 // a3 is 1yyyyy0000000000 | 0... = WINDOWSTART << (32 - sar)
- bgez a3, .Linvalid_ws // verify that msbit is indeed set
-
- srli a3, a3, 32-WSBITS // a3 is 0... | 1yyyyy0000000000 = a3 >> (32-NAREG/4)
- or a2, a2, a3 // a2 is 0... | 1yyyyyxxxxxxxxxx
-
- /*
- * FIND THE FIRST ONE
- *
- * Now we have (in a2) the window start bits rotated in order
- * from oldest (closest to lsbit) to current (msbit set).
- * Each start bit (that is set), other than the current one,
- * corresponds to a window frame to spill.
- *
- * Now find the first start bit, ie. the first frame to spill,
- * by looking for the first bit set in a2 (from lsbit side).
- */
-
-#if XCHAL_HAVE_NSA
- neg a3, a2 // keep only the least-significant bit set of a2 ...
- and a3, a3, a2 // ... in a3
- nsau a3, a3 // get index of that bit, numbered from msbit (32 if absent)
- ssl a3 // set sar = 32 - a3 = bit index numbered from lsbit + 1
-#else /* XCHAL_HAVE_NSA */
- wsr.windowstart a2 // temporarily save rotated start bits
- // (we can use WINDOWSTART because WOE=0)
-
- // NOTE: this could be optimized a bit, by explicit coding rather than the macro.
- find_ls_one a3, a2 // set a3 to index of lsmost bit set in a2 (a2 clobbered)
-
- addi a2, a3, 1 // index+1
- ssr a2 // set sar = index + 1
- rsr.windowstart a2 // restore a2 (rotated start bits)
-#endif /* XCHAL_HAVE_NSA */
- srl a2, a2 // right-justify the rotated start bits (dropping lsbit set)
- wsr.windowstart a2 // save rotated + justified window start bits,
- // because a2 will disappear when modifying WINDOWBASE
- // again, we can use WINDOWSTART because WOE=0
-
- /*
- * Rotate WindowBase so that a0 of the next window to spill is in a4
- * (ie. leaving us with a2 and a3 to play with, because a0 and a1
- * may be those of the original window which we must preserve).
- */
- rsr.windowbase a2
-#if XCHAL_HAVE_NSA
- addi a2, a2, 31
- sub a3, a2, a3 // a3 = WINDOWBASE + index = WINDOWBASE + (31 - msbit_index)
-#else /* XCHAL_HAVE_NSA */
- add a3, a2, a3 // a3 = WINDOWBASE + index
-#endif /* XCHAL_HAVE_NSA */
- wsr.windowbase a3 // effectively do: rotw index
- rsync // wait for write to WINDOWBASE to complete
- // Now our registers have changed!
-
- rsr.windowstart a2 // restore a2 (rotated + justified window start bits)
-
- /*
- * We are now ready to start the window spill loop.
- * Relative to the above, a2 and WINDOWBASE are now as follows:
- *
- * 1yyyyyxxxxxxxxxx = rotated start bits as shown above
- * 1yyyyyxxxx100000 = actual rotated start bits (example)
- * 0000001yyyyyxxxx ^ = a2 = rotated + justified start bits
- * ^ xxx1^ = window being spilled
- * ^ ^
- * | |
- * original current
- * WINDOWBASE WINDOWBASE
- *
- * The first window to spill (save) starts at what is now a4.
- * The spill loop maintains the adjusted start bits in a2,
- * shifting them right as each window is spilled.
- */
-
-.Lspill_loop:
- // Top of save loop.
- // Find the size of this call and branch to the appropriate save routine.
-
- beqz a2, .Ldone // if no start bit remaining, we're done
- bbsi.l a2, 0, .Lspill4 // if next start bit is set, it's a call4
- bbsi.l a2, 1, .Lspill8 // if 2nd next bit set, it's a call8
- bbsi.l a2, 2, .Lspill12 // if 3rd next bit set, it's a call12
- j .Linvalid_window // else it's an invalid window!
-
-
-
- // SAVE A CALL4
-.Lspill4:
- addi a3, a9, -16 // a3 gets call[i+1]'s sp - 16
- s32i a4, a3, 0 // store call[i]'s a0
- s32i a5, a3, 4 // store call[i]'s a1
- s32i a6, a3, 8 // store call[i]'s a2
- s32i a7, a3, 12 // store call[i]'s a3
-
- srli a6, a2, 1 // move and shift the start bits
- rotw 1 // rotate the window
-
- j .Lspill_loop
-
- // SAVE A CALL8
-.Lspill8:
- addi a3, a13, -16 // a0 gets call[i+1]'s sp - 16
- s32i a4, a3, 0 // store call[i]'s a0
- s32i a5, a3, 4 // store call[i]'s a1
- s32i a6, a3, 8 // store call[i]'s a2
- s32i a7, a3, 12 // store call[i]'s a3
-
- addi a3, a5, -12 // call[i-1]'s sp address
- l32i a3, a3, 0 // a3 is call[i-1]'s sp
- // (load slot)
- addi a3, a3, -32 // a3 points to our spill area
-
- s32i a8, a3, 0 // store call[i]'s a4
- s32i a9, a3, 4 // store call[i]'s a5
- s32i a10, a3, 8 // store call[i]'s a6
- s32i a11, a3, 12 // store call[i]'s a7
-
- srli a10, a2, 2 // move and shift the start bits
- rotw 2 // rotate the window
-
- j .Lspill_loop
-
- // SAVE A CALL12
-.Lspill12:
- rotw 1 // rotate to see call[i+1]'s sp
-
- addi a13, a13, -16 // set to the reg save area
- s32i a0, a13, 0 // store call[i]'s a0
- s32i a1, a13, 4 // store call[i]'s a1
- s32i a2, a13, 8 // store call[i]'s a2
- s32i a3, a13, 12 // store call[i]'s a3
-
- addi a3, a1, -12 // call[i-1]'s sp address
- l32i a3, a3, 0 // a3 has call[i-1]'s sp
- addi a13, a13, 16 // restore call[i+1]'s sp (here to fill load slot)
- addi a3, a3, -48 // a3 points to our save area
-
- s32i a4, a3, 0 // store call[i]'s a4
- s32i a5, a3, 4 // store call[i]'s a5
- s32i a6, a3, 8 // store call[i]'s a6
- s32i a7, a3, 12 // store call[i]'s a7
- s32i a8, a3, 16 // store call[i]'s a4
- s32i a9, a3, 20 // store call[i]'s a5
- s32i a10, a3, 24 // store call[i]'s a6
- s32i a11, a3, 28 // store call[i]'s a7
-
- rotw -1 // rotate to see start bits (a2)
- srli a14, a2, 3 // move and shift the start bits
- rotw 3 // rotate to next window
-
- j .Lspill_loop
-
-
-
-.Ldone:
- rotw 1 // back to the original window
- rsr.windowbase a2 // get (original) window base
- ssl a2 // setup for shift left by WINDOWBASE
- movi a2, 1
- sll a2, a2 // compute new WINDOWSTART = 1<<WINDOWBASE
- wsr.windowstart a2 // and apply it
- rsync
- movi a2, 0 // done!
- ret
- //jx a0
-
-
- // Invalid WINDOWSTART register.
- //
-.Linvalid_ws:
- movi a2, 1 // indicate invalid WINDOWSTART
- ret // return from subroutine
-
-
- // Invalid window size!
- // The three bits following the start bit are all clear, so
- // we have an invalid window state (can't determine a window size).
- //
- // So we exit with an error, but to do that we must first restore
- // the original WINDOWBASE. We also compute a sensible
- // WINDOWSTART that has the start bits of spilled windows
- // cleared, but all other start bits intact, so someone debugging
- // the failure can look at WINDOWSTART to see which window
- // failed to spill.
- //
-.Linvalid_window:
- slli a2, a2, 1 // space for missing start bit
- addi a2, a2, 1 // add missing start bit
- rsr.windowbase a3 // get current WINDOWBASE
- bbsi.l a2, WSBITS-1, 2f // branch if current WINDOWBASE==original
-1: addi a3, a3, -1 // decrement towards original WINDOWBASE
- slli a2, a2, 1 // shift towards original WINDOWSTART alignment
- bbci.l a2, WSBITS-1, 1b // repeat until ms start bit set
- extui a3, a3, 0, WBBITS // mask out upper base bits, in case of carry-over
-2: // Here, a3 = original WINDOWBASE;
- // and msbit of start bits in a2 is set, and no other bits above it.
- // Now rotate a2 to become the correct WINDOWSTART.
- ssl a3 // set shift left ... (sar = 32 - orig WB)
- slli a3, a2, 32-WSBITS // left-justify start bits
- src a2, a2, a3 // rotate left by original WINDOWBASE
- extui a2, a2, 0, WSBITS // keep only significant start bits
- wsr.windowstart a2 // we've cleared only start bits of spilled windows
- rsr.sar a3 // retrieve 32 - original WINDOWBASE
- movi a2, 32
- sub a3, a2, a3 // restore original WINDOWBASE
- wsr.windowbase a3 // back to original WINDOWBASE
- rsync
-
- movi a2, 2 // indicate invalid window size
- ret
-
-#endif /* XCHAL_HAVE_WINDOWED */
-
- .size xthal_window_spill_nw, . - xthal_window_spill_nw
-
-
-// void xthal_window_spill (void);
-//
-// Spill live register windows to the stack.
-//
-// This will spill all register windows except this
-// function's window, and possibly that of its caller.
-// (Currently, the caller's window is spilled and reloaded
-// when this function returns. This may change with
-// future optimisations.)
-//
-// Another, simpler way to implement this might be
-// to use an appropriate sequence of call/entry/retw
-// instructions to force overflow of any live windows.
-//
-// Assumes that PS.INTLEVEL=0 and PS.WOE=1 on entry/exit.
-//
- .text
- .align 4
- .global xthal_window_spill
- .type xthal_window_spill,@function
-xthal_window_spill:
- abi_entry
-#if XCHAL_HAVE_WINDOWED
- movi a6, ~(PS_WOE_MASK|PS_INTLEVEL_MASK) // (using a6 ensures any window using this a4..a7 is spilled)
- rsr.ps a5
- mov a4, a0 // save a0
- and a2, a5, a6 // clear WOE, INTLEVEL
- addi a2, a2, XCHAL_EXCM_LEVEL // set INTLEVEL = XCHAL_EXCM_LEVEL
- wsr.ps a2 // apply to PS
- rsync
- call0 xthal_window_spill_nw
- mov a0, a4 // restore a0
- wsr.ps a5 // restore PS
- rsync
-#endif /* XCHAL_HAVE_WINDOWED */
- abi_return
-
- .size xthal_window_spill, . - xthal_window_spill
-
diff --git a/src/arch/xtensa/smp/include/Makefile.am b/src/arch/xtensa/smp/include/Makefile.am
deleted file mode 100644
index f0ac9b7..0000000
--- a/src/arch/xtensa/smp/include/Makefile.am
+++ /dev/null
@@ -1 +0,0 @@
-SUBDIRS = arch
diff --git a/src/arch/xtensa/smp/include/arch/Makefile.am b/src/arch/xtensa/smp/include/arch/Makefile.am
deleted file mode 100644
index 7a4a5e1..0000000
--- a/src/arch/xtensa/smp/include/arch/Makefile.am
+++ /dev/null
@@ -1,3 +0,0 @@
-noinst_HEADERS = \
- alloc.h \
- idc.h
diff --git a/src/arch/xtensa/smp/include/arch/alloc.h b/src/arch/xtensa/smp/include/arch/alloc.h
deleted file mode 100644
index 65cb9b0..0000000
--- a/src/arch/xtensa/smp/include/arch/alloc.h
+++ /dev/null
@@ -1,88 +0,0 @@
-/*
- * Copyright (c) 2018, Intel Corporation
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- * * Redistributions of source code must retain the above copyright
- * notice, this list of conditions and the following disclaimer.
- * * Redistributions in binary form must reproduce the above copyright
- * notice, this list of conditions and the following disclaimer in the
- * documentation and/or other materials provided with the distribution.
- * * Neither the name of the Intel Corporation nor the
- * names of its contributors may be used to endorse or promote products
- * derived from this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
- * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
- * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
- * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
- * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
- * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
- * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
- * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
- * POSSIBILITY OF SUCH DAMAGE.
- *
- * Author: Tomasz Lauda <tomasz.lauda@linux.intel.com>
- */
-
-/**
- * \file arch/xtensa/smp/include/arch/alloc.h
- * \brief Xtensa SMP memory allocation header file
- * \authors Tomasz Lauda <tomasz.lauda@linux.intel.com>
- */
-
-#ifndef __ARCH_ALLOC_H__
-#define __ARCH_ALLOC_H__
-
-#include <xtos-structs.h>
-#include <sof/alloc.h>
-
-extern struct core_context *core_ctx_ptr[PLATFORM_CORE_COUNT];
-extern struct xtos_core_data *core_data_ptr[PLATFORM_CORE_COUNT];
-
-/**
- * \brief Allocates memory for core specific data.
- * \param[in] core Slave core for which data needs to be allocated.
- */
-static inline void alloc_core_context(int core)
-{
- struct core_context *core_ctx;
-
- core_ctx = rzalloc(RZONE_RUNTIME, SOF_MEM_CAPS_RAM, sizeof(*core_ctx));
- dcache_writeback_invalidate_region(core_ctx, sizeof(*core_ctx));
-
- /* xtos_core_data is a big struct, so allocate it from system heap
- * and never free again. Allocating from runtime heap would be
- * a waste of a very big memory block.
- */
- if (!core_data_ptr[core])
- core_data_ptr[core] = rzalloc(RZONE_SYS, SOF_MEM_CAPS_RAM,
- sizeof(*core_data_ptr[core]));
-
- core_data_ptr[core]->thread_data_ptr = &core_ctx->td;
- dcache_writeback_invalidate_region(core_data_ptr[core],
- sizeof(*core_data_ptr[core]));
-
- dcache_writeback_invalidate_region(core_data_ptr,
- sizeof(core_data_ptr));
-
- core_ctx_ptr[core] = core_ctx;
- dcache_writeback_invalidate_region(core_ctx_ptr,
- sizeof(core_ctx_ptr));
-}
-
-/**
- * \brief Frees memory allocated for core specific data.
- * \param[in] core Slave core for which data needs to be freed.
- */
-static inline void free_core_context(int core)
-{
- rfree(core_ctx_ptr[core]);
- dcache_writeback_invalidate_region(core_ctx_ptr[core],
- sizeof(*core_ctx_ptr[core]));
-}
-
-#endif
diff --git a/src/arch/xtensa/smp/include/arch/idc.h b/src/arch/xtensa/smp/include/arch/idc.h
deleted file mode 100644
index ad24007..0000000
--- a/src/arch/xtensa/smp/include/arch/idc.h
+++ /dev/null
@@ -1,359 +0,0 @@
-/*
- * Copyright (c) 2018, Intel Corporation
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- * * Redistributions of source code must retain the above copyright
- * notice, this list of conditions and the following disclaimer.
- * * Redistributions in binary form must reproduce the above copyright
- * notice, this list of conditions and the following disclaimer in the
- * documentation and/or other materials provided with the distribution.
- * * Neither the name of the Intel Corporation nor the
- * names of its contributors may be used to endorse or promote products
- * derived from this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
- * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
- * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
- * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
- * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
- * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
- * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
- * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
- * POSSIBILITY OF SUCH DAMAGE.
- *
- * Author: Tomasz Lauda <tomasz.lauda@linux.intel.com>
- */
-
-/**
- * \file arch/xtensa/smp/include/arch/idc.h
- * \brief Xtensa SMP architecture IDC header file
- * \authors Tomasz Lauda <tomasz.lauda@linux.intel.com>
- */
-
-#ifndef __ARCH_IDC_H__
-#define __ARCH_IDC_H__
-
-#include <xtos-structs.h>
-#include <arch/cpu.h>
-#include <platform/interrupt.h>
-#include <platform/platform.h>
-#include <sof/alloc.h>
-#include <sof/lock.h>
-#include <sof/trace.h>
-
-/** \brief IDC trace function. */
-#define trace_idc(__e) trace_event(TRACE_CLASS_IDC, __e)
-
-/** \brief IDC trace value function. */
-#define tracev_idc(__e) tracev_event(TRACE_CLASS_IDC, __e)
-
-/** \brief IDC trace error function. */
-#define trace_idc_error(__e) trace_error(TRACE_CLASS_IDC, __e)
-
-
-/** \brief IDC send blocking flag. */
-#define IDC_BLOCKING 0
-
-/** \brief IDC send non-blocking flag. */
-#define IDC_NON_BLOCKING 1
-
-/** \brief IDC send timeout in cycles. */
-#define IDC_TIMEOUT 800000
-
-/** \brief ROM wake version parsed by ROM during core wake up. */
-#define IDC_ROM_WAKE_VERSION 0x2
-
-/** \brief ROM control version parsed by ROM during core wake up. */
-#define IDC_ROM_CONTROL_VERSION 0x1
-
-// TODO: refactor below defines after universal IDC message template
-// will be defined and ready
-
-/** \brief Power up message header. */
-#define IDC_POWER_UP_MESSAGE \
- (IDC_ROM_WAKE_VERSION | (IDC_ROM_CONTROL_VERSION << 24))
-
-/** \brief Power up message extension. */
-#define IDC_POWER_UP_EXTENSION (SOF_TEXT_START >> 2)
-
-/** \brief Power down message header. */
-#define IDC_POWER_DOWN_MESSAGE 0x7FFFFFFF
-
-/** \brief IDC message. */
-struct idc_msg {
- uint32_t header; /**< header value */
- uint32_t extension; /**< extension value */
- uint32_t core; /**< core id */
-};
-
-/** \brief IDC data. */
-struct idc {
- spinlock_t lock; /**< lock mechanism */
- uint32_t busy_bit_mask; /**< busy interrupt mask */
- uint32_t done_bit_mask; /**< done interrupt mask */
- uint32_t msg_pending; /**< is message pending */
- struct idc_msg received_msg; /**< received message */
-};
-
-extern void cpu_power_down_core(void);
-
-/**
- * \brief Returns IDC data.
- * \return Pointer to pointer of IDC data.
- */
-static inline struct idc **idc_get(void)
-{
- struct core_context *ctx = (struct core_context *)cpu_read_threadptr();
-
- return &ctx->idc;
-}
-
-static inline void idc_enable_interrupts(int target_core, int source_core)
-{
- idc_write(IPC_IDCCTL, target_core,
- IPC_IDCCTL_IDCTBIE(source_core));
- platform_interrupt_unmask(PLATFORM_IDC_INTERRUPT(target_core), 0);
-}
-
-/**
- * \brief IDC interrupt handler.
- * \param[in,out] arg Pointer to IDC data.
- */
-static void idc_irq_handler(void *arg)
-{
- struct idc *idc = arg;
- int core = arch_cpu_get_id();
- uint32_t idctfc;
- uint32_t idctefc;
- uint32_t idcietc;
- uint32_t i;
-
- tracev_idc("IRQ");
-
- for (i = 0; i < PLATFORM_CORE_COUNT; i++) {
- idctfc = idc_read(IPC_IDCTFC(i), core);
-
- if (idctfc & IPC_IDCTFC_BUSY) {
- trace_idc("Nms");
-
- /* disable BUSY interrupt */
- idc_write(IPC_IDCCTL, core, idc->done_bit_mask);
-
- idc->received_msg.core = i;
- idc->received_msg.header =
- idctfc & IPC_IDCTFC_MSG_MASK;
-
- idctefc = idc_read(IPC_IDCTEFC(i), core);
- idc->received_msg.extension =
- idctefc & IPC_IDCTEFC_MSG_MASK;
-
- idc->msg_pending = 1;
-
- break;
- }
- }
-
- for (i = 0; i < PLATFORM_CORE_COUNT; i++) {
- idcietc = idc_read(IPC_IDCIETC(i), core);
-
- if (idcietc & IPC_IDCIETC_DONE) {
- tracev_idc("Rpy");
-
- idc_write(IPC_IDCIETC(i), core,
- idcietc | IPC_IDCIETC_DONE);
-
- break;
- }
- }
-}
-
-/**
- * \brief Sends IDC message.
- * \param[in,out] msg Pointer to IDC message.
- * \param[in] mode Is message blocking or not.
- * \return Error code.
- */
-static inline int arch_idc_send_msg(struct idc_msg *msg, uint32_t mode)
-{
- struct idc *idc = *idc_get();
- int core = arch_cpu_get_id();
- int ret = 0;
- uint32_t timeout = 0;
- uint32_t idcietc;
- uint32_t flags;
-
- tracev_idc("Msg");
-
- spin_lock_irq(&idc->lock, flags);
-
- idc_write(IPC_IDCIETC(msg->core), core, msg->extension);
- idc_write(IPC_IDCITC(msg->core), core, msg->header | IPC_IDCITC_BUSY);
-
- if (mode == IDC_BLOCKING) {
- do {
- idelay(PLATFORM_DEFAULT_DELAY);
- timeout += PLATFORM_DEFAULT_DELAY;
- idcietc = idc_read(IPC_IDCIETC(msg->core), core);
- } while (!(idcietc & IPC_IDCIETC_DONE) &&
- timeout < IDC_TIMEOUT);
-
- if (timeout >= IDC_TIMEOUT) {
- trace_idc_error("eS0");
- ret = -ETIME;
- }
- }
-
- spin_unlock_irq(&idc->lock, flags);
-
- return ret;
-}
-
-/**
- * \brief Executes IDC message based on type.
- * \param[in,out] msg Pointer to IDC message.
- * \return Error status.
- */
-static inline int32_t idc_cmd(struct idc_msg *msg)
-{
- /* right now we only handle power down */
- /* TODO: universal implementation */
- if (msg->header == IDC_POWER_DOWN_MESSAGE)
- cpu_power_down_core();
-
- return 0;
-}
-
-/**
- * \brief Handles received IDC message.
- * \param[in,out] idc Pointer to IDC data.
- */
-static inline void idc_do_cmd(struct idc *idc)
-{
- int core = arch_cpu_get_id();
- int initiator = idc->received_msg.core;
-
- trace_idc("Cmd");
-
- idc_cmd(&idc->received_msg);
-
- idc->msg_pending = 0;
-
- /* clear BUSY bit */
- idc_write(IPC_IDCTFC(initiator), core,
- idc_read(IPC_IDCTFC(initiator), core) | IPC_IDCTFC_BUSY);
-
- /* enable BUSY interrupt */
- idc_write(IPC_IDCCTL, core, idc->busy_bit_mask | idc->done_bit_mask);
-}
-
-/**
- * \brief Checks for pending IDC messages.
- */
-static inline void arch_idc_process_msg_queue(void)
-{
- struct idc *idc = *idc_get();
-
- if (idc->msg_pending)
- idc_do_cmd(idc);
-}
-
-/**
- * \brief Returns BUSY interrupt mask based on core id.
- * \param[in] core Core id.
- * \return BUSY interrupt mask.
- */
-static inline uint32_t idc_get_busy_bit_mask(int core)
-{
- uint32_t busy_mask = 0;
- int i;
-
- if (core == PLATFORM_MASTER_CORE_ID) {
- for (i = 0; i < PLATFORM_CORE_COUNT; i++) {
- if (i != PLATFORM_MASTER_CORE_ID)
- busy_mask |= IPC_IDCCTL_IDCTBIE(i);
- }
- } else {
- busy_mask = IPC_IDCCTL_IDCTBIE(PLATFORM_MASTER_CORE_ID);
- }
-
- return busy_mask;
-}
-
-/**
- * \brief Returns DONE interrupt mask based on core id.
- * \param[in] core Core id.
- * \return DONE interrupt mask.
- */
-static inline uint32_t idc_get_done_bit_mask(int core)
-{
- uint32_t done_mask = 0;
- int i;
-
- if (core == PLATFORM_MASTER_CORE_ID) {
- for (i = 0; i < PLATFORM_CORE_COUNT; i++) {
- if (i != PLATFORM_MASTER_CORE_ID)
- done_mask |= IPC_IDCCTL_IDCIDIE(i);
- }
- } else {
- done_mask = 0;
- }
-
- return done_mask;
-}
-
-/**
- * \brief Initializes IDC data and registers for interrupt.
- */
-static inline void arch_idc_init(void)
-{
- int core = arch_cpu_get_id();
-
- trace_idc("IDI");
-
- /* initialize idc data */
- struct idc **idc = idc_get();
- *idc = rzalloc(RZONE_RUNTIME, SOF_MEM_CAPS_RAM, sizeof(**idc));
- spinlock_init(&((*idc)->lock));
- (*idc)->busy_bit_mask = idc_get_busy_bit_mask(core);
- (*idc)->done_bit_mask = idc_get_done_bit_mask(core);
-
- /* configure interrupt */
- interrupt_register(PLATFORM_IDC_INTERRUPT(core),
- idc_irq_handler, *idc);
- interrupt_enable(PLATFORM_IDC_INTERRUPT(core));
-
- /* enable BUSY and DONE (only for master core) interrupts */
- idc_write(IPC_IDCCTL, core,
- (*idc)->busy_bit_mask | (*idc)->done_bit_mask);
-}
-
-/**
- * \brief Frees IDC data and unregisters interrupt.
- */
-static inline void idc_free(void)
-{
- int core = arch_cpu_get_id();
- int i = 0;
- uint32_t idctfc;
-
- trace_idc("IDF");
-
- /* disable and unregister interrupt */
- interrupt_disable(PLATFORM_IDC_INTERRUPT(core));
- interrupt_unregister(PLATFORM_IDC_INTERRUPT(core));
-
- /* clear BUSY bits */
- for (i = 0; i < PLATFORM_CORE_COUNT; i++) {
- idctfc = idc_read(IPC_IDCTFC(i), core);
- if (idctfc & IPC_IDCTFC_BUSY)
- idc_write(IPC_IDCTFC(i), core, idctfc);
- }
-
- rfree(*idc_get());
-}
-
-#endif
diff --git a/src/arch/xtensa/smp/init.c b/src/arch/xtensa/smp/init.c
deleted file mode 100644
index 16389c1..0000000
--- a/src/arch/xtensa/smp/init.c
+++ /dev/null
@@ -1,106 +0,0 @@
-/*
- * Copyright (c) 2016, Intel Corporation
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- * * Redistributions of source code must retain the above copyright
- * notice, this list of conditions and the following disclaimer.
- * * Redistributions in binary form must reproduce the above copyright
- * notice, this list of conditions and the following disclaimer in the
- * documentation and/or other materials provided with the distribution.
- * * Neither the name of the Intel Corporation nor the
- * names of its contributors may be used to endorse or promote products
- * derived from this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
- * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
- * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
- * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
- * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
- * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
- * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
- * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
- * POSSIBILITY OF SUCH DAMAGE.
- *
- * Author: Liam Girdwood <liam.r.girdwood@linux.intel.com>
- */
-
-/**
- * \file arch/xtensa/smp/init.c
- * \brief Xtensa SMP initialization functions
- * \authors Liam Girdwood <liam.r.girdwood@linux.intel.com>
- */
-
-#include <xtos-structs.h>
-#include <platform/memory.h>
-#include <sof/interrupt.h>
-#include <platform/interrupt.h>
-#include <sof/mailbox.h>
-#include <arch/cpu.h>
-#include <arch/init.h>
-#include <arch/task.h>
-#include <sof/init.h>
-#include <sof/lock.h>
-#include <stdint.h>
-
-#if DEBUG_LOCKS
-/** \brief Debug lock. */
-uint32_t lock_dbg_atomic = 0;
-
-/** \brief Debug locks per user. */
-uint32_t lock_dbg_user[DBG_LOCK_USERS] = {0};
-#endif
-
-/** \brief Core context for master core. */
-static struct core_context master_core_ctx;
-
-/** \brief Core context pointers for all the cores. */
-struct core_context *core_ctx_ptr[PLATFORM_CORE_COUNT];
-
-/** \brief Xtos core data for master core. */
-struct xtos_core_data master_core_data;
-
-/** \brief Xtos core data pointers for all the cores. */
-struct xtos_core_data *core_data_ptr[PLATFORM_CORE_COUNT];
-
-/**
- * \brief Initializes core specific data.
- */
-static void initialize_pointers_per_core(void)
-{
- int core = arch_cpu_get_id();
- struct xtos_core_data *core_data = core_data_ptr[core];
-
- if (core == PLATFORM_MASTER_CORE_ID) {
- master_core_data.thread_data_ptr = &master_core_ctx.td;
- core_ctx_ptr[PLATFORM_MASTER_CORE_ID] = &master_core_ctx;
- }
-
- cpu_write_threadptr((int)core_ctx_ptr[core]);
-
- xtos_structures_pointers *p = &core_data->thread_data_ptr->xtos_ptrs;
- p->xtos_enabled = &core_data->xtos_int_data.xtos_enabled;
- p->xtos_intstruct = &core_data->xtos_int_data;
- p->xtos_interrupt_table = &core_data->xtos_int_data.xtos_interrupt_table.array[0];
- p->xtos_interrupt_mask_table = &core_data->xtos_int_data.xtos_interrupt_mask_table[0];
- p->xtos_stack_for_interrupt_2 = core_data->xtos_stack_for_interrupt_2;
- p->xtos_stack_for_interrupt_3 = core_data->xtos_stack_for_interrupt_3;
- p->xtos_stack_for_interrupt_4 = core_data->xtos_stack_for_interrupt_4;
- p->xtos_stack_for_interrupt_5 = core_data->xtos_stack_for_interrupt_5;
-}
-
-/**
- * \brief Initializes architecture.
- * \param[in,out] sof Firmware main context.
- * \return Error status.
- */
-int arch_init(struct sof *sof)
-{
- initialize_pointers_per_core();
- register_exceptions();
- arch_assign_tasks();
- return 0;
-}
diff --git a/src/arch/xtensa/smp/schedule.c b/src/arch/xtensa/smp/schedule.c
deleted file mode 100644
index a759eb7..0000000
--- a/src/arch/xtensa/smp/schedule.c
+++ /dev/null
@@ -1,47 +0,0 @@
-/*
- * Copyright (c) 2018, Intel Corporation
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- * * Redistributions of source code must retain the above copyright
- * notice, this list of conditions and the following disclaimer.
- * * Redistributions in binary form must reproduce the above copyright
- * notice, this list of conditions and the following disclaimer in the
- * documentation and/or other materials provided with the distribution.
- * * Neither the name of the Intel Corporation nor the
- * names of its contributors may be used to endorse or promote products
- * derived from this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
- * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
- * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
- * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
- * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
- * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
- * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
- * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
- * POSSIBILITY OF SUCH DAMAGE.
- *
- * Author: Tomasz Lauda <tomasz.lauda@linux.intel.com>
- *
- */
-
-/**
- * \file arch/xtensa/smp/schedule.c
- * \brief Xtensa SMP schedule implementation file
- * \authors Tomasz Lauda <tomasz.lauda@linux.intel.com>
- */
-
-#include <xtos-structs.h>
-#include <arch/cpu.h>
-#include <sof/schedule.h>
-
-struct schedule_data **arch_schedule_get(void)
-{
- struct core_context *ctx = (struct core_context *)cpu_read_threadptr();
-
- return &ctx->sch;
-}
diff --git a/src/arch/xtensa/smp/task.c b/src/arch/xtensa/smp/task.c
deleted file mode 100644
index 6366fd0..0000000
--- a/src/arch/xtensa/smp/task.c
+++ /dev/null
@@ -1,61 +0,0 @@
-/*
- * Copyright (c) 2017, Intel Corporation
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- * * Redistributions of source code must retain the above copyright
- * notice, this list of conditions and the following disclaimer.
- * * Redistributions in binary form must reproduce the above copyright
- * notice, this list of conditions and the following disclaimer in the
- * documentation and/or other materials provided with the distribution.
- * * Neither the name of the Intel Corporation nor the
- * names of its contributors may be used to endorse or promote products
- * derived from this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
- * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
- * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
- * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
- * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
- * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
- * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
- * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
- * POSSIBILITY OF SUCH DAMAGE.
- *
- * Author: Liam Girdwood <liam.r.girdwood@linux.intel.com>
- *
- */
-
-/**
- * \file arch/xtensa/smp/task.c
- * \brief Xtensa SMP task implementation file
- * \authors Liam Girdwood <liam.r.girdwood@linux.intel.com>
- */
-
-#include <xtos-structs.h>
-#include <arch/cpu.h>
-#include <arch/task.h>
-
-struct irq_task **task_irq_low_get(void)
-{
- struct core_context *ctx = (struct core_context *)cpu_read_threadptr();
-
- return &ctx->irq_low_task;
-}
-
-struct irq_task **task_irq_med_get(void)
-{
- struct core_context *ctx = (struct core_context *)cpu_read_threadptr();
-
- return &ctx->irq_med_task;
-}
-
-struct irq_task **task_irq_high_get(void)
-{
- struct core_context *ctx = (struct core_context *)cpu_read_threadptr();
-
- return &ctx->irq_high_task;
-}
diff --git a/src/arch/xtensa/smp/xtos/Makefile.am b/src/arch/xtensa/smp/xtos/Makefile.am
deleted file mode 100644
index 95f385b..0000000
--- a/src/arch/xtensa/smp/xtos/Makefile.am
+++ /dev/null
@@ -1,158 +0,0 @@
-noinst_HEADERS = \
- xtos-internal.h \
- xtos-params.h \
- xtos-structs.h \
- interrupt-pri.h \
- int-highpri-dispatcher.S \
- int-medpri-dispatcher.S
-
-noinst_LIBRARIES = \
- libxtos.a \
- libxlevel2.a \
- libxlevel3.a \
- libxlevel4.a \
- libxlevel5.a
-
-VECTOR_DEFS = \
- -D__SPLIT__vector \
- -D__SPLIT__handler \
- -D__SPLIT__user \
- -D__SPLIT__level1int \
- -D__SPLIT__level2 \
- -D__SPLIT__level3 \
- -D__SPLIT__level4 \
- -D__SPLIT__level5
-
-
-if BUILD_BAYTRAIL
-PLATFORM_DEFS = $(VECTOR_DEFS)
-endif
-
-if BUILD_CHERRYTRAIL
-PLATFORM_DEFS = $(VECTOR_DEFS)
-endif
-
-if BUILD_APOLLOLAKE
-PLATFORM_DEFS = $(VECTOR_DEFS)
-noinst_LIBRARIES += libxlevel6.a
-VECTOR_DEFS += -D__SPLIT__level6
-endif
-
-if BUILD_BROADWELL
-PLATFORM_DEFS = $(VECTOR_DEFS)
-endif
-
-if BUILD_HASWELL
-PLATFORM_DEFS = $(VECTOR_DEFS)
-endif
-
-if BUILD_CANNONLAKE
-PLATFORM_DEFS = $(VECTOR_DEFS)
-noinst_LIBRARIES += libxlevel6.a
-VECTOR_DEFS += -D__SPLIT__level6
-endif
-
-LEVEL_SRC = \
- int-handler.S \
- int-vector.S \
- int-initlevel.S
-
-libxlevel2_a_SOURCES = \
- $(LEVEL_SRC)
-
-libxlevel2_a_CCASFLAGS = \
- $(ARCH_INCDIR) \
- $(ARCH_ASFLAGS) \
- $(PLATFORM_INCDIR) \
- $(PLATFORM_DEFS) \
- -D_INTERRUPT_LEVEL=2
-
-libxlevel3_a_SOURCES = \
- $(LEVEL_SRC)
-
-libxlevel3_a_CCASFLAGS = \
- $(ARCH_INCDIR) \
- $(ARCH_ASFLAGS) \
- $(PLATFORM_INCDIR) \
- $(PLATFORM_DEFS) \
- -D_INTERRUPT_LEVEL=3
-
-libxlevel4_a_SOURCES = \
- $(LEVEL_SRC)
-
-libxlevel4_a_CCASFLAGS = \
- $(ARCH_INCDIR) \
- $(ARCH_ASFLAGS) \
- $(PLATFORM_INCDIR) \
- $(PLATFORM_DEFS) \
- -D_INTERRUPT_LEVEL=4
-
-libxlevel5_a_SOURCES = \
- $(LEVEL_SRC)
-
-libxlevel5_a_CCASFLAGS = \
- $(ARCH_INCDIR) \
- $(ARCH_ASFLAGS) \
- $(PLATFORM_INCDIR) \
- $(PLATFORM_DEFS) \
- -D_INTERRUPT_LEVEL=5
-
-if BUILD_APOLLOLAKE
-libxlevel6_a_SOURCES = \
- $(LEVEL_SRC)
-
-libxlevel6_a_CCASFLAGS = \
- $(ARCH_INCDIR) \
- $(ARCH_ASFLAGS) \
- $(PLATFORM_INCDIR) \
- $(PLATFORM_DEFS) \
- -D_INTERRUPT_LEVEL=6
-endif
-
-libxtos_a_SOURCES = \
- core-restore.S \
- core-save.S \
- core-shutoff.S \
- double-vector.S \
- xea1/exc-alloca-handler.S \
- xea1/exc-c-wrapper-handler.S \
- xea2/exc-c-wrapper-handler.S \
- xea1/exc-return.S \
- xea2/exc-return.S \
- exc-sethandler.c \
- exc-syscall-handler.S \
- exc-table.S \
- exc-unhandled.S \
- interrupt-table.S \
- int-sethandler.c \
- xea1/intlevel-restore.S \
- xea2/intlevel-restore.S \
- xea1/intlevel-setmin.S \
- xea2/intlevel-setmin.S \
- xea1/intlevel-set.S \
- xea2/intlevel-set.S \
- xea1/int-lowpri-dispatcher.S \
- xea2/int-lowpri-dispatcher.S \
- ints-off.S \
- ints-on.S \
- kernel-vector.S \
- memep-enable.S \
- memep-initrams.S \
- memerror-vector.S \
- nmi-vector.S \
- xea2/reloc-vectors.S \
- user-vector.S \
- xea1/window-vectors.S \
- xea2/window-vectors.S
-
-libxtos_a_CFLAGS = \
- $(ARCH_INCDIR) \
- $(ARCH_CFLAGS) \
- $(PLATFORM_INCDIR) \
- $(PLATFORM_DEFS)
-
-libxtos_a_CCASFLAGS = \
- $(ARCH_INCDIR) \
- $(ARCH_ASFLAGS) \
- $(PLATFORM_INCDIR) \
- $(PLATFORM_DEFS)
diff --git a/src/arch/xtensa/smp/xtos/_sharedvectors-for-reset.S b/src/arch/xtensa/smp/xtos/_sharedvectors-for-reset.S
deleted file mode 100644
index ef60901..0000000
--- a/src/arch/xtensa/smp/xtos/_sharedvectors-for-reset.S
+++ /dev/null
@@ -1,40 +0,0 @@
-// _sharedvectors-for-reset.S -- Reference to pull in a shared reset vector
-// $Id: //depot/rel/Foxhill/dot.8/Xtensa/OS/xtos/_sharedvectors-for-reset.S#1 $
-
-// Copyright (c) 2008 Tensilica Inc.
-//
-// Permission is hereby granted, free of charge, to any person obtaining
-// a copy of this software and associated documentation files (the
-// "Software"), to deal in the Software without restriction, including
-// without limitation the rights to use, copy, modify, merge, publish,
-// distribute, sublicense, and/or sell copies of the Software, and to
-// permit persons to whom the Software is furnished to do so, subject to
-// the following conditions:
-//
-// The above copyright notice and this permission notice shall be included
-// in all copies or substantial portions of the Software.
-//
-// THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
-// EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
-// MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
-// IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY
-// CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
-// TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
-// SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
-
-#include <xtensa/coreasm.h>
-
-/* Multicore build flows can use this file (_sharedvectors-for-reset.o)
- by copying it to _sharedvectors.o early in the linker search path
- (to override the default one), and updating the memory map or linker
- scripts accordingly.
- This file pulls in a sharable reset vector (typically
- shared-reset-vector.S, which requires the PRID option). */
-
-.global _SharedResetVector
-
-/* The following allows this object file to be pulled in by reference: */
-.text
-.global _xtos_sharedvectors_ref_
-.set _xtos_sharedvectors_ref_, 0
-
diff --git a/src/arch/xtensa/smp/xtos/_sharedvectors.S b/src/arch/xtensa/smp/xtos/_sharedvectors.S
deleted file mode 100644
index def1441..0000000
--- a/src/arch/xtensa/smp/xtos/_sharedvectors.S
+++ /dev/null
@@ -1,37 +0,0 @@
-// _sharedvectors.S -- Reference symbols to pull in any shared vectors
-// (default version, used when not sharing any vector)
-// $Id: //depot/rel/Foxhill/dot.8/Xtensa/OS/xtos/_sharedvectors.S#1 $
-
-// Copyright (c) 2008 Tensilica Inc.
-//
-// Permission is hereby granted, free of charge, to any person obtaining
-// a copy of this software and associated documentation files (the
-// "Software"), to deal in the Software without restriction, including
-// without limitation the rights to use, copy, modify, merge, publish,
-// distribute, sublicense, and/or sell copies of the Software, and to
-// permit persons to whom the Software is furnished to do so, subject to
-// the following conditions:
-//
-// The above copyright notice and this permission notice shall be included
-// in all copies or substantial portions of the Software.
-//
-// THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
-// EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
-// MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
-// IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY
-// CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
-// TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
-// SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
-
-#include <xtensa/coreasm.h>
-
-/* Not present by default. Multicore build flows build/use a custom
- version of _sharedvectors.o that may pull in shared vectors. */
-
-/* .global _SharedResetVector */
-
-/* The following allows this object file to be pulled in by reference: */
-.text
-.global _xtos_sharedvectors_ref_
-.set _xtos_sharedvectors_ref_, 0
-
diff --git a/src/arch/xtensa/smp/xtos/_vectors.S b/src/arch/xtensa/smp/xtos/_vectors.S
deleted file mode 100644
index 8c70e3f..0000000
--- a/src/arch/xtensa/smp/xtos/_vectors.S
+++ /dev/null
@@ -1,94 +0,0 @@
-// _vectors.S -- Reference symbols to pull in all required vectors
-// $Id: //depot/rel/Foxhill/dot.8/Xtensa/OS/xtos/_vectors.S#1 $
-
-// Copyright (c) 2004, 2006-2007 Tensilica Inc.
-//
-// Permission is hereby granted, free of charge, to any person obtaining
-// a copy of this software and associated documentation files (the
-// "Software"), to deal in the Software without restriction, including
-// without limitation the rights to use, copy, modify, merge, publish,
-// distribute, sublicense, and/or sell copies of the Software, and to
-// permit persons to whom the Software is furnished to do so, subject to
-// the following conditions:
-//
-// The above copyright notice and this permission notice shall be included
-// in all copies or substantial portions of the Software.
-//
-// THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
-// EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
-// MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
-// IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY
-// CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
-// TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
-// SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
-
-#include <xtensa/coreasm.h>
-#include <xtensa/config/system.h> /* for XSHAL_VECTORS_PACKED */
-
-.global _ResetVector
-
-#if XCHAL_HAVE_EXCEPTIONS
-
-# if XCHAL_HAVE_DEBUG
-.global _DebugExceptionVector
-# endif
-
-.global _KernelExceptionVector
-.global _UserExceptionVector
-
-# ifdef XCHAL_DOUBLEEXC_VECTOR_VADDR
-.global _DoubleExceptionVector
-# endif
-
-# if XCHAL_HAVE_NMI
-.global _NMIExceptionVector
-# endif
-
-# if XCHAL_HAVE_WINDOWED
-.global _WindowOverflow4
-.global _WindowUnderflow4
-.global _WindowOverflow8
-.global _WindowUnderflow8
-.global _WindowOverflow12
-.global _WindowUnderflow12
-# endif
-
-# if XCHAL_HAVE_MEM_ECC_PARITY
-.global _MemErrorVector
-# endif
-
-#endif /* XCHAL_HAVE_EXCEPTIONS */
-
-
-#if (XCHAL_NUM_INTLEVELS >= 2) && (2 != XCHAL_DEBUGLEVEL)
-.global _Level2Vector
-#endif
-#if (XCHAL_NUM_INTLEVELS >= 3) && (3 != XCHAL_DEBUGLEVEL)
-.global _Level3Vector
-#endif
-#if (XCHAL_NUM_INTLEVELS >= 4) && (4 != XCHAL_DEBUGLEVEL)
-.global _Level4Vector
-#endif
-#if (XCHAL_NUM_INTLEVELS >= 5) && (5 != XCHAL_DEBUGLEVEL)
-.global _Level5Vector
-#endif
-#if (XCHAL_NUM_INTLEVELS >= 6) && (6 != XCHAL_DEBUGLEVEL)
-.global _Level6Vector
-#endif
-
-#if XCHAL_HAVE_VECBASE && XSHAL_VECTORS_PACKED
-.global _RelocVectors
-#endif
-
-/* These don't take up space: */
-.global xthals_hw_configid0
-.global xthals_hw_configid1
-.global xthals_release_major
-.global xthals_release_minor
-
-/* The following allows this object file to be pulled in by reference: */
-.text
-.global _xtos_vectors_ref_
-.set _xtos_vectors_ref_, 0
-
-
diff --git a/src/arch/xtensa/smp/xtos/checkvecsize b/src/arch/xtensa/smp/xtos/checkvecsize
deleted file mode 100755
index 7078981..0000000
--- a/src/arch/xtensa/smp/xtos/checkvecsize
+++ /dev/null
@@ -1,71 +0,0 @@
-# Script to check that vector code is 16 bytes or less
-# $Id: //depot/rel/Foxhill/dot.8/Xtensa/OS/xtos/checkvecsize#1 $
-
-# Copyright (c) 2001 Tensilica Inc.
-#
-# Permission is hereby granted, free of charge, to any person obtaining
-# a copy of this software and associated documentation files (the
-# "Software"), to deal in the Software without restriction, including
-# without limitation the rights to use, copy, modify, merge, publish,
-# distribute, sublicense, and/or sell copies of the Software, and to
-# permit persons to whom the Software is furnished to do so, subject to
-# the following conditions:
-#
-# The above copyright notice and this permission notice shall be included
-# in all copies or substantial portions of the Software.
-#
-# THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
-# EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
-# MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
-# IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY
-# CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
-# TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
-# SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
-
-package Xtensa::checkvecsize;
-
-# Perl library modules
-use strict;
-use Getopt::Long;
-use FileHandle;
-
-# Program
-
-use vars qw($objdump $maxsize);
-
-{
- $::myname = 'checkvecsize';
-
- # command line
- $maxsize = 16;
- die("Usage is: $::myname -objdump prog [-maxsize n] files...\n")
- unless &GetOptions("objdump=s" => \$objdump,
- "maxsize=i" => \$maxsize)
- && @ARGV > 0 && defined($objdump);
- my $file;
- foreach $file (@ARGV) {
- checkvecsize ($file);
- }
-}
-
-sub checkvecsize {
- my ($file) = @_;
- my $od = new FileHandle "${objdump} -h $file|";
- die("$::myname: $!, opening pipe to $objdump -h $file.\n")
- unless $od;
- while (<$od>) {
- if (/^\s*\d+\s+(\S+)\s+([0-9A-Fa-f]{8})\s/) {
- my $size = hex($2);
- die("$::myname: $file $1 section size is $size bytes.\n")
- if $size > $maxsize;
- }
- }
- $od->close();
-}
-
-
-# Local Variables:
-# mode:perl
-# perl-indent-level:2
-# cperl-indent-level:2
-# End:
diff --git a/src/arch/xtensa/smp/xtos/core-restore.S b/src/arch/xtensa/smp/xtos/core-restore.S
deleted file mode 100644
index dde823d..0000000
--- a/src/arch/xtensa/smp/xtos/core-restore.S
+++ /dev/null
@@ -1,606 +0,0 @@
-// core-restore.S -- core state restore routine (used by PSO)
-// $Id: //depot/rel/Foxhill/dot.8/Xtensa/OS/xtos/core-restore.S#1 $
-
-// Copyright (c) 2012-2013 Tensilica Inc.
-//
-// Permission is hereby granted, free of charge, to any person obtaining
-// a copy of this software and associated documentation files (the
-// "Software"), to deal in the Software without restriction, including
-// without limitation the rights to use, copy, modify, merge, publish,
-// distribute, sublicense, and/or sell copies of the Software, and to
-// permit persons to whom the Software is furnished to do so, subject to
-// the following conditions:
-//
-// The above copyright notice and this permission notice shall be included
-// in all copies or substantial portions of the Software.
-//
-// THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
-// EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
-// MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
-// IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY
-// CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
-// TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
-// SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
-
-#include <xtensa/coreasm.h>
-#include <xtensa/corebits.h>
-#include <xtensa/cacheasm.h>
-#include <xtensa/cacheattrasm.h>
-#include <xtensa/xdm-regs.h>
-#include <xtensa/config/core-isa.h>
-#include <xtensa/mpuasm.h>
-#include <xtensa/xtruntime-core-state.h>
-#include "xtos-internal.h"
-#include <xtensa/idmaasm.h>
-
- .text
-
-
-
- // void _xtos_core_restore(unsigned retvalue, XtosCoreState *savearea)
- //
- // Restore processor state.
- // If save area signature is bad, function just returns.
- // Else, processor state is restored, and execution resumes
- // according to that saved processor state.
- //
- // On entry:
- // Caches are ready to use (initialized or warm, as the case may be).
- //
- .align 4
- .global _xtos_core_restore
- .type _xtos_core_restore,@function
-_xtos_core_restore:
- abi_entry
-
- // Check the save area's signature:
- movi a5, CORE_STATE_SIGNATURE
- l32i a4, a3, CS_SA_signature
- movi a6, 0
- bne a4, a5, 1f // if bad, just return
-
-#if XCHAL_HAVE_INTERRUPTS
- rsil a4, 15 // disable interrupts...
- wsr.intenable a6
-#endif
-
- // Here, call0 is used as an unlimited range jump. It does not return.
- call0 _xtos_core_restore_nw
-
-1: abi_return
-
- .size _xtos_core_restore, . - _xtos_core_restore
-
-
-
- // Restore processor state.
- // On entry:
- // Caches are ready to use (initialized or warm, as the case may be).
- // a2 = return value passed to restored processor state
- // a3 = pointer to save area to restore from
- // INTENABLE = 0 (interrupts all disabled)
- // LITBASE = initialized (per reset vector, not restored)
- // touching a4..a7 won't overflow
- // other registers are mostly undefined
- //
- .align 4
- .global _xtos_core_restore_nw
- .type _xtos_core_restore_nw,@function
-_xtos_core_restore_nw:
-
-#if XCHAL_HAVE_WINDOWED
- s32i a2, a3, CS_SA_areg + 2*4 // save a2 thru rotation
- wsr.excsave1 a3 // save a3 thru rotation
- l32i a6, a3, CS_SA_windowstart // restore windowstart
- l32i a5, a3, CS_SA_windowbase // restore windowbase
- wsr.windowstart a6
- wsr.windowbase a5
- rsync
- // a0-a15 have possibly all changed, so need to reload a3
- rsr.excsave1 a3 // restore a3
- l32i a2, a3, CS_SA_areg + 2*4 // restore a2 (return value)
-#endif
-
- //movi a0, 0
- l32i a0, a3, CS_SA_restore_label // _xtos_core_save_common's return PC
-
- // Just for consistency...
-#if XCHAL_HAVE_INTERRUPTS || XCHAL_HAVE_EXCEPTIONS
- movi a4, 0x11
- wsr.ps a4
- rsync
-#endif
-
- l32i a5, a3, CS_SA_sar // restore sar
- wsr.sar a5
-
-#if XCHAL_HAVE_PSO_CDM
- // Restore PWRCTL (except ShutProcOffOnPWait, cleared when all is done).
- movi a4, XDM_MISC_PWRCTL
- movi a7, PWRCTL_CORE_SHUTOFF // aka ShutProcOffOnPWait
- rer a6, a4 // read pwrctl
- l32i a5, a3, CS_SA_pwrctl // get saved pwrctl
- and a7, a7, a6 // keep just ShutProcOffOnPWait bit
- or a5, a5, a7 // keep it set if already set (clear later)
- wer a5, a4 // restore pwrctl (except ShutProcOffOnPWait)
-#endif
-
- .set _idx, 2
- .rept XCHAL_NUM_INTLEVELS+XCHAL_HAVE_NMI-1
- l32i a5, a3, CS_SA_epc + 4*(_idx-2)
- INDEX_SR wsr.epc a5
- l32i a5, a3, CS_SA_eps + 4*(_idx-2)
- INDEX_SR wsr.eps a5
- l32i a5, a3, CS_SA_excsave + 4*(_idx-2)
- INDEX_SR wsr.excsave a5
- .set _idx, _idx+1
- .endr
-
-#if XCHAL_HAVE_LOOPS
- l32i a5, a3, CS_SA_lbeg
- wsr.lbeg a5
- l32i a5, a3, CS_SA_lend
- wsr.lend a5
- l32i a5, a3, CS_SA_lcount
- wsr.lcount a5
-#endif
-#if XCHAL_HAVE_ABSOLUTE_LITERALS
- l32i a5, a3, CS_SA_litbase
- wsr.litbase a5
-#endif
-#if XCHAL_HAVE_VECBASE
- l32i a5, a3, CS_SA_vecbase
- wsr.vecbase a5
-#endif
-#if XCHAL_HAVE_S32C1I && (XCHAL_HW_MIN_VERSION >= XTENSA_HWVERSION_RC_2009_0) /* have ATOMCTL ? */
- l32i a5, a3, CS_SA_atomctl
- wsr.atomctl a5
-#endif
-#if XCHAL_HAVE_PREFETCH
- l32i a5, a3, CS_SA_prefctl
- wsr.prefctl a5
-#endif
-#if XCHAL_USE_MEMCTL
- l32i a5, a3, CS_SA_memctl
- wsr.memctl a5
-#endif
-#if XCHAL_HAVE_DEBUG
- // NOTE: restore of debug state is conditional,
- // as the power-down and wakeup code might be actively debugged.
- rsr.icountlevel a5
- bnez a5, 1f // skip if being single-stepped (not failsafe!)
- l32i a5, a3, CS_SA_icount
- wsr.icount a5
- l32i a5, a3, CS_SA_icountlevel
- wsr.icountlevel a5
-1:
- //l32i a5, a3, CS_SA_debugcause // (won't get restored?)
- //wsr.debugcause a5
- //l32i a5, a3, CS_SA_ddr
- //wsr.ddr a5
-# if XCHAL_NUM_IBREAK
- rsr.ibreakenable a6
- bnez a5, 1f // skip restore if already some ibreaks defined
-
- .set _idx, 0
- .rept XCHAL_NUM_IBREAK
- l32i a5, a3, CS_SA_ibreaka + 4*_idx
- INDEX_SR wsr.ibreaka a5
- .set _idx, _idx+1
- .endr
-
- l32i a5, a3, CS_SA_ibreakenable
- wsr.ibreakenable a5
-1:
-# endif
- .set _idx, 0
- .rept XCHAL_NUM_DBREAK
- INDEX_SR rsr.dbreakc a6
- bbsi.l a6, 30, 1f // skip restore of that dbreak if already active
- bbsi.l a6, 31, 1f // ditto
- l32i a5, a3, CS_SA_dbreaka + 4*_idx
- INDEX_SR wsr.dbreaka a5
- l32i a5, a3, CS_SA_dbreakc + 4*_idx
- INDEX_SR wsr.dbreakc a5
-1:
- .set _idx, _idx+1
- .endr
-#endif
-
- .set _idx, 0
- .rept XCHAL_NUM_MISC_REGS
- l32i a5, a3, CS_SA_misc + 4*_idx
- INDEX_SR wsr.misc a5
- .set _idx, _idx+1
- .endr
-
-#if XCHAL_HAVE_MEM_ECC_PARITY
- l32i a5, a3, CS_SA_mepc
- wsr.mepc a5
- l32i a5, a3, CS_SA_meps
- wsr.meps a5
- l32i a5, a3, CS_SA_mesave
- wsr.mesave a5
- l32i a5, a3, CS_SA_mesr
- wsr.mesr a5
- l32i a5, a3, CS_SA_mecr
- wsr.mecr a5
- l32i a5, a3, CS_SA_mevaddr
- wsr.mevaddr a5
-#endif
-
- /* TIE state */
- addi a4, a3, CS_SA_ncp
- xchal_ncp_load a4, a5,a6,a7,a8 // restore non-coprocessor state
-#if XCHAL_HAVE_CP
- movi a6, -1
- wsr.cpenable a6 // enable all coprocessors
- rsync
- xchal_cp0_load a4, a5,a6,a7,a8 continue=1
- xchal_cp1_load a4, a5,a6,a7,a8 continue=1
- xchal_cp2_load a4, a5,a6,a7,a8 continue=1
- xchal_cp3_load a4, a5,a6,a7,a8 continue=1
- xchal_cp4_load a4, a5,a6,a7,a8 continue=1
- xchal_cp5_load a4, a5,a6,a7,a8 continue=1
- xchal_cp6_load a4, a5,a6,a7,a8 continue=1
- xchal_cp7_load a4, a5,a6,a7,a8 continue=1
- //xchal_cp8_load a4, a5,a6,a7,a8 continue=1
- //xchal_cp9_load a4, a5,a6,a7,a8 continue=1
- //xchal_cp10_load a4, a5,a6,a7,a8 continue=1
- //xchal_cp11_load a4, a5,a6,a7,a8 continue=1
- //xchal_cp12_load a4, a5,a6,a7,a8 continue=1
- //xchal_cp13_load a4, a5,a6,a7,a8 continue=1
- //xchal_cp14_load a4, a5,a6,a7,a8 continue=1
- //xchal_cp15_load a4, a5,a6,a7,a8 continue=1
- l32i a5, a3, CS_SA_cpenable
- wsr.cpenable a5
-#endif
-
- /* TLB state (for known MMU types only, not internal custom) */
- // FIXME FIXME FIXME TODO:
- // This restore code does not work in the general case,
- // for CaXLT or full MMU, in particular when any address mappings
- // were active when saved, that don't match reset state and affect
- // code and data currently being accessed for restore.
-#if XCHAL_HAVE_MIMIC_CACHEATTR || XCHAL_HAVE_XLT_CACHEATTR
- addi a4, a3, CS_SA_tlbs // where to start loading TLB entry info
- movi a5, 0x20000000
- movi a6, 0
-1:
- l32i a7, a4, 0
- wdtlb a7, a6 // write DTLB entry PPN + CA
- dsync
- l32i a7, a4, 4
- j 2f
- // Ensure WITLB and ISYNC are in same cache line, when writing ITLB
- // entry that maps this currently running code
- // (micro-architecture defined sequence):
- .begin no-transform
- .align 16
-2: witlb a7, a6 // write ITLB entry PPN + CA
- isync
- .end no-transform
- nop
- nop
- addi a4, a4, 8
- add a6, a6, a5
- bnez a6, 1b
-
-#elif XCHAL_HAVE_PTP_MMU
- addi a4, a3, CS_SA_tlbs // where to start storing TLB entry info
- movi a10, _xtos_pso_tlbmap
- movi a11, _xtos_pso_tlbmap_end
- l32i a14, a3, CS_SA_dtlbcfg
- l32i a15, a3, CS_SA_itlbcfg
- wsr.dtlbcfg a14 // page size index (0..3) for each DTLB way
- wsr.itlbcfg a15 // page size index (0..3) for each ITLB way
- l32i a5, a3, CS_SA_ptevaddr
- wsr.ptevaddr a5
- rsync
- // Loop from last way to first (less register pressure that way).
-.Loop_tlbmap_rest:
- addi a11, a11, -8 // next way
- l32i a8, a11, 0 // map of four (page size log2) per index for this way
- // DTLB page size:
- extui a12, a14, 0, 4 // page size index for this DTLB way
- srli a14, a14, 4 // (for next way)
- ssa8l a12 // prepare to shift right by 8*a12
- srl a12, a8 // page size log2 for this DTLB way
- ssl a12 // prepare to shift left by a12
- movi a12, 1 // (to compute 1 << (page size log2))
- sll a12, a12 // page size for this DTLB way
-
- // Restore all entries of this DTLB way:
- l32i a9, a11, 4 // number of entries for this way
- sub a5, a11, a10 // way number * 8
- srli a5, a5, 3 // way number
- extui a9, a9, 0, 8
-1:
- l32i a6, a4, 0 // read entry VPN + ASID
- extui a7, a6, 0, 8 // get ASID
- bnez a7, 2f // if non-zero, need WDTLB
- add a6, a6, a5 // zero, so need IDTLB - add way number
- idtlb a6 // invalidate DTLB entry
- j 5f
-2: // Non-zero ASID. Put in RASID and adjust PS.RING accordingly.
- bgeui a7, 5, 3f // branch if ASID >= 5
- addi a7, a7, -1
- slli a7, a7, 6 // PS.RING = ASID - 1
- addi a7, a7, 0x11 // PS.EXCM=1, PS.INTLEVEL=1
- movi a6, 0x04030201 // for ASID in {1 .. 4}
- j 4f
-3: // ASID >= 5, place it in RASID
- movi a6, 0x00030201
- slli a7, a7, 24
- add a6, a7, a6 // RASID = 0x <ASID> 03 02 01
- movi a7, 0xd1 // PS.RING=3, PS.EXCM=1, PS.INTLEVEL=1
-4: wsr.rasid a6
- wsr.ps a7
- rsync
- l32i a6, a4, 0 // read entry VPN + ASID
- l32i a7, a4, 4 // read entry PPN + CA
- srli a6, a6, 8 // replace ASID ...
- slli a6, a6, 8 // ...
- add a6, a6, a5 // ... with way number
- wdtlb a7, a6 // write DTLB entry ...
-5: dsync
- addi a4, a4, 8
- add a5, a5, a12 // next entry of this DTLB way
- addi a9, a9, -1
- bnez a9, 1b
-
- // ITLB page size:
- extui a12, a15, 0, 4 // page size index for this ITLB way
- srli a15, a15, 4 // (for next way)
- ssa8l a12 // prepare to shift right by 8*a12
- srl a12, a8 // page size log2 for this ITLB way
- ssl a12 // prepare to shift left by a12
- movi a12, 1 // (to compute 1 << (page size log2))
- sll a12, a12 // page size for this ITLB way
-
- // Restore all entries of this ITLB way:
- l32i a9, a11, 4 // number of entries for this way
- sub a5, a11, a10 // way number * 8
- srli a5, a5, 3 // way number
- bbsi.l a9, 15, 6f // skip ITLB if is a DTLB-only way
- extui a9, a9, 0, 8
-1:
- l32i a6, a4, 0 // read entry VPN + ASID
- extui a7, a6, 0, 8 // get ASID
- bnez a7, 2f // if non-zero, need WITLB
- add a6, a6, a5 // zero, so need IITLB - add way number
- iitlb a6 // invalidate ITLB entry
- j 5f
-2: // Non-zero ASID. Put in RASID and adjust PS.RING accordingly.
- bgeui a7, 5, 3f // branch if ASID >= 5
- addi a7, a7, -1
- slli a7, a7, 6 // PS.RING = ASID - 1
- addi a7, a7, 0x11 // PS.EXCM=1, PS.INTLEVEL=1
- movi a6, 0x04030201 // for ASID in {1 .. 4}
- j 4f
-3: // ASID >= 5, place it in RASID
- movi a6, 0x00030201
- slli a7, a7, 24
- add a6, a7, a6 // RASID = 0x <ASID> 03 02 01
- movi a7, 0xd1 // PS.RING=3, PS.EXCM=1, PS.INTLEVEL=1
-4: wsr.rasid a6
- wsr.ps a7
- rsync
- l32i a6, a4, 0 // read entry VPN + ASID
- l32i a7, a4, 4 // read entry PPN + CA
- srli a6, a6, 8 // replace ASID ...
- slli a6, a6, 8 // ...
- add a6, a6, a5 // ... with way number
- j 8f
- .align 16 // ensure WITLB and ISYNC in same cache line
-8: witlb a7, a6 // write ITLB entry ...
-5: isync
- addi a4, a4, 8
- add a5, a5, a12 // next entry of this ITLB way
- addi a9, a9, -1
- bnez a9, 1b
-6:
-
- bne a11, a10, .Loop_tlbmap_rest // loop for next TLB way
- l32i a5, a3, CS_SA_rasid
- wsr.rasid a5
- movi a6, 0x11
- wsr.ps a6
- rsync
- // Done saving TLBs.
-#endif
-
-#if XCHAL_HAVE_MPU
- addi a4, a3, CS_SA_mpuentry // MPU restore location
- movi a5, XCHAL_MPU_ENTRIES
- mpu_write_map a4, a5, a6, a7, a8, a9
- l32i a4, a3, CS_SA_cacheadrdis
- wsr.cacheadrdis a4
-#endif
-
-#if XCHAL_HAVE_IDMA
- addi a4, a3, CS_SA_idmaregs // IDMA regs restore location
- _idma_restore a4, a5, a6, a7
-#endif
-
-#if XCHAL_HAVE_WINDOWED
- // All the stack frames (except for our own) are supposed to be spilled
- // into the stack. So now we restore the saved registers for our caller
- // (and its caller) into the correct locations in the stack. See the
- // comments in core-save.S and also the Xtensa Programmers Guide for
- // more information. Of course we only restore if there is valid saved
- // state.
-
- l32i a4, a3, CS_SA_caller_regs_saved // flag
- beqz a4, .Lendcr // skip restore if 0
-
- // Restore our caller's a0-a3
-
- l32i a1, a3, CS_SA_areg + 1*4 // restore a1
- addi a4, a1, -16
- l32i a5, a3, CS_SA_caller_regs
- l32i a6, a3, CS_SA_caller_regs + 4
- s32i a5, a4, 0 // caller a0
- s32i a6, a4, 4 // caller a1
- l32i a5, a3, CS_SA_caller_regs + 8
- l32i a6, a3, CS_SA_caller_regs + 12
- s32i a5, a4, 8 // caller a2
- s32i a6, a4, 12 // caller a3
-
- // Now restore our callers caller's a0-a3
-
- l32i a5, a3, CS_SA_caller_regs + 16
- l32i a6, a3, CS_SA_caller_regs + 20
- s32i a5, a1, 0 // caller caller a0
- s32i a6, a1, 4 // caller caller a1
- l32i a5, a3, CS_SA_caller_regs + 24
- l32i a6, a3, CS_SA_caller_regs + 28
- s32i a5, a1, 8 // caller caller a2
- s32i a6, a1, 12 // caller caller a3
-
- // Now restore caller's a4-a11 as required
- // NOTE a0 is pointing to _xtos_core_save() not the actual caller
-
- l32i a4, a3, CS_SA_areg // load actual return address
- extui a4, a4, 30, 2 // top 2 bits of ret addr
- blti a4, 2, .Lendcr
- l32i a5, a1, 4 // a5 <- caller caller a1
- slli a4, a4, 4
- sub a4, a5, a4 // a4 <- bottom of extra save area
- addi a5, a5, -16 // a5 <- top of extra save area
- addi a6, a3, CS_SA_caller_regs + 32 // location to start restore from
-.Lcrloop:
- l32i a7, a6, 0 // Restore in groups of 4 registers
- l32i a8, a6, 4
- s32i a7, a4, 0
- s32i a8, a4, 4
- l32i a7, a6, 8
- l32i a8, a6, 12
- s32i a7, a4, 8
- s32i a8, a4, 12
- addi a4, a4, 16
- addi a6, a6, 16
- blt a4, a5, .Lcrloop
-.Lendcr:
-#endif
-
- // Restore timers and CCOUNT right before enabling interrupts. We will
- // try to restore any timer interrupts that were pending (as indicated
- // by the INTERRUPT register) at the time of the state save.
-#if XCHAL_HAVE_CCOUNT
- .macro restore_timer num intr
- l32i a5, a3, CS_SA_ccompare + 4*\num // Load CCOMPARE value
- l32i a6, a3, CS_SA_interrupt // Load old INTERRUPT value
- writesr ccompare \num a5 // Restore CCOMPARE
- bbci.l a6, \intr, .Lrtdone\num // Intr not set for this timer
- addi a5, a5, -1 // CCOUNT = CCOMPARE - 1
-.Lrttry\num:
- wsr.ccount a5 // Set CCOUNT and wait
- esync
- nop
- rsr.interrupt a6
- bbci.l a6, \intr, .Lrttry\num // If intr not set then retry
-.Lrtdone\num:
- .endm
-
-#if XCHAL_NUM_TIMERS > 0
- restore_timer 0 XCHAL_TIMER0_INTERRUPT
-#endif
-#if XCHAL_NUM_TIMERS > 1
- restore_timer 1 XCHAL_TIMER1_INTERRUPT
-#endif
-#if XCHAL_NUM_TIMERS > 2
- restore_timer 2 XCHAL_TIMER2_INTERRUPT
-#endif
-#if XCHAL_NUM_TIMERS > 3
- restore_timer 3 XCHAL_TIMER3_INTERRUPT
-#endif
-
- // Attempt to clear any spurious timer interrupts caused by the CCOUNT
- // dance above.
-#if XCHAL_NUM_TIMERS > 0
- l32i a5, a3, CS_SA_ccount // Restore CCOUNT
- wsr.ccount a5
- l32i a5, a3, CS_SA_interrupt // Load old intr value
- bbsi.l a5, XCHAL_TIMER0_INTERRUPT, .Lx1 // Skip if timer0 intr set
- rsr.ccompare0 a6 // Force timer0 intr clear
- wsr.ccompare0 a6
-.Lx1:
-#if XCHAL_NUM_TIMERS > 1
- bbsi.l a5, XCHAL_TIMER1_INTERRUPT, .Lx2 // Skip if timer1 intr set
- rsr.ccompare1 a6 // Force timer1 intr clear
- wsr.ccompare1 a6
-.Lx2:
-#endif
-#if XCHAL_NUM_TIMERS > 2
- bbsi.l a5, XCHAL_TIMER2_INTERRUPT, .Lx3 // Skip if timer2 intr set
- rsr.ccompare2 a6 // Force timer2 intr clear
- wsr.ccompare2 a6
-.Lx3:
-#endif
-#if XCHAL_NUM_TIMERS > 3
- bbsi.l a5, XCHAL_TIMER3_INTERRUPT, .Lx4 // Skip if timer3 intr set
- rsr.ccompare3 a6 // Force timer3 intr clear
- wsr.ccompare3 a6
-.Lx4:
-#endif
-#endif
-
- l32i a5, a3, CS_SA_ccount // Restore CCOUNT again
- wsr.ccount a5
-#endif
-
-#if XCHAL_HAVE_INTERRUPTS
- rsil a6, 15 // disable interrupts before enabling with INTENABLE
- l32i a5, a3, CS_SA_intenable
- wsr.intenable a5
- movi a4, XCHAL_INTTYPE_MASK_SOFTWARE // restore any pending software interrupts
- l32i a5, a3, CS_SA_interrupt
- and a5, a5, a4
- wsr.intset a5
- rsync
-#endif
-
- //l32i a0, a3, CS_SA_restore_label // _xtos_core_save_common's return PC
-#if XCHAL_HAVE_INTERRUPTS || XCHAL_HAVE_EXCEPTIONS
- //l32i a4, a3, CS_SA_ps
- l32i a5, a3, CS_SA_epc1
- wsr.epc1 a5
- l32i a5, a3, CS_SA_excsave1
- wsr.excsave1 a5
-# ifdef XCHAL_DOUBLEEXC_VECTOR_VADDR
- l32i a5, a3, CS_SA_depc
- wsr.depc a5
-# endif
- //wsr.ps a4 // PS restored by caller
- //rsync
-#endif
-
-#if XCHAL_HAVE_PSO_CDM
- // As late as possible, wait for debug to wakeup, and clear PWRCTL.ShutProcOffOnPWait.
- movi a4, XDM_MISC_PWRCTL
- rer a5, a4 // read pwrctl
-
- // Wait for debug powerup to complete (if started):
- bbci.l a5, PWRCTL_DEBUG_WAKEUP_SHIFT, 1f
- movi a7, XDM_MISC_PWRSTAT
-2: rer a6, a7 // read PWRSTAT
- bbci.l a6, PWRSTAT_DEBUG_DOMAIN_ON_SHIFT, 2b // loop until debug is powered up
-1:
-
- movi a7, ~PWRCTL_CORE_SHUTOFF // aka ShutProcOffOnPWait
- and a5, a5, a7 // clear ShutProcOffOnPWait bit
- wer a5, a4 // update pwrctl
-#endif
-
- movi a4, 0
- s32i a4, a3, CS_SA_signature // make sure save area is marked as no longer valid
-#if XCHAL_DCACHE_IS_WRITEBACK
- dhwb a3, CS_SA_signature
-#endif
- ret // return from _xtos_core_save_common
- // NOTE: a2 holds return value as specified to
- // _xtos_core_restore()
-
- .size _xtos_core_restore_nw, . - _xtos_core_restore_nw
-
diff --git a/src/arch/xtensa/smp/xtos/core-save.S b/src/arch/xtensa/smp/xtos/core-save.S
deleted file mode 100644
index 395c112..0000000
--- a/src/arch/xtensa/smp/xtos/core-save.S
+++ /dev/null
@@ -1,762 +0,0 @@
-// core-save.S -- core state save/restore routines (used by PSO)
-// $Id: //depot/rel/Foxhill/dot.8/Xtensa/OS/xtos/core-save.S#1 $
-
-// Copyright (c) 2012-2013 Tensilica Inc.
-//
-// Permission is hereby granted, free of charge, to any person obtaining
-// a copy of this software and associated documentation files (the
-// "Software"), to deal in the Software without restriction, including
-// without limitation the rights to use, copy, modify, merge, publish,
-// distribute, sublicense, and/or sell copies of the Software, and to
-// permit persons to whom the Software is furnished to do so, subject to
-// the following conditions:
-//
-// The above copyright notice and this permission notice shall be included
-// in all copies or substantial portions of the Software.
-//
-// THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
-// EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
-// MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
-// IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY
-// CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
-// TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
-// SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
-
-#include <xtensa/coreasm.h>
-#include <xtensa/corebits.h>
-#include <xtensa/cacheasm.h>
-#include <xtensa/cacheattrasm.h>
-#include <xtensa/xdm-regs.h>
-#include <xtensa/xtruntime-core-state.h>
-#include <xtensa/mpuasm.h>
-#include "xtos-internal.h"
-
-.weak _idma_pso_save
-//.type xtos_C_core_save, @function
-
-
- .text
-
-
- // (Place this alternate entry symbol *outside* the _xtos_core_save()
- // function, to avoid confusing debugging / profiling / etc.)
- .align 4
- .global _xtos_core_save_entry
- .type _xtos_core_save_entry,@function
-_xtos_core_save_entry:
- j .Lcore_save
- .size _xtos_core_save_entry, . - _xtos_core_save_entry
-
-
- // int _xtos_core_save(unsigned flags, XtosCoreState *savearea, void *code)
- //
- // Generic processor state save routine.
- //
- // On entry (after ENTRY if windowed):
- // a0 = return PC
- // a2 = flags argument
- // a3 = ptr to save area
- // a4 = ptr to code to jump to after save (just return if 0)
- // Returns:
- // 0 when first returning from this call (if a4 == 0)
- // non-zero (passed from restore call) when returning from restore
- // (if a4 != 0, return behavior if any depends on code at a4)
- //
- .align 4
- .global _xtos_core_save
- .type _xtos_core_save,@function
-_xtos_core_save:
- abi_entry
-
-.Lcore_save:
- s32i a0, a3, CS_SA_areg + 0*4 // save a0 (clobbered below)
- s32i a1, a3, CS_SA_areg + 1*4 // save a1
- s32i a2, a3, CS_SA_areg + 2*4 // save a2 (flags arg, for debugging only)
- s32i a4, a3, CS_SA_areg + 4*4 // save a4 (code to jump to after saving)
-#ifdef __XTENSA_CALL0_ABI__
- // Callee-saved regs:
- s32i a12, a3, CS_SA_areg + 12*4 // save a12
- s32i a13, a3, CS_SA_areg + 13*4 // save a13
- s32i a14, a3, CS_SA_areg + 14*4 // save a14
- s32i a15, a3, CS_SA_areg + 15*4 // save a15
-#else
- call4 xthal_window_spill // spill live caller windows to stack
-#endif
- j .Ls1
-
- .align 16
-.Ls1:
-#if XCHAL_HAVE_INTERRUPTS
- rsil a4, 15 // disable interrupts before clobbering a0
-#elif XCHAL_HAVE_EXCEPTIONS
- rsr.ps a4
-#endif
-
-#if XCHAL_HAVE_EXCEPTIONS
- s32i a4, a3, CS_SA_ps // save PS
-#endif
-
-#if XCHAL_HAVE_IDMA
- movi a4, _idma_pso_save
- beqz a4, .LnoIDMA
-# ifdef __XTENSA_CALL0_ABI__
- mov a13, a3
- mov a12, a2
- addi a3, a3, CS_SA_idmaregs // location for IDMA regs save
- call0 _idma_pso_save
- mov a3, a13
- mov a2, a12
-# else
- mov a6, a2
- addi a7, a3, CS_SA_idmaregs // location for IDMA regs save
- call4 _idma_pso_save
-# endif
-.LnoIDMA:
-#endif
-
-// not yet implemented
-//# ifdef __XTENSA_CALL0_ABI__
-// mov a13, a3
-// mov a12, a2
-// call0 xtos_C_core_save
-// mov a3, a13
-// mov a2, a12
-//# else
-// mov a6, a2
-// mov a7, a3
-// call4 xtos_C_core_save
-//# endif
-//#endif
-
-#if XCHAL_HAVE_CCOUNT
- rsr.ccount a5 // save CCOUNT restore value
-#endif
-#if XCHAL_HAVE_INTERRUPTS
- rsr.interrupt a6 // save pending interrupts
- s32i a6, a3, CS_SA_interrupt
-#endif
-#if XCHAL_HAVE_CCOUNT
- s32i a5, a3, CS_SA_ccount
-#endif
-
- call0 _xtos_core_save_common // save and shutoff -- returns after wakeup
-
- // a2 now contains return value.
- // a3 still points to save area.
- // Interrupts still disabled.
-
- // Restore WINDOWSTART to single window. Leave WINDOWBASE wherever it is.
- //rsr.windowbase a6
- //movi a5, 1
- //ssl a6
- //sll a5, a5
- //wsr.windowstart a5
- //rsync
-
- l32i a0, a3, CS_SA_areg + 0*4 // restore a0
- l32i a1, a3, CS_SA_areg + 1*4 // restore a1
-#ifdef __XTENSA_CALL0_ABI__
- // Callee-saved regs:
- l32i a12, a3, CS_SA_areg + 12*4 // restore a12
- l32i a13, a3, CS_SA_areg + 13*4 // restore a13
- l32i a14, a3, CS_SA_areg + 14*4 // restore a14
- l32i a15, a3, CS_SA_areg + 15*4 // restore a15
-#endif
-
-#if XCHAL_HAVE_EXCEPTIONS
- // Now that we've restored windowed state (a0,a1), we can restore interrupts.
- l32i a4, a3, CS_SA_ps // restore ps
- wsr.ps a4
- rsync
-#endif
-
- abi_return
-
-
-
- // Generic processor state save routine, callable from assembly-level
- // (Does not assume valid stack, saves all ARs, no window-spill etc.)
- //
- // On entry:
- // a0 = return PC
- // a2 = flags argument
- // a3 = ptr to save area
- // a4 = ptr to code to jump to after save (just return if 0)
- // All other registers are saved.
- // Returns:
- // 0 when first returning from this call (if a4 == 0)
- // non-zero (passed from restore call) when returning from restore
- // (if a4 != 0, return behavior if any depends on code at a4)
- //
- .align 4
- .global _xtos_core_save_nw
-_xtos_core_save_nw:
- s32i a0, a3, CS_SA_areg + 0*4 // save a0 (clobbered below)
- s32i a1, a3, CS_SA_areg + 1*4 // save a1
- s32i a2, a3, CS_SA_areg + 2*4 // save a2 (flags arg, for debugging only)
- s32i a4, a3, CS_SA_areg + 4*4 // save a4 (code to jump to after saving)
- s32i a5, a3, CS_SA_areg + 5*4 // save a5
- s32i a6, a3, CS_SA_areg + 6*4 // save a6
- s32i a7, a3, CS_SA_areg + 7*4 // save a7
- j .Ls2
-
- .align 16
-.Ls2:
-#if XCHAL_HAVE_INTERRUPTS
- rsil a4, 15 // disable interrupts before rotating etc
-#elif XCHAL_HAVE_EXCEPTIONS
- rsr.ps a4
-#endif
-
-#if XCHAL_HAVE_EXCEPTIONS
- s32i a4, a3, CS_SA_ps // save PS
-#endif
-
-#if XCHAL_HAVE_CCOUNT
- rsr.ccount a5 // save CCOUNT restore value
-#endif
-#if XCHAL_HAVE_INTERRUPTS
- rsr.interrupt a6 // save pending interrupts
- s32i a6, a3, CS_SA_interrupt
-#endif
-#if XCHAL_HAVE_CCOUNT
- s32i a5, a3, CS_SA_ccount
-#endif
-
-#if XCHAL_HAVE_WINDOWED
- movi a5, XCHAL_NUM_AREGS / 8 - 1 // number of 8-reg chunks to save (a0-a7 already done)
-#endif
-1: s32i a8, a3, CS_SA_areg + 8*4 // save a8
- s32i a9, a3, CS_SA_areg + 9*4 // save a9
- s32i a10,a3, CS_SA_areg + 10*4 // save a10
- s32i a11,a3, CS_SA_areg + 11*4 // save a11
- s32i a12,a3, CS_SA_areg + 12*4 // save a12
- s32i a13,a3, CS_SA_areg + 13*4 // save a13
- s32i a14,a3, CS_SA_areg + 14*4 // save a14
- s32i a15,a3, CS_SA_areg + 15*4 // save a15
-#if XCHAL_HAVE_WINDOWED
- addi a11, a3, 8*4 // next frame (a11 will become a3, a13 become a5)
- addi a13, a5, -1
- rotw 2
- bnez a5, 1b // loop until all frames done
- rotw 2 // back to starting windowbase
-#endif
-
- movi a1, 0 // not to save any regs from stack
- call0 _xtos_core_save_common
-
- // a2 now contains return value.
- // a3 still points to save area.
- // Interrupts still disabled.
-
-#if XCHAL_HAVE_WINDOWED
- rotw -2
- movi a5, XCHAL_NUM_AREGS / 8 - 1 // 8-reg chunks to restore (a0-a7 already done)
- addi a3, a11, XCHAL_NUM_AREGS * 4
-1: rotw -2
- addi a3, a11, -8*4
- addi a5, a13, -1
-#endif
- l32i a8, a3, CS_SA_areg + 8*4 // restore a8
- l32i a9, a3, CS_SA_areg + 9*4 // restore a9
- l32i a10,a3, CS_SA_areg + 10*4 // restore a10
- l32i a11,a3, CS_SA_areg + 11*4 // restore a11
- l32i a12,a3, CS_SA_areg + 12*4 // restore a12
- l32i a13,a3, CS_SA_areg + 13*4 // restore a13
- l32i a14,a3, CS_SA_areg + 14*4 // restore a14
- l32i a15,a3, CS_SA_areg + 15*4 // restore a15
-#if XCHAL_HAVE_WINDOWED
- bnez a5, 1b // loop until all frames done
- // We're now back to starting windowbase, and original a3.
-#endif
-
- l32i a0, a3, CS_SA_areg + 0*4 // restore a0
- l32i a1, a3, CS_SA_areg + 1*4 // restore a1
- // Don't clobber return value, so don't restore a2.
- l32i a4, a3, CS_SA_areg + 4*4 // restore a4
- l32i a5, a3, CS_SA_areg + 5*4 // restore a5
- l32i a6, a3, CS_SA_areg + 6*4 // restore a6
-#if XCHAL_HAVE_EXCEPTIONS
- // Now that we've restored windowed state (a0,a1,done rotating), we can restore interrupts.
- l32i a7, a3, CS_SA_ps // restore ps
- wsr.ps a7
- rsync
-#endif
- l32i a7, a3, CS_SA_areg + 7*4 // restore a7
- ret
-
-
-
-
- // Common state save / shut-off code.
- //
- // a0 = return PC within caller shut-off routine
- // a1 = stack if != 0
- // a2 = flags argument
- // a3 = pointer to _xtos_pso_savearea
- // a4 = PS to save/restore
- // PS.INTLEVEL = 15 (interrupts disabled, except NMI)
- // a5-a15 (and other ARs) are available.
- // NOTE: CCOUNT and INTERRUPT have already been saved in save area.
- //
- .align 4
- //.global _xtos_core_save_common
-_xtos_core_save_common:
-//#if XCHAL_HAVE_EXCEPTIONS
-// s32i a4, a3, CS_SA_ps // save PS
-//#endif
-
-#if XCHAL_HAVE_CACHE_BLOCKOPS
- pfend.o // terminate non-essential block-prefetch ops
-#endif
-
-#if XCHAL_HAVE_WINDOWED
- // The following discussion is valid if we have a stack:
- // At this point, all non-live register windows have been spilled to the
- // stack. However, we cannot leave any spilled registers in our stack frame
- // or our caller's stack frame, since these frames could change after we
- // return and before restore() is called. So all spilled registers in the
- // current and previous stack frames must be saved to the save area. This
- // means a max of 16 registers: 4 base save registers for our caller, upto
- // 8 extra save registers for our caller, and 4 base save registers for the
- // next function up from our caller. The stack looks like this:
- //
- // ------------------------------- <---- stack ptr of function (i - 2)
- // Base save area i - 3
- // -------------------------------
- // Extra save area i - 1
- // (0-8 registers depending on call type)
- // -------------------------------
- // Locals i - 1
- // ------------------------------- <---- stack ptr of function (i - 1)
- // Base save area i - 2 (our caller)
- //
- // ------------------------------- <---- Our stack ptr (a1)
- // Base save area i - 1
- // -------------------------------
- //
- // We don't have any extra save area or locals in our frame. See the
- // Xtensa Programmer's Guide for more details of the stack layout.
- //
- // NOTE that we are not counting the call0 to _xtos_core_save_common() since
- // that does not result in any register window rotation nor stack ptr change.
-
- s32i a1, a3, CS_SA_caller_regs_saved // save flag
- beqz a1, .Lendcr // skip if no stack
-
- // Save our caller's a0-a3 from the base save area (a1-16)
-
- addi a4, a1, -16
- l32i a5, a4, 0
- l32i a6, a4, 4
- s32i a5, a3, CS_SA_caller_regs // caller a0
- s32i a6, a3, CS_SA_caller_regs + 4 // caller a1
- l32i a5, a4, 8
- l32i a6, a4, 12
- s32i a5, a3, CS_SA_caller_regs + 8 // caller a2
- s32i a6, a3, CS_SA_caller_regs + 12 // caller a3
-
- // Save our callers caller's a0-a3 from its base save area (a1+0)
-
- l32i a5, a1, 0
- l32i a6, a1, 4
- s32i a5, a3, CS_SA_caller_regs + 16 // caller caller a0
- s32i a6, a3, CS_SA_caller_regs + 20 // caller caller a1
- l32i a5, a1, 8
- l32i a6, a1, 12
- s32i a5, a3, CS_SA_caller_regs + 24 // caller caller a2
- s32i a6, a3, CS_SA_caller_regs + 28 // caller caller a3
-
- // Now save 0-8 registers for our caller from its ext save area
- // NOTE we can't use a0 directly because we are one level down
-
- l32i a4, a3, CS_SA_areg // pull in the return address
- extui a4, a4, 30, 2 // Top 2 bits of ret addr
- blti a4, 2, .Lendcr // No regs to save
- l32i a5, a1, 4 // a5 <- caller caller a1
- slli a4, a4, 4
- sub a4, a5, a4 // a4 <- bottom of extra save area
- addi a5, a5, -16 // a5 <- top of extra save area
- addi a6, a3, CS_SA_caller_regs + 32 // location to start saving to
-.Lcrloop:
- l32i a7, a4, 0 // Save in groups of 4 registers
- l32i a8, a4, 4
- s32i a7, a6, 0
- s32i a8, a6, 4
- l32i a7, a4, 8
- l32i a8, a4, 12
- s32i a7, a6, 8
- s32i a8, a6, 12
- addi a4, a4, 16
- addi a6, a6, 16
- blt a4, a5, .Lcrloop
-.Lendcr:
-#endif
-
- // We want to save the CCOUNT value as soon as feasible after disabling
- // interrupts, so that the counter does not run past any CCOMPARE value
- // and miss a timer interrupt. The callers of this function have saved
- // the values of CCOUNT and INTERRUPT immediately after disabling interrupts.
-
-#if XCHAL_HAVE_CCOUNT
- .set _idx, 0
- .rept XCHAL_NUM_TIMERS
- INDEX_SR rsr.ccompare a5
- s32i a5, a3, CS_SA_ccompare + 4*_idx
- .set _idx, _idx+1
- .endr
-#endif
-
- s32i a0, a3, CS_SA_restore_label // where to return to, to return from function
-#if XCHAL_HAVE_INTERRUPTS || XCHAL_HAVE_EXCEPTIONS
- rsr.epc1 a5
- s32i a5, a3, CS_SA_epc1
- rsr.excsave1 a5
- s32i a5, a3, CS_SA_excsave1
-# ifdef XCHAL_DOUBLEEXC_VECTOR_VADDR
- rsr.depc a5
- s32i a5, a3, CS_SA_depc
-# endif
-#endif
-#if XCHAL_HAVE_WINDOWED
- rsr.windowbase a5
- s32i a5, a3, CS_SA_windowbase // save windowbase
- rsr.windowstart a5
- s32i a5, a3, CS_SA_windowstart // save windowstart
-#endif
- rsr.sar a5
- s32i a5, a3, CS_SA_sar // save sar
-
-#if XCHAL_HAVE_PSO_CDM
- // Save PWRCTL, and update according to flags argument.
- movi a4, XDM_MISC_PWRCTL
- movi a6, PWRCTL_MEM_WAKEUP
- rer a7, a4 // get pwrctl
- s32i a7, a3, CS_SA_pwrctl // save pwrctl
- // Avoid setting power-control bits if not already set, i.e. clear them only.
- bbci.l a2, XTOS_COREF_PSO_SHIFT, 1f // if not shutting off, don't touch power bits
-
- // Set PWRCTL MEM_WAKEUP bit according to flags (whether to let mem power off).
- or a5, a7, a6 // set...
- xor a5, a5, a6 // ... and clear MEM_WAKEUP bit to write
- and a6, a2, a6 // isolate MEM_WAKEUP bit from flags
- or a5, a5, a6 // set MEM_WAKEUP bit to write from flags
- // Clear PWRCTL DEBUG_WAKEUP bit if cleared in flags (if letting debug power off).
- movi a6, ~PWRCTL_DEBUG_WAKEUP
- or a6, a2, a6 // isolate DEBUG_WAKEUP bit from flags
- and a6, a5, a6 // clear it if was clear in flags
- // Update PWRCTL
- wer a6, a4 // write new pwrctl
- //extw // let the new pwrctl value settle
-1:
-#endif
-
- .set _idx, 2
- .rept XCHAL_NUM_INTLEVELS+XCHAL_HAVE_NMI-1
- INDEX_SR rsr.epc a5
- s32i a5, a3, CS_SA_epc + 4*(_idx-2)
- INDEX_SR rsr.eps a5
- s32i a5, a3, CS_SA_eps + 4*(_idx-2)
- INDEX_SR rsr.excsave a5
- s32i a5, a3, CS_SA_excsave + 4*(_idx-2)
- .set _idx, _idx+1
- .endr
-
-#if XCHAL_HAVE_LOOPS
- rsr.lbeg a5
- s32i a5, a3, CS_SA_lbeg
- rsr.lend a5
- s32i a5, a3, CS_SA_lend
- rsr.lcount a5
- s32i a5, a3, CS_SA_lcount
-#endif
-#if XCHAL_HAVE_ABSOLUTE_LITERALS
- rsr.litbase a5
- s32i a5, a3, CS_SA_litbase
-#endif
-#if XCHAL_HAVE_VECBASE
- rsr.vecbase a5
- s32i a5, a3, CS_SA_vecbase
-#endif
-#if XCHAL_HAVE_S32C1I && (XCHAL_HW_MIN_VERSION >= XTENSA_HWVERSION_RC_2009_0) /* have ATOMCTL ? */
- rsr.atomctl a5
- s32i a5, a3, CS_SA_atomctl
-#endif
-#if XCHAL_HAVE_PREFETCH
- movi a5, 0 // disable prefetch during shutoff
- xsr.prefctl a5
- s32i a5, a3, CS_SA_prefctl
-#endif
-#if XCHAL_USE_MEMCTL
- rsr.memctl a5
- s32i a5, a3, CS_SA_memctl
-#endif
-#if XCHAL_HAVE_INTERRUPTS
- rsr.intenable a5
- s32i a5, a3, CS_SA_intenable
-#endif
-#if XCHAL_HAVE_DEBUG
- // NOTE: restore of debug state is conditional,
- // as the power-down and wakeup code might be actively debugged.
- rsr.icount a5
- s32i a5, a3, CS_SA_icount
- rsr.icountlevel a5
- s32i a5, a3, CS_SA_icountlevel
- rsr.debugcause a5
- s32i a5, a3, CS_SA_debugcause // (won't get restored?)
- //rsr.ddr a5
- //s32i a5, a3, CS_SA_ddr
-# if XCHAL_NUM_IBREAK
- rsr.ibreakenable a5
- s32i a5, a3, CS_SA_ibreakenable
-# endif
- .set _idx, 0
- .rept XCHAL_NUM_IBREAK
- INDEX_SR rsr.ibreaka a5
- s32i a5, a3, CS_SA_ibreaka + 4*_idx
- .set _idx, _idx+1
- .endr
- .set _idx, 0
- .rept XCHAL_NUM_DBREAK
- INDEX_SR rsr.dbreakc a5
- s32i a5, a3, CS_SA_dbreakc + 4*_idx
- INDEX_SR rsr.dbreaka a5
- s32i a5, a3, CS_SA_dbreaka + 4*_idx
- .set _idx, _idx+1
- .endr
-#endif
-
- .set _idx, 0
- .rept XCHAL_NUM_MISC_REGS
- INDEX_SR rsr.misc a5
- s32i a5, a3, CS_SA_misc + 4*_idx
- .set _idx, _idx+1
- .endr
-
-#if XCHAL_HAVE_MEM_ECC_PARITY
- rsr.mepc a5
- s32i a5, a3, CS_SA_mepc
- rsr.meps a5
- s32i a5, a3, CS_SA_meps
- rsr.mesave a5
- s32i a5, a3, CS_SA_mesave
- rsr.mesr a5
- s32i a5, a3, CS_SA_mesr
- rsr.mecr a5
- s32i a5, a3, CS_SA_mecr
- rsr.mevaddr a5
- s32i a5, a3, CS_SA_mevaddr
-#endif
-
- /* TIE state */
- addi a4, a3, CS_SA_ncp
- xchal_ncp_store a4, a5,a6,a7,a8 // save non-coprocessor state
-#if XCHAL_HAVE_CP
- rsr.cpenable a5
- s32i a5, a3, CS_SA_cpenable
- movi a6, -1
- wsr.cpenable a6 // enable all coprocessors
- rsync
- xchal_cp0_store a4, a5,a6,a7,a8 continue=1
- xchal_cp1_store a4, a5,a6,a7,a8 continue=1
- xchal_cp2_store a4, a5,a6,a7,a8 continue=1
- xchal_cp3_store a4, a5,a6,a7,a8 continue=1
- xchal_cp4_store a4, a5,a6,a7,a8 continue=1
- xchal_cp5_store a4, a5,a6,a7,a8 continue=1
- xchal_cp6_store a4, a5,a6,a7,a8 continue=1
- xchal_cp7_store a4, a5,a6,a7,a8 continue=1
- //xchal_cp8_store a4, a5,a6,a7,a8 continue=1
- //xchal_cp9_store a4, a5,a6,a7,a8 continue=1
- //xchal_cp10_store a4, a5,a6,a7,a8 continue=1
- //xchal_cp11_store a4, a5,a6,a7,a8 continue=1
- //xchal_cp12_store a4, a5,a6,a7,a8 continue=1
- //xchal_cp13_store a4, a5,a6,a7,a8 continue=1
- //xchal_cp14_store a4, a5,a6,a7,a8 continue=1
- //xchal_cp15_store a4, a5,a6,a7,a8 continue=1
-#endif
-
- /* TLB state (for known MMU types only, not internal custom) */
-#if XCHAL_HAVE_MIMIC_CACHEATTR || XCHAL_HAVE_XLT_CACHEATTR
- addi a4, a3, CS_SA_tlbs // where to start storing TLB entry info
- movi a5, 0x20000000
- movi a6, 0
-1: rdtlb1 a7, a6 // read DTLB entry PPN + CA
- s32i a7, a4, 0
- ritlb1 a7, a6 // read ITLB entry PPN + CA
- s32i a7, a4, 4
- addi a4, a4, 8
- add a6, a6, a5
- bnez a6, 1b
-
-#elif XCHAL_HAVE_PTP_MMU
- // Declare a table of TLB entries to save/restore.
- // Each entry is a 32-bit index to use directly with [rw][di]tlb[01].
- // Indices assume ITLBCFG == DTLBCFG == 0.
- // Bit 4 means not-for-dtlb, and bit 5 means not-for-itlb
- // (these bits aren't used by these instructions, so okay to use for this).
- .section .rodata, "a"
- .global _xtos_pso_tlbmap
- .global _xtos_pso_tlbmap_end
- .type _xtos_pso_tlbmap, @object
-_xtos_pso_tlbmap:
- .long 0x0C0C0C0C, ARF_ENTRIES // *TLB way 0, 4/8 entries of 4KB
- .long 0x0C0C0C0C, ARF_ENTRIES // *TLB way 1, 4/8 entries of 4KB
- .long 0x0C0C0C0C, ARF_ENTRIES // *TLB way 2, 4/8 entries of 4KB
- .long 0x0C0C0C0C, ARF_ENTRIES // *TLB way 3, 4/8 entries of 4KB
- .long 0x1A181614, 4 // *TLB way 4, 4 entries of 1MB/4MB/16MB/64MB
-# if XCHAL_HAVE_SPANNING_WAY /* MMU v3 */
- .long 0x1C1B1C1B, 4 // *TLB way 5, 4 entries of 128MB/256MB
- .long 0x1B1D1B1D, 8 // *TLB way 6, 8 entries of 512MB/128MB
-# endif
- .long 0x0C0C0C0C, 0x8001 // DTLB way 7, 1 entry of 4KB
- .long 0x0C0C0C0C, 0x8001 // DTLB way 8, 1 entry of 4KB
- .long 0x0C0C0C0C, 0x8001 // DTLB way 9, 1 entry of 4KB
-_xtos_pso_tlbmap_end:
- .size _xtos_pso_tlbmap, . - _xtos_pso_tlbmap
-
- .text
- addi a4, a3, CS_SA_tlbs // where to start storing TLB entry info
- movi a10, _xtos_pso_tlbmap
- movi a11, _xtos_pso_tlbmap_end
- rsr.dtlbcfg a14 // page size index (0..3) for each DTLB way
- rsr.itlbcfg a15 // page size index (0..3) for each ITLB way
- s32i a14, a3, CS_SA_dtlbcfg
- s32i a15, a3, CS_SA_itlbcfg
- rsr.ptevaddr a5
- s32i a5, a3, CS_SA_ptevaddr
- rsr.rasid a5
- s32i a5, a3, CS_SA_rasid
- // Loop from last way to first (less register pressure that way).
-.Loop_tlbmap:
- addi a11, a11, -8 // next way
- l32i a8, a11, 0 // map of four (page size log2) per index for this way
- // DTLB page size:
- extui a12, a14, 0, 4 // page size index for this DTLB way
- srli a14, a14, 4 // (for next way)
- ssa8l a12 // prepare to shift right by 8*a12
- srl a12, a8 // page size log2 for this DTLB way
- ssl a12 // prepare to shift left by a12
- movi a12, 1 // (to compute 1 << (page size log2))
- sll a12, a12 // page size for this DTLB way
-
- // Save all entries of this DTLB way:
- l32i a9, a11, 4 // number of entries for this way
- sub a5, a11, a10 // way number * 8
- srli a5, a5, 3 // way number
- extui a9, a9, 0, 8
-1: rdtlb0 a6, a5 // read DTLB entry VPN + ASID ...
- rdtlb1 a7, a5 // read DTLB entry PPN + CA ...
- add a5, a5, a12 // next entry of this DTLB way
- s32i a6, a4, 0 // save entry ...
- s32i a7, a4, 4
- addi a4, a4, 8
- addi a9, a9, -1
- bnez a9, 1b
-
- // ITLB page size:
- extui a12, a15, 0, 4 // page size index for this ITLB way
- srli a15, a15, 4 // (for next way)
- ssa8l a12 // prepare to shift right by 8*a12
- srl a12, a8 // page size log2 for this ITLB way
- ssl a12 // prepare to shift left by a12
- movi a12, 1 // (to compute 1 << (page size log2))
- sll a12, a12 // page size for this ITLB way
-
- // Save all entries of this ITLB way:
- l32i a9, a11, 4 // number of entries for this way
- sub a5, a11, a10 // way number * 8
- srli a5, a5, 3 // way number
- bbsi.l a9, 15, 2f // skip ITLB if is a DTLB-only way
- extui a9, a9, 0, 8
-1: ritlb0 a6, a5 // read ITLB entry VPN + ASID ...
- ritlb1 a7, a5 // read ITLB entry PPN + CA ...
- add a5, a5, a12 // next entry of this ITLB way
- s32i a6, a4, 0 // save entry ...
- s32i a7, a4, 4
- addi a4, a4, 8
- addi a9, a9, -1
- bnez a9, 1b
-2:
- bne a11, a10, .Loop_tlbmap // loop for next TLB way
- // Done saving TLBs.
-#endif
-
-#if XCHAL_HAVE_CACHE_BLOCKOPS
- pfwait.a // wait for any remaining block-prefetch ops
-#endif
-
-#if XCHAL_HAVE_MPU
- addi a4, a3, CS_SA_mpuentry // location for MPU save
- mpu_read_map a4, a5, a6
- rsr.cacheadrdis a4
- addi a5, a3, CS_SA_cacheadrdis
- s32i a4, a5, 0
-
-#if XCHAL_DCACHE_IS_WRITEBACK
- // Must write this piece back to memory, because if it stays
- // in the cache and we try to restore with caches bypassed,
- // the wrong values will be fetched from memory.
- // TODO: See if possible to replace with call to xthal_dcache_region_writeback
- // TODO: If going to write back full dcache below, skip this step
- addi a4, a3, CS_SA_mpuentry
- movi a5, CS_SA_ncp - CS_SA_mpuentry
- dcache_writeback_region a4, a5, a7, a8
-#endif
-#endif
-
- // With data cache coherency enabled, need a full data cache
- // writeback and invalidate, then disable coherency, before shut-off.
- // Otherwise, if we'll let dcache power off, writeback its contents.
- //
- // We make sure the signature only gets written after everything
- // else is written back (if we writeback), and only gets written
- // back if the rest gets written back.
- movi a6, CORE_STATE_SIGNATURE
-#if XCHAL_DCACHE_IS_WRITEBACK
-# if XCHAL_HAVE_PSO_CDM && XCHAL_DCACHE_IS_COHERENT && XCHAL_HW_MIN_VERSION >= XTENSA_HWVERSION_RE_2012_0
- rsr.memctl a4
- bbci.l a2, XTOS_COREF_PSO_SHIFT, 1f // if not shutting off, leave snoops as is
- bbci.l a4, MEMCTL_SNOOP_EN_SHIFT, 1f // snoops (coherence) enabled?
- dcache_writeback_inv_all a4, a5, a7, 0 // yes: writeback-invalidate
- memw // wait for writeback to complete
- s32i a6, a3, CS_SA_signature
- dhwbi a3, CS_SA_signature
- // Now that dcache is empty, make sure snoops are off during shut-off.
- addi a4, a4, -MEMCTL_SNOOP_EN
- wsr.memctl a4
- j 9f
-1:
-# endif
- bbsi.l a2, PWRCTL_MEM_WAKEUP_SHIFT, 7f // letting caches power off?
- dcache_writeback_all a4, a5, a7, 0 // yes: writeback
- memw // wait for writeback to complete
- j 8f
-
- // The signature and the cache/TLB state must be written out to
- // main memory even though the caches stay on, because on restart
- // we will come up with caches bypassed and need to read the state
- // back before the cache/TLB is set up.
-7:
- mov a4, a3
- movi a5, CS_SA_ncp
- dcache_writeback_region a4, a5, a7, a8
- memw
-8:
- s32i a6, a3, CS_SA_signature
- dhwb a3, CS_SA_signature // needed even if caches stay on
-#else
- s32i a6, a3, CS_SA_signature
-#endif
-
-9: l32i a4, a3, CS_SA_areg + 4*4 // restore a4 (code to jump to after saving)
- memw // wait for signature to be in memory
-
- beqz a4, 1f // code to jump to?
- jx a4 // yes, jump to it
-1: l32i a0, a3, CS_SA_restore_label // no, return: restore return PC
- movi a2, 0 // return 0
- ret
-
-
- .size _xtos_core_save, . - _xtos_core_save
-
diff --git a/src/arch/xtensa/smp/xtos/core-shutoff.S b/src/arch/xtensa/smp/xtos/core-shutoff.S
deleted file mode 100644
index c848e38..0000000
--- a/src/arch/xtensa/smp/xtos/core-shutoff.S
+++ /dev/null
@@ -1,425 +0,0 @@
-// reset-pso.S -- PSO restore routine, invoked from Reset Vector
-// $Id: //depot/rel/Foxhill/dot.8/Xtensa/OS/xtos/core-shutoff.S#1 $
-
-// Copyright (c) 2012-2013 Tensilica Inc.
-//
-// Permission is hereby granted, free of charge, to any person obtaining
-// a copy of this software and associated documentation files (the
-// "Software"), to deal in the Software without restriction, including
-// without limitation the rights to use, copy, modify, merge, publish,
-// distribute, sublicense, and/or sell copies of the Software, and to
-// permit persons to whom the Software is furnished to do so, subject to
-// the following conditions:
-//
-// The above copyright notice and this permission notice shall be included
-// in all copies or substantial portions of the Software.
-//
-// THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
-// EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
-// MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
-// IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY
-// CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
-// TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
-// SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
-
-#include <xtensa/coreasm.h>
-#include <xtensa/corebits.h>
-#include <xtensa/cacheasm.h>
-#include <xtensa/cacheattrasm.h>
-#include <xtensa/xdm-regs.h>
-#include <xtensa/xtruntime-core-state.h>
-#include "xtos-internal.h"
-
-#if XCHAL_HAVE_PSO
- .macro simulate_reset
- // Single or multiple power domains, no retention.
- // Just simulate reset. Set PS:
- movi a5, 0x1F
- wsr.ps a5
- rsync
- // Scramble things:
- rotw 3
- // Jump to reset vector:
- movi a5, _ResetVector
- jx a5
- .endm
-#endif
-
-
-#if XCHAL_HAVE_PSO_CDM && ! XCHAL_HAVE_PSO_FULL_RETENTION
- // PSO: core state save area.
- // This could be pretty large (includes TIE state, TLB state, many regs).
- //
- .section .bss, "aw"
- .align XCHAL_TOTAL_SA_ALIGN
- .global _xtos_pso_savearea
- .type _xtos_pso_savearea, @object
- .size _xtos_pso_savearea, XtosCoreStateSize
-_xtos_pso_savearea:
- .space XtosCoreStateSize
-#endif
-
-
- .text
-
-
- // This version of the _xtos_core_shutoff() function can be called from assembly-level,
- // where the stack might not be defined/usable, so can't do window-spill
- // etc. This saves address registers per call0 ABI (all except a0/a2..a11).
- //
- // On entry: a0 = return PC, a2 = flags argument, a3..a11 = undefined/available.
- // All other registers are saved/restored.
- //
- .align 4
- .global _xtos_core_shutoff_nw
- .type _xtos_core_shutoff_nw,@function
-_xtos_core_shutoff_nw:
-#if XCHAL_HAVE_PSO_CDM && ! XCHAL_HAVE_PSO_FULL_RETENTION
- movi a5, _xtos_core_save_nw
-#endif
- mov a11, a0 // ABI-independent return PC
- j .Lcommon_shutoff
- .size _xtos_core_shutoff_nw, . - _xtos_core_shutoff_nw
-
-
-
- // int _xtos_core_shutoff(unsigned flags)
- //
- // Save all processor state and shut-off the core.
- // Returns when the core wakes up, and all state was restored
- // (except in single power domain case, see below).
- //
- // For more details see: System SW Ref Manual, XTOS Chapter.
- //
- // Possible return values:
- //
- // 0 core did shut-off (return via reset vector,
- // or after waiti for full-retention case)
- //
- // 1,2 core did not shut-off (other requestors were already
- // requesting this core to stay on at time of call)
- // (1 == early, 2 == late)
- //
- // 3 core did not shut-off (multi-power-domains no retention,
- // and waiti resumed; FIXME: can this happen?)
- //
- // -1 core does not have PSO feature
- //
- // NOTE: in the single power domain case, this function never returns.
- // The external system must power the core off than back on,
- // and execution resumes at the reset vector.
- //
- // The flags parameter indicates whether to request memory and/or debug domains
- // to stay powered on while the core is shut-off. (This parameter is ignored
- // for the single power domain case.) If 0, they are both allowed to
- // shut-off (although other external requesters may keep them powered on).
- // Otherwise, one or both of these bits may be specified (or'ed together):
- // XTOS_KEEPON_MEM force memory domain on during core power shut-off
- // XTOS_KEEPON_DEBUG force debug domain on during core power shut-off
- // If XTOS_KEEPON_MEM is specified, dcache writeback is NOT done.
- //
- // Effectively, the flags parameter sets the value of these two PWRCTL register
- // bits (over ERI) during core power shut-off. The value of these two bits
- // (as they were prior to calling this function) are saved, and restored on wakeup.
- // Thus, if the core was requesting that the debug domain be powered on, and
- // _xtos_core_shutoff() lets it power-off, then upon wakeup, the software restore
- // sequence restores debug domain power, and waits for debug power to be ON.
- //
- //
- .align 4
- .global _xtos_core_shutoff
- .type _xtos_core_shutoff,@function
-_xtos_core_shutoff:
- abi_entry
-
-#if XCHAL_HAVE_PSO_CDM && ! XCHAL_HAVE_PSO_FULL_RETENTION
- movi a5, _xtos_core_save_entry
-#endif
- movi a11, 1f // ABI-independent return PC
- j .Lcommon_shutoff
-
-1: abi_return
-
-
-
-
- .align 4
-.Lcommon_shutoff:
-
-
-
-#if XCHAL_HAVE_PSO_CDM && XCHAL_HAVE_PSO_FULL_RETENTION
- // Multiple power domains, full retention in HW.
- // Do the minimum required (things that need to be changed during shutoff):
-
- // Check whether other agents are keeping this core powered on,
- // and avoid going through save sequence if we're not going to
- // power down anyway.
- movi a3, XDM_MISC_PWRSTAT
- rer a6, a3
- movi a5, 1 // indicates other agents want this core powered on
- bbsi.l a6, PWRSTAT_CORE_STILL_NEEDED_SHIFT, 1f
-
- rsil a8, 15 // disable interrupts
-
-# if XCHAL_HAVE_PREFETCH
- // Save prefetch control and disable prefetch.
- movi a10, 0
- xsr.prefctl a10
-# endif
-
-# if XCHAL_DCACHE_IS_WRITEBACK
- bbsi.l a2, PWRCTL_MEM_WAKEUP_SHIFT, 7f // letting caches power off?
- dcache_writeback_all a4, a7, a9,0 // yes: writeback
- memw // wait for writeback to complete
-7:
-# endif
-
- // Save PWRCTL, and set ShutProcOffOnPWait (for WAITI to shut-off the core).
- // (With dcache coherence, can this be used as signal to system
- // to turn off snoops to this core?)
- //
- movi a4, XDM_MISC_PWRCTL
- rer a9, a4 // get pwrctl
- movi a6, PWRCTL_CORE_SHUTOFF // aka ShutProcOffOnPWait
- or a7, a9, a6 // indicate WAITI will shut-off
- xor a9, a7, a6 // make sure it's clear in saved pwrctl
- wer a7, a4 // write new pwrctl
-
- // Make sure everything stabilizes:
- isync
- extw
-
- // With ShutProcOffOnPWait set, external agents can't change their mind.
- // So check again whether other agents are keeping this core powered on,
- // and avoid going through save sequence if we're not going to
- // power down anyway.
- rer a6, a3 // read PWRSTAT
- movi a5, 2 // if abort: external agent wants core powered on
- bbsi.l a6, PWRSTAT_CORE_STILL_NEEDED_SHIFT, .Lshutoff_late_abort
-
- // Set PWRCTL MEM_WAKEUP bit according to flags (whether to let mem power off).
- movi a6, PWRCTL_MEM_WAKEUP
- or a5, a7, a6 // set...
- xor a5, a5, a6 // ... and clear MEM_WAKEUP bit to write
- and a6, a2, a6 // isolate MEM_WAKEUP bit from flags
- or a5, a5, a6 // set MEM_WAKEUP bit to write from flags
- // Clear PWRCTL DEBUG_WAKEUP bit if cleared in flags (if letting debug power off).
- movi a6, ~PWRCTL_DEBUG_WAKEUP
- or a6, a2, a6 // isolate DEBUG_WAKEUP bit from flags
- and a6, a5, a6 // clear it if was clear in flags
- // Update PWRCTL
- wer a6, a4 // write new pwrctl
- extw // let the new pwrctl value settle
-
- // Okay, go for it -- power down (shutoff).
-
-# if !XTOS_PSO_TEST
- waiti 0 // now shut-off! (interrupts enabled for power-on)
-# endif
- // Resumes here after power comes back on, after some interrupt taken.
- wsr.ps a8 // restore interrupts
- movi a5, 0 // successful
- rsync // ensure wsr.ps completes
-
- // FIXME: do we need to initialize caches?
-
-.Lshutoff_late_abort:
- wer a7, a4 // restore pwrctl (except ShutProcOffOnPWait still set)
-
- // Wait for debug powerup to complete (if started):
- bbci.l a7, PWRCTL_DEBUG_WAKEUP_SHIFT, 3f
- movi a6, XDM_MISC_PWRSTAT
-2: rer a6, a6 // read PWRSTAT
- bbci.l a6, PWRSTAT_DEBUG_DOMAIN_ON_SHIFT, 2b // loop until powered up
-3:
-
-# if XCHAL_HAVE_PREFETCH
- wsr.prefctl a10 // restore prefetch control
-# endif
-
- // If CachesLostPower bit set, is there need to initialize caches?
-
- wer a9, a4 // clear ShutProcOffOnPWait
-
- wsr.ps a8 // restore interrupts
- rsync // ensure wsr.ps completes
-
-1: mov a2, a5
- jx a11 // return (to ABI-dependent code if C callable)
-
-
-
-#elif XCHAL_HAVE_PSO_CDM /*&& !XCHAL_HAVE_PSO_FULL_RETENTION*/
- // Multiple power domains, no hardware retention.
- // Do full core state save/restore in software.
-
- // Check whether other agents are keeping this core powered on,
- // and avoid going through save sequence if we're not going to
- // power down anyway.
- movi a3, XDM_MISC_PWRSTAT
- rer a3, a3
- bbsi.l a3, PWRSTAT_CORE_STILL_NEEDED_SHIFT, 1f
-
- movi a3, XTOS_COREF_PSO
- or a2, a2, a3 // indicate power shutoff in flags
-
- movi a3, _xtos_pso_savearea
- movi a4, _xtos_core_shutoff_aftersave
- jx a5 // continue in _xtos_core_save (past prologue)
- // which saves processor state, powers down
- // debug/mem per a2, shuts off prefetch and
- // snooping, and jumps to a4
-
-1: movi a2, 1 // other agents want this core powered on
- jx a11 // return (to ABI-dependent code if C callable)
-
- .align 4
- //.global _xtos_core_shutoff_aftersave
-_xtos_core_shutoff_aftersave:
-
- // Multiple power domains, no retention.
-
- // Set ShutProcOffOnPWait, for WAITI to shut-off the core.
- // (With dcache coherence, can this be used as signal to system
- // to turn off snoops to this core?)
- //
- movi a4, XDM_MISC_PWRCTL
- rer a7, a4 // get pwrctl
- movi a6, PWRCTL_CORE_SHUTOFF // aka ShutProcOffOnPWait
- or a7, a7, a6 // indicate WAITI will shut-off
- wer a7, a4 // write new pwrctl
-
- // Make sure everything stabilizes:
- isync
- extw
-
- // Check whether other agents are keeping this core powered on,
- // and avoid going through save sequence if we're not going to
- // power down anyway.
- movi a4, XDM_MISC_PWRSTAT
- movi a2, 2 // if abort: external agent wants core powered on
- rer a6, a4
- bbsi.l a6, PWRSTAT_CORE_STILL_NEEDED_SHIFT, .Lshutoff_late_abort
-
- // Call system-specific function to wait for system specific
- // transactions to quiesce before shutting down the processor.
- // This function may also abort the shutdown, however whoever
- // attempts it must do it carefully: the function must know
- // that it's possible to abort, it must do whatever's needed
- // in the system to resume normal execution (e.g. restart
- // snoops, DMA, etc), and for power reasons the software must
- // avoid calling this shutdown routine in the first place if
- // it can know then that it would end up aborting here.
- //
- // This is always a call0 function.
- // TBD: can it be a C function instead?
- // TBD: describe exact calling conventions, if asm call0
-
- .weak xtos_system_ready_for_core_shutoff
- movi a2, xtos_system_ready_for_core_shutoff
- //isync
- beqz a2, 1f
- callx0 a2
- bnez a2, .Lshutoff_late_abort // if function returns error, abort shutdown
-1:
-
- // Okay, go for it -- power down (shutoff).
-
-
-# if XTOS_PSO_TEST
- // Test only -- weakly simulate shutoff in sw, don't actually do it.
- simulate_reset
-# elif XCHAL_HAVE_INTERRUPTS
- waiti 15 // now shut-off!
-# elif XCHAL_HAVE_HALT
- halt
-# else
-# error "PSO assumes interrupts (for WAITI) or HALT architecture (for HALT)"
-# endif
-
- // Execution should not proceed here.
- // If we get here, some error has occurred [FIXME]
-
- movi a2, 3 // WAITI resumed
-
-.Lshutoff_late_abort:
- // We end up here if returning from shutoff request.
- // Here, a2 == return code.
- // Restore what's been clobbered (and doesn't get restored by caller):
- // PWRCTL, MEMCTL, return PC.
-
- l32i a0, a3, CS_SA_restore_label // restore return PC
-
- // Restore PWRCTL.
- movi a4, XDM_MISC_PWRCTL
- l32i a5, a3, CS_SA_pwrctl // get saved pwrctl
- wer a5, a4 // restore pwrctl
- // Wait for debug powerup to complete (if started):
- bbci.l a5, PWRCTL_DEBUG_WAKEUP_SHIFT, 1f
- movi a7, XDM_MISC_PWRSTAT
-2: rer a6, a7 // read PWRSTAT
- bbci.l a6, PWRSTAT_DEBUG_DOMAIN_ON_SHIFT, 2b // loop until powered up
-1:
-
- // Restore MEMCTL.
-# if XCHAL_USE_MEMCTL
- l32i a5, a3, CS_SA_memctl
- wsr.memctl a5
-# endif
-
- // Clear the signature, to mark save area as no longer valid.
- s32i a2, a3, CS_SA_signature
-# if XCHAL_DCACHE_IS_WRITEBACK
- dhwb a3, CS_SA_signature
-# endif
-
- ret // return from _xtos_core_save_common
-
-
-
-#elif XCHAL_HAVE_PSO
- // Single power domain. (No retention.)
-
- rsil a8, 15 // disable interrupts
-
-# if XCHAL_HAVE_PREFETCH
- // Disable prefetch.
- movi a10, 0
- wsr.memctl a10
-# endif
-
-# if XCHAL_DCACHE_IS_WRITEBACK
- bbsi.l a2, PWRCTL_MEM_WAKEUP_SHIFT, 7f // letting caches power off?
- dcache_writeback_all a4, a5, a6, 0 // yes: writeback
- memw // wait for writeback to complete
-7:
-# endif
-
-1: waiti 15 // wait for shut-off
- j 1b // loop until we get powered off
-
-
-
-#else
- // No PSO.
- movi a2, -1
- jx a11 // return (to ABI-dependent code if C callable)
-
-#endif
-
-
-
-
-#if XCHAL_HAVE_PSO_CDM
-# if XCHAL_HAVE_PSO_FULL_RETENTION
-
-# else /* not full retention */
-
-
-# endif /* !retention */
-#endif /* multi power domains */
-
-
- .size _xtos_core_shutoff, . - _xtos_core_shutoff
-
diff --git a/src/arch/xtensa/smp/xtos/crt0-app.S b/src/arch/xtensa/smp/xtos/crt0-app.S
deleted file mode 100644
index 7f12337..0000000
--- a/src/arch/xtensa/smp/xtos/crt0-app.S
+++ /dev/null
@@ -1,174 +0,0 @@
-// crt0-app.S
-// Applications downloaded in RAM using a debug monitor (eg. XMON, RedBoot)
-// start here at _app_reset. Such applications don't have any vectors:
-// all exceptions are handled by the debug monitor.
-// Thus, this file essentially plays the role of the reset vector
-// to setup a few things before jumping to _start (in crt1*.S).
-
-// Copyright (c) 2005-2013 Tensilica Inc.
-//
-// Permission is hereby granted, free of charge, to any person obtaining
-// a copy of this software and associated documentation files (the
-// "Software"), to deal in the Software without restriction, including
-// without limitation the rights to use, copy, modify, merge, publish,
-// distribute, sublicense, and/or sell copies of the Software, and to
-// permit persons to whom the Software is furnished to do so, subject to
-// the following conditions:
-//
-// The above copyright notice and this permission notice shall be included
-// in all copies or substantial portions of the Software.
-//
-// THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
-// EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
-// MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
-// IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY
-// CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
-// TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
-// SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
-
-#include <xtensa/cacheattrasm.h>
-#include <xtensa/coreasm.h>
-
-
-// Assumptions on entry to _app_reset:
-// - debug monitor handles all exceptions, has setup all vectors
-// - interrupt related state is initialized
-// (interrupts disabled or enabled for debug monitor's purposes)
-// - debug option related state is initialized (for debug monitor)
-// - any MMU related state is initialized (all handled by debug monitor)
-// - caches are initialized (cache attributes not necessarily correct)
-// - entire application is loaded (no unpacking needed here)
-
-// Assumptions on exit from _app_reset, ie. when jumping to _start:
-// - low (level-one) and medium priority interrupts are disabled
-// - C calling context not initialized:
-// - PS not fully initialized (eg. PS.WOE not set per ABI)
-// - SP not initialized
-// - the following are initialized:
-// - LITBASE, WindowBase, WindowStart, LCOUNT, CPENABLE, FP's FCR and FSR,
-// cache attributes
-
-/**************************************************************************/
-
- .text
- .global _app_reset
-_app_reset:
- /* _app_reset may be required to be located at the beginning of the text
- segment. However, the constant pool for _app_reset must be placed
- before the code. Jump over the constant pool to solve this. */
- j .LpastInitialConstants
-
- .literal_position // tells the assembler/linker to place literals here
-
-.LpastInitialConstants:
- // Keep a0 zero. It is used to initialize a few things.
- // It is also the return address, where zero indicates
- // that the frame used by _start is the bottommost frame.
- //
- movi a0, 0 // keep this register zero.
-
-#if XCHAL_HAVE_LOOPS
- wsr.lcount a0 // loop count = 0
-#endif /* XCHAL_HAVE_LOOPS */
-
- // Interrupts might be enabled, make sure at least medium and low priority
- // interrupts are disabled until WindowBase, WindowStart, SP, and the stack
- // are all properly setup (which will happen outside this file, after the
- // _start label). We leave loops enabled on new exception architecture.
-#if XCHAL_HAVE_EXCEPTIONS
- movi a2, XCHAL_EXCM_LEVEL
- wsr.ps a2 // set PS.INTLEVEL=EXCM_LEVEL, PS.WOE=0, PS.EXCM=0
- rsync
-#endif
-
- // DO THIS FIRST: initialize the window start and base
- // before, so that windows don't move under us.
-#if XCHAL_HAVE_WINDOWED
- // We do this even if we are assembling for the
- // call0 abi, but it's not really needed.
- movi a2, 1
- wsr.windowstart a2 // window start = 1
- wsr.windowbase a0 // window base = 0
- rsync
-
- // NOTE: a0 may no longer be zero here, because
- // we wrote to WindowBase. So clear it again.
- movi a0, 0
-#endif
-
- // Now, BEFORE we do any L32R (or MOVI with non-immediate
- // range which results in an L32R), ensure LITBASE is set
- // correctly. This is necessary for RAM applications loaded
- // using a target-side debug monitor -- such applications
- // don't have a reset vector and start execution at _start.
- // (This part is unnecessary if running from a reset vector.)
- // The target-side debug monitor might have set LITBASE to
- // anything at all, so we cannot rely on its value here.
-#if XCHAL_HAVE_ABSOLUTE_LITERALS
- wsr.litbase a0 // force PC-relative L32R
- rsync
-# if XSHAL_USE_ABSOLUTE_LITERALS
- .begin no-absolute-literals // use PC-rel L32R to load
- movi a2, _lit4_start + 0x40001 // address of absolute literals
- .end no-absolute-literals // (see handlers/ResetVector.S
- wsr.litbase a2 // for explanation)
- rsync
-# endif
-#endif
-
-
- /*
- * Now "enable" the caches.
- *
- * NOTE: We don't *initialize* the caches here, because the loader
- * (eg. target debugger agent / debug monitor, boot code, etc)
- * is expected to have initialized them for us.
- *
- * The _memmap_cacheattr_reset symbol's value (address) is defined
- * by the LSP's linker script, as generated by xt-genldscripts.
- *
- * (NOTE: for configs that don't have CACHEATTR or region protection,
- * ie. for full MMUs, there is no equivalent cache attribute layout,
- * and the following code has no effect. We assume for now that the
- * application restricts itself to the static TLB entries, i.e. to
- * virtual addresses 0xD0000000 thru 0xFFFFFFFF.)
- */
-#if XCHAL_HAVE_CACHEATTR || XCHAL_HAVE_MIMIC_CACHEATTR || XCHAL_HAVE_XLT_CACHEATTR \
- || (XCHAL_HAVE_PTP_MMU && XCHAL_HAVE_SPANNING_WAY)
- movi a2, _memmap_cacheattr_reset /* note: absolute symbol, not a ptr */
- cacheattr_set /* set CACHEATTR from a2 (clobbers a3-a8) */
-#endif
-
-
-
- // Coprocessor option initialization
-#if XCHAL_HAVE_CP
- //movi a2, XCHAL_CP_MASK // enable existing CPs
- // To allow creating new coprocessors using TC that are not known
- // at GUI build time without having to explicitly enable them,
- // all CPENABLE bits must be set, even though they may not always
- // correspond to a coprocessor.
- movi a2, 0xFF // enable *all* bits, to allow dynamic TIE
- wsr.cpenable a2
-#endif
-
- // Floating point coprocessor option initialization
-#if XCHAL_HAVE_FP
- rsync /* wait for WSR to CPENABLE to complete before accessing FP coproc state */
- wur.fcr a0 /* clear FCR (default rounding mode, round-nearest) */
- wur.fsr a0 /* clear FSR */
-#endif
-
-
- /* NOTE: Future releases may clear BSS here rather than in the CRT1. */
-
-
- /*
- * Now jump to the application. This is typically the
- * C run-time initialization ("CRT") which in turn calls main():
- */
- movi a4, _start
- jx a4 // jump to _start
-
- .size _app_reset, . - _app_reset
-
diff --git a/src/arch/xtensa/smp/xtos/crt1-boards.S b/src/arch/xtensa/smp/xtos/crt1-boards.S
deleted file mode 100644
index 5ead4b1..0000000
--- a/src/arch/xtensa/smp/xtos/crt1-boards.S
+++ /dev/null
@@ -1,275 +0,0 @@
-// crt1-boards.S
-//
-// For most hardware / boards, this code sets up the C calling context
-// (setting up stack, PS, and clearing BSS) and jumps to __clibrary_start
-// which sets up the C library, calls constructors and registers destructors,
-// and calls main().
-//
-// Control arrives here at _start from the reset vector or from crt0-app.S.
-
-// Copyright (c) 1998-2017 Cadence Design Systems, Inc.
-//
-// Permission is hereby granted, free of charge, to any person obtaining
-// a copy of this software and associated documentation files (the
-// "Software"), to deal in the Software without restriction, including
-// without limitation the rights to use, copy, modify, merge, publish,
-// distribute, sublicense, and/or sell copies of the Software, and to
-// permit persons to whom the Software is furnished to do so, subject to
-// the following conditions:
-//
-// The above copyright notice and this permission notice shall be included
-// in all copies or substantial portions of the Software.
-//
-// THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
-// EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
-// MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
-// IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY
-// CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
-// TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
-// SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
-
-#include <xtensa/cacheasm.h>
-#include <xtensa/coreasm.h>
-#include "xtos-internal.h"
-#include <config.h>
-
-
-// Exports
-.global _start
-
-// Imports
-// __clibrary_init from C library (eg. newlib or uclibc)
-// exit from C library
-// main from user application
-// board_init board-specific (uart/mingloss/tinygloss.c)
-// xthal_dcache_all_writeback from HAL library
-// __stack from linker script (see LSP Ref Manual)
-// _bss_table_start from linker script (see LSP Ref Manual)
-// _bss_table_end from linker script (see LSP Ref Manual)
-
-.type main, @function
-
-.type master_core_data, @object
-.type core_data_ptr, @object
-
-// Macros to abstract away ABI differences
-
-#if __XTENSA_CALL0_ABI__
-# define CALL call0
-# define CALLX callx0
-#else
-# define CALL call4
-# define CALLX callx4
-#endif
-
-/**************************************************************************/
- .macro generate_stack_for_idle core_id
- .if GREATERTHAN(PLATFORM_CORE_COUNT, \core_id)
- .section .bss, "aw"
- .align XTOS_IDLE_STACK_SIZE
- .if EQUAL(0, \core_id)
- .global _stack_start
-_stack_start:
- .endif
- .global _stack_start&core_id
-_stack_start&core_id:
- .space XTOS_IDLE_STACK_SIZE
- .endif
- .endm
-
- generate_stack_for_idle 0
- generate_stack_for_idle 1
- generate_stack_for_idle 2
- generate_stack_for_idle 3
-
- .text
- .align 4
-_start:
- // each core unpacks xtos structures for itself
- // nevertheless core 0 initializes shared xtosstruct
- get_prid a5
-#if PLATFORM_MASTER_CORE_ID == 0
- bnez a5, xtos_per_core
-#else
- movi a4, PLATFORM_MASTER_CORE_ID
- bne a5, a4, xtos_per_core
-#endif
-
- // _start is typically NOT at the beginning of the text segment --
- // it is always called from either the reset vector or other code
- // that does equivalent initialization (such as crt0-app.S).
- //
- // Assumptions on entry to _start:
- // - low (level-one) and medium priority interrupts are disabled
- // via PS.INTLEVEL and/or INTENABLE (PS.INTLEVEL is expected to
- // be zeroed, to potentially enable them, before calling main)
- // - C calling context not initialized:
- // - PS not initialized
- // - SP not initialized
- // - the following are initialized:
- // - LITBASE, cache attributes, WindowBase, WindowStart,
- // CPENABLE, FP's FCR and FSR, EXCSAVE[n]
-
- // Keep a0 zero. It is used to initialize a few things.
- // It is also the return address, where zero indicates
- // that the frame used by _start is the bottommost frame.
- //
-#if !XCHAL_HAVE_HALT || !XCHAL_HAVE_BOOTLOADER // not needed for Xtensa TX
- movi a0, 0 // keep this register zero.
-#endif
-
-#if XTOS_RESET_UNNEEDED && !XCHAL_HAVE_HALT
-#include "reset-unneeded.S"
-#endif
-
- // Init xtos struct ptr
- movi a2, master_core_data
- movi a3, core_data_ptr
- s32i a2, a3, 0
-
- // Initialize the stack pointer.
- // See the "ABI and Software Conventions" chapter in the
- // Xtensa ISA Reference manual for details.
-
- // NOTE: Because the _start routine does not use any memory in its
- // stack frame, and because all of its CALL instructions use a
- // window size of 4 (or zero), the stack frame for _start can be empty.
-
-// Common xtos structures used by all cores.
-xtos_common:
- // Unpack xtos_exc_handler_table from rodata.
- movi a6, xtos_exc_handler_table
- movi a9, xtos_exc_handler_table_r
- movi a13, XCHAL_EXCCAUSE_NUM*4
-xtos_exc_handler_table_loop:
- l32i a12, a9, 0
- s32i a12, a6, 0
- addi a13, a13, -4
- addi a6, a6, 4
- addi a9, a9, 4
- bnez a13, xtos_exc_handler_table_loop
-
-// Xtos structures initialized per core from rodata.
-xtos_per_core:
-#if CONFIG_BOOT_LOADER
- .weak _Level2FromVector
- .weak _Level3FromVector
- .weak _Level4FromVector
- .weak _Level5FromVector
-
- movi a4, _Level2FromVector
- writesr excsave 2 a4
- movi a4, _Level3FromVector
- writesr excsave 3 a4
- movi a4, _Level4FromVector
- writesr excsave 4 a4
- movi a4, _Level5FromVector
- writesr excsave 5 a4
-#endif
-
-// Obtain core structs from given address.
-xtos_per_core_obtain_xtos_structs:
- get_prid a5
- movi a2, 4
- mull a2, a2, a5
- movi a3, core_data_ptr
- add a3, a3, a2
- l32i a3, a3, 0
-
-xtos_per_core_init_intstruct:
- movi a2, 0
- s32i a2, a3, 0
- movi a2, 0xFFFFFFFF
- s32i a2, a3, 4
- addi a3, a3, XTOS_INTSTRUCT_SIZE_PER_CORE
-
-xtos_per_core_init_interrupt_table:
- // Setup iterator.
- movi a6, XCHAL_NUM_INTERRUPTS
-
- // Setup init constants.
- movi a2, xtos_unhandled_interrupt
-
- 1:
- addi a6, a6, -1
- s32i a2, a3, 0
- s32i a6, a3, 4
- // Int handler size should be 8.
- addi a3, a3, 8
- bnez a6, 1b
-
-xtos_per_core_init_interrupt_mask:
- movi a6, XCHAL_NUM_INTERRUPTS
- movi a5, ~XCHAL_LOWPRI_MASK
- movi a7, -2
-
- 2:
- // i <==> a6
- addi a6, a6, -1
- // a4 := 1 << i
- movi a4, 1
- ssl a6
- sll a4, a4
- // a2 := (-2 * (1 << i) - 1) | ~XCHAL_LOWPRI_MASK
- mull a2, a4, a7
- addi a2, a2, -1
- or a2, a2, a5
-
- s32i a2, a3, 0
- s32i a4, a3, 4
- // Int handler size should be 8.
- addi a3, a3, 8
- addi a4, a4, 1
- bnez a6, 2b
-
- // Assign stack ptr before PS is initialized to avoid any debugger
- // side effects and prevent from double exception.
- xtos_stack_addr_percore_basic sp, a3, _stack_start, XTOS_IDLE_STACK_SIZE
-
- /*
- * Now that sp (a1) is set, we can set PS as per the application
- * (user vector mode, enable interrupts, enable window exceptions if applicable).
- */
-#if XCHAL_HAVE_EXCEPTIONS
- movi a3, PS_UM|PS_WOE_ABI // PS.WOE = 0|1, PS.UM = 1, PS.EXCM = 0, PS.INTLEVEL = 0
- wsr.ps a3
- rsync
-#endif
-
- /*
- * Do any initialization that affects the memory map, such as
- * setting up TLB entries, that needs to be done before we can
- * successfully clear BSS (e.g. if some BSS segments are in
- * remapped areas).
- *
- * NOTE: This hook works where the reset vector does not unpack
- * segments (see "ROM packing" in the LSP manual), or where
- * unpacking of segments is not affected by memory remapping.
- * If ROM unpacking is affected, TLB setup must be done in
- * assembler from the reset vector.
- *
- * The __memmap_init() routine can be a C function, however it
- * does not have BSS initialized! In particular, __memmap_init()
- * cannot set BSS variables, i.e. uninitialized global variables
- * (they'll be wiped out by the following BSS clear), nor can it
- * assume they are yet initialized to zero.
- *
- * The __memmap_init() function is optional. It is marked as a
- * weak symbol, so that it gets valued zero if not defined.
- */
- .weak __memmap_init
- movi a4, __memmap_init
- beqz a4, 1f
- CALLX a4
-1:
-
- // Call: int main(int argc, char ** argv, char ** environ);
- CALL main
- // Does not return here.
-
- .data
- // Mark argc/argv/envp parameters as weak so that an external
- // object file can override them.
- .text
-
- .size _start, . - _start
diff --git a/src/arch/xtensa/smp/xtos/crt1-sim.S b/src/arch/xtensa/smp/xtos/crt1-sim.S
deleted file mode 100644
index 9068792..0000000
--- a/src/arch/xtensa/smp/xtos/crt1-sim.S
+++ /dev/null
@@ -1,290 +0,0 @@
-// crt1-sim.S
-// For the Xtensa simulator target, this code sets up the C calling context
-// and calls main() (via __clibrary_start).
-// Control arrives here at _start from the reset vector or from crt0-app.S.
-
-// Copyright (c) 1998-2017 Cadence Design Systems, Inc.
-//
-// Permission is hereby granted, free of charge, to any person obtaining
-// a copy of this software and associated documentation files (the
-// "Software"), to deal in the Software without restriction, including
-// without limitation the rights to use, copy, modify, merge, publish,
-// distribute, sublicense, and/or sell copies of the Software, and to
-// permit persons to whom the Software is furnished to do so, subject to
-// the following conditions:
-//
-// The above copyright notice and this permission notice shall be included
-// in all copies or substantial portions of the Software.
-//
-// THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
-// EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
-// MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
-// IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY
-// CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
-// TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
-// SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
-
-#include <xtensa/simboard.h>
-#include <xtensa/simcall.h>
-#include <xtensa/coreasm.h>
-#include "xtos-internal.h"
-
-
-// Exports
-.global _start
-
-// Imports
-// __clibrary_init from C library (eg. newlib or uclibc)
-// exit from C library
-// main from user application
-// __stack from linker script (see LSP Ref Manual)
-
-.type __clibrary_init, @function
-.type main, @function
-.type exit, @function
-
-
-// Macros to abstract away ABI differences
-
-#if __XTENSA_CALL0_ABI__
-# define CALL call0
-# define CALLX callx0
-# define ARG1 a2 /* 1st outgoing call argument */
-# define ARG2 a3 /* 2nd outgoing call argument */
-# define ARG3 a4 /* 3rd outgoing call argument */
-# define ARG4 a5 /* 4th outgoing call argument */
-# define ARG5 a6 /* 5th outgoing call argument */
-#else
-# define CALL call4
-# define CALLX callx4
-# define ARG1 a6 /* 1st outgoing call argument */
-# define ARG2 a7 /* 2nd outgoing call argument */
-# define ARG3 a8 /* 3rd outgoing call argument */
-# define ARG4 a9 /* 4th outgoing call argument */
-# define ARG5 a10 /* 5th outgoing call argument */
-#endif
-
- .data
- .weak _start_envp // allow overriding
- .align 4
-_start_envp: .word 0 // empty environ
-
-
-
- .text
- .align 4
-
-_start:
- // _start is typically NOT at the beginning of the text segment --
- // it is always called from either the reset vector or other code
- // that does equivalent initialization (such as crt0-app.S).
- //
- // Assumptions on entry to _start:
- // - low (level-one) and medium priority interrupts are disabled
- // via PS.INTLEVEL and/or INTENABLE (PS.INTLEVEL is expected to
- // be zeroed, to potentially enable them, before calling main)
- // - C calling context not initialized:
- // - PS not initialized
- // - SP not initialized
- // - the following are initialized:
- // - LITBASE, cache attributes, WindowBase, WindowStart,
- // CPENABLE, FP's FCR and FSR, EXCSAVE[n]
-
- // Keep a0 zero. It is used to initialize a few things.
- // It is also the return address, where zero indicates
- // that the frame used by _start is the bottommost frame.
- //
- movi a0, 0 // keep this register zero.
-
-#if XTOS_RESET_UNNEEDED
-#include "reset-unneeded.S"
-#endif
-
-
- // Initialize the stack pointer.
- // See the "ABI and Software Conventions" chapter in the
- // Xtensa ISA Reference manual for details.
-
- // NOTE: Because the _start routine does not use any memory in its
- // stack frame, and because all of its CALL instructions use a
- // window size of 4, the stack frame for _start can be empty.
- movi sp, __stack
-
- // reserve stack space for
- // - argv array
- // - argument strings
- movi a2, SYS_iss_argv_size
- simcall // returns size of argv[] + its strings in a2
-#if XCHAL_HAVE_PIF
- // The stack only needs 16-byte alignment.
- // However, here we round up the argv size further to 128 byte multiples
- // so that in most cases, variations in argv[0]'s path do not result in
- // different stack allocation. Otherwise, such variations can impact
- // execution timing (eg. due to cache effects etc) for the same code and data.
- // If we have a PIF, it's more likely the extra required space is okay.
- addi a2, a2, 127
- srli a2, a2, 7
- slli a2, a2, 7
-#else
- // Keep stack 16-byte aligned.
- addi a2, a2, 15
- srli a2, a2, 4
- slli a2, a2, 4
-#endif
- // No need to use MOVSP because we have no caller (we're the
- // base caller); in fact it's better not to use MOVSP in this
- // context, to avoid unnecessary ALLOCA exceptions and copying
- // from undefined memory:
- // sub a3, sp, a2
- // movsp sp, a3
- sub sp, sp, a2
-
-
- /*
- * Now that sp (a1) is set, we can set PS as per the application
- * (user vector mode, enable interrupts, enable window exceptions if applicable).
- */
-#if XCHAL_HAVE_EXCEPTIONS
- movi a3, PS_UM|PS_WOE_ABI // PS.WOE = 0|1, PS.UM = 1, PS.EXCM = 0, PS.INTLEVEL = 0
- wsr.ps a3
- rsync
-#endif
-
-
- /*
- * Do any initialization that affects the memory map, such as
- * setting up TLB entries, that needs to be done before we can
- * successfully clear BSS (e.g. if some BSS segments are in
- * remapped areas).
- *
- * NOTE: This hook works where the reset vector does not unpack
- * segments (see "ROM packing" in the LSP manual), or where
- * unpacking of segments is not affected by memory remapping.
- * If ROM unpacking is affected, TLB setup must be done in
- * assembler from the reset vector.
- *
- * The __memmap_init() routine can be a C function, however it
- * does not have BSS initialized! In particular, __memmap_init()
- * cannot set BSS variables, i.e. uninitialized global variables
- * (they'll be wiped out by the following BSS clear), nor can it
- * assume they are yet initialized to zero.
- *
- * The __memmap_init() function is optional. It is marked as a
- * weak symbol, so that it gets valued zero if not defined.
- */
- .weak __memmap_init
- movi a4, __memmap_init
- beqz a4, 1f
- CALLX a4
-1:
-
-#if !XCHAL_HAVE_BOOTLOADER /* boot loader takes care of zeroing BSS */
-
- /* If a system-specific BSS init routine is defined, call it.
- * Such a routine must be named __bss_init(). It can be a C
- * function, however it must be written to be able to work
- * with BSS not yet initialized. This function is optional.
- * It is marked as a weak symbol, so that it gets value zero
- * if not defined.
- */
- .weak __bss_init
- movi a4, __bss_init
- beqz a4, 2f
- movi ARG1, _bss_table_start
- movi ARG2, _bss_table_end
- CALLX a4
- j .Lnobss // skip default BSS init code
-2:
-
- /* The new ISS simcall only appeared after RB-2007.2: */
-#if (XCHAL_HW_MAX_VERSION > XTENSA_HWVERSION_RB_2007_2)
- /*
- * Clear the BSS (uninitialized data) segments.
- * This code supports multiple zeroed sections (*.bss).
- * For speed, we clear memory using an ISS simcall
- * (see crt1-boards.S for more generic BSS clearing code).
- */
- movi a6, _bss_table_start
- movi a7, _bss_table_end
- bgeu a6, a7, .Lnobss
-.Lbssloop:
- movi a2, SYS_memset
- l32i a3, a6, 0 // arg1 = fill start address
- movi a4, 0 // arg2 = fill pattern
- l32i a5, a6, 4 // get end address
- addi a6, a6, 8 // next bss table entry
- sub a5, a5, a3 // arg3 = fill size in bytes
- simcall // memset(a3,a4,a5)
- bltu a6, a7, .Lbssloop // loop until end of bss table
-#endif /* XCHAL_HW_MAX_VERSION */
-.Lnobss:
-#endif /* XCHAL_HAVE_BOOTLOADER */
-
-
- /*
- * Call __clibrary_init to initialize the C library:
- *
- * void __clibrary_init(int argc, char ** argv, char ** environ,
- * void(*init_func)(void), void(*fini_func)(void));
- */
-
- // Get argv with the arguments from the ISS
- mov a3, sp // tell simcall where to write argv[]
- movi a2, SYS_iss_set_argv
- simcall // write argv[] array at a3
-
- movi a2, SYS_iss_argc
- simcall // put argc in a2
-
-
-// Alternative smaller code for Xtensa TX.
-// Many starting with simulation assume a full C env, so NOT DONE FOR NOW.
-//
-//#if XCHAL_HAVE_HALT
-//
-// // Assume minimalist environment for memory-constrained TX cores.
-// // No C library or board initialization, and no call to exit().
-// // However, in the interest of software regressions, for now we
-// // still pass parameters to main (but not the rarely used envp).
-//
-// //mov ARG1, a2 // argc already in a2.
-// mov ARG2, sp // argv
-// CALL main
-// halt
-//
-//#else /* !HALT */
-// ...
-
-
-#if __XTENSA_CALL0_ABI__
- mov a12, a2 // save argc (a2 is ARG1)
-#else
- mov ARG1, a2 // argc
-#endif
- mov ARG2, sp // argv
- movi ARG3, _start_envp // envp
- movi ARG4, _init // _init
- movi ARG5, _fini // _fini
- CALL __clibrary_init
-
- // Call: int main(int argc, char ** argv, char ** environ);
-#if __XTENSA_CALL0_ABI__
- mov ARG1, a12 // argc
-#else
- mov ARG1, a2 // argc
-#endif
- mov ARG2, sp // argv
- movi ARG3, _start_envp // envp = [0]
- CALL main
- // The return value is the same register as the first outgoing argument.
- CALL exit // exit with main's return value
- // Does not return here.
-
- .size _start, . - _start
-
-
-// Local Variables:
-// mode:fundamental
-// comment-start: "// "
-// comment-start-skip: "// *"
-// End:
diff --git a/src/arch/xtensa/smp/xtos/crt1-tiny.S b/src/arch/xtensa/smp/xtos/crt1-tiny.S
deleted file mode 100644
index d1684c5..0000000
--- a/src/arch/xtensa/smp/xtos/crt1-tiny.S
+++ /dev/null
@@ -1,127 +0,0 @@
-// crt1-tiny.S
-//
-// This is a reduced version of the code in crt1-boards.S .
-// For most hardware / boards, this code sets up the C calling context
-// (setting up stack, PS, and clearing BSS) and calls main().
-// It has some limitations (see LSP Ref Manual for details) such as:
-// - does not setup the C library (...)
-// - does not call C++ static constructors and destructors
-// - only clears .bss , not other *.bss sections
-//
-// Control arrives here at _start from the reset vector or from crt0-app.S.
-
-// Copyright (c) 1998-2013 Tensilica Inc.
-//
-// Permission is hereby granted, free of charge, to any person obtaining
-// a copy of this software and associated documentation files (the
-// "Software"), to deal in the Software without restriction, including
-// without limitation the rights to use, copy, modify, merge, publish,
-// distribute, sublicense, and/or sell copies of the Software, and to
-// permit persons to whom the Software is furnished to do so, subject to
-// the following conditions:
-//
-// The above copyright notice and this permission notice shall be included
-// in all copies or substantial portions of the Software.
-//
-// THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
-// EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
-// MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
-// IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY
-// CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
-// TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
-// SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
-
-#include <xtensa/coreasm.h>
-#include <xtensa/xtensa-versions.h>
-#include <xtensa/simcall.h>
-
-
-// Imports
-// __stack from linker script (see LSP Ref Manual)
-// _bss_start from linker script (see LSP Ref Manual)
-// _bss_end from linker script (see LSP Ref Manual)
-// main from user application
-
-
-
-#ifdef __XTENSA_CALL0_ABI__
-# define CALL call0
-#else
-# define CALL call4
-#endif
-
-
-/**************************************************************************/
-
- .text
- .align 4
- .global _start
-_start:
- // _start is typically NOT at the beginning of the text segment --
- // it is always called from either the reset vector or other code
- // that does equivalent initialization (such as crt0-app.S).
- // See crt1-boards.S for assumptions on entry to _start ,
- // and for comments on what is being done in this file.
-
-#if !XCHAL_HAVE_HALT || !XCHAL_HAVE_BOOTLOADER // not needed for Xtensa TX
- movi a0, 0 // mark base of call stack
-#endif
-
- movi sp, __stack // setup the stack
-
-#if XCHAL_HAVE_EXCEPTIONS
- movi a3, PS_UM|PS_WOE_ABI // PS: WOE=0|1, UM=1, EXCM=0, INTLEVEL=0
- wsr.ps a3 // setup PS for the application
- rsync
-#endif
-
-
- // Clear the BSS (uninitialized data) segment.
- //
- // This code only supports .bss, not multiple *.bss sections.
- // Corresponding code in crt1-boards.S does, and is faster but bigger.
-
-#if !XCHAL_HAVE_BOOTLOADER
- movi a6, _bss_start
- movi a7, _bss_end
- bgeu a6, a7, 2f
-1: s32i a0, a6, 0
- addi a6, a6, 4
- bltu a6, a7, 1b
-2:
-#endif
-
- // We can now call C code, the C calling environment is initialized.
- // This tiny C runtime assumes main is declared as "void main(void)"
- // rather than with the usual argc,argv. So there are no arguments.
-
- CALL main
-
- // In this tiny C runtime, main() is not expected to return.
- // If it does, just loop forever.
-
- //CALL xthal_dcache_all_writeback // sync dirty dcaches to memory
- //extw // sync TIE queues/ports/etc (LX or later only)
-
-.L0:
-#if XCHAL_HAVE_HALT
- halt
-#else
-# if XCHAL_HW_MIN_VERSION >= XTENSA_HWVERSION_RE_2013_2 /* SIMCALL is NOP in hw? */
- movi a2, SYS_exit
- simcall // exit if in simulator, else NOP
-# endif
-# if XCHAL_HAVE_DEBUG
- break 1, 15 // give control to debugger
-# endif
-#endif
- j .L0
-
- .size _start, . - _start
-
-
-// Local Variables:
-// mode:fundamental
-// comment-start: "// "
-// comment-start-skip: "// *"
-// End:
diff --git a/src/arch/xtensa/smp/xtos/debug-vector.S b/src/arch/xtensa/smp/xtos/debug-vector.S
deleted file mode 100644
index 049a2df..0000000
--- a/src/arch/xtensa/smp/xtos/debug-vector.S
+++ /dev/null
@@ -1,64 +0,0 @@
-// debug-vector.S -- Debug Exception Vector
-// $Id: //depot/rel/Foxhill/dot.8/Xtensa/OS/xtos/debug-vector.S#1 $
-
-// Copyright (c) 2003-2013 Tensilica Inc.
-//
-// Permission is hereby granted, free of charge, to any person obtaining
-// a copy of this software and associated documentation files (the
-// "Software"), to deal in the Software without restriction, including
-// without limitation the rights to use, copy, modify, merge, publish,
-// distribute, sublicense, and/or sell copies of the Software, and to
-// permit persons to whom the Software is furnished to do so, subject to
-// the following conditions:
-//
-// The above copyright notice and this permission notice shall be included
-// in all copies or substantial portions of the Software.
-//
-// THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
-// EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
-// MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
-// IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY
-// CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
-// TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
-// SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
-
-#include <xtensa/xtensa-versions.h>
-#include <xtensa/coreasm.h>
-#include <xtensa/simcall.h>
-
-#if XCHAL_HAVE_DEBUG && XCHAL_HAVE_EXCEPTIONS
-
- // This code goes at the debug exception vector
-
- .begin literal_prefix .DebugExceptionVector
- .section .DebugExceptionVector.text, "ax"
- .align 4
- .global _DebugExceptionVector
-_DebugExceptionVector:
-
-# if defined(SIMULATOR) || XCHAL_HW_MIN_VERSION >= XTENSA_HWVERSION_RE_2013_2 /* SIMCALL is NOP in hw? */
- // In the simulator (ISS), let the debugger (if any is attached)
- // handle the debug exception, else simply stop the simulation:
- //
- writesr excsave XCHAL_DEBUGLEVEL a2 // save a2 where simulator expects it
- movi a2, SYS_gdb_enter_sktloop
- simcall // have ISS handle the debug exception
-# endif
-# ifndef SIMULATOR
- // For hardware, this code does not handle debug exceptions.
- // To implement a target-side debug monitor, replace this
- // vector with a real one that uses target-specific facilities
- // to communicate with the debugger.
- //
-1:
-# if XCHAL_HAVE_INTERRUPTS
- //waiti XCHAL_DEBUGLEVEL // unexpected debug exception, loop in low-power mode
-# endif
- j 1b // infinite loop - unexpected debug exception
-# endif /*!SIMULATOR*/
-
- .end literal_prefix
- .size _DebugExceptionVector, . - _DebugExceptionVector
-
-#endif /* XCHAL_HAVE_DEBUG && XCHAL_HAVE_EXCEPTIONS */
-
diff --git a/src/arch/xtensa/smp/xtos/deprecated.S b/src/arch/xtensa/smp/xtos/deprecated.S
deleted file mode 100644
index db746db..0000000
--- a/src/arch/xtensa/smp/xtos/deprecated.S
+++ /dev/null
@@ -1,122 +0,0 @@
-// deprecated.S -- Deprecated assembler functions
-
-// Copyright (c) 2003-2015 Tensilica Inc.
-//
-// Permission is hereby granted, free of charge, to any person obtaining
-// a copy of this software and associated documentation files (the
-// "Software"), to deal in the Software without restriction, including
-// without limitation the rights to use, copy, modify, merge, publish,
-// distribute, sublicense, and/or sell copies of the Software, and to
-// permit persons to whom the Software is furnished to do so, subject to
-// the following conditions:
-//
-// The above copyright notice and this permission notice shall be included
-// in all copies or substantial portions of the Software.
-//
-// THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
-// EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
-// MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
-// IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY
-// CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
-// TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
-// SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
-
-#include <xtensa/coreasm.h>
-#include "xtos-internal.h"
-
-
-#if XCHAL_HAVE_XEA1 || XCHAL_HAVE_XEA2
-
- .text
-
-/*
- void _xtos_timer_<N>_delta(int cycles)
-
- Set the timer from the current ccount.
- DEPRECATED. PLEASE USE xthal_set_ccompare() AND xthal_get_ccount()
- INSTEAD, OR USE DIFFERENT ALGORITHM THAT UPDATES CCOMPAREn RELATIVE TO
- LAST CCOMPAREn FOR DRIFT-FREE PERIODIC TIMER INTERRUPTS.
-*/
- .macro define_timer_delta num, numtimers
- .if ((\num-\numtimers) & ~0xFFF) // num < numtimers ?
- .align 4
- .global _xtos_timer_&num&_delta
- .type _xtos_timer_&num&_delta,@function
-_xtos_timer_&num&_delta:
- abi_entry
- rsr.ccount a3
- add a3, a3, a2
- writesr ccompare \num a3
- abi_return
- .size _xtos_timer_&num&_delta, . - _xtos_timer_&num&_delta
- .endif
- .endm
-
-
-
-#if defined(__SPLIT__t0_delta)
-
- define_timer_delta 0, XCHAL_NUM_TIMERS
-
-#elif defined(__SPLIT__t1_delta)
-
- define_timer_delta 1, XCHAL_NUM_TIMERS
-
-#elif defined(__SPLIT__t2_delta)
-
- define_timer_delta 2, XCHAL_NUM_TIMERS
-
-#elif defined(__SPLIT__t3_delta)
-
- define_timer_delta 3, XCHAL_NUM_TIMERS
-
-
-#elif defined(__SPLIT__read_ints)
-
- //
- // u32 _xtos_read_ints( void )
- //
- // _xtos_read_ints() reads the INTERRUPT register and returns it.
- // DEPRECATED.
- // [Kept temporarily because it was documented in T1050 System SW Ref Manual.]
- //
- .text
- .align 4
- .global _xtos_read_ints
- .type _xtos_read_ints,@function
-_xtos_read_ints:
- abi_entry
-#if XCHAL_HAVE_INTERRUPTS
- rsr.interrupt a2
-#else /*XCHAL_HAVE_INTERRUPTS*/
- movi a2, 0
-#endif /*XCHAL_HAVE_INTERRUPTS*/
- abi_return
- .size _xtos_read_ints, . - _xtos_read_ints
-
-
-#elif defined(__SPLIT__clear_ints)
-
- //
- // void _xtos_clear_ints( u32 mask )
- //
- // _xtos_clear_ints() clears selected bits of the INTERRUPT register.
- // DEPRECATED.
- // [Kept temporarily because it was documented in T1050 System SW Ref Manual.]
- //
- .text
- .align 4
- .global _xtos_clear_ints
- .type _xtos_clear_ints,@function
-_xtos_clear_ints:
- abi_entry
-#if XCHAL_HAVE_INTERRUPTS
- wsr.intclear a2
-#endif /*XCHAL_HAVE_INTERRUPTS*/
- abi_return
- .size _xtos_clear_ints, . - _xtos_clear_ints
-
-#endif /* splitting */
-
-#endif /* XEA1 or XEA2 */
-
diff --git a/src/arch/xtensa/smp/xtos/double-vector.S b/src/arch/xtensa/smp/xtos/double-vector.S
deleted file mode 100644
index f52e384..0000000
--- a/src/arch/xtensa/smp/xtos/double-vector.S
+++ /dev/null
@@ -1,98 +0,0 @@
-// double-vector.S -- Double Exception Vector
-// $Id: //depot/rel/Foxhill/dot.8/Xtensa/OS/xtos/double-vector.S#1 $
-
-// Copyright (c) 2000-2004, 2006, 2010 Tensilica Inc.
-//
-// Permission is hereby granted, free of charge, to any person obtaining
-// a copy of this software and associated documentation files (the
-// "Software"), to deal in the Software without restriction, including
-// without limitation the rights to use, copy, modify, merge, publish,
-// distribute, sublicense, and/or sell copies of the Software, and to
-// permit persons to whom the Software is furnished to do so, subject to
-// the following conditions:
-//
-// The above copyright notice and this permission notice shall be included
-// in all copies or substantial portions of the Software.
-//
-// THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
-// EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
-// MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
-// IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY
-// CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
-// TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
-// SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
-
-#include <xtensa/coreasm.h>
-#include <xtensa/config/system.h>
-#ifdef SIMULATOR
-#include <xtensa/simcall.h>
-#endif
-
-
-#if XCHAL_HAVE_EXCEPTIONS && defined(XCHAL_DOUBLEEXC_VECTOR_VADDR)
-
-/*
- * This is a very minimalist implementation of the double
- * exception vector. For XEA2 configurations without a
- * full MMU, this vector is only expected to be executed
- * upon fatal errors (exceptions that occur within critical
- * sections of exception vectors and handlers).
- *
- * For configurations with a full MMU (ie. with TLBs and
- * auto-refill) and the windowed address registers option,
- * a more complete version of this handler is necessary if:
- * dynamic page mapping is implemented, and the stack
- * can ever point to a dynamically mapped area.
- * In this case, a double exception is a normal occurrence
- * when a stack access within a window handler causes
- * a TLB miss exception or other expected MMU fault.
- * XTOS does not support this scenario, hence a minimalist
- * double exception vector is sufficient.
- */
-
- .begin literal_prefix .DoubleExceptionVector
- .section .DoubleExceptionVector.text, "ax"
-
- .align 4
- .global _DoubleExceptionVector
-_DoubleExceptionVector:
-
-# if XCHAL_HAVE_DEBUG
-1: break 1,4 // unhandled double exception
-# elif defined(SIMULATOR)
- wsr.excsave1 a2 // save a2 where simulator expects it
- movi a2, SYS_unhandled_double_exc
-1: simcall // let simulator/debugger report unhandled exception
-# else
-1:
-# endif
- j 1b // infinite loop
-
- // NOTE: a non-minimalist vector may choose to
- // process the double exception in the vector itself
- // (by default, much more space is allocated to double
- // exception vectors than to most other vectors);
- // or, to jump to a double exception handler located
- // elsewhere. If only the normal case of double
- // exceptions occurring within a window handler is
- // being handled, then it is safe to use EXCSAVE_1 to
- // do this jump (window handlers don't use EXCSAVE_1).
- // For example:
- //
- // wsr.excsave1 a0
- // movi a0, _DoubleExceptionFromVector
- // jx a0
- //
- // .text
- // .align 4
- // .global _DoubleExceptionFromVector
- //_DoubleExceptionFromVector:
- // ...
-
-
- .size _DoubleExceptionVector, . - _DoubleExceptionVector
- .text
- .end literal_prefix
-
-#endif /* have double exceptions */
-
diff --git a/src/arch/xtensa/smp/xtos/exc-sethandler.c b/src/arch/xtensa/smp/xtos/exc-sethandler.c
deleted file mode 100644
index 9df2eff..0000000
--- a/src/arch/xtensa/smp/xtos/exc-sethandler.c
+++ /dev/null
@@ -1,70 +0,0 @@
-
-/* exc-sethandler.c - register an exception handler in XTOS */
-
-/*
- * Copyright (c) 1999-2017 Cadence Design Systems, Inc.
- *
- * Permission is hereby granted, free of charge, to any person obtaining
- * a copy of this software and associated documentation files (the
- * "Software"), to deal in the Software without restriction, including
- * without limitation the rights to use, copy, modify, merge, publish,
- * distribute, sublicense, and/or sell copies of the Software, and to
- * permit persons to whom the Software is furnished to do so, subject to
- * the following conditions:
- *
- * The above copyright notice and this permission notice shall be included
- * in all copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
- * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
- * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
- * IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY
- * CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
- * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
- * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
- */
-
-#include <xtensa/config/core.h>
-#include "xtos-internal.h"
-
-
-#if XCHAL_HAVE_EXCEPTIONS
-
-extern void xtos_c_wrapper_handler(void *arg); /* assembly-level wrapper for C handlers */
-extern void xtos_unhandled_exception(void *arg); /* assembly-level handler for exceptions
- with no registered handler */
-extern void xtos_p_none(void *arg); /* default/empty C handler */
-
-
-extern _xtos_handler xtos_c_handler_table[XCHAL_EXCCAUSE_NUM];
-extern _xtos_handler xtos_exc_handler_table[XCHAL_EXCCAUSE_NUM];
-
-/*
- * Register a C handler for the specified general exception
- * (specified EXCCAUSE value).
- */
-_xtos_handler _xtos_set_exception_handler( int n, _xtos_handler f )
-{
- _xtos_handler ret = 0;
-
- if( n < XCHAL_EXCCAUSE_NUM ) {
- _xtos_handler func = f;
-
- if( func == 0 ) {
- func = &xtos_p_none;
- }
- ret = xtos_c_handler_table[n];
- xtos_exc_handler_table[n] = ( (func == &xtos_p_none)
- ? &xtos_unhandled_exception
- : &xtos_c_wrapper_handler );
- xtos_c_handler_table[n] = func;
- if( ret == &xtos_p_none ) {
- ret = 0;
- }
- }
-
- return ret;
-}
-
-#endif /* XCHAL_HAVE_EXCEPTIONS */
-
diff --git a/src/arch/xtensa/smp/xtos/exc-syscall-handler.S b/src/arch/xtensa/smp/xtos/exc-syscall-handler.S
deleted file mode 100644
index 9c647ce..0000000
--- a/src/arch/xtensa/smp/xtos/exc-syscall-handler.S
+++ /dev/null
@@ -1,192 +0,0 @@
-/* exc-syscall-handler.S - XTOS syscall instruction handler */
-
-/*
- * Copyright (c) 1999-2010 Tensilica Inc.
- *
- * Permission is hereby granted, free of charge, to any person obtaining
- * a copy of this software and associated documentation files (the
- * "Software"), to deal in the Software without restriction, including
- * without limitation the rights to use, copy, modify, merge, publish,
- * distribute, sublicense, and/or sell copies of the Software, and to
- * permit persons to whom the Software is furnished to do so, subject to
- * the following conditions:
- *
- * The above copyright notice and this permission notice shall be included
- * in all copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
- * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
- * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
- * IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY
- * CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
- * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
- * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
- */
-
-/*
- * The SYSCALL instruction is typically used to implement system calls.
- * By convention, register a2 identifies the requested system call.
- * Typically, other parameters are passed in registers a3 and up,
- * and results are returned in a2.
- *
- * The Xtensa windowed ABI reserves the value zero of register a2
- * as a request to force register windows to the stack. The call0 ABI,
- * which has no equivalent operation, reserves this value as a no-op.
- *
- * Generally, only code that traverses the stack in unusual ways needs
- * to force (spill) register windows to the stack. In generic C or C++,
- * there are four cases, and they all use the standard SYSCALL mechanism:
- *
- * 1. C++ exceptions
- * 2. setjmp and longjmp
- * 3. functions using the GNU extension "__builtin_return_address"
- * 4. functions using the GNU extension "nonlocal goto"
- *
- * NOTE: Specific operating systems often need to spill register windows
- * to the stack in other situations such as context-switching, passing
- * Unix-like signals to threads, displaying stack tracebacks, etc.
- * They may choose to use the SYSCALL mechanism to do so, or use other
- * means such as calling xthal_window_spill() or other methods.
- *
- * If you want to handle other system calls, you can modify this file, or
- * use the C version of it in exc-syscall-handler.c . The Xtensa ABIs only
- * define system call zero; the behavior of other system calls is up to you.
- */
-
-#include <xtensa/coreasm.h>
-#include "xtos-internal.h"
-
-
-#if XCHAL_HAVE_EXCEPTIONS
-
-//Vector:
-// addi a1, a1, -ESF_TOTALSIZE // allocate exception stack frame, etc.
-// s32i a2, a1, UEXC_a2
-// s32i a3, a1, UEXC_a3
-// movi a3, xtos_exc_handler_table
-// rsr.exccause a2
-// addx4 a2, a2, a3
-// l32i a2, a2, 0
-// s32i a4, a1, UEXC_a4
-// jx a2 // jump to cause-specific handler
-
- .global _need_user_vector_ // pull-in real user vector (tiny LSP)
-
-
- /*
- * The SYSCALL handler is entered when the processor
- * executes the SYSCALL instruction.
- * By convention, the system call to execute is specified in a2.
- */
- .text
- .align 4
- .global _xtos_syscall_handler
-_xtos_syscall_handler:
- // HERE: a2, a3, a4 have been saved to the exception stack frame allocated with a1 (sp).
- // We ignore that a4 was saved, we don't clobber it.
-
- rsr.epc1 a3
-#if XCHAL_HAVE_LOOPS
- // If the SYSCALL instruction was the last instruction in the body of
- // a zero-overhead loop, and the loop will execute again, decrement
- // the loop count and resume execution at the head of the loop:
- //
- rsr.lend a2
- addi a3, a3, 3 // increment EPC to skip the SYSCALL instruction
- bne a2, a3, 1f
- rsr.lcount a2
- beqz a2, 1f
- addi a2, a2, -1
- wsr.lcount a2
- rsr.lbeg a3
-1: l32i a2, a1, UEXC_a2 // get the system call number
-#else
- // No loop registers.
- l32i a2, a1, UEXC_a2 // get the system call number
- addi a3, a3, 3 // increment EPC to skip the SYSCALL instruction
-#endif
- wsr.epc1 a3 // update EPC1 past SYSCALL
- l32i a3, a1, UEXC_a3 // restore a3
- // If you want to handle other system calls, check a2 here.
-
-#ifdef __XTENSA_WINDOWED_ABI__
- bnez a2, .Lnotzero // is syscall number zero?
-
- /* Spill register windows to the stack. */
-
- // Save a2 thru a5 in the nested-C-function area, where an interrupt
- // won't clobber them. The pseudo-CALL's ENTRY below clobbers a4 and a5.
- //s32i a2, a1, (ESF_TOTALSIZE - 32) + 0 // a2 is zero, no need to save
- s32i a3, a1, (ESF_TOTALSIZE - 32) + 4
- s32i a4, a1, (ESF_TOTALSIZE - 32) + 8
- s32i a5, a1, (ESF_TOTALSIZE - 32) + 12
-
- movi a3, PS_WOE|PS_CALLINC(1)|PS_UM|PS_INTLEVEL(XCHAL_EXCM_LEVEL) // CALL4 emulation
- rsr.ps a2 // save PS in a2
- wsr.ps a3 // PS.INTLEVEL=EXCMLEVEL (1 for XEA1)
- // HERE: window overflows enabled but NOT SAFE yet, touch only a0..a3 until it's safe.
- rsr.epc1 a3 // save EPC1 in a3
- addi a1, a1, ESF_TOTALSIZE // restore sp (dealloc ESF) for sane stack again
- rsync // wait for WSR to PS to complete
- // HERE: Window overflows and interrupts are safe, we saved EPC1 and
- // restored a1, and a4-a15 are unmodified.
- // Pseudo-CALL: make it look as if the code that executed SYSCALL
- // made a CALL4 to here. See user exc. handler comments for details.
- // ENTRY cannot cause window overflow; touch a4 to ensure a4-a7
- // overflow if needed:
- movi a4, 0 // clears pseudo-CALL's return PC
- // NOTE: On XEA1 processors, return from window overflow re-enables
- // interrupts (by clearing PS.INTLEVEL). This is okay even though SP
- // is unallocated because we saved state safe from interrupt dispatch.
- .global _SyscallException
-_SyscallException: // label makes tracebacks look nicer
- _entry a1, 64 // as if after a CALL4 (PS.CALLINC==1)
- // Call deep enough to force spill of entire address register file.
- _call12 __deep_call
-1: movi a14, 0x80000000 + .Ldelta_done
- add a0, a12, a14 // clear a0 msbit (per CALL4), offset
-3: retw // return from pseudo-CALL4
-
- // NOTE: a5 still contains the exception window's exception stack frame pointer.
-.LMdon: wsr.ps a2 // for XEA2, this sets EXCM; for XEA1, this sets INTLEVEL to 1; ...
- movi a2, 0 // indicate successful SYSCALL (?)
- l32i a4, a5, 32 + 8
- rsync // complete WSR to PS for safe write to EPC1
- wsr.epc1 a3
- l32i a3, a5, 32 + 4
- l32i a5, a5, 32 + 12
- rfe_rfue
-
- .set .Ldelta_retw, (3b - 1b)
- .set .Ldelta_done, (.LMdon - 1b)
-
- .align 4
- .local __deep_call
-__deep_call:
- entry a1, 48
-#if XCHAL_NUM_AREGS < 64
- mov a15, a15 // touch just far enough to overflow 32
-#else
- movi a12, .Ldelta_retw // use movi/add because of relocation
- add a12, a0, a12 // set return PC as per CALL12
- _entry a1, 48 // last call was call12 so PS.CALLINC==3
- mov a12, a0 // set return PC
- _entry a1, 48
- mov a12, a0 // set return PC
- _entry a1, 16
- mov a11, a11 // touch just far enough to overflow 64
-#endif
- retw
-
-#endif /* __XTENSA_WINDOWED_ABI__ */
-
-.Lnotzero:
- movi a2, -1 /*ENOSYS*/ // system call not supported
- addi a1, a1, ESF_TOTALSIZE
- rfe_rfue
-
- .size _xtos_syscall_handler, . - _xtos_syscall_handler
-
-
-#endif /* XCHAL_HAVE_EXCEPTIONS */
-
diff --git a/src/arch/xtensa/smp/xtos/exc-table.S b/src/arch/xtensa/smp/xtos/exc-table.S
deleted file mode 100644
index 76fa8fe..0000000
--- a/src/arch/xtensa/smp/xtos/exc-table.S
+++ /dev/null
@@ -1,58 +0,0 @@
-// exc-table.S - general exception C handler table
-
-// Copyright (c) 1999-2010 Tensilica Inc.
-//
-// Permission is hereby granted, free of charge, to any person obtaining
-// a copy of this software and associated documentation files (the
-// "Software"), to deal in the Software without restriction, including
-// without limitation the rights to use, copy, modify, merge, publish,
-// distribute, sublicense, and/or sell copies of the Software, and to
-// permit persons to whom the Software is furnished to do so, subject to
-// the following conditions:
-//
-// The above copyright notice and this permission notice shall be included
-// in all copies or substantial portions of the Software.
-//
-// THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
-// EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
-// MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
-// IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY
-// CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
-// TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
-// SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
-
-#include <xtensa/coreasm.h>
-#include "xtos-internal.h"
-
-
-#if XCHAL_HAVE_EXCEPTIONS
-
- /*
- * Table of exception handlers (in C) for user vectored exceptions.
- * Provides entries for all possible 64 exception causes
- * currently allowed for in the EXCCAUSE register.
- */
- .data
- .global xtos_c_handler_table
- .align 4
-xtos_c_handler_table:
-
- /*
- * Default/empty exception C handler.
- * This is just a placeholder for exception causes with no registered
- * handler; it normally never gets executed.
- * NOTE: control goes first to the debugger if one is present;
- * see xtos_unhandled_exception in exc-unhandled.S .
- */
- .text
- .align 4
- .global xtos_p_none
- .type xtos_p_none,@function
-xtos_p_none:
- abi_entry
- // Do nothing.
- abi_return
- .size xtos_p_none, . - xtos_p_none
-
-#endif /* XCHAL_HAVE_EXCEPTIONS */
-
diff --git a/src/arch/xtensa/smp/xtos/exc-unhandled.S b/src/arch/xtensa/smp/xtos/exc-unhandled.S
deleted file mode 100644
index 2f569c0..0000000
--- a/src/arch/xtensa/smp/xtos/exc-unhandled.S
+++ /dev/null
@@ -1,83 +0,0 @@
-// exc-unhandled.S - General Exception Handler for unhandled exceptions
-
-// Copyright (c) 2002-2004, 2006, 2010 Tensilica Inc.
-//
-// Permission is hereby granted, free of charge, to any person obtaining
-// a copy of this software and associated documentation files (the
-// "Software"), to deal in the Software without restriction, including
-// without limitation the rights to use, copy, modify, merge, publish,
-// distribute, sublicense, and/or sell copies of the Software, and to
-// permit persons to whom the Software is furnished to do so, subject to
-// the following conditions:
-//
-// The above copyright notice and this permission notice shall be included
-// in all copies or substantial portions of the Software.
-//
-// THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
-// EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
-// MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
-// IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY
-// CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
-// TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
-// SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
-
-#include <xtensa/coreasm.h>
-#include <xtensa/corebits.h>
-#include "xtos-internal.h"
-#ifdef SIMULATOR
-#include <xtensa/simcall.h>
-#endif
-
-#if XCHAL_HAVE_EXCEPTIONS
-
-/*
- * Assembly-level exception handler used when no handler was
- * registered for the specific exception cause.
- *
- * The BREAK instruction is used to give control to the debugger,
- * if one is present and active. (If none is present and active,
- * the default debug exception handler will typically skip over
- * this break instruction.)
- * This code follows the convention documented in the ISA manual
- * to use BREAK instructions to signal unhandled exceptions to the
- * debugger. For the debugger to report or handle this condition
- * in an OS-independent manner, all processor state (except PC)
- * must be restored as it was when the unhandled exception just
- * occurred (ie. as it was at the beginning of the vector).
- * If execution continues after the BREAK instruction (in which
- * case any register might have been modified by the debugger),
- * just return.
- */
- .text
- .align 4
-
- // If not pulled-in some other way, define it as unhandled:
- .weak xtos_cause3_handler
- .global xtos_cause3_handler
-xtos_cause3_handler:
-
- .global xtos_unhandled_exception
-xtos_unhandled_exception:
-#if XCHAL_HAVE_DEBUG || defined(SIMULATOR)
- l32i a2, a1, UEXC_a2 // restore a2
- l32i a3, a1, UEXC_a3 // restore a3
- // Note: a4-a5 not clobbered, no need to restore.
- addi a1, a1, ESF_TOTALSIZE // restore sp
-# if XCHAL_HAVE_DEBUG
- break 1, 1 // give control to the debugger (if any present)
-# else
- wsr.excsave1 a2 // save a2 where simulator expects it
- movi a2, SYS_unhandled_user_exc
- simcall // let simulator/debugger report unhandled exception
- rsr.excsave1 a2 // restore a2
-# endif
- rfe_rfue // if sim/debug resume, just return
-#else /* DEBUG or SIMULATOR */
- j xtos_unhandled_exception // just loop forever
-#endif /* DEBUG or SIMULATOR */
-
- .size xtos_unhandled_exception, . - xtos_unhandled_exception
-
-
-#endif /* XCHAL_HAVE_EXCEPTIONS */
-
diff --git a/src/arch/xtensa/smp/xtos/exit.S b/src/arch/xtensa/smp/xtos/exit.S
deleted file mode 100644
index eaee436..0000000
--- a/src/arch/xtensa/smp/xtos/exit.S
+++ /dev/null
@@ -1,93 +0,0 @@
-// exit.S
-//
-// For hardware / boards, this is the default _exit routine called by the
-// C library exit() function. If the program ever exits, we eventually
-// end up here after all C library cleanup (such as closing open files,
-// calling exit callbacks and C++ destructors, etc) is complete.
-
-// Copyright (c) 1998-2013 Tensilica Inc.
-//
-// Permission is hereby granted, free of charge, to any person obtaining
-// a copy of this software and associated documentation files (the
-// "Software"), to deal in the Software without restriction, including
-// without limitation the rights to use, copy, modify, merge, publish,
-// distribute, sublicense, and/or sell copies of the Software, and to
-// permit persons to whom the Software is furnished to do so, subject to
-// the following conditions:
-//
-// The above copyright notice and this permission notice shall be included
-// in all copies or substantial portions of the Software.
-//
-// THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
-// EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
-// MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
-// IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY
-// CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
-// TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
-// SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
-
-#include <xtensa/coreasm.h>
-#include <xtensa/config/core-isa.h>
-#include <xtensa/simcall.h>
-#include "xtos-internal.h"
-
-// Macros to abstract away ABI differences
-#if __XTENSA_CALL0_ABI__
-# define CALL call0
-#else
-# define CALL call4
-#endif
-
-
- .text
- .align 4
- .global _exit
- .type _exit, @function
-_exit:
- abi_entry 0, 4
-
-#if __XTENSA_CALL0_ABI__
- // save exit code as cache writeback will clobber a2 in call0
- mov a12, a2
-#endif
-
- // sync dirty data to memory before terminating
-#if XCHAL_DCACHE_IS_COHERENT
- CALL xthal_cache_coherence_optout
-#elif XCHAL_DCACHE_IS_WRITEBACK
- CALL xthal_dcache_all_writeback
-#endif
-
- // sync queues (if any, only for LX and later):
-#if XCHAL_HW_MIN_VERSION >= XTENSA_HWVERSION_RA_2004_1 /* LX or later? */
- extw
-#endif
- // can break to debug monitor, go to sleep with waiti, or just spin in a loop
-.L0:
-#if XCHAL_HAVE_HALT
- halt
-#else
-# if XCHAL_HW_MIN_VERSION >= XTENSA_HWVERSION_RE_2013_2 /* SIMCALL is NOP in hw? */
- // ISS expects exit code in a3
-# if __XTENSA_CALL0_ABI__
- mov a3, a12
-# else
- mov a3, a2
-# endif
- mov a4, a3 // save exitcode for the debugger, as simcall will erase a3
- movi a2, SYS_exit
- simcall // exit if in simulator, else NOP
- mov a2, a4
-# endif
-# if XCHAL_HAVE_DEBUG
- break 1, 15 // back to debugger, if one is attached
-# endif
-# if XCHAL_HAVE_INTERRUPTS
- waiti 15
-# endif
-#endif
- j .L0
- //abi_exit
-
- .size _exit, . - _exit
-
diff --git a/src/arch/xtensa/smp/xtos/int-handler.S b/src/arch/xtensa/smp/xtos/int-handler.S
deleted file mode 100644
index 3c86252..0000000
--- a/src/arch/xtensa/smp/xtos/int-handler.S
+++ /dev/null
@@ -1,59 +0,0 @@
-// int-handler.S - Interrupt Handler Template (for levels > 1)
-// $Id: //depot/main/Xtensa/OS/xtos/inth-template.S#1 $
-
-// Copyright (c) 2003-2004, 2006 Tensilica Inc.
-//
-// Permission is hereby granted, free of charge, to any person obtaining
-// a copy of this software and associated documentation files (the
-// "Software"), to deal in the Software without restriction, including
-// without limitation the rights to use, copy, modify, merge, publish,
-// distribute, sublicense, and/or sell copies of the Software, and to
-// permit persons to whom the Software is furnished to do so, subject to
-// the following conditions:
-//
-// The above copyright notice and this permission notice shall be included
-// in all copies or substantial portions of the Software.
-//
-// THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
-// EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
-// MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
-// IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY
-// CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
-// TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
-// SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
-
-
-// To use this template file, define a macro called _INTERRUPT_LEVEL
-// to be the interrupt priority level of the vector, then include this file.
-// The default Makefile defines _INTERRUPT_LEVEL when assembling this file
-// for each medium and high priority interrupt level.
-
-
-#include <xtensa/coreasm.h>
-#include "xtos-internal.h"
-
-
-#if XCHAL_HAVE_INTERRUPTS
-
-# if INTERRUPT_IS_HI(_INTERRUPT_LEVEL)
-
-# if _INTERRUPT_LEVEL > XTOS_LOCKLEVEL
- /* Not safe to dispatch interrupts in C above XTOS_LOCKLEVEL,
- * so default to assembly high-priority interrupt handlers template
- * in this case (with the default XTOS_LOCKLEVEL this never happens):
- */
-# include "int-highpri-template.S"
-# else
- /* Dispatch high-priority interrupt handlers in C: */
-# include "int-highpri-dispatcher.S"
-# endif
-
-# elif INTERRUPT_IS_MED(_INTERRUPT_LEVEL)
-
-# include "int-medpri-dispatcher.S"
-
-# elif (_INTERRUPT_LEVEL <= XCHAL_NUM_INTLEVELS) && (_INTERRUPT_LEVEL != XCHAL_DEBUGLEVEL)
-# error INTERNAL ERROR: Interrupt priority levels > 1 must be either hi or medium priority!
-# endif
-
-#endif /* XCHAL_HAVE_INTERRUPTS */
diff --git a/src/arch/xtensa/smp/xtos/int-highpri-dispatcher.S b/src/arch/xtensa/smp/xtos/int-highpri-dispatcher.S
deleted file mode 100644
index 2bcc066..0000000
--- a/src/arch/xtensa/smp/xtos/int-highpri-dispatcher.S
+++ /dev/null
@@ -1,474 +0,0 @@
-// High-Priority Interrupt Dispatcher Template
-// $Id: //depot/rel/Foxhill/dot.8/Xtensa/OS/xtos/int-highpri-dispatcher.S#1 $
-
-// Copyright (c) 2004-2015 Tensilica Inc.
-//
-// Permission is hereby granted, free of charge, to any person obtaining
-// a copy of this software and associated documentation files (the
-// "Software"), to deal in the Software without restriction, including
-// without limitation the rights to use, copy, modify, merge, publish,
-// distribute, sublicense, and/or sell copies of the Software, and to
-// permit persons to whom the Software is furnished to do so, subject to
-// the following conditions:
-//
-// The above copyright notice and this permission notice shall be included
-// in all copies or substantial portions of the Software.
-//
-// THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
-// EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
-// MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
-// IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY
-// CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
-// TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
-// SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
-
-//
-// This file allows writing high-priority interrupt handlers in C,
-// providing convenience at a significant cost in performance.
-//
-// By default, this file is included by inth-template.S .
-// The default Makefile defines _INTERRUPT_LEVEL when assembling
-// inth-template.S for each medium and high priority interrupt level.
-//
-// To use this template file, define a macro called _INTERRUPT_LEVEL
-// to be the interrupt priority level of the vector, then include this file.
-
-
-#include <xtensa/coreasm.h>
-#include "xtos-internal.h"
-#include <platform/platcfg.h>
-
-
-#if XCHAL_HAVE_INTERRUPTS && (XCHAL_HAVE_XEA1 || XCHAL_HAVE_XEA2)
-
-#define INTERRUPT_MASK XCHAL_INTLEVEL_MASK(_INTERRUPT_LEVEL)
-#define SINGLE_INTERRUPT ((INTERRUPT_MASK & (INTERRUPT_MASK - 1)) == 0)
-#define SINGLE_INT_NUM XCHAL_INTLEVEL_NUM(_INTERRUPT_LEVEL)
-
-
-#define INTLEVEL_N_MASK INTERRUPT_MASK // mask of interrupts at this priority
-#define INTLEVEL_N_NUM SINGLE_INT_NUM // interrupt number if there is only one
-#define INTLEVEL_N_BELOW_MASK XCHAL_INTLEVEL_ANDBELOW_MASK(_INTERRUPT_LEVEL)
-
-/* Indicates whether there are multiple interrupts at this interrupt
- * priority, ie. mapped to this interrupt vector.
- * If there is only one, its number is INTLEVEL_N_NUM
- */
-#define MULTIPLE_INTERRUPTS (!SINGLE_INTERRUPT)
-
-/*
- * High priority interrupt stack frame:
- */
-STRUCT_BEGIN
-STRUCT_FIELD (long,4,HESF_,SAR)
-STRUCT_FIELD (long,4,HESF_,WINDOWSTART)
-STRUCT_FIELD (long,4,HESF_,WINDOWBASE)
-STRUCT_FIELD (long,4,HESF_,EPC1)
-STRUCT_FIELD (long,4,HESF_,EXCCAUSE)
-STRUCT_FIELD (long,4,HESF_,EXCVADDR)
-STRUCT_FIELD (long,4,HESF_,EXCSAVE1)
-STRUCT_FIELD (long,4,HESF_,VPRI) /* (XEA1 only) */
-#if XCHAL_HAVE_MAC16
-STRUCT_FIELD (long,4,HESF_,ACCLO)
-STRUCT_FIELD (long,4,HESF_,ACCHI)
-/*STRUCT_AFIELD(long,4,HESF_,MR, 4)*/
-#endif
-#if XCHAL_HAVE_LOOPS
-STRUCT_FIELD (long,4,HESF_,LCOUNT)
-STRUCT_FIELD (long,4,HESF_,LBEG)
-STRUCT_FIELD (long,4,HESF_,LEND)
-#endif
-STRUCT_AFIELD(long,4,HESF_,AREG, 64) /* address registers ar0..ar63 */
-#define HESF_AR(n) HESF_AREG+((n)*4)
-STRUCT_END(HighPriFrame)
-#define HESF_TOTALSIZE HighPriFrameSize+32 /* 32 bytes for interrupted code's save areas under SP */
-
-
-#if XCHAL_HAVE_XEA1 && HAVE_XSR /* could be made true for T1040 and T1050 */
-# error "high-priority interrupt stack frame needs adjustment if HAVE_XSR is allowed with XEA1"
-#endif
-
-
-#define PRI_N_STACK_SIZE 1024 /* default to 1 kB stack for each level-N handling */
-
-
- // Allocate save area and stack:
- // (must use .bss, not .comm, because the subsequent .set does not work otherwise)
- .macro generate_stack_for_int core_id
- .if GREATERTHAN(PLATFORM_CORE_COUNT, \core_id)
- .section .bss, "aw"
- .align 16
-LABEL(_Pri_,_Stack&core_id): .space PRI_N_STACK_SIZE + HESF_TOTALSIZE
- .endif
- .endm
-
- generate_stack_for_int 0
- generate_stack_for_int 1
- generate_stack_for_int 2
- generate_stack_for_int 3
-
-#if HAVE_XSR
- .data
- .global LABEL(_Pri_,_HandlerAddress)
-LABEL(_Pri_,_HandlerAddress): .space 4
-#endif
-
-
- .text
- .align 4
- .global LABEL(_Level,FromVector)
-LABEL(_Level,FromVector):
- xtos_stack_addr_percore_add a2, LABEL(_Pri_,_Stack), PRI_N_STACK_SIZE // get ptr to save area
- // interlock
-
- // Save a few registers so we can do some work:
- s32i a0, a2, HESF_AR(0)
-#if HAVE_XSR
- //movi a0, LABEL(_Level,FromVector) // this dispatcher's address
- movi a0, LABEL(_Pri_,_HandlerAddress) // dispatcher address var.
- s32i a1, a2, HESF_AR(1)
- l32i a0, a0, 0 // get dispatcher address
- s32i a3, a2, HESF_AR(3)
- xchgsr excsave _INTERRUPT_LEVEL a0 // get saved a2, restore dispatcher address
-#else
- readsr excsave _INTERRUPT_LEVEL a0 // get saved a2
- s32i a1, a2, HESF_AR(1)
- s32i a3, a2, HESF_AR(3)
-#endif
- s32i a4, a2, HESF_AR(4)
- s32i a0, a2, HESF_AR(2)
-
- // Save/restore all exception state
- // (IMPORTANT: this code assumes no general exceptions occur
- // during the execution of this dispatcher until this state
- // is completely saved and from the point it is restored.)
- //
- // Exceptions that may normally occur within the C handler
- // include window exceptions (affecting EPC1), alloca exceptions
- // (affecting EPC1/EXCCAUSE and its handling uses EXCSAVE1),
- // and possibly others depending on the particular C handler
- // (possibly needing save/restore of EXCVADDR; and EXCVADDR
- // is also possibly corrupted by any access thru an auto-refill
- // way on a processor with a full MMU).
- //
- rsr.epc1 a3
- rsr.exccause a4
- s32i a3, a2, HESF_EPC1
- s32i a4, a2, HESF_EXCCAUSE
-#if !XCHAL_HAVE_XEA1
- rsr.excvaddr a3
- s32i a3, a2, HESF_EXCVADDR
-#endif
- rsr.excsave1 a4
- s32i a4, a2, HESF_EXCSAVE1
-
-#ifdef __XTENSA_WINDOWED_ABI__
- // Save remainder of entire address register file (!):
- movi a0, XCHAL_NUM_AREGS - 8 // how many saved so far
-#endif
-
- s32i a5, a2, HESF_AR(5)
- s32i a6, a2, HESF_AR(6)
- s32i a7, a2, HESF_AR(7)
-
-1: s32i a8, a2, HESF_AR(8)
- s32i a9, a2, HESF_AR(9)
- s32i a10, a2, HESF_AR(10)
- s32i a11, a2, HESF_AR(11)
- s32i a12, a2, HESF_AR(12)
- s32i a13, a2, HESF_AR(13)
- s32i a14, a2, HESF_AR(14)
- s32i a15, a2, HESF_AR(15)
-
-#ifdef __XTENSA_WINDOWED_ABI__
- addi a8, a0, -8
- addi a10, a2, 8*4
- rotw 2
- bnez a0, 1b // loop until done
-
- rotw 2
- // back to original a2 ...
-
- // Save a few other registers required for C:
- rsr.windowstart a3
- rsr.windowbase a4
- s32i a3, a2, HESF_WINDOWSTART
- s32i a4, a2, HESF_WINDOWBASE
-
- // Setup window registers for first caller:
- movi a3, 1
- movi a4, 0
- wsr.windowstart a3
- wsr.windowbase a4
- rsync
-
- // Note: register window has rotated, ie. a0..a15 clobbered.
-
-#endif /* __XTENSA_WINDOWED_ABI__ */
-
- xtos_stack_addr_percore_add a1, LABEL(_Pri_,_Stack), PRI_N_STACK_SIZE // get ptr to save area
- movi a0, 0 // mark start of call frames in stack
-
- // Critical state saved, a bit more to do to allow window exceptions...
-
- // We now have a C-coherent stack and window state.
- // Still have to fix PS while making sure interrupts stay disabled
- // at the appropriate level (ie. level 2 and below are disabled in this case).
-
-#if XCHAL_HAVE_XEA1
- xtos_addr_percore a7, xtos_intstruct // address of interrupt management globals
- rsilft a3, _INTERRUPT_LEVEL, XTOS_LOCKLEVEL // lockout
- movi a4, ~INTLEVEL_N_BELOW_MASK // mask out all interrupts at this level or lower
- l32i a3, a7, XTOS_VPRI_ENABLED_OFS // read previous _xtos_vpri_enabled
- l32i a5, a7, XTOS_ENABLED_OFS // read _xtos_enabled
- s32i a4, a7, XTOS_VPRI_ENABLED_OFS // set new _xtos_vpri_enabled (mask interrupts as if at _INTERRUPT_LEVEL)
- s32i a3, a1, HESF_VPRI // save previous vpri
- movi a2, PS_WOECALL4_ABI + PS_UM // UM=1, INTLEVEL=0
- and a3, a5, a4 // mask out selected interrupts
- wsr.intenable a3 // disable all low-priority interrupts
-#else
- // Load PS for C code, clear EXCM (NOTE: this step is different for XEA1):
- movi a2, PS_WOECALL4_ABI + PS_UM + _INTERRUPT_LEVEL // UM=1, INTLEVEL=N, EXCM=0, RING=0
-#endif
- wsr.ps a2 // update PS to enable window exceptions, etc as per above
- rsync
-
- // Okay, window exceptions can now happen (although we have to call
- // deep before any will happen because we've reset WINDOWSTART).
-
- // Save other state that might get clobbered by C code:
-
-////////////////// COMMON DISPATCH CODE BEGIN
-
- rsr.sar a14
- s32i a14, a1, HESF_SAR
-#if XCHAL_HAVE_LOOPS
- rsr.lcount a14
- s32i a14, a1, HESF_LCOUNT
- rsr.lbeg a14
- s32i a14, a1, HESF_LBEG
- rsr.lend a14
- s32i a14, a1, HESF_LEND
-#endif
-#if XCHAL_HAVE_MAC16
- rsr.acclo a14
- s32i a14, a1, HESF_ACCLO
- rsr.acchi a14
- s32i a14, a1, HESF_ACCHI
-#endif
-
-#if MULTIPLE_INTERRUPTS /* > 1 interrupts at this priority */ // _split_ multi_setup
-#define TABLE_OFS 0
-
- rsr.interrupt a15 // mask of pending interrupts
-# if XCHAL_HAVE_XEA1
- l32i a12, a7, XTOS_ENABLED_OFS // mask of enabled interrupts
-# else
- rsr.intenable a12 // mask of enabled interrupts
-# endif
- movi a13, INTLEVEL_N_MASK // mask of interrupts at this priority level
- and a15, a15, a12
- and a15, a15, a13 // enabled & pending interrupts at this priority
- _beqz a15, LABEL(Pri_,_spurious) // handle spurious interrupts (eg. level-trig.)
-LABEL(Pri_,_loop): // handle all enabled & pending interrupts
- neg a14, a15
- and a14, a14, a15 // single-out least-significant bit set in mask
- wsr.intclear a14 // clear if edge-trig. or s/w or wr/err (else no effect)
-
- // Compute pointer to interrupt table entry, given mask a14 with single bit set:
-
-# if XCHAL_HAVE_NSA
- xtos_addr_percore_sub a12, xtos_interrupt_table, (32-XCHAL_NUM_INTERRUPTS)*8
- nsau a14, a14 // get index of bit in a14, numbered from msbit
- addx8 a12, a14, a12
-# else /* XCHAL_HAVE_NSA */
- xtos_addr_percore a12, xtos_interrupt_table // pointer to interrupt table
- bltui a14, 0x10000, 1f // in 16 lsbits? (if so, check them)
- addi a12, a12, 16*8 // no, index is at least 16 entries further
- // (the above ADDI expands to an ADDI+ADDMI sequence, +128 is outside its range)
- extui a14, a14, 16,16 // shift right upper 16 bits
-1: bltui a14, 0x100, 1f // in 8 lsbits? (if so, check them)
- addi a12, a12, 8*8 // no, index is at least 8 entries further
- srli a14, a14, 8 // shift right upper 8 bits
-1: bltui a14, 0x10, 1f // in 4 lsbits? (if so, check them)
- addi a12, a12, 4*8 // no, index is at least 4 entries further
- srli a14, a14, 4 // shift right 4 bits
-1: bltui a14, 0x4, 1f // in 2 lsbits? (if so, check them)
- addi a12, a12, 2*8 // no, index is at least 2 entries further
- srli a14, a14, 2 // shift right 2 bits
-1: bltui a14, 0x2, 1f // is it the lsbit?
- addi a12, a12, 1*8 // no, index is one entry further
-1: // done! a12 points to interrupt's table entry
-# endif /* XCHAL_HAVE_NSA */
-
-#else /* !MULTIPLE_INTERRUPTS */
-
-# if XCHAL_HAVE_NSA
-# define TABLE_OFS 8 * (XCHAL_NUM_INTERRUPTS - 1 - INTLEVEL_N_NUM)
-# else
-# define TABLE_OFS 8 * INTLEVEL_N_NUM
-# endif
-
- movi a13, INTLEVEL_N_MASK // (if interrupt is s/w or edge-triggered or write/err only)
- xtos_addr_percore a12, xtos_interrupt_table // get pointer to its interrupt table entry
- wsr.intclear a13 // clear the interrupt (if s/w or edge or wr/err only)
-
-#endif /* ifdef MULTIPLE_INTERRUPTS */
-
- l32i a13, a12, TABLE_OFS + 0 // get pointer to handler from table entry
-#ifdef __XTENSA_CALL0_ABI__
- l32i a2, a12, TABLE_OFS + 4 // pass single argument to C handler
- callx0 a13 // call interrupt's C handler
-#else
- l32i a6, a12, TABLE_OFS + 4 // pass single argument to C handler
- callx4 a13 // call interrupt's C handler
-#endif
-
-#if XCHAL_HAVE_XEA1
- xtos_addr_percore a7, xtos_intstruct // address of interrupt management globals
-#endif
-#if MULTIPLE_INTERRUPTS /* > 1 interrupts at this priority */
- rsr.interrupt a15 // get pending interrupts
-# if XCHAL_HAVE_XEA1
- l32i a12, a7, XTOS_ENABLED_OFS // get enabled interrupts
-# else
- rsr.intenable a12 // get enabled interrupts
-# endif
- movi a13, INTLEVEL_N_MASK // get mask of interrupts at this priority level
- and a15, a15, a12
- and a15, a15, a13 // pending+enabled interrupts at this priority
- _bnez a15, LABEL(Pri_,_loop) // if any remain, dispatch one
-LABEL(Pri_,_spurious):
-#endif /* MULTIPLE_INTERRUPTS */
-
- // Restore everything, and return.
-
-#if XCHAL_HAVE_EXCLUSIVE
- // Clear exclusive monitors.
- clrex
-#endif
-
- // Three temp registers are required for this code to be optimal (no interlocks) in
- // T2xxx microarchitectures with 7-stage pipe; otherwise only two
- // registers would be needed.
- //
-#if XCHAL_HAVE_LOOPS
- l32i a13, a1, HESF_LCOUNT
- l32i a14, a1, HESF_LBEG
- l32i a15, a1, HESF_LEND
- wsr.lcount a13
- wsr.lbeg a14
- wsr.lend a15
-#endif
-
-#if XCHAL_HAVE_MAC16
- l32i a13, a1, HESF_ACCLO
- l32i a14, a1, HESF_ACCHI
- wsr.acclo a13
- wsr.acchi a14
-#endif
- l32i a15, a1, HESF_SAR
- wsr.sar a15
-
-////////////////// COMMON DISPATCH CODE END
-
-#if XCHAL_HAVE_XEA1
- // Here, a7 = address of interrupt management globals
- l32i a4, a1, HESF_VPRI // restore previous vpri
- rsil a3, XTOS_LOCKLEVEL // lockout
- l32i a5, a7, XTOS_ENABLED_OFS // read _xtos_enabled
- s32i a4, a7, XTOS_VPRI_ENABLED_OFS // set new _xtos_vpri_enabled
- movi a2, 0x00020 + _INTERRUPT_LEVEL // WOE=0, UM=1, INTLEVEL=N
- and a3, a5, a4 // mask out selected interrupts
- wsr.intenable a3 // disable all low-priority interrupts
-#else
- // Load PS for interrupt exit, set EXCM:
- movi a2, 0x00030 + _INTERRUPT_LEVEL // WOE=0, CALLINC=0, UM=1, INTLEVEL=N, EXCM=1, RING=0
-#endif
- wsr.ps a2 // update PS to disable window exceptions, etc as per above
- rsync
-
- // NOTE: here for XEA1, restore INTENABLE etc...
-
-#ifdef __XTENSA_WINDOWED_ABI__
- // Restore window registers:
- l32i a2, a1, HESF_WINDOWSTART
- l32i a3, a1, HESF_WINDOWBASE
- wsr.windowstart a2
- wsr.windowbase a3
- rsync
- // Note: register window has rotated, ie. a0..a15 clobbered.
-
- // Reload initial stack pointer:
- xtos_stack_addr_percore_add a1, LABEL(_Pri_,_Stack), PRI_N_STACK_SIZE // - 16
- movi a6, XCHAL_NUM_AREGS - 8 // how many saved so far
- addi a7, a1, -8*4
-
- // Restore entire register file (!):
-
-1:
- addi a14, a6, -8
- addi a15, a7, 8*4
- l32i a4, a15, HESF_AR(4)
- l32i a5, a15, HESF_AR(5)
- l32i a6, a15, HESF_AR(6)
- l32i a7, a15, HESF_AR(7)
- l32i a8, a15, HESF_AR(8)
- l32i a9, a15, HESF_AR(9)
- l32i a10,a15, HESF_AR(10)
- l32i a11,a15, HESF_AR(11)
- rotw 2
- bnez a6, 1b // loop until done
-
- l32i a4, a7, HESF_AR(12)
- l32i a5, a7, HESF_AR(13)
- l32i a6, a7, HESF_AR(14)
- l32i a7, a7, HESF_AR(15)
- rotw 2
-
- // back to original a1 ...
-
-#else /* Call0 ABI: */
-
- l32i a4, a1, HESF_AR(4) // restore general registers
- l32i a5, a1, HESF_AR(5)
- l32i a6, a1, HESF_AR(6)
- l32i a7, a1, HESF_AR(7)
- l32i a8, a1, HESF_AR(8)
- l32i a9, a1, HESF_AR(9)
- l32i a10, a1, HESF_AR(10)
- l32i a11, a1, HESF_AR(11)
- l32i a12, a1, HESF_AR(12)
- l32i a13, a1, HESF_AR(13)
- l32i a14, a1, HESF_AR(14)
- l32i a15, a1, HESF_AR(15)
-
-#endif /* __XTENSA_WINDOWED_ABI__ */
-
- // Restore exception state:
- l32i a2, a1, HESF_EPC1
- l32i a3, a1, HESF_EXCCAUSE
- wsr.epc1 a2
- wsr.exccause a3
-#if !XCHAL_HAVE_XEA1
- l32i a2, a1, HESF_EXCVADDR
- wsr.excvaddr a2
-#endif
- l32i a3, a1, HESF_EXCSAVE1
- wsr.excsave1 a3
-
- l32i a0, a1, HESF_AR(0)
- l32i a2, a1, HESF_AR(2)
- l32i a3, a1, HESF_AR(3)
- l32i a1, a1, HESF_AR(1)
- rfi _INTERRUPT_LEVEL
-
- .size LABEL(_Level,FromVector), . - LABEL(_Level,FromVector)
-
- // This symbol exists solely for the purpose of being able to pull-in this
- // dispatcher using _xtos_dispatch_level<n>() routines with the tiny-rt LSP:
- .global LABEL(_Level,HandlerLabel)
- .set LABEL(_Level,HandlerLabel), 0
-
-#endif /* XCHAL_HAVE_INTERRUPTS */
-
diff --git a/src/arch/xtensa/smp/xtos/int-highpri-template.S b/src/arch/xtensa/smp/xtos/int-highpri-template.S
deleted file mode 100644
index e41cc84..0000000
--- a/src/arch/xtensa/smp/xtos/int-highpri-template.S
+++ /dev/null
@@ -1,160 +0,0 @@
-// High-Priority Interrupt Handler Template
-// $Id: //depot/rel/Foxhill/dot.8/Xtensa/OS/xtos/int-highpri-template.S#1 $
-
-// Copyright (c) 2004-2010 Tensilica Inc.
-//
-// Permission is hereby granted, free of charge, to any person obtaining
-// a copy of this software and associated documentation files (the
-// "Software"), to deal in the Software without restriction, including
-// without limitation the rights to use, copy, modify, merge, publish,
-// distribute, sublicense, and/or sell copies of the Software, and to
-// permit persons to whom the Software is furnished to do so, subject to
-// the following conditions:
-//
-// The above copyright notice and this permission notice shall be included
-// in all copies or substantial portions of the Software.
-//
-// THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
-// EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
-// MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
-// IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY
-// CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
-// TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
-// SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
-
-//
-// This file provides skeleton code for writing high-priority interrupt
-// handlers in assembler for performance.
-//
-// By default, this file is included by inth-template.S .
-// The default Makefile defines _INTERRUPT_LEVEL when assembling
-// inth-template.S for each medium and high priority interrupt level.
-//
-// To use this template file, define a macro called _INTERRUPT_LEVEL
-// to be the interrupt priority level of the vector, then include this file.
-
-
-#include <xtensa/coreasm.h>
-#include "xtos-internal.h"
-
-
-#if XCHAL_HAVE_INTERRUPTS
-
-#define INTERRUPT_MASK XCHAL_INTLEVEL_MASK(_INTERRUPT_LEVEL)
-#define SINGLE_INTERRUPT (INTERRUPT_MASK & (INTERRUPT_MASK - 1) == 0)
-#define SINGLE_INT_NUM XCHAL_INTLEVEL_NUM(_INTERRUPT_LEVEL)
-
-
-// NOTE: It is strongly recommended that high-priority
-// interrupt handlers be written in assembly.
-//
-// High-priority interrupt handlers can be written in C,
-// but only at the cost of an unreasonable amount of state
-// save and restore (including the entire physical address
-// register file and others, see int-highpri-dispatcher.S)
-// that makes high-priority interrupt dispatching much slower
-// than for low and medium priority interrupts.
-// (Low and medium priority interrupts are masked by atomic
-// register window operations, so they take advantage of a
-// coherent window state for fast entry. High priority
-// interrupts are not masked by window operations so they
-// can interrupt them, leading to a potentially incoherent
-// window state at the time of the interrupt. Given that
-// high priority handlers must save and restore everything
-// they touch, they end up needing to save and restore the
-// entire window state [physical address register file etc.]
-// and all exception state which they can also interrupt.)
-// See also the Microprocessor Programmer's Guide.
-
-// High-priority interrupts are designed to be very fast and with
-// very low latency.
-// Typical high-priority interrupt service routines are kept
-// relatively small and fast. Either there is little to do,
-// or the routine handles only the necessary high priority
-// activities related to a device and leaves the rest
-// (other more complex and time-consuming activities)
-// to be scheduled later, eg. by triggering a level-one
-// (low-priority) or medium-priority software interrupt whose
-// handler can be written in C for the more extensive processing.
-
-// NOTE: The following handler is just skeleton example
-// code. It is NOT a functional handler. For software, edge-
-// triggered and write-error interrupts, it simply does nothing
-// and return. For other types (timer and level-triggered),
-// this code does not clear the source(s) of interrupt,
-// hence if any interrupt at this priority level are both enabled
-// and triggered, the processor repeatedly takes the interrupt
-// in a loop. This is all okay as a default, because
-// XTOS (and other operating systems) clears the INTENABLE
-// register at startup, requiring the application to
-// enable specific interrupts before they can be taken.
-// So as long as you don't enable any interrupt of this
-// priority level, this example handler will never execute.
-
-// Exports
-.global LABEL(_Level,FromVector)
-
- .data
- .align 4
-LABEL(int,save):
- .space 4 // save area
-
- .text
- .align 4
-LABEL(_Level,FromVector):
- // The vectoring code has already saved a2 in EXCSAVEn.
- // Save any other registers we'll use:
- movi a2, LABEL(int,save)
- s32i a1, a2, 0
- // ... add more as needed (increase save area accordingly) ...
-
- // WRITE YOUR INTERRUPT HANDLING CODE HERE...
-
- // If multiple interrupts are mapped to this priority level,
- // you'll probably need to distinguish which interrupt(s)
- // occurred by reading the INTERRUPT (INTREAD) and
- // INTENABLE registers, and'ing them together, and
- // looking at what bits are set in both.
- // If any of the interrupts are level-triggered, be ready
- // to handle the case where no interrupts are to be handled
- // -- this is called a spurious interrupt, and can happen
- // when the level-triggered interrupt line goes inactive
- // after the interrupt is taken but before the INTERRUPT
- // register is read.
-
- // You'll also normally want to clear the source of
- // the interrupt before returning, to avoid getting
- // the same interrupt again immediately. For illustration,
- // this code clears all software, edge-triggered, and
- // write-error interrupts at this priority level (if any).
- // NOTE: Timer interrupts must be cleared by writing to
- // the corresponding CCOMPAREn register; and level-sensitive
- // interrupts can only be cleared externally, usually by
- // requesting the associated device to do so (in a
- // device-specific manner).
- //
- movi a1, INTERRUPT_MASK
- wsr.intclear a1
-
- // Restore registers:
- l32i a1, a2, 0
-#if HAVE_XSR
- movi a2, LABEL(_Level,FromVector) // restore handler address
- xchgsr excsave _INTERRUPT_LEVEL a2
-#else
- readsr excsave _INTERRUPT_LEVEL a2
-#endif
- // ... add more if more are saved above ...
-
-#if XCHAL_HAVE_EXCLUSIVE
- // If your code used L32EX/S32EX, then clear any active excl monitors.
- // Uncomment the line below.
- // clrex
-#endif
-
- // Return:
- rfi _INTERRUPT_LEVEL
-
- .size LABEL(_Level,FromVector), . - LABEL(_Level,FromVector)
-
-#endif /* XCHAL_HAVE_INTERRUPTS */
diff --git a/src/arch/xtensa/smp/xtos/int-initlevel.S b/src/arch/xtensa/smp/xtos/int-initlevel.S
deleted file mode 100644
index 1b09f25..0000000
--- a/src/arch/xtensa/smp/xtos/int-initlevel.S
+++ /dev/null
@@ -1,59 +0,0 @@
-// int-initlevel.S - Routines used to pull-in interrupt dispatch code
-// in the tiny-rt LSP.
-// $Id: //depot/rel/Foxhill/dot.8/Xtensa/OS/xtos/int-initlevel.S#1 $
-
-// Copyright (c) 2006-2010 Tensilica Inc.
-//
-// Permission is hereby granted, free of charge, to any person obtaining
-// a copy of this software and associated documentation files (the
-// "Software"), to deal in the Software without restriction, including
-// without limitation the rights to use, copy, modify, merge, publish,
-// distribute, sublicense, and/or sell copies of the Software, and to
-// permit persons to whom the Software is furnished to do so, subject to
-// the following conditions:
-//
-// The above copyright notice and this permission notice shall be included
-// in all copies or substantial portions of the Software.
-//
-// THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
-// EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
-// MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
-// IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY
-// CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
-// TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
-// SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
-
-
-// To assemble this template file, define a macro called _INTERRUPT_LEVEL
-// to be the interrupt level of the vector. We use the same template for both
-// high-level and medium-level interrupts, but not debug level.
-
-
-#include <xtensa/coreasm.h>
-#include "xtos-internal.h"
-
-
-#if XCHAL_HAVE_INTERRUPTS && (_INTERRUPT_LEVEL <= XCHAL_NUM_INTLEVELS) && (_INTERRUPT_LEVEL != XCHAL_DEBUGLEVEL)
-
- // Nothing to do at runtime. This function only has effect
- // at link-time.
- //
- .text
- .global LABEL(_xtos_dispatch_level,_interrupts)
- .align 4
-LABEL(_xtos_dispatch_level,_interrupts):
- abi_entry
- abi_return
- .size LABEL(_xtos_dispatch_level,_interrupts), . - LABEL(_xtos_dispatch_level,_interrupts)
-
- // This reference is what does the work of pulling-in the
- // relevant interrupt vector at the specified level.
- // This is only needed in the tiny-rt LSP.
- //
-# if _INTERRUPT_LEVEL == 1
- .global _need_level1int_
-# else
- .global LABEL(_Level,Vector)
-# endif
-
-#endif /* XCHAL_HAVE_INTERRUPTS */
diff --git a/src/arch/xtensa/smp/xtos/int-medpri-dispatcher.S b/src/arch/xtensa/smp/xtos/int-medpri-dispatcher.S
deleted file mode 100644
index cbd6b82..0000000
--- a/src/arch/xtensa/smp/xtos/int-medpri-dispatcher.S
+++ /dev/null
@@ -1,269 +0,0 @@
-// Medium-Priority Interrupt Dispatcher Template
-// $Id: //depot/rel/Foxhill/dot.8/Xtensa/OS/xtos/int-medpri-dispatcher.S#1 $
-
-// Copyright (c) 2004-2010 Tensilica Inc.
-//
-// Permission is hereby granted, free of charge, to any person obtaining
-// a copy of this software and associated documentation files (the
-// "Software"), to deal in the Software without restriction, including
-// without limitation the rights to use, copy, modify, merge, publish,
-// distribute, sublicense, and/or sell copies of the Software, and to
-// permit persons to whom the Software is furnished to do so, subject to
-// the following conditions:
-//
-// The above copyright notice and this permission notice shall be included
-// in all copies or substantial portions of the Software.
-//
-// THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
-// EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
-// MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
-// IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY
-// CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
-// TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
-// SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
-
-//
-// By default, this file is included by inth-template.S .
-// The default Makefile defines _INTERRUPT_LEVEL when assembling
-// inth-template.S for each medium and high priority interrupt level.
-//
-// To use this template file, define a macro called _INTERRUPT_LEVEL
-// to be the interrupt priority level of the vector, then include this file.
-
-
-#include <xtensa/coreasm.h>
-#include "xtos-internal.h"
-
-
-#if XCHAL_HAVE_INTERRUPTS
-
-#define INTERRUPT_MASK XCHAL_INTLEVEL_MASK(_INTERRUPT_LEVEL)
-#define SINGLE_INTERRUPT ((INTERRUPT_MASK & (INTERRUPT_MASK - 1)) == 0)
-#define SINGLE_INT_NUM XCHAL_INTLEVEL_NUM(_INTERRUPT_LEVEL)
-
-
-// Strict non-preemptive prioritization
-
-
- .text
- .align 4
- .global LABEL(_Level,FromVector)
-LABEL(_Level,FromVector):
-
-/* Allocate an exception stack frame, save a2, a4, and a5, and fix PS as:
- *
- * if not Call0 ABI
- * - enable windowing for 'entry' (ps.woe=1, ps.excm=0)
- * - setup ps.callinc to simulate call4
- * endif
- * - preserve user mode
- * - mask all interrupts at EXCM_LEVEL and lower
- *
- * Then deallocate the stack, 'rsync' for the write to PS, then use
- * 'entry' to re-allocate the stack frame and rotate the register
- * window (like a call4, preserving a0..a3). */
-
-#if HAVE_XSR
- xchgsr excsave _INTERRUPT_LEVEL a2
-#else
- readsr excsave _INTERRUPT_LEVEL a2
-#endif
- addi a1, a1, -ESF_TOTALSIZE
- s32i a2, a1, UEXC_a2
- movi a2, PS_WOECALL4_ABI|PS_UM|PS_INTLEVEL(XCHAL_EXCM_LEVEL)
- s32i a4, a1, UEXC_a4
- s32i a5, a1, UEXC_a5
- wsr.ps a2
- rsync
-
-#ifdef __XTENSA_CALL0_ABI__
- s32i a0, a1, UEXC_a0
- s32i a3, a1, UEXC_a3
- s32i a6, a1, UEXC_a6
- s32i a7, a1, UEXC_a7
- s32i a8, a1, UEXC_a8
- s32i a9, a1, UEXC_a9
- s32i a10, a1, UEXC_a10
- s32i a11, a1, UEXC_a11
- s32i a12, a1, UEXC_a12
- s32i a13, a1, UEXC_a13
- s32i a14, a1, UEXC_a14
- s32i a15, a1, UEXC_a15
- movi a0, 0 /* terminate stack frames */
-# if XTOS_DEBUG_PC
- // TODO: setup return PC for call traceback through interrupt dispatch
-# endif
-#else
-# if XTOS_CNEST
- l32i a2, a1, ESF_TOTALSIZE-20 // save nested-C-func call-chain ptr
-# endif
- addi a1, a1, ESF_TOTALSIZE
-# if XTOS_DEBUG_PC
- readsr epc _INTERRUPT_LEVEL a4 // [for debug] get return PC
- movi a5, 0xC0000000 // [for debug] setup call size...
- or a4, a5, a4 // [for debug] set upper two bits of return PC
- addx2 a4, a5, a4 // [for debug] clear upper bit
-# else
- movi a4, 0 /* terminate stack frames, overflow check */
-# endif
- _entry a1, ESF_TOTALSIZE
-#endif
-
-/* Reset the interrupt level to mask all interrupts at the current
- * priority level and lower. Note the current priority level may be
- * less than or equal to EXCM_LEVEL. */
-
- rsil a15, _INTERRUPT_LEVEL
-
-#if SINGLE_INTERRUPT /* if only one interrupt at this priority level... */
-
-/* Preserve the SAR, loop, and MAC16 regs. Also, clear the interrupt. */
-
- rsr.sar a14
- movi a12, INTERRUPT_MASK
- s32i a14, a1, UEXC_sar
- wsr.intclear a12 // clear if edge-trig or s/w or wr/err (else no effect)
- save_loops_mac16 a1, a13, a14
-
- // Change stack pointer
- xtos_stack_addr_percore a13, _INTERRUPT_LEVEL, xtos_stack_for_interrupt
- s32i a1, a13, 0
- addi a1, a13, XTOS_STACK_FOR_INTERRUPT_SIZE
-
-/* Load the handler from the table, initialize two args (interrupt
- * number and exception stack frame), then call the interrupt handler.
- * Note: The callx12 preserves the original user task's a4..a15.*/
-
- xtos_addr_percore_add a12, xtos_interrupt_table, MAPINT(SINGLE_INT_NUM)*XIE_SIZE
- l32i a13, a12, XIE_HANDLER
-# ifdef __XTENSA_CALL0_ABI__
- l32i a2, a12, XIE_ARG
- mov a3, a1
- callx0 a13
-# else
- l32i a14, a12, XIE_ARG
- mov a15, a1
- callx12 a13
-# endif
-
-#else /* > 1 interrupts at this priority level */
-
-/* Get bit list of pending interrupts at the current interrupt priority level.
- * If bit list is empty, interrupt is spurious (can happen if a
- * genuine interrupt brings control this direction, but the interrupt
- * goes away before we read the INTERRUPT register). Also save off
- * sar, loops, and mac16 registers. */
-
- rsr.interrupt a15
- rsr.intenable a12
- movi a13, INTERRUPT_MASK
- and a15, a15, a12
- and a15, a15, a13
- rsr.sar a14
- _beqz a15, LABEL(spurious,int)
- s32i a14, a1, UEXC_sar
- save_loops_mac16 a1, a13, a14
-
-/* Loop to handle all pending interrupts. */
-
- // Change stack pointer
- xtos_stack_addr_percore a13, _INTERRUPT_LEVEL, xtos_stack_for_interrupt
- s32i a1, a13, 0
- addi a1, a13, XTOS_INT_STACK_SIZE
-
-LABEL(.L1,_loop0):
- neg a12, a15
- and a12, a12, a15
- wsr.intclear a12 // clear if edge-trig or s/w or wr/err (else no effect)
- xtos_addr_percore a13, xtos_interrupt_table
- find_ms_setbit a15, a12, a14, 0
- mapint a15
- addx8 a12, a15, a13
- l32i a13, a12, XIE_HANDLER
-# ifdef __XTENSA_CALL0_ABI__
- l32i a2, a12, XIE_ARG
- mov a3, a1
- callx0 a13
-# else
- l32i a14, a12, XIE_ARG
- mov a15, a1
- callx12 a13
-# endif
- rsr.interrupt a15
- rsr.intenable a12
- movi a13, INTERRUPT_MASK
- and a15, a15, a12
- and a15, a15, a13
- _bnez a15, LABEL(.L1,_loop0)
-
-#endif /* SINGLE_INTERRUPT */
-
-/* Restore everything, and return. */
-
- restore_loops_mac16 a1, a13, a14, a15
- l32i a14, a1, UEXC_sar
-LABEL(spurious,int):
-
-#if XCHAL_HAVE_EXCLUSIVE
- // Clear exclusive monitors.
- clrex
-#endif
-
-#ifdef __XTENSA_CALL0_ABI__
- wsr.sar a14
- l32i a0, a1, UEXC_a0
- l32i a2, a1, UEXC_a2
- l32i a3, a1, UEXC_a3
- l32i a4, a1, UEXC_a4
- l32i a5, a1, UEXC_a5
- l32i a6, a1, UEXC_a6
- l32i a7, a1, UEXC_a7
- l32i a8, a1, UEXC_a8
- l32i a9, a1, UEXC_a9
- l32i a10, a1, UEXC_a10
- l32i a11, a1, UEXC_a11
- l32i a12, a1, UEXC_a12
- l32i a13, a1, UEXC_a13
- l32i a14, a1, UEXC_a14
- l32i a15, a1, UEXC_a15
- addi a1, a1, ESF_TOTALSIZE // restore sp
- rfi _INTERRUPT_LEVEL
-
-#else /* windowed ABI: */
-
- movi a0, LABEL(return,from_exc)
- movi a13, 0xC0000000
- wsr.sar a14
- or a0, a0, a13
- addx2 a0, a13, a0
-# if _INTERRUPT_LEVEL < XCHAL_EXCM_LEVEL
-/* Raise the interrupt mask before
- * returning to avoid a race condition where we deallocate the
- * exception stack frame but still have more register values to
- * restore from it. */
- rsil a14, XCHAL_EXCM_LEVEL
-# endif
- retw
-LABEL(return,from_exc):
- // a5 contains ptr to stack dedicated for interrupt
- addi a5, a5, -XTOS_INT_STACK_SIZE
- l32i a5, a5, 0
-
-# if XTOS_CNEST
- s32i a2, a5, ESF_TOTALSIZE-20 // restore nested-C-func call-chain ptr
-# endif
- l32i a2, a5, UEXC_a2
- l32i a4, a5, UEXC_a4
- l32i a5, a5, UEXC_a5
- rfi _INTERRUPT_LEVEL
-#endif /* windowed ABI */
-
- .size LABEL(_Level,FromVector), . - LABEL(_Level,FromVector)
-
- // This symbol exists solely for the purpose of being able to pull-in this
- // dispatcher using _xtos_dispatch_level<n>() routines with the tiny-rt LSP:
- .global LABEL(_Level,HandlerLabel)
- .set LABEL(_Level,HandlerLabel), 0
-
-#endif /* XCHAL_HAVE_INTERRUPT */
-
diff --git a/src/arch/xtensa/smp/xtos/int-sethandler.c b/src/arch/xtensa/smp/xtos/int-sethandler.c
deleted file mode 100644
index ecb7b78..0000000
--- a/src/arch/xtensa/smp/xtos/int-sethandler.c
+++ /dev/null
@@ -1,65 +0,0 @@
-
-/* int-sethandler.c - register an interrupt handler in XTOS */
-
-/*
- * Copyright (c) 1999-2017 Cadence Design Systems, Inc.
- *
- * Permission is hereby granted, free of charge, to any person obtaining
- * a copy of this software and associated documentation files (the
- * "Software"), to deal in the Software without restriction, including
- * without limitation the rights to use, copy, modify, merge, publish,
- * distribute, sublicense, and/or sell copies of the Software, and to
- * permit persons to whom the Software is furnished to do so, subject to
- * the following conditions:
- *
- * The above copyright notice and this permission notice shall be included
- * in all copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
- * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
- * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
- * IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY
- * CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
- * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
- * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
- */
-
-#include "xtos-structs.h"
-#include <arch/cpu.h>
-
-extern struct xtos_core_data *core_data_ptr[PLATFORM_CORE_COUNT];
-
-_xtos_handler _xtos_set_interrupt_handler_arg( int n, _xtos_handler f, void *arg )
-{
- XtosIntHandlerEntry *entry;
- _xtos_handler old;
- _xtos_handler ret;
-
- if( (n < 0) || (n >= XCHAL_NUM_INTERRUPTS) ) {
- ret = 0; /* invalid interrupt number */
- }
- else if( (int) Xthal_intlevel[n] > XTOS_LOCKLEVEL ) {
- ret = 0; /* priority level too high to safely handle in C */
- }
- else {
- entry = &(core_data_ptr[arch_cpu_get_id()]->xtos_int_data.xtos_interrupt_table.array[MAPINT(n)]);
- old = entry->handler;
- if (f) {
- entry->handler = f;
- entry->u.varg = arg;
- } else {
- entry->handler = &xtos_unhandled_interrupt;
- entry->u.narg = n;
- }
- ret = (old == &xtos_unhandled_interrupt) ? 0 : old;
- }
-
- return ret;
-}
-
-
-_xtos_handler _xtos_set_interrupt_handler( int n, _xtos_handler f )
-{
- return _xtos_set_interrupt_handler_arg( n, f, (void *) n );
-}
-
diff --git a/src/arch/xtensa/smp/xtos/int-vector.S b/src/arch/xtensa/smp/xtos/int-vector.S
deleted file mode 100644
index f23ad50..0000000
--- a/src/arch/xtensa/smp/xtos/int-vector.S
+++ /dev/null
@@ -1,70 +0,0 @@
-// int-vector.S - Interrupt Vector Template (for levels > 1)
-// $Id: //depot/rel/Foxhill/dot.8/Xtensa/OS/xtos/int-vector.S#1 $
-
-// Copyright (c) 2003-2017 Tensilica Inc.
-//
-// Permission is hereby granted, free of charge, to any person obtaining
-// a copy of this software and associated documentation files (the
-// "Software"), to deal in the Software without restriction, including
-// without limitation the rights to use, copy, modify, merge, publish,
-// distribute, sublicense, and/or sell copies of the Software, and to
-// permit persons to whom the Software is furnished to do so, subject to
-// the following conditions:
-//
-// The above copyright notice and this permission notice shall be included
-// in all copies or substantial portions of the Software.
-//
-// THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
-// EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
-// MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
-// IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY
-// CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
-// TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
-// SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
-
-
-// To use this template file, define a macro called _INTERRUPT_LEVEL
-// to be the interrupt level of the vector, include "xtos-internal.h",
-// then include this file. We use the same template for both high-level
-// and medium-level interrupts, but not debug level.
-
-
-#define _ASMLANGUAGE
-#include "xtos-internal.h"
-#include <xtensa/coreasm.h>
-#include <xtensa/config/system.h>
-
-
-#if XCHAL_HAVE_INTERRUPTS && (_INTERRUPT_LEVEL <= XCHAL_NUM_INTLEVELS) && (_INTERRUPT_LEVEL != XCHAL_DEBUGLEVEL)
-
- .begin literal_prefix LABEL(.Level,InterruptVector)
- .section LABEL(.Level,InterruptVector.text), "ax"
- .align 4
- .global LABEL(_Level,Vector)
-LABEL(_Level,Vector):
- // Medium and high priority interrupt vector:
-
-# if HAVE_XSR
- // With XSR, we can use this vector which has the advantage of being ROMable
- // without requiring the handler to also be in ROM; however, it requires
- // initializing the EXCSAVEn register (see reset-vector.S) and a slightly
- // different save/restore sequence in the handler:
- hw_erratum_487_fix
- xchgsr excsave _INTERRUPT_LEVEL a2
- jx a2
-
- // Pull-in the real handler by reference, to ensure the reset vector gets it:
- .global LABEL(_Level,FromVector)
-
-# else
- writesr excsave _INTERRUPT_LEVEL a2
- movi a2, LABEL(_Level,FromVector)
- jx a2
-# endif
-
- .size LABEL(_Level,Vector), . - LABEL(_Level,Vector)
- .text
- .end literal_prefix
-
-#endif /* interrupt at that level */
-
diff --git a/src/arch/xtensa/smp/xtos/interrupt-pri.h b/src/arch/xtensa/smp/xtos/interrupt-pri.h
deleted file mode 100644
index ae22cd2..0000000
--- a/src/arch/xtensa/smp/xtos/interrupt-pri.h
+++ /dev/null
@@ -1,177 +0,0 @@
-/* interrupt-pri.h - Definitions and macros related to interrupt prioritization */
-/*
- * Copyright (c) 2002-2004, 2006 Tensilica Inc.
- *
- * Permission is hereby granted, free of charge, to any person obtaining
- * a copy of this software and associated documentation files (the
- * "Software"), to deal in the Software without restriction, including
- * without limitation the rights to use, copy, modify, merge, publish,
- * distribute, sublicense, and/or sell copies of the Software, and to
- * permit persons to whom the Software is furnished to do so, subject to
- * the following conditions:
- *
- * The above copyright notice and this permission notice shall be included
- * in all copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
- * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
- * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
- * IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY
- * CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
- * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
- * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
- */
-
-#if !defined(_ASMLANGUAGE) && !defined(__ASSEMBLER__)
-# error "The interrupt-pri.h header file is meant for inclusion by assembly source code only."
-#endif
-
-#include <xtensa/coreasm.h>
-#include "xtos-internal.h"
-
-/*
- * The following macros are used by int-lowpri-dispatcher.S to
- * implement prioritized interrupt dispatching and fairness.
- * The prioritization scheme is set by XTOS parameters in xtos-params.h .
- */
-
-
-#if XCHAL_HAVE_INTERRUPTS
-
- // msindex_int
- //
- // Return in register \aindex the index of the first (most significant) bit set
- // in register \amask.
- // Register \amask is clobbered (modified) by this macro.
- //
- // Note: this code is similar to the find_ms_setbit macro in <xtensa/coreasm.h>.
- //
- .macro msindex_int aindex, amask
-# if XCHAL_HAVE_NSA
- nsau \aindex, \amask // \aindex = interrupt index, from 0 to 31, from left to right
- //movi \amask, 31
- //sub \aindex, \amask, \aindex
-# else
- movi \aindex, 0 // start with result of 0 (point to lsbit of 32)
-# if XCHAL_NUM_INTERRUPTS > 16
- bltui \amask, 0x10000, 2f // is it one of the 16 lsbits? (if so, check lower 16 bits)
- addi \aindex, \aindex, 16 // no, increment result to upper 16 bits (of 32)
- extui \amask, \amask, 16, 16 // check upper half (shift right 16 bits)
-2:
-# endif
-# if XCHAL_NUM_INTERRUPTS > 8
- bltui \amask, 0x100, 2f // is it one of the 8 lsbits? (if so, check lower 8 bits)
- addi \aindex, \aindex, 8 // no, increment result to upper 8 bits (of 16)
- srli \amask, \amask, 8 // shift right to check upper 8 bits
-2:
-# endif
-# if XCHAL_NUM_INTERRUPTS > 4
- bltui \amask, 0x10, 2f // is it one of the 4 lsbits? (if so, check lower 4 bits)
- addi \aindex, \aindex, 4 // no, increment result to upper 4 bits (of 8)
- srli \amask, \amask, 4 // shift right 4 bits to check upper half
-2:
-# endif
- bltui \amask, 0x4, 2f // is it one of the 2 lsbits? (if so, check lower 2 bits)
- addi \aindex, \aindex, 2 // no, increment result to upper 2 bits (of 4)
- srli \amask, \amask, 2 // shift right 2 bits to check upper half
-2:
- bltui \amask, 0x2, 2f // is it the lsbit?
- addi \aindex, \aindex, 1 // no, increment result to upper bit (of 2)
-2: // done!
-# endif /*!NSA*/
- // HERE: \aindex = index of interrupt to handle
- // \amask is available
- .endm
-
-
- // msindex_int_nc
- //
- // Same as msindex_int, but does not clobber \amask.
- // Uses extra register \atmp (a temporary register) if needed.
- //
- .macro msindex_int_nc aindex, amask, atmp
-# if XCHAL_HAVE_NSA
- msindex_int \aindex, \amask // does not clobber \amask in this case
-# else
- mov \atmp, \amask
- msindex_int \aindex, \atmp
-# endif
- .endm
-
-
- // indexmask_int
- //
- // Compute index of highest priority interrupt in given mask,
- // and trim mask to single bit corresponding to that interrupt.
- // This is used for interrupt dispatching.
- //
- // Entry:
- // \index = (undefined)
- // \mask = non-zero mask of interrupt bits to consider handling
- // \intptr = &_xtos_intstruct if INTENABLE virtualized, else undefined
- // \tmp = (undefined)
- // Exit:
- // \index = index of interrupt (reversed if NSA present)
- // \mask = single bit corresponding to index
- // \intptr = (preserved)
- // \tmp = (clobbered)
- //
- .macro indexmask_int index, mask, intptr, tmp
-# if XTOS_SUBPRI_ORDER == XTOS_SPO_ZERO_LO
-
- msindex_int \index, \mask // \index = index of msbit set in \mask (\tmp is tmp, \mask clobbered)
- // \index now contains the index of the highest priority pending+enabled interrupt.
-# if XCHAL_HAVE_NSA
- movi \mask, 0x80000000
- ssr \index
- srl \mask, \mask // \mask = single bit set corresponding to interrupt to be processed...
-# else
- movi \mask, 1
- ssl \index
- sll \mask, \mask // \mask = single bit set corresponding to interrupt to be processed...
-# endif
-
-# elif XTOS_SUBPRI_ORDER == XTOS_SPO_ZERO_HI
-
- neg \index, \mask // find lsbit in \mask ...
- and \mask, \index, \mask // ...
- msindex_int_nc \index, \mask, \tmp // \index = index of msbit set in \mask (\tmp is tmp, \mask not clobbered)
-
-# else
-# error Unsupported priority ordering.
-# endif /*SUBPRI_ORDER*/
- .endm
-
-
- // index_int
- //
- // Compute index of highest priority interrupt in given mask.
- // This is used for fairness computations.
- //
- // Entry:
- // \index = (undefined)
- // \mask = non-zero mask of interrupt bits to consider handling
- // \intptr = &_xtos_intptr
- // \tmp = (undefined)
- // Exit:
- // \index = index of interrupt (reversed if NSA present)
- // \mask = (preserved)
- // \intptr = (preserved)
- // \tmp = (clobbered)
- //
- .macro index_int index, mask, intptr, tmp
-# if XTOS_SUBPRI_ORDER == XTOS_SPO_ZERO_LO
- msindex_int_nc \index, \mask, \tmp // \index = index of msbit set in \mask (\mask not clobbered)
-# elif XTOS_SUBPRI_ORDER == XTOS_SPO_ZERO_HI
- neg \tmp, \mask // find lsbit in \mask ...
- and \tmp, \tmp, \mask // ...
- msindex_int \index, \tmp // \index = index of msbit set in \tmp (\tmp is clobbered)
-# else
-# error oops
-# endif
- .endm // index_int
-
-
-#endif /* XCHAL_HAVE_INTERRUPTS */
-
-
diff --git a/src/arch/xtensa/smp/xtos/interrupt-table.S b/src/arch/xtensa/smp/xtos/interrupt-table.S
deleted file mode 100644
index 8e98080..0000000
--- a/src/arch/xtensa/smp/xtos/interrupt-table.S
+++ /dev/null
@@ -1,59 +0,0 @@
-// interrupt-table.S - Interrupt handler table and default handler
-
-// Copyright (c) 2004-2017 Cadence Design Systems, Inc.
-//
-// Permission is hereby granted, free of charge, to any person obtaining
-// a copy of this software and associated documentation files (the
-// "Software"), to deal in the Software without restriction, including
-// without limitation the rights to use, copy, modify, merge, publish,
-// distribute, sublicense, and/or sell copies of the Software, and to
-// permit persons to whom the Software is furnished to do so, subject to
-// the following conditions:
-//
-// The above copyright notice and this permission notice shall be included
-// in all copies or substantial portions of the Software.
-//
-// THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
-// EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
-// MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
-// IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY
-// CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
-// TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
-// SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
-
-#include <xtensa/coreasm.h>
-#include "xtos-internal.h"
-
-
-#if XCHAL_HAVE_INTERRUPTS
-
- //
- // void xtos_unhandled_interrupt( int n );
- //
- // Default/empty interrupt handler.
- // This is used for interrupts with no registered handler.
- // Parameter n is the interrupt number (0 thru 31).
- //
-
- .text
- .align 4
- .global xtos_unhandled_interrupt
- .type xtos_unhandled_interrupt,@function
-
-xtos_unhandled_interrupt:
- abi_entry
-# if XCHAL_HAVE_DEBUG
- // Break into the debugger if one is present and active:
-# if XCHAL_NUM_INTLEVELS > XCHAL_DEBUGLEVEL
- rsil a3, XCHAL_DEBUGLEVEL-1 // ensure break takes effect
-# endif
- break 1, 15 // unhandled (unregistered) interrupt $a2
-# else
-1: j 1b // unhandled interrupt - loop forever
-# endif
- abi_return
-
- .size xtos_unhandled_interrupt, . - xtos_unhandled_interrupt
-
-#endif /* XCHAL_HAVE_INTERRUPTS */
-
diff --git a/src/arch/xtensa/smp/xtos/ints-off.S b/src/arch/xtensa/smp/xtos/ints-off.S
deleted file mode 100644
index ede89d6..0000000
--- a/src/arch/xtensa/smp/xtos/ints-off.S
+++ /dev/null
@@ -1,73 +0,0 @@
-// ints-off.S - Interrupt related assembler code - _xtos_ints_off
-
-// Copyright (c) 2004-2015 Tensilica Inc.
-//
-// Permission is hereby granted, free of charge, to any person obtaining
-// a copy of this software and associated documentation files (the
-// "Software"), to deal in the Software without restriction, including
-// without limitation the rights to use, copy, modify, merge, publish,
-// distribute, sublicense, and/or sell copies of the Software, and to
-// permit persons to whom the Software is furnished to do so, subject to
-// the following conditions:
-//
-// The above copyright notice and this permission notice shall be included
-// in all copies or substantial portions of the Software.
-//
-// THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
-// EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
-// MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
-// IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY
-// CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
-// TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
-// SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
-
-#include <xtensa/coreasm.h>
-#include "xtos-internal.h"
-
-
-/***************************************************************************
- * _xtos_ints_on() and _xtos_ints_off() are used
- * to enable and disable interrupts from C code;
- * they can be called from the application or from a C interrupt handler.
- */
-
-// u32 _xtos_ints_off( u32 mask ); [T1050.0 docs this as returning old INTENABLE value]
-// Disables a set of interrupts. See _xtos_ints_on().
-//
-// MUST NOT be called when PS.INTLEVEL > XTOS_LOCKLEVEL
-// (otherwise PS.INTLEVEL gets lowered; and operation may be inconsistent
-// if this is called in the handler of an interrupt of level > LOCKLEVEL).
-//
- .text
- .align 4
- .global _xtos_ints_off
- .type _xtos_ints_off,@function
-_xtos_ints_off:
- abi_entry
-#if XCHAL_HAVE_INTERRUPTS && (XCHAL_HAVE_XEA1 || XCHAL_HAVE_XEA2)
-# if XTOS_VIRTUAL_INTENABLE
- xtos_addr_percore a4, xtos_intstruct
- xtos_lock a7 // MUST USE highest address register of function to avoid window overflows in critical section
- l32i a3, a4, XTOS_ENABLED_OFS // a3 = xtos_enabled
- l32i a6, a4, XTOS_VPRI_ENABLED_OFS // a6 = xtos_vpri_enabled
- or a5, a3, a2 // a5 = xtos_enabled | mask
- xor a5, a5, a2 // a5 = xtos_enabled & ~mask
- s32i a5, a4, XTOS_ENABLED_OFS // xtos_enabled &= ~mask
- and a5, a5, a6 // a5 = xtos_enabled & xtos_vpri_enabled
-# else
- xtos_lock a7 // MUST USE highest address register of function to avoid window overflows in critical section
- rsr.intenable a3
- //interlock
- or a5, a3, a2 // a5 = INTENABLE | mask
- xor a5, a5, a2 // a5 = INTENABLE & ~mask
-# endif
- wsr.intenable a5
- xtos_unlock a7
- mov a2, a3 // return previous (virtual or real) INTENABLE value
-#else /*XCHAL_HAVE_INTERRUPTS*/
- movi a2, 0 // this config does not have interrupts, so return 0
-#endif /*XCHAL_HAVE_INTERRUPTS*/
- abi_return
-
- .size _xtos_ints_off, . - _xtos_ints_off
-
diff --git a/src/arch/xtensa/smp/xtos/ints-on.S b/src/arch/xtensa/smp/xtos/ints-on.S
deleted file mode 100644
index 8d0795a..0000000
--- a/src/arch/xtensa/smp/xtos/ints-on.S
+++ /dev/null
@@ -1,74 +0,0 @@
-// ints-on.S - Interrupt related assembler code - _xtos_ints_on
-
-// Copyright (c) 2004-2015 Tensilica Inc.
-//
-// Permission is hereby granted, free of charge, to any person obtaining
-// a copy of this software and associated documentation files (the
-// "Software"), to deal in the Software without restriction, including
-// without limitation the rights to use, copy, modify, merge, publish,
-// distribute, sublicense, and/or sell copies of the Software, and to
-// permit persons to whom the Software is furnished to do so, subject to
-// the following conditions:
-//
-// The above copyright notice and this permission notice shall be included
-// in all copies or substantial portions of the Software.
-//
-// THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
-// EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
-// MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
-// IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY
-// CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
-// TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
-// SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
-
-#include <xtensa/coreasm.h>
-#include "xtos-internal.h"
-
-
-/***************************************************************************
- * _xtos_ints_on() and _xtos_ints_off() are used
- * to enable and disable interrupts from C code;
- * they can be called from the application or from a C interrupt handler.
- */
-
-
-// u32 _xtos_ints_on( u32 mask );
-// Enables a set of interrupts.
-// With INTENABLE virtualizing, does not simply set INTENABLE directly, but rather
-// computes it as a function of the current virtual priority.
-//
-// MUST NOT be called when PS.INTLEVEL > XTOS_LOCKLEVEL
-// (otherwise PS.INTLEVEL gets lowered; and operation may be inconsistent
-// if this is called in the handler of an interrupt of level > LOCKLEVEL).
-//
- .text
- .align 4
- .global _xtos_ints_on
- .type _xtos_ints_on,@function
-_xtos_ints_on:
- abi_entry
-#if XCHAL_HAVE_INTERRUPTS && (XCHAL_HAVE_XEA1 || XCHAL_HAVE_XEA2)
-# if XTOS_VIRTUAL_INTENABLE
- xtos_addr_percore a4, xtos_intstruct
- xtos_lock a7 // MUST USE highest address register of function to avoid window overflows in critical section
- l32i a3, a4, XTOS_ENABLED_OFS // a3 = xtos_enabled
- l32i a6, a4, XTOS_VPRI_ENABLED_OFS // a6 = xtos_vpri_enabled
- or a5, a3, a2 // xtos_enabled | mask
- s32i a5, a4, XTOS_ENABLED_OFS // xtos_enabled |= mask
- and a5, a5, a6 // a5 = xtos_enabled & xtos_vpri_enabled
-# else
- xtos_lock a7 // MUST USE highest address register of function to avoid window overflows in critical section
- rsr.intenable a3
- //interlock
- or a5, a3, a2 // INTENABLE | mask
-# endif
- wsr.intenable a5
- xtos_unlock a7
- mov a2, a3 // return previous (virtual or real) INTENABLE value
-#else /*XCHAL_HAVE_INTERRUPTS*/
- movi a2, 0 // this config does not have interrupts, so return 0
-#endif /*XCHAL_HAVE_INTERRUPTS*/
- abi_return
-
- .size _xtos_ints_on, . - _xtos_ints_on
-
diff --git a/src/arch/xtensa/smp/xtos/kernel-vector.S b/src/arch/xtensa/smp/xtos/kernel-vector.S
deleted file mode 100644
index 3f86b0e..0000000
--- a/src/arch/xtensa/smp/xtos/kernel-vector.S
+++ /dev/null
@@ -1,73 +0,0 @@
-// kernel-vector.S - Kernel Vector for General Exceptions
-// $Id: //depot/rel/Foxhill/dot.8/Xtensa/OS/xtos/kernel-vector.S#1 $
-
-// Copyright (c) 1999-2015 Tensilica Inc.
-//
-// Permission is hereby granted, free of charge, to any person obtaining
-// a copy of this software and associated documentation files (the
-// "Software"), to deal in the Software without restriction, including
-// without limitation the rights to use, copy, modify, merge, publish,
-// distribute, sublicense, and/or sell copies of the Software, and to
-// permit persons to whom the Software is furnished to do so, subject to
-// the following conditions:
-//
-// The above copyright notice and this permission notice shall be included
-// in all copies or substantial portions of the Software.
-//
-// THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
-// EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
-// MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
-// IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY
-// CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
-// TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
-// SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
-
-/*
- * General exceptions in kernel vector mode (PS.UM==0) go to this kernel
- * vector. This kernel vector does very little.
- * Under normal operation of the single-threaded runtime ("XTOS"), kernel
- * vectored general exceptions do not occur, so nothing needs to be done.
- * However when debugging, such as when writing exception and
- * interrupt handlers, kernel vectored exceptions may occur.
- * They are usually the sign of a bug, so here we take a breakpoint
- * (if debug option enabled) or take drastic action (infinite loop)
- * otherwise.
- *
- * XTOS does not allow exceptions in interrupt or exception handlers.
- * If it did, a more elaborate kernel vector handler would be needed.
- * See the Xtensa Microprocessor Programmer's Guide for an
- * example of how to implement such a kernel vector handler.
- */
-
-#include <xtensa/coreasm.h>
-#include <xtensa/config/system.h>
-#ifdef SIMULATOR
-#include <xtensa/simcall.h>
-#endif
-
-#if XCHAL_HAVE_EXCEPTIONS && (XCHAL_HAVE_XEA1 || XCHAL_HAVE_XEA2)
-
- .begin literal_prefix .KernelExceptionVector
- .section .KernelExceptionVector.text, "ax"
-
- .align 4
- .global _KernelExceptionVector
-_KernelExceptionVector:
-
-# if XCHAL_HAVE_DEBUG
-1: break 1,0 // unexpected kernel exception
-# elif defined(SIMULATOR)
- wsr a2, EXCSAVE1 // save a2 where simulator expects it
- movi a2, SYS_unhandled_kernel_exc
-1: simcall // let simulator/debugger report unhandled exception
-# else
-1:
-# endif
- j 1b // infinite loop - unexpected kernel exception
-
- .size _KernelExceptionVector, . - _KernelExceptionVector
- .text
- .end literal_prefix
-
-#endif /* XCHAL_HAVE_EXCEPTIONS */
-
diff --git a/src/arch/xtensa/smp/xtos/memctl_default.S b/src/arch/xtensa/smp/xtos/memctl_default.S
deleted file mode 100644
index 164f2c2..0000000
--- a/src/arch/xtensa/smp/xtos/memctl_default.S
+++ /dev/null
@@ -1,42 +0,0 @@
-// memctl_default.S - Default startup value for MEMCTL register.
-
-// Copyright (c) 1998-2015 Cadence Design Systems, Inc.
-//
-// Permission is hereby granted, free of charge, to any person obtaining
-// a copy of this software and associated documentation files (the
-// "Software"), to deal in the Software without restriction, including
-// without limitation the rights to use, copy, modify, merge, publish,
-// distribute, sublicense, and/or sell copies of the Software, and to
-// permit persons to whom the Software is furnished to do so, subject to
-// the following conditions:
-//
-// The above copyright notice and this permission notice shall be included
-// in all copies or substantial portions of the Software.
-//
-// THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
-// EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
-// MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
-// IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY
-// CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
-// TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
-// SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
-
-
-#include <xtensa/coreasm.h>
-#include <xtensa/config/system.h>
-
-
-// This file just contains this one symbol, used by the reset code.
-// It is here rather than in reset-vector.S because we want the symbol
-// to be external, so resolution is delayed until link time.
-//
-// To define your own value to override this default, redefine the
-// symbol __memctl_default to the desired value, e.g. -
-//
-// xt-xcc test.c -g -o test -Wl,--defsym=__memctl_default=0x08080808
-//
-
- .global __memctl_default
- .weak __memctl_default
- .equ __memctl_default, XCHAL_CACHE_MEMCTL_DEFAULT
-
diff --git a/src/arch/xtensa/smp/xtos/memep-enable.S b/src/arch/xtensa/smp/xtos/memep-enable.S
deleted file mode 100644
index c372420..0000000
--- a/src/arch/xtensa/smp/xtos/memep-enable.S
+++ /dev/null
@@ -1,63 +0,0 @@
-// memep-enable.S -- Turn on local memory ECC/parity checking
-// $Id: //depot/rel/Foxhill/dot.8/Xtensa/OS/xtos/memep-enable.S#1 $
-
-// Copyright (c) 2006-2010 Tensilica Inc.
-//
-// Permission is hereby granted, free of charge, to any person obtaining
-// a copy of this software and associated documentation files (the
-// "Software"), to deal in the Software without restriction, including
-// without limitation the rights to use, copy, modify, merge, publish,
-// distribute, sublicense, and/or sell copies of the Software, and to
-// permit persons to whom the Software is furnished to do so, subject to
-// the following conditions:
-//
-// The above copyright notice and this permission notice shall be included
-// in all copies or substantial portions of the Software.
-//
-// THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
-// EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
-// MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
-// IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY
-// CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
-// TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
-// SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
-
-#include <xtensa/coreasm.h>
-
-
- /*
- * void _xtos_memep_enable(int flags);
- *
- * Turn on local memory ECC/parity checking, for both
- * data access and instruction fetch.
- *
- * For now, flags are ignored. Caller is expected to pass zero.
- *
- * _xtos_memep_initrams() must have already been called, if necessary,
- * to ensure all ECC/parity bits are valid in any local instruction
- * or data RAM. The normal reset vector sequence already takes care
- * of initializing any local cache ECC/parity bits.
- */
- .text
- .align 4
- .global _xtos_memep_enable
-_xtos_memep_enable:
- abi_entry
-
-#if XCHAL_HAVE_MEM_ECC_PARITY
-
- // Local Memory ECC/Parity option initialization
- //
- // NOTE: We turn on exceptions on correctable errors and correct
- // them in the memory error handler.
- movi a2, MESR_ERRENAB | MESR_DATEXC | MESR_INSEXC
- wsr a2, MESR
- isync
-
-#endif /* XCHAL_HAVE_MEM_ECC_PARITY */
-
- movi a2, 0 // successfully turned on what we could
- abi_return
-
- .size _xtos_memep_enable, . - _xtos_memep_enable
-
diff --git a/src/arch/xtensa/smp/xtos/memep-initrams.S b/src/arch/xtensa/smp/xtos/memep-initrams.S
deleted file mode 100644
index 8cc399e..0000000
--- a/src/arch/xtensa/smp/xtos/memep-initrams.S
+++ /dev/null
@@ -1,91 +0,0 @@
-// memep-initrams.S -- Initialize local memory ECC/parity
-// $Id: //depot/rel/Foxhill/dot.8/Xtensa/OS/xtos/memep-initrams.S#1 $
-
-// Copyright (c) 2006-2010 Tensilica Inc.
-//
-// Permission is hereby granted, free of charge, to any person obtaining
-// a copy of this software and associated documentation files (the
-// "Software"), to deal in the Software without restriction, including
-// without limitation the rights to use, copy, modify, merge, publish,
-// distribute, sublicense, and/or sell copies of the Software, and to
-// permit persons to whom the Software is furnished to do so, subject to
-// the following conditions:
-//
-// The above copyright notice and this permission notice shall be included
-// in all copies or substantial portions of the Software.
-//
-// THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
-// EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
-// MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
-// IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY
-// CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
-// TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
-// SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
-
-#include <xtensa/coreasm.h>
-
-
- /*
- * void _xtos_memep_initrams(void);
- *
- * Most reset vectors initialize caches, leaving only the local memories
- * (instruction and data RAMs) with potentially some words that have
- * not been written to and thus have uninitialized ECC/parity bits.
- * Loading such a word after enabling ECC/parity checking would result
- * in an exception (or memory error reported in MESR). To avoid this,
- * an application must either carefully avoid loading from uninitialized
- * words, or ensure it writes to every instruction and data RAM word.
- * The latter is what this function does. It reads and writes every
- * word of every local instruction and data RAM. It should normally
- * be called with interrupts disabled. An interrupt might come in
- * between a load and store, in which case any modification made by the
- * interrupt handler to that local memory location is lost when this
- * function resumes and does the store. If no interrupt handler makes
- * any persistent modification to local memories, disabling them around
- * a call to this function may be unnecessary.
- *
- * On the simulator (ISS), everything comes up zeroed, so no there is
- * no need for this initialization.
- */
- .text
- .align 4
- .global _xtos_memep_initrams
-_xtos_memep_initrams:
- abi_entry
-
- // Local Memory ECC/Parity option initialization
-#if XCHAL_HAVE_MEM_ECC_PARITY && (XCHAL_NUM_DATARAM || XCHAL_NUM_INSTRAM /*|| XCHAL_NUM_URAM || XCHAL_NUM_XLMI*/) && !defined(SIMULATOR)
- .section .rodata, "a"
- .align 4
-.L_locmemep_start:
-# if XCHAL_NUM_DATARAM >= 1 && XCHAL_DATARAM0_ECC_PARITY
- .long XCHAL_DATARAM0_VADDR, XCHAL_DATARAM0_VADDR+XCHAL_DATARAM0_SIZE
-# endif
-# if XCHAL_NUM_DATARAM >= 2 && XCHAL_DATARAM1_ECC_PARITY
- .long XCHAL_DATARAM1_VADDR, XCHAL_DATARAM1_VADDR+XCHAL_DATARAM1_SIZE
-# endif
-# if XCHAL_NUM_INSTRAM >= 1 && XCHAL_INSTRAM0_ECC_PARITY
- .long XCHAL_INSTRAM0_VADDR, XCHAL_INSTRAM0_VADDR+XCHAL_INSTRAM0_SIZE
-# endif
-# if XCHAL_NUM_INSTRAM >= 2 && XCHAL_INSTRAM1_ECC_PARITY
- .long XCHAL_INSTRAM1_VADDR, XCHAL_INSTRAM1_VADDR+XCHAL_INSTRAM1_SIZE
-# endif
-.L_locmemep_end:
- .text
- movi a5, .L_locmemep_start // start of table of local memory ranges
- movi a6, .L_locmemep_end // end of table ...
-2: l32i a3, a5, 0 // start of local memory
- l32i a4, a5, 4 // end of local memory
- addi a5, a5, 8 // (next entry in table)
-1: l32i a2, a3, 0 // load and store every word of local memory...
- s32i a2, a3, 0 // ... to initialize all parity and/or ECC bits
- addi a3, a3, 4
- bltu a3, a4, 1b // loop until whole memory initialized
- bltu a5, a6, 2b // loop until all memories initialized
- // ECC/parity bits are now initialized, checking can be turned on.
-#endif /* ECC/parity on instruction or data RAM(s) */
-
- abi_return
-
- .size _xtos_memep_initrams, . - _xtos_memep_initrams
-
diff --git a/src/arch/xtensa/smp/xtos/memerror-vector.S b/src/arch/xtensa/smp/xtos/memerror-vector.S
deleted file mode 100644
index 460b58a..0000000
--- a/src/arch/xtensa/smp/xtos/memerror-vector.S
+++ /dev/null
@@ -1,581 +0,0 @@
-/* memerror-vector.S -- Memory Error Exception Vector and Handler */
-
-/* $Id: //depot/rel/Foxhill/dot.8/Xtensa/OS/xtos/memerror-vector.S#1 $ */
-
-/*
- * Copyright (c) 2006-2013 Tensilica Inc.
- *
- * Permission is hereby granted, free of charge, to any person obtaining
- * a copy of this software and associated documentation files (the
- * "Software"), to deal in the Software without restriction, including
- * without limitation the rights to use, copy, modify, merge, publish,
- * distribute, sublicense, and/or sell copies of the Software, and to
- * permit persons to whom the Software is furnished to do so, subject to
- * the following conditions:
- *
- * The above copyright notice and this permission notice shall be included
- * in all copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
- * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
- * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
- * IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY
- * CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
- * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
- * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
- */
-
-
-/*
- * This handler supports multiple user hooks to handle various cases.
- * This is the list of available hooks:
- *
- * _xtos_merr_hook_fatal_dme -- fatal error, double memory exception
- * _xtos_merr_hook_uncorrectable_local -- fatal error, uncorrectable error in IRAM/DRAM
- * _xtos_merr_hook_uncor_dtag -- fatal error, uncorrectable error in dcache tag
- * _xtos_merr_hook_uncor_dirty -- fatal error, uncorrectable error in dirty dcache data
- * _xtos_merr_hook_icache_relock -- non-fatal, hook to relock icache
- * _xtos_merr_hook_dcache_relock -- non-fatal, hook to relock dcache
- * _xtos_merr_hook_nonfatal -- non-fatal, correctable error
- */
-
-
-#include <xtensa/coreasm.h>
-#include <xtensa/corebits.h>
-
-#if XCHAL_HAVE_MEM_ECC_PARITY
-# if defined(__SPLIT__vector)
-
- // Place this code in the memory error exception vector:
- .begin literal_prefix .MemoryExceptionVector
- .section .MemoryExceptionVector.text, "ax"
-
- .global _MemErrorVector
- .align 4
-_MemErrorVector:
-# if 0 /* XCHAL_HAVE_DEBUG */
- // Memory errors raise PS.INTLEVEL above DEBUGLEVEL, so
- // break instructions have no effect within them (debug
- // exceptions are masked). So leave commented out for now.
- break 1, 5 // unhandled memory error exception
-# endif
- xsr.mesave a0
- jx a0
-
- .size _MemErrorVector, . - _MemErrorVector
- .text
- .end literal_prefix
-
-
-# elif defined(__SPLIT__handler)
-
-/*
- * Some rules and assumptions:
- *
- * Anything that can interrupt this handler (e.g. NMI):
- * - must not lock or unlock cache lines
- */
-
-
-#define ICACHE_WAYWIDTH (XCHAL_ICACHE_SETWIDTH + XCHAL_ICACHE_LINEWIDTH) /* LICT's "iis" */
-#define DCACHE_WAYWIDTH (XCHAL_DCACHE_SETWIDTH + XCHAL_DCACHE_LINEWIDTH) /* LDCT's "dis" */
-/* NOTE: Memory ECC/parity is not supported on XLMI or on local ROMs: */
-#define HAVE_LOCAL_RAM (XCHAL_NUM_DATARAM || XCHAL_NUM_INSTRAM /*|| XCHAL_NUM_URAM || XCHAL_NUM_XLMI*/)
-
-
-#if XCHAL_DCACHE_LINE_LOCKABLE && XCHAL_DCACHE_WAYS > 1 && XCHAL_HAVE_PREFETCH
- .comm _MemErrorSave, 12, 4
-#else
- //.lcomm _MemErrorSave, 8
- .comm _MemErrorSave, 8, 4
-#endif
-
- .text
- .align 4
- .global _MemErrorHandler
-_MemErrorHandler:
- hw_erratum_487_fix
- rsr.mesr a0
- bbsi.l a0, MESR_DME_SHIFT, .L_fatal_dme
-# if XCHAL_ICACHE_SIZE > 0 || XCHAL_DCACHE_SIZE > 0
- bbsi.l a0, MESR_MEMTYPE_SHIFT+1, .L_cache // branch if error on a cache
-# endif
- // Error in a local memory.
-# if HAVE_LOCAL_RAM
- bbsi.l a0, MESR_ERRTYPE_SHIFT, .L_uncorrectable_local
- // Correctable error in a local memory (IRAM or DRAM).
- // (MEVADDR has all 32 bits, so XSR preserves a register:)
- xsr.mevaddr a2
- // Note: MEVADDR is always 4-byte aligned,
- // so we can just do L32I/S32I to correct the error.
- // However, that's not atomic, and NMI can store in between;
- // that's usually a problem for D rather than I, avoid the
- // issue using S32C1I if configured (else NMI must not write DataRAM!?!):
-# if (XCHAL_HAVE_S32C1I && (XCHAL_NUM_DATARAM /*|| XCHAL_NUM_URAM || XCHAL_NUM_XLMI*/))
- bbci.l a0, MESR_MEMTYPE_SHIFT, .L_instram // branch if error on InstRAM
- // Unfortunately we need 3 registers to do S32C1I (data,addr,SCOMPARE1) so
- // we need to save to _MemErrorSave:
- movi a0, _MemErrorSave
- s32i a4, a0, 0 // save a4
- l32i a4, a2, 0 // load data (re-correct)
- rsr.scompare1 a0 // save SCOMPARE1
- wsr.scompare1 a4
- s32c1i a4, a2, 0 // store if still contains same value (else other store corrected error)
- movi a4, _MemErrorSave
- wsr.scompare1 a0 // restore SCOMPARE1
- l32i a4, a4, 0 // restore a4
- j 2f
-.L_instram:
-# endif
- l32i a0, a2, 0 // load data (re-correct)
- s32i a0, a2, 0 // store data to correct ECC bits
-2: xsr.mevaddr a2
-# endif /* HAVE_LOCAL_RAM */
-
-
- // Weak reference: if unresolved, links okay but with zero value:
- //
- // This hook must return using a RET instruction. It will receive
- // the return address in a0, and the MESR register value in a2.
- // The hook may use and trash a2 and a3, but all other registers
- // must be preserved.
-
- .weak _xtos_merr_hook_nonfatal
-
-.L_done:
- // Finished, now see if there is a user hook to call before returning
- movi a0, _xtos_merr_hook_nonfatal // hook address
- beqz a0, 1f // no hook, return
- movi a0, _MemErrorSave // save area address
- s32i a2, a0, 0 // save a2
- s32i a3, a0, 4 // save a3
- movi a0, _xtos_merr_hook_nonfatal // re-load hook address
- rsr.mesr a2 // pass MESR value as arg
- callx0 a0 // call user hook
- movi a3, _MemErrorSave
- l32i a2, a3, 0 // restore a2
- l32i a3, a3, 4 // restore a3
-1: movi a0, _MemErrorHandler // handler address
- xsr.mesave a0 // restore a0 and MESAVE
- rfme
-
-
- // Weak reference: if unresolved, links okay but with zero value:
- .weak _xtos_merr_hook_fatal_dme
-.L_fatal_dme:
- // Fatal (unrecoverable) error, double memory exception
- movi a0, _xtos_merr_hook_fatal_dme
-1: beqz a0, 1b // fatal double memory error, no hook, so infinite loop
- jx a0 // jump to user hook, if present
-
-
-# if HAVE_LOCAL_RAM
- // Weak reference: if unresolved, links okay but with zero value:
- .weak _xtos_merr_hook_uncorrectable_local
-.L_uncorrectable_local:
- // Fatal (unrecoverable) error in IRAM or DRAM: parity or uncorrectable ECC error
- movi a0, _xtos_merr_hook_uncorrectable_local
-1: beqz a0, 1b // fatal memory error, no hook provided, so infinite loop
- jx a0 // jump to user hook, if present
-# endif
-
-
-# if XCHAL_ICACHE_SIZE > 0 || XCHAL_DCACHE_SIZE > 0
-.L_cache:
- // Error in one of the caches.
-# endif
-
-# if XCHAL_ICACHE_SIZE > 0 && XCHAL_HAVE_ICACHE_TEST
-# if XCHAL_DCACHE_SIZE > 0 && XCHAL_HAVE_DCACHE_TEST
- bbsi.l a0, MESR_MEMTYPE_SHIFT, .L_dcache // branch if data cache error
-# endif
- // Error in the instruction cache.
- bbsi.l a0, MESR_ERRTYPE_SHIFT, .L_icache_noncorr // branch if uncorrectable
- // Correctable error in the instruction cache.
- xsr.mevaddr a2
- // TODO FIXME: remove these 5 lines if waynum is in MEVADDR!? by using III if tag and IHI otherwise!?!?!?:
-# if XCHAL_ICACHE_WAYS > 1
- extui a0, a0, MESR_WAYNUM_SHIFT, 2
- slli a0, a0, ICACHE_WAYWIDTH
- slli a2, a2, 32 - ICACHE_WAYWIDTH
- srli a2, a2, 32 - ICACHE_WAYWIDTH
- or a2, a2, a0
-# endif
-# if XCHAL_ICACHE_LINE_LOCKABLE
- // Preserve the lock bit. So check the tag...
- lict a0, a2 // load i-cache tag
- bbci.l a0, XCHAL_ICACHE_TAG_L_SHIFT, .L_icache_corr_unlocked // branch if unlocked
- // Correctable error in a locked instruction cache line.
- // Fix both tag and one word, quicker than figuring out whether error is in tag or data:
- sict a0, a2 // fix tag
- // TODO FIXME: on fetch wider than 32-bits, SICW might replicate its 32 bits to the
- // whole fetch width rather than just write 32-bits, depending on how customer wires up
- // I-cache RAMs. With ECC option and I-cache locking, they need 32-bit word write enables.
- licw a0, a2
- sicw a0, a2 // fix data word
- j .L_icache_done
-.L_icache_corr_unlocked:
- // We have to write the whole tag to avoid hitting an error here (if tag error).
- // So use IIU (which also invalidates) not III (which reads L bit so can hit error).
- iiu a2, 0 // unlock line ==> also invalidates! (I-side only)
-# else
- iii a2, 0 // invalidate line (whole set!)
-# endif
-.L_icache_done:
- xsr.mevaddr a2
- j .L_done
-
-.L_icache_noncorr:
- // Non-correctable error in the instruction cache.
- bbsi.l a0, MESR_MEMTYPE_SHIFT+2, .L_icache_tag_noncorr // branch if tag error
- // Non-correctable error in the instruction cache data.
- // Just invalidate the line if we can.
-# if XCHAL_ICACHE_LINE_LOCKABLE
- // If locked, need a different fix sequence.
- xsr.mevaddr a2
-
-# if XCHAL_ICACHE_WAYS > 1
- // This sequence is shorter, but does not retain original MEVADDR so
- // prevents subsequent use of instructions requiring a virtual address
- // (such as LICW, IPFL, etc):
-// extui a0, a0, MESR_WAYNUM_SHIFT, 2
-// slli a0, a0, ICACHE_WAYWIDTH
-// slli a2, a2, 32 - ICACHE_WAYWIDTH
-// srli a2, a2, 32 - ICACHE_WAYWIDTH
-// or a2, a2, a0
-
- extui a0, a0, MESR_WAYNUM_SHIFT, 2 // id of way with mem error
- slli a0, a0, ICACHE_WAYWIDTH
- xor a0, a2, a0 // xor corresponding bits of addr
- extui a0, a0, ICACHE_WAYWIDTH, 2 // take 2 xor'ed way bits
- or a2, a2, a0 // save them at bottom of addr
- slli a0, a0, ICACHE_WAYWIDTH
- xor a2, a2, a0 // and change 2 way bits of addr
-# endif
- lict a0, a2
- bbsi.l a0, XCHAL_ICACHE_TAG_L_SHIFT, .L_icache_locked_uncor // branch if locked
- // Cache line is not locked, just invalidate:
-# if XCHAL_ICACHE_WAYS > 1
- iii a2, 0
-# else
- ihi a2, 0
-# endif
- j .L_icache_done
-
- // NOTE: we don't use the LICW/SICW sequence below unless the line is locked,
- // otherwise the i-cache line might get replaced between LICW and SICW
- // (if we're not extremely careful), which would be disastrous.
- // Also, for locked lines, LICW/SICW is much safer than IHU/IHI/IPFL
- // because it doesn't leave a window where the line is unlocked;
- // however, if the error is non-correctable, we have no choice.
-
-.L_icache_locked_uncor:
- // If locked and uncorrectable however, the only recourse is relocking.
- // So we need to recover the virtual address so we can do IPFL.
- // Note: can't use MEPC instead of MEVADDR, because (a) it might not
- // point to the correct cache line, and (b) it might be completely wrong
- // in the case where the mem error happened e.g. during an LICW or IPFL.
-# if XCHAL_ICACHE_WAYS > 1
- // Recover virtual address in a2:
- extui a0, a2, 0, 2 // get saved xor'ed bits at bottom
- slli a0, a0, ICACHE_WAYWIDTH // line them up
- xor a2, a2, a0 // restore original MEVADDR
-# endif
- ihu a2, 0 // unlock line
- ihi a2, 0 // invalidate line
- ipfl a2, 0 // refetch-and-lock the line
- j .L_icache_done
-# else /* LOCKABLE */
- rsr.mevaddr a0
- ihi a0, 0 // invalidate that cache line
- j .L_done
-# endif /* LOCKABLE */
-
-.L_icache_tag_noncorr:
- // Non-correctable error in the instruction cache tag.
- // Just invalidate the tag or the entire set.
-# if XCHAL_ICACHE_LINE_LOCKABLE
- // Note:
- // With i-cache locking, IIU writes the entire tag without mem-error check,
- // and III writes part of it (leaves lock bit alone) so can hit errors.
- // Without i-cache locking, III writes the entire tag without mem-error check.
- // (Original assumption was that SICT is needed.)
-# if XCHAL_ICACHE_WAYS > 1
- // TODO FIXME: avoid this 8-line alternative if waynum is in MEVADDR!?:
- xsr.mevaddr a2
- extui a0, a0, MESR_WAYNUM_SHIFT, 2
- slli a0, a0, ICACHE_WAYWIDTH
- slli a2, a2, 32 - ICACHE_WAYWIDTH
- srli a2, a2, 32 - ICACHE_WAYWIDTH
- or a2, a2, a0
- iiu a2, 0 // unlock line ==> also invalidates! (I-side only)
- xsr.mevaddr a2
-# else
- rsr.mevaddr a0
- iiu a0, 0 // unlock line ==> also invalidates! (I-side only)
-# endif
- // If line was locked, can't recover lock state, need external info to recover.
- // User can provide an assembler hook routine _xtos_merr_hook_icache_relock
- // to relock the icache at the index in a2:
- // - any number of lines might still be locked at that index,
- // including all of them
- // - no stack is provided, a0 must be used as starting point to
- // load a save area and saved registers as necessary
- // - unless routine just does ret (i.e. does not modify any
- // register, only possible if it does nothing), it needs to
- // return by restoring all registers it modified, ending with:
- // movi a0, _MemErrorHandler
- // xsr.mesave a0
- // rfme
- // CAVEAT EMPTOR: this hook mechanism is subject to change.
- .weak _xtos_merr_hook_icache_relock // if unresolved, links with zero value
- movi a0, _xtos_merr_hook_icache_relock
-1: beqz a0, 1b // if no hook to recover lock state on icache tag mem error, loop forever
- callx0 a0 // invoke user hook to relock i-cache (index in MEVADDR)
-# else
- rsr.mevaddr a0
- iii a0, 0 // invalidate entire set
-# endif
- j .L_done
-# endif /* have ICACHE */
-
-
-# if XCHAL_DCACHE_SIZE > 0 && XCHAL_HAVE_DCACHE_TEST
-# if XCHAL_ICACHE_SIZE > 0 && XCHAL_HAVE_ICACHE_TEST
-.L_dcache:
-# endif
- // Error in the data cache.
-# if XCHAL_DCACHE_IS_WRITEBACK || XCHAL_DCACHE_LINE_LOCKABLE
- bbsi.l a0, MESR_ERRTYPE_SHIFT, .L_dcache_noncorr // branch if uncorrectable
- // Uncorrectable error on a writeback dcache might be unrecoverable:
-# endif
- bbsi.l a0, MESR_MEMTYPE_SHIFT+2, .L_dcache_tag // branch if tag error
- // Error in the data cache data (correctable, or non-correctable in writethru+unlockable cache).
- // MEVADDR always a real vaddr here; might point to cache-isolate mode area though.
-# if XCHAL_DCACHE_LINE_LOCKABLE
- // Correctable error on lockable dcache data.
- // If locked, need to refetch the line (or load/store its contents, which is less safe):
- xsr.mevaddr a2
-# if XCHAL_DCACHE_WAYS > 1
- // Need some extra computation to get the correct dcache way's tag:
- movi a0, _MemErrorSave
- s32i a4, a0, 0 // save a4
- s32i a5, a0, 4 // save a5
-# if XCHAL_HAVE_PREFETCH
- s32i a6, a0, 8 // save a6
- movi a6, 0
- xsr.prefctl a6 // disable prefetch during LDCT (issue TENX-24760)
-# endif
- rsr.mesr a4
- extui a4, a4, MESR_WAYNUM_SHIFT, 2
- slli a4, a4, DCACHE_WAYWIDTH
- slli a5, a2, 32 - DCACHE_WAYWIDTH
- srli a5, a5, 32 - DCACHE_WAYWIDTH
- add a4, a4, a5
- mov a5, a0
- ldct a0, a4
- l32i a4, a5, 0 // restore a4
-# if XCHAL_HAVE_PREFETCH
- wsr.prefctl a6 // restore prefetch
- l32i a6, a5, 8 // restore a6
-# endif
- l32i a5, a5, 4 // restore a5
-# else
-# if XCHAL_HAVE_PREFETCH
- movi a0, _MemErrorSave
- s32i a4, a0, 0 // save a4
- movi a4, 0
- xsr.prefctl a4 // disable prefetch during LDCT (issue TENX-24760)
-# endif
- ldct a0, a2 // invalidate and unlock that cache tag
-# if XCHAL_HAVE_PREFETCH
- wsr.prefctl a4 // restore prefetch
- movi a4, _MemErrorSave
- l32i a4, a4, 0 // restore a4
-# endif
-# endif
- // FIXME: if castout, a2 is a cache index (see PR 24103), from which
- // we can construct a physical address! need that paddr reconstruction,
- // and doesn't work with any address translation.
-# if 0 /* translation */
- movi a4, _xtos_vmap_vaddr // FIXME: do we need two variables for full MMU?
-1: beqz a4, 1b // if no vaddr to use, loop forever (FIXME: caxlt: could assume V==P)
- rdtlb1 a5, a4 // save current contents
- ... clear lower bits of a4 ...
- xx = some function of a2
- wdtlb xx, a4
- a2 = virtual address, i.e. some function of a2 and a4 ...
- ... do the sequence below ...
- ...
- wdtlb a5, a4 // restore TLB entry
-# endif
- // NOTE: the following sequence leaves the line temporarily unlocked, if locked.
- // We assume NMI handlers don't lock lines or rely on their being locked.
- // We could have used "l32i a0,a2,0; s32i a0,a2,0" but that's not atomic on the data.
- dhu a2, 0 // unlock the cache line, if locked
- dhwbi a2, 0 // writeback and invalidate cache line
- bbci.l a0, XCHAL_DCACHE_TAG_L_SHIFT, 1f
- dpfl a2, 0 // re-prefetch-and-lock the cache line
-1: xsr.mevaddr a2
-# else /* LOCKABLE */
- // Error in unlockable data cache data (correctable, or non-correctable in writethru cache).
- rsr.mevaddr a0
- // USELESS NOTE: if writethru dcache and NMI handlers don't store to this, we could use DHI instead:
- // FIXME: if castout, a0 is a physical address! doesn't work with any address translation.
- dhwbi a0, 0 // writeback (if correctable) and invalidate that cache line
-# endif /* LOCKABLE */
- j .L_done
-
-.L_dcache_tag:
- // Error in data cache tag (correctable, or non-correctable in writethru+unlockable cache).
- // MEVADDR only contains cache index here (not waynum), don't expect a vaddr (the ISA
- // says upper bits are undefined; actual hw does put a vaddr, but in future might not).
- // Whether or not correctable, just invalidate the particular way's line:
- xsr.mevaddr a2
- // NOTE: could remove these 5 lines if hw were designed with waynum in MEVADDR (but is not):
-# if XCHAL_DCACHE_WAYS > 1
- extui a0, a0, MESR_WAYNUM_SHIFT, 2
- slli a0, a0, DCACHE_WAYWIDTH
- slli a2, a2, 32 - DCACHE_WAYWIDTH
- srli a2, a2, 32 - DCACHE_WAYWIDTH
- or a2, a2, a0
-# endif
-# if XCHAL_DCACHE_LINE_LOCKABLE
-# if XCHAL_HAVE_PREFETCH
- movi a0, _MemErrorSave
- s32i a4, a0, 0 // save a4
- movi a4, 0
- xsr.prefctl a4 // disable prefetch during LDCT (issue TENX-24760)
-# endif
- ldct a0, a2 // invalidate and unlock that cache tag
-# if XCHAL_HAVE_PREFETCH
- wsr.prefctl a4 // restore prefetch
- movi a4, _MemErrorSave
- l32i a4, a4, 0 // restore a4
-# endif
- bbci.l a0, XCHAL_DCACHE_TAG_L_SHIFT, 1f // branch if not locked
- sdct a0, a2 // if locked, this safely writes whole tag
-# endif
-1: diwbi a2, 0 // writeback (if correctable) and invalidate the line
- xsr.mevaddr a2
- j .L_done
-
-
-
-# if XCHAL_DCACHE_IS_WRITEBACK || XCHAL_DCACHE_LINE_LOCKABLE
-.L_dcache_noncorr:
- // Uncorrectable error on a (writeback and/or lockable) data cache.
-# if XCHAL_DCACHE_IS_WRITEBACK
- // On tag errors we don't know whether the line is dirty, so this is unrecoverable:
- bbsi.l a0, MESR_MEMTYPE_SHIFT+2, .L_uncorrectable_dtag // branch if tag error
- // Castouts are by definition dirty, uncorrectable errors on these are unrecoverable:
- bbsi.l a0, MESR_ACCTYPE_SHIFT, .L_uncorrectable_dirty // branch if castout
- // Note: could still be an error on dirty dcache data, also unrecoverable.
-# else
- bbsi.l a0, MESR_MEMTYPE_SHIFT+2, .L_dcache_tag_noncorr // branch if tag error
-# endif
- // Uncorrectable error in dcache data.
- // May be dirty or locked, so get tag to find out.
- xsr.mevaddr a2
-# if XCHAL_DCACHE_WAYS > 1
- extui a0, a0, MESR_WAYNUM_SHIFT, 2 // id of way with mem error
- slli a0, a0, DCACHE_WAYWIDTH
- xor a0, a2, a0 // xor corresponding bits of addr
- extui a0, a0, DCACHE_WAYWIDTH, 2 // take 2 xor'ed way bits
- or a2, a2, a0 // save them at bottom of addr
- slli a0, a0, DCACHE_WAYWIDTH
- xor a2, a2, a0 // and change 2 way bits of addr
-# endif
-# if XCHAL_HAVE_PREFETCH
- movi a0, _MemErrorSave
- s32i a4, a0, 0 // save a4
- movi a4, 0
- xsr.prefctl a4 // disable prefetch during LDCT (issue TENX-24760)
-# endif
- ldct a0, a2 // get dcache tag
-# if XCHAL_HAVE_PREFETCH
- wsr.prefctl a4 // restore prefetch
- movi a4, _MemErrorSave
- l32i a4, a4, 0 // restore a4
-# endif
-# if XCHAL_DCACHE_IS_WRITEBACK
- bbsi.l a0, XCHAL_DCACHE_TAG_D_SHIFT, .L_uncorrectable_dirty_2 // branch if dirty
-# endif
- // Data cache line is clean.
-# if XCHAL_DCACHE_LINE_LOCKABLE
- bbsi.l a0, XCHAL_DCACHE_TAG_L_SHIFT, .L_dcache_nc_locked
-# endif
- // Data cache line is clean and unlocked. Just invalidate it.
- // FIXME: any stores to this line by an NMI handler will be lost.
- // On the other hand, if we use DHWBI, any stores by an NMI handler
- // that don't happen to fix the error result in an unrecoverable castout.
- //
-# if XCHAL_DCACHE_WAYS > 1
- // Recover virtual address in a2:
- extui a0, a2, 0, 2 // get saved xor'ed bits at bottom
- slli a0, a0, DCACHE_WAYWIDTH // line them up
- xor a2, a2, a0 // restore original MEVADDR
-# endif
- dhi a2, 0 // invalidate that data cache line
- xsr.mevaddr a2
- j .L_done
-
-# if XCHAL_DCACHE_LINE_LOCKABLE
-.L_dcache_nc_locked:
-# if XCHAL_DCACHE_WAYS > 1
- // Recover virtual address in a2:
- extui a0, a2, 0, 2 // get saved xor'ed bits at bottom
- slli a0, a0, DCACHE_WAYWIDTH // line them up
- xor a2, a2, a0 // restore original MEVADDR
-# endif
- // Unlock, invalidate, and relock it:
- dhu a2, 0 // unlock that data cache line
- dhi a2, 0 // invalidate that data cache line
- dpfl a2, 0 // prefetch-and-lock the line again
- xsr.mevaddr a2
- j .L_done
-# endif
-
-# if XCHAL_DCACHE_IS_WRITEBACK
- // Weak reference: if unresolved, links okay but with zero value:
- .weak _xtos_merr_hook_uncor_dtag
-.L_uncorrectable_dtag:
- // Fatal (unrecoverable) error in dcache tag (maybe dirty): parity or uncorrectable ECC error
- movi a0, _xtos_merr_hook_uncor_dtag
-1: beqz a0, 1b // fatal non-corr dcache tag, no hook, so infinite loop
- jx a0 // jump to user hook, if present
-
- // Weak reference: if unresolved, links okay but with zero value:
- .weak _xtos_merr_hook_uncor_dirty
-.L_uncorrectable_dirty_2:
- xsr.mevaddr a2
-.L_uncorrectable_dirty:
- // Fatal (unrecoverable) error, parity or non-correctable ECC error on dirty cache data
- movi a0, _xtos_merr_hook_uncor_dirty
-1: beqz a0, 1b // fatal non-corr dirty cache line, no hook, so infinite loop
- jx a0 // jump to user hook, if present
-# else
-.L_dcache_tag_noncorr:
- // Uncorrectable error on a lockable writethru data cache tag.
- // We have to invalidate the line, but that way we lose the lock bit.
- // Provide a hook to relock if necessary (using knowledge outside this module
- // about what needs to be locked). See _xtos_merr_hook_icache_relock for details.
- // CAVEAT EMPTOR: this hook mechanism is subject to change.
- .weak _xtos_merr_hook_dcache_relock // if unresolved, links with zero value
- movi a0, _xtos_merr_hook_dcache_relock
-1: beqz a0, 1b // if no hook to recover lock state on dcache tag mem error, loop forever
- callx0 a0 // invoke user hook to relock d-cache (index in MEVADDR)
- j .L_done
-# endif
-
-# endif /* DCACHE IS WRITEBACK || LINE_LOCKABLE */
-
-# endif /* have DCACHE */
-
- .size _MemErrorHandler, . - _MemErrorHandler
-
-
-
-# endif /* splitting */
-#endif /* XCHAL_HAVE_MEM_ECC_PARITY */
-
diff --git a/src/arch/xtensa/smp/xtos/nmi-vector.S b/src/arch/xtensa/smp/xtos/nmi-vector.S
deleted file mode 100644
index 637dcda..0000000
--- a/src/arch/xtensa/smp/xtos/nmi-vector.S
+++ /dev/null
@@ -1,60 +0,0 @@
-// nmi-vector.S -- Standalone NMI Interrupt Vector/Handler
-// $Id: //depot/rel/Foxhill/dot.8/Xtensa/OS/xtos/nmi-vector.S#1 $
-
-// Copyright (c) 2003, 2006, 2010 Tensilica Inc.
-//
-// Permission is hereby granted, free of charge, to any person obtaining
-// a copy of this software and associated documentation files (the
-// "Software"), to deal in the Software without restriction, including
-// without limitation the rights to use, copy, modify, merge, publish,
-// distribute, sublicense, and/or sell copies of the Software, and to
-// permit persons to whom the Software is furnished to do so, subject to
-// the following conditions:
-//
-// The above copyright notice and this permission notice shall be included
-// in all copies or substantial portions of the Software.
-//
-// THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
-// EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
-// MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
-// IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY
-// CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
-// TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
-// SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
-
-// The NMI exception vector handles non-maskable interrupts.
-
-#include <xtensa/coreasm.h>
-#include <xtensa/config/system.h>
-
-#if XCHAL_HAVE_NMI
-
- .begin literal_prefix .NMIExceptionVector
- .section .NMIExceptionVector.text, "ax"
-
- .align 4
- .global _NMIExceptionVector
-_NMIExceptionVector:
-
-// Insert any custom NMI handling code here.
-// For example:
-// writesr excsave XCHAL_NMILEVEL a0
-// movi a0, ...address of some save area specific to this code...
-// s32i a1, a0, 0 // save whatever registers are needed
-// :
-// do something useful ...
-// :
-// l32i a1, a0, 0 // restore whatever registers were saved
-// readsr excsave XCHAL_NMILEVEL a0
-//
-// This default NMI handler does not do anything. It just returns
-// immediately upon any occurrence of a non-maskable interrupt.
-
- rfi XCHAL_NMILEVEL
-
- .size _NMIExceptionVector, . - _NMIExceptionVector
- .text
- .end literal_prefix
-
-#endif /* XCHAL_HAVE_NMI */
-
diff --git a/src/arch/xtensa/smp/xtos/null-syscall.S b/src/arch/xtensa/smp/xtos/null-syscall.S
deleted file mode 100644
index fb53cf9..0000000
--- a/src/arch/xtensa/smp/xtos/null-syscall.S
+++ /dev/null
@@ -1,38 +0,0 @@
-// null-syscall.S - Stub for Unused SYSCALL Handler
-// $Id: //depot/rel/Foxhill/dot.8/Xtensa/OS/xtos/null-syscall.S#1 $
-
-// Copyright (c) 2006-2010 Tensilica Inc.
-//
-// Permission is hereby granted, free of charge, to any person obtaining
-// a copy of this software and associated documentation files (the
-// "Software"), to deal in the Software without restriction, including
-// without limitation the rights to use, copy, modify, merge, publish,
-// distribute, sublicense, and/or sell copies of the Software, and to
-// permit persons to whom the Software is furnished to do so, subject to
-// the following conditions:
-//
-// The above copyright notice and this permission notice shall be included
-// in all copies or substantial portions of the Software.
-//
-// THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
-// EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
-// MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
-// IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY
-// CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
-// TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
-// SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
-
-
- // Redirect SYSCALL exceptions as not handled, when
- // that functionality is not needed. Done this way, a user can
- // just specify this small handler to override the default one.
-
- .text
- .weak xtos_unhandled_exception
- .global _xtos_syscall_handler
-_xtos_syscall_handler:
- movi a3, xtos_unhandled_exception
-1: beqz a3, 1b
- jx a3
- .size _xtos_syscall_handler, . - _xtos_syscall_handler
-
diff --git a/src/arch/xtensa/smp/xtos/null-vectors.S b/src/arch/xtensa/smp/xtos/null-vectors.S
deleted file mode 100644
index 0bb274d..0000000
--- a/src/arch/xtensa/smp/xtos/null-vectors.S
+++ /dev/null
@@ -1,184 +0,0 @@
-// null-vectors.S - Stubs for Unused Vectors and Handlers
-// $Id: //depot/rel/Foxhill/dot.8/Xtensa/OS/xtos/null-vectors.S#1 $
-
-// Copyright (c) 2006-2010 Tensilica Inc.
-//
-// Permission is hereby granted, free of charge, to any person obtaining
-// a copy of this software and associated documentation files (the
-// "Software"), to deal in the Software without restriction, including
-// without limitation the rights to use, copy, modify, merge, publish,
-// distribute, sublicense, and/or sell copies of the Software, and to
-// permit persons to whom the Software is furnished to do so, subject to
-// the following conditions:
-//
-// The above copyright notice and this permission notice shall be included
-// in all copies or substantial portions of the Software.
-//
-// THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
-// EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
-// MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
-// IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY
-// CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
-// TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
-// SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
-
-
-// NOTE: The simulator version of this file is currently not used,
-// i.e. the SIMULATOR macro is never defined when assembling this file.
-// The relevant simulator code is left here for illustrative purposes only.
-
-
-#include <xtensa/coreasm.h>
-#include "xtos-internal.h"
-#ifdef SIMULATOR
-#include <xtensa/simcall.h>
-#endif
-
- // These are just tiny non-functional vectors and handlers for when
- // their functionality is not being used. They just try to signal
- // the debugger that an unhandled exception or interrupt occurred,
- // and otherwise just spin in a loop.
- //
- // For interrupts levels above DEBUGLEVEL, lowering PS.INTLEVEL
- // for break to work is tricky, and not always possible in a
- // generic fashion without interfering with normal program execution.
- // So for now we don't do it.
-
-
-#if defined(__SPLIT__user)
-
-# if XCHAL_HAVE_EXCEPTIONS
- .begin literal_prefix .UserExceptionVector
- .section .UserExceptionVector.text, "ax"
- .align 4
- .global _UserExceptionVector
-_UserExceptionVector:
-# if XCHAL_HAVE_DEBUG
- break 1, 1 // unexpected user-vectored general exception
-# endif
-1: j 1b // infinite loop - unexpected user-vectored exception
- .size _UserExceptionVector, . - _UserExceptionVector
- .end literal_prefix
-# endif
-
-#elif defined(__SPLIT__level1int)
-
- .text
- .global _xtos_l1int_handler
-_xtos_l1int_handler:
- movi a3, xtos_unhandled_exception
- jx a3
- .size _xtos_l1int_handler, . - _xtos_l1int_handler
-
-#elif defined(__SPLIT__level2)
-
-# if (XCHAL_NUM_INTLEVELS >= 2) && (XCHAL_DEBUGLEVEL != 2)
- .begin literal_prefix .Level2InterruptVector
- .section .Level2InterruptVector.text, "ax"
- .align 4
- .global _Level2Vector
-_Level2Vector:
-# if XCHAL_HAVE_DEBUG && (XCHAL_DEBUGLEVEL > 2)
- break 1, 2 // unexpected high-priority interrupt
-# elif defined(SIMULATOR)
- wsr a2, EXCSAVE_2
- movi a2, SYS_unhandled_highpri_interrupt
- simcall // let simulator/debugger report unhandled level-2 interrupt
-# endif
-1: j 1b // infinite loop - unexpected level-2 interrupt
- .size _Level2Vector, . - _Level2Vector
- .text
- .end literal_prefix
-# endif /* level 2 */
-
-
-#elif defined(__SPLIT__level3)
-
-# if (XCHAL_NUM_INTLEVELS >= 3) && (XCHAL_DEBUGLEVEL != 3)
- .begin literal_prefix .Level3InterruptVector
- .section .Level3InterruptVector.text, "ax"
- .align 4
- .global _Level3Vector
-_Level3Vector:
-# if XCHAL_HAVE_DEBUG && (XCHAL_DEBUGLEVEL > 3)
- break 1, 2 // unexpected high-priority interrupt
-# elif defined(SIMULATOR)
- wsr a2, EXCSAVE_3
- movi a2, SYS_unhandled_highpri_interrupt
- simcall // let simulator/debugger report unhandled level-3 interrupt
-# endif
-1: j 1b // infinite loop - unexpected level-3 interrupt
- .size _Level3Vector, . - _Level3Vector
- .text
- .end literal_prefix
-# endif /* level 3 */
-
-
-#elif defined(__SPLIT__level4)
-
-# if (XCHAL_NUM_INTLEVELS >= 4) && (XCHAL_DEBUGLEVEL != 4)
- .begin literal_prefix .Level4InterruptVector
- .section .Level4InterruptVector.text, "ax"
- .align 4
- .global _Level4Vector
-_Level4Vector:
-# if XCHAL_HAVE_DEBUG && (XCHAL_DEBUGLEVEL > 4)
- break 1, 2 // unexpected high-priority interrupt
-# elif defined(SIMULATOR)
- wsr a2, EXCSAVE_4
- movi a2, SYS_unhandled_highpri_interrupt
- simcall // let simulator/debugger report unhandled level-4 interrupt
-# endif
-1: j 1b // infinite loop - unexpected level-4 interrupt
- .size _Level4Vector, . - _Level4Vector
- .text
- .end literal_prefix
-# endif /* level 4 */
-
-
-#elif defined(__SPLIT__level5)
-
-# if (XCHAL_NUM_INTLEVELS >= 5) && (XCHAL_DEBUGLEVEL != 5)
- .begin literal_prefix .Level5InterruptVector
- .section .Level5InterruptVector.text, "ax"
- .align 4
- .global _Level5Vector
-_Level5Vector:
-# if XCHAL_HAVE_DEBUG && (XCHAL_DEBUGLEVEL > 5)
- break 1, 2 // unexpected high-priority interrupt
-# elif defined(SIMULATOR)
- wsr a2, EXCSAVE_5
- movi a2, SYS_unhandled_highpri_interrupt
- simcall // let simulator/debugger report unhandled level-5 interrupt
-# endif
-1: j 1b // infinite loop - unexpected level-5 interrupt
- .size _Level5Vector, . - _Level5Vector
- .text
- .end literal_prefix
-# endif /* level 5 */
-
-
-#elif defined(__SPLIT__level6)
-
-# if (XCHAL_NUM_INTLEVELS >= 6) && (XCHAL_DEBUGLEVEL != 6)
- .begin literal_prefix .Level6InterruptVector
- .section .Level6InterruptVector.text, "ax"
- .align 4
- .global _Level6Vector
-_Level6Vector:
-# if XCHAL_HAVE_DEBUG && (XCHAL_DEBUGLEVEL > 6)
- break 1, 2 // unexpected high-priority interrupt
-# elif defined(SIMULATOR)
- wsr a2, EXCSAVE_6
- movi a2, SYS_unhandled_highpri_interrupt
- simcall // let simulator/debugger report unhandled level-6 interrupt
-# endif
-1: j 1b // infinite loop - unexpected level-6 interrupt
- .size _Level6Vector, . - _Level6Vector
- .text
- .end literal_prefix
-# endif /* level 6 */
-
-
-#endif /* split */
-
diff --git a/src/arch/xtensa/smp/xtos/reset-unneeded.S b/src/arch/xtensa/smp/xtos/reset-unneeded.S
deleted file mode 100644
index e662a58..0000000
--- a/src/arch/xtensa/smp/xtos/reset-unneeded.S
+++ /dev/null
@@ -1,156 +0,0 @@
-// reset-unneeded.S -- Optional Extraneous Reset Code
-// $Id: //depot/rel/Foxhill/dot.8/Xtensa/OS/xtos/reset-unneeded.S#1 $
-
-// Copyright (c) 2002-2006 Tensilica Inc.
-//
-// Permission is hereby granted, free of charge, to any person obtaining
-// a copy of this software and associated documentation files (the
-// "Software"), to deal in the Software without restriction, including
-// without limitation the rights to use, copy, modify, merge, publish,
-// distribute, sublicense, and/or sell copies of the Software, and to
-// permit persons to whom the Software is furnished to do so, subject to
-// the following conditions:
-//
-// The above copyright notice and this permission notice shall be included
-// in all copies or substantial portions of the Software.
-//
-// THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
-// EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
-// MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
-// IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY
-// CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
-// TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
-// SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
-
-// This file is meant to be included by another, e.g. crt1-***.S .
-// The code it contains is generally not needed, so is kept in a
-// separate file for clarity of other code.
-
-#if XTOS_RESET_UNNEEDED
- /*
- * Reset registers that don't really need to be reset,
- * but may provide more predictability when buggy code
- * relies on uninitialized state. It might also clear
- * "X"s a bit earlier in hardware simulations.
- *
- * NOTE: This code is by no means exhaustive.
- * More processor registers/states could be reset if desired.
- * This is just an example.
- *
- * ASSUMPTION: a0 is still zero at this point.
- */
-
- // Interrupt initialization.
- // Because INTENABLE is cleared by the reset vector, clearing the
- // interrupt-pending register should not be needed. This assumes
- // that any application setting up an interrupt will register and
- // clear it before enabling it, which is the recommended sequence.
- //
-#if XCHAL_HAVE_INTERRUPTS && (XCHAL_INTCLEARABLE_MASK != 0) && !XCHAL_HAVE_FULL_RESET
- movi a2, XCHAL_INTCLEARABLE_MASK
- wsr a2, INTCLEAR // clear software and edge-trig ints
-#endif
-
- // Timer initialization (not strictly required, but sometimes helpful)
- .macro reset_timer num
- wsr a0, CCOMPARE_0 + \num
- .endm
- iterate 0, XCHAL_NUM_TIMERS-1, reset_timer
-
-# if XCHAL_HAVE_WINDOWED
- // Windowed address register init -- initialize entire physical AR file
- movi a0, XCHAL_NUM_AREGS/8 // number of 8-register chunks
-arloop:
- addi a8, a0, -1 // countdown into next chunk's a0
- movi a0, 0
- movi a1, 0
- movi a2, 0
- movi a3, 0
- movi a4, 0
- movi a5, 0
- movi a6, 0
- movi a7, 0
- rotw 2 // rotate to next chunk
- bnez a0, arloop
- // NOTE: WINDOWBASE is back to zero at this point.
-# else /* XCHAL_HAVE_WINDOWED */
- // Non-windowed address register init
- movi a1, 0
- movi a2, 0
- movi a3, 0
- movi a4, 0
- movi a5, 0
- movi a6, 0
- movi a7, 0
- movi a8, 0
- movi a9, 0
- movi a10, 0
- movi a11, 0
- movi a12, 0
- movi a13, 0
- movi a14, 0
- movi a15, 0
-# endif /* XCHAL_HAVE_WINDOWED */
- // Now all address registers are zero.
-
- // Initialize LBEG, LEND, and LCOUNT.
-# if XCHAL_HAVE_LOOPS
- wsr a0, LCOUNT // note: LCOUNT gets cleared by processor reset
- wsr a0, LBEG
- wsr a0, LEND
-# endif
-
-# if XCHAL_HAVE_DEBUG
- .macro reset_dbreaka num
- wsr a0, DBREAKA + \num
- .endm
- .macro reset_ibreaka num
- wsr a0, IBREAKA + \num
- .endm
- iterate 0, XCHAL_NUM_DBREAK-1, reset_dbreaka
- iterate 0, XCHAL_NUM_IBREAK-1, reset_ibreaka
-# endif
-
- // SAR initialization
- ssai 0
-
- // Exception initialization
-# if XCHAL_HAVE_EXCEPTIONS
- wsr a0, EPC+1
- wsr a0, EXCSAVE+1
- wsr a0, EXCCAUSE
-# endif
-
-# if XCHAL_HAVE_HIGHLEVEL_INTERRUPTS
- .macro reset_int num
- wsr a0, EPC + \num
- wsr a0, EPS + \num
- wsr a0, EXCSAVE + \num
- .endm
- iterate 2, XCHAL_NUM_INTLEVELS, reset_int
-# endif
-
- // Booleans initialization
-# if XCHAL_HAVE_BOOLEANS
- wsr a0, BR
-# endif
-
- // MAC16 initialization
-# if XCHAL_HAVE_MAC16
- wsr a0, ACCLO
- wsr a0, ACCHI
- wsr a0, M0
- wsr a0, M1
- wsr a0, M2
- wsr a0, M3
-# endif
-
- // OCD initialization
-# if XCHAL_HAVE_OCD
- wsr a0, DDR
-# endif
-
- isync // wait for all the above to take effect
-
-#endif /* XTOS_RESET_UNNEEDED */
-
diff --git a/src/arch/xtensa/smp/xtos/reset-vector.S b/src/arch/xtensa/smp/xtos/reset-vector.S
deleted file mode 100644
index 77de1b4..0000000
--- a/src/arch/xtensa/smp/xtos/reset-vector.S
+++ /dev/null
@@ -1,648 +0,0 @@
-// reset-vector.S -- Xtensa Reset Vector
-// $Id: //depot/rel/Foxhill/dot.8/Xtensa/OS/xtos/reset-vector.S#1 $
-
-// Copyright (c) 1999-2013 Tensilica Inc.
-//
-// Permission is hereby granted, free of charge, to any person obtaining
-// a copy of this software and associated documentation files (the
-// "Software"), to deal in the Software without restriction, including
-// without limitation the rights to use, copy, modify, merge, publish,
-// distribute, sublicense, and/or sell copies of the Software, and to
-// permit persons to whom the Software is furnished to do so, subject to
-// the following conditions:
-//
-// The above copyright notice and this permission notice shall be included
-// in all copies or substantial portions of the Software.
-//
-// THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
-// EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
-// MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
-// IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY
-// CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
-// TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
-// SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
-
-#include <xtensa/coreasm.h>
-#include <xtensa/corebits.h>
-#include <xtensa/cacheasm.h>
-#include <xtensa/cacheattrasm.h>
-#include <xtensa/xtensa-xer.h>
-#include <xtensa/xdm-regs.h>
-#include <xtensa/config/system.h> /* for XSHAL_USE_ABSOLUTE_LITERALS only */
-#include <xtensa/xtruntime-core-state.h>
-#include "xtos-internal.h"
-#include <config.h>
-#if CONFIG_BOOT_LOADER
-#include <platform/memory.h>
-#endif
-
-// The following reset vector avoids initializing certain registers already
-// initialized by processor reset. But it does initialize some of them
-// anyway, for minimal support of warm restart (restarting in software by
-// jumping to the reset vector rather than asserting hardware reset).
-
-
- .begin literal_prefix .ResetVector
- .section .ResetVector.text, "ax"
-
- .align 4
- .global _ResetVector
-_ResetVector:
-
-#if (!XCHAL_HAVE_HALT || defined(XTOS_UNPACK)) && XCHAL_HAVE_IMEM_LOADSTORE
- // NOTE:
- //
- // IMPORTANT: If you move the _ResetHandler portion to a section
- // other than .ResetVector.text that is outside the range of
- // the reset vector's 'j' instruction, the _ResetHandler symbol
- // and a more elaborate j/movi/jx sequence are needed in
- // .ResetVector.text to dispatch to the new location.
-
-/* cAVS 1.5+ platforms have reset vector in ROM */
-#if CONFIG_BAYTRAIL || CONFIG_CHERRYTRAIL \
- || CONFIG_HASWELL || CONFIG_BROADWELL
- j _ResetHandler
-#else
- // This is our VM ROM, it simply jumps to the reset handler.
- j .sram_jump // jump over the literals
-
- .align 4
- .literal_position // tells the assembler/linker to place literals here
-
-_reset_sram:
- .word _ResetHandler
- .align 4
-.sram_jump:
- l32r a0, _reset_sram // load SRAM reset handler address
- jx a0 // jump to the handler
-#endif
- .size _ResetVector, . - _ResetVector
-
-# if XCHAL_HAVE_HALT
- // Xtensa TX: reset vector segment is only 4 bytes, so must place the
- // unpacker code elsewhere in the memory that contains the reset vector.
-# if XCHAL_RESET_VECTOR_VADDR == XCHAL_INSTRAM0_VADDR
- .section .iram0.text, "ax"
-# elif XCHAL_RESET_VECTOR_VADDR == XCHAL_INSTROM0_VADDR
- .section .irom0.text, "ax"
-# elif XCHAL_RESET_VECTOR_VADDR == XCHAL_URAM0_VADDR
- .section .uram0.text, "ax"
-# else
-# warning "Xtensa TX reset vector not at start of iram0, irom0, or uram0 -- ROMing LSPs may not work"
- .text
-# endif
-# endif
-
- .extern __memctl_default
-
-#if CONFIG_BOOT_LOADER
- .section .ResetHandler.text, "ax"
- j _ResetHandler
-#endif
- .align 4
- .literal_position // tells the assembler/linker to place literals here
-
- // For MPU empty background map -- see XCHAL_HAVE_MPU code further below.
- // Cannot put this in .rodata (not unpacked before MPU init).
-# if XCHAL_HAVE_MPU && XCHAL_MPU_ENTRIES >= 8 && XCHAL_MPU_BACKGROUND_ENTRIES <= 2
- .global _xtos_mpu_attribs
- .align 4
-_xtos_mpu_attribs:
- .word 0x00006000+XCHAL_MPU_ENTRIES-8 // Illegal (---)
- .word 0x000F7700+XCHAL_MPU_ENTRIES-8 // Writeback (rwx Cacheable Non-shareable wb rd-alloc wr-alloc)
- .word 0x000D5700+XCHAL_MPU_ENTRIES-8 // WBNA (rwx Cacheable Non-shareable wb rd-alloc)
- .word 0x000C4700+XCHAL_MPU_ENTRIES-8 // Writethru (rwx Cacheable Non-shareable wt rd-alloc)
- .word 0x00006700+XCHAL_MPU_ENTRIES-8 // Bypass (rwx Device non-interruptible system-shareable)
-# endif
-
- .align 4
- .global _ResetHandler
-_ResetHandler:
-#endif
-
-#if !XCHAL_HAVE_HALT
-
- /*
- * Even if the processor supports the non-PC-relative L32R option,
- * it will always start up in PC-relative mode. We take advantage of
- * this, and use PC-relative mode at least until we're sure the .lit4
- * section is in place (which is sometimes only after unpacking).
- */
- .begin no-absolute-literals
-
- // If we have dynamic cache way support, init the caches as soon
- // as we can, which is now. Except, if we are waking up from a
- // PSO event, then we need to do this slightly later.
-
-#if XCHAL_HAVE_ICACHE_DYN_WAYS || XCHAL_HAVE_DCACHE_DYN_WAYS
-# if XCHAL_HAVE_PSO_CDM && !XCHAL_HAVE_PSO_FULL_RETENTION
- // Do this later on in the code -- see below
-# else
- movi a0, __memctl_default
- wsr.memctl a0
-# endif
-#endif
-
- // If we have PSO support, then we must check for a warm start with
- // caches left powered on. If the caches had been left powered on,
- // we must restore the state of MEMCTL to the saved state if any.
- // Note that MEMCTL may not be present depending on config.
-
-#if XCHAL_HAVE_PSO_CDM && !XCHAL_HAVE_PSO_FULL_RETENTION
- movi a2, XDM_MISC_PWRSTAT // Read PWRSTAT
- movi a3, _xtos_pso_savearea // Save area address - retained for later
- movi a5, CORE_STATE_SIGNATURE // Signature for compare - retained for later
- rer a7, a2 // PWRSTAT value - retained for later
- extui a4, a7, 1, 2 // Now bottom 2 bits are core wakeup and cache power lost
- bnei a4, 1, .Lcold_start // a4==1 means PSO wakeup, caches did not lose power
- l32i a4, a3, CS_SA_signature // Load save area signature field
- sub a4, a4, a5
- bnez a4, .Lcold_start // If signature mismatch then do cold start
-#if XCHAL_USE_MEMCTL
- l32i a4, a3, CS_SA_memctl // Load saved MEMCTL value
- movi a0, ~MEMCTL_INV_EN
- and a0, a4, a0 // Clear invalidate bit
- wsr.memctl a0
-#endif
- j .Lwarm_start
-
-.Lcold_start:
-
-#if XCHAL_HAVE_ICACHE_DYN_WAYS || XCHAL_HAVE_DCACHE_DYN_WAYS
- // Enable and invalidate all ways of both caches. If there is no
- // dynamic way support then this write will have no effect.
-
- movi a0, __memctl_default
- wsr.memctl a0
-#endif
-
-.Lwarm_start:
-
-#endif
-
- movi a0, 0 // a0 is always 0 in this code, used to initialize lots of things
-
-#if XCHAL_HAVE_INTERRUPTS // technically this should be under !FULL_RESET, assuming hard reset
- wsr.intenable a0 // make sure that interrupts are shut off (*before* we lower PS.INTLEVEL and PS.EXCM!)
-#endif
-
-#if !XCHAL_HAVE_FULL_RESET
-
-#if XCHAL_HAVE_CCOUNT && (XCHAL_HW_MIN_VERSION < XTENSA_HWVERSION_RB_2006_0) /* pre-LX2 cores only */
- wsr.ccount a0 // not really necessary, but nice; best done very early
-#endif
-
- // For full MMU configs, put page table at an unmapped virtual address.
- // This ensures that accesses outside the static maps result
- // in miss exceptions rather than random behaviour.
- // Assumes XCHAL_SEG_MAPPABLE_VADDR == 0 (true in released MMU).
-#if XCHAL_ITLB_ARF_WAYS > 0 || XCHAL_DTLB_ARF_WAYS > 0
- wsr.ptevaddr a0
-#endif
-
- // Debug initialization
- //
- // NOTE: DBREAKCn must be initialized before the combination of these two things:
- // any load/store, and a lowering of PS.INTLEVEL below DEBUG_LEVEL.
- // The processor already resets IBREAKENABLE appropriately.
- //
-#if XCHAL_HAVE_DEBUG
-# if XCHAL_NUM_DBREAK
-# if XCHAL_NUM_DBREAK >= 2
- wsr.dbreakc1 a0
-# endif
- wsr.dbreakc0 a0
- dsync // wait for WSRs to DBREAKCn to complete
-# endif
-
-# if XCHAL_HW_MIN_VERSION < XTENSA_HWVERSION_RA_2004_1 /* pre-LX cores only */
- // Starting in Xtensa LX, ICOUNTLEVEL resets to zero (not 15), so no need to initialize it.
- // Prior to that we do, otherwise we get an ICOUNT exception, 2^32 instructions after reset.
- rsr.icountlevel a2 // are we being debugged? (detected by ICOUNTLEVEL not 15, or dropped below 12)
- bltui a2, 12, 1f // if so, avoid initializing ICOUNTLEVEL which drops single-steps through here
- wsr.icountlevel a0 // avoid ICOUNT exceptions
- isync // wait for WSR to ICOUNTLEVEL to complete
-1:
-# endif
-#endif
-
-#endif /* !XCHAL_HAVE_FULL_RESET */
-
-#if XCHAL_HAVE_ABSOLUTE_LITERALS
- // Technically, this only needs to be done under !FULL_RESET, assuming hard reset:
- wsr.litbase a0
- rsync
-#endif
-
-#if XCHAL_HAVE_PSO_CDM && ! XCHAL_HAVE_PSO_FULL_RETENTION
- // If we're powering up from a temporary power shut-off (PSO),
- // restore state saved just prior to shut-off. Note that the
- // MEMCTL register was already restored earlier, and as a side
- // effect, registers a3, a5, a7 are now preloaded with values
- // that we will use here.
- // a3 - pointer to save area base address (_xtos_pso_savearea)
- // a5 - saved state signature (CORE_STATE_SIGNATURE)
- // a7 - contents of PWRSTAT register
-
- l32i a4, a3, CS_SA_signature // load save area signature
- sub a4, a4, a5 // compare signature with expected one
-# if XTOS_PSO_TEST
- movi a7, PWRSTAT_WAKEUP_RESET // pretend PSO warm start with warm caches
-# endif
- bbci.l a7, PWRSTAT_WAKEUP_RESET_SHIFT, 1f // wakeup from PSO? (branch if not)
- // Yes, wakeup from PSO. Check whether state was properly saved.
- addi a5, a7, - PWRSTAT_WAKEUP_RESET // speculatively clear PSO-wakeup bit
- movnez a7, a5, a4 // if state not saved (corrupted?), mark as cold start
- bnez a4, 1f // if state not saved, just continue with reset
- // Wakeup from PSO with good signature. Now check cache status:
- bbci.l a7, PWRSTAT_CACHES_LOST_POWER_SHIFT, .Lpso_restore // if caches warm, restore now
- // Caches got shutoff. Continue reset, we'll end up initializing caches, and check again later for PSO.
-# if XCHAL_HAVE_PRID && XCHAL_HAVE_S32C1I
- j .Ldonesync // skip reset sync, only done for cold start
-# endif
-1: // Cold start. (Not PSO wakeup.) Proceed with normal full reset.
-#endif
-
-#if XCHAL_HAVE_PRID && XCHAL_HAVE_S32C1I
- /* Core 0 initializes the XMP synchronization variable, if present. This operation needs to
- happen as early as possible in the startup sequence so that the other cores can be released
- from reset. */
- .weak _ResetSync
- movi a2, _ResetSync // address of sync variable
- rsr.prid a3 // core and multiprocessor ID
- extui a3, a3, 0, 8 // extract core ID (FIXME: need proper constants for PRID bits to extract)
- beqz a2, .Ldonesync // skip if no sync variable
- bnez a3, .Ldonesync // only do this on core 0
- s32i a0, a2, 0 // clear sync variable
-.Ldonesync:
-#endif
-#if XCHAL_HAVE_EXTERN_REGS && XCHAL_HAVE_MP_RUNSTALL
- /* On core 0, this releases other cores. On other cores this has no effect, because
- runstall control is unconnected. */
- movi a2, XER_MPSCORE
- wer a0, a2
-#endif
-
- /*
- * For processors with relocatable vectors, apply any alternate
- * vector base given to xt-genldscripts, which sets the
- * _memmap_vecbase_reset symbol accordingly.
- */
-#if XCHAL_HAVE_VECBASE
- movi a2, _memmap_vecbase_reset /* note: absolute symbol, not a ptr */
- wsr.vecbase a2
-#endif
-
-#if XCHAL_HAVE_S32C1I && (XCHAL_HW_MIN_VERSION >= XTENSA_HWVERSION_RC_2009_0) /* have ATOMCTL ? */
-# if XCHAL_DCACHE_IS_COHERENT
- movi a3, 0x25 /* MX -- internal for writeback, RCW otherwise */
-# else
- movi a3, 0x15 /* non-MX -- always RCW */
-# endif
- wsr.atomctl a3
-#endif
-
-#if XCHAL_HAVE_INTERRUPTS && XCHAL_HAVE_DEBUG
- rsil a2, 1 // lower PS.INTLEVEL here to make reset vector easier to debug
-#endif
-
- /* If either of the caches does not have dynamic way support, then
- * use the old (slow) method to init them. If the cache is absent
- * the macros will expand to empty.
- */
-#if ! XCHAL_HAVE_ICACHE_DYN_WAYS
- icache_reset a2, a3
-#endif
-#if ! XCHAL_HAVE_DCACHE_DYN_WAYS
- dcache_reset a2, a3
-#endif
-
-#if XCHAL_HAVE_PSO_CDM && ! XCHAL_HAVE_PSO_FULL_RETENTION
- // Here, a7 still contains status from the power status register,
- // or zero if signature check failed.
- bbci.l a7, PWRSTAT_WAKEUP_RESET_SHIFT, .Lcoldstart // wakeup from PSO with good signature?
- // Yes, wakeup from PSO. Caches had been powered down, now are initialized.
-.Lpso_restore:
- // Assume memory still initialized, so all code still unpacked etc.
- // So we can just jump/call to relevant state restore code (wherever located).
- movi a2, 0 // make shutoff routine return zero
- movi a3, _xtos_pso_savearea
- // Here, as below for _start, call0 is used as an unlimited-range jump.
- call0 _xtos_core_restore_nw
- // (does not return)
-.Lcoldstart:
-#endif
-
-#if XCHAL_HAVE_PREFETCH
- /* Enable cache prefetch if present. */
- movi a2, XCHAL_CACHE_PREFCTL_DEFAULT
- wsr.prefctl a2
-#endif
-
- /*
- * Now setup the memory attributes. On some cores this "enables" caches.
- * We do this ahead of unpacking, so it can proceed more efficiently.
- *
- * The _memmap_cacheattr_reset symbol's value (address) is defined
- * by the LSP's linker script, as generated by xt-genldscripts.
- * If defines 4-bit attributes for eight 512MB regions.
- *
- * (NOTE: for cores with the older MMU v1 or v2, or without any memory
- * protection mechanism, the following code has no effect.)
- */
-#if XCHAL_HAVE_MPU
- /* If there's an empty background map, setup foreground maps to mimic region protection: */
-# if XCHAL_MPU_ENTRIES >= 8 && XCHAL_MPU_BACKGROUND_ENTRIES <= 2
- // We assume reset state: all MPU entries zeroed and disabled.
- // Otherwise we'd need a loop to zero everything.
-
- movi a2, _memmap_cacheattr_reset // note: absolute symbol, not a ptr
- movi a3, _xtos_mpu_attribs // see literal area at start of reset vector
- movi a4, 0x20000000 // 512 MB delta
- movi a6, 8
- movi a7, 1 // MPU entry vaddr 0, with valid bit set
- movi a9, 0 // cacheadrdis value
- wsr.cacheadrdis a9 // enable everything temporarily while MPU updates
-
- // Write eight MPU entries, from the last one going backwards (entries n-1 thru n-8)
- //
-2: extui a8, a2, 28, 4 // get next attribute nibble (msb first)
- extui a5, a8, 0, 2 // lower two bit indicate whether cached
- slli a9, a9, 1 // add a bit to cacheadrdis...
- addi a10, a9, 1 // set that new bit if...
- moveqz a9, a10, a5 // ... that region is non-cacheable
- addx4 a5, a8, a3 // index into _xtos_mpu_attribs table
- addi a8, a8, -5 // make valid attrib indices negative
- movgez a5, a3, a8 // if not valid attrib, use Illegal
- l32i a5, a5, 0 // load access rights, memtype from table entry
- slli a2, a2, 4
- sub a7, a7, a4 // next 512MB region (last to first)
- addi a6, a6, -1
- add a5, a5, a6 // add the index
- wptlb a5, a7 // write the MPU entry
- bnez a6, 2b // loop until done
-# else
- movi a9, XCHAL_MPU_BG_CACHEADRDIS // default value of CACHEADRDIS for bgnd map
-# endif
- wsr.cacheadrdis a9 // update cacheadrdis
-#elif XCHAL_HAVE_CACHEATTR || XCHAL_HAVE_MIMIC_CACHEATTR || XCHAL_HAVE_XLT_CACHEATTR \
- || (XCHAL_HAVE_PTP_MMU && XCHAL_HAVE_SPANNING_WAY)
- movi a2, _memmap_cacheattr_reset /* note: absolute symbol, not a ptr */
- cacheattr_set /* set CACHEATTR from a2 (clobbers a3-a8) */
-#endif
-
- /* Now that caches are initialized, cache coherency can be enabled. */
-#if XCHAL_DCACHE_IS_COHERENT
-# if XCHAL_HAVE_EXTERN_REGS && XCHAL_HAVE_MX && (XCHAL_HW_MIN_VERSION < XTENSA_HWVERSION_RE_2012_0)
- /* Opt into coherence for MX (for backward compatibility / testing). */
- movi a3, 1
- movi a2, XER_CCON
- wer a3, a2
-# endif
-#endif
-
- /* Enable zero-overhead loop instr buffer and snoop responses if configured. */
- /* If HW erratum 453 fix is to be applied then disable loop instr buffer. */
-#if XCHAL_USE_MEMCTL && (XCHAL_SNOOP_LB_MEMCTL_DEFAULT || XCHAL_ERRATUM_453)
- rsr.memctl a2
-#if XCHAL_SNOOP_LB_MEMCTL_DEFAULT
- movi a3, XCHAL_SNOOP_LB_MEMCTL_DEFAULT
- or a2, a2, a3
-#endif
-#if XCHAL_ERRATUM_453
- srli a2, a2, 1 /* clear bit 0 (ZOL buffer enable) */
- slli a2, a2, 1
-#endif
- wsr.memctl a2
-#endif
-
- /* Caches are all up and running, clear PWRCTL.ShutProcOffOnPWait. */
-#if XCHAL_HAVE_PSO_CDM
- movi a2, XDM_MISC_PWRCTL
- movi a4, ~PWRCTL_CORE_SHUTOFF
- rer a3, a2
- and a3, a3, a4
- wer a3, a2
-#endif
-
-#endif /* !XCHAL_HAVE_HALT */
-
- /*
- * At this point we can unpack code and data (e.g. copy segments from
- * ROM to RAM, vectors into their proper location, etc.). However,
- *
- * 1) the destination of the unpack may require some setup,
- * for instance a DDR controller may need to be initialized
- * and enabled before anything is unpacked into DDR.
- * 2) users may wish to provide their own unpack code which works
- * faster or in a different way than the default unpack code.
- *
- * To support such uses, we provide a user hook at this point.
- * If the user hook function is defined, then it is called from
- * here, and its return value (in a2) is checked. If the return
- * value is non-zero, then we assume that code unpacking has been
- * completed. The user hook function must be written in assembly
- * and should make minimal assumptions about system state.
- */
-
- .weak __reset_user_init
-
- movi a2, __reset_user_init
- beqz a2, 1f // no user hook
- callx0 a2 // execute user hook
- movi a0, 0 // ensure a0 continues to hold 0
- bnez a2, unpackdone // if a2 != 0 then unpack is done
-1:
-
-#if defined(XTOS_UNPACK)
- movi a2, _rom_store_table
- beqz a2, unpackdone
-unpack: l32i a3, a2, 0 // start vaddr
- l32i a4, a2, 4 // end vaddr
- l32i a5, a2, 8 // store vaddr
- addi a2, a2, 12
- bgeu a3, a4, upnext // skip unless start < end
-uploop: l32i a6, a5, 0
- addi a5, a5, 4
- s32i a6, a3, 0
- addi a3, a3, 4
- bltu a3, a4, uploop
- j unpack
-upnext: bnez a3, unpack
- bnez a5, unpack
-#endif /* XTOS_UNPACK */
-
-unpackdone:
-
-#if defined(XTOS_UNPACK) || defined(XTOS_MP)
- /*
- * If writeback caches are configured and enabled, unpacked data must be
- * written out to memory before trying to execute it:
- */
- dcache_writeback_all a2, a3, a4, 0
- icache_sync a2 // ensure data written back is visible to i-fetch
- /*
- * Note: no need to invalidate the i-cache after the above, because we
- * already invalidated it further above and did not execute anything within
- * unpacked regions afterwards. [Strictly speaking, if an unpacked region
- * follows this code very closely, it's possible for cache-ahead to have
- * cached a bit of that unpacked region, so in the future we may need to
- * invalidate the entire i-cache here again anyway.]
- */
-#endif
-
-
-#if !XCHAL_HAVE_HALT /* skip for TX */
-
- /*
- * Now that we know the .lit4 section is present (if got unpacked)
- * (and if absolute literals are used), initialize LITBASE to use it.
- */
-#if XCHAL_HAVE_ABSOLUTE_LITERALS && XSHAL_USE_ABSOLUTE_LITERALS
- /*
- * Switch from PC-relative to absolute (litbase-relative) L32R mode.
- * Set LITBASE to 256 kB beyond the start of the literals in .lit4
- * (aligns to the nearest 4 kB boundary, LITBASE does not have bits 1..11)
- * and set the enable bit (_lit4_start is assumed 4-byte aligned).
- */
- movi a2, _lit4_start + 0x40001
- wsr.litbase a2
- rsync
-#endif /* have and use absolute literals */
- .end no-absolute-literals // we can now start using absolute literals
-
-
-// Technically, this only needs to be done pre-LX2, assuming hard reset:
-# if XCHAL_HAVE_WINDOWED && defined(__XTENSA_WINDOWED_ABI__)
- // Windowed register init, so we can call windowed code (eg. C code).
- movi a1, 1
- wsr.windowstart a1
- // The processor always clears WINDOWBASE at reset, so no need to clear it here.
- // It resets WINDOWSTART to 1 starting with LX2.0/X7.0 (RB-2006.0).
- // However, assuming hard reset is not yet always practical, so do this anyway:
- wsr.windowbase a0
- rsync
- movi a0, 0 // possibly a different a0, clear it
-# endif
-
-#if XCHAL_HW_MIN_VERSION < XTENSA_HWVERSION_RB_2006_0 /* only pre-LX2 needs this */
- // Coprocessor option initialization
-# if XCHAL_HAVE_CP
- //movi a2, XCHAL_CP_MASK // enable existing CPs
- // To allow creating new coprocessors using TC that are not known
- // at GUI build time without having to explicitly enable them,
- // all CPENABLE bits must be set, even though they may not always
- // correspond to a coprocessor.
- movi a2, 0xFF // enable *all* bits, to allow dynamic TIE
- wsr.cpenable a2
-# endif
-
- // Floating point coprocessor option initialization (at least
- // rounding mode, so that floating point ops give predictable results)
-# if XCHAL_HAVE_FP && !XCHAL_HAVE_VECTORFPU2005
- rsync /* wait for WSR to CPENABLE to complete before accessing FP coproc state */
- wur.fcr a0 /* clear FCR (default rounding mode, round-nearest) */
- wur.fsr a0 /* clear FSR */
-# endif
-#endif /* pre-LX2 */
-
-
- // Initialize memory error handler address.
- // Putting this address in a register allows multiple instances of
- // the same configured core (with separate program images but shared
- // code memory, thus forcing memory error vector to be shared given
- // it is not VECBASE relative) to have the same memory error vector,
- // yet each have their own handler and associated data save area.
-#if XCHAL_HAVE_MEM_ECC_PARITY_IGNORE
- movi a4, _MemErrorHandler
- wsr.mesave a4
-#endif
-
-
- /*
- * Initialize medium and high priority interrupt dispatchers:
- */
-#if HAVE_XSR && (XCHAL_HAVE_XEA1 || XCHAL_HAVE_XEA2)
-
-#if !CONFIG_BOOT_LOADER
-# ifndef XCHAL_DEBUGLEVEL /* debug option not selected? */
-# define XCHAL_DEBUGLEVEL 99 /* bogus value outside 2..6 */
-# endif
-
- .macro init_vector level
- .if GREATERTHAN(XCHAL_NUM_INTLEVELS+1,\level)
- .if XCHAL_DEBUGLEVEL-\level
- .weak _Level&level&FromVector
- movi a4, _Level&level&FromVector
- writesr excsave \level a4
- .if GREATERTHAN(\level,XCHAL_EXCM_LEVEL)
- movi a5, _Pri_&level&_HandlerAddress
- s32i a4, a5, 0
- /* If user provides their own handler, that handler might
- * not provide its own _Pri_<n>_HandlerAddress variable for
- * linking handlers. In that case, the reference below
- * would pull in the XTOS handler anyway, causing a conflict.
- * To avoid that, provide a weak version of it here:
- */
- .pushsection .data, "aw"
- .global _Pri_&level&_HandlerAddress
- .weak _Pri_&level&_HandlerAddress
- .align 4
- _Pri_&level&_HandlerAddress: .space 4
- .popsection
- .endif
- .endif
- .endif
- .endm
-
- init_vector 2
- init_vector 3
- init_vector 4
- init_vector 5
- init_vector 6
-#endif
-#endif /*HAVE_XSR*/
-
-
- /*
- * Complete reset initialization outside the vector,
- * to avoid requiring a vector that is larger than necessary.
- * This 2nd-stage startup code sets up the C Run-Time (CRT) and calls main().
- *
- * Here we use call0 not because we expect any return, but
- * because the assembler/linker dynamically sizes call0 as
- * needed (with -mlongcalls) which it doesn't with j or jx.
- * Note: This needs to be call0 regardless of the selected ABI.
- */
-
-#if CONFIG_BOOT_LOADER
- movi a0, SOF_TEXT_START
- callx0 a0
-#else
- call0 _start // jump to _start (in crt1-*.S)
-#endif
- /* does not return */
-
-#else /* XCHAL_HAVE_HALT */
-
- j _start // jump to _start (in crt1-*.S)
- // (TX has max 64kB IRAM, so J always in range)
-
- // Paranoia -- double-check requirements / assumptions of this Xtensa TX code:
-# if !defined(__XTENSA_CALL0_ABI__) || !XCHAL_HAVE_FULL_RESET || XCHAL_HAVE_INTERRUPTS || XCHAL_HAVE_CCOUNT || XCHAL_DTLB_ARF_WAYS || XCHAL_HAVE_DEBUG || XCHAL_HAVE_S32C1I || XCHAL_HAVE_ABSOLUTE_LITERALS || XCHAL_DCACHE_SIZE || XCHAL_ICACHE_SIZE || XCHAL_HAVE_PIF || XCHAL_HAVE_WINDOWED
-# error "Halt architecture (Xtensa TX) requires: call0 ABI, all flops reset, no exceptions or interrupts, no TLBs, no debug, no S32C1I, no LITBASE, no cache, no PIF, no windowed regs"
-# endif
-
-#endif /* XCHAL_HAVE_HALT */
-
-
-#if (!XCHAL_HAVE_HALT || defined(XTOS_UNPACK)) && XCHAL_HAVE_IMEM_LOADSTORE
- .size _ResetHandler, . - _ResetHandler
-#else
- .size _ResetVector, . - _ResetVector
-#endif
-
- .text
- .global xthals_hw_configid0, xthals_hw_configid1
- .global xthals_release_major, xthals_release_minor
- .end literal_prefix
diff --git a/src/arch/xtensa/smp/xtos/shared-reset-vector.S b/src/arch/xtensa/smp/xtos/shared-reset-vector.S
deleted file mode 100644
index ae457f9..0000000
--- a/src/arch/xtensa/smp/xtos/shared-reset-vector.S
+++ /dev/null
@@ -1,73 +0,0 @@
-// shared-reset-vector.S -- Sharable Reset Vector (requires PRID option)
-
-// Copyright (c) 1999-2010 Tensilica Inc.
-//
-// Permission is hereby granted, free of charge, to any person obtaining
-// a copy of this software and associated documentation files (the
-// "Software"), to deal in the Software without restriction, including
-// without limitation the rights to use, copy, modify, merge, publish,
-// distribute, sublicense, and/or sell copies of the Software, and to
-// permit persons to whom the Software is furnished to do so, subject to
-// the following conditions:
-//
-// The above copyright notice and this permission notice shall be included
-// in all copies or substantial portions of the Software.
-//
-// THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
-// EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
-// MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
-// IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY
-// CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
-// TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
-// SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
-
-#include <xtensa/coreasm.h>
-
- // Populate this processor's entry in the reset table.
- // The core instance specific LSP should put this section
- // in the correct location within the table.
- //
- .section .ResetTable.rodata, "a"
- .word _ResetHandler
-
- // This sharable reset code assumes RC-2009.0 or later hardware,
- // to guarantee that no processor state initialization is required
- // prior to doing loads etc.
- // Total size is 28 bytes (or 27 with density option).
- // By necessity, none of these bytes vary by core instance;
- // the appropriate reset table entry is selected using PRID.
- //
-#if XCHAL_HAVE_PRID
- .section .SharedResetVector.text, "ax"
- .begin no-absolute-literals
-
- .align 4
- .global _SharedResetVector
-_SharedResetVector:
- j .LSharedResetHandler
-
- .align 4
- .literal_position
-
- // Use L32R if available
-#if XCHAL_HAVE_L32R
- .literal rtbase, _ResetTable_base
-#endif
-
- .align 4
-.LSharedResetHandler:
- rsr.prid a0 // get processor ID (16 bits)
-#if XCHAL_HAVE_L32R
- l32r a1, rtbase // force use of L32R
-#else
- movi a1, _ResetTable_base // No L32R, will likely become CONST16
-#endif
- extui a0, a0, 0, 4 // ID of core within the multiprocessor (FIXME: need proper constant...)
- addx4 a1, a0, a1
- l32i a1, a1, 0
- jx a1 // jump to core-specific initialization
-
- .size _SharedResetVector, . - _SharedResetVector
- .end no-absolute-literals
-#endif
-
diff --git a/src/arch/xtensa/smp/xtos/textaddr b/src/arch/xtensa/smp/xtos/textaddr
deleted file mode 100755
index 4355fac..0000000
--- a/src/arch/xtensa/smp/xtos/textaddr
+++ /dev/null
@@ -1,59 +0,0 @@
-# Program to determine -Ttext parameter for ld
-# $Id: //depot/rel/Foxhill/dot.8/Xtensa/OS/xtos/textaddr#1 $
-
-# Copyright (c) 2001 Tensilica Inc.
-#
-# Permission is hereby granted, free of charge, to any person obtaining
-# a copy of this software and associated documentation files (the
-# "Software"), to deal in the Software without restriction, including
-# without limitation the rights to use, copy, modify, merge, publish,
-# distribute, sublicense, and/or sell copies of the Software, and to
-# permit persons to whom the Software is furnished to do so, subject to
-# the following conditions:
-#
-# The above copyright notice and this permission notice shall be included
-# in all copies or substantial portions of the Software.
-#
-# THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
-# EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
-# MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
-# IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY
-# CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
-# TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
-# SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
-
-package textaddr;
-
-use strict;
-use FileHandle;
-
-{
- $::myname = 'textaddr';
-
- die("Usage is: $::myname objfile label address\n")
- unless @ARGV == 3;
- my($objfile, $label, $address) = @ARGV;
-
-
- my $nm = new FileHandle "xt-nm $objfile|";
- die("$::myname: $!, opening pipe to xt-nm $objfile.\n")
- unless $nm;
- while (<$nm>) {
- if (/^([0-9a-f]{8}) . (\w+)$/) {
- my $oaddress = $1;
- my $olabel = $2;
- if ($olabel eq $label) {
- printf ("0x%x\n", hex($address) - hex($oaddress));
- exit(0);
- }
- }
- }
- die ("$::myname: $label not found in $objfile.\n");
-}
-
-#
-# Local Variables:
-# mode:perl
-# perl-indent-level:2
-# cperl-indent-level:2
-# End:
diff --git a/src/arch/xtensa/smp/xtos/tiny-refs-min.S b/src/arch/xtensa/smp/xtos/tiny-refs-min.S
deleted file mode 100644
index 453001c..0000000
--- a/src/arch/xtensa/smp/xtos/tiny-refs-min.S
+++ /dev/null
@@ -1,28 +0,0 @@
-// tiny-refs-min.S - References to pull-in selected modules into tiny LSPs
-
-// Copyright (c) 2006 Tensilica Inc.
-//
-// Permission is hereby granted, free of charge, to any person obtaining
-// a copy of this software and associated documentation files (the
-// "Software"), to deal in the Software without restriction, including
-// without limitation the rights to use, copy, modify, merge, publish,
-// distribute, sublicense, and/or sell copies of the Software, and to
-// permit persons to whom the Software is furnished to do so, subject to
-// the following conditions:
-//
-// The above copyright notice and this permission notice shall be included
-// in all copies or substantial portions of the Software.
-//
-// THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
-// EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
-// MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
-// IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY
-// CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
-// TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
-// SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
-
-
- .global _need_user_vector_
- .set _need_user_vector_, 0 // define this, so if referenced...
- .global _UserExceptionVector // ... we pull-in this
-
diff --git a/src/arch/xtensa/smp/xtos/tiny-refs.S b/src/arch/xtensa/smp/xtos/tiny-refs.S
deleted file mode 100644
index d89407e..0000000
--- a/src/arch/xtensa/smp/xtos/tiny-refs.S
+++ /dev/null
@@ -1,33 +0,0 @@
-// tiny-refs.S - References to pull-in selected modules into tiny LSPs
-
-// Copyright (c) 2006 Tensilica Inc.
-//
-// Permission is hereby granted, free of charge, to any person obtaining
-// a copy of this software and associated documentation files (the
-// "Software"), to deal in the Software without restriction, including
-// without limitation the rights to use, copy, modify, merge, publish,
-// distribute, sublicense, and/or sell copies of the Software, and to
-// permit persons to whom the Software is furnished to do so, subject to
-// the following conditions:
-//
-// The above copyright notice and this permission notice shall be included
-// in all copies or substantial portions of the Software.
-//
-// THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
-// EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
-// MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
-// IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY
-// CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
-// TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
-// SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
-
-#if defined(__SPLIT__level1int)
-
- .global _need_level1int_
- .set _need_level1int_, 0 // define this, so if referenced...
- .global _need_user_vector_ // ... we pull-in this
- .global _xtos_l1int_handler // and this
-
-#endif
-
-
diff --git a/src/arch/xtensa/smp/xtos/user-vector-min.S b/src/arch/xtensa/smp/xtos/user-vector-min.S
deleted file mode 100644
index d8f19ea..0000000
--- a/src/arch/xtensa/smp/xtos/user-vector-min.S
+++ /dev/null
@@ -1,110 +0,0 @@
-// user-vector-min.S - Minimal User Vector for General Exceptions
-// Takes less table space, but does not allow registering new handlers.
-// $Id: //depot/rel/Foxhill/dot.8/Xtensa/OS/xtos/user-vector-min.S#1 $
-
-// Copyright (c) 2003-2015 Tensilica Inc.
-//
-// Permission is hereby granted, free of charge, to any person obtaining
-// a copy of this software and associated documentation files (the
-// "Software"), to deal in the Software without restriction, including
-// without limitation the rights to use, copy, modify, merge, publish,
-// distribute, sublicense, and/or sell copies of the Software, and to
-// permit persons to whom the Software is furnished to do so, subject to
-// the following conditions:
-//
-// The above copyright notice and this permission notice shall be included
-// in all copies or substantial portions of the Software.
-//
-// THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
-// EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
-// MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
-// IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY
-// CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
-// TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
-// SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
-
-#include <xtensa/coreasm.h>
-#include <xtensa/config/system.h>
-#include "xtos-internal.h"
-
-#if XCHAL_HAVE_EXCEPTIONS && (XCHAL_HAVE_XEA1 || XCHAL_HAVE_XEA2)
-
- // Vector code
- .begin literal_prefix .UserExceptionVector
- .section .UserExceptionVector.text, "ax"
- .align 4
- .global _UserExceptionVector
-_UserExceptionVector:
-# if (((XSHAL_USER_VECTOR_SIZE >= 28) && XCHAL_HAVE_ADDX && XCHAL_HAVE_DENSITY && XCHAL_HAVE_L32R) || (XSHAL_USER_VECTOR_SIZE >= 36) || XSHAL_VECTORS_PACKED) && !defined(XSHAL_ERRATUM_487_FIX)
-
- addi a1, a1, -ESF_TOTALSIZE // allocate exception stack frame, etc.
- s32i a2, a1, UEXC_a2
- s32i a3, a1, UEXC_a3
- rsr.exccause a2 // get exception cause
- movi a3, _xtos_min_handler_table
- bgeui a2, 6, 1f // causes 6 and above map to zero
- addx4 a3, a2, a3 // index by cause if 1 .. 5
-1: l32i a3, a3, 0
- s32i a4, a1, UEXC_a4
- jx a3 // jump to cause-specific handler
-
- .size _UserExceptionVector, . - _UserExceptionVector
- .end literal_prefix
-
-# else /*vector as small as 12 bytes:*/
-
- addi a1, a1, -ESF_TOTALSIZE // allocate exception stack frame, etc.
- s32i a2, a1, UEXC_a2
- movi a2, _UserExceptionFromVector // load user exception handler address
- //interlock
- jx a2 // jump to handler
-
- .size _UserExceptionVector, . - _UserExceptionVector
- .end literal_prefix
-
- // Dispatch outside vector:
- .text
- .align 4
- .global _UserExceptionFromVector
-_UserExceptionFromVector:
- hw_erratum_487_fix
- rsr.exccause a2 // get exception cause
- s32i a3, a1, UEXC_a3
- movi a3, _xtos_min_handler_table
- bgeui a2, 6, 1f // causes 6 and above map to zero
- addx4 a3, a2, a3 // index by cause if 1 .. 5
-1: l32i a3, a3, 0
- s32i a4, a1, UEXC_a4
- jx a3 // jump to cause-specific handler
- .size _UserExceptionFromVector, . - _UserExceptionFromVector
-
-# endif
-
-
- /*
- * Read-only minimal table of assembly-level exception handlers
- * for user vectored exceptions.
- * Only provides entries for SYSCALL, MOVSP, and level-1 interrupt causes.
- */
- .section .rodata, "a"
- .global _xtos_min_handler_table
- .align 4
-_xtos_min_handler_table:
- .word xtos_unhandled_exception // 0 Illegal Instruction, and causes > 5
- .word _xtos_syscall_handler // 1 SYSCALL Instruction
- .word xtos_unhandled_exception // 2 Instruction Fetch Error
- .word xtos_unhandled_exception // 3 Load/Store Error
-# if XCHAL_HAVE_INTERRUPTS
- .word _xtos_l1int_handler // 4 Level-1 Interrupt
-# else
- .word xtos_unhandled_exception // 4 Level-1 Interrupt (not configured)
-# endif
-# if XCHAL_HAVE_WINDOWED && !defined(__XTENSA_CALL0_ABI__)
- .word _xtos_alloca_handler // 5 Alloca (MOVSP Instruction)
-# else
- .word xtos_unhandled_exception // 5 Alloca (MOVSP Instruction) (not configured)
-# endif
- .text
-
-#endif /* XCHAL_HAVE_EXCEPTIONS */
-
diff --git a/src/arch/xtensa/smp/xtos/user-vector.S b/src/arch/xtensa/smp/xtos/user-vector.S
deleted file mode 100644
index 01c529a..0000000
--- a/src/arch/xtensa/smp/xtos/user-vector.S
+++ /dev/null
@@ -1,189 +0,0 @@
-// user-vector.S - User Vector for General Exceptions
-// $Id: //depot/rel/Foxhill/dot.8/Xtensa/OS/xtos/user-vector.S#1 $
-
-// Copyright (c) 1998-2015 Tensilica Inc.
-//
-// Permission is hereby granted, free of charge, to any person obtaining
-// a copy of this software and associated documentation files (the
-// "Software"), to deal in the Software without restriction, including
-// without limitation the rights to use, copy, modify, merge, publish,
-// distribute, sublicense, and/or sell copies of the Software, and to
-// permit persons to whom the Software is furnished to do so, subject to
-// the following conditions:
-//
-// The above copyright notice and this permission notice shall be included
-// in all copies or substantial portions of the Software.
-//
-// THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
-// EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
-// MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
-// IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY
-// CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
-// TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
-// SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
-
-#include <xtensa/coreasm.h>
-#include <xtensa/config/system.h>
-#include "xtos-internal.h"
-
-#if XCHAL_HAVE_EXCEPTIONS && (XCHAL_HAVE_XEA1 || XCHAL_HAVE_XEA2)
-
- // Vector code
- .section .UserExceptionVector.text, "ax"
- .align 4
- .global _UserExceptionVector
-_UserExceptionVector:
-# if (((XSHAL_USER_VECTOR_SIZE >= 28) && XCHAL_HAVE_ADDX && XCHAL_HAVE_DENSITY && XCHAL_HAVE_L32R) || (XSHAL_USER_VECTOR_SIZE >= 36) || XSHAL_VECTORS_PACKED) && !defined (XSHAL_ERRATUM_487_FIX)
- // There is space to dispatch right at the vector:
-
- addi a1, a1, -ESF_TOTALSIZE // allocate exception stack frame, etc.
- s32i a2, a1, UEXC_a2
- s32i a3, a1, UEXC_a3
- movi a3, xtos_exc_handler_table
- rsr.exccause a2 // get exception cause
- //interlock
- addx4 a3, a2, a3
- l32i a3, a3, 0
- s32i a4, a1, UEXC_a4
- jx a3 // jump to cause-specific handler
-
- .size _UserExceptionVector, . - _UserExceptionVector
-
-# else
- // The vector may be as small as 12 bytes:
-
- addi a1, a1, -ESF_TOTALSIZE // allocate exception stack frame, etc.
- s32i a2, a1, UEXC_a2
- movi a2, _UserExceptionFromVector // load user exception handler address
- //interlock
- jx a2 // jump to handler
-
- .size _UserExceptionVector, . - _UserExceptionVector
-
- // Dispatch outside vector:
- .text
- //.subsection 2
- .align 4
- .global _UserExceptionFromVector
-_UserExceptionFromVector:
- hw_erratum_487_fix
- s32i a3, a1, UEXC_a3
- movi a3, xtos_exc_handler_table
- rsr.exccause a2 // get exception cause
- s32i a4, a1, UEXC_a4
- addx4 a3, a2, a3
- l32i a3, a3, 0
- jx a3 // jump to cause-specific handler
-
- .size _UserExceptionFromVector, . - _UserExceptionFromVector
-
-# endif
-
-
- .weak xtos_cause3_handler
-
- /*
- * Table of assembly-level general-exception handlers
- * (quickly entered) for user vectored exceptions.
- * Provides entries for all possible 64 exception causes
- * currently allowed for in the EXCCAUSE register.
- *
- * NOTE: entries that have a corresponding C handler
- * (registered at run-time) point to xtos_c_wrapper_handler;
- * entries that have no handler point to xtos_unhandled_exception.
- */
- .section .rodata, "a"
- .global xtos_exc_handler_table_r
- .align 4
-xtos_exc_handler_table_r:
- .word xtos_unhandled_exception // 0 IllegalInstruction
- .word _xtos_syscall_handler // 1 Syscall
- .word xtos_unhandled_exception // 2 InstructionFetchError
- .word xtos_unhandled_exception // 3 LoadStoreError
-# if XCHAL_HAVE_INTERRUPTS
- .word _xtos_l1int_handler // 4 Level1Interrupt
-# else
- .word xtos_unhandled_exception // 4 Level1Interrupt (not configured)
-# endif
-# if XCHAL_HAVE_WINDOWED && !defined(__XTENSA_CALL0_ABI__)
- .word _xtos_alloca_handler // 5 Alloca (MOVSP)
-# else
- .word xtos_unhandled_exception // 5 Alloca (MOVSP) (not configured)
-# endif
- .word xtos_unhandled_exception // 6 IntegerDivideByZero
- .word xtos_unhandled_exception // 7 Speculation
- .word xtos_unhandled_exception // 8 Privileged
- .word xtos_unhandled_exception // 9 Unaligned
- .word xtos_unhandled_exception //10 (reserved for Tensilica)
- .word xtos_unhandled_exception //11 (reserved for Tensilica)
- .word xtos_cause3_handler //12 PIF data error on fetch
- .word xtos_cause3_handler //13 PIF data error on ld/st
- .word xtos_cause3_handler //14 PIF address error on fetch
- .word xtos_cause3_handler //15 PIF address error on ld/st
- .word xtos_unhandled_exception //16 InstTLBMiss
- .word xtos_unhandled_exception //17 InstTLBMultiHit
- .word xtos_unhandled_exception //18 InstFetchPrivilege
- .word xtos_unhandled_exception //19 (reserved for Tensilica)
- .word xtos_unhandled_exception //20 InstFetchProhibited
- .word xtos_unhandled_exception //21 (reserved for Tensilica)
- .word xtos_unhandled_exception //22 (reserved for Tensilica)
- .word xtos_unhandled_exception //23 (reserved for Tensilica)
- .word xtos_unhandled_exception //24 LoadStoreTLBMiss
- .word xtos_unhandled_exception //25 LoadStoreTLBMultiHit
- .word xtos_unhandled_exception //26 LoadStorePrivilege
- .word xtos_unhandled_exception //27 (reserved for Tensilica)
- .word xtos_unhandled_exception //28 LoadProhibited
- .word xtos_unhandled_exception //29 StoreProhibited
- .word xtos_unhandled_exception //30 (reserved for Tensilica)
- .word xtos_unhandled_exception //31 (reserved for Tensilica)
- .rept 8
- .word xtos_unhandled_exception //32-39 Coprocessor<n>Disabled (n = 0..7)
- .endr
-
- .rept XCHAL_EXCCAUSE_NUM-40
- .word xtos_unhandled_exception //40-63 (reserved for TIE)
- .endr
- .data
- .global xtos_exc_handler_table
- .align 4
-xtos_exc_handler_table:
- .space XCHAL_EXCCAUSE_NUM*4
- .text
-
-
- // NOTES:
- //
- // Here are alternative vectors. They will NOT work with
- // the handlers currently provided with XTOS. However they
- // might be useful to someone writing their own handlers
- // from scratch. Note that XSR is only available on T1040
- // and later hardware.
- //
-//*** The typical tiny 9-byte vector: ***
-// wsr.excsave1 a3 // save user a3
-// movi a3, _UserExceptionFromVector // load user exception handler address
-// jx a3
-//
-//*** Minimizing EXCCAUSE-dispatch delay, not assuming valid SP: ***
-// wsr.depc a0 // save a0 (double exceptions fatal here, so not expected)
-// rsr.exccause a0
-// xsr.excsave1 a1 // EXCSAVE_1 always contains &exception_handlers[0]
-// //interlock
-// addx4 a0, a0, a1
-// l32i a0, a0, TABLE_OFS + EXC_CODE_KERNEL*4
-// xsr.excsave1 a1 // restore a1 (DEPC contains original a0)
-// jx a0 // jump to cause-specific handler
-//
-//*** Doing EXCCAUSE-dispatch with table in EXCSAVE_1: ***
-// addi a1, a1, -ESF_TOTALSIZE // allocate exception stack frame, etc.
-// s32i a2, a1, UEXC_a2
-// rsr.exccause a2
-// xsr.excsave1 a4 // EXCSAVE_1 always contains &exception_handlers[0]
-// s32i a3, a1, UEXC_a3
-// addx4 a2, a2, a4
-// l32i a2, a2, TABLE_OFS + EXC_CODE_KERNEL*4
-// xsr.excsave1 a4 // restore a1 (DEPC contains original a0)
-// jx a2 // jump to cause-specific handler
-
-#endif /* XCHAL_HAVE_EXCEPTIONS */
-
diff --git a/src/arch/xtensa/smp/xtos/xea1/exc-alloca-handler.S b/src/arch/xtensa/smp/xtos/xea1/exc-alloca-handler.S
deleted file mode 100644
index c3b63fb..0000000
--- a/src/arch/xtensa/smp/xtos/xea1/exc-alloca-handler.S
+++ /dev/null
@@ -1,275 +0,0 @@
-// exc-alloca-handler.S - OBSOLETE - ALLOCA cause exception assembly-level handler
-
-#if 0 /* This handler is OBSOLETE - now part of window-vectors.S */
-
-// Copyright (c) 2002-2010 Tensilica Inc.
-//
-// Permission is hereby granted, free of charge, to any person obtaining
-// a copy of this software and associated documentation files (the
-// "Software"), to deal in the Software without restriction, including
-// without limitation the rights to use, copy, modify, merge, publish,
-// distribute, sublicense, and/or sell copies of the Software, and to
-// permit persons to whom the Software is furnished to do so, subject to
-// the following conditions:
-//
-// The above copyright notice and this permission notice shall be included
-// in all copies or substantial portions of the Software.
-//
-// THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
-// EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
-// MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
-// IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY
-// CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
-// TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
-// SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
-
-/*
- * Code written to the windowed ABI must use the MOVSP instruction to modify
- * the stack pointer (except for startup code, which doesn't have a caller).
- * The compiler uses MOVSP to allocate very large or variable size stack frames.
- * MOVSP guarantees that the caller frame's a0-a3 registers, stored below the
- * stack pointer, are moved atomically with respect to interrupts and exceptions
- * to satisfy windowed ABI requirements. When user code executes the MOVSP
- * instruction and the caller frame is on the stack rather than in the register
- * file, the processor takes an ALLOCA exception. The ALLOCA exception handler
- * moves the caller frame's a0-a3 registers to follow the stack pointer.
- * This file implements this ALLOCA exception handler.
- *
- * Code written in C can generate a MOVSP in four situations:
- *
- * 1. By calling "alloca":
- *
- * void foo(int array_size) {
- * char * bar = alloca(array_size);
- * ...
- *
- * 2. By using variable sized arrays (a GNU C extension):
- *
- * void foo(int array_size) {
- * char bar[array_size];
- * ...
- *
- * 3. By using nested C functions (also a GNU C extension):
- *
- * void afunction(void) {
- * ...
- * int anotherfunction(void) {
- * }
- * ...
- *
- * 4. By using very large amounts of stack space in a single function. The exact
- * limit is 32,760 bytes (including 16-48 bytes of caller frame overhead).
- * Typically, users don't encounter this limit unless they have functions
- * that locally declare large arrays, for example:
- *
- * void foo(void) {
- * int an_array[8192]; // 32,768 bytes
- * int another_array[100]; // 400 bytes
- * ...
- *
- *
- * NOTE: This handler only works when MOVSP's destination register is the stack
- * pointer "a1" (synonym with "sp"), i.e. "MOVSP a1, <as>". This is the only
- * meaningful form of MOVSP in the windowed ABI, and the only form generated
- * by the compiler and used in assembly. The code below does not check the
- * destination register, so other forms of MOVSP cause unexpected behaviour.
- */
-
-#include <xtensa/coreasm.h>
-#include "xtos-internal.h"
-
-#define ERROR_CHECKING 1 // define as 0 to save a few bytes
-
-
-#if XCHAL_HAVE_EXCEPTIONS
-
-//Vector:
-// addi a1, a1, -ESF_TOTALSIZE // allocate exception stack frame, etc.
-// s32i a2, a1, UEXC_a2
-// s32i a3, a1, UEXC_a3
-// movi a3, xtos_exc_handler_table
-// rsr.exccause a2
-// addx4 a2, a2, a3
-// l32i a2, a2, 0
-// s32i a4, a1, UEXC_a4
-// jx a2 // jump to cause-specific handler
-
- .global _need_user_vector_ // pull-in real user vector (tiny LSP)
-
- .text
- .align 4
- .global _xtos_alloca_handler
-_xtos_alloca_handler:
-#if !XCHAL_HAVE_WINDOWED || defined(__XTENSA_CALL0_ABI__)
- rfe_rfue
-#else /* we have windows w/o call0 abi */
- // HERE: a2, a3, a4 have been saved to
- // exception stack frame allocated with a1 (sp).
- // a2 contains EXCCAUSE.
- // (12 cycles from vector to here, assuming cache hits, 5-stage pipe, etc)
-
- /*
- * Skip the MOVSP instruction so we don't execute it again on return:
- */
-
- rsr.epc1 a3 // load instruction address (PC)
- s32i a5, a1, UEXC_a5 // save a5
- addi a2, a3, 3 // increment PC to skip MOVSP instruction
-#if XCHAL_HAVE_LOOPS
- /*
- * If the MOVSP instruction is the last instruction in the body of
- * a zero-overhead loop that must be executed again, then decrement
- * the loop count and resume execution at the head of the loop.
- */
- rsr.lend a4
- rsr.lcount a5
- bne a4, a2, 1f // done unless next-PC matches LEND
- beqz a5, 1f // if LCOUNT zero, not in loop
- addi a5, a5, -1 // z.o. loopback! decrement LCOUNT...
- wsr.lcount a5
- rsr.lbeg a2 // PC back to start of loop
-#endif /*XCHAL_HAVE_LOOPS*/
-1: wsr.epc1 a2 // update return PC past MOVSP
-
- /*
- * Figure out what register MOVSP is moving from ('s' field, 2nd byte).
- * If MOVSP is in an instruction RAM or ROM, we can only access it with
- * 32-bit loads. So use shifts to read the byte from a 32-bit load.
- */
-
- addi a3, a3, 1 // advance to byte containing 's' field
- extui a2, a3, 0, 2 // get bits 0 and 1 of address of this byte
- sub a3, a3, a2 // put address on 32-bit boundary
- l32i a3, a3, 0 // get word containing byte (can't use l8ui on IRAM/IROM)
- rsr.sar a4 // save SAR
- // NOTE: possible addition here: verify destination register is indeed a1.
-# if XCHAL_HAVE_BE
- ssa8b a2
- sll a3, a3
- extui a3, a3, 28, 4 // extract source register number
-# else
- ssa8l a2
- srl a3, a3
- extui a3, a3, 0, 4 // extract source register number
-# endif
- wsr.sar a4 // restore SAR
- // (+?? cycles max above = ?? cycles, assuming cache hits, 5-stage pipe, no zoloops, etc)
-
- movi a4, .Ljmptable // jump table
- mov a5, a1 // save the exception stack frame ptr in a5
- addi a1, a1, ESF_TOTALSIZE // restore a1 (in case of MOVSP a1,a1)
-
-# if XCHAL_HAVE_DENSITY
- addx4 a4, a3, a4 // index by src reg number * 4
-# define ALIGN .align 4 // 4-byte jmptable entries
-# define MOV _mov.n
-# define L32I _l32i.n
-# define DONE _bnez.n a4, .Lmove_save_area // a4 known non-zero
-# else
- addx8 a4, a3, a4 // index by src reg number * 8
-# define ALIGN .align 8 // 8-byte jmptable entries
-# define MOV mov
-# define L32I l32i
-# define DONE j .Lmove_save_area
-# endif
-
- jx a4 // jump into the following table
-
- ALIGN
-.Ljmptable: MOV a1, a0 ; DONE // MOVSP a1, a0
- ALIGN ; DONE // MOVSP a1, a1
- ALIGN ; L32I a1, a5, UEXC_a2 ; DONE // MOVSP a1, a2
- ALIGN ; L32I a1, a5, UEXC_a3 ; DONE // MOVSP a1, a3
- ALIGN ; L32I a1, a5, UEXC_a4 ; DONE // MOVSP a1, a4
- ALIGN ; L32I a1, a5, UEXC_a5 ; DONE // MOVSP a1, a5
- ALIGN ; MOV a1, a6 ; DONE // MOVSP a1, a6
- ALIGN ; MOV a1, a7 ; DONE // MOVSP a1, a7
- ALIGN ; MOV a1, a8 ; DONE // MOVSP a1, a8
- ALIGN ; MOV a1, a9 ; DONE // MOVSP a1, a9
- ALIGN ; MOV a1, a10 ; DONE // MOVSP a1, a10
- ALIGN ; MOV a1, a11 ; DONE // MOVSP a1, a11
- ALIGN ; MOV a1, a12 ; DONE // MOVSP a1, a12
- ALIGN ; MOV a1, a13 ; DONE // MOVSP a1, a13
- ALIGN ; MOV a1, a14 ; DONE // MOVSP a1, a14
- ALIGN ; MOV a1, a15 // MOVSP a1, a15
-
-.Lmove_save_area:
- // Okay. a1 now contains the new SP value.
-
-# if ERROR_CHECKING
- // Verify it is sensible:
- extui a3, a1, 0, 2 // verify that new SP is 4-byte aligned
- beqz a3, 1f // if so, skip fixup
-
-// .global _xtos_misaligned_movsp // make label visible for debugging
-//_xtos_misaligned_movsp:
-# if XCHAL_HAVE_DEBUG
- break 1, 15 // break into debugger (if any)
-# endif
- sub a1, a1, a3 // FORCE alignment of the new pointer (!)
-1:
-# endif
-
-# if XCHAL_HAVE_XEA2
- addi a2, a5, ESF_TOTALSIZE // compute a2 = old SP
-# else /*XEA1:*/
- addi a2, a5, ESF_TOTALSIZE-16 // compute a2 = old SP's save area
-# endif
- // Does new SP (in a1) overlap with exception stack frame (in a5)?:
- movi a4, ESF_TOTALSIZE // size of exception stack frame
- sub a3, a1, a5 // distance from ESF ptr to new SP
- bgeu a3, a4, 1f // does new SP overlap ESF? branch if not
- // Move ESF down so it doesn't overlap with the new register save area:
- // (a1 = current ESF, a2 = new SP, a4 = ESF_TOTALSIZE)
- sub a5, a5, a4 // shift down ESF (by ESF size)
- l32i a3, a5, UEXC_a2+ESF_TOTALSIZE
- l32i a4, a5, UEXC_a3+ESF_TOTALSIZE
- s32i a3, a5, UEXC_a2
- s32i a4, a5, UEXC_a3
- l32i a3, a5, UEXC_a4+ESF_TOTALSIZE
- l32i a4, a5, UEXC_a5+ESF_TOTALSIZE
- s32i a3, a5, UEXC_a4
- s32i a4, a5, UEXC_a5
-1:
-
- // Move the register save area (from old SP to new SP):
-# if XCHAL_HAVE_XEA2
- l32e a3, a2, -16
- l32e a4, a2, -12
- s32e a3, a1, -16
- s32e a4, a1, -12
- l32e a3, a2, -8
- l32e a4, a2, -4
- s32e a3, a1, -8
- s32e a4, a1, -4
-# else /*XEA1:*/
- addi a1, a1, -16 // point to new save area
- l32i a3, a2, 0
- l32i a4, a2, 4
- s32i a3, a1, 0
- s32i a4, a1, 4
- l32i a3, a2, 8
- l32i a4, a2, 12
- s32i a3, a1, 8
- s32i a4, a1, 12
- addi a1, a1, 16 // back to correct new SP
-# endif /*XEA1*/
- // (+?? cycles max above = ?? cycles, assuming cache hits, 5-stage pipe, etc)
-
- // Restore a2, a3, a4, a5, and return:
- l32i a2, a5, UEXC_a2
- l32i a3, a5, UEXC_a3
- l32i a4, a5, UEXC_a4
- l32i a5, a5, UEXC_a5
- rfe_rfue
- // (+?? cycles max above = ?? cycles, assuming cache hits, 5-stage pipe, etc)
-
-
-#endif /* !XCHAL_HAVE_WINDOWED || __XTENSA_CALL0_ABI */
-
- .size _xtos_alloca_handler, . - _xtos_alloca_handler
-
-#endif /* XCHAL_HAVE_EXCEPTIONS */
-
-#endif /* 0 */
-
diff --git a/src/arch/xtensa/smp/xtos/xea1/exc-c-wrapper-handler.S b/src/arch/xtensa/smp/xtos/xea1/exc-c-wrapper-handler.S
deleted file mode 100644
index 9937e8f..0000000
--- a/src/arch/xtensa/smp/xtos/xea1/exc-c-wrapper-handler.S
+++ /dev/null
@@ -1,374 +0,0 @@
-// xea1/exc-c-wrapper-handler.S - General Exception Handler that Dispatches C Handlers
-
-// Copyright (c) 2002-2016 Tensilica Inc.
-//
-// Permission is hereby granted, free of charge, to any person obtaining
-// a copy of this software and associated documentation files (the
-// "Software"), to deal in the Software without restriction, including
-// without limitation the rights to use, copy, modify, merge, publish,
-// distribute, sublicense, and/or sell copies of the Software, and to
-// permit persons to whom the Software is furnished to do so, subject to
-// the following conditions:
-//
-// The above copyright notice and this permission notice shall be included
-// in all copies or substantial portions of the Software.
-//
-// THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
-// EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
-// MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
-// IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY
-// CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
-// TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
-// SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
-
-#include <xtensa/coreasm.h>
-#include <xtensa/corebits.h>
-#include <xtensa/config/specreg.h>
-#include "../xtos-internal.h"
-#ifdef SIMULATOR
-#include <xtensa/simcall.h>
-#endif
-
-#if XCHAL_HAVE_XEA1 && XCHAL_HAVE_EXCEPTIONS /* note - XEA1 always has exceptions */
-
-
-/*
- * This assembly-level handler causes the associated exception (usually causes 12-15)
- * to be handled as if it were exception cause 3 (load/store error exception).
- * This provides forward-compatibility with a possible future split of the
- * load/store error cause into multiple more specific causes.
- */
- .align 4
- .global xtos_cause3_handler
-xtos_cause3_handler:
- movi a2, EXCCAUSE_LOAD_STORE_ERROR
- j xtos_c_wrapper_handler
- .size xtos_cause3_handler, . - xtos_cause3_handler
-
-
-/*
- * This is the general exception assembly-level handler that dispatches C handlers.
- */
- .align 4
- .global xtos_c_wrapper_handler
-xtos_c_wrapper_handler:
-#ifdef __XTENSA_CALL0_ABI__
- // Redundantly de-allocate and re-allocate stack, so that GDB prologue
- // analysis picks up the allocate part, and figures out how to traceback
- // through the call stack through the exception.
- addi a1, a1, ESF_TOTALSIZE // de-allocate stack frame (FIXME is it safe)
-.global xtos_c_wrapper_dispatch
-xtos_c_wrapper_dispatch:
- // GDB starts analyzing prologue after most recent global symbol, so here:
- addi a1, a1, -ESF_TOTALSIZE // re-allocate stack frame
-#endif
-
- // HERE: a2, a3, a4 have been saved to exception stack frame allocated with a1 (sp).
- // a2 contains EXCCAUSE.
- s32i a5, a1, UEXC_a5 // a5 will get clobbered by ENTRY after the pseudo-CALL4
- // (a4..a15 spilled as needed; save if modified)
-
- //NOTA: Possible future improvement:
- // keep interrupts disabled until we get into the handler, such that
- // we don't have to save other critical state such as EXCVADDR here.
- //rsr.excvaddr a3
- s32i a2, a1, UEXC_exccause
- //s32i a3, a1, UEXC_excvaddr
-
-#if XCHAL_HAVE_INTERRUPTS
- rsilft a3, 1, XTOS_LOCKLEVEL // lockout
- rsr.intenable a2
- //movi a3, ~XCHAL_EXCM_MASK
- movi a3, ~XTOS_LOCKOUT_MASK // mask out low and medium priority levels, and high priority levels covered by
- // XTOS_LOCKLEVEL if any, so we can run at PS.INTLEVEL=0 while manipulating INTENABLE
- s32i a2, a1, UEXC_sar // (temporary holding place for INTENABLE value to restore after pseudo-CALL4 below)
- and a3, a2, a3 // mask out selected interrupts
- wsr.intenable a3 // disable all interrupts up to and including XTOS_LOCKLEVEL
-#endif
- movi a3, PS_WOECALL4_ABI|PS_UM // WOE=0|1, UM=1, INTLEVEL=0, CALLINC=0|1 (call4 emul), OWB=(dontcare)=0
-
- // NOTE: could use XSR here if targeting T1040 or T1050 hardware (requiring slight sequence adjustment as for XEA2):
- rsr.ps a2
- rsync //NOT-ISA-DEFINED // wait for WSR to INTENABLE to complete before clearing PS.INTLEVEL
- wsr.ps a3 // PS.INTLEVEL=0, effective INTLEVEL (via INTENABLE) is XTOS_LOCKLEVEL
-
- // HERE: window overflows enabled, but NOT SAFE because we're not quite
- // in a valid windowed context (haven't restored a1 yet...);
- // so don't cause any (keep to a0..a3) until we've saved critical state and restored a1:
-
- // NOTE: MUST SAVE EPC1 before causing any overflows, because overflows corrupt EPC1.
- rsr.epc1 a3
- s32i a2, a1, UEXC_ps
- s32i a3, a1, UEXC_pc
-
-
-#ifdef __XTENSA_CALL0_ABI__
-
- s32i a0, a1, UEXC_a0 // save the rest of the registers
- s32i a6, a1, UEXC_a6
- s32i a7, a1, UEXC_a7
- s32i a8, a1, UEXC_a8
- s32i a9, a1, UEXC_a9
- s32i a10, a1, UEXC_a10
- s32i a11, a1, UEXC_a11
- s32i a12, a1, UEXC_a12
- s32i a13, a1, UEXC_a13
- s32i a14, a1, UEXC_a14
- s32i a15, a1, UEXC_a15
-# if XTOS_DEBUG_PC
- // TODO: setup return PC for call traceback through interrupt dispatch
-# endif
-
- rsync // wait for WSR to PS to complete
-
-#else /* ! __XTENSA_CALL0_ABI__ */
-
-# if XTOS_CNEST
- l32i a2, a1, ESF_TOTALSIZE-20 // save nested-C-func call-chain ptr
-# endif
- addi a1, a1, ESF_TOTALSIZE // restore sp (dealloc ESF) for sane stack again
- rsync // wait for WSR to PS to complete
-
- /* HERE: we can SAFELY get window overflows.
- *
- * From here, registers a4..a15 automatically get spilled if needed.
- * They become a0..a11 after the ENTRY instruction.
- * Currently, we don't check whether or not these registers
- * get spilled, so we must save and restore any that we
- * modify. We've already saved a4 and a5
- * which we modify as part of the pseudo-CALL.
- *
- * IMPLEMENTATION NOTE:
- *
- * The pseudo-CALL below effectively saves registers a2..a3 so
- * that they are available again after the corresponding
- * RETW when returning from the exception handling. We
- * could choose to put something like EPC1 or PS in
- * there, so they're available more quickly when
- * restoring. HOWEVER, exception handlers may wish to
- * change such values, or anything on the exception stack
- * frame, and expect these to be restored as modified.
- *
- * NOTA: future: figure out what's the best thing to put
- * in a2 and a3. (candidate: a4 and a5 below; but what
- * if exception handler manipulates ARs, as in a syscall
- * handler.... oh well)
- *
- *
- * Now do the pseudo-CALL.
- * Make it look as if the code that got the exception made a
- * CALL4 to the exception handling code. (We call
- * this the "pseudo-CALL".)
- *
- * This pseudo-CALL is important and done this way:
- *
- * 1. There are only three ways to safely update the stack pointer
- * in the windowed ABI, such that window exceptions work correctly:
- * (a) spill all live windows to stack then switch to a new stack
- * (or, save the entire address register file and window
- * registers, which is likely even more expensive)
- * (b) use MOVSP (or equivalent)
- * (c) use ENTRY/RETW
- * Doing (a) is excessively expensive, and doing (b) here requires
- * copying 16 bytes back and forth which is also time-consuming;
- * whereas (c) is very efficient, so that's what we do here.
- *
- * 2. Normally we cannot do a pseudo-CALL8 or CALL12 here.
- * According to the
- * windowed ABI, a function must allocate enough space
- * for the largest call that it makes. However, the
- * pseudo-CALL is executed in the context of the
- * function that happened to be executing at the time
- * the interrupt was taken, and that function might or
- * might not have allocated enough stack space for a
- * CALL8 or a CALL12. If we try doing a pseudo-CALL8
- * or -CALL12 here, we corrupt the stack if the
- * interrupted function happened to not have allocated
- * space for such a call.
- *
- * 3. We set the return PC, but it's not strictly
- * necessary for proper operation. It does make
- * debugging, ie. stack tracebacks, much nicer if it
- * can point to the interrupted code (not always
- * possible, eg. if interrupted code is in a different
- * GB than the interrupt handling code, which is
- * unlikely in a system without protection where
- * interrupt handlers and general application code are
- * typically linked together).
- *
- * IMPORTANT: Interrupts must stay disabled while doing the pseudo-CALL,
- * or at least until after the ENTRY instruction, because SP has been
- * restored to its original value that does not reflect the exception
- * stack frame's allocation. An interrupt taken here would
- * corrupt the exception stack frame (ie. allocate another over it).
- * (High priority interrupts can remain enabled, they save and restore
- * all of their state and use their own stack or save area.)
- * For the same reason, we mustn't get any exceptions in this code
- * (other than window exceptions where noted) until ENTRY is done.
- */
-
- // HERE: may get a single window overflow (caused by the following instruction).
-
-# if XTOS_DEBUG_PC
- movi a4, 0xC0000000 // [for debug] for return PC computation below
- or a3, a4, a3 // [for debug] set upper two bits of return PC
- addx2 a4, a4, a3 // [for debug] clear upper bit
-# else
- movi a4, 0 // entry cannot cause overflow, cause it here
-# endif
-
- .global _GeneralException
-_GeneralException: // this label makes tracebacks through exceptions look nicer
-
- _entry a1, ESF_TOTALSIZE // as if after a CALL4 (PS.CALLINC set to 1 above)
-
- /*
- * The above ENTRY instruction does a number of things:
- *
- * 1. Because we're emulating CALL4, the ENTRY rotates windows
- * forward by 4 registers (as per 'ROTW +1'), so that
- * a4-a15 became a0-a11. So now: a0-a11 are part of
- * the interrupted context to be preserved. a0-a1
- * were already saved above when they were a4-a5.
- * a12-a15 are free to use as they're NOT part of the
- * interrupted context. We don't need to save/restore
- * them, and they will get spilled if needed.
- *
- * 2. Updates SP (new a1), allocating the exception stack
- * frame in the new window, preserving the old a1 in
- * the previous window.
- *
- * 3. The underscore prefix prevents the assembler from
- * automatically aligning the ENTRY instruction on a
- * 4-byte boundary, which could create a fatal gap in
- * the instruction stream.
- *
- * At this point, ie. before we re-enable interrupts, we know the caller is
- * always live so we can safely modify a1 without using MOVSP (we can use MOVSP
- * but it will never cause an ALLOCA or underflow exception here).
- * So this is a good point to modify the stack pointer if we want eg. to
- * switch to an interrupt stack (if we do, we need to save the current SP
- * because certain things have been saved to that exception stack frame).
- * We couldn't do this easily before ENTRY, where the caller wasn't
- * necessarily live.
- *
- * NOTE: We don't switch to an interrupt stack here, because exceptions
- * are generally caused by executing code -- so we handle exceptions in
- * the context of the thread that cause them, and thus remain on the same
- * stack. This means a thread's stack must be large enough to handle
- * the maximum level of nesting of exceptions that the thread can cause.
- */
-
- // NOTA: exception handlers for certain causes may need interrupts to be kept
- // disabled through their dispatch, so they can turn them off themselves at
- // the right point (if at all), eg. to save critical state unknown to this
- // code here, or for some recovery action that must be atomic with respect
- // to interrupts....
- //
- // Perhaps two versions of this assembly-level handler are needed, one that restores
- // interrupts to what they were before the exception was taken (as here)
- // and one that ensures at least low-priority interrupts are kept disabled?
- // NOTA: For now, always enable interrupts here.
-
- /*
- * Now we can enable interrupts.
- * (Pseudo-CALL is complete, and SP reflects allocation of exception stack frame.)
- */
-
-#endif /* __XTENSA_CALL0_ABI__ */
-
-
-#if XCHAL_HAVE_INTERRUPTS
- //... recompute and set INTENABLE ...
- l32i a13, a1, UEXC_sar // (temporary holding place for INTENABLE value saved before pseudo-CALL4 above)
- rsr.sar a12
- wsr.intenable a13 // restore INTENABLE as it was on entry
-#else
- rsr.sar a12
-#endif
-
- movi a13, xtos_c_handler_table // &table
- l32i a15, a1, UEXC_exccause // arg2: exccause
-
- s32i a12, a1, UEXC_sar
- save_loops_mac16 a1, a12, a14 // save LOOP & MAC16 regs, if configured
-
- addx4 a12, a15, a13 // a12 = table[exccause]
- l32i a12, a12, 0 // ...
-#ifdef __XTENSA_CALL0_ABI__
- mov a2, a1 // arg1: exception parameters
- mov a3, a15 // arg2: exccause
- beqz a12, 1f // null handler => skip call
- callx0 a12 // call C exception handler for this exception
-#else
- mov a14, a1 // arg1: exception parameters
- // mov a15, a15 // arg2: exccause, already in a15
- beqz a12, 1f // null handler => skip call
- callx12 a12 // call C exception handler for this exception
-#endif
-1:
- // Now exit the handler.
-
-
- // Restore special registers
-
- restore_loops_mac16 a1, a13, a14, a15 // restore LOOP & MAC16 regs, if configured
- l32i a14, a1, UEXC_sar
-
- /*
- * Disable interrupts while returning from the pseudo-CALL setup above,
- * for the same reason they were disabled while doing the pseudo-CALL:
- * this sequence restores SP such that it doesn't reflect the allocation
- * of the exception stack frame, which we still need to return from
- * the exception.
- */
-
-#if XCHAL_HAVE_INTERRUPTS
- // Must disable interrupts via INTENABLE, because PS.INTLEVEL gets zeroed
- // by any window exception exit, eg. the window underflow that may happen
- // upon executing the RETW instruction.
- // Also, must disable at XTOS_LOCKLEVEL, not just EXCM_LEVEL, because this
- // code effectively manipulates virtual INTENABLE state up to the point
- // INTENABLE is written in _xtos_return_from_exc.
- //
- rsilft a12, 1, XTOS_LOCKLEVEL // lockout
- rsr.intenable a12
- //movi a13, ~XCHAL_EXCM_MASK
- movi a13, ~XTOS_LOCKOUT_MASK // mask out low and medium priority levels, and high priority levels covered by
- // XTOS_LOCKLEVEL if any, so we can run at PS.INTLEVEL=0 while manipulating INTENABLE
- s32i a12, a1, UEXC_sar // (temporary holding place for INTENABLE value to restore after pseudo-CALL4 below)
- and a13, a12, a13 // mask out selected interrupts
- wsr.intenable a13 // disable all interrupts up to and including XTOS_LOCKLEVEL
-#endif
- wsr.sar a14
-
- movi a0, _xtos_return_from_exc
-#ifdef __XTENSA_CALL0_ABI__
- jx a0
-#else /* ! __XTENSA_CALL0_ABI__ */
- /* Now return from the pseudo-CALL from the interrupted code, to rotate
- * our windows back... */
-
- movi a13, 0xC0000000
- //movi a13, 3
- //slli a13, a13, 30
-# if XCHAL_HAVE_INTERRUPTS
- rsync //NOT-ISA-DEFINED // wait for WSR to INTENABLE to complete before doing RETW
- // (ie. before underflow exception exit)
- // (not needed, because underflow exception entry does implicit ISYNC ??
- // but in case underflow not taken, WSR must complete before wsr to PS that lowers PS.INTLEVEL
- // possibly below XTOS_LOCKLEVEL, in which RETW's jump is not sufficient sync, so a sync
- // is needed but it can be placed just before WSR to PS -- but here is fine)
-# endif
- or a0, a0, a13 // set upper two bits
- addx2 a0, a13, a0 // clear upper bit
- retw
-#endif /* ! __XTENSA_CALL0_ABI__ */
-
- /* FIXME: what about _GeneralException ? */
-
- .size xtos_c_wrapper_handler, . - xtos_c_wrapper_handler
-
-
-#endif /* XCHAL_HAVE_XEA1 && XCHAL_HAVE_EXCEPTIONS */
-
diff --git a/src/arch/xtensa/smp/xtos/xea1/exc-return.S b/src/arch/xtensa/smp/xtos/xea1/exc-return.S
deleted file mode 100644
index 25bfa32..0000000
--- a/src/arch/xtensa/smp/xtos/xea1/exc-return.S
+++ /dev/null
@@ -1,123 +0,0 @@
-// xea1/exc-return.S - Shared exception/interrupt return code
-
-// Copyright (c) 2002-2016 Tensilica Inc.
-//
-// Permission is hereby granted, free of charge, to any person obtaining
-// a copy of this software and associated documentation files (the
-// "Software"), to deal in the Software without restriction, including
-// without limitation the rights to use, copy, modify, merge, publish,
-// distribute, sublicense, and/or sell copies of the Software, and to
-// permit persons to whom the Software is furnished to do so, subject to
-// the following conditions:
-//
-// The above copyright notice and this permission notice shall be included
-// in all copies or substantial portions of the Software.
-//
-// THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
-// EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
-// MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
-// IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY
-// CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
-// TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
-// SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
-
-#include <xtensa/coreasm.h>
-#include <xtensa/corebits.h>
-#include <xtensa/config/specreg.h>
-#include "../xtos-internal.h"
-
-#if XCHAL_HAVE_XEA1 && XCHAL_HAVE_EXCEPTIONS /* XEA1 always has exceptions */
-
- .text
- .align 4
- .global _xtos_return_from_exc
-_xtos_return_from_exc:
-
-#ifdef __XTENSA_CALL0_ABI__
-
- l32i a0, a1, UEXC_a0 // restore general registers, pc, ps
- l32i a4, a1, UEXC_a4
- l32i a5, a1, UEXC_a5
- l32i a6, a1, UEXC_a6
- l32i a7, a1, UEXC_a7
- l32i a8, a1, UEXC_a8
- l32i a9, a1, UEXC_a9
- l32i a10, a1, UEXC_a10
- l32i a11, a1, UEXC_a11
- l32i a12, a1, UEXC_a12
- l32i a13, a1, UEXC_a13
- l32i a14, a1, UEXC_a14
- l32i a15, a1, UEXC_a15
-
- l32i a2, a1, UEXC_pc
- l32i a3, a1, UEXC_ps
- wsr.epc1 a2
- wsr.ps a3
-
- l32i a2, a1, UEXC_a2
- l32i a3, a1, UEXC_a3
-
- rsync // wait for WSR to PS to complete
-
- addi a1, a1, ESF_TOTALSIZE // restore sp
-
- rfe
-
-#else /* ! __XTENSA_CALL0_ABI__ */
-
-
- // Here we rotated back by N registers, to the interrupted code's register window.
- // NOTA: a2 and a3 might contain something useful, but we haven't determined
- // what that might be yet (for now, a2 contains nested-C-func call-chain ptr).
-
- // NOTE: a5 still contains the exception window's exception stack frame pointer.
-
-# if XTOS_CNEST
- s32i a2, a5, ESF_TOTALSIZE-20 // restore nested-C-func call-chain ptr
-# endif
- l32i a2, a5, UEXC_ps
- l32i a3, a5, UEXC_pc
- wsr.ps a2 // this sets INTLEVEL to 1; ...
-
-# if XCHAL_HAVE_INTERRUPTS
- l32i a4, a5, UEXC_sar // load INTENABLE value that restores original vpri
- l32i a2, a5, UEXC_a2
- rsync // wait for WSR to PS to complete
- wsr.intenable a4 // update INTENABLE to restore original vpri (PS.INTLEVEL=1 here)
- l32i a4, a5, UEXC_a4
-# else
- l32i a2, a5, UEXC_a2
- l32i a4, a5, UEXC_a4
- rsync // wait for WSR to PS to complete
-# endif
-
- /* FIXME: Enabling this here may break task-engine builds
- * because task engines have exceptions (sort of), but they do
- * not have the EPC_1 special register. XCHAL_HAVE_INTERRUPTS
- * is incorrect for normal configs without interrupts but with
- * exceptions (we still need to restore EPC_1). The correct
- * solution is to define XCHAL_HAVE_EXCEPTIONS more strictly
- * to mean something like "Have exceptions with
- * user/kernel/double vectors" so that task engines are
- * excluded. This would be a change to
- * <xtensa/config/core.h>. */
-
- wsr.epc1 a3
- // HERE:
- // - we cannot get window overflows anymore -- we're NOT in a valid windowed context
- // - low-priority interrupts are still disabled
-
- // NOTE: we don't restore EXCCAUSE or EXCVADDR, not needed.
-
- // Restore a3, a5:
- l32i a3, a5, UEXC_a3
- l32i a5, a5, UEXC_a5
-
- rfe_rfue
-
-#endif /* __XTENSA_CALL0_ABI__ */
-
- .size _xtos_return_from_exc, . - _xtos_return_from_exc
-
-#endif /* XCHAL_HAVE_XEA1 && XCHAL_HAVE_EXCEPTIONS */
-
diff --git a/src/arch/xtensa/smp/xtos/xea1/int-lowpri-dispatcher.S b/src/arch/xtensa/smp/xtos/xea1/int-lowpri-dispatcher.S
deleted file mode 100644
index 6195eb7..0000000
--- a/src/arch/xtensa/smp/xtos/xea1/int-lowpri-dispatcher.S
+++ /dev/null
@@ -1,610 +0,0 @@
-// XEA1 - Level-one interrupt dispatcher (user vectored handler)
-
-// Copyright (c) 1999-2016 Tensilica Inc.
-//
-// Permission is hereby granted, free of charge, to any person obtaining
-// a copy of this software and associated documentation files (the
-// "Software"), to deal in the Software without restriction, including
-// without limitation the rights to use, copy, modify, merge, publish,
-// distribute, sublicense, and/or sell copies of the Software, and to
-// permit persons to whom the Software is furnished to do so, subject to
-// the following conditions:
-//
-// The above copyright notice and this permission notice shall be included
-// in all copies or substantial portions of the Software.
-//
-// THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
-// EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
-// MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
-// IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY
-// CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
-// TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
-// SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
-
-#include <xtensa/coreasm.h>
-#include <xtensa/config/specreg.h>
-#include "../xtos-internal.h"
-#include "../interrupt-pri.h"
-
-#if XCHAL_HAVE_XEA1 && XCHAL_HAVE_EXCEPTIONS && XCHAL_HAVE_INTERRUPTS
-
-
- /*
- * Macros to slightly reduce the number of #if statements in the code:
- */
-
-/* This is set (for #if only) if there is only ONE interrupt configured at level one: */
-#define XTOS_SINGLE_INT defined(XCHAL_INTLEVEL1_NUM)
-
-/* Simplify the #if's around saving and restoring of SAR ('#' is a comment char): */
-#if ((XTOS_SUBPRI_ORDER == XTOS_SPO_ZERO_LO) || (XTOS_INT_FAIRNESS && XTOS_SUBPRI)) && !XTOS_SINGLE_INT
-# define NEEDSAR /* need SAR saved early w/ints locked */
-# define LATESAR # /* need SAR saved late w/ints unlocked */
-#else
-# define NEEDSAR # /* need SAR saved early w/ints locked */
-# define LATESAR /* need SAR saved late w/ints unlocked */
-#endif
-
-/* Simplify the #if's around fairness-specific code ('#' is a comment char): */
-#if XTOS_INT_FAIRNESS
-# define IFFAIR /* for code enabled only for fairness */
-# define NOFAIR # /* for code enabled only without fairness */
-#else
-# define IFFAIR # /* for code enabled only for fairness */
-# define NOFAIR /* for code enabled only without fairness */
-#endif
-/*
- * Note about implementation of "fairness".
- * The fairness mask is meant to represent, among a set of interrupts pending
- * at the same time, which ones haven't yet been serviced. It's to avoid,
- * among interrupts simultaneously pending at the same priority level,
- * servicing an interrupt more than once before servicing another.
- * Without the mask, if we for example just always serviced the lowest
- * numbered pending interrupt, then a lower numbered interrupt might get
- * serviced many times before servicing a higher numbered one, even though
- * they're at the same priority and pending at the same time -- thus an
- * "unfair" situation.
- * The typical way to do this fairly is to loop looking at each interrupt
- * number in sequence, determining whether that interrupt needs servicing,
- * and to repeat looping if at least one interrupt was serviced (or at
- * one remains pending).
- * Using the mask is faster, as we only look at pending interrupts,
- * instead of looping looking at all interrupts.
- */
-
-
- // NOTE: something equivalent to the following vector is executed
- // before entering this handler (see user-vector.S).
-//_UserExceptionVector:
-// addi a1, a1, -ESF_TOTALSIZE // allocate exception stack frame, etc.
-// s32i a2, a1, UEXC_a2
-// s32i a3, a1, UEXC_a3
-// movi a3, xtos_exc_handler_table
-// rsr.exccause a2
-// addx4 a2, a2, a3
-// l32i a2, a2, 0
-// s32i a4, a1, UEXC_a4
-// jx a2 // jump to cause-specific handler
-
- .global _need_user_vector_ // pull-in real user vector (tiny LSP)
-
- .text
- .align 4
- .global _xtos_l1int_handler
-_xtos_l1int_handler:
- // HERE: a2, a3, a4 have been saved to exception stack frame allocated with a1 (sp).
-
- s32i a5, a1, UEXC_a5 // a5 will get clobbered by ENTRY after pseudo-CALL4
- // (a4..a15 spilled as needed; save if modified)
-
- // Would need to save & clear LCOUNT only with protection. None here.
- // No need to save EXCVADDR or EXCCAUSE for low-priority interrupts.
-#if 1
- rsr.interrupt a2 // read INTERRUPT while PS.INTLEVEL is 1 and INTENABLE is intact
- rsilft a3, 1, XTOS_LOCKLEVEL // lockout
- s32i a2, a1, UEXC_vpri // save for interrupt computation
- rsr.intenable a2
- movi a3, XTOS_UNLOCKABLE_MASK // mask out level one, and high levels covered by XTOS_LOCKLEVEL if any,
- // so we can run at PS.INTLEVEL=0 while manipulating INTENABLE
- s32i a2, a1, UEXC_sar // save old INTENABLE, to handle the spurious interrupt case
- and a3, a2, a3 // mask out selected interrupts
- wsr.intenable a3 // disable all interrupts up to and including XTOS_LOCKLEVEL
-#else
- // Using this alternate code requires extensive changes elsewhere;
- // its only advantage is potentially lowered latency of interrupts
- // of priority levels 2 thru XTOS_LOCKLEVEL:
- xtos_addr_percore a2, xtos_intstruct // address of interrupt management globals
- rsilft a3, 1, XTOS_LOCKLEVEL // lockout
- l32i a3, a2, XTOS_VPRI_ENABLED_OFS // read previous _xtos_vpri_enabled
- //interlock
- s32i a3, a1, UEXC_vpri // save previous vpri
- movi a3, ~XCHAL_EXCM_MASK // mask out all low-priority interrupts
- // so we can run at PS.INTLEVEL=0 while ESF allocation not reflected in SP
- //interlock
- s32i a3, a2, XTOS_VPRI_ENABLED_OFS // set new _xtos_vpri_enabled (mask all low-priority interrupts)
- l32i a2, a2, XTOS_ENABLED_OFS // read _xtos_enabled
- //interlock
- and a3, a2, a3 // mask out selected interrupts
- wsr.intenable a3 // disable all low-priority interrupts
-#endif
- movi a3, PS_WOECALL4_ABI|PS_UM // WOE=0|1, UM=1, INTLEVEL=0, CALLINC=0|1 (call4 emul), OWB=(dontcare)=0
-
- // NOTE: could use XSR here if targeting T1040 or T1050 hardware (requiring slight sequence adjustment as for XEA2):
- rsr.ps a2
- rsync //NOT-ISA-DEFINED // wait for WSR to INTENABLE to complete before clearing PS.INTLEVEL
- wsr.ps a3 // PS.INTLEVEL=0, effective INTLEVEL (via INTENABLE) is XTOS_LOCKLEVEL (NOTA: LOWPRI_LEVELS)
-
- // HERE: window overflows enabled, but NOT SAFE because we're not quite
- // in a valid windowed context (haven't restored a1 yet...);
- // so don't cause any (keep to a0..a3) until we've saved critical state and restored a1:
-
- // NOTE: MUST SAVE EPC1 before causing any overflows, because overflows corrupt EPC1.
- rsr.epc1 a3
- s32i a2, a1, UEXC_ps
- s32i a3, a1, UEXC_pc
-
-
-#ifdef __XTENSA_CALL0_ABI__
-
- s32i a0, a1, UEXC_a0 // save the rest of the registers
- s32i a6, a1, UEXC_a6
- s32i a7, a1, UEXC_a7
- s32i a8, a1, UEXC_a8
- s32i a9, a1, UEXC_a9
- s32i a10, a1, UEXC_a10
- s32i a11, a1, UEXC_a11
- s32i a12, a1, UEXC_a12
- s32i a13, a1, UEXC_a13
- s32i a14, a1, UEXC_a14
- s32i a15, a1, UEXC_a15
-# if XTOS_DEBUG_PC
- // TODO: setup return PC for call traceback through interrupt dispatch
-# endif
-
- rsync // wait for WSR to PS to complete
-
-#else /* ! __XTENSA_CALL0_ABI__ */
-
-# if XTOS_CNEST
- l32i a2, a1, ESF_TOTALSIZE-20 // save nested-C-func call-chain ptr
-# endif
- addi a1, a1, ESF_TOTALSIZE // restore sp (dealloc ESF) for sane stack again
- rsync // wait for WSR to PS to complete
-
- /* HERE: we can SAFELY get window overflows.
- *
- * From here, registers a4..a15 automatically get spilled if needed.
- * They become a0..a11 after the ENTRY instruction.
- * Currently, we don't check whether or not these registers
- * get spilled, so we must save and restore any that we
- * modify. We've already saved a4 and a5
- * which we modify as part of the pseudo-CALL.
- *
- * IMPLEMENTATION NOTE:
- *
- * The pseudo-CALL below effectively saves registers a2..a3
- * so that they are available again after the corresponding
- * RETW when returning from the exception handling. We
- * could choose to put something like EPC1 or PS in
- * there, so they're available more quickly when
- * restoring. HOWEVER, exception handlers may wish to
- * change such values, or anything on the exception stack
- * frame, and expect these to be restored as modified.
- *
- * NOTA: future: figure out what's the best thing to put
- * in a2 and a3. (candidate: a4 and a5 below; but what
- * if exception handler manipulates ARs, as in a syscall
- * handler.... oh well)
- *
- *
- * Now do the pseudo-CALL.
- * Make it look as if the code that got the exception made a
- * CALL4 to the exception handling code. (We call
- * this the "pseudo-CALL".)
- *
- * This pseudo-CALL is important and done this way:
- *
- * 1. There are only three ways to safely update the stack pointer
- * in the windowed ABI, such that window exceptions work correctly:
- * (a) spill all live windows to stack then switch to a new stack
- * (or, save the entire address register file and window
- * registers, which is likely even more expensive)
- * (b) use MOVSP (or equivalent)
- * (c) use ENTRY/RETW
- * Doing (a) is excessively expensive, and doing (b) here requires
- * copying 16 bytes back and forth which is also time-consuming;
- * whereas (c) is very efficient, so that's what we do here.
- *
- * 2. Normally we cannot do a pseudo-CALL8 or CALL12 here.
- * According to the
- * windowed ABI, a function must allocate enough space
- * for the largest call that it makes. However, the
- * pseudo-CALL is executed in the context of the
- * function that happened to be executing at the time
- * the interrupt was taken, and that function might or
- * might not have allocated enough stack space for a
- * CALL8 or a CALL12. If we try doing a pseudo-CALL8
- * or -CALL12 here, we corrupt the stack if the
- * interrupted function happened to not have allocated
- * space for such a call.
- *
- * 3. We set the return PC, but it's not strictly
- * necessary for proper operation. It does make
- * debugging, ie. stack tracebacks, much nicer if it
- * can point to the interrupted code (not always
- * possible, eg. if interrupted code is in a different
- * GB than the interrupt handling code, which is
- * unlikely in a system without protection where
- * interrupt handlers and general application code are
- * typically linked together).
- *
- * IMPORTANT: Interrupts must stay disabled while doing the pseudo-CALL,
- * or at least until after the ENTRY instruction, because SP has been
- * restored to its original value that does not reflect the exception
- * stack frame's allocation. An interrupt taken here would
- * corrupt the exception stack frame (ie. allocate another over it).
- * (High priority interrupts can remain enabled, they save and restore
- * all of their state and use their own stack or save area.)
- * For the same reason, we mustn't get any exceptions in this code
- * (other than window exceptions where noted) until ENTRY is done.
- */
-
- // HERE: may get a single window overflow (caused by the following instruction).
-
-# if XTOS_DEBUG_PC
- movi a4, 0xC0000000 // [for debug] for return PC computation below
- or a3, a4, a3 // [for debug] set upper two bits of return PC
- addx2 a4, a4, a3 // [for debug] clear upper bit
-# else
- movi a4, 0 // entry cannot cause overflow, cause it here
-# endif
-
- .global _LevelOneInterrupt
-_LevelOneInterrupt: // this label makes tracebacks through interrupts look nicer
-
- _entry a1, ESF_TOTALSIZE // as if after a CALL4 (PS.CALLINC set to 1 above)
-
- /*
- * The above ENTRY instruction does a number of things:
- *
- * 1. Because we're emulating CALL4, the ENTRY rotates windows
- * forward by 4 registers (as per 'ROTW +1'), so that
- * a4-a15 became a0-a11. So now: a0-a11 are part of
- * the interrupted context to be preserved. a0-a1
- * were already saved above when they were a4-a5.
- * a12-a15 are free to use as they're NOT part of the
- * interrupted context. We don't need to save/restore
- * them, and they will get spilled if needed.
- *
- * 2. Updates SP (new a1), allocating the exception stack
- * frame in the new window, preserving the old a1 in
- * the previous window.
- *
- * 3. The underscore prefix prevents the assembler from
- * automatically aligning the ENTRY instruction on a
- * 4-byte boundary, which could create a fatal gap in
- * the instruction stream.
- *
- * At this point, ie. before we re-enable interrupts, we know the caller is
- * always live so we can safely modify a1 without using MOVSP (we can use MOVSP
- * but it will never cause an ALLOCA or underflow exception here).
- * So this is a good point to modify the stack pointer if we want eg. to
- * switch to an interrupt stack (if we do, we need to save the current SP
- * because certain things have been saved to that exception stack frame).
- * We couldn't do this easily before ENTRY, where the caller wasn't
- * necessarily live.
- */
-
-# if 0 /*... non-nested interrupt ...*/
- mov ...some address register..., a1 // save ptr to original ESF
- movi a1, _interrupt_stack // switch stack
-# endif
-
-#endif /* __XTENSA_CALL0_ABI__ */
-
- /*
- * Now we can enable interrupts of higher virtual priority than the one(s)
- * being dispatched/processed here. This may entail some software prioritization,
- * if so configured.
- * (Pseudo-CALL is complete, and SP reflects allocation of exception stack frame
- * or switch to new stack.)
- */
-
-#define CUR_INTLEVEL 0
- /* At this point, PS.INTLEVEL is 0. */
-
-
- /***************** Dispatch low-priority interrupts to service *****************/
-
- /* HERE: We may get up to 3 window overflows on the following instruction.
- *
- * The worst case is 3 overflows, two 4-register overflows and one
- * 12-register overflow.
- */
-
-
- /*
- * The INTENABLE register is virtualized, because it serves two purposes:
- * controlling which interrupts are active (eg. enabled once a handler
- * is registered) as reflected in _xtos_enabled, and what is the current
- * effective interrupt level as reflected in _xtos_vpri_enabled.
- *
- * The INTENABLE register always contains (_xtos_enabled & _xtos_vpri_enabled).
- * NOTE: It is important that INTENABLE, _xtos_enabled and _xtos_vpri_enabled
- * only be modified when interrupts at XTOS_LOCK_LEVEL and below are disabled,
- * that they never be modified by interrupts at levels above XTOS_LOCK_LEVEL,
- * and that they be consistent and never modified when the current interrupt
- * level is below XTOS_LOCK_LEVEL.
- *
- * NOTE: Reading the INTERRUPT register *must* be done at PS.INTLEVEL <= 1
- * otherwise we might incorrectly see higher priority interrupts.
- */
-
-
- xtos_addr_percore a14, xtos_intstruct // address of interrupt management globals
- rsr.interrupt a15 // interrupts pending
- rsr.intenable a12 // interrupts enabled (already should equal _xtos_enabled & _xtos_vpri_enabled)
- l32i a13, a14, XTOS_VPRI_ENABLED_OFS // read previous _xtos_vpri_enabled
- and a15, a15, a12 // a15 = INTERRUPT & (interrupts we can consider processing)
-NEEDSAR rsr.sar a12
- s32i a13, a1, UEXC_vpri // save previous vpri
-
- _beqz a15, spurious_int // no interrupt to handle (spurious interrupt)
-NEEDSAR s32i a12, a1, UEXC_sar // note: in XEA1, UEXC_sar must be set *after* beqz above
-
-IFFAIR s32i a2, a1, UEXC_exccause // save a2 (interrupted code's a6)
-IFFAIR movi a2, -1 // initial fairness mask
-
-.L1_loop0:
- // a15 = non-zero mask of interrupt bits to consider handling
-
-#if XTOS_SUBPRI_ORDER == XTOS_SPO_ZERO_HI && !XTOS_INT_FAIRNESS && !XTOS_SUBPRI_GROUPS
- // Special case that can be handled a bit more efficiently:
-
- neg a12, a15 // find lsbit in a15 ...
- and a12, a12, a15 // ...
- // a12 = single bit corresponding to interrupt to be processed (highest pri pending+enabled).
-
- // Compute a13 = new virtual priority based on this selected highest priority interrupt:
- movi a15, ~XCHAL_LOWPRI_MASK // mask of all low-priority interrupts
- addi a13, a12, -1 // mask of interrupts enabled at this new priority
- or a13, a13, a15 // also leave medium- and high-priority interrupts enabled
-
-#else /* special case */
-
- // Entry:
- // a12 = (undefined)
- // a13 = (undefined)
- // a14 = &_xtos_intstruct --or-- interrupt table adjusted base
- // a15 = non-zero mask of interrupt bits to consider handling
- // Exit:
- // a12 = index
- // a13 = (clobbered)
- // a14 = (preserved)
- // a15 = single bit corresponding to index
- //
- indexmask_int a12, a15, a14, a13
-
- // a12 = index of highest priority pending+enabled interrupt, to be processed.
- // a15 = (1 << a12), ie. bit corresponding to interrupt to be processed.
-IFFAIR xor a2, a2, a15 // update fairness mask - mask out this interrupt until recycling mask
- xtos_addr_percore_sub a13, xtos_interrupt_table, IFNSA( (32-XCHAL_NUM_INTERRUPTS)*XIE_SIZE, 0 )
- wsr.intclear a15 // clear interrupt (if software or external edge-triggered or write-error)
- addx8 a12, a12, a13 // a12 = address in interrupt table for given interrupt number
-
-.L1_loop1:
- // a12 now contains pointer to interrupt table entry for interrupt to be processed
- l32i a13, a12, XIE_VPRIMASK // a13 = new vpri (mask of interrupts enabled at this interrupt's priority)
-#endif /* !special case */
-
- // a13 = new virtual priority based on the selected highest priority interrupt
-
- rsilft a15, 0, XTOS_LOCKLEVEL // lockout
-
- // Now do the equivalent of: prev = _xtos_set_vpri( a13 );
-
- l32i a15, a14, XTOS_ENABLED_OFS // a15 = _xtos_enabled
- s32i a13, a14, XTOS_VPRI_ENABLED_OFS // update new _xtos_vpri_enabled
- and a15, a15, a13 // a15 = _xtos_enabled & _xtos_vpri_enabled
- //NOTE: Here, do: a15 &= ~_xtos_pending if XTOS_VIRTUAL_INTERRUPT is set.
- wsr.intenable a15
- //interlock
- //interlock
- rsync // NOTA - not ISA defined // wait for INTENABLE write to complete before we set PS.INTLEVEL to zero
-
-
- // Okay, we've updated INTENABLE to reflect the new virtual priority (vpri)
- // according to the highest priority pending+enabled (low-priority) interrupt.
-
- // IMPLEMENTATION NOTE - Before we unlock (enable interrupts), we could
- // switch stacks here, now that we have enough free registers through the unlock.
-
- // Now we can enable interrupts via PS.INTLEVEL. (Already done for XEA1.)
-
- rsil a15, 0 // unlock
-#undef CUR_INTLEVEL
-#define CUR_INTLEVEL 0
-
- // HERE: interrupts are enabled again (those interrupts of
- // higher virtual priority than the one we're currently processing).
-
- // HERE:
- // a12 = pointer to interrupt entry in table, or
- // mask of interrupt bit to process (special case only)
- // a13, a15 = available for use
- // a14 = available for use if virtual INTENABLE, else is pointer to interrupt table
-
-#if XTOS_SUBPRI_ORDER == XTOS_SPO_ZERO_HI && !XTOS_INT_FAIRNESS && !XTOS_SUBPRI_GROUPS
- /* In this special case, we moved as much as possible where interrupts are enabled again: */
- // a12 is bit corresponding to interrupt, convert to ptr to interrupt table entry...
- xtos_addr_percore_sub a14, xtos_interrupt_table, IFNSA( (32-XCHAL_NUM_INTERRUPTS)*XIE_SIZE, 0 )
- wsr.intclear a12 // clear interrupt (if software or external edge-triggered or write-error)
-//IFFAIR xor a2, a2, a12 // update fairness mask - mask out this interrupt until recycling mask
- msindex_int a15, a12 // a15 = index of msbit set in a12 (a12 clobbered)
- addx8 a12, a15, a14 // a12 = address in interrupt table for given interrupt number
-#endif /* special case */
-
-
- /* At this point, PS.INTLEVEL is 0. */
-
- // HERE: a12 = pointer to interrupt entry in table
-
- // (Possible enhancement: do at higher-level, to avoid doing it all the time? !?!?!?)
- save_loops_mac16 a1, a13, a15 // save LOOP & MAC16 regs, if configured
-
-LATESAR rsr.sar a15
-
- l32i a13, a12, XIE_HANDLER // a13 = address of interrupt handler
-LATESAR s32i a15, a1, UEXC_sar
-
-#ifdef __XTENSA_CALL0_ABI__
- l32i a2, a12, XIE_ARG // first arg
- mov a3, a1 // second arg, exception stack frame
- callx0 a13 // call interrupt handler
-#else
- mov a15, a1 // second arg, exception stack frame
- l32i a14, a12, XIE_ARG // first argument passed to interrupt handler (relayed by context-dispatcher, if non-nested)
- callx12 a13 // execute interrupt handler, directly or via context-dispatcher (clobbers a12-a15)
-#endif
-
- // (Possible enhancement: do at higher-level, to avoid doing it all the time? !?!?!?)
- restore_loops_mac16 a1, a13, a14, a15 // restore LOOP & MAC16 regs, if configured
-
-LATESAR l32i a12, a1, UEXC_sar
-
-
- /* Here, INTENABLE register is virtualized. */
-
- xtos_addr_percore a14, xtos_intstruct // address of interrupt management globals
-LATESAR wsr.sar a12
- movi a12, XTOS_UNLOCKABLE_MASK // mask out levels covered by XTOS_LOCKLEVEL
- // so we can run at PS.INTLEVEL=0 (for the RETW below)
- // while manipulating virtual INTENABLE
- rsr.interrupt a15
- rsil a13, XTOS_LOCKLEVEL
- l32i a13, a14, XTOS_ENABLED_OFS // a13 = _xtos_enabled
- and a12, a12, a13 // compute new INTENABLE
- wsr.intenable a12 // mask out at XTOS_LOCKLEVEL via INTENABLE
- l32i a12, a1, UEXC_vpri // read saved vpri
- //interlock
- and a13, a13, a12 // a13 = old-vpri & _xtos_enabled (INTENABLE value to restore)
- and a15, a15, a13 // what's pending among what we can handle?
-
-
- // a15 now contains the remaining pending+enabled interrupts.
- // NOTE: we MUST NOT consider interrupts potentially already being handled
- // by another interrupt handler that we pre-empted.
- // So we masked with saved vpri, ie. the set of interrupts enabled when we entered
- // this handler, ie. the set of interrupts that can pre-empt the previous context.
-NOFAIR _bnez a15, .L1_loop0 // more interrupt(s) to handle
-IFFAIR _bnez a15, preloop // more interrupt(s) to handle
-IFFAIR l32i a2, a1, UEXC_exccause // restore a2 (interrupted code's a6)
-
-
- // NOTE:
- // Register allocation is why we didn't restore *HERE* the loop regs, MAC16, SAR, etc.
- // (at least part of the reason)
- // We only have one registers (a15), however with 7-stage pipe, three registers
- // are required to avoid interlocks. We could get 2 more registers at 1 cycle each [now only one?],
- // but it isn't obvious whether paying these extra cycles are worth it...
-
- // Restore vpri as it was before we handled the interrupt(s):
- s32i a12, a14, XTOS_VPRI_ENABLED_OFS // restore _xtos_vpri_enabled
-NEEDSAR l32i a12, a1, UEXC_sar
- s32i a13, a1, UEXC_sar // save new INTENABLE value across RETW
-
-
- /***************************/
-
- // Now exit the handler.
-
- /*
- * Leave interrupts disabled while returning from the pseudo-CALL setup above,
- * for the same reason they were disabled while doing the pseudo-CALL:
- * this sequence restores SP such that it doesn't reflect the allocation
- * of the exception stack frame, which is still needed to return from
- * the exception.
- */
-
-spurious_int:
-
- movi a0, _xtos_return_from_exc
-#ifdef __XTENSA_CALL0_ABI__
-NEEDSAR wsr.sar a12
- jx a0
-#else /* ! __XTENSA_CALL0_ABI__ */
- // Now return from the pseudo-CALL from the interrupted code, to rotate
- // our windows back...
-
- movi a13, 0xC0000000
-NEEDSAR wsr.sar a12
- or a0, a0, a13 // set upper two bits
- addx2 a0, a13, a0 // clear upper bit
- retw
-#endif /* __XTENSA_CALL0_ABI__ */
-
-
-
-#if XTOS_INT_FAIRNESS
-preloop:
- // Lowering priority or recycling fairness-mask bits ...
- // a14 = &_xtos_intstruct *or* interrupt table ptr
- // a15 = non-zero mask of interrupt bits to consider handling
-
-# if !XTOS_SUBPRI
- and a13, a15, a2 // a13 = interrupt bits to consider handling, masked for fairness
- movi a12, -1 // (new fairness mask, all one's)
- moveqz a2, a12, a13 // recycle fairness mask if all bits to consider are masked by fairness, and leave a15 intact
- movnez a15, a13, a13 // otherwise set a15 = a13, ie. mask out bits for fairness (a15 is still non-zero)
- j .L1_loop0
-# else /* XTOS_SUBPRI */
- // NOTE: In this case, with SUBPRI, XTOS_VIRTUAL_INTENABLE is always set.
- // So: a14 = &_xtos_intstruct
-
- // Compute a13 = index of highest priority interrupt in a15 (a13 is reversed if NSA present)
- // (a14, a15 preserved; a12 is a temporary):
- index_int a13, a15, a14, a12
-
- // a12 = (available)
- // a13 = index
- // a14 = &_xtos_intstruct
- // a15 = mask of candidates
- xtos_addr_percore_sub a12, xtos_interrupt_table, IFNSA( (32-XCHAL_NUM_INTERRUPTS)*XIE_SIZE, 0 )
- //slot
- addx8 a12, a13, a12 // a12 = address in interrupt table for given interrupt number
- l32i a14, a12, XIE_LEVELMASK // a14 = mask of all interrupts at selected interrupt's level
- and a15, a15, a2 // mask out for fairness
- and a15, a15, a14 // only consider interrupts at highest pending level
- xtos_addr_percore a14, xtos_intstruct // needed at loop0, and below
- _bnez a15, .L1_loop0 // interrupts are allowed by current fairness mask, redo indexing with proper mask (a15, a14 = ...)
-
- // a12 = ptr to interrupt entry
- // a13 = index
- // a14 = &_xtos_intstruct
- // a15 = (available)
-
- // Compute bitmask of interrupt to be processed...
-# if XCHAL_HAVE_NSA
- movi a15, 0x80000000
- ssr a13
- srl a13, a15
-# else
- movi a15, 1
- ssl a13
- sll a13, a15
-# endif
- // a13 = single bit set corresponding to interrupt to be processed...
- l32i a15, a12, XIE_LEVELMASK // a15 = mask of all interrupts at selected interrupt's level
- wsr.intclear a13 // clear interrupt (if software or external edge-triggered or write-error)
- or a2, a2, a15 // recycle fairness mask for selected interrupt level
- xor a2, a2, a13 // update fairness mask - mask out this interrupt until recycling mask
- j .L1_loop1 // handle selected interrupt (a12 = interrupt entry, a14 = &_xtos_intstruct)
-
-# endif /* XTOS_SUBPRI */
-#endif /* XTOS_INT_FAIRNESS */
-
- /* FIXME: what about _LevelOneInterrupt ? */
- .size _xtos_l1int_handler, . - _xtos_l1int_handler
-
-#endif /* XCHAL_HAVE_XEA1 && XCHAL_HAVE_EXCEPTIONS && XCHAL_HAVE_INTERRUPTS */
-
diff --git a/src/arch/xtensa/smp/xtos/xea1/intlevel-restore.S b/src/arch/xtensa/smp/xtos/xea1/intlevel-restore.S
deleted file mode 100644
index a7b19ec..0000000
--- a/src/arch/xtensa/smp/xtos/xea1/intlevel-restore.S
+++ /dev/null
@@ -1,70 +0,0 @@
-// xea1/intlevel-restore.S - Interrupt related assembler code - _xtos_restore_intlevel
-
-// Copyright (c) 2004-2016 Tensilica Inc.
-//
-// Permission is hereby granted, free of charge, to any person obtaining
-// a copy of this software and associated documentation files (the
-// "Software"), to deal in the Software without restriction, including
-// without limitation the rights to use, copy, modify, merge, publish,
-// distribute, sublicense, and/or sell copies of the Software, and to
-// permit persons to whom the Software is furnished to do so, subject to
-// the following conditions:
-//
-// The above copyright notice and this permission notice shall be included
-// in all copies or substantial portions of the Software.
-//
-// THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
-// EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
-// MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
-// IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY
-// CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
-// TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
-// SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
-
-#include <xtensa/coreasm.h>
-#include <xtensa/config/specreg.h>
-#include "../xtos-internal.h"
-
-#if XCHAL_HAVE_XEA1
-
-/***************************************************************************
- * void _xtos_restore_intlevel(unsigned restoreval);
- *
- * _xtos_restore_intlevel() restores the current interrupt level
- * according to a value returned by _xtos_set_intlevel() or
- * _xtos_set_min_intlevel() (or one of the corresponding macros).
- *
- * NOTE: In XEA1, this function is implemented identically
- * to _xtos_set_vpri().
- */
-
-/***************************************************************************
- * _xtos_set_vpri() is used to set the current virtual priority from C code;
- * it can be called from the application or from a C interrupt handler.
- */
-
- .text
- .global _xtos_restore_intlevel
- .type _xtos_restore_intlevel,@function
- .global _xtos_set_vpri
- .type _xtos_set_vpri,@function
- .align 4
-_xtos_set_vpri:
-_xtos_restore_intlevel:
- abi_entry
-#if XCHAL_HAVE_INTERRUPTS && XTOS_VIRTUAL_INTENABLE
- mov a3, a2
- xtos_addr_percore a4, xtos_intstruct
- xtos_lock a7 // MUST USE highest address register of function to avoid window overflows in critical section
- l32i a2, a4, XTOS_VPRI_ENABLED_OFS // return old xtos_vpri_enabled (current vpri)
- l32i a5, a4, XTOS_ENABLED_OFS // a3 = xtos_enabled
- s32i a3, a4, XTOS_VPRI_ENABLED_OFS // set new xtos_vpri_enabled (current vpri)
- and a5, a5, a3 // a5 = xtos_enabled & xtos_vpri_enabled
- wsr.intenable a5
- xtos_unlock a7
-#endif /*XCHAL_HAVE_INTERRUPTS*/
- abi_return
- .size _xtos_set_vpri, . - _xtos_set_vpri
-
-#endif /* XEA1 */
-
diff --git a/src/arch/xtensa/smp/xtos/xea1/intlevel-set.S b/src/arch/xtensa/smp/xtos/xea1/intlevel-set.S
deleted file mode 100644
index 127ceb0..0000000
--- a/src/arch/xtensa/smp/xtos/xea1/intlevel-set.S
+++ /dev/null
@@ -1,71 +0,0 @@
-// xea1/intlevel-set.S - Interrupt related assembler code - _xtos_set_intlevel
-
-// Copyright (c) 2004-2016 Tensilica Inc.
-//
-// Permission is hereby granted, free of charge, to any person obtaining
-// a copy of this software and associated documentation files (the
-// "Software"), to deal in the Software without restriction, including
-// without limitation the rights to use, copy, modify, merge, publish,
-// distribute, sublicense, and/or sell copies of the Software, and to
-// permit persons to whom the Software is furnished to do so, subject to
-// the following conditions:
-//
-// The above copyright notice and this permission notice shall be included
-// in all copies or substantial portions of the Software.
-//
-// THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
-// EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
-// MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
-// IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY
-// CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
-// TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
-// SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
-
-#include <xtensa/coreasm.h>
-#include <xtensa/config/specreg.h>
-#include "../xtos-internal.h"
-
-#if XCHAL_HAVE_XEA1
-
-
-/***************************************************************************
- * unsigned _xtos_set_intlevel(int intlevel);
- *
- * _xtos_set_intlevel() is used to set the current priority from C code;
- * it can be called from the application or from a C interrupt handler.
- *
- * NOTE: This version allows the 'intlevel' parameter to be computed
- * at run-time, and thus is longer. It is much more efficient, and
- * highly recommented, to use the XTOS_SET_INTLEVEL(intlevel) macro instead
- * (which requires a constant intlevel).
- */
-
- .text
- .align 4
- .global _xtos_set_intlevel
- .type _xtos_set_intlevel,@function
-_xtos_set_intlevel:
- abi_entry
-#if XCHAL_HAVE_INTERRUPTS
- /* In XEA1, we have to rely on INTENABLE register virtualization: */
- movi a4, Xthal_intlevel_andbelow_mask
- extui a3, a2, 0, 4 // keep only INTLEVEL bits of parameter
- addx4 a5, a3, a4 // index mask to use
- l32i a3, a5, 0 // get mask of interrupts at requested intlevel and below
- movi a5, -1 // all 1's
- xtos_addr_percore a4, xtos_intstruct
- xor a3, a3, a5 // mask of interrupts at intlevels above the requested one (to enable)
- xtos_lock a7 // MUST USE highest address register of function to avoid window overflows in critical section
- l32i a2, a4, XTOS_VPRI_ENABLED_OFS // return old xtos_vpri_enabled (current vpri)
- l32i a5, a4, XTOS_ENABLED_OFS // a5 = xtos_enabled
- s32i a3, a4, XTOS_VPRI_ENABLED_OFS // set new xtos_vpri_enabled (current vpri)
- and a5, a5, a3 // a5 = xtos_enabled & xtos_vpri_enabled
- wsr.intenable a5
- xtos_unlock a7
-#endif /*XCHAL_HAVE_INTERRUPTS*/
- abi_return
-
- .size _xtos_set_intlevel, . - _xtos_set_intlevel
-
-#endif /* XEA1 */
-
diff --git a/src/arch/xtensa/smp/xtos/xea1/intlevel-setmin.S b/src/arch/xtensa/smp/xtos/xea1/intlevel-setmin.S
deleted file mode 100644
index 6484913..0000000
--- a/src/arch/xtensa/smp/xtos/xea1/intlevel-setmin.S
+++ /dev/null
@@ -1,74 +0,0 @@
-// xea1/intlevel-setmin.S - Interrupt related assembler code - _xtos_set_min_intlevel
-
-// Copyright (c) 2004-2016 Tensilica Inc.
-//
-// Permission is hereby granted, free of charge, to any person obtaining
-// a copy of this software and associated documentation files (the
-// "Software"), to deal in the Software without restriction, including
-// without limitation the rights to use, copy, modify, merge, publish,
-// distribute, sublicense, and/or sell copies of the Software, and to
-// permit persons to whom the Software is furnished to do so, subject to
-// the following conditions:
-//
-// The above copyright notice and this permission notice shall be included
-// in all copies or substantial portions of the Software.
-//
-// THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
-// EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
-// MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
-// IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY
-// CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
-// TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
-// SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
-
-#include <xtensa/coreasm.h>
-#include <xtensa/config/specreg.h>
-#include "../xtos-internal.h"
-
-#if XCHAL_HAVE_XEA1
-
-
-/***************************************************************************
- * unsigned _xtos_set_min_intlevel(int intlevel);
- *
- * _xtos_set_min_intlevel() is identical to _xtos_set_intlevel() except
- * that it will not lower the current interrupt level. Instead,
- * it ensures that the current interrupt level is at least as high
- * as specified.
- *
- * NOTE: This version allows the 'intlevel' parameter to be computed
- * at run-time, and thus is longer. It is much more efficient, and
- * highly recommented, to use the XTOS_SET_MIN_INTLEVEL(intlevel) macro instead
- * (which requires a constant intlevel).
- */
-
- .text
- .align 4
- .global _xtos_set_min_intlevel
- .type _xtos_set_min_intlevel,@function
-_xtos_set_min_intlevel:
- abi_entry
-#if XCHAL_HAVE_INTERRUPTS
- /* In XEA1, we have to rely on INTENABLE register virtualization: */
- movi a4, Xthal_intlevel_andbelow_mask
- extui a3, a2, 0, 4 // keep only INTLEVEL bits of parameter
- addx4 a5, a3, a4 // index mask to use
- l32i a3, a5, 0 // get mask of interrupts at requested intlevel and below
- movi a5, -1 // all 1's
- xtos_addr_percore a4, xtos_intstruct
- xor a3, a3, a5 // mask of interrupts at intlevels above the requested one (to enable)
- xtos_lock a7 // MUST USE highest address register of function to avoid window overflows in critical section
- l32i a2, a4, XTOS_VPRI_ENABLED_OFS // return old xtos_vpri_enabled (current vpri)
- l32i a5, a4, XTOS_ENABLED_OFS // a5 = xtos_enabled
- and a3, a3, a2 // make sure we don't enable any new interrupts
- s32i a3, a4, XTOS_VPRI_ENABLED_OFS // set new xtos_vpri_enabled (current vpri)
- and a5, a5, a3 // a5 = xtos_enabled & xtos_vpri_enabled
- wsr.intenable a5
- xtos_unlock a7
-#endif /*XCHAL_HAVE_INTERRUPTS*/
- abi_return
-
- .size _xtos_set_min_intlevel, . - _xtos_set_min_intlevel
-
-#endif /* XEA1 */
-
diff --git a/src/arch/xtensa/smp/xtos/xea1/window-vectors.S b/src/arch/xtensa/smp/xtos/xea1/window-vectors.S
deleted file mode 100644
index 1670ed9..0000000
--- a/src/arch/xtensa/smp/xtos/xea1/window-vectors.S
+++ /dev/null
@@ -1,355 +0,0 @@
-// window-vectors-xea1.S - Register Window Overflow/Underflow Handlers for XEA1
-// $Id: //depot/rel/Foxhill/dot.8/Xtensa/OS/xtos/xea1/window-vectors.S#1 $
-
-// Copyright (c) 1999-2013 Tensilica Inc.
-//
-// Permission is hereby granted, free of charge, to any person obtaining
-// a copy of this software and associated documentation files (the
-// "Software"), to deal in the Software without restriction, including
-// without limitation the rights to use, copy, modify, merge, publish,
-// distribute, sublicense, and/or sell copies of the Software, and to
-// permit persons to whom the Software is furnished to do so, subject to
-// the following conditions:
-//
-// The above copyright notice and this permission notice shall be included
-// in all copies or substantial portions of the Software.
-//
-// THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
-// EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
-// MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
-// IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY
-// CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
-// TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
-// SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
-
-#include <xtensa/coreasm.h>
-#include <xtensa/xtruntime-frames.h>
-
-#if XCHAL_HAVE_XEA1
-#if XCHAL_HAVE_WINDOWED && !defined(__XTENSA_CALL0_ABI__)
-
-# ifndef NO_SECTION_DIRECTIVES
-// Exports
-.global _WindowOverflow4
-.global _WindowUnderflow4
-.global _WindowOverflow8
-.global _WindowUnderflow8
-.global _WindowOverflow12
-.global _WindowUnderflow12
-.global _xtos_alloca_handler
-
- // Note: the current window exception vectors do not generate any
- // literals. Hence the literal_prefix directive is not necessary.
- // Specifying it "just in case" creates an empty section (named
- // ".WindowVectors.literal") which can in some cases cause linking
- // problems (the linker scripts don't place it anywhere).
- // So leave it commented out:
- //
- //.begin literal_prefix .WindowVectors
-
- .section .WindowVectors.text, "ax"
-# endif
-
-
-//
-// GENERAL NOTES:
-//
-// These window exception handlers need not be modified.
-// They are specific to the windowed call ABI only.
-//
-// Underflow Handlers:
-//
-// The underflow handler for returning from call[i+1] to call[i]
-// must preserve all the registers from call[i+1]'s window.
-// In particular, a0 and a1 must be preserved because the RETW instruction
-// will be reexecuted (and may even underflow again if an intervening
-// exception has flushed call[i]'s registers).
-// Registers a2 and up may contain return values.
-//
-// The caller could also potentially assume that the callee's a0 and a1
-// (its own a4&a5 if call4, a8&a9 if call8, a12&a13 if call12)
-// are correct for whatever reason (not a clean thing to do in general,
-// but if it's possible, unless the ABI explicitly prohibits it,
-// it will eventually be done :) -- whether the the ABI needs to
-// prohibit this is a different question).
-//
-// Timing of Handlers:
-//
-// Here is an overview of the overhead of taking a window exception,
-// ie. the number of additional cycles taken relative to case where
-// an exception is not taken.
-// NOTE: these numbers do not take into account any cache misses,
-// write buffer stalls, or other external stalls, if they occur.
-// The totals consist of 5 cycles to enter the handler (or 6 or 7
-// for optional longer pipelines in Xtensa LX), the number of instructions
-// and interlocks (2nd and 3rd columns below), and 2 cycles jump delay
-// on return (3 cycles for optional longer I-side pipeline in Xtensa LX):
-//
-// Instruction+bubbles Totals (5-stage)
-// XEA1 XEA2 XEA1 XEA2
-// Overflow-4 7 5 14 12
-// Overflow-8 14 10 21 17
-// Overflow-12 18 14 25 21
-// Underflow-4 6 5 13 12
-// Underflow-8 14 10 21 17
-// Underflow-12 18 14 25 21
-//
-// Underflow-8 15 12 25 22 (7-stage; could be made 1 less)
-// Underflow-12 19 16 29 26 (7-stage; could be made 1 less)
-
-#ifndef WINDOW_BASE_VECOFS
-#define WINDOW_BASE_VECOFS XCHAL_WINDOW_OF4_VECOFS
-#endif
-
-
-// 4-Register Window Overflow Vector (Handler)
-//
-// Invoked if a call[i] referenced a register (a4-a15)
-// that contains data from ancestor call[j];
-// call[j] had done a call4 to call[j+1].
-// On entry here:
-// window rotated to call[j] start point;
-// a0-a3 are registers to be saved;
-// a4-a15 must be preserved;
-// a5 is call[j+1]'s stack pointer.
-
- .org XCHAL_WINDOW_OF4_VECOFS - WINDOW_BASE_VECOFS
-_WindowOverflow4:
- addi a5, a5, -16 // to make store offsets positive
- s32i a0, a5, 0 // save a0 to call[j+1]'s stack frame
- s32i a1, a5, 4 // save a1 to call[j+1]'s stack frame
- s32i a2, a5, 8 // save a2 to call[j+1]'s stack frame
- s32i a3, a5, 12 // save a3 to call[j+1]'s stack frame
- addi a5, a5, 16 // restore a5
- rfwo // rotates back to call[i] position
-
- .size _WindowOverflow4, . - _WindowOverflow4
-
-
-// ALLOCA exception handler
-//
-// NOTE: The alloca exception handler is squeezed in between the window exception
-// handlers in order to save space, and also to allow short-range jumps to the
-// window underflow handlers (see below for why). Because of the limited space in
-// between the window handlers, this function is split into two to fit.
-//
-// Code written to the windowed ABI must use the MOVSP instruction to modify
-// the stack pointer (except for startup code, which doesn't have a caller).
-// The compiler uses MOVSP to allocate very large or variable size stack frames.
-// MOVSP guarantees that the caller frame's a0-a3 registers, stored below the
-// stack pointer, are moved atomically with respect to interrupts and exceptions
-// to satisfy windowed ABI requirements. When user code executes the MOVSP
-// instruction and the caller frame is on the stack rather than in the register
-// file, the processor takes an ALLOCA exception.
-//
-// The XTOS user exception dispatcher allocates an exception frame on the
-// stack and saves a2-a4 into that frame before calling us. So we need to
-// restore those registers and deallocate the stack frame before jumping
-// to the window underflow handler - which will restore the spilled registers
-// back into the register file.
-// The fact the alloca exception was taken means the registers associated with
-// the base-save area have been spilled and will be restored by the underflow
-// handler, so those 4 registers are available for scratch.
-
- .align 4
-
-_xtos_alloca_handler:
-
- l32i a2, a1, UEXC_a2 // restore a2-a4 and deallocate frame
- l32i a3, a1, UEXC_a3
- l32i a4, a1, UEXC_a4
- addi a1, a1, ESF_TOTALSIZE
- wsr.excsave1 a0 // save a0
- rsr.windowbase a0 // grab WINDOWBASE before rotw changes it
- rotw -1 // WINDOWBASE goes to a4, new a0-a3 are scratch
- rsr.ps a2
- extui a3, a2, XCHAL_PS_OWB_SHIFT, XCHAL_PS_OWB_BITS
- xor a3, a3, a4 // bits changed from old to current windowbase
- j _xtos_alloca_2 // not enough room here...
-
- .size _xtos_alloca_handler, . - _xtos_alloca_handler
-
-
-// 4-Register Window Underflow Vector (Handler)
-//
-// Invoked by RETW returning from call[i+1] to call[i]
-// where call[i]'s registers must be reloaded (not live in ARs);
-// call[i] had done a call4 to call[i+1].
-// On entry here:
-// window rotated to call[i] start point;
-// a0-a3 are undefined, must be reloaded with call[i].reg[0..3];
-// a4-a15 must be preserved (they are call[i+1].reg[0..11]);
-// a5 is call[i+1]'s stack pointer.
-
- .org XCHAL_WINDOW_UF4_VECOFS - WINDOW_BASE_VECOFS
-_WindowUnderflow4:
- addi a3, a5, -16 // to make load offsets positive
- l32i a0, a3, 0 // restore a0 from call[i+1]'s stack frame
- l32i a1, a3, 4 // restore a1 from call[i+1]'s stack frame
- l32i a2, a3, 8 // restore a2 from call[i+1]'s stack frame
- l32i a3, a3, 12 // restore a3 from call[i+1]'s stack frame
- rfwu
-
- .size _WindowUnderflow4, . - _WindowUnderflow4
-
-
-// This is the second part of the alloca handler.
-
- .align 4
-
-_xtos_alloca_2:
-
- rsr.excsave1 a4 // restore original a0 (now in a4)
- slli a3, a3, XCHAL_PS_OWB_SHIFT
- xor a2, a2, a3 // flip changed bits in old window base
- wsr.ps a2 // update PS.OWB to new window base
- rsync
- _bbci.l a4, 31, _WindowUnderflow4
- rotw -1 // original a0 goes to a8
- _bbci.l a8, 30, _WindowUnderflow8
- rotw -1
- j _WindowUnderflow12
-
- .size _xtos_alloca_2, . - _xtos_alloca_2
-
-// 8-Register Window Overflow Vector (Handler)
-//
-// Invoked if a call[i] referenced a register (a4-a15)
-// that contains data from ancestor call[j];
-// call[j] had done a call8 to call[j+1].
-// On entry here:
-// window rotated to call[j] start point;
-// a0-a7 are registers to be saved;
-// a8-a15 must be preserved;
-// a9 is call[j+1]'s stack pointer.
-
- .org XCHAL_WINDOW_OF8_VECOFS - WINDOW_BASE_VECOFS
-_WindowOverflow8:
- addi a9, a9, -16 // to make store offsets positive
- s32i a0, a9, 0 // save a0 to call[j+1]'s stack frame
- addi a0, a1, -16 // a0 <- call[j-1]'s sp
- s32i a1, a9, 4 // save a1 to call[j+1]'s stack frame
- l32i a0, a0, 4 // (used to find end of call[j]'s frame)
- s32i a2, a9, 8 // save a2 to call[j+1]'s stack frame
- s32i a3, a9, 12 // save a3 to call[j+1]'s stack frame
- addi a9, a9, 16 // restore a9
- addi a0, a0, -32 // to make load offsets positive
- s32i a4, a0, 0 // save a4 to call[j]'s stack frame
- s32i a5, a0, 4 // save a5 to call[j]'s stack frame
- s32i a6, a0, 8 // save a6 to call[j]'s stack frame
- s32i a7, a0, 12 // save a7 to call[j]'s stack frame
- rfwo // rotates back to call[i] position
-
- .size _WindowOverflow8, . - _WindowOverflow8
-
-
-// 8-Register Window Underflow Vector (Handler)
-//
-// Invoked by RETW returning from call[i+1] to call[i]
-// where call[i]'s registers must be reloaded (not live in ARs);
-// call[i] had done a call8 to call[i+1].
-// On entry here:
-// window rotated to call[i] start point;
-// a0-a7 are undefined, must be reloaded with call[i].reg[0..7];
-// a8-a15 must be preserved (they are call[i+1].reg[0..7]);
-// a9 is call[i+1]'s stack pointer.
-
- .org XCHAL_WINDOW_UF8_VECOFS - WINDOW_BASE_VECOFS
-_WindowUnderflow8:
- addi a9, a9, -16 // to make load offsets positive
- l32i a0, a9, 0 // restore a0 from call[i+1]'s stack frame
- l32i a1, a9, 4 // restore a1 from call[i+1]'s stack frame
- l32i a2, a9, 8 // restore a2 from call[i+1]'s stack frame
- addi a7, a1, -16 // a7 <- call[i-1]'s sp
- l32i a7, a7, 4 // (used to find end of call[i]'s frame)
- l32i a3, a9, 12 // restore a3 from call[i+1]'s stack frame
- addi a9, a9, 16 // restore a9
- addi a7, a7, -32 // to make load offsets positive
- l32i a4, a7, 0 // restore a4 from call[i]'s stack frame
- l32i a5, a7, 4 // restore a5 from call[i]'s stack frame
- l32i a6, a7, 8 // restore a6 from call[i]'s stack frame
- l32i a7, a7, 12 // restore a7 from call[i]'s stack frame
- rfwu
-
- .size _WindowUnderflow8, . - _WindowUnderflow8
-
-
-// 12-Register Window Overflow Vector (Handler)
-//
-// Invoked if a call[i] referenced a register (a4-a15)
-// that contains data from ancestor call[j];
-// call[j] had done a call12 to call[j+1].
-// On entry here:
-// window rotated to call[j] start point;
-// a0-a11 are registers to be saved;
-// a12-a15 must be preserved;
-// a13 is call[j+1]'s stack pointer.
-
- .org XCHAL_WINDOW_OF12_VECOFS - WINDOW_BASE_VECOFS
-_WindowOverflow12:
- addi a13, a13, -16 // to make store offsets positive
- s32i a0, a13, 0 // save a0 to call[j+1]'s stack frame
- addi a0, a1, -16 // a0 <- call[j-1]'s sp
- s32i a1, a13, 4 // save a1 to call[j+1]'s stack frame
- l32i a0, a0, 4 // (used to find end of call[j]'s frame)
- s32i a2, a13, 8 // save a2 to call[j+1]'s stack frame
- s32i a3, a13, 12 // save a3 to call[j+1]'s stack frame
- addi a13, a13, 16 // restore a13
- addi a0, a0, -48 // to make load offsets positive
- s32i a4, a0, 0 // save a4 to end of call[j]'s stack frame
- s32i a5, a0, 4 // save a5 to end of call[j]'s stack frame
- s32i a6, a0, 8 // save a6 to end of call[j]'s stack frame
- s32i a7, a0, 12 // save a7 to end of call[j]'s stack frame
- s32i a8, a0, 16 // save a8 to end of call[j]'s stack frame
- s32i a9, a0, 20 // save a9 to end of call[j]'s stack frame
- s32i a10, a0, 24 // save a10 to end of call[j]'s stack frame
- s32i a11, a0, 28 // save a11 to end of call[j]'s stack frame
- rfwo // rotates back to call[i] position
-
- .size _WindowOverflow12, . - _WindowOverflow12
-
-
-// 12-Register Window Underflow Vector (Handler)
-//
-// Invoked by RETW returning from call[i+1] to call[i]
-// where call[i]'s registers must be reloaded (not live in ARs);
-// call[i] had done a call12 to call[i+1].
-// On entry here:
-// window rotated to call[i] start point;
-// a0-a11 are undefined, must be reloaded with call[i].reg[0..11];
-// a12-a15 must be preserved (they are call[i+1].reg[0..3]);
-// a13 is call[i+1]'s stack pointer.
-
- .org XCHAL_WINDOW_UF12_VECOFS - WINDOW_BASE_VECOFS
-_WindowUnderflow12:
- addi a13, a13, -16 // to make load offsets positive
- l32i a0, a13, 0 // restore a0 from call[i+1]'s stack frame
- l32i a1, a13, 4 // restore a1 from call[i+1]'s stack frame
- l32i a2, a13, 8 // restore a2 from call[i+1]'s stack frame
- addi a11, a1, -16 // a11 <- call[i-1]'s sp
- l32i a11, a11, 4 // (used to find end of call[i]'s frame)
- l32i a3, a13, 12 // restore a3 from call[i+1]'s stack frame
- addi a13, a13, 16 // restore a13
- addi a11, a11, -48 // to make load offsets positive
- l32i a4, a11, 0 // restore a4 from end of call[i]'s stack frame
- l32i a5, a11, 4 // restore a5 from end of call[i]'s stack frame
- l32i a6, a11, 8 // restore a6 from end of call[i]'s stack frame
- l32i a7, a11, 12 // restore a7 from end of call[i]'s stack frame
- l32i a8, a11, 16 // restore a8 from end of call[i]'s stack frame
- l32i a9, a11, 20 // restore a9 from end of call[i]'s stack frame
- l32i a10, a11, 24 // restore a10 from end of call[i]'s stack frame
- l32i a11, a11, 28 // restore a11 from end of call[i]'s stack frame
- rfwu
-
- .size _WindowUnderflow12, . - _WindowUnderflow12
-
-
-# ifndef NO_SECTION_DIRECTIVES
- //.end literal_prefix
- .text
-# endif
-
-
-#endif /* XCHAL_HAVE_WINDOWED && !defined(__XTENSA_CALL0_ABI__) */
-#endif /* XCHAL_HAVE_XEA1 */
-
diff --git a/src/arch/xtensa/smp/xtos/xea2/exc-c-wrapper-handler.S b/src/arch/xtensa/smp/xtos/xea2/exc-c-wrapper-handler.S
deleted file mode 100644
index 08beb65..0000000
--- a/src/arch/xtensa/smp/xtos/xea2/exc-c-wrapper-handler.S
+++ /dev/null
@@ -1,361 +0,0 @@
-// exc-c-wrapper-handler.S - General Exception Handler that Dispatches C Handlers
-
-// Copyright (c) 2002-2017 Cadence Design Systems, Inc.
-//
-// Permission is hereby granted, free of charge, to any person obtaining
-// a copy of this software and associated documentation files (the
-// "Software"), to deal in the Software without restriction, including
-// without limitation the rights to use, copy, modify, merge, publish,
-// distribute, sublicense, and/or sell copies of the Software, and to
-// permit persons to whom the Software is furnished to do so, subject to
-// the following conditions:
-//
-// The above copyright notice and this permission notice shall be included
-// in all copies or substantial portions of the Software.
-//
-// THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
-// EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
-// MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
-// IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY
-// CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
-// TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
-// SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
-
-#include <xtensa/coreasm.h>
-#include <xtensa/corebits.h>
-#include "../xtos-internal.h"
-
-#if XCHAL_HAVE_XEA2 && XCHAL_HAVE_EXCEPTIONS
-
-
-/*
- * This assembly-level handler causes the associated exception (usually causes 12-15)
- * to be handled as if it were exception cause 3 (load/store error exception).
- * This provides forward-compatibility with a possible future split of the
- * load/store error cause into multiple more specific causes.
- */
- .align 4
- .global xtos_cause3_handler
-xtos_cause3_handler:
- movi a2, EXCCAUSE_LOAD_STORE_ERROR
- j xtos_c_wrapper_handler
- .size xtos_cause3_handler, . - xtos_cause3_handler
-
-
- .align 4
-.Lhi: addi a2, a2, -XCHAL_EXCM_LEVEL
- add a2, a2, a3
- j .Lps
-
-
-/*
- * This is the general exception assembly-level handler that dispatches C handlers.
- */
- .align 4
- .global xtos_c_wrapper_handler
-xtos_c_wrapper_handler:
-#ifdef __XTENSA_CALL0_ABI__
- // Redundantly de-allocate and re-allocate stack, so that GDB prologue
- // analysis picks up the allocate part, and figures out how to traceback
- // through the call stack through the exception.
- addi a1, a1, ESF_TOTALSIZE // de-allocate stack frame (FIXME is it safe)
-.global xtos_c_wrapper_dispatch
-xtos_c_wrapper_dispatch:
- // GDB starts analyzing prologue after most recent global symbol, so here:
- addi a1, a1, -ESF_TOTALSIZE // re-allocate stack frame
-#endif
-
- // HERE: a2, a3, a4 have been saved to exception stack frame allocated with a1 (sp).
- // a2 contains EXCCAUSE.
- s32i a5, a1, UEXC_a5 // a5 will get clobbered by ENTRY after the pseudo-CALL4
- // (a4..a15 spilled as needed; save if modified)
-
- //NOTA: Possible future improvement:
- // keep interrupts disabled until we get into the handler, such that
- // we don't have to save other critical state such as EXCVADDR here.
- //rsr.excvaddr a3
- s32i a2, a1, UEXC_exccause
- //s32i a3, a1, UEXC_excvaddr
-
- // Set PS fields:
- // EXCM = 0
- // WOE = __XTENSA_CALL0_ABI__ ? 0 : 1
- // UM = 1
- // INTLEVEL = MIN(INTLEVEL,EXCM_LEVEL)
- // CALLINC = __XTENSA_CALL0_ABI__ ? 0 : 1
- // OWB = 0 (really, a dont care if !__XTENSA_CALL0_ABI__)
-
- rsr.ps a3
- movi a2, PS_WOECALL4_ABI|PS_UM|PS_INTLEVEL(XCHAL_EXCM_LEVEL) // CALL4 emulation
- s32i a3, a1, UEXC_ps
- extui a3, a3, 0, 4 // extract PS.INTLEVEL
- bgeui a3, XCHAL_EXCM_LEVEL+1, .Lhi // at PS.INTLEVEL > EXCM_LEVEL ?
-.Lps: rsr.epc1 a3
- wsr.ps a2
-
- // HERE: window overflows enabled, but NOT SAFE because we're not quite
- // in a valid windowed context (haven't restored a1 yet...);
- // so don't cause any (keep to a0..a3) until we've saved critical state and restored a1:
-
- // NOTE: MUST SAVE EPC1 before causing any overflows, because overflows corrupt EPC1.
- s32i a3, a1, UEXC_pc
-
-#ifdef __XTENSA_CALL0_ABI__
-
- s32i a0, a1, UEXC_a0 // save the rest of the registers
- s32i a6, a1, UEXC_a6
- s32i a7, a1, UEXC_a7
- s32i a8, a1, UEXC_a8
- s32i a9, a1, UEXC_a9
- s32i a10, a1, UEXC_a10
- s32i a11, a1, UEXC_a11
- s32i a12, a1, UEXC_a12
- s32i a13, a1, UEXC_a13
- s32i a14, a1, UEXC_a14
- s32i a15, a1, UEXC_a15
-# if XTOS_DEBUG_PC
- // TODO: setup return PC for call traceback through interrupt dispatch
-# endif
-
- rsync // wait for WSR to PS to complete
-
-#else /* ! __XTENSA_CALL0_ABI__ */
-
-# if XTOS_CNEST
- l32i a2, a1, ESF_TOTALSIZE-20 // save nested-C-func call-chain ptr
-# endif
- addi a1, a1, ESF_TOTALSIZE // restore sp (dealloc ESF) for sane stack again
- rsync // wait for WSR to PS to complete
-
- /* HERE: we can SAFELY get window overflows.
- *
- * From here, registers a4..a15 automatically get spilled if needed.
- * They become a0..a11 after the ENTRY instruction.
- * Currently, we don't check whether or not these registers
- * get spilled, so we must save and restore any that we
- * modify. We've already saved a4 and a5
- * which we modify as part of the pseudo-CALL.
- *
- * IMPLEMENTATION NOTE:
- *
- * The pseudo-CALL below effectively saves registers a2..a3 so
- * that they are available again after the corresponding
- * RETW when returning from the exception handling. We
- * could choose to put something like EPC1 or PS in
- * there, so they're available more quickly when
- * restoring. HOWEVER, exception handlers may wish to
- * change such values, or anything on the exception stack
- * frame, and expect these to be restored as modified.
- *
- * NOTA: future: figure out what's the best thing to put
- * in a2 and a3. (candidate: a4 and a5 below; but what
- * if exception handler manipulates ARs, as in a syscall
- * handler.... oh well)
- *
- *
- * Now do the pseudo-CALL.
- * Make it look as if the code that got the exception made a
- * CALL4 to the exception handling code. (We call
- * this the "pseudo-CALL".)
- *
- * This pseudo-CALL is important and done this way:
- *
- * 1. There are only three ways to safely update the stack pointer
- * in the windowed ABI, such that window exceptions work correctly:
- * (a) spill all live windows to stack then switch to a new stack
- * (or, save the entire address register file and window
- * registers, which is likely even more expensive)
- * (b) use MOVSP (or equivalent)
- * (c) use ENTRY/RETW
- * Doing (a) is excessively expensive, and doing (b) here requires
- * copying 16 bytes back and forth which is also time-consuming;
- * whereas (c) is very efficient, so that's what we do here.
- *
- * 2. Normally we cannot do a pseudo-CALL8 or CALL12 here.
- * According to the
- * windowed ABI, a function must allocate enough space
- * for the largest call that it makes. However, the
- * pseudo-CALL is executed in the context of the
- * function that happened to be executing at the time
- * the interrupt was taken, and that function might or
- * might not have allocated enough stack space for a
- * CALL8 or a CALL12. If we try doing a pseudo-CALL8
- * or -CALL12 here, we corrupt the stack if the
- * interrupted function happened to not have allocated
- * space for such a call.
- *
- * 3. We set the return PC, but it's not strictly
- * necessary for proper operation. It does make
- * debugging, ie. stack tracebacks, much nicer if it
- * can point to the interrupted code (not always
- * possible, eg. if interrupted code is in a different
- * GB than the interrupt handling code, which is
- * unlikely in a system without protection where
- * interrupt handlers and general application code are
- * typically linked together).
- *
- * IMPORTANT: Interrupts must stay disabled while doing the pseudo-CALL,
- * or at least until after the ENTRY instruction, because SP has been
- * restored to its original value that does not reflect the exception
- * stack frame's allocation. An interrupt taken here would
- * corrupt the exception stack frame (ie. allocate another over it).
- * (High priority interrupts can remain enabled, they save and restore
- * all of their state and use their own stack or save area.)
- * For the same reason, we mustn't get any exceptions in this code
- * (other than window exceptions where noted) until ENTRY is done.
- */
-
- // HERE: may get a single window overflow (caused by the following instruction).
-
-# if XTOS_DEBUG_PC
- movi a4, 0xC0000000 // [for debug] for return PC computation below
- or a3, a4, a3 // [for debug] set upper two bits of return PC
- addx2 a4, a4, a3 // [for debug] clear upper bit
-# else
- movi a4, 0 // entry cannot cause overflow, cause it here
-# endif
-
- _entry a1, ESF_TOTALSIZE // as if after a CALL4 (PS.CALLINC set to 1 above)
-
- /*
- * The above ENTRY instruction does a number of things:
- *
- * 1. Because we're emulating CALL4, the ENTRY rotates windows
- * forward by 4 registers (as per 'ROTW +1'), so that
- * a4-a15 became a0-a11. So now: a0-a11 are part of
- * the interrupted context to be preserved. a0-a1
- * were already saved above when they were a4-a5.
- * a12-a15 are free to use as they're NOT part of the
- * interrupted context. We don't need to save/restore
- * them, and they will get spilled if needed.
- *
- * 2. Updates SP (new a1), allocating the exception stack
- * frame in the new window, preserving the old a1 in
- * the previous window.
- *
- * 3. The underscore prefix prevents the assembler from
- * automatically aligning the ENTRY instruction on a
- * 4-byte boundary, which could create a fatal gap in
- * the instruction stream.
- *
- * At this point, ie. before we re-enable interrupts, we know the caller is
- * always live so we can safely modify a1 without using MOVSP (we can use MOVSP
- * but it will never cause an ALLOCA or underflow exception here).
- * So this is a good point to modify the stack pointer if we want eg. to
- * switch to an interrupt stack (if we do, we need to save the current SP
- * because certain things have been saved to that exception stack frame).
- * We couldn't do this easily before ENTRY, where the caller wasn't
- * necessarily live.
- *
- * NOTE: We don't switch to an interrupt stack here, because exceptions
- * are generally caused by executing code -- so we handle exceptions in
- * the context of the thread that cause them, and thus remain on the same
- * stack. This means a thread's stack must be large enough to handle
- * the maximum level of nesting of exceptions that the thread can cause.
- */
-
- // NOTA: exception handlers for certain causes may need interrupts to be kept
- // disabled through their dispatch, so they can turn them off themselves at
- // the right point (if at all), eg. to save critical state unknown to this
- // code here, or for some recovery action that must be atomic with respect
- // to interrupts....
- //
- // Perhaps two versions of this assembly-level handler are needed, one that restores
- // interrupts to what they were before the exception was taken (as here)
- // and one that ensures at least low-priority interrupts are kept disabled?
- // NOTA: For now, always enable interrupts here.
-
- /*
- * Now we can enable interrupts.
- * (Pseudo-CALL is complete, and SP reflects allocation of exception stack frame.)
- */
-
-#endif /* __XTENSA_CALL0_ABI__ */
-
-
-#if XCHAL_HAVE_INTERRUPTS
- rsr.sar a12
- // Restore PS.INTLEVEL to its saved value (re-enables interrupts
- // if they were enabled before taking the exception):
- l32i a13, a1, UEXC_ps
- rsr.ps a14
- extui a13, a13, 0, 4 // extract saved PS.INTLEVEL
- extui a15, a14, 0, 4 // extract current PS.INTLEVEL
- xor a14, a14, a15 // clear a14.INTLEVEL
- xor a14, a14, a13 // replace with saved PS.INTLEVEL
- wsr.ps a14 // restore PS.INTLEVEL
-#else
- rsr.sar a12
-#endif
-
- movi a13, xtos_c_handler_table // &table
- l32i a15, a1, UEXC_exccause // arg2: exccause
-
- s32i a12, a1, UEXC_sar
- save_loops_mac16 a1, a12, a14 // save LOOP & MAC16 regs, if configured
-
- addx4 a12, a15, a13 // a12 = table[exccause]
- l32i a12, a12, 0 // ...
- .global _GeneralException
-_GeneralException: // this label makes tracebacks through exceptions look nicer
-
-#ifdef __XTENSA_CALL0_ABI__
- .global _GeneralExceptionFrameSize
- .set _GeneralExceptionFrameSize, ESF_TOTALSIZE
- .global _GeneralExceptionRegisterSaveOffset
- .set _GeneralExceptionRegisterSaveOffset, UEXC_a0
- mov a2, a1 // arg1: exception parameters
- mov a3, a15 // arg2: exccause
- beqz a12, 1f // null handler => skip call
- callx0 a12 // call C exception handler for this exception
-#else
- mov a14, a1 // arg1: exception parameters
- // mov a15, a15 // arg2: exccause, already in a15
- beqz a12, 1f // null handler => skip call
- callx12 a12 // call C exception handler for this exception
-#endif
- .size _GeneralException, . - _GeneralException
-1:
- // Now exit the handler.
-
-
- // Restore special registers
-
- restore_loops_mac16 a1, a13, a14, a15 // restore LOOP & MAC16 regs, if configured
- l32i a14, a1, UEXC_sar
-
- /*
- * Disable interrupts while returning from the pseudo-CALL setup above,
- * for the same reason they were disabled while doing the pseudo-CALL:
- * this sequence restores SP such that it doesn't reflect the allocation
- * of the exception stack frame, which we still need to return from
- * the exception.
- */
-
-#if XCHAL_HAVE_INTERRUPTS
- rsil a12, XCHAL_EXCM_LEVEL
-#endif
- wsr.sar a14
-
- movi a0, _xtos_return_from_exc
-#ifdef __XTENSA_CALL0_ABI__
- jx a0
-#else /* ! __XTENSA_CALL0_ABI__ */
- /* Now return from the pseudo-CALL from the interrupted code, to rotate
- * our windows back... */
-
- movi a13, 0xC0000000
- //movi a13, 3
- //slli a13, a13, 30
- or a0, a0, a13 // set upper two bits
- addx2 a0, a13, a0 // clear upper bit
- retw
-#endif /* ! __XTENSA_CALL0_ABI__ */
-
- /* FIXME: what about _GeneralException ? */
-
- .size xtos_c_wrapper_handler, . - xtos_c_wrapper_handler
-
-
-#endif /* XCHAL_HAVE_XEA2 && XCHAL_HAVE_EXCEPTIONS */
-
diff --git a/src/arch/xtensa/smp/xtos/xea2/exc-return.S b/src/arch/xtensa/smp/xtos/xea2/exc-return.S
deleted file mode 100644
index 083d782..0000000
--- a/src/arch/xtensa/smp/xtos/xea2/exc-return.S
+++ /dev/null
@@ -1,114 +0,0 @@
-// exc-return.S - Shared exception/interrupt return code
-
-// Copyright (c) 2002-2015 Tensilica Inc.
-//
-// Permission is hereby granted, free of charge, to any person obtaining
-// a copy of this software and associated documentation files (the
-// "Software"), to deal in the Software without restriction, including
-// without limitation the rights to use, copy, modify, merge, publish,
-// distribute, sublicense, and/or sell copies of the Software, and to
-// permit persons to whom the Software is furnished to do so, subject to
-// the following conditions:
-//
-// The above copyright notice and this permission notice shall be included
-// in all copies or substantial portions of the Software.
-//
-// THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
-// EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
-// MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
-// IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY
-// CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
-// TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
-// SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
-
-#include <xtensa/coreasm.h>
-#include <xtensa/corebits.h>
-#include "../xtos-internal.h"
-
-#if XCHAL_HAVE_XEA2 && XCHAL_HAVE_EXCEPTIONS
-
- .text
- .align 4
- .global _xtos_return_from_exc
-_xtos_return_from_exc:
-
-#ifdef __XTENSA_CALL0_ABI__
-
- l32i a0, a1, UEXC_a0 // restore general registers, pc, ps
- l32i a4, a1, UEXC_a4
- l32i a5, a1, UEXC_a5
- l32i a6, a1, UEXC_a6
- l32i a7, a1, UEXC_a7
- l32i a8, a1, UEXC_a8
- l32i a9, a1, UEXC_a9
- l32i a10, a1, UEXC_a10
- l32i a11, a1, UEXC_a11
- l32i a12, a1, UEXC_a12
- l32i a13, a1, UEXC_a13
- l32i a14, a1, UEXC_a14
- l32i a15, a1, UEXC_a15
-
- l32i a2, a1, UEXC_pc
- l32i a3, a1, UEXC_ps
- wsr.epc1 a2
- wsr.ps a3
-
- l32i a2, a1, UEXC_a2
- l32i a3, a1, UEXC_a3
-
- rsync // wait for WSR to PS to complete
-
- addi a1, a1, ESF_TOTALSIZE // restore sp
-
- rfe
-
-#else /* ! __XTENSA_CALL0_ABI__ */
-
-
- // Here we rotated back by N registers, to the interrupted code's register window.
- // NOTA: a2 and a3 might contain something useful, but we haven't determined
- // what that might be yet (for now, a2 contains nested-C-func call-chain ptr).
-
- // NOTE: a5 still contains the exception window's exception stack frame pointer.
-
-# if XTOS_CNEST
- s32i a2, a5, ESF_TOTALSIZE-20 // restore nested-C-func call-chain ptr
-# endif
- l32i a2, a5, UEXC_ps
- l32i a3, a5, UEXC_pc
- wsr.ps a2 // this sets PS.EXCM
-
- l32i a2, a5, UEXC_a2
- l32i a4, a5, UEXC_a4
- rsync // wait for WSR to PS to complete
-
- /* FIXME: Enabling this here may break task-engine builds
- * because task engines have exceptions (sort of), but they do
- * not have the EPC_1 special register. XCHAL_HAVE_INTERRUPTS
- * is incorrect for normal configs without interrupts but with
- * exceptions (we still need to restore EPC_1). The correct
- * solution is to define XCHAL_HAVE_EXCEPTIONS more strictly
- * to mean something like "Have exceptions with
- * user/kernel/double vectors" so that task engines are
- * excluded. This would be a change to
- * <xtensa/config/core.h>. */
-
- wsr.epc1 a3
- // HERE:
- // - we cannot get window overflows anymore -- we're NOT in a valid windowed context
- // - low-priority interrupts are still disabled
-
- // NOTE: we don't restore EXCCAUSE or EXCVADDR, not needed.
-
- // Restore a3, a5:
- l32i a3, a5, UEXC_a3
- l32i a5, a5, UEXC_a5
-
- rfe_rfue
-
-#endif /* __XTENSA_CALL0_ABI__ */
-
- .size _xtos_return_from_exc, . - _xtos_return_from_exc
-
-#endif /* XCHAL_HAVE_XEA2 && XCHAL_HAVE_EXCEPTIONS */
-
diff --git a/src/arch/xtensa/smp/xtos/xea2/int-lowpri-dispatcher.S b/src/arch/xtensa/smp/xtos/xea2/int-lowpri-dispatcher.S
deleted file mode 100644
index 38d6e44..0000000
--- a/src/arch/xtensa/smp/xtos/xea2/int-lowpri-dispatcher.S
+++ /dev/null
@@ -1,725 +0,0 @@
-// Level-one interrupt dispatcher (user vectored handler)
-
-// Copyright (c) 1999-2015 Tensilica Inc.
-//
-// Permission is hereby granted, free of charge, to any person obtaining
-// a copy of this software and associated documentation files (the
-// "Software"), to deal in the Software without restriction, including
-// without limitation the rights to use, copy, modify, merge, publish,
-// distribute, sublicense, and/or sell copies of the Software, and to
-// permit persons to whom the Software is furnished to do so, subject to
-// the following conditions:
-//
-// The above copyright notice and this permission notice shall be included
-// in all copies or substantial portions of the Software.
-//
-// THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
-// EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
-// MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
-// IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY
-// CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
-// TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
-// SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
-
-#include <xtensa/coreasm.h>
-#include "../xtos-internal.h"
-#include "../interrupt-pri.h"
-
-#if XCHAL_HAVE_XEA2 && XCHAL_HAVE_EXCEPTIONS && XCHAL_HAVE_INTERRUPTS
-
-
- /*
- * Macros to slightly reduce the number of #if statements in the code:
- */
-
-/* This is set (for #if only) if there is only ONE interrupt configured at level one: */
-#define XTOS_SINGLE_INT defined(XCHAL_INTLEVEL1_NUM)
-
-/* Simplify the #if's around saving and restoring of SAR ('#' is a comment char): */
-#if ((XTOS_SUBPRI_ORDER == XTOS_SPO_ZERO_LO) || (XTOS_INT_FAIRNESS && XTOS_SUBPRI)) && !XTOS_SINGLE_INT
-# define NEEDSAR /* need SAR saved early w/ints locked */
-# define LATESAR # /* need SAR saved late w/ints unlocked */
-#else
-# define NEEDSAR # /* need SAR saved early w/ints locked */
-# define LATESAR /* need SAR saved late w/ints unlocked */
-#endif
-
-/* Simplify the #if's around fairness-specific code ('#' is a comment char): */
-#if XTOS_INT_FAIRNESS
-# define IFFAIR /* for code enabled only for fairness */
-# define NOFAIR # /* for code enabled only without fairness */
-#else
-# define IFFAIR # /* for code enabled only for fairness */
-# define NOFAIR /* for code enabled only without fairness */
-#endif
-/*
- * Note about implementation of "fairness".
- * The fairness mask is meant to represent, among a set of interrupts pending
- * at the same time, which ones haven't yet been serviced. It's to avoid,
- * among interrupts simultaneously pending at the same priority level,
- * servicing an interrupt more than once before servicing another.
- * Without the mask, if we for example just always serviced the lowest
- * numbered pending interrupt, then a lower numbered interrupt might get
- * serviced many times before servicing a higher numbered one, even though
- * they're at the same priority and pending at the same time -- thus an
- * "unfair" situation.
- * The typical way to do this fairly is to loop looking at each interrupt
- * number in sequence, determining whether that interrupt needs servicing,
- * and to repeat looping if at least one interrupt was serviced (or at
- * one remains pending).
- * Using the mask is faster, as we only look at pending interrupts,
- * instead of looping looking at all interrupts.
- */
-
-
- // NOTE: something equivalent to the following vector is executed
- // before entering this handler (see user-vector.S).
-//_UserExceptionVector:
-// addi a1, a1, -ESF_TOTALSIZE // allocate exception stack frame, etc.
-// s32i a2, a1, UEXC_a2
-// s32i a3, a1, UEXC_a3
-// movi a3, xtos_exc_handler_table
-// rsr.exccause a2
-// addx4 a2, a2, a3
-// l32i a2, a2, 0
-// s32i a4, a1, UEXC_a4
-// jx a2 // jump to cause-specific handler
-
- .global _need_user_vector_ // pull-in real user vector (tiny LSP)
-
- .text
- .align 4
- .global _xtos_l1int_handler
-_xtos_l1int_handler:
- // HERE: a2, a3, a4 have been saved to exception stack frame allocated with a1 (sp).
-
- s32i a5, a1, UEXC_a5 // a5 will get clobbered by ENTRY after pseudo-CALL4
- // (a4..a15 spilled as needed; save if modified)
-
- // Set PS fields:
- // EXCM = 0
- // WOE = __XTENSA_CALL0_ABI__ ? 0 : 1
- // UM = 1
- // INTLEVEL = EXCM_LEVEL
- // CALLINC = __XTENSA_CALL0_ABI__ ? 0 : 1
- // OWB = 0 (actual value is a don't care)
-
- movi a2, PS_UM|PS_INTLEVEL(XCHAL_EXCM_LEVEL)|PS_WOECALL4_ABI // CALL4 emulation
- rsr.epc1 a3
- xsr.ps a2
-
-#ifdef __XTENSA_WINDOWED_ABI__
- // HERE: window overflows enabled, but NOT SAFE because we're not quite
- // in a valid windowed context (haven't restored a1 yet);
- // so don't cause any (by accessing only a0..a3) until we've saved critical state
- // and restored a1 (note: critical state already saved in a2 and a3):
- // NOTE: saved EPC1 before causing any overflows, because overflows corrupt EPC1.
-#endif
-
- s32i a3, a1, UEXC_pc
- s32i a2, a1, UEXC_ps
-
-
-#ifdef __XTENSA_CALL0_ABI__
-
- s32i a0, a1, UEXC_a0 // save the rest of the registers
- s32i a6, a1, UEXC_a6
- s32i a7, a1, UEXC_a7
- s32i a8, a1, UEXC_a8
- s32i a9, a1, UEXC_a9
- s32i a10, a1, UEXC_a10
- s32i a11, a1, UEXC_a11
- s32i a12, a1, UEXC_a12
- s32i a13, a1, UEXC_a13
- s32i a14, a1, UEXC_a14
- s32i a15, a1, UEXC_a15
-# if XTOS_DEBUG_PC
- // TODO: setup return PC for call traceback through interrupt dispatch
-# endif
-
- rsync // wait for WSR to PS to complete
-
-#else /* ! __XTENSA_CALL0_ABI__ */
-
-# if XTOS_CNEST
- l32i a2, a1, ESF_TOTALSIZE-20 // save nested-C-func call-chain ptr
-# endif
- addi a1, a1, ESF_TOTALSIZE // restore sp (dealloc ESF) for sane stack again
- rsync // wait for WSR to PS to complete
-
- /* HERE: we can SAFELY get window overflows.
- *
- * From here, registers a4..a15 automatically get spilled if needed.
- * They become a0..a11 after the ENTRY instruction.
- * Currently, we don't check whether or not these registers
- * get spilled, so we must save and restore any that we
- * modify. We've already saved a4 and a5
- * which we modify as part of the pseudo-CALL.
- *
- * IMPLEMENTATION NOTE:
- *
- * The pseudo-CALL below effectively saves registers a2..a3
- * so that they are available again after the corresponding
- * RETW when returning from the exception handling. We
- * could choose to put something like EPC1 or PS in
- * there, so they're available more quickly when
- * restoring. HOWEVER, exception handlers may wish to
- * change such values, or anything on the exception stack
- * frame, and expect these to be restored as modified.
- *
- * NOTA: future: figure out what's the best thing to put
- * in a2 and a3. (candidate: a4 and a5 below; but what
- * if exception handler manipulates ARs, as in a syscall
- * handler.... oh well)
- *
- *
- * Now do the pseudo-CALL.
- * Make it look as if the code that got the exception made a
- * CALL4 to the exception handling code. (We call
- * this the "pseudo-CALL".)
- *
- * This pseudo-CALL is important and done this way:
- *
- * 1. There are only three ways to safely update the stack pointer
- * in the windowed ABI, such that window exceptions work correctly:
- * (a) spill all live windows to stack then switch to a new stack
- * (or, save the entire address register file and window
- * registers, which is likely even more expensive)
- * (b) use MOVSP (or equivalent)
- * (c) use ENTRY/RETW
- * Doing (a) is excessively expensive, and doing (b) here requires
- * copying 16 bytes back and forth which is also time-consuming;
- * whereas (c) is very efficient, so that's what we do here.
- *
- * 2. Normally we cannot do a pseudo-CALL8 or CALL12 here.
- * According to the
- * windowed ABI, a function must allocate enough space
- * for the largest call that it makes. However, the
- * pseudo-CALL is executed in the context of the
- * function that happened to be executing at the time
- * the interrupt was taken, and that function might or
- * might not have allocated enough stack space for a
- * CALL8 or a CALL12. If we try doing a pseudo-CALL8
- * or -CALL12 here, we corrupt the stack if the
- * interrupted function happened to not have allocated
- * space for such a call.
- *
- * 3. We set the return PC, but it's not strictly
- * necessary for proper operation. It does make
- * debugging, ie. stack tracebacks, much nicer if it
- * can point to the interrupted code (not always
- * possible, eg. if interrupted code is in a different
- * GB than the interrupt handling code, which is
- * unlikely in a system without protection where
- * interrupt handlers and general application code are
- * typically linked together).
- *
- * IMPORTANT: Interrupts must stay disabled while doing the pseudo-CALL,
- * or at least until after the ENTRY instruction, because SP has been
- * restored to its original value that does not reflect the exception
- * stack frame's allocation. An interrupt taken here would
- * corrupt the exception stack frame (ie. allocate another over it).
- * (High priority interrupts can remain enabled, they save and restore
- * all of their state and use their own stack or save area.)
- * For the same reason, we mustn't get any exceptions in this code
- * (other than window exceptions where noted) until ENTRY is done.
- */
-
- // HERE: may get a single window overflow (caused by the following instruction).
-
-# if XTOS_DEBUG_PC
- movi a4, 0xC0000000 // [for debug] for return PC computation below
- or a3, a4, a3 // [for debug] set upper two bits of return PC
- addx2 a4, a4, a3 // [for debug] clear upper bit
-# else
- movi a4, 0 // entry cannot cause overflow, cause it here
-# endif
-
- .global _LevelOneInterrupt
-_LevelOneInterrupt: // this label makes tracebacks through interrupts look nicer
-
- _entry a1, ESF_TOTALSIZE // as if after a CALL4 (PS.CALLINC set to 1 above)
-
- /*
- * The above ENTRY instruction does a number of things:
- *
- * 1. Because we're emulating CALL4, the ENTRY rotates windows
- * forward by 4 registers (as per 'ROTW +1'), so that
- * a4-a15 became a0-a11. So now: a0-a11 are part of
- * the interrupted context to be preserved. a0-a1
- * were already saved above when they were a4-a5.
- * a12-a15 are free to use as they're NOT part of the
- * interrupted context. We don't need to save/restore
- * them, and they will get spilled if needed.
- *
- * 2. Updates SP (new a1), allocating the exception stack
- * frame in the new window, preserving the old a1 in
- * the previous window.
- *
- * 3. The underscore prefix prevents the assembler from
- * automatically aligning the ENTRY instruction on a
- * 4-byte boundary, which could create a fatal gap in
- * the instruction stream.
- *
- * At this point, ie. before we re-enable interrupts, we know the caller is
- * always live so we can safely modify a1 without using MOVSP (we can use MOVSP
- * but it will never cause an ALLOCA or underflow exception here).
- * So this is a good point to modify the stack pointer if we want eg. to
- * switch to an interrupt stack (if we do, we need to save the current SP
- * because certain things have been saved to that exception stack frame).
- * We couldn't do this easily before ENTRY, where the caller wasn't
- * necessarily live.
- */
-
-# if 0 /*... non-nested interrupt ...*/
- mov ...some address register..., a1 // save ptr to original ESF
- movi a1, _interrupt_stack // switch stack
-# endif
-
-#endif /* __XTENSA_CALL0_ABI__ */
-
- /*
- * Now we can enable interrupts of higher virtual priority than the one(s)
- * being dispatched/processed here. This may entail some software prioritization,
- * if so configured.
- * (Pseudo-CALL is complete, and SP reflects allocation of exception stack frame
- * or switch to new stack.)
- */
-
- rsilft a15, XCHAL_EXCM_LEVEL, 1 // INTERRUPT reg *must* be read at PS.INTLEVEL<=1
- // (otherwise it might get higher pri ints)
-#define CUR_INTLEVEL 1
- /* At this point, PS.INTLEVEL is 1. */
-
-
- /***************** Dispatch low-priority interrupts to service *****************/
-
- /* HERE: We may get up to 3 window overflows on the following instruction.
- *
- * The worst case is 3 overflows, two 4-register overflows and one
- * 12-register overflow.
- */
-
-
-#if XTOS_VIRTUAL_INTENABLE
- /*
- * The INTENABLE register is virtualized, because it serves two purposes:
- * controlling which interrupts are active (eg. enabled once a handler
- * is registered) as reflected in _xtos_enabled, and what is the current
- * effective interrupt level as reflected in _xtos_vpri_enabled.
- *
- * The INTENABLE register always contains (_xtos_enabled & _xtos_vpri_enabled).
- * NOTE: It is important that INTENABLE, _xtos_enabled and _xtos_vpri_enabled
- * only be modified when interrupts at XTOS_LOCK_LEVEL and below are disabled,
- * that they never be modified by interrupts at levels above XTOS_LOCK_LEVEL,
- * and that they be consistent and never modified when the current interrupt
- * level is below XTOS_LOCK_LEVEL.
- *
- * NOTE: Reading the INTERRUPT register *must* be done at PS.INTLEVEL <= 1
- * otherwise we might incorrectly see higher priority interrupts.
- */
- movi a13, 0xCCC
- movi a14, 0xbe00e000
- s32i a13, a14, 0
-
- xtos_addr_percore a14, xtos_intstruct // address of interrupt management globals
- rsr.interrupt a15 // interrupts pending
- rsr.intenable a12 // interrupts enabled (already should equal _xtos_enabled & _xtos_vpri_enabled)
- l32i a13, a14, XTOS_VPRI_ENABLED_OFS // read previous _xtos_vpri_enabled
- and a15, a15, a12 // a15 = INTERRUPT & (interrupts we can consider processing)
-NEEDSAR rsr.sar a12
- s32i a13, a1, UEXC_vpri // save previous vpri
-
- _beqz a15, spurious_int // no interrupt to handle (spurious interrupt)
-NEEDSAR s32i a12, a1, UEXC_sar // note: in XEA1, UEXC_sar must be set *after* beqz above
-
-IFFAIR s32i a2, a1, UEXC_exccause // save a2 (interrupted code's a6)
-IFFAIR movi a2, -1 // initial fairness mask
-
-.L1_loop0:
- // a15 = non-zero mask of interrupt bits to consider handling
-
-# if XTOS_SUBPRI_ORDER == XTOS_SPO_ZERO_HI && !XTOS_INT_FAIRNESS && !XTOS_SUBPRI_GROUPS
- // Special case that can be handled a bit more efficiently:
-
- neg a12, a15 // find lsbit in a15 ...
- and a12, a12, a15 // ...
- // a12 = single bit corresponding to interrupt to be processed (highest pri pending+enabled).
-
- // Compute a13 = new virtual priority based on this selected highest priority interrupt:
- movi a15, ~XCHAL_LOWPRI_MASK // mask of all low-priority interrupts
- addi a13, a12, -1 // mask of interrupts enabled at this new priority
- or a13, a13, a15 // also leave medium- and high-priority interrupts enabled
-
-# else /* special case */
-
- // Entry:
- // a12 = (undefined)
- // a13 = (undefined)
- // a14 = &_xtos_intstruct --or-- interrupt table adjusted base
- // a15 = non-zero mask of interrupt bits to consider handling
- // Exit:
- // a12 = index
- // a13 = (clobbered)
- // a14 = (preserved)
- // a15 = single bit corresponding to index
- //
- indexmask_int a12, a15, a14, a13
-
- // a12 = index of highest priority pending+enabled interrupt, to be processed.
- // a15 = (1 << a12), ie. bit corresponding to interrupt to be processed.
-IFFAIR xor a2, a2, a15 // update fairness mask - mask out this interrupt until recycling mask
- xtos_addr_percore_sub a13, xtos_interrupt_table, IFNSA( (32-XCHAL_NUM_INTERRUPTS)*XIE_SIZE, 0 )
- wsr.intclear a15 // clear interrupt (if software or external edge-triggered or write-error)
- addx8 a12, a12, a13 // a12 = address in interrupt table for given interrupt number
-
-.L1_loop1:
- // a12 now contains pointer to interrupt table entry for interrupt to be processed
- l32i a13, a12, XIE_VPRIMASK // a13 = new vpri (mask of interrupts enabled at this interrupt's priority)
-# endif /* !special case */
-
- // a13 = new virtual priority based on the selected highest priority interrupt
-
- rsilft a15, 1, XTOS_LOCKLEVEL // lockout
-
- // Now do the equivalent of: prev = _xtos_set_vpri( a13 );
-
- l32i a15, a14, XTOS_ENABLED_OFS // a15 = _xtos_enabled
- s32i a13, a14, XTOS_VPRI_ENABLED_OFS // update new _xtos_vpri_enabled
- and a15, a15, a13 // a15 = _xtos_enabled & _xtos_vpri_enabled
- //NOTE: Here, do: a15 &= ~_xtos_pending if XTOS_VIRTUAL_INTERRUPT is set.
- wsr.intenable a15
- //interlock
- //interlock
- rsync // NOTA - not ISA defined // wait for INTENABLE write to complete before we set PS.INTLEVEL to zero
-
-
- // Okay, we've updated INTENABLE to reflect the new virtual priority (vpri)
- // according to the highest priority pending+enabled (low-priority) interrupt.
-
- // IMPLEMENTATION NOTE - Before we unlock (enable interrupts), we could
- // switch stacks here, now that we have enough free registers through the unlock.
-
- // Now we can enable interrupts via PS.INTLEVEL.
-
- rsil a15, 0 // unlock
-# undef CUR_INTLEVEL
-# define CUR_INTLEVEL 0
-
- // HERE: interrupts are enabled again (those interrupts of
- // higher virtual priority than the one we're currently processing).
-
- // HERE:
- // a12 = pointer to interrupt entry in table, or
- // mask of interrupt bit to process (special case only)
- // a13, a15 = available for use
- // a14 = available for use if virtual INTENABLE, else is pointer to interrupt table
-
-# if XTOS_SUBPRI_ORDER == XTOS_SPO_ZERO_HI && !XTOS_INT_FAIRNESS && !XTOS_SUBPRI_GROUPS
- /* In this special case, we moved as much as possible where interrupts are enabled again: */
- // a12 is bit corresponding to interrupt, convert to ptr to interrupt table entry...
- xtos_addr_percore_sub a14, xtos_interrupt_table, IFNSA( (32-XCHAL_NUM_INTERRUPTS)*XIE_SIZE, 0 )
- wsr.intclear a12 // clear interrupt (if software or external edge-triggered or write-error)
-//IFFAIR xor a2, a2, a12 // update fairness mask - mask out this interrupt until recycling mask
- msindex_int a15, a12 // a15 = index of msbit set in a12 (a12 clobbered)
- addx8 a12, a15, a14 // a12 = address in interrupt table for given interrupt number
-# endif /* special case */
-
-
-
-#elif XTOS_SINGLE_INT
- /*
- * Only one interrupt is configured to map to this vector.
- * This simplifies the code considerably -- no checking and resolving of INTERRUPT
- * register required. Just call the handler and exit.
- *
- * (With INTENABLE register virtualization, the simplification is
- * not as great, and not implemented separately above.)
- */
-
-
-# define XTOS_SINGLE_INT_NUM XCHAL_INTLEVEL1_NUM
-# define XTOS_SINGLE_INT_MASK XCHAL_INTLEVEL1_MASK
-# define XTOS_SINGLE_INT_CLEAR ((XTOS_SINGLE_INT_MASK & XCHAL_INTCLEARABLE_MASK) != 0)
-# if XTOS_SINGLE_INT_CLEAR
- movi a13, XCHAL_LOWPRI_MASK // bit to clear in INTERRUPT register
-# endif
- // Get pointer to interrupt table entry for this vector's only interrupt:
- xtos_addr_percore_add a12, xtos_interrupt_table, MAPINT(XTOS_SINGLE_INT_NUM)*XIE_SIZE
-# if XTOS_SINGLE_INT_CLEAR
- wsr.intclear a13 // clear interrupt pending bit (if software or external-edge-triggered or write-error)
-# endif
-
-
-
-#else /* ie. if !XTOS_VIRTUAL_INTENABLE && !XTOS_SINGLE_INT */
- /*
- * Here, the INTENABLE register is NOT virtualized. There are no _xtos_enabled
- * or _xtos_vpri_enabled global variables to track. INTENABLE simply controls
- * which interrupts are active (eg. enabled once a handler is registered).
- *
- * NOTE: To ensure its coherency, it is still important to only modify the
- * INTENABLE register when interrupts at XTOS_LOCK_LEVEL and below are disabled,
- * that it never be modified by interrupts at levels above XTOS_LOCK_LEVEL,
- * and that it never be modified when the current interrupt level is below
- * XTOS_LOCK_LEVEL. This is because modifications to INTENABLE generally
- * require an RSR/modify/WSR sequence to modify only selected bits.
- *
- * NOTE: Reading the INTERRUPT register *must* be done at PS.INTLEVEL <= 1
- * otherwise we might incorrectly see higher priority interrupts.
- *
- * This option implies XEA2, because XEA1 always requires INTENABLE virtualization.
- * This option also implies SUBPRI is zero (no interrupt sub-prioritization in software).
- */
-
-
- rsr.interrupt a15 // interrupts pending
- rsr.intenable a13 // interrupts enabled (directly; no virtualization)
- xtos_addr_percore_sub a14, xtos_interrupt_table, IFNSA( (32-XCHAL_NUM_INTERRUPTS)*XIE_SIZE, 0 )
-NEEDSAR rsr.sar a12
- and a15, a15, a13 // a15 = INTERRUPT & INTENABLE
-
- _beqz a15, spurious_int // no interrupt to handle (spurious interrupt)
-NEEDSAR s32i a12, a1, UEXC_sar
-
-IFFAIR s32i a2, a1, UEXC_exccause // save a2 (interrupted code's a6)
-IFFAIR movi a2, -1 // initial fairness mask
-
-.L1_loop0:
- // Entry:
- // a12 = (undefined)
- // a13 = (undefined)
- // a14 = interrupt table adjusted base (not used here)
- // a15 = non-zero mask of interrupt bits to consider handling
- // Exit:
- // a12 = index
- // a13 = (clobbered)
- // a14 = (preserved)
- // a15 = single bit corresponding to index
- //
- indexmask_int a12, a15, a14_UNUSED, a13
-
- // a12 = index of highest priority pending+enabled interrupt, to be processed.
- // a15 = (1 << a12), ie. bit corresponding to interrupt to be processed.
-IFFAIR xor a2, a2, a15 // update fairness mask - mask out this interrupt until recycling mask
- wsr.intclear a15 // clear interrupt (if software or external edge-triggered or write-error)
-
- addx8 a12, a12, a14 // a12 = address in interrupt table for given interrupt number
-
-.L1_loop1:
- // a12 now contains pointer to interrupt table entry for interrupt to be processed
-
- // HERE:
- // a12 = pointer to interrupt entry in table
- // a13, a15 = available for use
- // a14 = available for use if virtual INTENABLE, else is pointer to interrupt table
-
-
-#endif /* !XTOS_VIRTUAL_INTENABLE && !XTOS_SINGLE_INT */
- /* At this point, PS.INTLEVEL is: 1 if (XTOS_SINGLE_INT || !XTOS_VIRTUAL_INTENABLE), 0 otherwise */
-
- // HERE: a12 = pointer to interrupt entry in table
-
- // (Possible enhancement: do at higher-level, to avoid doing it all the time? !?!?!?)
- save_loops_mac16 a1, a13, a15 // save LOOP & MAC16 regs, if configured
-
-LATESAR rsr.sar a15
-
- l32i a13, a12, XIE_HANDLER // a13 = address of interrupt handler
-LATESAR s32i a15, a1, UEXC_sar
-
-#ifdef __XTENSA_CALL0_ABI__
- l32i a2, a12, XIE_ARG // first arg
- mov a3, a1 // second arg, exception stack frame
- callx0 a13 // call interrupt handler
-#else
- mov a15, a1 // second arg, exception stack frame
- l32i a14, a12, XIE_ARG // first argument passed to interrupt handler (relayed by context-dispatcher, if non-nested)
- callx12 a13 // execute interrupt handler, directly or via context-dispatcher (clobbers a12-a15)
-#endif
-
- // (Possible enhancement: do at higher-level, to avoid doing it all the time? !?!?!?)
- restore_loops_mac16 a1, a13, a14, a15 // restore LOOP & MAC16 regs, if configured
-
-LATESAR l32i a12, a1, UEXC_sar
-
-
-#if XTOS_VIRTUAL_INTENABLE
- /* Here, INTENABLE register is virtualized. */
-
- xtos_addr_percore a14, xtos_intstruct // address of interrupt management globals
-LATESAR wsr.sar a12
- rsr.interrupt a15
- rsil a13, XTOS_LOCKLEVEL
- l32i a13, a14, XTOS_ENABLED_OFS // a13 = _xtos_enabled
- l32i a12, a1, UEXC_vpri // read saved vpri
- //interlock
- and a13, a13, a12 // a13 = old-vpri & _xtos_enabled (INTENABLE value to restore)
- and a15, a15, a13 // what's pending among what we can handle?
-
-
- // a15 now contains the remaining pending+enabled interrupts.
- // NOTE: we MUST NOT consider interrupts potentially already being handled
- // by another interrupt handler that we pre-empted.
- // So we masked with saved vpri, ie. the set of interrupts enabled when we entered
- // this handler, ie. the set of interrupts that can pre-empt the previous context.
-NOFAIR _bnez a15, .L1_loop0 // more interrupt(s) to handle
-IFFAIR _bnez a15, preloop // more interrupt(s) to handle
-IFFAIR l32i a2, a1, UEXC_exccause // restore a2 (interrupted code's a6)
-
-
- // NOTE:
- // Register allocation is why we didn't restore *HERE* the loop regs, MAC16, SAR, etc.
- // (at least part of the reason)
- // We only have one registers (a15), however with 7-stage pipe, three registers
- // are required to avoid interlocks. We could get 2 more registers at 1 cycle each [now only one?],
- // but it isn't obvious whether paying these extra cycles are worth it...
-
- // Restore vpri as it was before we handled the interrupt(s):
- s32i a12, a14, XTOS_VPRI_ENABLED_OFS // restore _xtos_vpri_enabled
-NEEDSAR l32i a12, a1, UEXC_sar
- wsr.intenable a13 // update INTENABLE per original vpri
-
- // NOTE: leave locked, disabling only the low- and medium-priority interrupts
- rsilft a13, XTOS_LOCKLEVEL, XCHAL_EXCM_LEVEL // lockout
-# undef CUR_INTLEVEL
-# define CUR_INTLEVEL XCHAL_EXCM_LEVEL
-
-#elif XTOS_SINGLE_INT
-
-# undef NEEDSAR
-# define NEEDSAR
-
-#else /* ie. if !XTOS_VIRTUAL_INTENABLE && !XTOS_SINGLE_INT */
- /* Here, INTENABLE register is NOT virtualized (implies XEA2). */
-
- rsr.interrupt a15 // interrupts pending
- rsr.intenable a13 // interrupts enabled (directly; no virtualization)
- xtos_addr_percore_sub a14, xtos_interrupt_table, IFNSA( (32-XCHAL_NUM_INTERRUPTS)*XIE_SIZE, 0 )
-LATESAR wsr.sar a12
- and a15, a15, a13 // a15 = INTERRUPT & INTENABLE
-
- // a15 now contains the remaining pending+enabled interrupts.
- // NOTE: we MUST NOT consider interrupts potentially already being handled
- // by another interrupt handler that we pre-empted.
- // So we masked with saved vpri, ie. the set of interrupts enabled when we entered
- // this handler, ie. the set of interrupts that can pre-empt the previous context.
-NOFAIR _bnez a15, .L1_loop0 // more interrupt(s) to handle
-IFFAIR _bnez a15, preloop // more interrupt(s) to handle
-IFFAIR l32i a2, a1, UEXC_exccause // restore a2 (interrupted code's a6)
-
-
- // NOTE:
- // Register allocation is why we didn't restore *HERE* the loop regs, MAC16, SAR, etc.
- // (at least part of the reason)
- // We only have one registers (a15), however with 7-stage pipe, three registers
- // are required to avoid interlocks. We could get 2 more registers at 1 cycle each [now only one?],
- // but it isn't obvious whether paying these extra cycles are worth it...
-
-NEEDSAR l32i a12, a1, UEXC_sar
-#endif /* !XTOS_VIRTUAL_INTENABLE && !XTOS_SINGLE_INT */
-
-
- /***************************/
-
- // Now exit the handler.
-
- /*
- * Leave interrupts disabled while returning from the pseudo-CALL setup above,
- * for the same reason they were disabled while doing the pseudo-CALL:
- * this sequence restores SP such that it doesn't reflect the allocation
- * of the exception stack frame, which is still needed to return from
- * the exception.
- */
-
-spurious_int:
-
-# if XCHAL_HAVE_EXCLUSIVE
- // Clear exclusive monitors.
- clrex
-# endif
-
- movi a0, _xtos_return_from_exc
-#ifdef __XTENSA_CALL0_ABI__
-NEEDSAR wsr.sar a12
- jx a0
-#else /* ! __XTENSA_CALL0_ABI__ */
- // Now return from the pseudo-CALL from the interrupted code, to rotate
- // our windows back...
-
- movi a13, 0xC0000000
-NEEDSAR wsr.sar a12
- or a0, a0, a13 // set upper two bits
- addx2 a0, a13, a0 // clear upper bit
-
- // Disable ints during unalloc'ed live stack after RETW below.
- rsil a13, XCHAL_EXCM_LEVEL // might come here via spurious_int, so always rsil
-
- retw
-#endif /* __XTENSA_CALL0_ABI__ */
-
-
-
-#if XTOS_INT_FAIRNESS
-preloop:
- // Lowering priority or recycling fairness-mask bits ...
- // a14 = &_xtos_intstruct *or* interrupt table ptr
- // a15 = non-zero mask of interrupt bits to consider handling
-
-# if !XTOS_SUBPRI
- and a13, a15, a2 // a13 = interrupt bits to consider handling, masked for fairness
- movi a12, -1 // (new fairness mask, all one's)
- moveqz a2, a12, a13 // recycle fairness mask if all bits to consider are masked by fairness, and leave a15 intact
- movnez a15, a13, a13 // otherwise set a15 = a13, ie. mask out bits for fairness (a15 is still non-zero)
- j .L1_loop0
-# else /* XTOS_SUBPRI */
- // NOTE: In this case, with SUBPRI, XTOS_VIRTUAL_INTENABLE is always set.
- // So: a14 = &_xtos_intstruct
-
- // Compute a13 = index of highest priority interrupt in a15 (a13 is reversed if NSA present)
- // (a14, a15 preserved; a12 is a temporary):
- index_int a13, a15, a14, a12
-
- // a12 = (available)
- // a13 = index
- // a14 = &_xtos_intstruct
- // a15 = mask of candidates
- xtos_addr_percore_sub a12, xtos_interrupt_table, IFNSA( (32-XCHAL_NUM_INTERRUPTS)*XIE_SIZE, 0 )
- //slot
- addx8 a12, a13, a12 // a12 = address in interrupt table for given interrupt number
- l32i a14, a12, XIE_LEVELMASK // a14 = mask of all interrupts at selected interrupt's level
- and a15, a15, a2 // mask out for fairness
- and a15, a15, a14 // only consider interrupts at highest pending level
- xtos_addr_percore a14, xtos_intstruct // needed at loop0, and below
- _bnez a15, .L1_loop0 // interrupts are allowed by current fairness mask, redo indexing with proper mask (a15, a14 = ...)
-
- // a12 = ptr to interrupt entry
- // a13 = index
- // a14 = &_xtos_intstruct
- // a15 = (available)
-
- // Compute bitmask of interrupt to be processed...
-# if XCHAL_HAVE_NSA
- movi a15, 0x80000000
- ssr a13
- srl a13, a15
-# else
- movi a15, 1
- ssl a13
- sll a13, a15
-# endif
- // a13 = single bit set corresponding to interrupt to be processed...
- l32i a15, a12, XIE_LEVELMASK // a15 = mask of all interrupts at selected interrupt's level
- wsr.intclear a13 // clear interrupt (if software or external edge-triggered or write-error)
- or a2, a2, a15 // recycle fairness mask for selected interrupt level
- xor a2, a2, a13 // update fairness mask - mask out this interrupt until recycling mask
- j .L1_loop1 // handle selected interrupt (a12 = interrupt entry, a14 = &_xtos_intstruct)
-
-# endif /* XTOS_SUBPRI */
-#endif /* XTOS_INT_FAIRNESS */
-
- /* FIXME: what about _LevelOneInterrupt ? */
- .size _xtos_l1int_handler, . - _xtos_l1int_handler
-
-#endif /* XCHAL_HAVE_XEA2 && XCHAL_HAVE_EXCEPTIONS && XCHAL_HAVE_INTERRUPTS */
-
diff --git a/src/arch/xtensa/smp/xtos/xea2/intlevel-restore.S b/src/arch/xtensa/smp/xtos/xea2/intlevel-restore.S
deleted file mode 100644
index 76fa727..0000000
--- a/src/arch/xtensa/smp/xtos/xea2/intlevel-restore.S
+++ /dev/null
@@ -1,86 +0,0 @@
-// intlevel-restore.S - Interrupt related assembler code - _xtos_restore_intlevel
-
-// Copyright (c) 2004-2015 Tensilica Inc.
-//
-// Permission is hereby granted, free of charge, to any person obtaining
-// a copy of this software and associated documentation files (the
-// "Software"), to deal in the Software without restriction, including
-// without limitation the rights to use, copy, modify, merge, publish,
-// distribute, sublicense, and/or sell copies of the Software, and to
-// permit persons to whom the Software is furnished to do so, subject to
-// the following conditions:
-//
-// The above copyright notice and this permission notice shall be included
-// in all copies or substantial portions of the Software.
-//
-// THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
-// EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
-// MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
-// IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY
-// CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
-// TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
-// SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
-
-#include <xtensa/coreasm.h>
-#include "../xtos-internal.h"
-
-#if XCHAL_HAVE_XEA2
-
-/***************************************************************************
- * void _xtos_restore_intlevel(unsigned restoreval);
- *
- * _xtos_restore_intlevel() restores the current interrupt level
- * according to a value returned by _xtos_set_intlevel() or
- * _xtos_set_min_intlevel() (or one of the corresponding macros).
- *
- * NOTE: In XEA2, this function may restore the entire PS register, not
- * just the PS.INTLEVEL field. If some other PS field(s) must be changed
- * and kept intact across restoring PS.INTLEVEL (this is generally unlikely),
- * use the XTOS_RESTORE_JUST_INTLEVEL() macro instead (which is slower).
- *
- * NOTE: The macro form of this function (XTOS_RESTORE_INTLEVEL())
- * is recommended (for XEA2 configs or where the config is unknown)
- * because it may be more efficient.
- */
-
- .text
- .global _xtos_restore_intlevel
- .type _xtos_restore_intlevel,@function
- .align 4
-_xtos_restore_intlevel:
- abi_entry
-# if XCHAL_HAVE_INTERRUPTS
- wsr a2, PS // restore PS
- rsync // wait for WSR to PS to complete
-# endif
- abi_return
- .size _xtos_restore_intlevel, . - _xtos_restore_intlevel
-
-
-
-/***************************************************************************
- * _xtos_set_vpri() is used to set the current virtual priority from C code;
- * it can be called from the application or from a C interrupt handler.
- */
-
- .global _xtos_set_vpri
- .type _xtos_set_vpri,@function
- .align 4
-_xtos_set_vpri:
- abi_entry
-#if XCHAL_HAVE_INTERRUPTS && XTOS_VIRTUAL_INTENABLE
- mov a3, a2
- xtos_addr_percore a4, xtos_intstruct
- xtos_lock a7 // MUST USE highest address register of function to avoid window overflows in critical section
- l32i a2, a4, XTOS_VPRI_ENABLED_OFS // return old xtos_vpri_enabled (current vpri)
- l32i a5, a4, XTOS_ENABLED_OFS // a3 = xtos_enabled
- s32i a3, a4, XTOS_VPRI_ENABLED_OFS // set new xtos_vpri_enabled (current vpri)
- and a5, a5, a3 // a5 = xtos_enabled & xtos_vpri_enabled
- wsr a5, INTENABLE
- xtos_unlock a7
-#endif /*XCHAL_HAVE_INTERRUPTS*/
- abi_return
- .size _xtos_set_vpri, . - _xtos_set_vpri
-
-#endif /* XEA2 */
-
diff --git a/src/arch/xtensa/smp/xtos/xea2/intlevel-set.S b/src/arch/xtensa/smp/xtos/xea2/intlevel-set.S
deleted file mode 100644
index 30a82c3..0000000
--- a/src/arch/xtensa/smp/xtos/xea2/intlevel-set.S
+++ /dev/null
@@ -1,63 +0,0 @@
-// intlevel-set.S - Interrupt related assembler code - _xtos_set_intlevel
-
-// Copyright (c) 2004-2015 Tensilica Inc.
-//
-// Permission is hereby granted, free of charge, to any person obtaining
-// a copy of this software and associated documentation files (the
-// "Software"), to deal in the Software without restriction, including
-// without limitation the rights to use, copy, modify, merge, publish,
-// distribute, sublicense, and/or sell copies of the Software, and to
-// permit persons to whom the Software is furnished to do so, subject to
-// the following conditions:
-//
-// The above copyright notice and this permission notice shall be included
-// in all copies or substantial portions of the Software.
-//
-// THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
-// EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
-// MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
-// IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY
-// CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
-// TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
-// SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
-
-#include <xtensa/coreasm.h>
-#include "../xtos-internal.h"
-
-#if XCHAL_HAVE_XEA2
-
-
-/***************************************************************************
- * unsigned _xtos_set_intlevel(int intlevel);
- *
- * _xtos_set_intlevel() is used to set the current priority from C code;
- * it can be called from the application or from a C interrupt handler.
- *
- * NOTE: This version allows the 'intlevel' parameter to be computed
- * at run-time, and thus is longer. It is much more efficient, and
- * highly recommented, to use the XTOS_SET_INTLEVEL(intlevel) macro instead
- * (which requires a constant intlevel).
- */
-
- .text
- .align 4
- .global _xtos_set_intlevel
- .type _xtos_set_intlevel,@function
-_xtos_set_intlevel:
- abi_entry
-#if XCHAL_HAVE_INTERRUPTS
- /* In XEA2, we can simply safely set PS.INTLEVEL directly: */
- extui a3, a2, 0, 4 // keep only INTLEVEL bits of parameter
- rsr.ps a2 // get old (current) PS.INTLEVEL
- movi a4, ~0xF
- and a4, a4, a2 // mask out PS.INTLEVEL
- or a4, a4, a3 // insert requested INTLEVEL
- wsr.ps a4 // update PS.INTLEVEL
- rsync // wait for WSR to PS to complete
-#endif /*XCHAL_HAVE_INTERRUPTS*/
- abi_return
-
- .size _xtos_set_intlevel, . - _xtos_set_intlevel
-
-#endif /* XEA2 */
-
diff --git a/src/arch/xtensa/smp/xtos/xea2/intlevel-setmin.S b/src/arch/xtensa/smp/xtos/xea2/intlevel-setmin.S
deleted file mode 100644
index 0d9f70e..0000000
--- a/src/arch/xtensa/smp/xtos/xea2/intlevel-setmin.S
+++ /dev/null
@@ -1,68 +0,0 @@
-// intlevel-setmin.S - Interrupt related assembler code - _xtos_set_min_intlevel
-
-// Copyright (c) 2004-2015 Tensilica Inc.
-//
-// Permission is hereby granted, free of charge, to any person obtaining
-// a copy of this software and associated documentation files (the
-// "Software"), to deal in the Software without restriction, including
-// without limitation the rights to use, copy, modify, merge, publish,
-// distribute, sublicense, and/or sell copies of the Software, and to
-// permit persons to whom the Software is furnished to do so, subject to
-// the following conditions:
-//
-// The above copyright notice and this permission notice shall be included
-// in all copies or substantial portions of the Software.
-//
-// THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
-// EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
-// MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
-// IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY
-// CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
-// TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
-// SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
-
-#include <xtensa/coreasm.h>
-#include "../xtos-internal.h"
-
-#if XCHAL_HAVE_XEA2
-
-
-/***************************************************************************
- * unsigned _xtos_set_min_intlevel(int intlevel);
- *
- * _xtos_set_min_intlevel() is identical to _xtos_set_intlevel() except
- * that it will not lower the current interrupt level. Instead,
- * it ensures that the current interrupt level is at least as high
- * as specified.
- *
- * NOTE: This version allows the 'intlevel' parameter to be computed
- * at run-time, and thus is longer. It is much more efficient, and
- * highly recommented, to use the XTOS_SET_MIN_INTLEVEL(intlevel) macro instead
- * (which requires a constant intlevel).
- */
-
- .text
- .align 4
- .global _xtos_set_min_intlevel
- .type _xtos_set_min_intlevel,@function
-_xtos_set_min_intlevel:
- abi_entry
-#if XCHAL_HAVE_INTERRUPTS
- /* In XEA2, we can simply safely set PS.INTLEVEL directly: */
- extui a3, a2, 0, 4 // keep only INTLEVEL bits of parameter
- rsr.ps a2 // get old (current) PS.INTLEVEL
- movi a4, ~0xF
- extui a5, a2, 0, 4 // look at old PS.INTLEVEL
- sub a5, a3, a5 // new.intlevel - old.intlevel
- and a4, a4, a2 // mask out PS.INTLEVEL
- or a4, a4, a3 // insert requested INTLEVEL
- movltz a4, a2, a5 // keep same PS if already higher than requested
- wsr.ps a4 // update PS.INTLEVEL
- rsync // wait for WSR to PS to complete
-#endif /*XCHAL_HAVE_INTERRUPTS*/
- abi_return
-
- .size _xtos_set_min_intlevel, . - _xtos_set_min_intlevel
-
-#endif /* XEA2 */
-
diff --git a/src/arch/xtensa/smp/xtos/xea2/reloc-vectors.S b/src/arch/xtensa/smp/xtos/xea2/reloc-vectors.S
deleted file mode 100644
index 7e9c176..0000000
--- a/src/arch/xtensa/smp/xtos/xea2/reloc-vectors.S
+++ /dev/null
@@ -1,120 +0,0 @@
-// reloc-vector.S - Relocatable Vectors section
-// $Id: //depot/rel/Foxhill/dot.8/Xtensa/OS/xtos/xea2/reloc-vectors.S#1 $
-
-// Copyright (c) 2007-2017 Tensilica Inc.
-//
-// Permission is hereby granted, free of charge, to any person obtaining
-// a copy of this software and associated documentation files (the
-// "Software"), to deal in the Software without restriction, including
-// without limitation the rights to use, copy, modify, merge, publish,
-// distribute, sublicense, and/or sell copies of the Software, and to
-// permit persons to whom the Software is furnished to do so, subject to
-// the following conditions:
-//
-// The above copyright notice and this permission notice shall be included
-// in all copies or substantial portions of the Software.
-//
-// THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
-// EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
-// MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
-// IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY
-// CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
-// TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
-// SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
-
-/*
- * This file is only used if the relocatable vectors option is enabled.
- */
-
-
-#include <xtensa/coreasm.h>
-#include <xtensa/config/system.h>
-
-#if XCHAL_HAVE_VECBASE
-
- .section .RelocatableVectors.text, "ax"
-
- .global _RelocVectors
-_RelocVectors:
-
-//if XCHAL_RESET_VECBASE_OVERLAP ...
-# if XSHAL_VECTORS_PACKED \
- && (XCHAL_RESET_VECTOR0_VADDR == XCHAL_VECBASE_RESET_VADDR \
- || XCHAL_RESET_VECTOR1_VADDR == XCHAL_VECBASE_RESET_VADDR)
-# define JUMP_TO_RESET 1
- j .Ljump_to_reset
-# endif
-
-# if XCHAL_HAVE_WINDOWED
-# define NO_SECTION_DIRECTIVES 1
-# define WINDOW_BASE_VECOFS 0
-# include "window-vectors.S"
-# endif
-
-#if XCHAL_HAVE_DEBUG && XCHAL_HAVE_EXCEPTIONS
-# if XCHAL_DEBUGLEVEL == 2
-# define _Level2Vector _DebugExceptionVector
-# elif XCHAL_DEBUGLEVEL == 3
-# define _Level3Vector _DebugExceptionVector
-# elif XCHAL_DEBUGLEVEL == 4
-# define _Level4Vector _DebugExceptionVector
-# elif XCHAL_DEBUGLEVEL == 5
-# define _Level5Vector _DebugExceptionVector
-# elif XCHAL_DEBUGLEVEL == 6
-# define _Level6Vector _DebugExceptionVector
-# endif
-#endif
-
-# if XCHAL_HAVE_INTERRUPTS
-# if XCHAL_NUM_INTLEVELS >= 2
- .org XCHAL_INTLEVEL2_VECOFS
- j _Level2Vector
-# endif
-# if XCHAL_NUM_INTLEVELS >= 3
- .org XCHAL_INTLEVEL3_VECOFS
- j _Level3Vector
-# endif
-# if XCHAL_NUM_INTLEVELS >= 4
- .org XCHAL_INTLEVEL4_VECOFS
- j _Level4Vector
-# endif
-# if XCHAL_NUM_INTLEVELS >= 5
- .org XCHAL_INTLEVEL5_VECOFS
- j _Level5Vector
-# endif
-# if XCHAL_NUM_INTLEVELS >= 6
- .org XCHAL_INTLEVEL6_VECOFS
- j _Level6Vector
-# endif
-# if XCHAL_HAVE_NMI
- .org XCHAL_NMI_VECOFS
- j _NMIExceptionVector
-# endif
-# endif
-# if XCHAL_HAVE_EXCEPTIONS
- .org XCHAL_KERNEL_VECOFS
- j _KernelExceptionVector
- .org XCHAL_USER_VECOFS
- j _UserExceptionVector
- .org XCHAL_DOUBLEEXC_VECOFS
- j _DoubleExceptionVector
-# endif
-
-// Put literals here.
-
-// Put actual handlers here.
-
-# if JUMP_TO_RESET
- .align 4
- .literal rvec, _ResetVector
-.Ljump_to_reset:
- l32r a2, rvec
- jx a2
-# endif
-
- .size _RelocVectors, . - _RelocVectors
-
- .text
-
-#endif /* XCHAL_HAVE_VECBASE */
-
diff --git a/src/arch/xtensa/smp/xtos/xea2/switch_context.S b/src/arch/xtensa/smp/xtos/xea2/switch_context.S
deleted file mode 100644
index b4ed2fa..0000000
--- a/src/arch/xtensa/smp/xtos/xea2/switch_context.S
+++ /dev/null
@@ -1,94 +0,0 @@
-/* switch_contexts.S - setup for multiple contexts */
-
-/*
- * Copyright (c) 2003-2010 Tensilica Inc.
- *
- * Permission is hereby granted, free of charge, to any person obtaining
- * a copy of this software and associated documentation files (the
- * "Software"), to deal in the Software without restriction, including
- * without limitation the rights to use, copy, modify, merge, publish,
- * distribute, sublicense, and/or sell copies of the Software, and to
- * permit persons to whom the Software is furnished to do so, subject to
- * the following conditions:
- *
- * The above copyright notice and this permission notice shall be included
- * in all copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
- * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
- * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
- * IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY
- * CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
- * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
- * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
- */
-
-#include <xtensa/coreasm.h>
-#include <xtensa/xtruntime-frames.h>
-
-#if XCHAL_NUM_CONTEXTS > 1
-
-
-/*
- * void _xtos_setup_context(int context_num, StartInfo *info);
- */
- .align 4
- .global _xtos_setup_context
- .type _xtos_setup_context,@function
-_xtos_setup_context:
- abi_entry
-#if XCHAL_HAVE_INTERRUPTS
- rsil a5, 15 /* disable interrupts so we can use EXCSAVE_1 */
-#else
- rsr.ps a5 /* just read PS */
-#endif
- wsr.excsave1 a3 /* save pointer to new context info */
- s32i a5, a3, INFO_prevps /* save previous PS */
- movi a4, ~0x01F00000 /* mask out PS.CTXT */
- slli a2, a2, 20 /* shift up new PS.CTXT value */
- and a4, a5, a4
- or a4, a4, a2 /* new PS value */
- wsr.ps a4
- rsync
- /* We're now in the new context! */
- movi a0, 0
- movi a1, 1
- wsr.windowstart a1
- wsr.windowbase a0
- rsync
- rsr.excsave1 a9 /* get pointer to context info */
- movi a0, 0 /* terminate call frames */
- l32i a1, a9, INFO_sp /* get stack pointer */
- l32i a10, a9, INFO_arg1 /* get start function's arguments... */
- l32i a8, a9, INFO_funcpc /* get start function's address */
- /* Okay, now switch back to context zero: */
- l32i a9, a9, INFO_prevps /* retrieve previous PS */
- wsr.ps a9
- rsync
- /* Back to original context! */
- abi_return
-
- .size _xtos_setup_context, . - _xtos_setup_context
-
-
-
- /*
- * This is the first thing to be executed in the new context
- * by explicit setting of PC:
- */
- .align 4
- .global _xtos_start_context
-_xtos_start_context:
-#ifdef __XTENSA_CALL0_ABI__
- Crash the assembler here: I think this is wrong.
- callx0 a8
-#else
- callx8 a8
-#endif
-1: nop
- j 1b /* do nothing until context 0 exits */
- .size _xtos_start_context, . - _xtos_start_context
-
-
-#endif /* XCHAL_NUM_CONTEXTS > 1 */
-
diff --git a/src/arch/xtensa/smp/xtos/xea2/window-vectors.S b/src/arch/xtensa/smp/xtos/xea2/window-vectors.S
deleted file mode 100644
index b6bd0f0..0000000
--- a/src/arch/xtensa/smp/xtos/xea2/window-vectors.S
+++ /dev/null
@@ -1,338 +0,0 @@
-// window-vectors-xea2.S - Register Window Overflow/Underflow Handlers for XEA2
-// $Id: //depot/rel/Foxhill/dot.8/Xtensa/OS/xtos/xea2/window-vectors.S#1 $
-
-// Copyright (c) 1999-2016 Tensilica Inc.
-//
-// Permission is hereby granted, free of charge, to any person obtaining
-// a copy of this software and associated documentation files (the
-// "Software"), to deal in the Software without restriction, including
-// without limitation the rights to use, copy, modify, merge, publish,
-// distribute, sublicense, and/or sell copies of the Software, and to
-// permit persons to whom the Software is furnished to do so, subject to
-// the following conditions:
-//
-// The above copyright notice and this permission notice shall be included
-// in all copies or substantial portions of the Software.
-//
-// THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
-// EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
-// MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
-// IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY
-// CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
-// TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
-// SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
-
-#include <xtensa/coreasm.h>
-#include <xtensa/xtruntime-frames.h>
-
-#if XCHAL_HAVE_XEA2 && XCHAL_HAVE_WINDOWED && !defined(__XTENSA_CALL0_ABI__)
-
-# ifndef NO_SECTION_DIRECTIVES
-// Exports
-.global _WindowOverflow4
-.global _WindowUnderflow4
-.global _WindowOverflow8
-.global _WindowUnderflow8
-.global _WindowOverflow12
-.global _WindowUnderflow12
-.global _xtos_alloca_handler
-
- // Note: the current window exception vectors do not generate any
- // literals. Hence the literal_prefix directive is not necessary.
- // Specifying it "just in case" creates an empty section (named
- // ".WindowVectors.literal") which can in some cases cause linking
- // problems (the linker scripts don't place it anywhere).
- // So leave it commented out:
- //
- //.begin literal_prefix .WindowVectors
-
- .section .WindowVectors.text, "ax"
-# endif
-
-
-//
-// GENERAL NOTES:
-//
-// These window exception handlers need not be modified.
-// They are specific to the windowed call ABI only.
-//
-// Underflow Handlers:
-//
-// The underflow handler for returning from call[i+1] to call[i]
-// must preserve all the registers from call[i+1]'s window.
-// In particular, a0 and a1 must be preserved because the RETW instruction
-// will be reexecuted (and may even underflow again if an intervening
-// exception has flushed call[i]'s registers).
-// Registers a2 and up may contain return values.
-//
-// The caller could also potentially assume that the callee's a0 and a1
-// (its own a4&a5 if call4, a8&a9 if call8, a12&a13 if call12)
-// are correct for whatever reason (not a clean thing to do in general,
-// but if it's possible, unless the ABI explicitly prohibits it,
-// it will eventually be done :) -- whether the the ABI needs to
-// prohibit this is a different question).
-//
-// Timing of Handlers:
-//
-// Here is an overview of the overhead of taking a window exception,
-// ie. the number of additional cycles taken relative to case where
-// an exception is not taken.
-// NOTE: these numbers do not take into account any cache misses,
-// write buffer stalls, or other external stalls, if they occur.
-// The totals consist of 5 cycles to enter the handler (or 6 or 7
-// for optional longer pipelines in Xtensa LX), the number of instructions
-// and interlocks (2nd and 3rd columns below), and 2 cycles jump delay
-// on return (3 cycles for optional longer I-side pipeline in Xtensa LX):
-//
-// Instruction+bubbles Totals (5-stage)
-// XEA1 XEA2 XEA1 XEA2
-// Overflow-4 7 5 14 12
-// Overflow-8 14 10 21 17
-// Overflow-12 18 14 25 21
-// Underflow-4 6 5 13 12
-// Underflow-8 14 10 21 17
-// Underflow-12 18 14 25 21
-//
-// Underflow-8 15 12 25 22 (7-stage; could be made 1 less)
-// Underflow-12 19 16 29 26 (7-stage; could be made 1 less)
-
-#ifndef WINDOW_BASE_VECOFS
-#define WINDOW_BASE_VECOFS XCHAL_WINDOW_OF4_VECOFS
-#endif
-
-
-// 4-Register Window Overflow Vector (Handler)
-//
-// Invoked if a call[i] referenced a register (a4-a15)
-// that contains data from ancestor call[j];
-// call[j] had done a call4 to call[j+1].
-// On entry here:
-// window rotated to call[j] start point;
-// a0-a3 are registers to be saved;
-// a4-a15 must be preserved;
-// a5 is call[j+1]'s stack pointer.
-
- .org XCHAL_WINDOW_OF4_VECOFS - WINDOW_BASE_VECOFS
-_WindowOverflow4:
- hw_erratum_487_fix
- s32e a0, a5, -16 // save a0 to call[j+1]'s stack frame
- s32e a1, a5, -12 // save a1 to call[j+1]'s stack frame
- s32e a2, a5, -8 // save a2 to call[j+1]'s stack frame
- s32e a3, a5, -4 // save a3 to call[j+1]'s stack frame
- rfwo // rotates back to call[i] position
-
- .size _WindowOverflow4, . - _WindowOverflow4
-
-
-// ALLOCA exception handler
-//
-// NOTE: The alloca exception handler is squeezed in between the window exception
-// handlers in order to save space, and also to allow short-range jumps to the
-// window underflow handlers (see below for why). Because of the limited space in
-// between the window handlers, this function is split into two to fit.
-//
-// Code written to the windowed ABI must use the MOVSP instruction to modify
-// the stack pointer (except for startup code, which doesn't have a caller).
-// The compiler uses MOVSP to allocate very large or variable size stack frames.
-// MOVSP guarantees that the caller frame's a0-a3 registers, stored below the
-// stack pointer, are moved atomically with respect to interrupts and exceptions
-// to satisfy windowed ABI requirements. When user code executes the MOVSP
-// instruction and the caller frame is on the stack rather than in the register
-// file, the processor takes an ALLOCA exception.
-//
-// The XTOS user exception dispatcher allocates an exception frame on the
-// stack and saves a2-a4 into that frame before calling us. So we need to
-// restore those registers and deallocate the stack frame before jumping
-// to the window underflow handler - which will restore the spilled registers
-// back into the register file.
-// The fact the alloca exception was taken means the registers associated with
-// the base-save area have been spilled and will be restored by the underflow
-// handler, so those 4 registers are available for scratch.
-
- .align 4
-
-_xtos_alloca_handler:
-
- l32i a2, a1, UEXC_a2 // restore a2-a4 and deallocate frame
- l32i a3, a1, UEXC_a3
- l32i a4, a1, UEXC_a4
- addi a1, a1, ESF_TOTALSIZE
- wsr.excsave1 a0 // save a0
- rsr.windowbase a0 // grab WINDOWBASE before rotw changes it
- rotw -1 // WINDOWBASE goes to a4, new a0-a3 are scratch
- rsr.ps a2
- extui a3, a2, XCHAL_PS_OWB_SHIFT, XCHAL_PS_OWB_BITS
- xor a3, a3, a4 // bits changed from old to current windowbase
- j _xtos_alloca_2 // not enough room here...
-
- .size _xtos_alloca_handler, . - _xtos_alloca_handler
-
-
-// 4-Register Window Underflow Vector (Handler)
-//
-// Invoked by RETW returning from call[i+1] to call[i]
-// where call[i]'s registers must be reloaded (not live in ARs);
-// call[i] had done a call4 to call[i+1].
-// On entry here:
-// window rotated to call[i] start point;
-// a0-a3 are undefined, must be reloaded with call[i].reg[0..3];
-// a4-a15 must be preserved (they are call[i+1].reg[0..11]);
-// a5 is call[i+1]'s stack pointer.
-
- .org XCHAL_WINDOW_UF4_VECOFS - WINDOW_BASE_VECOFS
-_WindowUnderflow4:
- l32e a0, a5, -16 // restore a0 from call[i+1]'s stack frame
- l32e a1, a5, -12 // restore a1 from call[i+1]'s stack frame
- l32e a2, a5, -8 // restore a2 from call[i+1]'s stack frame
- l32e a3, a5, -4 // restore a3 from call[i+1]'s stack frame
- rfwu
-
- .size _WindowUnderflow4, . - _WindowUnderflow4
-
-
-// This is the second part of the alloca handler.
-
- .align 4
-
-_xtos_alloca_2:
-
- rsr.excsave1 a4 // restore original a0 (now in a4)
- slli a3, a3, XCHAL_PS_OWB_SHIFT
- xor a2, a2, a3 // flip changed bits in old window base
- wsr.ps a2 // update PS.OWB to new window base
- rsync
- _bbci.l a4, 31, _WindowUnderflow4
- rotw -1 // original a0 goes to a8
- _bbci.l a8, 30, _WindowUnderflow8
- rotw -1
- j _WindowUnderflow12
-
- .size _xtos_alloca_2, . - _xtos_alloca_2
-
-
-// 8-Register Window Overflow Vector (Handler)
-//
-// Invoked if a call[i] referenced a register (a4-a15)
-// that contains data from ancestor call[j];
-// call[j] had done a call8 to call[j+1].
-// On entry here:
-// window rotated to call[j] start point;
-// a0-a7 are registers to be saved;
-// a8-a15 must be preserved;
-// a9 is call[j+1]'s stack pointer.
-
- .org XCHAL_WINDOW_OF8_VECOFS - WINDOW_BASE_VECOFS
-_WindowOverflow8:
- hw_erratum_487_fix
- s32e a0, a9, -16 // save a0 to call[j+1]'s stack frame
- l32e a0, a1, -12 // a0 <- call[j-1]'s sp (used to find end of call[j]'s frame)
- s32e a1, a9, -12 // save a1 to call[j+1]'s stack frame
- s32e a2, a9, -8 // save a2 to call[j+1]'s stack frame
- s32e a3, a9, -4 // save a3 to call[j+1]'s stack frame
- s32e a4, a0, -32 // save a4 to call[j]'s stack frame
- s32e a5, a0, -28 // save a5 to call[j]'s stack frame
- s32e a6, a0, -24 // save a6 to call[j]'s stack frame
- s32e a7, a0, -20 // save a7 to call[j]'s stack frame
- rfwo // rotates back to call[i] position
-
- .size _WindowOverflow8, . - _WindowOverflow8
-
-
-// 8-Register Window Underflow Vector (Handler)
-//
-// Invoked by RETW returning from call[i+1] to call[i]
-// where call[i]'s registers must be reloaded (not live in ARs);
-// call[i] had done a call8 to call[i+1].
-// On entry here:
-// window rotated to call[i] start point;
-// a0-a7 are undefined, must be reloaded with call[i].reg[0..7];
-// a8-a15 must be preserved (they are call[i+1].reg[0..7]);
-// a9 is call[i+1]'s stack pointer.
-
- .org XCHAL_WINDOW_UF8_VECOFS - WINDOW_BASE_VECOFS
-_WindowUnderflow8:
- l32e a0, a9, -16 // restore a0 from call[i+1]'s stack frame
- l32e a1, a9, -12 // restore a1 from call[i+1]'s stack frame
- l32e a2, a9, -8 // restore a2 from call[i+1]'s stack frame
- l32e a7, a1, -12 // a7 <- call[i-1]'s sp (used to find end of call[i]'s frame)
- l32e a3, a9, -4 // restore a3 from call[i+1]'s stack frame
- l32e a4, a7, -32 // restore a4 from call[i]'s stack frame
- l32e a5, a7, -28 // restore a5 from call[i]'s stack frame
- l32e a6, a7, -24 // restore a6 from call[i]'s stack frame
- l32e a7, a7, -20 // restore a7 from call[i]'s stack frame
- rfwu
-
- .size _WindowUnderflow8, . - _WindowUnderflow8
-
-
-// 12-Register Window Overflow Vector (Handler)
-//
-// Invoked if a call[i] referenced a register (a4-a15)
-// that contains data from ancestor call[j];
-// call[j] had done a call12 to call[j+1].
-// On entry here:
-// window rotated to call[j] start point;
-// a0-a11 are registers to be saved;
-// a12-a15 must be preserved;
-// a13 is call[j+1]'s stack pointer.
-
- .org XCHAL_WINDOW_OF12_VECOFS - WINDOW_BASE_VECOFS
-_WindowOverflow12:
- hw_erratum_487_fix
- s32e a0, a13, -16 // save a0 to call[j+1]'s stack frame
- l32e a0, a1, -12 // a0 <- call[j-1]'s sp (used to find end of call[j]'s frame)
- s32e a1, a13, -12 // save a1 to call[j+1]'s stack frame
- s32e a2, a13, -8 // save a2 to call[j+1]'s stack frame
- s32e a3, a13, -4 // save a3 to call[j+1]'s stack frame
- s32e a4, a0, -48 // save a4 to end of call[j]'s stack frame
- s32e a5, a0, -44 // save a5 to end of call[j]'s stack frame
- s32e a6, a0, -40 // save a6 to end of call[j]'s stack frame
- s32e a7, a0, -36 // save a7 to end of call[j]'s stack frame
- s32e a8, a0, -32 // save a8 to end of call[j]'s stack frame
- s32e a9, a0, -28 // save a9 to end of call[j]'s stack frame
- s32e a10, a0, -24 // save a10 to end of call[j]'s stack frame
- s32e a11, a0, -20 // save a11 to end of call[j]'s stack frame
- rfwo // rotates back to call[i] position
-
- .size _WindowOverflow12, . - _WindowOverflow12
-
-
-// 12-Register Window Underflow Vector (Handler)
-//
-// Invoked by RETW returning from call[i+1] to call[i]
-// where call[i]'s registers must be reloaded (not live in ARs);
-// call[i] had done a call12 to call[i+1].
-// On entry here:
-// window rotated to call[i] start point;
-// a0-a11 are undefined, must be reloaded with call[i].reg[0..11];
-// a12-a15 must be preserved (they are call[i+1].reg[0..3]);
-// a13 is call[i+1]'s stack pointer.
-
- .org XCHAL_WINDOW_UF12_VECOFS - WINDOW_BASE_VECOFS
-_WindowUnderflow12:
- l32e a0, a13, -16 // restore a0 from call[i+1]'s stack frame
- l32e a1, a13, -12 // restore a1 from call[i+1]'s stack frame
- l32e a2, a13, -8 // restore a2 from call[i+1]'s stack frame
- l32e a11, a1, -12 // a11 <- call[i-1]'s sp (used to find end of call[i]'s frame)
- l32e a3, a13, -4 // restore a3 from call[i+1]'s stack frame
- l32e a4, a11, -48 // restore a4 from end of call[i]'s stack frame
- l32e a5, a11, -44 // restore a5 from end of call[i]'s stack frame
- l32e a6, a11, -40 // restore a6 from end of call[i]'s stack frame
- l32e a7, a11, -36 // restore a7 from end of call[i]'s stack frame
- l32e a8, a11, -32 // restore a8 from end of call[i]'s stack frame
- l32e a9, a11, -28 // restore a9 from end of call[i]'s stack frame
- l32e a10, a11, -24 // restore a10 from end of call[i]'s stack frame
- l32e a11, a11, -20 // restore a11 from end of call[i]'s stack frame
- rfwu
-
- .size _WindowUnderflow12, . - _WindowUnderflow12
-
-
-# ifndef NO_SECTION_DIRECTIVES
- //.end literal_prefix
- .text
-# endif
-
-
-#endif /* XCHAL_HAVE_XEA2 && XCHAL_HAVE_WINDOWED && !defined(__XTENSA_CALL0_ABI__) */
-
diff --git a/src/arch/xtensa/smp/xtos/xtos-internal.h b/src/arch/xtensa/smp/xtos/xtos-internal.h
deleted file mode 100644
index 8d5b765..0000000
--- a/src/arch/xtensa/smp/xtos/xtos-internal.h
+++ /dev/null
@@ -1,524 +0,0 @@
-/*
- * xtos-internal.h -- internal definitions for single-threaded run-time
- *
- * Copyright (c) 2003-2010 Tensilica Inc.
- *
- * Permission is hereby granted, free of charge, to any person obtaining
- * a copy of this software and associated documentation files (the
- * "Software"), to deal in the Software without restriction, including
- * without limitation the rights to use, copy, modify, merge, publish,
- * distribute, sublicense, and/or sell copies of the Software, and to
- * permit persons to whom the Software is furnished to do so, subject to
- * the following conditions:
- *
- * The above copyright notice and this permission notice shall be included
- * in all copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
- * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
- * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
- * IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY
- * CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
- * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
- * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
- */
-
-#ifndef XTOS_INTERNAL_H
-#define XTOS_INTERNAL_H
-
-#include <xtensa/config/core.h>
-#include <xtensa/xtruntime.h>
-#include <xtensa/xtruntime-frames.h>
-#include <xtensa/xtensa-versions.h>
-#include <platform/platcfg.h>
-#ifndef XTOS_PARAMS_H /* this to allow indirect inclusion of this header from the outside */
-#include "xtos-params.h"
-#endif
-
-/* Relative ordering of subpriorities within an interrupt level (or vector): */
-#define XTOS_SPO_ZERO_LO 0 /* lower (eg. zero) numbered interrupts are lower priority than higher numbered interrupts */
-#define XTOS_SPO_ZERO_HI 1 /* lower (eg. zero) numbered interrupts are higher priority than higher numbered interrupts */
-
-
-/* Sanity check some parameters from xtos-params.h: */
-#if XTOS_LOCKLEVEL < XCHAL_EXCM_LEVEL || XTOS_LOCKLEVEL > 15
-# error Invalid XTOS_LOCKLEVEL value, must be >= EXCM_LEVEL and <= 15, please fix xtos-params.h
-#endif
-
-/* Mask of interrupts locked out at XTOS_LOCKLEVEL: */
-#define XTOS_LOCKOUT_MASK XCHAL_INTLEVEL_ANDBELOW_MASK(XTOS_LOCKLEVEL)
-/* Mask of interrupts that can still be enabled at XTOS_LOCKLEVEL: */
-#define XTOS_UNLOCKABLE_MASK (0xFFFFFFFF-XTOS_LOCKOUT_MASK)
-
-/* Don't set this: */
-#define XTOS_HIGHINT_TRAMP 0 /* mapping high-pri ints to low-pri not auto-supported */
-#define XTOS_VIRTUAL_INTERRUPT XTOS_HIGHINT_TRAMP /* partially-virtualized INTERRUPT register not currently supported */
-#if XTOS_HIGHINT_TRAMP
-# error Automatically-generated high-level interrupt trampolines are not presently supported.
-#endif
-
-/*
- * If single interrupt at level-one, sub-prioritization is irrelevant:
- */
-#if defined(XCHAL_INTLEVEL1_NUM)
-# undef XTOS_SUBPRI
-# define XTOS_SUBPRI 0 /* override - only one interrupt */
-#endif
-
-/*
- * In XEA1, the INTENABLE special register must be virtualized to provide
- * standard XTOS functionality.
- * In XEA2, this is only needed for software interrupt prioritization.
- */
-#if XTOS_SUBPRI || XCHAL_HAVE_XEA1
-#define XTOS_VIRTUAL_INTENABLE 1
-#else
-#define XTOS_VIRTUAL_INTENABLE 0
-#endif
-
-/*
- * If single interrupt per priority, then fairness is irrelevant:
- */
-#if (XTOS_SUBPRI && !XTOS_SUBPRI_GROUPS) || defined(XCHAL_INTLEVEL1_NUM)
-# undef XTOS_INT_FAIRNESS
-# define XTOS_INT_FAIRNESS 0
-#endif
-
-/* Identify special case interrupt handling code in int-lowpri-dispatcher.S: */
-#define XTOS_INT_SPECIALCASE (XTOS_SUBPRI_ORDER == XTOS_SPO_ZERO_HI && XTOS_INT_FAIRNESS == 0 && XTOS_SUBPRI_GROUPS == 0)
-
-/*
- * Determine whether to extend the interrupt entry array:
- */
-#define XIE_EXTEND (XTOS_VIRTUAL_INTENABLE && !XTOS_INT_SPECIALCASE)
-
-/* If we have the NSAU instruction, ordering of interrupts is reversed in xtos_interrupt_table[]: */
-#if XCHAL_HAVE_NSA
-# define MAPINT(n) ((XCHAL_NUM_INTERRUPTS-1)-(n))
-# ifdef _ASMLANGUAGE
- .macro mapint an
- neg \an, \an
- addi \an, \an, XCHAL_NUM_INTERRUPTS-1
- .endm
-# endif
-#else /* no NSA */
-# define MAPINT(n) (n)
-# ifdef _ASMLANGUAGE
- .macro mapint an
- .endm
-# endif
-#endif
-
-
-#if defined(_ASMLANGUAGE) || defined(__ASSEMBLER__)
-/*********** Useful macros ***********/
-
-/*
- * A useful looping macro:
- * 'iterate' invokes 'what' (an instruction, pseudo-op or other macro)
- * multiple times, passing it a numbered parameter from 'from' to 'to'
- * inclusively. Does not invoke 'what' at all if from > to.
- * Maximum difference between 'from' and 'to' is 99 minus nesting depth
- * (GNU 'as' doesn't allow nesting deeper than 100).
- */
- .macro iterate from, to, what
- .ifeq ((\to-\from) & ~0xFFF)
- \what \from
- iterate "(\from+1)", \to, \what
- .endif
- .endm // iterate
-
-
-
- // rsilft
- //
- // Execute RSIL \ar, \tolevel if \tolevel is different than \fromlevel.
- // This way the RSIL is avoided if we know at assembly time that
- // it will not change the level. Typically, this means the \ar register
- // is ignored, ie. RSIL is used only to change PS.INTLEVEL.
- //
- .macro rsilft ar, fromlevel, tolevel
-#if XCHAL_HAVE_INTERRUPTS
- .if \fromlevel - \tolevel
- rsil \ar, \tolevel
- .endif
-#endif
- .endm
-
-
- // Save LOOP and MAC16 registers, if configured, to the exception stack
- // frame pointed to by address register \esf, using \aa and \ab as temporaries.
- //
- // This macro essentially saves optional registers that the compiler uses by
- // default when present.
- // Note that the acclo/acchi subset of MAC16 may be used even if others
- // multipliers are present (e.g. mul16, mul32).
- //
- // Only two temp registers required for this code to be optimal (no interlocks) in both
- // T10xx (Athens) and Xtensa LX microarchitectures (both 5 and 7 stage pipes):
- //
- .macro save_loops_mac16 esf, aa, ab
-#if XCHAL_HAVE_LOOPS
- rsr.lcount \aa
- rsr.lbeg \ab
- s32i \aa, \esf, UEXC_lcount
- rsr.lend \aa
- s32i \ab, \esf, UEXC_lbeg
- s32i \aa, \esf, UEXC_lend
-#endif
-#if XCHAL_HAVE_MAC16
- rsr.acclo \aa
- rsr.acchi \ab
- s32i \aa, \esf, UEXC_acclo
- s32i \ab, \esf, UEXC_acchi
-# if XTOS_SAVE_ALL_MAC16
- rsr.m0 \aa
- rsr.m1 \ab
- s32i \aa, \esf, UEXC_mr + 0
- s32i \ab, \esf, UEXC_mr + 4
- rsr.m2 \aa
- rsr.m3 \ab
- s32i \aa, \esf, UEXC_mr + 8
- s32i \ab, \esf, UEXC_mr + 12
-# endif
-#endif
- .endm
-
- // Restore LOOP and MAC16 registers, if configured, from the exception stack
- // frame pointed to by address register \esf, using \aa, \ab and \ac as temporaries.
- //
- // Three temp registers are required for this code to be optimal (no interlocks) in
- // Xtensa LX microarchitectures with 7-stage pipe; otherwise only two
- // registers would be needed.
- //
- .macro restore_loops_mac16 esf, aa, ab, ac
-#if XCHAL_HAVE_LOOPS
- l32i \aa, \esf, UEXC_lcount
- l32i \ab, \esf, UEXC_lbeg
- l32i \ac, \esf, UEXC_lend
- wsr.lcount \aa
- wsr.lbeg \ab
- wsr.lend \ac
-#endif
-#if XCHAL_HAVE_MAC16
- l32i \aa, \esf, UEXC_acclo
- l32i \ab, \esf, UEXC_acchi
-# if XTOS_SAVE_ALL_MAC16
- l32i \ac, \esf, UEXC_mr + 0
- wsr.acclo \aa
- wsr.acchi \ab
- wsr.m0 \ac
- l32i \aa, \esf, UEXC_mr + 4
- l32i \ab, \esf, UEXC_mr + 8
- l32i \ac, \esf, UEXC_mr + 12
- wsr.m1 \aa
- wsr.m2 \ab
- wsr.m3 \ac
-# else
- wsr.acclo \aa
- wsr.acchi \ab
-# endif
-#endif
- .endm
-
-
-/* Offsets from _xtos_intstruct structure: */
- .struct 0
-#if XTOS_VIRTUAL_INTENABLE
-XTOS_ENABLED_OFS: .space 4 /* _xtos_enabled variable */
-XTOS_VPRI_ENABLED_OFS: .space 4 /* _xtos_vpri_enabled variable */
-#endif
-#if XTOS_VIRTUAL_INTERRUPT
-XTOS_PENDING_OFS: .space 4 /* _xtos_pending variable */
-#endif
- .text
-
-
-#if XTOS_VIRTUAL_INTENABLE
- // Update INTENABLE register, computing it as follows:
- // INTENABLE = _xtos_enabled & _xtos_vpri_enabled
- // [ & ~_xtos_pending ]
- //
- // Entry:
- // register ax = &_xtos_intstruct
- // register ay, az undefined (temporaries)
- // PS.INTLEVEL set to XTOS_LOCKLEVEL or higher (eg. via xtos_lock)
- // window overflows prevented (PS.WOE=0, PS.EXCM=1, or overflows
- // already done for registers ax, ay, az)
- //
- // Exit:
- // registers ax, ay, az clobbered
- // PS unchanged
- // caller needs to SYNC (?) for INTENABLE changes to take effect
- //
- // Note: in other software prioritization schemes/implementations,
- // the term <_xtos_vpri_enabled> in the above expression is often
- // replaced with another expression that computes the set of
- // interrupts allowed to be enabled at the current software virtualized
- // interrupt priority.
- //
- // For example, a simple alternative implementation of software
- // prioritization for XTOS might have been the following:
- // INTENABLE = _xtos_enabled & (vpri_enabled | UNLOCKABLE_MASK)
- // which removes the need for the interrupt dispatcher to 'or' the
- // UNLOCKABLE_MASK bits into _xtos_vpri_enabled, and lets other code
- // disable all lockout level interrupts by just clearing _xtos_vpri_enabled
- // rather than setting it to UNLOCKABLE_MASK.
- // Other implementations sometimes use a table, eg:
- // INTENABLE = _xtos_enabled & enable_table[current_vpri]
- // The HAL (used by some 3rd party OSes) uses essentially a table-driven
- // version, with other tables enabling run-time changing of priorities.
- //
- .macro xtos_update_intenable ax, ay, az
- //movi \ax, _xtos_intstruct
- l32i \ay, \ax, XTOS_VPRI_ENABLED_OFS // ay = _xtos_vpri_enabled
- l32i \az, \ax, XTOS_ENABLED_OFS // az = _xtos_enabled
- //interlock
- and \az, \az, \ay // az = _xtos_enabled & _xtos_vpri_enabled
-# if XTOS_VIRTUAL_INTERRUPT
- l32i \ay, \ax, XTOS_PENDING_OFS // ay = _xtos_pending
- movi \ax, -1
- xor \ay, \ay, \ax // ay = ~_xtos_pending
- and \az, \az, \ay // az &= ~_xtos_pending
-# endif
- wsr.intenable \az
- .endm
-#endif /* VIRTUAL_INTENABLE */
-
- .macro xtos_lock ax
- rsil \ax, XTOS_LOCKLEVEL // lockout
- .endm
-
- .macro xtos_unlock ax
- wsr.ps \ax // unlock
- rsync
- .endm
-
-/* Offsets to XtosIntHandlerEntry structure fields (see below): */
-# define XIE_HANDLER 0
-# define XIE_ARG 4
-# define XIE_SIZE 8
-# if XIE_EXTEND
-# define XIE_VPRIMASK (XIE_SIZE*XCHAL_NUM_INTERRUPTS+0) /* if VIRTUAL_INTENABLE [SUBPRI||XEA1] && !SPECIALCASE */
-# define XIE_LEVELMASK (XIE_SIZE*XCHAL_NUM_INTERRUPTS+4) /* [fairness preloop] if FAIRNESS && SUBPRI [&& SUBPRI_GROUPS] */
-# endif
-
-/* To simplify code: */
-# if XCHAL_HAVE_NSA
-# define IFNSA(a,b) a
-# else
-# define IFNSA(a,b) b
-# endif
-
-
- // get_prid ax
- // Extracts core id.
- .macro get_prid ax
-#if XCHAL_HAVE_PRID
- rsr.prid \ax
- extui \ax, \ax, 0, 8
-#else
- movi \ax, PLATFORM_MASTER_CORE_ID
-#endif
- .endm
-
- // xtos_stack_addr_percore_basic ax, ay, stack_name, stack_size
- // Retrieves address of end of stack buffer for certain core to register ax.
- .macro xtos_stack_addr_percore_basic ax, ay, stack_name, stack_size
- get_prid \ax
- addi \ax, \ax, 1
- movi \ay, \stack_size
- mull \ax, \ax, \ay
- movi \ay, \stack_name
- add \ax, \ax, \ay
- .endm
-
- // xtos_stack_addr_percore ax, int_level, stack_name
- // Pointer to dedicated interrupt stack.
- .macro xtos_stack_addr_percore ax, int_level, stack_name
-#if XCHAL_HAVE_THREADPTR
- rur.threadptr \ax
- l32i \ax, \ax, XTOS_PTR_TO_\stack_name\()_&int_level
-#else
-#error "This architecture requires core support for XCHAL_HAVE_THREADPTR"
-#endif
- .endm
-
- // xtos_stack_addr_percore_add ax, stack_name, offset
- // Pointer to dedicated interrupt stack + offset.
- .macro xtos_stack_addr_percore_add ax, stack_name, offset
- get_prid \ax
- beqz \ax, core_0
- beqi \ax, 1, core_1
- beqi \ax, 2, core_2
- beqi \ax, 3, core_3
- j exit
-core_0:
- movi \ax, \stack_name\()0 + (\offset)
- j exit
-core_1:
- movi \ax, \stack_name\()1 + (\offset)
- j exit
-core_2:
- movi \ax, \stack_name\()2 + (\offset)
- j exit
-core_3:
- movi \ax, \stack_name\()3 + (\offset)
- j exit
-exit:
- .endm
-
- // xtos_addr_percore ax, structure_name
- // Pointer to structure per core.
- .macro xtos_addr_percore ax, structure_name
-#if XCHAL_HAVE_THREADPTR
- rur.threadptr \ax
- l32i \ax, \ax, XTOS_PTR_TO_\structure_name
-#else
-#error "This architecture requires core support for XCHAL_HAVE_THREADPTR"
-#endif
- .endm
-
- // xtos_addr_percore_add ax, symbol, offset
- // Pointer to structure per core + offset.
- .macro xtos_addr_percore_add ax, symbol, offset
- xtos_addr_percore \ax, \symbol
- addi \ax, \ax, \offset
- .endm
-
- // xtos_addr_percore_sub ax, symbol, offset
- // Pointer to structure per core - offset.
- .macro xtos_addr_percore_sub ax, symbol, offset
- xtos_addr_percore \ax, \symbol
- addi \ax, \ax, -\offset
- .endm
-
-#else /* !_ASMLANGUAGE && !__ASSEMBLER__ */
-
-/*
- * Interrupt handler table entry.
- * Unregistered entries have 'handler' point to xtos_unhandled_interrupt().
- */
-typedef struct XtosIntHandlerEntry {
- _xtos_handler handler;
- union {
- void * varg;
- int narg;
- } u;
-} XtosIntHandlerEntry;
-# if XIE_EXTEND
-typedef struct XtosIntMaskEntry {
- unsigned vpri_mask; /* mask of interrupts enabled when this interrupt is taken */
- unsigned level_mask; /* mask of interrupts at this interrupt's level */
-} XtosIntMaskEntry;
-# endif
-
-struct XtosIntStruct
-{
- unsigned xtos_enabled;
- unsigned vpri_enabled;
-};
-
-// XtosIntInterruptTable holds array of interrupt handler descriptors.
-struct XtosIntInterruptTable
-{
- struct XtosIntHandlerEntry array[XCHAL_NUM_INTERRUPTS];
-};
-
-// XtosInterruptStructure describes layout of xtos interrupt structures per core
-// generated for certain platform in file interrupt-table.S.
-struct XtosInterruptStructure
-{
- struct XtosIntStruct xtos_enabled;
- struct XtosIntInterruptTable xtos_interrupt_table;
- struct XtosIntMaskEntry xtos_interrupt_mask_table[XCHAL_NUM_INTERRUPTS];
- __attribute__((aligned(XCHAL_DCACHE_LINESIZE))) int al[0];
-};
-
-extern void xtos_unhandled_interrupt();
-
-#endif /* !_ASMLANGUAGE && !__ASSEMBLER__ */
-
-/*
- * Notes...
- *
- * XEA1 and interrupt-SUBPRIoritization both imply virtualization of INTENABLE.
- * Synchronous trampoloines imply partial virtualization of the INTERRUPT
- * register, which in turn also implies virtualization of INTENABLE register.
- * High-level interrupts manipulating the set of enabled interrupts implies
- * at least a high XTOS_LOCK_LEVEL, although not necessarily INTENABLE virtualization.
- *
- * With INTENABLE register virtualization, at all times the INTENABLE
- * register reflects the expression:
- * (set of interrupts enabled) & (set of interrupts enabled by current
- * virtual priority)
- *
- * Unrelated (DBREAK semantics):
- *
- * A[31-6] = DBA[3-6]
- * ---------------------
- * A[5-0] & DBC[5-C] & szmask
- *
- * = DBA[5-0] & szmask
- * ^___ ???
- */
-
-
-/* Report whether the XSR instruction is available (conservative): */
-#define HAVE_XSR (XCHAL_HAVE_XEA2 || !XCHAL_HAVE_EXCEPTIONS)
-/*
- * This is more accurate, but not a reliable test in software releases prior to 6.0
- * (where the targeted hardware parameter was not explicit in the XPG):
- *
- *#define HAVE_XSR (XCHAL_HW_MIN_VERSION >= XTENSA_HWVERSION_T1040_0)
- */
-
-
-
-/* Macros for supporting hi-level and medium-level interrupt handling. */
-
-#if XCHAL_NUM_INTLEVELS > 6
-#error Template files (*-template.S) limit support to interrupt levels <= 6
-#endif
-
-#if defined(__XTENSA_WINDOWED_ABI__) && XCHAL_HAVE_CALL4AND12 == 0
-#error CALL8-only is not supported!
-#endif
-
-#define INTERRUPT_IS_HI(level) \
- ( XCHAL_HAVE_INTERRUPTS && \
- (XCHAL_EXCM_LEVEL < level) && \
- (XCHAL_NUM_INTLEVELS >= level) && \
- (XCHAL_HAVE_DEBUG ? XCHAL_DEBUGLEVEL != level : 1))
-
-#define INTERRUPT_IS_MED(level) \
- (XCHAL_HAVE_INTERRUPTS && (XCHAL_EXCM_LEVEL >= level))
-
-
-#define _JOIN(x,y) x ## y
-#define JOIN(x,y) _JOIN(x,y)
-
-#define _JOIN3(a,b,c) a ## b ## c
-#define JOIN3(a,b,c) _JOIN3(a,b,c)
-
-#define LABEL(x,y) JOIN3(x,_INTERRUPT_LEVEL,y)
-#define EXCSAVE_LEVEL JOIN(EXCSAVE_,_INTERRUPT_LEVEL)
-#define INTLEVEL_VSIZE JOIN3(XSHAL_INTLEVEL,_INTERRUPT_LEVEL,_VECTOR_SIZE)
-
-/* For asm macros; works for positive a,b smaller than 1000: */
-#define GREATERTHAN(a, b) (((b) - (a)) & ~0xFFF)
-#define EQUAL(a, b) ((1 << (a)) & (1 << (b)))
-
-#define XTOS_INT_STACK_SIZE 4096
-#define XTOS_IDLE_STACK_SIZE 4096
-
-// sizeof(xtos_enabled)
-#define XTOS_ENABLED_SIZE_PER_CORE (4)
-// sizeof(vpri_enabled)
-#define XTOS_VPRI_ENABLED_SIZE_PER_CORE (4)
-// sizeof(XtosIntStruct)
-#define XTOS_INTSTRUCT_SIZE_PER_CORE (XTOS_ENABLED_SIZE_PER_CORE + \
- XTOS_VPRI_ENABLED_SIZE_PER_CORE)
-
-#endif /* XTOS_INTERNAL_H */
-
diff --git a/src/arch/xtensa/smp/xtos/xtos-params.h b/src/arch/xtensa/smp/xtos/xtos-params.h
deleted file mode 100644
index 334aba7..0000000
--- a/src/arch/xtensa/smp/xtos/xtos-params.h
+++ /dev/null
@@ -1,123 +0,0 @@
-/*
- * xtos-params.h -- user-settable parameters for XTOS single-threaded run-time
- *
- * Copyright (c) 2002, 2004, 2006-2007 Tensilica Inc.
- *
- * Permission is hereby granted, free of charge, to any person obtaining
- * a copy of this software and associated documentation files (the
- * "Software"), to deal in the Software without restriction, including
- * without limitation the rights to use, copy, modify, merge, publish,
- * distribute, sublicense, and/or sell copies of the Software, and to
- * permit persons to whom the Software is furnished to do so, subject to
- * the following conditions:
- *
- * The above copyright notice and this permission notice shall be included
- * in all copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
- * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
- * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
- * IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY
- * CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
- * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
- * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
- */
-
-#ifndef XTOS_PARAMS_H
-#define XTOS_PARAMS_H
-
-/*
- * IMPORTANT NOTE.
- * This file contains XTOS parameters that may be modified
- * according to needs. HOWEVER, any modifications are NOT
- * supported. Handling of parameters other than the defaults
- * provided in the original version of this file are for
- * illustrative and educational purposes only. If you do
- * change the parameters here-in (which requires rebuilding
- * XTOS), please verify the resulting code extensively
- * before even considering its use in production code.
- *
- * To rebuild XTOS, see instructions in the Xtensa System Software
- * Reference Manual. The following sequence is no longer supported.
- *
- * cd <config_dir>/xtensa-elf/src/handlers
- * xt-make clean
- * xt-make
- * xt-make install
- *
- * (Note: the last step installs the modified XTOS in *ALL*
- * LSPs that normally include XTOS. You may prefer copying
- * the generated files to your own custom LSP instead. Or
- * better yet, also make a copy of all source files and maintain
- * them somewhere completely separate -- which may require
- * minor adjustments to the makefile.)
- *
- * PERFORMANCE TUNING:
- * To slightly improve performance of interrupt dispatching,
- * you can do some combination of the following:
- * - change XTOS_SUBPRI to zero
- * - change XTOS_SUBPRI_GROUPS to zero
- * - change XTOS_SUBPRI_ORDER to XTOS_SPO_ZERO_HI
- * - change XTOS_DEBUG_PC to zero
- * - change XTOS_INT_FAIRNESS to zero
- * - change XTOS_CNEST to zero
- * There are non-trivial trade-offs in making such changes however,
- * such as loss of support (see important note above), loss of
- * interrupt scheduling fairness, loss of ability to traceback
- * interrupt handlers across interrupted code when debugging them,
- * loss of supported for nested C functions, etc.
- */
-
-
-/*
- * Lower LOCKLEVEL to XCHAL_EXCM_LEVEL for improved interrupt latency
- * if you don't register C handlers for high-priority interrupts and your
- * high-priority handlers don't touch INTENABLE nor virtual priorities.
- *
- * XTOS_LOCKLEVEL is less meaningful but still relevant if XEA2 and SUBPRI is zero,
- * ie. if INTENABLE doesn't get virtualized (XTOS_VIRTUAL_INTENABLE not set);
- * in this case, it is the interrupt level at which INTENABLE accesses are guarded,
- * so that interrupt handlers up to this level can safely manipulate INTENABLE.
- */
-#define XTOS_LOCKLEVEL XCHAL_NUM_INTLEVELS /* intlevel of INTENABLE register virtualization
- (minimum is EXCM_LEVEL) */
-
-/*
- * NOTE: the following four parameters (SUBPRI, SUBPRI_GROUPS, SUBPRI_ORDER, INT_FAIRNESS)
- * are irrelevant and ignored for interrupt vectors to which only one interrupt is mapped.
- */
-
-#define XTOS_SUBPRI 1 /* set to 0 if you don't need sub-prioritization
- within level-one interrupts via software;
- for XEA2 configs, this might improve performance of
- certain sections of code, because INTENABLE register
- virtualization becomes unnecessary in this case */
-
-/* Ignored unless SUBPRI set: */
-#define XTOS_SUBPRI_GROUPS 1 /* 1 = support selective grouping of interrupts at the same priority */
-
-#define XTOS_SUBPRI_ORDER XTOS_SPO_ZERO_LO /* one of XTOS_SPO_ZERO_LO, XTOS_SPO_ZERO_HI */
-
-/* Ignored if SUBPRI set but SUBPRI_GROUPS is not (single interrupt per subpri),
- * or if single interrupt configured at level/vector: */
-#define XTOS_INT_FAIRNESS 1 /* 1 = enable round-robin/fifo scheduling of interrupt
- handlers of a given level or sub-priority */
-
-
-#define XTOS_DEBUG_PC 1 /* 1 = enable nice stack traceback showing interrupted code
- when debugging interrupt or exception handler;
- not implemented for high-priority handlers, or
- for call0 ABI */
-
-#define XTOS_CNEST 1 /* 1 = enable support for nested C functions
- (save/restore nested C function call-chain pointer) */
-
-/* Current compilers only use ACC (not MRn) when MAC16 is enabled, so you can leave this 0 for performance: */
-#define XTOS_SAVE_ALL_MAC16 0 /* set to save/restore MAC16 MRn registers */
-
-/* Setting this might be useful to clear X's in hardware simulation a bit earlier, but
- * should not be needed in production code: */
-#define XTOS_RESET_UNNEEDED 0 /* set to reset more registers than are really needed */
-
-#endif /* XTOS_PARAMS_H */
-
diff --git a/src/arch/xtensa/smp/xtos/xtos-structs.h b/src/arch/xtensa/smp/xtos/xtos-structs.h
deleted file mode 100644
index 11d49e0..0000000
--- a/src/arch/xtensa/smp/xtos/xtos-structs.h
+++ /dev/null
@@ -1,65 +0,0 @@
-/*
- * Copyright (c) 2018, Intel Corporation
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- * * Redistributions of source code must retain the above copyright
- * notice, this list of conditions and the following disclaimer.
- * * Redistributions in binary form must reproduce the above copyright
- * notice, this list of conditions and the following disclaimer in the
- * documentation and/or other materials provided with the distribution.
- * * Neither the name of the Intel Corporation nor the
- * names of its contributors may be used to endorse or promote products
- * derived from this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
- * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
- * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
- * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
- * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
- * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
- * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
- * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
- * POSSIBILITY OF SUCH DAMAGE.
- *
- * Author: Tomasz Lauda <tomasz.lauda@linux.intel.com>
- */
-
-#include "xtos-internal.h"
-
-#ifndef __XTOS_STRUCTS_H__
-#define __XTOS_STRUCTS_H__
-
-struct idc;
-struct irq_task;
-struct schedule_data;
-
-struct thread_data {
- xtos_structures_pointers xtos_ptrs;
-};
-
-struct xtos_core_data {
- struct XtosInterruptStructure xtos_int_data;
- int xtos_stack_for_interrupt_2[XTOS_INT_STACK_SIZE / 4];
- int xtos_stack_for_interrupt_3[XTOS_INT_STACK_SIZE / 4];
- int xtos_stack_for_interrupt_4[XTOS_INT_STACK_SIZE / 4];
- int xtos_stack_for_interrupt_5[XTOS_INT_STACK_SIZE / 4];
-
- struct thread_data *thread_data_ptr;
-};
-
-struct core_context {
- struct thread_data td;
- struct irq_task *irq_low_task;
- struct irq_task *irq_med_task;
- struct irq_task *irq_high_task;
- struct schedule_data *sch;
- struct idc *idc;
-};
-
-void _xtos_initialize_pointers_per_core(void);
-
-#endif /* __XTOS_STRUCTS_H__ */
diff --git a/src/arch/xtensa/timer.c b/src/arch/xtensa/timer.c
deleted file mode 100644
index 3b499b1..0000000
--- a/src/arch/xtensa/timer.c
+++ /dev/null
@@ -1,231 +0,0 @@
-/*
- * Copyright (c) 2016, Intel Corporation
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- * * Redistributions of source code must retain the above copyright
- * notice, this list of conditions and the following disclaimer.
- * * Redistributions in binary form must reproduce the above copyright
- * notice, this list of conditions and the following disclaimer in the
- * documentation and/or other materials provided with the distribution.
- * * Neither the name of the Intel Corporation nor the
- * names of its contributors may be used to endorse or promote products
- * derived from this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
- * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
- * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
- * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
- * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
- * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
- * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
- * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
- * POSSIBILITY OF SUCH DAMAGE.
- *
- * Author: Liam Girdwood <liam.r.girdwood@linux.intel.com>
- */
-
-#include <xtensa/xtruntime.h>
-#include <xtensa/hal.h>
-#include <arch/timer.h>
-#include <platform/memory.h>
-#include <platform/interrupt.h>
-#include <platform/timer.h>
-#include <sof/mailbox.h>
-#include <sof/debug.h>
-#include <sof/timer.h>
-#include <sof/interrupt.h>
-#include <stdint.h>
-#include <errno.h>
-
-struct timer_data {
- void (*handler2)(void *arg);
- void *arg2;
-};
-
-static struct timer_data xtimer[3] = {};
-
-void timer_64_handler(void *arg)
-{
- struct timer *timer = arg;
- struct timer_data *tdata = timer->timer_data;
- uint32_t ccompare;
-
- /* get comparator value - will tell us timeout reason */
- switch (timer->id) {
- case TIMER0:
- ccompare = xthal_get_ccompare(0);
- break;
- case TIMER1:
- ccompare = xthal_get_ccompare(1);
- break;
- case TIMER2:
- ccompare = xthal_get_ccompare(2);
- break;
- default:
- return;
- }
-
- /* is this a 32 bit rollover ? */
- if (ccompare == 1) {
- /* roll over the timer */
- timer->hitime++;
- arch_timer_clear(timer);
- } else {
- /* no roll over, run the handler */
- tdata->handler2(tdata->arg2);
- }
-
- /* get next timeout value */
- if (timer->hitimeout == timer->hitime) {
- /* timeout is in this 32 bit period */
- ccompare = timer->lowtimeout;
- } else {
- /* timeout is in another 32 bit period */
- ccompare = 1;
- }
-
- switch (timer->id) {
- case TIMER0:
- xthal_set_ccompare(0, ccompare);
- break;
- case TIMER1:
- xthal_set_ccompare(1, ccompare);
- break;
- case TIMER2:
- xthal_set_ccompare(2, ccompare);
- break;
- default:
- return;
- }
-}
-
-int timer64_register(struct timer *timer, void(*handler)(void *arg), void *arg)
-{
- struct timer_data *tdata;
-
- switch (timer->id) {
- case TIMER0:
- tdata = &xtimer[0];
- break;
- case TIMER1:
- tdata = &xtimer[1];
- break;
- case TIMER2:
- tdata = &xtimer[2];
- break;
- default:
- return -EINVAL;
- }
-
- tdata->handler2 = handler;
- tdata->arg2 = arg;
- timer->timer_data = tdata;
- timer->hitime = 0;
- timer->hitimeout = 0;
- return 0;
-}
-
-uint64_t arch_timer_get_system(struct timer *timer)
-{
- uint64_t time;
- uint32_t flags;
- uint32_t low;
- uint32_t high;
- uint32_t ccompare;
-
- switch (timer->id) {
- case TIMER0:
- ccompare = xthal_get_ccompare(0);
- break;
- case TIMER1:
- ccompare = xthal_get_ccompare(1);
- break;
- case TIMER2:
- ccompare = xthal_get_ccompare(2);
- break;
- default:
- return 0;
- }
-
- flags = arch_interrupt_global_disable();
-
- /* read low 32 bits */
- low = xthal_get_ccount();
-
- /* check and see whether 32bit IRQ is pending for timer */
- if (arch_interrupt_get_status() & (1 << timer->irq) && ccompare == 1) {
- /* yes, overflow has occured but handler has not run */
- high = timer->hitime + 1;
- } else {
- /* no overflow */
- high = timer->hitime;
- }
-
- time = ((uint64_t)high << 32) | low;
-
- arch_interrupt_global_enable(flags);
-
- return time;
-}
-
-int arch_timer_set(struct timer *timer, uint64_t ticks)
-{
- uint32_t time = 1;
- uint32_t hitimeout = ticks >> 32;
- uint32_t flags;
-
- /* value of 1 represents rollover */
- if ((ticks & 0xffffffff) == 0x1)
- ticks++;
-
- flags = arch_interrupt_global_disable();
-
- /* same hi 64 bit context as ticks ? */
- if (hitimeout < timer->hitime) {
- /* cant be in the past */
- arch_interrupt_global_enable(flags);
- return -EINVAL;
- } else {
- /* set for checking at next timeout */
- time = ticks;
- timer->hitimeout = hitimeout;
- timer->lowtimeout = ticks;
- }
-
- switch (timer->id) {
- case TIMER0:
- xthal_set_ccompare(0, time);
- break;
- case TIMER1:
- xthal_set_ccompare(1, time);
- break;
- case TIMER2:
- xthal_set_ccompare(2, time);
- break;
- default:
- return -EINVAL;
- }
-
- arch_interrupt_global_enable(flags);
- return 0;
-}
-
-void timer_unregister(struct timer *timer)
-{
- interrupt_unregister(timer->irq);
-}
-
-void timer_enable(struct timer *timer)
-{
- interrupt_enable(timer->irq);
-}
-
-void timer_disable(struct timer *timer)
-{
- interrupt_disable(timer->irq);
-}
-
diff --git a/src/arch/xtensa/up/Makefile.am b/src/arch/xtensa/up/Makefile.am
deleted file mode 100644
index a937680..0000000
--- a/src/arch/xtensa/up/Makefile.am
+++ /dev/null
@@ -1 +0,0 @@
-SUBDIRS = hal include xtos
diff --git a/src/arch/xtensa/up/cpu.c b/src/arch/xtensa/up/cpu.c
deleted file mode 100644
index 8d87cbb..0000000
--- a/src/arch/xtensa/up/cpu.c
+++ /dev/null
@@ -1,44 +0,0 @@
-/*
- * Copyright (c) 2018, Intel Corporation
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- * * Redistributions of source code must retain the above copyright
- * notice, this list of conditions and the following disclaimer.
- * * Redistributions in binary form must reproduce the above copyright
- * notice, this list of conditions and the following disclaimer in the
- * documentation and/or other materials provided with the distribution.
- * * Neither the name of the Intel Corporation nor the
- * names of its contributors may be used to endorse or promote products
- * derived from this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
- * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
- * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
- * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
- * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
- * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
- * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
- * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
- * POSSIBILITY OF SUCH DAMAGE.
- *
- * Author: Tomasz Lauda <tomasz.lauda@linux.intel.com>
- *
- */
-
-/**
- * \file arch/xtensa/up/cpu.c
- * \brief Xtensa UP CPU implementation file
- * \authors Tomasz Lauda <tomasz.lauda@linux.intel.com>
- */
-
-#include <arch/cpu.h>
-
-void arch_cpu_enable_core(int id) { }
-
-void arch_cpu_disable_core(int id) { }
-
-int arch_cpu_is_core_enabled(int id) { return 1; }
diff --git a/src/arch/xtensa/up/hal/Makefile.am b/src/arch/xtensa/up/hal/Makefile.am
deleted file mode 100644
index fcaec14..0000000
--- a/src/arch/xtensa/up/hal/Makefile.am
+++ /dev/null
@@ -1,234 +0,0 @@
-STATE_DEFS = \
- -D__SPLIT__extra_size \
- -D__SPLIT__extra_align \
- -D__SPLIT__cpregs_size \
- -D__SPLIT__cpregs_align \
- -D__SPLIT__cp_names \
- -D__SPLIT__all_extra_size \
- -D__SPLIT__all_extra_align \
- -D__SPLIT__num_coprocessors \
- -D__SPLIT__cp_num \
- -D__SPLIT__cp_max \
- -D__SPLIT__cp_mask \
- -D__SPLIT__cp_id_mappings \
- -D__SPLIT__cp_mask_mappings \
- -D__SPLIT__init_mem_extra \
- -D__SPLIT__init_mem_cp \
- -D__SPLIT__save_extra \
- -D__SPLIT__restore_extra \
- -D__SPLIT__save_cpregs \
- -D__SPLIT__save_cp0 \
- -D__SPLIT__save_cp1 \
- -D__SPLIT__save_cp2 \
- -D__SPLIT__save_cp3 \
- -D__SPLIT__save_cp4 \
- -D__SPLIT__save_cp5 \
- -D__SPLIT__save_cp6 \
- -D__SPLIT__save_cp7 \
- -D__SPLIT__restore_cpregs \
- -D__SPLIT__restore_cp0 \
- -D__SPLIT__restore_cp1 \
- -D__SPLIT__restore_cp2 \
- -D__SPLIT__restore_cp3 \
- -D__SPLIT__restore_cp4 \
- -D__SPLIT__restore_cp5 \
- -D__SPLIT__restore_cp6 \
- -D__SPLIT__restore_cp7 \
- -D__SPLIT__cpregs_save_fn \
- -D__SPLIT__cpregs_restore_fn \
- -D__SPLIT__validate_cp \
- -D__SPLIT__invalidate_cp \
- -D__SPLIT__get_cpenable \
- -D__SPLIT__set_cpenable
-
-STATE_DEFS_CNL = \
- -D__SPLIT__extra_size \
- -D__SPLIT__extra_align \
- -D__SPLIT__cpregs_size \
- -D__SPLIT__cpregs_align \
- -D__SPLIT__cp_names \
- -D__SPLIT__all_extra_size \
- -D__SPLIT__all_extra_align \
- -D__SPLIT__num_coprocessors \
- -D__SPLIT__cp_num \
- -D__SPLIT__cp_max \
- -D__SPLIT__cp_mask \
- -D__SPLIT__cp_id_mappings \
- -D__SPLIT__cp_mask_mappings \
- -D__SPLIT__init_mem_extra \
- -D__SPLIT__init_mem_cp \
- -D__SPLIT__save_extra \
- -D__SPLIT__restore_extra \
- -D__SPLIT__cpregs_save_fn \
- -D__SPLIT__cpregs_restore_fn \
- -D__SPLIT__validate_cp \
- -D__SPLIT__invalidate_cp \
- -D__SPLIT__get_cpenable \
- -D__SPLIT__set_cpenable
-
-DISASS_DEFS = \
- -D__SPLIT__op0_format_lengths \
- -D__SPLIT__byte0_format_lengths \
- -D__SPLIT__disassemble_size \
- -D__SPLIT__disassemble
-
-MISC_DEFS = \
- -D__SPLIT__clear_regcached_code
-
-# Call0 ABI means the xthal... and xthal..._nw functions are
-# identical. If we're building for Call0 ABI, omit the ..._nw
-# functions (except for xthal_get_intpending_nw, an interrupt handler
-# helper function for which there is no duplicate and which does not
-# obey _any_ calling conventions).
-INTERRUPTS_DEFS = \
- -D__SPLIT__num_intlevels \
- -D__SPLIT__num_interrupts \
- -D__SPLIT__excm_level \
- -D__SPLIT__intlevel \
- -D__SPLIT__get_intenable \
- -D__SPLIT__set_intenable \
- -D__SPLIT__get_interrupt \
- -D__SPLIT__set_intset \
- -D__SPLIT__set_intclear
-
-CACHE_DEFS = \
- -D__SPLIT__get_cacheattr \
- -D__SPLIT__get_icacheattr \
- -D__SPLIT__set_cacheattr \
- -D__SPLIT__set_icacheattr \
- -D__SPLIT__set_dcacheattr \
- -D__SPLIT__set_idcacheattr \
- -D__SPLIT__idcache_is_enabled \
- -D__SPLIT__icache_is_enabled \
- -D__SPLIT__dcache_is_enabled \
- -D__SPLIT__idcache_is_enabled \
- -D__SPLIT__icache_all_invalidate \
- -D__SPLIT__dcache_all_invalidate \
- -D__SPLIT__dcache_all_writeback \
- -D__SPLIT__dcache_all_writeback_inv \
- -D__SPLIT__icache_all_unlock \
- -D__SPLIT__dcache_all_unlock \
- -D__SPLIT__icache_region_invalidate \
- -D__SPLIT__dcache_region_invalidate \
- -D__SPLIT__dcache_region_writeback \
- -D__SPLIT__dcache_region_writeback_inv \
- -D__SPLIT__icache_region_lock \
- -D__SPLIT__dcache_region_lock \
- -D__SPLIT__icache_region_unlock \
- -D__SPLIT__dcache_region_unlock \
- -D__SPLIT__icache_line_invalidate \
- -D__SPLIT__dcache_line_invalidate \
- -D__SPLIT__dcache_line_writeback \
- -D__SPLIT__dcache_line_writeback_inv \
- -D__SPLIT__icache_line_lock \
- -D__SPLIT__dcache_line_lock \
- -D__SPLIT__icache_line_unlock \
- -D__SPLIT__dcache_line_unlock \
- -D__SPLIT__icache_sync \
- -D__SPLIT__dcache_sync \
- -D__SPLIT__icache_get_ways \
- -D__SPLIT__icache_set_ways \
- -D__SPLIT__dcache_get_ways \
- -D__SPLIT__dcache_set_ways \
- -D__SPLIT__cache_coherence_on \
- -D__SPLIT__cache_coherence_off \
- -D__SPLIT__set_cache_prefetch_long \
- -D__SPLIT__set_cache_prefetch \
- -D__SPLIT__get_cache_prefetch \
- -D__SPLIT__hw_configid0 \
- -D__SPLIT__hw_configid1 \
- -D__SPLIT__release_major \
- -D__SPLIT__release_minor
-
-
-if BUILD_BAYTRAIL
-PLATFORM_DEFS = \
- $(STATE_DEFS) \
- $(DISASS_DEFS) \
- $(MISC_DEFS) \
- $(INTERRUPTS_DEFS) \
- $(CACHE_DEFS)
-endif
-
-if BUILD_CHERRYTRAIL
-PLATFORM_DEFS = \
- $(STATE_DEFS) \
- $(DISASS_DEFS) \
- $(MISC_DEFS) \
- $(INTERRUPTS_DEFS) \
- $(CACHE_DEFS)
-endif
-
-if BUILD_BROADWELL
-PLATFORM_DEFS = \
- $(STATE_DEFS) \
- $(DISASS_DEFS) \
- $(MISC_DEFS) \
- $(INTERRUPTS_DEFS) \
- $(CACHE_DEFS)
-endif
-
-if BUILD_HASWELL
-PLATFORM_DEFS = \
- $(STATE_DEFS) \
- $(DISASS_DEFS) \
- $(MISC_DEFS) \
- $(INTERRUPTS_DEFS) \
- $(CACHE_DEFS)
-endif
-
-if BUILD_APOLLOLAKE
-PLATFORM_DEFS = \
- $(STATE_DEFS) \
- $(DISASS_DEFS) \
- $(MISC_DEFS) \
- $(INTERRUPTS_DEFS) \
- $(CACHE_DEFS)
-endif
-
-if BUILD_CANNONLAKE
-PLATFORM_DEFS = \
- $(STATE_DEFS_CNL) \
- $(DISASS_DEFS) \
- $(MISC_DEFS) \
- $(INTERRUPTS_DEFS) \
- $(CACHE_DEFS)
-endif
-
-noinst_LIBRARIES = libhal.a
-
-libhal_a_SOURCES = \
- attribute.c \
- cache.c \
- cache_asm.S \
- clock.S \
- coherence.c \
- debug.c \
- debug_hndlr.S \
- disass.c \
- int_asm.S \
- interrupts.c \
- memcopy.S \
- mem_ecc_parity.S \
- misc.c \
- miscellaneous.S \
- mmu.c \
- mp_asm.S \
- set_region_translate.c \
- state_asm.S \
- state.c \
- syscache_asm.S \
- windowspill_asm.S
-
-libhal_a_CFLAGS = \
- $(ARCH_INCDIR) \
- $(AM_CFLAGS) \
- $(ARCH_CFLAGS) \
- $(PLATFORM_INCDIR) \
- $(PLATFORM_DEFS)
-
-libhal_a_CCASFLAGS = \
- $(ARCH_INCDIR) \
- $(AM_CCASFLAGS) \
- $(PLATFORM_INCDIR) \
- $(PLATFORM_DEFS)
diff --git a/src/arch/xtensa/up/hal/attribute.c b/src/arch/xtensa/up/hal/attribute.c
deleted file mode 100644
index 489a39b..0000000
--- a/src/arch/xtensa/up/hal/attribute.c
+++ /dev/null
@@ -1,248 +0,0 @@
-/* attribute.c - Cache attribute (memory access mode) related functions */
-
-/* $Id: //depot/rel/Eaglenest/Xtensa/OS/hal/attribute.c#1 $ */
-
-/*
- * Copyright (c) 2004-2009 Tensilica Inc.
- *
- * Permission is hereby granted, free of charge, to any person obtaining
- * a copy of this software and associated documentation files (the
- * "Software"), to deal in the Software without restriction, including
- * without limitation the rights to use, copy, modify, merge, publish,
- * distribute, sublicense, and/or sell copies of the Software, and to
- * permit persons to whom the Software is furnished to do so, subject to
- * the following conditions:
- *
- * The above copyright notice and this permission notice shall be included
- * in all copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
- * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
- * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
- * IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY
- * CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
- * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
- * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
- */
-
-#include <xtensa/config/core.h>
-
-
-
-/*
- * Set the "cache attribute" (encoded memory access modes)
- * of the region of memory specified by <vaddr> and <size>.
- *
- * This function is only supported on processor configurations
- * with region protection (or XEA1). It has no effect on
- * a processor configured with an MMU (with autorefill).
- *
- * SPECIFYING THE MEMORY REGION
- * The full (4 GB) address space may be specified with an
- * address of zero and a size of 0xFFFFFFFF (or -1);
- * in fact whenever <vaddr>+<size> equal 0xFFFFFFFF, <size>
- * is interpreted as one byte greater than that specified.
- *
- * If the specified memory range exactly covers a series
- * of consecutive 512 MB regions, the cache attributes of
- * these regions are updated with the requested attribute.
- * If this is not the case, e.g. if either or both the
- * start and end of the range only partially cover a 512 MB
- * region, one of three results are possible:
- *
- * 1. By default, the cache attribute of all regions
- * covered, even just partially, is changed to
- * the requested attribute.
- *
- * 2. If the XTHAL_CAFLAG_EXACT flag is specified,
- * a non-zero error code is returned.
- *
- * 3. If the XTHAL_CAFLAG_NO_PARTIAL flag is specified
- * (but not the EXACT flag), only regions fully
- * covered by the specified range are updated with
- * the requested attribute.
- *
- * WRITEBACK CACHE HANDLING
- * This function automatically writes back dirty data when
- * switching a region from writeback mode to a non-writeback mode.
- * This writeback is done safely, ie. by first switching to writethrough
- * mode, then invoking xthal_dcache_all_writeback(), then switching to
- * the selected <cattr> mode. Such a sequence is necessary to ensure
- * there is no longer any dirty data in the memory region by the time
- * this function returns, even in the presence of interrupts, speculation, etc.
- * This avoids memory coherency problems when switching from writeback
- * to bypass mode (in bypass mode, loads go directly to memory, ignoring
- * any dirty data in the cache; also, such dirty data can still be castout
- * due to seemingly unrelated stores).
- * This automatic write-back can be disabled using the XTHAL_CAFLAG_NO_AUTO_WB flag.
- *
- * CACHE DISABLE THEN ENABLE HANDLING
- * To avoid cache coherency issues when the cache is disabled, then
- * memory is modified, then then cache is re-enabled (thus making
- * visible stale cache entries), this function automatically
- * invalidates the cache when any region switches to bypass mode.
- * For efficiency, the entire cache is invalidated -- this is done
- * using writeback-invalidate operations to ensure coherency even
- * when other regions still have write-back caches enabled.
- * This automatic invalidate can be disabled using the XTHAL_CAFLAG_NO_AUTO_INV flag.
- *
- * Parameters:
- * vaddr starting virtual address of region of memory
- *
- * size number of bytes in region of memory
- * (see above, SPECIFYING THE MEMORY REGION)
- *
- * cattr cache attribute (encoded);
- * typically taken from compile-time HAL constants
- * XCHAL_CA_{BYPASS, WRITETHRU, WRITEBACK[_NOALLOC], ILLEGAL}
- * (defined in <xtensa/config/core.h>);
- * in XEA1, this corresponds to the value of a nibble
- * in the CACHEATTR register;
- * in XEA2, this corresponds to the value of the
- * cache attribute (CA) field of each TLB entry
- *
- * flags bitwise combination of flags XTHAL_CAFLAG_*
- * (see xtensa/hal.h for brief description of each flag);
- * (see also various descriptions above);
- *
- * The XTHAL_CAFLAG_EXPAND flag prevents attribute changes
- * to regions whose current cache attribute already provide
- * greater access than the requested attribute.
- * This ensures access to each region can only "expand",
- * and thus continue to work correctly in most instances,
- * possibly at the expense of performance. This helps
- * make this flag safer to use in a variety of situations.
- * For the purposes of this flag, cache attributes are
- * ordered (in "expansion" order, from least to greatest
- * access) as follows:
- * XCHAL_CA_ILLEGAL no access allowed
- * (various special and reserved attributes)
- * XCHAL_CA_WRITEBACK writeback cached
- * XCHAL_CA_WRITEBACK_NOALLOC writeback no-write-alloc
- * XCHAL_CA_WRITETHRU writethrough cached
- * XCHAL_CA_BYPASS bypass (uncached)
- * This is consistent with requirements of certain
- * devices that no caches be used, or in certain cases
- * that writethrough caching is allowed but not writeback.
- * Thus, bypass mode is assumed to work for most/all types
- * of devices and memories (albeit at reduced performance
- * compared to cached modes), and is ordered as providing
- * greatest access (to most devices).
- * Thus, this XTHAL_CAFLAG_EXPAND flag has no effect when
- * requesting the XCHAL_CA_BYPASS attribute (one can always
- * expand to bypass mode). And at the other extreme,
- * no action is ever taken by this function when specifying
- * both the XTHAL_CAFLAG_EXPAND flag and the XCHAL_CA_ILLEGAL
- * cache attribute.
- *
- * Returns:
- * 0 successful, or size is zero
- * -1 XTHAL_CAFLAG_NO_PARTIAL flag specified and address range
- * is valid with a non-zero size, however no 512 MB region (or page)
- * is completely covered by the range
- * -2 XTHAL_CAFLAG_EXACT flag specified, and address range does
- * not exactly specify a 512 MB region (or page)
- * -3 invalid address range specified (wraps around the end of memory)
- * -4 function not supported in this processor configuration
- */
-int xthal_set_region_attribute( void *vaddr, unsigned size, unsigned cattr, unsigned flags )
-{
-#if XCHAL_HAVE_PTP_MMU && !XCHAL_HAVE_SPANNING_WAY
- return -4; /* full MMU not supported */
-#else
-/* These cache attribute encodings are valid for XEA1 and region protection only: */
-# if XCHAL_HAVE_PTP_MMU
-# define CA_BYPASS XCHAL_CA_BYPASS
-# define CA_WRITETHRU XCHAL_CA_WRITETHRU
-# define CA_WRITEBACK XCHAL_CA_WRITEBACK
-# define CA_WRITEBACK_NOALLOC XCHAL_CA_WRITEBACK_NOALLOC
-# define CA_ILLEGAL XCHAL_CA_ILLEGAL
-# else
-/* Hardcode these, because they get remapped when caches or writeback not configured: */
-# define CA_BYPASS 2
-# define CA_WRITETHRU 1
-# define CA_WRITEBACK 4
-# define CA_WRITEBACK_NOALLOC 5
-# define CA_ILLEGAL 15
-# endif
-# define CA_MASK 0xF /*((1L<<XCHAL_CA_BITS)-1)*/ /* mask of cache attribute bits */
-
- unsigned start_region, start_offset, end_vaddr, end_region, end_offset;
- unsigned cacheattr, cachewrtr, i, disabled_cache = 0;
-
- if (size == 0)
- return 0;
- end_vaddr = (unsigned)vaddr + size - 1;
- if (end_vaddr < (unsigned)vaddr)
- return -3; /* address overflow/wraparound error */
- if (end_vaddr == 0xFFFFFFFE /*&& (unsigned)vaddr == 0*/ )
- end_vaddr = 0xFFFFFFFF; /* allow specifying 4 GB */
- start_region = ((unsigned)vaddr >> 29);
- start_offset = ((unsigned)vaddr & 0x1FFFFFFF);
- end_region = (end_vaddr >> 29);
- end_offset = ((end_vaddr+1) & 0x1FFFFFFF);
- if (flags & XTHAL_CAFLAG_EXACT) {
- if (start_offset != 0 || end_offset != 0)
- return -2; /* not an exact-sized range */
- } else if (flags & XTHAL_CAFLAG_NO_PARTIAL) {
- if (start_offset != 0)
- start_region++;
- if (end_offset != 0)
- end_region--;
- if (start_region > end_region)
- return -1; /* nothing fully covered by specified range */
- }
- cacheattr = cachewrtr = xthal_get_cacheattr();
- cattr &= CA_MASK;
-# if XCHAL_ICACHE_SIZE == 0 && XCHAL_DCACHE_SIZE == 0
- if (cattr == CA_WRITETHRU || cattr == CA_WRITEBACK || cattr == CA_WRITEBACK_NOALLOC)
- cattr = CA_BYPASS; /* no caches configured, only do protection */
-# elif XCHAL_DCACHE_IS_WRITEBACK == 0
- if (cattr == CA_WRITEBACK || cattr == CA_WRITEBACK_NOALLOC)
- cattr = CA_WRITETHRU; /* no writeback configured for data cache */
-# endif
- for (i = start_region; i <= end_region; i++) {
- unsigned sh = (i << 2); /* bit offset of nibble for region i */
- unsigned oldattr = ((cacheattr >> sh) & CA_MASK);
- unsigned newattr = cattr;
- if (flags & XTHAL_CAFLAG_EXPAND) {
- /* This array determines whether a cache attribute can be changed
- * from <a> to <b> with the EXPAND flag; an attribute's "pri"
- * value (from this array) can only monotonically increase: */
- const static signed char _Xthal_ca_pri[16] = {[CA_ILLEGAL] = -1,
- [CA_WRITEBACK] = 3, [CA_WRITEBACK_NOALLOC] = 3, [CA_WRITETHRU] = 4, [CA_BYPASS] = 9 };
- if (_Xthal_ca_pri[newattr] < _Xthal_ca_pri[oldattr])
- newattr = oldattr; /* avoid going to lesser access */
- }
- if (newattr == CA_BYPASS && oldattr != CA_BYPASS)
- disabled_cache = 1; /* we're disabling the cache for some region */
-# if XCHAL_DCACHE_IS_WRITEBACK
- {
- unsigned tmpattr = newattr;
- if ((oldattr == CA_WRITEBACK || oldattr == CA_WRITEBACK_NOALLOC)
- && newattr != CA_WRITEBACK && newattr != CA_WRITEBACK_NOALLOC) /* leaving writeback mode? */
- tmpattr = CA_WRITETHRU; /* leave it safely! */
- cachewrtr = ((cachewrtr & ~(CA_MASK << sh)) | (tmpattr << sh));
- }
-# endif
- cacheattr = ((cacheattr & ~(CA_MASK << sh)) | (newattr << sh));
- }
-# if XCHAL_DCACHE_IS_WRITEBACK
- if (cacheattr != cachewrtr /* need to leave writeback safely? */
- && (flags & XTHAL_CAFLAG_NO_AUTO_WB) == 0) {
- xthal_set_cacheattr(cachewrtr); /* set to writethru first, to safely writeback any dirty data */
- xthal_dcache_all_writeback(); /* much quicker than scanning entire 512MB region(s) */
- }
-# endif
- xthal_set_cacheattr(cacheattr);
- /* After disabling the cache, invalidate cache entries
- * to avoid coherency issues when later re-enabling it: */
- if (disabled_cache && (flags & XTHAL_CAFLAG_NO_AUTO_INV) == 0) {
- xthal_dcache_all_writeback_inv(); /* we might touch regions of memory still enabled write-back,
- so must use writeback-invalidate, not just invalidate */
- xthal_icache_all_invalidate();
- }
- return( 0 );
-#endif /* !(XCHAL_HAVE_PTP_MMU && !XCHAL_HAVE_SPANNING_WAY) */
-}
-
diff --git a/src/arch/xtensa/up/hal/cache.c b/src/arch/xtensa/up/hal/cache.c
deleted file mode 100644
index 679e4f8..0000000
--- a/src/arch/xtensa/up/hal/cache.c
+++ /dev/null
@@ -1,54 +0,0 @@
-//
-// cache.c -- cache management routines
-//
-// $Id: //depot/rel/Eaglenest/Xtensa/OS/hal/cache.c#1 $
-
-// Copyright (c) 2002 Tensilica Inc.
-//
-// Permission is hereby granted, free of charge, to any person obtaining
-// a copy of this software and associated documentation files (the
-// "Software"), to deal in the Software without restriction, including
-// without limitation the rights to use, copy, modify, merge, publish,
-// distribute, sublicense, and/or sell copies of the Software, and to
-// permit persons to whom the Software is furnished to do so, subject to
-// the following conditions:
-//
-// The above copyright notice and this permission notice shall be included
-// in all copies or substantial portions of the Software.
-//
-// THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
-// EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
-// MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
-// IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY
-// CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
-// TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
-// SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
-
-#include <xtensa/config/core.h>
-#include <xtensa/config/specreg.h>
-
-// size of the cache lines in log2(bytes)
-const unsigned char Xthal_icache_linewidth = XCHAL_ICACHE_LINEWIDTH;
-const unsigned char Xthal_dcache_linewidth = XCHAL_DCACHE_LINEWIDTH;
-
-// size of the cache lines in bytes
-const unsigned short Xthal_icache_linesize = XCHAL_ICACHE_LINESIZE;
-const unsigned short Xthal_dcache_linesize = XCHAL_DCACHE_LINESIZE;
-
-// number of cache sets in log2(lines per way)
-const unsigned char Xthal_icache_setwidth = XCHAL_ICACHE_SETWIDTH;
-const unsigned char Xthal_dcache_setwidth = XCHAL_DCACHE_SETWIDTH;
-
-// cache set associativity (number of ways)
-const unsigned int Xthal_icache_ways = XCHAL_ICACHE_WAYS;
-const unsigned int Xthal_dcache_ways = XCHAL_DCACHE_WAYS;
-
-// size of the caches in bytes (ways * 2^(linewidth + setwidth))
-const unsigned int Xthal_icache_size = XCHAL_ICACHE_SIZE;
-const unsigned int Xthal_dcache_size = XCHAL_DCACHE_SIZE;
-
-// cache features
-const unsigned char Xthal_dcache_is_writeback = XCHAL_DCACHE_IS_WRITEBACK;
-const unsigned char Xthal_icache_line_lockable = XCHAL_ICACHE_LINE_LOCKABLE;
-const unsigned char Xthal_dcache_line_lockable = XCHAL_DCACHE_LINE_LOCKABLE;
-
diff --git a/src/arch/xtensa/up/hal/cache_asm.S b/src/arch/xtensa/up/hal/cache_asm.S
deleted file mode 100644
index 8bdc17e..0000000
--- a/src/arch/xtensa/up/hal/cache_asm.S
+++ /dev/null
@@ -1,1315 +0,0 @@
-//
-// cache_asm.S - assembly language cache management routines
-//
-// $Id: //depot/rel/Eaglenest/Xtensa/OS/hal/cache_asm.S#5 $
-
-// Copyright (c) 1999-2014 Cadence Design Systems, Inc.
-//
-// Permission is hereby granted, free of charge, to any person obtaining
-// a copy of this software and associated documentation files (the
-// "Software"), to deal in the Software without restriction, including
-// without limitation the rights to use, copy, modify, merge, publish,
-// distribute, sublicense, and/or sell copies of the Software, and to
-// permit persons to whom the Software is furnished to do so, subject to
-// the following conditions:
-//
-// The above copyright notice and this permission notice shall be included
-// in all copies or substantial portions of the Software.
-//
-// THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
-// EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
-// MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
-// IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY
-// CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
-// TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
-// SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
-
-#include <xtensa/cacheasm.h>
-#include <xtensa/cacheattrasm.h>
-#include <xtensa/xtensa-versions.h>
-
-/* For Call0 ABI, the xthal... and xthal..._nw versions are identical,
- * so we define both labels for the same function body. The Makefile
- * does not define any of the __SPLIT__..._nw macros if Call0 ABI.
- * Use SYM() when we don't want .type information. */
-
-#if defined (__XTENSA_CALL0_ABI__)
-# define SYMBOL(x) _SYMT(x); _SYM2(x ## _nw)
-#else
-# define SYMBOL(x) _SYMT(x)
-#endif
-
-
-
- .text
-
-//----------------------------------------------------------------------
-// Read CACHEATTR register
-//----------------------------------------------------------------------
-
-#if defined(__SPLIT__get_cacheattr)
-
-// unsigned xthal_get_cacheattr(void);
-
-SYMBOL(xthal_get_cacheattr)
-SYMBOL(xthal_get_dcacheattr)
-# if XCHAL_HAVE_CACHEATTR /* single CACHEATTR register used for both I and D */
-SYMBOL(xthal_get_icacheattr)
-# endif
- abi_entry
- dcacheattr_get
- abi_return
- endfunc
-
-#endif
-#if defined(__SPLIT__get_cacheattr_nw)
-
-SYM(xthal_get_cacheattr_nw)
-SYM(xthal_get_dcacheattr_nw)
-# if XCHAL_HAVE_CACHEATTR /* single CACHEATTR register used for both I and D */
-SYM(xthal_get_icacheattr_nw)
-# endif
- dcacheattr_get
- ret
- endfunc
-
-#endif
-#if defined(__SPLIT__get_icacheattr)
-
-// unsigned xthal_get_icacheattr(void);
-
-# if !XCHAL_HAVE_CACHEATTR /* possibly independent CACHEATTR states used for I and D */
-SYMBOL(xthal_get_icacheattr)
- abi_entry
- icacheattr_get
- abi_return
- endfunc
-# endif
-
-#endif
-#if defined(__SPLIT__get_icacheattr_nw)
-
-# if !XCHAL_HAVE_CACHEATTR /* possibly independent CACHEATTR states used for I and D */
-SYM(xthal_get_icacheattr_nw)
- icacheattr_get
- ret
- endfunc
-# endif
-
-#endif /*split*/
-
-
-//----------------------------------------------------------------------
-// Write CACHEATTR register, or equivalent.
-//----------------------------------------------------------------------
-
-/*
- * Set CACHEATTR register in a safe manner.
- *
- * void xthal_set_cacheattr( unsigned new_cacheattr );
- * void xthal_set_icacheattr( unsigned new_cacheattr );
- * void xthal_set_dcacheattr( unsigned new_cacheattr );
- */
-
-#if defined(__SPLIT__set_cacheattr)
-
-# if XCHAL_HAVE_CACHEATTR /* single CACHEATTR register used for both I and D accesses */
-SYMBOL(xthal_set_icacheattr)
-SYMBOL(xthal_set_dcacheattr)
-# endif
-SYMBOL(xthal_set_cacheattr)
- abi_entry
- cacheattr_set
- abi_return
- endfunc
-
-
-#endif
-#if defined(__SPLIT__set_cacheattr_nw)
-
-#if XCHAL_HAVE_CACHEATTR /* single CACHEATTR register used for both Instruction and Data accesses */
-SYM(xthal_set_icacheattr_nw)
-SYM(xthal_set_dcacheattr_nw)
-#endif
-SYM(xthal_set_cacheattr_nw)
- cacheattr_set
- ret
- endfunc
-
-#endif /*split*/
-
-
-#if XCHAL_HAVE_CACHEATTR
-
- /*
- * Already done above.
- *
- * Since we can't enable/disable the icache and dcache independently,
- * and don't have a nice place to store a state which would enable
- * us to only enable them both when both have been requested to be
- * enabled, we simply enable both for any request to enable either,
- * and disable both for any request to disable either cache.
- */
-
-#elif XCHAL_HAVE_MIMIC_CACHEATTR || XCHAL_HAVE_XLT_CACHEATTR || (XCHAL_HAVE_PTP_MMU && XCHAL_HAVE_SPANNING_WAY)
-
-# if defined(__SPLIT__set_icacheattr)
-
-SYMBOL(xthal_set_icacheattr)
- abi_entry
- icacheattr_set
- isync_retw_nop
- abi_return
- endfunc
-
-#endif
-#if defined(__SPLIT__set_icacheattr_nw)
-
-SYM(xthal_set_icacheattr_nw)
- icacheattr_set
- ret
- endfunc
-
-#endif
-#if defined(__SPLIT__set_dcacheattr)
-
-SYMBOL(xthal_set_dcacheattr)
- abi_entry
- dcacheattr_set
- abi_return
- endfunc
-
-#endif
-#if defined(__SPLIT__set_dcacheattr_nw)
-
- .align 4
-SYM(xthal_set_dcacheattr_nw)
- dcacheattr_set
- ret
- endfunc
-
-# endif /*split*/
-
-#else /* full MMU (pre-v3): */
-
-# if defined(__SPLIT__set_idcacheattr)
-
-// These functions aren't applicable to arbitrary MMU configurations.
-// Do nothing in this case.
-
-SYMBOL(xthal_set_icacheattr)
-SYMBOL(xthal_set_dcacheattr)
- abi_entry
- abi_return
- endfunc
-
-#endif
-#if defined(__SPLIT__set_idcacheattr_nw)
-
-SYM(xthal_set_icacheattr_nw)
-SYM(xthal_set_dcacheattr_nw)
- ret
- endfunc
-
-# endif /*split*/
-
-#endif /* cacheattr/MMU type */
-
-
-//----------------------------------------------------------------------
-// Determine (guess) whether caches are "enabled"
-//----------------------------------------------------------------------
-
-/*
- * There is no "cache enable" bit in the Xtensa architecture,
- * but we can use CACHEATTR (if it or its equivalent exists)
- * as an indication that caches have been enabled.
- */
-
-#if XCHAL_HAVE_CACHEATTR
-
-# if defined(__SPLIT__idcache_is_enabled)
-
-SYMBOL(xthal_icache_is_enabled)
-SYMBOL(xthal_dcache_is_enabled)
- abi_entry
- cacheattr_is_enabled 2f
- movi a2, 0
- abi_return
-2: movi a2, 1
- abi_return
- endfunc
-
-#endif
-#if defined(__SPLIT__idcache_is_enabled_nw)
-
-SYM(xthal_icache_is_enabled_nw)
-SYM(xthal_dcache_is_enabled_nw)
- cacheattr_is_enabled 2f
- movi a2, 0
- ret
-2: movi a2, 1
- ret
- endfunc
-
-# endif /*split*/
-
-#elif XCHAL_HAVE_MIMIC_CACHEATTR || XCHAL_HAVE_XLT_CACHEATTR
-
-# if defined(__SPLIT__icache_is_enabled)
-
-SYMBOL(xthal_icache_is_enabled)
- abi_entry
- icacheattr_is_enabled 2f
- movi a2, 0
- abi_return
-2: movi a2, 1
- abi_return
- endfunc
-
-#endif
-#if defined(__SPLIT__icache_is_enabled_nw)
-
-SYM(xthal_icache_is_enabled_nw)
- icacheattr_is_enabled 2f
- movi a2, 0
- ret
-2: movi a2, 1
- ret
- endfunc
-
-#endif
-#if defined(__SPLIT__dcache_is_enabled)
-
-SYMBOL(xthal_dcache_is_enabled)
- abi_entry
- dcacheattr_is_enabled 2f
- movi a2, 0
- abi_return
-2: movi a2, 1
- abi_return
- endfunc
-
-#endif
-#if defined(__SPLIT__dcache_is_enabled_nw)
-
-SYM(xthal_dcache_is_enabled_nw)
- dcacheattr_is_enabled 2f
- movi a2, 0
- ret
-2: movi a2, 1
- ret
- endfunc
-
-# endif /*split*/
-
-#else
-
-// These functions aren't applicable to arbitrary MMU configurations.
-// Assume caches are enabled in this case (!).
-
-# if defined(__SPLIT__idcache_is_enabled)
-
-SYMBOL(xthal_icache_is_enabled)
-SYMBOL(xthal_dcache_is_enabled)
- abi_entry
- movi a2, 1
- abi_return
- endfunc
-
-#endif
-#if defined(__SPLIT__idcache_is_enabled_nw)
-
-SYM(xthal_icache_is_enabled_nw)
-SYM(xthal_dcache_is_enabled_nw)
- movi a2, 1
- ret
- endfunc
-
-# endif /*split*/
-
-#endif
-
-
-
-//----------------------------------------------------------------------
-// invalidate the icache
-//----------------------------------------------------------------------
-
-#if defined(__SPLIT__icache_all_invalidate)
-
-// void xthal_icache_all_invalidate(void);
-
-SYMBOL(xthal_icache_all_invalidate)
- abi_entry
- icache_invalidate_all a2, a3
- isync_retw_nop
- abi_return
- endfunc
-
-#endif
-#if defined(__SPLIT__icache_all_invalidate_nw)
-
-// void xthal_icache_all_invalidate_nw(void);
-
-SYM(xthal_icache_all_invalidate_nw)
- icache_invalidate_all a2, a3
- ret
- endfunc
-
-
-//----------------------------------------------------------------------
-// invalidate the dcache
-//----------------------------------------------------------------------
-
-#endif
-#if defined(__SPLIT__dcache_all_invalidate)
-
-// void xthal_dcache_all_invalidate(void);
-
-SYMBOL(xthal_dcache_all_invalidate)
- abi_entry
- dcache_invalidate_all a2, a3
- abi_return
- endfunc
-
-#endif
-#if defined(__SPLIT__dcache_all_invalidate_nw)
-
-// void xthal_dcache_all_invalidate_nw(void);
-
-SYM(xthal_dcache_all_invalidate_nw)
- dcache_invalidate_all a2, a3
- ret
- endfunc
-
-
-//----------------------------------------------------------------------
-// write dcache dirty data
-//----------------------------------------------------------------------
-
-#endif
-#if defined(__SPLIT__dcache_all_writeback)
-
-// void xthal_dcache_all_writeback(void);
-
-SYMBOL(xthal_dcache_all_writeback)
- abi_entry
- dcache_writeback_all a2, a3
- abi_return
- endfunc
-
-#endif
-#if defined(__SPLIT__dcache_all_writeback_nw)
-
-// void xthal_dcache_all_writeback_nw(void);
-
-SYM(xthal_dcache_all_writeback_nw)
- dcache_writeback_all a2, a3
- ret
- endfunc
-
-
-//----------------------------------------------------------------------
-// write dcache dirty data and invalidate
-//----------------------------------------------------------------------
-
-#endif
-#if defined(__SPLIT__dcache_all_writeback_inv)
-
-// void xthal_dcache_all_writeback_inv(void);
-
-SYMBOL(xthal_dcache_all_writeback_inv)
- abi_entry
- dcache_writeback_inv_all a2, a3
- abi_return
- endfunc
-
-#endif
-#if defined(__SPLIT__dcache_all_writeback_inv_nw)
-
-// void xthal_dcache_all_writeback_inv_nw(void);
-
-SYM(xthal_dcache_all_writeback_inv_nw)
- dcache_writeback_inv_all a2, a3
- ret
- endfunc
-
-
-//----------------------------------------------------------------------
-// unlock instructions from icache
-//----------------------------------------------------------------------
-
-#endif
-#if defined(__SPLIT__icache_all_unlock)
-
-// void xthal_icache_all_unlock(void);
-
-SYMBOL(xthal_icache_all_unlock)
- abi_entry
- icache_unlock_all a2, a3
- abi_return
- endfunc
-
-#endif
-#if defined(__SPLIT__icache_all_unlock_nw)
-
-// void xthal_icache_all_unlock_nw(void);
-
-SYM(xthal_icache_all_unlock_nw)
- icache_unlock_all a2, a3
- ret
- endfunc
-
-
-//----------------------------------------------------------------------
-// unlock data from dcache
-//----------------------------------------------------------------------
-
-#endif
-#if defined(__SPLIT__dcache_all_unlock)
-
-// void xthal_dcache_all_unlock(void);
-
-SYMBOL(xthal_dcache_all_unlock)
- abi_entry
- dcache_unlock_all a2, a3
- abi_return
- endfunc
-
-#endif
-#if defined(__SPLIT__dcache_all_unlock_nw)
-
-// void xthal_dcache_all_unlock_nw(void);
-
-SYM(xthal_dcache_all_unlock_nw)
- dcache_unlock_all a2, a3
- ret
- endfunc
-
-
-//----------------------------------------------------------------------
-// invalidate the address range in the icache
-//----------------------------------------------------------------------
-
-#endif
-#if defined(__SPLIT__icache_region_invalidate)
-
-// void xthal_icache_region_invalidate( void *addr, unsigned size );
-
-SYMBOL(xthal_icache_region_invalidate)
- abi_entry
- icache_invalidate_region a2, a3, a4
- isync_retw_nop
- abi_return
- endfunc
-
-#endif
-#if defined(__SPLIT__icache_region_invalidate_nw)
-
-// void xthal_icache_region_invalidate_nw( void *addr, unsigned size );
-
-SYM(xthal_icache_region_invalidate_nw)
- icache_invalidate_region a2, a3, a4
- ret
- endfunc
-
-
-//----------------------------------------------------------------------
-// invalidate the address range in the dcache
-//----------------------------------------------------------------------
-
-#endif
-#if defined(__SPLIT__dcache_region_invalidate)
-
-// void xthal_dcache_region_invalidate( void *addr, unsigned size );
-
-SYMBOL(xthal_dcache_region_invalidate)
- abi_entry
- dcache_invalidate_region a2, a3, a4
- abi_return
- endfunc
-
-#endif
-#if defined(__SPLIT__dcache_region_invalidate_nw)
-
-// void xthal_dcache_region_invalidate_nw( void *addr, unsigned size );
-
-SYM(xthal_dcache_region_invalidate_nw)
- dcache_invalidate_region a2, a3, a4
- ret
- endfunc
-
-
-//----------------------------------------------------------------------
-// write dcache region dirty data
-//----------------------------------------------------------------------
-
-#endif
-#if defined(__SPLIT__dcache_region_writeback)
-
-// void xthal_dcache_region_writeback( void *addr, unsigned size );
-
-SYMBOL(xthal_dcache_region_writeback)
- abi_entry
- dcache_writeback_region a2, a3, a4
- abi_return
- endfunc
-
-#endif
-#if defined(__SPLIT__dcache_region_writeback_nw)
-
-// void xthal_dcache_region_writeback_nw( void *addr, unsigned size );
-
-SYM(xthal_dcache_region_writeback_nw)
- dcache_writeback_region a2, a3, a4
- ret
- endfunc
-
-
-//----------------------------------------------------------------------
-// write dcache region dirty data and invalidate
-//----------------------------------------------------------------------
-
-#endif
-#if defined(__SPLIT__dcache_region_writeback_inv)
-
-// void xthal_dcache_region_writeback_inv( void *addr, unsigned size );
-
-SYMBOL(xthal_dcache_region_writeback_inv)
- abi_entry
- dcache_writeback_inv_region a2, a3, a4
- abi_return
- endfunc
-
-#endif
-#if defined(__SPLIT__dcache_region_writeback_inv_nw)
-
-// void xthal_dcache_region_writeback_inv_nw( void *addr, unsigned size );
-
-SYM(xthal_dcache_region_writeback_inv_nw)
- dcache_writeback_inv_region a2, a3, a4
- ret
- endfunc
-
-
-//----------------------------------------------------------------------
-// lock instructions in icache region
-//----------------------------------------------------------------------
-
-#endif
-#if defined(__SPLIT__icache_region_lock)
-
-// void xthal_icache_region_lock(void);
-
-SYMBOL(xthal_icache_region_lock)
- abi_entry
- icache_lock_region a2, a3, a4
- abi_return
- endfunc
-
-#endif
-#if defined(__SPLIT__icache_region_lock_nw)
-
-// void xthal_icache_region_lock_nw(void);
-
-SYM(xthal_icache_region_lock_nw)
- icache_lock_region a2, a3, a4
- ret
- endfunc
-
-
-//----------------------------------------------------------------------
-// lock data in dcache region
-//----------------------------------------------------------------------
-
-#endif
-#if defined(__SPLIT__dcache_region_lock)
-
-// void xthal_dcache_region_lock(void);
-
-SYMBOL(xthal_dcache_region_lock)
- abi_entry
- dcache_lock_region a2, a3, a4
- abi_return
- endfunc
-
-#endif
-#if defined(__SPLIT__dcache_region_lock_nw)
-
-// void xthal_dcache_region_lock_nw(void);
-
-SYM(xthal_dcache_region_lock_nw)
- dcache_lock_region a2, a3, a4
- ret
- endfunc
-
-
-//----------------------------------------------------------------------
-// unlock instructions from icache region
-//----------------------------------------------------------------------
-
-#endif
-#if defined(__SPLIT__icache_region_unlock)
-
-// void xthal_icache_region_unlock(void);
-
-SYMBOL(xthal_icache_region_unlock)
- abi_entry
- icache_unlock_region a2, a3, a4
- abi_return
- endfunc
-
-#endif
-#if defined(__SPLIT__icache_region_unlock_nw)
-
-// void xthal_icache_region_unlock_nw(void);
-
-SYM(xthal_icache_region_unlock_nw)
- icache_unlock_region a2, a3, a4
- ret
- endfunc
-
-
-//----------------------------------------------------------------------
-// unlock data from dcache region
-//----------------------------------------------------------------------
-
-#endif
-#if defined(__SPLIT__dcache_region_unlock)
-
-// void xthal_dcache_region_unlock(void);
-
-SYMBOL(xthal_dcache_region_unlock)
- abi_entry
- dcache_unlock_region a2, a3, a4
- abi_return
- endfunc
-
-#endif
-#if defined(__SPLIT__dcache_region_unlock_nw)
-
-// void xthal_dcache_region_unlock_nw(void);
-
-SYM(xthal_dcache_region_unlock_nw)
- dcache_unlock_region a2, a3, a4
- ret
- endfunc
-
-
-//----------------------------------------------------------------------
-// invalidate single icache line
-//----------------------------------------------------------------------
-
-#endif
-#if defined(__SPLIT__icache_line_invalidate)
-
-// void xthal_icache_line_invalidate(void *addr);
-
-SYMBOL(xthal_icache_line_invalidate)
- abi_entry
- icache_invalidate_line a2, 0
- isync_retw_nop
- abi_return
- endfunc
-
-#endif
-#if defined(__SPLIT__icache_line_invalidate_nw)
-
-// void xthal_icache_line_invalidate_nw(void *addr);
-
-SYM(xthal_icache_line_invalidate_nw)
- icache_invalidate_line a2, 0
- ret
- endfunc
-
-
-//----------------------------------------------------------------------
-// invalidate single dcache line
-//----------------------------------------------------------------------
-
-#endif
-#if defined(__SPLIT__dcache_line_invalidate)
-
-// void xthal_dcache_line_invalidate(void *addr);
-
-SYMBOL(xthal_dcache_line_invalidate)
- abi_entry
- dcache_invalidate_line a2, 0
- abi_return
- endfunc
-
-#endif
-#if defined(__SPLIT__dcache_line_invalidate_nw)
-
-// void xthal_dcache_line_invalidate_nw(void *addr);
-
-SYM(xthal_dcache_line_invalidate_nw)
- dcache_invalidate_line a2, 0
- ret
- endfunc
-
-
-//----------------------------------------------------------------------
-// write single dcache line dirty data
-//----------------------------------------------------------------------
-
-#endif
-#if defined(__SPLIT__dcache_line_writeback)
-
-// void xthal_dcache_line_writeback(void *addr);
-
-SYMBOL(xthal_dcache_line_writeback)
- abi_entry
- dcache_writeback_line a2, 0
- abi_return
- endfunc
-
-#endif
-#if defined(__SPLIT__dcache_line_writeback_nw)
-
-// void xthal_dcache_line_writeback_nw(void *addr);
-
-SYM(xthal_dcache_line_writeback_nw)
- dcache_writeback_line a2, 0
- ret
- endfunc
-
-
-//----------------------------------------------------------------------
-// write single dcache line dirty data and invalidate
-//----------------------------------------------------------------------
-
-#endif
-#if defined(__SPLIT__dcache_line_writeback_inv)
-
-// void xthal_dcache_line_writeback_inv(void *addr);
-
-SYMBOL(xthal_dcache_line_writeback_inv)
- abi_entry
- dcache_writeback_inv_line a2, 0
- abi_return
- endfunc
-
-#endif
-#if defined(__SPLIT__dcache_line_writeback_inv_nw)
-
-// void xthal_dcache_line_writeback_inv_nw(void *addr);
-
-SYM(xthal_dcache_line_writeback_inv_nw)
- dcache_writeback_inv_line a2, 0
- ret
- endfunc
-
-
-//----------------------------------------------------------------------
-// lock instructions in icache line
-//----------------------------------------------------------------------
-
-#endif
-#if defined(__SPLIT__icache_line_lock)
-
-// void xthal_icache_line_lock(void);
-
-SYMBOL(xthal_icache_line_lock)
- abi_entry
- icache_lock_line a2, 0
- abi_return
- endfunc
-
-#endif
-#if defined(__SPLIT__icache_line_lock_nw)
-
-// void xthal_icache_line_lock_nw(void);
-
-SYM(xthal_icache_line_lock_nw)
- icache_lock_line a2, 0
- ret
- endfunc
-
-
-//----------------------------------------------------------------------
-// lock data in dcache line
-//----------------------------------------------------------------------
-
-#endif
-#if defined(__SPLIT__dcache_line_lock)
-
-// void xthal_dcache_line_lock(void);
-
-SYMBOL(xthal_dcache_line_lock)
- abi_entry
- dcache_lock_line a2, 0
- abi_return
- endfunc
-
-#endif
-#if defined(__SPLIT__dcache_line_lock_nw)
-
-// void xthal_dcache_line_lock_nw(void);
-
-SYM(xthal_dcache_line_lock_nw)
- dcache_lock_line a2, 0
- ret
- endfunc
-
-
-//----------------------------------------------------------------------
-// unlock instructions from icache line
-//----------------------------------------------------------------------
-
-#endif
-#if defined(__SPLIT__icache_line_unlock)
-
-// void xthal_icache_line_unlock(void);
-
-SYMBOL(xthal_icache_line_unlock)
- abi_entry
- icache_unlock_line a2, 0
- abi_return
- endfunc
-
-#endif
-#if defined(__SPLIT__icache_line_unlock_nw)
-
-// void xthal_icache_line_unlock_nw(void);
-
-SYM(xthal_icache_line_unlock_nw)
- icache_unlock_line a2, 0
- ret
- endfunc
-
-
-//----------------------------------------------------------------------
-// unlock data from dcache line
-//----------------------------------------------------------------------
-
-#endif
-#if defined(__SPLIT__dcache_line_unlock)
-
-// void xthal_dcache_line_unlock(void);
-
-SYMBOL(xthal_dcache_line_unlock)
- abi_entry
- dcache_unlock_line a2, 0
- abi_return
- endfunc
-
-#endif
-#if defined(__SPLIT__dcache_line_unlock_nw)
-
-// void xthal_dcache_line_unlock_nw(void);
-
-SYM(xthal_dcache_line_unlock_nw)
- dcache_unlock_line a2, 0
- ret
- endfunc
-
-
-//----------------------------------------------------------------------
-// sync icache and memory (???)
-//----------------------------------------------------------------------
-
-#endif
-#if defined(__SPLIT__icache_sync)
-
-// void xthal_icache_sync(void);
-
-SYMBOL(xthal_icache_sync)
- abi_entry
- icache_sync a2
- isync_retw_nop
- abi_return
- endfunc
-
-#endif
-#if defined(__SPLIT__icache_sync_nw)
-
-// void xthal_icache_sync_nw(void);
-
-SYM(xthal_icache_sync_nw)
- icache_sync a2
- ret
- endfunc
-
-
-//----------------------------------------------------------------------
-// sync dcache and memory (???)
-//----------------------------------------------------------------------
-
-#endif
-#if defined(__SPLIT__dcache_sync)
-
-// void xthal_dcache_sync(void);
-
-SYMBOL(xthal_dcache_sync)
- abi_entry
- dcache_sync a2
- abi_return
- endfunc
-
-#endif
-#if defined(__SPLIT__dcache_sync_nw)
-
-// void xthal_dcache_sync_nw(void)
-
-SYM(xthal_dcache_sync_nw)
- dcache_sync a2
- ret
- endfunc
-
-//----------------------------------------------------------------------
-// Get/Set icache number of ways enabled
-//----------------------------------------------------------------------
-
-#elif defined (__SPLIT__icache_get_ways)
-
-// unsigned int xthal_icache_get_ways(void);
-
-SYMBOL(xthal_icache_get_ways)
- abi_entry
- icache_get_ways a2
- abi_return
- endfunc
-
-#elif defined (__SPLIT__icache_set_ways)
-
-// void xthal_icache_set_ways(unsigned int ways);
-
-SYMBOL(xthal_icache_set_ways)
- abi_entry
- icache_set_ways a2 a3 a4
- abi_return
- endfunc
-
-#elif defined (__SPLIT__icache_get_ways_nw)
-
-// unsigned int xthal_icache_get_ways_nw(void);
-
-SYM(xthal_icache_get_ways_nw)
- icache_get_ways a2
- ret
- endfunc
-
-#elif defined (__SPLIT__icache_set_ways_nw)
-
-// void xthal_icache_set_ways_nw(unsigned int ways);
-
-SYM(xthal_icache_set_ways_nw)
- icache_set_ways a2 a3 a4
- ret
- endfunc
-
-//----------------------------------------------------------------------
-// Get/Set dcache number of ways enabled
-//----------------------------------------------------------------------
-
-#elif defined (__SPLIT__dcache_get_ways)
-
-// unsigned int xthal_dcache_get_ways(void);
-
-SYMBOL(xthal_dcache_get_ways)
- abi_entry
- dcache_get_ways a2
- abi_return
- endfunc
-
-#elif defined (__SPLIT__dcache_set_ways)
-
-// void xthal_dcache_set_ways(unsigned int ways);
-
-SYMBOL(xthal_dcache_set_ways)
- abi_entry
- dcache_set_ways a2 a3 a4
- abi_return
- endfunc
-
-#elif defined (__SPLIT__dcache_get_ways_nw)
-
-// unsigned int xthal_dcache_get_ways_nw(void);
-
-SYM(xthal_dcache_get_ways_nw)
- dcache_get_ways a2
- ret
- endfunc
-
-#elif defined (__SPLIT__dcache_set_ways_nw)
-
-// void xthal_dcache_set_ways_nw(unsigned int ways);
-
-SYM(xthal_dcache_set_ways_nw)
- dcache_set_ways a2 a3 a4
- ret
- endfunc
-
-//----------------------------------------------------------------------
-// opt into and out of coherence
-//----------------------------------------------------------------------
-
-#endif
-#if defined(__SPLIT__cache_coherence_on)
-
-// The opt-in routine assumes cache was initialized at reset,
-// so it's equivalent to the low-level coherence_on routine.
-
-// void xthal_cache_coherence_optin(void)
-// void xthal_cache_coherence_on(void)
-
-SYMBOL(xthal_cache_coherence_optin)
-SYMBOL(xthal_cache_coherence_on)
- abi_entry
- cache_coherence_on a2, a3
- abi_return
- endfunc
-
-#endif
-#if defined(__SPLIT__cache_coherence_on_nw)
-
-// void xthal_cache_coherence_on_nw(void)
-
-SYM(xthal_cache_coherence_on_nw)
- cache_coherence_on a2, a3
- ret
- endfunc
-
-#endif
-#if defined(__SPLIT__cache_coherence_off)
-
-// The coherence_off routines should not normally be called directly.
-// Use the xthal_cache_coherence_optout() C routine instead
-// (which first empties the cache).
-
-// void xthal_cache_coherence_off
-
-SYMBOL(xthal_cache_coherence_off)
- abi_entry
- cache_coherence_off a2, a3
- abi_return
- endfunc
-
-#endif
-#if defined(__SPLIT__cache_coherence_off_nw)
-
-// void xthal_cache_coherence_on_nw
-
-SYM(xthal_cache_coherence_off_nw)
- cache_coherence_off a2, a3
- ret
- endfunc
-
-//----------------------------------------------------------------------
-// Control cache prefetch
-//----------------------------------------------------------------------
-
-#endif
-#if defined(__SPLIT__set_cache_prefetch_long)
-
-# if XCHAL_HAVE_BE
-# define aH a2 /* msb word = prefctl mask */
-# define aL a3 /* lsb word = prefctl value */
-# else
-# define aH a3 /* msb word = prefctl mask */
-# define aL a2 /* lsb word = prefctl value */
-# endif
-
-// Set cache prefetch state (-1=enable, 0=disable, and see XTHAL_*PREFETCH_*),
-// and return previous one.
-//
-// int xthal_set_cache_prefetch_long( unsigned long long );
-//
-SYMBOL(xthal_set_cache_prefetch_long)
- abi_entry
-# if XCHAL_HAVE_PREFETCH
- movi a5, XCHAL_CACHE_PREFCTL_DEFAULT
- addi a4, aL, 1 // does prefctl value aL == -1 ?
- moveqz aL, a5, a4 // if yes (XTHAL_PREFETCH_ENABLE), set it to default
- movgez a2, aL, aL // if the high bit is not set, then we want to transfer the contents of aL to prefctl
- // so we move it to a2
- bgez aL, 1f // high bit set indicates masked update
- ssai 16 // 16-bit right shifts
- src a5, aL, aH // get 16-bit-swapped 32-bit value
- src a5, a5, a5 // get 32-bit value (rotate by 16)
- rsr.prefctl a4
- src a3, aH, aL // get 32-bit mask
- or a4, a4, a3 // set masked bits
- xor a4, a4, a3 // clear masked bits
- and a5, a5, a3 // only use masked bits
- or a2, a4, a5 // combine masked bits
-1:
-# if XCHAL_HW_MIN_VERSION <= XTENSA_HWVERSION_RC_2010_1 /* for erratum #325 */
- j 1f ; .align 8 ; 1: xsr.prefctl a2 ; isync // ensure XSR.PREFCTL;ISYNC wholly within an icache line
-# else
- xsr.prefctl a2
-# endif
-# else
- movi a2, 0
-# endif
- abi_return
- endfunc
-
-//----------------------------------------------------------------------
-
-#endif
-#if defined(__SPLIT__set_cache_prefetch_long_nw)
-
-# if XCHAL_HAVE_BE
-# define aH a2 /* msb word = prefctl mask */
-# define aL a3 /* lsb word = prefctl value */
-# else
-# define aH a3 /* msb word = prefctl mask */
-# define aL a2 /* lsb word = prefctl value */
-# endif
-
-// int xthal_set_cache_prefetch_long_nw( unsigned long long )
-SYM(xthal_set_cache_prefetch_long_nw)
-# if XCHAL_HAVE_PREFETCH
- movi a5, XCHAL_CACHE_PREFCTL_DEFAULT
- addi a4, aL, 1 // does prefctl value aL == -1 ?
- moveqz aL, a5, a4 // if yes (XTHAL_PREFETCH_ENABLE), set it to default
- movgez a2, aL, aL // if the high bit is not set, then we want to transfer the contents of aL to prefctl
- // so we move it to a2
- bgez aL, 1f // high bit set indicates masked update
- ssai 16 // 16-bit right shifts
- src a5, aL, aH // get 16-bit-swapped 32-bit value
- src a5, a5, a5 // get 32-bit value (rotate by 16)
- rsr.prefctl a4
- src a3, aH, aL // get 32-bit mask
- or a4, a4, a3 // set masked bits
- xor a4, a4, a3 // clear masked bits
- and a5, a5, a3 // only use masked bits
- or a2, a4, a5 // combine masked bits
-1:
-# if XCHAL_HW_MIN_VERSION <= XTENSA_HWVERSION_RC_2010_1 /* for erratum #325 */
- j 1f ; .align 8 ; 1: xsr.prefctl a2 ; isync // ensure XSR.PREFCTL;ISYNC wholly within an icache line
-# else
- xsr.prefctl a2
-# endif
-# else
- movi a2, 0
-# endif
- ret
- endfunc
-
-//----------------------------------------------------------------------
-
-#endif
-#if defined(__SPLIT__set_cache_prefetch)
-
-// FOR BACKWARD COMPATIBILITY WITH PRE-RF RELEASE OBJECT CODE ONLY.
-// Set cache prefetch state (-1=enable, 0=disable, and see the
-// definitions of XTHAL_*PREFETCH_* with only the lower 32 bits set),
-// and return previous one.
-// int xthal_set_cache_prefetch( int )
-//
-SYMBOL(xthal_set_cache_prefetch)
- abi_entry
-# if XCHAL_HAVE_PREFETCH
- movi a3, XCHAL_CACHE_PREFCTL_DEFAULT
- addi a4, a2, 1 // does a2 == -1 ?
- moveqz a2, a3, a4 // if yes (XTHAL_PREFETCH_ENABLE), set it to default
- bbci.l a2, 31, 1f // high bit set indicates masked update
- rsr.prefctl a4
- extui a5, a2, 16, 15
- or a4, a4, a5 // set masked bits
- xor a4, a4, a5 // clear masked bits
- and a2, a2, a5 // only use masked bits
- or a2, a4, a2 // combine masked bits
-1:
-# if XCHAL_HW_MIN_VERSION <= XTENSA_HWVERSION_RC_2010_1 /* for erratum #325 */
- j 1f ; .align 8 ; 1: xsr.prefctl a2 ; isync // ensure XSR.PREFCTL;ISYNC wholly within an icache line
-# else
- xsr.prefctl a2
-# endif
-# else
- movi a2, 0
-# endif
- abi_return
- endfunc
-
-//----------------------------------------------------------------------
-
-#endif
-#if defined(__SPLIT__set_cache_prefetch_nw)
-
-// FOR BACKWARD COMPATIBILITY WITH PRE-RF RELEASE OBJECT CODE ONLY.
-// int xthal_set_cache_prefetch_nw( int )
-SYM(xthal_set_cache_prefetch_nw)
-# if XCHAL_HAVE_PREFETCH
- movi a3, XCHAL_CACHE_PREFCTL_DEFAULT
- addi a4, a2, 1 // does a2 == -1 ?
- moveqz a2, a3, a4 // if yes (XTHAL_PREFETCH_ENABLE), set it to default
- bbci.l a2, 31, 1f // high bit set indicates masked update
- rsr.prefctl a4
- extui a5, a2, 16, 15
- or a4, a4, a5 // set masked bits
- xor a4, a4, a5 // clear masked bits
- and a2, a2, a5 // only use masked bits
- or a2, a4, a2 // combine masked bits
-1:
-# if XCHAL_HW_MIN_VERSION <= XTENSA_HWVERSION_RC_2010_1 /* for erratum #325 */
- j 1f ; .align 8 ; 1: xsr.prefctl a2 ; isync // ensure XSR.PREFCTL;ISYNC wholly within an icache line
-# else
- xsr.prefctl a2
-# endif
-# else
- movi a2, 0
-# endif
- ret
- endfunc
-
-//----------------------------------------------------------------------
-
-#endif
-#if defined(__SPLIT__get_cache_prefetch)
-
-// Return current cache prefetch state.
-// int xthal_get_cache_prefetch( void )
-SYMBOL(xthal_get_cache_prefetch)
- abi_entry
-# if XCHAL_HAVE_PREFETCH
- rsr.prefctl a2
-# else
- movi a2, 0
-# endif
- abi_return
- endfunc
-
-#endif
-#if defined(__SPLIT__get_cache_prefetch_nw)
-
-// int xthal_get_cache_prefetch_nw( void )
-
-SYM(xthal_get_cache_prefetch_nw)
-# if XCHAL_HAVE_PREFETCH
- rsr.prefctl a2
-# else
- movi a2, 0
-# endif
- ret
- endfunc
-
-//----------------------------------------------------------------------
-// Misc configuration info
-//----------------------------------------------------------------------
-
-// Eventually these will move to their own file:
-#endif
-#if defined(__SPLIT__hw_configid0)
- .set xthals_hw_configid0, XCHAL_HW_CONFIGID0
-#endif
-#if defined(__SPLIT__hw_configid1)
- .set xthals_hw_configid1, XCHAL_HW_CONFIGID1
-#endif
-#if defined(__SPLIT__release_major)
- .set xthals_release_major, XTHAL_RELEASE_MAJOR
-#endif
-#if defined(__SPLIT__release_minor)
- .set xthals_release_minor, XTHAL_RELEASE_MINOR
-
-#endif /*split*/
-
- .global xthals_hw_configid0, xthals_hw_configid1
- .global xthals_release_major, xthals_release_minor
-
-//----------------------------------------------------------------------
-
diff --git a/src/arch/xtensa/up/hal/clock.S b/src/arch/xtensa/up/hal/clock.S
deleted file mode 100644
index f6f43e1..0000000
--- a/src/arch/xtensa/up/hal/clock.S
+++ /dev/null
@@ -1,133 +0,0 @@
-//
-// clock.S - assembly language clock routines
-//
-// $Id: //depot/rel/Eaglenest/Xtensa/OS/hal/clock.S#1 $
-
-// Copyright (c) 2003-2010 Tensilica Inc.
-//
-// Permission is hereby granted, free of charge, to any person obtaining
-// a copy of this software and associated documentation files (the
-// "Software"), to deal in the Software without restriction, including
-// without limitation the rights to use, copy, modify, merge, publish,
-// distribute, sublicense, and/or sell copies of the Software, and to
-// permit persons to whom the Software is furnished to do so, subject to
-// the following conditions:
-//
-// The above copyright notice and this permission notice shall be included
-// in all copies or substantial portions of the Software.
-//
-// THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
-// EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
-// MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
-// IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY
-// CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
-// TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
-// SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
-
-#include <xtensa/coreasm.h>
-
-
-// A useful looping macro:
-// 'iterate' invokes 'what' (an instruction, pseudo-op or other macro)
-// multiple times, passing it a numbered parameter from 'from' to 'to'
-// inclusively. Does not invoke 'what' at all if from > to.
-// Maximum difference between 'from' and 'to' is 99 minus nesting depth
-// (GNU 'as' doesn't allow nesting deeper than 100).
-//
- .macro iterate from, to, what
- .ifeq ((\to-\from) & ~0xFFF)
- \what \from
- iterate "(\from+1)", \to, \what
- .endif
- .endm // iterate
-
-
-//----------------------------------------------------------------------
-// Read CCOUNT register
-//----------------------------------------------------------------------
-
-// unsigned xthal_get_ccount(void)
-//
- .global xthal_get_ccount
- .type xthal_get_ccount,@function
- .align 4
-xthal_get_ccount:
- abi_entry
-#if XCHAL_HAVE_CCOUNT
- rsr a2, CCOUNT
-/*
- * The following alternative (in absence of CCOUNT) doesn't work well,
- * because ICOUNT is often used for debugging. (And when it isn't,
- * one would have to ensure that ICOUNTLEVEL is high enough and that
- * ICOUNT is incremented to zero in the debug exception handler upon
- * ICOUNT exceptions.)
- *
- * #elif XCHAL_HAVE_DEBUG
- * rsr a2, ICOUNT // no CCOUNT, return ICOUNT if available
- */
-#else
- movi a2, 0 // else no counter at all, just return zero
-#endif
- abi_return
- .size xthal_get_ccount, . - xthal_get_ccount
-
-
-//----------------------------------------------------------------------
-// Access CCOMPAREn registers
-//----------------------------------------------------------------------
-
-// void xthal_set_ccompare(int, unsigned)
-//
- .global xthal_set_ccompare
- .type xthal_set_ccompare,@function
- .align 4
-xthal_set_ccompare:
- abi_entry
-#if XCHAL_NUM_TIMERS > 0
- bnez a2, 1f
- wsr a3, CCOMPARE_0
-
- .macro set_ccompare_n num
- j 2f
-1:
- bgeui a2, (\num + 1), 1f
- wsr a3, CCOMPARE_0 + \num
- .endm
- iterate 1, XCHAL_NUM_TIMERS-1, set_ccompare_n
-
-2: isync
- isync_retw_nop
-1:
-#endif /* XCHAL_NUM_TIMERS > 0 */
- abi_return
- .size xthal_set_ccompare, . - xthal_set_ccompare
-
-
-// unsigned xthal_get_ccompare(int)
-//
- .global xthal_get_ccompare
- .type xthal_get_ccompare,@function
- .align 4
-xthal_get_ccompare:
- abi_entry
-#if XCHAL_NUM_TIMERS > 0
- bnez a2, 1f
- rsr a2, CCOMPARE_0
- abi_return
-1:
-
- .macro get_ccompare_n num
- bgeui a2, (\num + 1), 1f
- rsr a2, CCOMPARE_0 + \num
- abi_return
-1:
- .endm
- iterate 1, XCHAL_NUM_TIMERS-1, get_ccompare_n
-
-#endif /* XCHAL_NUM_TIMERS > 0 */
- movi a2, 0 // non-existent CCOMPAREn, return 0
-2:
- abi_return
- .size xthal_get_ccompare, . - xthal_get_ccompare
-
-
diff --git a/src/arch/xtensa/up/hal/coherence.c b/src/arch/xtensa/up/hal/coherence.c
deleted file mode 100644
index 39e67a1..0000000
--- a/src/arch/xtensa/up/hal/coherence.c
+++ /dev/null
@@ -1,59 +0,0 @@
-/* coherence.c - Cache coherence opt-in / opt-out functions */
-
-/* $Id: //depot/rel/Eaglenest/Xtensa/OS/hal/coherence.c#1 $ */
-
-/*
- * Copyright (c) 2008 Tensilica Inc.
- *
- * Permission is hereby granted, free of charge, to any person obtaining
- * a copy of this software and associated documentation files (the
- * "Software"), to deal in the Software without restriction, including
- * without limitation the rights to use, copy, modify, merge, publish,
- * distribute, sublicense, and/or sell copies of the Software, and to
- * permit persons to whom the Software is furnished to do so, subject to
- * the following conditions:
- *
- * The above copyright notice and this permission notice shall be included
- * in all copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
- * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
- * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
- * IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY
- * CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
- * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
- * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
- */
-
-#include <xtensa/config/core.h>
-
-
-/*
- * Opt-out of cache coherence.
- *
- * Caveat: on a core with full MMU, cache attribute handling done here only
- * works well with the default (reset) TLB mapping of eight 512MB regions.
- * It likely won't work correctly when other page sizes are in use (it may
- * appear to work but be open to race conditions, depending on situation).
- */
-void xthal_cache_coherence_optout( void )
-{
-#if XCHAL_HAVE_EXTERN_REGS && XCHAL_DCACHE_IS_COHERENT
- unsigned ca = xthal_get_cacheattr();
- /* Writeback all dirty entries. Writethru mode avoids new dirty entries. */
- xthal_set_region_attribute(0,0xFFFFFFFF, XCHAL_CA_WRITETHRU, XTHAL_CAFLAG_EXPAND);
- xthal_dcache_all_writeback();
- /* Invalidate all cache entries. Cache-bypass mode avoids new entries. */
- xthal_set_region_attribute(0,0xFFFFFFFF, XCHAL_CA_BYPASS, XTHAL_CAFLAG_EXPAND);
- xthal_dcache_all_writeback_inv();
- /* Wait for everything to settle. */
- asm("memw");
- xthal_dcache_sync();
- xthal_icache_sync();
- /* Opt-out of cache coherency protocol. */
- xthal_cache_coherence_off();
- /* Restore cache attributes, as of entry to this function. */
- xthal_set_cacheattr(ca);
-#endif
-}
-
diff --git a/src/arch/xtensa/up/hal/debug.c b/src/arch/xtensa/up/hal/debug.c
deleted file mode 100644
index 6b905a0..0000000
--- a/src/arch/xtensa/up/hal/debug.c
+++ /dev/null
@@ -1,526 +0,0 @@
-//
-// debug.c - debug related constants and functions
-//
-// $Id: //depot/rel/Eaglenest/Xtensa/OS/hal/debug.c#1 $
-
-// Copyright (c) 2002 Tensilica Inc.
-//
-// Permission is hereby granted, free of charge, to any person obtaining
-// a copy of this software and associated documentation files (the
-// "Software"), to deal in the Software without restriction, including
-// without limitation the rights to use, copy, modify, merge, publish,
-// distribute, sublicense, and/or sell copies of the Software, and to
-// permit persons to whom the Software is furnished to do so, subject to
-// the following conditions:
-//
-// The above copyright notice and this permission notice shall be included
-// in all copies or substantial portions of the Software.
-//
-// THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
-// EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
-// MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
-// IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY
-// CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
-// TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
-// SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
-
-#include <xtensa/hal.h>
-#include <xtensa/config/specreg.h>
-#include <xtensa/config/core.h>
-
-
-/* 1 if debug option configured, 0 if not: */
-const int Xthal_debug_configured = XCHAL_HAVE_DEBUG;
-
-/* Number of instruction and data break registers: */
-const int Xthal_num_ibreak = XCHAL_NUM_IBREAK;
-const int Xthal_num_dbreak = XCHAL_NUM_DBREAK;
-
-
-#ifdef INCLUDE_DEPRECATED_HAL_DEBUG_CODE
-/* This array is incorrect: */
-const unsigned short Xthal_ill_inst_16[16] =
-{
-#if XCHAL_HAVE_BE
- 0xfd0f, 0xfd1f, 0xfd2f, 0xfd3f,
- 0xfd4f, 0xfd5f, 0xfd6f, 0xfd7f,
- 0xfd8f, 0xfd9f, 0xfdaf, 0xfdbf,
- 0xfdcf, 0xfddf, 0xfdef, 0xfdff
-#else
- 0xf0fd, 0xf1fd, 0xf2fd, 0xf3fd,
- 0xf4fd, 0xf5fd, 0xf6fd, 0xf7fd,
- 0xf8fd, 0xf9fd, 0xfafd, 0xfbfd,
- 0xfcfd, 0xfdfd, 0xfefd, 0xfffd
-#endif
-};
-#endif /* INCLUDE_DEPRECATED_HAL_DEBUG_CODE */
-
-
-#undef XTHAL_24_BIT_BREAK
-#undef XTHAL_16_BIT_BREAK
-#define XTHAL_24_BIT_BREAK 0x80000000
-#define XTHAL_16_BIT_BREAK 0x40000000
-
-
-
-// set software breakpoint and synchronize cache
-unsigned int
-xthal_set_soft_break(void *addr)
-{
- unsigned inst;
- int is24bit = (xthal_disassemble_size( (unsigned char *)addr ) == 3);
- unsigned int ret_val;
-
-#if XCHAL_HAVE_BE
- inst = ((((char *)addr)[0])<<24) +
- ((((char *)addr)[1])<<16) +
- ((((char *)addr)[2])<<8);
-#else
- inst = ((((char *)addr)[0])) +
- ((((char *)addr)[1])<<8) +
- ((((char *)addr)[2])<<16);
-#endif
-#if XCHAL_HAVE_BE
- if (is24bit) {
- ret_val = XTHAL_24_BIT_BREAK & ((inst>>8)&0xffffff);
- ((unsigned char *)addr)[0] = 0x00;
- ((unsigned char *)addr)[1] = 0x04;
- ((unsigned char *)addr)[2] = 0x00;
- } else {
- ret_val = XTHAL_16_BIT_BREAK & ((inst>>16)&0xffff);
- ((unsigned char *)addr)[0] = 0xD2;
- ((unsigned char *)addr)[1] = 0x0f;
- }
-#else
- if (is24bit) {
- ret_val = XTHAL_24_BIT_BREAK & (inst&0xffffff);
- ((unsigned char *)addr)[0] = 0x00;
- ((unsigned char *)addr)[1] = 0x40;
- ((unsigned char *)addr)[2] = 0x00;
- } else {
- ret_val = XTHAL_16_BIT_BREAK & (inst&0xffff);
- ((unsigned char *)addr)[0] = 0x2D;
- ((unsigned char *)addr)[1] = 0xf0;
- }
-#endif
- *((unsigned int *)addr) = inst;
-#if XCHAL_DCACHE_IS_WRITEBACK
- xthal_dcache_region_writeback((void*)addr, 3);
-#endif
-#if XCHAL_ICACHE_SIZE > 0
- xthal_icache_region_invalidate((void*)addr, 3);
-#endif
- return ret_val;
-}
-
-
-// remove software breakpoint and synchronize cache
-void
-xthal_remove_soft_break(void *addr, unsigned int inst)
-{
-#if XCHAL_HAVE_BE
- if (inst&XTHAL_24_BIT_BREAK) {
- ((unsigned char *)addr)[0] = (inst>>16)&0xff;
- ((unsigned char *)addr)[1] = (inst>>8)&0xff;
- ((unsigned char *)addr)[2] = inst&0xff;
- } else {
- ((unsigned char *)addr)[0] = (inst>>8)&0xff;
- ((unsigned char *)addr)[1] = inst&0xff;
- }
-#else
- ((unsigned char *)addr)[0] = inst&0xff;
- ((unsigned char *)addr)[1] = (inst>>8)&0xff;
- if (inst&XTHAL_24_BIT_BREAK)
- ((unsigned char *)addr)[2] = (inst>>16)&0xff;
-#endif
-#if XCHAL_DCACHE_IS_WRITEBACK
- xthal_dcache_region_writeback((void*)addr, 3);
-#endif
-#if XCHAL_ICACHE_SIZE > 0
- xthal_icache_region_invalidate((void*)addr, 3);
-#endif
-}
-
-
-
-
-#ifdef INCLUDE_DEPRECATED_HAL_DEBUG_CODE
-
-// return instruction type
-unsigned int
-xthal_inst_type(void *addr)
-{
- unsigned int inst_type = 0;
- unsigned inst;
-// unsigned int inst = *((unsigned int *)addr);
- unsigned char op0, op1, op2;
- unsigned char i, m, n, r, s, t, z;
-
-#if XCHAL_HAVE_BE
- inst = ((((char *)addr)[0])<<24) +
- ((((char *)addr)[1])<<16) +
- ((((char *)addr)[2])<<8);
- op0 = inst>>28;
- op1 = (inst>>12)&0xf;
- op2 = (inst>>16)&0xf;
- i = (inst>>27)&0x1;
- z = (inst>>26)&0x1;
- m = (inst>>24)&0x3;
- n = (inst>>26)&0x3;
- r = (inst>>16)&0xf;
- s = (inst>>20)&0xf;
- t = (inst>>24)&0xf;
-#else
- inst = ((((char *)addr)[0])) +
- ((((char *)addr)[1])<<8) +
- ((((char *)addr)[2])<<16);
- op0 = inst&0xf;
- op1 = (inst&0xf0000)>>16;
- op2 = (inst&0xf00000)>>20;
- i = (inst&0x80)>>7;
- z = (inst&0x40)>>6;
- m = (inst&0xc0)>>6;
- n = (inst&0x30)>>4;
- r = (inst&0xf000)>>12;
- s = (inst&0xf00)>>8;
- t = (inst&0xf0)>4;
-#endif
- switch (op0) {
- case 0x0:
- inst_type |= XTHAL_24_BIT_INST;
- if ((op1==0)&&(op2==0))
- switch (r) {
- case 0:
- if (m==0x2) {
- if (!(n&0x2)) // RET, RETW
- inst_type |= XTHAL_RET_INST;
- else if (n==0x2) // JX
- inst_type |= (XTHAL_JUMP_INST|XTHAL_DEST_REG_INST);
- inst_type |= (s<<28);
- } else if (m==3) // CALLX
- inst_type |= (XTHAL_JUMP_INST|XTHAL_DEST_REG_INST);
- inst_type |= (s<<28);
- break;
- case 0x3:
- if (t==0)
- switch (s) {
- case 0x0: // RFE
- inst_type |= XTHAL_RFE_INST;
- break;
- case 0x1: // RFUE
- inst_type |= XTHAL_RFUE_INST;
- break;
- case 0x4: // RFW
- case 0x5:
- inst_type |= XTHAL_RFW_INST;
- break;
- }
- else if (t==1) // RFI
- inst_type |= XTHAL_RFI_INST;
- break;
- case 0x4: // BREAK
- inst_type |= XTHAL_BREAK_INST;
- break;
- case 0x5: // SYSCALL
- inst_type |= XTHAL_SYSCALL_INST;
- break;
- }
- break;
- case 0x5: // CALL
- inst_type |= XTHAL_24_BIT_INST;
- inst_type |= (XTHAL_JUMP_INST|XTHAL_DEST_REL_INST);
- break;
- case 0x6: // B
- inst_type |= XTHAL_24_BIT_INST;
- if (n==0) // J
- inst_type |= (XTHAL_JUMP_INST|XTHAL_DEST_REL_INST);
- else if ((n==0x1)||(n==0x2))
- inst_type |= (XTHAL_BRANCH_INST|XTHAL_DEST_REL_INST);
- else {
- if (m&0x2)
- inst_type |= (XTHAL_BRANCH_INST|XTHAL_DEST_REL_INST);
- else if ((m==0x1)&&((r==0x0)||(r==0x1)))
- inst_type |= (XTHAL_BRANCH_INST|XTHAL_DEST_REL_INST);
- }
- break;
- case 0x7: // B
- inst_type |= XTHAL_24_BIT_INST;
- inst_type |= (XTHAL_BRANCH_INST|XTHAL_DEST_REL_INST);
- break;
-#if XCHAL_HAVE_DENSITY
- case 0x8: // L32I.N
- case 0x9: // S32I.N
- case 0xA: // ADD.N
- case 0xb: // ADDI.N
- inst_type |= XTHAL_16_BIT_INST;
- break;
- case 0xc:
- inst_type |= XTHAL_16_BIT_INST; // MOVI.N BEQZ.N, BNEZ.N
- if (i)
- inst_type |= (XTHAL_BRANCH_INST|XTHAL_DEST_REL_INST);
- break;
- case 0xd: // MOV.N NOP.N
- inst_type |= XTHAL_16_BIT_INST;
- if (r==0xf)
- switch(t) {
- case 0x0:
- case 0x1:
- inst_type |= XTHAL_RET_INST; // RET.N, RETW.N
- break;
- case 0x2:
- inst_type |= XTHAL_BREAK_INST; // BREAK.N
- break;
- }
- break;
-#endif /* XCHAL_HAVE_DENSITY */
- default:
- inst_type |= XTHAL_24_BIT_INST;
- }
- return inst_type;
-}
-
-// returns branch address
-unsigned int
-xthal_branch_addr(void *addr)
-{
- unsigned int b_addr = (unsigned int) addr;
- unsigned inst;
-// unsigned int inst = *((unsigned int *)addr);
- int offset;
- unsigned int inst_type = xthal_inst_type(addr);
- unsigned int inst_type_mask;
-#if XCHAL_HAVE_BE
- inst = ((((char *)addr)[0])<<24) +
- ((((char *)addr)[1])<<16) +
- ((((char *)addr)[2])<<8);
-#else
- inst = ((((char *)addr)[0])) +
- ((((char *)addr)[1])<<8) +
- ((((char *)addr)[2])<<16);
-#endif
-#if XCHAL_HAVE_DENSITY
- inst_type_mask = XTHAL_16_BIT_INST|XTHAL_BRANCH_INST|XTHAL_DEST_REL_INST;
- if ((inst_type&inst_type_mask)==inst_type_mask) {
-# if XCHAL_HAVE_BE
- b_addr += (4+((inst&0x3000000)>>20)+((inst&0xf0000)>>16));
-# else
- b_addr += (4+(inst&0x30)+((inst&0xf000)>>12));
-# endif
- }
-#endif /* XCHAL_HAVE_DENSITY */
- inst_type_mask = XTHAL_24_BIT_INST|XTHAL_BRANCH_INST|XTHAL_DEST_REL_INST;
- if ((inst_type&inst_type_mask)==inst_type_mask) {
-#if XCHAL_HAVE_BE
- if ((inst&0xf0000000)==0x70000000)
- offset = ((int)(inst<<16))>>24;
- else if ((inst&0xf2000000)==0x62000000)
- offset = ((int)(inst<<16))>>24;
- else
- offset = ((int)(inst<<12))>>20;
-#else
- if ((inst&0xf)==0x7)
- offset = ((int)(inst<<8))>>24;
- else if ((inst&0x2f)==0x26)
- offset = ((int)(inst<<8))>>24;
- else
- offset = ((int)(inst<<8))>>20;
-#endif
- b_addr += 4 + offset;
- }
- inst_type_mask = XTHAL_24_BIT_INST|XTHAL_JUMP_INST|XTHAL_DEST_REL_INST;
- if ((inst_type&inst_type_mask)==inst_type_mask) {
-#if XCHAL_HAVE_BE
- if ((inst&0xfc000000)==0x60000000)
- offset = ((int)(inst<<6))>>14;
- else
- {
- b_addr &= 0xfffffffc;
- offset = ((int)(inst<<6))>>12;
- }
-#else
- if ((inst&0x3f)==0x6)
- offset = ((int)(inst<<8))>>14;
- else
- {
- b_addr &= 0xfffffffc;
- offset = ((int)(inst<<8))>>12;
- }
-#endif
- b_addr += 4 + offset;
- }
- return b_addr;
-}
-
-// return pc of next instruction for a given state
-unsigned int xthal_get_npc(XTHAL_STATE *user_state)
-{
- unsigned inst_type;
- unsigned npc;
- inst_type = xthal_inst_type((void *)user_state->pc);
- if (inst_type & XTHAL_24_BIT_INST)
- npc = user_state->pc + 3;
- else
- npc = user_state->pc + 2;
- if (inst_type & XTHAL_RFW_INST) {
- /* Can not debug level 1 interrupts */
- // xt_panic();
- } else if (inst_type & XTHAL_RFUE_INST) {
- /* Can not debug level 1 interrupts */
- // xt_panic();
- } else if (inst_type & XTHAL_RFI_INST) {
- /* Can not debug level 1 interrupts */
- // xt_panic();
- } else if (inst_type & XTHAL_RFE_INST) {
- /* Can not debug level 1 interrupts */
- // xt_panic();
- } else if (inst_type & XTHAL_RET_INST) {
- npc = (user_state->pc&0xc0000000)+(user_state->ar[0]&0x3fffffff);
- } else if (inst_type & XTHAL_BREAK_INST) {
- /* Can not debug break */
- // xt_panic();
- } else if (inst_type & XTHAL_SYSCALL_INST) {
- /* Can not debug exceptions */
- // xt_panic();
- } else if (inst_type & XTHAL_LOOP_END) {
- // xt_panic();
- } else if (inst_type & XTHAL_JUMP_INST) {
- if (inst_type & XTHAL_DEST_REG_INST) {
- return user_state->ar[inst_type>>28];
- } else if (inst_type & XTHAL_DEST_REL_INST) {
- return xthal_branch_addr((void *)user_state->pc);
- }
- } else if (inst_type & XTHAL_BRANCH_INST) {
- int branch_taken = 0;
- unsigned short inst;
- unsigned char op0, t, s, r, m, n;
- memcpy(&inst, (void *)user_state->pc, 2);
-#if XCHAL_HAVE_BE
- op0 = (inst&0xf000)>>12;
- t = (inst&0x0f00)>>8;
- s = (inst&0x00f0)>>4;
- r = (inst&0x000f);
- m = t&3;
- n = t>>2;
-#else
- op0 = (inst&0x000f);
- t = (inst&0x00f0)>>4;
- s = (inst&0x0f00)>>8;
- r = (inst&0xf000)>>12;
- m = t>>2;
- n = t&3;
-#endif
- if (inst_type &XTHAL_16_BIT_INST) {
-#if XCHAL_HAVE_BE
- if (inst&0x400) /* BNEZ.N */
- branch_taken = (user_state->ar[(inst>>4)&0xf]!=0);
- else /* BEQZ.N */
- branch_taken = (user_state->ar[(inst>>4)&0xf]==0);
-#else
- if (inst&0x40) /* BNEZ.N */
- branch_taken = (user_state->ar[(inst>>8)&0xf]!=0);
- else /* BEQZ.N */
- branch_taken = (user_state->ar[(inst>>8)&0xf]==0);
-#endif
- }
- if (op0==0x6) {
- if (n==1) {
- if (m==0) { /* BEQZ */
- branch_taken = (user_state->ar[s]==0);
- } else if (m==1) { /* BNEZ */
- branch_taken = (user_state->ar[s]!=0);
- } else if (m==2) { /* BLTZ */
- branch_taken = (((int)user_state->ar[s])<0);
- } else if (m==3) { /* BGEZ */
- branch_taken = (((int)user_state->ar[s])>=0);
- }
- } else if (n==2) {
- int b4const[16] =
- { -1, 1, 2, 3, 4, 5, 6, 7,
- 8, 10, 12, 16, 32, 62, 128, 256 };
- if (m==0) { /* BEQI */
- branch_taken = (user_state->ar[s]==b4const[r]);
- } else if (m==1) { /* BNEI */
- branch_taken = (user_state->ar[s]!=b4const[r]);
- } else if (m==2) { /* BLTI */
- branch_taken = (((int)user_state->ar[s])<b4const[r]);
- } else if (m==3) { /* BGEI */
- branch_taken = (((int)user_state->ar[s])>=b4const[r]);
- }
- } else if (n==3) {
- int b4constu[16] =
- { 32768, 65536, 2, 3, 4, 5, 6, 7,
- 8, 10, 12, 16, 32, 62, 128, 256 };
- if (m==2) { /* BLTUI */
- branch_taken = (user_state->ar[s]<b4constu[r]);
- } else if (m==3) { /* BGEUI */
- branch_taken = (user_state->ar[s]>=b4constu[r]);
- }
- }
- } else if (op0==0x7) {
- if (r==0) { /* BNONE */
- branch_taken = ((user_state->ar[s]&user_state->ar[t])==0);
- } else if (r==1) { /* BEQ */
- branch_taken = (user_state->ar[s]==user_state->ar[t]);
- } else if (r==2) { /* BLT */
- branch_taken = ((int)user_state->ar[s]<(int)user_state->ar[t]);
- } else if (r==3) { /* BLTU */
- branch_taken = (user_state->ar[s]<user_state->ar[t]);
- } else if (r==4) { /* BALL */
- branch_taken = (((~user_state->ar[s])&user_state->ar[t])==0);
- } else if (r==5) { /* BBC */
-#if XCHAL_HAVE_BE
- branch_taken = ((user_state->ar[s]&(0x80000000>>user_state->ar[t]))==0);
- } else if (r==6) { /* BBCI */
- branch_taken = ((user_state->ar[s]&(0x80000000>>t))==0);
- } else if (r==7) { /* BBCI */
- branch_taken = ((user_state->ar[s]&(0x80000000>>(t+16)))==0);
-#else
- branch_taken = ((user_state->ar[s]&(1<<user_state->ar[t]))==0);
- } else if (r==6) { /* BBCI */
- branch_taken = ((user_state->ar[s]&(1<<t))==0);
- } else if (r==7) { /* BBCI */
- branch_taken = ((user_state->ar[s]&(1<<(t+16)))==0);
-#endif
- } else if (r==8) { /* BANY */
- branch_taken = ((user_state->ar[s]&user_state->ar[t])!=0);
- } else if (r==9) { /* BNE */
- branch_taken = (user_state->ar[s]!=user_state->ar[t]);
- } else if (r==10) { /* BGE */
- branch_taken = ((int)user_state->ar[s]>=(int)user_state->ar[t]);
- } else if (r==11) { /* BGEU */
- branch_taken = (user_state->ar[s]>=user_state->ar[t]);
- } else if (r==12) { /* BNALL */
- branch_taken = (((~user_state->ar[s])&user_state->ar[t])!=0);
- } else if (r==13) { /* BBS */
-#if XCHAL_HAVE_BE
- branch_taken = ((user_state->ar[s]&(0x80000000>>user_state->ar[t]))!=0);
- } else if (r==14) { /* BBSI */
- branch_taken = ((user_state->ar[s]&(0x80000000>>t))!=0);
- } else if (r==15) { /* BBSI */
- branch_taken = ((user_state->ar[s]&(0x80000000>>(t+16)))!=0);
-#else
- branch_taken = ((user_state->ar[s]&(1<<user_state->ar[t]))!=0);
- } else if (r==14) { /* BBSI */
- branch_taken = ((user_state->ar[s]&(1<<t))!=0);
- } else if (r==15) { /* BBSI */
- branch_taken = ((user_state->ar[s]&(1<<(t+16)))!=0);
-#endif
- }
- }
- if (branch_taken) {
- if (inst_type & XTHAL_DEST_REG_INST) {
- return user_state->ar[inst_type>>24];
- } else if (inst_type & XTHAL_DEST_REL_INST) {
- return xthal_branch_addr((void *)user_state->pc);
- }
- }
-#if XCHAL_HAVE_LOOPS
- else if (user_state->lcount && (npc==user_state->lend))
- return user_state->lbeg;
-#endif
- }
- return npc;
-}
-
-#endif /* INCLUDE_DEPRECATED_HAL_DEBUG_CODE */
-
diff --git a/src/arch/xtensa/up/hal/debug_hndlr.S b/src/arch/xtensa/up/hal/debug_hndlr.S
deleted file mode 100644
index 55809d8..0000000
--- a/src/arch/xtensa/up/hal/debug_hndlr.S
+++ /dev/null
@@ -1,147 +0,0 @@
-//
-// debug_hndlr.S -- default Xtensa debug exception handler
-//
-// $Id: //depot/rel/Eaglenest/Xtensa/OS/hal/debug_hndlr.S#1 $
-
-// Copyright (c) 2003-2010 Tensilica Inc.
-//
-// Permission is hereby granted, free of charge, to any person obtaining
-// a copy of this software and associated documentation files (the
-// "Software"), to deal in the Software without restriction, including
-// without limitation the rights to use, copy, modify, merge, publish,
-// distribute, sublicense, and/or sell copies of the Software, and to
-// permit persons to whom the Software is furnished to do so, subject to
-// the following conditions:
-//
-// The above copyright notice and this permission notice shall be included
-// in all copies or substantial portions of the Software.
-//
-// THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
-// EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
-// MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
-// IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY
-// CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
-// TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
-// SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
-
-#include <xtensa/coreasm.h>
-#include <xtensa/config/specreg.h>
-#include <xtensa/config/system.h>
-
-#if XCHAL_HAVE_DEBUG && XCHAL_HAVE_EXCEPTIONS
-
- /*
- * Default debug exception handler.
- *
- * Note that the debug exception vector must save a3
- * in EXCSAVE+XCHAL_DEBUGLEVEL before jumping here.
- *
- * This handler is used when no debugger is present.
- * The end result of executing this default handler
- * is as if no debug exception had occurred, eg. as if
- * the core was running at PS.INTLEVEL >= DEBUGLEVEL.
- *
- * Because the debug exception vector might get
- * placed in ROM, and be expected to work regardless
- * of what executable image or OS is running in RAM,
- * we're very careful not to use any RAM here.
- * We don't know what RAM we can safely use.
- * This tricky part to accomplishing this feat
- * is to use only *one* register (a3, which was
- * saved in EXCSAVE+XCHAL_DEBUGLEVEL), because we don't
- * have RAM in which to safely store other regs.
- *
- * A real debugger application would normally
- * have some kind of conventions, or special
- * hardware support, to have its own RAM workspace
- * in which to save context and do real work
- * in this handler.
- */
-
-
-#if XSHAL_DEBUG_VECTOR_ISROM
- // Debug exception vector is in ROM, so place the handler
- // in ROM also. Otherwise running different executables
- // with that ROM will not work because the handler would
- // likely not be there or be at the wrong address.
- //
- .section .srom.text, "ax"
-#else
- // Debug exception vector is in RAM, so we can safely
- // place the handler in RAM as well.
- //
- .text
-#endif
-
- .global xthal_debugexc_defhndlr_nw
- .align 4
-xthal_debugexc_defhndlr_nw:
- rsr a3, DEBUGCAUSE // get cause of debug exception
-
- // Check for possible debug causes, in priority order.
- // We only handle the highest priority condition present.
- // (If there are multiple conditions, the lower priority
- // condition(s) will normally trigger upon return from
- // this exception handler.)
-
- bbci.l a3, DEBUGCAUSE_ICOUNT_SHIFT, 1f // ICOUNT trap?
- movi a3, 0
- wsr a3, ICOUNT // clear ICOUNT
- j 3f
-
-/*
- * Ensure that we have IBREAKs, otherwise the IBREAKENABLE
- * special register is not there:
- */
-#if XCHAL_NUM_IBREAK > 0
-1: bbci.l a3, DEBUGCAUSE_IBREAK_SHIFT, 1f // IBREAK match?
- movi a3, 0
- wsr a3, IBREAKENABLE // disable IBREAK traps
- j 3f
-#endif
-
-/* Also check for DBREAK registers: */
-#if XCHAL_NUM_DBREAK > 0
-1: bbci.l a3, DEBUGCAUSE_DBREAK_SHIFT, 1f // DBREAK match?
- movi a3, 0
- wsr a3, DBREAKC_0 // disable DBREAK register 0
-# if XCHAL_NUM_DBREAK > 1
- wsr a3, DBREAKC_1 // disable DBREAK register 1
-# endif
- j 3f
-#endif
-
-1: bbci.l a3, DEBUGCAUSE_BREAK_SHIFT, 1f // BREAK instruction?
- //rsr a3, EPC+XCHAL_DEBUGLEVEL // get PC pointing to BREAK
- //l8ui a3, a3, 1 // get first 4-bit operand of BREAK (in 2nd byte)
- //extui a3, a3, (XCHAL_HAVE_BE*4), 4 // pos depends on endianness
- //bnei a3, 1, 3f // is it a BREAK 1,x instruction?
- rsr a3, EPC+XCHAL_DEBUGLEVEL // get PC pointing to BREAK
- addi a3, a3, 3 // skip BREAK instruction
- wsr a3, EPC+XCHAL_DEBUGLEVEL // update PC
- j 3f
-
-1: bbci.l a3, DEBUGCAUSE_BREAKN_SHIFT, 1f // BREAK.N instruction?
- rsr a3, EPC+XCHAL_DEBUGLEVEL // get PC pointing to BREAK
- addi a3, a3, 2 // skip BREAK.N instruction
- wsr a3, EPC+XCHAL_DEBUGLEVEL // update PC
- j 3f
-
-1: bbci.l a3, DEBUGCAUSE_DEBUGINT_SHIFT, 1f // debug interrupt?
- // Nothing to do...
- j 3f
-
-1: // Unknown debug case? ignore
-
-3: rsr a3, EXCSAVE+XCHAL_DEBUGLEVEL // restore a3
- rfi XCHAL_DEBUGLEVEL // return from debug exception
-
- .size xthal_debugexc_defhndlr_nw, . - xthal_debugexc_defhndlr_nw
-
-
-#if XSHAL_DEBUG_VECTOR_ISROM
- .text // in case this gets included by something else
-#endif
-
-#endif /* XCHAL_HAVE_DEBUG */
-
diff --git a/src/arch/xtensa/up/hal/disass.c b/src/arch/xtensa/up/hal/disass.c
deleted file mode 100644
index f262dad..0000000
--- a/src/arch/xtensa/up/hal/disass.c
+++ /dev/null
@@ -1,156 +0,0 @@
-//
-// disass.c - disassembly routines for Xtensa
-//
-// $Id: //depot/rel/Eaglenest/Xtensa/OS/hal/disass.c#1 $
-
-// Copyright (c) 2004-2013 Tensilica Inc.
-//
-// Permission is hereby granted, free of charge, to any person obtaining
-// a copy of this software and associated documentation files (the
-// "Software"), to deal in the Software without restriction, including
-// without limitation the rights to use, copy, modify, merge, publish,
-// distribute, sublicense, and/or sell copies of the Software, and to
-// permit persons to whom the Software is furnished to do so, subject to
-// the following conditions:
-//
-// The above copyright notice and this permission notice shall be included
-// in all copies or substantial portions of the Software.
-//
-// THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
-// EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
-// MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
-// IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY
-// CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
-// TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
-// SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
-
-#include <xtensa/hal.h>
-#include <xtensa/config/core.h>
-
-#ifdef XCHAL_OP0_FORMAT_LENGTHS
-extern const unsigned char Xthal_op0_format_lengths[16];
-#endif
-extern const unsigned char Xthal_byte0_format_lengths[256];
-
-
-#if defined(__SPLIT__op0_format_lengths)
-
-/* Instruction length in bytes as function of its op0 field (first nibble): */
-#ifdef XCHAL_OP0_FORMAT_LENGTHS
-const unsigned char Xthal_op0_format_lengths[16] = {
- XCHAL_OP0_FORMAT_LENGTHS
-};
-#endif
-
-
-#endif
-#if defined(__SPLIT__byte0_format_lengths)
-
-/* Instruction length in bytes as function of its first byte: */
-const unsigned char Xthal_byte0_format_lengths[256] = {
- XCHAL_BYTE0_FORMAT_LENGTHS
-};
-
-
-#endif
-#if defined(__SPLIT__disassemble_size)
-
-//
-// Disassembly is currently not supported in xtensa hal.
-//
-
-int xthal_disassemble_size( unsigned char *instr_buf )
-{
-#ifdef XCHAL_OP0_FORMAT_LENGTHS
- /* Extract op0 field of instruction (first nibble used for decoding): */
-# if XCHAL_HAVE_BE
- int op0 = ((*instr_buf >> 4) & 0xF);
-# else
- int op0 = (*instr_buf & 0xF);
-# endif
- /*return (op0 & 8) ? 2 : 3;*/ /* simple case only works consistently on older hardware */
- return Xthal_op0_format_lengths[op0];
-#else
- return Xthal_byte0_format_lengths[*instr_buf];
-#endif
-}
-
-
-#endif
-#if defined(__SPLIT__disassemble)
-
-/*
- * Note: we make sure to avoid the use of library functions,
- * to minimize dependencies.
- */
-int xthal_disassemble(
- unsigned char *instr_buffer, /* the address of the instructions */
- void *tgt_address, /* where the instruction is to be */
- char *buffer, /* where the result goes */
- unsigned buflen, /* size of buffer */
- unsigned options /* what to display */
- )
-{
-#define OUTC(c) do{ if( p < endp ) *p = c; p++; }while(0)
- int i, n;
- char *p = buffer, *endp = buffer + buflen - 1;
- /*static char *ret = " decoding not supported";*/
- static const char _hexc[16] = "0123456789ABCDEF";
-
- n = xthal_disassemble_size( instr_buffer );
-
- if( options & XTHAL_DISASM_OPT_ADDR ) {
- unsigned addr = (unsigned)tgt_address;
- for( i = 0; i < 8; i++ ) {
- OUTC( _hexc[(addr >> 28) & 0xF] );
- addr <<= 4;
- }
- }
-
- if( options & XTHAL_DISASM_OPT_OPHEX ) {
- if( p > buffer )
- OUTC( ' ' );
- for( i = 0; i < 3; i++ ) {
- if( i < n ) {
- OUTC( _hexc[(*instr_buffer >> 4) & 0xF] );
- OUTC( _hexc[*instr_buffer++ & 0xF] );
- } else {
- OUTC( ' ' );
- OUTC( ' ' );
- }
- OUTC( ' ' );
- }
- }
-
- if( options & XTHAL_DISASM_OPT_OPCODE ) {
- if( p > buffer )
- OUTC( ' ' );
- OUTC( '?' );
- OUTC( '?' );
- OUTC( '?' );
- OUTC( ' ' );
- OUTC( ' ' );
- OUTC( ' ' );
- OUTC( ' ' );
- }
-
- if( options & XTHAL_DISASM_OPT_PARMS ) {
- if( p > buffer )
- OUTC( ' ' );
- OUTC( '?' );
- OUTC( '?' );
- OUTC( '?' );
- }
-
- if( p < endp )
- *p = 0;
- else if( buflen > 0 )
- *endp = 0;
-
- return p - buffer; /* return length needed, even if longer than buflen */
-}
-
-#undef OUTC
-
-
-#endif /*split*/
diff --git a/src/arch/xtensa/up/hal/int_asm.S b/src/arch/xtensa/up/hal/int_asm.S
deleted file mode 100644
index bdaae4a..0000000
--- a/src/arch/xtensa/up/hal/int_asm.S
+++ /dev/null
@@ -1,643 +0,0 @@
-//
-// int_asm.S - assembly language interrupt utility routines
-//
-// $Id: //depot/rel/Eaglenest/Xtensa/OS/hal/int_asm.S#1 $
-
-// Copyright (c) 2003-2010 Tensilica Inc.
-//
-// Permission is hereby granted, free of charge, to any person obtaining
-// a copy of this software and associated documentation files (the
-// "Software"), to deal in the Software without restriction, including
-// without limitation the rights to use, copy, modify, merge, publish,
-// distribute, sublicense, and/or sell copies of the Software, and to
-// permit persons to whom the Software is furnished to do so, subject to
-// the following conditions:
-//
-// The above copyright notice and this permission notice shall be included
-// in all copies or substantial portions of the Software.
-//
-// THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
-// EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
-// MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
-// IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY
-// CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
-// TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
-// SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
-
-#include <xtensa/coreasm.h>
-
-
-/* For Call0 ABI, the xthal... and xthal..._nw versions are identical,
- * so we define both labels for the same function body. The Makefile
- * does not define any of the __SPLIT__..._nw macros if Call0 ABI.
- * Use SYM() when we don't want .type information. */
-
-#if defined (__XTENSA_CALL0_ABI__)
-# define SYMBOL(x) _SYMT(x); _SYMT(x ## _nw)
-#else
-# define SYMBOL(x) _SYMT(x)
-#endif
-
-#if XCHAL_HAVE_INTERRUPTS
-/* Offsets of XtHalVPriState structure members (Xthal_vpri_state variable): */
-#define XTHAL_VPRI_VPRI_OFS 0x00
-#define XTHAL_VPRI_LOCKLEVEL_OFS 0x01
-#define XTHAL_VPRI_LOCKVPRI_OFS 0x02
-#define XTHAL_VPRI_PAD0_OFS 0x03
-#define XTHAL_VPRI_ENABLED_OFS 0x04
-#define XTHAL_VPRI_LOCKMASK_OFS 0x08
-#define XTHAL_VPRI_PAD1_OFS 0x0C
-#define XTHAL_VPRI_ENABLEMAP_OFS 0x10
-#define XTHAL_VPRI_RESOLVEMAP_OFS (0x10+0x40*(XCHAL_NUM_INTLEVELS+1))
-#define XTHAL_VPRI_END_OFS (0x10+0x40*(XCHAL_NUM_INTLEVELS*2+1))
-#endif /* XCHAL_HAVE_INTERRUPTS */
-
-
-#if defined(__SPLIT__get_intenable)
-
-//----------------------------------------------------------------------
-// Access INTENABLE register from C
-//----------------------------------------------------------------------
-
-// unsigned xthal_get_intenable(void)
-//
-_SYMT(xthal_get_intenable)
- abi_entry
-# if XCHAL_HAVE_INTERRUPTS
- rsr a2, INTENABLE
-# else
- movi a2, 0 // if no INTENABLE (no interrupts), tell caller nothing is enabled
-# endif
- abi_return
- endfunc
-
-#endif
-#if defined(__SPLIT__set_intenable)
-
-// void xthal_set_intenable(unsigned)
-//
-_SYMT(xthal_set_intenable)
- abi_entry
-# if XCHAL_HAVE_INTERRUPTS
- wsr a2, INTENABLE
-# endif
- abi_return
- endfunc
-
-
-//----------------------------------------------------------------------
-// Access INTERRUPT, INTSET, INTCLEAR register from C
-//----------------------------------------------------------------------
-
-#endif
-#if defined(__SPLIT__get_interrupt)
-
-// unsigned xthal_get_interrupt(void)
-//
-_SYMT(xthal_get_interrupt)
-_SYMT(xthal_get_intread)
- abi_entry
-# if XCHAL_HAVE_INTERRUPTS
- rsr a2, INTERRUPT
-# else
- movi a2, 0 // if no INTERRUPT (no interrupts), tell caller nothing is pending
-# endif
- abi_return
- endfunc
-
-#endif
-#if defined(__SPLIT__set_intset)
-
-// void xthal_set_intset(unsigned)
-//
-_SYMT(xthal_set_intset)
- abi_entry
-# if XCHAL_HAVE_INTERRUPTS
- wsr a2, INTSET
-# endif
- abi_return
- endfunc
-
-#endif
-#if defined(__SPLIT__set_intclear)
-
-// void xthal_set_intclear(unsigned)
-//
-_SYMT(xthal_set_intclear)
- abi_entry
-# if XCHAL_HAVE_INTERRUPTS
- wsr a2, INTCLEAR
-# endif
- abi_return
- endfunc
-
-
-
-//----------------------------------------------------------------------
-// Virtual PS.INTLEVEL support:
-// allows running C code at virtual PS.INTLEVEL > 0
-// using INTENABLE to simulate the masking that PS.INTLEVEL would do.
-//----------------------------------------------------------------------
-
-
-#endif
-#if defined(__SPLIT__get_vpri)
-
-// unsigned xthal_get_vpri(void);
-
-SYMBOL(xthal_get_vpri)
- abi_entry
-# if XCHAL_HAVE_INTERRUPTS
- movi a2, Xthal_vpri_state
- l8ui a2, a2, XTHAL_VPRI_VPRI_OFS
-# else
- movi a2, 0 // no interrupts, report we're always at level 0
-# endif
- abi_return
- endfunc
-
-
-#endif
-#if defined(__SPLIT__get_vpri_nw)
-
-// unsigned xthal_get_vpri_nw(void);
-
-_SYM(xthal_get_vpri_nw)
-
-# if XCHAL_HAVE_INTERRUPTS
- movi a2, Xthal_vpri_state
- l8ui a2, a2, XTHAL_VPRI_VPRI_OFS
-# else
- movi a2, 0 // no interrupts, report we're always at level 0
-# endif
- ret
- endfunc
-
-
-#endif
-#if defined(__SPLIT__set_vpri_nw)
-
-// unsigned xthal_set_vpri_nw(unsigned)
-//
-// Must be called at PS.INTLEVEL <= 1.
-// Doesn't touch the stack (doesn't reference a1 at all).
-// Normally, PS should be restored with a6 after return from this call
-// (it isn't restored automatically because some exception handlers
-// want to keep ints locked for a while).
-//
-// On entry:
-// a2 = new virtual interrupt priority (0x00 .. 0x1F)
-// a3-a6 = undefined
-// PS.INTLEVEL <= 1
-// On exit:
-// a2 = previous virtual interrupt priority (0x0F .. 0x1F, or 0 if no interrupts)
-// a3-a5 = clobbered
-// a6 = PS as it was on entry
-// PS.INTLEVEL = 1
-// !!!!!!!!! PS.WOE = 0 (but not if there are no interrupts; is this really needed???)
-// INTENABLE = updated according to new vpri
-
-_SYM(xthal_set_vpri_nw)
-
-# if XCHAL_HAVE_INTERRUPTS
- /* Make sure a2 is in the range 0x0F .. 0x1F: */
- movi a3, 0x1F // highest legal virtual interrupt priority
- sub a4, a2, a3 // (a4 = newlevel - maxlevel)
- movgez a2, a3, a4 // newlevel = maxlevel if (newlevel - maxlevel) >= 0
- movi a3, 15 // lowest legal virtual interrupt priority
- sub a4, a2, a3 // (a4 = newlevel - 15)
- movltz a2, a3, a4 // newlevel = 15 if newlevel < 15
-
-xthal_set_vpri_nw_common:
- movi a4, Xthal_vpri_state // address of vpri state structure
-
- /*
- * Lockout interrupts for exclusive access to virtual priority structure
- * while we examine and modify it.
- * Note that we accessed a4 and don't access any further than a6,
- * so we won't cause any spills, so we could leave WOE enabled (if it is),
- * but we clear it because that might be what the caller wants,
- * and is cleaner.
- */
- // Get PS and mask off INTLEVEL:
- rsil a6, 1 // save a6 = PS, set PS.INTLEVEL = 1
-
- // Clear PS.WOE. (Can we get rid of this?!!!!!):
- movi a3, ~0x00040000 // mask to...
- rsr a5, PS // get and save a6 = PS
-//a2,a3,a4,a5,a6
- and a5, a5, a3 // ... clear a5.WOE
- wsr a5, PS // clear PS.WOE
- rsync
-
-//a2,a4,a6
- /* Get mask of interrupts to be turned off at requested level: */
- l32i a5, a4, XTHAL_VPRI_ENABLED_OFS // get the global mask
- addx4 a3, a2, a4 // a3 = a4 + a2*4 (index into enablemap[] array)
-//a2,a3,a4,a5,a6
- l32i a3, a3, XTHAL_VPRI_ENABLEMAP_OFS // get the per-level mask
- and a3, a5, a3 // new INTENABLE value according to new intlevel
- wsr a3, INTENABLE // set it!
-//a2,a4,a6
-
- l8ui a5, a4, XTHAL_VPRI_VPRI_OFS // previous virtual priority
- s8i a2, a4, XTHAL_VPRI_VPRI_OFS // new virtual priority
-
- // Let the caller restore PS:
- //wsr a6, PS // restore PS.INTLEVEL
- //rsync
-
- mov a2, a5 // return previous virtual intlevel
-
-# else /* ! XCHAL_HAVE_INTERRUPTS */
-xthal_set_vpri_nw_common:
-# if XCHAL_HAVE_EXCEPTIONS
- rsr a6, PS // return PS for caller to restore
-# else
- movi a6, 0
-# endif
- movi a2, 0 // no interrupts, report we're always at virtual priority 0
-# endif /* XCHAL_HAVE_INTERRUPTS */
- ret
- endfunc
-
-
-
-// unsigned xthal_set_vpri_intlevel_nw(unsigned);
-//
-// Same as xthal_set_vpri_nw() except that it accepts
-// an interrupt level rather than a virtual interrupt priority.
-// This just converts intlevel to vpri and jumps to xthal_set_vpri_nw.
-
-_SYM(xthal_set_vpri_intlevel_nw)
-# if XCHAL_HAVE_INTERRUPTS
- movi a3, 0x10
- movnez a2, a3, a2 // a2 = (a2 ? 0x10 : 0)
- addi a2, a2, 0x0F // a2 += 0x0F
-# endif
- j xthal_set_vpri_nw_common // set vpri to a2
- endfunc
-
-
-
-
-#endif
-#if defined(__SPLIT__set_vpri)
-
-// unsigned xthal_set_vpri (unsigned newvpri);
-//
-// Normal windowed call (PS.INTLEVEL=0 and PS.WOE=1 on entry and exit).
-// (PS.UM = 0 or 1)
-//
-// Returns previous virtual interrupt priority
-// (0x0F .. 0x1F, or 0 if no interrupts).
-//
-// On entry:
-// a2 = new virtual interrupt priority (0x00 .. 0x1F)
-// On exit:
-// a2 = previous vpri
-// INTENABLE = updated according to new vpri
-
-SYMBOL(xthal_set_vpri)
- abi_entry
-# if XCHAL_HAVE_INTERRUPTS
- /* Make sure a2 is in the range 0x0F .. 0x1F: */
- movi a3, 0x1F // highest legal virtual interrupt priority
- sub a4, a2, a3 // (a4 = newlevel - maxlevel)
- movgez a2, a3, a4 // newlevel = maxlevel if (newlevel - maxlevel) >= 0
- movi a3, 15 // lowest legal virtual interrupt priority
- sub a4, a2, a3 // (a4 = newlevel - 15)
- movltz a2, a3, a4 // newlevel = 15 if newlevel < 15
-
-xthal_set_vpri_common1:
- movi a4, Xthal_vpri_state // address of vpri state structure
-
- /*
- * Lockout interrupts for exclusive access to virtual priority structure
- * while we examine and modify it.
- * Note that we accessed a4 and don't access any further than a6,
- * so we won't cause any spills, so we can leave WOE enabled.
- */
- // Get PS and mask off INTLEVEL:
- rsil a6, 1 // save a6 = PS, set PS.INTLEVEL = 1
-
- l8ui a7, a4, XTHAL_VPRI_VPRI_OFS // previous virtual priority (vpri)
-
- /* Get mask of interrupts to be turned off at requested level: */
- l32i a5, a4, XTHAL_VPRI_ENABLED_OFS // get the global mask
- addx4 a3, a2, a4 // a3 = a4 + a2*4 (index into enablemap[] array)
- l32i a3, a3, XTHAL_VPRI_ENABLEMAP_OFS // get the per-level mask
- s8i a2, a4, XTHAL_VPRI_VPRI_OFS // new virtual priority (in load-slot)
- and a3, a5, a3 // new INTENABLE value according to new intlevel
- wsr a3, INTENABLE // set it!
-
- wsr a6, PS // restore PS.INTLEVEL
- rsync
-
- mov a2, a7 // return previous vpri
-
-# else /* ! XCHAL_HAVE_INTERRUPTS */
- movi a2, 0 // no interrupts, report we're always at virtual priority 0
-# endif /* XCHAL_HAVE_INTERRUPTS */
- abi_return
- endfunc
-
-
-
-// unsigned xthal_set_vpri_intlevel (unsigned intlevel);
-//
-// Equivalent to xthal_set_vpri(XTHAL_VPRI(intlevel,0xF)).
-// This just converts intlevel to vpri and jumps inside xthal_set_vpri.
-
-SYMBOL(xthal_set_vpri_intlevel)
- abi_entry
-# if XCHAL_HAVE_INTERRUPTS
- movi a3, 0x10
- movnez a2, a3, a2 // a2 = (a2 ? 0x10 : 0)
- addi a2, a2, 0x0F // a2 += 0x0F
- j xthal_set_vpri_common1 // set vpri to a2
-# else
- movi a2, 0 // no interrupts, report we're always at virtual priority 0
- abi_return
-# endif
- endfunc
-
-
-
-// unsigned xthal_set_vpri_lock (void);
-//
-// Equivalent to xthal_set_vpri(0x1F);
-// Returns previous virtual interrupt priority.
-//
-_SYMT(xthal_set_vpri_lock)
- abi_entry
-# if XCHAL_HAVE_INTERRUPTS
- movi a2, 0x1F // lock at intlevel 1
- j xthal_set_vpri_common1
-# else
- movi a2, 0 // no interrupts, report we're always at virtual priority 0
- abi_return
-# endif
- endfunc
-
-
-
-#endif
-#if defined(__SPLIT__get_intpending_nw)
-
-// unsigned xthal_get_intpending_nw(void)
-//
-// Of the pending level-1 interrupts, returns
-// the bitmask of interrupts at the highest software priority,
-// and the index of the first of these.
-// It also disables interrupts of that software priority and lower
-// via INTENABLE.
-//
-// On entry:
-// a0 = return PC
-// a1 = sp
-// a2-a6 = (available) (undefined)
-// PS.INTLEVEL = 1
-// PS.WOE = 0
-// On exit:
-// a0 = return PC
-// a1 = sp (NOTE: stack is untouched, a1 is never referenced)
-// a2 = index of first highest-soft-pri pending l1 interrupt (0..31), or -1 if none
-// a3 = bitmask of highest-soft-pri pending l1 interrupts (0 if none) (may be deprecated)
-// a4 = (clobbered)
-// a5 = new vpri (not typically used by caller? so might get deprecated...?)
-// a6 = old vpri (eg. to be saved as part of interrupt context's state)
-// INTENABLE = updated according to new vpri
-// INTERRUPT bit cleared for interrupt returned in a2 (if any), if software or edge-triggered or write-error
-// all others = preserved
-
-_SYM(xthal_get_intpending_nw)
-# if XCHAL_HAVE_INTERRUPTS
- // Give us one more register to play with
- //wsr a4, EXCSAVE_1
-
- // Figure out which interrupt to process
-
- /*
- Perform a binary search to find a mask of the interrupts that are
- ready at the highest virtual priority level.
- Xthal_vpri_resolvemap is a binary tree implemented within an array,
- sorted by priority: each node contains the set of interrupts in
- the range of priorities corresponding to the right half of its branch.
- The mask of enabled & pending interrupts is compared with each node to
- determine in which subbranch (left or right) the highest priority one is
- present. After 4 such masks and comparisons (for 16 priorities), we have
- determined the priority of the highest priority enabled&pending interrupt.
-
- Table entries for intlevel 'i' are bitmasks defined as follows (map=Xthal_vpri_resolvemap[i-1]):
- map[8+(x=0)] = ints at pri x + 8..15 (8-15)
- map[4+(x=0,8)] = ints at pri x + 4..7 (4-7,12-15)
- map[2+(x=0,4,8,12)] = ints at pri x + 2..3 (2-3,6-7,10-11,14-15)
- map[1+(x=0,2..12,14)] = ints at pri x + 1 (1,3,5,7,9,11,13,15)
- map[0] = 0 (unused; for alignment)
- */
-
- rsr a4, INTERRUPT // a4 = mask of interrupts pending, including those disabled
- rsr a2, INTENABLE // a2 = mask of interrupts enabled
- movi a3, Xthal_vpri_state
- and a4, a2, a4 // a4 = mask of enabled interrupts pending
- beqz a4, gipfail // if none (can happen for spurious level-triggered interrupts,
- // or ???), we're done
-
- mov a5, a3
- l32i a2, a5, XTHAL_VPRI_RESOLVEMAP_OFS+8*4
- bnone a2, a4, 1f
- addi a5, a5, 8*4
-1: l32i a2, a5, XTHAL_VPRI_RESOLVEMAP_OFS+4*4
- bnone a2, a4, 1f
- addi a5, a5, 4*4
-1: l32i a2, a5, XTHAL_VPRI_RESOLVEMAP_OFS+2*4
- bnone a2, a4, 1f
- addi a5, a5, 2*4
-1: l32i a2, a5, XTHAL_VPRI_RESOLVEMAP_OFS+1*4
- bnone a2, a4, 1f
- addi a5, a5, 1*4
-1:
-
-# if 0
- a5 = address of map ...
- l32i a2, a5, XTHAL_VPRI_RESOLVEMAP_OFS+8*4
- addi a?, a5, 8*4
- and a2, a2, a4
- movnez a5, a?, a2
- l32i a2, a5, XTHAL_VPRI_RESOLVEMAP_OFS+4*4
- addi a?, a5, 4*4
- and a2, a2, a4
- movnez a5, a?, a2
- l32i a2, a5, XTHAL_VPRI_RESOLVEMAP_OFS+2*4
- addi a?, a5, 2*4
- and a2, a2, a4
- movnez a5, a?, a2
- l32i a2, a5, XTHAL_VPRI_RESOLVEMAP_OFS+1*4
- addi a?, a5, 1*4
- and a2, a2, a4
- movnez a5, a?, a2
-# endif
-
- // Here:
- // a3 = Xthal_vpri_state
- // a5 = Xthal_vpri_state + softpri*4
- // a4 = mask of enabled interrupts pending
- // a2,a6 = available
-
- // Lock interrupts during virtual priority data structure transaction:
- //rsil a6, 1 // set PS.INTLEVEL = 1 (a6 ignored)
- // a2,a6 = available
-
- // The highest priority interrupt(s) in a4 is at softpri = (a5-a3) / 4.
- // So interrupts in enablemap[1][softpri] are not in a4 (they are higher priority).
- // The set of interrupts at softpri are:
- // enablemap[1][softpri-1] - enablemap[1][softpri]
- // So and'ing a4 with enablemap[1][softpri - 1] will give us
- // the set of interrupts pending at the highest soft priority.
- //
- l32i a2, a5, XTHAL_VPRI_ENABLEMAP_OFS + 16*4 - 4 // get enablemap[1][softpri-1]
- and a4, a2, a4 // only keep interrupts of highest pri (softpri)
-
- // a4 now has mask of pending interrupts at highest ready level (new vpri)
-
- // Update INTENABLE for this new virtual priority
- l32i a2, a5, XTHAL_VPRI_ENABLEMAP_OFS + 16*4 // get vpri-specific mask = enablemap[1][softpri]
- l32i a6, a3, XTHAL_VPRI_ENABLED_OFS // get global mask
- sub a5, a5, a3 // a5 = softpri * 4 (for below; here for efficiency)
- and a2, a2, a6 // and together
- wsr a2, INTENABLE // disable interrupts at or below new vpri
- // a2,a6 = available
-
- // Update new virtual priority:
- l8ui a6, a3, XTHAL_VPRI_VPRI_OFS // get old vpri (returned)
- srli a5, a5, 2 // a5 = softpri (0..15)
- addi a5, a5, 0x10 // a5 = 0x10 + softpri = new virtual priority
- s8i a5, a3, XTHAL_VPRI_VPRI_OFS // store new vpri (returned)
-
- // Undo the temporary lock (if was at PS.INTLEVEL > 1):
- //rsil a2, 1
-
- mov a3, a4 // save for the caller (in case it wants it?)
-
- // Choose one of the set of highest-vpri pending interrupts to process.
- // For speed (and simplicity), use this simple two-instruction sequence
- // to select the least significant bit set in a4. This implies that
- // interrupts with a lower interrupt number take precedence over those
- // with a higher interrupt number (!!).
- //
- neg a2, a4 // keep only the least-significant bit that is set...
- and a4, a2, a4 // ... in a4
-
- // Software, edge-triggered, and write-error interrupts are cleared by writing to the
- // INTCLEAR pseudo-reg (to clear relevant bits of the INTERRUPT register).
- // To simplify interrupt handlers (so they avoid tracking which type of
- // interrupt they handle and act accordingly), clear such interrupts here.
- // To avoid race conditions, the clearing must occur *after* we undertake
- // to process the interrupt, and *before* actually handling the interrupt.
- // Interrupt handlers may additionally clear the interrupt themselves
- // at appropriate points if needed to avoid unnecessary interrupts.
- //
-#define CLEARABLE_INTLEVEL1_MASK (XCHAL_INTLEVEL1_MASK & XCHAL_INTCLEARABLE_MASK)
-# if CLEARABLE_INTLEVEL1_MASK != 0
- //movi a2, CLEARABLE_INTLEVEL1_MASK
- //and a2, a2, a4
- //wsr a2, INTCLEAR
- wsr a4, INTCLEAR // no effect if a4 not a software or edge-triggered or write-error interrupt
-# endif
-
- // Convert the single-bit interrupt mask to an interrupt number.
- // (ie. compute log2 using either the NSAU instruction or a binary search)
-
- find_ms_setbit a2, a4, a2, 0 // set a2 to index of lsbit set in a4 (0..31)
- // NOTE: assumes a4 != 0 (otherwise a2 is undefined[?])
-
- // a2 has vector number (0..31)
-
- //rsr a4, EXCSAVE_1
- ret
-
-gipfail:
- l8ui a6, a3, XTHAL_VPRI_VPRI_OFS // get old vpri
- mov a5, a6 // is also new vpri (unchanged)
-# else /* XCHAL_HAVE_INTERRUPTS */
- // No interrupts configured!
- movi a5, 0 // return zero new vpri
- movi a6, 0 // return zero old vpri
-# endif /* XCHAL_HAVE_INTERRUPTS */
- movi a2, -1 // return bogus vector number (eg. can be quickly tested for negative)
- movi a3, 0 // return zero bitmask of interrupts pending
- ret
- endfunc
-
-// -----------------------------------------------------------------
-
-#endif
-#if defined(__SPLIT__vpri_lock)
-
-// void xthal_vpri_lock()
-//
-// Used internally by the Core HAL to block interrupts of higher or equal
-// priority than Xthal_vpri_locklevel during virtual interrupt operations.
-//
-_SYMT(xthal_vpri_lock)
- abi_entry
-# if XCHAL_HAVE_INTERRUPTS
- rsil a6, 1 // save a6 = PS, set PS.INTLEVEL = 1
-
- // if( Xthal_vpri_level < Xthal_vpri_locklevel )
- //
- movi a2, Xthal_vpri_state // a2 := address of global var. Xthal_vpri_state
- //interlock
- l8ui a3, a2, XTHAL_VPRI_VPRI_OFS // a3 := Xthal_vpri_level == Xthal_vpri_state.vpri
- l8ui a5, a2, XTHAL_VPRI_LOCKLEVEL_OFS // a5 := Xthal_vpri_locklevel
- l32i a4, a2, XTHAL_VPRI_ENABLED_OFS // a4 := Xthal_vpri_enabled
- bgeu a3, a5, xthal_vpri_lock_done
-
- // xthal_set_intenable( Xthal_vpri_enablemap[0][Xthal_vpri_locklevel] & Xthal_vpri_enabled );
- //
- addx4 a3, a5, a2 // a3 := a2 + a5*4 (index into enablemap[] array)
- l32i a3, a3, XTHAL_VPRI_ENABLEMAP_OFS // a3 := Xthal_vpri_enablemap[0][Xthal_vpri_locklevel]
- //interlock
- and a2, a4, a3
- wsr a2, INTENABLE
-
-xthal_vpri_lock_done:
- wsr a6, PS // restore PS.INTLEVEL
- rsync
-# endif
- abi_return
- endfunc
-
-#endif
-#if defined(__SPLIT__vpri_unlock)
-
-// void xthal_vpri_unlock(void)
-//
-// Enable interrupts according to the current virtual interrupt priority.
-// This effectively "unlocks" interrupts disabled by xthal_vpri_lock()
-// (assuming the virtual interrupt priority hasn't changed).
-//
-_SYMT(xthal_vpri_unlock)
- abi_entry
-# if XCHAL_HAVE_INTERRUPTS
- //
- // This should be free of race-conditions.
- //
- // xthal_set_intenable( Xthal_vpri_enablemap[0][Xthal_vpri_level] & Xthal_vpri_enabled );
- //
- movi a2, Xthal_vpri_state // a2 := address of global var. Xthal_vpri_state
- //interlock
- l8ui a3, a2, XTHAL_VPRI_VPRI_OFS // a3 := Xthal_vpri_level == Xthal_vpri_state.vpri
- l32i a4, a2, XTHAL_VPRI_ENABLED_OFS // a4 := Xthal_vpri_enabled
- addx4 a3, a3, a2 // a3 := a2 + a3*4 (index into enablemap[] array)
- l32i a3, a3, XTHAL_VPRI_ENABLEMAP_OFS // a3 := Xthal_vpri_enablemap[0][Xthal_vpri_level]
- //interlock
- and a2, a4, a3
- wsr a2, INTENABLE
-# endif
- abi_return
- endfunc
-
-#endif /*SPLIT*/
-
diff --git a/src/arch/xtensa/up/hal/interrupts.c b/src/arch/xtensa/up/hal/interrupts.c
deleted file mode 100644
index f8892a3..0000000
--- a/src/arch/xtensa/up/hal/interrupts.c
+++ /dev/null
@@ -1,844 +0,0 @@
-//
-// interrupts.c - interrupts related constants and functions
-//
-// $Id: //depot/rel/Eaglenest/Xtensa/OS/hal/interrupts.c#1 $
-
-// Copyright (c) 2002-2004 Tensilica Inc.
-//
-// Permission is hereby granted, free of charge, to any person obtaining
-// a copy of this software and associated documentation files (the
-// "Software"), to deal in the Software without restriction, including
-// without limitation the rights to use, copy, modify, merge, publish,
-// distribute, sublicense, and/or sell copies of the Software, and to
-// permit persons to whom the Software is furnished to do so, subject to
-// the following conditions:
-//
-// The above copyright notice and this permission notice shall be included
-// in all copies or substantial portions of the Software.
-//
-// THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
-// EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
-// MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
-// IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY
-// CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
-// TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
-// SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
-
-#include <xtensa/config/core.h>
-#include <xtensa/config/specreg.h>
-
-#if XCHAL_HAVE_INTERRUPTS
-
-/* For internal use by the HAL: */
-// static void xthal_vpri_lock(void);
-// static void xthal_vpri_unlock(void);
-extern void xthal_vpri_lock(void);
-extern void xthal_vpri_unlock(void);
-
-
-/*
- * Definitions:
- *
- * Virtual interrupt level = 0 .. 0xFF
- *
- * ...
- */
-
-#define XTHAL_DEFAULT_SOFTPRI 4 /* default software priority (range 0..15) */
- /* IMPORTANT: if you change this, you also
- need to update the initial resolvemap[]
- value below... */
-
-/*
- * Macros to convert between:
- * intlevel (0..15) and software priority within an intlevel (0..15)
- * and
- * virtual interrupt priority (0..0xFF), which is a combination of the above two.
- */
-#define XTHAL_VPRI_INTLEVEL(vpri) (((vpri) >> 4) & 0xF)
-#define XTHAL_VPRI_SOFTPRI(vpri) ((vpri) & 0xF)
-#define XTHAL_VPRI(intlevel,softpri) ((((intlevel)&0xF)<<4)|((softpri)&0xF))
-
-
-/*
- * Virtual priority management data structures.
- * This structure is instantiated as Xthal_vpri_state (below).
- *
- * IMPORTANT: if you change anything in this structure,
- * you must accordingly change structure offsets
- * defined in int_asm.S .
- *
- * IMPORTANT: the worst-case offset of the resolvemap[] field is 976 bytes
- * (0x10 + 0x40*15), which is accessed in int_asm.S at a further
- * offset of 8*4==32 for a total offset of 1008, very close
- * to l32i's offset limit of 1020. So you can't push it much
- * further.
- *
- * [INTERNAL NOTE: There might be a trick that will save 64 bytes,
- * if really needed, by trimming 15 word entries from the start
- * of enablemap[] ... -MG]
- */
-typedef struct XtHalVPriState {
- /*
- * Current virtual interrupt priority (0x0F .. 0xFF)
- * (or actually, 0x0F .. XCHAL_NUM_INTLEVELS*0x10+0x0F).
- * Virtual priorities 0x00 to 0x0E are mapped to 0x0F (they're all
- * equivalent, because there's no such thing as a level 0 interrupt),
- * which may help optimize the size of enablemap[] in the future.
- * Virtual priorities above XCHAL_NUM_INTLEVELS*0x10+0x0F are
- * mapped to XCHAL_NUM_INTLEVELS*0x10+0x0F, which is equivalent.
- *
- * NOTE: this variable is actually part of the processor context,
- * which means (for most OSes) that it must be saved
- * in the task control block along with other register state.
- */
- unsigned char vpri; // current virtual interrupt priority (0x0F..0xFF)
- unsigned char locklevel; // real interrupt level used to get exclusive
- // access to this structure; MUST be at least one (1)
- unsigned char lockvpri; // virtual interrupt level used to get exclusive
- // access to this structure; MUST be XTHAL_VPRI(locklevel,15)
- // (so it's at least 0x1F); placed here for efficiency
- unsigned char pad0; // (alignment padding, unused)
-
- unsigned enabled; // mask of which interrupts are enabled, regardless of level
- // (level masking is applied on top of this)
-
- unsigned lockmask; // (unused?) INTENABLE value used to lock out
- // interrupts for exclusive access to this structure
-
- unsigned pad1; // (alignment padding, unused)
-
- /*
- * For each virtual interrupt priority, this array provides the
- * bitmask of interrupts of greater virtual priority
- * (ie. the set of interrupts to enable at that virtual priority,
- * if all interrupts were enabled in field 'enabled').
- */
- unsigned enablemap[XCHAL_NUM_INTLEVELS+1][16];
-
- /*
- * Table entries for intlevel 'i' are bitmasks defined as follows,
- * with map == Xthal_vpri_resolvemap[i-1]:
- * map[8+(x=0)] = ints at pri x + 8..15 (8-15)
- * map[4+(x=0,8)] = ints at pri x + 4..7 (4-7,12-15)
- * map[2+(x=0,4,8,12)] = ints at pri x + 2..3 (2-3,6-7,10-11,14-15)
- * map[1+(x=0,2..12,14)] = ints at pri x + 1 (1,3,5,7,9,11,13,15)
- * map[0] = 0 (unused; for alignment)
- */
- unsigned resolvemap[XCHAL_NUM_INTLEVELS][16];
-
-} XtHalVPriState;
-
-
-extern XtHalVPriState Xthal_vpri_state;
-extern unsigned char Xthal_int_vpri[32];
-extern XtHalVoidFunc * Xthal_tram_trigger_fn;
-
-extern void xthal_null_func(void);
-
-/* Shorthand for structure members: */
-#define Xthal_vpri_level Xthal_vpri_state.vpri
-#define Xthal_vpri_locklevel Xthal_vpri_state.locklevel
-#define Xthal_vpri_lockvpri Xthal_vpri_state.lockvpri
-#define Xthal_vpri_enabled Xthal_vpri_state.enabled
-#define Xthal_vpri_lockmask Xthal_vpri_state.lockmask // unused?
-#define Xthal_vpri_enablemap Xthal_vpri_state.enablemap
-#define Xthal_vpri_resolvemap Xthal_vpri_state.resolvemap
-#if 0
-Combined refs:
- - enablemap, vpri, enabled (xthal_set_vpri[_nw])
- - enablemap, vpri, enabled, resolvemap (xthal_get_intpending_nw)
- - enablemap, vpri, enabled, locklevel (xthal_vpri_lock)
- - enablemap, vpri, enabled (xthal_vpri_unlock)
-#endif
-
-#endif /* XCHAL_HAVE_INTERRUPTS */
-
-
-
-#if defined(__SPLIT__num_intlevels)
-
-// the number of interrupt levels
-const unsigned char Xthal_num_intlevels = XCHAL_NUM_INTLEVELS;
-
-#endif
-#if defined(__SPLIT__num_interrupts)
-
-// the number of interrupts
-const unsigned char Xthal_num_interrupts = XCHAL_NUM_INTERRUPTS;
-
-#endif
-#if defined(__SPLIT__excm_level)
-
-// the highest level of interrupts masked by PS.EXCM (if XEA2)
-const unsigned char Xthal_excm_level = XCHAL_EXCM_LEVEL;
-
-#endif
-#if defined(__SPLIT__intlevel_mask)
-
-// mask of interrupts at each intlevel
-const unsigned Xthal_intlevel_mask[16] = {
- XCHAL_INTLEVEL_MASKS
-};
-
-
-#endif
-#if defined(__SPLIT__intlevel_andbelow_mask)
-
-// mask for level 1 to N interrupts
-const unsigned Xthal_intlevel_andbelow_mask[16] = {
- XCHAL_INTLEVEL_ANDBELOW_MASKS
-};
-
-
-#endif
-#if defined(__SPLIT__intlevel)
-
-// level per interrupt
-const unsigned char Xthal_intlevel[32] = {
- XCHAL_INT_LEVELS
-};
-
-
-#endif
-#if defined(__SPLIT__inttype)
-
-// type of each interrupt
-const unsigned char Xthal_inttype[32] = {
- XCHAL_INT_TYPES
-};
-
-
-#endif
-#if defined(__SPLIT__inttype_mask)
-
-const unsigned Xthal_inttype_mask[XTHAL_MAX_INTTYPES] = {
- XCHAL_INTTYPE_MASKS
-};
-
-
-#endif
-#if defined(__SPLIT__timer_interrupt)
-
-// interrupts assigned to each timer (CCOMPARE0 to CCOMPARE3), -1 if unassigned
-const int Xthal_timer_interrupt[XTHAL_MAX_TIMERS] = {
- XCHAL_TIMER_INTERRUPTS
-};
-
-
-#endif
-#if defined(__SPLIT__vpri)
-
-#if XCHAL_HAVE_INTERRUPTS
-
-/*
- * Note: this structure changes dynamically at run-time,
- * but is initialized here for efficiency and simplicity,
- * according to configuration.
- */
-XtHalVPriState Xthal_vpri_state = {
- 0x00, /* vpri */
- 1, /* locklevel */
- 0x1F, /* lockvpri */
- 0, /* pad0 */
- 0x00000000, /* enabled */
- 0x00000000, /* lockmask (unused?) */
- 0, /* pad1 */
-
-#define DEFAULT_ENABLEMAP(levela,levelb) \
- { (XCHAL_INTLEVEL15_ANDBELOW_MASK & ~(XTHAL_DEFAULT_SOFTPRI > 0 ? levela : levelb)), \
- (XCHAL_INTLEVEL15_ANDBELOW_MASK & ~(XTHAL_DEFAULT_SOFTPRI > 1 ? levela : levelb)), \
- (XCHAL_INTLEVEL15_ANDBELOW_MASK & ~(XTHAL_DEFAULT_SOFTPRI > 2 ? levela : levelb)), \
- (XCHAL_INTLEVEL15_ANDBELOW_MASK & ~(XTHAL_DEFAULT_SOFTPRI > 3 ? levela : levelb)), \
- (XCHAL_INTLEVEL15_ANDBELOW_MASK & ~(XTHAL_DEFAULT_SOFTPRI > 4 ? levela : levelb)), \
- (XCHAL_INTLEVEL15_ANDBELOW_MASK & ~(XTHAL_DEFAULT_SOFTPRI > 5 ? levela : levelb)), \
- (XCHAL_INTLEVEL15_ANDBELOW_MASK & ~(XTHAL_DEFAULT_SOFTPRI > 6 ? levela : levelb)), \
- (XCHAL_INTLEVEL15_ANDBELOW_MASK & ~(XTHAL_DEFAULT_SOFTPRI > 7 ? levela : levelb)), \
- (XCHAL_INTLEVEL15_ANDBELOW_MASK & ~(XTHAL_DEFAULT_SOFTPRI > 8 ? levela : levelb)), \
- (XCHAL_INTLEVEL15_ANDBELOW_MASK & ~(XTHAL_DEFAULT_SOFTPRI > 9 ? levela : levelb)), \
- (XCHAL_INTLEVEL15_ANDBELOW_MASK & ~(XTHAL_DEFAULT_SOFTPRI >10 ? levela : levelb)), \
- (XCHAL_INTLEVEL15_ANDBELOW_MASK & ~(XTHAL_DEFAULT_SOFTPRI >11 ? levela : levelb)), \
- (XCHAL_INTLEVEL15_ANDBELOW_MASK & ~(XTHAL_DEFAULT_SOFTPRI >12 ? levela : levelb)), \
- (XCHAL_INTLEVEL15_ANDBELOW_MASK & ~(XTHAL_DEFAULT_SOFTPRI >13 ? levela : levelb)), \
- (XCHAL_INTLEVEL15_ANDBELOW_MASK & ~(XTHAL_DEFAULT_SOFTPRI >14 ? levela : levelb)), \
- (XCHAL_INTLEVEL15_ANDBELOW_MASK & ~(XTHAL_DEFAULT_SOFTPRI >15 ? levela : levelb)) }
-
- /* Xthal_vpri_enablemap[XCHAL_NUM_INTLEVELS+1][16]: */
- {
- DEFAULT_ENABLEMAP(XCHAL_INTLEVEL0_ANDBELOW_MASK,XCHAL_INTLEVEL0_ANDBELOW_MASK),
-#if XCHAL_NUM_INTLEVELS >= 1
- DEFAULT_ENABLEMAP(XCHAL_INTLEVEL0_ANDBELOW_MASK,XCHAL_INTLEVEL1_ANDBELOW_MASK),
-#endif
-#if XCHAL_NUM_INTLEVELS >= 2
- DEFAULT_ENABLEMAP(XCHAL_INTLEVEL1_ANDBELOW_MASK,XCHAL_INTLEVEL2_ANDBELOW_MASK),
-#endif
-#if XCHAL_NUM_INTLEVELS >= 3
- DEFAULT_ENABLEMAP(XCHAL_INTLEVEL2_ANDBELOW_MASK,XCHAL_INTLEVEL3_ANDBELOW_MASK),
-#endif
-#if XCHAL_NUM_INTLEVELS >= 4
- DEFAULT_ENABLEMAP(XCHAL_INTLEVEL3_ANDBELOW_MASK,XCHAL_INTLEVEL4_ANDBELOW_MASK),
-#endif
-#if XCHAL_NUM_INTLEVELS >= 5
- DEFAULT_ENABLEMAP(XCHAL_INTLEVEL4_ANDBELOW_MASK,XCHAL_INTLEVEL5_ANDBELOW_MASK),
-#endif
-#if XCHAL_NUM_INTLEVELS >= 6
- DEFAULT_ENABLEMAP(XCHAL_INTLEVEL5_ANDBELOW_MASK,XCHAL_INTLEVEL6_ANDBELOW_MASK),
-#endif
-#if XCHAL_NUM_INTLEVELS >= 7
-# error Interrupt levels greater than 6 not currently supported in the HAL interrupt routines.
-#endif
- },
-
- /* Xthal_vpri_resolvemap[XCHAL_NUM_INTLEVELS][16]: */
- {
-#if XCHAL_NUM_INTLEVELS >= 1 /* set for default soft priority of 4: */
- {0,0,0,0, XCHAL_INTLEVEL1_MASK,0,0,0, 0,0,0,0, 0,0,0,0},
-#endif
-#if XCHAL_NUM_INTLEVELS >= 2 /* set for default soft priority of 4: */
- {0,0,0,0, XCHAL_INTLEVEL2_MASK,0,0,0, 0,0,0,0, 0,0,0,0},
-#endif
-#if XCHAL_NUM_INTLEVELS >= 3 /* set for default soft priority of 4: */
- {0,0,0,0, XCHAL_INTLEVEL3_MASK,0,0,0, 0,0,0,0, 0,0,0,0},
-#endif
-#if XCHAL_NUM_INTLEVELS >= 4 /* set for default soft priority of 4: */
- {0,0,0,0, XCHAL_INTLEVEL4_MASK,0,0,0, 0,0,0,0, 0,0,0,0},
-#endif
-#if XCHAL_NUM_INTLEVELS >= 5 /* set for default soft priority of 4: */
- {0,0,0,0, XCHAL_INTLEVEL5_MASK,0,0,0, 0,0,0,0, 0,0,0,0},
-#endif
-#if XCHAL_NUM_INTLEVELS >= 6 /* set for default soft priority of 4: */
- {0,0,0,0, XCHAL_INTLEVEL6_MASK,0,0,0, 0,0,0,0, 0,0,0,0},
-#endif
-#if XCHAL_NUM_INTLEVELS >= 7 /* set for default soft priority of 4: */
-# error Interrupt levels greater than 6 not currently supported in the HAL interrupt routines.
-#endif
- }
-
-};
-
-
-/*
- * Virtual (software) priority (0x00..0xFF) of each interrupt.
- * This isn't referenced by assembler.
- */
-unsigned char Xthal_int_vpri[32] = {
-#define DEFAULT_INTVPRI(level) (level ? ((level << 4) | XTHAL_DEFAULT_SOFTPRI) : 0)
- DEFAULT_INTVPRI( XCHAL_INT0_LEVEL ),
- DEFAULT_INTVPRI( XCHAL_INT1_LEVEL ),
- DEFAULT_INTVPRI( XCHAL_INT2_LEVEL ),
- DEFAULT_INTVPRI( XCHAL_INT3_LEVEL ),
- DEFAULT_INTVPRI( XCHAL_INT4_LEVEL ),
- DEFAULT_INTVPRI( XCHAL_INT5_LEVEL ),
- DEFAULT_INTVPRI( XCHAL_INT6_LEVEL ),
- DEFAULT_INTVPRI( XCHAL_INT7_LEVEL ),
- DEFAULT_INTVPRI( XCHAL_INT8_LEVEL ),
- DEFAULT_INTVPRI( XCHAL_INT9_LEVEL ),
- DEFAULT_INTVPRI( XCHAL_INT10_LEVEL ),
- DEFAULT_INTVPRI( XCHAL_INT11_LEVEL ),
- DEFAULT_INTVPRI( XCHAL_INT12_LEVEL ),
- DEFAULT_INTVPRI( XCHAL_INT13_LEVEL ),
- DEFAULT_INTVPRI( XCHAL_INT14_LEVEL ),
- DEFAULT_INTVPRI( XCHAL_INT15_LEVEL ),
- DEFAULT_INTVPRI( XCHAL_INT16_LEVEL ),
- DEFAULT_INTVPRI( XCHAL_INT17_LEVEL ),
- DEFAULT_INTVPRI( XCHAL_INT18_LEVEL ),
- DEFAULT_INTVPRI( XCHAL_INT19_LEVEL ),
- DEFAULT_INTVPRI( XCHAL_INT20_LEVEL ),
- DEFAULT_INTVPRI( XCHAL_INT21_LEVEL ),
- DEFAULT_INTVPRI( XCHAL_INT22_LEVEL ),
- DEFAULT_INTVPRI( XCHAL_INT23_LEVEL ),
- DEFAULT_INTVPRI( XCHAL_INT24_LEVEL ),
- DEFAULT_INTVPRI( XCHAL_INT25_LEVEL ),
- DEFAULT_INTVPRI( XCHAL_INT26_LEVEL ),
- DEFAULT_INTVPRI( XCHAL_INT27_LEVEL ),
- DEFAULT_INTVPRI( XCHAL_INT28_LEVEL ),
- DEFAULT_INTVPRI( XCHAL_INT29_LEVEL ),
- DEFAULT_INTVPRI( XCHAL_INT30_LEVEL ),
- DEFAULT_INTVPRI( XCHAL_INT31_LEVEL )
-};
-
-
-#if 0
-/*
- * A number of things may have already been written not calling
- * this function, so it isn't straightforward to start requiring it:
- */
-void xthal_vpri_init( int default_vpri )
-{
- int i, j;
-
- Xthal_vpri_level = 0; /* vpri */
- Xthal_vpri_locklevel = 1; /* locklevel */
- Xthal_vpri_lockvpri = 0x1F; /* lockvpri */
- Xthal_vpri_enabled = 0x00000000; /* enabled */
- Xthal_vpri_lockmask = 0x00000000; /* lockmask (unused?) */
- for( i = 0; i < XCHAL_NUM_INTLEVELS; i++ ) {
- for( j = 0; j < 16; j++ )
- Xthal_vpri_enablemap[i][j] = XCHAL_INTLEVEL15_ANDBELOW_MASK
- & ~Xthal_intlevel_andbelow_mask[i - (j < default_vpri && i > 0)];
- }
- for( i = 1; i < XCHAL_NUM_INTLEVELS; i++ ) {
- for( j = 0; j < 16; j++ )
- Xthal_vpri_resolvemap[i-1][j] = 0;
- if( (default_vpri & 1) != 0 )
- Xthal_vpri_resolvemap[i-1][default_vpri & 0xF] |= Xthal_intlevel_mask[i];
- if( (default_vpri & 2) != 0 )
- Xthal_vpri_resolvemap[i-1][default_vpri & 0xE] |= Xthal_intlevel_mask[i];
- if( (default_vpri & 4) != 0 )
- Xthal_vpri_resolvemap[i-1][default_vpri & 0xC] |= Xthal_intlevel_mask[i];
- if( (default_vpri & 8) != 0 )
- Xthal_vpri_resolvemap[i-1][default_vpri & 0x8] |= Xthal_intlevel_mask[i];
- }
- for( i = 0; i < 32; i++ )
- Xthal_int_vpri[i] = (Xthal_intlevel[i] << 4) | (default_vpri & 0xF);
-}
-#endif /*0*/
-
-void xthal_null_func(void) { }
-XtHalVoidFunc *Xthal_tram_trigger_fn = xthal_null_func;
-
-
-#endif /* XCHAL_HAVE_INTERRUPTS */
-
-
-#endif
-#if defined(__SPLIT__vpri_to_intlevel)
-
-/*
- * xthal_vpri_to_intlevel
- *
- * Converts a virtual interrupt priority to the closest equivalent
- * (equal or higher) interrupt level.
- */
-unsigned xthal_vpri_to_intlevel(unsigned vpri)
-{
-#if XCHAL_HAVE_INTERRUPTS
- return( XTHAL_VPRI_INTLEVEL( vpri ) );
-#else
- return( vpri );
-#endif
-}
-
-#endif
-#if defined(__SPLIT__intlevel_to_vpri)
-
-/*
- * xthal_intlevel_to_vpri
- *
- * Converts an interrupt level to a virtual interrupt priority.
- */
-unsigned xthal_intlevel_to_vpri(unsigned intlevel)
-{
-#if XCHAL_HAVE_INTERRUPTS
- return( XTHAL_VPRI( intlevel, 0xF ) );
-#else
- return( intlevel );
-#endif
-}
-
-
-#endif
-#if defined(__SPLIT__vpri_int_enable)
-
-/*
- * xthal_int_enable
- *
- * Enables given set of interrupts, and returns previous enabled-state of these interrupts.
- */
-unsigned xthal_int_enable(unsigned mask)
-{
-#if XCHAL_HAVE_INTERRUPTS
- unsigned prev_enabled, syncmask;
-
- xthal_vpri_lock();
- prev_enabled = Xthal_vpri_enabled | Xthal_tram_enabled;
-
- /* Figure out which bits must go in Xthal_tram_enabled: */
- syncmask = (mask & Xthal_tram_pending & Xthal_tram_sync);
- if( syncmask != 0 ) {
- Xthal_tram_enabled |= syncmask;
- mask &= ~syncmask;
- /*
- * If we are re-enabling a pending trampolined interrupt,
- * there is a possibility that the level-1 software interrupt
- * is no longer pending, having already occurred (without processing
- * the trampoline because it was disabled). So we have to
- * ensure that the level-1 software interrupt used for trampolining
- * is pending.
- * We let the BSP do this rather than the HAL, because it could
- * potentially use an external level-1 interrupt to trampoline
- * (if proper hardware was available) rather than a software interrupt.
- */
- (*Xthal_tram_trigger_fn)();
- }
- /* The rest go in the global enabled mask: */
- Xthal_vpri_enabled |= mask;
-
- xthal_vpri_unlock(); /* update INTENABLE as per current vpri */
- return( prev_enabled );
-
-#else /* XCHAL_HAVE_INTERRUPTS */
- return( 0 );
-#endif /* XCHAL_HAVE_INTERRUPTS */
-}
-
-#endif
-#if defined(__SPLIT__vpri_int_disable)
-
-/*
- * xthal_int_disable
- *
- * Disables given set of interrupts, and returns previous enabled-state of these interrupts.
- */
-unsigned xthal_int_disable(unsigned mask)
-{
-#if XCHAL_HAVE_INTERRUPTS
- unsigned prev_enabled;
-
- xthal_vpri_lock();
- prev_enabled = Xthal_vpri_enabled | Xthal_tram_enabled;
- Xthal_vpri_enabled &= ~mask;
- Xthal_tram_enabled &= ~mask;
- xthal_vpri_unlock(); /* update INTENABLE as per current vpri */
- return( prev_enabled );
-#else
- return( 0 );
-#endif
-}
-
-
-#endif
-#if defined(__SPLIT__set_vpri_locklevel)
-
-void xthal_set_vpri_locklevel(unsigned intlevel)
-{
-#if XCHAL_HAVE_INTERRUPTS
- if( intlevel < 1 )
- intlevel = 1;
- else if( intlevel > XCHAL_NUM_INTLEVELS )
- intlevel = XCHAL_NUM_INTLEVELS;
- Xthal_vpri_state.locklevel = intlevel;
- Xthal_vpri_state.lockvpri = XTHAL_VPRI(intlevel, 15);
-#endif
-}
-
-#endif
-#if defined(__SPLIT__get_vpri_locklevel)
-
-unsigned xthal_get_vpri_locklevel(void)
-{
-#if XCHAL_HAVE_INTERRUPTS
- return( Xthal_vpri_state.locklevel );
-#else
- return( 1 ); /* must return at least 1, some OSes assume this */
-#endif
-}
-
-
-#endif
-#if defined(__SPLIT__set_int_vpri)
-
-/*
- * xthal_set_int_vpri (was intSetL1Pri)
- *
- * Set the virtual (software) priority of an interrupt.
- * Note: the intlevel of an interrupt CANNOT be changed -- this is
- * set in hardware according to the core configuration file.
- *
- * intnum interrupt number (0..31)
- * vpri virtual interrupt priority (0..15, or intlevel*16+(0..15) )
- */
-int xthal_set_int_vpri(int intnum, int vpri)
-{
-#if XCHAL_HAVE_INTERRUPTS
- unsigned mask, maskoff, basepri, prevpri, intlevel, *maskp, i;
-
- /*
- * Verify parameters:
- */
- if( (unsigned)intnum >= XCHAL_NUM_INTERRUPTS || (unsigned)vpri > 0xFF )
- return( 0 ); /* error: bad parameter(s) */
- /*
- * If requested priority specifies an intlevel, it must match that
- * of the interrupt specified; otherwise (0..15) the proper intlevel of
- * the specified interrupt is assumed, and added to the parameter:
- */
- intlevel = Xthal_intlevel[intnum]; /* intnum's intlevel */
- if( intlevel == 0 || intlevel > XCHAL_NUM_INTLEVELS )
- return( 0 ); /* error: no support for setting priority of NMI etc. */
- basepri = intlevel << 4; /* intnum's base soft-pri. */
- if( vpri > 0x0F ) { /* intlevel portion given? */
- if( (vpri & 0xF0) != basepri ) /* then it must be correct */
- return( 0 ); /* error: intlevel mismatch */
- vpri &= 0x0F; /* remove it */
- }
-
- mask = 1L << intnum;
-
- /*
- * Lock interrupts during virtual priority data structure updates:
- */
- xthal_vpri_lock();
-
- /*
- * Update virtual priority of 'intnum':
- */
- prevpri = Xthal_int_vpri[intnum]; /* save for return value */
- Xthal_int_vpri[intnum] = basepri | vpri;
- /* This interrupt must only be enabled at virtual priorities lower than its own: */
- for( i = 0; i < vpri; i++ )
- Xthal_vpri_enablemap[0][basepri++] |= mask;
- maskoff = ~mask;
- for( ; i <= 0x0F; i++ )
- Xthal_vpri_enablemap[0][basepri++] &= maskoff;
-
- /*
- * Update the prioritization table used to resolve priorities by binary search:
- */
- /* Remove interrupt <intnum> from prioritization table: */
- maskp = Xthal_vpri_resolvemap[intlevel-1];
- for (i=0; i<16; i++)
- maskp[i] &= maskoff;
- /* Add interrupt <intnum> to prioritization table at its (new) given priority: */
- if( vpri & 0x1 )
- maskp[vpri] |= mask;
- if( vpri & 0x2 )
- maskp[vpri & 0xE] |= mask;
- if( vpri & 0x4 )
- maskp[vpri & 0xC] |= mask;
- if( vpri & 0x8 )
- maskp[vpri & 0x8] |= mask;
-
- /*
- * Unlock interrupts (back to current level) and update INTENABLE:
- */
- xthal_vpri_unlock();
-
- return( prevpri );
-#else /* XCHAL_HAVE_INTERRUPTS */
- return( 0 );
-#endif /* XCHAL_HAVE_INTERRUPTS */
-} /* xthal_set_int_vpri */
-
-
-#endif
-#if defined(__SPLIT__get_int_vpri)
-
-int xthal_get_int_vpri(int intnum)
-{
-#if XCHAL_HAVE_INTERRUPTS
- if( (unsigned)intnum >= XCHAL_NUM_INTERRUPTS )
- return( 0 ); /* error: bad parameter */
- return( Xthal_int_vpri[intnum] );
-#else
- return( 0 );
-#endif
-}
-
-
-
-#endif
-#if defined(__SPLIT__trampolines)
-
-
- /*
- SUPPORT FOR TRAMPOLINES
-
- NOTE: trampolining is a special case.
- There are two ways (defined here) to trampoline down
- from a high-level interrupt to a level-one interrupt.
-
- a) Synchronous (restrained) trampolining.
- Trampolining without clearing the high-level interrupt,
- letting the level-one interrupt handler clear the
- source of the interrupt.
- Here the high-level interrupt must be kept disabled
- while trampolining down, and re-enabled after the
- level-one interrupt handler completes.
- This is what one might do to "convert" a high-level
- interrupt into a level-one interrupt.
- The high-level interrupt handler code can be generic.
- [One could argue this type of trampolining isn't required,
- which may? be true...]
- b) Asynchronous (free) trampolining.
- Trampolining when clearing the high-level interrupt
- right away in the high-level interrupt handler.
- Here the high-level interrupt is allowed to remain
- enabled while trampolining occurs. This is very
- useful when some processing must occur with low
- latency, but the rest of the processing can occur
- at lower (eg. level-one) priority. It is particularly
- useful when the lower-priority processing occurs
- for only some of the high-level interrupts.
- Of course this requires custom assembler code to
- handle the high-level interrupt and clear the source
- of the interrupt, so the high-level interrupt handler
- cannot be generic (as opposed to synchronous trampolining).
-
- In both cases, a level-one software interrupt is used
- for trampolining (one could also trampoline from level
- m to n, m > n, n > 1, but that isn't nearly as useful;
- it's generally the ability to execute C code and
- to process exceptions that is sought after).
-
- Default trampolining support is currently implemented as follows.
-
- Trampoline handler:
-
- A high-level interrupt is considered enabled if *either*
- its INTENABLE bit or its xt_tram_ints bit is set
- (note that both should never be set at the same time).
-
- */
-
-
-/* These are described in xtensa/hal.h (assumed initialized to zero, in BSS): */
-unsigned Xthal_tram_pending;
-unsigned Xthal_tram_enabled;
-unsigned Xthal_tram_sync;
-
-
-
-XtHalVoidFunc* xthal_set_tram_trigger_func( XtHalVoidFunc *trigger_fn )
-{
-#if XCHAL_HAVE_INTERRUPTS
- XtHalVoidFunc *fn;
-
- fn = Xthal_tram_trigger_fn;
- Xthal_tram_trigger_fn = trigger_fn;
- return( fn );
-#else
- (void)trigger_fn;
- return( 0 );
-#endif
-}
-
-
-/*
- * xthal_tram_set_sync
- *
- * Configure type of trampoline for a high-level interrupt.
- * By default any trampoline is asynchronous, this need only
- * be called to tell the Core HAL that a high-level interrupt
- * will be using synchronous trampolining (down to a level-1 interrupt).
- *
- * intnum interrupt number (0 .. 31)
- * sync 0 = async, 1 = synchronous
- *
- * Returns previous sync state of interrupt (0 or 1)
- * or -1 if invalid interrupt number provided.
- */
-int xthal_tram_set_sync( int intnum, int sync )
-{
-#if XCHAL_HAVE_INTERRUPTS
- unsigned mask;
- int prev;
-
- if( (unsigned)intnum >= XCHAL_NUM_INTERRUPTS )
- return( -1 );
- mask = 1L << intnum;
- prev = ((Xthal_tram_sync & mask) != 0);
- if( sync )
- Xthal_tram_sync |= mask;
- else
- Xthal_tram_sync &= ~mask;
- return( prev );
-#else /* XCHAL_HAVE_INTERRUPTS */
- return( 0 );
-#endif /* XCHAL_HAVE_INTERRUPTS */
-}
-
-
-/*
- * xthal_tram_pending_to_service
- *
- * This is called by the trampoline interrupt handler
- * (eg. by a level-one software interrupt handler)
- * to obtain the bitmask of high-level interrupts
- * that it must service.
- * Returns that bitmask (note: this can sometimes be zero,
- * eg. if currently executing level-one code disables the high-level
- * interrupt before the trampoline handler has a chance to run).
- *
- * This call automatically clears the trampoline pending
- * bits for the interrupts in the returned mask.
- * So the caller *must* process all interrupts that have
- * a corresponding bit set if the value returned by this function
- * (otherwise those interrupts may likely be lost).
- *
- * This function should be called with level-one interrupts disabled
- * (via INTENABLE; can't be via PS.INTLEVEL because this is C code).
- */
-unsigned xthal_tram_pending_to_service( void )
-{
-#if XCHAL_HAVE_INTERRUPTS
- unsigned service_mask;
-
- service_mask = ( Xthal_tram_pending
- & (Xthal_vpri_enabled | Xthal_tram_enabled) ) ;
-
- /*
- * Clear trampoline pending bits.
- * Each bit must be cleared *before* processing of the corresponding
- * interrupt occurs, to avoid missing interrupts.
- * Here we just clear all bits for simplicity and convenience.
- */
- Xthal_tram_pending &= ~service_mask;
-
- return( service_mask );
-#else /* XCHAL_HAVE_INTERRUPTS */
- return( 0 );
-#endif /* XCHAL_HAVE_INTERRUPTS */
-}
-
-/*
- * xthal_tram_done
- *
- * This is called by the trampoline interrupt handler
- * (eg. by a level-one software interrupt handler)
- * to indicate that processing of a trampolined interrupt
- * (eg. one or more of the bits it received from
- * xthal_tram_acknowledge()) has completed.
- *
- * For asynchronously trampolined interrupt(s), there is nothing to do.
- * For synchronously trampolined interrupt(s), the high-level
- * interrupt(s) must be re-enabled (presumably the level-one
- * interrupt handler that just completed has cleared the source
- * of the high-level interrupt).
- *
- * This function should be called with level-one interrupts disabled
- * (via INTENABLE; can't be via PS.INTLEVEL because this is C code).
- */
-void xthal_tram_done( unsigned serviced_mask )
-{
-#if XCHAL_HAVE_INTERRUPTS
- serviced_mask &= Xthal_tram_enabled; /* sync. trampolined interrupts that completed */
- Xthal_tram_enabled &= ~serviced_mask;
- xthal_int_enable( serviced_mask );
-#endif
-}
-
-#endif
-#if defined(__SPLIT__deprecated)
-
-
-/**********************************************************************/
-
-#ifdef INCLUDE_DEPRECATED_HAL_CODE
-/* These definitions were present in an early beta version of the HAL and should not be used: */
-const unsigned Xthal_num_int_levels = XCHAL_NUM_INTLEVELS;
-const unsigned Xthal_num_ints = XCHAL_NUM_INTERRUPTS;
-__asm__(".global Xthal_int_level_mask\n" ".set Xthal_int_level_mask, Xthal_intlevel_mask+4");
-__asm__(".global Xthal_int_level1_to_n_mask\n" ".set Xthal_int_level1_to_n_mask, Xthal_intlevel_andbelow_mask+8");
-/*const unsigned Xthal_int_level_mask[15] = { XCHAL_INTLEVEL_MASKS }; ... minus the first entry ...*/
-/*const unsigned Xthal_int_level1_to_n_mask[14] = { XCHAL_INTLEVEL_ANDBELOW_MASKS }; ... minus the first two entries ...*/
-const unsigned Xthal_int_level[32] = { XCHAL_INT_LEVELS };
-const unsigned Xthal_int_type_edge = XCHAL_INTTYPE_MASK_EXTERN_EDGE;
-const unsigned Xthal_int_type_level = XCHAL_INTTYPE_MASK_EXTERN_LEVEL;
-const unsigned Xthal_int_type_timer = XCHAL_INTTYPE_MASK_TIMER;
-const unsigned Xthal_int_type_software = XCHAL_INTTYPE_MASK_SOFTWARE;
-#endif /* INCLUDE_DEPRECATED_HAL_CODE */
-
-
-#endif /* SPLITs */
-
diff --git a/src/arch/xtensa/up/hal/mem_ecc_parity.S b/src/arch/xtensa/up/hal/mem_ecc_parity.S
deleted file mode 100644
index f992180..0000000
--- a/src/arch/xtensa/up/hal/mem_ecc_parity.S
+++ /dev/null
@@ -1,285 +0,0 @@
-//
-// mem_ecc_parity.S - utility routines for the local memory ECC/parity option
-// (memory error checking and exceptions)
-//
-// $Id: //depot/rel/Eaglenest/Xtensa/OS/hal/mem_ecc_parity.S#1 $
-
-// Copyright (c) 2006-2010 Tensilica Inc.
-//
-// Permission is hereby granted, free of charge, to any person obtaining
-// a copy of this software and associated documentation files (the
-// "Software"), to deal in the Software without restriction, including
-// without limitation the rights to use, copy, modify, merge, publish,
-// distribute, sublicense, and/or sell copies of the Software, and to
-// permit persons to whom the Software is furnished to do so, subject to
-// the following conditions:
-//
-// The above copyright notice and this permission notice shall be included
-// in all copies or substantial portions of the Software.
-//
-// THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
-// EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
-// MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
-// IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY
-// CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
-// TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
-// SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
-
-#include <xtensa/coreasm.h>
-
-
-/*
- * For most functions, the link-time HAL defines two entry points:
- * xthal_...() and xthal_..._nw(). The former is the main entry point
- * invoked from C code, or assembly code that follows the C ABI.
- * The latter is for use in assembly code that cannot easily follow
- * all the requirements of the windowed ABI, e.g. in exception handlers;
- * these use the call0 ABI instead (in most cases; some use their own conventions).
- *
- * When software tools are configured to use the call0 ABI, both variants
- * are identical (with some exceptions as noted). To avoid duplicating
- * code, we define both labels for the same function body. The Makefile
- * defines __SPLIT__..._nw macros with windowed ABI but not with Call0 ABI.
- * Use SYM_NW() for the _nw variants defined with the __SPLIT_..._nw macros,
- * i.e. for call0 ABI variants when windowed ABI is in use; these are not
- * C callable so SYM_NW() does not specify .type information.
- * Use SYMBOL() otherwise, which defines both symbols if call0 ABI is selected.
- */
-
-#if defined (__XTENSA_CALL0_ABI__)
-# define SYMBOL(x) .global x ; .type x,@function ; \
- .global x ## _nw ; .type x ## _nw,@function ; \
- .align 4 ; x: ; x ## _nw:
-#else
-# define SYMBOL(x) .global x ; .type x,@function ; .align 4 ; x:
-#endif
-#define SYM_NW(x) .global x ; .align 4 ; x:
-
-
-/* Compute smaller of I and D cache line sizes: */
-#if XCHAL_ICACHE_LINEWIDTH < XCHAL_DCACHE_LINEWIDTH && XCHAL_ICACHE_SIZE > 0
-# define CACHE_LINEWIDTH_MIN XCHAL_ICACHE_LINEWIDTH
-# define CACHE_LINESIZE_MIN XCHAL_ICACHE_LINESIZE
-#else
-# define CACHE_LINEWIDTH_MIN XCHAL_DCACHE_LINEWIDTH
-# define CACHE_LINESIZE_MIN XCHAL_DCACHE_LINESIZE
-#endif
-
-
- .text
-
-//------------------------------------------------------------------------
-// Inject errors into instruction and/or data RAMs, or cache data or tags
-//------------------------------------------------------------------------
-
-#if defined(__SPLIT__memep_inject_error)
-
-// void xthal_memep_inject_error(void *addr, int size, int flags);
-// where:
-// addr (a2) pointer to local memory, or cache address
-// size (a3) size in bytes (gets aligned to words or lines)
-// flags (a4) is a combination of the following bits:
-// bit 31-5: (reserved)
-// bit 4: 0 = inject non-correctable error,
-// 16 = inject correctable error (if ECC)
-// bit 3: (reserved)
-// bit 2: 0 = local memory, 4 = cache
-// bit 1: 0 = data cache, 2 = instruction cache
-// bit 0: 0 = cache data, 1 = cache tag
-//
-// (note: data cache data is handled same as local memories;
-// to access specific dcache data entries, you have to setup
-// a region or page in cache-isolate mode yourself)
-
-SYMBOL(xthal_memep_inject_error)
- abi_entry
-
-#if XCHAL_HAVE_MEM_ECC_PARITY
-
- // These MOVIs may be L32Rs, load them before enabling test mode:
- movi a6, 0x02020202 // XOR'ing this creates a correctable error
- bbsi.l a4, 4, 1f // branch if correctable error requested
- movi a6, 0x03030303 // XOR'ing this creates a non-correctable error
-1:
-
- // Lock out all interrupts, to avoid interrupt handlers running with
- // test mode enabled (corrupting their stores, likely leading to
- // non-correctable memory errors).
- //
- // If NMI is possible, you're toast
- // (no stores during NMI handler will have properly computed ECC/parity bits)
- // although you might make the NMI handler check MESR.ERRTEST and save/clear
- // it if it's set on entry, so that its stores work correctly.
- //
- // If memory exceptions are possible, might be okay as long as the
- // handler checks whether test mode is on, and turns it off temporarily
- // to do its work.
- //
-# if XCHAL_HAVE_INTERRUPTS
- rsil a11, 15
-# endif
-
- // Save current MESR and set test mode:
-
- rsr a8, MESR
- bbsi.l a8, MESR_ERRTEST_SHIFT, .Lproceed // already in test mode?
- addmi a9, a8, MESR_ERRTEST // enable test mode
- bbci.l a8, MESR_ERRENAB_SHIFT, 1f
- addmi a9, a9, - MESR_ERRENAB // disable error checks
-1: xsr a9, MESR
- beq a8, a9, .Lproceed // clean update, continue
- bbci.l a9, MESR_RCE_SHIFT, .Lproceed // we likely restored a lost RCE, just keep it
- // At this point, either we:
- // a) cleared an RCE record that got created between RSR and XSR
- // b) cleared LCE bits that got set between RSR and XSR
- // c) more eclectic, and presumably much less likely, cases of
- // RCE/LCE bits being cleared and set again between RSR and XSR
- // due to multiple memory errors and memory error exceptions
- // in that period; for now, we ignore this possibility
- // (decreasing returns on addressing these arbitrarily complex cases)
- // Assuming (a) or (b), restore the bits we took away.
- //addmi a8, a8, MESR_ERRTEST
- addmi a9, a9, MESR_ERRTEST
- bbci.l a9, MESR_ERRENAB_SHIFT, 1f
- addmi a9, a9, - MESR_ERRENAB // disable error checks
-1: wsr a9, MESR
- //xsr a9, MESR
- //beq a8, a9, .Lproceed // updated fine, continue
- //
- // Above we could have used XSR instead of WSR.
- // However, it's not clear at this point what's the cleanest thing
- // to do if what we read back doesn't match what we expected,
- // because at that point we have multiple errors to deal with.
- // Unless we have code here to handle (fix and/or log) these errors,
- // we have to chuck something away or write a bunch more code to
- // handle another LCE bit getting set etc (also starting to be
- // a low probability occurrence).
-.Lproceed:
- // Test mode enabled. From this point until we restore MESR,
- // the only loads and stores done are for injecting errors.
-
-# if XCHAL_ICACHE_SIZE || XCHAL_DCACHE_SIZE
- bbci.l a4, 2, .L_inject_local // branch if injecting to local memory
- bbsi.l a4, 1, .L_inject_icache // branch if injecting to icache
- // Inject errors in dcache:
- bbci.l a4, 0, .L_inject_local // branch if injecting to dcache data
-# if XCHAL_DCACHE_SIZE && XCHAL_HAVE_DCACHE_TEST
- // Inject errors in dcache tags:
-
- // Round addr/size to fully rather than partially cover
- // all aligned cache lines:
- extui a9, a2, 0, XCHAL_DCACHE_LINEWIDTH
- sub a2, a2, a9
- add a3, a3, a9
- addi a3, a3, XCHAL_DCACHE_LINESIZE-1
- srli a3, a3, XCHAL_DCACHE_LINEWIDTH // size in cache lines
-
- floopgtz a3, .Ldctagloop
- ldct a9, a2 // load dcache line tag
- rsr a7, MECR // get check bits
- xor a7, a7, a6 // ECC: single-bit error; Parity: NO-OP
- wsr a7, MECR // setup modified check bits
- sdct a9, a2 // store tag with modified check bits
- addi a2, a2, XCHAL_DCACHE_LINESIZE // increment to next line
- floopend a3, .Ldctagloop
-# endif /* have dcache */
- j .L_inject_done
-
- // Inject errors in icache:
-.L_inject_icache:
-# if XCHAL_ICACHE_SIZE && XCHAL_HAVE_ICACHE_TEST
- bbci.l a4, 0, .L_inject_icw // branch if injecting to icache data
-
- // Inject errors in icache tags:
- // Round addr/size to fully rather than partially cover
- // all aligned cache lines:
- extui a9, a2, 0, XCHAL_ICACHE_LINEWIDTH
- sub a2, a2, a9
- add a3, a3, a9
- addi a3, a3, XCHAL_ICACHE_LINESIZE-1
- srli a3, a3, XCHAL_ICACHE_LINEWIDTH // size in cache lines
-
- floopgtz a3, .Lictagloop
- lict a9, a2 // load icache line tag
- rsr a7, MECR // get check bits
- xor a7, a7, a6 // ECC: single-bit error; Parity: NO-OP
- wsr a7, MECR // setup modified check bits
- sict a9, a2 // store tag with modified check bits
- addi a2, a2, XCHAL_ICACHE_LINESIZE // increment to next line
- floopend a3, .Lictagloop
- j .L_inject_done
-
-.L_inject_icw:
-# if XCHAL_ICACHE_ACCESS_SIZE <= 4 /* SICW does not work usefully (replicates data) if accessWidth > 32 bits */
- // Inject errors in icache data words:
- // Round addr/size to fully rather than partially cover
- // all aligned 32-bit words:
- extui a9, a2, 0, 2
- sub a2, a2, a9
- add a3, a3, a9
- addi a3, a3, 3
- srli a3, a3, 2 // size in words
-
- floopgtz a3, .Licwloop
- licw a9, a2 // load word of icache line data
- rsr a7, MECR // get check bits
- xor a7, a7, a6 // ECC: single-bit error; Parity: NO-OP
- wsr a7, MECR // setup modified check bits
- sicw a9, a2 // store data with modified check bits
- addi a2, a2, 4 // increment to next word
- floopend a3, .Licwloop
-# endif
-# endif /* have icache */
- j .L_inject_done
-# endif /* have icache or dcache */
-
-.L_inject_local:
- // Round addr/size to fully rather than partially cover
- // all aligned 32-bit words:
- extui a9, a2, 0, 2
- sub a2, a2, a9
- add a3, a3, a9
- addi a3, a3, 3
- srli a3, a3, 2 // size in words
-
- floopgtz a3, .Lendloop
- l32i a9, a2, 0 // load data
- rsr a7, MECR // get check bits
- xor a7, a7, a6 // ECC: single-bit error; Parity: NO-OP
- wsr a7, MECR // setup modified check bits
- s32i a9, a2, 0 // store data with modified check bits
- addi a2, a2, 4 // increment to next word
- floopend a3, .Lendloop
-
-.L_inject_done:
- // Restore MESR (a8 is the saved original MESR):
- bbsi.l a8, MESR_ERRTEST_SHIFT, 2f // was already in test mode
- rsr a6, MESR
- addmi a9, a6, - MESR_ERRTEST // disable test mode
- bbci.l a8, MESR_ERRENAB_SHIFT, 1f
- addmi a9, a9, MESR_ERRENAB // enable error checks
-1: xsr a9, MESR
- beq a6, a9, 2f // clean update, done
- bbci.l a9, MESR_RCE_SHIFT, 2f // we likely restored a lost RCE, just keep it
- addmi a9, a9, - MESR_ERRTEST
- bbci.l a8, MESR_ERRENAB_SHIFT, 1f
- addmi a9, a9, MESR_ERRENAB // disable error checks
-1: wsr a9, MESR
-2:
-
- // Restore PS.INTLEVEL:
-# if XCHAL_HAVE_INTERRUPTS
- wsr a11, PS
- rsync
-# endif
-#endif /* XCHAL_HAVE_MEM_ECC_PARITY */
-
- abi_return
-
- .size xthal_memep_inject_error, . - xthal_memep_inject_error
-
-
-#endif /*split*/
-
-//----------------------------------------------------------------------
-
diff --git a/src/arch/xtensa/up/hal/memcopy.S b/src/arch/xtensa/up/hal/memcopy.S
deleted file mode 100644
index 5cabcf1..0000000
--- a/src/arch/xtensa/up/hal/memcopy.S
+++ /dev/null
@@ -1,409 +0,0 @@
-/*
- * Core HAL library functions xthal_memcpy and xthal_bcopy
- */
-
-/*
- * Copyright (c) 2003, 2006, 2010 Tensilica Inc.
- *
- * Permission is hereby granted, free of charge, to any person obtaining
- * a copy of this software and associated documentation files (the
- * "Software"), to deal in the Software without restriction, including
- * without limitation the rights to use, copy, modify, merge, publish,
- * distribute, sublicense, and/or sell copies of the Software, and to
- * permit persons to whom the Software is furnished to do so, subject to
- * the following conditions:
- *
- * The above copyright notice and this permission notice shall be included
- * in all copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
- * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
- * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
- * IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY
- * CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
- * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
- * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
- */
-
-#include <xtensa/coreasm.h>
-
-
-#ifdef __XTENSA_EB__
-# define BL(b,l) b
-#else
-# define BL(b,l) l
-#endif
-
- .macro srcel r, early, late // combine early and late words, shift into \r
- src \r, BL(\early,\late), BL(\late,\early)
- .endm
-
- .macro ssa8f r // set shift-amount for shift *from* given 2-bit alignment
- BL(ssa8b,ssa8l) \r
- .endm
-
- .macro ssa8t r // set shift-amount for shift *to* given 2-bit alignment
- BL(ssa8l,ssa8b) \r // (reverse of ssa8f)
- .endm
-
- .macro s2ll r, s // shift-to-later logical (away from zero-addressed byte)
- BL(srl,sll) \r, \s
- .endm
-
- .macro s2el r, s // shift-to-early logical (towards zero-addressed byte)
- BL(sll,srl) \r, \s
- .endm
-
-/*
- * void *xthal_memcpy(void *dst, const void *src, size_t len);
- * void *xthal_bcopy(const void *src, void *dst, size_t len);
- *
- * This function is intended to do the same thing as the standard
- * library function memcpy() (or bcopy()) for most cases.
- * However, it uses strictly 32-bit load and store instructions
- * to copy data. This ensures this function will work
- * where the source and/or destination references an
- * instruction RAM or ROM, which can only be accessed
- * using l32i (IRAM+IROM) and s32i (IRAM).
- *
- * The bcopy version is provided here to avoid the overhead
- * of an extra call, for callers that require this convention.
- *
- * The (general case) algorithm is as follows:
- * If destination is unaligned, align it by copying 1 to 3 bytes.
- * If source is aligned,
- * do 16 bytes with a loop, and then finish up with
- * 8, 4, and 0-3 byte copies conditional on the length;
- * else (if source is unaligned),
- * do the same, but use SRC to align the source data.
- * This code tries to use fall-through branches for the common
- * case of aligned source and destination and multiple
- * of 4 length.
- *
- * Register use:
- * a0/ return address
- * a1/ stack pointer
- * a2/ return value
- * a3/ src
- * a4/ length
- * a5/ dst
- * a6/ tmp
- * a7/ tmp
- * a8/ tmp
- * a9/ tmp
- * a10/ tmp
- * a11/ tmp
- * a12/ tmp
- */
-
-/* xthal_bcopy and xthal_memcpy need to allocate the same stack size
- * on entry since they share the same function-return code. Also,
- * there is more than one return point. */
-
-#define SAVE_A0 0
-#define SAVE_A3 4
-#define SAVE_A4 8
-#define SAVE_A5 12
-#define SAVE_A12 16
-#define STKSIZE 32
-
-
- .text
- .align 4
- .global xthal_bcopy
- .type xthal_bcopy,@function
-xthal_bcopy:
-#ifdef __XTENSA_CALL0_ABI__
- addi sp, sp, -STKSIZE
- s32i a12, a1, SAVE_A12
-#else
- entry sp, 32 // allow for call8 below
-#endif
- // a2=src, a3=dst, a4=len
- mov a5, a3 // copy dst so that a2 is return value
- mov a3, a2
- mov a2, a5
- j .Lcommon // go to common code for memcpy+bcopy
-
- .size xthal_bcopy, . - xthal_bcopy
-
-
-
-/*
- * Destination is unaligned
- */
-
- .align 4
-xthal_memcpy.prefixcode: // purely for purpose of .size
-.Ldstunaligned:
- mov a10, a5
- mov a11, a3
- movi a12, 4
- sub a6, a12, a6 // number of bytes to copy for dst alignment
- mov a12, a6
-#ifdef __XTENSA_CALL0_ABI__
- s32i a0, a1, SAVE_A0 // preserve live registers
- s32i a3, a1, SAVE_A3
- s32i a4, a1, SAVE_A4
- s32i a5, a1, SAVE_A5
- call0 xthal_copy123
- l32i a0, a1, SAVE_A0 // restore live registers
- l32i a3, a1, SAVE_A3
- l32i a4, a1, SAVE_A4
- l32i a5, a1, SAVE_A5
- mov a6, a12 // restore a6 from callee-saved register
-#else
- call8 xthal_copy123
-#endif
- add a5, a5, a6
- add a3, a3, a6
- sub a4, a4, a6
- j .Ldstaligned
-
- // Not sure how else to count code that precedes a function, in .size:
- .size xthal_memcpy.prefixcode, . - xthal_memcpy.prefixcode
-
-
- .align 4
- .global xthal_memcpy
- .type xthal_memcpy,@function
-xthal_memcpy:
-#ifdef __XTENSA_CALL0_ABI__
- addi sp, sp, -STKSIZE
- s32i a12, a1, SAVE_A12
-#else
- entry sp, 32 // allow for call8 below
-#endif
- // a2=dst, a3=src, a4=len
- mov a5, a2 // copy dst so that a2 is return value
-.Lcommon:
-#ifdef __XTENSA_CALL0_ABI__
- /*
- * have to restore the stack
- */
- _bgeui a4, 4, 1f
- mov a12, a0 // preserve return address
- call0 xthal_copy123
- mov a0, a12 // restore return address
- l32i a12, a1, SAVE_A12
- addi sp, sp, STKSIZE
- ret
-1:
-#else
- bltui a4, 4, xthal_copy123_pastentry // NOTE: sometimes relaxes
-#endif
-
- extui a6, a2, 0, 2 // destination unalignment offset
- bnez a6, .Ldstunaligned // align the destination
-.Ldstaligned: // return here once dst is aligned
- srli a7, a4, 4 // number of loop iterations of 16-bytes each
- extui a11, a3, 0, 2 // source unalignment offset
- _bnez a11, .Lsrcunaligned // if source not aligned, use shifting copy
- /*
- * Destination and source are 32-bit aligned, use 32-bit copy.
- */
-#if XCHAL_HAVE_LOOPS
- loopnez a7, .Loop1done
-#else /* !XCHAL_HAVE_LOOPS */
- beqz a7, .Loop1done
- slli a8, a7, 4
- add a8, a8, a3 // a8 = end of last 16B source chunk
-#endif /* !XCHAL_HAVE_LOOPS */
-.Loop1:
- l32i a6, a3, 0
- l32i a7, a3, 4
- s32i a6, a5, 0
- l32i a6, a3, 8
- s32i a7, a5, 4
- l32i a7, a3, 12
- s32i a6, a5, 8
- addi a3, a3, 16
- s32i a7, a5, 12
- addi a5, a5, 16
-#if !XCHAL_HAVE_LOOPS
- blt a3, a8, .Loop1
-#endif /* !XCHAL_HAVE_LOOPS */
-.Loop1done:
- bbci.l a4, 3, .L2
- // copy 8 bytes
- l32i a6, a3, 0
- l32i a7, a3, 4
- addi a3, a3, 8
- s32i a6, a5, 0
- s32i a7, a5, 4
- addi a5, a5, 8
-.L2:
- bbci.l a4, 2, .L3
- // copy 4 bytes
- l32i a6, a3, 0
- addi a3, a3, 4
- s32i a6, a5, 0
- addi a5, a5, 4
-.L3:
- // Copy last 0 to 3 bytes using 32-bit accesses (aligned source and destination):
- extui a4, a4, 0, 2 // any bytes to copy?
- beqz a4, 1f // if not, skip this to avoid extraneous loads/stores
- l32i a6, a3, 0 // get source word
- l32i a7, a5, 0 // get destination word
- ssa8f a4 // shift from length (end of source)
- s2ll a6, a6 // align source to last byte
- s2el a7, a7 // align parts of a7 following modified bytes, to early byte
- ssa8t a4 // shift to end of modified destination (length)
- srcel a7, a6, a7 // combine source with late-dst to form last word
- s32i a7, a5, 0 // update last word
-1:
-
-#ifdef __XTENSA_CALL0_ABI__
- l32i a12, a1, SAVE_A12
- addi sp, sp, STKSIZE
- ret
-#else
- retw
-#endif
-
- .size xthal_memcpy, . - xthal_memcpy
-
-
- // void xthal_copy123(dst, src, len);
- //
- // Copy from 0 to 3 bytes, using only 32-bit loads and stores,
- // with arbitrarily aligned source and destination.
- //
- // arg1 = a2 = dst
- // arg2 = a3 = src
- // arg3 = a4 = len
-
- .global xthal_copy123
- .type xthal_copy123,@function
- .align 4
-xthal_copy123:
- abi_entry
-
-xthal_copy123_pastentry:
- _beqz a4, cdone // don't load or store if zero bytes
- // First get the bytes:
- movi a5, ~3
- and a5, a3, a5 // align src address
- l32i a6, a5, 0
- l32i a7, a5, 4
- ssa8f a3
- srcel a3, a6, a7
- // a3 now contains source bytes, aligned to 1st byte (memory order)
- // (source address is no longer needed at this point)
-
- // Does destination span two words?:
- extui a10, a2, 0, 2 // destination alignment
- sub a5, a2, a10 // align destination address
- l32i a8, a5, 0 // get first destination word regardless
- add a6, a10, a4 // dst_align + len
- ssa8f a2 // shift from dst_align (to 1st or last byte)
- s2ll a10, a8 // a10 = first part of destination, aligned to last byte
- bltui a6, 4, oneword // branch if destination contained in single word
-
- // Two-word destination case:
- l32i a8, a5, 4 // get second word
- ssa8t a2 // shift to dst_align
- srcel a10, a10, a3 // with a10 in early bytes, a3 in later bytes
- s32i a10, a5, 0 // update first word
- addi a5, a5, 4 // advance to last word for common code below
- //movi a10, 0 // not needed, gets dropped
-
-oneword:
- // One-word (and two-word) destination case:
- // a8 = contents of last destination word
- // a10 = early part of a8 preceding modified bytes, shifted towards last byte
- //
- ssa8f a4 // shift from length (end of source)
- srcel a3, a10, a3 // combine early-destination with source, aligned to last byte
-
- ssa8f a6 // shift from end of modified destination (dst_align+len)
- s2el a8, a8 // align parts of a8 following modified bytes, to early byte
- ssa8t a6 // shift to end of modified destination (dst_align+len)
- srcel a8, a3, a8 // combine early-dst+source with late-dst to form last word
- s32i a8, a5, 0 // update last word
-cdone: abi_return // return dst
-
-/*
- * Destination is aligned, Source is unaligned
- */
-
- .align 4
-.Lsrcunaligned:
- // Copy 16 bytes per iteration for word-aligned dst and unaligned src
- ssa8f a3 // set shift amount from byte offset
-#define SIM_CHECKS_ALIGNMENT 1 /* set to 1 when running on ISS (simulator) with the
- lint or ferret client, or 0 to save a few cycles */
-#if XCHAL_UNALIGNED_LOAD_EXCEPTION || SIM_CHECKS_ALIGNMENT
- extui a11, a3, 0, 2 // save unalignment offset for below
- sub a3, a3, a11 // align a3
-#endif
- l32i a6, a3, 0 // load first word
-#if XCHAL_HAVE_LOOPS
- loopnez a7, .Loop2done
-#else /* !XCHAL_HAVE_LOOPS */
- beqz a7, .Loop2done
- slli a10, a7, 4
- add a10, a10, a3 // a10 = end of last 16B source chunk
-#endif /* !XCHAL_HAVE_LOOPS */
-.Loop2:
- l32i a7, a3, 4
- l32i a8, a3, 8
- srcel a6, a6, a7
- s32i a6, a5, 0
- l32i a9, a3, 12
- srcel a7, a7, a8
- s32i a7, a5, 4
- l32i a6, a3, 16
- srcel a8, a8, a9
- s32i a8, a5, 8
- addi a3, a3, 16
- srcel a9, a9, a6
- s32i a9, a5, 12
- addi a5, a5, 16
-#if !XCHAL_HAVE_LOOPS
- blt a3, a10, .Loop2
-#endif /* !XCHAL_HAVE_LOOPS */
-.Loop2done:
- bbci.l a4, 3, .L12
- // copy 8 bytes
- l32i a7, a3, 4
- l32i a8, a3, 8
- srcel a6, a6, a7
- s32i a6, a5, 0
- addi a3, a3, 8
- srcel a7, a7, a8
- s32i a7, a5, 4
- addi a5, a5, 8
- mov a6, a8
-.L12:
- bbci.l a4, 2, .L13
- // copy 4 bytes
- l32i a7, a3, 4
- addi a3, a3, 4
- srcel a6, a6, a7
- s32i a6, a5, 0
- addi a5, a5, 4
- mov a6, a7
-.L13:
- // Copy last 0 to 3 bytes using 32-bit accesses (shifting source, aligned destination):
- //_beqz a4[1:0], cdone // don't load or store if zero bytes
- l32i a7, a3, 4 // get source word
- l32i a3, a5, 0 // get destination word
- srcel a6, a6, a7 // source bytes, aligned to early (1st) byte
- ssa8f a4 // shift from length (end of source)
- s2ll a6, a6 // combine early-destination with source, aligned to last byte
- s2el a3, a3 // align parts of a3 following modified bytes, to early byte
- ssa8t a4 // shift to end of modified destination (length)
- srcel a3, a6, a3 // combine early-dst+source with late-dst to form last word
- s32i a3, a5, 0 // update last word
-.Ldone:
-#ifdef __XTENSA_CALL0_ABI__
- l32i a12, a1, SAVE_A12
- addi sp, sp, STKSIZE
- ret
-#else
- retw
-#endif
-
- .size xthal_copy123, . - xthal_copy123
-
diff --git a/src/arch/xtensa/up/hal/misc.c b/src/arch/xtensa/up/hal/misc.c
deleted file mode 100644
index 7b52337..0000000
--- a/src/arch/xtensa/up/hal/misc.c
+++ /dev/null
@@ -1,170 +0,0 @@
-//
-// misc.c - miscellaneous constants
-//
-// $Id: //depot/rel/Eaglenest/Xtensa/OS/hal/misc.c#1 $
-
-// Copyright (c) 2004-2005 Tensilica Inc.
-//
-// Permission is hereby granted, free of charge, to any person obtaining
-// a copy of this software and associated documentation files (the
-// "Software"), to deal in the Software without restriction, including
-// without limitation the rights to use, copy, modify, merge, publish,
-// distribute, sublicense, and/or sell copies of the Software, and to
-// permit persons to whom the Software is furnished to do so, subject to
-// the following conditions:
-//
-// The above copyright notice and this permission notice shall be included
-// in all copies or substantial portions of the Software.
-//
-// THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
-// EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
-// MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
-// IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY
-// CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
-// TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
-// SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
-
-#include <xtensa/config/core.h>
-
-
-// Software release info (not configuration-specific!):
-const unsigned int Xthal_release_major = XTHAL_RELEASE_MAJOR;
-const unsigned int Xthal_release_minor = XTHAL_RELEASE_MINOR;
-const char * const Xthal_release_name = XTHAL_RELEASE_NAME;
-#ifdef XTHAL_RELEASE_INTERNAL
-const char * const Xthal_release_internal = XTHAL_RELEASE_INTERNAL;
-#else
-const char * const Xthal_release_internal = 0;
-#endif
-/* Old format, for backward compatibility: */
-const unsigned int Xthal_rev_no = (XTHAL_MAJOR_REV<<16)|XTHAL_MINOR_REV;
-
-// number of registers in register window, or number of registers if not windowed
-const unsigned int Xthal_num_aregs = XCHAL_NUM_AREGS;
-const unsigned char Xthal_num_aregs_log2 = XCHAL_NUM_AREGS_LOG2;
-
-const unsigned char Xthal_memory_order = XCHAL_MEMORY_ORDER;
-const unsigned char Xthal_have_windowed = XCHAL_HAVE_WINDOWED;
-const unsigned char Xthal_have_density = XCHAL_HAVE_DENSITY;
-const unsigned char Xthal_have_booleans = XCHAL_HAVE_BOOLEANS;
-const unsigned char Xthal_have_loops = XCHAL_HAVE_LOOPS;
-const unsigned char Xthal_have_nsa = XCHAL_HAVE_NSA;
-const unsigned char Xthal_have_minmax = XCHAL_HAVE_MINMAX;
-const unsigned char Xthal_have_sext = XCHAL_HAVE_SEXT;
-const unsigned char Xthal_have_clamps = XCHAL_HAVE_CLAMPS;
-const unsigned char Xthal_have_mac16 = XCHAL_HAVE_MAC16;
-const unsigned char Xthal_have_mul16 = XCHAL_HAVE_MUL16;
-const unsigned char Xthal_have_fp = XCHAL_HAVE_FP;
-const unsigned char Xthal_have_speculation = XCHAL_HAVE_SPECULATION;
-const unsigned char Xthal_have_exceptions = XCHAL_HAVE_EXCEPTIONS;
-const unsigned char Xthal_xea_version = XCHAL_XEA_VERSION;
-const unsigned char Xthal_have_interrupts = XCHAL_HAVE_INTERRUPTS;
-const unsigned char Xthal_have_highlevel_interrupts = XCHAL_HAVE_HIGHLEVEL_INTERRUPTS;
-const unsigned char Xthal_have_nmi = XCHAL_HAVE_NMI;
-const unsigned char Xthal_have_prid = XCHAL_HAVE_PRID;
-const unsigned char Xthal_have_release_sync = XCHAL_HAVE_RELEASE_SYNC;
-const unsigned char Xthal_have_s32c1i = XCHAL_HAVE_S32C1I;
-const unsigned char Xthal_have_threadptr = XCHAL_HAVE_THREADPTR;
-
-const unsigned char Xthal_have_pif = XCHAL_HAVE_PIF;
-const unsigned short Xthal_num_writebuffer_entries = XCHAL_NUM_WRITEBUFFER_ENTRIES;
-
-const unsigned int Xthal_build_unique_id = XCHAL_BUILD_UNIQUE_ID;
-// Release info for hardware targeted by software upgrades:
-const unsigned int Xthal_hw_configid0 = XCHAL_HW_CONFIGID0;
-const unsigned int Xthal_hw_configid1 = XCHAL_HW_CONFIGID1;
-const unsigned int Xthal_hw_release_major = XCHAL_HW_VERSION_MAJOR;
-const unsigned int Xthal_hw_release_minor = XCHAL_HW_VERSION_MINOR;
-const char * const Xthal_hw_release_name = XCHAL_HW_VERSION_NAME;
-const unsigned int Xthal_hw_min_version_major = XCHAL_HW_MIN_VERSION_MAJOR;
-const unsigned int Xthal_hw_min_version_minor = XCHAL_HW_MIN_VERSION_MINOR;
-const unsigned int Xthal_hw_max_version_major = XCHAL_HW_MAX_VERSION_MAJOR;
-const unsigned int Xthal_hw_max_version_minor = XCHAL_HW_MAX_VERSION_MINOR;
-#ifdef XCHAL_HW_RELEASE_INTERNAL
-const char * const Xthal_hw_release_internal = XCHAL_HW_RELEASE_INTERNAL;
-#else
-const char * const Xthal_hw_release_internal = 0;
-#endif
-
-/* MMU related info... */
-
-const unsigned char Xthal_have_spanning_way = XCHAL_HAVE_SPANNING_WAY;
-const unsigned char Xthal_have_identity_map = XCHAL_HAVE_IDENTITY_MAP;
-const unsigned char Xthal_have_mimic_cacheattr = XCHAL_HAVE_MIMIC_CACHEATTR;
-const unsigned char Xthal_have_xlt_cacheattr = XCHAL_HAVE_XLT_CACHEATTR;
-const unsigned char Xthal_have_cacheattr = XCHAL_HAVE_CACHEATTR;
-const unsigned char Xthal_have_tlbs = XCHAL_HAVE_TLBS;
-
-const unsigned char Xthal_mmu_asid_bits = XCHAL_MMU_ASID_BITS;
-const unsigned char Xthal_mmu_asid_kernel = XCHAL_MMU_ASID_KERNEL;
-const unsigned char Xthal_mmu_rings = XCHAL_MMU_RINGS;
-const unsigned char Xthal_mmu_ring_bits = XCHAL_MMU_RING_BITS;
-const unsigned char Xthal_mmu_sr_bits = XCHAL_MMU_SR_BITS;
-const unsigned char Xthal_mmu_ca_bits = XCHAL_MMU_CA_BITS;
-#if XCHAL_HAVE_TLBS
-const unsigned int Xthal_mmu_max_pte_page_size = XCHAL_MMU_MAX_PTE_PAGE_SIZE;
-const unsigned int Xthal_mmu_min_pte_page_size = XCHAL_MMU_MIN_PTE_PAGE_SIZE;
-const unsigned char Xthal_itlb_way_bits = XCHAL_ITLB_WAY_BITS;
-const unsigned char Xthal_itlb_ways = XCHAL_ITLB_WAYS;
-const unsigned char Xthal_itlb_arf_ways = XCHAL_ITLB_ARF_WAYS;
-const unsigned char Xthal_dtlb_way_bits = XCHAL_DTLB_WAY_BITS;
-const unsigned char Xthal_dtlb_ways = XCHAL_DTLB_WAYS;
-const unsigned char Xthal_dtlb_arf_ways = XCHAL_DTLB_ARF_WAYS;
-#else
-const unsigned int Xthal_mmu_max_pte_page_size = 0;
-const unsigned int Xthal_mmu_min_pte_page_size = 0;
-const unsigned char Xthal_itlb_way_bits = 0;
-const unsigned char Xthal_itlb_ways = 0;
-const unsigned char Xthal_itlb_arf_ways = 0;
-const unsigned char Xthal_dtlb_way_bits = 0;
-const unsigned char Xthal_dtlb_ways = 0;
-const unsigned char Xthal_dtlb_arf_ways = 0;
-#endif
-
-
-/* Internal memories... */
-
-const unsigned char Xthal_num_instrom = XCHAL_NUM_INSTROM;
-const unsigned char Xthal_num_instram = XCHAL_NUM_INSTRAM;
-const unsigned char Xthal_num_datarom = XCHAL_NUM_DATAROM;
-const unsigned char Xthal_num_dataram = XCHAL_NUM_DATARAM;
-const unsigned char Xthal_num_xlmi = XCHAL_NUM_XLMI;
-
-/* Define arrays of internal memories' addresses and sizes: */
-#define MEMTRIPLET(n,mem,memcap) _MEMTRIPLET(n,mem,memcap)
-#define _MEMTRIPLET(n,mem,memcap) MEMTRIPLET##n(mem,memcap)
-#define MEMTRIPLET0(mem,memcap) \
- const unsigned int Xthal_##mem##_vaddr[1] = { 0 }; \
- const unsigned int Xthal_##mem##_paddr[1] = { 0 }; \
- const unsigned int Xthal_##mem##_size [1] = { 0 };
-#define MEMTRIPLET1(mem,memcap) \
- const unsigned int Xthal_##mem##_vaddr[1] = { XCHAL_##memcap##0_VADDR }; \
- const unsigned int Xthal_##mem##_paddr[1] = { XCHAL_##memcap##0_PADDR }; \
- const unsigned int Xthal_##mem##_size [1] = { XCHAL_##memcap##0_SIZE };
-#define MEMTRIPLET2(mem,memcap) \
- const unsigned int Xthal_##mem##_vaddr[2] = { XCHAL_##memcap##0_VADDR, XCHAL_##memcap##1_VADDR }; \
- const unsigned int Xthal_##mem##_paddr[2] = { XCHAL_##memcap##0_PADDR, XCHAL_##memcap##1_PADDR }; \
- const unsigned int Xthal_##mem##_size [2] = { XCHAL_##memcap##0_SIZE, XCHAL_##memcap##1_SIZE };
-MEMTRIPLET(XCHAL_NUM_INSTROM, instrom, INSTROM)
-MEMTRIPLET(XCHAL_NUM_INSTRAM, instram, INSTRAM)
-MEMTRIPLET(XCHAL_NUM_DATAROM, datarom, DATAROM)
-MEMTRIPLET(XCHAL_NUM_DATARAM, dataram, DATARAM)
-MEMTRIPLET(XCHAL_NUM_XLMI, xlmi, XLMI)
-
-/* Timer info... */
-
-const unsigned char Xthal_have_ccount = XCHAL_HAVE_CCOUNT;
-const unsigned char Xthal_num_ccompare = XCHAL_NUM_TIMERS;
-
-#ifdef INCLUDE_DEPRECATED_HAL_CODE
-const unsigned char Xthal_have_old_exc_arch = XCHAL_HAVE_XEA1;
-const unsigned char Xthal_have_mmu = XCHAL_HAVE_TLBS;
-const unsigned int Xthal_num_regs = XCHAL_NUM_AREGS; /*DEPRECATED*/
-const unsigned char Xthal_num_irom = XCHAL_NUM_INSTROM; /*DEPRECATED*/
-const unsigned char Xthal_num_iram = XCHAL_NUM_INSTRAM; /*DEPRECATED*/
-const unsigned char Xthal_num_drom = XCHAL_NUM_DATAROM; /*DEPRECATED*/
-const unsigned char Xthal_num_dram = XCHAL_NUM_DATARAM; /*DEPRECATED*/
-const unsigned int Xthal_configid0 = XCHAL_HW_CONFIGID0;
-const unsigned int Xthal_configid1 = XCHAL_HW_CONFIGID1;
-#endif
-
diff --git a/src/arch/xtensa/up/hal/miscellaneous.S b/src/arch/xtensa/up/hal/miscellaneous.S
deleted file mode 100644
index cabea95..0000000
--- a/src/arch/xtensa/up/hal/miscellaneous.S
+++ /dev/null
@@ -1,78 +0,0 @@
-//
-// miscellaneous.S - miscellaneous assembly language routines
-//
-// $Id: //depot/rel/Eaglenest/Xtensa/OS/hal/miscellaneous.S#1 $
-
-// Copyright (c) 2011 Tensilica Inc.
-//
-// Permission is hereby granted, free of charge, to any person obtaining
-// a copy of this software and associated documentation files (the
-// "Software"), to deal in the Software without restriction, including
-// without limitation the rights to use, copy, modify, merge, publish,
-// distribute, sublicense, and/or sell copies of the Software, and to
-// permit persons to whom the Software is furnished to do so, subject to
-// the following conditions:
-//
-// The above copyright notice and this permission notice shall be included
-// in all copies or substantial portions of the Software.
-//
-// THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
-// EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
-// MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
-// IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY
-// CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
-// TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
-// SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
-
-#include <xtensa/cacheasm.h>
-#include <xtensa/cacheattrasm.h>
-#include <xtensa/xtensa-versions.h>
-
-/* For Call0 ABI, the xthal... and xthal..._nw versions are identical,
- * so we define both labels for the same function body. The Makefile
- * does not define any of the __SPLIT__..._nw macros if Call0 ABI.
- * Use SYM() when we don't want .type information. */
-
-#if defined (__XTENSA_CALL0_ABI__)
-# define SYMBOL(x) _SYMT(x); _SYMT(x ## _nw)
-#else
-# define SYMBOL(x) _SYMT(x)
-#endif
-
-
-
- .text
-
-//----------------------------------------------------------------------
-// Clear any remnant register state pointing to (or containing) code.
-// Specifically, clear loop registers (LCOUNT) to avoid hardware loopback
-// from LEND to LBEGIN when new code is loaded where code containing a
-// zero-overhead loop was located. See the HAL chapter of the Tensilica
-// System Software Reference Manual for details on the use of this function.
-//----------------------------------------------------------------------
-
-#if defined(__SPLIT__clear_regcached_code)
-
-SYMBOL(xthal_clear_regcached_code)
- abi_entry
-# if XCHAL_HAVE_LOOPS
- movi a2, 0
- wsr.lcount a2
-# endif
- isync_retw_nop
- abi_return
- endfunc
-
-#endif
-#if defined(__SPLIT__clear_regcached_code_nw)
-
-SYM(xthal_clear_regcached_code_nw)
-# if XCHAL_HAVE_LOOPS
- movi a2, 0
- wsr.lcount a2
-# endif
- ret
- endfunc
-
-#endif
-
diff --git a/src/arch/xtensa/up/hal/mmu.c b/src/arch/xtensa/up/hal/mmu.c
deleted file mode 100644
index 3843917..0000000
--- a/src/arch/xtensa/up/hal/mmu.c
+++ /dev/null
@@ -1,93 +0,0 @@
-//
-// mmu.c - MMU related functions
-//
-// $Id: //depot/rel/Eaglenest/Xtensa/OS/hal/mmu.c#1 $
-
-// Copyright (c) 2002, 2008 Tensilica Inc.
-//
-// Permission is hereby granted, free of charge, to any person obtaining
-// a copy of this software and associated documentation files (the
-// "Software"), to deal in the Software without restriction, including
-// without limitation the rights to use, copy, modify, merge, publish,
-// distribute, sublicense, and/or sell copies of the Software, and to
-// permit persons to whom the Software is furnished to do so, subject to
-// the following conditions:
-//
-// The above copyright notice and this permission notice shall be included
-// in all copies or substantial portions of the Software.
-//
-// THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
-// EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
-// MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
-// IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY
-// CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
-// TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
-// SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
-
-#include <xtensa/config/core.h>
-
-/*
- * Convert a virtual address to a physical address
- * (through static maps only).
- * Returns 0 if successful (*paddrp is set), -1 if not (no mapping).
- */
-int xthal_static_v2p( unsigned vaddr, unsigned *paddrp /*, unsigned len, unsigned rasid*/ )
-{
-#if XCHAL_HAVE_PTP_MMU && !XCHAL_HAVE_SPANNING_WAY
- if( vaddr >= XCHAL_KSEG_CACHED_VADDR
- && vaddr <= XCHAL_KSEG_CACHED_VADDR + XCHAL_KSEG_CACHED_SIZE )
- vaddr += XCHAL_KSEG_CACHED_PADDR - XCHAL_KSEG_CACHED_VADDR;
- else if( vaddr >= XCHAL_KSEG_BYPASS_VADDR
- && vaddr <= XCHAL_KSEG_BYPASS_VADDR + XCHAL_KSEG_BYPASS_SIZE )
- vaddr += XCHAL_KSEG_BYPASS_PADDR - XCHAL_KSEG_BYPASS_VADDR;
- else if( vaddr >= XCHAL_KIO_CACHED_VADDR
- && vaddr <= XCHAL_KIO_CACHED_VADDR + XCHAL_KIO_CACHED_SIZE )
- vaddr += XCHAL_KIO_CACHED_PADDR - XCHAL_KIO_CACHED_VADDR;
- else if( vaddr >= XCHAL_KIO_BYPASS_VADDR
- && vaddr <= XCHAL_KIO_BYPASS_VADDR + XCHAL_KIO_BYPASS_SIZE )
- vaddr += XCHAL_KIO_BYPASS_PADDR - XCHAL_KIO_BYPASS_VADDR;
- else
- return( -1 ); /* no known mapping */
-#endif /* XCHAL_HAVE_PTP_MMU && !XCHAL_HAVE_SPANNING_WAY */
- *paddrp = vaddr; /* virtual == physical */
- return( 0 );
-}
-
-/*
- * Convert a physical address to a virtual address
- * (through static maps only).
- * Returns 0 if successful (*vaddrp is set), -1 if not (no mapping).
- *
- * NOTE: A physical address can be mapped from multiple virtual addresses
- * (or one or none).
- * There should be better parameter(s) to help select the mapping returned
- * (eg. cache mode, address, asid, etc), or somehow return them all.
- * Mappings returned currently assume the current RASID setting.
- */
-int xthal_static_p2v( unsigned paddr, unsigned *vaddrp, /*unsigned len, unsigned rasid,*/ unsigned cached )
-{
-#if XCHAL_HAVE_PTP_MMU && !XCHAL_HAVE_SPANNING_WAY
- if( cached ) {
- if( paddr >= XCHAL_KSEG_CACHED_PADDR
- && paddr <= XCHAL_KSEG_CACHED_PADDR + XCHAL_KSEG_CACHED_SIZE )
- paddr += XCHAL_KSEG_CACHED_VADDR - XCHAL_KSEG_CACHED_PADDR;
- else if( paddr >= XCHAL_KIO_BYPASS_PADDR
- && paddr <= XCHAL_KIO_BYPASS_PADDR + XCHAL_KIO_BYPASS_SIZE )
- paddr += XCHAL_KIO_BYPASS_VADDR - XCHAL_KIO_BYPASS_PADDR;
- else
- return -1; /* no known mapping */
- } else {
- if( paddr >= XCHAL_KSEG_BYPASS_PADDR
- && paddr <= XCHAL_KSEG_BYPASS_PADDR + XCHAL_KSEG_BYPASS_SIZE )
- paddr += XCHAL_KSEG_BYPASS_VADDR - XCHAL_KSEG_BYPASS_PADDR;
- else if( paddr >= XCHAL_KIO_CACHED_PADDR
- && paddr <= XCHAL_KIO_CACHED_PADDR + XCHAL_KIO_CACHED_SIZE )
- paddr += XCHAL_KIO_CACHED_VADDR - XCHAL_KIO_CACHED_PADDR;
- else
- return -1; /* no known mapping */
- }
-#endif /* XCHAL_HAVE_PTP_MMU && !XCHAL_HAVE_SPANNING_WAY */
- *vaddrp = paddr; /* virtual == physical */
- return( 0 );
-}
-
diff --git a/src/arch/xtensa/up/hal/mp_asm.S b/src/arch/xtensa/up/hal/mp_asm.S
deleted file mode 100644
index 7d52417..0000000
--- a/src/arch/xtensa/up/hal/mp_asm.S
+++ /dev/null
@@ -1,102 +0,0 @@
-//
-// mp_asm.S - multi-processor synchronization routines
-//
-// $Id$
-
-// Copyright (c) 2003, 2005, 2010 Tensilica Inc.
-//
-// Permission is hereby granted, free of charge, to any person obtaining
-// a copy of this software and associated documentation files (the
-// "Software"), to deal in the Software without restriction, including
-// without limitation the rights to use, copy, modify, merge, publish,
-// distribute, sublicense, and/or sell copies of the Software, and to
-// permit persons to whom the Software is furnished to do so, subject to
-// the following conditions:
-//
-// The above copyright notice and this permission notice shall be included
-// in all copies or substantial portions of the Software.
-//
-// THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
-// EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
-// MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
-// IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY
-// CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
-// TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
-// SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
-
-#include <xtensa/coreasm.h>
-
-
-/*
- int xthal_compare_and_set( int *address, int test_value, int set_value )
-
- Atomically sets *address to set_value if *address equals test_value.
- Returns the previous value of *address (the one compared with test_value).
-
- Uses the S32C1I instruction if available.
- S32C1I requires special support from the memory controller for
- memory accessed via the PIF interface. For this and other reasons,
- S32C1I might not work on the entire 4GB address range. This function
- does not test address validity. That is the responsibility of the
- software invoking this function.
-*/
- .text
- .align 4
- .global xthal_compare_and_set
- .type xthal_compare_and_set,@function
-
-xthal_compare_and_set:
- abi_entry
- // a2 == address
- // a3 == test value
- // a4 == set value
-
-#if XCHAL_HAVE_S32C1I && XCHAL_HW_MIN_VERSION_MAJOR >= 2200
- wsr a3, SCOMPARE1
- s32c1i a4, a2, 0
- mov a2, a4
-#else
- mov a7, a2 // a7 == address, a2 is return val
-# if XCHAL_HAVE_INTERRUPTS
- rsil a5, 15 // a5 == new ps
-# endif
- l32i a2, a7, 0 // a2 == value to test, return val
- bne a3, a2, done // test
-
- s32i a4, a7, 0 // write the new value
-
-done:
-# if XCHAL_HAVE_INTERRUPTS
- wsr a5, PS // restore the PS
- rsync
-# endif
-#endif
- abi_return
-
- .size xthal_compare_and_set, . - xthal_compare_and_set
-
-
-/*
- unsigned xthal_get_prid( void );
-
- Returns the value of the PRID register (processor ID),
- or 0 if not configured.
- (Note: this register, when present, cannot / must-not
- change value during runtime; on certain processors,
- its value may get sampled only at reset.
- It can never be written to, hence
- there is no xthal_set_prid() function.)
-*/
- .align 4
- .global xthal_get_prid
- .type xthal_get_prid,@function
-xthal_get_prid:
- abi_entry
-#if XCHAL_HAVE_PRID
- rsr a2, PRID
-#else
- movi a2, 0
-#endif
- abi_return
- .size xthal_get_prid, . - xthal_get_prid
-
diff --git a/src/arch/xtensa/up/hal/set_region_translate.c b/src/arch/xtensa/up/hal/set_region_translate.c
deleted file mode 100644
index a628869..0000000
--- a/src/arch/xtensa/up/hal/set_region_translate.c
+++ /dev/null
@@ -1,516 +0,0 @@
-/*
- * Copyright (c) 2004-2014 Tensilica Inc.
- *
- * Permission is hereby granted, free of charge, to any person obtaining
- * a copy of this software and associated documentation files (the
- * "Software"), to deal in the Software without restriction, including
- * without limitation the rights to use, copy, modify, merge, publish,
- * distribute, sublicense, and/or sell copies of the Software, and to
- * permit persons to whom the Software is furnished to do so, subject to
- * the following conditions:
- *
- * The above copyright notice and this permission notice shall be included
- * in all copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
- * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
- * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
- * IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY
- * CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
- * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
- * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
- */
-#include <xtensa/config/core.h>
-
-#if XCHAL_HAVE_XEA2
-/*
- * C-stubs to issue the tlb related instructions (with dsync and isync's if needed).
- *
- */
-static inline void write_dtlb_entry(unsigned vpn_way, unsigned ppn_ca) {
- __asm__ __volatile__("wdtlb %1, %0; dsync\n\t"
- : : "r" (vpn_way), "r" (ppn_ca) );
-}
-
-static inline void write_itlb_entry(unsigned vpn_way, unsigned ppn_ca) {
- __asm__ __volatile__("witlb %1, %0; isync\n\t"
- : : "r" (vpn_way), "r" (ppn_ca) );
-}
-
-static inline unsigned read_dtlb1_entry(unsigned addr) {
- unsigned long tmp;
- __asm__ __volatile__("rdtlb1 %0, %1\n\t"
- : "=a" (tmp)
- : "a" (addr));
- return tmp;
-}
-
-static inline unsigned read_itlb1_entry(unsigned addr) {
- unsigned long tmp;
- __asm__ __volatile__("ritlb1 %0, %1\n\t"
- : "=a" (tmp)
- : "a" (addr));
- return tmp;
-}
-
-static inline unsigned probe_dtlb(unsigned addr) {
- unsigned long tmp;
- __asm__ __volatile__("pdtlb %0, %1\n\t"
- : "=a" (tmp)
- : "a" (addr));
- return tmp;
-}
-
-static inline unsigned probe_itlb(unsigned addr) {
- unsigned long tmp;
- __asm__ __volatile__("pitlb %0, %1\n\t"
- : "=a" (tmp)
- : "a" (addr));
- return tmp;
-}
-
-static inline void invalidate_dtlb_entry(unsigned addr) {
- __asm__ __volatile__("idtlb %0; dsync \n\t"
- : : "a" (addr));
-}
-
-static inline void invalidate_itlb_entry(unsigned addr) {
- __asm__ __volatile__("iitlb %0 ; isync\n\t"
- : : "a" (addr));
-}
-
-static inline unsigned read_dtlbcfg() {
- unsigned long tmp;
- __asm__ __volatile__("rsr.dtlbcfg %0\n\t"
- : "=a" (tmp));
- return tmp;
-}
-
-static inline unsigned read_itlbcfg() {
- unsigned long tmp;
- __asm__ __volatile__("rsr.itlbcfg %0\n\t"
- : "=a" (tmp));
- return tmp;
-}
-
-#endif
-
-/*
- * xthal_set_region_translation_raw is a quick and simple function
- * to set both physical address <paddr> and cache attribute <cattr> for
- * a 512MB region at <vaddr>.
- *
- * Parameters:
- * void* vaddr 512MB aligned pointer representing the start of virtual address region
- * void* paddr 512MB aligned pointer representing the start of physical address region
- * unsigned cattr 4 bit value encoding the caching properties and rights (MMU only).
- *
- * returns 0 (XCHAL_SUCCESS) if successful
- * returns non zero (XCHAL_UNSUPPORTED_ON_THIS_ARCH) on failure
- *
- * This function has the following limitations:
- *
- * 1) Requires either the Region Translation Option or a v3 MMU running in the default mode (with spanning way)
- * 2) It does no error checking.
- * 3) Deals with one 512MB region (vaddr and paddr are required to be 512MB aligned although that is not explicitly checked)
- * 4) It requires the caller to do any cache flushing that is needed
- * 5) Doesn't support mnemonically setting the 'rights' (rwx, rw, ... ) bit on the MMU
- * 6) It is illegal to change the mapping of the region containing the current PC (not checked)
- *
- */
-int xthal_set_region_translation_raw(void *vaddr, void *paddr, unsigned cattr) {
-#if XCHAL_HAVE_XEA2
-#if XCHAL_HAVE_XLT_CACHEATTR || (XCHAL_HAVE_PTP_MMU && XCHAL_HAVE_SPANNING_WAY)
-# if XCHAL_HAVE_XLT_CACHEATTR
- unsigned vpn_way = (unsigned)vaddr;
-# else
- unsigned vpn_way = ((unsigned) vaddr & 0xFFFFFFF0) + XCHAL_SPANNING_WAY;
-# endif
- unsigned ppn_ca = ((unsigned) paddr & 0xFFFFFFF0) + (cattr & 0xF);
- write_dtlb_entry(vpn_way, ppn_ca);
- write_itlb_entry(vpn_way, ppn_ca);
- return XCHAL_SUCCESS;
-#else
- return XCHAL_UNSUPPORTED_ON_THIS_ARCH;
-#endif
-#else
- return XCHAL_UNSUPPORTED_ON_THIS_ARCH;
-#endif
-}
-
-/*
- * xthal_v2p() takes a virtual address as input, and if that virtual address is mapped to a physical address
- * by the MMU, it returns the:
- * a) corresponding physical address
- * b) the tlb way that is used to translate the address
- * c) cache attribute for translation
- *
- * Parameters:
- * void* vaddr A pointer representing the virtual address (there are no alignment requirements for this address)
- * void** paddr This value can be 0, or can point to a pointer variable which will be updated to contain the physical address
- * unsigned* way This value can be 0, or can point to an unsigned variable which will be updated to contain the TLB way.
- * unsigned* cattr This value can be 0, or can point to an unsigned variable which will be updated to contain the cache attr
- *
- * Returns 0 (XCHAL_SUCCESS) if successful
- * XTHAL_NO_MAPPING if there is no current mapping for the virtual address
- * XCHAL_UNSUPPORTED_ON_THIS_ARCH if unsupported
- *
- * Limitations:
- * Assumes that architecture variable DVARWAY56 is "Variable"
- * Uses the D-TLBS for the translation ... assumption is that ITLB's have same mappings
- */
-int xthal_v2p(void* vaddr, void** paddr, unsigned *way, unsigned* cattr) {
-#if XCHAL_HAVE_XEA2
- unsigned long probe = probe_dtlb((unsigned) vaddr);
-#if !XCHAL_HAVE_PTP_MMU
- if (!(0x1 & probe))
- return XTHAL_NO_MAPPING;
- if (way)
- *way = 1;
- if (paddr || cattr) {
- unsigned long temp;
- temp = read_dtlb1_entry(probe);
- unsigned ppn = 0xe0000000 & temp;
- unsigned att = 0xf & temp;
- if (paddr)
- *paddr = ((void*) (ppn + (((unsigned) vaddr) & 0x1fffffff)));
- if (cattr)
- *cattr = att;
- }
-#else
- {
- unsigned iway;
- if (!(0x10 & probe))
- return XTHAL_NO_MAPPING;
- iway = 0xf & probe;
- if (way)
- *way = iway;
- if (paddr || cattr) {
- unsigned temp;
- unsigned ppn;
- unsigned ppn1;
- unsigned dtlbcfg = read_dtlbcfg();
- temp = read_dtlb1_entry(probe);
- unsigned att = 0xf & temp;
- if (cattr)
- *cattr = att;
- if (paddr)
- switch (iway) // followin code derived from fig 4-40 from ISA MMU Option Data (at) Format for RxTLB1
- { /* 4k pages */
- case 0:
- case 1:
- case 2:
- case 3:
- case 7:
- case 8:
- case 9:
- ppn = 0xfffff000; // 4k pages
- break;
- case 4: {
- switch ((dtlbcfg & (0x3 << 16)) >> 16) // bits 16 & 17
- {
- case 0: // 1MB pages
- ppn = 0xfff00000;
- break;
- case 1: // 4MB pages
- ppn = 0xffc00000;
- break;
- case 2: // 16MB pages
- ppn = 0xff000000;
- break;
- case 3: // 64MB pages
- ppn = 0xfc000000;
- break;
- default:
- return XCHAL_UNSUPPORTED_ON_THIS_ARCH;
- }
- }
- break;
- case 5:
- if ((dtlbcfg & (1 << 20)))
- ppn = 0xf8000000; // 128MB pages
- else
- ppn = 0xf0000000; // 256MB pages
- break;
- case 6:
- if ((dtlbcfg & (1 << 24)))
- ppn = 0xe0000000; // 512MB pages
- else
- ppn = 0xf0000000; // 256MB pages
- break;
- default:
- return XCHAL_UNSUPPORTED_ON_THIS_ARCH;
- break;
- }
- ppn1 = ppn & temp;
- *paddr = ((void*) (ppn1 + (((unsigned) vaddr) & (~ppn))));
- }
- }
-#endif
- return XCHAL_SUCCESS;
-#else
- return XCHAL_UNSUPPORTED_ON_THIS_ARCH;
-#endif
-}
-
-/* these constants borrowed from xthal_set_region_attribute */
-# if XCHAL_HAVE_PTP_MMU
-# define CA_BYPASS XCHAL_CA_BYPASS
-# define CA_WRITETHRU XCHAL_CA_WRITETHRU
-# define CA_WRITEBACK XCHAL_CA_WRITEBACK
-# define CA_WRITEBACK_NOALLOC XCHAL_CA_WRITEBACK_NOALLOC
-# define CA_ILLEGAL XCHAL_CA_ILLEGAL
-# else
-/* Hardcode these, because they get remapped when caches or writeback not configured: */
-# define CA_BYPASS 2
-# define CA_WRITETHRU 1
-# define CA_WRITEBACK 4
-# define CA_WRITEBACK_NOALLOC 5
-# define CA_ILLEGAL 15
-# endif
-
-/* internal function that returns 1 if the supplied attr indicates the
- * cache is in writeback mode.
- */
-static inline int is_writeback(unsigned attr) {
-#if XCHAL_HAVE_XLT_CACHEATTR
- return attr == CA_WRITEBACK || attr == CA_WRITEBACK_NOALLOC;
-#endif
-#if XCHAL_HAVE_PTP_MMU && XCHAL_HAVE_SPANNING_WAY
- return (attr | 0x3) == CA_WRITEBACK;
-#endif
- return -1; /* unsupported */
-}
-
-/*
- * xthal_set_region_translation()
- *
- * Establishes a new mapping (with the supplied cache attributes)
- * between a virtual address region, and a physical address region.
- *
- * This function is only supported with following processor configurations:
- * a) Region Translation
- * b) v3 MMU with a spanning way running in the default mode
- *
- * If the specified memory range exactly covers a series
- * of consecutive 512 MB regions, the address mapping and cache
- * attributes of these regions are updated.
- *
- * If this is not the case, e.g. if either or both the
- * start and end of the range only partially cover a 512 MB
- * region, one of three results are possible:
- *
- * 1. By default, the cache attribute of all regions
- * covered, even just partially, is changed to
- * the requested attribute.
- *
- * 2. If the XTHAL_CAFLAG_EXACT flag is specified,
- * a non-zero error code is returned.
- *
- * 3. If the XTHAL_CAFLAG_NO_PARTIAL flag is specified
- * (but not the EXACT flag), only regions fully
- * covered by the specified range are updated with
- * the requested attribute.
- *
- * CACHE HANDLING
- *
- * This function automatically writes back dirty data before remapping a
- * virtual address region.
- *
- * This writeback is done safely, ie. by first switching to writethrough
- * mode, and then invoking xthal_dcache_all_writeback(). Such a sequence is
- * necessary to ensure there is no longer any dirty data in the memory region by the time
- * this function returns, even in the presence of interrupts, speculation, etc.
- * This automatic write-back can be disabled using the XTHAL_CAFLAG_NO_AUTO_WB flag.
- *
- * This function also invalidates the caches after remapping a region because the
- * cache could contain (now invalid) data from the previous mapping.
- * This automatic invalidate can be disabled using the XTHAL_CAFLAG_NO_AUTO_INV flag.
- *
- * Parameters:
- * vaddr starting virtual address of region of memory
- *
- * paddr starting physical address for the mapping (this should be 512MB aligned to vaddr such that ((vaddr ^ paddr) & 0x10000000 == 0)
- *
- * size number of bytes in region of memory
- * (see above, SPECIFYING THE MEMORY REGION)
- *
- * cattr cache attribute (encoded);
- * typically taken from compile-time HAL constants
- * XCHAL_CA_{BYPASS, WRITETHRU, WRITEBACK[_NOALLOC], ILLEGAL}
- * (defined in <xtensa/config/core.h>);
- * in XEA1, this corresponds to the value of a nibble
- * in the CACHEATTR register;
- * in XEA2, this corresponds to the value of the
- * cache attribute (CA) field of each TLB entry
- *
- * flags bitwise combination of flags XTHAL_CAFLAG_*
- *
- * XTHAL_CAFLAG_EXACT - If this flag is present,
- * the mapping will only be done if the specified
- * region exactly matches on or more 512MB pages otherwise
- * XCHAL_INEXACT is returned (and no mapping is done).
- *
- * XTHAL_CAFLAG_NO_PARTIAL - If this flag is specified, then
- * only pages that are completely covered by the specified region
- * are affected. If this flag is specified, and no pages are completely
- * covered by the region, then no pages are affected and XCHAL_NO_PAGES_MAPPED
- * is returned.
- *
- *
- *
- * Returns:
- * XCHAL_SUCCESS - successful, or size is zero
- *
- * XCHAL_NO_PAGES_MAPPED - XTHAL_CAFLAG_NO_PARTIAL flag specified and address range
- * is valid with a non-zero size, however no 512 MB region (or page)
- * is completely covered by the range
- *
- * XCHAL_INEXACT XTHAL_CAFLAG_EXACT flag specified, and address range does
- * not exactly specify a 512 MB region (or page)
- *
- * XCHAL_INVALID_ADDRESS invalid address range specified (wraps around the end of memory)
- *
- * XCHAL_ADDRESS_MISALIGNED virtual and physical addresses are not aligned (512MB)
- *
- *
- * XCHAL_UNSUPPORTED_ON_THIS_ARCH function not supported in this processor configuration
- */
-int xthal_set_region_translation(void* vaddr, void* paddr, unsigned size,
- unsigned cattr, unsigned flags) {
-#if XCHAL_HAVE_XEA2
-#if XCHAL_HAVE_XLT_CACHEATTR || (XCHAL_HAVE_PTP_MMU && XCHAL_HAVE_SPANNING_WAY)
- const unsigned CA_MASK = 0xF;
- const unsigned addr_mask = 0x1fffffff;
- const unsigned addr_shift = 29;
- unsigned vaddr_a = (unsigned) vaddr;
- unsigned paddr_a = (unsigned) paddr;
- unsigned end_vaddr;
- unsigned end_paddr;
- unsigned start_va_reg;
- unsigned end_va_reg;
- unsigned start_pa_reg;
- unsigned icache_attr = 0;
- int rv;
- int i;
- if (size == 0)
- return XCHAL_SUCCESS;
- if ((vaddr_a & addr_mask) ^ (paddr_a & addr_mask))
- return XCHAL_ADDRESS_MISALIGNED;
- icache_attr = cattr & CA_MASK;
-#if (XCHAL_HAVE_PTP_MMU && XCHAL_HAVE_SPANNING_WAY)
- // if using the mmu in spanning way mode then 'and in' the R, RX, RW, RWX bits
- if ((cattr & 0x40000000) && (icache_attr < 12))
- icache_attr = icache_attr & ((cattr & 0xF0) >> 4);
-#endif
- end_vaddr = vaddr_a + size - 1;
- end_paddr = paddr_a + size - 1;
-
- if ((end_vaddr < vaddr_a) || (end_paddr < paddr_a))
- return XCHAL_INVALID_ADDRESS;
- start_va_reg = vaddr_a >> addr_shift;
- end_va_reg = end_vaddr >> addr_shift;
- start_pa_reg = paddr_a >> addr_shift;
- if ((flags & XTHAL_CAFLAG_EXACT)
- && ((size & addr_mask) || (vaddr_a & addr_mask)
- || (paddr_a & addr_mask)))
- return XCHAL_INEXACT;
- if (flags & XTHAL_CAFLAG_NO_PARTIAL) {
- if (vaddr_a & addr_mask) {
- start_va_reg++;
- start_pa_reg++;
- }
- if ((end_vaddr & addr_mask) != addr_mask)
- end_va_reg--;
- }
- if (end_va_reg < start_va_reg)
- return XCHAL_NO_PAGES_MAPPED;
- /*
- * Now we need to take care of any uncommitted cache writes in the affected regions
- * 1) first determine if any regions are in write back mode
- * 2) change those pages to write through
- * 3) force the writeback of d-cache by calling xthal_dcach_all_writeback()
- */
-#if ((XCHAL_DCACHE_SIZE >0) && XCHAL_DCACHE_IS_WRITEBACK)
- if (!(flags & XTHAL_CAFLAG_NO_AUTO_WB)) {
- unsigned old_cache_attr = xthal_get_cacheattr();
- unsigned cachewrtr = old_cache_attr;
- unsigned need_safe_writeback = 0;
- for (i = start_va_reg; i <= end_va_reg; i++) {
- unsigned sh = i << 2;
- unsigned old_attr = (old_cache_attr >> sh) & CA_MASK;
- if (is_writeback(old_attr)) {
- need_safe_writeback = 1;
- cachewrtr = (cachewrtr & ~(CA_MASK << sh))
- | (CA_WRITETHRU << sh);
- }
- }
-
- if (need_safe_writeback) {
- xthal_set_cacheattr(cachewrtr); /* set to writethru first, to safely writeback any dirty data */
- xthal_dcache_all_writeback(); /* much quicker than scanning entire 512MB region(s) */
- }
- }
-#endif
- /* Now we set the affected region translations */
- for (i = start_va_reg; i <= end_va_reg; i++) {
- if ((rv = xthal_set_region_translation_raw(
- (void*) ((start_va_reg++) << addr_shift),
- (void*) ((start_pa_reg++) << addr_shift), icache_attr)))
- return rv;
- }
-
- /*
- * Now we need to invalidate the cache in the affected regions. For now invalidate entire cache,
- * but investigate if there are faster alternatives on some architectures.
- */
- if (!(flags & XTHAL_CAFLAG_NO_AUTO_INV)) {
-# if XCHAL_DCACHE_SIZE > 0
- xthal_dcache_all_writeback_inv(); /* some areas in memory (outside the intended region) may have uncommitted
- data so we need the writeback_inv(). */
-#endif
-#if XCHAL_ICACHE_SIZE >0
- xthal_icache_all_invalidate();
-#endif
- }
- return XCHAL_SUCCESS;
-#else
- return XCHAL_UNSUPPORTED_ON_THIS_ARCH;
-#endif
-#else
- return XCHAL_UNSUPPORTED_ON_THIS_ARCH;
-#endif
-}
-
-/* xthal_invalidate_region()
- * invalidates the tlb entry for the specified region.
- *
- * This function is only supported on processor configurations
- * with a v3 MMU with a spanning way.
- *
- * Parameter
- * vaddr - virtual address of region to invalidate (512MB aligned)
- *
- * returns:
- * XCHAL_SUCCESS - Success
- * XCHAL_UNSUPPORTED_ON_THIS_ARCH - Unsupported
- *
- */
-int xthal_invalidate_region(void* vaddr) {
-#if XCHAL_HAVE_XEA2
-#if (XCHAL_HAVE_PTP_MMU && XCHAL_HAVE_SPANNING_WAY)
- unsigned addr = (unsigned) vaddr;
- if (addr & 0x1fffffff)
- return XCHAL_INVALID_ADDRESS;
- addr += XCHAL_SPANNING_WAY;
- invalidate_dtlb_entry(addr);
- invalidate_itlb_entry(addr);
- return XCHAL_SUCCESS;
-#else
- return XCHAL_UNSUPPORTED_ON_THIS_ARCH;
-#endif
-#else
- return XCHAL_UNSUPPORTED_ON_THIS_ARCH;
-#endif
-}
-
diff --git a/src/arch/xtensa/up/hal/state.c b/src/arch/xtensa/up/hal/state.c
deleted file mode 100644
index 62351f0..0000000
--- a/src/arch/xtensa/up/hal/state.c
+++ /dev/null
@@ -1,336 +0,0 @@
-//
-// processor_state.c - processor state management routines
-//
-
-// Copyright (c) 2005-2010 Tensilica Inc.
-//
-// Permission is hereby granted, free of charge, to any person obtaining
-// a copy of this software and associated documentation files (the
-// "Software"), to deal in the Software without restriction, including
-// without limitation the rights to use, copy, modify, merge, publish,
-// distribute, sublicense, and/or sell copies of the Software, and to
-// permit persons to whom the Software is furnished to do so, subject to
-// the following conditions:
-//
-// The above copyright notice and this permission notice shall be included
-// in all copies or substantial portions of the Software.
-//
-// THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
-// EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
-// MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
-// IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY
-// CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
-// TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
-// SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
-
-#include <xtensa/hal.h>
-#include <xtensa/config/specreg.h>
-#include <xtensa/config/core.h>
-
-
-//----------------------------------------------------------------------
-
-#if defined(__SPLIT__extra_size)
-// space for "extra" (user special registers and non-coprocessor TIE) state:
-const unsigned int Xthal_extra_size = XCHAL_NCP_SA_SIZE;
-
-#endif
-#if defined(__SPLIT__extra_align)
-const unsigned int Xthal_extra_align = XCHAL_NCP_SA_ALIGN;
-
-#endif
-#if defined(__SPLIT__cpregs_size)
-// space for state of TIE coprocessors:
-const unsigned int Xthal_cpregs_size[8] =
- {
- XCHAL_CP0_SA_SIZE,
- XCHAL_CP1_SA_SIZE,
- XCHAL_CP2_SA_SIZE,
- XCHAL_CP3_SA_SIZE,
- XCHAL_CP4_SA_SIZE,
- XCHAL_CP5_SA_SIZE,
- XCHAL_CP6_SA_SIZE,
- XCHAL_CP7_SA_SIZE
- };
-
-#endif
-#if defined(__SPLIT__cpregs_align)
-const unsigned int Xthal_cpregs_align[8] =
- {
- XCHAL_CP0_SA_ALIGN,
- XCHAL_CP1_SA_ALIGN,
- XCHAL_CP2_SA_ALIGN,
- XCHAL_CP3_SA_ALIGN,
- XCHAL_CP4_SA_ALIGN,
- XCHAL_CP5_SA_ALIGN,
- XCHAL_CP6_SA_ALIGN,
- XCHAL_CP7_SA_ALIGN
- };
-
-#endif
-#if defined(__SPLIT__cp_names)
-const char * const Xthal_cp_names[8] =
- {
- XCHAL_CP0_NAME,
- XCHAL_CP1_NAME,
- XCHAL_CP2_NAME,
- XCHAL_CP3_NAME,
- XCHAL_CP4_NAME,
- XCHAL_CP5_NAME,
- XCHAL_CP6_NAME,
- XCHAL_CP7_NAME
- };
-
-#endif
-#if defined(__SPLIT__all_extra_size)
-// total save area size (extra + all coprocessors + min 16-byte alignment everywhere)
-const unsigned int Xthal_all_extra_size = XCHAL_TOTAL_SA_SIZE;
-
-#endif
-#if defined(__SPLIT__all_extra_align)
-// maximum required alignment for the total save area (this might be useful):
-const unsigned int Xthal_all_extra_align = XCHAL_TOTAL_SA_ALIGN;
-
-#endif
-#if defined(__SPLIT__num_coprocessors)
-// number of coprocessors starting contiguously from zero
-// (same as Xthal_cp_max, but included for Tornado2):
-const unsigned int Xthal_num_coprocessors = XCHAL_CP_MAX;
-
-#endif
-#if defined(__SPLIT__cp_num)
-// actual number of coprocessors:
-const unsigned char Xthal_cp_num = XCHAL_CP_NUM;
-
-#endif
-#if defined(__SPLIT__cp_max)
-// index of highest numbered coprocessor, plus one:
-const unsigned char Xthal_cp_max = XCHAL_CP_MAX;
-
-// index of highest allowed coprocessor number, per cfg, plus one:
-//const unsigned char Xthal_cp_maxcfg = XCHAL_CP_MAXCFG;
-
-#endif
-#if defined(__SPLIT__cp_mask)
-// bitmask of which coprocessors are present:
-const unsigned int Xthal_cp_mask = XCHAL_CP_MASK;
-
-#endif
-#if defined(__SPLIT__cp_id_mappings)
-// Coprocessor ID from its name
-
-# ifdef XCHAL_CP0_IDENT
-const unsigned char XCJOIN(Xthal_cp_id_,XCHAL_CP0_IDENT) = 0;
-# endif
-# ifdef XCHAL_CP1_IDENT
-const unsigned char XCJOIN(Xthal_cp_id_,XCHAL_CP1_IDENT) = 1;
-# endif
-# ifdef XCHAL_CP2_IDENT
-const unsigned char XCJOIN(Xthal_cp_id_,XCHAL_CP2_IDENT) = 2;
-# endif
-# ifdef XCHAL_CP3_IDENT
-const unsigned char XCJOIN(Xthal_cp_id_,XCHAL_CP3_IDENT) = 3;
-# endif
-# ifdef XCHAL_CP4_IDENT
-const unsigned char XCJOIN(Xthal_cp_id_,XCHAL_CP4_IDENT) = 4;
-# endif
-# ifdef XCHAL_CP5_IDENT
-const unsigned char XCJOIN(Xthal_cp_id_,XCHAL_CP5_IDENT) = 5;
-# endif
-# ifdef XCHAL_CP6_IDENT
-const unsigned char XCJOIN(Xthal_cp_id_,XCHAL_CP6_IDENT) = 6;
-# endif
-# ifdef XCHAL_CP7_IDENT
-const unsigned char XCJOIN(Xthal_cp_id_,XCHAL_CP7_IDENT) = 7;
-# endif
-
-#endif
-#if defined(__SPLIT__cp_mask_mappings)
-// Coprocessor "mask" (1 << ID) from its name
-
-# ifdef XCHAL_CP0_IDENT
-const unsigned int XCJOIN(Xthal_cp_mask_,XCHAL_CP0_IDENT) = (1 << 0);
-# endif
-# ifdef XCHAL_CP1_IDENT
-const unsigned int XCJOIN(Xthal_cp_mask_,XCHAL_CP1_IDENT) = (1 << 1);
-# endif
-# ifdef XCHAL_CP2_IDENT
-const unsigned int XCJOIN(Xthal_cp_mask_,XCHAL_CP2_IDENT) = (1 << 2);
-# endif
-# ifdef XCHAL_CP3_IDENT
-const unsigned int XCJOIN(Xthal_cp_mask_,XCHAL_CP3_IDENT) = (1 << 3);
-# endif
-# ifdef XCHAL_CP4_IDENT
-const unsigned int XCJOIN(Xthal_cp_mask_,XCHAL_CP4_IDENT) = (1 << 4);
-# endif
-# ifdef XCHAL_CP5_IDENT
-const unsigned int XCJOIN(Xthal_cp_mask_,XCHAL_CP5_IDENT) = (1 << 5);
-# endif
-# ifdef XCHAL_CP6_IDENT
-const unsigned int XCJOIN(Xthal_cp_mask_,XCHAL_CP6_IDENT) = (1 << 6);
-# endif
-# ifdef XCHAL_CP7_IDENT
-const unsigned int XCJOIN(Xthal_cp_mask_,XCHAL_CP7_IDENT) = (1 << 7);
-# endif
-
-//----------------------------------------------------------------------
-
-#endif
-#if defined(__SPLIT__init_mem_extra)
-// CMS: I have made the assumptions that 0's are safe initial
-// values. That may be wrong at some point.
-//
-// initialize the extra processor
-void
-xthal_init_mem_extra(void *address)
-/* not clear that it is safe to call memcpy and also not clear
- that performance is important. */
-{
- unsigned int *ptr;
- unsigned int *end;
-
- ptr = (unsigned int *)address;
- end = (unsigned int *)((int)address + XCHAL_NCP_SA_SIZE);
- while( ptr < end )
- {
- *ptr++ = 0;
- }
-}
-
-#endif
-#if defined(__SPLIT__init_mem_cp)
-// initialize the TIE coprocessor
-void
-xthal_init_mem_cp(void *address, int cp)
-{
- unsigned int *ptr;
- unsigned int *end;
-
- if( cp <= 7 )
- {
- end = (unsigned int *)((int)address + Xthal_cpregs_size[cp]);
- ptr = (unsigned int *)address;
- while( ptr < end )
- {
- *ptr++ = 0;
- }
- }
-}
-
-#endif /*splitting*/
-
-
-/* Nothing implemented below this point. */
-/************************************************************************/
-
-// save all extra+cp processor state (NOT IMPLEMENTED)
-/*void xthal_save_all_extra(void *base)
-{
- xthal_save_extra(base);
- ... here we need to iterate over configured coprocessor register files ...
-// xthal_save_cpregs(base+XCHAL_NCP_SA_SIZE, 0);
-}*/
-
-// restore all extra+cp processor state (NOT IMPLEMENTED)
-/*void xthal_restore_all_extra(void *base)
-{
- xthal_restore_extra(base);
- ... here we need to iterate over configured coprocessor register files ...
-// xthal_restore_cpregs(base+XCHAL_NCP_SA_SIZE, 0);
-}*/
-
-
-// initialize the extra processor (NOT IMPLEMENTED)
-/*void xthal_init_extra()
-{
-}*/
-
-// initialize the TIE coprocessor (NOT IMPLEMENTED)
-/*void xthal_init_cp(int cp)
-{
-}*/
-
-
-#if 0
-
-/* read extra state register (NOT IMPLEMENTED) */
-int xthal_read_extra(void *base, unsigned reg, unsigned *value)
-{
- if (reg&0x1000) {
- switch(reg) {
-#if XCHAL_HAVE_MAC16
- case 16:
- *value = ((unsigned *)base)[0];
- return reg;
- case 17:
- *value = ((unsigned *)base)[1];
- return reg;
- case 32:
- *value = ((unsigned *)base)[2];
- return reg;
- case 33:
- *value = ((unsigned *)base)[3];
- return reg;
- case 34:
- *value = ((unsigned *)base)[4];
- return reg;
- case 35:
- *value = ((unsigned *)base)[5];
- return reg;
-#endif /* XCHAL_HAVE_MAC16 */
- }
- }
- return -1;
-}
-
-/* write extra state register (NOT IMPLEMENTED) */
-int xthal_write_extra(void *base, unsigned reg, unsigned value)
-{
- if (reg&0x1000) {
- switch(reg) {
-#if XCHAL_HAVE_MAC16
- case 16:
- ((unsigned *)base)[0] = value;
- return reg;
- case 17:
- ((unsigned *)base)[1] = value;
- return reg;
- case 32:
- ((unsigned *)base)[2] = value;
- return reg;
- case 33:
- ((unsigned *)base)[3] = value;
- return reg;
- case 34:
- ((unsigned *)base)[4] = value;
- return reg;
- case 35:
- ((unsigned *)base)[5] = value;
- return reg;
-#endif /* XCHAL_HAVE_MAC16 */
- }
- }
- return -1;
-}
-
-#endif /*0*/
-
-
-/* read TIE coprocessor register (NOT IMPLEMENTED) */
-/*int xthal_read_cpreg(void *base, int cp, unsigned reg, unsigned *value)
-{
- return -1;
-}*/
-
-/* write TIE coproessor register (NOT IMPLEMENTED) */
-/*int xthal_write_cpreg(void *base, int cp, unsigned reg, unsigned value)
-{
- return -1;
-}*/
-
-/* return coprocessor number based on register (NOT IMPLEMENTED) */
-/*int xthal_which_cp(unsigned reg)
-{
- return -1;
-}*/
-
diff --git a/src/arch/xtensa/up/hal/state_asm.S b/src/arch/xtensa/up/hal/state_asm.S
deleted file mode 100644
index e15a985..0000000
--- a/src/arch/xtensa/up/hal/state_asm.S
+++ /dev/null
@@ -1,703 +0,0 @@
-/*
- * state_asm.S - assembly language processor management routines
- */
-
-/*
- * Copyright (c) 2005-2010 Tensilica Inc.
- *
- * Permission is hereby granted, free of charge, to any person obtaining
- * a copy of this software and associated documentation files (the
- * "Software"), to deal in the Software without restriction, including
- * without limitation the rights to use, copy, modify, merge, publish,
- * distribute, sublicense, and/or sell copies of the Software, and to
- * permit persons to whom the Software is furnished to do so, subject to
- * the following conditions:
- *
- * The above copyright notice and this permission notice shall be included
- * in all copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
- * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
- * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
- * IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY
- * CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
- * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
- * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
- */
-
-#include <xtensa/coreasm.h>
-
-/* For Call0 ABI, the xthal... and xthal..._nw versions are identical,
- * so we define both labels for the same function body. The Makefile
- * does not define any of the __SPLIT__..._nw macros if Call0 ABI.
- * Use SYM() when we don't want .type information. */
-
-#if defined (__XTENSA_CALL0_ABI__)
-# define SYMBOL(x) _SYMT(x); _SYMT(x ## _nw)
-#else
-# define SYMBOL(x) _SYMT(x)
-#endif
-
- .text
-
-//----------------------------------------------------------------------
-// save the extra processor state.
-//----------------------------------------------------------------------
-
-#if defined(__SPLIT__save_extra)
-
-// void xthal_save_extra(void *base)
-
-SYMBOL(xthal_save_extra)
- abi_entry
- xchal_extra_store_funcbody
- abi_return
- endfunc
-
-#endif
-#if defined(__SPLIT__save_extra_nw)
-
-// void xthal_save_extra_nw(void *base)
-
-_SYM(xthal_save_extra_nw)
- //addi sp, sp, 0
- xchal_extra_store_funcbody
- ret
- endfunc
-
-
-//----------------------------------------------------------------------
-// restore the extra processor state.
-//----------------------------------------------------------------------
-
-#endif
-#if defined(__SPLIT__restore_extra)
-
-// void xthal_restore_extra(void *base)
-
-SYMBOL(xthal_restore_extra)
- abi_entry
- xchal_extra_load_funcbody
- abi_return
- endfunc
-
-#endif
-#if defined(__SPLIT__restore_extra_nw)
-
-// void xthal_restore_extra_nw(void *base)
-
-_SYM(xthal_restore_extra_nw)
- //addi sp, sp, 0
- xchal_extra_load_funcbody
- ret
- endfunc
-
-
-//----------------------------------------------------------------------
-// save the TIE COPROCESSORS state
-//----------------------------------------------------------------------
-
-#endif
-#if defined(__SPLIT__save_cpregs)
-
-// void xthal_save_cpregs(void *base, int)
-
-SYMBOL(xthal_save_cpregs)
- abi_entry
- xchal_cpi_store_funcbody
- abi_return
- endfunc
-
-#endif
-#if defined(__SPLIT__save_cp0)
-// void xthal_save_cp0(void *base)
-SYMBOL(xthal_save_cp0)
- abi_entry
- xchal_cp0_store_a2
- abi_return
- endfunc
-#endif
-#if defined(__SPLIT__save_cp1)
-// void xthal_save_cp1(void *base)
-SYMBOL(xthal_save_cp1)
- abi_entry
- xchal_cp1_store_a2
- abi_return
- endfunc
-#endif
-#if defined(__SPLIT__save_cp2)
-// void xthal_save_cp2(void *base)
-SYMBOL(xthal_save_cp2)
- abi_entry
- xchal_cp2_store_a2
- abi_return
- endfunc
-#endif
-#if defined(__SPLIT__save_cp3)
-// void xthal_save_cp3(void *base)
-SYMBOL(xthal_save_cp3)
- abi_entry
- xchal_cp3_store_a2
- abi_return
- endfunc
-#endif
-#if defined(__SPLIT__save_cp4)
-// void xthal_save_cp4(void *base)
-SYMBOL(xthal_save_cp4)
- abi_entry
- xchal_cp4_store_a2
- abi_return
- endfunc
-#endif
-#if defined(__SPLIT__save_cp5)
-// void xthal_save_cp5(void *base)
-SYMBOL(xthal_save_cp5)
- abi_entry
- xchal_cp5_store_a2
- abi_return
- endfunc
-#endif
-#if defined(__SPLIT__save_cp6)
-// void xthal_save_cp6(void *base)
-SYMBOL(xthal_save_cp6)
- abi_entry
- xchal_cp6_store_a2
- abi_return
- endfunc
-#endif
-#if defined(__SPLIT__save_cp7)
-// void xthal_save_cp7(void *base)
-SYMBOL(xthal_save_cp7)
- abi_entry
- xchal_cp7_store_a2
- abi_return
- endfunc
-
-#endif
-#if defined(__SPLIT__save_cpregs_nw)
-
-// void xthal_save_cpregs_nw(void *base, int)
-
-_SYM(xthal_save_cpregs_nw)
- //addi sp, sp, 0
- xchal_cpi_store_funcbody
- ret
- endfunc
-
-#endif
-#if defined(__SPLIT__save_cp0_nw)
-// void xthal_save_cp0(void *base)
-_SYM(xthal_save_cp0_nw)
- //addi sp, sp, 0
- xchal_cp0_store_a2
- ret
- endfunc
-#endif
-#if defined(__SPLIT__save_cp1_nw)
-// void xthal_save_cp1(void *base)
-_SYM(xthal_save_cp1_nw)
- //addi sp, sp, 0
- xchal_cp1_store_a2
- ret
- endfunc
-#endif
-#if defined(__SPLIT__save_cp2_nw)
-// void xthal_save_cp2(void *base)
-_SYM(xthal_save_cp2_nw)
- //addi sp, sp, 0
- xchal_cp2_store_a2
- ret
- endfunc
-#endif
-#if defined(__SPLIT__save_cp3_nw)
-// void xthal_save_cp3(void *base)
-_SYM(xthal_save_cp3_nw)
- //addi sp, sp, 0
- xchal_cp3_store_a2
- ret
- endfunc
-#endif
-#if defined(__SPLIT__save_cp4_nw)
-// void xthal_save_cp4(void *base)
-_SYM(xthal_save_cp4_nw)
- //addi sp, sp, 0
- xchal_cp4_store_a2
- ret
- endfunc
-#endif
-#if defined(__SPLIT__save_cp5_nw)
-// void xthal_save_cp5(void *base)
-_SYM(xthal_save_cp5_nw)
- //addi sp, sp, 0
- xchal_cp5_store_a2
- ret
- endfunc
-#endif
-#if defined(__SPLIT__save_cp6_nw)
-// void xthal_save_cp6(void *base)
-_SYM(xthal_save_cp6_nw)
- //addi sp, sp, 0
- xchal_cp6_store_a2
- ret
- endfunc
-#endif
-#if defined(__SPLIT__save_cp7_nw)
-// void xthal_save_cp7(void *base)
-_SYM(xthal_save_cp7_nw)
- //addi sp, sp, 0
- xchal_cp7_store_a2
- ret
- endfunc
-
-
-//----------------------------------------------------------------------
-// restore the TIE coprocessor state
-//----------------------------------------------------------------------
-
-#endif
-#if defined(__SPLIT__restore_cpregs)
-
-// void xthal_restore_cpregs(void *base, int)
-
-SYMBOL(xthal_restore_cpregs)
- abi_entry
- xchal_cpi_load_funcbody
- abi_return
- endfunc
-
-#endif
-#if defined(__SPLIT__restore_cp0)
-// void xthal_restore_cp0(void *base)
-SYMBOL(xthal_restore_cp0)
- abi_entry
- xchal_cp0_load_a2
- abi_return
- endfunc
-#endif
-#if defined(__SPLIT__restore_cp1)
-// void xthal_restore_cp1(void *base)
-SYMBOL(xthal_restore_cp1)
- abi_entry
- xchal_cp1_load_a2
- abi_return
- endfunc
-#endif
-#if defined(__SPLIT__restore_cp2)
-// void xthal_restore_cp2(void *base)
-SYMBOL(xthal_restore_cp2)
- abi_entry
- xchal_cp2_load_a2
- abi_return
- endfunc
-#endif
-#if defined(__SPLIT__restore_cp3)
-// void xthal_restore_cp3(void *base)
-SYMBOL(xthal_restore_cp3)
- abi_entry
- xchal_cp3_load_a2
- abi_return
- endfunc
-#endif
-#if defined(__SPLIT__restore_cp4)
-// void xthal_restore_cp4(void *base)
-SYMBOL(xthal_restore_cp4)
- abi_entry
- xchal_cp4_load_a2
- abi_return
- endfunc
-#endif
-#if defined(__SPLIT__restore_cp5)
-// void xthal_restore_cp5(void *base)
-SYMBOL(xthal_restore_cp5)
- abi_entry
- xchal_cp5_load_a2
- abi_return
- endfunc
-#endif
-#if defined(__SPLIT__restore_cp6)
-// void xthal_restore_cp6(void *base)
-SYMBOL(xthal_restore_cp6)
- abi_entry
- xchal_cp6_load_a2
- abi_return
- endfunc
-#endif
-#if defined(__SPLIT__restore_cp7)
-// void xthal_restore_cp7(void *base)
-SYMBOL(xthal_restore_cp7)
- abi_entry
- xchal_cp7_load_a2
- abi_return
- endfunc
-
-#endif
-#if defined(__SPLIT__restore_cpregs_nw)
-
-// void xthal_restore_cpregs_nw(void *base, int)
-
-_SYM(xthal_restore_cpregs_nw)
- //addi sp, sp, 0
- xchal_cpi_load_funcbody
- ret
- endfunc
-
-#endif
-#if defined(__SPLIT__restore_cp0_nw)
-// void xthal_restore_cp0(void *base)
-_SYM(xthal_restore_cp0_nw)
- //addi sp, sp, 0
- xchal_cp0_load_a2
- ret
- endfunc
-#endif
-#if defined(__SPLIT__restore_cp1_nw)
-// void xthal_restore_cp1(void *base)
-_SYM(xthal_restore_cp1_nw)
- //addi sp, sp, 0
- xchal_cp1_load_a2
- ret
- endfunc
-#endif
-#if defined(__SPLIT__restore_cp2_nw)
-// void xthal_restore_cp2(void *base)
-_SYM(xthal_restore_cp2_nw)
- //addi sp, sp, 0
- xchal_cp2_load_a2
- ret
- endfunc
-#endif
-#if defined(__SPLIT__restore_cp3_nw)
-// void xthal_restore_cp3(void *base)
-_SYM(xthal_restore_cp3_nw)
- //addi sp, sp, 0
- xchal_cp3_load_a2
- ret
- endfunc
-#endif
-#if defined(__SPLIT__restore_cp4_nw)
-// void xthal_restore_cp4(void *base)
-_SYM(xthal_restore_cp4_nw)
- //addi sp, sp, 0
- xchal_cp4_load_a2
- ret
- endfunc
-#endif
-#if defined(__SPLIT__restore_cp5_nw)
-// void xthal_restore_cp5(void *base)
-SYM(xthal_restore_cp5_nw)
- //addi sp, sp, 0
- xchal_cp5_load_a2
- ret
- endfunc
-#endif
-#if defined(__SPLIT__restore_cp6_nw)
-// void xthal_restore_cp6(void *base)
-_SYM(xthal_restore_cp6_nw)
- //addi sp, sp, 0
- xchal_cp6_load_a2
- ret
- endfunc
-#endif
-#if defined(__SPLIT__restore_cp7_nw)
-// void xthal_restore_cp7(void *base)
-_SYM(xthal_restore_cp7_nw)
- //addi sp, sp, 0
- xchal_cp7_load_a2
- ret
- endfunc
-
-#endif
-#if defined(__SPLIT__cpregs_save_fn)
- .section .rodata, "a"
-_SYM(Xthal_cpregs_save_fn)
-# ifdef __XTENSA_CALL0_ABI__
-_SYM(Xthal_cpregs_save_nw_fn)
-# endif
- .long xthal_save_cp0
- .long xthal_save_cp1
- .long xthal_save_cp2
- .long xthal_save_cp3
- .long xthal_save_cp4
- .long xthal_save_cp5
- .long xthal_save_cp6
- .long xthal_save_cp7
- endfunc
- .text
-
-#endif
-#if defined(__SPLIT__cpregs_save_nw_fn)
-# ifndef __XTENSA_CALL0_ABI__
- .section .rodata, "a"
-_SYM(Xthal_cpregs_save_nw_fn)
- .long xthal_save_cp0_nw
- .long xthal_save_cp1_nw
- .long xthal_save_cp2_nw
- .long xthal_save_cp3_nw
- .long xthal_save_cp4_nw
- .long xthal_save_cp5_nw
- .long xthal_save_cp6_nw
- .long xthal_save_cp7_nw
- endfunc
- .text
-# endif
-
-#endif
-#if defined(__SPLIT__cpregs_restore_fn)
- .section .rodata, "a"
-_SYM(Xthal_cpregs_restore_fn)
-# ifdef __XTENSA_CALL0_ABI__
-_SYM(Xthal_cpregs_restore_nw_fn)
-# endif
- .long xthal_restore_cp0
- .long xthal_restore_cp1
- .long xthal_restore_cp2
- .long xthal_restore_cp3
- .long xthal_restore_cp4
- .long xthal_restore_cp5
- .long xthal_restore_cp6
- .long xthal_restore_cp7
- endfunc
- .text
-
-#endif
-#if defined(__SPLIT__cpregs_restore_nw_fn)
-# ifndef __XTENSA_CALL0_ABI__
- .section .rodata, "a"
-_SYM(Xthal_cpregs_restore_nw_fn)
- .long xthal_restore_cp0_nw
- .long xthal_restore_cp1_nw
- .long xthal_restore_cp2_nw
- .long xthal_restore_cp3_nw
- .long xthal_restore_cp4_nw
- .long xthal_restore_cp5_nw
- .long xthal_restore_cp6_nw
- .long xthal_restore_cp7_nw
- endfunc
- .text
-# endif
-
-
-//----------------------------------------------------------------------
-// coprocessor enable/disable
-//----------------------------------------------------------------------
-
-#endif
-#if defined(__SPLIT__validate_cp)
-
-// validate the register file.
-// void xthal_validate_cp(int)
-
-SYMBOL(xthal_validate_cp)
- abi_entry
-#if XCHAL_HAVE_CP
- rsr a3, CPENABLE
- movi a4, 1
- ssl a2
- sll a4, a4
- or a3, a3, a4
- wsr a3, CPENABLE
-#endif
- abi_return
- endfunc
-
-#endif
-#if defined(__SPLIT__validate_cp_nw)
-
-// validate the register file.
-// void xthal_validate_cp_nw(int)
-
-_SYM(xthal_validate_cp_nw)
- //addi sp, sp, 0
-#if XCHAL_HAVE_CP
- rsr a3, CPENABLE
- movi a4, 1
- ssl a2
- sll a4, a4
- or a3, a3, a4
- wsr a3, CPENABLE
-#endif
- ret
- endfunc
-
-#endif
-#if defined(__SPLIT__invalidate_cp)
-
-// invalidate the register file.
-// void xthal_invalidate_cp(int)
-
-SYMBOL(xthal_invalidate_cp)
- abi_entry
-#if XCHAL_HAVE_CP
- rsr a3, CPENABLE
- movi a4, 1
- ssl a2
- sll a4, a4
- and a4, a3, a4
- xor a3, a3, a4
- wsr a3, CPENABLE
-#endif
- abi_return
- endfunc
-
-#endif
-#if defined(__SPLIT__invalidate_cp_nw)
-
-// invalidate the register file.
-// void xthal_invalidate_cp_nw(int)
-
-SYMBOL(xthal_invalidate_cp_nw)
- //addi sp, sp, 0
-#if XCHAL_HAVE_CP
- rsr a3, CPENABLE
- movi a4, 1
- ssl a2
- sll a4, a4
- and a4, a3, a4
- xor a3, a3, a4
- wsr a3, CPENABLE
-#endif
- ret
- endfunc
-
-
-//----------------------------------------------------------------------
-// Access the CPENABLE register
-//----------------------------------------------------------------------
-
-#endif
-#if defined(__SPLIT__get_cpenable)
-
-// unsigned xthal_get_cpenable(void);
-
-SYMBOL(xthal_get_cpenable)
- abi_entry
-#if XCHAL_HAVE_CP
- rsr a2, CPENABLE
-#else
- movi a2, 0 // if no CPENABLE (no coprocessors), none is ever enabled
-#endif
- abi_return
- endfunc
-
-#endif
-#if defined(__SPLIT__get_cpenable_nw)
-
-// unsigned xthal_get_cpenable_nw(void);
-
-_SYM(xthal_get_cpenable_nw)
- //addi sp, sp, 0
-#if XCHAL_HAVE_CP
- rsr a2, CPENABLE
-#else
- movi a2, 0 // if no CPENABLE (no coprocessors), none is ever enabled
-#endif
- ret
- endfunc
-
-#endif
-#if defined(__SPLIT__set_cpenable)
-
-// void xthal_set_cpenable(unsigned);
-//
-// Note: to help asm code performance (eg. OS task switch),
-// this routine returns the previous value of CPENABLE in a3
-// (not a2, because that could require an extra mov instruction).
-// This return value is not shown in the prototype, because
-// C code won't see it.
-// [Perhaps this should go in an RTOS-specific Core HAL or BSP. TBD.]
-
-SYMBOL(xthal_set_cpenable)
- abi_entry
-#if XCHAL_HAVE_CP
- //rsr a3, CPENABLE // return previous CPENABLE
- movi a3, 0 // for now, always return 0 (VxWorks currently done that way)
-
- wsr a2, CPENABLE
-#else
- movi a3, 0 // if no CPENABLE (no coprocessors), none is ever enabled
-#endif
- abi_return
- endfunc
-
-#endif
-#if defined(__SPLIT__set_cpenable_nw)
-
-// unsigned[a3] xthal_set_cpenable_nw(unsigned);
-//
-// Note: to help asm code performance (eg. OS task switch),
-// this routine returns the previous value of CPENABLE in a3
-// (not a2, because that could require an extra mov instruction).
-
-SYMBOL(xthal_set_cpenable_nw)
- //addi sp, sp, 0
-#if XCHAL_HAVE_CP
- //rsr a3, CPENABLE // return previous CPENABLE
- movi a3, 0 // for now, always return 0 (note: no OS currently calls this)
-
- wsr a2, CPENABLE
-#else
- movi a3, 0 // if no CPENABLE (no coprocessors), none is ever enabled
-#endif
- ret
- endfunc
-
-#endif
-
-
-/* Nothing implemented below this point. */
-/************************************************************************/
-
-#if 0
-
-//----------------------------------------------------------------------
-// initialize the processor state
-//----------------------------------------------------------------------
-
-// void xthal_init_extra_nw()
- .global xthal_init_extra_nw
- .align 4
-xthal_init_extra_nw:
- //addi sp, sp, 0
- ... NOT IMPLEMENTED ...
- ret
-
-//----------------------------------------------------------------------
-// initialize the TIE coprocessor
-//----------------------------------------------------------------------
-
-// void xthal_init_cp_nw(int)
- .global xthal_init_cp_nw
- .align 4
-xthal_init_cp_nw:
- //addi sp, sp, 0
- ... NOT IMPLEMENTED ...
- ret
-
-//----------------------------------------------------------------------
-//
-//----------------------------------------------------------------------
-
-// initialize the extra processor
-// void xthal_init_mem_extra_nw()
- .global xthal_init_mem_extra_nw
- .align 4
-xthal_init_mem_extra_nw:
- //addi sp, sp, 0
- ... NOT IMPLEMENTED ...
- ret
-
-//----------------------------------------------------------------------
-//
-//----------------------------------------------------------------------
-
-// initialize the TIE coprocessor
-// void xthal_init_mem_cp_nw(int)
- .global xthal_init_mem_cp_nw
- .align 4
-xthal_init_mem_cp_nw:
- //addi sp, sp, 0
- ... NOT IMPLEMENTED ...
- ret
-
-#endif /*0*/
-
diff --git a/src/arch/xtensa/up/hal/syscache_asm.S b/src/arch/xtensa/up/hal/syscache_asm.S
deleted file mode 100644
index 974faf1..0000000
--- a/src/arch/xtensa/up/hal/syscache_asm.S
+++ /dev/null
@@ -1,141 +0,0 @@
-//
-// syscache_asm.S - system-dependent assembly language cache management routines
-//
-// These functions are now obsolete. They cannot be properly implemented
-// in the HAL, because the required settings of CACHEATTR are entirely
-// system- or board-dependent. The HAL is not board specific; it is merely
-// processor-configuration specific. These cache enable and disable
-// functions do a "best-guess" of what values may be appropriate.
-// They should be avoided. (Instead, use xthal_set_[id]cacheattr()
-// and provide specific CACHEATTR values for the board or system.
-// See the LSP ref manual for info on how to obtain such a value as
-// computed by xt-genldscripts for a specific LSP, e.g. by using the
-// address of the _memmap_cacheattr_reset symbol.)
-//
-// $Id: //depot/rel/Eaglenest/Xtensa/OS/hal/syscache_asm.S#1 $
-
-// Copyright (c) 2003-2013 Tensilica Inc.
-//
-// Permission is hereby granted, free of charge, to any person obtaining
-// a copy of this software and associated documentation files (the
-// "Software"), to deal in the Software without restriction, including
-// without limitation the rights to use, copy, modify, merge, publish,
-// distribute, sublicense, and/or sell copies of the Software, and to
-// permit persons to whom the Software is furnished to do so, subject to
-// the following conditions:
-//
-// The above copyright notice and this permission notice shall be included
-// in all copies or substantial portions of the Software.
-//
-// THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
-// EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
-// MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
-// IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY
-// CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
-// TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
-// SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
-
-#ifdef INCLUDE_DEPRECATED_HAL_CACHE_CODE
-
-#include <xtensa/cacheasm.h>
-#include <xtensa/cacheattrasm.h>
-#include <xtensa/config/system.h>
-
-/*** Modify this for your particular board or system: ***/
-#define CACHEATTR_DEFAULT XSHAL_ISS_CACHEATTR_DEFAULT
-#define CACHEATTR_BYPASS XSHAL_ISS_CACHEATTR_BYPASS
-
-//----------------------------------------------------------------------
-// Enable and disable the caches
-//----------------------------------------------------------------------
-
- .text
-
- .global xthal_icache_enable
- .global xthal_dcache_enable
- .global xthal_icache_enable_nw
- .global xthal_dcache_enable_nw
-
- .global xthal_icache_disable
- .global xthal_dcache_disable
- .global xthal_icache_disable_nw
- .global xthal_dcache_disable_nw
-
- /*
- * Since we can't enable/disable the icache and dcache independently,
- * and don't have a nice place to store a state which would enable
- * us to only enable them both when both have been requested to be
- * enabled, we simply enable both for any request to enable either,
- * and disable both for any request to disable either cache.
- */
-
- .align 4
-xthal_icache_enable:
- abi_entry
- movi a3, xthal_set_icacheattr
- movi a6, CACHEATTR_DEFAULT // get cache-enabled attributes
- callx4 a3 // enable i-cache
- mov a2, a6 // (in case future version has a return value)
- abi_return
- .size xthal_icache_enable, . - xthal_icache_enable
-
- .align 4
-xthal_dcache_enable:
- abi_entry
- movi a3, xthal_set_dcacheattr
- movi a6, CACHEATTR_DEFAULT // get cache-enabled attributes
- callx4 a3 // enable d-cache
- mov a2, a6 // (in case future version has a return value)
- abi_return
- .size xthal_dcache_enable, . - xthal_dcache_enable
-
- .align 4
-xthal_icache_disable:
- abi_entry
- movi a3, xthal_set_icacheattr
- movi a6, CACHEATTR_BYPASS // get cache-disabled attributes
- callx4 a3 // disable i-cache
- mov a2, a6 // (in case future version has a return value)
- abi_return
- .size xthal_icache_disable, . - xthal_icache_disable
-
- .align 4
-xthal_dcache_disable:
- abi_entry
- movi a3, xthal_set_dcacheattr
- movi a6, CACHEATTR_BYPASS // get cache-disabled attributes
- callx4 a3 // disable d-cache
- mov a2, a6 // (in case future version has a return value)
- abi_return
- .size xthal_dcache_disable, . - xthal_dcache_disable
-
- .align 4
-xthal_icache_enable_nw:
- movi a3, xthal_set_icacheattr_nw
- movi a2, CACHEATTR_DEFAULT // get cache-enabled attributes
- jx a3 // enable i-cache
- .size xthal_icache_enable_nw, . - xthal_icache_enable_nw
-
- .align 4
-xthal_dcache_enable_nw:
- movi a3, xthal_set_dcacheattr_nw
- movi a2, CACHEATTR_DEFAULT // get cache-enabled attributes
- jx a3 // enable d-cache
- .size xthal_dcache_enable_nw, . - xthal_dcache_enable_nw
-
- .align 4
-xthal_icache_disable_nw:
- movi a3, xthal_set_icacheattr_nw
- movi a2, CACHEATTR_BYPASS // get cache-disabled attributes
- jx a3 // disable i-cache
- .size xthal_icache_disable_nw, . - xthal_icache_disable_nw
-
- .align 4
-xthal_dcache_disable_nw:
- movi a3, xthal_set_dcacheattr_nw
- movi a2, CACHEATTR_BYPASS // get cache-disabled attributes
- jx a3 // disable d-cache
- .size xthal_dcache_disable_nw, . - xthal_dcache_disable_nw
-
-#endif /* INCLUDE_DEPRECATED_HAL_CACHE_CODE */
-
diff --git a/src/arch/xtensa/up/hal/windowspill_asm.S b/src/arch/xtensa/up/hal/windowspill_asm.S
deleted file mode 100644
index b7bbedc..0000000
--- a/src/arch/xtensa/up/hal/windowspill_asm.S
+++ /dev/null
@@ -1,386 +0,0 @@
-//
-// windowspill.S -- register window spill routine
-//
-// $Id: //depot/rel/Eaglenest/Xtensa/OS/hal/windowspill_asm.S#1 $
-
-// Copyright (c) 1999-2010 Tensilica Inc.
-//
-// Permission is hereby granted, free of charge, to any person obtaining
-// a copy of this software and associated documentation files (the
-// "Software"), to deal in the Software without restriction, including
-// without limitation the rights to use, copy, modify, merge, publish,
-// distribute, sublicense, and/or sell copies of the Software, and to
-// permit persons to whom the Software is furnished to do so, subject to
-// the following conditions:
-//
-// The above copyright notice and this permission notice shall be included
-// in all copies or substantial portions of the Software.
-//
-// THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
-// EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
-// MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
-// IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY
-// CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
-// TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
-// SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
-
-#include <xtensa/coreasm.h>
-
-
-// xthal_window_spill_nw
-//
-// Spill live register windows to the stack.
-//
-// Required entry conditions:
-// PS.WOE = 0
-// PS.INTLEVEL >= XCHAL_EXCM_LEVEL
-// a1 = valid stack pointer (note: some regs may be spilled at a1-16)
-// a0 = return PC (usually set by call0 or callx0 when calling this function)
-// a2,a3 undefined
-// a4 thru a15 valid, if they are part of window(s) to be spilled
-// (Current window a0..a15 saved if necessary.)
-// WINDOWSTART[WINDOWBASE] = 1
-//
-// Exit conditions:
-// PS.WOE, PS.INTLEVEL = same as on entry
-// WINDOWBASE = same as on entry
-// WINDOWSTART updated to reflect spilled windows
-// (equals 1<<WINDOWBASE if successful return)
-// a0 = return PC
-// a1 = same as on entry
-// a2 = error code:
-// 0 --> successful
-// (WINDOWSTART = 1<<WINDOWBASE)
-// 1 --> invalid WINDOWSTART (WINDOWBASE bit not set)
-// (WINDOWSTART unchanged)
-// 2 --> invalid window size (not 4, 8 or 12 regs)
-// (WINDOWSTART bits of successfully spilled
-// windows are cleared, others left intact)
-// a3 clobbered
-// a4,a5,a8,a9,a12,a13 = same as on entry
-// a6,a7,a10,a11,a14,a15 clobbered if they were part of window(s)
-// to be spilled, otherwise they are the same as on entry
-// loop registers (LCOUNT,LBEG,LEND) are NOT affected (they were in earlier versions)
-// SAR clobbered
-//
-// All non-spilled register windows will be spilled.
-// Beware that this may include a4..a15 of the current window,
-// so generally these should not have been clobbered by the
-// caller if it is at all possible that these registers
-// are part of an unspilled window (it often is possible)
-// (otherwise the spilled stack would be invalid).
-//
-// THIS MEANS: the caller is responsible for saving a0-a15 but
-// the caller must leave a4-a15 intact when control is transferred
-// here.
-//
-// It may be reentrant (but stack pointer is invalid during
-// execution due to window rotations, so can't take interrupts
-// and exceptions in the usual manner, so ... what does
-// reentrancy really mean here?).
-
-
- // The xthal_spill_registers_into_stack_nw entry point
- // is kept here only for backwards compatibility.
- // It will be removed in the very near future.
- .global xthal_spill_registers_into_stack_nw
-
- .text
- .align 4
- .global xthal_window_spill_nw
-xthal_window_spill_nw:
-xthal_spill_registers_into_stack_nw: // BACKWARD COMPATIBILITY ONLY - see above
-
-#if ! XCHAL_HAVE_WINDOWED
- // Nothing to do -- window option was not selected.
- movi a2, 0 // always report success
- ret
-#else /* XCHAL_HAVE_WINDOWED */
-#define WSBITS (XCHAL_NUM_AREGS / 4) /* width of WINDOWSTART register in bits */
-#define WBBITS (XCHAL_NUM_AREGS_LOG2 - 2) /* width of WINDOWBASE register in bits */
- /*
- * Rearrange (rotate) window start bits relative to the current
- * window (WINDOWBASE). WINDOWSTART currently looks like this:
- *
- * a15-a0
- * NAREG-1 | | 0
- * | vvvv |
- * xxxxxxxxxx1yyyyy
- * ^
- * |
- * WINDOWBASE
- *
- * The start bit pointed to by WINDOWBASE must be set
- * (we return an error if it isn't), as it corresponds
- * to the start of the current window (shown as a0-a15).
- *
- * We want the window start bits rotated to look like this:
- * 1yyyyyxxxxxxxxxx
- *
- * Note that there is one start bit for every four registers;
- * and the total number of registers (NAREG) can be 32 or 64;
- * so the number of start bits in WINDOWSTART is NAREG/4,
- * and the size of WINDOWSTART can be 8 or 16.
- */
-
- rsr a2, WINDOWBASE
- addi a2, a2, 1
- ssr a2 // sar = WINDOWBASE + 1
- rsr a3, WINDOWSTART
- srl a2, a3 // a2 is 0... | 000000xxxxxxxxxx = WINDOWSTART >> sar
- sll a3, a3 // a3 is 1yyyyy0000000000 | 0... = WINDOWSTART << (32 - sar)
- bgez a3, .Linvalid_ws // verify that msbit is indeed set
-
- srli a3, a3, 32-WSBITS // a3 is 0... | 1yyyyy0000000000 = a3 >> (32-NAREG/4)
- or a2, a2, a3 // a2 is 0... | 1yyyyyxxxxxxxxxx
-
- /*
- * FIND THE FIRST ONE
- *
- * Now we have (in a2) the window start bits rotated in order
- * from oldest (closest to lsbit) to current (msbit set).
- * Each start bit (that is set), other than the current one,
- * corresponds to a window frame to spill.
- *
- * Now find the first start bit, ie. the first frame to spill,
- * by looking for the first bit set in a2 (from lsbit side).
- */
-
-#if XCHAL_HAVE_NSA
- neg a3, a2 // keep only the least-significant bit set of a2 ...
- and a3, a3, a2 // ... in a3
- nsau a3, a3 // get index of that bit, numbered from msbit (32 if absent)
- ssl a3 // set sar = 32 - a3 = bit index numbered from lsbit + 1
-#else /* XCHAL_HAVE_NSA */
- wsr a2, WINDOWSTART // temporarily save rotated start bits
- // (we can use WINDOWSTART because WOE=0)
-
- // NOTE: this could be optimized a bit, by explicit coding rather than the macro.
- find_ls_one a3, a2 // set a3 to index of lsmost bit set in a2 (a2 clobbered)
-
- addi a2, a3, 1 // index+1
- ssr a2 // set sar = index + 1
- rsr a2, WINDOWSTART // restore a2 (rotated start bits)
-#endif /* XCHAL_HAVE_NSA */
- srl a2, a2 // right-justify the rotated start bits (dropping lsbit set)
- wsr a2, WINDOWSTART // save rotated + justified window start bits,
- // because a2 will disappear when modifying WINDOWBASE
- // again, we can use WINDOWSTART because WOE=0
-
- /*
- * Rotate WindowBase so that a0 of the next window to spill is in a4
- * (ie. leaving us with a2 and a3 to play with, because a0 and a1
- * may be those of the original window which we must preserve).
- */
- rsr a2, WINDOWBASE
-#if XCHAL_HAVE_NSA
- addi a2, a2, 31
- sub a3, a2, a3 // a3 = WINDOWBASE + index = WINDOWBASE + (31 - msbit_index)
-#else /* XCHAL_HAVE_NSA */
- add a3, a2, a3 // a3 = WINDOWBASE + index
-#endif /* XCHAL_HAVE_NSA */
- wsr a3, WINDOWBASE // effectively do: rotw index
- rsync // wait for write to WINDOWBASE to complete
- // Now our registers have changed!
-
- rsr a2, WINDOWSTART // restore a2 (rotated + justified window start bits)
-
- /*
- * We are now ready to start the window spill loop.
- * Relative to the above, a2 and WINDOWBASE are now as follows:
- *
- * 1yyyyyxxxxxxxxxx = rotated start bits as shown above
- * 1yyyyyxxxx100000 = actual rotated start bits (example)
- * 0000001yyyyyxxxx ^ = a2 = rotated + justified start bits
- * ^ xxx1^ = window being spilled
- * ^ ^
- * | |
- * original current
- * WINDOWBASE WINDOWBASE
- *
- * The first window to spill (save) starts at what is now a4.
- * The spill loop maintains the adjusted start bits in a2,
- * shifting them right as each window is spilled.
- */
-
-.Lspill_loop:
- // Top of save loop.
- // Find the size of this call and branch to the appropriate save routine.
-
- beqz a2, .Ldone // if no start bit remaining, we're done
- bbsi.l a2, 0, .Lspill4 // if next start bit is set, it's a call4
- bbsi.l a2, 1, .Lspill8 // if 2nd next bit set, it's a call8
- bbsi.l a2, 2, .Lspill12 // if 3rd next bit set, it's a call12
- j .Linvalid_window // else it's an invalid window!
-
-
-
- // SAVE A CALL4
-.Lspill4:
- addi a3, a9, -16 // a3 gets call[i+1]'s sp - 16
- s32i a4, a3, 0 // store call[i]'s a0
- s32i a5, a3, 4 // store call[i]'s a1
- s32i a6, a3, 8 // store call[i]'s a2
- s32i a7, a3, 12 // store call[i]'s a3
-
- srli a6, a2, 1 // move and shift the start bits
- rotw 1 // rotate the window
-
- j .Lspill_loop
-
- // SAVE A CALL8
-.Lspill8:
- addi a3, a13, -16 // a0 gets call[i+1]'s sp - 16
- s32i a4, a3, 0 // store call[i]'s a0
- s32i a5, a3, 4 // store call[i]'s a1
- s32i a6, a3, 8 // store call[i]'s a2
- s32i a7, a3, 12 // store call[i]'s a3
-
- addi a3, a5, -12 // call[i-1]'s sp address
- l32i a3, a3, 0 // a3 is call[i-1]'s sp
- // (load slot)
- addi a3, a3, -32 // a3 points to our spill area
-
- s32i a8, a3, 0 // store call[i]'s a4
- s32i a9, a3, 4 // store call[i]'s a5
- s32i a10, a3, 8 // store call[i]'s a6
- s32i a11, a3, 12 // store call[i]'s a7
-
- srli a10, a2, 2 // move and shift the start bits
- rotw 2 // rotate the window
-
- j .Lspill_loop
-
- // SAVE A CALL12
-.Lspill12:
- rotw 1 // rotate to see call[i+1]'s sp
-
- addi a13, a13, -16 // set to the reg save area
- s32i a0, a13, 0 // store call[i]'s a0
- s32i a1, a13, 4 // store call[i]'s a1
- s32i a2, a13, 8 // store call[i]'s a2
- s32i a3, a13, 12 // store call[i]'s a3
-
- addi a3, a1, -12 // call[i-1]'s sp address
- l32i a3, a3, 0 // a3 has call[i-1]'s sp
- addi a13, a13, 16 // restore call[i+1]'s sp (here to fill load slot)
- addi a3, a3, -48 // a3 points to our save area
-
- s32i a4, a3, 0 // store call[i]'s a4
- s32i a5, a3, 4 // store call[i]'s a5
- s32i a6, a3, 8 // store call[i]'s a6
- s32i a7, a3, 12 // store call[i]'s a7
- s32i a8, a3, 16 // store call[i]'s a4
- s32i a9, a3, 20 // store call[i]'s a5
- s32i a10, a3, 24 // store call[i]'s a6
- s32i a11, a3, 28 // store call[i]'s a7
-
- rotw -1 // rotate to see start bits (a2)
- srli a14, a2, 3 // move and shift the start bits
- rotw 3 // rotate to next window
-
- j .Lspill_loop
-
-
-
-.Ldone:
- rotw 1 // back to the original window
- rsr a2, WINDOWBASE // get (original) window base
- ssl a2 // setup for shift left by WINDOWBASE
- movi a2, 1
- sll a2, a2 // compute new WINDOWSTART = 1<<WINDOWBASE
- wsr a2, WINDOWSTART // and apply it
- rsync
- movi a2, 0 // done!
- ret
- //jx a0
-
-
- // Invalid WINDOWSTART register.
- //
-.Linvalid_ws:
- movi a2, 1 // indicate invalid WINDOWSTART
- ret // return from subroutine
-
-
- // Invalid window size!
- // The three bits following the start bit are all clear, so
- // we have an invalid window state (can't determine a window size).
- //
- // So we exit with an error, but to do that we must first restore
- // the original WINDOWBASE. We also compute a sensible
- // WINDOWSTART that has the start bits of spilled windows
- // cleared, but all other start bits intact, so someone debugging
- // the failure can look at WINDOWSTART to see which window
- // failed to spill.
- //
-.Linvalid_window:
- slli a2, a2, 1 // space for missing start bit
- addi a2, a2, 1 // add missing start bit
- rsr a3, WINDOWBASE // get current WINDOWBASE
- bbsi.l a2, WSBITS-1, 2f // branch if current WINDOWBASE==original
-1: addi a3, a3, -1 // decrement towards original WINDOWBASE
- slli a2, a2, 1 // shift towards original WINDOWSTART alignment
- bbci.l a2, WSBITS-1, 1b // repeat until ms start bit set
- extui a3, a3, 0, WBBITS // mask out upper base bits, in case of carry-over
-2: // Here, a3 = original WINDOWBASE;
- // and msbit of start bits in a2 is set, and no other bits above it.
- // Now rotate a2 to become the correct WINDOWSTART.
- ssl a3 // set shift left ... (sar = 32 - orig WB)
- slli a3, a2, 32-WSBITS // left-justify start bits
- src a2, a2, a3 // rotate left by original WINDOWBASE
- extui a2, a2, 0, WSBITS // keep only significant start bits
- wsr a2, WINDOWSTART // we've cleared only start bits of spilled windows
- rsr a3, SAR // retrieve 32 - original WINDOWBASE
- movi a2, 32
- sub a3, a2, a3 // restore original WINDOWBASE
- wsr a3, WINDOWBASE // back to original WINDOWBASE
- rsync
-
- movi a2, 2 // indicate invalid window size
- ret
-
-#endif /* XCHAL_HAVE_WINDOWED */
-
- .size xthal_window_spill_nw, . - xthal_window_spill_nw
-
-
-// void xthal_window_spill (void);
-//
-// Spill live register windows to the stack.
-//
-// This will spill all register windows except this
-// function's window, and possibly that of its caller.
-// (Currently, the caller's window is spilled and reloaded
-// when this function returns. This may change with
-// future optimisations.)
-//
-// Another, simpler way to implement this might be
-// to use an appropriate sequence of call/entry/retw
-// instructions to force overflow of any live windows.
-//
-// Assumes that PS.INTLEVEL=0 and PS.WOE=1 on entry/exit.
-//
- .text
- .align 4
- .global xthal_window_spill
- .type xthal_window_spill,@function
-xthal_window_spill:
- abi_entry
-#if XCHAL_HAVE_WINDOWED
- movi a6, ~(PS_WOE_MASK|PS_INTLEVEL_MASK) // (using a6 ensures any window using this a4..a7 is spilled)
- rsr a5, PS
- mov a4, a0 // save a0
- and a2, a5, a6 // clear WOE, INTLEVEL
- addi a2, a2, XCHAL_EXCM_LEVEL // set INTLEVEL = XCHAL_EXCM_LEVEL
- wsr a2, PS // apply to PS
- rsync
- call0 xthal_window_spill_nw
- mov a0, a4 // restore a0
- wsr a5, PS // restore PS
- rsync
-#endif /* XCHAL_HAVE_WINDOWED */
- abi_return
-
- .size xthal_window_spill, . - xthal_window_spill
-
diff --git a/src/arch/xtensa/up/include/Makefile.am b/src/arch/xtensa/up/include/Makefile.am
deleted file mode 100644
index f0ac9b7..0000000
--- a/src/arch/xtensa/up/include/Makefile.am
+++ /dev/null
@@ -1 +0,0 @@
-SUBDIRS = arch
diff --git a/src/arch/xtensa/up/include/arch/Makefile.am b/src/arch/xtensa/up/include/arch/Makefile.am
deleted file mode 100644
index eaf72bb..0000000
--- a/src/arch/xtensa/up/include/arch/Makefile.am
+++ /dev/null
@@ -1,2 +0,0 @@
-noinst_HEADERS = \
- idc.h
diff --git a/src/arch/xtensa/up/include/arch/idc.h b/src/arch/xtensa/up/include/arch/idc.h
deleted file mode 100644
index 488e287..0000000
--- a/src/arch/xtensa/up/include/arch/idc.h
+++ /dev/null
@@ -1,61 +0,0 @@
-/*
- * Copyright (c) 2018, Intel Corporation
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- * * Redistributions of source code must retain the above copyright
- * notice, this list of conditions and the following disclaimer.
- * * Redistributions in binary form must reproduce the above copyright
- * notice, this list of conditions and the following disclaimer in the
- * documentation and/or other materials provided with the distribution.
- * * Neither the name of the Intel Corporation nor the
- * names of its contributors may be used to endorse or promote products
- * derived from this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
- * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
- * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
- * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
- * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
- * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
- * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
- * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
- * POSSIBILITY OF SUCH DAMAGE.
- *
- * Author: Tomasz Lauda <tomasz.lauda@linux.intel.com>
- */
-
-/**
- * \file arch/xtensa/up/include/arch/idc.h
- * \brief Xtensa UP architecture IDC header file
- * \authors Tomasz Lauda <tomasz.lauda@linux.intel.com>
- */
-
-#ifndef __ARCH_IDC_H__
-#define __ARCH_IDC_H__
-
-struct idc_msg;
-
-/**
- * \brief Sends IDC message.
- * \param[in,out] msg Pointer to IDC message.
- * \param[in] mode Is message blocking or not.
- * \return Error code.
- */
-static inline int arch_idc_send_msg(struct idc_msg *msg,
- uint32_t mode) { return 0; }
-
-/**
- * \brief Checks for pending IDC messages.
- */
-static inline void arch_idc_process_msg_queue(void) { }
-
-/**
- * \brief Initializes IDC data and registers for interrupt.
- */
-static inline void arch_idc_init(void) { }
-
-#endif
diff --git a/src/arch/xtensa/up/init.c b/src/arch/xtensa/up/init.c
deleted file mode 100644
index 31fa93a..0000000
--- a/src/arch/xtensa/up/init.c
+++ /dev/null
@@ -1,66 +0,0 @@
-/*
- * Copyright (c) 2016, Intel Corporation
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- * * Redistributions of source code must retain the above copyright
- * notice, this list of conditions and the following disclaimer.
- * * Redistributions in binary form must reproduce the above copyright
- * notice, this list of conditions and the following disclaimer in the
- * documentation and/or other materials provided with the distribution.
- * * Neither the name of the Intel Corporation nor the
- * names of its contributors may be used to endorse or promote products
- * derived from this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
- * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
- * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
- * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
- * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
- * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
- * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
- * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
- * POSSIBILITY OF SUCH DAMAGE.
- *
- * Author: Liam Girdwood <liam.r.girdwood@linux.intel.com>
- */
-
-#include <platform/memory.h>
-#include <sof/interrupt.h>
-#include <platform/interrupt.h>
-#include <sof/mailbox.h>
-#include <arch/init.h>
-#include <arch/task.h>
-#include <sof/init.h>
-#include <sof/lock.h>
-#include <stdint.h>
-
-/**
- * \file arch/xtensa/up/init.c
- * \brief Xtensa UP initialization functions
- * \authors Liam Girdwood <liam.r.girdwood@linux.intel.com>
- */
-
-#if DEBUG_LOCKS
-/** \brief Debug lock. */
-uint32_t lock_dbg_atomic = 0;
-
-/** \brief Debug locks per user. */
-uint32_t lock_dbg_user[DBG_LOCK_USERS] = {0};
-#endif
-
-/**
- * \brief Initializes architecture.
- * \param[in,out] sof Firmware main context.
- * \return Error status.
- */
-int arch_init(struct sof *sof)
-{
- register_exceptions();
- arch_assign_tasks();
- return 0;
-}
-
diff --git a/src/arch/xtensa/up/schedule.c b/src/arch/xtensa/up/schedule.c
deleted file mode 100644
index c5f8c86..0000000
--- a/src/arch/xtensa/up/schedule.c
+++ /dev/null
@@ -1,46 +0,0 @@
-/*
- * Copyright (c) 2018, Intel Corporation
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- * * Redistributions of source code must retain the above copyright
- * notice, this list of conditions and the following disclaimer.
- * * Redistributions in binary form must reproduce the above copyright
- * notice, this list of conditions and the following disclaimer in the
- * documentation and/or other materials provided with the distribution.
- * * Neither the name of the Intel Corporation nor the
- * names of its contributors may be used to endorse or promote products
- * derived from this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
- * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
- * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
- * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
- * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
- * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
- * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
- * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
- * POSSIBILITY OF SUCH DAMAGE.
- *
- * Author: Tomasz Lauda <tomasz.lauda@linux.intel.com>
- *
- */
-
-/**
- * \file arch/xtensa/up/schedule.c
- * \brief Xtensa UP schedule implementation file
- * \authors Tomasz Lauda <tomasz.lauda@linux.intel.com>
- */
-
-#include <sof/schedule.h>
-
-/** \brief Schedule data pointer. */
-static struct schedule_data *sch;
-
-struct schedule_data **arch_schedule_get(void)
-{
- return &sch;
-}
diff --git a/src/arch/xtensa/up/task.c b/src/arch/xtensa/up/task.c
deleted file mode 100644
index c584c06..0000000
--- a/src/arch/xtensa/up/task.c
+++ /dev/null
@@ -1,62 +0,0 @@
-/*
- * Copyright (c) 2017, Intel Corporation
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- * * Redistributions of source code must retain the above copyright
- * notice, this list of conditions and the following disclaimer.
- * * Redistributions in binary form must reproduce the above copyright
- * notice, this list of conditions and the following disclaimer in the
- * documentation and/or other materials provided with the distribution.
- * * Neither the name of the Intel Corporation nor the
- * names of its contributors may be used to endorse or promote products
- * derived from this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
- * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
- * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
- * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
- * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
- * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
- * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
- * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
- * POSSIBILITY OF SUCH DAMAGE.
- *
- * Author: Liam Girdwood <liam.r.girdwood@linux.intel.com>
- *
- */
-
-/**
- * \file arch/xtensa/up/task.c
- * \brief Xtensa UP task implementation file
- * \authors Liam Girdwood <liam.r.girdwood@linux.intel.com>
- */
-
-#include <arch/task.h>
-
-/** \brief IRQ low task data pointer. */
-static struct irq_task *irq_low_task;
-
-/** \brief IRQ medium task data pointer. */
-static struct irq_task *irq_med_task;
-
-/** \brief IRQ high task data pointer. */
-static struct irq_task *irq_high_task;
-
-struct irq_task **task_irq_low_get(void)
-{
- return &irq_low_task;
-}
-
-struct irq_task **task_irq_med_get(void)
-{
- return &irq_med_task;
-}
-
-struct irq_task **task_irq_high_get(void)
-{
- return &irq_high_task;
-}
diff --git a/src/arch/xtensa/up/xtos/Makefile.am b/src/arch/xtensa/up/xtos/Makefile.am
deleted file mode 100644
index 4163d1d..0000000
--- a/src/arch/xtensa/up/xtos/Makefile.am
+++ /dev/null
@@ -1,154 +0,0 @@
-noinst_HEADERS = \
- xtos-internal.h \
- xtos-params.h \
- interrupt-pri.h \
- window-vectors-new.S \
- int-highpri-dispatcher.S \
- int-medpri-dispatcher.S
-
-noinst_LIBRARIES = \
- libxtos.a \
- libxlevel2.a \
- libxlevel3.a \
- libxlevel4.a \
- libxlevel5.a
-
-VECTOR_DEFS = \
- -D__SPLIT__vector \
- -D__SPLIT__handler \
- -D__SPLIT__user \
- -D__SPLIT__level1int \
- -D__SPLIT__level2 \
- -D__SPLIT__level3 \
- -D__SPLIT__level4 \
- -D__SPLIT__level5
-
-
-if BUILD_BAYTRAIL
-PLATFORM_DEFS = $(VECTOR_DEFS)
-endif
-
-if BUILD_CHERRYTRAIL
-PLATFORM_DEFS = $(VECTOR_DEFS)
-endif
-
-if BUILD_APOLLOLAKE
-PLATFORM_DEFS = $(VECTOR_DEFS)
-noinst_LIBRARIES += libxlevel6.a
-VECTOR_DEFS += -D__SPLIT__level6
-endif
-
-if BUILD_BROADWELL
-PLATFORM_DEFS = $(VECTOR_DEFS)
-endif
-
-if BUILD_HASWELL
-PLATFORM_DEFS = $(VECTOR_DEFS)
-endif
-
-if BUILD_CANNONLAKE
-PLATFORM_DEFS = $(VECTOR_DEFS)
-noinst_LIBRARIES += libxlevel6.a
-VECTOR_DEFS += -D__SPLIT__level6
-endif
-
-LEVEL_SRC = \
- int-handler.S \
- int-vector.S \
- int-initlevel.S
-
-libxlevel2_a_SOURCES = \
- $(LEVEL_SRC)
-
-libxlevel2_a_CCASFLAGS = \
- $(ARCH_INCDIR) \
- $(AM_CCASFLAGS) \
- $(PLATFORM_INCDIR) \
- $(PLATFORM_DEFS) \
- -D_INTERRUPT_LEVEL=2
-
-libxlevel3_a_SOURCES = \
- $(LEVEL_SRC)
-
-libxlevel3_a_CCASFLAGS = \
- $(ARCH_INCDIR) \
- $(AM_CCASFLAGS) \
- $(PLATFORM_INCDIR) \
- $(PLATFORM_DEFS) \
- -D_INTERRUPT_LEVEL=3
-
-libxlevel4_a_SOURCES = \
- $(LEVEL_SRC)
-
-libxlevel4_a_CCASFLAGS = \
- $(ARCH_INCDIR) \
- $(AM_CCASFLAGS) \
- $(PLATFORM_INCDIR) \
- $(PLATFORM_DEFS) \
- -D_INTERRUPT_LEVEL=4
-
-libxlevel5_a_SOURCES = \
- $(LEVEL_SRC)
-
-libxlevel5_a_CCASFLAGS = \
- $(ARCH_INCDIR) \
- $(AM_CCASFLAGS) \
- $(PLATFORM_INCDIR) \
- $(PLATFORM_DEFS) \
- -D_INTERRUPT_LEVEL=5
-
-if BUILD_APOLLOLAKE
-libxlevel6_a_SOURCES = \
- $(LEVEL_SRC)
-
-libxlevel6_a_CCASFLAGS = \
- $(ARCH_INCDIR) \
- $(AM_CCASFLAGS) \
- $(PLATFORM_INCDIR) \
- $(PLATFORM_DEFS) \
- -D_INTERRUPT_LEVEL=6
-endif
-
-libxtos_a_SOURCES = \
- core-restore.S \
- core-save.S \
- core-shutoff.S \
- double-vector.S \
- exc-alloca-handler.S \
- exc-c-wrapper-handler.S \
- exc-return.S \
- exc-sethandler.c \
- exc-syscall-c-handler.c \
- exc-syscall-handler.S \
- exc-table.S \
- exc-unhandled.S \
- init.c \
- interrupt-table.S \
- int-sethandler.c \
- intlevel-restore.S \
- intlevel-setmin.S \
- intlevel-set.S \
- int-lowpri-dispatcher.S \
- ints-off.S \
- ints-on.S \
- kernel-vector.S \
- memep-enable.S \
- memep-initrams.S \
- memerror-vector.S \
- nmi-vector.S \
- reloc-vectors.S \
- user-vector.S \
- window-vectors.S
-
-libxtos_a_CFLAGS = \
- $(ARCH_INCDIR) \
- $(AM_CFLAGS) \
- $(ARCH_CFLAGS) \
- $(PLATFORM_INCDIR) \
- $(PLATFORM_DEFS)
-
-libxtos_a_CCASFLAGS = \
- $(ARCH_INCDIR) \
- $(AM_CCASFLAGS) \
- $(PLATFORM_INCDIR) \
- $(PLATFORM_DEFS)
diff --git a/src/arch/xtensa/up/xtos/_sharedvectors-for-reset.S b/src/arch/xtensa/up/xtos/_sharedvectors-for-reset.S
deleted file mode 100644
index 8556478..0000000
--- a/src/arch/xtensa/up/xtos/_sharedvectors-for-reset.S
+++ /dev/null
@@ -1,40 +0,0 @@
-// _sharedvectors-for-reset.S -- Reference to pull in a shared reset vector
-// $Id: //depot/rel/Eaglenest/Xtensa/OS/xtos/_sharedvectors-for-reset.S#1 $
-
-// Copyright (c) 2008 Tensilica Inc.
-//
-// Permission is hereby granted, free of charge, to any person obtaining
-// a copy of this software and associated documentation files (the
-// "Software"), to deal in the Software without restriction, including
-// without limitation the rights to use, copy, modify, merge, publish,
-// distribute, sublicense, and/or sell copies of the Software, and to
-// permit persons to whom the Software is furnished to do so, subject to
-// the following conditions:
-//
-// The above copyright notice and this permission notice shall be included
-// in all copies or substantial portions of the Software.
-//
-// THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
-// EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
-// MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
-// IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY
-// CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
-// TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
-// SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
-
-#include <xtensa/coreasm.h>
-
-/* Multicore build flows can use this file (_sharedvectors-for-reset.o)
- by copying it to _sharedvectors.o early in the linker search path
- (to override the default one), and updating the memory map or linker
- scripts accordingly.
- This file pulls in a sharable reset vector (typically
- shared-reset-vector.S, which requires the PRID option). */
-
-.global _SharedResetVector
-
-/* The following allows this object file to be pulled in by reference: */
-.text
-.global _xtos_sharedvectors_ref_
-.set _xtos_sharedvectors_ref_, 0
-
diff --git a/src/arch/xtensa/up/xtos/_sharedvectors.S b/src/arch/xtensa/up/xtos/_sharedvectors.S
deleted file mode 100644
index bfa4541..0000000
--- a/src/arch/xtensa/up/xtos/_sharedvectors.S
+++ /dev/null
@@ -1,37 +0,0 @@
-// _sharedvectors.S -- Reference symbols to pull in any shared vectors
-// (default version, used when not sharing any vector)
-// $Id: //depot/rel/Eaglenest/Xtensa/OS/xtos/_sharedvectors.S#1 $
-
-// Copyright (c) 2008 Tensilica Inc.
-//
-// Permission is hereby granted, free of charge, to any person obtaining
-// a copy of this software and associated documentation files (the
-// "Software"), to deal in the Software without restriction, including
-// without limitation the rights to use, copy, modify, merge, publish,
-// distribute, sublicense, and/or sell copies of the Software, and to
-// permit persons to whom the Software is furnished to do so, subject to
-// the following conditions:
-//
-// The above copyright notice and this permission notice shall be included
-// in all copies or substantial portions of the Software.
-//
-// THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
-// EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
-// MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
-// IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY
-// CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
-// TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
-// SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
-
-#include <xtensa/coreasm.h>
-
-/* Not present by default. Multicore build flows build/use a custom
- version of _sharedvectors.o that may pull in shared vectors. */
-
-/* .global _SharedResetVector */
-
-/* The following allows this object file to be pulled in by reference: */
-.text
-.global _xtos_sharedvectors_ref_
-.set _xtos_sharedvectors_ref_, 0
-
diff --git a/src/arch/xtensa/up/xtos/_vectors.S b/src/arch/xtensa/up/xtos/_vectors.S
deleted file mode 100644
index a33846a..0000000
--- a/src/arch/xtensa/up/xtos/_vectors.S
+++ /dev/null
@@ -1,94 +0,0 @@
-// _vectors.S -- Reference symbols to pull in all required vectors
-// $Id: //depot/rel/Eaglenest/Xtensa/OS/xtos/_vectors.S#1 $
-
-// Copyright (c) 2004, 2006-2007 Tensilica Inc.
-//
-// Permission is hereby granted, free of charge, to any person obtaining
-// a copy of this software and associated documentation files (the
-// "Software"), to deal in the Software without restriction, including
-// without limitation the rights to use, copy, modify, merge, publish,
-// distribute, sublicense, and/or sell copies of the Software, and to
-// permit persons to whom the Software is furnished to do so, subject to
-// the following conditions:
-//
-// The above copyright notice and this permission notice shall be included
-// in all copies or substantial portions of the Software.
-//
-// THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
-// EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
-// MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
-// IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY
-// CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
-// TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
-// SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
-
-#include <xtensa/coreasm.h>
-#include <xtensa/config/system.h> /* for XSHAL_VECTORS_PACKED */
-
-.global _ResetVector
-
-#if XCHAL_HAVE_EXCEPTIONS
-
-# if XCHAL_HAVE_DEBUG
-.global _DebugExceptionVector
-# endif
-
-.global _KernelExceptionVector
-.global _UserExceptionVector
-
-# ifdef XCHAL_DOUBLEEXC_VECTOR_VADDR
-.global _DoubleExceptionVector
-# endif
-
-# if XCHAL_HAVE_NMI
-.global _NMIExceptionVector
-# endif
-
-# if XCHAL_HAVE_WINDOWED
-.global _WindowOverflow4
-.global _WindowUnderflow4
-.global _WindowOverflow8
-.global _WindowUnderflow8
-.global _WindowOverflow12
-.global _WindowUnderflow12
-# endif
-
-# if XCHAL_HAVE_MEM_ECC_PARITY
-.global _MemErrorVector
-# endif
-
-#endif /* XCHAL_HAVE_EXCEPTIONS */
-
-
-#if (XCHAL_NUM_INTLEVELS >= 2) && (2 != XCHAL_DEBUGLEVEL)
-.global _Level2Vector
-#endif
-#if (XCHAL_NUM_INTLEVELS >= 3) && (3 != XCHAL_DEBUGLEVEL)
-.global _Level3Vector
-#endif
-#if (XCHAL_NUM_INTLEVELS >= 4) && (4 != XCHAL_DEBUGLEVEL)
-.global _Level4Vector
-#endif
-#if (XCHAL_NUM_INTLEVELS >= 5) && (5 != XCHAL_DEBUGLEVEL)
-.global _Level5Vector
-#endif
-#if (XCHAL_NUM_INTLEVELS >= 6) && (6 != XCHAL_DEBUGLEVEL)
-.global _Level6Vector
-#endif
-
-#if XCHAL_HAVE_VECBASE && XSHAL_VECTORS_PACKED
-.global _RelocVectors
-#endif
-
-/* These don't take up space: */
-.global xthals_hw_configid0
-.global xthals_hw_configid1
-.global xthals_release_major
-.global xthals_release_minor
-
-/* The following allows this object file to be pulled in by reference: */
-.text
-.global _xtos_vectors_ref_
-.set _xtos_vectors_ref_, 0
-
-
diff --git a/src/arch/xtensa/up/xtos/checkvecsize b/src/arch/xtensa/up/xtos/checkvecsize
deleted file mode 100755
index 5730de6..0000000
--- a/src/arch/xtensa/up/xtos/checkvecsize
+++ /dev/null
@@ -1,71 +0,0 @@
-# Script to check that vector code is 16 bytes or less
-# $Id: //depot/rel/Eaglenest/Xtensa/OS/xtos/checkvecsize#1 $
-
-# Copyright (c) 2001 Tensilica Inc.
-#
-# Permission is hereby granted, free of charge, to any person obtaining
-# a copy of this software and associated documentation files (the
-# "Software"), to deal in the Software without restriction, including
-# without limitation the rights to use, copy, modify, merge, publish,
-# distribute, sublicense, and/or sell copies of the Software, and to
-# permit persons to whom the Software is furnished to do so, subject to
-# the following conditions:
-#
-# The above copyright notice and this permission notice shall be included
-# in all copies or substantial portions of the Software.
-#
-# THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
-# EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
-# MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
-# IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY
-# CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
-# TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
-# SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
-
-package Xtensa::checkvecsize;
-
-# Perl library modules
-use strict;
-use Getopt::Long;
-use FileHandle;
-
-# Program
-
-use vars qw($objdump $maxsize);
-
-{
- $::myname = 'checkvecsize';
-
- # command line
- $maxsize = 16;
- die("Usage is: $::myname -objdump prog [-maxsize n] files...\n")
- unless &GetOptions("objdump=s" => \$objdump,
- "maxsize=i" => \$maxsize)
- && @ARGV > 0 && defined($objdump);
- my $file;
- foreach $file (@ARGV) {
- checkvecsize ($file);
- }
-}
-
-sub checkvecsize {
- my ($file) = @_;
- my $od = new FileHandle "${objdump} -h $file|";
- die("$::myname: $!, opening pipe to $objdump -h $file.\n")
- unless $od;
- while (<$od>) {
- if (/^\s*\d+\s+(\S+)\s+([0-9A-Fa-f]{8})\s/) {
- my $size = hex($2);
- die("$::myname: $file $1 section size is $size bytes.\n")
- if $size > $maxsize;
- }
- }
- $od->close();
-}
-
-
-# Local Variables:
-# mode:perl
-# perl-indent-level:2
-# cperl-indent-level:2
-# End:
diff --git a/src/arch/xtensa/up/xtos/core-restore.S b/src/arch/xtensa/up/xtos/core-restore.S
deleted file mode 100644
index 872c297..0000000
--- a/src/arch/xtensa/up/xtos/core-restore.S
+++ /dev/null
@@ -1,586 +0,0 @@
-// core-restore.S -- core state restore routine (used by PSO)
-// $Id: //depot/rel/Eaglenest/Xtensa/OS/xtos/core-restore.S#1 $
-
-// Copyright (c) 2012-2013 Tensilica Inc.
-//
-// Permission is hereby granted, free of charge, to any person obtaining
-// a copy of this software and associated documentation files (the
-// "Software"), to deal in the Software without restriction, including
-// without limitation the rights to use, copy, modify, merge, publish,
-// distribute, sublicense, and/or sell copies of the Software, and to
-// permit persons to whom the Software is furnished to do so, subject to
-// the following conditions:
-//
-// The above copyright notice and this permission notice shall be included
-// in all copies or substantial portions of the Software.
-//
-// THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
-// EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
-// MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
-// IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY
-// CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
-// TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
-// SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
-
-#include <xtensa/coreasm.h>
-#include <xtensa/corebits.h>
-#include <xtensa/specreg.h>
-#include <xtensa/cacheasm.h>
-#include <xtensa/cacheattrasm.h>
-#include <xtensa/xdm-regs.h>
-#include <xtensa/config/specreg.h>
-#include <xtensa/config/core-isa.h>
-#include <xtensa/xtruntime-core-state.h>
-#include "xtos-internal.h"
-
-
- .text
-
-
-
- // void _xtos_core_restore(unsigned retvalue, XtosCoreState *savearea)
- //
- // Restore processor state.
- // If save area signature is bad, function just returns.
- // Else, processor state is restored, and execution resumes
- // according to that saved processor state.
- //
- // On entry:
- // Caches are ready to use (initialized or warm, as the case may be).
- //
- .align 4
- .global _xtos_core_restore
- .type _xtos_core_restore,@function
-_xtos_core_restore:
- abi_entry
-
- // Check the save area's signature:
- movi a5, CORE_STATE_SIGNATURE
- l32i a4, a3, CS_SA_signature
- movi a6, 0
- bne a4, a5, 1f // if bad, just return
-
-#if XCHAL_HAVE_INTERRUPTS
- rsil a4, 15 // disable interrupts...
- wsr a6, INTENABLE
-#endif
-
- // Here, call0 is used as an unlimited range jump. It does not return.
- call0 _xtos_core_restore_nw
-
-1: abi_return
-
- .size _xtos_core_restore, . - _xtos_core_restore
-
-
-
- // Restore processor state.
- // On entry:
- // Caches are ready to use (initialized or warm, as the case may be).
- // a2 = return value passed to restored processor state
- // a3 = pointer to save area to restore from
- // INTENABLE = 0 (interrupts all disabled)
- // LITBASE = initialized (per reset vector, not restored)
- // touching a4..a7 won't overflow
- // other registers are mostly undefined
- //
- .align 4
- .global _xtos_core_restore_nw
- .type _xtos_core_restore_nw,@function
-_xtos_core_restore_nw:
-
-#if XCHAL_HAVE_WINDOWED
- s32i a2, a3, CS_SA_areg + 2*4 // save a2 thru rotation
- wsr a3, EXCSAVE1 // save a3 thru rotation
- l32i a6, a3, CS_SA_windowstart // restore windowstart
- l32i a5, a3, CS_SA_windowbase // restore windowbase
- wsr a6, WINDOWSTART
- wsr a5, WINDOWBASE
- rsync
- // a0-a15 have possibly all changed, so need to reload a3
- rsr a3, EXCSAVE1 // restore a3
- l32i a2, a3, CS_SA_areg + 2*4 // restore a2 (return value)
-#endif
-
- //movi a0, 0
- l32i a0, a3, CS_SA_restore_label // _xtos_core_save_common's return PC
-
- // Just for consistency...
-#if XCHAL_HAVE_INTERRUPTS || XCHAL_HAVE_EXCEPTIONS
- movi a4, 0x11
- wsr a4, ps
- rsync
-#endif
-
- l32i a5, a3, CS_SA_sar // restore sar
- wsr a5, sar
-
-#if XCHAL_HAVE_PSO_CDM
- // Restore PWRCTL (except ShutProcOffOnPWait, cleared when all is done).
- movi a4, XDM_MISC_PWRCTL
- movi a7, PWRCTL_CORE_SHUTOFF // aka ShutProcOffOnPWait
- rer a6, a4 // read pwrctl
- l32i a5, a3, CS_SA_pwrctl // get saved pwrctl
- and a7, a7, a6 // keep just ShutProcOffOnPWait bit
- or a5, a5, a7 // keep it set if already set (clear later)
- wer a5, a4 // restore pwrctl (except ShutProcOffOnPWait)
-#endif
-
- .macro rest_level num
- l32i a5, a3, CS_SA_epc + 4*\num
- wsr a5, EPC_2 + \num
- l32i a5, a3, CS_SA_eps + 4*\num
- wsr a5, EPS_2 + \num
- l32i a5, a3, CS_SA_excsave + 4*\num
- wsr a5, EXCSAVE_2 + \num
- .endm
- iterate 0, XCHAL_NUM_INTLEVELS+XCHAL_HAVE_NMI-2, rest_level
-
-#if XCHAL_HAVE_LOOPS
- l32i a5, a3, CS_SA_lbeg
- wsr a5, LBEG
- l32i a5, a3, CS_SA_lend
- wsr a5, LEND
- l32i a5, a3, CS_SA_lcount
- wsr a5, LCOUNT
-#endif
-#if XCHAL_HAVE_ABSOLUTE_LITERALS
- l32i a5, a3, CS_SA_litbase
- wsr a5, LITBASE
-#endif
-#if XCHAL_HAVE_VECBASE
- l32i a5, a3, CS_SA_vecbase
- wsr a5, VECBASE
-#endif
-#if XCHAL_HAVE_S32C1I && (XCHAL_HW_MIN_VERSION >= XTENSA_HWVERSION_RC_2009_0) /* have ATOMCTL ? */
- l32i a5, a3, CS_SA_atomctl
- wsr a5, ATOMCTL
-#endif
-#if XCHAL_HAVE_PREFETCH
- l32i a5, a3, CS_SA_prefctl
- wsr a5, PREFCTL
-#endif
-#if XCHAL_USE_MEMCTL
- l32i a5, a3, CS_SA_memctl
- wsr a5, MEMCTL
-#endif
-#if XCHAL_HAVE_DEBUG
- // NOTE: restore of debug state is conditional,
- // as the power-down and wakeup code might be actively debugged.
- rsr a5, ICOUNTLEVEL
- bnez a5, 1f // skip if being single-stepped (not failsafe!)
- l32i a5, a3, CS_SA_icount
- wsr a5, ICOUNT
- l32i a5, a3, CS_SA_icountlevel
- wsr a5, ICOUNTLEVEL
-1:
- //l32i a5, a3, CS_SA_debugcause // (won't get restored?)
- //wsr a5, DEBUGCAUSE
- //l32i a5, a3, CS_SA_ddr
- //wsr a5, DDR
-# if XCHAL_NUM_IBREAK
- rsr a6, IBREAKENABLE
- bnez a5, 1f // skip restore if already some ibreaks defined
- .macro rest_ibreak num
- l32i a5, a3, CS_SA_ibreaka + 4*\num
- wsr a5, IBREAKA + \num
- .endm
- iterate 0, XCHAL_NUM_IBREAK-1, rest_ibreak
- l32i a5, a3, CS_SA_ibreakenable
- wsr a5, IBREAKENABLE
-1:
-# endif
- .macro rest_dbreak num
- rsr a6, DBREAKC + \num
- bbsi.l a6, 30, 1f // skip restore of that dbreak if already active
- bbsi.l a6, 31, 1f // ditto
- l32i a5, a3, CS_SA_dbreaka + 4*\num
- wsr a5, DBREAKA + \num
- l32i a5, a3, CS_SA_dbreakc + 4*\num
- wsr a5, DBREAKC + \num
-1:
- .endm
- iterate 0, XCHAL_NUM_DBREAK-1, rest_dbreak
-#endif
- .macro rest_misc num
- l32i a5, a3, CS_SA_misc + 4*\num
- wsr a5, MISC_REG_0 + \num
- .endm
- iterate 0, XCHAL_NUM_MISC_REGS-1, rest_misc
-#if XCHAL_HAVE_MEM_ECC_PARITY
- l32i a5, a3, CS_SA_mepc
- wsr a5, MEPC
- l32i a5, a3, CS_SA_meps
- wsr a5, MEPS
- l32i a5, a3, CS_SA_mesave
- wsr a5, MESAVE
- l32i a5, a3, CS_SA_mesr
- wsr a5, MESR
- l32i a5, a3, CS_SA_mecr
- wsr a5, MECR
- l32i a5, a3, CS_SA_mevaddr
- wsr a5, MEVADDR
-#endif
-
- /* TIE state */
- addi a4, a3, CS_SA_ncp
- xchal_ncp_load a4, a5,a6,a7,a8 // restore non-coprocessor state
-#if XCHAL_HAVE_CP
- movi a6, -1
- wsr a6, CPENABLE // enable all coprocessors
- rsync
- xchal_cp0_load a4, a5,a6,a7,a8 continue=1
- xchal_cp1_load a4, a5,a6,a7,a8 continue=1
- xchal_cp2_load a4, a5,a6,a7,a8 continue=1
- xchal_cp3_load a4, a5,a6,a7,a8 continue=1
- xchal_cp4_load a4, a5,a6,a7,a8 continue=1
- xchal_cp5_load a4, a5,a6,a7,a8 continue=1
- xchal_cp6_load a4, a5,a6,a7,a8 continue=1
- xchal_cp7_load a4, a5,a6,a7,a8 continue=1
- //xchal_cp8_load a4, a5,a6,a7,a8 continue=1
- //xchal_cp9_load a4, a5,a6,a7,a8 continue=1
- //xchal_cp10_load a4, a5,a6,a7,a8 continue=1
- //xchal_cp11_load a4, a5,a6,a7,a8 continue=1
- //xchal_cp12_load a4, a5,a6,a7,a8 continue=1
- //xchal_cp13_load a4, a5,a6,a7,a8 continue=1
- //xchal_cp14_load a4, a5,a6,a7,a8 continue=1
- //xchal_cp15_load a4, a5,a6,a7,a8 continue=1
- l32i a5, a3, CS_SA_cpenable
- wsr a5, CPENABLE
-#endif
-
- /* TLB state (for known MMU types only, not internal custom) */
- // FIXME FIXME FIXME TODO:
- // This restore code does not work in the general case,
- // for CaXLT or full MMU, in particular when any address mappings
- // were active when saved, that don't match reset state and affect
- // code and data currently being accessed for restore.
-#if XCHAL_HAVE_MIMIC_CACHEATTR || XCHAL_HAVE_XLT_CACHEATTR
- addi a4, a3, CS_SA_tlbs // where to start loading TLB entry info
- movi a5, 0x20000000
- movi a6, 0
-1:
- l32i a7, a4, 0
- wdtlb a7, a6 // write DTLB entry PPN + CA
- dsync
- l32i a7, a4, 4
- j 2f
- // Ensure WITLB and ISYNC are in same cache line, when writing ITLB
- // entry that maps this currently running code
- // (micro-architecture defined sequence):
- .begin no-transform
- .align 16
-2: witlb a7, a6 // write ITLB entry PPN + CA
- isync
- .end no-transform
- nop
- nop
- addi a4, a4, 8
- add a6, a6, a5
- bnez a6, 1b
-
-#elif XCHAL_HAVE_PTP_MMU
- addi a4, a3, CS_SA_tlbs // where to start storing TLB entry info
- movi a10, _xtos_pso_tlbmap
- movi a11, _xtos_pso_tlbmap_end
- l32i a14, a3, CS_SA_dtlbcfg
- l32i a15, a3, CS_SA_itlbcfg
- wsr a14, dtlbcfg // page size index (0..3) for each DTLB way
- wsr a15, itlbcfg // page size index (0..3) for each ITLB way
- l32i a5, a3, CS_SA_ptevaddr
- wsr a5, ptevaddr
- rsync
- // Loop from last way to first (less register pressure that way).
-.Loop_tlbmap_rest:
- addi a11, a11, -8 // next way
- l32i a8, a11, 0 // map of four (page size log2) per index for this way
- // DTLB page size:
- extui a12, a14, 0, 4 // page size index for this DTLB way
- srli a14, a14, 4 // (for next way)
- ssa8l a12 // prepare to shift right by 8*a12
- srl a12, a8 // page size log2 for this DTLB way
- ssl a12 // prepare to shift left by a12
- movi a12, 1 // (to compute 1 << (page size log2))
- sll a12, a12 // page size for this DTLB way
-
- // Restore all entries of this DTLB way:
- l32i a9, a11, 4 // number of entries for this way
- sub a5, a11, a10 // way number * 8
- srli a5, a5, 3 // way number
- extui a9, a9, 0, 8
-1:
- l32i a6, a4, 0 // read entry VPN + ASID
- extui a7, a6, 0, 8 // get ASID
- bnez a7, 2f // if non-zero, need WDTLB
- add a6, a6, a5 // zero, so need IDTLB - add way number
- idtlb a6 // invalidate DTLB entry
- j 5f
-2: // Non-zero ASID. Put in RASID and adjust PS.RING accordingly.
- bgeui a7, 5, 3f // branch if ASID >= 5
- addi a7, a7, -1
- slli a7, a7, 6 // PS.RING = ASID - 1
- addi a7, a7, 0x11 // PS.EXCM=1, PS.INTLEVEL=1
- movi a6, 0x04030201 // for ASID in {1 .. 4}
- j 4f
-3: // ASID >= 5, place it in RASID
- movi a6, 0x00030201
- slli a7, a7, 24
- add a6, a7, a6 // RASID = 0x <ASID> 03 02 01
- movi a7, 0xd1 // PS.RING=3, PS.EXCM=1, PS.INTLEVEL=1
-4: wsr a6, rasid
- wsr a7, ps
- rsync
- l32i a6, a4, 0 // read entry VPN + ASID
- l32i a7, a4, 4 // read entry PPN + CA
- srli a6, a6, 8 // replace ASID ...
- slli a6, a6, 8 // ...
- add a6, a6, a5 // ... with way number
- wdtlb a7, a6 // write DTLB entry ...
-5: dsync
- addi a4, a4, 8
- add a5, a5, a12 // next entry of this DTLB way
- addi a9, a9, -1
- bnez a9, 1b
-
- // ITLB page size:
- extui a12, a15, 0, 4 // page size index for this ITLB way
- srli a15, a15, 4 // (for next way)
- ssa8l a12 // prepare to shift right by 8*a12
- srl a12, a8 // page size log2 for this ITLB way
- ssl a12 // prepare to shift left by a12
- movi a12, 1 // (to compute 1 << (page size log2))
- sll a12, a12 // page size for this ITLB way
-
- // Restore all entries of this ITLB way:
- l32i a9, a11, 4 // number of entries for this way
- sub a5, a11, a10 // way number * 8
- srli a5, a5, 3 // way number
- bbsi.l a9, 15, 6f // skip ITLB if is a DTLB-only way
- extui a9, a9, 0, 8
-1:
- l32i a6, a4, 0 // read entry VPN + ASID
- extui a7, a6, 0, 8 // get ASID
- bnez a7, 2f // if non-zero, need WITLB
- add a6, a6, a5 // zero, so need IITLB - add way number
- iitlb a6 // invalidate ITLB entry
- j 5f
-2: // Non-zero ASID. Put in RASID and adjust PS.RING accordingly.
- bgeui a7, 5, 3f // branch if ASID >= 5
- addi a7, a7, -1
- slli a7, a7, 6 // PS.RING = ASID - 1
- addi a7, a7, 0x11 // PS.EXCM=1, PS.INTLEVEL=1
- movi a6, 0x04030201 // for ASID in {1 .. 4}
- j 4f
-3: // ASID >= 5, place it in RASID
- movi a6, 0x00030201
- slli a7, a7, 24
- add a6, a7, a6 // RASID = 0x <ASID> 03 02 01
- movi a7, 0xd1 // PS.RING=3, PS.EXCM=1, PS.INTLEVEL=1
-4: wsr a6, rasid
- wsr a7, ps
- rsync
- l32i a6, a4, 0 // read entry VPN + ASID
- l32i a7, a4, 4 // read entry PPN + CA
- srli a6, a6, 8 // replace ASID ...
- slli a6, a6, 8 // ...
- add a6, a6, a5 // ... with way number
- j 8f
- .align 16 // ensure WITLB and ISYNC in same cache line
-8: witlb a7, a6 // write ITLB entry ...
-5: isync
- addi a4, a4, 8
- add a5, a5, a12 // next entry of this ITLB way
- addi a9, a9, -1
- bnez a9, 1b
-6:
-
- bne a11, a10, .Loop_tlbmap_rest // loop for next TLB way
- l32i a5, a3, CS_SA_rasid
- wsr a5, rasid
- movi a6, 0x11
- wsr a6, ps
- rsync
- // Done saving TLBs.
-#endif
-
-#if XCHAL_HAVE_WINDOWED
- // All the stack frames (except for our own) are supposed to be spilled
- // into the stack. So now we restore the saved registers for our caller
- // (and its caller) into the correct locations in the stack. See the
- // comments in core-save.S and also the Xtensa Programmers Guide for
- // more information. Of course we only restore if there is valid saved
- // state.
-
- l32i a4, a3, CS_SA_caller_regs_saved // flag
- beqz a4, .Lendcr // skip restore if 0
-
- // Restore our caller's a0-a3
-
- l32i a1, a3, CS_SA_areg + 1*4 // restore a1
- addi a4, a1, -16
- l32i a5, a3, CS_SA_caller_regs
- l32i a6, a3, CS_SA_caller_regs + 4
- s32i a5, a4, 0 // caller a0
- s32i a6, a4, 4 // caller a1
- l32i a5, a3, CS_SA_caller_regs + 8
- l32i a6, a3, CS_SA_caller_regs + 12
- s32i a5, a4, 8 // caller a2
- s32i a6, a4, 12 // caller a3
-
- // Now restore our callers caller's a0-a3
-
- l32i a5, a3, CS_SA_caller_regs + 16
- l32i a6, a3, CS_SA_caller_regs + 20
- s32i a5, a1, 0 // caller caller a0
- s32i a6, a1, 4 // caller caller a1
- l32i a5, a3, CS_SA_caller_regs + 24
- l32i a6, a3, CS_SA_caller_regs + 28
- s32i a5, a1, 8 // caller caller a2
- s32i a6, a1, 12 // caller caller a3
-
- // Now restore caller's a4-a11 as required
- // NOTE a0 is pointing to _xtos_core_save() not the actual caller
-
- l32i a4, a3, CS_SA_areg // load actual return address
- extui a4, a4, 30, 2 // top 2 bits of ret addr
- blti a4, 2, .Lendcr
- l32i a5, a1, 4 // a5 <- caller caller a1
- slli a4, a4, 4
- sub a4, a5, a4 // a4 <- bottom of extra save area
- addi a5, a5, -16 // a5 <- top of extra save area
- addi a6, a3, CS_SA_caller_regs + 32 // location to start restore from
-.Lcrloop:
- l32i a7, a6, 0 // Restore in groups of 4 registers
- l32i a8, a6, 4
- s32i a7, a4, 0
- s32i a8, a4, 4
- l32i a7, a6, 8
- l32i a8, a6, 12
- s32i a7, a4, 8
- s32i a8, a4, 12
- addi a4, a4, 16
- addi a6, a6, 16
- blt a4, a5, .Lcrloop
-.Lendcr:
-#endif
-
- // Restore timers and CCOUNT right before enabling interrupts. We will
- // try to restore any timer interrupts that were pending (as indicated
- // by the INTERRUPT register) at the time of the state save.
-#if XCHAL_HAVE_CCOUNT
- .macro restore_timer num intr
- l32i a5, a3, CS_SA_ccompare + 4*\num // Load CCOMPARE value
- l32i a6, a3, CS_SA_interrupt // Load old INTERRUPT value
- wsr a5, CCOMPARE_0 + \num // Restore CCOMPARE
- bbci a6, \intr, .Lrtdone\num // Intr not set for this timer
- addi a5, a5, -1 // CCOUNT = CCOMPARE - 1
-.Lrttry\num:
- wsr a5, CCOUNT // Set CCOUNT and wait
- esync
- nop
- rsr a6, INTERRUPT
- bbci a6, \intr, .Lrttry\num // If intr not set then retry
-.Lrtdone\num:
- .endm
-
-#if XCHAL_NUM_TIMERS > 0
- restore_timer 0 XCHAL_TIMER0_INTERRUPT
-#endif
-#if XCHAL_NUM_TIMERS > 1
- restore_timer 1 XCHAL_TIMER1_INTERRUPT
-#endif
-#if XCHAL_NUM_TIMERS > 2
- restore_timer 2 XCHAL_TIMER2_INTERRUPT
-#endif
-#if XCHAL_NUM_TIMERS > 3
- restore_timer 3 XCHAL_TIMER3_INTERRUPT
-#endif
-
- // Attempt to clear any spurious timer interrupts caused by the CCOUNT
- // dance above.
-#if XCHAL_NUM_TIMERS > 0
- l32i a5, a3, CS_SA_ccount // Restore CCOUNT
- wsr a5, CCOUNT
- l32i a5, a3, CS_SA_interrupt // Load old intr value
- bbsi a5, XCHAL_TIMER0_INTERRUPT, .Lx1 // Skip if timer0 intr set
- rsr a6, CCOMPARE_0 // Force timer0 intr clear
- wsr a6, CCOMPARE_0
-.Lx1:
-#if XCHAL_NUM_TIMERS > 1
- bbsi a5, XCHAL_TIMER1_INTERRUPT, .Lx2 // Skip if timer1 intr set
- rsr a6, CCOMPARE_1 // Force timer1 intr clear
- wsr a6, CCOMPARE_1
-.Lx2:
-#endif
-#if XCHAL_NUM_TIMERS > 2
- bbsi a5, XCHAL_TIMER2_INTERRUPT, .Lx3 // Skip if timer2 intr set
- rsr a6, CCOMPARE_2 // Force timer2 intr clear
- wsr a6, CCOMPARE_2
-.Lx3:
-#endif
-#if XCHAL_NUM_TIMERS > 3
- bbsi a5, XCHAL_TIMER3_INTERRUPT, .Lx4 // Skip if timer3 intr set
- rsr a6, CCOMPARE_3 // Force timer3 intr clear
- wsr a6, CCOMPARE_3
-.Lx4:
-#endif
-#endif
-
- l32i a5, a3, CS_SA_ccount // Restore CCOUNT again
- wsr a5, CCOUNT
-#endif
-
-#if XCHAL_HAVE_INTERRUPTS
- rsil a6, 15 // disable interrupts before enabling with INTENABLE
- l32i a5, a3, CS_SA_intenable
- wsr a5, INTENABLE
- movi a4, XCHAL_INTTYPE_MASK_SOFTWARE // restore any pending software interrupts
- l32i a5, a3, CS_SA_interrupt
- and a5, a5, a4
- wsr a5, INTSET
- rsync
-#endif
-
- //l32i a0, a3, CS_SA_restore_label // _xtos_core_save_common's return PC
-#if XCHAL_HAVE_INTERRUPTS || XCHAL_HAVE_EXCEPTIONS
- //l32i a4, a3, CS_SA_ps
- l32i a5, a3, CS_SA_epc1
- wsr a5, EPC1
- l32i a5, a3, CS_SA_excsave1
- wsr a5, EXCSAVE1
-# ifdef XCHAL_DOUBLEEXC_VECTOR_VADDR
- l32i a5, a3, CS_SA_depc
- wsr a5, DEPC
-# endif
- //wsr a4, ps // PS restored by caller
- //rsync
-#endif
-
-#if XCHAL_HAVE_PSO_CDM
- // As late as possible, wait for debug to wakeup, and clear PWRCTL.ShutProcOffOnPWait.
- movi a4, XDM_MISC_PWRCTL
- rer a5, a4 // read pwrctl
-
- // Wait for debug powerup to complete (if started):
- bbci.l a5, PWRCTL_DEBUG_WAKEUP_SHIFT, 1f
- movi a7, XDM_MISC_PWRSTAT
-2: rer a6, a7 // read PWRSTAT
- bbci.l a6, PWRSTAT_DEBUG_DOMAIN_ON_SHIFT, 2b // loop until debug is powered up
-1:
-
- movi a7, ~PWRCTL_CORE_SHUTOFF // aka ShutProcOffOnPWait
- and a5, a5, a7 // clear ShutProcOffOnPWait bit
- wer a5, a4 // update pwrctl
-#endif
-
- movi a4, 0
- s32i a4, a3, CS_SA_signature // make sure save area is marked as no longer valid
-#if XCHAL_DCACHE_IS_WRITEBACK
- dhwb a3, CS_SA_signature
-#endif
- ret // return from _xtos_core_save_common
- // NOTE: a2 holds return value as specified to
- // _xtos_core_restore()
-
- .size _xtos_core_restore_nw, . - _xtos_core_restore_nw
-
diff --git a/src/arch/xtensa/up/xtos/core-save.S b/src/arch/xtensa/up/xtos/core-save.S
deleted file mode 100644
index dd1aa7a..0000000
--- a/src/arch/xtensa/up/xtos/core-save.S
+++ /dev/null
@@ -1,684 +0,0 @@
-// core-save.S -- core state save/restore routines (used by PSO)
-// $Id: //depot/rel/Eaglenest/Xtensa/OS/xtos/core-save.S#1 $
-
-// Copyright (c) 2012-2013 Tensilica Inc.
-//
-// Permission is hereby granted, free of charge, to any person obtaining
-// a copy of this software and associated documentation files (the
-// "Software"), to deal in the Software without restriction, including
-// without limitation the rights to use, copy, modify, merge, publish,
-// distribute, sublicense, and/or sell copies of the Software, and to
-// permit persons to whom the Software is furnished to do so, subject to
-// the following conditions:
-//
-// The above copyright notice and this permission notice shall be included
-// in all copies or substantial portions of the Software.
-//
-// THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
-// EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
-// MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
-// IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY
-// CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
-// TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
-// SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
-
-#include <xtensa/coreasm.h>
-#include <xtensa/corebits.h>
-#include <xtensa/specreg.h>
-#include <xtensa/cacheasm.h>
-#include <xtensa/cacheattrasm.h>
-#include <xtensa/xdm-regs.h>
-#include <xtensa/config/specreg.h>
-#include <xtensa/xtruntime-core-state.h>
-#include "xtos-internal.h"
-
-
- .text
-
-
- // (Place this alternate entry symbol *outside* the _xtos_core_save()
- // function, to avoid confusing debugging / profiling / etc.)
- .align 4
- .global _xtos_core_save_entry
- .type _xtos_core_save_entry,@function
-_xtos_core_save_entry:
- j .Lcore_save
- .size _xtos_core_save_entry, . - _xtos_core_save_entry
-
-
- // int _xtos_core_save(unsigned flags, XtosCoreState *savearea, void *code)
- //
- // Generic processor state save routine.
- //
- // On entry (after ENTRY if windowed):
- // a0 = return PC
- // a2 = flags argument
- // a3 = ptr to save area
- // a4 = ptr to code to jump to after save (just return if 0)
- // Returns:
- // 0 when first returning from this call (if a4 == 0)
- // non-zero (passed from restore call) when returning from restore
- // (if a4 != 0, return behavior if any depends on code at a4)
- //
- .align 4
- .global _xtos_core_save
- .type _xtos_core_save,@function
-_xtos_core_save:
- abi_entry
-
-.Lcore_save:
- s32i a0, a3, CS_SA_areg + 0*4 // save a0 (clobbered below)
- s32i a1, a3, CS_SA_areg + 1*4 // save a1
- s32i a2, a3, CS_SA_areg + 2*4 // save a2 (flags arg, for debugging only)
- s32i a4, a3, CS_SA_areg + 4*4 // save a4 (code to jump to after saving)
-#ifdef __XTENSA_CALL0_ABI__
- // Callee-saved regs:
- s32i a12, a3, CS_SA_areg + 12*4 // save a12
- s32i a13, a3, CS_SA_areg + 13*4 // save a13
- s32i a14, a3, CS_SA_areg + 14*4 // save a14
- s32i a15, a3, CS_SA_areg + 15*4 // save a15
-#else
- call4 xthal_window_spill // spill live caller windows to stack
-#endif
- j .Ls1
-
- .align 16
-.Ls1:
-#if XCHAL_HAVE_INTERRUPTS
- rsil a4, 15 // disable interrupts before clobbering a0
-#elif XCHAL_HAVE_EXCEPTIONS
- rsr a4, ps
-#endif
-#if XCHAL_HAVE_CCOUNT
- rsr a5, CCOUNT // save CCOUNT restore value
-#endif
-#if XCHAL_HAVE_INTERRUPTS
- rsr a6, INTERRUPT // save pending interrupts
- s32i a6, a3, CS_SA_interrupt
-#endif
-#if XCHAL_HAVE_CCOUNT
- s32i a5, a3, CS_SA_ccount
-#endif
-
- call0 _xtos_core_save_common // save and shutoff -- returns after wakeup
-
- // a2 now contains return value.
- // a3 still points to save area.
- // Interrupts still disabled.
-
- // Restore WINDOWSTART to single window. Leave WINDOWBASE wherever it is.
- //rsr a6, WINDOWBASE
- //movi a5, 1
- //ssl a6
- //sll a5, a5
- //wsr a5, WINDOWSTART
- //rsync
-
- l32i a0, a3, CS_SA_areg + 0*4 // restore a0
- l32i a1, a3, CS_SA_areg + 1*4 // restore a1
-#ifdef __XTENSA_CALL0_ABI__
- // Callee-saved regs:
- l32i a12, a3, CS_SA_areg + 12*4 // restore a12
- l32i a13, a3, CS_SA_areg + 13*4 // restore a13
- l32i a14, a3, CS_SA_areg + 14*4 // restore a14
- l32i a15, a3, CS_SA_areg + 15*4 // restore a15
-#endif
-
-#if XCHAL_HAVE_EXCEPTIONS
- // Now that we've restored windowed state (a0,a1), we can restore interrupts.
- l32i a4, a3, CS_SA_ps // restore ps
- wsr a4, ps
- rsync
-#endif
-
- abi_return
-
-
-
- // Generic processor state save routine, callable from assembly-level
- // (Does not assume valid stack, saves all ARs, no window-spill etc.)
- //
- // On entry:
- // a0 = return PC
- // a2 = flags argument
- // a3 = ptr to save area
- // a4 = ptr to code to jump to after save (just return if 0)
- // All other registers are saved.
- // Returns:
- // 0 when first returning from this call (if a4 == 0)
- // non-zero (passed from restore call) when returning from restore
- // (if a4 != 0, return behavior if any depends on code at a4)
- //
- .align 4
- .global _xtos_core_save_nw
-_xtos_core_save_nw:
- s32i a0, a3, CS_SA_areg + 0*4 // save a0 (clobbered below)
- s32i a1, a3, CS_SA_areg + 1*4 // save a1
- s32i a2, a3, CS_SA_areg + 2*4 // save a2 (flags arg, for debugging only)
- s32i a4, a3, CS_SA_areg + 4*4 // save a4 (code to jump to after saving)
- s32i a5, a3, CS_SA_areg + 5*4 // save a5
- s32i a6, a3, CS_SA_areg + 6*4 // save a6
- s32i a7, a3, CS_SA_areg + 7*4 // save a7
- j .Ls2
-
- .align 16
-.Ls2:
-#if XCHAL_HAVE_INTERRUPTS
- rsil a4, 15 // disable interrupts before rotating etc
-#elif XCHAL_HAVE_EXCEPTIONS
- rsr a4, ps
-#endif
-#if XCHAL_HAVE_CCOUNT
- rsr a5, CCOUNT // save CCOUNT restore value
-#endif
-#if XCHAL_HAVE_INTERRUPTS
- rsr a6, INTERRUPT // save pending interrupts
- s32i a6, a3, CS_SA_interrupt
-#endif
-#if XCHAL_HAVE_CCOUNT
- s32i a5, a3, CS_SA_ccount
-#endif
-
-#if XCHAL_HAVE_WINDOWED
- movi a5, XCHAL_NUM_AREGS / 8 - 1 // number of 8-reg chunks to save (a0-a7 already done)
-#endif
-1: s32i a8, a3, CS_SA_areg + 8*4 // save a8
- s32i a9, a3, CS_SA_areg + 9*4 // save a9
- s32i a10,a3, CS_SA_areg + 10*4 // save a10
- s32i a11,a3, CS_SA_areg + 11*4 // save a11
- s32i a12,a3, CS_SA_areg + 12*4 // save a12
- s32i a13,a3, CS_SA_areg + 13*4 // save a13
- s32i a14,a3, CS_SA_areg + 14*4 // save a14
- s32i a15,a3, CS_SA_areg + 15*4 // save a15
-#if XCHAL_HAVE_WINDOWED
- addi a11, a3, 8*4 // next frame (a11 will become a3, a13 become a5)
- addi a13, a5, -1
- rotw 2
- bnez a5, 1b // loop until all frames done
- rotw 2 // back to starting windowbase
-#endif
-
- movi a1, 0 // not to save any regs from stack
- call0 _xtos_core_save_common
-
- // a2 now contains return value.
- // a3 still points to save area.
- // Interrupts still disabled.
-
-#if XCHAL_HAVE_WINDOWED
- rotw -2
- movi a5, XCHAL_NUM_AREGS / 8 - 1 // 8-reg chunks to restore (a0-a7 already done)
- addi a3, a11, XCHAL_NUM_AREGS * 4
-1: rotw -2
- addi a3, a11, -8*4
- addi a5, a13, -1
-#endif
- l32i a8, a3, CS_SA_areg + 8*4 // restore a8
- l32i a9, a3, CS_SA_areg + 9*4 // restore a9
- l32i a10,a3, CS_SA_areg + 10*4 // restore a10
- l32i a11,a3, CS_SA_areg + 11*4 // restore a11
- l32i a12,a3, CS_SA_areg + 12*4 // restore a12
- l32i a13,a3, CS_SA_areg + 13*4 // restore a13
- l32i a14,a3, CS_SA_areg + 14*4 // restore a14
- l32i a15,a3, CS_SA_areg + 15*4 // restore a15
-#if XCHAL_HAVE_WINDOWED
- bnez a5, 1b // loop until all frames done
- // We're now back to starting windowbase, and original a3.
-#endif
-
- l32i a0, a3, CS_SA_areg + 0*4 // restore a0
- l32i a1, a3, CS_SA_areg + 1*4 // restore a1
- // Don't clobber return value, so don't restore a2.
- l32i a4, a3, CS_SA_areg + 4*4 // restore a4
- l32i a5, a3, CS_SA_areg + 5*4 // restore a5
- l32i a6, a3, CS_SA_areg + 6*4 // restore a6
-#if XCHAL_HAVE_EXCEPTIONS
- // Now that we've restored windowed state (a0,a1,done rotating), we can restore interrupts.
- l32i a7, a3, CS_SA_ps // restore ps
- wsr a7, ps
- rsync
-#endif
- l32i a7, a3, CS_SA_areg + 7*4 // restore a7
- ret
-
-
-
-
- // Common state save / shut-off code.
- //
- // a0 = return PC within caller shut-off routine
- // a1 = stack if != 0
- // a2 = flags argument
- // a3 = pointer to _xtos_pso_savearea
- // a4 = PS to save/restore
- // PS.INTLEVEL = 15 (interrupts disabled, except NMI)
- // a5-a15 (and other ARs) are available.
- // NOTE: CCOUNT and INTERRUPT have already been saved in save area.
- //
- .align 4
- //.global _xtos_core_save_common
-_xtos_core_save_common:
-#if XCHAL_HAVE_EXCEPTIONS
- s32i a4, a3, CS_SA_ps // save PS
-#endif
-
-#if XCHAL_HAVE_WINDOWED
- // The following discussion is valid if we have a stack:
- // At this point, all non-live register windows have been spilled to the
- // stack. However, we cannot leave any spilled registers in our stack frame
- // or our caller's stack frame, since these frames could change after we
- // return and before restore() is called. So all spilled registers in the
- // current and previous stack frames must be saved to the save area. This
- // means a max of 16 registers: 4 base save registers for our caller, upto
- // 8 extra save registers for our caller, and 4 base save registers for the
- // next function up from our caller. The stack looks like this:
- //
- // ------------------------------- <---- stack ptr of function (i - 2)
- // Base save area i - 3
- // -------------------------------
- // Extra save area i - 1
- // (0-8 registers depending on call type)
- // -------------------------------
- // Locals i - 1
- // ------------------------------- <---- stack ptr of function (i - 1)
- // Base save area i - 2 (our caller)
- //
- // ------------------------------- <---- Our stack ptr (a1)
- // Base save area i - 1
- // -------------------------------
- //
- // We don't have any extra save area or locals in our frame. See the
- // Xtensa Programmer's Guide for more details of the stack layout.
- //
- // NOTE that we are not counting the call0 to _xtos_core_save_common() since
- // that does not result in any register window rotation nor stack ptr change.
-
- s32i a1, a3, CS_SA_caller_regs_saved // save flag
- beqz a1, .Lendcr // skip if no stack
-
- // Save our caller's a0-a3 from the base save area (a1-16)
-
- addi a4, a1, -16
- l32i a5, a4, 0
- l32i a6, a4, 4
- s32i a5, a3, CS_SA_caller_regs // caller a0
- s32i a6, a3, CS_SA_caller_regs + 4 // caller a1
- l32i a5, a4, 8
- l32i a6, a4, 12
- s32i a5, a3, CS_SA_caller_regs + 8 // caller a2
- s32i a6, a3, CS_SA_caller_regs + 12 // caller a3
-
- // Save our callers caller's a0-a3 from its base save area (a1+0)
-
- l32i a5, a1, 0
- l32i a6, a1, 4
- s32i a5, a3, CS_SA_caller_regs + 16 // caller caller a0
- s32i a6, a3, CS_SA_caller_regs + 20 // caller caller a1
- l32i a5, a1, 8
- l32i a6, a1, 12
- s32i a5, a3, CS_SA_caller_regs + 24 // caller caller a2
- s32i a6, a3, CS_SA_caller_regs + 28 // caller caller a3
-
- // Now save 0-8 registers for our caller from its ext save area
- // NOTE we can't use a0 directly because we are one level down
-
- l32i a4, a3, CS_SA_areg // pull in the return address
- extui a4, a4, 30, 2 // Top 2 bits of ret addr
- blti a4, 2, .Lendcr // No regs to save
- l32i a5, a1, 4 // a5 <- caller caller a1
- slli a4, a4, 4
- sub a4, a5, a4 // a4 <- bottom of extra save area
- addi a5, a5, -16 // a5 <- top of extra save area
- addi a6, a3, CS_SA_caller_regs + 32 // location to start saving to
-.Lcrloop:
- l32i a7, a4, 0 // Save in groups of 4 registers
- l32i a8, a4, 4
- s32i a7, a6, 0
- s32i a8, a6, 4
- l32i a7, a4, 8
- l32i a8, a4, 12
- s32i a7, a6, 8
- s32i a8, a6, 12
- addi a4, a4, 16
- addi a6, a6, 16
- blt a4, a5, .Lcrloop
-.Lendcr:
-#endif
-
- // We want to save the CCOUNT value as soon as feasible after disabling
- // interrupts, so that the counter does not run past any CCOMPARE value
- // and miss a timer interrupt. The callers of this function have saved
- // the values of CCOUNT and INTERRUPT immediately after disabling interrupts.
-
-#if XCHAL_HAVE_CCOUNT
- .macro save_timer num
- rsr a5, CCOMPARE_0 + \num
- s32i a5, a3, CS_SA_ccompare + 4*\num
- .endm
- iterate 0, XCHAL_NUM_TIMERS-1, save_timer
-#endif
-
- s32i a0, a3, CS_SA_restore_label // where to return to, to return from function
-#if XCHAL_HAVE_INTERRUPTS || XCHAL_HAVE_EXCEPTIONS
- rsr a5, EPC1
- s32i a5, a3, CS_SA_epc1
- rsr a5, EXCSAVE1
- s32i a5, a3, CS_SA_excsave1
-# ifdef XCHAL_DOUBLEEXC_VECTOR_VADDR
- rsr a5, DEPC
- s32i a5, a3, CS_SA_depc
-# endif
-#endif
-#if XCHAL_HAVE_WINDOWED
- rsr a5, WINDOWBASE
- s32i a5, a3, CS_SA_windowbase // save windowbase
- rsr a5, WINDOWSTART
- s32i a5, a3, CS_SA_windowstart // save windowstart
-#endif
- rsr a5, sar
- s32i a5, a3, CS_SA_sar // save sar
-
-#if XCHAL_HAVE_PSO_CDM
- // Save PWRCTL, and update according to flags argument.
- movi a4, XDM_MISC_PWRCTL
- movi a6, PWRCTL_MEM_WAKEUP
- rer a7, a4 // get pwrctl
- s32i a7, a3, CS_SA_pwrctl // save pwrctl
- // Avoid setting power-control bits if not already set, i.e. clear them only.
- bbci.l a2, XTOS_COREF_PSO_SHIFT, 1f // if not shutting off, don't touch power bits
-
- // Set PWRCTL MEM_WAKEUP bit according to flags (whether to let mem power off).
- or a5, a7, a6 // set...
- xor a5, a5, a6 // ... and clear MEM_WAKEUP bit to write
- and a6, a2, a6 // isolate MEM_WAKEUP bit from flags
- or a5, a5, a6 // set MEM_WAKEUP bit to write from flags
- // Clear PWRCTL DEBUG_WAKEUP bit if cleared in flags (if letting debug power off).
- movi a6, ~PWRCTL_DEBUG_WAKEUP
- or a6, a2, a6 // isolate DEBUG_WAKEUP bit from flags
- and a6, a5, a6 // clear it if was clear in flags
- // Update PWRCTL
- wer a6, a4 // write new pwrctl
- //extw // let the new pwrctl value settle
-1:
-#endif
-
- .macro save_level num
- rsr a5, EPC_2 + \num
- s32i a5, a3, CS_SA_epc + 4*\num
- rsr a5, EPS_2 + \num
- s32i a5, a3, CS_SA_eps + 4*\num
- rsr a5, EXCSAVE_2 + \num
- s32i a5, a3, CS_SA_excsave + 4*\num
- .endm
- iterate 0, XCHAL_NUM_INTLEVELS+XCHAL_HAVE_NMI-2, save_level
-
-#if XCHAL_HAVE_LOOPS
- rsr a5, LBEG
- s32i a5, a3, CS_SA_lbeg
- rsr a5, LEND
- s32i a5, a3, CS_SA_lend
- rsr a5, LCOUNT
- s32i a5, a3, CS_SA_lcount
-#endif
-#if XCHAL_HAVE_ABSOLUTE_LITERALS
- rsr a5, LITBASE
- s32i a5, a3, CS_SA_litbase
-#endif
-#if XCHAL_HAVE_VECBASE
- rsr a5, VECBASE
- s32i a5, a3, CS_SA_vecbase
-#endif
-#if XCHAL_HAVE_S32C1I && (XCHAL_HW_MIN_VERSION >= XTENSA_HWVERSION_RC_2009_0) /* have ATOMCTL ? */
- rsr a5, ATOMCTL
- s32i a5, a3, CS_SA_atomctl
-#endif
-#if XCHAL_HAVE_PREFETCH
- movi a5, 0 // disable prefetch during shutoff
- xsr a5, PREFCTL
- s32i a5, a3, CS_SA_prefctl
-#endif
-#if XCHAL_USE_MEMCTL
- rsr a5, MEMCTL
- s32i a5, a3, CS_SA_memctl
-#endif
-#if XCHAL_HAVE_INTERRUPTS
- rsr a5, INTENABLE
- s32i a5, a3, CS_SA_intenable
-#endif
-#if XCHAL_HAVE_DEBUG
- // NOTE: restore of debug state is conditional,
- // as the power-down and wakeup code might be actively debugged.
- rsr a5, ICOUNT
- s32i a5, a3, CS_SA_icount
- rsr a5, ICOUNTLEVEL
- s32i a5, a3, CS_SA_icountlevel
- rsr a5, DEBUGCAUSE
- s32i a5, a3, CS_SA_debugcause // (won't get restored?)
- //rsr a5, DDR
- //s32i a5, a3, CS_SA_ddr
-# if XCHAL_NUM_IBREAK
- rsr a5, IBREAKENABLE
- s32i a5, a3, CS_SA_ibreakenable
-# endif
- .macro save_ibreak num
- rsr a5, IBREAKA + \num
- s32i a5, a3, CS_SA_ibreaka + 4*\num
- .endm
- iterate 0, XCHAL_NUM_IBREAK-1, save_ibreak
- .macro save_dbreak num
- rsr a5, DBREAKC + \num
- s32i a5, a3, CS_SA_dbreakc + 4*\num
- rsr a5, DBREAKA + \num
- s32i a5, a3, CS_SA_dbreaka + 4*\num
- .endm
- iterate 0, XCHAL_NUM_DBREAK-1, save_dbreak
-#endif
- .macro save_misc num
- rsr a5, MISC_REG_0 + \num
- s32i a5, a3, CS_SA_misc + 4*\num
- .endm
- iterate 0, XCHAL_NUM_MISC_REGS-1, save_misc
-#if XCHAL_HAVE_MEM_ECC_PARITY
- rsr a5, MEPC
- s32i a5, a3, CS_SA_mepc
- rsr a5, MEPS
- s32i a5, a3, CS_SA_meps
- rsr a5, MESAVE
- s32i a5, a3, CS_SA_mesave
- rsr a5, MESR
- s32i a5, a3, CS_SA_mesr
- rsr a5, MECR
- s32i a5, a3, CS_SA_mecr
- rsr a5, MEVADDR
- s32i a5, a3, CS_SA_mevaddr
-#endif
-
- /* TIE state */
- addi a4, a3, CS_SA_ncp
- xchal_ncp_store a4, a5,a6,a7,a8 // save non-coprocessor state
-#if XCHAL_HAVE_CP
- rsr a5, CPENABLE
- s32i a5, a3, CS_SA_cpenable
- movi a6, -1
- wsr a6, CPENABLE // enable all coprocessors
- rsync
- xchal_cp0_store a4, a5,a6,a7,a8 continue=1
- xchal_cp1_store a4, a5,a6,a7,a8 continue=1
- xchal_cp2_store a4, a5,a6,a7,a8 continue=1
- xchal_cp3_store a4, a5,a6,a7,a8 continue=1
- xchal_cp4_store a4, a5,a6,a7,a8 continue=1
- xchal_cp5_store a4, a5,a6,a7,a8 continue=1
- xchal_cp6_store a4, a5,a6,a7,a8 continue=1
- xchal_cp7_store a4, a5,a6,a7,a8 continue=1
- //xchal_cp8_store a4, a5,a6,a7,a8 continue=1
- //xchal_cp9_store a4, a5,a6,a7,a8 continue=1
- //xchal_cp10_store a4, a5,a6,a7,a8 continue=1
- //xchal_cp11_store a4, a5,a6,a7,a8 continue=1
- //xchal_cp12_store a4, a5,a6,a7,a8 continue=1
- //xchal_cp13_store a4, a5,a6,a7,a8 continue=1
- //xchal_cp14_store a4, a5,a6,a7,a8 continue=1
- //xchal_cp15_store a4, a5,a6,a7,a8 continue=1
-#endif
-
- /* TLB state (for known MMU types only, not internal custom) */
-#if XCHAL_HAVE_MIMIC_CACHEATTR || XCHAL_HAVE_XLT_CACHEATTR
- addi a4, a3, CS_SA_tlbs // where to start storing TLB entry info
- movi a5, 0x20000000
- movi a6, 0
-1: rdtlb1 a7, a6 // read DTLB entry PPN + CA
- s32i a7, a4, 0
- ritlb1 a7, a6 // read ITLB entry PPN + CA
- s32i a7, a4, 4
- addi a4, a4, 8
- add a6, a6, a5
- bnez a6, 1b
-
-#elif XCHAL_HAVE_PTP_MMU
- // Declare a table of TLB entries to save/restore.
- // Each entry is a 32-bit index to use directly with [rw][di]tlb[01].
- // Indices assume ITLBCFG == DTLBCFG == 0.
- // Bit 4 means not-for-dtlb, and bit 5 means not-for-itlb
- // (these bits aren't used by these instructions, so okay to use for this).
- .section .rodata, "a"
- .global _xtos_pso_tlbmap
- .global _xtos_pso_tlbmap_end
- .type _xtos_pso_tlbmap, @object
-_xtos_pso_tlbmap:
- .long 0x0C0C0C0C, ARF_ENTRIES // *TLB way 0, 4/8 entries of 4KB
- .long 0x0C0C0C0C, ARF_ENTRIES // *TLB way 1, 4/8 entries of 4KB
- .long 0x0C0C0C0C, ARF_ENTRIES // *TLB way 2, 4/8 entries of 4KB
- .long 0x0C0C0C0C, ARF_ENTRIES // *TLB way 3, 4/8 entries of 4KB
- .long 0x1A181614, 4 // *TLB way 4, 4 entries of 1MB/4MB/16MB/64MB
-# if XCHAL_HAVE_SPANNING_WAY /* MMU v3 */
- .long 0x1C1B1C1B, 4 // *TLB way 5, 4 entries of 128MB/256MB
- .long 0x1B1D1B1D, 8 // *TLB way 6, 8 entries of 512MB/128MB
-# endif
- .long 0x0C0C0C0C, 0x8001 // DTLB way 7, 1 entry of 4KB
- .long 0x0C0C0C0C, 0x8001 // DTLB way 8, 1 entry of 4KB
- .long 0x0C0C0C0C, 0x8001 // DTLB way 9, 1 entry of 4KB
-_xtos_pso_tlbmap_end:
- .size _xtos_pso_tlbmap, . - _xtos_pso_tlbmap
-
- .text
- addi a4, a3, CS_SA_tlbs // where to start storing TLB entry info
- movi a10, _xtos_pso_tlbmap
- movi a11, _xtos_pso_tlbmap_end
- rsr a14, dtlbcfg // page size index (0..3) for each DTLB way
- rsr a15, itlbcfg // page size index (0..3) for each ITLB way
- s32i a14, a3, CS_SA_dtlbcfg
- s32i a15, a3, CS_SA_itlbcfg
- rsr a5, ptevaddr
- s32i a5, a3, CS_SA_ptevaddr
- rsr a5, rasid
- s32i a5, a3, CS_SA_rasid
- // Loop from last way to first (less register pressure that way).
-.Loop_tlbmap:
- addi a11, a11, -8 // next way
- l32i a8, a11, 0 // map of four (page size log2) per index for this way
- // DTLB page size:
- extui a12, a14, 0, 4 // page size index for this DTLB way
- srli a14, a14, 4 // (for next way)
- ssa8l a12 // prepare to shift right by 8*a12
- srl a12, a8 // page size log2 for this DTLB way
- ssl a12 // prepare to shift left by a12
- movi a12, 1 // (to compute 1 << (page size log2))
- sll a12, a12 // page size for this DTLB way
-
- // Save all entries of this DTLB way:
- l32i a9, a11, 4 // number of entries for this way
- sub a5, a11, a10 // way number * 8
- srli a5, a5, 3 // way number
- extui a9, a9, 0, 8
-1: rdtlb0 a6, a5 // read DTLB entry VPN + ASID ...
- rdtlb1 a7, a5 // read DTLB entry PPN + CA ...
- add a5, a5, a12 // next entry of this DTLB way
- s32i a6, a4, 0 // save entry ...
- s32i a7, a4, 4
- addi a4, a4, 8
- addi a9, a9, -1
- bnez a9, 1b
-
- // ITLB page size:
- extui a12, a15, 0, 4 // page size index for this ITLB way
- srli a15, a15, 4 // (for next way)
- ssa8l a12 // prepare to shift right by 8*a12
- srl a12, a8 // page size log2 for this ITLB way
- ssl a12 // prepare to shift left by a12
- movi a12, 1 // (to compute 1 << (page size log2))
- sll a12, a12 // page size for this ITLB way
-
- // Save all entries of this ITLB way:
- l32i a9, a11, 4 // number of entries for this way
- sub a5, a11, a10 // way number * 8
- srli a5, a5, 3 // way number
- bbsi.l a9, 15, 2f // skip ITLB if is a DTLB-only way
- extui a9, a9, 0, 8
-1: ritlb0 a6, a5 // read ITLB entry VPN + ASID ...
- ritlb1 a7, a5 // read ITLB entry PPN + CA ...
- add a5, a5, a12 // next entry of this ITLB way
- s32i a6, a4, 0 // save entry ...
- s32i a7, a4, 4
- addi a4, a4, 8
- addi a9, a9, -1
- bnez a9, 1b
-2:
- bne a11, a10, .Loop_tlbmap // loop for next TLB way
- // Done saving TLBs.
-#endif
-
- // With data cache coherency enabled, need a full data cache
- // writeback and invalidate, then disable coherency, before shut-off.
- // Otherwise, if we'll let dcache power off, writeback its contents.
- //
- // We make sure the signature only gets written after everything
- // else is written back (if we writeback), and only gets written
- // back if the rest gets written back.
- movi a6, CORE_STATE_SIGNATURE
-#if XCHAL_DCACHE_IS_WRITEBACK
-# if XCHAL_HAVE_PSO_CDM && XCHAL_DCACHE_IS_COHERENT && XCHAL_HW_MIN_VERSION >= XTENSA_HWVERSION_RE_2012_0
- rsr a4, MEMCTL
- bbci.l a2, XTOS_COREF_PSO_SHIFT, 1f // if not shutting off, leave snoops as is
- bbci.l a4, MEMCTL_SNOOP_EN_SHIFT, 1f // snoops (coherence) enabled?
- dcache_writeback_inv_all a4, a5, 0 // yes: writeback-invalidate
- memw // wait for writeback to complete
- s32i a6, a3, CS_SA_signature
- dhwbi a3, CS_SA_signature
- // Now that dcache is empty, make sure snoops are off during shut-off.
- addi a4, a4, -MEMCTL_SNOOP_EN
- wsr a4, MEMCTL
- j 9f
-1:
-# endif
- bbsi.l a2, PWRCTL_MEM_WAKEUP_SHIFT, 7f // letting caches power off?
- dcache_writeback_all a4, a5, 0 // yes: writeback
- memw // wait for writeback to complete
- j 8f
-
- // The signature and the cache/TLB state must be written out to
- // main memory even though the caches stay on, because on restart
- // we will come up with caches bypassed and need to read the state
- // back before the cache/TLB is set up.
-7:
- mov a4, a3
- movi a5, CS_SA_ncp
- dcache_writeback_region a4, a5, a7
- memw
-8:
- s32i a6, a3, CS_SA_signature
- dhwb a3, CS_SA_signature // needed even if caches stay on
-#else
- s32i a6, a3, CS_SA_signature
-#endif
-
-9: l32i a4, a3, CS_SA_areg + 4*4 // restore a4 (code to jump to after saving)
- memw // wait for signature to be in memory
-
- beqz a4, 1f // code to jump to?
- jx a4 // yes, jump to it
-1: l32i a0, a3, CS_SA_restore_label // no, return: restore return PC
- movi a2, 0 // return 0
- ret
-
-
- .size _xtos_core_save, . - _xtos_core_save
-
diff --git a/src/arch/xtensa/up/xtos/core-shutoff.S b/src/arch/xtensa/up/xtos/core-shutoff.S
deleted file mode 100644
index fed3c02..0000000
--- a/src/arch/xtensa/up/xtos/core-shutoff.S
+++ /dev/null
@@ -1,427 +0,0 @@
-// reset-pso.S -- PSO restore routine, invoked from Reset Vector
-// $Id: //depot/rel/Eaglenest/Xtensa/OS/xtos/core-shutoff.S#1 $
-
-// Copyright (c) 2012-2013 Tensilica Inc.
-//
-// Permission is hereby granted, free of charge, to any person obtaining
-// a copy of this software and associated documentation files (the
-// "Software"), to deal in the Software without restriction, including
-// without limitation the rights to use, copy, modify, merge, publish,
-// distribute, sublicense, and/or sell copies of the Software, and to
-// permit persons to whom the Software is furnished to do so, subject to
-// the following conditions:
-//
-// The above copyright notice and this permission notice shall be included
-// in all copies or substantial portions of the Software.
-//
-// THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
-// EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
-// MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
-// IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY
-// CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
-// TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
-// SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
-
-#include <xtensa/coreasm.h>
-#include <xtensa/corebits.h>
-#include <xtensa/specreg.h>
-#include <xtensa/cacheasm.h>
-#include <xtensa/cacheattrasm.h>
-#include <xtensa/xdm-regs.h>
-#include <xtensa/config/specreg.h>
-#include <xtensa/xtruntime-core-state.h>
-#include "xtos-internal.h"
-
-#if XCHAL_HAVE_PSO
- .macro simulate_reset
- // Single or multiple power domains, no retention.
- // Just simulate reset. Set PS:
- movi a5, 0x1F
- wsr a5, PS
- rsync
- // Scramble things:
- rotw 3
- // Jump to reset vector:
- movi a5, _ResetVector
- jx a5
- .endm
-#endif
-
-
-#if XCHAL_HAVE_PSO_CDM && ! XCHAL_HAVE_PSO_FULL_RETENTION
- // PSO: core state save area.
- // This could be pretty large (includes TIE state, TLB state, many regs).
- //
- .section .bss, "aw"
- .align XCHAL_TOTAL_SA_ALIGN
- .global _xtos_pso_savearea
- .type _xtos_pso_savearea, @object
- .size _xtos_pso_savearea, XtosCoreStateSize
-_xtos_pso_savearea:
- .space XtosCoreStateSize
-#endif
-
-
- .text
-
-
- // This version of the _xtos_core_shutoff() function can be called from assembly-level,
- // where the stack might not be defined/usable, so can't do window-spill
- // etc. This saves address registers per call0 ABI (all except a0/a2..a11).
- //
- // On entry: a0 = return PC, a2 = flags argument, a3..a11 = undefined/available.
- // All other registers are saved/restored.
- //
- .align 4
- .global _xtos_core_shutoff_nw
- .type _xtos_core_shutoff_nw,@function
-_xtos_core_shutoff_nw:
-#if XCHAL_HAVE_PSO_CDM && ! XCHAL_HAVE_PSO_FULL_RETENTION
- movi a5, _xtos_core_save_nw
-#endif
- mov a11, a0 // ABI-independent return PC
- j .Lcommon_shutoff
- .size _xtos_core_shutoff_nw, . - _xtos_core_shutoff_nw
-
-
-
- // int _xtos_core_shutoff(unsigned flags)
- //
- // Save all processor state and shut-off the core.
- // Returns when the core wakes up, and all state was restored
- // (except in single power domain case, see below).
- //
- // For more details see: System SW Ref Manual, XTOS Chapter.
- //
- // Possible return values:
- //
- // 0 core did shut-off (return via reset vector,
- // or after waiti for full-retention case)
- //
- // 1,2 core did not shut-off (other requestors were already
- // requesting this core to stay on at time of call)
- // (1 == early, 2 == late)
- //
- // 3 core did not shut-off (multi-power-domains no retention,
- // and waiti resumed; FIXME: can this happen?)
- //
- // -1 core does not have PSO feature
- //
- // NOTE: in the single power domain case, this function never returns.
- // The external system must power the core off than back on,
- // and execution resumes at the reset vector.
- //
- // The flags parameter indicates whether to request memory and/or debug domains
- // to stay powered on while the core is shut-off. (This parameter is ignored
- // for the single power domain case.) If 0, they are both allowed to
- // shut-off (although other external requesters may keep them powered on).
- // Otherwise, one or both of these bits may be specified (or'ed together):
- // XTOS_KEEPON_MEM force memory domain on during core power shut-off
- // XTOS_KEEPON_DEBUG force debug domain on during core power shut-off
- // If XTOS_KEEPON_MEM is specified, dcache writeback is NOT done.
- //
- // Effectively, the flags parameter sets the value of these two PWRCTL register
- // bits (over ERI) during core power shut-off. The value of these two bits
- // (as they were prior to calling this function) are saved, and restored on wakeup.
- // Thus, if the core was requesting that the debug domain be powered on, and
- // _xtos_core_shutoff() lets it power-off, then upon wakeup, the software restore
- // sequence restores debug domain power, and waits for debug power to be ON.
- //
- //
- .align 4
- .global _xtos_core_shutoff
- .type _xtos_core_shutoff,@function
-_xtos_core_shutoff:
- abi_entry
-
-#if XCHAL_HAVE_PSO_CDM && ! XCHAL_HAVE_PSO_FULL_RETENTION
- movi a5, _xtos_core_save_entry
-#endif
- movi a11, 1f // ABI-independent return PC
- j .Lcommon_shutoff
-
-1: abi_return
-
-
-
-
- .align 4
-.Lcommon_shutoff:
-
-
-
-#if XCHAL_HAVE_PSO_CDM && XCHAL_HAVE_PSO_FULL_RETENTION
- // Multiple power domains, full retention in HW.
- // Do the minimum required (things that need to be changed during shutoff):
-
- // Check whether other agents are keeping this core powered on,
- // and avoid going through save sequence if we're not going to
- // power down anyway.
- movi a3, XDM_MISC_PWRSTAT
- rer a6, a3
- movi a5, 1 // indicates other agents want this core powered on
- bbsi.l a6, PWRSTAT_CORE_STILL_NEEDED_SHIFT, 1f
-
- rsil a8, 15 // disable interrupts
-
-# if XCHAL_HAVE_PREFETCH
- // Save prefetch control and disable prefetch.
- movi a10, 0
- xsr a10, PREFCTL
-# endif
-
-# if XCHAL_DCACHE_IS_WRITEBACK
- bbsi.l a2, PWRCTL_MEM_WAKEUP_SHIFT, 7f // letting caches power off?
- dcache_writeback_all a4, a7, 0 // yes: writeback
- memw // wait for writeback to complete
-7:
-# endif
-
- // Save PWRCTL, and set ShutProcOffOnPWait (for WAITI to shut-off the core).
- // (With dcache coherence, can this be used as signal to system
- // to turn off snoops to this core?)
- //
- movi a4, XDM_MISC_PWRCTL
- rer a9, a4 // get pwrctl
- movi a6, PWRCTL_CORE_SHUTOFF // aka ShutProcOffOnPWait
- or a7, a9, a6 // indicate WAITI will shut-off
- xor a9, a7, a6 // make sure it's clear in saved pwrctl
- wer a7, a4 // write new pwrctl
-
- // Make sure everything stabilizes:
- isync
- extw
-
- // With ShutProcOffOnPWait set, external agents can't change their mind.
- // So check again whether other agents are keeping this core powered on,
- // and avoid going through save sequence if we're not going to
- // power down anyway.
- rer a6, a3 // read PWRSTAT
- movi a5, 2 // if abort: external agent wants core powered on
- bbsi.l a6, PWRSTAT_CORE_STILL_NEEDED_SHIFT, .Lshutoff_late_abort
-
- // Set PWRCTL MEM_WAKEUP bit according to flags (whether to let mem power off).
- movi a6, PWRCTL_MEM_WAKEUP
- or a5, a7, a6 // set...
- xor a5, a5, a6 // ... and clear MEM_WAKEUP bit to write
- and a6, a2, a6 // isolate MEM_WAKEUP bit from flags
- or a5, a5, a6 // set MEM_WAKEUP bit to write from flags
- // Clear PWRCTL DEBUG_WAKEUP bit if cleared in flags (if letting debug power off).
- movi a6, ~PWRCTL_DEBUG_WAKEUP
- or a6, a2, a6 // isolate DEBUG_WAKEUP bit from flags
- and a6, a5, a6 // clear it if was clear in flags
- // Update PWRCTL
- wer a6, a4 // write new pwrctl
- extw // let the new pwrctl value settle
-
- // Okay, go for it -- power down (shutoff).
-
-# if !XTOS_PSO_TEST
- waiti 0 // now shut-off! (interrupts enabled for power-on)
-# endif
- // Resumes here after power comes back on, after some interrupt taken.
- wsr.ps a8 // restore interrupts
- movi a5, 0 // successful
- rsync // ensure wsr.ps completes
-
- // FIXME: do we need to initialize caches?
-
-.Lshutoff_late_abort:
- wer a7, a4 // restore pwrctl (except ShutProcOffOnPWait still set)
-
- // Wait for debug powerup to complete (if started):
- bbci.l a7, PWRCTL_DEBUG_WAKEUP_SHIFT, 3f
- movi a6, XDM_MISC_PWRSTAT
-2: rer a6, a6 // read PWRSTAT
- bbci.l a6, PWRSTAT_DEBUG_DOMAIN_ON_SHIFT, 2b // loop until powered up
-3:
-
-# if XCHAL_HAVE_PREFETCH
- wsr a10, PREFCTL // restore prefetch control
-# endif
-
- // If CachesLostPower bit set, is there need to initialize caches?
-
- wer a9, a4 // clear ShutProcOffOnPWait
-
- wsr.ps a8 // restore interrupts
- rsync // ensure wsr.ps completes
-
-1: mov a2, a5
- jx a11 // return (to ABI-dependent code if C callable)
-
-
-
-#elif XCHAL_HAVE_PSO_CDM /*&& !XCHAL_HAVE_PSO_FULL_RETENTION*/
- // Multiple power domains, no hardware retention.
- // Do full core state save/restore in software.
-
- // Check whether other agents are keeping this core powered on,
- // and avoid going through save sequence if we're not going to
- // power down anyway.
- movi a3, XDM_MISC_PWRSTAT
- rer a3, a3
- bbsi.l a3, PWRSTAT_CORE_STILL_NEEDED_SHIFT, 1f
-
- movi a3, XTOS_COREF_PSO
- or a2, a2, a3 // indicate power shutoff in flags
-
- movi a3, _xtos_pso_savearea
- movi a4, _xtos_core_shutoff_aftersave
- jx a5 // continue in _xtos_core_save (past prologue)
- // which saves processor state, powers down
- // debug/mem per a2, shuts off prefetch and
- // snooping, and jumps to a4
-
-1: movi a2, 1 // other agents want this core powered on
- jx a11 // return (to ABI-dependent code if C callable)
-
- .align 4
- //.global _xtos_core_shutoff_aftersave
-_xtos_core_shutoff_aftersave:
-
- // Multiple power domains, no retention.
-
- // Set ShutProcOffOnPWait, for WAITI to shut-off the core.
- // (With dcache coherence, can this be used as signal to system
- // to turn off snoops to this core?)
- //
- movi a4, XDM_MISC_PWRCTL
- rer a7, a4 // get pwrctl
- movi a6, PWRCTL_CORE_SHUTOFF // aka ShutProcOffOnPWait
- or a7, a7, a6 // indicate WAITI will shut-off
- wer a7, a4 // write new pwrctl
-
- // Make sure everything stabilizes:
- isync
- extw
-
- // Check whether other agents are keeping this core powered on,
- // and avoid going through save sequence if we're not going to
- // power down anyway.
- movi a4, XDM_MISC_PWRSTAT
- movi a2, 2 // if abort: external agent wants core powered on
- rer a6, a4
- bbsi.l a6, PWRSTAT_CORE_STILL_NEEDED_SHIFT, .Lshutoff_late_abort
-
- // Call system-specific function to wait for system specific
- // transactions to quiesce before shutting down the processor.
- // This function may also abort the shutdown, however whoever
- // attempts it must do it carefully: the function must know
- // that it's possible to abort, it must do whatever's needed
- // in the system to resume normal execution (e.g. restart
- // snoops, DMA, etc), and for power reasons the software must
- // avoid calling this shutdown routine in the first place if
- // it can know then that it would end up aborting here.
- //
- // This is always a call0 function.
- // TBD: can it be a C function instead?
- // TBD: describe exact calling conventions, if asm call0
-
- .weak xtos_system_ready_for_core_shutoff
- movi a2, xtos_system_ready_for_core_shutoff
- //isync
- beqz a2, 1f
- callx0 a2
- bnez a2, .Lshutoff_late_abort // if function returns error, abort shutdown
-1:
-
- // Okay, go for it -- power down (shutoff).
-
-
-# if XTOS_PSO_TEST
- // Test only -- weakly simulate shutoff in sw, don't actually do it.
- simulate_reset
-# elif XCHAL_HAVE_INTERRUPTS
- waiti 15 // now shut-off!
-# elif XCHAL_HAVE_HALT
- halt
-# else
-# error "PSO assumes interrupts (for WAITI) or HALT architecture (for HALT)"
-# endif
-
- // Execution should not proceed here.
- // If we get here, some error has occurred [FIXME]
-
- movi a2, 3 // WAITI resumed
-
-.Lshutoff_late_abort:
- // We end up here if returning from shutoff request.
- // Here, a2 == return code.
- // Restore what's been clobbered (and doesn't get restored by caller):
- // PWRCTL, MEMCTL, return PC.
-
- l32i a0, a3, CS_SA_restore_label // restore return PC
-
- // Restore PWRCTL.
- movi a4, XDM_MISC_PWRCTL
- l32i a5, a3, CS_SA_pwrctl // get saved pwrctl
- wer a5, a4 // restore pwrctl
- // Wait for debug powerup to complete (if started):
- bbci.l a5, PWRCTL_DEBUG_WAKEUP_SHIFT, 1f
- movi a7, XDM_MISC_PWRSTAT
-2: rer a6, a7 // read PWRSTAT
- bbci.l a6, PWRSTAT_DEBUG_DOMAIN_ON_SHIFT, 2b // loop until powered up
-1:
-
- // Restore MEMCTL.
-# if XCHAL_USE_MEMCTL
- l32i a5, a3, CS_SA_memctl
- wsr a5, MEMCTL
-# endif
-
- // Clear the signature, to mark save area as no longer valid.
- s32i a2, a3, CS_SA_signature
-# if XCHAL_DCACHE_IS_WRITEBACK
- dhwb a3, CS_SA_signature
-# endif
-
- ret // return from _xtos_core_save_common
-
-
-
-#elif XCHAL_HAVE_PSO
- // Single power domain. (No retention.)
-
- rsil a8, 15 // disable interrupts
-
-# if XCHAL_HAVE_PREFETCH
- // Disable prefetch.
- movi a10, 0
- wsr a10, PREFCTL
-# endif
-
-# if XCHAL_DCACHE_IS_WRITEBACK
- bbsi.l a2, PWRCTL_MEM_WAKEUP_SHIFT, 7f // letting caches power off?
- dcache_writeback_all a4, a5, 0 // yes: writeback
- memw // wait for writeback to complete
-7:
-# endif
-
-1: waiti 15 // wait for shut-off
- j 1b // loop until we get powered off
-
-
-
-#else
- // No PSO.
- movi a2, -1
- jx a11 // return (to ABI-dependent code if C callable)
-
-#endif
-
-
-
-
-#if XCHAL_HAVE_PSO_CDM
-# if XCHAL_HAVE_PSO_FULL_RETENTION
-
-# else /* not full retention */
-
-
-# endif /* !retention */
-#endif /* multi power domains */
-
-
- .size _xtos_core_shutoff, . - _xtos_core_shutoff
-
diff --git a/src/arch/xtensa/up/xtos/crt0-app.S b/src/arch/xtensa/up/xtos/crt0-app.S
deleted file mode 100644
index 56701d4..0000000
--- a/src/arch/xtensa/up/xtos/crt0-app.S
+++ /dev/null
@@ -1,174 +0,0 @@
-// crt0-app.S
-// Applications downloaded in RAM using a debug monitor (eg. XMON, RedBoot)
-// start here at _app_reset. Such applications don't have any vectors:
-// all exceptions are handled by the debug monitor.
-// Thus, this file essentially plays the role of the reset vector
-// to setup a few things before jumping to _start (in crt1*.S).
-
-// Copyright (c) 2005-2013 Tensilica Inc.
-//
-// Permission is hereby granted, free of charge, to any person obtaining
-// a copy of this software and associated documentation files (the
-// "Software"), to deal in the Software without restriction, including
-// without limitation the rights to use, copy, modify, merge, publish,
-// distribute, sublicense, and/or sell copies of the Software, and to
-// permit persons to whom the Software is furnished to do so, subject to
-// the following conditions:
-//
-// The above copyright notice and this permission notice shall be included
-// in all copies or substantial portions of the Software.
-//
-// THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
-// EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
-// MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
-// IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY
-// CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
-// TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
-// SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
-
-#include <xtensa/cacheattrasm.h>
-#include <xtensa/coreasm.h>
-
-
-// Assumptions on entry to _app_reset:
-// - debug monitor handles all exceptions, has setup all vectors
-// - interrupt related state is initialized
-// (interrupts disabled or enabled for debug monitor's purposes)
-// - debug option related state is initialized (for debug monitor)
-// - any MMU related state is initialized (all handled by debug monitor)
-// - caches are initialized (cache attributes not necessarily correct)
-// - entire application is loaded (no unpacking needed here)
-
-// Assumptions on exit from _app_reset, ie. when jumping to _start:
-// - low (level-one) and medium priority interrupts are disabled
-// - C calling context not initialized:
-// - PS not fully initialized (eg. PS.WOE not set per ABI)
-// - SP not initialized
-// - the following are initialized:
-// - LITBASE, WindowBase, WindowStart, LCOUNT, CPENABLE, FP's FCR and FSR,
-// cache attributes
-
-/**************************************************************************/
-
- .text
- .global _app_reset
-_app_reset:
- /* _app_reset may be required to be located at the beginning of the text
- segment. However, the constant pool for _app_reset must be placed
- before the code. Jump over the constant pool to solve this. */
- j .LpastInitialConstants
-
- .literal_position // tells the assembler/linker to place literals here
-
-.LpastInitialConstants:
- // Keep a0 zero. It is used to initialize a few things.
- // It is also the return address, where zero indicates
- // that the frame used by _start is the bottommost frame.
- //
- movi a0, 0 // keep this register zero.
-
-#if XCHAL_HAVE_LOOPS
- wsr a0, LCOUNT // loop count = 0
-#endif /* XCHAL_HAVE_LOOPS */
-
- // Interrupts might be enabled, make sure at least medium and low priority
- // interrupts are disabled until WindowBase, WindowStart, SP, and the stack
- // are all properly setup (which will happen outside this file, after the
- // _start label). We leave loops enabled on new exception architecture.
-#if XCHAL_HAVE_EXCEPTIONS
- movi a2, XCHAL_EXCM_LEVEL
- wsr a2, PS // set PS.INTLEVEL=EXCM_LEVEL, PS.WOE=0, PS.EXCM=0
- rsync
-#endif
-
- // DO THIS FIRST: initialize the window start and base
- // before, so that windows don't move under us.
-#if XCHAL_HAVE_WINDOWED
- // We do this even if we are assembling for the
- // call0 abi, but it's not really needed.
- movi a2, 1
- wsr a2, WINDOWSTART // window start = 1
- wsr a0, WINDOWBASE // window base = 0
- rsync
-
- // NOTE: a0 may no longer be zero here, because
- // we wrote to WindowBase. So clear it again.
- movi a0, 0
-#endif
-
- // Now, BEFORE we do any L32R (or MOVI with non-immediate
- // range which results in an L32R), ensure LITBASE is set
- // correctly. This is necessary for RAM applications loaded
- // using a target-side debug monitor -- such applications
- // don't have a reset vector and start execution at _start.
- // (This part is unnecessary if running from a reset vector.)
- // The target-side debug monitor might have set LITBASE to
- // anything at all, so we cannot rely on its value here.
-#if XCHAL_HAVE_ABSOLUTE_LITERALS
- wsr a0, LITBASE // force PC-relative L32R
- rsync
-# if XSHAL_USE_ABSOLUTE_LITERALS
- .begin no-absolute-literals // use PC-rel L32R to load
- movi a2, _lit4_start + 0x40001 // address of absolute literals
- .end no-absolute-literals // (see handlers/ResetVector.S
- wsr a2, LITBASE // for explanation)
- rsync
-# endif
-#endif
-
-
- /*
- * Now "enable" the caches.
- *
- * NOTE: We don't *initialize* the caches here, because the loader
- * (eg. target debugger agent / debug monitor, boot code, etc)
- * is expected to have initialized them for us.
- *
- * The _memmap_cacheattr_reset symbol's value (address) is defined
- * by the LSP's linker script, as generated by xt-genldscripts.
- *
- * (NOTE: for configs that don't have CACHEATTR or region protection,
- * ie. for full MMUs, there is no equivalent cache attribute layout,
- * and the following code has no effect. We assume for now that the
- * application restricts itself to the static TLB entries, i.e. to
- * virtual addresses 0xD0000000 thru 0xFFFFFFFF.)
- */
-#if XCHAL_HAVE_CACHEATTR || XCHAL_HAVE_MIMIC_CACHEATTR || XCHAL_HAVE_XLT_CACHEATTR \
- || (XCHAL_HAVE_PTP_MMU && XCHAL_HAVE_SPANNING_WAY)
- movi a2, _memmap_cacheattr_reset /* note: absolute symbol, not a ptr */
- cacheattr_set /* set CACHEATTR from a2 (clobbers a3-a8) */
-#endif
-
-
-
- // Coprocessor option initialization
-#if XCHAL_HAVE_CP
- //movi a2, XCHAL_CP_MASK // enable existing CPs
- // To allow creating new coprocessors using TC that are not known
- // at GUI build time without having to explicitly enable them,
- // all CPENABLE bits must be set, even though they may not always
- // correspond to a coprocessor.
- movi a2, 0xFF // enable *all* bits, to allow dynamic TIE
- wsr a2, CPENABLE
-#endif
-
- // Floating point coprocessor option initialization
-#if XCHAL_HAVE_FP
- rsync /* wait for WSR to CPENABLE to complete before accessing FP coproc state */
- wur.FCR a0 /* clear FCR (default rounding mode, round-nearest) */
- wur.FSR a0 /* clear FSR */
-#endif
-
-
- /* NOTE: Future releases may clear BSS here rather than in the CRT1. */
-
-
- /*
- * Now jump to the application. This is typically the
- * C run-time initialization ("CRT") which in turn calls main():
- */
- movi a4, _start
- jx a4 // jump to _start
-
- .size _app_reset, . - _app_reset
-
diff --git a/src/arch/xtensa/up/xtos/crt1-boards.S b/src/arch/xtensa/up/xtos/crt1-boards.S
deleted file mode 100644
index a66fe84..0000000
--- a/src/arch/xtensa/up/xtos/crt1-boards.S
+++ /dev/null
@@ -1,313 +0,0 @@
-// crt1-boards.S
-//
-// For most hardware / boards, this code sets up the C calling context
-// (setting up stack, PS, and clearing BSS) and jumps to __clibrary_start
-// which sets up the C library, calls constructors and registers destructors,
-// and calls main().
-//
-// Control arrives here at _start from the reset vector or from crt0-app.S.
-
-// Copyright (c) 1998-2010 Tensilica Inc.
-//
-// Permission is hereby granted, free of charge, to any person obtaining
-// a copy of this software and associated documentation files (the
-// "Software"), to deal in the Software without restriction, including
-// without limitation the rights to use, copy, modify, merge, publish,
-// distribute, sublicense, and/or sell copies of the Software, and to
-// permit persons to whom the Software is furnished to do so, subject to
-// the following conditions:
-//
-// The above copyright notice and this permission notice shall be included
-// in all copies or substantial portions of the Software.
-//
-// THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
-// EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
-// MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
-// IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY
-// CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
-// TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
-// SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
-
-#include <xtensa/coreasm.h>
-#include <config.h>
-// DF #include "xtos-internal.h"
-//#include <xtensa/../../src/xtos/xtos-internal.h>
-
-//.global _ResetVector
-#if 0
-/*
- * Reset vector.
- * Only a trampoline to jump to _start
- * (Note that we have to mark the section writable as the section contains
- * a relocatable literal)
- */
-
- .section .ResetVector.text, "awx"
- .global _ResetVector
-_ResetVector:
-
- j 1f
- .align 4
-2: .long _start
-1: l32r a2, 2b
- jx a2
-#endif
-
-// Exports
-.global _start
-
-// Imports
-// __clibrary_init from C library (eg. newlib or uclibc)
-// exit from C library
-// main from user application
-// board_init board-specific (uart/mingloss/tinygloss.c)
-// xthal_dcache_all_writeback from HAL library
-// __stack from linker script (see LSP Ref Manual)
-// _bss_table_start from linker script (see LSP Ref Manual)
-// _bss_table_end from linker script (see LSP Ref Manual)
-
-.type main, @function
-
-// Macros to abstract away ABI differences
-
-#if __XTENSA_CALL0_ABI__
-# define CALL call0
-# define ARG1 a2 /* 1st outgoing call argument */
-# define ARG2 a3 /* 2nd outgoing call argument */
-# define ARG3 a4 /* 3rd outgoing call argument */
-# define ARG4 a5 /* 4th outgoing call argument */
-# define ARG5 a6 /* 5th outgoing call argument */
-#else
-# define CALL call4
-# define CALLX callx4
-# define ARG1 a6 /* 1st outgoing call argument */
-# define ARG2 a7 /* 2nd outgoing call argument */
-# define ARG3 a8 /* 3rd outgoing call argument */
-# define ARG4 a9 /* 4th outgoing call argument */
-# define ARG5 a10 /* 5th outgoing call argument */
-#endif
-
-
-/**************************************************************************/
-
- .text
- .align 4
- .literal_position
-_start:
- // _start is typically NOT at the beginning of the text segment --
- // it is always called from either the reset vector or other code
- // that does equivalent initialization (such as crt0-app.S).
- //
- // Assumptions on entry to _start:
- // - low (level-one) and medium priority interrupts are disabled
- // via PS.INTLEVEL and/or INTENABLE (PS.INTLEVEL is expected to
- // be zeroed, to potentially enable them, before calling main)
- // - C calling context not initialized:
- // - PS not initialized
- // - SP not initialized
- // - the following are initialized:
- // - LITBASE, cache attributes, WindowBase, WindowStart,
- // CPENABLE, FP's FCR and FSR, EXCSAVE[n]
-
- // Keep a0 zero. It is used to initialize a few things.
- // It is also the return address, where zero indicates
- // that the frame used by _start is the bottommost frame.
- //
-
-// not needed for Xtensa TX
-#if !XCHAL_HAVE_HALT || !defined(CONFIG_BOOT_LOADER)
- movi a0, 0 // keep this register zero.
-#endif
-
-#if XTOS_RESET_UNNEEDED && !XCHAL_HAVE_HALT
-#include "reset-unneeded.S"
-#endif
-
-#if defined(CONFIG_BOOT_LOADER)
- .weak _Level2FromVector
- .weak _Level3FromVector
- .weak _Level4FromVector
- .weak _Level5FromVector
-
- movi a4, _Level2FromVector
- wsr a4, EXCSAVE+2
- movi a4, _Level3FromVector
- wsr a4, EXCSAVE+3
- movi a4, _Level4FromVector
- wsr a4, EXCSAVE+4
- movi a4, _Level5FromVector
- wsr a4, EXCSAVE+5
-#endif
-
- // Initialize the stack pointer.
- // See the "ABI and Software Conventions" chapter in the
- // Xtensa ISA Reference manual for details.
-
- // NOTE: Because the _start routine does not use any memory in its
- // stack frame, and because all of its CALL instructions use a
- // window size of 4 (or zero), the stack frame for _start can be empty.
-
- movi sp, __stack
-
- /*
- * Now that sp (a1) is set, we can set PS as per the application
- * (user vector mode, enable interrupts,
- * enable window exceptions if applicable).
- */
-#if XCHAL_HAVE_EXCEPTIONS
-# ifdef __XTENSA_CALL0_ABI__
- // PS.WOE = 0, PS.UM = 1, PS.EXCM = 0, PS.INTLEVEL = 0
- movi a3, PS_UM
-# else
- // PS.WOE = 1, PS.UM = 1, PS.EXCM = 0, PS.INTLEVEL = 0
- movi a3, PS_UM|PS_WOE
-# endif
- wsr a3, PS
- rsync
-#endif
-
-/*
- * Do any initialization that affects the memory map, such as
- * setting up TLB entries, that needs to be done before we can
- * successfully clear BSS (e.g. if some BSS segments are in
- * remapped areas).
- *
- * NOTE: This hook works where the reset vector does not unpack
- * segments (see "ROM packing" in the LSP manual), or where
- * unpacking of segments is not affected by memory remapping.
- * If ROM unpacking is affected, TLB setup must be done in
- * assembler from the reset vector.
- *
- * The __memmap_init() routine can be a C function, however it
- * does not have BSS initialized! In particular, __memmap_init()
- * cannot set BSS variables, i.e. uninitialized global variables
- * (they'll be wiped out by the following BSS clear), nor can it
- * assume they are yet initialized to zero.
- *
- * The __memmap_init() function is optional. It is marked as a
- * weak symbol, so that it gets valued zero if not defined.
- */
-
- .weak __memmap_init
- movi a4, __memmap_init
- beqz a4, 1f
- CALLX a4
-1:
-
-/* boot loader takes care of zeroing BSS */
-#if !defined(CONFIG_BOOT_LOADER)
- /*
- * Clear the BSS (uninitialized data) segments.
- * This code supports multiple zeroed sections (*.bss).
- *
- * Register allocation:
- * a0 = 0
- * a6 = pointer to start of table, and through table
- * a7 = pointer to end of table
- * a8 = start address of bytes to be zeroed
- * a9 = end address of bytes to be zeroed
- * a10 = length of bytes to be zeroed
- */
- movi a0, 0
- movi a6, _bss_table_start
- movi a7, _bss_table_end
- bgeu a6, a7, .L3zte
-
-.L0zte: l32i a8, a6, 0 // get start address, assumed multiple of 4
- l32i a9, a6, 4 // get end address, assumed multiple of 4
- addi a6, a6, 8 // next entry
- sub a10, a9, a8 // a10 = length, assumed a multiple of 4
- bbci.l a10, 2, .L1zte
- s32i a0, a8, 0 // clear 4 bytes to make length multiple of 8
- addi a8, a8, 4
-.L1zte: bbci.l a10, 3, .L2zte
- s32i a0, a8, 0 // clear 8 bytes to make length multiple of 16
- s32i a0, a8, 4
- addi a8, a8, 8
-.L2zte: srli a10, a10, 4 // length is now multiple of 16, divide by 16
- floopnez a10, clearzte
- s32i a0, a8, 0 // clear 16 bytes at a time...
- s32i a0, a8, 4
- s32i a0, a8, 8
- s32i a0, a8, 12
- addi a8, a8, 16
- floopend a10, clearzte
-
- bltu a6, a7, .L0zte // loop until end of table of *.bss sections
-.L3zte:
-#endif
-
-
- // We can now call C code,
- // the C calling environment has been initialized.
- //
- // From this point on, we use ABI-specific macros to refer
- // to registers a0 .. a15
- // (ARG#).
-
-
-#if XCHAL_HAVE_HALT
- // Assume minimalist environment for memory-constrained TX cores.
- // No C library or board initialization, no parameters passed to main
- // (assume declared as "void main(void)") and no call to exit().
-
- CALL main
- halt
-
-#else /* !HALT */
-
- .type board_init, @function
- .type __clibrary_init, @function
- .type exit, @function
-
-
- // Initialize the board (eg. the UART on the XT2000).
- //CALL board_init
-
- /*
- * Call __clibrary_init to initialize the C library:
- *
- * void __clibrary_init(int argc, char ** argv, char ** environ,
- * void(*init_func)(void), void(*fini_func)(void));
- */
-
- // Pass an empty argv array, with an empty string as the program name.
-#if 0
- movi ARG1, _start_argc // argc address
- movi ARG2, _start_argv // argv = ["", 0]
- movi ARG3, _start_envp // envp = [0]
-// movi ARG4, _init // function that calls constructors
-// movi ARG5, _fini // function that calls destructors
- l32i ARG1, ARG1, 0 // argc = 1
- CALL __clibrary_init
-#endif
- // Call: int main(int argc, char ** argv, char ** environ);
- movi ARG1, _start_argc // argc address
- movi ARG2, _start_argv // argv = ["", 0]
- movi ARG3, _start_envp // envp = [0]
- l32i ARG1, ARG1, 0 // argc = 1
- CALL main
- // The return value is the same register
- // as the first outgoing argument.
-// CALL exit // exit with main's return value
- // Does not return here.
-
- .data
- // Mark argc/argv/envp parameters as weak so that an external
- // object file can override them.
- .weak _start_argc, _start_argv, _start_envp
- .align 4
-_start_argv:
- .word _start_null // empty program name
-_start_null:
-_start_envp:
- .word 0 // end of argv array, empty string, empty environ
-_start_argc:
- .word 1 // one argument (program name)
- .text
-
-#endif /* !HALT */
-
- .size _start, . - _start
-
-//#endif
diff --git a/src/arch/xtensa/up/xtos/crt1-sim.S b/src/arch/xtensa/up/xtos/crt1-sim.S
deleted file mode 100644
index 19f7f7d..0000000
--- a/src/arch/xtensa/up/xtos/crt1-sim.S
+++ /dev/null
@@ -1,279 +0,0 @@
-// crt1-sim.S
-// For the Xtensa simulator target, this code sets up the C calling context
-// and calls main() (via __clibrary_start).
-// Control arrives here at _start from the reset vector or from crt0-app.S.
-
-// Copyright (c) 1998-2012 Tensilica Inc.
-//
-// Permission is hereby granted, free of charge, to any person obtaining
-// a copy of this software and associated documentation files (the
-// "Software"), to deal in the Software without restriction, including
-// without limitation the rights to use, copy, modify, merge, publish,
-// distribute, sublicense, and/or sell copies of the Software, and to
-// permit persons to whom the Software is furnished to do so, subject to
-// the following conditions:
-//
-// The above copyright notice and this permission notice shall be included
-// in all copies or substantial portions of the Software.
-//
-// THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
-// EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
-// MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
-// IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY
-// CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
-// TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
-// SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
-
-#include <xtensa/simboard.h>
-#include <xtensa/simcall.h>
-#include <xtensa/coreasm.h>
-#include "xtos-internal.h"
-#include <config.h>
-
-
-// Exports
-.global _start
-
-// Imports
-// __clibrary_init from C library (eg. newlib or uclibc)
-// exit from C library
-// main from user application
-// __stack from linker script (see LSP Ref Manual)
-
-.type __clibrary_init, @function
-.type main, @function
-.type exit, @function
-
-
-// Macros to abstract away ABI differences
-
-#if __XTENSA_CALL0_ABI__
-# define CALL call0
-# define CALLX callx0
-# define ARG1 a2 /* 1st outgoing call argument */
-# define ARG2 a3 /* 2nd outgoing call argument */
-# define ARG3 a4 /* 3rd outgoing call argument */
-# define ARG4 a5 /* 4th outgoing call argument */
-# define ARG5 a6 /* 5th outgoing call argument */
-#else
-# define CALL call4
-# define CALLX callx4
-# define ARG1 a6 /* 1st outgoing call argument */
-# define ARG2 a7 /* 2nd outgoing call argument */
-# define ARG3 a8 /* 3rd outgoing call argument */
-# define ARG4 a9 /* 4th outgoing call argument */
-# define ARG5 a10 /* 5th outgoing call argument */
-#endif
-
- .data
- .weak _start_envp // allow overriding
- .align 4
-_start_envp: .word 0 // empty environ
-
-
-
- .text
- .align 4
-
-_start:
- // _start is typically NOT at the beginning of the text segment --
- // it is always called from either the reset vector or other code
- // that does equivalent initialization (such as crt0-app.S).
- //
- // Assumptions on entry to _start:
- // - low (level-one) and medium priority interrupts are disabled
- // via PS.INTLEVEL and/or INTENABLE (PS.INTLEVEL is expected to
- // be zeroed, to potentially enable them, before calling main)
- // - C calling context not initialized:
- // - PS not initialized
- // - SP not initialized
- // - the following are initialized:
- // - LITBASE, cache attributes, WindowBase, WindowStart,
- // CPENABLE, FP's FCR and FSR, EXCSAVE[n]
-
- // Keep a0 zero. It is used to initialize a few things.
- // It is also the return address, where zero indicates
- // that the frame used by _start is the bottommost frame.
- //
- movi a0, 0 // keep this register zero.
-
-#if XTOS_RESET_UNNEEDED
-#include "reset-unneeded.S"
-#endif
-
-
- // Initialize the stack pointer.
- // See the "ABI and Software Conventions" chapter in the
- // Xtensa ISA Reference manual for details.
-
- // NOTE: Because the _start routine does not use any memory in its
- // stack frame, and because all of its CALL instructions use a
- // window size of 4, the stack frame for _start can be empty.
- movi sp, __stack
-
- // reserve stack space for
- // - argv array
- // - argument strings
- movi a2, SYS_iss_argv_size
- simcall // returns size of argv[] + its strings in a2
-#if XCHAL_HAVE_PIF
- // The stack only needs 16-byte alignment.
- // However, here we round up the argv size further to 128 byte multiples
- // so that in most cases, variations in argv[0]'s path do not result in
- // different stack allocation. Otherwise, such variations can impact
- // execution timing (eg. due to cache effects etc) for the same code and data.
- // If we have a PIF, it's more likely the extra required space is okay.
- addi a2, a2, 127
- srli a2, a2, 7
- slli a2, a2, 7
-#else
- // Keep stack 16-byte aligned.
- addi a2, a2, 15
- srli a2, a2, 4
- slli a2, a2, 4
-#endif
- // No need to use MOVSP because we have no caller (we're the
- // base caller); in fact it's better not to use MOVSP in this
- // context, to avoid unnecessary ALLOCA exceptions and copying
- // from undefined memory:
- // sub a3, sp, a2
- // movsp sp, a3
- sub sp, sp, a2
-
-
- /*
- * Now that sp (a1) is set, we can set PS as per the application
- * (user vector mode, enable interrupts, enable window exceptions if applicable).
- */
-#if XCHAL_HAVE_EXCEPTIONS
-# ifdef __XTENSA_CALL0_ABI__
- movi a3, PS_UM // PS.WOE = 0, PS.UM = 1, PS.EXCM = 0, PS.INTLEVEL = 0
-# else
- movi a3, PS_UM|PS_WOE // PS.WOE = 1, PS.UM = 1, PS.EXCM = 0, PS.INTLEVEL = 0
-# endif
- wsr a3, PS
- rsync
-#endif
-
-
- /*
- * Do any initialization that affects the memory map, such as
- * setting up TLB entries, that needs to be done before we can
- * successfully clear BSS (e.g. if some BSS segments are in
- * remapped areas).
- *
- * NOTE: This hook works where the reset vector does not unpack
- * segments (see "ROM packing" in the LSP manual), or where
- * unpacking of segments is not affected by memory remapping.
- * If ROM unpacking is affected, TLB setup must be done in
- * assembler from the reset vector.
- *
- * The __memmap_init() routine can be a C function, however it
- * does not have BSS initialized! In particular, __memmap_init()
- * cannot set BSS variables, i.e. uninitialized global variables
- * (they'll be wiped out by the following BSS clear), nor can it
- * assume they are yet initialized to zero.
- *
- * The __memmap_init() function is optional. It is marked as a
- * weak symbol, so that it gets valued zero if not defined.
- */
- .weak __memmap_init
- movi a4, __memmap_init
- beqz a4, 1f
- CALLX a4
-1:
-
-
- /* The new ISS simcall only appeared after RB-2007.2: */
-#if !defined(CONFIG_BOOT_LOADER) &&
- /* pre-LX2 cores only */
- (XCHAL_HW_MAX_VERSION > XTENSA_HWVERSION_RB_2007_2)
- /*
- * Clear the BSS (uninitialized data) segments.
- * This code supports multiple zeroed sections (*.bss).
- * For speed, we clear memory using an ISS simcall
- * (see crt1-boards.S for more generic BSS clearing code).
- */
- movi a6, _bss_table_start
- movi a7, _bss_table_end
- bgeu a6, a7, .Lnobss
-.Lbssloop:
- movi a2, SYS_memset
- l32i a3, a6, 0 // arg1 = fill start address
- movi a4, 0 // arg2 = fill pattern
- l32i a5, a6, 4 // get end address
- addi a6, a6, 8 // next bss table entry
- sub a5, a5, a3 // arg3 = fill size in bytes
- simcall // memset(a3,a4,a5)
- bltu a6, a7, .Lbssloop // loop until end of bss table
-.Lnobss:
-#endif
-
-
- /*
- * Call __clibrary_init to initialize the C library:
- *
- * void __clibrary_init(int argc, char ** argv, char ** environ,
- * void(*init_func)(void), void(*fini_func)(void));
- */
-
- // Get argv with the arguments from the ISS
- mov a3, sp // tell simcall where to write argv[]
- movi a2, SYS_iss_set_argv
- simcall // write argv[] array at a3
-
- movi a2, SYS_iss_argc
- simcall // put argc in a2
-
-
-// Alternative smaller code for Xtensa TX.
-// Many starting with simulation assume a full C env, so NOT DONE FOR NOW.
-//
-//#if XCHAL_HAVE_HALT
-//
-// // Assume minimalist environment for memory-constrained TX cores.
-// // No C library or board initialization, and no call to exit().
-// // However, in the interest of software regressions, for now we
-// // still pass parameters to main (but not the rarely used envp).
-//
-// //mov ARG1, a2 // argc already in a2.
-// mov ARG2, sp // argv
-// CALL main
-// halt
-//
-//#else /* !HALT */
-// ...
-
-
-#if __XTENSA_CALL0_ABI__
- mov a12, a2 // save argc (a2 is ARG1)
-#else
- mov ARG1, a2 // argc
-#endif
- mov ARG2, sp // argv
- movi ARG3, _start_envp // envp
- movi ARG4, _init // _init
- movi ARG5, _fini // _fini
- CALL __clibrary_init
-
- // Call: int main(int argc, char ** argv, char ** environ);
-#if __XTENSA_CALL0_ABI__
- mov ARG1, a12 // argc
-#else
- mov ARG1, a2 // argc
-#endif
- mov ARG2, sp // argv
- movi ARG3, _start_envp // envp = [0]
- CALL main
- // The return value is the same register as the first outgoing argument.
- CALL exit // exit with main's return value
- // Does not return here.
-
- .size _start, . - _start
-
-
-// Local Variables:
-// mode:fundamental
-// comment-start: "// "
-// comment-start-skip: "// *"
-// End:
diff --git a/src/arch/xtensa/up/xtos/crt1-tiny.S b/src/arch/xtensa/up/xtos/crt1-tiny.S
deleted file mode 100644
index bc6360f..0000000
--- a/src/arch/xtensa/up/xtos/crt1-tiny.S
+++ /dev/null
@@ -1,133 +0,0 @@
-// crt1-tiny.S
-//
-// This is a reduced version of the code in crt1-boards.S .
-// For most hardware / boards, this code sets up the C calling context
-// (setting up stack, PS, and clearing BSS) and calls main().
-// It has some limitations (see LSP Ref Manual for details) such as:
-// - does not setup the C library (...)
-// - does not call C++ static constructors and destructors
-// - only clears .bss , not other *.bss sections
-//
-// Control arrives here at _start from the reset vector or from crt0-app.S.
-
-// Copyright (c) 1998-2013 Tensilica Inc.
-//
-// Permission is hereby granted, free of charge, to any person obtaining
-// a copy of this software and associated documentation files (the
-// "Software"), to deal in the Software without restriction, including
-// without limitation the rights to use, copy, modify, merge, publish,
-// distribute, sublicense, and/or sell copies of the Software, and to
-// permit persons to whom the Software is furnished to do so, subject to
-// the following conditions:
-//
-// The above copyright notice and this permission notice shall be included
-// in all copies or substantial portions of the Software.
-//
-// THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
-// EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
-// MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
-// IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY
-// CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
-// TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
-// SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
-
-#include <xtensa/coreasm.h>
-#include <xtensa/xtensa-versions.h>
-#include <xtensa/simcall.h>
-#include <config.h>
-
-
-// Imports
-// __stack from linker script (see LSP Ref Manual)
-// _bss_start from linker script (see LSP Ref Manual)
-// _bss_end from linker script (see LSP Ref Manual)
-// main from user application
-
-
-
-#ifdef __XTENSA_CALL0_ABI__
-# define CALL call0
-#else
-# define CALL call4
-#endif
-
-
-/**************************************************************************/
-
- .text
- .align 4
- .global _start
-_start:
- // _start is typically NOT at the beginning of the text segment --
- // it is always called from either the reset vector or other code
- // that does equivalent initialization (such as crt0-app.S).
- // See crt1-boards.S for assumptions on entry to _start ,
- // and for comments on what is being done in this file.
-
-// not needed for Xtensa TX
-#if !XCHAL_HAVE_HALT || !defined(CONFIG_BOOT_LOADER)
- movi a0, 0 // mark base of call stack
-#endif
-
- movi sp, __stack // setup the stack
-
-#if XCHAL_HAVE_EXCEPTIONS
-# ifdef __XTENSA_CALL0_ABI__
- movi a3, PS_UM // PS: WOE=0, UM=1, EXCM=0, INTLEVEL=0
-# else
- movi a3, PS_UM|PS_WOE // PS: WOE=1, UM=1, EXCM=0, INTLEVEL=0
-# endif
- wsr a3, PS // setup PS for the application
- rsync
-#endif
-
-
- // Clear the BSS (uninitialized data) segment.
- //
- // This code only supports .bss, not multiple *.bss sections.
- // Corresponding code in crt1-boards.S does, and is faster but bigger.
-
-#if !defined(CONFIG_BOOT_LOADER)
- movi a6, _bss_start
- movi a7, _bss_end
- bgeu a6, a7, 2f
-1: s32i a0, a6, 0
- addi a6, a6, 4
- bltu a6, a7, 1b
-2:
-#endif
-
- // We can now call C code, the C calling environment is initialized.
- // This tiny C runtime assumes main is declared as "void main(void)"
- // rather than with the usual argc,argv. So there are no arguments.
-
- CALL main
-
- // In this tiny C runtime, main() is not expected to return.
- // If it does, just loop forever.
-
- //CALL xthal_dcache_all_writeback // sync dirty dcaches to memory
- //extw // sync TIE queues/ports/etc (LX or later only)
-
-.L0:
-#if XCHAL_HAVE_HALT
- halt
-#else
-# if XCHAL_HW_MIN_VERSION >= XTENSA_HWVERSION_RE_2013_2 /* SIMCALL is NOP in hw? */
- movi a2, SYS_exit
- simcall // exit if in simulator, else NOP
-# endif
-# if XCHAL_HAVE_DEBUG
- break 1, 15 // give control to debugger
-# endif
-#endif
- j .L0
-
- .size _start, . - _start
-
-
-// Local Variables:
-// mode:fundamental
-// comment-start: "// "
-// comment-start-skip: "// *"
-// End:
diff --git a/src/arch/xtensa/up/xtos/debug-vector.S b/src/arch/xtensa/up/xtos/debug-vector.S
deleted file mode 100644
index 9c22b89..0000000
--- a/src/arch/xtensa/up/xtos/debug-vector.S
+++ /dev/null
@@ -1,66 +0,0 @@
-// debug-vector.S -- Debug Exception Vector
-// $Id: //depot/rel/Eaglenest/Xtensa/OS/xtos/debug-vector.S#2 $
-
-// Copyright (c) 2003-2013 Tensilica Inc.
-//
-// Permission is hereby granted, free of charge, to any person obtaining
-// a copy of this software and associated documentation files (the
-// "Software"), to deal in the Software without restriction, including
-// without limitation the rights to use, copy, modify, merge, publish,
-// distribute, sublicense, and/or sell copies of the Software, and to
-// permit persons to whom the Software is furnished to do so, subject to
-// the following conditions:
-//
-// The above copyright notice and this permission notice shall be included
-// in all copies or substantial portions of the Software.
-//
-// THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
-// EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
-// MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
-// IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY
-// CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
-// TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
-// SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
-
-#include <xtensa/xtensa-versions.h>
-#include <xtensa/coreasm.h>
-#include <xtensa/config/specreg.h>
-#include <xtensa/simcall.h>
-
-#if XCHAL_HAVE_DEBUG && XCHAL_HAVE_EXCEPTIONS
-
- // This code goes at the debug exception vector
-
- .begin literal_prefix .DebugExceptionVector
- .section .DebugExceptionVector.text, "ax"
- .align 4
- .global _DebugExceptionVector
-_DebugExceptionVector:
-
- isync_erratum453
-# if defined(SIMULATOR) || XCHAL_HW_MIN_VERSION >= XTENSA_HWVERSION_RE_2013_2 /* SIMCALL is NOP in hw? */
- // In the simulator (ISS), let the debugger (if any is attached)
- // handle the debug exception, else simply stop the simulation:
- //
- wsr a2, EXCSAVE+XCHAL_DEBUGLEVEL // save a2 where simulator expects it
- movi a2, SYS_gdb_enter_sktloop
- simcall // have ISS handle the debug exception
-# endif
-# ifndef SIMULATOR
- // For hardware, this code does not handle debug exceptions.
- // To implement a target-side debug monitor, replace this
- // vector with a real one that uses target-specific facilities
- // to communicate with the debugger.
- //
-1:
-# if XCHAL_HAVE_INTERRUPTS
- //waiti XCHAL_DEBUGLEVEL // unexpected debug exception, loop in low-power mode
-# endif
- j 1b // infinite loop - unexpected debug exception
-# endif /*!SIMULATOR*/
-
- .end literal_prefix
- .size _DebugExceptionVector, . - _DebugExceptionVector
-
-#endif /* XCHAL_HAVE_DEBUG && XCHAL_HAVE_EXCEPTIONS */
-
diff --git a/src/arch/xtensa/up/xtos/deprecated.S b/src/arch/xtensa/up/xtos/deprecated.S
deleted file mode 100644
index 2eb2af3..0000000
--- a/src/arch/xtensa/up/xtos/deprecated.S
+++ /dev/null
@@ -1,120 +0,0 @@
-// deprecated.S -- Deprecated assembler functions
-
-// Copyright (c) 2003-2010 Tensilica Inc.
-//
-// Permission is hereby granted, free of charge, to any person obtaining
-// a copy of this software and associated documentation files (the
-// "Software"), to deal in the Software without restriction, including
-// without limitation the rights to use, copy, modify, merge, publish,
-// distribute, sublicense, and/or sell copies of the Software, and to
-// permit persons to whom the Software is furnished to do so, subject to
-// the following conditions:
-//
-// The above copyright notice and this permission notice shall be included
-// in all copies or substantial portions of the Software.
-//
-// THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
-// EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
-// MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
-// IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY
-// CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
-// TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
-// SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
-
-#include <xtensa/coreasm.h>
-#include <xtensa/config/specreg.h>
-#include "xtos-internal.h"
-
-
-
- .text
-
-/*
- void _xtos_timer_<N>_delta(int cycles)
-
- Set the timer from the current ccount.
- DEPRECATED. PLEASE USE xthal_set_ccompare() AND xthal_get_ccount()
- INSTEAD, OR USE DIFFERENT ALGORITHM THAT UPDATES CCOMPAREn RELATIVE TO
- LAST CCOMPAREn FOR DRIFT-FREE PERIODIC TIMER INTERRUPTS.
-*/
- .macro define_timer_delta num, numtimers
- .if ((\num-\numtimers) & ~0xFFF) // num < numtimers ?
- .align 4
- .global _xtos_timer_&num&_delta
- .type _xtos_timer_&num&_delta,@function
-_xtos_timer_&num&_delta:
- abi_entry
- rsr a3, CCOUNT
- add a3, a3, a2
- wsr a3, CCOMPARE_0+&num&
- abi_return
- .size _xtos_timer_&num&_delta, . - _xtos_timer_&num&_delta
- .endif
- .endm
-
-
-
-#if defined(__SPLIT__t0_delta)
-
- define_timer_delta 0, XCHAL_NUM_TIMERS
-
-#elif defined(__SPLIT__t1_delta)
-
- define_timer_delta 1, XCHAL_NUM_TIMERS
-
-#elif defined(__SPLIT__t2_delta)
-
- define_timer_delta 2, XCHAL_NUM_TIMERS
-
-#elif defined(__SPLIT__t3_delta)
-
- define_timer_delta 3, XCHAL_NUM_TIMERS
-
-
-#elif defined(__SPLIT__read_ints)
-
- //
- // u32 _xtos_read_ints( void )
- //
- // _xtos_read_ints() reads the INTERRUPT register and returns it.
- // DEPRECATED. PLEASE USE xthal_get_interrupt() INSTEAD.
- // [Kept temporarily because it was documented in T1050 System SW Ref Manual.]
- //
- .text
- .align 4
- .global _xtos_read_ints
- .type _xtos_read_ints,@function
-_xtos_read_ints:
- abi_entry
-#if XCHAL_HAVE_INTERRUPTS
- rsr a2, INTERRUPT
-#else /*XCHAL_HAVE_INTERRUPTS*/
- movi a2, 0
-#endif /*XCHAL_HAVE_INTERRUPTS*/
- abi_return
- .size _xtos_read_ints, . - _xtos_read_ints
-
-
-#elif defined(__SPLIT__clear_ints)
-
- //
- // void _xtos_clear_ints( u32 mask )
- //
- // _xtos_clear_ints() clears selected bits of the INTERRUPT register.
- // DEPRECATED. PLEASE USE xthal_set_intclear() INSTEAD.
- // [Kept temporarily because it was documented in T1050 System SW Ref Manual.]
- //
- .text
- .align 4
- .global _xtos_clear_ints
- .type _xtos_clear_ints,@function
-_xtos_clear_ints:
- abi_entry
-#if XCHAL_HAVE_INTERRUPTS
- wsr a2, INTCLEAR
-#endif /*XCHAL_HAVE_INTERRUPTS*/
- abi_return
- .size _xtos_clear_ints, . - _xtos_clear_ints
-
-#endif /* splitting */
-
diff --git a/src/arch/xtensa/up/xtos/double-vector.S b/src/arch/xtensa/up/xtos/double-vector.S
deleted file mode 100644
index 1288ae6..0000000
--- a/src/arch/xtensa/up/xtos/double-vector.S
+++ /dev/null
@@ -1,100 +0,0 @@
-// double-vector.S -- Double Exception Vector
-// $Id: //depot/rel/Eaglenest/Xtensa/OS/xtos/double-vector.S#2 $
-
-// Copyright (c) 2000-2004, 2006, 2010 Tensilica Inc.
-//
-// Permission is hereby granted, free of charge, to any person obtaining
-// a copy of this software and associated documentation files (the
-// "Software"), to deal in the Software without restriction, including
-// without limitation the rights to use, copy, modify, merge, publish,
-// distribute, sublicense, and/or sell copies of the Software, and to
-// permit persons to whom the Software is furnished to do so, subject to
-// the following conditions:
-//
-// The above copyright notice and this permission notice shall be included
-// in all copies or substantial portions of the Software.
-//
-// THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
-// EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
-// MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
-// IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY
-// CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
-// TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
-// SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
-
-#include <xtensa/coreasm.h>
-#include <xtensa/config/system.h>
-#include <xtensa/config/specreg.h>
-#ifdef SIMULATOR
-#include <xtensa/simcall.h>
-#endif
-
-
-#if XCHAL_HAVE_EXCEPTIONS && defined(XCHAL_DOUBLEEXC_VECTOR_VADDR)
-
-/*
- * This is a very minimalist implementation of the double
- * exception vector. For XEA2 configurations without a
- * full MMU, this vector is only expected to be executed
- * upon fatal errors (exceptions that occur within critical
- * sections of exception vectors and handlers).
- *
- * For configurations with a full MMU (ie. with TLBs and
- * auto-refill) and the windowed address registers option,
- * a more complete version of this handler is necessary if:
- * dynamic page mapping is implemented, and the stack
- * can ever point to a dynamically mapped area.
- * In this case, a double exception is a normal occurrence
- * when a stack access within a window handler causes
- * a TLB miss exception or other expected MMU fault.
- * XTOS does not support this scenario, hence a minimalist
- * double exception vector is sufficient.
- */
-
- .begin literal_prefix .DoubleExceptionVector
- .section .DoubleExceptionVector.text, "ax"
-
- .align 4
- .global _DoubleExceptionVector
-_DoubleExceptionVector:
-
- isync_erratum453
-# if XCHAL_HAVE_DEBUG
-1: break 1,4 // unhandled double exception
-# elif defined(SIMULATOR)
- wsr a2, EXCSAVE1 // save a2 where simulator expects it
- movi a2, SYS_unhandled_double_exc
-1: simcall // let simulator/debugger report unhandled exception
-# else
-1:
-# endif
- j 1b // infinite loop
-
- // NOTE: a non-minimalist vector may choose to
- // process the double exception in the vector itself
- // (by default, much more space is allocated to double
- // exception vectors than to most other vectors);
- // or, to jump to a double exception handler located
- // elsewhere. If only the normal case of double
- // exceptions occurring within a window handler is
- // being handled, then it is safe to use EXCSAVE_1 to
- // do this jump (window handlers don't use EXCSAVE_1).
- // For example:
- //
- // wsr a0, EXCSAVE_1
- // movi a0, _DoubleExceptionFromVector
- // jx a0
- //
- // .text
- // .align 4
- // .global _DoubleExceptionFromVector
- //_DoubleExceptionFromVector:
- // ...
-
-
- .size _DoubleExceptionVector, . - _DoubleExceptionVector
- .text
- .end literal_prefix
-
-#endif /* have double exceptions */
-
diff --git a/src/arch/xtensa/up/xtos/exc-alloca-handler.S b/src/arch/xtensa/up/xtos/exc-alloca-handler.S
deleted file mode 100644
index 42834d5..0000000
--- a/src/arch/xtensa/up/xtos/exc-alloca-handler.S
+++ /dev/null
@@ -1,273 +0,0 @@
-// exc-alloca-handler.S - ALLOCA cause exception assembly-level handler
-// $Id: //depot/rel/Eaglenest/Xtensa/OS/xtos/exc-alloca-handler.S#1 $
-
-// Copyright (c) 2002-2010 Tensilica Inc.
-//
-// Permission is hereby granted, free of charge, to any person obtaining
-// a copy of this software and associated documentation files (the
-// "Software"), to deal in the Software without restriction, including
-// without limitation the rights to use, copy, modify, merge, publish,
-// distribute, sublicense, and/or sell copies of the Software, and to
-// permit persons to whom the Software is furnished to do so, subject to
-// the following conditions:
-//
-// The above copyright notice and this permission notice shall be included
-// in all copies or substantial portions of the Software.
-//
-// THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
-// EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
-// MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
-// IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY
-// CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
-// TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
-// SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
-
-/*
- * Code written to the windowed ABI must use the MOVSP instruction to modify
- * the stack pointer (except for startup code, which doesn't have a caller).
- * The compiler uses MOVSP to allocate very large or variable size stack frames.
- * MOVSP guarantees that the caller frame's a0-a3 registers, stored below the
- * stack pointer, are moved atomically with respect to interrupts and exceptions
- * to satisfy windowed ABI requirements. When user code executes the MOVSP
- * instruction and the caller frame is on the stack rather than in the register
- * file, the processor takes an ALLOCA exception. The ALLOCA exception handler
- * moves the caller frame's a0-a3 registers to follow the stack pointer.
- * This file implements this ALLOCA exception handler.
- *
- * Code written in C can generate a MOVSP in four situations:
- *
- * 1. By calling "alloca":
- *
- * void foo(int array_size) {
- * char * bar = alloca(array_size);
- * ...
- *
- * 2. By using variable sized arrays (a GNU C extension):
- *
- * void foo(int array_size) {
- * char bar[array_size];
- * ...
- *
- * 3. By using nested C functions (also a GNU C extension):
- *
- * void afunction(void) {
- * ...
- * int anotherfunction(void) {
- * }
- * ...
- *
- * 4. By using very large amounts of stack space in a single function. The exact
- * limit is 32,760 bytes (including 16-48 bytes of caller frame overhead).
- * Typically, users don't encounter this limit unless they have functions
- * that locally declare large arrays, for example:
- *
- * void foo(void) {
- * int an_array[8192]; // 32,768 bytes
- * int another_array[100]; // 400 bytes
- * ...
- *
- *
- * NOTE: This handler only works when MOVSP's destination register is the stack
- * pointer "a1" (synonym with "sp"), i.e. "MOVSP a1, <as>". This is the only
- * meaningful form of MOVSP in the windowed ABI, and the only form generated
- * by the compiler and used in assembly. The code below does not check the
- * destination register, so other forms of MOVSP cause unexpected behaviour.
- */
-
-#include <xtensa/coreasm.h>
-#include <xtensa/config/specreg.h>
-#include "xtos-internal.h"
-
-#define ERROR_CHECKING 1 // define as 0 to save a few bytes
-
-
-#if XCHAL_HAVE_EXCEPTIONS
-
-//Vector:
-// addi a1, a1, -ESF_TOTALSIZE // allocate exception stack frame, etc.
-// s32i a2, a1, UEXC_a2
-// s32i a3, a1, UEXC_a3
-// movi a3, _xtos_exc_handler_table
-// rsr a2, EXCCAUSE
-// addx4 a2, a2, a3
-// l32i a2, a2, 0
-// s32i a4, a1, UEXC_a4
-// jx a2 // jump to cause-specific handler
-
- .global _need_user_vector_ // pull-in real user vector (tiny LSP)
-
- .text
- .align 4
- .global _xtos_alloca_handler
-_xtos_alloca_handler:
-#if !XCHAL_HAVE_WINDOWED || defined(__XTENSA_CALL0_ABI__)
- rfe_rfue
-#else /* we have windows w/o call0 abi */
- // HERE: a2, a3, a4 have been saved to
- // exception stack frame allocated with a1 (sp).
- // a2 contains EXCCAUSE.
- // (12 cycles from vector to here, assuming cache hits, 5-stage pipe, etc)
-
- /*
- * Skip the MOVSP instruction so we don't execute it again on return:
- */
-
- rsr a3, EPC_1 // load instruction address (PC)
- s32i a5, a1, UEXC_a5 // save a5
- addi a2, a3, 3 // increment PC to skip MOVSP instruction
-#if XCHAL_HAVE_LOOPS
- /*
- * If the MOVSP instruction is the last instruction in the body of
- * a zero-overhead loop that must be executed again, then decrement
- * the loop count and resume execution at the head of the loop.
- */
- rsr a4, LEND
- rsr a5, LCOUNT
- bne a4, a2, 1f // done unless next-PC matches LEND
- beqz a5, 1f // if LCOUNT zero, not in loop
- addi a5, a5, -1 // z.o. loopback! decrement LCOUNT...
- wsr a5, LCOUNT
- rsr a2, LBEG // PC back to start of loop
-#endif /*XCHAL_HAVE_LOOPS*/
-1: wsr a2, EPC_1 // update return PC past MOVSP
-
- /*
- * Figure out what register MOVSP is moving from ('s' field, 2nd byte).
- * If MOVSP is in an instruction RAM or ROM, we can only access it with
- * 32-bit loads. So use shifts to read the byte from a 32-bit load.
- */
-
- addi a3, a3, 1 // advance to byte containing 's' field
- extui a2, a3, 0, 2 // get bits 0 and 1 of address of this byte
- sub a3, a3, a2 // put address on 32-bit boundary
- l32i a3, a3, 0 // get word containing byte (can't use l8ui on IRAM/IROM)
- rsr a4, SAR // save SAR
- // NOTE: possible addition here: verify destination register is indeed a1.
-# if XCHAL_HAVE_BE
- ssa8b a2
- sll a3, a3
- extui a3, a3, 28, 4 // extract source register number
-# else
- ssa8l a2
- srl a3, a3
- extui a3, a3, 0, 4 // extract source register number
-# endif
- wsr a4, SAR // restore SAR
- // (+?? cycles max above = ?? cycles, assuming cache hits, 5-stage pipe, no zoloops, etc)
-
- movi a4, .Ljmptable // jump table
- mov a5, a1 // save the exception stack frame ptr in a5
- addi a1, a1, ESF_TOTALSIZE // restore a1 (in case of MOVSP a1,a1)
-
-# if XCHAL_HAVE_DENSITY
- addx4 a4, a3, a4 // index by src reg number * 4
-# define ALIGN .align 4 // 4-byte jmptable entries
-# define MOV _mov.n
-# define L32I _l32i.n
-# define DONE _bnez.n a4, .Lmove_save_area // a4 known non-zero
-# else
- addx8 a4, a3, a4 // index by src reg number * 8
-# define ALIGN .align 8 // 8-byte jmptable entries
-# define MOV mov
-# define L32I l32i
-# define DONE j .Lmove_save_area
-# endif
-
- jx a4 // jump into the following table
-
- ALIGN
-.Ljmptable: MOV a1, a0 ; DONE // MOVSP a1, a0
- ALIGN ; DONE // MOVSP a1, a1
- ALIGN ; L32I a1, a5, UEXC_a2 ; DONE // MOVSP a1, a2
- ALIGN ; L32I a1, a5, UEXC_a3 ; DONE // MOVSP a1, a3
- ALIGN ; L32I a1, a5, UEXC_a4 ; DONE // MOVSP a1, a4
- ALIGN ; L32I a1, a5, UEXC_a5 ; DONE // MOVSP a1, a5
- ALIGN ; MOV a1, a6 ; DONE // MOVSP a1, a6
- ALIGN ; MOV a1, a7 ; DONE // MOVSP a1, a7
- ALIGN ; MOV a1, a8 ; DONE // MOVSP a1, a8
- ALIGN ; MOV a1, a9 ; DONE // MOVSP a1, a9
- ALIGN ; MOV a1, a10 ; DONE // MOVSP a1, a10
- ALIGN ; MOV a1, a11 ; DONE // MOVSP a1, a11
- ALIGN ; MOV a1, a12 ; DONE // MOVSP a1, a12
- ALIGN ; MOV a1, a13 ; DONE // MOVSP a1, a13
- ALIGN ; MOV a1, a14 ; DONE // MOVSP a1, a14
- ALIGN ; MOV a1, a15 // MOVSP a1, a15
-
-.Lmove_save_area:
- // Okay. a1 now contains the new SP value.
-
-# if ERROR_CHECKING
- // Verify it is sensible:
- extui a3, a1, 0, 2 // verify that new SP is 4-byte aligned
- beqz a3, 1f // if so, skip fixup
-
-// .global _xtos_misaligned_movsp // make label visible for debugging
-//_xtos_misaligned_movsp:
-# if XCHAL_HAVE_DEBUG
- break 1, 15 // break into debugger (if any)
-# endif
- sub a1, a1, a3 // FORCE alignment of the new pointer (!)
-1:
-# endif
-
-# if XCHAL_HAVE_XEA2
- addi a2, a5, ESF_TOTALSIZE // compute a2 = old SP
-# else /*XEA1:*/
- addi a2, a5, ESF_TOTALSIZE-16 // compute a2 = old SP's save area
-# endif
- // Does new SP (in a1) overlap with exception stack frame (in a5)?:
- movi a4, ESF_TOTALSIZE // size of exception stack frame
- sub a3, a1, a5 // distance from ESF ptr to new SP
- bgeu a3, a4, 1f // does new SP overlap ESF? branch if not
- // Move ESF down so it doesn't overlap with the new register save area:
- // (a1 = current ESF, a2 = new SP, a4 = ESF_TOTALSIZE)
- sub a5, a5, a4 // shift down ESF (by ESF size)
- l32i a3, a5, UEXC_a2+ESF_TOTALSIZE
- l32i a4, a5, UEXC_a3+ESF_TOTALSIZE
- s32i a3, a5, UEXC_a2
- s32i a4, a5, UEXC_a3
- l32i a3, a5, UEXC_a4+ESF_TOTALSIZE
- l32i a4, a5, UEXC_a5+ESF_TOTALSIZE
- s32i a3, a5, UEXC_a4
- s32i a4, a5, UEXC_a5
-1:
-
- // Move the register save area (from old SP to new SP):
-# if XCHAL_HAVE_XEA2
- l32e a3, a2, -16
- l32e a4, a2, -12
- s32e a3, a1, -16
- s32e a4, a1, -12
- l32e a3, a2, -8
- l32e a4, a2, -4
- s32e a3, a1, -8
- s32e a4, a1, -4
-# else /*XEA1:*/
- addi a1, a1, -16 // point to new save area
- l32i a3, a2, 0
- l32i a4, a2, 4
- s32i a3, a1, 0
- s32i a4, a1, 4
- l32i a3, a2, 8
- l32i a4, a2, 12
- s32i a3, a1, 8
- s32i a4, a1, 12
- addi a1, a1, 16 // back to correct new SP
-# endif /*XEA1*/
- // (+?? cycles max above = ?? cycles, assuming cache hits, 5-stage pipe, etc)
-
- // Restore a2, a3, a4, a5, and return:
- l32i a2, a5, UEXC_a2
- l32i a3, a5, UEXC_a3
- l32i a4, a5, UEXC_a4
- l32i a5, a5, UEXC_a5
- rfe_rfue
- // (+?? cycles max above = ?? cycles, assuming cache hits, 5-stage pipe, etc)
-
-
-#endif /* !XCHAL_HAVE_WINDOWED || __XTENSA_CALL0_ABI */
-
- .size _xtos_alloca_handler, . - _xtos_alloca_handler
-
-#endif /* XCHAL_HAVE_EXCEPTIONS */
-
diff --git a/src/arch/xtensa/up/xtos/exc-c-wrapper-handler.S b/src/arch/xtensa/up/xtos/exc-c-wrapper-handler.S
deleted file mode 100644
index 0db2257..0000000
--- a/src/arch/xtensa/up/xtos/exc-c-wrapper-handler.S
+++ /dev/null
@@ -1,429 +0,0 @@
-// exc-c-wrapper-handler.S - General Exception Handler that Dispatches C Handlers
-
-// Copyright (c) 2002-2012 Tensilica Inc.
-//
-// Permission is hereby granted, free of charge, to any person obtaining
-// a copy of this software and associated documentation files (the
-// "Software"), to deal in the Software without restriction, including
-// without limitation the rights to use, copy, modify, merge, publish,
-// distribute, sublicense, and/or sell copies of the Software, and to
-// permit persons to whom the Software is furnished to do so, subject to
-// the following conditions:
-//
-// The above copyright notice and this permission notice shall be included
-// in all copies or substantial portions of the Software.
-//
-// THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
-// EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
-// MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
-// IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY
-// CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
-// TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
-// SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
-
-#include <xtensa/coreasm.h>
-#include <xtensa/corebits.h>
-#include <xtensa/config/specreg.h>
-#include "xtos-internal.h"
-#ifdef SIMULATOR
-#include <xtensa/simcall.h>
-#endif
-
-#if XCHAL_HAVE_EXCEPTIONS
-
-
-/*
- * This assembly-level handler causes the associated exception (usually causes 12-15)
- * to be handled as if it were exception cause 3 (load/store error exception).
- * This provides forward-compatibility with a possible future split of the
- * load/store error cause into multiple more specific causes.
- */
- .align 4
- .global _xtos_cause3_handler
-_xtos_cause3_handler:
- movi a2, EXCCAUSE_LOAD_STORE_ERROR
- j _xtos_c_wrapper_handler
- .size _xtos_cause3_handler, . - _xtos_cause3_handler
-
-
-#if ! XCHAL_HAVE_XEA1
- .align 4
-.Lhi: addi a3, a3, -XCHAL_EXCM_LEVEL
- add a3, a3, a2
- j .Lps
-#endif
-
-
-/*
- * This is the general exception assembly-level handler that dispatches C handlers.
- */
- .align 4
- .global _xtos_c_wrapper_handler
-_xtos_c_wrapper_handler:
-#ifdef __XTENSA_CALL0_ABI__
- // Redundantly de-allocate and re-allocate stack, so that GDB prologue
- // analysis picks up the allocate part, and figures out how to traceback
- // through the call stack through the exception.
- addi a1, a1, ESF_TOTALSIZE // de-allocate stack frame (FIXME is it safe)
-.global _xtos_c_wrapper_dispatch
-_xtos_c_wrapper_dispatch:
- // GDB starts analyzing prologue after most recent global symbol, so here:
- addi a1, a1, -ESF_TOTALSIZE // re-allocate stack frame
-#endif
-
- // HERE: a2, a3, a4 have been saved to exception stack frame allocated with a1 (sp).
- // a2 contains EXCCAUSE.
- s32i a5, a1, UEXC_a5 // a5 will get clobbered by ENTRY after the pseudo-CALL4
- // (a4..a15 spilled as needed; save if modified)
-
- //NOTA: Possible future improvement:
- // keep interrupts disabled until we get into the handler, such that
- // we don't have to save other critical state such as EXCVADDR here.
- //rsr a3, EXCVADDR
- s32i a2, a1, UEXC_exccause
- //s32i a3, a1, UEXC_excvaddr
-
-#if XCHAL_HAVE_XEA1
-# if XCHAL_HAVE_INTERRUPTS
- rsilft a3, 1, XTOS_LOCKLEVEL // lockout
- rsr a2, INTENABLE
- //movi a3, ~XCHAL_EXCM_MASK
- movi a3, ~XTOS_LOCKOUT_MASK // mask out low and medium priority levels, and high priority levels covered by
- // XTOS_LOCKLEVEL if any, so we can run at PS.INTLEVEL=0 while manipulating INTENABLE
- s32i a2, a1, UEXC_sar // (temporary holding place for INTENABLE value to restore after pseudo-CALL4 below)
- and a3, a2, a3 // mask out selected interrupts
- wsr a3, INTENABLE // disable all interrupts up to and including XTOS_LOCKLEVEL
-# endif
- movi a3, PS_WOE|PS_CALLINC(1)|PS_UM // WOE=1, UM=1, INTLEVEL=0, CALLINC=1 (call4 emul), OWB=(dontcare)=0
-
- // NOTE: could use XSR here if targeting T1040 or T1050 hardware (requiring slight sequence adjustment as for XEA2):
- rsr a2, PS
- rsync //NOT-ISA-DEFINED // wait for WSR to INTENABLE to complete before clearing PS.INTLEVEL
- wsr a3, PS // PS.INTLEVEL=0, effective INTLEVEL (via INTENABLE) is XTOS_LOCKLEVEL
-
- // HERE: window overflows enabled, but NOT SAFE because we're not quite
- // in a valid windowed context (haven't restored a1 yet...);
- // so don't cause any (keep to a0..a3) until we've saved critical state and restored a1:
-
- // NOTE: MUST SAVE EPC1 before causing any overflows, because overflows corrupt EPC1.
- rsr a3, EPC_1
- s32i a2, a1, UEXC_ps
- s32i a3, a1, UEXC_pc
-
-#else /* !XEA1 */
-
- // Set PS fields:
- // EXCM = 0
- // WOE = __XTENSA_CALL0_ABI__ ? 0 : 1
- // UM = 1
- // INTLEVEL = MIN(INTLEVEL,EXCM_LEVEL)
- // CALLINC = __XTENSA_CALL0_ABI__ ? 0 : 1
- // OWB = 0 (really, a dont care if !__XTENSA_CALL0_ABI__)
-
- rsr a2, PS
-# ifdef __XTENSA_CALL0_ABI__
- movi a3, PS_UM|PS_INTLEVEL(XCHAL_EXCM_LEVEL)
-# else
- movi a3, PS_WOE|PS_CALLINC(1)|PS_UM|PS_INTLEVEL(XCHAL_EXCM_LEVEL) // CALL4 emulation
-# endif
- s32i a2, a1, UEXC_ps
- extui a2, a2, 0, 4 // extract PS.INTLEVEL
- bgeui a2, XCHAL_EXCM_LEVEL+1, .Lhi // at PS.INTLEVEL > EXCM_LEVEL ?
-.Lps: rsr a2, EPC_1
- wsr a3, PS
-
- // HERE: window overflows enabled, but NOT SAFE because we're not quite
- // in a valid windowed context (haven't restored a1 yet...);
- // so don't cause any (keep to a0..a3) until we've saved critical state and restored a1:
-
- // NOTE: MUST SAVE EPC1 before causing any overflows, because overflows corrupt EPC1.
- s32i a2, a1, UEXC_pc
-#endif
-
-#ifdef __XTENSA_CALL0_ABI__
-
- s32i a0, a1, UEXC_a0 // save the rest of the registers
- s32i a6, a1, UEXC_a6
- s32i a7, a1, UEXC_a7
- s32i a8, a1, UEXC_a8
- s32i a9, a1, UEXC_a9
- s32i a10, a1, UEXC_a10
- s32i a11, a1, UEXC_a11
- s32i a12, a1, UEXC_a12
- s32i a13, a1, UEXC_a13
- s32i a14, a1, UEXC_a14
- s32i a15, a1, UEXC_a15
-# if XTOS_DEBUG_PC
- // TODO: setup return PC for call traceback through interrupt dispatch
-# endif
-
- rsync // wait for WSR to PS to complete
-
-#else /* ! __XTENSA_CALL0_ABI__ */
-
-# if XTOS_CNEST
- l32i a2, a1, ESF_TOTALSIZE-20 // save nested-C-func call-chain ptr
-# endif
- addi a1, a1, ESF_TOTALSIZE // restore sp (dealloc ESF) for sane stack again
- rsync // wait for WSR to PS to complete
-
- /* HERE: we can SAFELY get window overflows.
- *
- * From here, registers a4..a15 automatically get spilled if needed.
- * They become a0..a11 after the ENTRY instruction.
- * Currently, we don't check whether or not these registers
- * get spilled, so we must save and restore any that we
- * modify. We've already saved a4 and a5
- * which we modify as part of the pseudo-CALL.
- *
- * IMPLEMENTATION NOTE:
- *
- * The pseudo-CALL below effectively saves registers a2..a3 so
- * that they are available again after the corresponding
- * RETW when returning from the exception handling. We
- * could choose to put something like EPC1 or PS in
- * there, so they're available more quickly when
- * restoring. HOWEVER, exception handlers may wish to
- * change such values, or anything on the exception stack
- * frame, and expect these to be restored as modified.
- *
- * NOTA: future: figure out what's the best thing to put
- * in a2 and a3. (candidate: a4 and a5 below; but what
- * if exception handler manipulates ARs, as in a syscall
- * handler.... oh well)
- *
- *
- * Now do the pseudo-CALL.
- * Make it look as if the code that got the exception made a
- * CALL4 to the exception handling code. (We call
- * this the "pseudo-CALL".)
- *
- * This pseudo-CALL is important and done this way:
- *
- * 1. There are only three ways to safely update the stack pointer
- * in the windowed ABI, such that window exceptions work correctly:
- * (a) spill all live windows to stack then switch to a new stack
- * (or, save the entire address register file and window
- * registers, which is likely even more expensive)
- * (b) use MOVSP (or equivalent)
- * (c) use ENTRY/RETW
- * Doing (a) is excessively expensive, and doing (b) here requires
- * copying 16 bytes back and forth which is also time-consuming;
- * whereas (c) is very efficient, so that's what we do here.
- *
- * 2. Normally we cannot do a pseudo-CALL8 or CALL12 here.
- * According to the
- * windowed ABI, a function must allocate enough space
- * for the largest call that it makes. However, the
- * pseudo-CALL is executed in the context of the
- * function that happened to be executing at the time
- * the interrupt was taken, and that function might or
- * might not have allocated enough stack space for a
- * CALL8 or a CALL12. If we try doing a pseudo-CALL8
- * or -CALL12 here, we corrupt the stack if the
- * interrupted function happened to not have allocated
- * space for such a call.
- *
- * 3. We set the return PC, but it's not strictly
- * necessary for proper operation. It does make
- * debugging, ie. stack tracebacks, much nicer if it
- * can point to the interrupted code (not always
- * possible, eg. if interrupted code is in a different
- * GB than the interrupt handling code, which is
- * unlikely in a system without protection where
- * interrupt handlers and general application code are
- * typically linked together).
- *
- * IMPORTANT: Interrupts must stay disabled while doing the pseudo-CALL,
- * or at least until after the ENTRY instruction, because SP has been
- * restored to its original value that does not reflect the exception
- * stack frame's allocation. An interrupt taken here would
- * corrupt the exception stack frame (ie. allocate another over it).
- * (High priority interrupts can remain enabled, they save and restore
- * all of their state and use their own stack or save area.)
- * For the same reason, we mustn't get any exceptions in this code
- * (other than window exceptions where noted) until ENTRY is done.
- */
-
- // HERE: may get a single window overflow (caused by the following instruction).
-
-# if XTOS_DEBUG_PC
- movi a4, 0xC0000000 // [for debug] for return PC computation below
- or a3, a4, a3 // [for debug] set upper two bits of return PC
- addx2 a4, a4, a3 // [for debug] clear upper bit
-# else
- movi a4, 0 // entry cannot cause overflow, cause it here
-# endif
-
- .global _GeneralException
-_GeneralException: // this label makes tracebacks through exceptions look nicer
-
- _entry a1, ESF_TOTALSIZE // as if after a CALL4 (PS.CALLINC set to 1 above)
-
- /*
- * The above ENTRY instruction does a number of things:
- *
- * 1. Because we're emulating CALL4, the ENTRY rotates windows
- * forward by 4 registers (as per 'ROTW +1'), so that
- * a4-a15 became a0-a11. So now: a0-a11 are part of
- * the interrupted context to be preserved. a0-a1
- * were already saved above when they were a4-a5.
- * a12-a15 are free to use as they're NOT part of the
- * interrupted context. We don't need to save/restore
- * them, and they will get spilled if needed.
- *
- * 2. Updates SP (new a1), allocating the exception stack
- * frame in the new window, preserving the old a1 in
- * the previous window.
- *
- * 3. The underscore prefix prevents the assembler from
- * automatically aligning the ENTRY instruction on a
- * 4-byte boundary, which could create a fatal gap in
- * the instruction stream.
- *
- * At this point, ie. before we re-enable interrupts, we know the caller is
- * always live so we can safely modify a1 without using MOVSP (we can use MOVSP
- * but it will never cause an ALLOCA or underflow exception here).
- * So this is a good point to modify the stack pointer if we want eg. to
- * switch to an interrupt stack (if we do, we need to save the current SP
- * because certain things have been saved to that exception stack frame).
- * We couldn't do this easily before ENTRY, where the caller wasn't
- * necessarily live.
- *
- * NOTE: We don't switch to an interrupt stack here, because exceptions
- * are generally caused by executing code -- so we handle exceptions in
- * the context of the thread that cause them, and thus remain on the same
- * stack. This means a thread's stack must be large enough to handle
- * the maximum level of nesting of exceptions that the thread can cause.
- */
-
- // NOTA: exception handlers for certain causes may need interrupts to be kept
- // disabled through their dispatch, so they can turn them off themselves at
- // the right point (if at all), eg. to save critical state unknown to this
- // code here, or for some recovery action that must be atomic with respect
- // to interrupts....
- //
- // Perhaps two versions of this assembly-level handler are needed, one that restores
- // interrupts to what they were before the exception was taken (as here)
- // and one that ensures at least low-priority interrupts are kept disabled?
- // NOTA: For now, always enable interrupts here.
-
- /*
- * Now we can enable interrupts.
- * (Pseudo-CALL is complete, and SP reflects allocation of exception stack frame.)
- */
-
-#endif /* __XTENSA_CALL0_ABI__ */
-
-
-#if XCHAL_HAVE_INTERRUPTS
-# if XCHAL_HAVE_XEA1
- //... recompute and set INTENABLE ...
- l32i a13, a1, UEXC_sar // (temporary holding place for INTENABLE value saved before pseudo-CALL4 above)
- rsr a12, SAR
- wsr a13, INTENABLE // restore INTENABLE as it was on entry
-# else
- rsr a12, SAR
- // Restore PS.INTLEVEL to its saved value (re-enables interrupts
- // if they were enabled before taking the exception):
- l32i a13, a1, UEXC_ps
- rsr a14, PS
- extui a13, a13, 0, 4 // extract saved PS.INTLEVEL
- extui a15, a14, 0, 4 // extract current PS.INTLEVEL
- xor a14, a14, a15 // clear a14.INTLEVEL
- xor a14, a14, a13 // replace with saved PS.INTLEVEL
- wsr a14, PS // restore PS.INTLEVEL
-# endif
-#else
- rsr a12, SAR
-#endif
-
- movi a13, _xtos_c_handler_table // &table
- l32i a15, a1, UEXC_exccause // arg2: exccause
-
- s32i a12, a1, UEXC_sar
- save_loops_mac16 a1, a12, a14 // save LOOP & MAC16 regs, if configured
-
- addx4 a12, a15, a13 // a12 = table[exccause]
- l32i a12, a12, 0 // ...
-#ifdef __XTENSA_CALL0_ABI__
- mov a2, a1 // arg1: exception parameters
- mov a3, a15 // arg2: exccause
- beqz a12, 1f // null handler => skip call
- callx0 a12 // call C exception handler for this exception
-#else
- mov a14, a1 // arg1: exception parameters
- // mov a15, a15 // arg2: exccause, already in a15
- beqz a12, 1f // null handler => skip call
- callx12 a12 // call C exception handler for this exception
-#endif
-1:
- // Now exit the handler.
-
-
- // Restore special registers
-
- restore_loops_mac16 a1, a13, a14, a15 // restore LOOP & MAC16 regs, if configured
- l32i a14, a1, UEXC_sar
-
- /*
- * Disable interrupts while returning from the pseudo-CALL setup above,
- * for the same reason they were disabled while doing the pseudo-CALL:
- * this sequence restores SP such that it doesn't reflect the allocation
- * of the exception stack frame, which we still need to return from
- * the exception.
- */
-
-#if XCHAL_HAVE_INTERRUPTS
-# if XCHAL_HAVE_XEA1
- // Must disable interrupts via INTENABLE, because PS.INTLEVEL gets zeroed
- // by any window exception exit, eg. the window underflow that may happen
- // upon executing the RETW instruction.
- // Also, must disable at XTOS_LOCKLEVEL, not just EXCM_LEVEL, because this
- // code effectively manipulates virtual INTENABLE state up to the point
- // INTENABLE is written in _xtos_return_from_exc.
- //
- rsilft a12, 1, XTOS_LOCKLEVEL // lockout
- rsr a12, INTENABLE
- //movi a13, ~XCHAL_EXCM_MASK
- movi a13, ~XTOS_LOCKOUT_MASK // mask out low and medium priority levels, and high priority levels covered by
- // XTOS_LOCKLEVEL if any, so we can run at PS.INTLEVEL=0 while manipulating INTENABLE
- s32i a12, a1, UEXC_sar // (temporary holding place for INTENABLE value to restore after pseudo-CALL4 below)
- and a13, a12, a13 // mask out selected interrupts
- wsr a13, INTENABLE // disable all interrupts up to and including XTOS_LOCKLEVEL
-# else
- rsil a12, XCHAL_EXCM_LEVEL
-# endif
-#endif
- wsr a14, SAR
-
- movi a0, _xtos_return_from_exc
-#ifdef __XTENSA_CALL0_ABI__
- jx a0
-#else /* ! __XTENSA_CALL0_ABI__ */
- /* Now return from the pseudo-CALL from the interrupted code, to rotate
- * our windows back... */
-
- movi a13, 0xC0000000
- //movi a13, 3
- //slli a13, a13, 30
-# if XCHAL_HAVE_XEA1 && XCHAL_HAVE_INTERRUPTS
- rsync //NOT-ISA-DEFINED // wait for WSR to INTENABLE to complete before doing RETW
- // (ie. before underflow exception exit)
- // (not needed, because underflow exception entry does implicit ISYNC ??
- // but in case underflow not taken, WSR must complete before wsr to PS that lowers PS.INTLEVEL
- // possibly below XTOS_LOCKLEVEL, in which RETW's jump is not sufficient sync, so a sync
- // is needed but it can be placed just before WSR to PS -- but here is fine)
-# endif
- or a0, a0, a13 // set upper two bits
- addx2 a0, a13, a0 // clear upper bit
- retw
-#endif /* ! __XTENSA_CALL0_ABI__ */
-
- /* FIXME: what about _GeneralException ? */
-
- .size _xtos_c_wrapper_handler, . - _xtos_c_wrapper_handler
-
-
-#endif /* XCHAL_HAVE_EXCEPTIONS */
-
diff --git a/src/arch/xtensa/up/xtos/exc-return.S b/src/arch/xtensa/up/xtos/exc-return.S
deleted file mode 100644
index 5a85b10..0000000
--- a/src/arch/xtensa/up/xtos/exc-return.S
+++ /dev/null
@@ -1,123 +0,0 @@
-// exc-return.S - Shared exception/interrupt return code
-
-// Copyright (c) 2002-2004, 2006-2007, 2010 Tensilica Inc.
-//
-// Permission is hereby granted, free of charge, to any person obtaining
-// a copy of this software and associated documentation files (the
-// "Software"), to deal in the Software without restriction, including
-// without limitation the rights to use, copy, modify, merge, publish,
-// distribute, sublicense, and/or sell copies of the Software, and to
-// permit persons to whom the Software is furnished to do so, subject to
-// the following conditions:
-//
-// The above copyright notice and this permission notice shall be included
-// in all copies or substantial portions of the Software.
-//
-// THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
-// EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
-// MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
-// IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY
-// CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
-// TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
-// SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
-
-#include <xtensa/coreasm.h>
-#include <xtensa/corebits.h>
-#include <xtensa/config/specreg.h>
-#include "xtos-internal.h"
-
-#if XCHAL_HAVE_EXCEPTIONS
-
- .text
- .align 4
- .global _xtos_return_from_exc
-_xtos_return_from_exc:
-
-#ifdef __XTENSA_CALL0_ABI__
-
- l32i a0, a1, UEXC_a0 // restore general registers, pc, ps
- l32i a4, a1, UEXC_a4
- l32i a5, a1, UEXC_a5
- l32i a6, a1, UEXC_a6
- l32i a7, a1, UEXC_a7
- l32i a8, a1, UEXC_a8
- l32i a9, a1, UEXC_a9
- l32i a10, a1, UEXC_a10
- l32i a11, a1, UEXC_a11
- l32i a12, a1, UEXC_a12
- l32i a13, a1, UEXC_a13
- l32i a14, a1, UEXC_a14
- l32i a15, a1, UEXC_a15
-
- l32i a2, a1, UEXC_pc
- l32i a3, a1, UEXC_ps
- wsr a2, EPC_1
- wsr a3, PS
-
- l32i a2, a1, UEXC_a2
- l32i a3, a1, UEXC_a3
-
- rsync // wait for WSR to PS to complete
-
- addi a1, a1, ESF_TOTALSIZE // restore sp
-
- rfe
-
-#else /* ! __XTENSA_CALL0_ABI__ */
-
-
- // Here we rotated back by N registers, to the interrupted code's register window.
- // NOTA: a2 and a3 might contain something useful, but we haven't determined
- // what that might be yet (for now, a2 contains nested-C-func call-chain ptr).
-
- // NOTE: a5 still contains the exception window's exception stack frame pointer.
-
-# if XTOS_CNEST
- s32i a2, a5, ESF_TOTALSIZE-20 // restore nested-C-func call-chain ptr
-# endif
- l32i a2, a5, UEXC_ps
- l32i a3, a5, UEXC_pc
- wsr a2, PS // for XEA2, this sets EXCM; for XEA1, this sets INTLEVEL to 1; ...
-
-# if XCHAL_HAVE_XEA1 && XCHAL_HAVE_INTERRUPTS
- l32i a4, a5, UEXC_sar // load INTENABLE value that restores original vpri
- l32i a2, a5, UEXC_a2
- rsync // wait for WSR to PS to complete
- wsr a4, INTENABLE // update INTENABLE to restore original vpri (PS.INTLEVEL=1 here)
- l32i a4, a5, UEXC_a4
-# else
- l32i a2, a5, UEXC_a2
- l32i a4, a5, UEXC_a4
- rsync // wait for WSR to PS to complete
-# endif
-
- /* FIXME: Enabling this here may break task-engine builds
- * because task engines have exceptions (sort of), but they do
- * not have the EPC_1 special register. XCHAL_HAVE_INTERRUPTS
- * is incorrect for normal configs without interrupts but with
- * exceptions (we still need to restore EPC_1). The correct
- * solution is to define XCHAL_HAVE_EXCEPTIONS more strictly
- * to mean something like "Have exceptions with
- * user/kernel/double vectors" so that task engines are
- * excluded. This would be a change to
- * <xtensa/config/core.h>. */
-
- wsr a3, EPC_1
- // HERE:
- // - we cannot get window overflows anymore -- we're NOT in a valid windowed context
- // - low-priority interrupts are still disabled
-
- // NOTE: we don't restore EXCCAUSE or EXCVADDR, not needed.
-
- // Restore a3, a5:
- l32i a3, a5, UEXC_a3
- l32i a5, a5, UEXC_a5
-
- rfe_rfue
-
-#endif /* __XTENSA_CALL0_ABI__ */
-
- .size _xtos_return_from_exc, . - _xtos_return_from_exc
-
-#endif /* XCHAL_HAVE_EXCEPTIONS */
-
diff --git a/src/arch/xtensa/up/xtos/exc-sethandler.c b/src/arch/xtensa/up/xtos/exc-sethandler.c
deleted file mode 100644
index 7d83b73..0000000
--- a/src/arch/xtensa/up/xtos/exc-sethandler.c
+++ /dev/null
@@ -1,66 +0,0 @@
-/* exc-sethandler.c - register an exception handler in XTOS */
-
-/*
- * Copyright (c) 1999-2006 Tensilica Inc.
- *
- * Permission is hereby granted, free of charge, to any person obtaining
- * a copy of this software and associated documentation files (the
- * "Software"), to deal in the Software without restriction, including
- * without limitation the rights to use, copy, modify, merge, publish,
- * distribute, sublicense, and/or sell copies of the Software, and to
- * permit persons to whom the Software is furnished to do so, subject to
- * the following conditions:
- *
- * The above copyright notice and this permission notice shall be included
- * in all copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
- * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
- * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
- * IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY
- * CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
- * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
- * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
- */
-
-#include <xtensa/config/core.h>
-#include <xtensa/config/specreg.h>
-#include "xtos-internal.h"
-
-
-#if XCHAL_HAVE_EXCEPTIONS
-
-extern void _xtos_c_wrapper_handler(void); /* assembly-level handler for C handlers */
-extern void _xtos_unhandled_exception(void); /* assembly-level handler for exceptions
- with no registered handler */
-extern void _xtos_p_none(void); /* default/empty C handler */
-
-
-extern _xtos_handler _xtos_c_handler_table[];
-extern _xtos_handler _xtos_exc_handler_table[];
-
-/*
- * Register a C handler for the specified general exception
- * (specified EXCCAUSE value).
- */
-_xtos_handler _xtos_set_exception_handler( int n, _xtos_handler f )
-{
- _xtos_handler ret;
-
- if( (unsigned) n >= XCHAL_EXCCAUSE_NUM )
- return 0;
- if( f == 0 )
- f = &_xtos_p_none;
- ret = _xtos_c_handler_table[n];
- _xtos_exc_handler_table[n] = ( (f == &_xtos_p_none)
- ? &_xtos_unhandled_exception
- : &_xtos_c_wrapper_handler );
- _xtos_c_handler_table[n] = f;
- if( ret == &_xtos_p_none )
- ret = 0;
-
- return ret;
-}
-
-#endif /* XCHAL_HAVE_EXCEPTIONS */
-
diff --git a/src/arch/xtensa/up/xtos/exc-syscall-c-handler.c b/src/arch/xtensa/up/xtos/exc-syscall-c-handler.c
deleted file mode 100644
index eaa6142..0000000
--- a/src/arch/xtensa/up/xtos/exc-syscall-c-handler.c
+++ /dev/null
@@ -1,102 +0,0 @@
-/* exc-syscall-c-handler.c - SYSCALL instruction XTOS handler in C */
-
-/*
- * Copyright (c) 1999-2006 Tensilica Inc.
- *
- * Permission is hereby granted, free of charge, to any person obtaining
- * a copy of this software and associated documentation files (the
- * "Software"), to deal in the Software without restriction, including
- * without limitation the rights to use, copy, modify, merge, publish,
- * distribute, sublicense, and/or sell copies of the Software, and to
- * permit persons to whom the Software is furnished to do so, subject to
- * the following conditions:
- *
- * The above copyright notice and this permission notice shall be included
- * in all copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
- * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
- * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
- * IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY
- * CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
- * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
- * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
- */
-
-#include <xtensa/config/core.h>
-#include "xtos-internal.h"
-
-UserFrame* _xtos_p_syscall_handler( UserFrame *uf /*, int cause */ );
-
-/*
- * User vector mode exception handler for the SYSCALL cause.
- *
- * NOTE: This function is NOT used by default. The assembly-level
- * handler version of this function is normally used instead.
- * This function is provided as an example only.
- * To use it instead of the default assembly-level version,
- * you can register it using _xtos_set_exception_handler().
- * For example:
- *
- * #include <xtensa/xtruntime.h>
- * #include <xtensa/corebits.h>
- * _xtos_set_exception_handler( EXCCAUSE_SYSCALL,
- * (_xtos_handler)_xtos_p_syscall_handler );
- */
-UserFrame* _xtos_p_syscall_handler( UserFrame *uf /*, int cause */ )
-{
- uf->pc += 3; /* skip SYSCALL instruction */
-
-#if XCHAL_HAVE_LOOPS
- /*
- * If the SYSCALL instruction was the last instruction in the body
- * of a zero-overhead loop, then we should decrement the loop count
- * and resume execution at the head of the loop.
- */
-
- if( uf->pc == uf->lend && uf->lcount != 0 )
- {
- uf->lcount--;
- uf->pc = uf->lbeg;
- }
-#endif /*XCHAL_HAVE_LOOP*/
-
- /*
- * Handle the system call.
- *
- * A typical SYSCALL handler uses code such as this to handle
- * the system call, where the operation to be done is determined
- * by the a2 register. Parameters to the operation are typically
- * passed in address registers a3 and up. Results are typically
- * returned in a2. (See Linux source code for example.)
- */
- switch( uf->a2 ) {
- case 0:
- /* Spill register windows to the stack. */
- /*
- * The Xtensa architecture reserves the a2==0 condition as a request
- * to flush (spill) register windows to the stack. The current exception
- * handling implementation never spills windows to the stack (it used
- * to always spill, not true anymore), so we have to spill windows
- * explicitly here. (Note that xthal_window_spill() spills windows
- * that are part of the interrupt handling context, that don't
- * really need to be spilled, but that's harmless other than being
- * less than optimally efficient.)
- *
- * Also, be nice to programmers here. If they're
- * building for Call0 ABI, silently do nothing for
- * syscall a2==0.
- */
-#ifdef __XTENSA_WINDOWED_ABI__
- xthal_window_spill();
-#endif
- break;
-
- default:
- uf->a2 = -1 /*ENOSYS*/; /* system call not supported */
- break;
- }
-
- return( uf );
-}
-
diff --git a/src/arch/xtensa/up/xtos/exc-syscall-handler.S b/src/arch/xtensa/up/xtos/exc-syscall-handler.S
deleted file mode 100644
index 014cb26..0000000
--- a/src/arch/xtensa/up/xtos/exc-syscall-handler.S
+++ /dev/null
@@ -1,192 +0,0 @@
-/* exc-syscall-handler.S - XTOS syscall instruction handler */
-
-/*
- * Copyright (c) 1999-2010 Tensilica Inc.
- *
- * Permission is hereby granted, free of charge, to any person obtaining
- * a copy of this software and associated documentation files (the
- * "Software"), to deal in the Software without restriction, including
- * without limitation the rights to use, copy, modify, merge, publish,
- * distribute, sublicense, and/or sell copies of the Software, and to
- * permit persons to whom the Software is furnished to do so, subject to
- * the following conditions:
- *
- * The above copyright notice and this permission notice shall be included
- * in all copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
- * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
- * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
- * IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY
- * CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
- * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
- * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
- */
-
-/*
- * The SYSCALL instruction is typically used to implement system calls.
- * By convention, register a2 identifies the requested system call.
- * Typically, other parameters are passed in registers a3 and up,
- * and results are returned in a2.
- *
- * The Xtensa windowed ABI reserves the value zero of register a2
- * as a request to force register windows to the stack. The call0 ABI,
- * which has no equivalent operation, reserves this value as a no-op.
- *
- * Generally, only code that traverses the stack in unusual ways needs
- * to force (spill) register windows to the stack. In generic C or C++,
- * there are four cases, and they all use the standard SYSCALL mechanism:
- *
- * 1. C++ exceptions
- * 2. setjmp and longjmp
- * 3. functions using the GNU extension "__builtin_return_address"
- * 4. functions using the GNU extension "nonlocal goto"
- *
- * NOTE: Specific operating systems often need to spill register windows
- * to the stack in other situations such as context-switching, passing
- * Unix-like signals to threads, displaying stack tracebacks, etc.
- * They may choose to use the SYSCALL mechanism to do so, or use other
- * means such as calling xthal_window_spill() or other methods.
- *
- * If you want to handle other system calls, you can modify this file, or
- * use the C version of it in exc-syscall-handler.c . The Xtensa ABIs only
- * define system call zero; the behavior of other system calls is up to you.
- */
-
-#include <xtensa/coreasm.h>
-#include "xtos-internal.h"
-
-
-#if XCHAL_HAVE_EXCEPTIONS
-
-//Vector:
-// addi a1, a1, -ESF_TOTALSIZE // allocate exception stack frame, etc.
-// s32i a2, a1, UEXC_a2
-// s32i a3, a1, UEXC_a3
-// movi a3, _xtos_exc_handler_table
-// rsr a2, EXCCAUSE
-// addx4 a2, a2, a3
-// l32i a2, a2, 0
-// s32i a4, a1, UEXC_a4
-// jx a2 // jump to cause-specific handler
-
- .global _need_user_vector_ // pull-in real user vector (tiny LSP)
-
-
- /*
- * The SYSCALL handler is entered when the processor
- * executes the SYSCALL instruction.
- * By convention, the system call to execute is specified in a2.
- */
- .text
- .align 4
- .global _xtos_syscall_handler
-_xtos_syscall_handler:
- // HERE: a2, a3, a4 have been saved to the exception stack frame allocated with a1 (sp).
- // We ignore that a4 was saved, we don't clobber it.
-
- rsr a3, EPC_1
-#if XCHAL_HAVE_LOOPS
- // If the SYSCALL instruction was the last instruction in the body of
- // a zero-overhead loop, and the loop will execute again, decrement
- // the loop count and resume execution at the head of the loop:
- //
- rsr a2, LEND
- addi a3, a3, 3 // increment EPC to skip the SYSCALL instruction
- bne a2, a3, 1f
- rsr a2, LCOUNT
- beqz a2, 1f
- addi a2, a2, -1
- wsr a2, LCOUNT
- rsr a3, LBEG
-1: l32i a2, a1, UEXC_a2 // get the system call number
-#else
- // No loop registers.
- l32i a2, a1, UEXC_a2 // get the system call number
- addi a3, a3, 3 // increment EPC to skip the SYSCALL instruction
-#endif
- wsr a3, EPC_1 // update EPC1 past SYSCALL
- l32i a3, a1, UEXC_a3 // restore a3
- // If you want to handle other system calls, check a2 here.
-
-#ifdef __XTENSA_WINDOWED_ABI__
- bnez a2, .Lnotzero // is syscall number zero?
-
- /* Spill register windows to the stack. */
-
- // Save a2 thru a5 in the nested-C-function area, where an interrupt
- // won't clobber them. The pseudo-CALL's ENTRY below clobbers a4 and a5.
- //s32i a2, a1, (ESF_TOTALSIZE - 32) + 0 // a2 is zero, no need to save
- s32i a3, a1, (ESF_TOTALSIZE - 32) + 4
- s32i a4, a1, (ESF_TOTALSIZE - 32) + 8
- s32i a5, a1, (ESF_TOTALSIZE - 32) + 12
-
- movi a3, PS_WOE|PS_CALLINC(1)|PS_UM|PS_INTLEVEL(XCHAL_EXCM_LEVEL) // CALL4 emulation
- rsr a2, PS // save PS in a2
- wsr a3, PS // PS.INTLEVEL=EXCMLEVEL (1 for XEA1)
- // HERE: window overflows enabled but NOT SAFE yet, touch only a0..a3 until it's safe.
- rsr a3, EPC_1 // save EPC1 in a3
- addi a1, a1, ESF_TOTALSIZE // restore sp (dealloc ESF) for sane stack again
- rsync // wait for WSR to PS to complete
- // HERE: Window overflows and interrupts are safe, we saved EPC1 and
- // restored a1, and a4-a15 are unmodified.
- // Pseudo-CALL: make it look as if the code that executed SYSCALL
- // made a CALL4 to here. See user exc. handler comments for details.
- // ENTRY cannot cause window overflow; touch a4 to ensure a4-a7
- // overflow if needed:
- movi a4, 0 // clears pseudo-CALL's return PC
- // NOTE: On XEA1 processors, return from window overflow re-enables
- // interrupts (by clearing PS.INTLEVEL). This is okay even though SP
- // is unallocated because we saved state safe from interrupt dispatch.
- .global _SyscallException
-_SyscallException: // label makes tracebacks look nicer
- _entry a1, 64 // as if after a CALL4 (PS.CALLINC==1)
- // Call deep enough to force spill of entire address register file.
- _call12 __deep_call
-1: movi a14, 0x80000000 + .Ldelta_done
- add a0, a12, a14 // clear a0 msbit (per CALL4), offset
-3: retw // return from pseudo-CALL4
-
- // NOTE: a5 still contains the exception window's exception stack frame pointer.
-.LMdon: wsr a2, PS // for XEA2, this sets EXCM; for XEA1, this sets INTLEVEL to 1; ...
- movi a2, 0 // indicate successful SYSCALL (?)
- l32i a4, a5, 32 + 8
- rsync // complete WSR to PS for safe write to EPC1
- wsr a3, EPC_1
- l32i a3, a5, 32 + 4
- l32i a5, a5, 32 + 12
- rfe_rfue
-
- .set .Ldelta_retw, (3b - 1b)
- .set .Ldelta_done, (.LMdon - 1b)
-
- .align 4
- .local __deep_call
-__deep_call:
- entry a1, 48
-#if XCHAL_NUM_AREGS < 64
- mov a15, a15 // touch just far enough to overflow 32
-#else
- movi a12, .Ldelta_retw // use movi/add because of relocation
- add a12, a0, a12 // set return PC as per CALL12
- _entry a1, 48 // last call was call12 so PS.CALLINC==3
- mov a12, a0 // set return PC
- _entry a1, 48
- mov a12, a0 // set return PC
- _entry a1, 16
- mov a11, a11 // touch just far enough to overflow 64
-#endif
- retw
-
-#endif /* __XTENSA_WINDOWED_ABI__ */
-
-.Lnotzero:
- movi a2, -1 /*ENOSYS*/ // system call not supported
- addi a1, a1, ESF_TOTALSIZE
- rfe_rfue
-
- .size _xtos_syscall_handler, . - _xtos_syscall_handler
-
-
-#endif /* XCHAL_HAVE_EXCEPTIONS */
-
diff --git a/src/arch/xtensa/up/xtos/exc-table.S b/src/arch/xtensa/up/xtos/exc-table.S
deleted file mode 100644
index db6eaa5..0000000
--- a/src/arch/xtensa/up/xtos/exc-table.S
+++ /dev/null
@@ -1,62 +0,0 @@
-// exc-table.S - general exception C handler table
-
-// Copyright (c) 1999-2010 Tensilica Inc.
-//
-// Permission is hereby granted, free of charge, to any person obtaining
-// a copy of this software and associated documentation files (the
-// "Software"), to deal in the Software without restriction, including
-// without limitation the rights to use, copy, modify, merge, publish,
-// distribute, sublicense, and/or sell copies of the Software, and to
-// permit persons to whom the Software is furnished to do so, subject to
-// the following conditions:
-//
-// The above copyright notice and this permission notice shall be included
-// in all copies or substantial portions of the Software.
-//
-// THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
-// EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
-// MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
-// IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY
-// CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
-// TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
-// SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
-
-#include <xtensa/coreasm.h>
-#include <xtensa/config/specreg.h>
-#include "xtos-internal.h"
-
-
-#if XCHAL_HAVE_EXCEPTIONS
-
- /*
- * Table of exception handlers (in C) for user vectored exceptions.
- * Provides entries for all possible 64 exception causes
- * currently allowed for in the EXCCAUSE register.
- */
- .data
- .global _xtos_c_handler_table
- .align 4
-_xtos_c_handler_table:
- .rept XCHAL_EXCCAUSE_NUM
- .word _xtos_p_none
- .endr
-
- /*
- * Default/empty exception C handler.
- * This is just a placeholder for exception causes with no registered
- * handler; it normally never gets executed.
- * NOTE: control goes first to the debugger if one is present;
- * see _xtos_unhandled_exception in exc-unhandled.S .
- */
- .text
- .align 4
- .global _xtos_p_none
- .type _xtos_p_none,@function
-_xtos_p_none:
- abi_entry
- // Do nothing.
- abi_return
- .size _xtos_p_none, . - _xtos_p_none
-
-#endif /* XCHAL_HAVE_EXCEPTIONS */
-
diff --git a/src/arch/xtensa/up/xtos/exc-unhandled.S b/src/arch/xtensa/up/xtos/exc-unhandled.S
deleted file mode 100644
index 29723ea..0000000
--- a/src/arch/xtensa/up/xtos/exc-unhandled.S
+++ /dev/null
@@ -1,84 +0,0 @@
-// exc-unhandled.S - General Exception Handler for unhandled exceptions
-
-// Copyright (c) 2002-2004, 2006, 2010 Tensilica Inc.
-//
-// Permission is hereby granted, free of charge, to any person obtaining
-// a copy of this software and associated documentation files (the
-// "Software"), to deal in the Software without restriction, including
-// without limitation the rights to use, copy, modify, merge, publish,
-// distribute, sublicense, and/or sell copies of the Software, and to
-// permit persons to whom the Software is furnished to do so, subject to
-// the following conditions:
-//
-// The above copyright notice and this permission notice shall be included
-// in all copies or substantial portions of the Software.
-//
-// THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
-// EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
-// MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
-// IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY
-// CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
-// TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
-// SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
-
-#include <xtensa/coreasm.h>
-#include <xtensa/corebits.h>
-#include <xtensa/config/specreg.h>
-#include "xtos-internal.h"
-#ifdef SIMULATOR
-#include <xtensa/simcall.h>
-#endif
-
-#if XCHAL_HAVE_EXCEPTIONS
-
-/*
- * Assembly-level exception handler used when no handler was
- * registered for the specific exception cause.
- *
- * The BREAK instruction is used to give control to the debugger,
- * if one is present and active. (If none is present and active,
- * the default debug exception handler will typically skip over
- * this break instruction.)
- * This code follows the convention documented in the ISA manual
- * to use BREAK instructions to signal unhandled exceptions to the
- * debugger. For the debugger to report or handle this condition
- * in an OS-independent manner, all processor state (except PC)
- * must be restored as it was when the unhandled exception just
- * occurred (ie. as it was at the beginning of the vector).
- * If execution continues after the BREAK instruction (in which
- * case any register might have been modified by the debugger),
- * just return.
- */
- .text
- .align 4
-
- // If not pulled-in some other way, define it as unhandled:
- .weak _xtos_cause3_handler
- .global _xtos_cause3_handler
-_xtos_cause3_handler:
-
- .global _xtos_unhandled_exception
-_xtos_unhandled_exception:
-#if XCHAL_HAVE_DEBUG || defined(SIMULATOR)
- l32i a2, a1, UEXC_a2 // restore a2
- l32i a3, a1, UEXC_a3 // restore a3
- // Note: a4-a5 not clobbered, no need to restore.
- addi a1, a1, ESF_TOTALSIZE // restore sp
-# if XCHAL_HAVE_DEBUG
- break 1, 1 // give control to the debugger (if any present)
-# else
- wsr a2, EXCSAVE1 // save a2 where simulator expects it
- movi a2, SYS_unhandled_user_exc
- simcall // let simulator/debugger report unhandled exception
- rsr a2, EXCSAVE1 // restore a2
-# endif
- rfe_rfue // if sim/debug resume, just return
-#else /* DEBUG or SIMULATOR */
- j _xtos_unhandled_exception // just loop forever
-#endif /* DEBUG or SIMULATOR */
-
- .size _xtos_unhandled_exception, . - _xtos_unhandled_exception
-
-
-#endif /* XCHAL_HAVE_EXCEPTIONS */
-
diff --git a/src/arch/xtensa/up/xtos/exit.S b/src/arch/xtensa/up/xtos/exit.S
deleted file mode 100644
index af99691..0000000
--- a/src/arch/xtensa/up/xtos/exit.S
+++ /dev/null
@@ -1,80 +0,0 @@
-// exit.S
-//
-// For hardware / boards, this is the default _exit routine called by the
-// C library exit() function. If the program ever exits, we eventually
-// end up here after all C library cleanup (such as closing open files,
-// calling exit callbacks and C++ destructors, etc) is complete.
-
-// Copyright (c) 1998-2013 Tensilica Inc.
-//
-// Permission is hereby granted, free of charge, to any person obtaining
-// a copy of this software and associated documentation files (the
-// "Software"), to deal in the Software without restriction, including
-// without limitation the rights to use, copy, modify, merge, publish,
-// distribute, sublicense, and/or sell copies of the Software, and to
-// permit persons to whom the Software is furnished to do so, subject to
-// the following conditions:
-//
-// The above copyright notice and this permission notice shall be included
-// in all copies or substantial portions of the Software.
-//
-// THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
-// EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
-// MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
-// IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY
-// CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
-// TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
-// SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
-
-#include <xtensa/coreasm.h>
-#include <xtensa/config/core-isa.h>
-#include <xtensa/simcall.h>
-#include "xtos-internal.h"
-
-// Macros to abstract away ABI differences
-#if __XTENSA_CALL0_ABI__
-# define CALL call0
-#else
-# define CALL call4
-#endif
-
-
- .text
- .align 4
- .global _exit
- .type _exit, @function
-_exit:
- abi_entry 0, 4
-
- // sync dirty data to memory before terminating
-#if XCHAL_DCACHE_IS_COHERENT
- CALL xthal_cache_coherence_optout
-#elif XCHAL_DCACHE_IS_WRITEBACK
- CALL xthal_dcache_all_writeback
-#endif
-
- // sync queues (if any, only for LX and later):
-#if XCHAL_HW_MIN_VERSION >= XTENSA_HWVERSION_RA_2004_1 /* LX or later? */
- extw
-#endif
- // can break to debug monitor, go to sleep with waiti, or just spin in a loop
-.L0:
-#if XCHAL_HAVE_HALT
- halt
-#else
-# if XCHAL_HW_MIN_VERSION >= XTENSA_HWVERSION_RE_2013_2 /* SIMCALL is NOP in hw? */
- movi a2, SYS_exit
- simcall // exit if in simulator, else NOP
-# endif
-# if XCHAL_HAVE_DEBUG
- break 1, 15 // back to debugger, if one is attached
-# endif
-# if XCHAL_HAVE_INTERRUPTS
- waiti 15
-# endif
-#endif
- j .L0
- //abi_exit
-
- .size _exit, . - _exit
-
diff --git a/src/arch/xtensa/up/xtos/init.c b/src/arch/xtensa/up/xtos/init.c
deleted file mode 100644
index 065fb08..0000000
--- a/src/arch/xtensa/up/xtos/init.c
+++ /dev/null
@@ -1,64 +0,0 @@
-/* init.c - context initialization */
-
-/*
- * Copyright (c) 1999-2006 Tensilica Inc.
- *
- * Permission is hereby granted, free of charge, to any person obtaining
- * a copy of this software and associated documentation files (the
- * "Software"), to deal in the Software without restriction, including
- * without limitation the rights to use, copy, modify, merge, publish,
- * distribute, sublicense, and/or sell copies of the Software, and to
- * permit persons to whom the Software is furnished to do so, subject to
- * the following conditions:
- *
- * The above copyright notice and this permission notice shall be included
- * in all copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
- * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
- * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
- * IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY
- * CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
- * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
- * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
- */
-
-#include <xtensa/config/core.h>
-#if XCHAL_NUM_CONTEXTS > 1
-#include <stdlib.h>
-#endif
-
-
-
-#if 0 /* XCHAL_NUM_CONTEXTS > 1 */
-extern void _xtos_setup_context(int context_num, SetupInfo *info);
-extern void _xtos_start_context(void);
-
-/*
- * Sets up a context for running code.
- *
- * Returns PC at which to set the new context, or 0 on error.
- */
-unsigned _xtos_init_context(int context_num, int stack_size,
- _xtos_handler_func *start_func, int arg1)
-{
- SetupInfo info;
-
- /* Allocate stack: */
- char *sp;
- char *stack = malloc(stack_size);
- if (stack == NULL)
- return 0;
-
- /* Setup stack for call8: */
- sp = stack + stack_size - 16;
- *(unsigned*)(sp - 12) = (unsigned)(sp + 32);
-
- info.sp = (unsigned)sp;
- info.funcpc = (unsigned)start_func;
- info.arg1 = arg1;
- _xtos_setup_context(context_num, &info);
- return (unsigned) &_xtos_start_context;
-}
-#endif /* multiple contexts */
-
diff --git a/src/arch/xtensa/up/xtos/int-handler.S b/src/arch/xtensa/up/xtos/int-handler.S
deleted file mode 100644
index 3c86252..0000000
--- a/src/arch/xtensa/up/xtos/int-handler.S
+++ /dev/null
@@ -1,59 +0,0 @@
-// int-handler.S - Interrupt Handler Template (for levels > 1)
-// $Id: //depot/main/Xtensa/OS/xtos/inth-template.S#1 $
-
-// Copyright (c) 2003-2004, 2006 Tensilica Inc.
-//
-// Permission is hereby granted, free of charge, to any person obtaining
-// a copy of this software and associated documentation files (the
-// "Software"), to deal in the Software without restriction, including
-// without limitation the rights to use, copy, modify, merge, publish,
-// distribute, sublicense, and/or sell copies of the Software, and to
-// permit persons to whom the Software is furnished to do so, subject to
-// the following conditions:
-//
-// The above copyright notice and this permission notice shall be included
-// in all copies or substantial portions of the Software.
-//
-// THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
-// EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
-// MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
-// IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY
-// CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
-// TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
-// SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
-
-
-// To use this template file, define a macro called _INTERRUPT_LEVEL
-// to be the interrupt priority level of the vector, then include this file.
-// The default Makefile defines _INTERRUPT_LEVEL when assembling this file
-// for each medium and high priority interrupt level.
-
-
-#include <xtensa/coreasm.h>
-#include "xtos-internal.h"
-
-
-#if XCHAL_HAVE_INTERRUPTS
-
-# if INTERRUPT_IS_HI(_INTERRUPT_LEVEL)
-
-# if _INTERRUPT_LEVEL > XTOS_LOCKLEVEL
- /* Not safe to dispatch interrupts in C above XTOS_LOCKLEVEL,
- * so default to assembly high-priority interrupt handlers template
- * in this case (with the default XTOS_LOCKLEVEL this never happens):
- */
-# include "int-highpri-template.S"
-# else
- /* Dispatch high-priority interrupt handlers in C: */
-# include "int-highpri-dispatcher.S"
-# endif
-
-# elif INTERRUPT_IS_MED(_INTERRUPT_LEVEL)
-
-# include "int-medpri-dispatcher.S"
-
-# elif (_INTERRUPT_LEVEL <= XCHAL_NUM_INTLEVELS) && (_INTERRUPT_LEVEL != XCHAL_DEBUGLEVEL)
-# error INTERNAL ERROR: Interrupt priority levels > 1 must be either hi or medium priority!
-# endif
-
-#endif /* XCHAL_HAVE_INTERRUPTS */
diff --git a/src/arch/xtensa/up/xtos/int-highpri-dispatcher.S b/src/arch/xtensa/up/xtos/int-highpri-dispatcher.S
deleted file mode 100644
index 0d52884..0000000
--- a/src/arch/xtensa/up/xtos/int-highpri-dispatcher.S
+++ /dev/null
@@ -1,464 +0,0 @@
-// High-Priority Interrupt Dispatcher Template
-// $Id: //depot/rel/Eaglenest/Xtensa/OS/xtos/int-highpri-dispatcher.S#1 $
-
-// Copyright (c) 2004-2010 Tensilica Inc.
-//
-// Permission is hereby granted, free of charge, to any person obtaining
-// a copy of this software and associated documentation files (the
-// "Software"), to deal in the Software without restriction, including
-// without limitation the rights to use, copy, modify, merge, publish,
-// distribute, sublicense, and/or sell copies of the Software, and to
-// permit persons to whom the Software is furnished to do so, subject to
-// the following conditions:
-//
-// The above copyright notice and this permission notice shall be included
-// in all copies or substantial portions of the Software.
-//
-// THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
-// EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
-// MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
-// IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY
-// CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
-// TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
-// SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
-
-//
-// This file allows writing high-priority interrupt handlers in C,
-// providing convenience at a significant cost in performance.
-//
-// By default, this file is included by inth-template.S .
-// The default Makefile defines _INTERRUPT_LEVEL when assembling
-// inth-template.S for each medium and high priority interrupt level.
-//
-// To use this template file, define a macro called _INTERRUPT_LEVEL
-// to be the interrupt priority level of the vector, then include this file.
-
-
-#include <xtensa/coreasm.h>
-#include "xtos-internal.h"
-
-
-#if XCHAL_HAVE_INTERRUPTS
-
-#define INTERRUPT_MASK XCHAL_INTLEVEL_MASK(_INTERRUPT_LEVEL)
-#define SINGLE_INTERRUPT ((INTERRUPT_MASK & (INTERRUPT_MASK - 1)) == 0)
-#define SINGLE_INT_NUM _INTERRUPT_LEVEL
-
-
-#define INTLEVEL_N_MASK INTERRUPT_MASK // mask of interrupts at this priority
-#define INTLEVEL_N_NUM SINGLE_INT_NUM // interrupt number if there is only one
-#define INTLEVEL_N_BELOW_MASK XCHAL_INTLEVEL_ANDBELOW_MASK(_INTERRUPT_LEVEL)
-
-/* Indicates whether there are multiple interrupts at this interrupt
- * priority, ie. mapped to this interrupt vector.
- * If there is only one, its number is INTLEVEL_N_NUM
- */
-#define MULTIPLE_INTERRUPTS (!SINGLE_INTERRUPT)
-
-/*
- * High priority interrupt stack frame:
- */
-STRUCT_BEGIN
-STRUCT_FIELD (long,4,HESF_,SAR)
-STRUCT_FIELD (long,4,HESF_,WINDOWSTART)
-STRUCT_FIELD (long,4,HESF_,WINDOWBASE)
-STRUCT_FIELD (long,4,HESF_,EPC1)
-STRUCT_FIELD (long,4,HESF_,EXCCAUSE)
-STRUCT_FIELD (long,4,HESF_,EXCVADDR)
-STRUCT_FIELD (long,4,HESF_,EXCSAVE1)
-STRUCT_FIELD (long,4,HESF_,VPRI) /* (XEA1 only) */
-#if XCHAL_HAVE_MAC16
-STRUCT_FIELD (long,4,HESF_,ACCLO)
-STRUCT_FIELD (long,4,HESF_,ACCHI)
-/*STRUCT_AFIELD(long,4,HESF_,MR, 4)*/
-#endif
-#if XCHAL_HAVE_LOOPS
-STRUCT_FIELD (long,4,HESF_,LCOUNT)
-STRUCT_FIELD (long,4,HESF_,LBEG)
-STRUCT_FIELD (long,4,HESF_,LEND)
-#endif
-STRUCT_AFIELD(long,4,HESF_,AREG, 64) /* address registers ar0..ar63 */
-#define HESF_AR(n) HESF_AREG+((n)*4)
-STRUCT_END(HighPriFrame)
-#define HESF_TOTALSIZE HighPriFrameSize+32 /* 32 bytes for interrupted code's save areas under SP */
-
-
-#if XCHAL_HAVE_XEA1 && HAVE_XSR /* could be made true for T1040 and T1050 */
-# error "high-priority interrupt stack frame needs adjustment if HAVE_XSR is allowed with XEA1"
-#endif
-
-
-#define PRI_N_STACK_SIZE 1024 /* default to 1 kB stack for each level-N handling */
-
-
- // Allocate save area and stack:
- // (must use .bss, not .comm, because the subsequent .set does not work otherwise)
- .section .bss, "aw"
- .align 16
-LABEL(_Pri_,_Stack): .space PRI_N_STACK_SIZE + HESF_TOTALSIZE
-
-#if HAVE_XSR
- .data
- .global LABEL(_Pri_,_HandlerAddress)
-LABEL(_Pri_,_HandlerAddress): .space 4
-#endif
-
-
- .text
- .align 4
- .global LABEL(_Level,FromVector)
-LABEL(_Level,FromVector):
- movi a2, LABEL(_Pri_,_Stack) + PRI_N_STACK_SIZE // get ptr to save area
- // interlock
-
- // Save a few registers so we can do some work:
- s32i a0, a2, HESF_AR(0)
-#if HAVE_XSR
- //movi a0, LABEL(_Level,FromVector) // this dispatcher's address
- movi a0, LABEL(_Pri_,_HandlerAddress) // dispatcher address var.
- s32i a1, a2, HESF_AR(1)
- l32i a0, a0, 0 // get dispatcher address
- s32i a3, a2, HESF_AR(3)
- xsr a0, EXCSAVE_LEVEL // get saved a2, restore dispatcher address
-#else
- rsr a0, EXCSAVE_LEVEL // get saved a2
- s32i a1, a2, HESF_AR(1)
- s32i a3, a2, HESF_AR(3)
-#endif
- s32i a4, a2, HESF_AR(4)
- s32i a0, a2, HESF_AR(2)
-
- // Save/restore all exception state
- // (IMPORTANT: this code assumes no general exceptions occur
- // during the execution of this dispatcher until this state
- // is completely saved and from the point it is restored.)
- //
- // Exceptions that may normally occur within the C handler
- // include window exceptions (affecting EPC1), alloca exceptions
- // (affecting EPC1/EXCCAUSE and its handling uses EXCSAVE1),
- // and possibly others depending on the particular C handler
- // (possibly needing save/restore of EXCVADDR; and EXCVADDR
- // is also possibly corrupted by any access thru an auto-refill
- // way on a processor with a full MMU).
- //
- rsr a3, EPC1
- rsr a4, EXCCAUSE
- s32i a3, a2, HESF_EPC1
- s32i a4, a2, HESF_EXCCAUSE
-#if !XCHAL_HAVE_XEA1
- rsr a3, EXCVADDR
- s32i a3, a2, HESF_EXCVADDR
-#endif
- rsr a4, EXCSAVE1
- s32i a4, a2, HESF_EXCSAVE1
-
-#ifdef __XTENSA_WINDOWED_ABI__
- // Save remainder of entire address register file (!):
- movi a0, XCHAL_NUM_AREGS - 8 // how many saved so far
-#endif
-
- s32i a5, a2, HESF_AR(5)
- s32i a6, a2, HESF_AR(6)
- s32i a7, a2, HESF_AR(7)
-
-1: s32i a8, a2, HESF_AR(8)
- s32i a9, a2, HESF_AR(9)
- s32i a10, a2, HESF_AR(10)
- s32i a11, a2, HESF_AR(11)
- s32i a12, a2, HESF_AR(12)
- s32i a13, a2, HESF_AR(13)
- s32i a14, a2, HESF_AR(14)
- s32i a15, a2, HESF_AR(15)
-
-#ifdef __XTENSA_WINDOWED_ABI__
- addi a8, a0, -8
- addi a10, a2, 8*4
- rotw 2
- bnez a0, 1b // loop until done
-
- rotw 2
- // back to original a2 ...
-
- // Save a few other registers required for C:
- rsr a3, WINDOWSTART
- rsr a4, WINDOWBASE
- s32i a3, a2, HESF_WINDOWSTART
- s32i a4, a2, HESF_WINDOWBASE
-
- // Setup window registers for first caller:
- movi a3, 1
- movi a4, 0
- wsr a3, WINDOWSTART
- wsr a4, WINDOWBASE
- rsync
-
- // Note: register window has rotated, ie. a0..a15 clobbered.
-
-#endif /* __XTENSA_WINDOWED_ABI__ */
-
- movi a1, LABEL(_Pri_,_Stack) + PRI_N_STACK_SIZE // get ptr to save area (is also initial stack ptr)
- movi a0, 0 // mark start of call frames in stack
-
- // Critical state saved, a bit more to do to allow window exceptions...
-
- // We now have a C-coherent stack and window state.
- // Still have to fix PS while making sure interrupts stay disabled
- // at the appropriate level (ie. level 2 and below are disabled in this case).
-
-#if XCHAL_HAVE_XEA1
- movi a7, _xtos_intstruct // address of interrupt management globals
- rsilft a3, _INTERRUPT_LEVEL, XTOS_LOCKLEVEL // lockout
- movi a4, ~INTLEVEL_N_BELOW_MASK // mask out all interrupts at this level or lower
- l32i a3, a7, XTOS_VPRI_ENABLED_OFS // read previous _xtos_vpri_enabled
- l32i a5, a7, XTOS_ENABLED_OFS // read _xtos_enabled
- s32i a4, a7, XTOS_VPRI_ENABLED_OFS // set new _xtos_vpri_enabled (mask interrupts as if at _INTERRUPT_LEVEL)
- s32i a3, a1, HESF_VPRI // save previous vpri
- movi a2, 0x50020 // WOE=1, UM=1, INTLEVEL=0
- and a3, a5, a4 // mask out selected interrupts
- wsr a3, INTENABLE // disable all low-priority interrupts
-#else
- // Load PS for C code, clear EXCM (NOTE: this step is different for XEA1):
-# ifdef __XTENSA_CALL0_ABI__
- movi a2, 0x00020 + _INTERRUPT_LEVEL // WOE=0, CALLINC=0, UM=1, INTLEVEL=N, EXCM=0, RING=0
-# else
- movi a2, 0x50020 + _INTERRUPT_LEVEL // WOE=1, CALLINC=1, UM=1, INTLEVEL=N, EXCM=0, RING=0
-# endif
-
-#endif
- wsr a2, PS // update PS to enable window exceptions, etc as per above
- rsync
-
- // Okay, window exceptions can now happen (although we have to call
- // deep before any will happen because we've reset WINDOWSTART).
-
- // Save other state that might get clobbered by C code:
-
-////////////////// COMMON DISPATCH CODE BEGIN
-
- rsr a14, SAR
- s32i a14, a1, HESF_SAR
-#if XCHAL_HAVE_LOOPS
- rsr a14, LCOUNT
- s32i a14, a1, HESF_LCOUNT
- rsr a14, LBEG
- s32i a14, a1, HESF_LBEG
- rsr a14, LEND
- s32i a14, a1, HESF_LEND
-#endif
-#if XCHAL_HAVE_MAC16
- rsr a14, ACCLO
- s32i a14, a1, HESF_ACCLO
- rsr a14, ACCHI
- s32i a14, a1, HESF_ACCHI
-#endif
-
-#if MULTIPLE_INTERRUPTS /* > 1 interrupts at this priority */ // _split_ multi_setup
-#define TABLE_OFS 0
-
- rsr a15, INTERRUPT // mask of pending interrupts
-# if XCHAL_HAVE_XEA1
- l32i a12, a7, XTOS_ENABLED_OFS // mask of enabled interrupts
-# else
- rsr a12, INTENABLE // mask of enabled interrupts
-# endif
- movi a13, INTLEVEL_N_MASK // mask of interrupts at this priority level
- and a15, a15, a12
- and a15, a15, a13 // enabled & pending interrupts at this priority
- _beqz a15, LABEL(Pri_,_spurious) // handle spurious interrupts (eg. level-trig.)
-LABEL(Pri_,_loop): // handle all enabled & pending interrupts
- neg a14, a15
- and a14, a14, a15 // single-out least-significant bit set in mask
- wsr a14, INTCLEAR // clear if edge-trig. or s/w or wr/err (else no effect)
-
- // Compute pointer to interrupt table entry, given mask a14 with single bit set:
-
-# if XCHAL_HAVE_NSA
- movi a12, _xtos_interrupt_table - (32-XCHAL_NUM_INTERRUPTS)*8
- nsau a14, a14 // get index of bit in a14, numbered from msbit
- addx8 a12, a14, a12
-# else /* XCHAL_HAVE_NSA */
- movi a12, _xtos_interrupt_table // pointer to interrupt table
- bltui a14, 0x10000, 1f // in 16 lsbits? (if so, check them)
- addi a12, a12, 16*8 // no, index is at least 16 entries further
- // (the above ADDI expands to an ADDI+ADDMI sequence, +128 is outside its range)
- extui a14, a14, 16,16 // shift right upper 16 bits
-1: bltui a14, 0x100, 1f // in 8 lsbits? (if so, check them)
- addi a12, a12, 8*8 // no, index is at least 8 entries further
- srli a14, a14, 8 // shift right upper 8 bits
-1: bltui a14, 0x10, 1f // in 4 lsbits? (if so, check them)
- addi a12, a12, 4*8 // no, index is at least 4 entries further
- srli a14, a14, 4 // shift right 4 bits
-1: bltui a14, 0x4, 1f // in 2 lsbits? (if so, check them)
- addi a12, a12, 2*8 // no, index is at least 2 entries further
- srli a14, a14, 2 // shift right 2 bits
-1: bltui a14, 0x2, 1f // is it the lsbit?
- addi a12, a12, 1*8 // no, index is one entry further
-1: // done! a12 points to interrupt's table entry
-# endif /* XCHAL_HAVE_NSA */
-
-#else /* !MULTIPLE_INTERRUPTS */
-
-# if XCHAL_HAVE_NSA
-# define TABLE_OFS 8 * (XCHAL_NUM_INTERRUPTS - 1 - INTLEVEL_N_NUM)
-# else
-# define TABLE_OFS 8 * INTLEVEL_N_NUM
-# endif
-
- movi a13, INTLEVEL_N_MASK // (if interrupt is s/w or edge-triggered or write/err only)
- movi a12, _xtos_interrupt_table // get pointer to its interrupt table entry
- wsr a13, INTCLEAR // clear the interrupt (if s/w or edge or wr/err only)
-
-#endif /* ifdef MULTIPLE_INTERRUPTS */
-
- l32i a13, a12, TABLE_OFS + 0 // get pointer to handler from table entry
-#ifdef __XTENSA_CALL0_ABI__
- l32i a2, a12, TABLE_OFS + 4 // pass single argument to C handler
- callx0 a13 // call interrupt's C handler
-#else
- l32i a6, a12, TABLE_OFS + 4 // pass single argument to C handler
- callx4 a13 // call interrupt's C handler
-#endif
-
-#if XCHAL_HAVE_XEA1
- movi a7, _xtos_intstruct // address of interrupt management globals
-#endif
-#if MULTIPLE_INTERRUPTS /* > 1 interrupts at this priority */
- rsr a15, INTERRUPT // get pending interrupts
-# if XCHAL_HAVE_XEA1
- l32i a12, a7, XTOS_ENABLED_OFS // get enabled interrupts
-# else
- rsr a12, INTENABLE // get enabled interrupts
-# endif
- movi a13, INTLEVEL_N_MASK // get mask of interrupts at this priority level
- and a15, a15, a12
- and a15, a15, a13 // pending+enabled interrupts at this priority
- _bnez a15, LABEL(Pri_,_loop) // if any remain, dispatch one
-LABEL(Pri_,_spurious):
-#endif /* MULTIPLE_INTERRUPTS */
-
- // Restore everything, and return.
-
- // Three temp registers are required for this code to be optimal (no interlocks) in
- // T2xxx microarchitectures with 7-stage pipe; otherwise only two
- // registers would be needed.
- //
-#if XCHAL_HAVE_LOOPS
- l32i a13, a1, HESF_LCOUNT
- l32i a14, a1, HESF_LBEG
- l32i a15, a1, HESF_LEND
- wsr a13, LCOUNT
- wsr a14, LBEG
- wsr a15, LEND
-#endif
-
-#if XCHAL_HAVE_MAC16
- l32i a13, a1, HESF_ACCLO
- l32i a14, a1, HESF_ACCHI
- wsr a13, ACCLO
- wsr a14, ACCHI
-#endif
- l32i a15, a1, HESF_SAR
- wsr a15, SAR
-
-////////////////// COMMON DISPATCH CODE END
-
-#if XCHAL_HAVE_XEA1
- // Here, a7 = address of interrupt management globals
- l32i a4, a1, HESF_VPRI // restore previous vpri
- rsil a3, XTOS_LOCKLEVEL // lockout
- l32i a5, a7, XTOS_ENABLED_OFS // read _xtos_enabled
- s32i a4, a7, XTOS_VPRI_ENABLED_OFS // set new _xtos_vpri_enabled
- movi a2, 0x00020 + _INTERRUPT_LEVEL // WOE=0, UM=1, INTLEVEL=N
- and a3, a5, a4 // mask out selected interrupts
- wsr a3, INTENABLE // disable all low-priority interrupts
-#else
- // Load PS for interrupt exit, set EXCM:
- movi a2, 0x00030 + _INTERRUPT_LEVEL // WOE=0, CALLINC=0, UM=1, INTLEVEL=N, EXCM=1, RING=0
-#endif
- wsr a2, PS // update PS to disable window exceptions, etc as per above
- rsync
-
- // NOTE: here for XEA1, restore INTENABLE etc...
-
-#ifdef __XTENSA_WINDOWED_ABI__
- // Restore window registers:
- l32i a2, a1, HESF_WINDOWSTART
- l32i a3, a1, HESF_WINDOWBASE
- wsr a2, WINDOWSTART
- wsr a3, WINDOWBASE
- rsync
- // Note: register window has rotated, ie. a0..a15 clobbered.
-
- // Reload initial stack pointer:
- movi a1, LABEL(_Pri_,_Stack) + PRI_N_STACK_SIZE // - 16
- movi a6, XCHAL_NUM_AREGS - 8 // how many saved so far
- addi a7, a1, -8*4
-
- // Restore entire register file (!):
-
-1:
- addi a14, a6, -8
- addi a15, a7, 8*4
- l32i a4, a15, HESF_AR(4)
- l32i a5, a15, HESF_AR(5)
- l32i a6, a15, HESF_AR(6)
- l32i a7, a15, HESF_AR(7)
- l32i a8, a15, HESF_AR(8)
- l32i a9, a15, HESF_AR(9)
- l32i a10,a15, HESF_AR(10)
- l32i a11,a15, HESF_AR(11)
- rotw 2
- bnez a6, 1b // loop until done
-
- l32i a4, a7, HESF_AR(12)
- l32i a5, a7, HESF_AR(13)
- l32i a6, a7, HESF_AR(14)
- l32i a7, a7, HESF_AR(15)
- rotw 2
-
- // back to original a1 ...
-
-#else /* Call0 ABI: */
-
- l32i a4, a1, HESF_AR(4) // restore general registers
- l32i a5, a1, HESF_AR(5)
- l32i a6, a1, HESF_AR(6)
- l32i a7, a1, HESF_AR(7)
- l32i a8, a1, HESF_AR(8)
- l32i a9, a1, HESF_AR(9)
- l32i a10, a1, HESF_AR(10)
- l32i a11, a1, HESF_AR(11)
- l32i a12, a1, HESF_AR(12)
- l32i a13, a1, HESF_AR(13)
- l32i a14, a1, HESF_AR(14)
- l32i a15, a1, HESF_AR(15)
-
-#endif /* __XTENSA_WINDOWED_ABI__ */
-
- // Restore exception state:
- l32i a2, a1, HESF_EPC1
- l32i a3, a1, HESF_EXCCAUSE
- wsr a2, EPC1
- wsr a3, EXCCAUSE
-#if !XCHAL_HAVE_XEA1
- l32i a2, a1, HESF_EXCVADDR
- wsr a2, EXCVADDR
-#endif
- l32i a3, a1, HESF_EXCSAVE1
- wsr a3, EXCSAVE1
-
- l32i a0, a1, HESF_AR(0)
- l32i a2, a1, HESF_AR(2)
- l32i a3, a1, HESF_AR(3)
- l32i a1, a1, HESF_AR(1)
- rfi _INTERRUPT_LEVEL
-
- .size LABEL(_Level,FromVector), . - LABEL(_Level,FromVector)
-
- // This symbol exists solely for the purpose of being able to pull-in this
- // dispatcher using _xtos_dispatch_level<n>() routines with the tiny-rt LSP:
- .global LABEL(_Level,HandlerLabel)
- .set LABEL(_Level,HandlerLabel), 0
-
-#endif /* XCHAL_HAVE_INTERRUPTS */
-
diff --git a/src/arch/xtensa/up/xtos/int-highpri-template.S b/src/arch/xtensa/up/xtos/int-highpri-template.S
deleted file mode 100644
index 2b9a02e..0000000
--- a/src/arch/xtensa/up/xtos/int-highpri-template.S
+++ /dev/null
@@ -1,154 +0,0 @@
-// High-Priority Interrupt Handler Template
-// $Id: //depot/rel/Eaglenest/Xtensa/OS/xtos/int-highpri-template.S#1 $
-
-// Copyright (c) 2004-2010 Tensilica Inc.
-//
-// Permission is hereby granted, free of charge, to any person obtaining
-// a copy of this software and associated documentation files (the
-// "Software"), to deal in the Software without restriction, including
-// without limitation the rights to use, copy, modify, merge, publish,
-// distribute, sublicense, and/or sell copies of the Software, and to
-// permit persons to whom the Software is furnished to do so, subject to
-// the following conditions:
-//
-// The above copyright notice and this permission notice shall be included
-// in all copies or substantial portions of the Software.
-//
-// THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
-// EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
-// MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
-// IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY
-// CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
-// TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
-// SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
-
-//
-// This file provides skeleton code for writing high-priority interrupt
-// handlers in assembler for performance.
-//
-// By default, this file is included by inth-template.S .
-// The default Makefile defines _INTERRUPT_LEVEL when assembling
-// inth-template.S for each medium and high priority interrupt level.
-//
-// To use this template file, define a macro called _INTERRUPT_LEVEL
-// to be the interrupt priority level of the vector, then include this file.
-
-
-#include <xtensa/coreasm.h>
-#include "xtos-internal.h"
-
-
-#if XCHAL_HAVE_INTERRUPTS
-
-#define INTERRUPT_MASK XCHAL_INTLEVEL_MASK(_INTERRUPT_LEVEL)
-#define SINGLE_INTERRUPT (INTERRUPT_MASK & (INTERRUPT_MASK - 1) == 0)
-#define SINGLE_INT_NUM XCHAL_INTLEVEL_NUM(_INTERRUPT_LEVEL)
-
-
-// NOTE: It is strongly recommended that high-priority
-// interrupt handlers be written in assembly.
-//
-// High-priority interrupt handlers can be written in C,
-// but only at the cost of an unreasonable amount of state
-// save and restore (including the entire physical address
-// register file and others, see int-highpri-dispatcher.S)
-// that makes high-priority interrupt dispatching much slower
-// than for low and medium priority interrupts.
-// (Low and medium priority interrupts are masked by atomic
-// register window operations, so they take advantage of a
-// coherent window state for fast entry. High priority
-// interrupts are not masked by window operations so they
-// can interrupt them, leading to a potentially incoherent
-// window state at the time of the interrupt. Given that
-// high priority handlers must save and restore everything
-// they touch, they end up needing to save and restore the
-// entire window state [physical address register file etc.]
-// and all exception state which they can also interrupt.)
-// See also the Microprocessor Programmer's Guide.
-
-// High-priority interrupts are designed to be very fast and with
-// very low latency.
-// Typical high-priority interrupt service routines are kept
-// relatively small and fast. Either there is little to do,
-// or the routine handles only the necessary high priority
-// activities related to a device and leaves the rest
-// (other more complex and time-consuming activities)
-// to be scheduled later, eg. by triggering a level-one
-// (low-priority) or medium-priority software interrupt whose
-// handler can be written in C for the more extensive processing.
-
-// NOTE: The following handler is just skeleton example
-// code. It is NOT a functional handler. For software, edge-
-// triggered and write-error interrupts, it simply does nothing
-// and return. For other types (timer and level-triggered),
-// this code does not clear the source(s) of interrupt,
-// hence if any interrupt at this priority level are both enabled
-// and triggered, the processor repeatedly takes the interrupt
-// in a loop. This is all okay as a default, because
-// XTOS (and other operating systems) clears the INTENABLE
-// register at startup, requiring the application to
-// enable specific interrupts before they can be taken.
-// So as long as you don't enable any interrupt of this
-// priority level, this example handler will never execute.
-
-// Exports
-.global LABEL(_Level,FromVector)
-
- .data
- .align 4
-LABEL(int,save):
- .space 4 // save area
-
- .text
- .align 4
-LABEL(_Level,FromVector):
- // The vectoring code has already saved a2 in EXCSAVEn.
- // Save any other registers we'll use:
- movi a2, LABEL(int,save)
- s32i a1, a2, 0
- // ... add more as needed (increase save area accordingly) ...
-
- // WRITE YOUR INTERRUPT HANDLING CODE HERE...
-
- // If multiple interrupts are mapped to this priority level,
- // you'll probably need to distinguish which interrupt(s)
- // occurred by reading the INTERRUPT (INTREAD) and
- // INTENABLE registers, and'ing them together, and
- // looking at what bits are set in both.
- // If any of the interrupts are level-triggered, be ready
- // to handle the case where no interrupts are to be handled
- // -- this is called a spurious interrupt, and can happen
- // when the level-triggered interrupt line goes inactive
- // after the interrupt is taken but before the INTERRUPT
- // register is read.
-
- // You'll also normally want to clear the source of
- // the interrupt before returning, to avoid getting
- // the same interrupt again immediately. For illustration,
- // this code clears all software, edge-triggered, and
- // write-error interrupts at this priority level (if any).
- // NOTE: Timer interrupts must be cleared by writing to
- // the corresponding CCOMPAREn register; and level-sensitive
- // interrupts can only be cleared externally, usually by
- // requesting the associated device to do so (in a
- // device-specific manner).
- //
- movi a1, INTERRUPT_MASK
- wsr a1, INTCLEAR
-
- // Restore registers:
- l32i a1, a2, 0
-#if HAVE_XSR
- movi a2, LABEL(_Level,FromVector) // restore handler address
- xsr a2, EXCSAVE_LEVEL
-#else
- rsr a2, EXCSAVE_LEVEL
-#endif
- // ... add more if more are saved above ...
-
- // Return:
- rfi _INTERRUPT_LEVEL
-
- .size LABEL(_Level,FromVector), . - LABEL(_Level,FromVector)
-
-#endif /* XCHAL_HAVE_INTERRUPTS */
diff --git a/src/arch/xtensa/up/xtos/int-initlevel.S b/src/arch/xtensa/up/xtos/int-initlevel.S
deleted file mode 100644
index 2c512f5..0000000
--- a/src/arch/xtensa/up/xtos/int-initlevel.S
+++ /dev/null
@@ -1,59 +0,0 @@
-// int-initlevel.S - Routines used to pull-in interrupt dispatch code
-// in the tiny-rt LSP.
-// $Id: //depot/rel/Eaglenest/Xtensa/OS/xtos/int-initlevel.S#1 $
-
-// Copyright (c) 2006-2010 Tensilica Inc.
-//
-// Permission is hereby granted, free of charge, to any person obtaining
-// a copy of this software and associated documentation files (the
-// "Software"), to deal in the Software without restriction, including
-// without limitation the rights to use, copy, modify, merge, publish,
-// distribute, sublicense, and/or sell copies of the Software, and to
-// permit persons to whom the Software is furnished to do so, subject to
-// the following conditions:
-//
-// The above copyright notice and this permission notice shall be included
-// in all copies or substantial portions of the Software.
-//
-// THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
-// EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
-// MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
-// IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY
-// CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
-// TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
-// SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
-
-
-// To assemble this template file, define a macro called _INTERRUPT_LEVEL
-// to be the interrupt level of the vector. We use the same template for both
-// high-level and medium-level interrupts, but not debug level.
-
-
-#include <xtensa/coreasm.h>
-#include "xtos-internal.h"
-
-
-#if XCHAL_HAVE_INTERRUPTS && (_INTERRUPT_LEVEL <= XCHAL_NUM_INTLEVELS) && (_INTERRUPT_LEVEL != XCHAL_DEBUGLEVEL)
-
- // Nothing to do at runtime. This function only has effect
- // at link-time.
- //
- .text
- .global LABEL(_xtos_dispatch_level,_interrupts)
- .align 4
-LABEL(_xtos_dispatch_level,_interrupts):
- abi_entry
- abi_return
- .size LABEL(_xtos_dispatch_level,_interrupts), . - LABEL(_xtos_dispatch_level,_interrupts)
-
- // This reference is what does the work of pulling-in the
- // relevant interrupt vector at the specified level.
- // This is only needed in the tiny-rt LSP.
- //
-# if _INTERRUPT_LEVEL == 1
- .global _need_level1int_
-# else
- .global LABEL(_Level,Vector)
-# endif
-
-#endif /* XCHAL_HAVE_INTERRUPTS */
diff --git a/src/arch/xtensa/up/xtos/int-lowpri-dispatcher.S b/src/arch/xtensa/up/xtos/int-lowpri-dispatcher.S
deleted file mode 100644
index 71c9a74..0000000
--- a/src/arch/xtensa/up/xtos/int-lowpri-dispatcher.S
+++ /dev/null
@@ -1,807 +0,0 @@
-// Level-one interrupt dispatcher (user vectored handler)
-
-// Copyright (c) 1999-2010 Tensilica Inc.
-//
-// Permission is hereby granted, free of charge, to any person obtaining
-// a copy of this software and associated documentation files (the
-// "Software"), to deal in the Software without restriction, including
-// without limitation the rights to use, copy, modify, merge, publish,
-// distribute, sublicense, and/or sell copies of the Software, and to
-// permit persons to whom the Software is furnished to do so, subject to
-// the following conditions:
-//
-// The above copyright notice and this permission notice shall be included
-// in all copies or substantial portions of the Software.
-//
-// THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
-// EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
-// MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
-// IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY
-// CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
-// TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
-// SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
-
-#include <xtensa/coreasm.h>
-#include <xtensa/config/specreg.h>
-#include "xtos-internal.h"
-#include "interrupt-pri.h"
-
-#if XCHAL_HAVE_EXCEPTIONS && XCHAL_HAVE_INTERRUPTS
-
-
- /*
- * Macros to slightly reduce the number of #if statements in the code:
- */
-
-/* This is set (for #if only) if there is only ONE interrupt configured at level one: */
-# define XTOS_SINGLE_INT defined(XCHAL_INTLEVEL1_NUM)
-
-/* Simplify the #if's around saving and restoring of SAR ('#' is a comment char): */
-# if ((XTOS_SUBPRI_ORDER == XTOS_SPO_ZERO_LO) || (XTOS_INT_FAIRNESS && XTOS_SUBPRI)) && !XTOS_SINGLE_INT
-# define NEEDSAR /* need SAR saved early w/ints locked */
-# define LATESAR # /* need SAR saved late w/ints unlocked */
-# else
-# define NEEDSAR # /* need SAR saved early w/ints locked */
-# define LATESAR /* need SAR saved late w/ints unlocked */
-# endif
-
-/* Simplify the #if's around fairness-specific code ('#' is a comment char): */
-# if XTOS_INT_FAIRNESS
-# define IFFAIR /* for code enabled only for fairness */
-# define NOFAIR # /* for code enabled only without fairness */
-# else
-# define IFFAIR # /* for code enabled only for fairness */
-# define NOFAIR /* for code enabled only without fairness */
-# endif
-/*
- * Note about implementation of "fairness".
- * The fairness mask is meant to represent, among a set of interrupts pending
- * at the same time, which ones haven't yet been serviced. It's to avoid,
- * among interrupts simultaneously pending at the same priority level,
- * servicing an interrupt more than once before servicing another.
- * Without the mask, if we for example just always serviced the lowest
- * numbered pending interrupt, then a lower numbered interrupt might get
- * serviced many times before servicing a higher numbered one, even though
- * they're at the same priority and pending at the same time -- thus an
- * "unfair" situation.
- * The typical way to do this fairly is to loop looking at each interrupt
- * number in sequence, determining whether that interrupt needs servicing,
- * and to repeat looping if at least one interrupt was serviced (or at
- * one remains pending).
- * Using the mask is faster, as we only look at pending interrupts,
- * instead of looping looking at all interrupts.
- */
-
-
- // NOTE: something equivalent to the following vector is executed
- // before entering this handler (see user-vector.S).
-//_UserExceptionVector:
-// addi a1, a1, -ESF_TOTALSIZE // allocate exception stack frame, etc.
-// s32i a2, a1, UEXC_a2
-// s32i a3, a1, UEXC_a3
-// movi a3, _xtos_exc_handler_table
-// rsr a2, EXCCAUSE
-// addx4 a2, a2, a3
-// l32i a2, a2, 0
-// s32i a4, a1, UEXC_a4
-// jx a2 // jump to cause-specific handler
-
- .global _need_user_vector_ // pull-in real user vector (tiny LSP)
-
- .text
- .align 4
- .global _xtos_l1int_handler
-_xtos_l1int_handler:
- // HERE: a2, a3, a4 have been saved to exception stack frame allocated with a1 (sp).
-
- s32i a5, a1, UEXC_a5 // a5 will get clobbered by ENTRY after pseudo-CALL4
- // (a4..a15 spilled as needed; save if modified)
-
-# if XCHAL_HAVE_XEA2
-
- // Set PS fields:
- // EXCM = 0
- // WOE = __XTENSA_CALL0_ABI__ ? 0 : 1
- // UM = 1
- // INTLEVEL = EXCM_LEVEL
- // CALLINC = __XTENSA_CALL0_ABI__ ? 0 : 1
- // OWB = 0 (actual value is a don't care)
-
-# ifdef __XTENSA_CALL0_ABI__
- movi a2, PS_UM|PS_INTLEVEL(XCHAL_EXCM_LEVEL)
-# else
- movi a2, PS_UM|PS_INTLEVEL(XCHAL_EXCM_LEVEL)|PS_WOE|PS_CALLINC(1) // CALL4 emulation
-# endif
- rsr a3, EPC_1
- xsr a2, PS
-
-# ifdef __XTENSA_WINDOWED_ABI__
- // HERE: window overflows enabled, but NOT SAFE because we're not quite
- // in a valid windowed context (haven't restored a1 yet);
- // so don't cause any (by accessing only a0..a3) until we've saved critical state
- // and restored a1 (note: critical state already saved in a2 and a3):
- // NOTE: saved EPC1 before causing any overflows, because overflows corrupt EPC1.
-# endif
-
- s32i a3, a1, UEXC_pc
- s32i a2, a1, UEXC_ps
-
-# else /*if XEA1:*/
-
- // Would need to save & clear LCOUNT only with protection. None here.
- // No need to save EXCVADDR or EXCCAUSE for low-priority interrupts.
-# if 1
- rsr a2, INTERRUPT // read INTERRUPT while PS.INTLEVEL is 1 and INTENABLE is intact
- rsilft a3, 1, XTOS_LOCKLEVEL // lockout
- s32i a2, a1, UEXC_vpri // save for interrupt computation
- rsr a2, INTENABLE
- movi a3, XTOS_UNLOCKABLE_MASK // mask out level one, and high levels covered by XTOS_LOCKLEVEL if any,
- // so we can run at PS.INTLEVEL=0 while manipulating INTENABLE
- s32i a2, a1, UEXC_sar // save old INTENABLE, to handle the spurious interrupt case
- and a3, a2, a3 // mask out selected interrupts
- wsr a3, INTENABLE // disable all interrupts up to and including XTOS_LOCKLEVEL
-# else
- // Using this alternate code requires extensive changes elsewhere;
- // its only advantage is potentially lowered latency of interrupts
- // of priority levels 2 thru XTOS_LOCKLEVEL:
- movi a2, _xtos_intstruct // address of interrupt management globals
- rsilft a3, 1, XTOS_LOCKLEVEL // lockout
- l32i a3, a2, XTOS_VPRI_ENABLED_OFS // read previous _xtos_vpri_enabled
- //interlock
- s32i a3, a1, UEXC_vpri // save previous vpri
- movi a3, ~XCHAL_EXCM_MASK // mask out all low-priority interrupts
- // so we can run at PS.INTLEVEL=0 while ESF allocation not reflected in SP
- //interlock
- s32i a3, a2, XTOS_VPRI_ENABLED_OFS // set new _xtos_vpri_enabled (mask all low-priority interrupts)
- l32i a2, a2, XTOS_ENABLED_OFS // read _xtos_enabled
- //interlock
- and a3, a2, a3 // mask out selected interrupts
- wsr a3, INTENABLE // disable all low-priority interrupts
-# endif
- movi a3, PS_WOE|PS_CALLINC(1)|PS_UM // WOE=1, UM=1, INTLEVEL=0, CALLINC=1 (call4 emul), OWB=(dontcare)=0
-
- // NOTE: could use XSR here if targeting T1040 or T1050 hardware (requiring slight sequence adjustment as for XEA2):
- rsr a2, PS
- rsync //NOT-ISA-DEFINED // wait for WSR to INTENABLE to complete before clearing PS.INTLEVEL
- wsr a3, PS // PS.INTLEVEL=0, effective INTLEVEL (via INTENABLE) is XTOS_LOCKLEVEL (NOTA: LOWPRI_LEVELS)
-
- // HERE: window overflows enabled, but NOT SAFE because we're not quite
- // in a valid windowed context (haven't restored a1 yet...);
- // so don't cause any (keep to a0..a3) until we've saved critical state and restored a1:
-
- // NOTE: MUST SAVE EPC1 before causing any overflows, because overflows corrupt EPC1.
- rsr a3, EPC_1
- s32i a2, a1, UEXC_ps
- s32i a3, a1, UEXC_pc
-
-# endif /* XEA1 */
-
-
-# ifdef __XTENSA_CALL0_ABI__
-
- s32i a0, a1, UEXC_a0 // save the rest of the registers
- s32i a6, a1, UEXC_a6
- s32i a7, a1, UEXC_a7
- s32i a8, a1, UEXC_a8
- s32i a9, a1, UEXC_a9
- s32i a10, a1, UEXC_a10
- s32i a11, a1, UEXC_a11
- s32i a12, a1, UEXC_a12
- s32i a13, a1, UEXC_a13
- s32i a14, a1, UEXC_a14
- s32i a15, a1, UEXC_a15
-# if XTOS_DEBUG_PC
- // TODO: setup return PC for call traceback through interrupt dispatch
-# endif
-
- rsync // wait for WSR to PS to complete
-
-# else /* ! __XTENSA_CALL0_ABI__ */
-
-# if XTOS_CNEST
- l32i a2, a1, ESF_TOTALSIZE-20 // save nested-C-func call-chain ptr
-# endif
- addi a1, a1, ESF_TOTALSIZE // restore sp (dealloc ESF) for sane stack again
- rsync // wait for WSR to PS to complete
-
- /* HERE: we can SAFELY get window overflows.
- *
- * From here, registers a4..a15 automatically get spilled if needed.
- * They become a0..a11 after the ENTRY instruction.
- * Currently, we don't check whether or not these registers
- * get spilled, so we must save and restore any that we
- * modify. We've already saved a4 and a5
- * which we modify as part of the pseudo-CALL.
- *
- * IMPLEMENTATION NOTE:
- *
- * The pseudo-CALL below effectively saves registers a2..a3
- * so that they are available again after the corresponding
- * RETW when returning from the exception handling. We
- * could choose to put something like EPC1 or PS in
- * there, so they're available more quickly when
- * restoring. HOWEVER, exception handlers may wish to
- * change such values, or anything on the exception stack
- * frame, and expect these to be restored as modified.
- *
- * NOTA: future: figure out what's the best thing to put
- * in a2 and a3. (candidate: a4 and a5 below; but what
- * if exception handler manipulates ARs, as in a syscall
- * handler.... oh well)
- *
- *
- * Now do the pseudo-CALL.
- * Make it look as if the code that got the exception made a
- * CALL4 to the exception handling code. (We call
- * this the "pseudo-CALL".)
- *
- * This pseudo-CALL is important and done this way:
- *
- * 1. There are only three ways to safely update the stack pointer
- * in the windowed ABI, such that window exceptions work correctly:
- * (a) spill all live windows to stack then switch to a new stack
- * (or, save the entire address register file and window
- * registers, which is likely even more expensive)
- * (b) use MOVSP (or equivalent)
- * (c) use ENTRY/RETW
- * Doing (a) is excessively expensive, and doing (b) here requires
- * copying 16 bytes back and forth which is also time-consuming;
- * whereas (c) is very efficient, so that's what we do here.
- *
- * 2. Normally we cannot do a pseudo-CALL8 or CALL12 here.
- * According to the
- * windowed ABI, a function must allocate enough space
- * for the largest call that it makes. However, the
- * pseudo-CALL is executed in the context of the
- * function that happened to be executing at the time
- * the interrupt was taken, and that function might or
- * might not have allocated enough stack space for a
- * CALL8 or a CALL12. If we try doing a pseudo-CALL8
- * or -CALL12 here, we corrupt the stack if the
- * interrupted function happened to not have allocated
- * space for such a call.
- *
- * 3. We set the return PC, but it's not strictly
- * necessary for proper operation. It does make
- * debugging, ie. stack tracebacks, much nicer if it
- * can point to the interrupted code (not always
- * possible, eg. if interrupted code is in a different
- * GB than the interrupt handling code, which is
- * unlikely in a system without protection where
- * interrupt handlers and general application code are
- * typically linked together).
- *
- * IMPORTANT: Interrupts must stay disabled while doing the pseudo-CALL,
- * or at least until after the ENTRY instruction, because SP has been
- * restored to its original value that does not reflect the exception
- * stack frame's allocation. An interrupt taken here would
- * corrupt the exception stack frame (ie. allocate another over it).
- * (High priority interrupts can remain enabled, they save and restore
- * all of their state and use their own stack or save area.)
- * For the same reason, we mustn't get any exceptions in this code
- * (other than window exceptions where noted) until ENTRY is done.
- */
-
- // HERE: may get a single window overflow (caused by the following instruction).
-
-# if XTOS_DEBUG_PC
- movi a4, 0xC0000000 // [for debug] for return PC computation below
- or a3, a4, a3 // [for debug] set upper two bits of return PC
- addx2 a4, a4, a3 // [for debug] clear upper bit
-# else
- movi a4, 0 // entry cannot cause overflow, cause it here
-# endif
-
- .global _LevelOneInterrupt
-_LevelOneInterrupt: // this label makes tracebacks through interrupts look nicer
-
- _entry a1, ESF_TOTALSIZE // as if after a CALL4 (PS.CALLINC set to 1 above)
-
- /*
- * The above ENTRY instruction does a number of things:
- *
- * 1. Because we're emulating CALL4, the ENTRY rotates windows
- * forward by 4 registers (as per 'ROTW +1'), so that
- * a4-a15 became a0-a11. So now: a0-a11 are part of
- * the interrupted context to be preserved. a0-a1
- * were already saved above when they were a4-a5.
- * a12-a15 are free to use as they're NOT part of the
- * interrupted context. We don't need to save/restore
- * them, and they will get spilled if needed.
- *
- * 2. Updates SP (new a1), allocating the exception stack
- * frame in the new window, preserving the old a1 in
- * the previous window.
- *
- * 3. The underscore prefix prevents the assembler from
- * automatically aligning the ENTRY instruction on a
- * 4-byte boundary, which could create a fatal gap in
- * the instruction stream.
- *
- * At this point, ie. before we re-enable interrupts, we know the caller is
- * always live so we can safely modify a1 without using MOVSP (we can use MOVSP
- * but it will never cause an ALLOCA or underflow exception here).
- * So this is a good point to modify the stack pointer if we want eg. to
- * switch to an interrupt stack (if we do, we need to save the current SP
- * because certain things have been saved to that exception stack frame).
- * We couldn't do this easily before ENTRY, where the caller wasn't
- * necessarily live.
- */
-
-# if 0 /*... non-nested interrupt ...*/
- mov ...some address register..., a1 // save ptr to original ESF
- movi a1, _interrupt_stack // switch stack
-# endif
-
-# endif /* __XTENSA_CALL0_ABI__ */
-
- /*
- * Now we can enable interrupts of higher virtual priority than the one(s)
- * being dispatched/processed here. This may entail some software prioritization,
- * if so configured.
- * (Pseudo-CALL is complete, and SP reflects allocation of exception stack frame
- * or switch to new stack.)
- */
-
-# if XCHAL_HAVE_XEA2
- rsilft a15, XCHAL_EXCM_LEVEL, 1 // INTERRUPT reg *must* be read at PS.INTLEVEL<=1
- // (otherwise it might get higher pri ints)
-# define CUR_INTLEVEL 1
-# else
-# define CUR_INTLEVEL 0
-# endif
- /* At this point, PS.INTLEVEL is: 0 if XEA1, 1 if XEA2 (per CUR_INTLEVEL) */
-
-
- /***************** Dispatch low-priority interrupts to service *****************/
-
- /* HERE: We may get up to 3 window overflows on the following instruction.
- *
- * The worst case is 3 overflows, two 4-register overflows and one
- * 12-register overflow.
- */
-
-
-# if XTOS_VIRTUAL_INTENABLE
- /*
- * The INTENABLE register is virtualized, because it serves two purposes:
- * controlling which interrupts are active (eg. enabled once a handler
- * is registered) as reflected in _xtos_enabled, and what is the current
- * effective interrupt level as reflected in _xtos_vpri_enabled.
- *
- * The INTENABLE register always contains (_xtos_enabled & _xtos_vpri_enabled).
- * NOTE: It is important that INTENABLE, _xtos_enabled and _xtos_vpri_enabled
- * only be modified when interrupts at XTOS_LOCK_LEVEL and below are disabled,
- * that they never be modified by interrupts at levels above XTOS_LOCK_LEVEL,
- * and that they be consistent and never modified when the current interrupt
- * level is below XTOS_LOCK_LEVEL.
- *
- * NOTE: Reading the INTERRUPT register *must* be done at PS.INTLEVEL <= 1
- * otherwise we might incorrectly see higher priority interrupts.
- */
-
-
- movi a14, _xtos_intstruct // address of interrupt management globals
-# if XCHAL_HAVE_XEA1
- l32i a15, a1, UEXC_vpri // read saved INTERRUPT register value
- l32i a13, a14, XTOS_VPRI_ENABLED_OFS // read previous _xtos_vpri_enabled
- l32i a12, a14, XTOS_ENABLED_OFS // read _xtos_enabled
- and a15, a15, a13 // don't handle ints already being handled
-# else
- rsr a15, INTERRUPT // interrupts pending
- rsr a12, INTENABLE // interrupts enabled (already should equal _xtos_enabled & _xtos_vpri_enabled)
- l32i a13, a14, XTOS_VPRI_ENABLED_OFS // read previous _xtos_vpri_enabled
-# endif
- and a15, a15, a12 // a15 = INTERRUPT & (interrupts we can consider processing)
-NEEDSAR rsr a12, SAR
- s32i a13, a1, UEXC_vpri // save previous vpri
-
- _beqz a15, spurious_int // no interrupt to handle (spurious interrupt)
-NEEDSAR s32i a12, a1, UEXC_sar // note: in XEA1, UEXC_sar must be set *after* beqz above
-
-IFFAIR s32i a2, a1, UEXC_exccause // save a2 (interrupted code's a6)
-IFFAIR movi a2, -1 // initial fairness mask
-
-.L1_loop0:
- // a15 = non-zero mask of interrupt bits to consider handling
-
-# if XTOS_SUBPRI_ORDER == XTOS_SPO_ZERO_HI && !XTOS_INT_FAIRNESS && !XTOS_SUBPRI_GROUPS
- // Special case that can be handled a bit more efficiently:
-
- neg a12, a15 // find lsbit in a15 ...
- and a12, a12, a15 // ...
- // a12 = single bit corresponding to interrupt to be processed (highest pri pending+enabled).
-
- // Compute a13 = new virtual priority based on this selected highest priority interrupt:
- movi a15, ~XCHAL_LOWPRI_MASK // mask of all low-priority interrupts
- addi a13, a12, -1 // mask of interrupts enabled at this new priority
- or a13, a13, a15 // also leave medium- and high-priority interrupts enabled
-
-# else /* special case */
-
- // Entry:
- // a12 = (undefined)
- // a13 = (undefined)
- // a14 = &_xtos_intstruct --or-- interrupt table adjusted base
- // a15 = non-zero mask of interrupt bits to consider handling
- // Exit:
- // a12 = index
- // a13 = (clobbered)
- // a14 = (preserved)
- // a15 = single bit corresponding to index
- //
- indexmask_int a12, a15, a14, a13
-
- // a12 = index of highest priority pending+enabled interrupt, to be processed.
- // a15 = (1 << a12), ie. bit corresponding to interrupt to be processed.
-IFFAIR xor a2, a2, a15 // update fairness mask - mask out this interrupt until recycling mask
- movi a13, _xtos_interrupt_table - IFNSA( (32-XCHAL_NUM_INTERRUPTS)*XIE_SIZE, 0 )
- wsr a15, INTCLEAR // clear interrupt (if software or external edge-triggered or write-error)
- addx8 a12, a12, a13 // a12 = address in interrupt table for given interrupt number
-
-.L1_loop1:
- // a12 now contains pointer to interrupt table entry for interrupt to be processed
- l32i a13, a12, XIE_VPRIMASK // a13 = new vpri (mask of interrupts enabled at this interrupt's priority)
-# endif /* !special case */
-
- // a13 = new virtual priority based on the selected highest priority interrupt
-
- rsilft a15, 1*XCHAL_HAVE_XEA2, XTOS_LOCKLEVEL // lockout
-
- // Now do the equivalent of: prev = _xtos_set_vpri( a13 );
-
- l32i a15, a14, XTOS_ENABLED_OFS // a15 = _xtos_enabled
- s32i a13, a14, XTOS_VPRI_ENABLED_OFS // update new _xtos_vpri_enabled
- and a15, a15, a13 // a15 = _xtos_enabled & _xtos_vpri_enabled
- //NOTE: Here, do: a15 &= ~_xtos_pending if XTOS_VIRTUAL_INTERRUPT is set.
- wsr a15, INTENABLE
- //interlock
- //interlock
- rsync // NOTA - not ISA defined // wait for INTENABLE write to complete before we set PS.INTLEVEL to zero
-
-
- // Okay, we've updated INTENABLE to reflect the new virtual priority (vpri)
- // according to the highest priority pending+enabled (low-priority) interrupt.
-
- // IMPLEMENTATION NOTE - Before we unlock (enable interrupts), we could
- // switch stacks here, now that we have enough free registers through the unlock.
-
- // Now we can enable interrupts via PS.INTLEVEL. (Already done for XEA1.)
-
- rsil a15, 0 // unlock
-# undef CUR_INTLEVEL
-# define CUR_INTLEVEL 0
-
- // HERE: interrupts are enabled again (those interrupts of
- // higher virtual priority than the one we're currently processing).
-
- // HERE:
- // a12 = pointer to interrupt entry in table, or
- // mask of interrupt bit to process (special case only)
- // a13, a15 = available for use
- // a14 = available for use if virtual INTENABLE, else is pointer to interrupt table
-
-# if XTOS_SUBPRI_ORDER == XTOS_SPO_ZERO_HI && !XTOS_INT_FAIRNESS && !XTOS_SUBPRI_GROUPS
- /* In this special case, we moved as much as possible where interrupts are enabled again: */
- // a12 is bit corresponding to interrupt, convert to ptr to interrupt table entry...
- movi a14, _xtos_interrupt_table - IFNSA( (32-XCHAL_NUM_INTERRUPTS)*XIE_SIZE, 0 )
- wsr a12, INTCLEAR // clear interrupt (if software or external edge-triggered or write-error)
-//IFFAIR xor a2, a2, a12 // update fairness mask - mask out this interrupt until recycling mask
- msindex_int a15, a12 // a15 = index of msbit set in a12 (a12 clobbered)
- addx8 a12, a15, a14 // a12 = address in interrupt table for given interrupt number
-# endif /* special case */
-
-
-
-# elif XTOS_SINGLE_INT
- /*
- * Only one interrupt is configured to map to this vector.
- * This simplifies the code considerably -- no checking and resolving of INTERRUPT
- * register required. Just call the handler and exit.
- *
- * (With INTENABLE register virtualization, the simplification is
- * not as great, and not implemented separately above.)
- */
-
-
-# define XTOS_SINGLE_INT_NUM XCHAL_INTLEVEL1_NUM
-# define XTOS_SINGLE_INT_MASK XCHAL_INTLEVEL1_MASK
-# define XTOS_SINGLE_INT_CLEAR ((XTOS_SINGLE_INT_MASK & XCHAL_INTCLEARABLE_MASK) != 0)
-# if XTOS_SINGLE_INT_CLEAR
- movi a13, XCHAL_LOWPRI_MASK // bit to clear in INTERRUPT register
-# endif
- // Get pointer to interrupt table entry for this vector's only interrupt:
- movi a12, _xtos_interrupt_table + MAPINT(XTOS_SINGLE_INT_NUM)*XIE_SIZE
-# if XTOS_SINGLE_INT_CLEAR
- wsr a13, INTCLEAR // clear interrupt pending bit (if software or external-edge-triggered or write-error)
-# endif
-
-
-
-# else /* ie. if !XTOS_VIRTUAL_INTENABLE && !XTOS_SINGLE_INT */
- /*
- * Here, the INTENABLE register is NOT virtualized. There are no _xtos_enabled
- * or _xtos_vpri_enabled global variables to track. INTENABLE simply controls
- * which interrupts are active (eg. enabled once a handler is registered).
- *
- * NOTE: To ensure its coherency, it is still important to only modify the
- * INTENABLE register when interrupts at XTOS_LOCK_LEVEL and below are disabled,
- * that it never be modified by interrupts at levels above XTOS_LOCK_LEVEL,
- * and that it never be modified when the current interrupt level is below
- * XTOS_LOCK_LEVEL. This is because modifications to INTENABLE generally
- * require an RSR/modify/WSR sequence to modify only selected bits.
- *
- * NOTE: Reading the INTERRUPT register *must* be done at PS.INTLEVEL <= 1
- * otherwise we might incorrectly see higher priority interrupts.
- *
- * This option implies XEA2, because XEA1 always requires INTENABLE virtualization.
- * This option also implies SUBPRI is zero (no interrupt sub-prioritization in software).
- */
-
-
- rsr a15, INTERRUPT // interrupts pending
- rsr a13, INTENABLE // interrupts enabled (directly; no virtualization)
- movi a14, _xtos_interrupt_table - IFNSA( (32-XCHAL_NUM_INTERRUPTS)*XIE_SIZE, 0 )
-NEEDSAR rsr a12, SAR
- and a15, a15, a13 // a15 = INTERRUPT & INTENABLE
-
- _beqz a15, spurious_int // no interrupt to handle (spurious interrupt)
-NEEDSAR s32i a12, a1, UEXC_sar
-
-IFFAIR s32i a2, a1, UEXC_exccause // save a2 (interrupted code's a6)
-IFFAIR movi a2, -1 // initial fairness mask
-
-.L1_loop0:
- // Entry:
- // a12 = (undefined)
- // a13 = (undefined)
- // a14 = interrupt table adjusted base (not used here)
- // a15 = non-zero mask of interrupt bits to consider handling
- // Exit:
- // a12 = index
- // a13 = (clobbered)
- // a14 = (preserved)
- // a15 = single bit corresponding to index
- //
- indexmask_int a12, a15, a14_UNUSED, a13
-
- // a12 = index of highest priority pending+enabled interrupt, to be processed.
- // a15 = (1 << a12), ie. bit corresponding to interrupt to be processed.
-IFFAIR xor a2, a2, a15 // update fairness mask - mask out this interrupt until recycling mask
- wsr a15, INTCLEAR // clear interrupt (if software or external edge-triggered or write-error)
-
- addx8 a12, a12, a14 // a12 = address in interrupt table for given interrupt number
-
-.L1_loop1:
- // a12 now contains pointer to interrupt table entry for interrupt to be processed
-
- // HERE:
- // a12 = pointer to interrupt entry in table
- // a13, a15 = available for use
- // a14 = available for use if virtual INTENABLE, else is pointer to interrupt table
-
-
-# endif /* !XTOS_VIRTUAL_INTENABLE && !XTOS_SINGLE_INT */
- /* At this point, PS.INTLEVEL is: 1 if XEA2 and (XTOS_SINGLE_INT || !XTOS_VIRTUAL_INTENABLE), 0 otherwise */
-
- // HERE: a12 = pointer to interrupt entry in table
-
- // (Possible enhancement: do at higher-level, to avoid doing it all the time? !?!?!?)
- save_loops_mac16 a1, a13, a15 // save LOOP & MAC16 regs, if configured
-
-LATESAR rsr a15, SAR
-
-# if 0
- /* ... alternate code to allow context-switching would go here ... */
-# else
- l32i a13, a12, XIE_HANDLER // a13 = address of interrupt handler
-LATESAR s32i a15, a1, UEXC_sar
-# endif
-
-# ifdef __XTENSA_CALL0_ABI__
- mov a14, a2 // save fairness mask
- l32i a2, a12, XIE_ARG // first arg
- mov a3, a1 // second arg, exception stack frame
- callx0 a13 // call interrupt handler
- mov a2, a14 // restore fairness mask
-# else
- mov a15, a1 // second arg, exception stack frame
- l32i a14, a12, XIE_ARG // first argument passed to interrupt handler (relayed by context-dispatcher, if non-nested)
- callx12 a13 // execute interrupt handler, directly or via context-dispatcher (clobbers a12-a15)
-# endif
-
- // (Possible enhancement: do at higher-level, to avoid doing it all the time? !?!?!?)
- restore_loops_mac16 a1, a13, a14, a15 // restore LOOP & MAC16 regs, if configured
-
-LATESAR l32i a12, a1, UEXC_sar
-
-
-# if XTOS_VIRTUAL_INTENABLE
- /* Here, INTENABLE register is virtualized. */
-
- movi a14, _xtos_intstruct // address of interrupt management globals
-LATESAR wsr a12, SAR
-# if XCHAL_HAVE_XEA1
- movi a12, XTOS_UNLOCKABLE_MASK // mask out levels covered by XTOS_LOCKLEVEL
- // so we can run at PS.INTLEVEL=0 (for the RETW below)
- // while manipulating virtual INTENABLE
-# endif
- rsr a15, INTERRUPT
- rsil a13, XTOS_LOCKLEVEL
- l32i a13, a14, XTOS_ENABLED_OFS // a13 = _xtos_enabled
-# if XCHAL_HAVE_XEA1
- and a12, a12, a13 // compute new INTENABLE
- wsr a12, INTENABLE // mask out at XTOS_LOCKLEVEL via INTENABLE
-# endif
- l32i a12, a1, UEXC_vpri // read saved vpri
- //interlock
- and a13, a13, a12 // a13 = old-vpri & _xtos_enabled (INTENABLE value to restore)
- and a15, a15, a13 // what's pending among what we can handle?
-
-
- // a15 now contains the remaining pending+enabled interrupts.
- // NOTE: we MUST NOT consider interrupts potentially already being handled
- // by another interrupt handler that we pre-empted.
- // So we masked with saved vpri, ie. the set of interrupts enabled when we entered
- // this handler, ie. the set of interrupts that can pre-empt the previous context.
-NOFAIR _bnez a15, .L1_loop0 // more interrupt(s) to handle
-IFFAIR _bnez a15, preloop // more interrupt(s) to handle
-IFFAIR l32i a2, a1, UEXC_exccause // restore a2 (interrupted code's a6)
-
-
- // NOTE:
- // Register allocation is why we didn't restore *HERE* the loop regs, MAC16, SAR, etc.
- // (at least part of the reason)
- // We only have one registers (a15), however with 7-stage pipe, three registers
- // are required to avoid interlocks. We could get 2 more registers at 1 cycle each [now only one?],
- // but it isn't obvious whether paying these extra cycles are worth it...
-
- // Restore vpri as it was before we handled the interrupt(s):
- s32i a12, a14, XTOS_VPRI_ENABLED_OFS // restore _xtos_vpri_enabled
-NEEDSAR l32i a12, a1, UEXC_sar
-# if XCHAL_HAVE_XEA1
- s32i a13, a1, UEXC_sar // save new INTENABLE value across RETW
-# else
- wsr a13, INTENABLE // update INTENABLE per original vpri
-
- // NOTE: leave locked, disabling only the low- and medium-priority interrupts
- rsilft a13, XTOS_LOCKLEVEL, XCHAL_EXCM_LEVEL // lockout
-# undef CUR_INTLEVEL
-# define CUR_INTLEVEL XCHAL_EXCM_LEVEL
-# endif
-
-# elif XTOS_SINGLE_INT
-
-# undef NEEDSAR
-# define NEEDSAR
-
-# else /* ie. if !XTOS_VIRTUAL_INTENABLE && !XTOS_SINGLE_INT */
- /* Here, INTENABLE register is NOT virtualized (implies XEA2). */
-
- rsr a15, INTERRUPT // interrupts pending
- rsr a13, INTENABLE // interrupts enabled (directly; no virtualization)
- movi a14, _xtos_interrupt_table - IFNSA( (32-XCHAL_NUM_INTERRUPTS)*XIE_SIZE, 0 )
-LATESAR wsr a12, SAR
- and a15, a15, a13 // a15 = INTERRUPT & INTENABLE
-
- // a15 now contains the remaining pending+enabled interrupts.
- // NOTE: we MUST NOT consider interrupts potentially already being handled
- // by another interrupt handler that we pre-empted.
- // So we masked with saved vpri, ie. the set of interrupts enabled when we entered
- // this handler, ie. the set of interrupts that can pre-empt the previous context.
-NOFAIR _bnez a15, .L1_loop0 // more interrupt(s) to handle
-IFFAIR _bnez a15, preloop // more interrupt(s) to handle
-IFFAIR l32i a2, a1, UEXC_exccause // restore a2 (interrupted code's a6)
-
-
- // NOTE:
- // Register allocation is why we didn't restore *HERE* the loop regs, MAC16, SAR, etc.
- // (at least part of the reason)
- // We only have one registers (a15), however with 7-stage pipe, three registers
- // are required to avoid interlocks. We could get 2 more registers at 1 cycle each [now only one?],
- // but it isn't obvious whether paying these extra cycles are worth it...
-
-NEEDSAR l32i a12, a1, UEXC_sar
-# endif /* !XTOS_VIRTUAL_INTENABLE && !XTOS_SINGLE_INT */
-
-
- /***************************/
-
- // Now exit the handler.
-
- /*
- * Leave interrupts disabled while returning from the pseudo-CALL setup above,
- * for the same reason they were disabled while doing the pseudo-CALL:
- * this sequence restores SP such that it doesn't reflect the allocation
- * of the exception stack frame, which is still needed to return from
- * the exception.
- */
-
-spurious_int:
-
- movi a0, _xtos_return_from_exc
-# ifdef __XTENSA_CALL0_ABI__
-NEEDSAR wsr a12, SAR
- jx a0
-# else /* ! __XTENSA_CALL0_ABI__ */
- // Now return from the pseudo-CALL from the interrupted code, to rotate
- // our windows back...
-
- movi a13, 0xC0000000
-NEEDSAR wsr a12, SAR
- or a0, a0, a13 // set upper two bits
- addx2 a0, a13, a0 // clear upper bit
-
-# if XCHAL_HAVE_XEA2
- // Disable ints during unalloc'ed live stack after RETW below.
- rsil a13, XCHAL_EXCM_LEVEL // might come here via spurious_int, so always rsil
-# endif
-
- retw
-# endif /* __XTENSA_CALL0_ABI__ */
-
-
-
-# if XTOS_INT_FAIRNESS
-preloop:
- // Lowering priority or recycling fairness-mask bits ...
- // a14 = &_xtos_intstruct *or* interrupt table ptr
- // a15 = non-zero mask of interrupt bits to consider handling
-
-# if !XTOS_SUBPRI
- and a13, a15, a2 // a13 = interrupt bits to consider handling, masked for fairness
- movi a12, -1 // (new fairness mask, all one's)
- moveqz a2, a12, a13 // recycle fairness mask if all bits to consider are masked by fairness, and leave a15 intact
- movnez a15, a13, a13 // otherwise set a15 = a13, ie. mask out bits for fairness (a15 is still non-zero)
- j .L1_loop0
-# else /* XTOS_SUBPRI */
- // NOTE: In this case, with SUBPRI, XTOS_VIRTUAL_INTENABLE is always set.
- // So: a14 = &_xtos_intstruct
-
- // Compute a13 = index of highest priority interrupt in a15 (a13 is reversed if NSA present)
- // (a14, a15 preserved; a12 is a temporary):
- index_int a13, a15, a14, a12
-
- // a12 = (available)
- // a13 = index
- // a14 = &_xtos_intstruct
- // a15 = mask of candidates
- movi a12, _xtos_interrupt_table - IFNSA( (32-XCHAL_NUM_INTERRUPTS)*XIE_SIZE, 0 )
- //slot
- addx8 a12, a13, a12 // a12 = address in interrupt table for given interrupt number
- l32i a14, a12, XIE_LEVELMASK // a14 = mask of all interrupts at selected interrupt's level
- and a15, a15, a2 // mask out for fairness
- and a15, a15, a14 // only consider interrupts at highest pending level
- movi a14, _xtos_intstruct // needed at loop0, and below
- _bnez a15, .L1_loop0 // interrupts are allowed by current fairness mask, redo indexing with proper mask (a15, a14 = ...)
-
- // a12 = ptr to interrupt entry
- // a13 = index
- // a14 = &_xtos_intstruct
- // a15 = (available)
-
- // Compute bitmask of interrupt to be processed...
-# if XCHAL_HAVE_NSA
- movi a15, 0x80000000
- ssr a13
- srl a13, a15
-# else
- movi a15, 1
- ssl a13
- sll a13, a15
-# endif
- // a13 = single bit set corresponding to interrupt to be processed...
- l32i a15, a12, XIE_LEVELMASK // a15 = mask of all interrupts at selected interrupt's level
- wsr a13, INTCLEAR // clear interrupt (if software or external edge-triggered or write-error)
- or a2, a2, a15 // recycle fairness mask for selected interrupt level
- xor a2, a2, a13 // update fairness mask - mask out this interrupt until recycling mask
- j .L1_loop1 // handle selected interrupt (a12 = interrupt entry, a14 = &_xtos_intstruct)
-
-# endif /* XTOS_SUBPRI */
-# endif /* XTOS_INT_FAIRNESS */
-
- /* FIXME: what about _LevelOneInterrupt ? */
- .size _xtos_l1int_handler, . - _xtos_l1int_handler
-
-#endif /* XCHAL_HAVE_EXCEPTIONS && XCHAL_HAVE_INTERRUPTS */
-
diff --git a/src/arch/xtensa/up/xtos/int-medpri-dispatcher.S b/src/arch/xtensa/up/xtos/int-medpri-dispatcher.S
deleted file mode 100644
index 1975b65..0000000
--- a/src/arch/xtensa/up/xtos/int-medpri-dispatcher.S
+++ /dev/null
@@ -1,254 +0,0 @@
-// Medium-Priority Interrupt Dispatcher Template
-// $Id: //depot/rel/Eaglenest/Xtensa/OS/xtos/int-medpri-dispatcher.S#1 $
-
-// Copyright (c) 2004-2010 Tensilica Inc.
-//
-// Permission is hereby granted, free of charge, to any person obtaining
-// a copy of this software and associated documentation files (the
-// "Software"), to deal in the Software without restriction, including
-// without limitation the rights to use, copy, modify, merge, publish,
-// distribute, sublicense, and/or sell copies of the Software, and to
-// permit persons to whom the Software is furnished to do so, subject to
-// the following conditions:
-//
-// The above copyright notice and this permission notice shall be included
-// in all copies or substantial portions of the Software.
-//
-// THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
-// EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
-// MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
-// IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY
-// CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
-// TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
-// SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
-
-//
-// By default, this file is included by inth-template.S .
-// The default Makefile defines _INTERRUPT_LEVEL when assembling
-// inth-template.S for each medium and high priority interrupt level.
-//
-// To use this template file, define a macro called _INTERRUPT_LEVEL
-// to be the interrupt priority level of the vector, then include this file.
-
-
-#include <xtensa/coreasm.h>
-#include "xtos-internal.h"
-
-
-#if XCHAL_HAVE_INTERRUPTS
-
-#define INTERRUPT_MASK XCHAL_INTLEVEL_MASK(_INTERRUPT_LEVEL)
-#define SINGLE_INTERRUPT ((INTERRUPT_MASK & (INTERRUPT_MASK - 1)) == 0)
-#define SINGLE_INT_NUM _INTERRUPT_LEVEL
-
-
-// Strict non-preemptive prioritization
-
-
- .text
- .align 4
- .global LABEL(_Level,FromVector)
-LABEL(_Level,FromVector):
-
-/* Allocate an exception stack frame, save a2, a4, and a5, and fix PS as:
- *
- * if not Call0 ABI
- * - enable windowing for 'entry' (ps.woe=1, ps.excm=0)
- * - setup ps.callinc to simulate call4
- * endif
- * - preserve user mode
- * - mask all interrupts at EXCM_LEVEL and lower
- *
- * Then deallocate the stack, 'rsync' for the write to PS, then use
- * 'entry' to re-allocate the stack frame and rotate the register
- * window (like a call4, preserving a0..a3). */
-
-#if HAVE_XSR
- xsr a2, EXCSAVE_LEVEL
-#else
- rsr a2, EXCSAVE_LEVEL
-#endif
- addi a1, a1, -ESF_TOTALSIZE
- s32i a2, a1, UEXC_a2
-#ifdef __XTENSA_CALL0_ABI__
- movi a2, PS_UM|PS_INTLEVEL(XCHAL_EXCM_LEVEL)
-#else
- movi a2, PS_WOE|PS_CALLINC(1)|PS_UM|PS_INTLEVEL(XCHAL_EXCM_LEVEL)
-#endif
- s32i a4, a1, UEXC_a4
- s32i a5, a1, UEXC_a5
- wsr a2, PS
- rsync
-
-#ifdef __XTENSA_CALL0_ABI__
- s32i a0, a1, UEXC_a0
- s32i a3, a1, UEXC_a3
- s32i a6, a1, UEXC_a6
- s32i a7, a1, UEXC_a7
- s32i a8, a1, UEXC_a8
- s32i a9, a1, UEXC_a9
- s32i a10, a1, UEXC_a10
- s32i a11, a1, UEXC_a11
- s32i a12, a1, UEXC_a12
- s32i a13, a1, UEXC_a13
- s32i a14, a1, UEXC_a14
- s32i a15, a1, UEXC_a15
- movi a0, 0 /* terminate stack frames */
-# if XTOS_DEBUG_PC
- // TODO: setup return PC for call traceback through interrupt dispatch
-# endif
-#else
-# if XTOS_CNEST
- l32i a2, a1, ESF_TOTALSIZE-20 // save nested-C-func call-chain ptr
-# endif
- addi a1, a1, ESF_TOTALSIZE
-# if XTOS_DEBUG_PC
- rsr a4, EPC+_INTERRUPT_LEVEL // [for debug] get return PC
- movi a5, 0xC0000000 // [for debug] setup call size...
- or a4, a5, a4 // [for debug] set upper two bits of return PC
- addx2 a4, a5, a4 // [for debug] clear upper bit
-# else
- movi a4, 0 /* terminate stack frames, overflow check */
-# endif
- _entry a1, ESF_TOTALSIZE
-#endif
-
-/* Reset the interrupt level to mask all interrupts at the current
- * priority level and lower. Note the current priority level may be
- * less than or equal to EXCM_LEVEL. */
-
- rsil a15, _INTERRUPT_LEVEL
-
-#if SINGLE_INTERRUPT /* if only one interrupt at this priority level... */
-
-/* Preserve the SAR, loop, and MAC16 regs. Also, clear the interrupt. */
-
- rsr a14, SAR
- movi a12, INTERRUPT_MASK
- s32i a14, a1, UEXC_sar
- wsr a12, INTCLEAR // clear if edge-trig or s/w or wr/err (else no effect)
- save_loops_mac16 a1, a13, a14
-
-/* Load the handler from the table, initialize two args (interrupt
- * number and exception stack frame), then call the interrupt handler.
- * Note: The callx12 preserves the original user task's a4..a15.*/
-
- movi a12, _xtos_interrupt_table + (MAPINT(SINGLE_INT_NUM) * XIE_SIZE)
- l32i a13, a12, XIE_HANDLER
-# ifdef __XTENSA_CALL0_ABI__
- l32i a2, a12, XIE_ARG
- mov a3, a1
- callx0 a13
-# else
- l32i a14, a12, XIE_ARG
- mov a15, a1
- callx12 a13
-# endif
-
-#else /* > 1 interrupts at this priority level */
-
-/* Get bit list of pending interrupts at the current interrupt priority level.
- * If bit list is empty, interrupt is spurious (can happen if a
- * genuine interrupt brings control this direction, but the interrupt
- * goes away before we read the INTERRUPT register). Also save off
- * sar, loops, and mac16 registers. */
-
- rsr a15, INTERRUPT
- rsr a12, INTENABLE
- movi a13, INTERRUPT_MASK
- and a15, a15, a12
- and a15, a15, a13
- rsr a14, SAR
- _beqz a15, LABEL(spurious,int)
- s32i a14, a1, UEXC_sar
- save_loops_mac16 a1, a13, a14
-
-/* Loop to handle all pending interrupts. */
-
-LABEL(.L1,_loop0):
- neg a12, a15
- and a12, a12, a15
- wsr a12, INTCLEAR // clear if edge-trig or s/w or wr/err (else no effect)
- movi a13, _xtos_interrupt_table
- find_ms_setbit a15, a12, a14, 0
- mapint a15
- addx8 a12, a15, a13
- l32i a13, a12, XIE_HANDLER
-# ifdef __XTENSA_CALL0_ABI__
- l32i a2, a12, XIE_ARG
- mov a3, a1
- callx0 a13
-# else
- l32i a14, a12, XIE_ARG
- mov a15, a1
- callx12 a13
-# endif
- rsr a15, INTERRUPT
- rsr a12, INTENABLE
- movi a13, INTERRUPT_MASK
- and a15, a15, a12
- and a15, a15, a13
- _bnez a15, LABEL(.L1,_loop0)
-
-#endif /* SINGLE_INTERRUPT */
-
-/* Restore everything, and return. */
-
- restore_loops_mac16 a1, a13, a14, a15
- l32i a14, a1, UEXC_sar
-LABEL(spurious,int):
-
-#ifdef __XTENSA_CALL0_ABI__
- wsr a14, SAR
- l32i a0, a1, UEXC_a0
- l32i a2, a1, UEXC_a2
- l32i a3, a1, UEXC_a3
- l32i a4, a1, UEXC_a4
- l32i a5, a1, UEXC_a5
- l32i a6, a1, UEXC_a6
- l32i a7, a1, UEXC_a7
- l32i a8, a1, UEXC_a8
- l32i a9, a1, UEXC_a9
- l32i a10, a1, UEXC_a10
- l32i a11, a1, UEXC_a11
- l32i a12, a1, UEXC_a12
- l32i a13, a1, UEXC_a13
- l32i a14, a1, UEXC_a14
- l32i a15, a1, UEXC_a15
- addi a1, a1, ESF_TOTALSIZE // restore sp
- rfi _INTERRUPT_LEVEL
-
-#else /* windowed ABI: */
-
- movi a0, LABEL(return,from_exc)
- movi a13, 0xC0000000
- wsr a14, SAR
- or a0, a0, a13
- addx2 a0, a13, a0
-# if _INTERRUPT_LEVEL < XCHAL_EXCM_LEVEL
-/* Raise the interrupt mask before
- * returning to avoid a race condition where we deallocate the
- * exception stack frame but still have more register values to
- * restore from it. */
- rsil a14, XCHAL_EXCM_LEVEL
-# endif
- retw
-LABEL(return,from_exc):
-# if XTOS_CNEST
- s32i a2, a5, ESF_TOTALSIZE-20 // restore nested-C-func call-chain ptr
-# endif
- l32i a2, a5, UEXC_a2
- l32i a4, a5, UEXC_a4
- l32i a5, a5, UEXC_a5
- rfi _INTERRUPT_LEVEL
-#endif /* windowed ABI */
-
- .size LABEL(_Level,FromVector), . - LABEL(_Level,FromVector)
-
- // This symbol exists solely for the purpose of being able to pull-in this
- // dispatcher using _xtos_dispatch_level<n>() routines with the tiny-rt LSP:
- .global LABEL(_Level,HandlerLabel)
- .set LABEL(_Level,HandlerLabel), 0
-
-#endif /* XCHAL_HAVE_INTERRUPT */
-
diff --git a/src/arch/xtensa/up/xtos/int-sethandler.c b/src/arch/xtensa/up/xtos/int-sethandler.c
deleted file mode 100644
index 98bdb39..0000000
--- a/src/arch/xtensa/up/xtos/int-sethandler.c
+++ /dev/null
@@ -1,116 +0,0 @@
-/* int-sethandler.c - register an interrupt handler in XTOS */
-
-/*
- * Copyright (c) 1999-2006 Tensilica Inc.
- *
- * Permission is hereby granted, free of charge, to any person obtaining
- * a copy of this software and associated documentation files (the
- * "Software"), to deal in the Software without restriction, including
- * without limitation the rights to use, copy, modify, merge, publish,
- * distribute, sublicense, and/or sell copies of the Software, and to
- * permit persons to whom the Software is furnished to do so, subject to
- * the following conditions:
- *
- * The above copyright notice and this permission notice shall be included
- * in all copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
- * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
- * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
- * IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY
- * CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
- * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
- * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
- */
-
-#include <xtensa/config/core.h>
-#include <xtensa/config/specreg.h>
-#include "xtos-internal.h"
-
-
-#if XCHAL_HAVE_INTERRUPTS
-/*
- * Table of interrupt handlers.
- * NOTE: if the NSA/NSAU instructions are configured, then to save
- * a few cycles in the interrupt dispatcher code, the
- * _xtos_interrupt_table[] array is filled in reverse.
- * IMPORTANT: Use the MAPINT() macro defined in xtos-internal.h to index entries in this array.
- */
-extern XtosIntHandlerEntry _xtos_interrupt_table[XCHAL_NUM_INTERRUPTS];
-extern void _xtos_unhandled_interrupt();
-#endif
-
-
-_xtos_handler _xtos_set_interrupt_handler_arg( int n, _xtos_handler f, void *arg )
-{
-#if XCHAL_HAVE_INTERRUPTS
- XtosIntHandlerEntry *entry;
- _xtos_handler old;
-
- if( n < 0 || n >= XCHAL_NUM_INTERRUPTS )
- return 0; /* invalid interrupt number */
- if( Xthal_intlevel[n] > XTOS_LOCKLEVEL )
- return 0; /* priority level too high to safely handle in C */
- entry = _xtos_interrupt_table + MAPINT(n);
- old = entry->handler;
- if (f) {
- entry->handler = f;
- entry->arg = arg;
- } else {
- entry->handler = &_xtos_unhandled_interrupt;
- entry->arg = (void*)n;
- }
- return ((old == &_xtos_unhandled_interrupt) ? 0 : old);
-#else
- return 0;
-#endif
-}
-
-
-_xtos_handler _xtos_set_interrupt_handler( int n, _xtos_handler f )
-{
- return _xtos_set_interrupt_handler_arg( n, f, (void*) n );
-}
-
-
-#if 0
-/*
- * User vector mode exception handler for the LEVEL1_INTERRUPT cause.
- * NOTE: this is now implemented in assembler for performance.
- * This C handler is left as an example interrupt dispatcher written in C.
- * The actual handler in int-lowpri-dispatcher.S is more fully featured.
- */
-UserFrame* _xtos_p_level1int_handler( UserFrame* uf /*, int cause */ )
-{
-#if XCHAL_HAVE_INTERRUPTS
- unsigned int ints;
- unsigned int index;
-
- ints = xthal_get_interrupt();
-# if XTOS_VIRTUAL_INTENABLE
- ints &= _xtos_enabled;
-# else
- ints &= xthal_get_intenable();
-# endif
- for( index = 0 ; ints != 0 ; ints >>= 1, index++ )
- {
- if( ints & 1 )
- {
- void (*f)();
-
- /*
- * Clear interrupt (in case it's edge-triggered or software or write-error).
- * This must be done *before* processing the interrupt.
- */
- xthal_set_intclear( 1 << index );
-
- f = _xtos_interrupt_table[MAPINT(index)].handler;
- if( f )
- f( _xtos_interrupt_table[MAPINT(index)].arg /*, uf, index*/ );
- }
- }
-#endif /*XCHAL_HAVE_INTERRUPTS*/
- return uf;
-}
-#endif
-
diff --git a/src/arch/xtensa/up/xtos/int-vector.S b/src/arch/xtensa/up/xtos/int-vector.S
deleted file mode 100644
index beeb0f4..0000000
--- a/src/arch/xtensa/up/xtos/int-vector.S
+++ /dev/null
@@ -1,70 +0,0 @@
-// int-vector.S - Interrupt Vector Template (for levels > 1)
-// $Id: //depot/rel/Eaglenest/Xtensa/OS/xtos/int-vector.S#2 $
-
-// Copyright (c) 2003-2004, 2006, 2010 Tensilica Inc.
-//
-// Permission is hereby granted, free of charge, to any person obtaining
-// a copy of this software and associated documentation files (the
-// "Software"), to deal in the Software without restriction, including
-// without limitation the rights to use, copy, modify, merge, publish,
-// distribute, sublicense, and/or sell copies of the Software, and to
-// permit persons to whom the Software is furnished to do so, subject to
-// the following conditions:
-//
-// The above copyright notice and this permission notice shall be included
-// in all copies or substantial portions of the Software.
-//
-// THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
-// EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
-// MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
-// IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY
-// CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
-// TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
-// SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
-
-
-// To use this template file, define a macro called _INTERRUPT_LEVEL
-// to be the interrupt level of the vector, include "xtos-internal.h",
-// then include this file. We use the same template for both high-level
-// and medium-level interrupts, but not debug level.
-
-
-#define _ASMLANGUAGE
-#include "xtos-internal.h"
-#include <xtensa/coreasm.h>
-#include <xtensa/config/system.h>
-
-
-#if XCHAL_HAVE_INTERRUPTS && (_INTERRUPT_LEVEL <= XCHAL_NUM_INTLEVELS) && (_INTERRUPT_LEVEL != XCHAL_DEBUGLEVEL)
-
- .begin literal_prefix LABEL(.Level,InterruptVector)
- .section LABEL(.Level,InterruptVector.text), "ax"
- .align 4
- .global LABEL(_Level,Vector)
-LABEL(_Level,Vector):
- // Medium and high priority interrupt vector:
-
- isync_erratum453
-# if HAVE_XSR
- // With XSR, we can use this vector which has the advantage of being ROMable
- // without requiring the handler to also be in ROM; however, it requires
- // initializing the EXCSAVEn register (see ResetEpilog.S) and a slightly
- // different save/restore sequence in the handler:
- xsr a2, EXCSAVE_LEVEL
- jx a2
-
- // Pull-in the real handler by reference, to ensure the reset epilog gets it:
- .global LABEL(_Level,FromVector)
-
-# else
- wsr a2, EXCSAVE_LEVEL
- movi a2, LABEL(_Level,FromVector)
- jx a2
-# endif
-
- .size LABEL(_Level,Vector), . - LABEL(_Level,Vector)
- .text
- .end literal_prefix
-
-#endif /* interrupt at that level */
-
diff --git a/src/arch/xtensa/up/xtos/interrupt-pri.h b/src/arch/xtensa/up/xtos/interrupt-pri.h
deleted file mode 100644
index 41116a5..0000000
--- a/src/arch/xtensa/up/xtos/interrupt-pri.h
+++ /dev/null
@@ -1,178 +0,0 @@
-/* interrupt-pri.h - Definitions and macros related to interrupt prioritization */
-/*
- * Copyright (c) 2002-2004, 2006 Tensilica Inc.
- *
- * Permission is hereby granted, free of charge, to any person obtaining
- * a copy of this software and associated documentation files (the
- * "Software"), to deal in the Software without restriction, including
- * without limitation the rights to use, copy, modify, merge, publish,
- * distribute, sublicense, and/or sell copies of the Software, and to
- * permit persons to whom the Software is furnished to do so, subject to
- * the following conditions:
- *
- * The above copyright notice and this permission notice shall be included
- * in all copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
- * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
- * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
- * IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY
- * CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
- * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
- * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
- */
-
-#if !defined(_ASMLANGUAGE) && !defined(__ASSEMBLER__)
-# error "The interrupt-pri.h header file is meant for inclusion by assembly source code only."
-#endif
-
-#include <xtensa/coreasm.h>
-#include <xtensa/config/specreg.h>
-#include "xtos-internal.h"
-
-/*
- * The following macros are used by int-lowpri-dispatcher.S to
- * implement prioritized interrupt dispatching and fairness.
- * The prioritization scheme is set by XTOS parameters in xtos-params.h .
- */
-
-
-#if XCHAL_HAVE_INTERRUPTS
-
- // msindex_int
- //
- // Return in register \aindex the index of the first (most significant) bit set
- // in register \amask.
- // Register \amask is clobbered (modified) by this macro.
- //
- // Note: this code is similar to the find_ms_setbit macro in <xtensa/coreasm.h>.
- //
- .macro msindex_int aindex, amask
-# if XCHAL_HAVE_NSA
- nsau \aindex, \amask // \aindex = interrupt index, from 0 to 31, from left to right
- //movi \amask, 31
- //sub \aindex, \amask, \aindex
-# else
- movi \aindex, 0 // start with result of 0 (point to lsbit of 32)
-# if XCHAL_NUM_INTERRUPTS > 16
- bltui \amask, 0x10000, 2f // is it one of the 16 lsbits? (if so, check lower 16 bits)
- addi \aindex, \aindex, 16 // no, increment result to upper 16 bits (of 32)
- extui \amask, \amask, 16, 16 // check upper half (shift right 16 bits)
-2:
-# endif
-# if XCHAL_NUM_INTERRUPTS > 8
- bltui \amask, 0x100, 2f // is it one of the 8 lsbits? (if so, check lower 8 bits)
- addi \aindex, \aindex, 8 // no, increment result to upper 8 bits (of 16)
- srli \amask, \amask, 8 // shift right to check upper 8 bits
-2:
-# endif
-# if XCHAL_NUM_INTERRUPTS > 4
- bltui \amask, 0x10, 2f // is it one of the 4 lsbits? (if so, check lower 4 bits)
- addi \aindex, \aindex, 4 // no, increment result to upper 4 bits (of 8)
- srli \amask, \amask, 4 // shift right 4 bits to check upper half
-2:
-# endif
- bltui \amask, 0x4, 2f // is it one of the 2 lsbits? (if so, check lower 2 bits)
- addi \aindex, \aindex, 2 // no, increment result to upper 2 bits (of 4)
- srli \amask, \amask, 2 // shift right 2 bits to check upper half
-2:
- bltui \amask, 0x2, 2f // is it the lsbit?
- addi \aindex, \aindex, 1 // no, increment result to upper bit (of 2)
-2: // done!
-# endif /*!NSA*/
- // HERE: \aindex = index of interrupt to handle
- // \amask is available
- .endm
-
-
- // msindex_int_nc
- //
- // Same as msindex_int, but does not clobber \amask.
- // Uses extra register \atmp (a temporary register) if needed.
- //
- .macro msindex_int_nc aindex, amask, atmp
-# if XCHAL_HAVE_NSA
- msindex_int \aindex, \amask // does not clobber \amask in this case
-# else
- mov \atmp, \amask
- msindex_int \aindex, \atmp
-# endif
- .endm
-
-
- // indexmask_int
- //
- // Compute index of highest priority interrupt in given mask,
- // and trim mask to single bit corresponding to that interrupt.
- // This is used for interrupt dispatching.
- //
- // Entry:
- // \index = (undefined)
- // \mask = non-zero mask of interrupt bits to consider handling
- // \intptr = &_xtos_intstruct if INTENABLE virtualized, else undefined
- // \tmp = (undefined)
- // Exit:
- // \index = index of interrupt (reversed if NSA present)
- // \mask = single bit corresponding to index
- // \intptr = (preserved)
- // \tmp = (clobbered)
- //
- .macro indexmask_int index, mask, intptr, tmp
-# if XTOS_SUBPRI_ORDER == XTOS_SPO_ZERO_LO
-
- msindex_int \index, \mask // \index = index of msbit set in \mask (\tmp is tmp, \mask clobbered)
- // \index now contains the index of the highest priority pending+enabled interrupt.
-# if XCHAL_HAVE_NSA
- movi \mask, 0x80000000
- ssr \index
- srl \mask, \mask // \mask = single bit set corresponding to interrupt to be processed...
-# else
- movi \mask, 1
- ssl \index
- sll \mask, \mask // \mask = single bit set corresponding to interrupt to be processed...
-# endif
-
-# elif XTOS_SUBPRI_ORDER == XTOS_SPO_ZERO_HI
-
- neg \index, \mask // find lsbit in \mask ...
- and \mask, \index, \mask // ...
- msindex_int_nc \index, \mask, \tmp // \index = index of msbit set in \mask (\tmp is tmp, \mask not clobbered)
-
-# else
-# error Unsupported priority ordering.
-# endif /*SUBPRI_ORDER*/
- .endm
-
-
- // index_int
- //
- // Compute index of highest priority interrupt in given mask.
- // This is used for fairness computations.
- //
- // Entry:
- // \index = (undefined)
- // \mask = non-zero mask of interrupt bits to consider handling
- // \intptr = &_xtos_intptr
- // \tmp = (undefined)
- // Exit:
- // \index = index of interrupt (reversed if NSA present)
- // \mask = (preserved)
- // \intptr = (preserved)
- // \tmp = (clobbered)
- //
- .macro index_int index, mask, intptr, tmp
-# if XTOS_SUBPRI_ORDER == XTOS_SPO_ZERO_LO
- msindex_int_nc \index, \mask, \tmp // \index = index of msbit set in \mask (\mask not clobbered)
-# elif XTOS_SUBPRI_ORDER == XTOS_SPO_ZERO_HI
- neg \tmp, \mask // find lsbit in \mask ...
- and \tmp, \tmp, \mask // ...
- msindex_int \index, \tmp // \index = index of msbit set in \tmp (\tmp is clobbered)
-# else
-# error oops
-# endif
- .endm // index_int
-
-
-#endif /* XCHAL_HAVE_INTERRUPTS */
-
-
diff --git a/src/arch/xtensa/up/xtos/interrupt-table.S b/src/arch/xtensa/up/xtos/interrupt-table.S
deleted file mode 100644
index f933fb5..0000000
--- a/src/arch/xtensa/up/xtos/interrupt-table.S
+++ /dev/null
@@ -1,134 +0,0 @@
-// interrupt-table.S - Interrupt handler table and default handler
-
-// Copyright (c) 2004-2010 Tensilica Inc.
-//
-// Permission is hereby granted, free of charge, to any person obtaining
-// a copy of this software and associated documentation files (the
-// "Software"), to deal in the Software without restriction, including
-// without limitation the rights to use, copy, modify, merge, publish,
-// distribute, sublicense, and/or sell copies of the Software, and to
-// permit persons to whom the Software is furnished to do so, subject to
-// the following conditions:
-//
-// The above copyright notice and this permission notice shall be included
-// in all copies or substantial portions of the Software.
-//
-// THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
-// EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
-// MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
-// IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY
-// CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
-// TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
-// SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
-
-#include <xtensa/coreasm.h>
-#include <xtensa/config/specreg.h>
-#include "xtos-internal.h"
-#ifdef SIMULATOR
-#include <xtensa/simcall.h>
-#endif
-
-
-#if XCHAL_HAVE_INTERRUPTS
-
- .data
-
- .global _xtos_intstruct
- .align 8
-_xtos_intstruct:
-# if XTOS_VIRTUAL_INTENABLE
- .global _xtos_enabled
- .type _xtos_enabled,@object
- .size _xtos_enabled,4
- .global _xtos_vpri_enabled
- .type _xtos_vpri_enabled,@object
- .size _xtos_vpri_enabled,4
-_xtos_enabled: .word 0
-_xtos_vpri_enabled: .word 0xFFFFFFFF
-# endif
-# if XTOS_VIRTUAL_INTERRUPT
-# error Virtualized INTERRUPT register not yet supported.
- .global _xtos_pending
- .type _xtos_pending,@object
- .size _xtos_pending,4
-_xtos_pending: .word 0
-# endif
-
- /*
- * Table of C-level interrupt handlers (and args, etc) for each interrupt.
- * NOTE: if the NSA/NSAU instructions are configured, then to save a few
- * cycles in the interrupt dispatcher code, this table is filled in reverse.
- * C code uses the MAPINT() macro defined in xtos-internal.h to index entries.
- * NOTE: Under some conditions (turned off by default in xtos-params.h),
- * this table gets properly initialized by the _xtos_init() function in
- * init.c . NOTA: A future enhancement may be to always configure
- * and build this table at build-time rather than ever doing it at run-time.
- */
-#define i .Li /* workaround a silly GDB testsuite regression */
- .data
- .global _xtos_interrupt_table
- .align 8
-_xtos_interrupt_table:
- .set i, XCHAL_HAVE_NSA*(XCHAL_NUM_INTERRUPTS-1)
- .rept XCHAL_NUM_INTERRUPTS
- .word _xtos_unhandled_interrupt
- .word i // parameter: interrupt number
- .set i, i+1-(XCHAL_HAVE_NSA*2)
- .endr
-
-# if XIE_EXTEND
- /* MUST *IMMEDIATELY* follow _xtos_interrupt_table: */
- .global _xtos_interrupt_mask_table
-_xtos_interrupt_mask_table:
- .set i, XCHAL_HAVE_NSA*(XCHAL_NUM_INTERRUPTS-1)
- .rept XCHAL_NUM_INTERRUPTS
- /* Default to all low-priority (level-one) interrupts at their own virtual priority: */
-# if XTOS_SUBPRI_ORDER == XTOS_SPO_ZERO_HI
- .word ((1<<i)-1) | ~XCHAL_LOWPRI_MASK // vpri_mask default - lower-numbered ints (and high/medium-pri ints) pre-empt other low-pri ints
-# else
- .word (-2*(1<<i)) | ~XCHAL_LOWPRI_MASK // vpri_mask default - higher-numbered ints (and high/medium-pri ints) pre-empt other low-pri ints
-# endif
- .word (1<<i) // level_mask default - each low-pri (level-one) interrupt at its own subpriority
- .set i, i+1-(XCHAL_HAVE_NSA*2)
- .endr
-# endif /*XIE_EXTEND*/
-
-#endif /* XCHAL_HAVE_INTERRUPTS */
-
- .text
-
-
-
-#if XCHAL_HAVE_INTERRUPTS
-
- //
- // void _xtos_unhandled_interrupt( int n );
- //
- // Default/empty interrupt handler.
- // This is used for interrupts with no registered handler.
- // Parameter n is the interrupt number (0 thru 31).
- //
- .text
- .align 4
- .global _xtos_unhandled_interrupt
- .type _xtos_unhandled_interrupt,@function
-_xtos_unhandled_interrupt:
- abi_entry
-# if XCHAL_HAVE_DEBUG
- // Break into the debugger if one is present and active:
-# if XCHAL_NUM_INTLEVELS > XCHAL_DEBUGLEVEL
- rsil a3, XCHAL_DEBUGLEVEL-1 // ensure break takes effect
-# endif
- break 1, 15 // unhandled (unregistered) interrupt $a2
-//# elif defined(SIMULATOR)
-// addmi a2, a2, SYS_unhandled_interrupt ...
-// simcall // unhandled interrupt
-# else
-1: j 1b // unhandled interrupt - loop forever
-# endif
- abi_return
-
- .size _xtos_unhandled_interrupt, . - _xtos_unhandled_interrupt
-
-#endif /* XCHAL_HAVE_INTERRUPTS */
-
diff --git a/src/arch/xtensa/up/xtos/intlevel-restore.S b/src/arch/xtensa/up/xtos/intlevel-restore.S
deleted file mode 100644
index a1490e8..0000000
--- a/src/arch/xtensa/up/xtos/intlevel-restore.S
+++ /dev/null
@@ -1,92 +0,0 @@
-// intlevel-restore.S - Interrupt related assembler code - _xtos_restore_intlevel
-
-// Copyright (c) 2004-2010 Tensilica Inc.
-//
-// Permission is hereby granted, free of charge, to any person obtaining
-// a copy of this software and associated documentation files (the
-// "Software"), to deal in the Software without restriction, including
-// without limitation the rights to use, copy, modify, merge, publish,
-// distribute, sublicense, and/or sell copies of the Software, and to
-// permit persons to whom the Software is furnished to do so, subject to
-// the following conditions:
-//
-// The above copyright notice and this permission notice shall be included
-// in all copies or substantial portions of the Software.
-//
-// THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
-// EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
-// MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
-// IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY
-// CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
-// TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
-// SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
-
-#include <xtensa/coreasm.h>
-#include <xtensa/config/specreg.h>
-#include "xtos-internal.h"
-
-
-/***************************************************************************
- * void _xtos_restore_intlevel(unsigned restoreval);
- *
- * _xtos_restore_intlevel() restores the current interrupt level
- * according to a value returned by _xtos_set_intlevel() or
- * _xtos_set_min_intlevel() (or one of the corresponding macros).
- *
- * NOTE: In XEA2, this function may restore the entire PS register, not
- * just the PS.INTLEVEL field. If some other PS field(s) must be changed
- * and kept intact across restoring PS.INTLEVEL (this is generally unlikely),
- * use the XTOS_RESTORE_JUST_INTLEVEL() macro instead (which is slower).
- *
- * NOTE: In XEA1, this function is implemented further below, identically
- * to _xtos_set_vpri().
- *
- * NOTE: The macro form of this function (XTOS_RESTORE_INTLEVEL())
- * is recommended (for XEA2 configs or where the config is unknown)
- * because it may be more efficient.
- */
-
- .text
- .global _xtos_restore_intlevel
- .type _xtos_restore_intlevel,@function
-#if XCHAL_HAVE_XEA2
- .align 4
-_xtos_restore_intlevel:
- abi_entry
-# if XCHAL_HAVE_INTERRUPTS
- wsr a2, PS // restore PS
- rsync // wait for WSR to PS to complete
-# endif
- abi_return
- .size _xtos_restore_intlevel, . - _xtos_restore_intlevel
-#endif
-
-
-
-/***************************************************************************
- * _xtos_set_vpri() is used to set the current virtual priority from C code;
- * it can be called from the application or from a C interrupt handler.
- */
-
- .global _xtos_set_vpri
- .type _xtos_set_vpri,@function
- .align 4
-_xtos_set_vpri:
-#if XCHAL_HAVE_XEA1
-_xtos_restore_intlevel:
-#endif
- abi_entry
-#if XCHAL_HAVE_INTERRUPTS && XTOS_VIRTUAL_INTENABLE
- mov a3, a2
- movi a4, _xtos_intstruct
- xtos_lock a7 // MUST USE highest address register of function to avoid window overflows in critical section
- l32i a2, a4, XTOS_VPRI_ENABLED_OFS // return old xtos_vpri_enabled (current vpri)
- l32i a5, a4, XTOS_ENABLED_OFS // a3 = xtos_enabled
- s32i a3, a4, XTOS_VPRI_ENABLED_OFS // set new xtos_vpri_enabled (current vpri)
- and a5, a5, a3 // a5 = xtos_enabled & xtos_vpri_enabled
- wsr a5, INTENABLE
- xtos_unlock a7
-#endif /*XCHAL_HAVE_INTERRUPTS*/
- abi_return
- .size _xtos_set_vpri, . - _xtos_set_vpri
-
diff --git a/src/arch/xtensa/up/xtos/intlevel-set.S b/src/arch/xtensa/up/xtos/intlevel-set.S
deleted file mode 100644
index 33167a7..0000000
--- a/src/arch/xtensa/up/xtos/intlevel-set.S
+++ /dev/null
@@ -1,79 +0,0 @@
-// intlevel-set.S - Interrupt related assembler code - _xtos_set_intlevel
-
-// Copyright (c) 2004-2010 Tensilica Inc.
-//
-// Permission is hereby granted, free of charge, to any person obtaining
-// a copy of this software and associated documentation files (the
-// "Software"), to deal in the Software without restriction, including
-// without limitation the rights to use, copy, modify, merge, publish,
-// distribute, sublicense, and/or sell copies of the Software, and to
-// permit persons to whom the Software is furnished to do so, subject to
-// the following conditions:
-//
-// The above copyright notice and this permission notice shall be included
-// in all copies or substantial portions of the Software.
-//
-// THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
-// EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
-// MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
-// IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY
-// CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
-// TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
-// SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
-
-#include <xtensa/coreasm.h>
-#include <xtensa/config/specreg.h>
-#include "xtos-internal.h"
-
-
-/***************************************************************************
- * unsigned _xtos_set_intlevel(int intlevel);
- *
- * _xtos_set_intlevel() is used to set the current priority from C code;
- * it can be called from the application or from a C interrupt handler.
- *
- * NOTE: This version allows the 'intlevel' parameter to be computed
- * at run-time, and thus is longer. It is much more efficient, and
- * highly recommented, to use the XTOS_SET_INTLEVEL(intlevel) macro instead
- * (which requires a constant intlevel).
- */
-
- .text
- .align 4
- .global _xtos_set_intlevel
- .type _xtos_set_intlevel,@function
-_xtos_set_intlevel:
- abi_entry
-#if XCHAL_HAVE_INTERRUPTS
-# if XCHAL_HAVE_XEA2
- /* In XEA2, we can simply safely set PS.INTLEVEL directly: */
- rsr a3, PS // get old (current) PS.INTLEVEL
- movi a4, ~0xF
- extui a2, a2, 0, 4 // keep only INTLEVEL bits of parameter
- and a4, a4, a3 // mask out PS.INTLEVEL
- or a4, a4, a2 // insert requested INTLEVEL
- wsr a4, PS // update PS.INTLEVEL
- extui a2, a3, 0, 4 // return only old PS.INTLEVEL field
- rsync // wait for WSR to PS to complete
-# else
- /* In XEA1, we have to rely on INTENABLE register virtualization: */
- movi a4, Xthal_intlevel_andbelow_mask
- extui a3, a2, 0, 4 // keep only INTLEVEL bits of parameter
- addx4 a5, a3, a4 // index mask to use
- l32i a3, a5, 0 // get mask of interrupts at requested intlevel and below
- movi a5, -1 // all 1's
- movi a4, _xtos_intstruct
- xor a3, a3, a5 // mask of interrupts at intlevels above the requested one (to enable)
- xtos_lock a7 // MUST USE highest address register of function to avoid window overflows in critical section
- l32i a2, a4, XTOS_VPRI_ENABLED_OFS // return old xtos_vpri_enabled (current vpri)
- l32i a5, a4, XTOS_ENABLED_OFS // a5 = xtos_enabled
- s32i a3, a4, XTOS_VPRI_ENABLED_OFS // set new xtos_vpri_enabled (current vpri)
- and a5, a5, a3 // a5 = xtos_enabled & xtos_vpri_enabled
- wsr a5, INTENABLE
- xtos_unlock a7
-# endif
-#endif /*XCHAL_HAVE_INTERRUPTS*/
- abi_return
-
- .size _xtos_set_intlevel, . - _xtos_set_intlevel
-
diff --git a/src/arch/xtensa/up/xtos/intlevel-setmin.S b/src/arch/xtensa/up/xtos/intlevel-setmin.S
deleted file mode 100644
index 72530fd..0000000
--- a/src/arch/xtensa/up/xtos/intlevel-setmin.S
+++ /dev/null
@@ -1,84 +0,0 @@
-// intlevel-setmin.S - Interrupt related assembler code - _xtos_set_min_intlevel
-
-// Copyright (c) 2004-2010 Tensilica Inc.
-//
-// Permission is hereby granted, free of charge, to any person obtaining
-// a copy of this software and associated documentation files (the
-// "Software"), to deal in the Software without restriction, including
-// without limitation the rights to use, copy, modify, merge, publish,
-// distribute, sublicense, and/or sell copies of the Software, and to
-// permit persons to whom the Software is furnished to do so, subject to
-// the following conditions:
-//
-// The above copyright notice and this permission notice shall be included
-// in all copies or substantial portions of the Software.
-//
-// THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
-// EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
-// MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
-// IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY
-// CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
-// TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
-// SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
-
-#include <xtensa/coreasm.h>
-#include <xtensa/config/specreg.h>
-#include "xtos-internal.h"
-
-
-/***************************************************************************
- * unsigned _xtos_set_min_intlevel(int intlevel);
- *
- * _xtos_set_min_intlevel() is identical to _xtos_set_intlevel() except
- * that it will not lower the current interrupt level. Instead,
- * it ensures that the current interrupt level is at least as high
- * as specified.
- *
- * NOTE: This version allows the 'intlevel' parameter to be computed
- * at run-time, and thus is longer. It is much more efficient, and
- * highly recommented, to use the XTOS_SET_MIN_INTLEVEL(intlevel) macro instead
- * (which requires a constant intlevel).
- */
-
- .text
- .align 4
- .global _xtos_set_min_intlevel
- .type _xtos_set_min_intlevel,@function
-_xtos_set_min_intlevel:
- abi_entry
-#if XCHAL_HAVE_INTERRUPTS
-# if XCHAL_HAVE_XEA2
- /* In XEA2, we can simply safely set PS.INTLEVEL directly: */
- extui a3, a2, 0, 4 // keep only INTLEVEL bits of parameter
- rsr a2, PS // get old (current) PS.INTLEVEL
- movi a4, ~0xF
- extui a5, a2, 0, 4 // look at old PS.INTLEVEL
- sub a5, a3, a5 // new.intlevel - old.intlevel
- and a4, a4, a2 // mask out PS.INTLEVEL
- or a4, a4, a3 // insert requested INTLEVEL
- movltz a4, a2, a5 // keep same PS if already higher than requested
- wsr a4, PS // update PS.INTLEVEL
- rsync // wait for WSR to PS to complete
-# else
- /* In XEA1, we have to rely on INTENABLE register virtualization: */
- movi a4, Xthal_intlevel_andbelow_mask
- extui a3, a2, 0, 4 // keep only INTLEVEL bits of parameter
- addx4 a5, a3, a4 // index mask to use
- l32i a3, a5, 0 // get mask of interrupts at requested intlevel and below
- movi a5, -1 // all 1's
- movi a4, _xtos_intstruct
- xor a3, a3, a5 // mask of interrupts at intlevels above the requested one (to enable)
- xtos_lock a7 // MUST USE highest address register of function to avoid window overflows in critical section
- l32i a2, a4, XTOS_VPRI_ENABLED_OFS // return old xtos_vpri_enabled (current vpri)
- l32i a5, a4, XTOS_ENABLED_OFS // a5 = xtos_enabled
- and a3, a3, a2 // make sure we don't enable any new interrupts
- s32i a3, a4, XTOS_VPRI_ENABLED_OFS // set new xtos_vpri_enabled (current vpri)
- and a5, a5, a3 // a5 = xtos_enabled & xtos_vpri_enabled
- wsr a5, INTENABLE
- xtos_unlock a7
-# endif
-#endif /*XCHAL_HAVE_INTERRUPTS*/
- abi_return
-
- .size _xtos_set_min_intlevel, . - _xtos_set_min_intlevel
-
diff --git a/src/arch/xtensa/up/xtos/ints-off.S b/src/arch/xtensa/up/xtos/ints-off.S
deleted file mode 100644
index 01cc32d..0000000
--- a/src/arch/xtensa/up/xtos/ints-off.S
+++ /dev/null
@@ -1,74 +0,0 @@
-// ints-off.S - Interrupt related assembler code - _xtos_ints_off
-
-// Copyright (c) 2004-2010 Tensilica Inc.
-//
-// Permission is hereby granted, free of charge, to any person obtaining
-// a copy of this software and associated documentation files (the
-// "Software"), to deal in the Software without restriction, including
-// without limitation the rights to use, copy, modify, merge, publish,
-// distribute, sublicense, and/or sell copies of the Software, and to
-// permit persons to whom the Software is furnished to do so, subject to
-// the following conditions:
-//
-// The above copyright notice and this permission notice shall be included
-// in all copies or substantial portions of the Software.
-//
-// THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
-// EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
-// MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
-// IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY
-// CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
-// TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
-// SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
-
-#include <xtensa/coreasm.h>
-#include <xtensa/config/specreg.h>
-#include "xtos-internal.h"
-
-
-/***************************************************************************
- * _xtos_ints_on() and _xtos_ints_off() are used
- * to enable and disable interrupts from C code;
- * they can be called from the application or from a C interrupt handler.
- */
-
-// u32 _xtos_ints_off( u32 mask ); [T1050.0 docs this as returning old INTENABLE value]
-// Disables a set of interrupts. See _xtos_ints_on().
-//
-// MUST NOT be called when PS.INTLEVEL > XTOS_LOCKLEVEL
-// (otherwise PS.INTLEVEL gets lowered; and operation may be inconsistent
-// if this is called in the handler of an interrupt of level > LOCKLEVEL).
-//
- .text
- .align 4
- .global _xtos_ints_off
- .type _xtos_ints_off,@function
-_xtos_ints_off:
- abi_entry
-#if XCHAL_HAVE_INTERRUPTS
-# if XTOS_VIRTUAL_INTENABLE
- movi a4, _xtos_intstruct
- xtos_lock a7 // MUST USE highest address register of function to avoid window overflows in critical section
- l32i a3, a4, XTOS_ENABLED_OFS // a3 = xtos_enabled
- l32i a6, a4, XTOS_VPRI_ENABLED_OFS // a6 = xtos_vpri_enabled
- or a5, a3, a2 // a5 = xtos_enabled | mask
- xor a5, a5, a2 // a5 = xtos_enabled & ~mask
- s32i a5, a4, XTOS_ENABLED_OFS // xtos_enabled &= ~mask
- and a5, a5, a6 // a5 = xtos_enabled & xtos_vpri_enabled
-# else
- xtos_lock a7 // MUST USE highest address register of function to avoid window overflows in critical section
- rsr a3, INTENABLE
- //interlock
- or a5, a3, a2 // a5 = INTENABLE | mask
- xor a5, a5, a2 // a5 = INTENABLE & ~mask
-# endif
- wsr a5, INTENABLE
- xtos_unlock a7
- mov a2, a3 // return previous (virtual or real) INTENABLE value
-#else /*XCHAL_HAVE_INTERRUPTS*/
- movi a2, 0 // this config does not have interrupts, so return 0
-#endif /*XCHAL_HAVE_INTERRUPTS*/
- abi_return
-
- .size _xtos_ints_off, . - _xtos_ints_off
-
diff --git a/src/arch/xtensa/up/xtos/ints-on.S b/src/arch/xtensa/up/xtos/ints-on.S
deleted file mode 100644
index 1225e4b..0000000
--- a/src/arch/xtensa/up/xtos/ints-on.S
+++ /dev/null
@@ -1,75 +0,0 @@
-// ints-on.S - Interrupt related assembler code - _xtos_ints_on
-
-// Copyright (c) 2004-2010 Tensilica Inc.
-//
-// Permission is hereby granted, free of charge, to any person obtaining
-// a copy of this software and associated documentation files (the
-// "Software"), to deal in the Software without restriction, including
-// without limitation the rights to use, copy, modify, merge, publish,
-// distribute, sublicense, and/or sell copies of the Software, and to
-// permit persons to whom the Software is furnished to do so, subject to
-// the following conditions:
-//
-// The above copyright notice and this permission notice shall be included
-// in all copies or substantial portions of the Software.
-//
-// THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
-// EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
-// MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
-// IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY
-// CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
-// TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
-// SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
-
-#include <xtensa/coreasm.h>
-#include <xtensa/config/specreg.h>
-#include "xtos-internal.h"
-
-
-/***************************************************************************
- * _xtos_ints_on() and _xtos_ints_off() are used
- * to enable and disable interrupts from C code;
- * they can be called from the application or from a C interrupt handler.
- */
-
-
-// u32 _xtos_ints_on( u32 mask );
-// Enables a set of interrupts.
-// With INTENABLE virtualizing, does not simply set INTENABLE directly, but rather
-// computes it as a function of the current virtual priority.
-//
-// MUST NOT be called when PS.INTLEVEL > XTOS_LOCKLEVEL
-// (otherwise PS.INTLEVEL gets lowered; and operation may be inconsistent
-// if this is called in the handler of an interrupt of level > LOCKLEVEL).
-//
- .text
- .align 4
- .global _xtos_ints_on
- .type _xtos_ints_on,@function
-_xtos_ints_on:
- abi_entry
-#if XCHAL_HAVE_INTERRUPTS
-# if XTOS_VIRTUAL_INTENABLE
- movi a4, _xtos_intstruct
- xtos_lock a7 // MUST USE highest address register of function to avoid window overflows in critical section
- l32i a3, a4, XTOS_ENABLED_OFS // a3 = xtos_enabled
- l32i a6, a4, XTOS_VPRI_ENABLED_OFS // a6 = xtos_vpri_enabled
- or a5, a3, a2 // xtos_enabled | mask
- s32i a5, a4, XTOS_ENABLED_OFS // xtos_enabled |= mask
- and a5, a5, a6 // a5 = xtos_enabled & xtos_vpri_enabled
-# else
- xtos_lock a7 // MUST USE highest address register of function to avoid window overflows in critical section
- rsr a3, INTENABLE
- //interlock
- or a5, a3, a2 // INTENABLE | mask
-# endif
- wsr a5, INTENABLE
- xtos_unlock a7
- mov a2, a3 // return previous (virtual or real) INTENABLE value
-#else /*XCHAL_HAVE_INTERRUPTS*/
- movi a2, 0 // this config does not have interrupts, so return 0
-#endif /*XCHAL_HAVE_INTERRUPTS*/
- abi_return
-
- .size _xtos_ints_on, . - _xtos_ints_on
-
diff --git a/src/arch/xtensa/up/xtos/kernel-vector.S b/src/arch/xtensa/up/xtos/kernel-vector.S
deleted file mode 100644
index 11aa473..0000000
--- a/src/arch/xtensa/up/xtos/kernel-vector.S
+++ /dev/null
@@ -1,79 +0,0 @@
-// kernel-vector.S - Kernel Vector for General Exceptions
-// $Id: //depot/rel/Eaglenest/Xtensa/OS/xtos/kernel-vector.S#2 $
-
-// Copyright (c) 1999-2002, 2004, 2006, 2010 Tensilica Inc.
-//
-// Permission is hereby granted, free of charge, to any person obtaining
-// a copy of this software and associated documentation files (the
-// "Software"), to deal in the Software without restriction, including
-// without limitation the rights to use, copy, modify, merge, publish,
-// distribute, sublicense, and/or sell copies of the Software, and to
-// permit persons to whom the Software is furnished to do so, subject to
-// the following conditions:
-//
-// The above copyright notice and this permission notice shall be included
-// in all copies or substantial portions of the Software.
-//
-// THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
-// EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
-// MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
-// IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY
-// CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
-// TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
-// SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
-
-/*
- * General exceptions in kernel vector mode (PS.UM==0) go to this kernel
- * vector. This kernel vector does very little.
- * Under normal operation of the single-threaded runtime ("XTOS"), kernel
- * vectored general exceptions do not occur, so nothing needs to be done.
- * However when debugging, such as when writing exception and
- * interrupt handlers, kernel vectored exceptions may occur.
- * They are usually the sign of a bug, so here we take a breakpoint
- * (if debug option enabled) or take drastic action (infinite loop)
- * otherwise.
- *
- * XTOS does not allow exceptions in interrupt or exception handlers.
- * If it did, a more elaborate kernel vector handler would be needed.
- * See the Xtensa Microprocessor Programmer's Guide for an
- * example of how to implement such a kernel vector handler.
- */
-
-#include <xtensa/coreasm.h>
-#include <xtensa/config/system.h>
-#ifdef SIMULATOR
-#include <xtensa/simcall.h>
-#endif
-
-#if XCHAL_HAVE_EXCEPTIONS
-
- .begin literal_prefix .KernelExceptionVector
- .section .KernelExceptionVector.text, "ax"
-
- .align 4
- .global _KernelExceptionVector
-_KernelExceptionVector:
-
- // NOTE: this macro is required to work around hw erratum 453. If you are writing
- // your own kernel exception handler then you must add this macro to your handler.
- // If your hardware is not affected by this erratum, the macro will do nothing.
-
- isync_erratum453
-
-# if XCHAL_HAVE_DEBUG
-1: break 1,0 // unexpected kernel exception
-# elif defined(SIMULATOR)
- wsr a2, EXCSAVE1 // save a2 where simulator expects it
- movi a2, SYS_unhandled_kernel_exc
-1: simcall // let simulator/debugger report unhandled exception
-# else
-1:
-# endif
- j 1b // infinite loop - unexpected kernel exception
-
- .size _KernelExceptionVector, . - _KernelExceptionVector
- .text
- .end literal_prefix
-
-#endif /* XCHAL_HAVE_EXCEPTIONS */
-
diff --git a/src/arch/xtensa/up/xtos/memep-enable.S b/src/arch/xtensa/up/xtos/memep-enable.S
deleted file mode 100644
index a915611..0000000
--- a/src/arch/xtensa/up/xtos/memep-enable.S
+++ /dev/null
@@ -1,63 +0,0 @@
-// memep-enable.S -- Turn on local memory ECC/parity checking
-// $Id: //depot/rel/Eaglenest/Xtensa/OS/xtos/memep-enable.S#1 $
-
-// Copyright (c) 2006-2010 Tensilica Inc.
-//
-// Permission is hereby granted, free of charge, to any person obtaining
-// a copy of this software and associated documentation files (the
-// "Software"), to deal in the Software without restriction, including
-// without limitation the rights to use, copy, modify, merge, publish,
-// distribute, sublicense, and/or sell copies of the Software, and to
-// permit persons to whom the Software is furnished to do so, subject to
-// the following conditions:
-//
-// The above copyright notice and this permission notice shall be included
-// in all copies or substantial portions of the Software.
-//
-// THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
-// EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
-// MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
-// IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY
-// CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
-// TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
-// SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
-
-#include <xtensa/coreasm.h>
-
-
- /*
- * void _xtos_memep_enable(int flags);
- *
- * Turn on local memory ECC/parity checking, for both
- * data access and instruction fetch.
- *
- * For now, flags are ignored. Caller is expected to pass zero.
- *
- * _xtos_memep_initrams() must have already been called, if necessary,
- * to ensure all ECC/parity bits are valid in any local instruction
- * or data RAM. The normal reset vector sequence already takes care
- * of initializing any local cache ECC/parity bits.
- */
- .text
- .align 4
- .global _xtos_memep_enable
-_xtos_memep_enable:
- abi_entry
-
-#if XCHAL_HAVE_MEM_ECC_PARITY
-
- // Local Memory ECC/Parity option initialization
- //
- // NOTE: We turn on exceptions on correctable errors and correct
- // them in the memory error handler.
- movi a2, MESR_ERRENAB | MESR_DATEXC | MESR_INSEXC
- wsr a2, MESR
- isync
-
-#endif /* XCHAL_HAVE_MEM_ECC_PARITY */
-
- movi a2, 0 // successfully turned on what we could
- abi_return
-
- .size _xtos_memep_enable, . - _xtos_memep_enable
-
diff --git a/src/arch/xtensa/up/xtos/memep-initrams.S b/src/arch/xtensa/up/xtos/memep-initrams.S
deleted file mode 100644
index c160fd7..0000000
--- a/src/arch/xtensa/up/xtos/memep-initrams.S
+++ /dev/null
@@ -1,91 +0,0 @@
-// memep-initrams.S -- Initialize local memory ECC/parity
-// $Id: //depot/rel/Eaglenest/Xtensa/OS/xtos/memep-initrams.S#1 $
-
-// Copyright (c) 2006-2010 Tensilica Inc.
-//
-// Permission is hereby granted, free of charge, to any person obtaining
-// a copy of this software and associated documentation files (the
-// "Software"), to deal in the Software without restriction, including
-// without limitation the rights to use, copy, modify, merge, publish,
-// distribute, sublicense, and/or sell copies of the Software, and to
-// permit persons to whom the Software is furnished to do so, subject to
-// the following conditions:
-//
-// The above copyright notice and this permission notice shall be included
-// in all copies or substantial portions of the Software.
-//
-// THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
-// EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
-// MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
-// IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY
-// CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
-// TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
-// SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
-
-#include <xtensa/coreasm.h>
-
-
- /*
- * void _xtos_memep_initrams(void);
- *
- * Most reset vectors initialize caches, leaving only the local memories
- * (instruction and data RAMs) with potentially some words that have
- * not been written to and thus have uninitialized ECC/parity bits.
- * Loading such a word after enabling ECC/parity checking would result
- * in an exception (or memory error reported in MESR). To avoid this,
- * an application must either carefully avoid loading from uninitialized
- * words, or ensure it writes to every instruction and data RAM word.
- * The latter is what this function does. It reads and writes every
- * word of every local instruction and data RAM. It should normally
- * be called with interrupts disabled. An interrupt might come in
- * between a load and store, in which case any modification made by the
- * interrupt handler to that local memory location is lost when this
- * function resumes and does the store. If no interrupt handler makes
- * any persistent modification to local memories, disabling them around
- * a call to this function may be unnecessary.
- *
- * On the simulator (ISS), everything comes up zeroed, so no there is
- * no need for this initialization.
- */
- .text
- .align 4
- .global _xtos_memep_initrams
-_xtos_memep_initrams:
- abi_entry
-
- // Local Memory ECC/Parity option initialization
-#if XCHAL_HAVE_MEM_ECC_PARITY && (XCHAL_NUM_DATARAM || XCHAL_NUM_INSTRAM /*|| XCHAL_NUM_URAM || XCHAL_NUM_XLMI*/) && !defined(SIMULATOR)
- .section .rodata, "a"
- .align 4
-.L_locmemep_start:
-# if XCHAL_NUM_DATARAM >= 1 && XCHAL_DATARAM0_ECC_PARITY
- .long XCHAL_DATARAM0_VADDR, XCHAL_DATARAM0_VADDR+XCHAL_DATARAM0_SIZE
-# endif
-# if XCHAL_NUM_DATARAM >= 2 && XCHAL_DATARAM1_ECC_PARITY
- .long XCHAL_DATARAM1_VADDR, XCHAL_DATARAM1_VADDR+XCHAL_DATARAM1_SIZE
-# endif
-# if XCHAL_NUM_INSTRAM >= 1 && XCHAL_INSTRAM0_ECC_PARITY
- .long XCHAL_INSTRAM0_VADDR, XCHAL_INSTRAM0_VADDR+XCHAL_INSTRAM0_SIZE
-# endif
-# if XCHAL_NUM_INSTRAM >= 2 && XCHAL_INSTRAM1_ECC_PARITY
- .long XCHAL_INSTRAM1_VADDR, XCHAL_INSTRAM1_VADDR+XCHAL_INSTRAM1_SIZE
-# endif
-.L_locmemep_end:
- .text
- movi a5, .L_locmemep_start // start of table of local memory ranges
- movi a6, .L_locmemep_end // end of table ...
-2: l32i a3, a5, 0 // start of local memory
- l32i a4, a5, 4 // end of local memory
- addi a5, a5, 8 // (next entry in table)
-1: l32i a2, a3, 0 // load and store every word of local memory...
- s32i a2, a3, 0 // ... to initialize all parity and/or ECC bits
- addi a3, a3, 4
- bltu a3, a4, 1b // loop until whole memory initialized
- bltu a5, a6, 2b // loop until all memories initialized
- // ECC/parity bits are now initialized, checking can be turned on.
-#endif /* ECC/parity on instruction or data RAM(s) */
-
- abi_return
-
- .size _xtos_memep_initrams, . - _xtos_memep_initrams
-
diff --git a/src/arch/xtensa/up/xtos/memerror-vector.S b/src/arch/xtensa/up/xtos/memerror-vector.S
deleted file mode 100644
index 99bc31f..0000000
--- a/src/arch/xtensa/up/xtos/memerror-vector.S
+++ /dev/null
@@ -1,545 +0,0 @@
-/* memerror-vector.S -- Memory Error Exception Vector and Handler */
-
-/* $Id: //depot/rel/Eaglenest/Xtensa/OS/xtos/memerror-vector.S#4 $ */
-
-/*
- * Copyright (c) 2006-2013 Tensilica Inc.
- *
- * Permission is hereby granted, free of charge, to any person obtaining
- * a copy of this software and associated documentation files (the
- * "Software"), to deal in the Software without restriction, including
- * without limitation the rights to use, copy, modify, merge, publish,
- * distribute, sublicense, and/or sell copies of the Software, and to
- * permit persons to whom the Software is furnished to do so, subject to
- * the following conditions:
- *
- * The above copyright notice and this permission notice shall be included
- * in all copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
- * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
- * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
- * IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY
- * CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
- * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
- * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
- */
-
-//#include <xtensa/config/specreg.h>
-#include <xtensa/coreasm.h>
-#include <xtensa/corebits.h>
-
-#if XCHAL_HAVE_MEM_ECC_PARITY
-# if defined(__SPLIT__vector)
-
- // Place this code in the memory error exception vector:
- .begin literal_prefix .MemoryExceptionVector
- .section .MemoryExceptionVector.text, "ax"
-
- .global _MemErrorVector
- .align 4
-_MemErrorVector:
-# if 0 /* XCHAL_HAVE_DEBUG */
- // Memory errors raise PS.INTLEVEL above DEBUGLEVEL, so
- // break instructions have no effect within them (debug
- // exceptions are masked). So leave commented out for now.
- break 1, 5 // unhandled memory error exception
-# endif
- isync_erratum453
- xsr a0, MESAVE
- jx a0
-
- .size _MemErrorVector, . - _MemErrorVector
- .text
- .end literal_prefix
-
-
-#endif
-#if defined(__SPLIT__handler)
-
-/*
- * Some rules and assumptions:
- *
- * Anything that can interrupt this handler (e.g. NMI):
- * - must not lock or unlock cache lines
- */
-
-
-#define ICACHE_WAYWIDTH (XCHAL_ICACHE_SETWIDTH + XCHAL_ICACHE_LINEWIDTH) /* LICT's "iis" */
-#define DCACHE_WAYWIDTH (XCHAL_DCACHE_SETWIDTH + XCHAL_DCACHE_LINEWIDTH) /* LDCT's "dis" */
-/* NOTE: Memory ECC/parity is not supported on XLMI or on local ROMs: */
-#define HAVE_LOCAL_RAM (XCHAL_NUM_DATARAM || XCHAL_NUM_INSTRAM /*|| XCHAL_NUM_URAM || XCHAL_NUM_XLMI*/)
-
-
-#if XCHAL_DCACHE_LINE_LOCKABLE && XCHAL_DCACHE_WAYS > 1 && XCHAL_HAVE_PREFETCH
- .comm _MemErrorSave, 12, 4
-#else
- //.lcomm _MemErrorSave, 8
- .comm _MemErrorSave, 8, 4
-#endif
-
- .text
- .align 4
- .global _MemErrorHandler
-_MemErrorHandler:
- rsr a0, MESR
- bbsi.l a0, MESR_DME_SHIFT, .L_fatal_dme
-# if XCHAL_ICACHE_SIZE > 0 || XCHAL_DCACHE_SIZE > 0
- bbsi.l a0, MESR_MEMTYPE_SHIFT+1, .L_cache // branch if error on a cache
-# endif
- // Error in a local memory.
-# if HAVE_LOCAL_RAM
- bbsi.l a0, MESR_ERRTYPE_SHIFT, .L_uncorrectable_local
- // Correctable error in a local memory (IRAM or DRAM).
- // (MEVADDR has all 32 bits, so XSR preserves a register:)
- xsr a2, MEVADDR
- // Note: MEVADDR is always 4-byte aligned,
- // so we can just do L32I/S32I to correct the error.
- // However, that's not atomic, and NMI can store in between;
- // that's usually a problem for D rather than I, avoid the
- // issue using S32C1I if configured (else NMI must not write DataRAM!?!):
-# if (XCHAL_HAVE_S32C1I && (XCHAL_NUM_DATARAM /*|| XCHAL_NUM_URAM || XCHAL_NUM_XLMI*/))
- bbci.l a0, MESR_MEMTYPE_SHIFT, .L_instram // branch if error on InstRAM
- // Unfortunately we need 3 registers to do S32C1I (data,addr,SCOMPARE1) so
- // we need to save to _MemErrorSave:
- movi a0, _MemErrorSave
- s32i a4, a0, 0 // save a4
- l32i a4, a2, 0 // load data (re-correct)
- rsr a0, SCOMPARE1 // save SCOMPARE1
- wsr a4, SCOMPARE1
- s32c1i a4, a2, 0 // store if still contains same value (else other store corrected error)
- movi a4, _MemErrorSave
- wsr a0, SCOMPARE1 // restore SCOMPARE1
- l32i a4, a4, 0 // restore a4
- j 2f
-.L_instram:
-# endif
- l32i a0, a2, 0 // load data (re-correct)
- s32i a0, a2, 0 // store data to correct ECC bits
-2: xsr a2, MEVADDR
-# endif /* HAVE_LOCAL_RAM */
-.L_done:
- movi a0, _MemErrorHandler
- xsr a0, MESAVE // restore a0 and MESAVE
- rfme
-
-
- // Weak reference: if unresolved, links okay but with zero value:
- .weak _xtos_merr_hook_fatal_dme
-.L_fatal_dme:
- // Fatal (unrecoverable) error, double memory exception
- movi a0, _xtos_merr_hook_fatal_dme
-1: beqz a0, 1b // fatal double memory error, no hook, so infinite loop
- jx a0 // jump to user hook, if present
-
-
-# if HAVE_LOCAL_RAM
- // Weak reference: if unresolved, links okay but with zero value:
- .weak _xtos_merr_hook_uncorrectable_local
-.L_uncorrectable_local:
- // Fatal (unrecoverable) error in IRAM or DRAM: parity or uncorrectable ECC error
- movi a0, _xtos_merr_hook_uncorrectable_local
-1: beqz a0, 1b // fatal memory error, no hook provided, so infinite loop
- jx a0 // jump to user hook, if present
-# endif
-
-
-# if XCHAL_ICACHE_SIZE > 0 || XCHAL_DCACHE_SIZE > 0
-.L_cache:
- // Error in one of the caches.
-# endif
-
-# if XCHAL_ICACHE_SIZE > 0 && XCHAL_HAVE_ICACHE_TEST
-# if XCHAL_DCACHE_SIZE > 0 && XCHAL_HAVE_DCACHE_TEST
- bbsi.l a0, MESR_MEMTYPE_SHIFT, .L_dcache // branch if data cache error
-# endif
- // Error in the instruction cache.
- bbsi.l a0, MESR_ERRTYPE_SHIFT, .L_icache_noncorr // branch if uncorrectable
- // Correctable error in the instruction cache.
- xsr a2, MEVADDR
- // TODO FIXME: remove these 5 lines if waynum is in MEVADDR!? by using III if tag and IHI otherwise!?!?!?:
-# if XCHAL_ICACHE_WAYS > 1
- extui a0, a0, MESR_WAYNUM_SHIFT, 2
- slli a0, a0, ICACHE_WAYWIDTH
- slli a2, a2, 32 - ICACHE_WAYWIDTH
- srli a2, a2, 32 - ICACHE_WAYWIDTH
- or a2, a2, a0
-# endif
-# if XCHAL_ICACHE_LINE_LOCKABLE
- // Preserve the lock bit. So check the tag...
- lict a0, a2 // load i-cache tag
- bbci.l a0, XCHAL_ICACHE_TAG_L_SHIFT, .L_icache_corr_unlocked // branch if unlocked
- // Correctable error in a locked instruction cache line.
- // Fix both tag and one word, quicker than figuring out whether error is in tag or data:
- sict a0, a2 // fix tag
- // TODO FIXME: on fetch wider than 32-bits, SICW might replicate its 32 bits to the
- // whole fetch width rather than just write 32-bits, depending on how customer wires up
- // I-cache RAMs. With ECC option and I-cache locking, they need 32-bit word write enables.
- licw a0, a2
- sicw a0, a2 // fix data word
- j .L_icache_done
-.L_icache_corr_unlocked:
- // We have to write the whole tag to avoid hitting an error here (if tag error).
- // So use IIU (which also invalidates) not III (which reads L bit so can hit error).
- iiu a2, 0 // unlock line ==> also invalidates! (I-side only)
-# else
- iii a2, 0 // invalidate line (whole set!)
-# endif
-.L_icache_done:
- xsr a2, MEVADDR
- j .L_done
-
-.L_icache_noncorr:
- // Non-correctable error in the instruction cache.
- bbsi.l a0, MESR_MEMTYPE_SHIFT+2, .L_icache_tag_noncorr // branch if tag error
- // Non-correctable error in the instruction cache data.
- // Just invalidate the line if we can.
-# if XCHAL_ICACHE_LINE_LOCKABLE
- // If locked, need a different fix sequence.
- xsr a2, MEVADDR
-
-# if XCHAL_ICACHE_WAYS > 1
- // This sequence is shorter, but does not retain original MEVADDR so
- // prevents subsequent use of instructions requiring a virtual address
- // (such as LICW, IPFL, etc):
-// extui a0, a0, MESR_WAYNUM_SHIFT, 2
-// slli a0, a0, ICACHE_WAYWIDTH
-// slli a2, a2, 32 - ICACHE_WAYWIDTH
-// srli a2, a2, 32 - ICACHE_WAYWIDTH
-// or a2, a2, a0
-
- extui a0, a0, MESR_WAYNUM_SHIFT, 2 // id of way with mem error
- slli a0, a0, ICACHE_WAYWIDTH
- xor a0, a2, a0 // xor corresponding bits of addr
- extui a0, a0, ICACHE_WAYWIDTH, 2 // take 2 xor'ed way bits
- or a2, a2, a0 // save them at bottom of addr
- slli a0, a0, ICACHE_WAYWIDTH
- xor a2, a2, a0 // and change 2 way bits of addr
-# endif
- lict a0, a2
- bbsi.l a0, XCHAL_ICACHE_TAG_L_SHIFT, .L_icache_locked_uncor // branch if locked
- // Cache line is not locked, just invalidate:
-# if XCHAL_ICACHE_WAYS > 1
- iii a2, 0
-# else
- ihi a2, 0
-# endif
- j .L_icache_done
-
- // NOTE: we don't use the LICW/SICW sequence below unless the line is locked,
- // otherwise the i-cache line might get replaced between LICW and SICW
- // (if we're not extremely careful), which would be disastrous.
- // Also, for locked lines, LICW/SICW is much safer than IHU/IHI/IPFL
- // because it doesn't leave a window where the line is unlocked;
- // however, if the error is non-correctable, we have no choice.
-
-.L_icache_locked_uncor:
- // If locked and uncorrectable however, the only recourse is relocking.
- // So we need to recover the virtual address so we can do IPFL.
- // Note: can't use MEPC instead of MEVADDR, because (a) it might not
- // point to the correct cache line, and (b) it might be completely wrong
- // in the case where the mem error happened e.g. during an LICW or IPFL.
-# if XCHAL_ICACHE_WAYS > 1
- // Recover virtual address in a2:
- extui a0, a2, 0, 2 // get saved xor'ed bits at bottom
- slli a0, a0, ICACHE_WAYWIDTH // line them up
- xor a2, a2, a0 // restore original MEVADDR
-# endif
- ihu a2, 0 // unlock line
- ihi a2, 0 // invalidate line
- ipfl a2, 0 // refetch-and-lock the line
- j .L_icache_done
-# else /* LOCKABLE */
- rsr a0, MEVADDR
- ihi a0, 0 // invalidate that cache line
- j .L_done
-# endif /* LOCKABLE */
-
-.L_icache_tag_noncorr:
- // Non-correctable error in the instruction cache tag.
- // Just invalidate the tag or the entire set.
-# if XCHAL_ICACHE_LINE_LOCKABLE
- // Note:
- // With i-cache locking, IIU writes the entire tag without mem-error check,
- // and III writes part of it (leaves lock bit alone) so can hit errors.
- // Without i-cache locking, III writes the entire tag without mem-error check.
- // (Original assumption was that SICT is needed.)
-# if XCHAL_ICACHE_WAYS > 1
- // TODO FIXME: avoid this 8-line alternative if waynum is in MEVADDR!?:
- xsr a2, MEVADDR
- extui a0, a0, MESR_WAYNUM_SHIFT, 2
- slli a0, a0, ICACHE_WAYWIDTH
- slli a2, a2, 32 - ICACHE_WAYWIDTH
- srli a2, a2, 32 - ICACHE_WAYWIDTH
- or a2, a2, a0
- iiu a2, 0 // unlock line ==> also invalidates! (I-side only)
- xsr a2, MEVADDR
-# else
- rsr a0, MEVADDR
- iiu a0, 0 // unlock line ==> also invalidates! (I-side only)
-# endif
- // If line was locked, can't recover lock state, need external info to recover.
- // User can provide an assembler hook routine _xtos_merr_hook_icache_relock
- // to relock the icache at the index in a2:
- // - any number of lines might still be locked at that index,
- // including all of them
- // - no stack is provided, a0 must be used as starting point to
- // load a save area and saved registers as necessary
- // - unless routine just does ret (i.e. does not modify any
- // register, only possible if it does nothing), it needs to
- // return by restoring all registers it modified, ending with:
- // movi a0, _MemErrorHandler
- // xsr a0, MESAVE
- // rfme
- // CAVEAT EMPTOR: this hook mechanism is subject to change.
- .weak _xtos_merr_hook_icache_relock // if unresolved, links with zero value
- movi a0, _xtos_merr_hook_icache_relock
-1: beqz a0, 1b // if no hook to recover lock state on icache tag mem error, loop forever
- callx0 a0 // invoke user hook to relock i-cache (index in MEVADDR)
-# else
- rsr a0, MEVADDR
- iii a0, 0 // invalidate entire set
-# endif
- j .L_done
-# endif /* have ICACHE */
-
-
-# if XCHAL_DCACHE_SIZE > 0 && XCHAL_HAVE_DCACHE_TEST
-# if XCHAL_ICACHE_SIZE > 0 && XCHAL_HAVE_ICACHE_TEST
-.L_dcache:
-# endif
- // Error in the data cache.
-# if XCHAL_DCACHE_IS_WRITEBACK || XCHAL_DCACHE_LINE_LOCKABLE
- bbsi.l a0, MESR_ERRTYPE_SHIFT, .L_dcache_noncorr // branch if uncorrectable
- // Uncorrectable error on a writeback dcache might be unrecoverable:
-# endif
- bbsi.l a0, MESR_MEMTYPE_SHIFT+2, .L_dcache_tag // branch if tag error
- // Error in the data cache data (correctable, or non-correctable in writethru+unlockable cache).
- // MEVADDR always a real vaddr here; might point to cache-isolate mode area though.
-# if XCHAL_DCACHE_LINE_LOCKABLE
- // Correctable error on lockable dcache data.
- // If locked, need to refetch the line (or load/store its contents, which is less safe):
- xsr a2, MEVADDR
-# if XCHAL_DCACHE_WAYS > 1
- // Need some extra computation to get the correct dcache way's tag:
- movi a0, _MemErrorSave
- s32i a4, a0, 0 // save a4
- s32i a5, a0, 4 // save a5
-# if XCHAL_HAVE_PREFETCH
- s32i a6, a0, 8 // save a6
- movi a6, 0
- xsr.prefctl a6 // disable prefetch during LDCT (issue TENX-24760)
-# endif
- rsr a4, MESR
- extui a4, a4, MESR_WAYNUM_SHIFT, 2
- slli a4, a4, DCACHE_WAYWIDTH
- slli a5, a2, 32 - DCACHE_WAYWIDTH
- srli a5, a5, 32 - DCACHE_WAYWIDTH
- add a4, a4, a5
- mov a5, a0
- ldct a0, a4
- l32i a4, a5, 0 // restore a4
-# if XCHAL_HAVE_PREFETCH
- wsr.prefctl a6 // restore prefetch
- l32i a6, a5, 8 // restore a6
-# endif
- l32i a5, a5, 4 // restore a5
-# else
-# if XCHAL_HAVE_PREFETCH
- movi a0, _MemErrorSave
- s32i a4, a0, 0 // save a4
- movi a4, 0
- xsr.prefctl a4 // disable prefetch during LDCT (issue TENX-24760)
-# endif
- ldct a0, a2 // invalidate and unlock that cache tag
-# if XCHAL_HAVE_PREFETCH
- wsr.prefctl a4 // restore prefetch
- movi a4, _MemErrorSave
- l32i a4, a4, 0 // restore a4
-# endif
-# endif
- // FIXME: if castout, a2 is a cache index (see PR 24103), from which
- // we can construct a physical address! need that paddr reconstruction,
- // and doesn't work with any address translation.
-# if 0 /* translation */
- movi a4, _xtos_vmap_vaddr // FIXME: do we need two variables for full MMU?
-1: beqz a4, 1b // if no vaddr to use, loop forever (FIXME: caxlt: could assume V==P)
- rdtlb1 a5, a4 // save current contents
- ... clear lower bits of a4 ...
- xx = some function of a2
- wdtlb xx, a4
- a2 = virtual address, i.e. some function of a2 and a4 ...
- ... do the sequence below ...
- ...
- wdtlb a5, a4 // restore TLB entry
-# endif
- // NOTE: the following sequence leaves the line temporarily unlocked, if locked.
- // We assume NMI handlers don't lock lines or rely on their being locked.
- // We could have used "l32i a0,a2,0; s32i a0,a2,0" but that's not atomic on the data.
- dhu a2, 0 // unlock the cache line, if locked
- dhwbi a2, 0 // writeback and invalidate cache line
- bbci.l a0, XCHAL_DCACHE_TAG_L_SHIFT, 1f
- dpfl a2, 0 // re-prefetch-and-lock the cache line
-1: xsr a2, MEVADDR
-# else /* LOCKABLE */
- // Error in unlockable data cache data (correctable, or non-correctable in writethru cache).
- rsr a0, MEVADDR
- // USELESS NOTE: if writethru dcache and NMI handlers don't store to this, we could use DHI instead:
- // FIXME: if castout, a0 is a physical address! doesn't work with any address translation.
- dhwbi a0, 0 // writeback (if correctable) and invalidate that cache line
-# endif /* LOCKABLE */
- j .L_done
-
-.L_dcache_tag:
- // Error in data cache tag (correctable, or non-correctable in writethru+unlockable cache).
- // MEVADDR only contains cache index here (not waynum), don't expect a vaddr (the ISA
- // says upper bits are undefined; actual hw does put a vaddr, but in future might not).
- // Whether or not correctable, just invalidate the particular way's line:
- xsr a2, MEVADDR
- // NOTE: could remove these 5 lines if hw were designed with waynum in MEVADDR (but is not):
-# if XCHAL_DCACHE_WAYS > 1
- extui a0, a0, MESR_WAYNUM_SHIFT, 2
- slli a0, a0, DCACHE_WAYWIDTH
- slli a2, a2, 32 - DCACHE_WAYWIDTH
- srli a2, a2, 32 - DCACHE_WAYWIDTH
- or a2, a2, a0
-# endif
-# if XCHAL_DCACHE_LINE_LOCKABLE
-# if XCHAL_HAVE_PREFETCH
- movi a0, _MemErrorSave
- s32i a4, a0, 0 // save a4
- movi a4, 0
- xsr.prefctl a4 // disable prefetch during LDCT (issue TENX-24760)
-# endif
- ldct a0, a2 // invalidate and unlock that cache tag
-# if XCHAL_HAVE_PREFETCH
- wsr.prefctl a4 // restore prefetch
- movi a4, _MemErrorSave
- l32i a4, a4, 0 // restore a4
-# endif
- bbci.l a0, XCHAL_DCACHE_TAG_L_SHIFT, 1f // branch if not locked
- sdct a0, a2 // if locked, this safely writes whole tag
-# endif
-1: diwbi a2, 0 // writeback (if correctable) and invalidate the line
- xsr a2, MEVADDR
- j .L_done
-
-
-
-# if XCHAL_DCACHE_IS_WRITEBACK || XCHAL_DCACHE_LINE_LOCKABLE
-.L_dcache_noncorr:
- // Uncorrectable error on a (writeback and/or lockable) data cache.
-# if XCHAL_DCACHE_IS_WRITEBACK
- // On tag errors we don't know whether the line is dirty, so this is unrecoverable:
- bbsi.l a0, MESR_MEMTYPE_SHIFT+2, .L_uncorrectable_dtag // branch if tag error
- // Castouts are by definition dirty, uncorrectable errors on these are unrecoverable:
- bbsi.l a0, MESR_ACCTYPE_SHIFT, .L_uncorrectable_dirty // branch if castout
- // Note: could still be an error on dirty dcache data, also unrecoverable.
-# else
- bbsi.l a0, MESR_MEMTYPE_SHIFT+2, .L_dcache_tag_noncorr // branch if tag error
-# endif
- // Uncorrectable error in dcache data.
- // May be dirty or locked, so get tag to find out.
- xsr a2, MEVADDR
-# if XCHAL_DCACHE_WAYS > 1
- extui a0, a0, MESR_WAYNUM_SHIFT, 2 // id of way with mem error
- slli a0, a0, DCACHE_WAYWIDTH
- xor a0, a2, a0 // xor corresponding bits of addr
- extui a0, a0, DCACHE_WAYWIDTH, 2 // take 2 xor'ed way bits
- or a2, a2, a0 // save them at bottom of addr
- slli a0, a0, DCACHE_WAYWIDTH
- xor a2, a2, a0 // and change 2 way bits of addr
-# endif
-# if XCHAL_HAVE_PREFETCH
- movi a0, _MemErrorSave
- s32i a4, a0, 0 // save a4
- movi a4, 0
- xsr.prefctl a4 // disable prefetch during LDCT (issue TENX-24760)
-# endif
- ldct a0, a2 // get dcache tag
-# if XCHAL_HAVE_PREFETCH
- wsr.prefctl a4 // restore prefetch
- movi a4, _MemErrorSave
- l32i a4, a4, 0 // restore a4
-# endif
-# if XCHAL_DCACHE_IS_WRITEBACK
- bbsi.l a0, XCHAL_DCACHE_TAG_D_SHIFT, .L_uncorrectable_dirty_2 // branch if dirty
-# endif
- // Data cache line is clean.
-# if XCHAL_DCACHE_LINE_LOCKABLE
- bbsi.l a0, XCHAL_DCACHE_TAG_L_SHIFT, .L_dcache_nc_locked
-# endif
- // Data cache line is clean and unlocked. Just invalidate it.
- // FIXME: any stores to this line by an NMI handler will be lost.
- // On the other hand, if we use DHWBI, any stores by an NMI handler
- // that don't happen to fix the error result in an unrecoverable castout.
- //
-# if XCHAL_DCACHE_WAYS > 1
- // Recover virtual address in a2:
- extui a0, a2, 0, 2 // get saved xor'ed bits at bottom
- slli a0, a0, DCACHE_WAYWIDTH // line them up
- xor a2, a2, a0 // restore original MEVADDR
-# endif
- dhi a2, 0 // invalidate that data cache line
- xsr a2, MEVADDR
- j .L_done
-
-# if XCHAL_DCACHE_LINE_LOCKABLE
-.L_dcache_nc_locked:
-# if XCHAL_DCACHE_WAYS > 1
- // Recover virtual address in a2:
- extui a0, a2, 0, 2 // get saved xor'ed bits at bottom
- slli a0, a0, DCACHE_WAYWIDTH // line them up
- xor a2, a2, a0 // restore original MEVADDR
-# endif
- // Unlock, invalidate, and relock it:
- dhu a2, 0 // unlock that data cache line
- dhi a2, 0 // invalidate that data cache line
- dpfl a2, 0 // prefetch-and-lock the line again
- xsr a2, MEVADDR
- j .L_done
-# endif
-
-# if XCHAL_DCACHE_IS_WRITEBACK
- // Weak reference: if unresolved, links okay but with zero value:
- .weak _xtos_merr_hook_uncor_dtag
-.L_uncorrectable_dtag:
- // Fatal (unrecoverable) error in dcache tag (maybe dirty): parity or uncorrectable ECC error
- movi a0, _xtos_merr_hook_uncor_dtag
-1: beqz a0, 1b // fatal non-corr dcache tag, no hook, so infinite loop
- jx a0 // jump to user hook, if present
-
- // Weak reference: if unresolved, links okay but with zero value:
- .weak _xtos_merr_hook_uncor_dirty
-.L_uncorrectable_dirty_2:
- xsr a2, MEVADDR
-.L_uncorrectable_dirty:
- // Fatal (unrecoverable) error, parity or non-correctable ECC error on dirty cache data
- movi a0, _xtos_merr_hook_uncor_dirty
-1: beqz a0, 1b // fatal non-corr dirty cache line, no hook, so infinite loop
- jx a0 // jump to user hook, if present
-# else
-.L_dcache_tag_noncorr:
- // Uncorrectable error on a lockable writethru data cache tag.
- // We have to invalidate the line, but that way we lose the lock bit.
- // Provide a hook to relock if necessary (using knowledge outside this module
- // about what needs to be locked). See _xtos_merr_hook_icache_relock for details.
- // CAVEAT EMPTOR: this hook mechanism is subject to change.
- .weak _xtos_merr_hook_dcache_relock // if unresolved, links with zero value
- movi a0, _xtos_merr_hook_dcache_relock
-1: beqz a0, 1b // if no hook to recover lock state on dcache tag mem error, loop forever
- callx0 a0 // invoke user hook to relock d-cache (index in MEVADDR)
- j .L_done
-# endif
-
-# endif /* DCACHE IS WRITEBACK || LINE_LOCKABLE */
-
-# endif /* have DCACHE */
-
- .size _MemErrorHandler, . - _MemErrorHandler
-
-
-
-# endif /* splitting */
-#endif /* XCHAL_HAVE_MEM_ECC_PARITY */
-
diff --git a/src/arch/xtensa/up/xtos/nmi-vector.S b/src/arch/xtensa/up/xtos/nmi-vector.S
deleted file mode 100644
index 9c5074a..0000000
--- a/src/arch/xtensa/up/xtos/nmi-vector.S
+++ /dev/null
@@ -1,63 +0,0 @@
-// nmi-vector.S -- Standalone NMI Interrupt Vector/Handler
-// $Id: //depot/rel/Eaglenest/Xtensa/OS/xtos/nmi-vector.S#2 $
-
-// Copyright (c) 2003, 2006, 2010 Tensilica Inc.
-//
-// Permission is hereby granted, free of charge, to any person obtaining
-// a copy of this software and associated documentation files (the
-// "Software"), to deal in the Software without restriction, including
-// without limitation the rights to use, copy, modify, merge, publish,
-// distribute, sublicense, and/or sell copies of the Software, and to
-// permit persons to whom the Software is furnished to do so, subject to
-// the following conditions:
-//
-// The above copyright notice and this permission notice shall be included
-// in all copies or substantial portions of the Software.
-//
-// THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
-// EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
-// MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
-// IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY
-// CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
-// TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
-// SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
-
-// The NMI exception vector handles non-maskable interrupts.
-
-#include <xtensa/coreasm.h>
-#include <xtensa/config/system.h>
-#include <xtensa/config/specreg.h>
-
-#if XCHAL_HAVE_NMI
-
- .begin literal_prefix .NMIExceptionVector
- .section .NMIExceptionVector.text, "ax"
-
- .align 4
- .global _NMIExceptionVector
-_NMIExceptionVector:
-
- isync_erratum453
-
-// Insert any custom NMI handling code here.
-// For example:
-// wsr a0, EXCSAVE+XCHAL_NMILEVEL
-// movi a0, ...address of some save area specific to this code...
-// s32i a1, a0, 0 // save whatever registers are needed
-// :
-// do something useful ...
-// :
-// l32i a1, a0, 0 // restore whatever registers were saved
-// rsr a0, EXCSAVE+XCHAL_NMILEVEL
-//
-// This default NMI handler does not do anything. It just returns
-// immediately upon any occurrence of a non-maskable interrupt.
-
- rfi XCHAL_NMILEVEL
-
- .size _NMIExceptionVector, . - _NMIExceptionVector
- .text
- .end literal_prefix
-
-#endif /* XCHAL_HAVE_NMI */
-
diff --git a/src/arch/xtensa/up/xtos/null-alloca.S b/src/arch/xtensa/up/xtos/null-alloca.S
deleted file mode 100644
index 4f78a63..0000000
--- a/src/arch/xtensa/up/xtos/null-alloca.S
+++ /dev/null
@@ -1,38 +0,0 @@
-// null-alloca.S - Stub for Unused Alloca (MOVSP) Handler
-// $Id: //depot/rel/Eaglenest/Xtensa/OS/xtos/null-alloca.S#1 $
-
-// Copyright (c) 2006-2010 Tensilica Inc.
-//
-// Permission is hereby granted, free of charge, to any person obtaining
-// a copy of this software and associated documentation files (the
-// "Software"), to deal in the Software without restriction, including
-// without limitation the rights to use, copy, modify, merge, publish,
-// distribute, sublicense, and/or sell copies of the Software, and to
-// permit persons to whom the Software is furnished to do so, subject to
-// the following conditions:
-//
-// The above copyright notice and this permission notice shall be included
-// in all copies or substantial portions of the Software.
-//
-// THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
-// EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
-// MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
-// IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY
-// CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
-// TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
-// SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
-
-
- // Redirect alloca (MOVSP) exceptions as not handled, when
- // that functionality is not needed. Done this way, a user can
- // just specify this small handler to override the default one.
-
- .text
- .weak _xtos_unhandled_exception
- .global _xtos_alloca_handler
-_xtos_alloca_handler:
- movi a3, _xtos_unhandled_exception
-1: beqz a3, 1b
- jx a3
- .size _xtos_alloca_handler, . - _xtos_alloca_handler
-
diff --git a/src/arch/xtensa/up/xtos/null-syscall.S b/src/arch/xtensa/up/xtos/null-syscall.S
deleted file mode 100644
index 4052f7d..0000000
--- a/src/arch/xtensa/up/xtos/null-syscall.S
+++ /dev/null
@@ -1,38 +0,0 @@
-// null-syscall.S - Stub for Unused SYSCALL Handler
-// $Id: //depot/rel/Eaglenest/Xtensa/OS/xtos/null-syscall.S#1 $
-
-// Copyright (c) 2006-2010 Tensilica Inc.
-//
-// Permission is hereby granted, free of charge, to any person obtaining
-// a copy of this software and associated documentation files (the
-// "Software"), to deal in the Software without restriction, including
-// without limitation the rights to use, copy, modify, merge, publish,
-// distribute, sublicense, and/or sell copies of the Software, and to
-// permit persons to whom the Software is furnished to do so, subject to
-// the following conditions:
-//
-// The above copyright notice and this permission notice shall be included
-// in all copies or substantial portions of the Software.
-//
-// THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
-// EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
-// MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
-// IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY
-// CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
-// TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
-// SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
-
-
- // Redirect SYSCALL exceptions as not handled, when
- // that functionality is not needed. Done this way, a user can
- // just specify this small handler to override the default one.
-
- .text
- .weak _xtos_unhandled_exception
- .global _xtos_syscall_handler
-_xtos_syscall_handler:
- movi a3, _xtos_unhandled_exception
-1: beqz a3, 1b
- jx a3
- .size _xtos_syscall_handler, . - _xtos_syscall_handler
-
diff --git a/src/arch/xtensa/up/xtos/null-vectors.S b/src/arch/xtensa/up/xtos/null-vectors.S
deleted file mode 100644
index 1d9fe06..0000000
--- a/src/arch/xtensa/up/xtos/null-vectors.S
+++ /dev/null
@@ -1,190 +0,0 @@
-// null-vectors.S - Stubs for Unused Vectors and Handlers
-// $Id: //depot/rel/Eaglenest/Xtensa/OS/xtos/null-vectors.S#1 $
-
-// Copyright (c) 2006-2010 Tensilica Inc.
-//
-// Permission is hereby granted, free of charge, to any person obtaining
-// a copy of this software and associated documentation files (the
-// "Software"), to deal in the Software without restriction, including
-// without limitation the rights to use, copy, modify, merge, publish,
-// distribute, sublicense, and/or sell copies of the Software, and to
-// permit persons to whom the Software is furnished to do so, subject to
-// the following conditions:
-//
-// The above copyright notice and this permission notice shall be included
-// in all copies or substantial portions of the Software.
-//
-// THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
-// EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
-// MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
-// IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY
-// CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
-// TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
-// SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
-
-
-// NOTE: The simulator version of this file is currently not used,
-// i.e. the SIMULATOR macro is never defined when assembling this file.
-// The relevant simulator code is left here for illustrative purposes only.
-
-
-#include <xtensa/coreasm.h>
-#include "xtos-internal.h"
-#ifdef SIMULATOR
-#include <xtensa/simcall.h>
-#endif
-
- // These are just tiny non-functional vectors and handlers for when
- // their functionality is not being used. They just try to signal
- // the debugger that an unhandled exception or interrupt occurred,
- // and otherwise just spin in a loop.
- //
- // For interrupts levels above DEBUGLEVEL, lowering PS.INTLEVEL
- // for break to work is tricky, and not always possible in a
- // generic fashion without interfering with normal program execution.
- // So for now we don't do it.
-
-
-#if defined(__SPLIT__user)
-
-# if XCHAL_HAVE_EXCEPTIONS
- .begin literal_prefix .UserExceptionVector
- .section .UserExceptionVector.text, "ax"
- .align 4
- .global _UserExceptionVector
-_UserExceptionVector:
-# if XCHAL_HAVE_DEBUG
- break 1, 1 // unexpected user-vectored general exception
-# endif
-1: j 1b // infinite loop - unexpected user-vectored exception
- .size _UserExceptionVector, . - _UserExceptionVector
- .end literal_prefix
-# endif
-
-#endif
-#if defined(__SPLIT__level1int)
-
- .text
- .global _xtos_l1int_handler
-_xtos_l1int_handler:
- movi a3, _xtos_unhandled_exception
- jx a3
- .size _xtos_l1int_handler, . - _xtos_l1int_handler
-
-#endif
-#if defined(__SPLIT__level2)
-
-# if (XCHAL_NUM_INTLEVELS >= 2) && (XCHAL_DEBUGLEVEL != 2)
- .begin literal_prefix .Level2InterruptVector
- .section .Level2InterruptVector.text, "ax"
- .align 4
- .global _Level2Vector
-_Level2Vector:
-# if XCHAL_HAVE_DEBUG && (XCHAL_DEBUGLEVEL > 2)
- break 1, 2 // unexpected high-priority interrupt
-# elif defined(SIMULATOR)
- wsr a2, EXCSAVE_2
- movi a2, SYS_unhandled_highpri_interrupt
- simcall // let simulator/debugger report unhandled level-2 interrupt
-# endif
-1: j 1b // infinite loop - unexpected level-2 interrupt
- .size _Level2Vector, . - _Level2Vector
- .text
- .end literal_prefix
-# endif /* level 2 */
-
-
-#endif
-#if defined(__SPLIT__level3)
-
-# if (XCHAL_NUM_INTLEVELS >= 3) && (XCHAL_DEBUGLEVEL != 3)
- .begin literal_prefix .Level3InterruptVector
- .section .Level3InterruptVector.text, "ax"
- .align 4
- .global _Level3Vector
-_Level3Vector:
-# if XCHAL_HAVE_DEBUG && (XCHAL_DEBUGLEVEL > 3)
- break 1, 2 // unexpected high-priority interrupt
-# elif defined(SIMULATOR)
- wsr a2, EXCSAVE_3
- movi a2, SYS_unhandled_highpri_interrupt
- simcall // let simulator/debugger report unhandled level-3 interrupt
-# endif
-1: j 1b // infinite loop - unexpected level-3 interrupt
- .size _Level3Vector, . - _Level3Vector
- .text
- .end literal_prefix
-# endif /* level 3 */
-
-
-#endif
-#if defined(__SPLIT__level4)
-
-# if (XCHAL_NUM_INTLEVELS >= 4) && (XCHAL_DEBUGLEVEL != 4)
- .begin literal_prefix .Level4InterruptVector
- .section .Level4InterruptVector.text, "ax"
- .align 4
- .global _Level4Vector
-_Level4Vector:
-# if XCHAL_HAVE_DEBUG && (XCHAL_DEBUGLEVEL > 4)
- break 1, 2 // unexpected high-priority interrupt
-# elif defined(SIMULATOR)
- wsr a2, EXCSAVE_4
- movi a2, SYS_unhandled_highpri_interrupt
- simcall // let simulator/debugger report unhandled level-4 interrupt
-# endif
-1: j 1b // infinite loop - unexpected level-4 interrupt
- .size _Level4Vector, . - _Level4Vector
- .text
- .end literal_prefix
-# endif /* level 4 */
-
-
-#endif
-#if defined(__SPLIT__level5)
-
-# if (XCHAL_NUM_INTLEVELS >= 5) && (XCHAL_DEBUGLEVEL != 5)
- .begin literal_prefix .Level5InterruptVector
- .section .Level5InterruptVector.text, "ax"
- .align 4
- .global _Level5Vector
-_Level5Vector:
-# if XCHAL_HAVE_DEBUG && (XCHAL_DEBUGLEVEL > 5)
- break 1, 2 // unexpected high-priority interrupt
-# elif defined(SIMULATOR)
- wsr a2, EXCSAVE_5
- movi a2, SYS_unhandled_highpri_interrupt
- simcall // let simulator/debugger report unhandled level-5 interrupt
-# endif
-1: j 1b // infinite loop - unexpected level-5 interrupt
- .size _Level5Vector, . - _Level5Vector
- .text
- .end literal_prefix
-# endif /* level 5 */
-
-
-#endif
-#if defined(__SPLIT__level6)
-
-# if (XCHAL_NUM_INTLEVELS >= 6) && (XCHAL_DEBUGLEVEL != 6)
- .begin literal_prefix .Level6InterruptVector
- .section .Level6InterruptVector.text, "ax"
- .align 4
- .global _Level6Vector
-_Level6Vector:
-# if XCHAL_HAVE_DEBUG && (XCHAL_DEBUGLEVEL > 6)
- break 1, 2 // unexpected high-priority interrupt
-# elif defined(SIMULATOR)
- wsr a2, EXCSAVE_6
- movi a2, SYS_unhandled_highpri_interrupt
- simcall // let simulator/debugger report unhandled level-6 interrupt
-# endif
-1: j 1b // infinite loop - unexpected level-6 interrupt
- .size _Level6Vector, . - _Level6Vector
- .text
- .end literal_prefix
-# endif /* level 6 */
-
-
-#endif /* split */
-
diff --git a/src/arch/xtensa/up/xtos/reloc-vectors.S b/src/arch/xtensa/up/xtos/reloc-vectors.S
deleted file mode 100644
index 99ee510..0000000
--- a/src/arch/xtensa/up/xtos/reloc-vectors.S
+++ /dev/null
@@ -1,119 +0,0 @@
-// reloc-vector.S - Relocatable Vectors section
-// $Id: //depot/rel/Eaglenest/Xtensa/OS/xtos/reloc-vectors.S#1 $
-
-// Copyright (c) 2007-2010 Tensilica Inc.
-//
-// Permission is hereby granted, free of charge, to any person obtaining
-// a copy of this software and associated documentation files (the
-// "Software"), to deal in the Software without restriction, including
-// without limitation the rights to use, copy, modify, merge, publish,
-// distribute, sublicense, and/or sell copies of the Software, and to
-// permit persons to whom the Software is furnished to do so, subject to
-// the following conditions:
-//
-// The above copyright notice and this permission notice shall be included
-// in all copies or substantial portions of the Software.
-//
-// THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
-// EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
-// MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
-// IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY
-// CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
-// TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
-// SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
-
-/*
- * This file is only used if the relocatable vectors option is enabled.
- */
-
-#include <xtensa/coreasm.h>
-#include <xtensa/config/system.h>
-
-#if XCHAL_HAVE_VECBASE
-
- .section .RelocatableVectors.text, "ax"
-
- .global _RelocVectors
-_RelocVectors:
-
-//if XCHAL_RESET_VECBASE_OVERLAP ...
-# if XSHAL_VECTORS_PACKED \
- && (XCHAL_RESET_VECTOR0_VADDR == XCHAL_VECBASE_RESET_VADDR \
- || XCHAL_RESET_VECTOR1_VADDR == XCHAL_VECBASE_RESET_VADDR)
-# define JUMP_TO_RESET 1
- j .Ljump_to_reset
-# endif
-
-# if XCHAL_HAVE_WINDOWED
-# define NO_SECTION_DIRECTIVES 1
-# define WINDOW_BASE_VECOFS 0
-# include "window-vectors.S"
-# endif
-
-#if XCHAL_HAVE_DEBUG && XCHAL_HAVE_EXCEPTIONS
-# if XCHAL_DEBUGLEVEL == 2
-# define _Level2Vector _DebugExceptionVector
-# elif XCHAL_DEBUGLEVEL == 3
-# define _Level3Vector _DebugExceptionVector
-# elif XCHAL_DEBUGLEVEL == 4
-# define _Level4Vector _DebugExceptionVector
-# elif XCHAL_DEBUGLEVEL == 5
-# define _Level5Vector _DebugExceptionVector
-# elif XCHAL_DEBUGLEVEL == 6
-# define _Level6Vector _DebugExceptionVector
-# endif
-#endif
-
-# if XCHAL_HAVE_INTERRUPTS
-# if XCHAL_NUM_INTLEVELS >= 2
- .org XCHAL_INTLEVEL2_VECOFS
- j _Level2Vector
-# endif
-# if XCHAL_NUM_INTLEVELS >= 3
- .org XCHAL_INTLEVEL3_VECOFS
- j _Level3Vector
-# endif
-# if XCHAL_NUM_INTLEVELS >= 4
- .org XCHAL_INTLEVEL4_VECOFS
- j _Level4Vector
-# endif
-# if XCHAL_NUM_INTLEVELS >= 5
- .org XCHAL_INTLEVEL5_VECOFS
- j _Level5Vector
-# endif
-# if XCHAL_NUM_INTLEVELS >= 6
- .org XCHAL_INTLEVEL6_VECOFS
- j _Level6Vector
-# endif
-# if XCHAL_HAVE_NMI
- .org XCHAL_NMI_VECOFS
- j _NMIExceptionVector
-# endif
-# endif
-# if XCHAL_HAVE_EXCEPTIONS
- .org XCHAL_KERNEL_VECOFS
- j _KernelExceptionVector
- .org XCHAL_USER_VECOFS
- j _UserExceptionVector
- .org XCHAL_DOUBLEEXC_VECOFS
- j _DoubleExceptionVector
-# endif
-
-// Put literals here.
-
-// Put actual handlers here.
-
-# if JUMP_TO_RESET
- .align 4
- .literal rvec, _ResetVector
-.Ljump_to_reset:
- l32r a2, rvec
- jx a2
-# endif
-
- .size _RelocVectors, . - _RelocVectors
-
- .text
-
-#endif /* XCHAL_HAVE_VECBASE */
-
diff --git a/src/arch/xtensa/up/xtos/reset-unneeded.S b/src/arch/xtensa/up/xtos/reset-unneeded.S
deleted file mode 100644
index 48dfb72..0000000
--- a/src/arch/xtensa/up/xtos/reset-unneeded.S
+++ /dev/null
@@ -1,156 +0,0 @@
-// reset-unneeded.S -- Optional Extraneous Reset Code
-// $Id: //depot/rel/Eaglenest/Xtensa/OS/xtos/reset-unneeded.S#1 $
-
-// Copyright (c) 2002-2006 Tensilica Inc.
-//
-// Permission is hereby granted, free of charge, to any person obtaining
-// a copy of this software and associated documentation files (the
-// "Software"), to deal in the Software without restriction, including
-// without limitation the rights to use, copy, modify, merge, publish,
-// distribute, sublicense, and/or sell copies of the Software, and to
-// permit persons to whom the Software is furnished to do so, subject to
-// the following conditions:
-//
-// The above copyright notice and this permission notice shall be included
-// in all copies or substantial portions of the Software.
-//
-// THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
-// EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
-// MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
-// IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY
-// CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
-// TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
-// SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
-
-// This file is meant to be included by another, e.g. crt1-***.S .
-// The code it contains is generally not needed, so is kept in a
-// separate file for clarity of other code.
-
-#if XTOS_RESET_UNNEEDED
- /*
- * Reset registers that don't really need to be reset,
- * but may provide more predictability when buggy code
- * relies on uninitialized state. It might also clear
- * "X"s a bit earlier in hardware simulations.
- *
- * NOTE: This code is by no means exhaustive.
- * More processor registers/states could be reset if desired.
- * This is just an example.
- *
- * ASSUMPTION: a0 is still zero at this point.
- */
-
- // Interrupt initialization.
- // Because INTENABLE is cleared by the reset vector, clearing the
- // interrupt-pending register should not be needed. This assumes
- // that any application setting up an interrupt will register and
- // clear it before enabling it, which is the recommended sequence.
- //
-#if XCHAL_HAVE_INTERRUPTS && (XCHAL_INTCLEARABLE_MASK != 0) && !XCHAL_HAVE_FULL_RESET
- movi a2, XCHAL_INTCLEARABLE_MASK
- wsr a2, INTCLEAR // clear software and edge-trig ints
-#endif
-
- // Timer initialization (not strictly required, but sometimes helpful)
- .macro reset_timer num
- wsr a0, CCOMPARE_0 + \num
- .endm
- iterate 0, XCHAL_NUM_TIMERS-1, reset_timer
-
-# if XCHAL_HAVE_WINDOWED
- // Windowed address register init -- initialize entire physical AR file
- movi a0, XCHAL_NUM_AREGS/8 // number of 8-register chunks
-arloop:
- addi a8, a0, -1 // countdown into next chunk's a0
- movi a0, 0
- movi a1, 0
- movi a2, 0
- movi a3, 0
- movi a4, 0
- movi a5, 0
- movi a6, 0
- movi a7, 0
- rotw 2 // rotate to next chunk
- bnez a0, arloop
- // NOTE: WINDOWBASE is back to zero at this point.
-# else /* XCHAL_HAVE_WINDOWED */
- // Non-windowed address register init
- movi a1, 0
- movi a2, 0
- movi a3, 0
- movi a4, 0
- movi a5, 0
- movi a6, 0
- movi a7, 0
- movi a8, 0
- movi a9, 0
- movi a10, 0
- movi a11, 0
- movi a12, 0
- movi a13, 0
- movi a14, 0
- movi a15, 0
-# endif /* XCHAL_HAVE_WINDOWED */
- // Now all address registers are zero.
-
- // Initialize LBEG, LEND, and LCOUNT.
-# if XCHAL_HAVE_LOOPS
- wsr a0, LCOUNT // note: LCOUNT gets cleared by processor reset
- wsr a0, LBEG
- wsr a0, LEND
-# endif
-
-# if XCHAL_HAVE_DEBUG
- .macro reset_dbreaka num
- wsr a0, DBREAKA + \num
- .endm
- .macro reset_ibreaka num
- wsr a0, IBREAKA + \num
- .endm
- iterate 0, XCHAL_NUM_DBREAK-1, reset_dbreaka
- iterate 0, XCHAL_NUM_IBREAK-1, reset_ibreaka
-# endif
-
- // SAR initialization
- ssai 0
-
- // Exception initialization
-# if XCHAL_HAVE_EXCEPTIONS
- wsr a0, EPC+1
- wsr a0, EXCSAVE+1
- wsr a0, EXCCAUSE
-# endif
-
-# if XCHAL_HAVE_HIGHLEVEL_INTERRUPTS
- .macro reset_int num
- wsr a0, EPC + \num
- wsr a0, EPS + \num
- wsr a0, EXCSAVE + \num
- .endm
- iterate 2, XCHAL_NUM_INTLEVELS, reset_int
-# endif
-
- // Booleans initialization
-# if XCHAL_HAVE_BOOLEANS
- wsr a0, BR
-# endif
-
- // MAC16 initialization
-# if XCHAL_HAVE_MAC16
- wsr a0, ACCLO
- wsr a0, ACCHI
- wsr a0, M0
- wsr a0, M1
- wsr a0, M2
- wsr a0, M3
-# endif
-
- // OCD initialization
-# if XCHAL_HAVE_OCD
- wsr a0, DDR
-# endif
-
- isync // wait for all the above to take effect
-
-#endif /* XTOS_RESET_UNNEEDED */
-
diff --git a/src/arch/xtensa/up/xtos/reset-vector.S b/src/arch/xtensa/up/xtos/reset-vector.S
deleted file mode 100644
index 099a578..0000000
--- a/src/arch/xtensa/up/xtos/reset-vector.S
+++ /dev/null
@@ -1,624 +0,0 @@
-// reset-vector.S -- Xtensa Reset Vector
-// $Id: //depot/rel/Eaglenest/Xtensa/OS/xtos/reset-vector.S#3 $
-
-// Copyright (c) 1999-2013 Tensilica Inc.
-// Copyright (c) 2016 Intel Corporation.
-//
-// Permission is hereby granted, free of charge, to any person obtaining
-// a copy of this software and associated documentation files (the
-// "Software"), to deal in the Software without restriction, including
-// without limitation the rights to use, copy, modify, merge, publish,
-// distribute, sublicense, and/or sell copies of the Software, and to
-// permit persons to whom the Software is furnished to do so, subject to
-// the following conditions:
-//
-// The above copyright notice and this permission notice shall be included
-// in all copies or substantial portions of the Software.
-//
-// THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
-// EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
-// MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
-// IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY
-// CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
-// TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
-// SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
-
-#include <xtensa/coreasm.h>
-#include <xtensa/corebits.h>
-#include <xtensa/cacheasm.h>
-#include <xtensa/cacheattrasm.h>
-#include <xtensa/xtensa-xer.h>
-#include <xtensa/xdm-regs.h>
-#include <xtensa/config/specreg.h>
-#include <xtensa/config/system.h> /* for XSHAL_USE_ABSOLUTE_LITERALS only */
-#include <xtensa/xtruntime-core-state.h>
-#include "xtos-internal.h"
-#include <config.h>
-
-#if CONFIG_BOOT_LOADER
-#include <platform/memory.h>
-#endif
-
-// The following reset vector avoids initializing certain registers already
-// initialized by processor reset. But it does initialize some of them
-// anyway, for minimal support of warm restart (restarting in software by
-// jumping to the reset vector rather than asserting hardware reset).
-
-
- .begin literal_prefix .ResetVector
- .section .ResetVector.text, "ax"
-
- .align 4
- .global _ResetVector
-_ResetVector:
-
-# if 0 /* if XCHAL_HAVE_HALT */
- // In theory, minimal reset vector for Xtensa TX (assuming bootloader to clear BSS).
- // In practice we let crt*.S decide whether to do more (e.g. for sim LSP)
- // and we might unpack below for ROMing LSPs.
- movi sp, __stack // setup the stack
- call0 main // assume declared as "void main(void)" (no args)
- halt // toodaloo
-# endif
-
-#if (!XCHAL_HAVE_HALT || defined(XTOS_UNPACK)) && XCHAL_HAVE_IMEM_LOADSTORE
- // NOTE:
- //
- // IMPORTANT: If you move the _ResetHandler portion to a section
- // other than .ResetVector.text that is outside the range of
- // the reset vector's 'j' instruction, the _ResetHandler symbol
- // and a more elaborate j/movi/jx sequence are needed in
- // .ResetVector.text to dispatch to the new location.
-
- // If we have dynamic cache way support, init the caches as soon
- // as we can, which is now. Except, if we are waking up from a
- // PSO event, then we need to do this slightly later.
-
-#if XCHAL_USE_MEMCTL
-#if XCHAL_HAVE_PSO_CDM && !XCHAL_HAVE_PSO_FULL_RETENTION
- // Do this later on in the code -- see below
-#else
- movi a0, ~MEMCTL_SNOOP_EN
- wsr a0, MEMCTL
-#endif
-#endif
-
-/* Apollolake+ have reset vector in ROM */
-#if defined(CONFIG_BAYTRAIL) || defined(CONFIG_CHERRYTRAIL) \
- || defined (CONFIG_HASWELL) || defined(CONFIG_BROADWELL)
- j _ResetHandler
-#else
-
- // This is our VM bxt ROM. It simply jumps to the reset handler.
- j .sram_jump // jump over the literals
-
- .align 4
- .literal_position // tells the assembler/linker to place literals here
-
-_reset_sram:
- .word _ResetHandler
- .align 4
-.sram_jump:
- l32r a0, _reset_sram // load SRAM reset hanler address
- jx a0 // jump to the hanlder
-#endif
- .size _ResetVector, . - _ResetVector
-
-# if XCHAL_HAVE_HALT
- // Xtensa TX: reset vector segment is only 4 bytes, so must place the
- // unpacker code elsewhere in the memory that contains the reset vector.
-# if XCHAL_RESET_VECTOR_VADDR == XCHAL_INSTRAM0_VADDR
- .section .iram0.text, "ax"
-# elif XCHAL_RESET_VECTOR_VADDR == XCHAL_INSTROM0_VADDR
- .section .irom0.text, "ax"
-# elif XCHAL_RESET_VECTOR_VADDR == XCHAL_URAM0_VADDR
- .section .uram0.text, "ax"
-# else
-# warning "Xtensa TX reset vector not at start of iram0, irom0, or uram0 -- ROMing LSPs may not work"
- .text
-# endif
-# endif
-
-#if defined(CONFIG_BOOT_LOADER)
- .section .ResetHandler.text, "ax"
- j _ResetHandler
-#endif
- .align 4
- .literal_position // tells the assembler/linker to place literals here
-
- .align 4
- .global _ResetHandler
-
-_ResetHandler:
-#endif
-
-#if !XCHAL_HAVE_HALT
-
- /*
- * Even if the processor supports the non-PC-relative L32R option,
- * it will always start up in PC-relative mode. We take advantage of
- * this, and use PC-relative mode at least until we're sure the .lit4
- * section is in place (which is sometimes only after unpacking).
- */
- .begin no-absolute-literals
-
- // If we have PSO support, then we must check for a warm start with
- // caches left powered on. If the caches had been left powered on,
- // we must restore the state of MEMCTL to the saved state if any.
- // Note that MEMCTL may not be present depending on config.
-
-#if XCHAL_HAVE_PSO_CDM && !XCHAL_HAVE_PSO_FULL_RETENTION
- movi a2, XDM_MISC_PWRSTAT // Read PWRSTAT
- movi a3, _xtos_pso_savearea // Save area address - retained for later
- movi a5, CORE_STATE_SIGNATURE // Signature for compare - retained for later
- rer a7, a2 // PWRSTAT value - retained for later
- extui a4, a7, 1, 2 // Now bottom 2 bits are core wakeup and cache power lost
- bnei a4, 1, .Lcold_start // a4==1 means PSO wakeup, caches did not lose power
- l32i a4, a3, CS_SA_signature // Load save area signature field
- sub a4, a4, a5
- bnez a4, .Lcold_start // If signature mismatch then do cold start
-#if XCHAL_USE_MEMCTL
- l32i a4, a3, CS_SA_memctl // Load saved MEMCTL value
- movi a0, ~MEMCTL_INV_EN
- and a0, a4, a0 // Clear invalidate bit
- wsr a0, MEMCTL
-#endif
- j .Lwarm_start
-
-.Lcold_start:
-
-#if XCHAL_USE_MEMCTL
- // Enable and invalidate all ways of both caches. If there is no
- // dynamic way support then this write will have no effect.
-
- movi a0, ~MEMCTL_SNOOP_EN
- wsr a0, MEMCTL
-#endif
-
-.Lwarm_start:
-
-#endif
-
-#if defined(CONFIG_APOLLOLAKE)
- call0 _call_init
-#endif
-
-#if defined(CONFIG_APOLLOLAKE)
- movi a0, 0 // a0 is always 0 in this code, used to initialize lots of things
- movi a0, 0
- movi a1, 0
- movi a2, 0
-#else
- movi a0, 0 // a0 is always 0 in this code, used to initialize lots of things
-#endif
-
-
-#if XCHAL_HAVE_INTERRUPTS // technically this should be under !FULL_RESET, assuming hard reset
- wsr a0, INTENABLE // make sure that interrupts are shut off (*before* we lower PS.INTLEVEL and PS.EXCM!)
-#endif
-
-#if !XCHAL_HAVE_FULL_RESET
-
-#if XCHAL_HAVE_CCOUNT && (XCHAL_HW_MIN_VERSION < XTENSA_HWVERSION_RB_2006_0) /* pre-LX2 cores only */
- wsr a0, CCOUNT // not really necessary, but nice; best done very early
-#endif
-
- // For full MMU configs, put page table at an unmapped virtual address.
- // This ensures that accesses outside the static maps result
- // in miss exceptions rather than random behaviour.
- // Assumes XCHAL_SEG_MAPPABLE_VADDR == 0 (true in released MMU).
-#if XCHAL_ITLB_ARF_WAYS > 0 || XCHAL_DTLB_ARF_WAYS > 0
- wsr a0, PTEVADDR
-#endif
-
- // Debug initialization
- //
- // NOTE: DBREAKCn must be initialized before the combination of these two things:
- // any load/store, and a lowering of PS.INTLEVEL below DEBUG_LEVEL.
- // The processor already resets IBREAKENABLE appropriately.
- //
-#if XCHAL_HAVE_DEBUG
-# if XCHAL_NUM_DBREAK
-# if XCHAL_NUM_DBREAK >= 2
- wsr a0, DBREAKC1
-# endif
- wsr a0, DBREAKC0
- dsync // wait for WSRs to DBREAKCn to complete
-# endif
-
-# if XCHAL_HW_MIN_VERSION < XTENSA_HWVERSION_RA_2004_1 /* pre-LX cores only */
- // Starting in Xtensa LX, ICOUNTLEVEL resets to zero (not 15), so no need to initialize it.
- // Prior to that we do, otherwise we get an ICOUNT exception, 2^32 instructions after reset.
- rsr a2, ICOUNTLEVEL // are we being debugged? (detected by ICOUNTLEVEL not 15, or dropped below 12)
- bltui a2, 12, 1f // if so, avoid initializing ICOUNTLEVEL which drops single-steps through here
- wsr a0, ICOUNTLEVEL // avoid ICOUNT exceptions
- isync // wait for WSR to ICOUNTLEVEL to complete
-1:
-# endif
-#endif
-
-#endif /* !XCHAL_HAVE_FULL_RESET */
-
-
-#if XCHAL_HAVE_ABSOLUTE_LITERALS
- // Technically, this only needs to be done under !FULL_RESET, assuming hard reset:
- wsr a0, LITBASE
- rsync
-#endif
-
-#if XCHAL_HAVE_PSO_CDM && ! XCHAL_HAVE_PSO_FULL_RETENTION
- // If we're powering up from a temporary power shut-off (PSO),
- // restore state saved just prior to shut-off. Note that the
- // MEMCTL register was already restored earlier, and as a side
- // effect, registers a3, a5, a7 are now preloaded with values
- // that we will use here.
- // a3 - pointer to save area base address (_xtos_pso_savearea)
- // a5 - saved state signature (CORE_STATE_SIGNATURE)
- // a7 - contents of PWRSTAT register
-
- l32i a4, a3, CS_SA_signature // load save area signature
- sub a4, a4, a5 // compare signature with expected one
-# if XTOS_PSO_TEST
- movi a7, PWRSTAT_WAKEUP_RESET // pretend PSO warm start with warm caches
-# endif
- bbci.l a7, PWRSTAT_WAKEUP_RESET_SHIFT, 1f // wakeup from PSO? (branch if not)
- // Yes, wakeup from PSO. Check whether state was properly saved.
- addi a5, a7, - PWRSTAT_WAKEUP_RESET // speculatively clear PSO-wakeup bit
- movnez a7, a5, a4 // if state not saved (corrupted?), mark as cold start
- bnez a4, 1f // if state not saved, just continue with reset
- // Wakeup from PSO with good signature. Now check cache status:
- bbci.l a7, PWRSTAT_CACHES_LOST_POWER_SHIFT, .Lpso_restore // if caches warm, restore now
- // Caches got shutoff. Continue reset, we'll end up initializing caches, and check again later for PSO.
-# if XCHAL_HAVE_PRID && XCHAL_HAVE_S32C1I
- j .Ldonesync // skip reset sync, only done for cold start
-# endif
-1: // Cold start. (Not PSO wakeup.) Proceed with normal full reset.
-#endif
-
-#if XCHAL_HAVE_PRID && XCHAL_HAVE_S32C1I
- /* Core 0 initializes the XMP synchronization variable, if present. This operation needs to
- happen as early as possible in the startup sequence so that the other cores can be released
- from reset. */
- .weak _ResetSync
- movi a2, _ResetSync // address of sync variable
- rsr.prid a3 // core and multiprocessor ID
- extui a3, a3, 0, 8 // extract core ID (FIXME: need proper constants for PRID bits to extract)
- beqz a2, .Ldonesync // skip if no sync variable
- bnez a3, .Ldonesync // only do this on core 0
-#if defined(CONFIG_APOLLOLAKE)
- movi a2, 100 // delay here for 100 iterations if we are not core 0
-2: addi.n a2, a2, -1
- bnez a2, 2b
- j .Ldonesync
-#endif
- s32i a0, a2, 0 // clear sync variable
-.Ldonesync:
-#endif
-
-#if XCHAL_HAVE_EXTERN_REGS && XCHAL_HAVE_MP_RUNSTALL
- /* On core 0, this releases other cores. On other cores this has no effect, because
- runstall control is unconnected. */
- movi a2, XER_MPSCORE
- wer a0, a2
-#endif
-
-
- /*
- * For processors with relocatable vectors, apply any alternate
- * vector base given to xt-genldscripts, which sets the
- * _memmap_vecbase_reset symbol accordingly.
- */
-#if XCHAL_HAVE_VECBASE
- movi a2, _memmap_vecbase_reset /* note: absolute symbol, not a ptr */
- wsr a2, vecbase
-#endif
-
-#if XCHAL_HAVE_S32C1I && (XCHAL_HW_MIN_VERSION >= XTENSA_HWVERSION_RC_2009_0) /* have ATOMCTL ? */
-# if XCHAL_DCACHE_IS_COHERENT
- movi a3, 0x25 /* MX -- internal for writeback, RCW otherwise */
-# else
- movi a3, 0x15 /* non-MX -- always RCW */
-# endif
- wsr a3, ATOMCTL
-#endif
-
-#if XCHAL_HAVE_INTERRUPTS && XCHAL_HAVE_DEBUG
- rsil a2, 1 // lower PS.INTLEVEL here to make reset vector easier to debug
-#endif
-
- /* If either of the caches does not have dynamic way support, then
- * use the old (slow) method to init them. If the cache is absent
- * the macros will expand to empty.
- */
-#if ! XCHAL_HAVE_ICACHE_DYN_WAYS
- icache_reset a2, a3
-#endif
-#if ! XCHAL_HAVE_DCACHE_DYN_WAYS
- dcache_reset a2, a3
-#endif
-
-#if XCHAL_HAVE_PSO_CDM && ! XCHAL_HAVE_PSO_FULL_RETENTION
- // Here, a7 still contains status from the power status register,
- // or zero if signature check failed.
- bbci.l a7, PWRSTAT_WAKEUP_RESET_SHIFT, .Lcoldstart // wakeup from PSO with good signature?
- // Yes, wakeup from PSO. Caches had been powered down, now are initialized.
-.Lpso_restore:
- // Assume memory still initialized, so all code still unpacked etc.
- // So we can just jump/call to relevant state restore code (wherever located).
- movi a2, 0 // make shutoff routine return zero
- movi a3, _xtos_pso_savearea
- // Here, as below for _start, call0 is used as an unlimited-range jump.
- call0 _xtos_core_restore_nw
- // (does not return)
-.Lcoldstart:
-#endif
-
-#if XCHAL_HAVE_PREFETCH
- /* Enable cache prefetch if present. */
-#if defined(CONFIG_APOLLOLAKE)
- movi.n a2, 34
-#else
- movi.n a2, 68
-#endif
- wsr a2, PREFCTL
-#endif
- /*
- * Now "enable" the caches.
- * We do this ahead of unpacking, so it can proceed more efficiently.
- *
- * The _memmap_cacheattr_reset symbol's value (address) is defined
- * by the LSP's linker script, as generated by xt-genldscripts.
- *
- * (NOTE: for configs that don't have CACHEATTR or region protection,
- * ie. for full MMUs, there is no equivalent cache attribute layout,
- * and the following code has no effect. We assume for now that the
- * application restricts itself to the static TLB entries, i.e. to
- * virtual addresses 0xD0000000 thru 0xFFFFFFFF.)
- */
-#if XCHAL_HAVE_CACHEATTR || XCHAL_HAVE_MIMIC_CACHEATTR || XCHAL_HAVE_XLT_CACHEATTR \
- || (XCHAL_HAVE_PTP_MMU && XCHAL_HAVE_SPANNING_WAY)
- movi a2, _memmap_cacheattr_reset /* note: absolute symbol, not a ptr */
- cacheattr_set /* set CACHEATTR from a2 (clobbers a3-a8) */
-#endif
- /* Now that caches are initialized, cache coherency can be enabled. */
-#if XCHAL_DCACHE_IS_COHERENT
-# if XCHAL_HAVE_EXTERN_REGS && XCHAL_HAVE_MX && (XCHAL_HW_MIN_VERSION < XTENSA_HWVERSION_RE_2012_0)
- /* Opt into coherence for MX (for backward compatibility / testing). */
- movi a3, 1
- movi a2, XER_CCON
- wer a3, a2
-# endif
-#endif
-#if (XCHAL_DCACHE_IS_COHERENT || XCHAL_LOOP_BUFFER_SIZE) && XCHAL_HW_MIN_VERSION >= XTENSA_HWVERSION_RE_2012_0 /* have MEMCTL ? */
- /* Enable zero-overhead loop instr buffer, and snoop responses, if configured. */
- movi a3, (MEMCTL_SNOOP_EN | MEMCTL_L0IBUF_EN)
- rsr a2, MEMCTL
- or a2, a2, a3
- wsr a2, MEMCTL
-#endif
-
- /* Caches are all up and running, clear PWRCTL.ShutProcOffOnPWait. */
-#if XCHAL_HAVE_PSO_CDM
- movi a2, XDM_MISC_PWRCTL
- movi a4, ~PWRCTL_CORE_SHUTOFF
- rer a3, a2
- and a3, a3, a4
- wer a3, a2
-#endif
-
-#endif /* !XCHAL_HAVE_HALT */
-
- /*
- * Unpack code and data (eg. copy ROMed segments to RAM, vectors into
- * their proper location, etc).
- */
-
-#if defined(XTOS_UNPACK)
- movi a2, _rom_store_table
- beqz a2, unpackdone
-unpack: l32i a3, a2, 0 // start vaddr
- l32i a4, a2, 4 // end vaddr
- l32i a5, a2, 8 // store vaddr
- addi a2, a2, 12
- bgeu a3, a4, upnext // skip unless start < end
-uploop: l32i a6, a5, 0
- addi a5, a5, 4
- s32i a6, a3, 0
- addi a3, a3, 4
- bltu a3, a4, uploop
- j unpack
-upnext: bnez a3, unpack
- bnez a5, unpack
-#endif /* XTOS_UNPACK */
-
-unpackdone:
-
-#if defined(XTOS_UNPACK) || defined(XTOS_MP)
- /*
- * If writeback caches are configured and enabled, unpacked data must be
- * written out to memory before trying to execute it:
- */
- dcache_writeback_all a2, a3, 0
- icache_sync a2 // ensure data written back is visible to i-fetch
- /*
- * Note: no need to invalidate the i-cache after the above, because we
- * already invalidated it further above and did not execute anything within
- * unpacked regions afterwards. [Strictly speaking, if an unpacked region
- * follows this code very closely, it's possible for cache-ahead to have
- * cached a bit of that unpacked region, so in the future we may need to
- * invalidate the entire i-cache here again anyway.]
- */
-#endif
-
-
-#if !XCHAL_HAVE_HALT /* skip for TX */
-
- /*
- * Now that we know the .lit4 section is present (if got unpacked)
- * (and if absolute literals are used), initialize LITBASE to use it.
- */
-#if XCHAL_HAVE_ABSOLUTE_LITERALS && XSHAL_USE_ABSOLUTE_LITERALS
- /*
- * Switch from PC-relative to absolute (litbase-relative) L32R mode.
- * Set LITBASE to 256 kB beyond the start of the literals in .lit4
- * (aligns to the nearest 4 kB boundary, LITBASE does not have bits 1..11)
- * and set the enable bit (_lit4_start is assumed 4-byte aligned).
- */
- movi a2, _lit4_start + 0x40001
- wsr a2, LITBASE
- rsync
-#endif /* have and use absolute literals */
- .end no-absolute-literals // we can now start using absolute literals
-
-
-// Technically, this only needs to be done pre-LX2, assuming hard reset:
-# if XCHAL_HAVE_WINDOWED && defined(__XTENSA_WINDOWED_ABI__)
- // Windowed register init, so we can call windowed code (eg. C code).
- movi a1, 1
- wsr a1, WINDOWSTART
- // The processor always clears WINDOWBASE at reset, so no need to clear it here.
- // It resets WINDOWSTART to 1 starting with LX2.0/X7.0 (RB-2006.0).
- // However, assuming hard reset is not yet always practical, so do this anyway:
- wsr a0, WINDOWBASE
- rsync
- movi a0, 0 // possibly a different a0, clear it
-# endif
-
-#if XCHAL_HW_MIN_VERSION < XTENSA_HWVERSION_RB_2006_0 /* only pre-LX2 needs this */
- // Coprocessor option initialization
-# if XCHAL_HAVE_CP
- //movi a2, XCHAL_CP_MASK // enable existing CPs
- // To allow creating new coprocessors using TC that are not known
- // at GUI build time without having to explicitly enable them,
- // all CPENABLE bits must be set, even though they may not always
- // correspond to a coprocessor.
- movi a2, 0xFF // enable *all* bits, to allow dynamic TIE
- wsr a2, CPENABLE
-# endif
-
- // Floating point coprocessor option initialization (at least
- // rounding mode, so that floating point ops give predictable results)
-# if XCHAL_HAVE_FP && !XCHAL_HAVE_VECTORFPU2005
-# define FCR 232 /* floating-point control register (user register number) */
-# define FSR 233 /* floating-point status register (user register number) */
- rsync /* wait for WSR to CPENABLE to complete before accessing FP coproc state */
- wur a0, FCR /* clear FCR (default rounding mode, round-nearest) */
- wur a0, FSR /* clear FSR */
-# endif
-#endif /* pre-LX2 */
-
-
- // Initialize memory error handler address.
- // Putting this address in a register allows multiple instances of
- // the same configured core (with separate program images but shared
- // code memory, thus forcing memory error vector to be shared given
- // it is not VECBASE relative) to have the same memory error vector,
- // yet each have their own handler and associated data save area.
-#if XCHAL_HAVE_MEM_ECC_PARITY_IGNORE
- movi a4, _MemErrorHandler
- wsr a4, MESAVE
-#endif
-
-
- /*
- * Initialize medium and high priority interrupt dispatchers:
- */
-#if HAVE_XSR
-
-#if !defined(CONFIG_BOOT_LOADER)
-/* For asm macros; works for positive a,b smaller than 1000: */
-# define GREATERTHAN(a,b) (((b)-(a)) & ~0xFFF)
-
-# ifndef XCHAL_DEBUGLEVEL /* debug option not selected? */
-# define XCHAL_DEBUGLEVEL 99 /* bogus value outside 2..6 */
-# endif
-
- .macro init_vector level
- .if GREATERTHAN(XCHAL_NUM_INTLEVELS+1,\level)
- .if XCHAL_DEBUGLEVEL-\level
- .weak _Level&level&FromVector
- movi a4, _Level&level&FromVector
- wsr a4, EXCSAVE+\level
- .if GREATERTHAN(\level,XCHAL_EXCM_LEVEL)
- movi a5, _Pri_&level&_HandlerAddress
- s32i a4, a5, 0
- /* If user provides their own handler, that handler might
- * not provide its own _Pri_<n>_HandlerAddress variable for
- * linking handlers. In that case, the reference below
- * would pull in the XTOS handler anyway, causing a conflict.
- * To avoid that, provide a weak version of it here:
- */
- .pushsection .data, "aw"
- .global _Pri_&level&_HandlerAddress
- .weak _Pri_&level&_HandlerAddress
- .align 4
- _Pri_&level&_HandlerAddress: .space 4
- .popsection
- .endif
- .endif
- .endif
- .endm
-
- init_vector 2
- init_vector 3
- init_vector 4
- init_vector 5
- init_vector 6
-#endif
-#endif /*HAVE_XSR*/
-
-
- /*
- * Complete reset initialization outside the vector,
- * to avoid requiring a vector that is larger than necessary.
- * This 2nd-stage startup code sets up the C Run-Time (CRT) and calls main().
- *
- * Here we use call0 not because we expect any return, but
- * because the assembler/linker dynamically sizes call0 as
- * needed (with -mlongcalls) which it doesn't with j or jx.
- * Note: This needs to be call0 regardless of the selected ABI.
- */
-
-#if CONFIG_BOOT_LOADER
- /*ToDo refine the _start*/
- movi a0, SOF_TEXT_START
- callx0 a0
-#else
- call0 _start // jump to _start (in crt1-*.S)
-#endif
-
- /* does not return */
-
-#else /* XCHAL_HAVE_HALT */
-
- j _start // jump to _start (in crt1-*.S)
- // (TX has max 64kB IRAM, so J always in range)
-
- // Paranoia -- double-check requirements / assumptions of this Xtensa TX code:
-# if !defined(__XTENSA_CALL0_ABI__) || !XCHAL_HAVE_FULL_RESET || XCHAL_HAVE_INTERRUPTS || XCHAL_HAVE_CCOUNT || XCHAL_DTLB_ARF_WAYS || XCHAL_HAVE_DEBUG || XCHAL_HAVE_S32C1I || XCHAL_HAVE_ABSOLUTE_LITERALS || XCHAL_DCACHE_SIZE || XCHAL_ICACHE_SIZE || XCHAL_HAVE_PIF || XCHAL_HAVE_WINDOWED
-# error "Halt architecture (Xtensa TX) requires: call0 ABI, all flops reset, no exceptions or interrupts, no TLBs, no debug, no S32C1I, no LITBASE, no cache, no PIF, no windowed regs"
-# endif
-
-#endif /* XCHAL_HAVE_HALT */
-
-
-#if (!XCHAL_HAVE_HALT || defined(XTOS_UNPACK)) && XCHAL_HAVE_IMEM_LOADSTORE
- .size _ResetHandler, . - _ResetHandler
-#else
- .size _ResetVector, . - _ResetVector
-#endif
-
-#if defined(CONFIG_APOLLOLAKE)
- .align 4
- .global _call_init
- .type _call_init,@function
-
-_call_init:
- ret.n
- .size _call_init, . - _call_init
-#endif
-
- .text
- .global xthals_hw_configid0, xthals_hw_configid1
- .global xthals_release_major, xthals_release_minor
- .end literal_prefix
diff --git a/src/arch/xtensa/up/xtos/shared-reset-vector.S b/src/arch/xtensa/up/xtos/shared-reset-vector.S
deleted file mode 100644
index ae457f9..0000000
--- a/src/arch/xtensa/up/xtos/shared-reset-vector.S
+++ /dev/null
@@ -1,73 +0,0 @@
-// shared-reset-vector.S -- Sharable Reset Vector (requires PRID option)
-
-// Copyright (c) 1999-2010 Tensilica Inc.
-//
-// Permission is hereby granted, free of charge, to any person obtaining
-// a copy of this software and associated documentation files (the
-// "Software"), to deal in the Software without restriction, including
-// without limitation the rights to use, copy, modify, merge, publish,
-// distribute, sublicense, and/or sell copies of the Software, and to
-// permit persons to whom the Software is furnished to do so, subject to
-// the following conditions:
-//
-// The above copyright notice and this permission notice shall be included
-// in all copies or substantial portions of the Software.
-//
-// THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
-// EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
-// MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
-// IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY
-// CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
-// TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
-// SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
-
-#include <xtensa/coreasm.h>
-
- // Populate this processor's entry in the reset table.
- // The core instance specific LSP should put this section
- // in the correct location within the table.
- //
- .section .ResetTable.rodata, "a"
- .word _ResetHandler
-
- // This sharable reset code assumes RC-2009.0 or later hardware,
- // to guarantee that no processor state initialization is required
- // prior to doing loads etc.
- // Total size is 28 bytes (or 27 with density option).
- // By necessity, none of these bytes vary by core instance;
- // the appropriate reset table entry is selected using PRID.
- //
-#if XCHAL_HAVE_PRID
- .section .SharedResetVector.text, "ax"
- .begin no-absolute-literals
-
- .align 4
- .global _SharedResetVector
-_SharedResetVector:
- j .LSharedResetHandler
-
- .align 4
- .literal_position
-
- // Use L32R if available
-#if XCHAL_HAVE_L32R
- .literal rtbase, _ResetTable_base
-#endif
-
- .align 4
-.LSharedResetHandler:
- rsr.prid a0 // get processor ID (16 bits)
-#if XCHAL_HAVE_L32R
- l32r a1, rtbase // force use of L32R
-#else
- movi a1, _ResetTable_base // No L32R, will likely become CONST16
-#endif
- extui a0, a0, 0, 4 // ID of core within the multiprocessor (FIXME: need proper constant...)
- addx4 a1, a0, a1
- l32i a1, a1, 0
- jx a1 // jump to core-specific initialization
-
- .size _SharedResetVector, . - _SharedResetVector
- .end no-absolute-literals
-#endif
-
diff --git a/src/arch/xtensa/up/xtos/switch_context.S b/src/arch/xtensa/up/xtos/switch_context.S
deleted file mode 100644
index c70c0c8..0000000
--- a/src/arch/xtensa/up/xtos/switch_context.S
+++ /dev/null
@@ -1,94 +0,0 @@
-/* switch_contexts.S - setup for multiple contexts */
-
-/*
- * Copyright (c) 2003-2010 Tensilica Inc.
- *
- * Permission is hereby granted, free of charge, to any person obtaining
- * a copy of this software and associated documentation files (the
- * "Software"), to deal in the Software without restriction, including
- * without limitation the rights to use, copy, modify, merge, publish,
- * distribute, sublicense, and/or sell copies of the Software, and to
- * permit persons to whom the Software is furnished to do so, subject to
- * the following conditions:
- *
- * The above copyright notice and this permission notice shall be included
- * in all copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
- * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
- * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
- * IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY
- * CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
- * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
- * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
- */
-
-#include <xtensa/coreasm.h>
-#include <xtensa/xtruntime-frames.h>
-
-#if XCHAL_NUM_CONTEXTS > 1
-
-
-/*
- * void _xtos_setup_context(int context_num, StartInfo *info);
- */
- .align 4
- .global _xtos_setup_context
- .type _xtos_setup_context,@function
-_xtos_setup_context:
- abi_entry
-#if XCHAL_HAVE_INTERRUPTS
- rsil a5, 15 /* disable interrupts so we can use EXCSAVE_1 */
-#else
- rsr a5, PS /* just read PS */
-#endif
- wsr a3, EXCSAVE_1 /* save pointer to new context info */
- s32i a5, a3, INFO_prevps /* save previous PS */
- movi a4, ~0x01F00000 /* mask out PS.CTXT */
- slli a2, a2, 20 /* shift up new PS.CTXT value */
- and a4, a5, a4
- or a4, a4, a2 /* new PS value */
- wsr a4, PS
- rsync
- /* We're now in the new context! */
- movi a0, 0
- movi a1, 1
- wsr a1, WINDOWSTART
- wsr a0, WINDOWBASE
- rsync
- rsr a9, EXCSAVE_1 /* get pointer to context info */
- movi a0, 0 /* terminate call frames */
- l32i a1, a9, INFO_sp /* get stack pointer */
- l32i a10, a9, INFO_arg1 /* get start function's arguments... */
- l32i a8, a9, INFO_funcpc /* get start function's address */
- /* Okay, now switch back to context zero: */
- l32i a9, a9, INFO_prevps /* retrieve previous PS */
- wsr a9, PS
- rsync
- /* Back to original context! */
- abi_return
-
- .size _xtos_setup_context, . - _xtos_setup_context
-
-
-
- /*
- * This is the first thing to be executed in the new context
- * by explicit setting of PC:
- */
- .align 4
- .global _xtos_start_context
-_xtos_start_context:
-#ifdef __XTENSA_CALL0_ABI__
- Crash the assembler here: I think this is wrong.
- callx0 a8
-#else
- callx8 a8
-#endif
-1: nop
- j 1b /* do nothing until context 0 exits */
- .size _xtos_start_context, . - _xtos_start_context
-
-
-#endif /* XCHAL_NUM_CONTEXTS > 1 */
-
diff --git a/src/arch/xtensa/up/xtos/textaddr b/src/arch/xtensa/up/xtos/textaddr
deleted file mode 100755
index 91eb8c9..0000000
--- a/src/arch/xtensa/up/xtos/textaddr
+++ /dev/null
@@ -1,59 +0,0 @@
-# Program to determine -Ttext parameter for ld
-# $Id: //depot/rel/Eaglenest/Xtensa/OS/xtos/textaddr#1 $
-
-# Copyright (c) 2001 Tensilica Inc.
-#
-# Permission is hereby granted, free of charge, to any person obtaining
-# a copy of this software and associated documentation files (the
-# "Software"), to deal in the Software without restriction, including
-# without limitation the rights to use, copy, modify, merge, publish,
-# distribute, sublicense, and/or sell copies of the Software, and to
-# permit persons to whom the Software is furnished to do so, subject to
-# the following conditions:
-#
-# The above copyright notice and this permission notice shall be included
-# in all copies or substantial portions of the Software.
-#
-# THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
-# EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
-# MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
-# IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY
-# CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
-# TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
-# SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
-
-package textaddr;
-
-use strict;
-use FileHandle;
-
-{
- $::myname = 'textaddr';
-
- die("Usage is: $::myname objfile label address\n")
- unless @ARGV == 3;
- my($objfile, $label, $address) = @ARGV;
-
-
- my $nm = new FileHandle "xt-nm $objfile|";
- die("$::myname: $!, opening pipe to xt-nm $objfile.\n")
- unless $nm;
- while (<$nm>) {
- if (/^([0-9a-f]{8}) . (\w+)$/) {
- my $oaddress = $1;
- my $olabel = $2;
- if ($olabel eq $label) {
- printf ("0x%x\n", hex($address) - hex($oaddress));
- exit(0);
- }
- }
- }
- die ("$::myname: $label not found in $objfile.\n");
-}
-
-#
-# Local Variables:
-# mode:perl
-# perl-indent-level:2
-# cperl-indent-level:2
-# End:
diff --git a/src/arch/xtensa/up/xtos/tiny-refs-min.S b/src/arch/xtensa/up/xtos/tiny-refs-min.S
deleted file mode 100644
index 453001c..0000000
--- a/src/arch/xtensa/up/xtos/tiny-refs-min.S
+++ /dev/null
@@ -1,28 +0,0 @@
-// tiny-refs-min.S - References to pull-in selected modules into tiny LSPs
-
-// Copyright (c) 2006 Tensilica Inc.
-//
-// Permission is hereby granted, free of charge, to any person obtaining
-// a copy of this software and associated documentation files (the
-// "Software"), to deal in the Software without restriction, including
-// without limitation the rights to use, copy, modify, merge, publish,
-// distribute, sublicense, and/or sell copies of the Software, and to
-// permit persons to whom the Software is furnished to do so, subject to
-// the following conditions:
-//
-// The above copyright notice and this permission notice shall be included
-// in all copies or substantial portions of the Software.
-//
-// THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
-// EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
-// MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
-// IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY
-// CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
-// TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
-// SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
-
-
- .global _need_user_vector_
- .set _need_user_vector_, 0 // define this, so if referenced...
- .global _UserExceptionVector // ... we pull-in this
-
diff --git a/src/arch/xtensa/up/xtos/tiny-refs.S b/src/arch/xtensa/up/xtos/tiny-refs.S
deleted file mode 100644
index d89407e..0000000
--- a/src/arch/xtensa/up/xtos/tiny-refs.S
+++ /dev/null
@@ -1,33 +0,0 @@
-// tiny-refs.S - References to pull-in selected modules into tiny LSPs
-
-// Copyright (c) 2006 Tensilica Inc.
-//
-// Permission is hereby granted, free of charge, to any person obtaining
-// a copy of this software and associated documentation files (the
-// "Software"), to deal in the Software without restriction, including
-// without limitation the rights to use, copy, modify, merge, publish,
-// distribute, sublicense, and/or sell copies of the Software, and to
-// permit persons to whom the Software is furnished to do so, subject to
-// the following conditions:
-//
-// The above copyright notice and this permission notice shall be included
-// in all copies or substantial portions of the Software.
-//
-// THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
-// EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
-// MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
-// IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY
-// CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
-// TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
-// SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
-
-#if defined(__SPLIT__level1int)
-
- .global _need_level1int_
- .set _need_level1int_, 0 // define this, so if referenced...
- .global _need_user_vector_ // ... we pull-in this
- .global _xtos_l1int_handler // and this
-
-#endif
-
-
diff --git a/src/arch/xtensa/up/xtos/user-vector-min.S b/src/arch/xtensa/up/xtos/user-vector-min.S
deleted file mode 100644
index d1d9669..0000000
--- a/src/arch/xtensa/up/xtos/user-vector-min.S
+++ /dev/null
@@ -1,112 +0,0 @@
-// user-vector-min.S - Minimal User Vector for General Exceptions
-// Takes less table space, but does not allow registering new handlers.
-// $Id: //depot/rel/Eaglenest/Xtensa/OS/xtos/user-vector-min.S#2 $
-
-// Copyright (c) 2003-2004, 2006-2007, 2010 Tensilica Inc.
-//
-// Permission is hereby granted, free of charge, to any person obtaining
-// a copy of this software and associated documentation files (the
-// "Software"), to deal in the Software without restriction, including
-// without limitation the rights to use, copy, modify, merge, publish,
-// distribute, sublicense, and/or sell copies of the Software, and to
-// permit persons to whom the Software is furnished to do so, subject to
-// the following conditions:
-//
-// The above copyright notice and this permission notice shall be included
-// in all copies or substantial portions of the Software.
-//
-// THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
-// EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
-// MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
-// IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY
-// CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
-// TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
-// SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
-
-#include <xtensa/coreasm.h>
-#include <xtensa/config/system.h>
-#include "xtos-internal.h"
-
-#if XCHAL_HAVE_EXCEPTIONS
-
- // Vector code
- .begin literal_prefix .UserExceptionVector
- .section .UserExceptionVector.text, "ax"
- .align 4
- .global _UserExceptionVector
-_UserExceptionVector:
-# if (((XSHAL_USER_VECTOR_SIZE >= 28) && XCHAL_HAVE_DENSITY) || XSHAL_VECTORS_PACKED) && !((XSHAL_USER_VECTOR_SIZE < 30) && XCHAL_ERRATUM_453)
-
- isync_erratum453
- addi a1, a1, -ESF_TOTALSIZE // allocate exception stack frame, etc.
- s32i a2, a1, UEXC_a2
- s32i a3, a1, UEXC_a3
- rsr a2, EXCCAUSE // get exception cause
- movi a3, _xtos_min_handler_table
- bgeui a2, 6, 1f // causes 6 and above map to zero
- addx4 a3, a2, a3 // index by cause if 1 .. 5
-1: l32i a3, a3, 0
- s32i a4, a1, UEXC_a4
- jx a3 // jump to cause-specific handler
-
- .size _UserExceptionVector, . - _UserExceptionVector
- .end literal_prefix
-
-# else /*vector as small as 12 bytes:*/
-
- addi a1, a1, -ESF_TOTALSIZE // allocate exception stack frame, etc.
- s32i a2, a1, UEXC_a2
- movi a2, _UserExceptionFromVector // load user exception handler address
- //interlock
- jx a2 // jump to handler
-
- .size _UserExceptionVector, . - _UserExceptionVector
- .end literal_prefix
-
- // Dispatch outside vector:
- .text
- .align 4
- .global _UserExceptionFromVector
-_UserExceptionFromVector:
-
- isync_erratum453
- rsr a2, EXCCAUSE // get exception cause
- s32i a3, a1, UEXC_a3
- movi a3, _xtos_min_handler_table
- bgeui a2, 6, 1f // causes 6 and above map to zero
- addx4 a3, a2, a3 // index by cause if 1 .. 5
-1: l32i a3, a3, 0
- s32i a4, a1, UEXC_a4
- jx a3 // jump to cause-specific handler
- .size _UserExceptionFromVector, . - _UserExceptionFromVector
-
-# endif /*XEA2*/
-
-
- /*
- * Read-only minimal table of assembly-level exception handlers
- * for user vectored exceptions.
- * Only provides entries for SYSCALL, MOVSP, and level-1 interrupt causes.
- */
- .section .rodata, "a"
- .global _xtos_min_handler_table
- .align 4
-_xtos_min_handler_table:
- .word _xtos_unhandled_exception // 0 Illegal Instruction, and causes > 5
- .word _xtos_syscall_handler // 1 SYSCALL Instruction
- .word _xtos_unhandled_exception // 2 Instruction Fetch Error
- .word _xtos_unhandled_exception // 3 Load/Store Error
-# if XCHAL_HAVE_INTERRUPTS
- .word _xtos_l1int_handler // 4 Level-1 Interrupt
-# else
- .word _xtos_unhandled_exception // 4 Level-1 Interrupt (not configured)
-# endif
-# if XCHAL_HAVE_WINDOWED && !defined(__XTENSA_CALL0_ABI__)
- .word _xtos_alloca_handler // 5 Alloca (MOVSP Instruction)
-# else
- .word _xtos_unhandled_exception // 5 Alloca (MOVSP Instruction) (not configured)
-# endif
- .text
-
-#endif /* XCHAL_HAVE_EXCEPTIONS */
-
diff --git a/src/arch/xtensa/up/xtos/user-vector.S b/src/arch/xtensa/up/xtos/user-vector.S
deleted file mode 100644
index 16f13b9..0000000
--- a/src/arch/xtensa/up/xtos/user-vector.S
+++ /dev/null
@@ -1,187 +0,0 @@
-// user-vector.S - User Vector for General Exceptions
-// $Id: //depot/rel/Eaglenest/Xtensa/OS/xtos/user-vector.S#2 $
-
-// Copyright (c) 1998-2010 Tensilica Inc.
-//
-// Permission is hereby granted, free of charge, to any person obtaining
-// a copy of this software and associated documentation files (the
-// "Software"), to deal in the Software without restriction, including
-// without limitation the rights to use, copy, modify, merge, publish,
-// distribute, sublicense, and/or sell copies of the Software, and to
-// permit persons to whom the Software is furnished to do so, subject to
-// the following conditions:
-//
-// The above copyright notice and this permission notice shall be included
-// in all copies or substantial portions of the Software.
-//
-// THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
-// EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
-// MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
-// IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY
-// CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
-// TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
-// SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
-
-#include <xtensa/coreasm.h>
-#include <xtensa/config/system.h>
-#include "xtos-internal.h"
-
-#if XCHAL_HAVE_EXCEPTIONS
-
- // Vector code
- .section .UserExceptionVector.text, "ax"
- .align 4
- .global _UserExceptionVector
-_UserExceptionVector:
-# if (((XSHAL_USER_VECTOR_SIZE >= 28) && XCHAL_HAVE_ADDX) || (XSHAL_USER_VECTOR_SIZE >= 36) || XSHAL_VECTORS_PACKED) && !((XSHAL_USER_VECTOR_SIZE < 30) && XCHAL_ERRATUM_453)
- // There is space to dispatch right at the vector:
-
- isync_erratum453
- addi a1, a1, -ESF_TOTALSIZE // allocate exception stack frame, etc.
- s32i a2, a1, UEXC_a2
- s32i a3, a1, UEXC_a3
- movi a3, _xtos_exc_handler_table
- rsr a2, EXCCAUSE // get exception cause
- //interlock
- addx4 a3, a2, a3
- l32i a3, a3, 0
- s32i a4, a1, UEXC_a4
- jx a3 // jump to cause-specific handler
-
- .size _UserExceptionVector, . - _UserExceptionVector
-
-# else
- // The vector may be as small as 12 bytes:
-
- addi a1, a1, -ESF_TOTALSIZE // allocate exception stack frame, etc.
- s32i a2, a1, UEXC_a2
- movi a2, _UserExceptionFromVector // load user exception handler address
- //interlock
- jx a2 // jump to handler
-
- .size _UserExceptionVector, . - _UserExceptionVector
-
- // Dispatch outside vector:
- .text
- //.subsection 2
- .align 4
- .global _UserExceptionFromVector
-_UserExceptionFromVector:
-
- isync_erratum453
- s32i a3, a1, UEXC_a3
- movi a3, _xtos_exc_handler_table
- rsr a2, EXCCAUSE // get exception cause
- s32i a4, a1, UEXC_a4
- addx4 a3, a2, a3
- l32i a3, a3, 0
- jx a3 // jump to cause-specific handler
-
- .size _UserExceptionFromVector, . - _UserExceptionFromVector
-
-# endif /*XEA2*/
-
-
- .weak _xtos_cause3_handler
-
- /*
- * Table of assembly-level general-exception handlers
- * (quickly entered) for user vectored exceptions.
- * Provides entries for all possible 64 exception causes
- * currently allowed for in the EXCCAUSE register.
- *
- * NOTE: entries that have a corresponding C handler
- * (registered at run-time) point to _xtos_c_wrapper_handler;
- * entries that have no handler point to _xtos_unhandled_exception.
- */
- .data
- .global _xtos_exc_handler_table
- .align 4
-_xtos_exc_handler_table:
- .word _xtos_unhandled_exception // 0 IllegalInstruction
- .word _xtos_syscall_handler // 1 Syscall
- .word _xtos_unhandled_exception // 2 InstructionFetchError
- .word _xtos_unhandled_exception // 3 LoadStoreError
-# if XCHAL_HAVE_INTERRUPTS
- .word _xtos_l1int_handler // 4 Level1Interrupt
-# else
- .word _xtos_unhandled_exception // 4 Level1Interrupt (not configured)
-# endif
-# if XCHAL_HAVE_WINDOWED && !defined(__XTENSA_CALL0_ABI__)
- .word _xtos_alloca_handler // 5 Alloca (MOVSP)
-# else
- .word _xtos_unhandled_exception // 5 Alloca (MOVSP) (not configured)
-# endif
- .word _xtos_unhandled_exception // 6 IntegerDivideByZero
- .word _xtos_unhandled_exception // 7 Speculation
- .word _xtos_unhandled_exception // 8 Privileged
- .word _xtos_unhandled_exception // 9 Unaligned
- .word _xtos_unhandled_exception //10 (reserved for Tensilica)
- .word _xtos_unhandled_exception //11 (reserved for Tensilica)
- .word _xtos_cause3_handler //12 PIF data error on fetch
- .word _xtos_cause3_handler //13 PIF data error on ld/st
- .word _xtos_cause3_handler //14 PIF address error on fetch
- .word _xtos_cause3_handler //15 PIF address error on ld/st
- .word _xtos_unhandled_exception //16 InstTLBMiss
- .word _xtos_unhandled_exception //17 InstTLBMultiHit
- .word _xtos_unhandled_exception //18 InstFetchPrivilege
- .word _xtos_unhandled_exception //19 (reserved for Tensilica)
- .word _xtos_unhandled_exception //20 InstFetchProhibited
- .word _xtos_unhandled_exception //21 (reserved for Tensilica)
- .word _xtos_unhandled_exception //22 (reserved for Tensilica)
- .word _xtos_unhandled_exception //23 (reserved for Tensilica)
- .word _xtos_unhandled_exception //24 LoadStoreTLBMiss
- .word _xtos_unhandled_exception //25 LoadStoreTLBMultiHit
- .word _xtos_unhandled_exception //26 LoadStorePrivilege
- .word _xtos_unhandled_exception //27 (reserved for Tensilica)
- .word _xtos_unhandled_exception //28 LoadProhibited
- .word _xtos_unhandled_exception //29 StoreProhibited
- .word _xtos_unhandled_exception //30 (reserved for Tensilica)
- .word _xtos_unhandled_exception //31 (reserved for Tensilica)
- .rept 8
- .word _xtos_unhandled_exception //32-39 Coprocessor<n>Disabled (n = 0..7)
- .endr
-
- .rept XCHAL_EXCCAUSE_NUM-40
- .word _xtos_unhandled_exception //40-63 (reserved for TIE)
- .endr
-
- .text
-
-
- // NOTES:
- //
- // Here are alternative vectors. They will NOT work with
- // the handlers currently provided with XTOS. However they
- // might be useful to someone writing their own handlers
- // from scratch. Note that XSR is only available on T1040
- // and later hardware.
- //
-//*** The typical tiny 9-byte vector: ***
-// wsr a3, EXCSAVE_1 // save user a3
-// movi a3, _UserExceptionFromVector // load user exception handler address
-// jx a3
-//
-//*** Minimizing EXCCAUSE-dispatch delay, not assuming valid SP: ***
-// wsr a0, DEPC // save a0 (double exceptions fatal here, so not expected)
-// rsr a0, EXCCAUSE
-// xsr a1, EXCSAVE_1 // EXCSAVE_1 always contains &exception_handlers[0]
-// //interlock
-// addx4 a0, a0, a1
-// l32i a0, a0, TABLE_OFS + EXC_CODE_KERNEL*4
-// xsr a1, EXCSAVE_1 // restore a1 (DEPC contains original a0)
-// jx a0 // jump to cause-specific handler
-//
-//*** Doing EXCCAUSE-dispatch with table in EXCSAVE_1: ***
-// addi a1, a1, -ESF_TOTALSIZE // allocate exception stack frame, etc.
-// s32i a2, a1, UEXC_a2
-// rsr a2, EXCCAUSE
-// xsr a4, EXCSAVE_1 // EXCSAVE_1 always contains &exception_handlers[0]
-// s32i a3, a1, UEXC_a3
-// addx4 a2, a2, a4
-// l32i a2, a2, TABLE_OFS + EXC_CODE_KERNEL*4
-// xsr a4, EXCSAVE_1 // restore a1 (DEPC contains original a0)
-// jx a2 // jump to cause-specific handler
-
-#endif /* XCHAL_HAVE_EXCEPTIONS */
-
diff --git a/src/arch/xtensa/up/xtos/window-vectors-new.S b/src/arch/xtensa/up/xtos/window-vectors-new.S
deleted file mode 100644
index 34acebc..0000000
--- a/src/arch/xtensa/up/xtos/window-vectors-new.S
+++ /dev/null
@@ -1,343 +0,0 @@
-// window-vectors-new.S - Register Window Overflow/Underflow Handlers for XEA2
-// $Id: //depot/rel/Eaglenest/Xtensa/OS/xtos/window-vectors-new.S#2 $
-
-// Copyright (c) 1999-2013 Tensilica Inc.
-//
-// Permission is hereby granted, free of charge, to any person obtaining
-// a copy of this software and associated documentation files (the
-// "Software"), to deal in the Software without restriction, including
-// without limitation the rights to use, copy, modify, merge, publish,
-// distribute, sublicense, and/or sell copies of the Software, and to
-// permit persons to whom the Software is furnished to do so, subject to
-// the following conditions:
-//
-// The above copyright notice and this permission notice shall be included
-// in all copies or substantial portions of the Software.
-//
-// THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
-// EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
-// MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
-// IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY
-// CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
-// TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
-// SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
-
-#include <xtensa/coreasm.h>
-#include <xtensa/xtruntime-frames.h>
-
-#if !XCHAL_HAVE_XEA1
-#if XCHAL_HAVE_WINDOWED && !defined(__XTENSA_CALL0_ABI__)
-
-# ifndef NO_SECTION_DIRECTIVES
-// Exports
-.global _WindowOverflow4
-.global _WindowUnderflow4
-.global _WindowOverflow8
-.global _WindowUnderflow8
-.global _WindowOverflow12
-.global _WindowUnderflow12
-.global _xtos_alloca_handler
-
- // Note: the current window exception vectors do not generate any
- // literals. Hence the literal_prefix directive is not necessary.
- // Specifying it "just in case" creates an empty section (named
- // ".WindowVectors.literal") which can in some cases cause linking
- // problems (the linker scripts don't place it anywhere).
- // So leave it commented out:
- //
- //.begin literal_prefix .WindowVectors
-
- .section .WindowVectors.text, "ax"
-# endif
-
-
-//
-// GENERAL NOTES:
-//
-// These window exception handlers need not be modified.
-// They are specific to the windowed call ABI only.
-//
-// Underflow Handlers:
-//
-// The underflow handler for returning from call[i+1] to call[i]
-// must preserve all the registers from call[i+1]'s window.
-// In particular, a0 and a1 must be preserved because the RETW instruction
-// will be reexecuted (and may even underflow again if an intervening
-// exception has flushed call[i]'s registers).
-// Registers a2 and up may contain return values.
-//
-// The caller could also potentially assume that the callee's a0 and a1
-// (its own a4&a5 if call4, a8&a9 if call8, a12&a13 if call12)
-// are correct for whatever reason (not a clean thing to do in general,
-// but if it's possible, unless the ABI explicitly prohibits it,
-// it will eventually be done :) -- whether the the ABI needs to
-// prohibit this is a different question).
-//
-// Timing of Handlers:
-//
-// Here is an overview of the overhead of taking a window exception,
-// ie. the number of additional cycles taken relative to case where
-// an exception is not taken.
-// NOTE: these numbers do not take into account any cache misses,
-// write buffer stalls, or other external stalls, if they occur.
-// The totals consist of 5 cycles to enter the handler (or 6 or 7
-// for optional longer pipelines in Xtensa LX), the number of instructions
-// and interlocks (2nd and 3rd columns below), and 2 cycles jump delay
-// on return (3 cycles for optional longer I-side pipeline in Xtensa LX):
-//
-// Instruction+bubbles Totals (5-stage)
-// XEA1 XEA2 XEA1 XEA2
-// Overflow-4 7 5 14 12
-// Overflow-8 14 10 21 17
-// Overflow-12 18 14 25 21
-// Underflow-4 6 5 13 12
-// Underflow-8 14 10 21 17
-// Underflow-12 18 14 25 21
-//
-// Underflow-8 15 12 25 22 (7-stage; could be made 1 less)
-// Underflow-12 19 16 29 26 (7-stage; could be made 1 less)
-
-#ifndef WINDOW_BASE_VECOFS
-#define WINDOW_BASE_VECOFS XCHAL_WINDOW_OF4_VECOFS
-#endif
-
-
-// 4-Register Window Overflow Vector (Handler)
-//
-// Invoked if a call[i] referenced a register (a4-a15)
-// that contains data from ancestor call[j];
-// call[j] had done a call4 to call[j+1].
-// On entry here:
-// window rotated to call[j] start point;
-// a0-a3 are registers to be saved;
-// a4-a15 must be preserved;
-// a5 is call[j+1]'s stack pointer.
-
- .org XCHAL_WINDOW_OF4_VECOFS - WINDOW_BASE_VECOFS
-_WindowOverflow4:
- isync_erratum453
- s32e a0, a5, -16 // save a0 to call[j+1]'s stack frame
- s32e a1, a5, -12 // save a1 to call[j+1]'s stack frame
- s32e a2, a5, -8 // save a2 to call[j+1]'s stack frame
- s32e a3, a5, -4 // save a3 to call[j+1]'s stack frame
- rfwo // rotates back to call[i] position
-
- .size _WindowOverflow4, . - _WindowOverflow4
-
-
-// ALLOCA exception handler
-//
-// NOTE: The alloca exception handler is squeezed in between the window exception
-// handlers in order to save space, and also to allow short-range jumps to the
-// window underflow handlers (see below for why). Because of the limited space in
-// between the window handlers, this function is split into two to fit.
-//
-// Code written to the windowed ABI must use the MOVSP instruction to modify
-// the stack pointer (except for startup code, which doesn't have a caller).
-// The compiler uses MOVSP to allocate very large or variable size stack frames.
-// MOVSP guarantees that the caller frame's a0-a3 registers, stored below the
-// stack pointer, are moved atomically with respect to interrupts and exceptions
-// to satisfy windowed ABI requirements. When user code executes the MOVSP
-// instruction and the caller frame is on the stack rather than in the register
-// file, the processor takes an ALLOCA exception.
-//
-// The XTOS user exception dispatcher allocates an exception frame on the
-// stack and saves a2-a4 into that frame before calling us. So we need to
-// restore those registers and deallocate the stack frame before jumping
-// to the window underflow handler - which will restore the spilled registers
-// back into the register file.
-// The fact the alloca exception was taken means the registers associated with
-// the base-save area have been spilled and will be restored by the underflow
-// handler, so those 4 registers are available for scratch.
-
- .align 4
-
-_xtos_alloca_handler:
-
- l32i a2, a1, UEXC_a2 // restore a2-a4 and deallocate frame
- l32i a3, a1, UEXC_a3
- l32i a4, a1, UEXC_a4
- addi a1, a1, ESF_TOTALSIZE
- wsr a0, EXCSAVE_1 // save a0
- rsr a0, WINDOWBASE // grab WINDOWBASE before rotw changes it
- rotw -1 // WINDOWBASE goes to a4, new a0-a3 are scratch
- rsr a2, PS
- extui a3, a2, XCHAL_PS_OWB_SHIFT, XCHAL_PS_OWB_BITS
- xor a3, a3, a4 // bits changed from old to current windowbase
- j _xtos_alloca_2 // not enough room here...
-
- .size _xtos_alloca_handler, . - _xtos_alloca_handler
-
-
-// 4-Register Window Underflow Vector (Handler)
-//
-// Invoked by RETW returning from call[i+1] to call[i]
-// where call[i]'s registers must be reloaded (not live in ARs);
-// call[i] had done a call4 to call[i+1].
-// On entry here:
-// window rotated to call[i] start point;
-// a0-a3 are undefined, must be reloaded with call[i].reg[0..3];
-// a4-a15 must be preserved (they are call[i+1].reg[0..11]);
-// a5 is call[i+1]'s stack pointer.
-
- .org XCHAL_WINDOW_UF4_VECOFS - WINDOW_BASE_VECOFS
-_WindowUnderflow4:
- isync_erratum453
- l32e a0, a5, -16 // restore a0 from call[i+1]'s stack frame
- l32e a1, a5, -12 // restore a1 from call[i+1]'s stack frame
- l32e a2, a5, -8 // restore a2 from call[i+1]'s stack frame
- l32e a3, a5, -4 // restore a3 from call[i+1]'s stack frame
- rfwu
-
- .size _WindowUnderflow4, . - _WindowUnderflow4
-
-
-// This is the second part of the alloca handler.
-
- .align 4
-
-_xtos_alloca_2:
-
- rsr a4, EXCSAVE_1 // restore original a0 (now in a4)
- slli a3, a3, XCHAL_PS_OWB_SHIFT
- xor a2, a2, a3 // flip changed bits in old window base
- wsr a2, PS // update PS.OWB to new window base
- rsync
- _bbci.l a4, 31, _WindowUnderflow4
- rotw -1 // original a0 goes to a8
- _bbci.l a8, 30, _WindowUnderflow8
- rotw -1
- j _WindowUnderflow12
-
- .size _xtos_alloca_2, . - _xtos_alloca_2
-
-
-// 8-Register Window Overflow Vector (Handler)
-//
-// Invoked if a call[i] referenced a register (a4-a15)
-// that contains data from ancestor call[j];
-// call[j] had done a call8 to call[j+1].
-// On entry here:
-// window rotated to call[j] start point;
-// a0-a7 are registers to be saved;
-// a8-a15 must be preserved;
-// a9 is call[j+1]'s stack pointer.
-
- .org XCHAL_WINDOW_OF8_VECOFS - WINDOW_BASE_VECOFS
-_WindowOverflow8:
- isync_erratum453
- s32e a0, a9, -16 // save a0 to call[j+1]'s stack frame
- l32e a0, a1, -12 // a0 <- call[j-1]'s sp (used to find end of call[j]'s frame)
- s32e a1, a9, -12 // save a1 to call[j+1]'s stack frame
- s32e a2, a9, -8 // save a2 to call[j+1]'s stack frame
- s32e a3, a9, -4 // save a3 to call[j+1]'s stack frame
- s32e a4, a0, -32 // save a4 to call[j]'s stack frame
- s32e a5, a0, -28 // save a5 to call[j]'s stack frame
- s32e a6, a0, -24 // save a6 to call[j]'s stack frame
- s32e a7, a0, -20 // save a7 to call[j]'s stack frame
- rfwo // rotates back to call[i] position
-
- .size _WindowOverflow8, . - _WindowOverflow8
-
-
-// 8-Register Window Underflow Vector (Handler)
-//
-// Invoked by RETW returning from call[i+1] to call[i]
-// where call[i]'s registers must be reloaded (not live in ARs);
-// call[i] had done a call8 to call[i+1].
-// On entry here:
-// window rotated to call[i] start point;
-// a0-a7 are undefined, must be reloaded with call[i].reg[0..7];
-// a8-a15 must be preserved (they are call[i+1].reg[0..7]);
-// a9 is call[i+1]'s stack pointer.
-
- .org XCHAL_WINDOW_UF8_VECOFS - WINDOW_BASE_VECOFS
-_WindowUnderflow8:
- isync_erratum453
- l32e a0, a9, -16 // restore a0 from call[i+1]'s stack frame
- l32e a1, a9, -12 // restore a1 from call[i+1]'s stack frame
- l32e a2, a9, -8 // restore a2 from call[i+1]'s stack frame
- l32e a7, a1, -12 // a7 <- call[i-1]'s sp (used to find end of call[i]'s frame)
- l32e a3, a9, -4 // restore a3 from call[i+1]'s stack frame
- l32e a4, a7, -32 // restore a4 from call[i]'s stack frame
- l32e a5, a7, -28 // restore a5 from call[i]'s stack frame
- l32e a6, a7, -24 // restore a6 from call[i]'s stack frame
- l32e a7, a7, -20 // restore a7 from call[i]'s stack frame
- rfwu
-
- .size _WindowUnderflow8, . - _WindowUnderflow8
-
-
-// 12-Register Window Overflow Vector (Handler)
-//
-// Invoked if a call[i] referenced a register (a4-a15)
-// that contains data from ancestor call[j];
-// call[j] had done a call12 to call[j+1].
-// On entry here:
-// window rotated to call[j] start point;
-// a0-a11 are registers to be saved;
-// a12-a15 must be preserved;
-// a13 is call[j+1]'s stack pointer.
-
- .org XCHAL_WINDOW_OF12_VECOFS - WINDOW_BASE_VECOFS
-_WindowOverflow12:
- isync_erratum453
- s32e a0, a13, -16 // save a0 to call[j+1]'s stack frame
- l32e a0, a1, -12 // a0 <- call[j-1]'s sp (used to find end of call[j]'s frame)
- s32e a1, a13, -12 // save a1 to call[j+1]'s stack frame
- s32e a2, a13, -8 // save a2 to call[j+1]'s stack frame
- s32e a3, a13, -4 // save a3 to call[j+1]'s stack frame
- s32e a4, a0, -48 // save a4 to end of call[j]'s stack frame
- s32e a5, a0, -44 // save a5 to end of call[j]'s stack frame
- s32e a6, a0, -40 // save a6 to end of call[j]'s stack frame
- s32e a7, a0, -36 // save a7 to end of call[j]'s stack frame
- s32e a8, a0, -32 // save a8 to end of call[j]'s stack frame
- s32e a9, a0, -28 // save a9 to end of call[j]'s stack frame
- s32e a10, a0, -24 // save a10 to end of call[j]'s stack frame
- s32e a11, a0, -20 // save a11 to end of call[j]'s stack frame
- rfwo // rotates back to call[i] position
-
- .size _WindowOverflow12, . - _WindowOverflow12
-
-
-// 12-Register Window Underflow Vector (Handler)
-//
-// Invoked by RETW returning from call[i+1] to call[i]
-// where call[i]'s registers must be reloaded (not live in ARs);
-// call[i] had done a call12 to call[i+1].
-// On entry here:
-// window rotated to call[i] start point;
-// a0-a11 are undefined, must be reloaded with call[i].reg[0..11];
-// a12-a15 must be preserved (they are call[i+1].reg[0..3]);
-// a13 is call[i+1]'s stack pointer.
-
- .org XCHAL_WINDOW_UF12_VECOFS - WINDOW_BASE_VECOFS
-_WindowUnderflow12:
- isync_erratum453
- l32e a0, a13, -16 // restore a0 from call[i+1]'s stack frame
- l32e a1, a13, -12 // restore a1 from call[i+1]'s stack frame
- l32e a2, a13, -8 // restore a2 from call[i+1]'s stack frame
- l32e a11, a1, -12 // a11 <- call[i-1]'s sp (used to find end of call[i]'s frame)
- l32e a3, a13, -4 // restore a3 from call[i+1]'s stack frame
- l32e a4, a11, -48 // restore a4 from end of call[i]'s stack frame
- l32e a5, a11, -44 // restore a5 from end of call[i]'s stack frame
- l32e a6, a11, -40 // restore a6 from end of call[i]'s stack frame
- l32e a7, a11, -36 // restore a7 from end of call[i]'s stack frame
- l32e a8, a11, -32 // restore a8 from end of call[i]'s stack frame
- l32e a9, a11, -28 // restore a9 from end of call[i]'s stack frame
- l32e a10, a11, -24 // restore a10 from end of call[i]'s stack frame
- l32e a11, a11, -20 // restore a11 from end of call[i]'s stack frame
- rfwu
-
- .size _WindowUnderflow12, . - _WindowUnderflow12
-
-
-# ifndef NO_SECTION_DIRECTIVES
- //.end literal_prefix
- .text
-# endif
-
-
-#endif /* XCHAL_HAVE_WINDOWED && !defined(__XTENSA_CALL0_ABI__) */
-#endif /* !XCHAL_HAVE_XEA1 */
-
diff --git a/src/arch/xtensa/up/xtos/window-vectors-xea1.S b/src/arch/xtensa/up/xtos/window-vectors-xea1.S
deleted file mode 100644
index ab7180b..0000000
--- a/src/arch/xtensa/up/xtos/window-vectors-xea1.S
+++ /dev/null
@@ -1,355 +0,0 @@
-// window-vectors-xea1.S - Register Window Overflow/Underflow Handlers for XEA1
-// $Id: //depot/rel/Eaglenest/Xtensa/OS/xtos/window-vectors-xea1.S#1 $
-
-// Copyright (c) 1999-2013 Tensilica Inc.
-//
-// Permission is hereby granted, free of charge, to any person obtaining
-// a copy of this software and associated documentation files (the
-// "Software"), to deal in the Software without restriction, including
-// without limitation the rights to use, copy, modify, merge, publish,
-// distribute, sublicense, and/or sell copies of the Software, and to
-// permit persons to whom the Software is furnished to do so, subject to
-// the following conditions:
-//
-// The above copyright notice and this permission notice shall be included
-// in all copies or substantial portions of the Software.
-//
-// THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
-// EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
-// MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
-// IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY
-// CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
-// TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
-// SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
-
-#include <xtensa/coreasm.h>
-#include <xtensa/xtruntime-frames.h>
-
-#if XCHAL_HAVE_XEA1
-#if XCHAL_HAVE_WINDOWED && !defined(__XTENSA_CALL0_ABI__)
-
-# ifndef NO_SECTION_DIRECTIVES
-// Exports
-.global _WindowOverflow4
-.global _WindowUnderflow4
-.global _WindowOverflow8
-.global _WindowUnderflow8
-.global _WindowOverflow12
-.global _WindowUnderflow12
-.global _xtos_alloca_handler
-
- // Note: the current window exception vectors do not generate any
- // literals. Hence the literal_prefix directive is not necessary.
- // Specifying it "just in case" creates an empty section (named
- // ".WindowVectors.literal") which can in some cases cause linking
- // problems (the linker scripts don't place it anywhere).
- // So leave it commented out:
- //
- //.begin literal_prefix .WindowVectors
-
- .section .WindowVectors.text, "ax"
-# endif
-
-
-//
-// GENERAL NOTES:
-//
-// These window exception handlers need not be modified.
-// They are specific to the windowed call ABI only.
-//
-// Underflow Handlers:
-//
-// The underflow handler for returning from call[i+1] to call[i]
-// must preserve all the registers from call[i+1]'s window.
-// In particular, a0 and a1 must be preserved because the RETW instruction
-// will be reexecuted (and may even underflow again if an intervening
-// exception has flushed call[i]'s registers).
-// Registers a2 and up may contain return values.
-//
-// The caller could also potentially assume that the callee's a0 and a1
-// (its own a4&a5 if call4, a8&a9 if call8, a12&a13 if call12)
-// are correct for whatever reason (not a clean thing to do in general,
-// but if it's possible, unless the ABI explicitly prohibits it,
-// it will eventually be done :) -- whether the the ABI needs to
-// prohibit this is a different question).
-//
-// Timing of Handlers:
-//
-// Here is an overview of the overhead of taking a window exception,
-// ie. the number of additional cycles taken relative to case where
-// an exception is not taken.
-// NOTE: these numbers do not take into account any cache misses,
-// write buffer stalls, or other external stalls, if they occur.
-// The totals consist of 5 cycles to enter the handler (or 6 or 7
-// for optional longer pipelines in Xtensa LX), the number of instructions
-// and interlocks (2nd and 3rd columns below), and 2 cycles jump delay
-// on return (3 cycles for optional longer I-side pipeline in Xtensa LX):
-//
-// Instruction+bubbles Totals (5-stage)
-// XEA1 XEA2 XEA1 XEA2
-// Overflow-4 7 5 14 12
-// Overflow-8 14 10 21 17
-// Overflow-12 18 14 25 21
-// Underflow-4 6 5 13 12
-// Underflow-8 14 10 21 17
-// Underflow-12 18 14 25 21
-//
-// Underflow-8 15 12 25 22 (7-stage; could be made 1 less)
-// Underflow-12 19 16 29 26 (7-stage; could be made 1 less)
-
-#ifndef WINDOW_BASE_VECOFS
-#define WINDOW_BASE_VECOFS XCHAL_WINDOW_OF4_VECOFS
-#endif
-
-
-// 4-Register Window Overflow Vector (Handler)
-//
-// Invoked if a call[i] referenced a register (a4-a15)
-// that contains data from ancestor call[j];
-// call[j] had done a call4 to call[j+1].
-// On entry here:
-// window rotated to call[j] start point;
-// a0-a3 are registers to be saved;
-// a4-a15 must be preserved;
-// a5 is call[j+1]'s stack pointer.
-
- .org XCHAL_WINDOW_OF4_VECOFS - WINDOW_BASE_VECOFS
-_WindowOverflow4:
- addi a5, a5, -16 // to make store offsets positive
- s32i a0, a5, 0 // save a0 to call[j+1]'s stack frame
- s32i a1, a5, 4 // save a1 to call[j+1]'s stack frame
- s32i a2, a5, 8 // save a2 to call[j+1]'s stack frame
- s32i a3, a5, 12 // save a3 to call[j+1]'s stack frame
- addi a5, a5, 16 // restore a5
- rfwo // rotates back to call[i] position
-
- .size _WindowOverflow4, . - _WindowOverflow4
-
-
-// ALLOCA exception handler
-//
-// NOTE: The alloca exception handler is squeezed in between the window exception
-// handlers in order to save space, and also to allow short-range jumps to the
-// window underflow handlers (see below for why). Because of the limited space in
-// between the window handlers, this function is split into two to fit.
-//
-// Code written to the windowed ABI must use the MOVSP instruction to modify
-// the stack pointer (except for startup code, which doesn't have a caller).
-// The compiler uses MOVSP to allocate very large or variable size stack frames.
-// MOVSP guarantees that the caller frame's a0-a3 registers, stored below the
-// stack pointer, are moved atomically with respect to interrupts and exceptions
-// to satisfy windowed ABI requirements. When user code executes the MOVSP
-// instruction and the caller frame is on the stack rather than in the register
-// file, the processor takes an ALLOCA exception.
-//
-// The XTOS user exception dispatcher allocates an exception frame on the
-// stack and saves a2-a4 into that frame before calling us. So we need to
-// restore those registers and deallocate the stack frame before jumping
-// to the window underflow handler - which will restore the spilled registers
-// back into the register file.
-// The fact the alloca exception was taken means the registers associated with
-// the base-save area have been spilled and will be restored by the underflow
-// handler, so those 4 registers are available for scratch.
-
- .align 4
-
-_xtos_alloca_handler:
-
- l32i a2, a1, UEXC_a2 // restore a2-a4 and deallocate frame
- l32i a3, a1, UEXC_a3
- l32i a4, a1, UEXC_a4
- addi a1, a1, ESF_TOTALSIZE
- wsr a0, EXCSAVE_1 // save a0
- rsr a0, WINDOWBASE // grab WINDOWBASE before rotw changes it
- rotw -1 // WINDOWBASE goes to a4, new a0-a3 are scratch
- rsr a2, PS
- extui a3, a2, XCHAL_PS_OWB_SHIFT, XCHAL_PS_OWB_BITS
- xor a3, a3, a4 // bits changed from old to current windowbase
- j _xtos_alloca_2 // not enough room here...
-
- .size _xtos_alloca_handler, . - _xtos_alloca_handler
-
-
-// 4-Register Window Underflow Vector (Handler)
-//
-// Invoked by RETW returning from call[i+1] to call[i]
-// where call[i]'s registers must be reloaded (not live in ARs);
-// call[i] had done a call4 to call[i+1].
-// On entry here:
-// window rotated to call[i] start point;
-// a0-a3 are undefined, must be reloaded with call[i].reg[0..3];
-// a4-a15 must be preserved (they are call[i+1].reg[0..11]);
-// a5 is call[i+1]'s stack pointer.
-
- .org XCHAL_WINDOW_UF4_VECOFS - WINDOW_BASE_VECOFS
-_WindowUnderflow4:
- addi a3, a5, -16 // to make load offsets positive
- l32i a0, a3, 0 // restore a0 from call[i+1]'s stack frame
- l32i a1, a3, 4 // restore a1 from call[i+1]'s stack frame
- l32i a2, a3, 8 // restore a2 from call[i+1]'s stack frame
- l32i a3, a3, 12 // restore a3 from call[i+1]'s stack frame
- rfwu
-
- .size _WindowUnderflow4, . - _WindowUnderflow4
-
-
-// This is the second part of the alloca handler.
-
- .align 4
-
-_xtos_alloca_2:
-
- rsr a4, EXCSAVE_1 // restore original a0 (now in a4)
- slli a3, a3, XCHAL_PS_OWB_SHIFT
- xor a2, a2, a3 // flip changed bits in old window base
- wsr a2, PS // update PS.OWB to new window base
- rsync
- _bbci.l a4, 31, _WindowUnderflow4
- rotw -1 // original a0 goes to a8
- _bbci.l a8, 30, _WindowUnderflow8
- rotw -1
- j _WindowUnderflow12
-
- .size _xtos_alloca_2, . - _xtos_alloca_2
-
-// 8-Register Window Overflow Vector (Handler)
-//
-// Invoked if a call[i] referenced a register (a4-a15)
-// that contains data from ancestor call[j];
-// call[j] had done a call8 to call[j+1].
-// On entry here:
-// window rotated to call[j] start point;
-// a0-a7 are registers to be saved;
-// a8-a15 must be preserved;
-// a9 is call[j+1]'s stack pointer.
-
- .org XCHAL_WINDOW_OF8_VECOFS - WINDOW_BASE_VECOFS
-_WindowOverflow8:
- addi a9, a9, -16 // to make store offsets positive
- s32i a0, a9, 0 // save a0 to call[j+1]'s stack frame
- addi a0, a1, -16 // a0 <- call[j-1]'s sp
- s32i a1, a9, 4 // save a1 to call[j+1]'s stack frame
- l32i a0, a0, 4 // (used to find end of call[j]'s frame)
- s32i a2, a9, 8 // save a2 to call[j+1]'s stack frame
- s32i a3, a9, 12 // save a3 to call[j+1]'s stack frame
- addi a9, a9, 16 // restore a9
- addi a0, a0, -32 // to make load offsets positive
- s32i a4, a0, 0 // save a4 to call[j]'s stack frame
- s32i a5, a0, 4 // save a5 to call[j]'s stack frame
- s32i a6, a0, 8 // save a6 to call[j]'s stack frame
- s32i a7, a0, 12 // save a7 to call[j]'s stack frame
- rfwo // rotates back to call[i] position
-
- .size _WindowOverflow8, . - _WindowOverflow8
-
-
-// 8-Register Window Underflow Vector (Handler)
-//
-// Invoked by RETW returning from call[i+1] to call[i]
-// where call[i]'s registers must be reloaded (not live in ARs);
-// call[i] had done a call8 to call[i+1].
-// On entry here:
-// window rotated to call[i] start point;
-// a0-a7 are undefined, must be reloaded with call[i].reg[0..7];
-// a8-a15 must be preserved (they are call[i+1].reg[0..7]);
-// a9 is call[i+1]'s stack pointer.
-
- .org XCHAL_WINDOW_UF8_VECOFS - WINDOW_BASE_VECOFS
-_WindowUnderflow8:
- addi a9, a9, -16 // to make load offsets positive
- l32i a0, a9, 0 // restore a0 from call[i+1]'s stack frame
- l32i a1, a9, 4 // restore a1 from call[i+1]'s stack frame
- l32i a2, a9, 8 // restore a2 from call[i+1]'s stack frame
- addi a7, a1, -16 // a7 <- call[i-1]'s sp
- l32i a7, a7, 4 // (used to find end of call[i]'s frame)
- l32i a3, a9, 12 // restore a3 from call[i+1]'s stack frame
- addi a9, a9, 16 // restore a9
- addi a7, a7, -32 // to make load offsets positive
- l32i a4, a7, 0 // restore a4 from call[i]'s stack frame
- l32i a5, a7, 4 // restore a5 from call[i]'s stack frame
- l32i a6, a7, 8 // restore a6 from call[i]'s stack frame
- l32i a7, a7, 12 // restore a7 from call[i]'s stack frame
- rfwu
-
- .size _WindowUnderflow8, . - _WindowUnderflow8
-
-
-// 12-Register Window Overflow Vector (Handler)
-//
-// Invoked if a call[i] referenced a register (a4-a15)
-// that contains data from ancestor call[j];
-// call[j] had done a call12 to call[j+1].
-// On entry here:
-// window rotated to call[j] start point;
-// a0-a11 are registers to be saved;
-// a12-a15 must be preserved;
-// a13 is call[j+1]'s stack pointer.
-
- .org XCHAL_WINDOW_OF12_VECOFS - WINDOW_BASE_VECOFS
-_WindowOverflow12:
- addi a13, a13, -16 // to make store offsets positive
- s32i a0, a13, 0 // save a0 to call[j+1]'s stack frame
- addi a0, a1, -16 // a0 <- call[j-1]'s sp
- s32i a1, a13, 4 // save a1 to call[j+1]'s stack frame
- l32i a0, a0, 4 // (used to find end of call[j]'s frame)
- s32i a2, a13, 8 // save a2 to call[j+1]'s stack frame
- s32i a3, a13, 12 // save a3 to call[j+1]'s stack frame
- addi a13, a13, 16 // restore a13
- addi a0, a0, -48 // to make load offsets positive
- s32i a4, a0, 0 // save a4 to end of call[j]'s stack frame
- s32i a5, a0, 4 // save a5 to end of call[j]'s stack frame
- s32i a6, a0, 8 // save a6 to end of call[j]'s stack frame
- s32i a7, a0, 12 // save a7 to end of call[j]'s stack frame
- s32i a8, a0, 16 // save a8 to end of call[j]'s stack frame
- s32i a9, a0, 20 // save a9 to end of call[j]'s stack frame
- s32i a10, a0, 24 // save a10 to end of call[j]'s stack frame
- s32i a11, a0, 28 // save a11 to end of call[j]'s stack frame
- rfwo // rotates back to call[i] position
-
- .size _WindowOverflow12, . - _WindowOverflow12
-
-
-// 12-Register Window Underflow Vector (Handler)
-//
-// Invoked by RETW returning from call[i+1] to call[i]
-// where call[i]'s registers must be reloaded (not live in ARs);
-// call[i] had done a call12 to call[i+1].
-// On entry here:
-// window rotated to call[i] start point;
-// a0-a11 are undefined, must be reloaded with call[i].reg[0..11];
-// a12-a15 must be preserved (they are call[i+1].reg[0..3]);
-// a13 is call[i+1]'s stack pointer.
-
- .org XCHAL_WINDOW_UF12_VECOFS - WINDOW_BASE_VECOFS
-_WindowUnderflow12:
- addi a13, a13, -16 // to make load offsets positive
- l32i a0, a13, 0 // restore a0 from call[i+1]'s stack frame
- l32i a1, a13, 4 // restore a1 from call[i+1]'s stack frame
- l32i a2, a13, 8 // restore a2 from call[i+1]'s stack frame
- addi a11, a1, -16 // a11 <- call[i-1]'s sp
- l32i a11, a11, 4 // (used to find end of call[i]'s frame)
- l32i a3, a13, 12 // restore a3 from call[i+1]'s stack frame
- addi a13, a13, 16 // restore a13
- addi a11, a11, -48 // to make load offsets positive
- l32i a4, a11, 0 // restore a4 from end of call[i]'s stack frame
- l32i a5, a11, 4 // restore a5 from end of call[i]'s stack frame
- l32i a6, a11, 8 // restore a6 from end of call[i]'s stack frame
- l32i a7, a11, 12 // restore a7 from end of call[i]'s stack frame
- l32i a8, a11, 16 // restore a8 from end of call[i]'s stack frame
- l32i a9, a11, 20 // restore a9 from end of call[i]'s stack frame
- l32i a10, a11, 24 // restore a10 from end of call[i]'s stack frame
- l32i a11, a11, 28 // restore a11 from end of call[i]'s stack frame
- rfwu
-
- .size _WindowUnderflow12, . - _WindowUnderflow12
-
-
-# ifndef NO_SECTION_DIRECTIVES
- //.end literal_prefix
- .text
-# endif
-
-
-#endif /* XCHAL_HAVE_WINDOWED && !defined(__XTENSA_CALL0_ABI__) */
-#endif /* XCHAL_HAVE_XEA1 */
-
diff --git a/src/arch/xtensa/up/xtos/window-vectors.S b/src/arch/xtensa/up/xtos/window-vectors.S
deleted file mode 100644
index 1f0ce0e..0000000
--- a/src/arch/xtensa/up/xtos/window-vectors.S
+++ /dev/null
@@ -1,38 +0,0 @@
-// window-vectors.S - Register Window Overflow/Underflow Handlers
-// $Id: //depot/rel/Eaglenest/Xtensa/OS/xtos/window-vectors.S#1 $
-
-// Copyright (c) 1999-2013 Tensilica Inc.
-//
-// Permission is hereby granted, free of charge, to any person obtaining
-// a copy of this software and associated documentation files (the
-// "Software"), to deal in the Software without restriction, including
-// without limitation the rights to use, copy, modify, merge, publish,
-// distribute, sublicense, and/or sell copies of the Software, and to
-// permit persons to whom the Software is furnished to do so, subject to
-// the following conditions:
-//
-// The above copyright notice and this permission notice shall be included
-// in all copies or substantial portions of the Software.
-//
-// THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
-// EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
-// MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
-// IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY
-// CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
-// TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
-// SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
-
-#include <xtensa/coreasm.h>
-
-#if XCHAL_HAVE_WINDOWED && !defined(__XTENSA_CALL0_ABI__)
-
-// Simply include the correct version of the actual handlers
-
-#if XCHAL_HAVE_XEA1
-#include "window-vectors-xea1.S"
-#else
-#include "window-vectors-new.S"
-#endif
-
-#endif /* XCHAL_HAVE_WINDOWED && !defined(__XTENSA_CALL0_ABI__) */
-
diff --git a/src/arch/xtensa/up/xtos/xtos-internal.h b/src/arch/xtensa/up/xtos/xtos-internal.h
deleted file mode 100644
index c6f1185..0000000
--- a/src/arch/xtensa/up/xtos/xtos-internal.h
+++ /dev/null
@@ -1,401 +0,0 @@
-/*
- * xtos-internal.h -- internal definitions for single-threaded run-time
- *
- * Copyright (c) 2003-2010 Tensilica Inc.
- *
- * Permission is hereby granted, free of charge, to any person obtaining
- * a copy of this software and associated documentation files (the
- * "Software"), to deal in the Software without restriction, including
- * without limitation the rights to use, copy, modify, merge, publish,
- * distribute, sublicense, and/or sell copies of the Software, and to
- * permit persons to whom the Software is furnished to do so, subject to
- * the following conditions:
- *
- * The above copyright notice and this permission notice shall be included
- * in all copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
- * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
- * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
- * IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY
- * CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
- * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
- * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
- */
-
-#ifndef XTOS_INTERNAL_H
-#define XTOS_INTERNAL_H
-
-#include <xtensa/config/core.h>
-#include <xtensa/xtruntime.h>
-#include <xtensa/xtruntime-frames.h>
-#include <xtensa/xtensa-versions.h>
-#ifndef XTOS_PARAMS_H /* this to allow indirect inclusion of this header from the outside */
-#include "xtos-params.h"
-#endif
-
-/* Relative ordering of subpriorities within an interrupt level (or vector): */
-#define XTOS_SPO_ZERO_LO 0 /* lower (eg. zero) numbered interrupts are lower priority than higher numbered interrupts */
-#define XTOS_SPO_ZERO_HI 1 /* lower (eg. zero) numbered interrupts are higher priority than higher numbered interrupts */
-
-
-/* Sanity check some parameters from xtos-params.h: */
-#if XTOS_LOCKLEVEL < XCHAL_EXCM_LEVEL || XTOS_LOCKLEVEL > 15
-# error Invalid XTOS_LOCKLEVEL value, must be >= EXCM_LEVEL and <= 15, please fix xtos-params.h
-#endif
-
-/* Mask of interrupts locked out at XTOS_LOCKLEVEL: */
-#define XTOS_LOCKOUT_MASK XCHAL_INTLEVEL_ANDBELOW_MASK(XTOS_LOCKLEVEL)
-/* Mask of interrupts that can still be enabled at XTOS_LOCKLEVEL: */
-#define XTOS_UNLOCKABLE_MASK (0xFFFFFFFF-XTOS_LOCKOUT_MASK)
-
-/* Don't set this: */
-#define XTOS_HIGHINT_TRAMP 0 /* mapping high-pri ints to low-pri not auto-supported */
-#define XTOS_VIRTUAL_INTERRUPT XTOS_HIGHINT_TRAMP /* partially-virtualized INTERRUPT register not currently supported */
-#if XTOS_HIGHINT_TRAMP
-# error Automatically-generated high-level interrupt trampolines are not presently supported.
-#endif
-
-/*
- * If single interrupt at level-one, sub-prioritization is irrelevant:
- */
-#if defined(XCHAL_INTLEVEL1_NUM)
-# undef XTOS_SUBPRI
-# define XTOS_SUBPRI 0 /* override - only one interrupt */
-#endif
-
-/*
- * In XEA1, the INTENABLE special register must be virtualized to provide
- * standard XTOS functionality.
- * In XEA2, this is only needed for software interrupt prioritization.
- */
-#if XTOS_SUBPRI || XCHAL_HAVE_XEA1
-#define XTOS_VIRTUAL_INTENABLE 1
-#else
-#define XTOS_VIRTUAL_INTENABLE 0
-#endif
-
-/*
- * If single interrupt per priority, then fairness is irrelevant:
- */
-#if (XTOS_SUBPRI && !XTOS_SUBPRI_GROUPS) || defined(XCHAL_INTLEVEL1_NUM)
-# undef XTOS_INT_FAIRNESS
-# define XTOS_INT_FAIRNESS 0
-#endif
-
-/* Identify special case interrupt handling code in int-lowpri-dispatcher.S: */
-#define XTOS_INT_SPECIALCASE (XTOS_SUBPRI_ORDER == XTOS_SPO_ZERO_HI && XTOS_INT_FAIRNESS == 0 && XTOS_SUBPRI_GROUPS == 0)
-
-/*
- * Determine whether to extend the interrupt entry array:
- */
-#define XIE_EXTEND (XTOS_VIRTUAL_INTENABLE && !XTOS_INT_SPECIALCASE)
-
-/* If we have the NSAU instruction, ordering of interrupts is reversed in _xtos_interrupt_table[]: */
-#if XCHAL_HAVE_NSA
-# define MAPINT(n) ((XCHAL_NUM_INTERRUPTS-1)-(n))
-# ifdef _ASMLANGUAGE
- .macro mapint an
- neg \an, \an
- addi \an, \an, XCHAL_NUM_INTERRUPTS-1
- .endm
-# endif
-#else /* no NSA */
-# define MAPINT(n) (n)
-# ifdef _ASMLANGUAGE
- .macro mapint an
- .endm
-# endif
-#endif
-
-
-#if defined(_ASMLANGUAGE) || defined(__ASSEMBLER__)
-
-/*********** Useful macros ***********/
-
-/*
- * A useful looping macro:
- * 'iterate' invokes 'what' (an instruction, pseudo-op or other macro)
- * multiple times, passing it a numbered parameter from 'from' to 'to'
- * inclusively. Does not invoke 'what' at all if from > to.
- * Maximum difference between 'from' and 'to' is 99 minus nesting depth
- * (GNU 'as' doesn't allow nesting deeper than 100).
- */
- .macro iterate from, to, what
- .ifeq ((\to-\from) & ~0xFFF)
- \what \from
- iterate "(\from+1)", \to, \what
- .endif
- .endm // iterate
-
-
-
- // rsilft
- //
- // Execute RSIL \ar, \tolevel if \tolevel is different than \fromlevel.
- // This way the RSIL is avoided if we know at assembly time that
- // it will not change the level. Typically, this means the \ar register
- // is ignored, ie. RSIL is used only to change PS.INTLEVEL.
- //
- .macro rsilft ar, fromlevel, tolevel
-#if XCHAL_HAVE_INTERRUPTS
- .if \fromlevel - \tolevel
- rsil \ar, \tolevel
- .endif
-#endif
- .endm
-
-
- // Save LOOP and MAC16 registers, if configured, to the exception stack
- // frame pointed to by address register \esf, using \aa and \ab as temporaries.
- //
- // This macro essentially saves optional registers that the compiler uses by
- // default when present.
- // Note that the acclo/acchi subset of MAC16 may be used even if others
- // multipliers are present (e.g. mul16, mul32).
- //
- // Only two temp registers required for this code to be optimal (no interlocks) in both
- // T10xx (Athens) and Xtensa LX microarchitectures (both 5 and 7 stage pipes):
- //
- .macro save_loops_mac16 esf, aa, ab
-#if XCHAL_HAVE_LOOPS
- rsr \aa, LCOUNT
- rsr \ab, LBEG
- s32i \aa, \esf, UEXC_lcount
- rsr \aa, LEND
- s32i \ab, \esf, UEXC_lbeg
- s32i \aa, \esf, UEXC_lend
-#endif
-#if XCHAL_HAVE_MAC16
- rsr \aa, ACCLO
- rsr \ab, ACCHI
- s32i \aa, \esf, UEXC_acclo
- s32i \ab, \esf, UEXC_acchi
-# if XTOS_SAVE_ALL_MAC16
- rsr \aa, M0
- rsr \ab, M1
- s32i \aa, \esf, UEXC_mr + 0
- s32i \ab, \esf, UEXC_mr + 4
- rsr \aa, M2
- rsr \ab, M3
- s32i \aa, \esf, UEXC_mr + 8
- s32i \ab, \esf, UEXC_mr + 12
-# endif
-#endif
- .endm
-
- // Restore LOOP and MAC16 registers, if configured, from the exception stack
- // frame pointed to by address register \esf, using \aa, \ab and \ac as temporaries.
- //
- // Three temp registers are required for this code to be optimal (no interlocks) in
- // Xtensa LX microarchitectures with 7-stage pipe; otherwise only two
- // registers would be needed.
- //
- .macro restore_loops_mac16 esf, aa, ab, ac
-#if XCHAL_HAVE_LOOPS
- l32i \aa, \esf, UEXC_lcount
- l32i \ab, \esf, UEXC_lbeg
- l32i \ac, \esf, UEXC_lend
- wsr \aa, LCOUNT
- wsr \ab, LBEG
- wsr \ac, LEND
-#endif
-#if XCHAL_HAVE_MAC16
- l32i \aa, \esf, UEXC_acclo
- l32i \ab, \esf, UEXC_acchi
-# if XTOS_SAVE_ALL_MAC16
- l32i \ac, \esf, UEXC_mr + 0
- wsr \aa, ACCLO
- wsr \ab, ACCHI
- wsr \ac, M0
- l32i \aa, \esf, UEXC_mr + 4
- l32i \ab, \esf, UEXC_mr + 8
- l32i \ac, \esf, UEXC_mr + 12
- wsr \aa, M1
- wsr \ab, M2
- wsr \ac, M3
-# else
- wsr \aa, ACCLO
- wsr \ab, ACCHI
-# endif
-#endif
- .endm
-
-
-/* Offsets from _xtos_intstruct structure: */
- .struct 0
-#if XTOS_VIRTUAL_INTENABLE
-XTOS_ENABLED_OFS: .space 4 /* _xtos_enabled variable */
-XTOS_VPRI_ENABLED_OFS: .space 4 /* _xtos_vpri_enabled variable */
-#endif
-#if XTOS_VIRTUAL_INTERRUPT
-XTOS_PENDING_OFS: .space 4 /* _xtos_pending variable */
-#endif
- .text
-
-
-#if XTOS_VIRTUAL_INTENABLE
- // Update INTENABLE register, computing it as follows:
- // INTENABLE = _xtos_enabled & _xtos_vpri_enabled
- // [ & ~_xtos_pending ]
- //
- // Entry:
- // register ax = &_xtos_intstruct
- // register ay, az undefined (temporaries)
- // PS.INTLEVEL set to XTOS_LOCKLEVEL or higher (eg. via xtos_lock)
- // window overflows prevented (PS.WOE=0, PS.EXCM=1, or overflows
- // already done for registers ax, ay, az)
- //
- // Exit:
- // registers ax, ay, az clobbered
- // PS unchanged
- // caller needs to SYNC (?) for INTENABLE changes to take effect
- //
- // Note: in other software prioritization schemes/implementations,
- // the term <_xtos_vpri_enabled> in the above expression is often
- // replaced with another expression that computes the set of
- // interrupts allowed to be enabled at the current software virtualized
- // interrupt priority.
- //
- // For example, a simple alternative implementation of software
- // prioritization for XTOS might have been the following:
- // INTENABLE = _xtos_enabled & (vpri_enabled | UNLOCKABLE_MASK)
- // which removes the need for the interrupt dispatcher to 'or' the
- // UNLOCKABLE_MASK bits into _xtos_vpri_enabled, and lets other code
- // disable all lockout level interrupts by just clearing _xtos_vpri_enabled
- // rather than setting it to UNLOCKABLE_MASK.
- // Other implementations sometimes use a table, eg:
- // INTENABLE = _xtos_enabled & enable_table[current_vpri]
- // The HAL (used by some 3rd party OSes) uses essentially a table-driven
- // version, with other tables enabling run-time changing of priorities.
- //
- .macro xtos_update_intenable ax, ay, az
- //movi \ax, _xtos_intstruct
- l32i \ay, \ax, XTOS_VPRI_ENABLED_OFS // ay = _xtos_vpri_enabled
- l32i \az, \ax, XTOS_ENABLED_OFS // az = _xtos_enabled
- //interlock
- and \az, \az, \ay // az = _xtos_enabled & _xtos_vpri_enabled
-# if XTOS_VIRTUAL_INTERRUPT
- l32i \ay, \ax, XTOS_PENDING_OFS // ay = _xtos_pending
- movi \ax, -1
- xor \ay, \ay, \ax // ay = ~_xtos_pending
- and \az, \az, \ay // az &= ~_xtos_pending
-# endif
- wsr \az, INTENABLE
- .endm
-#endif /* VIRTUAL_INTENABLE */
-
- .macro xtos_lock ax
- rsil \ax, XTOS_LOCKLEVEL // lockout
- .endm
-
- .macro xtos_unlock ax
- wsr \ax, PS // unlock
- rsync
- .endm
-
-/* Offsets to XtosIntHandlerEntry structure fields (see below): */
-# define XIE_HANDLER 0
-# define XIE_ARG 4
-# define XIE_SIZE 8
-# if XIE_EXTEND
-# define XIE_VPRIMASK (XIE_SIZE*XCHAL_NUM_INTERRUPTS+0) /* if VIRTUAL_INTENABLE [SUBPRI||XEA1] && !SPECIALCASE */
-# define XIE_LEVELMASK (XIE_SIZE*XCHAL_NUM_INTERRUPTS+4) /* [fairness preloop] if FAIRNESS && SUBPRI [&& SUBPRI_GROUPS] */
-# endif
-
-/* To simplify code: */
-# if XCHAL_HAVE_NSA
-# define IFNSA(a,b) a
-# else
-# define IFNSA(a,b) b
-# endif
-
-#else /* !_ASMLANGUAGE && !__ASSEMBLER__ */
-
-/*
- * Interrupt handler table entry.
- * Unregistered entries have 'handler' point to _xtos_unhandled_interrupt().
- */
-typedef struct XtosIntHandlerEntry {
- _xtos_handler handler;
- void * arg;
-} XtosIntHandlerEntry;
-# if XIE_EXTEND
-typedef struct XtosIntMaskEntry {
- unsigned vpri_mask; /* mask of interrupts enabled when this interrupt is taken */
- unsigned level_mask; /* mask of interrupts at this interrupt's level */
-} XtosIntMaskEntry;
-# endif
-
-#endif /* !_ASMLANGUAGE && !__ASSEMBLER__ */
-
-/*
- * Notes...
- *
- * XEA1 and interrupt-SUBPRIoritization both imply virtualization of INTENABLE.
- * Synchronous trampoloines imply partial virtualization of the INTERRUPT
- * register, which in turn also implies virtualization of INTENABLE register.
- * High-level interrupts manipulating the set of enabled interrupts implies
- * at least a high XTOS_LOCK_LEVEL, although not necessarily INTENABLE virtualization.
- *
- * With INTENABLE register virtualization, at all times the INTENABLE
- * register reflects the expression:
- * (set of interrupts enabled) & (set of interrupts enabled by current
- * virtual priority)
- *
- * Unrelated (DBREAK semantics):
- *
- * A[31-6] = DBA[3-6]
- * ---------------------
- * A[5-0] & DBC[5-C] & szmask
- *
- * = DBA[5-0] & szmask
- * ^___ ???
- */
-
-
-/* Report whether the XSR instruction is available (conservative): */
-#define HAVE_XSR (XCHAL_HAVE_XEA2 || !XCHAL_HAVE_EXCEPTIONS)
-/*
- * This is more accurate, but not a reliable test in software releases prior to 6.0
- * (where the targeted hardware parameter was not explicit in the XPG):
- *
- *#define HAVE_XSR (XCHAL_HW_MIN_VERSION >= XTENSA_HWVERSION_T1040_0)
- */
-
-
-
-/* Macros for supporting hi-level and medium-level interrupt handling. */
-
-#if XCHAL_NUM_INTLEVELS > 6
-#error Template files (*-template.S) limit support to interrupt levels <= 6
-#endif
-
-#if defined(__XTENSA_WINDOWED_ABI__) && XCHAL_HAVE_CALL4AND12 == 0
-#error CALL8-only is not supported!
-#endif
-
-#define INTERRUPT_IS_HI(level) \
- ( XCHAL_HAVE_INTERRUPTS && \
- (XCHAL_EXCM_LEVEL < level) && \
- (XCHAL_NUM_INTLEVELS >= level) && \
- (XCHAL_HAVE_DEBUG ? XCHAL_DEBUGLEVEL != level : 1))
-
-#define INTERRUPT_IS_MED(level) \
- (XCHAL_HAVE_INTERRUPTS && (XCHAL_EXCM_LEVEL >= level))
-
-
-#define _JOIN(x,y) x ## y
-#define JOIN(x,y) _JOIN(x,y)
-
-#define _JOIN3(a,b,c) a ## b ## c
-#define JOIN3(a,b,c) _JOIN3(a,b,c)
-
-#define LABEL(x,y) JOIN3(x,_INTERRUPT_LEVEL,y)
-#define EXCSAVE_LEVEL JOIN(EXCSAVE_,_INTERRUPT_LEVEL)
-#define INTLEVEL_VSIZE JOIN3(XSHAL_INTLEVEL,_INTERRUPT_LEVEL,_VECTOR_SIZE)
-
-
-
-#endif /* XTOS_INTERNAL_H */
-
diff --git a/src/arch/xtensa/up/xtos/xtos-params.h b/src/arch/xtensa/up/xtos/xtos-params.h
deleted file mode 100644
index 334aba7..0000000
--- a/src/arch/xtensa/up/xtos/xtos-params.h
+++ /dev/null
@@ -1,123 +0,0 @@
-/*
- * xtos-params.h -- user-settable parameters for XTOS single-threaded run-time
- *
- * Copyright (c) 2002, 2004, 2006-2007 Tensilica Inc.
- *
- * Permission is hereby granted, free of charge, to any person obtaining
- * a copy of this software and associated documentation files (the
- * "Software"), to deal in the Software without restriction, including
- * without limitation the rights to use, copy, modify, merge, publish,
- * distribute, sublicense, and/or sell copies of the Software, and to
- * permit persons to whom the Software is furnished to do so, subject to
- * the following conditions:
- *
- * The above copyright notice and this permission notice shall be included
- * in all copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
- * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
- * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
- * IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY
- * CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
- * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
- * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
- */
-
-#ifndef XTOS_PARAMS_H
-#define XTOS_PARAMS_H
-
-/*
- * IMPORTANT NOTE.
- * This file contains XTOS parameters that may be modified
- * according to needs. HOWEVER, any modifications are NOT
- * supported. Handling of parameters other than the defaults
- * provided in the original version of this file are for
- * illustrative and educational purposes only. If you do
- * change the parameters here-in (which requires rebuilding
- * XTOS), please verify the resulting code extensively
- * before even considering its use in production code.
- *
- * To rebuild XTOS, see instructions in the Xtensa System Software
- * Reference Manual. The following sequence is no longer supported.
- *
- * cd <config_dir>/xtensa-elf/src/handlers
- * xt-make clean
- * xt-make
- * xt-make install
- *
- * (Note: the last step installs the modified XTOS in *ALL*
- * LSPs that normally include XTOS. You may prefer copying
- * the generated files to your own custom LSP instead. Or
- * better yet, also make a copy of all source files and maintain
- * them somewhere completely separate -- which may require
- * minor adjustments to the makefile.)
- *
- * PERFORMANCE TUNING:
- * To slightly improve performance of interrupt dispatching,
- * you can do some combination of the following:
- * - change XTOS_SUBPRI to zero
- * - change XTOS_SUBPRI_GROUPS to zero
- * - change XTOS_SUBPRI_ORDER to XTOS_SPO_ZERO_HI
- * - change XTOS_DEBUG_PC to zero
- * - change XTOS_INT_FAIRNESS to zero
- * - change XTOS_CNEST to zero
- * There are non-trivial trade-offs in making such changes however,
- * such as loss of support (see important note above), loss of
- * interrupt scheduling fairness, loss of ability to traceback
- * interrupt handlers across interrupted code when debugging them,
- * loss of supported for nested C functions, etc.
- */
-
-
-/*
- * Lower LOCKLEVEL to XCHAL_EXCM_LEVEL for improved interrupt latency
- * if you don't register C handlers for high-priority interrupts and your
- * high-priority handlers don't touch INTENABLE nor virtual priorities.
- *
- * XTOS_LOCKLEVEL is less meaningful but still relevant if XEA2 and SUBPRI is zero,
- * ie. if INTENABLE doesn't get virtualized (XTOS_VIRTUAL_INTENABLE not set);
- * in this case, it is the interrupt level at which INTENABLE accesses are guarded,
- * so that interrupt handlers up to this level can safely manipulate INTENABLE.
- */
-#define XTOS_LOCKLEVEL XCHAL_NUM_INTLEVELS /* intlevel of INTENABLE register virtualization
- (minimum is EXCM_LEVEL) */
-
-/*
- * NOTE: the following four parameters (SUBPRI, SUBPRI_GROUPS, SUBPRI_ORDER, INT_FAIRNESS)
- * are irrelevant and ignored for interrupt vectors to which only one interrupt is mapped.
- */
-
-#define XTOS_SUBPRI 1 /* set to 0 if you don't need sub-prioritization
- within level-one interrupts via software;
- for XEA2 configs, this might improve performance of
- certain sections of code, because INTENABLE register
- virtualization becomes unnecessary in this case */
-
-/* Ignored unless SUBPRI set: */
-#define XTOS_SUBPRI_GROUPS 1 /* 1 = support selective grouping of interrupts at the same priority */
-
-#define XTOS_SUBPRI_ORDER XTOS_SPO_ZERO_LO /* one of XTOS_SPO_ZERO_LO, XTOS_SPO_ZERO_HI */
-
-/* Ignored if SUBPRI set but SUBPRI_GROUPS is not (single interrupt per subpri),
- * or if single interrupt configured at level/vector: */
-#define XTOS_INT_FAIRNESS 1 /* 1 = enable round-robin/fifo scheduling of interrupt
- handlers of a given level or sub-priority */
-
-
-#define XTOS_DEBUG_PC 1 /* 1 = enable nice stack traceback showing interrupted code
- when debugging interrupt or exception handler;
- not implemented for high-priority handlers, or
- for call0 ABI */
-
-#define XTOS_CNEST 1 /* 1 = enable support for nested C functions
- (save/restore nested C function call-chain pointer) */
-
-/* Current compilers only use ACC (not MRn) when MAC16 is enabled, so you can leave this 0 for performance: */
-#define XTOS_SAVE_ALL_MAC16 0 /* set to save/restore MAC16 MRn registers */
-
-/* Setting this might be useful to clear X's in hardware simulation a bit earlier, but
- * should not be needed in production code: */
-#define XTOS_RESET_UNNEEDED 0 /* set to reset more registers than are really needed */
-
-#endif /* XTOS_PARAMS_H */
-
diff --git a/src/audio/Makefile.am b/src/audio/Makefile.am
deleted file mode 100644
index 85bc270..0000000
--- a/src/audio/Makefile.am
+++ /dev/null
@@ -1,918 +0,0 @@
-includedir = $(prefix)/include/sof/audio
-
-include_HEADERS = \
- eq_iir.h \
- iir.h \
- fir.h \
- fir_config.h \
- src_config.h \
- src.h \
- volume.h
-
-COMP_SRC = \
- eq_iir.c \
- iir.c \
- eq_fir.c \
- fir.c \
- tone.c \
- src.c \
- src_generic.c \
- mixer.c \
- mux.c \
- volume.c \
- volume_generic.c \
- switch.c \
- dai.c \
- host.c \
- pipeline.c \
- component.c \
- buffer.c
-
-SOF_SRC = \
- dai.c \
- host.c \
- pipeline.c \
- component.c \
- buffer.c
-
-SRC_SRC = \
- src.c \
- src_generic.c
-
-EQ_FIR_SRC = \
- eq_fir.c \
- fir.c
-
-EQ_IIR_SRC = \
- eq_iir.c \
- iir.c
-
-VOLUME_SRC = \
- volume.c \
- volume_generic.c
-
-# common compiler flags for libs
-lib_cflags = \
- $(AM_CFLAGS) \
- $(ARCH_CFLAGS)
-
-if BUILD_LIB
-
-# only host builds shared libraries, the rest are static
-if BUILD_HOST
-
-# common linker flags for host libs
-host_lib_ldflags = \
- $(AM_LDFLAGS) \
- -version-info `echo $(VERSION) | cut -d '.' -f 1 | cut -d '0' -f 2` \
- -no-undefined \
- -export-dynamic
-
-# libsof
-lib_LTLIBRARIES = libsof.la
-
-libsof_la_SOURCES = $(SOF_SRC)
-
-libsof_la_CFLAGS = \
- $(lib_cflags) \
- $(COMMON_INCDIR)
-
-libsof_la_LDFLAGS = $(host_lib_ldflags)
-
-# libsof_src
-lib_LTLIBRARIES += libsof_src.la
-
-libsof_src_la_SOURCES = $(SRC_SRC)
-
-libsof_src_la_CFLAGS = \
- $(lib_cflags) \
- $(COMMON_INCDIR)
-
-libsof_src_la_LDFLAGS = $(host_lib_ldflags)
-
-# libsof_eq_fir
-lib_LTLIBRARIES += libsof_eq_fir.la
-
-libsof_eq_fir_la_SOURCES = $(EQ_FIR_SRC)
-
-libsof_eq_fir_la_CFLAGS = \
- $(lib_cflags) \
- $(COMMON_INCDIR)
-
-libsof_eq_fir_la_LDFLAGS = $(host_lib_ldflags)
-
-# libsof_eq_iir
-lib_LTLIBRARIES += libsof_eq_iir.la
-
-libsof_eq_iir_la_SOURCES = $(EQ_IIR_SRC)
-
-libsof_eq_iir_la_CFLAGS = \
- $(lib_cflags) \
- $(COMMON_INCDIR)
-
-libsof_eq_iir_la_LDFLAGS = $(host_lib_ldflags)
-
-# libsof_volume
-lib_LTLIBRARIES += libsof_volume.la
-
-libsof_volume_la_SOURCES = $(VOLUME_SRC)
-
-libsof_volume_la_CFLAGS = \
- $(lib_cflags) \
- $(COMMON_INCDIR)
-
-libsof_volume_la_LDFLAGS = $(host_lib_ldflags)
-
-# libsof_mux
-lib_LTLIBRARIES += libsof_mux.la
-
-libsof_mux_la_SOURCES = mux.c
-
-libsof_mux_la_CFLAGS = \
- $(lib_cflags) \
- $(COMMON_INCDIR)
-
-libsof_mux_la_LDFLAGS = $(host_lib_ldflags)
-
-# libsof_switch
-lib_LTLIBRARIES += libsof_switch.la
-
-libsof_switch_la_SOURCES = switch.c
-
-libsof_switch_la_CFLAGS = \
- $(lib_cflags) \
- $(COMMON_INCDIR)
-
-libsof_switch_la_LDFLAGS = $(host_lib_ldflags)
-
-# libsof_mixer
-lib_LTLIBRARIES += libsof_mixer.la
-
-libsof_mixer_la_SOURCES = mixer.c
-
-libsof_mixer_la_CFLAGS = \
- $(lib_cflags) \
- $(COMMON_INCDIR)
-
-libsof_mixer_la_LDFLAGS = $(host_lib_ldflags)
-
-# libsof_tone
-lib_LTLIBRARIES += libsof_tone.la
-
-libsof_tone_la_SOURCES = tone.c
-
-libsof_tone_la_CFLAGS = \
- $(lib_cflags) \
- $(COMMON_INCDIR)
-
-libsof_tone_la_LDFLAGS = $(host_lib_ldflags)
-
-if HAVE_SSE42
-# libsof
-lib_LTLIBRARIES += libsof_sse42.la
-
-libsof_sse42_la_SOURCES = $(SOF_SRC)
-
-libsof_sse42_la_CFLAGS = \
- $(lib_cflags) \
- $(SSE42_CFLAGS) \
- $(COMMON_INCDIR)
-
-libsof_sse42_la_LDFLAGS = $(host_lib_ldflags)
-
-# libsof_src
-lib_LTLIBRARIES += libsof_src_sse42.la
-
-libsof_src_sse42_la_SOURCES = $(SRC_SRC)
-
-libsof_src_sse42_la_CFLAGS = \
- $(lib_cflags) \
- $(SSE42_CFLAGS) \
- $(COMMON_INCDIR)
-
-libsof_src_sse42_la_LDFLAGS = $(host_lib_ldflags)
-
-# libsof_eq_fir
-lib_LTLIBRARIES += libsof_eq_fir_sse42.la
-
-libsof_eq_fir_sse42_la_SOURCES = $(EQ_FIR_SRC)
-
-libsof_eq_fir_sse42_la_CFLAGS = \
- $(lib_cflags) \
- $(SSE42_CFLAGS) \
- $(COMMON_INCDIR)
-
-libsof_eq_fir_sse42_la_LDFLAGS = $(host_lib_ldflags)
-
-# libsof_eq_iir
-lib_LTLIBRARIES += libsof_eq_iir_sse42.la
-
-libsof_eq_iir_sse42_la_SOURCES = $(EQ_IIR_SRC)
-
-libsof_eq_iir_sse42_la_CFLAGS = \
- $(lib_cflags) \
- $(SSE42_CFLAGS) \
- $(COMMON_INCDIR)
-
-libsof_eq_iir_sse42_la_LDFLAGS = $(host_lib_ldflags)
-
-# libsof_volume
-lib_LTLIBRARIES += libsof_volume_sse42.la
-
-libsof_volume_sse42_la_SOURCES = $(VOLUME_SRC)
-
-libsof_volume_sse42_la_CFLAGS = \
- $(lib_cflags) \
- $(SSE42_CFLAGS) \
- $(COMMON_INCDIR)
-
-libsof_volume_sse42_la_LDFLAGS = $(host_lib_ldflags)
-
-# libsof_mux
-lib_LTLIBRARIES += libsof_mux_sse42.la
-
-libsof_mux_sse42_la_SOURCES = mux.c
-
-libsof_mux_sse42_la_CFLAGS = \
- $(lib_cflags) \
- $(SSE42_CFLAGS) \
- $(COMMON_INCDIR)
-
-libsof_mux_sse42_la_LDFLAGS = $(host_lib_ldflags)
-
-# libsof_switch
-lib_LTLIBRARIES += libsof_switch_sse42.la
-
-libsof_switch_sse42_la_SOURCES = switch.c
-
-libsof_switch_sse42_la_CFLAGS = \
- $(lib_cflags) \
- $(SSE42_CFLAGS) \
- $(COMMON_INCDIR)
-
-libsof_switch_sse42_la_LDFLAGS = $(host_lib_ldflags)
-
-# libsof_mixer
-lib_LTLIBRARIES += libsof_mixer_sse42.la
-
-libsof_mixer_sse42_la_SOURCES = mixer.c
-
-libsof_mixer_sse42_la_CFLAGS = \
- $(lib_cflags) \
- $(SSE42_CFLAGS) \
- $(COMMON_INCDIR)
-
-libsof_mixer_sse42_la_LDFLAGS = $(host_lib_ldflags)
-
-# libsof_tone
-lib_LTLIBRARIES += libsof_tone_sse42.la
-
-libsof_tone_sse42_la_SOURCES = tone.c
-
-libsof_tone_sse42_la_CFLAGS = \
- $(lib_cflags) \
- $(SSE42_CFLAGS) \
- $(COMMON_INCDIR)
-
-libsof_tone_sse42_la_LDFLAGS = $(host_lib_ldflags)
-endif
-
-if HAVE_AVX
-# libsof
-lib_LTLIBRARIES += libsof_avx.la
-
-libsof_avx_la_SOURCES = $(SOF_SRC)
-
-libsof_avx_la_CFLAGS = \
- $(lib_cflags) \
- $(AVX_CFLAGS) \
- $(COMMON_INCDIR)
-
-libsof_avx_la_LDFLAGS = $(host_lib_ldflags)
-
-# libsof_src
-lib_LTLIBRARIES += libsof_src_avx.la
-
-libsof_src_avx_la_SOURCES = $(SRC_SRC)
-
-libsof_src_avx_la_CFLAGS = \
- $(lib_cflags) \
- $(AVX_CFLAGS) \
- $(COMMON_INCDIR)
-
-libsof_src_avx_la_LDFLAGS = $(host_lib_ldflags)
-
-# libsof_eq_fir
-lib_LTLIBRARIES += libsof_eq_fir_avx.la
-
-libsof_eq_fir_avx_la_SOURCES = $(EQ_FIR_SRC)
-
-libsof_eq_fir_avx_la_CFLAGS = \
- $(lib_cflags) \
- $(AVX_CFLAGS) \
- $(COMMON_INCDIR)
-
-libsof_eq_fir_avx_la_LDFLAGS = $(host_lib_ldflags)
-
-# libsof_eq_iir
-lib_LTLIBRARIES += libsof_eq_iir_avx.la
-
-libsof_eq_iir_avx_la_SOURCES = $(EQ_IIR_SRC)
-
-libsof_eq_iir_avx_la_CFLAGS = \
- $(lib_cflags) \
- $(AVX_CFLAGS) \
- $(COMMON_INCDIR)
-
-libsof_eq_iir_avx_la_LDFLAGS = $(host_lib_ldflags)
-
-# libsof_volume
-lib_LTLIBRARIES += libsof_volume_avx.la
-
-libsof_volume_avx_la_SOURCES = $(VOLUME_SRC)
-
-libsof_volume_avx_la_CFLAGS = \
- $(lib_cflags) \
- $(AVX_CFLAGS) \
- $(COMMON_INCDIR)
-
-libsof_volume_avx_la_LDFLAGS = $(host_lib_ldflags)
-
-# libsof_mux
-lib_LTLIBRARIES += libsof_mux_avx.la
-
-libsof_mux_avx_la_SOURCES = mux.c
-
-libsof_mux_avx_la_CFLAGS = \
- $(lib_cflags) \
- $(AVX_CFLAGS) \
- $(COMMON_INCDIR)
-
-libsof_mux_avx_la_LDFLAGS = $(host_lib_ldflags)
-
-# libsof_switch
-lib_LTLIBRARIES += libsof_switch_avx.la
-
-libsof_switch_avx_la_SOURCES = switch.c
-
-libsof_switch_avx_la_CFLAGS = \
- $(lib_cflags) \
- $(AVX_CFLAGS) \
- $(COMMON_INCDIR)
-
-libsof_switch_avx_la_LDFLAGS = $(host_lib_ldflags)
-
-# libsof_mixer
-lib_LTLIBRARIES += libsof_mixer_avx.la
-
-libsof_mixer_avx_la_SOURCES = mixer.c
-
-libsof_mixer_avx_la_CFLAGS = \
- $(lib_cflags) \
- $(AVX_CFLAGS) \
- $(COMMON_INCDIR)
-
-libsof_mixer_avx_la_LDFLAGS = $(host_lib_ldflags)
-
-# libsof_tone
-lib_LTLIBRARIES += libsof_tone_avx.la
-
-libsof_tone_avx_la_SOURCES = tone.c
-
-libsof_tone_avx_la_CFLAGS = \
- $(lib_cflags) \
- $(AVX_CFLAGS) \
- $(COMMON_INCDIR)
-
-libsof_tone_avx_la_LDFLAGS = $(host_lib_ldflags)
-endif
-
-if HAVE_AVX2
-# libsof
-lib_LTLIBRARIES += libsof_avx2.la
-
-libsof_avx2_la_SOURCES = $(SOF_SRC)
-
-libsof_avx2_la_CFLAGS = \
- $(lib_cflags) \
- $(AVX2_CFLAGS) \
- $(COMMON_INCDIR)
-
-libsof_avx2_la_LDFLAGS = $(host_lib_ldflags)
-
-# libsof_src
-lib_LTLIBRARIES += libsof_src_avx2.la
-
-libsof_src_avx2_la_SOURCES = $(SRC_SRC)
-
-libsof_src_avx2_la_CFLAGS = \
- $(lib_cflags) \
- $(AVX2_CFLAGS) \
- $(COMMON_INCDIR)
-
-libsof_src_avx2_la_LDFLAGS = $(host_lib_ldflags)
-
-# libsof_eq_fir
-lib_LTLIBRARIES += libsof_eq_fir_avx2.la
-
-libsof_eq_fir_avx2_la_SOURCES = $(EQ_FIR_SRC)
-
-libsof_eq_fir_avx2_la_CFLAGS = \
- $(lib_cflags) \
- $(AVX2_CFLAGS) \
- $(COMMON_INCDIR)
-
-libsof_eq_fir_avx2_la_LDFLAGS = $(host_lib_ldflags)
-
-# libsof_eq_iir
-lib_LTLIBRARIES += libsof_eq_iir_avx2.la
-
-libsof_eq_iir_avx2_la_SOURCES = $(EQ_IIR_SRC)
-
-libsof_eq_iir_avx2_la_CFLAGS = \
- $(lib_cflags) \
- $(AVX2_CFLAGS) \
- $(COMMON_INCDIR)
-
-libsof_eq_iir_avx2_la_LDFLAGS = $(host_lib_ldflags)
-
-# libsof_volume
-lib_LTLIBRARIES += libsof_volume_avx2.la
-
-libsof_volume_avx2_la_SOURCES = $(VOLUME_SRC)
-
-libsof_volume_avx2_la_CFLAGS = \
- $(lib_cflags) \
- $(AVX2_CFLAGS) \
- $(COMMON_INCDIR)
-
-libsof_volume_avx2_la_LDFLAGS = $(host_lib_ldflags)
-
-# libsof_mux
-lib_LTLIBRARIES += libsof_mux_avx2.la
-
-libsof_mux_avx2_la_SOURCES = mux.c
-
-libsof_mux_avx2_la_CFLAGS = \
- $(lib_cflags) \
- $(AVX2_CFLAGS) \
- $(COMMON_INCDIR)
-
-libsof_mux_avx2_la_LDFLAGS = $(host_lib_ldflags)
-
-# libsof_switch
-lib_LTLIBRARIES += libsof_switch_avx2.la
-
-libsof_switch_avx2_la_SOURCES = switch.c
-
-libsof_switch_avx2_la_CFLAGS = \
- $(lib_cflags) \
- $(AVX2_CFLAGS) \
- $(COMMON_INCDIR)
-
-libsof_switch_avx2_la_LDFLAGS = $(host_lib_ldflags)
-
-# libsof_mixer
-lib_LTLIBRARIES += libsof_mixer_avx2.la
-
-libsof_mixer_avx2_la_SOURCES = mixer.c
-
-libsof_mixer_avx2_la_CFLAGS = \
- $(lib_cflags) \
- $(AVX2_CFLAGS) \
- $(COMMON_INCDIR)
-
-libsof_mixer_avx2_la_LDFLAGS = $(host_lib_ldflags)
-
-# libsof_tone
-lib_LTLIBRARIES += libsof_tone_avx2.la
-
-libsof_tone_avx2_la_SOURCES = tone.c
-
-libsof_tone_avx2_la_CFLAGS = \
- $(lib_cflags) \
- $(AVX2_CFLAGS) \
- $(COMMON_INCDIR)
-
-libsof_tone_avx2_la_LDFLAGS = $(host_lib_ldflags)
-
-endif
-
-if HAVE_FMA
-# libsof
-lib_LTLIBRARIES += libsof_fma.la
-
-libsof_fma_la_SOURCES = $(SOF_SRC)
-
-libsof_fma_la_CFLAGS = \
- $(lib_cflags) \
- $(FMA_CFLAGS) \
- $(COMMON_INCDIR)
-
-libsof_fma_la_LDFLAGS = $(host_lib_ldflags)
-
-# libsof_src
-lib_LTLIBRARIES += libsof_src_fma.la
-
-libsof_src_fma_la_SOURCES = $(SRC_SRC)
-
-libsof_src_fma_la_CFLAGS = \
- $(lib_cflags) \
- $(FMA_CFLAGS) \
- $(COMMON_INCDIR)
-
-libsof_src_fma_la_LDFLAGS = $(host_lib_ldflags)
-
-# libsof_eq_fir
-lib_LTLIBRARIES += libsof_eq_fir_fma.la
-
-libsof_eq_fir_fma_la_SOURCES = $(EQ_FIR_SRC)
-
-libsof_eq_fir_fma_la_CFLAGS = \
- $(lib_cflags) \
- $(FMA_CFLAGS) \
- $(COMMON_INCDIR)
-
-libsof_eq_fir_fma_la_LDFLAGS = $(host_lib_ldflags)
-
-# libsof_eq_iir
-lib_LTLIBRARIES += libsof_eq_iir_fma.la
-
-libsof_eq_iir_fma_la_SOURCES = $(EQ_IIR_SRC)
-
-libsof_eq_iir_fma_la_CFLAGS = \
- $(lib_cflags) \
- $(FMA_CFLAGS) \
- $(COMMON_INCDIR)
-
-libsof_eq_iir_fma_la_LDFLAGS = $(host_lib_ldflags)
-
-# libsof_volume
-lib_LTLIBRARIES += libsof_volume_fma.la
-
-libsof_volume_fma_la_SOURCES = $(VOLUME_SRC)
-
-libsof_volume_fma_la_CFLAGS = \
- $(lib_cflags) \
- $(FMA_CFLAGS) \
- $(COMMON_INCDIR)
-
-libsof_volume_fma_la_LDFLAGS = $(host_lib_ldflags)
-
-# libsof_mux
-lib_LTLIBRARIES += libsof_mux_fma.la
-
-libsof_mux_fma_la_SOURCES = mux.c
-
-libsof_mux_fma_la_CFLAGS = \
- $(lib_cflags) \
- $(FMA_CFLAGS) \
- $(COMMON_INCDIR)
-
-libsof_mux_fma_la_LDFLAGS = $(host_lib_ldflags)
-
-# libsof_switch
-lib_LTLIBRARIES += libsof_switch_fma.la
-
-libsof_switch_fma_la_SOURCES = switch.c
-
-libsof_switch_fma_la_CFLAGS = \
- $(lib_cflags) \
- $(FMA_CFLAGS) \
- $(COMMON_INCDIR)
-
-libsof_switch_fma_la_LDFLAGS = $(host_lib_ldflags)
-
-# libsof_mixer
-lib_LTLIBRARIES += libsof_mixer_fma.la
-
-libsof_mixer_fma_la_SOURCES = mixer.c
-
-libsof_mixer_fma_la_CFLAGS = \
- $(lib_cflags) \
- $(FMA_CFLAGS) \
- $(COMMON_INCDIR)
-
-libsof_mixer_fma_la_LDFLAGS = $(host_lib_ldflags)
-
-# libsof_tone
-lib_LTLIBRARIES += libsof_tone_fma.la
-
-libsof_tone_fma_la_SOURCES = tone.c
-
-libsof_tone_fma_la_CFLAGS = \
- $(lib_cflags) \
- $(FMA_CFLAGS) \
- $(COMMON_INCDIR)
-
-libsof_tone_fma_la_LDFLAGS = $(host_lib_ldflags)
-endif
-
-else
-
-# Build for non host targets
-
-# libsof
-lib_LIBRARIES = libsof.a
-
-libsof_a_SOURCES = $(SOF_SRC)
-
-libsof_a_CFLAGS = \
- $(lib_cflags) \
- $(COMMON_INCDIR)
-
-# libsof_src
-lib_LIBRARIES += libsof_src.a
-
-libsof_src_a_SOURCES = $(SRC_SRC)
-
-libsof_src_a_CFLAGS = \
- $(lib_cflags) \
- $(COMMON_INCDIR)
-
-# libsof_eq_fir
-lib_LIBRARIES += libsof_eq_fir.a
-
-libsof_eq_fir_a_SOURCES = $(EQ_FIR_SRC)
-
-libsof_eq_fir_a_CFLAGS = \
- $(lib_cflags) \
- $(COMMON_INCDIR)
-
-# libsof_eq_iir
-lib_LIBRARIES += libsof_eq_iir.a
-
-libsof_eq_iir_a_SOURCES = $(EQ_IIR_SRC)
-
-libsof_eq_iir_a_CFLAGS = \
- $(lib_cflags) \
- $(COMMON_INCDIR)
-
-# libsof_volume
-lib_LIBRARIES += libsof_volume.a
-
-libsof_volume_a_SOURCES = $(VOLUME_SRC)
-
-libsof_volume_a_CFLAGS = \
- $(lib_cflags) \
- $(COMMON_INCDIR)
-
-# libsof_mux
-lib_LIBRARIES += libsof_mux.a
-
-libsof_mux_a_SOURCES = mux.c
-
-libsof_mux_a_CFLAGS = \
- $(lib_cflags) \
- $(COMMON_INCDIR)
-
-# libsof_switch
-lib_LIBRARIES += libsof_switch.a
-
-libsof_switch_a_SOURCES = switch.c
-
-libsof_switch_a_CFLAGS = \
- $(lib_cflags) \
- $(COMMON_INCDIR)
-
-# libsof_mixer
-lib_LIBRARIES += libsof_mixer.a
-
-libsof_mixer_a_SOURCES = mixer.c
-
-libsof_mixer_a_CFLAGS = \
- $(lib_cflags) \
- $(COMMON_INCDIR)
-
-# libsof_tone
-lib_LIBRARIES += libsof_tone.a
-
-libsof_tone_a_SOURCES = tone.c
-
-libsof_tone_a_CFLAGS = \
- $(lib_cflags) \
- $(COMMON_INCDIR)
-
-
-if HAVE_HIFI2EP
-# libsof
-lib_LIBRARIES += libsof_hifi2ep.a
-
-libsof_hifi2ep_a_SOURCES = $(SOF_SRC)
-
-libsof_hifi2ep_a_CFLAGS = \
- $(lib_cflags) \
- $(SSE42_CFLAGS) \
- $(COMMON_INCDIR)
-
-# libsof_src
-lib_LIBRARIES += libsof_src_hifi2ep.a
-
-libsof_src_hifi2ep_a_SOURCES = $(SRC_SRC)
-
-libsof_src_hifi2ep_a_CFLAGS = \
- $(lib_cflags) \
- $(SSE42_CFLAGS) \
- $(COMMON_INCDIR)
-
-# libsof_eq_fir
-lib_LIBRARIES += libsof_eq_fir_hifi2ep.a
-
-libsof_eq_fir_hifi2ep_a_SOURCES = $(EQ_FIR_SRC)
-
-libsof_eq_fir_hifi2ep_a_CFLAGS = \
- $(lib_cflags) \
- $(SSE42_CFLAGS) \
- $(COMMON_INCDIR)
-
-# libsof_eq_iir
-lib_LIBRARIES += libsof_eq_iir_hifi2ep.a
-
-libsof_eq_iir_hifi2ep_a_SOURCES = $(EQ_IIR_SRC)
-
-libsof_eq_iir_hifi2ep_a_CFLAGS = \
- $(lib_cflags) \
- $(SSE42_CFLAGS) \
- $(COMMON_INCDIR)
-
-# libsof_volume
-lib_LIBRARIES += libsof_volume_hifi2ep.a
-
-libsof_volume_hifi2ep_a_SOURCES = $(VOLUME_SRC)
-
-libsof_volume_hifi2ep_a_CFLAGS = \
- $(lib_cflags) \
- $(SSE42_CFLAGS) \
- $(COMMON_INCDIR)
-
-# libsof_mux
-lib_LIBRARIES += libsof_mux_hifi2ep.a
-
-libsof_mux_hifi2ep_a_SOURCES = mux.c
-
-libsof_mux_hifi2ep_a_CFLAGS = \
- $(lib_cflags) \
- $(SSE42_CFLAGS) \
- $(COMMON_INCDIR)
-
-# libsof_switch
-lib_LIBRARIES += libsof_switch_hifi2ep.a
-
-libsof_switch_hifi2ep_a_SOURCES = switch.c
-
-libsof_switch_hifi2ep_a_CFLAGS = \
- $(lib_cflags) \
- $(SSE42_CFLAGS) \
- $(COMMON_INCDIR)
-
-# libsof_mixer
-lib_LIBRARIES += libsof_mixer_hifi2ep.a
-
-libsof_mixer_hifi2ep_a_SOURCES = mixer.c
-
-libsof_mixer_hifi2ep_a_CFLAGS = \
- $(lib_cflags) \
- $(SSE42_CFLAGS) \
- $(COMMON_INCDIR)
-
-# libsof_tone
-lib_LIBRARIES += libsof_tone_hifi2ep.a
-
-libsof_tone_hifi2ep_a_SOURCES = tone.c
-
-libsof_tone_hifi2ep_a_CFLAGS = \
- $(lib_cflags) \
- $(SSE42_CFLAGS) \
- $(COMMON_INCDIR)
-endif
-
-if HAVE_HIFI3
-# libsof
-lib_LIBRARIES += libsof_hifi3.a
-
-libsof_hifi3_a_SOURCES = $(COMP_SRC)
-
-libsof_hifi3_a_CFLAGS = \
- $(lib_cflags) \
- $(SSE42_CFLAGS) \
- $(COMMON_INCDIR)
-
-# libsof_src
-lib_LIBRARIES += libsof_src_hifi3.a
-
-libsof_src_hifi3_a_SOURCES = $(SRC_SRC)
-
-libsof_src_hifi3_a_CFLAGS = \
- $(lib_cflags) \
- $(SSE42_CFLAGS) \
- $(COMMON_INCDIR)
-
-# libsof_eq_fir
-lib_LIBRARIES += libsof_eq_fir_hifi3.a
-
-libsof_eq_fir_hifi3_a_SOURCES = $(EQ_FIR_SRC)
-
-libsof_eq_fir_hifi3_a_CFLAGS = \
- $(lib_cflags) \
- $(SSE42_CFLAGS) \
- $(COMMON_INCDIR)
-
-# libsof_eq_iir
-lib_LIBRARIES += libsof_eq_iir_hifi3.a
-
-libsof_eq_iir_hifi3_a_SOURCES = $(EQ_IIR_SRC)
-
-libsof_eq_iir_hifi3_a_CFLAGS = \
- $(lib_cflags) \
- $(SSE42_CFLAGS) \
- $(COMMON_INCDIR)
-
-# libsof_volume
-lib_LIBRARIES += libsof_volume_hifi3.a
-
-libsof_volume_hifi3_a_SOURCES = $(VOLUME_SRC)
-
-libsof_volume_hifi3_a_CFLAGS = \
- $(lib_cflags) \
- $(SSE42_CFLAGS) \
- $(COMMON_INCDIR)
-
-# libsof_mux
-lib_LIBRARIES += libsof_mux_hifi3.a
-
-libsof_mux_hifi3_a_SOURCES = mux.c
-
-libsof_mux_hifi3_a_CFLAGS = \
- $(lib_cflags) \
- $(SSE42_CFLAGS) \
- $(COMMON_INCDIR)
-
-# libsof_switch
-lib_LIBRARIES += libsof_switch_hifi3.a
-
-libsof_switch_hifi3_a_SOURCES = switch.c
-
-libsof_switch_hifi3_a_CFLAGS = \
- $(lib_cflags) \
- $(SSE42_CFLAGS) \
- $(COMMON_INCDIR)
-
-# libsof_mixer
-lib_LIBRARIES += libsof_mixer_hifi3.a
-
-libsof_mixer_hifi3_a_SOURCES = mixer.c
-
-libsof_mixer_hifi3_a_CFLAGS = \
- $(lib_cflags) \
- $(SSE42_CFLAGS) \
- $(COMMON_INCDIR)
-
-# libsof_tone
-lib_LIBRARIES += libsof_tone_hifi3.a
-
-libsof_tone_hifi3_a_SOURCES = tone.c
-
-libsof_tone_hifi3_a_CFLAGS = \
- $(lib_cflags) \
- $(SSE42_CFLAGS) \
- $(COMMON_INCDIR)
-endif
-
-endif
-
-else
-
-# build for firmware image
-
-noinst_LIBRARIES = libaudio.a
-
-libaudio_a_SOURCES = \
- eq_iir.c \
- iir.c \
- eq_fir.c \
- fir.c \
- fir_hifi2ep.c \
- fir_hifi3.c \
- tone.c \
- src.c \
- src_generic.c \
- src_hifi2ep.c \
- src_hifi3.c \
- mixer.c \
- mux.c \
- volume.c \
- volume_generic.c \
- volume_hifi3.c \
- switch.c \
- dai.c \
- host.c \
- pipeline.c \
- pipeline_static.c \
- component.c \
- buffer.c
-
-libaudio_a_CFLAGS = \
- $(lib_cflags) \
- $(COMMON_INCDIR)
-
-endif
diff --git a/src/audio/buffer.c b/src/audio/buffer.c
deleted file mode 100644
index 8121355..0000000
--- a/src/audio/buffer.c
+++ /dev/null
@@ -1,184 +0,0 @@
-/*
- * Copyright (c) 2016, Intel Corporation
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- * * Redistributions of source code must retain the above copyright
- * notice, this list of conditions and the following disclaimer.
- * * Redistributions in binary form must reproduce the above copyright
- * notice, this list of conditions and the following disclaimer in the
- * documentation and/or other materials provided with the distribution.
- * * Neither the name of the Intel Corporation nor the
- * names of its contributors may be used to endorse or promote products
- * derived from this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
- * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
- * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
- * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
- * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
- * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
- * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
- * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
- * POSSIBILITY OF SUCH DAMAGE.
- *
- * Author: Liam Girdwood <liam.r.girdwood@linux.intel.com>
- * Keyon Jie <yang.jie@linux.intel.com>
- */
-
-#include <stdint.h>
-#include <stddef.h>
-#include <errno.h>
-#include <sof/sof.h>
-#include <sof/lock.h>
-#include <sof/list.h>
-#include <sof/stream.h>
-#include <sof/alloc.h>
-#include <sof/debug.h>
-#include <sof/ipc.h>
-#include <platform/timer.h>
-#include <platform/platform.h>
-#include <sof/audio/component.h>
-#include <sof/audio/pipeline.h>
-#include <sof/audio/buffer.h>
-
-/* create a new component in the pipeline */
-struct comp_buffer *buffer_new(struct sof_ipc_buffer *desc)
-{
- struct comp_buffer *buffer;
-
- trace_buffer("new");
-
- /* validate request */
- if (desc->size == 0 || desc->size > HEAP_BUFFER_SIZE) {
- trace_buffer_error("ebg");
- trace_error_value(desc->size);
- return NULL;
- }
-
- /* allocate new buffer */
- buffer = rzalloc(RZONE_RUNTIME, SOF_MEM_CAPS_RAM, sizeof(*buffer));
- if (buffer == NULL) {
- trace_buffer_error("ebN");
- return NULL;
- }
-
- buffer->addr = rballoc(RZONE_RUNTIME, desc->caps, desc->size);
- if (buffer->addr == NULL) {
- rfree(buffer);
- trace_buffer_error("ebm");
- return NULL;
- }
-
- memcpy(&buffer->ipc_buffer, desc, sizeof(*desc));
-
- buffer->size = buffer->alloc_size = desc->size;
- buffer->ipc_buffer = *desc;
- buffer->w_ptr = buffer->r_ptr = buffer->addr;
- buffer->end_addr = buffer->addr + buffer->ipc_buffer.size;
- buffer->free = buffer->ipc_buffer.size;
- buffer->avail = 0;
- buffer->connected = 0;
-
- buffer_zero(buffer);
-
- spinlock_init(&buffer->lock);
-
- return buffer;
-}
-
-/* free component in the pipeline */
-void buffer_free(struct comp_buffer *buffer)
-{
- trace_buffer("BFr");
-
- list_item_del(&buffer->source_list);
- list_item_del(&buffer->sink_list);
- rfree(buffer->addr);
- rfree(buffer);
-}
-
-void comp_update_buffer_produce(struct comp_buffer *buffer, uint32_t bytes)
-{
- uint32_t flags;
-
- spin_lock_irq(&buffer->lock, flags);
-
- /*
- * new data produce, handle consistency for buffer and cache:
- * 1. source(DMA) --> buffer --> sink(non-DMA): invalidate cache.
- * 2. source(non-DMA) --> buffer --> sink(DMA): write back to memory.
- * 3. source(DMA) --> buffer --> sink(DMA): do nothing.
- * 4. source(non-DMA) --> buffer --> sink(non-DMA): do nothing.
- */
- if (buffer->source->is_dma_connected &&
- !buffer->sink->is_dma_connected)
- /* need invalidate cache for sink component to use */
- dcache_invalidate_region(buffer->w_ptr, bytes);
- else if (!buffer->source->is_dma_connected &&
- buffer->sink->is_dma_connected)
- /* need write back to memory for sink component to use */
- dcache_writeback_region(buffer->w_ptr, bytes);
-
- buffer->w_ptr += bytes;
-
- /* check for pointer wrap */
- if (buffer->w_ptr >= buffer->end_addr)
- buffer->w_ptr = buffer->addr + (buffer->w_ptr - buffer->end_addr);
-
- /* calculate available bytes */
- if (buffer->r_ptr < buffer->w_ptr)
- buffer->avail = buffer->w_ptr - buffer->r_ptr;
- else if (buffer->r_ptr == buffer->w_ptr)
- buffer->avail = buffer->size; /* full */
- else
- buffer->avail = buffer->size - (buffer->r_ptr - buffer->w_ptr);
-
- /* calculate free bytes */
- buffer->free = buffer->size - buffer->avail;
-
- spin_unlock_irq(&buffer->lock, flags);
-
- tracev_buffer("pro");
- tracev_value((buffer->avail << 16) | buffer->free);
- tracev_value((buffer->ipc_buffer.comp.id << 16) | buffer->size);
- tracev_value((buffer->r_ptr - buffer->addr) << 16 | (buffer->w_ptr - buffer->addr));
-}
-
-void comp_update_buffer_consume(struct comp_buffer *buffer, uint32_t bytes)
-{
- uint32_t flags;
-
- spin_lock_irq(&buffer->lock, flags);
-
- buffer->r_ptr += bytes;
-
- /* check for pointer wrap */
- if (buffer->r_ptr >= buffer->end_addr)
- buffer->r_ptr = buffer->addr + (buffer->r_ptr - buffer->end_addr);
-
- /* calculate available bytes */
- if (buffer->r_ptr < buffer->w_ptr)
- buffer->avail = buffer->w_ptr - buffer->r_ptr;
- else if (buffer->r_ptr == buffer->w_ptr)
- buffer->avail = 0; /* empty */
- else
- buffer->avail = buffer->size - (buffer->r_ptr - buffer->w_ptr);
-
- /* calculate free bytes */
- buffer->free = buffer->size - buffer->avail;
-
- if (buffer->sink->is_dma_connected &&
- !buffer->source->is_dma_connected)
- dcache_writeback_region(buffer->r_ptr, bytes);
-
- spin_unlock_irq(&buffer->lock, flags);
-
- tracev_buffer("con");
- tracev_value((buffer->avail << 16) | buffer->free);
- tracev_value((buffer->ipc_buffer.comp.id << 16) | buffer->size);
- tracev_value((buffer->r_ptr - buffer->addr) << 16 | (buffer->w_ptr - buffer->addr));
-}
diff --git a/src/audio/component.c b/src/audio/component.c
deleted file mode 100644
index 5d91a9b..0000000
--- a/src/audio/component.c
+++ /dev/null
@@ -1,195 +0,0 @@
-/*
- * Copyright (c) 2016, Intel Corporation
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- * * Redistributions of source code must retain the above copyright
- * notice, this list of conditions and the following disclaimer.
- * * Redistributions in binary form must reproduce the above copyright
- * notice, this list of conditions and the following disclaimer in the
- * documentation and/or other materials provided with the distribution.
- * * Neither the name of the Intel Corporation nor the
- * names of its contributors may be used to endorse or promote products
- * derived from this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
- * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
- * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
- * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
- * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
- * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
- * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
- * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
- * POSSIBILITY OF SUCH DAMAGE.
- *
- * Author: Liam Girdwood <liam.r.girdwood@linux.intel.com>
- */
-
-#include <stdint.h>
-#include <stddef.h>
-#include <errno.h>
-#include <sof/sof.h>
-#include <sof/lock.h>
-#include <sof/list.h>
-#include <sof/stream.h>
-#include <sof/alloc.h>
-#include <sof/audio/component.h>
-#include <sof/audio/pipeline.h>
-#include <uapi/ipc.h>
-
-struct comp_data {
- struct list_item list; /* list of components */
- spinlock_t lock;
-};
-
-static struct comp_data *cd;
-
-static struct comp_driver *get_drv(uint32_t type)
-{
- struct list_item *clist;
- struct comp_driver *drv = NULL;
-
- spin_lock(&cd->lock);
-
- /* search driver list for driver type */
- list_for_item(clist, &cd->list) {
-
- drv = container_of(clist, struct comp_driver, list);
- if (drv->type == type)
- goto out;
- }
-
- /* not found */
- drv = NULL;
-
-out:
- spin_unlock(&cd->lock);
- return drv;
-}
-
-struct comp_dev *comp_new(struct sof_ipc_comp *comp)
-{
- struct comp_dev *cdev;
- struct comp_driver *drv;
-
- /* find the driver for our new component */
- drv = get_drv(comp->type);
- if (drv == NULL) {
- trace_comp_error("eCD");
- trace_error_value(comp->type);
- return NULL;
- }
-
- /* create the new component */
- cdev = drv->ops.new(comp);
- if (cdev == NULL) {
- trace_comp_error("eCN");
- return NULL;
- }
-
- /* init component */
- memcpy(&cdev->comp, comp, sizeof(*comp));
- cdev->drv = drv;
- spinlock_init(&cdev->lock);
- list_init(&cdev->bsource_list);
- list_init(&cdev->bsink_list);
-
- return cdev;
-}
-
-int comp_register(struct comp_driver *drv)
-{
- spin_lock(&cd->lock);
- list_item_prepend(&drv->list, &cd->list);
- spin_unlock(&cd->lock);
-
- return 0;
-}
-
-void comp_unregister(struct comp_driver *drv)
-{
- spin_lock(&cd->lock);
- list_item_del(&drv->list);
- spin_unlock(&cd->lock);
-}
-
-int comp_set_state(struct comp_dev *dev, int cmd)
-{
- int ret = 0;
-
- switch (cmd) {
- case COMP_TRIGGER_START:
- if (dev->state == COMP_STATE_PREPARE) {
- dev->state = COMP_STATE_ACTIVE;
- } else {
- trace_comp_error("CES");
- trace_error_value(dev->state);
- ret = -EINVAL;
- }
- break;
- case COMP_TRIGGER_RELEASE:
- if (dev->state == COMP_STATE_PAUSED) {
- dev->state = COMP_STATE_ACTIVE;
- } else {
- trace_comp_error("CEr");
- trace_error_value(dev->state);
- ret = -EINVAL;
- }
- break;
- case COMP_TRIGGER_STOP:
- case COMP_TRIGGER_XRUN:
- if (dev->state == COMP_STATE_ACTIVE ||
- dev->state == COMP_STATE_PAUSED) {
- dev->state = COMP_STATE_PREPARE;
- } else {
- trace_comp_error("CEs");
- trace_error_value(dev->state);
- ret = -EINVAL;
- }
- break;
- case COMP_TRIGGER_PAUSE:
- /* only support pausing for running */
- if (dev->state == COMP_STATE_ACTIVE)
- dev->state = COMP_STATE_PAUSED;
- else {
- trace_comp_error("CEp");
- trace_error_value(dev->state);
- ret = -EINVAL;
- }
- break;
- case COMP_TRIGGER_RESET:
- /* reset always succeeds */
- if (dev->state == COMP_STATE_ACTIVE ||
- dev->state == COMP_STATE_PAUSED) {
- trace_comp_error("CER");
- trace_error_value(dev->state);
- ret = 0;
- }
- dev->state = COMP_STATE_READY;
- break;
- case COMP_TRIGGER_PREPARE:
- if (dev->state == COMP_STATE_PREPARE ||
- dev->state == COMP_STATE_READY) {
- dev->state = COMP_STATE_PREPARE;
- } else {
- trace_comp_error("CEP");
- trace_error_value(dev->state);
- ret = -EINVAL;
- }
- break;
- default:
- break;
- }
-
- return ret;
-}
-
-void sys_comp_init(void)
-{
- cd = rzalloc(RZONE_SYS, SOF_MEM_CAPS_RAM, sizeof(*cd));
- list_init(&cd->list);
- spinlock_init(&cd->lock);
-}
diff --git a/src/audio/dai.c b/src/audio/dai.c
deleted file mode 100644
index 4e1b677..0000000
--- a/src/audio/dai.c
+++ /dev/null
@@ -1,778 +0,0 @@
- /*
- * Copyright (c) 2016, Intel Corporation
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- * * Redistributions of source code must retain the above copyright
- * notice, this list of conditions and the following disclaimer.
- * * Redistributions in binary form must reproduce the above copyright
- * notice, this list of conditions and the following disclaimer in the
- * documentation and/or other materials provided with the distribution.
- * * Neither the name of the Intel Corporation nor the
- * names of its contributors may be used to endorse or promote products
- * derived from this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
- * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
- * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
- * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
- * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
- * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
- * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
- * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
- * POSSIBILITY OF SUCH DAMAGE.
- *
- * Author: Liam Girdwood <liam.r.girdwood@linux.intel.com>
- * Keyon Jie <yang.jie@linux.intel.com>
- */
-
-#include <stdint.h>
-#include <stddef.h>
-#include <errno.h>
-#include <sof/sof.h>
-#include <sof/lock.h>
-#include <sof/list.h>
-#include <sof/dai.h>
-#include <sof/alloc.h>
-#include <sof/dma.h>
-#include <sof/wait.h>
-#include <sof/stream.h>
-#include <sof/audio/component.h>
-#include <sof/audio/pipeline.h>
-#include <platform/dma.h>
-#include <arch/cache.h>
-
-#define DAI_PLAYBACK_STREAM 0
-#define DAI_CAPTURE_STREAM 1
-
-#define DAI_PTR_INIT_DAI 1 /* buffer ptr initialized by dai */
-#define DAI_PTR_INIT_HOST 2 /* buffer ptr initialized by host */
-
-/* tracing */
-#define trace_dai(__e) trace_event(TRACE_CLASS_DAI, __e)
-#define trace_dai_error(__e) trace_error(TRACE_CLASS_DAI, __e)
-#define tracev_dai(__e) tracev_event(TRACE_CLASS_DAI, __e)
-
-
-struct dai_data {
- /* local DMA config */
- int chan;
- struct dma_sg_config config;
-
- struct dai *dai;
- struct dma *dma;
- uint32_t period_bytes;
- completion_t complete;
- int xrun; /* true if we are doing xrun recovery */
- int pointer_init; /* true if buffer pointer was initialized */
-
- uint32_t last_bytes; /* the last bytes(<period size) it copies. */
- uint32_t dai_pos_blks; /* position in bytes (nearest block) */
-
- volatile uint64_t *dai_pos; /* host can read back this value without IPC */
- uint64_t wallclock; /* wall clock at stream start */
-};
-
-/* this is called by DMA driver every time descriptor has completed */
-static void dai_dma_cb(void *data, uint32_t type, struct dma_sg_elem *next)
-{
- struct comp_dev *dev = (struct comp_dev *)data;
- struct dai_data *dd = comp_get_drvdata(dev);
- struct comp_buffer *dma_buffer;
- uint32_t copied_size;
-
- tracev_dai("irq");
-
- /* stop dma copy for pause/stop/xrun */
- if (dev->state != COMP_STATE_ACTIVE || dd->xrun) {
-
- /* stop the DAI */
- dai_trigger(dd->dai, COMP_TRIGGER_STOP, dev->params.direction);
-
- /* tell DMA not to reload */
- next->size = DMA_RELOAD_END;
-
- /* inform waiters */
- wait_completed(&dd->complete);
- }
-
- /* is our pipeline handling an XRUN ? */
- if (dd->xrun) {
-
- /* make sure we only playback silence during an XRUN */
- if (dev->params.direction == SOF_IPC_STREAM_PLAYBACK) {
-
- dma_buffer = list_first_item(&dev->bsource_list,
- struct comp_buffer, sink_list);
-
- /* fill buffer with silence */
- buffer_zero(dma_buffer);
- }
- return;
- }
-
- if (dev->params.direction == SOF_IPC_STREAM_PLAYBACK) {
- dma_buffer = list_first_item(&dev->bsource_list,
- struct comp_buffer, sink_list);
-
- copied_size = dd->last_bytes ? dd->last_bytes : dd->period_bytes;
-
- /* recalc available buffer space */
- comp_update_buffer_consume(dma_buffer, copied_size);
-
- /* update host position(in bytes offset) for drivers */
- dev->position += copied_size;
- if (dd->dai_pos) {
- dd->dai_pos_blks += copied_size;
- *dd->dai_pos = dd->dai_pos_blks +
- dma_buffer->r_ptr - dma_buffer->addr;
- }
-
- /* make sure there is availble bytes for next period */
- if (dma_buffer->avail < dd->period_bytes) {
- trace_dai_error("xru");
- comp_underrun(dev, dma_buffer, copied_size, 0);
- }
-
- } else {
- dma_buffer = list_first_item(&dev->bsink_list,
- struct comp_buffer, source_list);
-
- /* recalc available buffer space */
- comp_update_buffer_produce(dma_buffer, dd->period_bytes);
-
- /* update positions */
- dev->position += dd->period_bytes;
- if (dd->dai_pos) {
- dd->dai_pos_blks += dd->period_bytes;
- *dd->dai_pos = dd->dai_pos_blks +
- dma_buffer->w_ptr - dma_buffer->addr;
- }
-
- /* make sure there is free bytes for next period */
- if (dma_buffer->free < dd->period_bytes) {
- trace_dai_error("xro");
- comp_overrun(dev, dma_buffer, dd->period_bytes, 0);
- }
- }
-
- /* notify pipeline that DAI needs its buffer processed */
- if (dev->state == COMP_STATE_ACTIVE)
- pipeline_schedule_copy(dev->pipeline, 0);
-}
-
-static struct comp_dev *dai_new(struct sof_ipc_comp *comp)
-{
- struct comp_dev *dev;
- struct sof_ipc_comp_dai *dai;
- struct sof_ipc_comp_dai *ipc_dai = (struct sof_ipc_comp_dai *)comp;
- struct dai_data *dd;
- uint32_t dir, caps, dma_dev;
-
- trace_dai("new");
-
- dev = rzalloc(RZONE_RUNTIME, SOF_MEM_CAPS_RAM,
- COMP_SIZE(struct sof_ipc_comp_dai));
- if (dev == NULL)
- return NULL;
-
- dai = (struct sof_ipc_comp_dai *)&dev->comp;
- memcpy(dai, ipc_dai, sizeof(struct sof_ipc_comp_dai));
-
- dd = rzalloc(RZONE_RUNTIME, SOF_MEM_CAPS_RAM, sizeof(*dd));
- if (dd == NULL) {
- rfree(dev);
- return NULL;
- }
-
- comp_set_drvdata(dev, dd);
-
- dd->dai = dai_get(dai->type, dai->dai_index);
- if (dd->dai == NULL) {
- trace_dai_error("eDg");
- goto error;
- }
-
- /* request GP LP DMA with shared access privilege */
- /* TODO: hda: retrieve req'ed caps from the dai,
- * dmas are not cross-compatible.
- */
- switch (dai->type) {
- case SOF_DAI_INTEL_HDA:
- dir = dai->direction == SOF_IPC_STREAM_PLAYBACK ?
- DMA_DIR_DEV_TO_MEM : DMA_DIR_MEM_TO_DEV;
- caps = DMA_CAP_HDA;
- dma_dev = DMA_DEV_HDA;
- break;
- case SOF_DAI_INTEL_SSP:
- case SOF_DAI_INTEL_DMIC:
- default:
- dir = DMA_DIR_MEM_TO_DEV | DMA_DIR_DEV_TO_MEM;
- caps = DMA_CAP_GP_LP | DMA_CAP_GP_HP;
- dma_dev = DMA_DEV_SSP | DMA_DEV_DMIC;
- break;
- }
- dd->dma = dma_get(dir, caps, dma_dev, DMA_ACCESS_SHARED);
- if (dd->dma == NULL) {
- trace_dai_error("eDd");
- goto error;
- }
-
- list_init(&dd->config.elem_list);
- dd->dai_pos = NULL;
- dd->dai_pos_blks = 0;
- dd->last_bytes = 0;
- dd->xrun = 0;
- dd->pointer_init = 0;
-
- dev->state = COMP_STATE_READY;
- return dev;
-
-error:
- rfree(dd);
- rfree(dev);
- return NULL;
-}
-
-static void dai_free(struct comp_dev *dev)
-{
- struct dai_data *dd = comp_get_drvdata(dev);
-
- dma_channel_put(dd->dma, dd->chan);
-
- rfree(dd);
- rfree(dev);
-}
-
-/* set component audio SSP and DMA configuration */
-static int dai_playback_params(struct comp_dev *dev)
-{
- struct dai_data *dd = comp_get_drvdata(dev);
- struct dma_sg_config *config = &dd->config;
- struct sof_ipc_comp_config *source_config;
- struct dma_sg_elem *elem;
- struct comp_buffer *dma_buffer;
- struct list_item *elist;
- struct list_item *tlist;
- int i;
- int err;
- uint32_t buffer_size;
-
- /* set up DMA configuration */
- config->direction = DMA_DIR_MEM_TO_DEV;
- config->src_width = comp_sample_bytes(dev);
- config->dest_width = comp_sample_bytes(dev);
- config->cyclic = 1;
- config->dest_dev = dd->dai->plat_data.fifo[0].handshake;
-
- /* set up local and host DMA elems to reset values */
- dma_buffer = list_first_item(&dev->bsource_list,
- struct comp_buffer, sink_list);
- source_config = COMP_GET_CONFIG(dma_buffer->source);
- buffer_size = source_config->periods_sink * dd->period_bytes;
-
- /* resize the buffer if space is available to align with period size */
- err = buffer_set_size(dma_buffer, buffer_size);
- if (err < 0) {
- trace_dai_error("ep1");
- trace_error_value(source_config->periods_sink);
- trace_error_value(dd->period_bytes);
- trace_error_value(buffer_size);
- trace_error_value(dma_buffer->alloc_size);
- return err;
- }
-
- if (list_is_empty(&config->elem_list)) {
- /* set up cyclic list of DMA elems */
- for (i = 0; i < source_config->periods_sink; i++) {
-
- elem = rzalloc(RZONE_RUNTIME, SOF_MEM_CAPS_RAM,
- sizeof(*elem));
- if (elem == NULL)
- goto err_unwind;
-
- elem->size = dd->period_bytes;
- elem->src = (uintptr_t)(dma_buffer->r_ptr) +
- i * dd->period_bytes;
-
- elem->dest = dai_fifo(dd->dai, SOF_IPC_STREAM_PLAYBACK);
-
- list_item_append(&elem->list, &config->elem_list);
- }
- }
-
- return 0;
-
-err_unwind:
- trace_dai_error("ep3");
- list_for_item_safe(elist, tlist, &config->elem_list) {
- elem = container_of(elist, struct dma_sg_elem, list);
- list_item_del(&elem->list);
- rfree(elem);
- }
- return -ENOMEM;
-}
-
-static int dai_capture_params(struct comp_dev *dev)
-{
- struct dai_data *dd = comp_get_drvdata(dev);
- struct dma_sg_config *config = &dd->config;
- struct sof_ipc_comp_config *sink_config;
- struct dma_sg_elem *elem;
- struct comp_buffer *dma_buffer;
- struct list_item *elist;
- struct list_item *tlist;
- int i;
- int err;
- uint32_t buffer_size;
-
- /* set up DMA configuration */
- config->direction = DMA_DIR_DEV_TO_MEM;
- config->src_width = comp_sample_bytes(dev);
- config->dest_width = comp_sample_bytes(dev);
- config->cyclic = 1;
- config->src_dev = dd->dai->plat_data.fifo[1].handshake;
-
- /* set up local and host DMA elems to reset values */
- dma_buffer = list_first_item(&dev->bsink_list,
- struct comp_buffer, source_list);
- sink_config = COMP_GET_CONFIG(dma_buffer->sink);
- buffer_size = sink_config->periods_source * dd->period_bytes;
-
- /* resize the buffer if space is available to align with period size */
- err = buffer_set_size(dma_buffer, buffer_size);
- if (err < 0) {
- trace_dai_error("ec1");
- trace_error_value(sink_config->periods_sink);
- trace_error_value(dd->period_bytes);
- trace_error_value(buffer_size);
- trace_error_value(dma_buffer->alloc_size);
- return err;
- }
-
- if (list_is_empty(&config->elem_list)) {
- /* set up cyclic list of DMA elems */
- for (i = 0; i < sink_config->periods_source; i++) {
-
- elem = rzalloc(RZONE_RUNTIME, SOF_MEM_CAPS_RAM,
- sizeof(*elem));
- if (elem == NULL)
- goto err_unwind;
-
- elem->size = dd->period_bytes;
- elem->dest = (uintptr_t)(dma_buffer->w_ptr) +
- i * dd->period_bytes;
- elem->src = dai_fifo(dd->dai, SOF_IPC_STREAM_CAPTURE);
- list_item_append(&elem->list, &config->elem_list);
- }
- }
-
- return 0;
-
-err_unwind:
- trace_dai_error("ec3");
- list_for_item_safe(elist, tlist, &config->elem_list) {
- elem = container_of(elist, struct dma_sg_elem, list);
- list_item_del(&elem->list);
- rfree(elem);
- }
- return -ENOMEM;
-}
-
-static int dai_params(struct comp_dev *dev)
-{
- struct dai_data *dd = comp_get_drvdata(dev);
- struct comp_buffer *dma_buffer;
- struct sof_ipc_comp_config *dconfig = COMP_GET_CONFIG(dev);
-
- trace_dai("par");
-
- /* can set params on only init state */
- if (dev->state != COMP_STATE_READY) {
- trace_dai_error("wdp");
- return -EINVAL;
- }
-
- /* get DMA channel, once the stream_tag is known */
- dd->chan = dma_channel_get(dd->dma, dev->params.stream_tag);
- if (dd->chan < 0) {
- trace_dai_error("eDc");
- return -EINVAL;
- }
-
- /* set up callback */
- dma_set_cb(dd->dma, dd->chan, DMA_IRQ_TYPE_BLOCK |
- DMA_IRQ_TYPE_LLIST, dai_dma_cb, dev);
- dev->is_dma_connected = 1;
-
- /* for DAI, we should configure its frame_fmt from topology */
- dev->params.frame_fmt = dconfig->frame_fmt;
-
- /* calculate period size based on config */
- dev->frame_bytes = comp_frame_bytes(dev);
- if (dev->frame_bytes == 0) {
- trace_dai_error("ed1");
- return -EINVAL;
- }
-
- dd->period_bytes = dev->frames * dev->frame_bytes;
- if (dd->period_bytes == 0) {
- trace_dai_error("ed2");
- return -EINVAL;
- }
-
- if (dev->params.direction == SOF_IPC_STREAM_PLAYBACK) {
- dma_buffer = list_first_item(&dev->bsource_list,
- struct comp_buffer, sink_list);
- dma_buffer->r_ptr = dma_buffer->addr;
-
- return dai_playback_params(dev);
- } else {
- dma_buffer = list_first_item(&dev->bsink_list,
- struct comp_buffer, source_list);
- dma_buffer->w_ptr = dma_buffer->addr;
-
- return dai_capture_params(dev);
- }
-}
-
-static int dai_prepare(struct comp_dev *dev)
-{
- struct dai_data *dd = comp_get_drvdata(dev);
- struct comp_buffer *dma_buffer;
- int ret = 0;
-
- trace_dai("pre");
-
- ret = comp_set_state(dev, COMP_TRIGGER_PREPARE);
- if (ret < 0)
- return ret;
-
- dev->position = 0;
-
- if (list_is_empty(&dd->config.elem_list)) {
- trace_dai_error("wdm");
- comp_set_state(dev, COMP_TRIGGER_RESET);
- return -EINVAL;
- }
-
- /* initialise buffers */
- if (dev->params.direction == SOF_IPC_STREAM_PLAYBACK) {
- dma_buffer = list_first_item(&dev->bsource_list,
- struct comp_buffer, sink_list);
- } else {
- dma_buffer = list_first_item(&dev->bsink_list,
- struct comp_buffer, source_list);
- }
-
- /* TODO: not sure what this wb is for? */
- /* write back buffer contents from cache */
- dcache_writeback_region(dma_buffer->addr, dma_buffer->size);
-
- dd->pointer_init = 0;
-
- /* dma reconfig not required if XRUN handling */
- if (dd->xrun) {
- /* after prepare, we have recovered from xrun */
- dd->xrun = 0;
- return ret;
- }
-
- ret = dma_set_config(dd->dma, dd->chan, &dd->config);
- if (ret < 0)
- comp_set_state(dev, COMP_TRIGGER_RESET);
-
- return ret;
-}
-
-static int dai_reset(struct comp_dev *dev)
-{
- struct dai_data *dd = comp_get_drvdata(dev);
- struct dma_sg_config *config = &dd->config;
- struct list_item *elist;
- struct list_item *tlist;
- struct dma_sg_elem *elem;
-
- trace_dai("res");
-
- dma_channel_put(dd->dma, dd->chan);
-
- list_for_item_safe(elist, tlist, &config->elem_list) {
- elem = container_of(elist, struct dma_sg_elem, list);
- list_item_del(&elem->list);
- rfree(elem);
- }
-
- dd->dai_pos_blks = 0;
- if (dd->dai_pos)
- *dd->dai_pos = 0;
- dd->dai_pos = NULL;
- dd->last_bytes = 0;
- dd->wallclock = 0;
- dev->position = 0;
- dd->xrun = 0;
- dd->pointer_init = 0;
- comp_set_state(dev, COMP_TRIGGER_RESET);
-
- return 0;
-}
-
-/* The playback source pipeline must be advanced by one period so that it
- * does not write to the period that DMA is reading. The configuration of the
- * upstream pipeline is unknown to the DAI but we can check if the source buffer
- * is shared with another DMA engine (which preloads the buffer by one period)
- * and only advance the write pointer when source component is not another
- * DMA engine.
- */
-static void dai_pointer_init(struct comp_dev *dev)
-{
- struct comp_buffer *dma_buffer;
- struct dai_data *dd = comp_get_drvdata(dev);
-
- dd->pointer_init = DAI_PTR_INIT_DAI;
-
- /* not required for capture streams */
- if (dev->params.direction == SOF_IPC_STREAM_PLAYBACK) {
- dma_buffer = list_first_item(&dev->bsource_list,
- struct comp_buffer, sink_list);
-
- switch (dma_buffer->source->comp.type) {
- case SOF_COMP_HOST:
- case SOF_COMP_SG_HOST:
- /* buffer is preloaded and advanced by host DMA engine */
- dd->pointer_init = DAI_PTR_INIT_HOST;
- break;
- default:
- /* advance source pipeline w_ptr by one period
- * this places pipeline w_ptr in period before DAI r_ptr */
- comp_update_buffer_produce(dma_buffer, dd->period_bytes);
- break;
- }
- }
-}
-
-/* used to pass standard and bespoke command (with data) to component */
-static int dai_comp_trigger(struct comp_dev *dev, int cmd)
-{
- struct dai_data *dd = comp_get_drvdata(dev);
- int ret;
-
- trace_dai("trg");
- tracev_value(cmd);
-
- wait_init(&dd->complete);
-
- ret = comp_set_state(dev, cmd);
- if (ret < 0)
- return ret;
-
- switch (cmd) {
- case COMP_TRIGGER_START:
- trace_dai("tsa");
- if (!dd->pointer_init)
- dai_pointer_init(dev);
- /* only start the DAI if we are not XRUN handling
- * and the ptr is not initialized by the host as in this
- * case start is deferred to the first copy call as the buffer
- * is populated by the host only then
- */
- if (dd->xrun == 0 && dd->pointer_init != DAI_PTR_INIT_HOST) {
- /* start the DAI */
- ret = dma_start(dd->dma, dd->chan);
- if (ret < 0)
- return ret;
- dai_trigger(dd->dai, cmd, dev->params.direction);
- } else {
- dd->xrun = 0;
- }
-
- /* update starting wallclock */
- platform_dai_wallclock(dev, &dd->wallclock);
- break;
- case COMP_TRIGGER_RELEASE:
- /* before release, we clear the buffer data to 0s,
- * then there is no history data sent out after release.
- * this is only supported at capture mode.
- */
- if (dev->params.direction == SOF_IPC_STREAM_CAPTURE) {
- struct comp_buffer *dma_buffer =
- list_first_item(&dev->bsink_list,
- struct comp_buffer, source_list);
- buffer_zero(dma_buffer);
- }
-
- /* only start the DAI if we are not XRUN handling */
- if (dd->xrun == 0) {
- /* start the DAI */
- ret = dma_start(dd->dma, dd->chan);
- if (ret < 0)
- return ret;
- dai_trigger(dd->dai, cmd, dev->params.direction);
- } else {
- dd->xrun = 0;
- }
-
- /* update starting wallclock */
- platform_dai_wallclock(dev, &dd->wallclock);
- break;
- case COMP_TRIGGER_XRUN:
- trace_dai("txr");
- dd->xrun = 1;
- /* stop the DAI unconditionally */
- dai_trigger(dd->dai, COMP_TRIGGER_STOP, dev->params.direction);
- ret = dma_stop(dd->dma, dd->chan);
- break;
- case COMP_TRIGGER_PAUSE:
- case COMP_TRIGGER_STOP:
- trace_dai("tsp");
- wait_init(&dd->complete);
-
- /* wait for DMA to complete */
- dd->complete.timeout = dev->pipeline->ipc_pipe.deadline;
- ret = wait_for_completion_timeout(&dd->complete);
- if (ret < 0) {
- trace_dai_error("ed0");
- trace_error_value(cmd);
- /* forced stop of DMA+DAI to avoid refcount issues */
- dai_trigger(dd->dai, COMP_TRIGGER_STOP,
- dev->params.direction);
- ret = dma_stop(dd->dma, dd->chan);
- }
- break;
- default:
- break;
- }
-
- return ret;
-}
-
-/* copy and process stream data from source to sink buffers */
-static int dai_copy(struct comp_dev *dev)
-{
- struct dai_data *dd = comp_get_drvdata(dev);
- int ret;
-
- if (dd->pointer_init == DAI_PTR_INIT_HOST) {
- /* start the DAI */
- ret = dma_start(dd->dma, dd->chan);
- if (ret < 0)
- return ret;
- dai_trigger(dd->dai, COMP_TRIGGER_START, dev->params.direction);
- dd->pointer_init = DAI_PTR_INIT_DAI; /* next copy just quits */
- platform_dai_wallclock(dev, &dd->wallclock);
- }
- return 0;
-}
-
-static int dai_position(struct comp_dev *dev, struct sof_ipc_stream_posn *posn)
-{
- struct dai_data *dd = comp_get_drvdata(dev);
-
- /* TODO: improve accuracy by adding current DMA position */
- posn->dai_posn = dev->position;
-
- /* set stream start wallclock */
- posn->wallclock = dd->wallclock;
-
- return 0;
-}
-
-static int dai_config(struct comp_dev *dev, struct sof_ipc_dai_config *config)
-{
- struct dai_data *dd = comp_get_drvdata(dev);
-
- switch (config->type) {
- case SOF_DAI_INTEL_SSP:
- /* set dma burst elems to slot number */
- dd->config.burst_elems = config->ssp.tdm_slots;
-
- /* calc frame bytes */
- switch (config->ssp.sample_valid_bits) {
- case 16:
- dev->frame_bytes = 2 * config->ssp.tdm_slots;
- break;
- case 17 ... 32:
- dev->frame_bytes = 4 * config->ssp.tdm_slots;
- break;
- default:
- break;
- }
- break;
- case SOF_DAI_INTEL_DMIC:
- /* The frame bytes setting follows only FIFO A setting in
- * this DMIC driver version.
- */
- trace_dai("did");
-
- /* We can use always the largest burst length. */
- dd->config.burst_elems = 8;
-
- /* Set frame size in bytes to match the configuration. */
- if (config->dmic.num_pdm_active > 1) {
- /* For two or more controllers capture from each
- * controller must be stereo.
- */
- dev->frame_bytes = 2 * config->dmic.num_pdm_active *
- config->dmic.fifo_bits_a >> 3;
- } else {
- /* For one controller the capture can be mono or
- * stereo. In mono configuration only one of mic A or B
- * is enabled.
- */
- if (config->dmic.pdm[0].enable_mic_a +
- config->dmic.pdm[0].enable_mic_b == 1)
- dev->frame_bytes =
- config->dmic.fifo_bits_a >> 3;
- else
- dev->frame_bytes = 2 *
- config->dmic.fifo_bits_a >> 3;
- }
- trace_value(config->dmic.fifo_bits_a);
- trace_value(config->dmic.num_pdm_active);
- trace_value(config->dmic.pdm[0].enable_mic_a);
- trace_value(config->dmic.pdm[0].enable_mic_b);
- trace_value(dev->frame_bytes);
- break;
- case SOF_DAI_INTEL_HDA:
- /* set to some non-zero value to satisfy the condition below,
- * it is recalculated in dai_params() later
- * this is temp until dai/hda model is changed.
- */
- dev->frame_bytes = 4;
- break;
- default:
- /* other types of DAIs not handled for now */
- trace_dai_error("de2");
- break;
- }
-
- if (dev->frame_bytes == 0) {
- trace_dai_error("de1");
- return -EINVAL;
- }
-
- return 0;
-}
-
-static struct comp_driver comp_dai = {
- .type = SOF_COMP_DAI,
- .ops = {
- .new = dai_new,
- .free = dai_free,
- .params = dai_params,
- .trigger = dai_comp_trigger,
- .copy = dai_copy,
- .prepare = dai_prepare,
- .reset = dai_reset,
- .dai_config = dai_config,
- .position = dai_position,
- },
-};
-
-void sys_comp_dai_init(void)
-{
- comp_register(&comp_dai);
-}
diff --git a/src/audio/eq_fir.c b/src/audio/eq_fir.c
deleted file mode 100644
index b31b561..0000000
--- a/src/audio/eq_fir.c
+++ /dev/null
@@ -1,607 +0,0 @@
-/*
- * Copyright (c) 2017, Intel Corporation
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- * * Redistributions of source code must retain the above copyright
- * notice, this list of conditions and the following disclaimer.
- * * Redistributions in binary form must reproduce the above copyright
- * notice, this list of conditions and the following disclaimer in the
- * documentation and/or other materials provided with the distribution.
- * * Neither the name of the Intel Corporation nor the
- * names of its contributors may be used to endorse or promote products
- * derived from this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
- * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
- * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
- * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
- * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
- * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
- * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
- * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
- * POSSIBILITY OF SUCH DAMAGE.
- *
- * Author: Seppo Ingalsuo <seppo.ingalsuo@linux.intel.com>
- * Liam Girdwood <liam.r.girdwood@linux.intel.com>
- * Keyon Jie <yang.jie@linux.intel.com>
- */
-
-#include <stdbool.h>
-#include <sof/sof.h>
-#include <sof/audio/component.h>
-#include <uapi/eq.h>
-#include "fir_config.h"
-
-#if FIR_GENERIC
-#include "fir.h"
-#endif
-
-#if FIR_HIFIEP
-#include "fir_hifi2ep.h"
-#endif
-
-#if FIR_HIFI3
-#include "fir_hifi3.h"
-#endif
-
-#ifdef MODULE_TEST
-#include <stdio.h>
-#endif
-
-#define trace_eq(__e) trace_event(TRACE_CLASS_EQ_FIR, __e)
-#define tracev_eq(__e) tracev_event(TRACE_CLASS_EQ_FIR, __e)
-#define trace_eq_error(__e) trace_error(TRACE_CLASS_EQ_FIR, __e)
-
-/* src component private data */
-struct comp_data {
- struct fir_state_32x16 fir[PLATFORM_MAX_CHANNELS];
- struct sof_eq_fir_config *config;
- uint32_t period_bytes;
- void (*eq_fir_func)(struct fir_state_32x16 fir[],
- struct comp_buffer *source,
- struct comp_buffer *sink,
- int frames, int nch);
- void (*eq_fir_func_odd)(struct fir_state_32x16 fir[],
- struct comp_buffer *source,
- struct comp_buffer *sink,
- int frames, int nch);
-};
-
-static void eq_fir_passthrough(struct fir_state_32x16 fir[],
- struct comp_buffer *source,
- struct comp_buffer *sink,
- int frames, int nch)
-{
- int32_t *src = (int32_t *)source->r_ptr;
- int32_t *dest = (int32_t *)sink->w_ptr;
- int n = frames * nch;
-
- memcpy(dest, src, n * sizeof(int32_t));
-}
-
-/*
- * EQ control code is next. The processing is in fir_ C modules.
- */
-
-static void eq_fir_free_parameters(struct sof_eq_fir_config **config)
-{
- if (*config)
- rfree(*config);
-
- *config = NULL;
-}
-
-static void eq_fir_clear_delaylines(struct fir_state_32x16 fir[])
-{
- int i = 0;
-
- /* 1st active EQ data is at beginning of the single allocated buffer */
- for (i = 0; i < PLATFORM_MAX_CHANNELS; i++) {
- if (fir[i].delay) {
- memset(fir[i].delay, 0,
- fir[i].length * sizeof(int32_t));
- }
- }
-}
-
-static void eq_fir_free_delaylines(struct fir_state_32x16 fir[])
-{
- int i = 0;
- int32_t *data = NULL;
-
- /* 1st active EQ data is at beginning of the single allocated buffer */
- for (i = 0; i < PLATFORM_MAX_CHANNELS; i++) {
- if (fir[i].delay && !data)
- data = (int32_t *)fir[i].delay;
-
- /* Set all to NULL to avoid duplicated free later */
- fir[i].delay = NULL;
- }
-
- if (data) {
- trace_eq("fr1");
- trace_value((uint32_t)data);
-
- rfree(data);
-
- trace_eq("fr2");
- }
-}
-
-static int eq_fir_setup(struct fir_state_32x16 fir[],
- struct sof_eq_fir_config *config, int nch)
-{
- int i;
- int j;
- int idx;
- int length;
- int resp;
- int32_t *fir_data;
- int16_t *coef_data, *assign_response;
- int response_index[PLATFORM_MAX_CHANNELS];
- int length_sum = 0;
-
- trace_eq("fse");
- trace_value(config->channels_in_config);
- trace_value(config->number_of_responses);
- if (nch > PLATFORM_MAX_CHANNELS ||
- config->channels_in_config > PLATFORM_MAX_CHANNELS) {
- trace_eq_error("ech");
- return -EINVAL;
- }
-
- /* Collect index of respose start positions in all_coefficients[] */
- j = 0;
- assign_response = &config->data[0];
- coef_data = &config->data[config->channels_in_config];
- trace_eq("idx");
- for (i = 0; i < PLATFORM_MAX_CHANNELS; i++) {
- if (i < config->number_of_responses) {
- response_index[i] = j;
- trace_value(j);
- j += SOF_EQ_FIR_COEF_NHEADER + coef_data[j];
- } else {
- response_index[i] = 0;
- }
- }
-
- /* Free existing FIR channels data if it was allocated */
- eq_fir_free_delaylines(fir);
-
- /* Initialize 1st phase */
- trace_eq("asr");
- for (i = 0; i < nch; i++) {
- /* If the configuration blob contains less channels for
- * response assign to channels than the current channels count
- * use the first channel response to remaining channels. E.g.
- * a blob that contains just a mono EQ can be used for stereo
- * stream by using the same response for all channels.
- */
- if (i < config->channels_in_config)
- resp = assign_response[i];
- else
- resp = assign_response[0];
-
- trace_value(resp);
- if (resp >= config->number_of_responses || resp < 0) {
- trace_eq_error("eas");
- trace_value(resp);
- return -EINVAL;
- }
-
- /* Initialize EQ coefficients. Each channel EQ returns the
- * number of samples it needs to store into the delay line. The
- * sum is used to allocate storate for all EQs.
- */
- idx = response_index[resp];
- length = fir_init_coef(&fir[i], &coef_data[idx]);
- if (length > 0) {
- length_sum += length;
- } else {
- trace_eq_error("ecl");
- trace_value(length);
- return -EINVAL;
- }
- }
-
- trace_eq("all");
- /* Allocate all FIR channels data in a big chunk and clear it */
- fir_data = rballoc(RZONE_SYS, SOF_MEM_CAPS_RAM,
- length_sum * sizeof(int32_t));
- if (!fir_data)
- return -ENOMEM;
-
- memset(fir_data, 0, length_sum * sizeof(int32_t));
-
- /* Initialize 2nd phase to set EQ delay lines pointers */
- trace_eq("ini");
- for (i = 0; i < nch; i++) {
- resp = assign_response[i];
- if (resp >= 0) {
- trace_value((uint32_t)fir_data);
- trace_value(fir->length);
- fir_init_delay(&fir[i], &fir_data);
- }
- }
-
- return 0;
-}
-
-static int eq_fir_switch_response(struct fir_state_32x16 fir[],
- struct sof_eq_fir_config *config, uint32_t ch, int32_t response)
-{
- int ret;
-
- /* Copy assign response from update and re-initialize EQ */
- if (!config || ch >= PLATFORM_MAX_CHANNELS)
- return -EINVAL;
-
- config->data[ch] = response;
- ret = eq_fir_setup(fir, config, PLATFORM_MAX_CHANNELS);
-
- return ret;
-}
-
-/*
- * End of algorithm code. Next the standard component methods.
- */
-
-static struct comp_dev *eq_fir_new(struct sof_ipc_comp *comp)
-{
- struct comp_dev *dev;
- struct sof_ipc_comp_eq_fir *eq_fir;
- struct sof_ipc_comp_eq_fir *ipc_eq_fir
- = (struct sof_ipc_comp_eq_fir *)comp;
- struct comp_data *cd;
- int i;
-
- trace_eq("new");
-
- dev = rzalloc(RZONE_RUNTIME, SOF_MEM_CAPS_RAM,
- COMP_SIZE(struct sof_ipc_comp_eq_fir));
- if (!dev)
- return NULL;
-
- eq_fir = (struct sof_ipc_comp_eq_fir *)&dev->comp;
- memcpy(eq_fir, ipc_eq_fir, sizeof(struct sof_ipc_comp_eq_fir));
-
- cd = rzalloc(RZONE_RUNTIME, SOF_MEM_CAPS_RAM, sizeof(*cd));
- if (!cd) {
- rfree(dev);
- return NULL;
- }
-
- comp_set_drvdata(dev, cd);
-
- cd->eq_fir_func = eq_fir_passthrough;
- cd->eq_fir_func_odd = eq_fir_passthrough;
- cd->config = NULL;
- for (i = 0; i < PLATFORM_MAX_CHANNELS; i++)
- fir_reset(&cd->fir[i]);
-
- dev->state = COMP_STATE_READY;
- return dev;
-}
-
-static void eq_fir_free(struct comp_dev *dev)
-{
- struct comp_data *cd = comp_get_drvdata(dev);
-
- trace_eq("fre");
-
- eq_fir_free_delaylines(cd->fir);
- eq_fir_free_parameters(&cd->config);
-
- rfree(cd);
- rfree(dev);
-}
-
-/* set component audio stream parameters */
-static int eq_fir_params(struct comp_dev *dev)
-{
- struct sof_ipc_comp_config *config = COMP_GET_CONFIG(dev);
- struct comp_data *cd = comp_get_drvdata(dev);
- struct comp_buffer *sink;
- int err;
-
- trace_eq("par");
-
- /* Calculate period size based on config. First make sure that
- * frame_bytes is set.
- */
- dev->frame_bytes =
- dev->params.sample_container_bytes * dev->params.channels;
- cd->period_bytes = dev->frames * dev->frame_bytes;
-
- /* configure downstream buffer */
- sink = list_first_item(&dev->bsink_list,
- struct comp_buffer, source_list);
- err = buffer_set_size(sink, cd->period_bytes * config->periods_sink);
- if (err < 0) {
- trace_eq_error("eSz");
- return err;
- }
-
- /* EQ supports only S32_LE PCM format */
- if (config->frame_fmt != SOF_IPC_FRAME_S32_LE)
- return -EINVAL;
-
- return 0;
-}
-
-static int fir_cmd_get_data(struct comp_dev *dev,
- struct sof_ipc_ctrl_data *cdata)
-{
- struct comp_data *cd = comp_get_drvdata(dev);
-
- size_t bs;
- int ret = 0;
-
- switch (cdata->cmd) {
- case SOF_CTRL_CMD_BINARY:
- trace_eq("gbi");
-
- struct sof_eq_fir_config *cfg =
- (struct sof_eq_fir_config *)cdata->data->data;
-
- /* Copy back to user space */
- bs = cfg->size;
- if (bs > SOF_EQ_FIR_MAX_SIZE || bs < 1)
- return -EINVAL;
- if (!cd->config) {
- cd->config = rzalloc(RZONE_RUNTIME,
- SOF_MEM_CAPS_RAM,
- bs);
-
- if (!cd->config)
- return -ENOMEM;
-
- memcpy(cdata->data->data, cd->config, bs);
- }
- break;
- default:
- trace_eq_error("egt");
- ret = -EINVAL;
- break;
- }
- return ret;
-}
-
-static int fir_cmd_set_data(struct comp_dev *dev,
- struct sof_ipc_ctrl_data *cdata)
-{
- struct comp_data *cd = comp_get_drvdata(dev);
- struct sof_ipc_ctrl_value_comp *compv;
- struct sof_eq_fir_config *cfg;
- size_t bs;
- int i;
- int ret = 0;
-
- /* TODO: determine if data is DMAed or appended to cdata */
-
- /* Check version from ABI header */
- if (cdata->data->comp_abi != SOF_EQ_FIR_ABI_VERSION) {
- trace_eq_error("eab");
- return -EINVAL;
- }
-
- switch (cdata->cmd) {
- case SOF_CTRL_CMD_ENUM:
- trace_eq("snu");
- compv = (struct sof_ipc_ctrl_value_comp *)cdata->data->data;
- if (cdata->index == SOF_EQ_FIR_IDX_SWITCH) {
- trace_eq("fsw");
- for (i = 0; i < (int)cdata->num_elems; i++) {
- tracev_value(compv[i].index);
- tracev_value(compv[i].svalue);
- ret = eq_fir_switch_response(cd->fir,
- cd->config,
- compv[i].index,
- compv[i].svalue);
- if (ret < 0) {
- trace_eq_error("esw");
- return -EINVAL;
- }
- }
- } else {
- trace_eq_error("enu");
- trace_error_value(cdata->index);
- return -EINVAL;
- }
- break;
- case SOF_CTRL_CMD_BINARY:
- trace_eq("sbi");
-
- /* Check and free old config */
- eq_fir_free_parameters(&cd->config);
-
- /* Copy new config, find size from header */
- if (!cdata->data->data) {
- trace_eq_error("edn");
- return -EINVAL;
- }
-
- cfg = (struct sof_eq_fir_config *)cdata->data->data;
- bs = cfg->size;
- trace_value(bs);
- if (bs > SOF_EQ_FIR_MAX_SIZE || bs < 1)
- return -EINVAL;
-
- cd->config = rzalloc(RZONE_RUNTIME, SOF_MEM_CAPS_RAM, bs);
- if (!cd->config)
- return -EINVAL;
-
- memcpy(cd->config, cdata->data->data, bs);
- ret = eq_fir_setup(cd->fir, cd->config, PLATFORM_MAX_CHANNELS);
- if (ret == 0) {
-#if 1
-#if FIR_GENERIC
- cd->eq_fir_func = eq_fir_s32;
- cd->eq_fir_func_odd = eq_fir_s32;
-#endif
-#if FIR_HIFIEP
- cd->eq_fir_func = eq_fir_2x_s32_hifiep;
- cd->eq_fir_func_odd = eq_fir_s32_hifiep;
-#endif
-#if FIR_HIFI3
- cd->eq_fir_func = eq_fir_2x_s32_hifi3;
- cd->eq_fir_func_odd = eq_fir_s32_hifi3;
-#endif
-#endif
- trace_eq("fok");
- } else {
- cd->eq_fir_func = eq_fir_passthrough;
- cd->eq_fir_func_odd = eq_fir_passthrough;
- trace_eq_error("ept");
- return -EINVAL;
- }
- break;
- default:
- trace_eq_error("ecm");
- ret = -EINVAL;
- break;
- }
-
- return ret;
-}
-
-/* used to pass standard and bespoke commands (with data) to component */
-static int eq_fir_cmd(struct comp_dev *dev, int cmd, void *data)
-{
- struct sof_ipc_ctrl_data *cdata = data;
- int ret = 0;
-
- trace_eq("cmd");
-
- switch (cmd) {
- case COMP_CMD_SET_DATA:
- ret = fir_cmd_set_data(dev, cdata);
- break;
- case COMP_CMD_GET_DATA:
- ret = fir_cmd_get_data(dev, cdata);
- break;
- }
-
- return ret;
-}
-
-static int eq_fir_trigger(struct comp_dev *dev, int cmd)
-{
- trace_eq("trg");
-
- return comp_set_state(dev, cmd);
-}
-
-/* copy and process stream data from source to sink buffers */
-static int eq_fir_copy(struct comp_dev *dev)
-{
- struct comp_data *sd = comp_get_drvdata(dev);
- struct comp_buffer *source;
- struct comp_buffer *sink;
- int res;
- int nch = dev->params.channels;
- struct fir_state_32x16 *fir = sd->fir;
-
- tracev_comp("fcp");
-
- /* get source and sink buffers */
- source = list_first_item(&dev->bsource_list, struct comp_buffer,
- sink_list);
- sink = list_first_item(&dev->bsink_list, struct comp_buffer,
- source_list);
-
- /* make sure source component buffer has enough data available and that
- * the sink component buffer has enough free bytes for copy. Also
- * check for XRUNs.
- */
- res = comp_buffer_can_copy_bytes(source, sink, sd->period_bytes);
- if (res) {
- trace_eq_error("xrn");
- return -EIO; /* xrun */
- }
-
- if (dev->frames & 1)
- sd->eq_fir_func_odd(fir, source, sink, dev->frames, nch);
- else
- sd->eq_fir_func(fir, source, sink, dev->frames, nch);
-
- /* calc new free and available */
- comp_update_buffer_consume(source, sd->period_bytes);
- comp_update_buffer_produce(sink, sd->period_bytes);
-
- return dev->frames;
-}
-
-static int eq_fir_prepare(struct comp_dev *dev)
-{
- struct comp_data *cd = comp_get_drvdata(dev);
- int ret;
-
- trace_eq("pre");
-
- ret = comp_set_state(dev, COMP_TRIGGER_PREPARE);
- if (ret < 0)
- return ret;
-
- /* Initialize EQ */
- cd->eq_fir_func = eq_fir_passthrough;
- if (cd->config) {
- ret = eq_fir_setup(cd->fir, cd->config, dev->params.channels);
- if (ret < 0) {
- comp_set_state(dev, COMP_TRIGGER_RESET);
- return ret;
- }
-#if FIR_GENERIC
- cd->eq_fir_func = eq_fir_s32;
- cd->eq_fir_func_odd = eq_fir_s32;
-#endif
-#if FIR_HIFIEP
- cd->eq_fir_func = eq_fir_2x_s32_hifiep;
- cd->eq_fir_func_odd = eq_fir_s32_hifiep;
-#endif
-#if FIR_HIFI3
- cd->eq_fir_func = eq_fir_2x_s32_hifi3;
- cd->eq_fir_func_odd = eq_fir_s32_hifi3;
-#endif
- }
- trace_eq("len");
- trace_value(cd->fir[0].length);
- trace_value(cd->fir[1].length);
-
- return 0;
-}
-
-static int eq_fir_reset(struct comp_dev *dev)
-{
- struct comp_data *cd = comp_get_drvdata(dev);
-
- trace_eq("res");
-
- eq_fir_clear_delaylines(cd->fir);
-
- comp_set_state(dev, COMP_TRIGGER_RESET);
- return 0;
-}
-
-struct comp_driver comp_eq_fir = {
- .type = SOF_COMP_EQ_FIR,
- .ops = {
- .new = eq_fir_new,
- .free = eq_fir_free,
- .params = eq_fir_params,
- .cmd = eq_fir_cmd,
- .trigger = eq_fir_trigger,
- .copy = eq_fir_copy,
- .prepare = eq_fir_prepare,
- .reset = eq_fir_reset,
- },
-};
-
-void sys_comp_eq_fir_init(void)
-{
- comp_register(&comp_eq_fir);
-}
diff --git a/src/audio/eq_iir.c b/src/audio/eq_iir.c
deleted file mode 100644
index b874518..0000000
--- a/src/audio/eq_iir.c
+++ /dev/null
@@ -1,546 +0,0 @@
-/*
- * Copyright (c) 2017, Intel Corporation
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- * * Redistributions of source code must retain the above copyright
- * notice, this list of conditions and the following disclaimer.
- * * Redistributions in binary form must reproduce the above copyright
- * notice, this list of conditions and the following disclaimer in the
- * documentation and/or other materials provided with the distribution.
- * * Neither the name of the Intel Corporation nor the
- * names of its contributors may be used to endorse or promote products
- * derived from this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
- * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
- * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
- * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
- * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
- * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
- * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
- * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
- * POSSIBILITY OF SUCH DAMAGE.
- *
- * Author: Seppo Ingalsuo <seppo.ingalsuo@linux.intel.com>
- * Liam Girdwood <liam.r.girdwood@linux.intel.com>
- * Keyon Jie <yang.jie@linux.intel.com>
- */
-
-#include <stdint.h>
-#include <stddef.h>
-#include <errno.h>
-#include <stdbool.h>
-#include <sof/sof.h>
-#include <sof/lock.h>
-#include <sof/list.h>
-#include <sof/stream.h>
-#include <sof/alloc.h>
-#include <sof/work.h>
-#include <sof/clock.h>
-#include <sof/audio/component.h>
-#include <sof/audio/pipeline.h>
-#include <sof/audio/format.h>
-#include <uapi/ipc.h>
-#include <uapi/eq.h>
-#include "eq_iir.h"
-#include "iir.h"
-
-#ifdef MODULE_TEST
-#include <stdio.h>
-#endif
-
-#define trace_eq_iir(__e) trace_event(TRACE_CLASS_EQ_IIR, __e)
-#define tracev_eq_iir(__e) tracev_event(TRACE_CLASS_EQ_IIR, __e)
-#define trace_eq_iir_error(__e) trace_error(TRACE_CLASS_EQ_IIR, __e)
-
-/* src component private data */
-struct comp_data {
- struct sof_eq_iir_config *config;
- uint32_t period_bytes;
- struct iir_state_df2t iir[PLATFORM_MAX_CHANNELS];
- void (*eq_iir_func)(struct comp_dev *dev,
- struct comp_buffer *source,
- struct comp_buffer *sink,
- uint32_t frames);
-};
-
-/*
- * EQ IIR algorithm code
- */
-
-static void eq_iir_s32_default(struct comp_dev *dev,
- struct comp_buffer *source, struct comp_buffer *sink, uint32_t frames)
-{
- struct comp_data *cd = comp_get_drvdata(dev);
- int ch;
- int n;
- int n_wrap_src;
- int n_wrap_snk;
- int n_wrap_min;
- int32_t *src = (int32_t *) source->r_ptr;
- int32_t *snk = (int32_t *) sink->w_ptr;
- int nch = dev->params.channels;
- int32_t *x = src + nch - 1;
- int32_t *y = snk + nch - 1;
-
- for (ch = 0; ch < nch; ch++) {
- n = frames * nch;
- x = src++;
- y = snk++;
- while (n > 0) {
- n_wrap_src = (int32_t *) source->end_addr - x;
- n_wrap_snk = (int32_t *) sink->end_addr - y;
- n_wrap_min = (n_wrap_src < n_wrap_snk) ?
- n_wrap_src : n_wrap_snk;
- if (n < n_wrap_min) {
- /* No circular wrap need */
- while (n > 0) {
- *y = iir_df2t(&cd->iir[ch], *x);
- x += nch;
- y += nch;
- n -= nch;
- }
- } else {
- /* Wrap in n_wrap_min/nch samples */
- while (n_wrap_min > 0) {
- *y = iir_df2t(&cd->iir[ch], *x);
- x += nch;
- y += nch;
- n_wrap_min -= nch;
- n -= nch;
- }
- /* Check both source and destination for wrap */
- if (x > (int32_t *) source->end_addr)
- x = (int32_t *)
- ((size_t) x - source->size);
- if (snk > (int32_t *) sink->end_addr)
- y = (int32_t *)
- ((size_t) y - sink->size);
- }
- }
-
- }
-}
-
-static void eq_iir_free_parameters(struct sof_eq_iir_config **config)
-{
- if (*config != NULL)
- rfree(*config);
-
- *config = NULL;
-}
-
-static void eq_iir_free_delaylines(struct iir_state_df2t *iir)
-{
- int i = 0;
- int64_t *delay = NULL; /* TODO should not need to know the type */
-
- /* 1st active EQ delay line data is at beginning of the single
- * allocated buffer
- */
- for (i = 0; i < PLATFORM_MAX_CHANNELS; i++) {
- if ((iir[i].delay != NULL) && (delay == NULL))
- delay = iir[i].delay;
-
- /* Point all delays to NULL to avoid duplicated free later */
- iir[i].delay = NULL;
- }
-
- if (delay != NULL)
- rfree(delay);
-
-}
-
-static int eq_iir_setup(struct iir_state_df2t iir[],
- struct sof_eq_iir_config *config, int nch)
-{
- int i;
- int j;
- int idx;
- int resp;
- size_t s;
- size_t size_sum = 0;
- int64_t *iir_delay; /* TODO should not need to know the type */
- int32_t *coef_data, *assign_response;
- int response_index[PLATFORM_MAX_CHANNELS];
-
- /* Free existing IIR channels data if it was allocated */
- eq_iir_free_delaylines(iir);
-
- if ((nch > PLATFORM_MAX_CHANNELS)
- || (config->channels_in_config > PLATFORM_MAX_CHANNELS))
- return -EINVAL;
-
- /* Collect index of response start positions in all_coefficients[] */
- j = 0;
- assign_response = &config->data[0];
- coef_data = &config->data[config->channels_in_config];
- for (i = 0; i < PLATFORM_MAX_CHANNELS; i++) {
- if (i < config->number_of_responses) {
- response_index[i] = j;
- j += NHEADER_DF2T
- + NBIQUAD_DF2T * coef_data[j];
- } else {
- response_index[i] = 0;
- }
- }
-
- /* Initialize 1st phase */
- for (i = 0; i < nch; i++) {
- resp = assign_response[i];
- if (resp > config->number_of_responses - 1)
- return -EINVAL;
-
- if (resp < 0) {
- /* Initialize EQ channel to bypass */
- iir_reset_df2t(&iir[i]);
- } else {
- /* Initialize EQ coefficients */
- idx = response_index[resp];
- s = iir_init_coef_df2t(&iir[i], &coef_data[idx]);
- if (s > 0)
- size_sum += s;
- else
- return -EINVAL;
- }
-
- }
-
- /* Allocate all IIR channels data in a big chunk and clear it */
- iir_delay = rzalloc(RZONE_RUNTIME, SOF_MEM_CAPS_RAM, size_sum);
- if (iir_delay == NULL)
- return -ENOMEM;
-
- memset(iir_delay, 0, size_sum);
-
- /* Initialize 2nd phase to set EQ delay lines pointers */
- for (i = 0; i < nch; i++) {
- resp = assign_response[i];
- if (resp >= 0) {
- iir_init_delay_df2t(&iir[i], &iir_delay);
- }
-
- }
-
- return 0;
-}
-
-static int eq_iir_switch_response(struct iir_state_df2t iir[],
- struct sof_eq_iir_config *config, uint32_t ch, int32_t response)
-{
- int ret;
-
- /* Copy assign response from update and re-initialize EQ */
- if ((config == NULL) || (ch >= PLATFORM_MAX_CHANNELS))
- return -EINVAL;
-
- config->data[ch] = response;
- ret = eq_iir_setup(iir, config, PLATFORM_MAX_CHANNELS);
-
- return ret;
-}
-
-/*
- * End of EQ setup code. Next the standard component methods.
- */
-
-static struct comp_dev *eq_iir_new(struct sof_ipc_comp *comp)
-{
- struct comp_dev *dev;
- struct comp_data *cd;
- int i;
-
- trace_eq_iir("new");
-
- dev = rzalloc(RZONE_RUNTIME, SOF_MEM_CAPS_RAM,
- COMP_SIZE(struct sof_ipc_comp_eq_iir));
- if (dev == NULL)
- return NULL;
-
- memcpy(&dev->comp, comp, sizeof(struct sof_ipc_comp_eq_iir));
-
- cd = rzalloc(RZONE_RUNTIME, SOF_MEM_CAPS_RAM, sizeof(*cd));
- if (cd == NULL) {
- rfree(dev);
- return NULL;
- }
-
- comp_set_drvdata(dev, cd);
-
- cd->eq_iir_func = eq_iir_s32_default;
- cd->config = NULL;
- for (i = 0; i < PLATFORM_MAX_CHANNELS; i++)
- iir_reset_df2t(&cd->iir[i]);
-
- dev->state = COMP_STATE_READY;
- return dev;
-}
-
-static void eq_iir_free(struct comp_dev *dev)
-{
- struct comp_data *cd = comp_get_drvdata(dev);
-
- trace_eq_iir("fre");
-
- eq_iir_free_delaylines(cd->iir);
- eq_iir_free_parameters(&cd->config);
-
- rfree(cd);
- rfree(dev);
-}
-
-/* set component audio stream parameters */
-static int eq_iir_params(struct comp_dev *dev)
-{
- struct comp_data *cd = comp_get_drvdata(dev);
- struct sof_ipc_comp_config *config = COMP_GET_CONFIG(dev);
- struct comp_buffer *sink;
- int err;
-
- trace_eq_iir("par");
-
- /* Calculate period size based on config. First make sure that
- * frame_bytes is set.
- */
- dev->frame_bytes =
- dev->params.sample_container_bytes * dev->params.channels;
- cd->period_bytes = dev->frames * dev->frame_bytes;
-
- /* configure downstream buffer */
- sink = list_first_item(&dev->bsink_list, struct comp_buffer, source_list);
- err = buffer_set_size(sink, cd->period_bytes * config->periods_sink);
- if (err < 0) {
- trace_eq_iir_error("eSz");
- return err;
- }
-
- /* EQ supports only S32_LE PCM format */
- if (config->frame_fmt != SOF_IPC_FRAME_S32_LE)
- return -EINVAL;
-
- return 0;
-}
-
-static int iir_cmd_set_value(struct comp_dev *dev, struct sof_ipc_ctrl_data *cdata)
-{
- struct comp_data *cd = comp_get_drvdata(dev);
- int j;
- uint32_t ch;
- bool val;
-
- if (cdata->cmd == SOF_CTRL_CMD_SWITCH) {
- trace_eq_iir("mst");
- for (j = 0; j < cdata->num_elems; j++) {
- ch = cdata->chanv[j].channel;
- val = cdata->chanv[j].value;
- tracev_value(ch);
- tracev_value(val);
- if (ch >= PLATFORM_MAX_CHANNELS) {
- trace_eq_iir_error("che");
- return -EINVAL;
- }
- if (val)
- iir_unmute_df2t(&cd->iir[ch]);
- else
- iir_mute_df2t(&cd->iir[ch]);
- }
- } else {
- trace_eq_iir_error("ste");
- return -EINVAL;
- }
-
- return 0;
-}
-
-static int iir_cmd_set_data(struct comp_dev *dev, struct sof_ipc_ctrl_data *cdata)
-{
- struct comp_data *cd = comp_get_drvdata(dev);
- struct sof_ipc_ctrl_value_comp *compv;
- int i;
- int ret = 0;
- size_t bs;
-
- switch (cdata->cmd) {
- case SOF_CTRL_CMD_ENUM:
- trace_eq_iir("EIe");
- if (cdata->index == SOF_EQ_IIR_IDX_SWITCH) {
- trace_eq_iir("EIs");
- compv = (struct sof_ipc_ctrl_value_comp *) cdata->data->data;
- for (i = 0; i < (int) cdata->num_elems; i++) {
- tracev_value(compv[i].index);
- tracev_value(compv[i].svalue);
- ret = eq_iir_switch_response(cd->iir, cd->config,
- compv[i].index, compv[i].svalue);
- if (ret < 0) {
- trace_eq_iir_error("swe");
- return -EINVAL;
- }
- }
- } else {
- trace_eq_iir_error("une");
- trace_error_value(cdata->index);
- return -EINVAL;
- }
- break;
- case SOF_CTRL_CMD_BINARY:
- trace_eq_iir("EIb");
- /* Check and free old config */
- eq_iir_free_parameters(&cd->config);
-
- /* Copy new config, need to decode data to know the size */
- bs = cdata->data->size;
- if ((bs > SOF_EQ_IIR_MAX_SIZE) || (bs < 1))
- return -EINVAL;
-
- /* Allocate and make a copy of the blob and setup IIR */
- cd->config = rzalloc(RZONE_RUNTIME, SOF_MEM_CAPS_RAM, bs);
- if (cd->config == NULL)
- return -EINVAL;
-
- memcpy(cd->config, cdata->data->data, bs);
- /* Initialize all channels, the actual number of channels may
- * not be set yet.
- */
- ret = eq_iir_setup(cd->iir, cd->config, PLATFORM_MAX_CHANNELS);
- break;
- default:
- trace_eq_iir_error("ec1");
- ret = -EINVAL;
- break;
- }
-
- return ret;
-}
-
-/* used to pass standard and bespoke commands (with data) to component */
-static int eq_iir_cmd(struct comp_dev *dev, int cmd, void *data)
-{
- struct sof_ipc_ctrl_data *cdata = data;
- int ret = 0;
-
- trace_eq_iir("cmd");
-
- switch (cmd) {
- case COMP_CMD_SET_VALUE:
- ret = iir_cmd_set_value(dev, cdata);
- break;
- case COMP_CMD_SET_DATA:
- ret = iir_cmd_set_data(dev, cdata);
- break;
- }
-
- return ret;
-}
-
-static int eq_iir_trigger(struct comp_dev *dev, int cmd)
-{
- trace_eq_iir("trg");
-
- return comp_set_state(dev, cmd);
-}
-
-/* copy and process stream data from source to sink buffers */
-static int eq_iir_copy(struct comp_dev *dev)
-{
- struct comp_data *cd = comp_get_drvdata(dev);
- struct comp_buffer *source;
- struct comp_buffer *sink;
- int res;
-
- trace_comp("EqI");
-
- /* get source and sink buffers */
- source = list_first_item(&dev->bsource_list, struct comp_buffer,
- sink_list);
- sink = list_first_item(&dev->bsink_list, struct comp_buffer,
- source_list);
-
- /* make sure source component buffer has enough data available and that
- * the sink component buffer has enough free bytes for copy. Also
- * check for XRUNs */
- res = comp_buffer_can_copy_bytes(source, sink, cd->period_bytes);
- if (res) {
- trace_eq_iir_error("xrn");
- return -EIO; /* xrun */
- }
-
- cd->eq_iir_func(dev, source, sink, dev->frames);
-
- /* calc new free and available */
- comp_update_buffer_consume(source, cd->period_bytes);
- comp_update_buffer_produce(sink, cd->period_bytes);
-
- return dev->frames;
-}
-
-static int eq_iir_prepare(struct comp_dev *dev)
-{
- struct comp_data *cd = comp_get_drvdata(dev);
- int ret;
-
- trace_eq_iir("EPp");
-
- ret = comp_set_state(dev, COMP_TRIGGER_PREPARE);
- if (ret < 0)
- return ret;
-
- cd->eq_iir_func = eq_iir_s32_default;
-
- /* Initialize EQ. Note that if EQ has not received command to
- * configure the response the EQ prepare returns an error that
- * interrupts pipeline prepare for downstream.
- */
- if (cd->config == NULL) {
- comp_set_state(dev, COMP_TRIGGER_RESET);
- return -EINVAL;
- }
-
- ret = eq_iir_setup(cd->iir, cd->config, dev->params.channels);
- if (ret < 0) {
- comp_set_state(dev, COMP_TRIGGER_RESET);
- return ret;
- }
-
- return 0;
-}
-
-static int eq_iir_reset(struct comp_dev *dev)
-{
- int i;
- struct comp_data *cd = comp_get_drvdata(dev);
-
- trace_eq_iir("ERe");
-
- eq_iir_free_delaylines(cd->iir);
- eq_iir_free_parameters(&cd->config);
-
- cd->eq_iir_func = eq_iir_s32_default;
- for (i = 0; i < PLATFORM_MAX_CHANNELS; i++)
- iir_reset_df2t(&cd->iir[i]);
-
- comp_set_state(dev, COMP_TRIGGER_RESET);
- return 0;
-}
-
-struct comp_driver comp_eq_iir = {
- .type = SOF_COMP_EQ_IIR,
- .ops = {
- .new = eq_iir_new,
- .free = eq_iir_free,
- .params = eq_iir_params,
- .cmd = eq_iir_cmd,
- .trigger = eq_iir_trigger,
- .copy = eq_iir_copy,
- .prepare = eq_iir_prepare,
- .reset = eq_iir_reset,
- },
-};
-
-void sys_comp_eq_iir_init(void)
-{
- comp_register(&comp_eq_iir);
-}
diff --git a/src/audio/eq_iir.h b/src/audio/eq_iir.h
deleted file mode 100644
index e28a1a3..0000000
--- a/src/audio/eq_iir.h
+++ /dev/null
@@ -1,36 +0,0 @@
-/*
- * Copyright (c) 2017, Intel Corporation
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- * * Redistributions of source code must retain the above copyright
- * notice, this list of conditions and the following disclaimer.
- * * Redistributions in binary form must reproduce the above copyright
- * notice, this list of conditions and the following disclaimer in the
- * documentation and/or other materials provided with the distribution.
- * * Neither the name of the Intel Corporation nor the
- * names of its contributors may be used to endorse or promote products
- * derived from this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
- * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
- * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
- * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
- * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
- * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
- * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
- * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
- * POSSIBILITY OF SUCH DAMAGE.
- *
- * Author: Seppo Ingalsuo <seppo.ingalsuo@linux.intel.com>
- * Liam Girdwood <liam.r.girdwood@linux.intel.com>
- * Keyon Jie <yang.jie@linux.intel.com>
- */
-
-#ifndef EQ_IIR_H
-#define EQ_IIR_H
-
-#endif
diff --git a/src/audio/fir.c b/src/audio/fir.c
deleted file mode 100644
index d64475a..0000000
--- a/src/audio/fir.c
+++ /dev/null
@@ -1,112 +0,0 @@
-/*
- * Copyright (c) 2017, Intel Corporation
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- * * Redistributions of source code must retain the above copyright
- * notice, this list of conditions and the following disclaimer.
- * * Redistributions in binary form must reproduce the above copyright
- * notice, this list of conditions and the following disclaimer in the
- * documentation and/or other materials provided with the distribution.
- * * Neither the name of the Intel Corporation nor the
- * names of its contributors may be used to endorse or promote products
- * derived from this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
- * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
- * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
- * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
- * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
- * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
- * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
- * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
- * POSSIBILITY OF SUCH DAMAGE.
- *
- * Author: Seppo Ingalsuo <seppo.ingalsuo@linux.intel.com>
- * Liam Girdwood <liam.r.girdwood@linux.intel.com>
- * Keyon Jie <yang.jie@linux.intel.com>
- */
-
-#include <stdint.h>
-#include <stddef.h>
-#include <errno.h>
-#include <sof/audio/component.h>
-#include <sof/audio/format.h>
-#include <uapi/eq.h>
-#include "fir_config.h"
-
-#if FIR_GENERIC
-
-#include "fir.h"
-
-/*
- * EQ FIR algorithm code
- */
-
-void fir_reset(struct fir_state_32x16 *fir)
-{
- fir->rwi = 0;
- fir->length = 0;
- fir->delay_size = 0;
- fir->out_shift = 0;
- fir->coef = NULL;
- /* There may need to know the beginning of dynamic allocation after
- * reset so omitting setting also fir->delay to NULL.
- */
-}
-
-int fir_init_coef(struct fir_state_32x16 *fir, int16_t config[])
-{
- struct sof_eq_fir_coef_data *setup;
-
- setup = (struct sof_eq_fir_coef_data *)config;
- fir->rwi = 0;
- fir->length = (int)setup->length;
- fir->out_shift = (int)setup->out_shift;
- fir->coef = &setup->coef[0];
- fir->delay = NULL;
- fir->delay_size = 0;
-
- /* Check for sane FIR length. The length is constrained to be a
- * multiple of 4 for optimized code.
- */
- if (fir->length > SOF_EQ_FIR_MAX_LENGTH || fir->length < 1)
- return -EINVAL;
-
- return fir->length;
-}
-
-void fir_init_delay(struct fir_state_32x16 *fir, int32_t **data)
-{
- fir->delay = *data;
- fir->delay_size = fir->length;
- *data += fir->delay_size; /* Point to next delay line start */
-}
-
-void eq_fir_s32(struct fir_state_32x16 fir[], struct comp_buffer *source,
- struct comp_buffer *sink, int frames, int nch)
-{
- struct fir_state_32x16 *filter;
- int32_t *src = (int32_t *)source->r_ptr;
- int32_t *snk = (int32_t *)sink->w_ptr;
- int32_t *x;
- int32_t *y;
- int ch;
- int i;
-
- for (ch = 0; ch < nch; ch++) {
- filter = &fir[ch];
- x = src++;
- y = snk++;
- for (i = 0; i < frames; i++) {
- *y = fir_32x16(filter, *x);
- x += nch;
- y += nch;
- }
- }
-}
-
-#endif
diff --git a/src/audio/fir.h b/src/audio/fir.h
deleted file mode 100644
index fab87ed..0000000
--- a/src/audio/fir.h
+++ /dev/null
@@ -1,117 +0,0 @@
-/*
- * Copyright (c) 2017, Intel Corporation
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- * * Redistributions of source code must retain the above copyright
- * notice, this list of conditions and the following disclaimer.
- * * Redistributions in binary form must reproduce the above copyright
- * notice, this list of conditions and the following disclaimer in the
- * documentation and/or other materials provided with the distribution.
- * * Neither the name of the Intel Corporation nor the
- * names of its contributors may be used to endorse or promote products
- * derived from this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
- * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
- * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
- * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
- * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
- * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
- * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
- * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
- * POSSIBILITY OF SUCH DAMAGE.
- *
- * Author: Seppo Ingalsuo <seppo.ingalsuo@linux.intel.com>
- * Liam Girdwood <liam.r.girdwood@linux.intel.com>
- * Keyon Jie <yang.jie@linux.intel.com>
- */
-
-#ifndef FIR_H
-#define FIR_H
-
-#include "fir_config.h"
-
-#if FIR_GENERIC
-
-#include <sof/audio/format.h>
-
-struct fir_state_32x16 {
- int rwi; /* Circular read and write index */
- int length; /* Number of FIR taps */
- int delay_size; /* Actual delay lentgh, must be >= length */
- int out_shift; /* Amount of right shifts at output */
- int16_t *coef; /* Pointer to FIR coefficients */
- int32_t *delay; /* Pointer to FIR delay line */
-};
-
-void fir_reset(struct fir_state_32x16 *fir);
-
-int fir_init_coef(struct fir_state_32x16 *fir, int16_t config[]);
-
-void fir_init_delay(struct fir_state_32x16 *fir, int32_t **data);
-
-void eq_fir_s32(struct fir_state_32x16 fir[], struct comp_buffer *source,
- struct comp_buffer *sink, int frames, int nch);
-
-/* The next functions are inlined to optmize execution speed */
-
-static inline void fir_part_32x16(int64_t *y, int taps, const int16_t c[],
- int *ic, int32_t d[], int *id)
-{
- int n;
-
- /* Data is Q8.24, coef is Q1.15, product is Q9.39 */
- for (n = 0; n < taps; n++) {
- *y += (int64_t)c[*ic] * d[*id];
- (*ic)++;
- (*id)--;
- }
-}
-
-static inline int32_t fir_32x16(struct fir_state_32x16 *fir, int32_t x)
-{
- int64_t y = 0;
- int n1;
- int n2;
- int i = 0; /* Start from 1st tap */
- int tmp_ri;
-
- /* Write sample to delay */
- fir->delay[fir->rwi] = x;
-
- /* Start FIR calculation. Calculate first number of taps possible to
- * calculate before circular wrap need.
- */
- n1 = fir->rwi + 1;
- /* Point to newest sample and advance read index */
- tmp_ri = (fir->rwi)++;
- if (fir->rwi == fir->delay_size)
- fir->rwi = 0;
-
- if (n1 > fir->length) {
- /* No need to un-wrap fir read index, make sure ri
- * is >= 0 after FIR computation.
- */
- fir_part_32x16(&y, fir->length, fir->coef, &i, fir->delay,
- &tmp_ri);
- } else {
- n2 = fir->length - n1;
- /* Part 1, loop n1 times, fir_ri becomes -1 */
- fir_part_32x16(&y, n1, fir->coef, &i, fir->delay, &tmp_ri);
-
- /* Part 2, unwrap fir_ri, continue rest of filter */
- tmp_ri = fir->delay_size - 1;
- fir_part_32x16(&y, n2, fir->coef, &i, fir->delay, &tmp_ri);
- }
- /* Q9.39 -> Q9.24, saturate to Q8.24 */
- y = sat_int32(y >> (15 + fir->out_shift));
-
- return (int32_t)y;
-}
-
-#endif
-#endif
diff --git a/src/audio/fir_config.h b/src/audio/fir_config.h
deleted file mode 100644
index 317e0bf..0000000
--- a/src/audio/fir_config.h
+++ /dev/null
@@ -1,76 +0,0 @@
-/*
- * Copyright (c) 2017, Intel Corporation
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- * * Redistributions of source code must retain the above copyright
- * notice, this list of conditions and the following disclaimer.
- * * Redistributions in binary form must reproduce the above copyright
- * notice, this list of conditions and the following disclaimer in the
- * documentation and/or other materials provided with the distribution.
- * * Neither the name of the Intel Corporation nor the
- * names of its contributors may be used to endorse or promote products
- * derived from this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
- * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
- * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
- * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
- * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
- * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
- * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
- * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
- * POSSIBILITY OF SUCH DAMAGE.
- *
- * Author: Seppo Ingalsuo <seppo.ingalsuo@linux.intel.com>
- * Liam Girdwood <liam.r.girdwood@linux.intel.com>
- * Keyon Jie <yang.jie@linux.intel.com>
- */
-
-#ifndef FIR_CONFIG_H
-
-/* Get platforms configuration */
-#include <config.h>
-
-/* If next defines are set to 1 the EQ is configured automatically. Setting
- * to zero temporarily is useful is for testing needs.
- * Setting EQ_FIR_AUTOARCH to 0 allows to manually set the code variant.
- */
-#define FIR_AUTOARCH 1
-
-/* Force manually some code variant when EQ_FIR_AUTODSP is set to zero. These
- * are useful in code debugging.
- */
-#if FIR_AUTOARCH == 0
-#define FIR_GENERIC 0
-#define FIR_HIFIEP 0
-#define FIR_HIFI3 1
-#endif
-
-/* Select optimized code variant when xt-xcc compiler is used */
-#if FIR_AUTOARCH == 1
-#if defined __XCC__
-#include <xtensa/config/core-isa.h>
-#define FIR_GENERIC 0
-#if XCHAL_HAVE_HIFI2EP == 1
-#define FIR_HIFIEP 1
-#define FIR_HIFI3 0
-#endif
-#if XCHAL_HAVE_HIFI3 == 1
-#define FIR_HIFI3 1
-#define FIR_HIFIEP 0
-#endif
-#else
-/* GCC */
-#define FIR_GENERIC 1
-#define FIR_HIFIEP 0
-#define FIR_HIFI3 0
-#endif
-#endif
-
-#define FIR_CONFIG_H
-
-#endif
diff --git a/src/audio/fir_hifi2ep.c b/src/audio/fir_hifi2ep.c
deleted file mode 100644
index 77cdba2..0000000
--- a/src/audio/fir_hifi2ep.c
+++ /dev/null
@@ -1,189 +0,0 @@
-/*
- * Copyright (c) 2017, Intel Corporation
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- * * Redistributions of source code must retain the above copyright
- * notice, this list of conditions and the following disclaimer.
- * * Redistributions in binary form must reproduce the above copyright
- * notice, this list of conditions and the following disclaimer in the
- * documentation and/or other materials provided with the distribution.
- * * Neither the name of the Intel Corporation nor the
- * names of its contributors may be used to endorse or promote products
- * derived from this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
- * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
- * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
- * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
- * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
- * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
- * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
- * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
- * POSSIBILITY OF SUCH DAMAGE.
- *
- * Author: Seppo Ingalsuo <seppo.ingalsuo@linux.intel.com>
- */
-
-#include <stdint.h>
-#include <stddef.h>
-#include <errno.h>
-#include <sof/audio/component.h>
-#include <sof/audio/format.h>
-#include <uapi/eq.h>
-#include "fir_config.h"
-
-#if FIR_HIFIEP
-
-#include <xtensa/config/defs.h>
-#include <xtensa/tie/xt_hifi2.h>
-#include "fir_hifi2ep.h"
-
-/*
- * EQ FIR algorithm code
- */
-
-void fir_reset(struct fir_state_32x16 *fir)
-{
- fir->mute = 1;
- fir->length = 0;
- fir->out_shift = 0;
- fir->rwp = NULL;
- fir->delay = NULL;
- fir->delay_end = NULL;
- fir->coef = NULL;
- /* There may need to know the beginning of dynamic allocation after
- * reset so omitting setting also fir->delay to NULL.
- */
-}
-
-int fir_init_coef(struct fir_state_32x16 *fir, int16_t config[])
-{
- struct sof_eq_fir_coef_data *setup;
-
- /* The length is taps plus two since the filter computes two
- * samples per call. Length plus one would be minimum but the add
- * must be even. The even length is needed for 64 bit loads from delay
- * lines with 32 bit samples.
- */
- setup = (struct sof_eq_fir_coef_data *)config;
- fir->mute = 0;
- fir->rwp = NULL;
- fir->taps = (int)setup->length;
- fir->length = fir->taps + 2;
- fir->out_shift = (int)setup->out_shift;
- fir->coef = (ae_p16x2s *)&setup->coef[0];
- fir->delay = NULL;
- fir->delay_end = NULL;
-
- /* Check FIR tap count for implementation specific constraints */
- if (fir->taps > SOF_EQ_FIR_MAX_LENGTH || fir->taps < 4)
- return -EINVAL;
-
- if (fir->taps & 3)
- return -EINVAL;
-
- return fir->length;
-}
-
-void fir_init_delay(struct fir_state_32x16 *fir, int32_t **data)
-{
- fir->delay = (ae_p24f *) *data;
- fir->delay_end = fir->delay + fir->length;
- fir->rwp = (ae_p24x2f *)(fir->delay + fir->length - 1);
- *data += fir->length; /* Point to next delay line start */
-}
-
-void fir_get_lrshifts(struct fir_state_32x16 *fir, int *lshift,
- int *rshift)
-{
- if (fir->mute) {
- *lshift = 0;
- *rshift = 31;
- } else {
- *lshift = (fir->out_shift < 0) ? -fir->out_shift : 0;
- *rshift = (fir->out_shift > 0) ? fir->out_shift : 0;
- }
-}
-
-/* For even frame lengths use FIR filter that processes two sequential
- * sample per call.
- */
-void eq_fir_2x_s32_hifiep(struct fir_state_32x16 fir[],
- struct comp_buffer *source,
- struct comp_buffer *sink,
- int frames, int nch)
-{
- struct fir_state_32x16 *f;
- int32_t *src = (int32_t *)source->r_ptr;
- int32_t *snk = (int32_t *)sink->w_ptr;
- int32_t *x0;
- int32_t *y0;
- int32_t *x1;
- int32_t *y1;
- int ch;
- int i;
- int rshift;
- int lshift;
- int inc = nch << 1;
-
- for (ch = 0; ch < nch; ch++) {
- /* Get FIR instance and get shifts to e.g. apply mute
- * without overhead.
- */
- f = &fir[ch];
- fir_get_lrshifts(f, &lshift, &rshift);
-
- /* Setup circular buffer for FIR input data delay */
- fir_hifiep_setup_circular(f);
-
- x0 = src++;
- y0 = snk++;
- for (i = 0; i < (frames >> 1); i++) {
- x1 = x0 + nch;
- y1 = y0 + nch;
- fir_32x16_2x_hifiep(f, x0, x1, y0, y1, lshift, rshift);
- x0 += inc;
- y0 += inc;
- }
- }
-}
-
-/* FIR for any number of frames */
-void eq_fir_s32_hifiep(struct fir_state_32x16 fir[], struct comp_buffer *source,
- struct comp_buffer *sink, int frames, int nch)
-{
- struct fir_state_32x16 *f;
- int32_t *src = (int32_t *)source->r_ptr;
- int32_t *snk = (int32_t *)sink->w_ptr;
- int32_t *x;
- int32_t *y;
- int ch;
- int i;
- int rshift;
- int lshift;
-
- for (ch = 0; ch < nch; ch++) {
- /* Get FIR instance and get shifts to e.g. apply mute
- * without overhead.
- */
- f = &fir[ch];
- fir_get_lrshifts(f, &lshift, &rshift);
-
- /* Setup circular buffer for FIR input data delay */
- fir_hifiep_setup_circular(f);
-
- x = src++;
- y = snk++;
- for (i = 0; i < frames; i++) {
- fir_32x16_hifiep(f, x, y, lshift, rshift);
- x += nch;
- y += nch;
- }
- }
-}
-
-#endif
diff --git a/src/audio/fir_hifi2ep.h b/src/audio/fir_hifi2ep.h
deleted file mode 100644
index f9aff38..0000000
--- a/src/audio/fir_hifi2ep.h
+++ /dev/null
@@ -1,248 +0,0 @@
-/*
- * Copyright (c) 2017, Intel Corporation
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- * * Redistributions of source code must retain the above copyright
- * notice, this list of conditions and the following disclaimer.
- * * Redistributions in binary form must reproduce the above copyright
- * notice, this list of conditions and the following disclaimer in the
- * documentation and/or other materials provided with the distribution.
- * * Neither the name of the Intel Corporation nor the
- * names of its contributors may be used to endorse or promote products
- * derived from this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
- * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
- * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
- * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
- * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
- * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
- * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
- * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
- * POSSIBILITY OF SUCH DAMAGE.
- *
- * Author: Seppo Ingalsuo <seppo.ingalsuo@linux.intel.com>
- */
-
-#ifndef FIR_HIFI2EP_H
-#define FIR_HIFI2EP_H
-
-#include "fir_config.h"
-
-#if FIR_HIFIEP
-
-#include <xtensa/config/defs.h>
-#include <xtensa/tie/xt_hifi2.h>
-#include <sof/audio/format.h>
-
-struct fir_state_32x16 {
- ae_p24x2f *rwp; /* Circular read and write pointer */
- ae_p24f *delay; /* Pointer to FIR delay line */
- ae_p24f *delay_end; /* Pointer to FIR delay line end */
- ae_p16x2s *coef; /* Pointer to FIR coefficients */
- int mute; /* Set to 1 to mute EQ output, 0 otherwise */
- int taps; /* Number of FIR taps */
- int length; /* Number of FIR taps plus input length (even) */
- int in_shift; /* Amount of right shifts at input */
- int out_shift; /* Amount of right shifts at output */
-};
-
-void fir_reset(struct fir_state_32x16 *fir);
-
-int fir_init_coef(struct fir_state_32x16 *fir, int16_t config[]);
-
-void fir_init_delay(struct fir_state_32x16 *fir, int32_t **data);
-
-void eq_fir_2x_s32_hifiep(struct fir_state_32x16 fir[],
- struct comp_buffer *source,
- struct comp_buffer *sink,
- int frames, int nch);
-
-void eq_fir_s32_hifiep(struct fir_state_32x16 fir[], struct comp_buffer *source,
- struct comp_buffer *sink, int frames, int nch);
-
-/* The next trivial functions are inlined */
-
-static inline void fir_mute(struct fir_state_32x16 *fir)
-{
- fir->mute = 1;
-}
-
-static inline void fir_unmute(struct fir_state_32x16 *fir)
-{
- fir->mute = 0;
-}
-
-/* Setup circular buffer for FIR input data delay */
-static inline void fir_hifiep_setup_circular(struct fir_state_32x16 *fir)
-{
- AE_SETCBEGIN0(fir->delay);
- AE_SETCEND0(fir->delay_end);
-}
-
-void fir_get_lrshifts(struct fir_state_32x16 *fir, int *lshift,
- int *rshift);
-
-/* The next functions are inlined to optmize execution speed */
-
-/* HiFi EP has the follow number of reqisters that should not be exceeded
- * 4x 56 bit registers in register file Q
- * 8x 48 bit registers in register file P
- */
-
-static inline void fir_32x16_hifiep(struct fir_state_32x16 *fir, int32_t *x,
- int32_t *y, int lshift, int rshift)
-{
- /* This function uses
- * 1x 56 bit registers Q,
- * 4x 48 bit registers P
- * 3x integers
- * 2x address pointers,
- */
- ae_q56s a;
- ae_p24x2f data2;
- ae_p24x2f coef2;
- ae_p24x2f d0;
- ae_p24x2f d1;
- int i;
- ae_p24x2f *dp = fir->rwp;
- ae_p16x2s *coefp = fir->coef;
- const int taps_div_4 = fir->taps >> 2;
- const int inc = sizeof(int32_t);
-
- /* Write sample to delay */
- a = AE_LQ32F_I((ae_q32s *)x, 0);
- AE_SQ32F_C(a, (ae_q32s *)fir->rwp, -sizeof(int32_t));
-
- /* Note: If the next function is converted to handle two samples
- * per call the data load can be done with single instruction
- * AE_LP24X2F_C(data2, dp, sizeof(ae_p24x2f));
- */
- a = AE_ZEROQ56();
- for (i = 0; i < taps_div_4; i++) {
- /* Load two coefficients. Coef2_h contains tap coefp[n]
- * and coef2_l contains coef[n+1].
- */
- coef2 = AE_LP16X2F_I(coefp, 0);
-
- /* Load two data samples and pack to d0 to data2_h and
- * d1 to data2_l.
- */
- AE_LP24F_C(d0, dp, inc);
- AE_LP24F_C(d1, dp, inc);
- data2 = AE_SELP24_LL(d0, d1);
-
- /* Accumulate
- * data2_h * coef2_h + data2_l * coef2_l. The Q1.31
- * data and Q1.15 coefficients are used as 24 bits as
- * Q1.23 values.
- */
- AE_MULAAFP24S_HH_LL(a, data2, coef2);
-
- /* Repeat the same for next two taps and increase coefp. */
- coef2 = AE_LP16X2F_I(coefp, sizeof(ae_p16x2s));
- AE_LP24F_C(d0, dp, inc);
- AE_LP24F_C(d1, dp, inc);
- data2 = AE_SELP24_LL(d0, d1);
- AE_MULAAFP24S_HH_LL(a, data2, coef2);
- coefp += 2;
- }
-
- /* Do scaling shifts and store sample. */
- a = AE_SRAAQ56(AE_SLLASQ56S(a, lshift), rshift);
- AE_SQ32F_I(AE_ROUNDSQ32SYM(a), (ae_q32s *)y, 0);
-}
-
-/* HiFi EP has the follow number of reqisters that should not be exceeded
- * 4x 56 bit registers in register file Q
- * 8x 48 bit registers in register file P
- */
-
-static inline void fir_32x16_2x_hifiep(struct fir_state_32x16 *fir, int32_t *x0,
- int32_t *x1, int32_t *y0, int32_t *y1,
- int lshift, int rshift)
-{
- /* This function uses
- * 2x 56 bit registers Q,
- * 4x 48 bit registers P
- * 3x integers
- * 2x address pointers,
- */
- ae_q56s a;
- ae_q56s b;
- ae_p24x2f d0;
- ae_p24x2f d1;
- ae_p24x2f d3;
- ae_p24x2f coefs;
- int i;
- ae_p24x2f *dp;
- ae_p16x2s *coefp = fir->coef;
- const int taps_div_4 = fir->taps >> 2;
- const int inc = 2 * sizeof(int32_t);
-
- /* Write samples to delay */
- a = AE_LQ32F_I((ae_q32s *)x0, 0);
- AE_SQ32F_C(a, (ae_q32s *)fir->rwp, -sizeof(int32_t));
- a = AE_LQ32F_I((ae_q32s *)x1, 0);
- dp = fir->rwp;
- AE_SQ32F_C(a, (ae_q32s *)fir->rwp, -sizeof(int32_t));
-
- /* Note: If the next function is converted to handle two samples
- * per call the data load can be done with single instruction
- * AE_LP24X2F_C(data2, dp, sizeof(ae_p24x2f));
- */
- a = AE_ZEROQ56();
- b = AE_ZEROQ56();
- /* Load two data samples and pack to d0 to data2_h and
- * d1 to data2_l.
- */
- AE_LP24X2F_C(d0, dp, inc);
- for (i = 0; i < taps_div_4; i++) {
- /* Load two coefficients. Coef2_h contains tap coefp[n]
- * and coef2_l contains coef[n+1].
- */
- coefs = AE_LP16X2F_I(coefp, 0);
-
- /* Load two data samples. Upper part d1_h is x[n+1] and
- * lower part d1_l is x[n].
- */
- AE_LP24X2F_C(d1, dp, inc);
-
- /* Accumulate
- * b += d0_h * coefs_h + d0_l * coefs_l. The Q1.31 data
- * and Q1.15 coefficients are converted to 24 bits as
- * Q1.23 values.
- */
- AE_MULAAFP24S_HH_LL(b, d0, coefs);
-
- /* Pack d0_l and d1_h to d3. Then accumulate
- * a += d3_h * coefs_h + d3_l * coefs_l. Pass d1 to d1 for
- * next unrolled iteration.
- */
- d3 = AE_SELP24_LH(d0, d1);
- AE_MULAAFP24S_HH_LL(a, d3, coefs);
- d0 = d1;
-
- /* Repeat the same for next two taps and increase coefp. */
- coefs = AE_LP16X2F_I(coefp, sizeof(ae_p16x2s));
- AE_LP24X2F_C(d1, dp, inc);
- AE_MULAAFP24S_HH_LL(b, d0, coefs);
- d3 = AE_SELP24_LH(d0, d1);
- AE_MULAAFP24S_HH_LL(a, d3, coefs);
- d0 = d1;
- coefp += 2;
- }
-
- /* Do scaling shifts and store sample. */
- b = AE_SRAAQ56(AE_SLLASQ56S(b, lshift), rshift);
- a = AE_SRAAQ56(AE_SLLASQ56S(a, lshift), rshift);
- AE_SQ32F_I(AE_ROUNDSQ32SYM(b), (ae_q32s *)y1, 0);
- AE_SQ32F_I(AE_ROUNDSQ32SYM(a), (ae_q32s *)y0, 0);
-}
-
-#endif
-#endif
diff --git a/src/audio/fir_hifi3.c b/src/audio/fir_hifi3.c
deleted file mode 100644
index dad79e0..0000000
--- a/src/audio/fir_hifi3.c
+++ /dev/null
@@ -1,192 +0,0 @@
-/*
- * Copyright (c) 2017, Intel Corporation
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- * * Redistributions of source code must retain the above copyright
- * notice, this list of conditions and the following disclaimer.
- * * Redistributions in binary form must reproduce the above copyright
- * notice, this list of conditions and the following disclaimer in the
- * documentation and/or other materials provided with the distribution.
- * * Neither the name of the Intel Corporation nor the
- * names of its contributors may be used to endorse or promote products
- * derived from this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
- * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
- * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
- * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
- * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
- * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
- * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
- * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
- * POSSIBILITY OF SUCH DAMAGE.
- *
- * Author: Seppo Ingalsuo <seppo.ingalsuo@linux.intel.com>
- */
-
-#include <stdint.h>
-#include <stddef.h>
-#include <errno.h>
-#include <sof/audio/component.h>
-#include <sof/audio/format.h>
-#include <uapi/eq.h>
-#include "fir_config.h"
-
-#if FIR_HIFI3
-
-#include <xtensa/config/defs.h>
-#include <xtensa/tie/xt_hifi3.h>
-#include "fir_hifi3.h"
-
-/*
- * EQ FIR algorithm code
- */
-
-void fir_reset(struct fir_state_32x16 *fir)
-{
- fir->mute = 1;
- fir->length = 0;
- fir->out_shift = 0;
- fir->rwp = NULL;
- fir->delay = NULL;
- fir->delay_end = NULL;
- fir->coef = NULL;
- /* There may need to know the beginning of dynamic allocation after
- * reset so omitting setting also fir->delay to NULL.
- */
-}
-
-int fir_init_coef(struct fir_state_32x16 *fir, int16_t config[])
-{
- struct sof_eq_fir_coef_data *setup;
-
- /* The length is taps plus two since the filter computes two
- * samples per call. Length plus one would be minimum but the add
- * must be even. The even length is needed for 64 bit loads from delay
- * lines with 32 bit samples.
- */
- setup = (struct sof_eq_fir_coef_data *)config;
- fir->mute = 0;
- fir->rwp = NULL;
- fir->taps = (int)setup->length;
- fir->length = fir->taps + 2;
- fir->out_shift = (int)setup->out_shift;
- fir->coef = (ae_f16x4 *)&setup->coef[0];
- fir->delay = NULL;
- fir->delay_end = NULL;
-
- /* Check FIR tap count for implementation specific constraints */
- if (fir->taps > SOF_EQ_FIR_MAX_LENGTH || fir->taps < 4)
- return -EINVAL;
-
- if (fir->taps & 3)
- return -EINVAL;
-
- return fir->length;
-}
-
-void fir_init_delay(struct fir_state_32x16 *fir, int32_t **data)
-{
- fir->delay = (ae_int32 *) *data;
- fir->delay_end = fir->delay + fir->length;
- fir->rwp = (ae_int32 *)(fir->delay + fir->length - 1);
- *data += fir->length; /* Point to next delay line start */
-}
-
-void fir_get_lrshifts(struct fir_state_32x16 *fir, int *lshift,
- int *rshift)
-{
- if (fir->mute) {
- *lshift = 0;
- *rshift = 31;
- } else {
- *lshift = (fir->out_shift < 0) ? -fir->out_shift : 0;
- *rshift = (fir->out_shift > 0) ? fir->out_shift : 0;
- }
-}
-
-/* For even frame lengths use FIR filter that processes two sequential
- * sample per call.
- */
-void eq_fir_2x_s32_hifi3(struct fir_state_32x16 fir[],
- struct comp_buffer *source, struct comp_buffer *sink,
- int frames, int nch)
-{
- struct fir_state_32x16 *f;
- int32_t *src = (int32_t *)source->r_ptr;
- int32_t *snk = (int32_t *)sink->w_ptr;
- int32_t *x0;
- int32_t *y0;
- int32_t *x1;
- int32_t *y1;
- int ch;
- int i;
- int rshift;
- int lshift;
- int shift;
- int inc = nch << 1;
-
- for (ch = 0; ch < nch; ch++) {
- /* Get FIR instance and get shifts to e.g. apply mute
- * without overhead.
- */
- f = &fir[ch];
- fir_get_lrshifts(f, &lshift, &rshift);
- shift = lshift - rshift;
-
- /* Setup circular buffer for FIR input data delay */
- fir_hifi3_setup_circular(f);
-
- x0 = src++;
- y0 = snk++;
- for (i = 0; i < (frames >> 1); i++) {
- x1 = x0 + nch;
- y1 = y0 + nch;
- fir_32x16_2x_hifi3(f, x0, x1, y0, y1, shift);
- x0 += inc;
- y0 += inc;
- }
- }
-}
-
-/* FIR for any number of frames */
-void eq_fir_s32_hifi3(struct fir_state_32x16 fir[], struct comp_buffer *source,
- struct comp_buffer *sink, int frames, int nch)
-{
- struct fir_state_32x16 *f;
- int32_t *src = (int32_t *)source->r_ptr;
- int32_t *snk = (int32_t *)sink->w_ptr;
- int32_t *x;
- int32_t *y;
- int ch;
- int i;
- int rshift;
- int lshift;
- int shift;
-
- for (ch = 0; ch < nch; ch++) {
- /* Get FIR instance and get shifts to e.g. apply mute
- * without overhead.
- */
- f = &fir[ch];
- fir_get_lrshifts(f, &lshift, &rshift);
- shift = lshift - rshift;
-
- /* Setup circular buffer for FIR input data delay */
- fir_hifi3_setup_circular(f);
-
- x = src++;
- y = snk++;
- for (i = 0; i < frames; i++) {
- fir_32x16_hifi3(f, x, y, shift);
- x += nch;
- y += nch;
- }
- }
-}
-
-#endif
diff --git a/src/audio/fir_hifi3.h b/src/audio/fir_hifi3.h
deleted file mode 100644
index 20896f0..0000000
--- a/src/audio/fir_hifi3.h
+++ /dev/null
@@ -1,248 +0,0 @@
-/*
- * Copyright (c) 2017, Intel Corporation
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- * * Redistributions of source code must retain the above copyright
- * notice, this list of conditions and the following disclaimer.
- * * Redistributions in binary form must reproduce the above copyright
- * notice, this list of conditions and the following disclaimer in the
- * documentation and/or other materials provided with the distribution.
- * * Neither the name of the Intel Corporation nor the
- * names of its contributors may be used to endorse or promote products
- * derived from this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
- * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
- * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
- * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
- * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
- * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
- * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
- * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
- * POSSIBILITY OF SUCH DAMAGE.
- *
- * Author: Seppo Ingalsuo <seppo.ingalsuo@linux.intel.com>
- */
-
-#ifndef FIR_HIFI3_H
-#define FIR_HIFI3_H
-
-#include "fir_config.h"
-
-#if FIR_HIFI3
-
-#include <xtensa/config/defs.h>
-#include <xtensa/tie/xt_hifi2.h>
-#include <sof/audio/format.h>
-
-struct fir_state_32x16 {
- ae_int32 *rwp; /* Circular read and write pointer */
- ae_int32 *delay; /* Pointer to FIR delay line */
- ae_int32 *delay_end; /* Pointer to FIR delay line end */
- ae_f16x4 *coef; /* Pointer to FIR coefficients */
- int mute; /* Set to 1 to mute EQ output, 0 otherwise */
- int taps; /* Number of FIR taps */
- int length; /* Number of FIR taps plus input length (even) */
- int in_shift; /* Amount of right shifts at input */
- int out_shift; /* Amount of right shifts at output */
-};
-
-void fir_reset(struct fir_state_32x16 *fir);
-
-int fir_init_coef(struct fir_state_32x16 *fir, int16_t config[]);
-
-void fir_init_delay(struct fir_state_32x16 *fir, int32_t **data);
-
-void eq_fir_2x_s32_hifi3(struct fir_state_32x16 fir[],
- struct comp_buffer *source, struct comp_buffer *sink,
- int frames, int nch);
-
-void eq_fir_s32_hifi3(struct fir_state_32x16 fir[], struct comp_buffer *source,
- struct comp_buffer *sink, int frames, int nch);
-
-/* The next trivial functions are inlined */
-
-static inline void fir_mute(struct fir_state_32x16 *fir)
-{
- fir->mute = 1;
-}
-
-static inline void fir_unmute(struct fir_state_32x16 *fir)
-{
- fir->mute = 0;
-}
-
-/* Setup circular buffer for FIR input data delay */
-static inline void fir_hifi3_setup_circular(struct fir_state_32x16 *fir)
-{
- AE_SETCBEGIN0(fir->delay);
- AE_SETCEND0(fir->delay_end);
-}
-
-void fir_get_lrshifts(struct fir_state_32x16 *fir, int *lshift,
- int *rshift);
-
-/* The next functions are inlined to optmize execution speed */
-
-/* HiFi EP has the follow number of reqisters that should not be exceeded
- * 4x 56 bit registers in register file Q
- * 8x 48 bit registers in register file P
- */
-
-static inline void fir_32x16_hifi3(struct fir_state_32x16 *fir, int32_t *x,
- int32_t *y, int shift)
-{
- /* This function uses
- * 1x 56 bit registers Q,
- * 4x 48 bit registers P
- * 3x integers
- * 2x address pointers,
- */
- ae_f64 a;
- ae_valign u;
- ae_f32x2 data2;
- ae_f16x4 coefs;
- ae_f32x2 d0;
- ae_f32x2 d1;
- int i;
- ae_int32 *dp = fir->rwp;
- ae_int16x4 *coefp = (ae_int16x4 *)fir->coef;
- const int taps_div_4 = fir->taps >> 2;
- const int inc = sizeof(int32_t);
-
- /* Write sample to delay */
- AE_S32_L_XC((ae_int32)*x, fir->rwp, -sizeof(int32_t));
-
- /* Prime the coefficients stream */
- u = AE_LA64_PP(coefp);
-
- /* Note: If the next function is converted to handle two samples
- * per call the data load can be done with single instruction
- * AE_LP24X2F_C(data2, dp, sizeof(ae_p24x2f));
- */
- a = AE_ZEROQ56();
- for (i = 0; i < taps_div_4; i++) {
- /* Load four coefficients. Coef_3 contains tap h[n],
- * coef_2 contains h[n+1], coef_1 contains h[n+2], and
- * coef_0 contains h[n+3];
- */
- AE_LA16X4_IP(coefs, u, coefp);
-
- /* Load two data samples and pack to d0 to data2_h and
- * d1 to data2_l.
- */
- AE_L32_XC(d0, dp, inc);
- AE_L32_XC(d1, dp, inc);
- data2 = AE_SEL32_LL(d0, d1);
-
- /* Accumulate
- * a += data2_h * coefs_3 + data2_l * coefs_2. The Q1.31
- * data and Q1.15 coefficients are used as 24 bits as
- * Q1.23 values.
- */
- AE_MULAAFD32X16_H3_L2(a, data2, coefs);
-
- /* Repeat the same for next two taps and increase coefp.
- * a += data2_h * coefs_1 + data2_l * coefs_0.
- */
- AE_L32_XC(d0, dp, inc);
- AE_L32_XC(d1, dp, inc);
- data2 = AE_SEL32_LL(d0, d1);
- AE_MULAAFD32X16_H1_L0(a, data2, coefs);
- //coefp += 4;
- }
-
- /* Do scaling shifts and store sample. */
- a = AE_SLAA64S(a, shift);
- AE_S32_L_I(AE_ROUND32F48SSYM(a), (ae_int32 *)y, 0);
-}
-
-/* HiFi EP has the follow number of reqisters that should not be exceeded
- * 4x 56 bit registers in register file Q
- * 8x 48 bit registers in register file P
- */
-
-static inline void fir_32x16_2x_hifi3(struct fir_state_32x16 *fir, int32_t *x0,
- int32_t *x1, int32_t *y0, int32_t *y1,
- int shift)
-{
- /* This function uses
- * 2x 56 bit registers Q,
- * 4x 48 bit registers P
- * 3x integers
- * 2x address pointers,
- */
- ae_f64 a;
- ae_f64 b;
- ae_valign u;
- ae_f32x2 d0;
- ae_f32x2 d1;
- ae_f16x4 coefs;
- int i;
- ae_f32x2 *dp;
- ae_f16x4 *coefp = fir->coef;
- const int taps_div_4 = fir->taps >> 2;
- const int inc = 2 * sizeof(int32_t);
-
- /* Write samples to delay */
- AE_S32_L_XC((ae_int32)*x0, fir->rwp, -sizeof(int32_t));
- dp = (ae_f32x2 *)fir->rwp;
- AE_S32_L_XC((ae_int32)*x1, fir->rwp, -sizeof(int32_t));
-
- /* Note: If the next function is converted to handle two samples
- * per call the data load can be done with single instruction
- * AE_LP24X2F_C(data2, dp, sizeof(ae_p24x2f));
- */
- a = AE_ZERO64();
- b = AE_ZERO64();
-
- /* Prime the coefficients stream */
- u = AE_LA64_PP(coefp);
-
- /* Load two data samples and pack to d0 to data2_h and
- * d1 to data2_l.
- */
- AE_L32X2_XC(d0, dp, inc);
- for (i = 0; i < taps_div_4; i++) {
- /* Load four coefficients. Coef_3 contains tap h[n],
- * coef_2 contains h[n+1], coef_1 contains h[n+2], and
- * coef_0 contains h[n+3];
- */
- AE_LA16X4_IP(coefs, u, coefp);
-
- /* Load two data samples. Upper part d1_h is x[n+1] and
- * lower part d1_l is x[n].
- */
- AE_L32X2_XC(d1, dp, inc);
-
- /* Quad MAC (HH)
- * b += d0_h * coefs_3 + d0_l * coefs_2
- * a += d0_l * coefs_3 + d1_h * coefs_2
- */
- AE_MULAFD32X16X2_FIR_HH(b, a, d0, d1, coefs);
- d0 = d1;
-
- /* Repeat the same for next two taps and increase coefp. */
- AE_L32X2_XC(d1, dp, inc);
-
- /* Quad MAC (HL)
- * b += d0_h * coefs_1 + d0_l * coefs_0
- * a += d0_l * coefs_1 + d1_h * coefs_0
- */
- AE_MULAFD32X16X2_FIR_HL(b, a, d0, d1, coefs);
- d0 = d1;
- }
-
- /* Do scaling shifts and store sample. */
- b = AE_SLAA64S(b, shift);
- a = AE_SLAA64S(a, shift);
- AE_S32_L_I(AE_ROUND32F48SSYM(b), (ae_int32 *)y1, 0);
- AE_S32_L_I(AE_ROUND32F48SSYM(a), (ae_int32 *)y0, 0);
-}
-
-#endif
-#endif
diff --git a/src/audio/host.c b/src/audio/host.c
deleted file mode 100644
index 9ef59a3..0000000
--- a/src/audio/host.c
+++ /dev/null
@@ -1,785 +0,0 @@
-/*
- * Copyright (c) 2016, Intel Corporation
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- * * Redistributions of source code must retain the above copyright
- * notice, this list of conditions and the following disclaimer.
- * * Redistributions in binary form must reproduce the above copyright
- * notice, this list of conditions and the following disclaimer in the
- * documentation and/or other materials provided with the distribution.
- * * Neither the name of the Intel Corporation nor the
- * names of its contributors may be used to endorse or promote products
- * derived from this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
- * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
- * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
- * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
- * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
- * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
- * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
- * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
- * POSSIBILITY OF SUCH DAMAGE.
- *
- * Author: Liam Girdwood <liam.r.girdwood@linux.intel.com>
- * Keyon Jie <yang.jie@linux.intel.com>
- */
-
-#include <stdint.h>
-#include <stdbool.h>
-#include <stddef.h>
-#include <errno.h>
-#include <sof/sof.h>
-#include <sof/lock.h>
-#include <sof/list.h>
-#include <sof/stream.h>
-#include <sof/alloc.h>
-#include <sof/trace.h>
-#include <sof/dma.h>
-#include <sof/ipc.h>
-#include <sof/wait.h>
-#include <sof/audio/component.h>
-#include <sof/audio/pipeline.h>
-#include <platform/dma.h>
-#include <arch/cache.h>
-#include <uapi/ipc.h>
-
-#define trace_host(__e) trace_event(TRACE_CLASS_HOST, __e)
-#define tracev_host(__e) tracev_event(TRACE_CLASS_HOST, __e)
-#define trace_host_error(__e) trace_error(TRACE_CLASS_HOST, __e)
-
-struct hc_buf {
- /* host buffer info */
- struct list_item elem_list;
- struct list_item *current;
- uint32_t current_end;
-};
-
-/**
- * \brief Host component data.
- *
- * Host reports local position in the host buffer every params.host_period_bytes
- * if the latter is != 0. report_pos is used to track progress since the last
- * multiple of host_period_bytes.
- *
- * host_size is the host buffer size (in bytes) specified in the IPC parameters.
- */
-struct host_data {
- /* local DMA config */
- struct dma *dma;
- int chan;
- struct dma_sg_config config;
- completion_t complete;
- struct comp_buffer *dma_buffer;
-
- uint32_t period_bytes; /**< Size of a single period (in bytes) */
- uint32_t period_count; /**< Number of periods */
- uint32_t pointer_init;
-
- /* host position reporting related */
- uint32_t host_size; /**< Host buffer size (in bytes) */
- uint32_t report_pos; /**< Position in current report period */
- uint32_t local_pos; /**< Local position in host buffer */
-
- /* local and host DMA buffer info */
-#if !defined CONFIG_DMA_GW
- struct hc_buf host;
- struct hc_buf local;
- /* pointers set during params to host or local above */
- struct hc_buf *source;
- struct hc_buf *sink;
- uint32_t split_remaining;
- uint32_t next_inc;
-#endif
-
- /* stream info */
- struct sof_ipc_stream_posn posn; /* TODO: update this */
-};
-
-static int host_stop(struct comp_dev *dev);
-static int host_copy_int(struct comp_dev *dev, bool preload_run);
-
-#if !defined CONFIG_DMA_GW
-
-static inline struct dma_sg_elem *next_buffer(struct hc_buf *hc)
-{
- struct dma_sg_elem *elem;
-
- if (list_item_is_last(hc->current, &hc->elem_list))
- elem = list_first_item(&hc->elem_list, struct dma_sg_elem, list);
- else
- elem = list_first_item(hc->current, struct dma_sg_elem, list);
-
- hc->current = &elem->list;
- return elem;
-}
-
-#endif
-
-/*
- * Host period copy between DSP and host DMA completion.
- * This is called by DMA driver every time when DMA completes its current
- * transfer between host and DSP. The host memory is not guaranteed to be
- * continuous and also not guaranteed to have a period/buffer size that is a
- * multiple of the DSP period size. This means we must check we do not
- * overflow host period/buffer/page boundaries on each transfer and split the
- * DMA transfer if we do overflow.
- */
-static void host_dma_cb(void *data, uint32_t type, struct dma_sg_elem *next)
-{
- struct comp_dev *dev = (struct comp_dev *)data;
- struct host_data *hd = comp_get_drvdata(dev);
- struct dma_sg_elem *local_elem;
-#if !defined CONFIG_DMA_GW
- struct dma_sg_elem *source_elem;
- struct dma_sg_elem *sink_elem;
- uint32_t next_size;
- uint32_t need_copy = 0;
- uint32_t period_bytes = hd->period_bytes;
-#endif
-
- local_elem = list_first_item(&hd->config.elem_list,
- struct dma_sg_elem, list);
-
- tracev_host("irq");
-
- if (dev->params.direction == SOF_IPC_STREAM_PLAYBACK)
- /* recalc available buffer space */
- comp_update_buffer_produce(hd->dma_buffer, local_elem->size);
- else
- /* recalc available buffer space */
- comp_update_buffer_consume(hd->dma_buffer, local_elem->size);
-
- dev->position += local_elem->size;
-
- /* new local period, update host buffer position blks
- * local_pos is queried by the ops.potision() API
- */
- hd->local_pos += local_elem->size;
-
- /* buffer overlap, hard code host buffer size at the moment ? */
- if (hd->local_pos >= hd->host_size)
- hd->local_pos = 0;
-
- /* NO_IRQ mode if host_period_size == 0 */
- if (dev->params.host_period_bytes != 0) {
- hd->report_pos += local_elem->size;
-
- /* send IPC message to driver if needed */
- if (hd->report_pos >= dev->params.host_period_bytes) {
- hd->report_pos = 0;
-
- /* send timestamped position to host
- * (updates position first, by calling ops.position())
- */
- pipeline_get_timestamp(dev->pipeline, dev, &hd->posn);
- ipc_stream_send_position(dev, &hd->posn);
- }
- }
-
-#if !defined CONFIG_DMA_GW
- /* update src and dest positions and check for overflow */
- local_elem->src += local_elem->size;
- local_elem->dest += local_elem->size;
- if (local_elem->src == hd->source->current_end) {
- /* end of elem, so use next */
-
- source_elem = next_buffer(hd->source);
- hd->source->current_end = source_elem->src + source_elem->size;
- local_elem->src = source_elem->src;
- }
- if (local_elem->dest == hd->sink->current_end) {
- /* end of elem, so use next */
-
- sink_elem = next_buffer(hd->sink);
- hd->sink->current_end = sink_elem->dest + sink_elem->size;
- local_elem->dest = sink_elem->dest;
- }
-
- /* calc size of next transfer */
- next_size = period_bytes;
- if (local_elem->src + next_size > hd->source->current_end)
- next_size = hd->source->current_end - local_elem->src;
- if (local_elem->dest + next_size > hd->sink->current_end)
- next_size = hd->sink->current_end - local_elem->dest;
-
- /* are we dealing with a split transfer ? */
- if (!hd->split_remaining) {
-
- /* no, is next transfer split ? */
- if (next_size != period_bytes)
- hd->split_remaining = period_bytes - next_size;
- } else {
-
- /* yes, than calc transfer size */
- need_copy = 1;
- next_size = next_size < hd->split_remaining ?
- next_size : hd->split_remaining;
- hd->split_remaining -= next_size;
- }
- local_elem->size = next_size;
-
- /* schedule immediate split transfer if needed */
- if (need_copy) {
- next->src = local_elem->src;
- next->dest = local_elem->dest;
- next->size = local_elem->size;
- return;
- } else
- next->size = DMA_RELOAD_END;
-
- /* let any waiters know we have completed */
- wait_completed(&hd->complete);
-#endif
-}
-
-static int create_local_elems(struct comp_dev *dev)
-{
- struct host_data *hd = comp_get_drvdata(dev);
- struct dma_sg_elem *e;
- struct list_item *elist;
- struct list_item *tlist;
- int i;
-
- /* TODO: simplify elem storage by using an array */
- for (i = 0; i < hd->period_count; i++) {
- /* allocate new host DMA elem and add it to our list */
- e = rzalloc(RZONE_RUNTIME, SOF_MEM_CAPS_RAM, sizeof(*e));
- if (e == NULL)
- goto unwind;
-
- if (dev->params.direction == SOF_IPC_STREAM_PLAYBACK)
- e->dest = (uintptr_t)(hd->dma_buffer->addr) +
- i * hd->period_bytes;
- else
- e->src = (uintptr_t)(hd->dma_buffer->addr) +
- i * hd->period_bytes;
-
- e->size = hd->period_bytes;
-#if defined CONFIG_DMA_GW
- list_item_append(&e->list, &hd->config.elem_list);
-#else
- list_item_append(&e->list, &hd->local.elem_list);
-#endif
- }
-
- return 0;
-
-unwind:
-#if defined CONFIG_DMA_GW
- list_for_item_safe(elist, tlist, &hd->config.elem_list) {
-#else
- list_for_item_safe(elist, tlist, &hd->local.elem_list) {
-#endif
- e = container_of(elist, struct dma_sg_elem, list);
- list_item_del(&e->list);
- rfree(e);
- }
-
- trace_host_error("el0");
- return -ENOMEM;
-}
-
-/**
- * \brief Command handler.
- * \param[in,out] dev Device
- * \param[in] cmd Command
- * \return 0 if successful, error code otherwise.
- *
- * Used to pass standard and bespoke commands (with data) to component.
- * This function is common for all dma types, with one exception:
- * dw-dma is run on demand, so no start()/stop() is issued.
- */
-static int host_trigger(struct comp_dev *dev, int cmd)
-{
- struct host_data *hd = comp_get_drvdata(dev);
- int ret = 0;
-
- trace_host("trg");
-
- ret = comp_set_state(dev, cmd);
- if (ret < 0)
- goto out;
-
- switch (cmd) {
- case COMP_TRIGGER_STOP:
- ret = host_stop(dev);
- /* fall through */
- case COMP_TRIGGER_XRUN:
-/* TODO: add attribute to dma interface and do run-time if() here */
-#if defined CONFIG_DMA_GW
- ret = dma_stop(hd->dma, hd->chan);
-#endif
- break;
- case COMP_TRIGGER_START:
-#if defined CONFIG_DMA_GW
- ret = dma_start(hd->dma, hd->chan);
- if (ret < 0) {
- trace_host_error("TsF");
- trace_error_value(ret);
- goto out;
- }
-#endif
- /* preload first playback period for preloader task */
- if (dev->params.direction == SOF_IPC_STREAM_PLAYBACK) {
- if (!hd->pointer_init) {
- ret = host_copy_int(dev, true);
-
- if (ret == dev->frames)
- ret = 0;
- // wait for completion ?
-
- hd->pointer_init = 1;
- }
- }
- break;
- default:
- break;
- }
-
-out:
- return ret;
-}
-
-static struct comp_dev *host_new(struct sof_ipc_comp *comp)
-{
- struct comp_dev *dev;
- struct host_data *hd;
- struct sof_ipc_comp_host *host;
- struct sof_ipc_comp_host *ipc_host = (struct sof_ipc_comp_host *)comp;
- uint32_t dir, caps, dma_dev;
-#if !defined CONFIG_DMA_GW
- struct dma_sg_elem *elem = NULL;
-#endif
-
- trace_host("new");
-
- dev = rzalloc(RZONE_RUNTIME, SOF_MEM_CAPS_RAM,
- COMP_SIZE(struct sof_ipc_comp_host));
- if (dev == NULL)
- return NULL;
-
- host = (struct sof_ipc_comp_host *)&dev->comp;
- memcpy(host, ipc_host, sizeof(struct sof_ipc_comp_host));
-
- hd = rzalloc(RZONE_RUNTIME, SOF_MEM_CAPS_RAM, sizeof(*hd));
- if (hd == NULL) {
- rfree(dev);
- return NULL;
- }
-
- comp_set_drvdata(dev, hd);
-
- /* request HDA DMA with shared access privilege */
- if (ipc_host->direction == SOF_IPC_STREAM_PLAYBACK)
- dir = DMA_DIR_HMEM_TO_LMEM;
- else
- dir = DMA_DIR_LMEM_TO_HMEM;
-
- caps = 0;
- dma_dev = DMA_DEV_HOST;
- hd->dma = dma_get(dir, caps, dma_dev, DMA_ACCESS_SHARED);
- if (hd->dma == NULL) {
- trace_host_error("eDM");
- goto error;
- }
-
- /* init buffer elems */
- list_init(&hd->config.elem_list);
-#if !defined CONFIG_DMA_GW
- list_init(&hd->host.elem_list);
- list_init(&hd->local.elem_list);
-
- elem = rzalloc(RZONE_RUNTIME, SOF_MEM_CAPS_RAM, sizeof(*elem));
- if (!elem)
- goto error;
- list_item_prepend(&elem->list, &hd->config.elem_list);
-#endif
-
- /* init posn data. TODO: other fields */
- hd->posn.comp_id = comp->id;
- hd->pointer_init = 0;
- dev->state = COMP_STATE_READY;
- dev->is_dma_connected = 1;
- return dev;
-
-error:
-#if !defined CONFIG_DMA_GW
- rfree(elem);
-#endif
- rfree(hd);
- rfree(dev);
- return NULL;
-}
-
-static void host_free(struct comp_dev *dev)
-{
- struct host_data *hd = comp_get_drvdata(dev);
- struct dma_sg_elem *elem;
-
- trace_host("fre");
-
- elem = list_first_item(&hd->config.elem_list,
- struct dma_sg_elem, list);
-
-#if !defined CONFIG_DMA_GW
- dma_channel_put(hd->dma, hd->chan);
-#endif
-
- rfree(elem);
- rfree(hd);
- rfree(dev);
-}
-
-#if !defined CONFIG_DMA_GW
-static int host_elements_reset(struct comp_dev *dev)
-{
- struct host_data *hd = comp_get_drvdata(dev);
- struct dma_sg_elem *source_elem;
- struct dma_sg_elem *sink_elem;
- struct dma_sg_elem *local_elem;
-
- /* setup elem to point to first source elem */
- source_elem = list_first_item(&hd->source->elem_list,
- struct dma_sg_elem, list);
- hd->source->current = &source_elem->list;
- hd->source->current_end = source_elem->src + source_elem->size;
-
- /* setup elem to point to first sink elem */
- sink_elem = list_first_item(&hd->sink->elem_list,
- struct dma_sg_elem, list);
- hd->sink->current = &sink_elem->list;
- hd->sink->current_end = sink_elem->dest + sink_elem->size;
-
- /* local element */
- local_elem = list_first_item(&hd->config.elem_list,
- struct dma_sg_elem, list);
- local_elem->dest = sink_elem->dest;
- local_elem->size = hd->period_bytes;
- local_elem->src = source_elem->src;
- hd->next_inc = hd->period_bytes;
-
- return 0;
-}
-#endif
-
-/* configure the DMA params and descriptors for host buffer IO */
-static int host_params(struct comp_dev *dev)
-{
- struct host_data *hd = comp_get_drvdata(dev);
- struct sof_ipc_comp_config *cconfig = COMP_GET_CONFIG(dev);
- struct dma_sg_config *config = &hd->config;
- uint32_t buffer_size;
- int err;
-
- trace_host("par");
-
- /* host params always installed by pipeline IPC */
- hd->host_size = dev->params.buffer.size;
-
- /* determine source and sink buffer elems */
- if (dev->params.direction == SOF_IPC_STREAM_PLAYBACK) {
-#if !defined CONFIG_DMA_GW
- hd->source = &hd->host;
- hd->sink = &hd->local;
-#endif
- hd->dma_buffer = list_first_item(&dev->bsink_list,
- struct comp_buffer, source_list);
-
- config->direction = DMA_DIR_HMEM_TO_LMEM;
- hd->period_count = cconfig->periods_sink;
- } else {
-#if !defined CONFIG_DMA_GW
- hd->source = &hd->local;
- hd->sink = &hd->host;
-#endif
- hd->dma_buffer = list_first_item(&dev->bsource_list,
- struct comp_buffer, sink_list);
-
- config->direction = DMA_DIR_LMEM_TO_HMEM;
- hd->period_count = cconfig->periods_source;
- }
-
- /* validate period count */
- if (hd->period_count == 0) {
- trace_host_error("eS0");
- return -EINVAL;
- }
-
- /* calculate period size based on config */
- hd->period_bytes = dev->frames * comp_frame_bytes(dev);
- if (hd->period_bytes == 0) {
- trace_host_error("eS1");
- return -EINVAL;
- }
-
- /* resize the buffer if space is available to align with period size */
- buffer_size = hd->period_count * hd->period_bytes;
- err = buffer_set_size(hd->dma_buffer, buffer_size);
- if (err < 0) {
- trace_host_error("eSz");
- trace_error_value(buffer_size);
- return err;
- }
-
- /* component buffer size must be divisor of host buffer size */
- if (hd->host_size % hd->period_bytes) {
- trace_comp_error("eHB");
- trace_error_value(hd->host_size);
- trace_error_value(hd->period_bytes);
- return -EINVAL;
- }
-
- /* create SG DMA elems for local DMA buffer */
- err = create_local_elems(dev);
- if (err < 0)
- return err;
-
- /* set up DMA configuration - copy in sample bytes. */
- config->src_width = comp_sample_bytes(dev);
- config->dest_width = comp_sample_bytes(dev);
- config->cyclic = 0;
-
-#if !defined CONFIG_DMA_GW
- host_elements_reset(dev);
-#endif
-
- dev->params.stream_tag -= 1;
- /* get DMA channel from DMAC
- * note: stream_tag is ignored by dw-dma
- */
- hd->chan = dma_channel_get(hd->dma, dev->params.stream_tag);
- if (hd->chan < 0) {
- trace_host_error("eDC");
- return -ENODEV;
- }
-#if defined CONFIG_DMA_GW
- err = dma_set_config(hd->dma, hd->chan, &hd->config);
- if (err < 0) {
- trace_host_error("eDc");
- dma_channel_put(hd->dma, hd->chan);
- return err;
- }
-#endif
- /* set up callback */
- dma_set_cb(hd->dma, hd->chan, DMA_IRQ_TYPE_LLIST,
- host_dma_cb,
- dev);
- return 0;
-}
-
-static int host_prepare(struct comp_dev *dev)
-{
- struct host_data *hd = comp_get_drvdata(dev);
- int ret;
-
- trace_host("pre");
-
- ret = comp_set_state(dev, COMP_TRIGGER_PREPARE);
- if (ret < 0)
- return ret;
-
- hd->local_pos = 0;
- hd->report_pos = 0;
-#if !defined CONFIG_DMA_GW
- hd->split_remaining = 0;
-#endif
- hd->pointer_init = 0;
- dev->position = 0;
-
- return 0;
-}
-
-static int host_pointer_reset(struct comp_dev *dev)
-{
- struct host_data *hd = comp_get_drvdata(dev);
-
- /* reset buffer pointers */
- hd->local_pos = 0;
- hd->report_pos = 0;
- dev->position = 0;
-
- return 0;
-}
-
-static int host_stop(struct comp_dev *dev)
-{
- return 0;
-}
-
-static int host_position(struct comp_dev *dev,
- struct sof_ipc_stream_posn *posn)
-{
- struct host_data *hd = comp_get_drvdata(dev);
-
- /* TODO: improve accuracy by adding current DMA position */
- posn->host_posn = hd->local_pos;
-
- return 0;
-}
-
-#if !defined CONFIG_DMA_GW
-static int host_buffer(struct comp_dev *dev, struct dma_sg_elem *elem,
- uint32_t host_size)
-{
- struct host_data *hd = comp_get_drvdata(dev);
- struct dma_sg_elem *e;
-
- /* allocate new host DMA elem and add it to our list */
- e = rzalloc(RZONE_RUNTIME, SOF_MEM_CAPS_RAM, sizeof(*e));
- if (e == NULL)
- return -ENOMEM;
-
- *e = *elem;
-
- list_item_append(&e->list, &hd->host.elem_list);
- return 0;
-}
-#endif
-
-static int host_reset(struct comp_dev *dev)
-{
- struct host_data *hd = comp_get_drvdata(dev);
- struct dma_sg_elem *e;
- struct list_item *elist;
- struct list_item *tlist;
-
- trace_host("res");
-
-#if !defined CONFIG_DMA_GW
- /* free all host DMA elements */
- list_for_item_safe(elist, tlist, &hd->host.elem_list) {
- e = container_of(elist, struct dma_sg_elem, list);
- list_item_del(&e->list);
- rfree(e);
- }
-
- /* free all local DMA elements */
- list_for_item_safe(elist, tlist, &hd->local.elem_list) {
- e = container_of(elist, struct dma_sg_elem, list);
- list_item_del(&e->list);
- rfree(e);
- }
-#endif
-
-#if defined CONFIG_DMA_GW
- dma_stop(hd->dma, hd->chan);
- dma_channel_put(hd->dma, hd->chan);
-
- e = list_first_item(&hd->config.elem_list,
- struct dma_sg_elem, list);
- /*
- * here free dma_sg_elem those allocated in create_local_elems(),
- * we should keep header and the first local elem after reset (but only
- * for dw-dma since hda-dma allocates the full list again)
- */
- list_for_item_safe(elist, tlist, &e->list) {
- e = container_of(elist, struct dma_sg_elem, list);
-#if !defined CONFIG_DMA_GW
- /* should not free the header, finished */
- if (elist == &hd->config.elem_list)
- break;
-#endif
- list_item_del(&e->list);
- rfree(e);
- }
-#endif
-
- host_pointer_reset(dev);
- hd->pointer_init = 0;
-#if !defined CONFIG_DMA_GW
- hd->source = NULL;
- hd->sink = NULL;
-#endif
- dev->state = COMP_STATE_READY;
-
- return 0;
-}
-
-/* copy and process stream data from source to sink buffers */
-static int host_copy(struct comp_dev *dev)
-{
- return host_copy_int(dev, false);
-}
-
-static int host_copy_int(struct comp_dev *dev, bool preload_run)
-{
- struct host_data *hd = comp_get_drvdata(dev);
- struct dma_sg_elem *local_elem;
- int ret;
-
- tracev_host("cpy");
-
- if (dev->state != COMP_STATE_ACTIVE)
- return 0;
-
- local_elem = list_first_item(&hd->config.elem_list,
- struct dma_sg_elem, list);
-
- /* enough free or avail to copy ? */
- if (dev->params.direction == SOF_IPC_STREAM_PLAYBACK) {
- if (hd->dma_buffer->free < local_elem->size) {
- /* buffer is enough avail, just return. */
- trace_host("Bea");
- return 0;
- }
- } else {
-
- if (hd->dma_buffer->avail < local_elem->size) {
- /* buffer is enough empty, just return. */
- trace_host("Bee");
- return 0;
- }
- }
-/* TODO: this could be run-time if() based on the same attribute
- * as in the host_trigger().
- */
-#if defined CONFIG_DMA_GW
- /* tell gateway to copy another period */
- ret = dma_copy(hd->dma, hd->chan, hd->period_bytes,
- preload_run ? DMA_COPY_PRELOAD : 0);
- if (ret < 0)
- goto out;
-
- /* note: update() moved to callback */
-#else
- /* do DMA transfer */
- ret = dma_set_config(hd->dma, hd->chan, &hd->config);
- if (ret < 0)
- goto out;
- ret = dma_start(hd->dma, hd->chan);
- if (ret < 0)
- goto out;
-#endif
- return dev->frames;
-out:
- trace_host_error("CpF");
- trace_error_value(ret);
- return ret;
-}
-
-struct comp_driver comp_host = {
- .type = SOF_COMP_HOST,
- .ops = {
- .new = host_new,
- .free = host_free,
- .params = host_params,
- .reset = host_reset,
- .trigger = host_trigger,
- .copy = host_copy,
- .prepare = host_prepare,
-#if !defined CONFIG_DMA_GW
- .host_buffer = host_buffer,
-#endif
- .position = host_position,
- },
-};
-
-void sys_comp_host_init(void)
-{
- comp_register(&comp_host);
-}
diff --git a/src/audio/iir.c b/src/audio/iir.c
deleted file mode 100644
index a56a962..0000000
--- a/src/audio/iir.c
+++ /dev/null
@@ -1,163 +0,0 @@
-/*
- * Copyright (c) 2017, Intel Corporation
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- * * Redistributions of source code must retain the above copyright
- * notice, this list of conditions and the following disclaimer.
- * * Redistributions in binary form must reproduce the above copyright
- * notice, this list of conditions and the following disclaimer in the
- * documentation and/or other materials provided with the distribution.
- * * Neither the name of the Intel Corporation nor the
- * names of its contributors may be used to endorse or promote products
- * derived from this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
- * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
- * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
- * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
- * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
- * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
- * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
- * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
- * POSSIBILITY OF SUCH DAMAGE.
- *
- * Author: Seppo Ingalsuo <seppo.ingalsuo@linux.intel.com>
- * Liam Girdwood <liam.r.girdwood@linux.intel.com>
- * Keyon Jie <yang.jie@linux.intel.com>
- */
-
-#include <stdint.h>
-#include <stddef.h>
-#include <errno.h>
-
-#ifdef MODULE_TEST
-#include <stdio.h>
-#endif
-
-#include <sof/audio/format.h>
-#include "iir.h"
-
-/*
- * Direct form II transposed second order filter block (biquad)
- *
- * +----+ +---+ +-------+
- * X(z) ---o--->| b0 |---> + -------------o--->| g |--->| shift |---> Y(z)
- * | +----+ ^ | +---+ +-------+
- * | | |
- * | +------+ |
- * | | z^-1 | |
- * | +------+ |
- * | ^ |
- * | +----+ | +----+ |
- * o--->| b1 |---> + <---| a1 |---o
- * | +----+ ^ +----+ |
- * | | |
- * | +------+ |
- * | | z^-1 | |
- * | +------+ |
- * | ^ |
- * | +----+ | +----+ |
- * o--->| b2 |---> + <---| a2 |---+
- * +----+ +----+
- *
- */
-
-/* Series DF2T IIR */
-
-/* 32 bit data, 32 bit coefficients and 64 bit state variables */
-
-int32_t iir_df2t(struct iir_state_df2t *iir, int32_t x)
-{
- int32_t in;
- int32_t tmp;
- int64_t acc;
- int32_t out = 0;
- int i;
- int j;
- int d = 0; /* Index to delays */
- int c = 2; /* Index to coefficient a2 */
-
- /* Coefficients order in coef[] is {a2, a1, b2, b1, b0, shift, gain} */
- in = x;
- for (j = 0; j < iir->biquads; j += iir->biquads_in_series) {
- for (i = 0; i < iir->biquads_in_series; i++) {
- /* Compute output: Delay is Q3.61
- * Q2.30 x Q1.31 -> Q3.61
- * Shift Q3.61 to Q3.31 with rounding
- */
- acc = ((int64_t) iir->coef[c + 4]) * in + iir->delay[d];
- tmp = (int32_t) Q_SHIFT_RND(acc, 61, 31);
-
- /* Compute 1st delay */
- acc = iir->delay[d + 1];
- acc += ((int64_t) iir->coef[c + 3]) * in; /* Coef b1 */
- acc += ((int64_t) iir->coef[c + 1]) * tmp; /* Coef a1 */
- iir->delay[d] = acc;
-
- /* Compute 2nd delay */
- acc = ((int64_t) iir->coef[c + 2]) * in; /* Coef b2 */
- acc += ((int64_t) iir->coef[c]) * tmp; /* Coef a2 */
- iir->delay[d + 1] = acc;
-
- /* Gain, output shift, prepare for next biquad
- * Q2.14 x Q1.31 -> Q3.45, shift too Q3.31 and saturate
- */
- acc = ((int64_t) iir->coef[c + 6]) * tmp; /* Gain */
- acc = Q_SHIFT_RND(acc, 45 + iir->coef[c + 5], 31);
- in = sat_int32(acc);
- c += 7; /* Next coefficients section */
- d += 2; /* Next biquad delays */
- }
- /* Output of previous section is in variable in */
- out = sat_int32((int64_t) out + in);
- }
- return out;
-}
-
-size_t iir_init_coef_df2t(struct iir_state_df2t *iir, int32_t config[])
-{
- iir->mute = 0;
- iir->biquads = (int) config[0];
- iir->biquads_in_series = (int) config[1];
- iir->coef = &config[0]; /* TODO: Could change this to config[2] */
- iir->delay = NULL;
-
- if ((iir->biquads > IIR_DF2T_BIQUADS_MAX) || (iir->biquads < 1)) {
- iir_reset_df2t(iir);
- return -EINVAL;
- }
-
- return 2 * iir->biquads * sizeof(int64_t); /* Needed delay line size */
-}
-
-void iir_init_delay_df2t(struct iir_state_df2t *iir, int64_t **delay)
-{
- iir->delay = *delay; /* Delay line of this IIR */
- *delay += 2 * iir->biquads; /* Point to next IIR delay line start */
-
-}
-
-void iir_mute_df2t(struct iir_state_df2t *iir)
-{
- iir->mute = 1;
-}
-
-void iir_unmute_df2t(struct iir_state_df2t *iir)
-{
- iir->mute = 0;
-}
-
-void iir_reset_df2t(struct iir_state_df2t *iir)
-{
- iir->mute = 1;
- iir->biquads = 0;
- iir->biquads_in_series = 0;
- iir->coef = NULL;
- /* Note: May need to know the beginning of dynamic allocation after so
- * omitting setting iir->delay to NULL.
- */
-}
diff --git a/src/audio/iir.h b/src/audio/iir.h
deleted file mode 100644
index 0de275a..0000000
--- a/src/audio/iir.h
+++ /dev/null
@@ -1,75 +0,0 @@
-/*
- * Copyright (c) 2017, Intel Corporation
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- * * Redistributions of source code must retain the above copyright
- * notice, this list of conditions and the following disclaimer.
- * * Redistributions in binary form must reproduce the above copyright
- * notice, this list of conditions and the following disclaimer in the
- * documentation and/or other materials provided with the distribution.
- * * Neither the name of the Intel Corporation nor the
- * names of its contributors may be used to endorse or promote products
- * derived from this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
- * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
- * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
- * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
- * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
- * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
- * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
- * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
- * POSSIBILITY OF SUCH DAMAGE.
- *
- * Author: Seppo Ingalsuo <seppo.ingalsuo@linux.intel.com>
- * Liam Girdwood <liam.r.girdwood@linux.intel.com>
- * Keyon Jie <yang.jie@linux.intel.com>
- */
-
-/* A full 22th order equalizer with 11 biquads cover octave bands 1-11 in
- * in the 0 - 20 kHz bandwidth.
- */
-#define IIR_DF2T_BIQUADS_MAX 11
-
-struct iir_state_df2t {
- int mute; /* Set to 1 to mute EQ output, 0 otherwise */
- int biquads; /* Number of IIR 2nd order sections total */
- int biquads_in_series; /* Number of IIR 2nd order sections in series*/
- int32_t *coef; /* Pointer to IIR coefficients */
- int64_t *delay; /* Pointer to IIR delay line */
-};
-
-#define NHEADER_DF2T 2
-
-struct iir_header_df2t {
- int32_t num_sections;
- int32_t num_sections_in_series;
-};
-
-#define NBIQUAD_DF2T 7
-
-struct iir_biquad_df2t {
- int32_t a2; /* Q2.30 */
- int32_t a1; /* Q2.30 */
- int32_t b2; /* Q2.30 */
- int32_t b1; /* Q2.30 */
- int32_t b0; /* Q2.30 */
- int32_t output_shift; /* Number of right shifts */
- int32_t output_gain; /* Q2.14 */
-};
-
-int32_t iir_df2t(struct iir_state_df2t *iir, int32_t x);
-
-size_t iir_init_coef_df2t(struct iir_state_df2t *iir, int32_t config[]);
-
-void iir_init_delay_df2t(struct iir_state_df2t *iir, int64_t **delay);
-
-void iir_mute_df2t(struct iir_state_df2t *iir);
-
-void iir_unmute_df2t(struct iir_state_df2t *iir);
-
-void iir_reset_df2t(struct iir_state_df2t *iir);
diff --git a/src/audio/mixer.c b/src/audio/mixer.c
deleted file mode 100644
index dee02ae..0000000
--- a/src/audio/mixer.c
+++ /dev/null
@@ -1,356 +0,0 @@
-/*
- * Copyright (c) 2016, Intel Corporation
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- * * Redistributions of source code must retain the above copyright
- * notice, this list of conditions and the following disclaimer.
- * * Redistributions in binary form must reproduce the above copyright
- * notice, this list of conditions and the following disclaimer in the
- * documentation and/or other materials provided with the distribution.
- * * Neither the name of the Intel Corporation nor the
- * names of its contributors may be used to endorse or promote products
- * derived from this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
- * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
- * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
- * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
- * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
- * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
- * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
- * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
- * POSSIBILITY OF SUCH DAMAGE.
- *
- * Author: Liam Girdwood <liam.r.girdwood@linux.intel.com>
- * Keyon Jie <yang.jie@linux.intel.com>
- */
-
-#include <stdint.h>
-#include <stddef.h>
-#include <sof/lock.h>
-#include <sof/list.h>
-#include <sof/stream.h>
-#include <sof/alloc.h>
-#include <sof/audio/component.h>
-#include <sof/audio/format.h>
-
-#define trace_mixer(__e) trace_event(TRACE_CLASS_MIXER, __e)
-#define tracev_mixer(__e) tracev_event(TRACE_CLASS_MIXER, __e)
-#define trace_mixer_error(__e) trace_error(TRACE_CLASS_MIXER, __e)
-
-/* mixer component private data */
-struct mixer_data {
- uint32_t period_bytes;
- void (*mix_func)(struct comp_dev *dev, struct comp_buffer *sink,
- struct comp_buffer **sources, uint32_t count, uint32_t frames);
-};
-
-/* mix N PCM source streams to one sink stream */
-static void mix_n(struct comp_dev *dev, struct comp_buffer *sink,
- struct comp_buffer **sources, uint32_t num_sources, uint32_t frames)
-{
- int32_t *src;
- int32_t *dest = sink->w_ptr;
- int32_t count;
- int64_t val[2];
- int i;
- int j;
-
- count = frames * dev->params.channels;
-
- for (i = 0; i < count; i += 2) {
- val[0] = 0;
- val[1] = 0;
- for (j = 0; j < num_sources; j++) {
- src = sources[j]->r_ptr;
- val[0] += src[i];
- val[1] += src[i + 1];
- }
-
- /* Saturate to 32 bits */
- dest[i] = sat_int32(val[0]);
- dest[i + 1] = sat_int32(val[1]);
- }
-}
-
-static struct comp_dev *mixer_new(struct sof_ipc_comp *comp)
-{
- struct comp_dev *dev;
- struct sof_ipc_comp_mixer *mixer;
- struct sof_ipc_comp_mixer *ipc_mixer =
- (struct sof_ipc_comp_mixer *)comp;
- struct mixer_data *md;
-
- trace_mixer("new");
- dev = rzalloc(RZONE_RUNTIME, SOF_MEM_CAPS_RAM,
- COMP_SIZE(struct sof_ipc_comp_mixer));
- if (dev == NULL)
- return NULL;
-
- mixer = (struct sof_ipc_comp_mixer *)&dev->comp;
- memcpy(mixer, ipc_mixer, sizeof(struct sof_ipc_comp_mixer));
-
- md = rzalloc(RZONE_RUNTIME, SOF_MEM_CAPS_RAM, sizeof(*md));
- if (md == NULL) {
- rfree(dev);
- return NULL;
- }
-
- comp_set_drvdata(dev, md);
- dev->state = COMP_STATE_READY;
- return dev;
-}
-
-static void mixer_free(struct comp_dev *dev)
-{
- struct mixer_data *md = comp_get_drvdata(dev);
-
- trace_mixer("fre");
-
- rfree(md);
- rfree(dev);
-}
-
-/* set component audio stream parameters */
-static int mixer_params(struct comp_dev *dev)
-{
- struct mixer_data *md = comp_get_drvdata(dev);
- struct sof_ipc_comp_config *config = COMP_GET_CONFIG(dev);
- struct comp_buffer *sink;
- int ret;
-
- trace_mixer("par");
-
- /* calculate frame size based on config */
- dev->frame_bytes = comp_frame_bytes(dev);
- if (dev->frame_bytes == 0) {
- trace_mixer_error("mx1");
- return -EINVAL;
- }
-
- /* calculate period size based on config */
- md->period_bytes = dev->frames * dev->frame_bytes;
- if (md->period_bytes == 0) {
- trace_mixer_error("mx2");
- return -EINVAL;
- }
-
- sink = list_first_item(&dev->bsink_list, struct comp_buffer, source_list);
-
- /* set downstream buffer size */
- ret = buffer_set_size(sink, md->period_bytes * config->periods_sink);
- if (ret < 0) {
- trace_mixer_error("mx3");
- return ret;
- }
-
- return 0;
-}
-
-static int mixer_source_status_count(struct comp_dev *mixer, uint32_t status)
-{
- struct comp_buffer *source;
- struct list_item * blist;
- int count = 0;
-
- /* count source with state == status */
- list_for_item(blist, &mixer->bsource_list) {
- source = container_of(blist, struct comp_buffer, sink_list);
- if (source->source->state == status)
- count++;
- }
-
- return count;
-}
-
-static inline int mixer_sink_status(struct comp_dev *mixer)
-{
- struct comp_buffer *sink;
-
- sink = list_first_item(&mixer->bsink_list, struct comp_buffer,
- source_list);
- return sink->sink->state;
-}
-
-/* used to pass standard and bespoke commands (with data) to component */
-static int mixer_trigger(struct comp_dev *dev, int cmd)
-{
- int ret;
-
- trace_mixer("trg");
-
- ret = comp_set_state(dev, cmd);
- if (ret < 0)
- return ret;
-
- switch(cmd) {
- case COMP_TRIGGER_START:
- case COMP_TRIGGER_RELEASE:
- if (mixer_sink_status(dev) == COMP_STATE_ACTIVE)
- return 1; /* no need to go downstream */
- break;
- case COMP_TRIGGER_PAUSE:
- case COMP_TRIGGER_STOP:
- if (mixer_source_status_count(dev, COMP_STATE_ACTIVE) > 0) {
- dev->state = COMP_STATE_ACTIVE;
- return 1; /* no need to go downstream */
- }
- break;
- default:
- break;
- }
-
- return 0; /* send cmd downstream */
-}
-
-/*
- * Mix N source PCM streams to one sink PCM stream. Frames copied is constant.
- */
-static int mixer_copy(struct comp_dev *dev)
-{
- struct mixer_data *md = comp_get_drvdata(dev);
- struct comp_buffer *sink;
- struct comp_buffer *sources[PLATFORM_MAX_STREAMS];
- struct comp_buffer *source;
- struct list_item *blist;
- int32_t i = 0;
- int32_t num_mix_sources = 0;
- int res;
-
- tracev_mixer("cpy");
-
- sink = list_first_item(&dev->bsink_list, struct comp_buffer, source_list);
-
- /* calculate the highest runtime component status between input streams */
- list_for_item(blist, &dev->bsource_list) {
- source = container_of(blist, struct comp_buffer, sink_list);
-
- /* only mix the sources with the same state with mixer */
- if (source->source->state == dev->state)
- sources[num_mix_sources++] = source;
-
- /* too many sources ? */
- if (num_mix_sources == PLATFORM_MAX_STREAMS - 1)
- return 0;
- }
-
- /* don't have any work if all sources are inactive */
- if (num_mix_sources == 0)
- return 0;
-
- /* make sure no sources have underruns */
- for (i = 0; i < num_mix_sources; i++) {
-
- /* make sure source component buffer has enough data available
- * and that the sink component buffer has enough free bytes
- * for copy. Also check for XRUNs */
- res = comp_buffer_can_copy_bytes(sources[i], sink, md->period_bytes);
- if (res < 0) {
- trace_mixer_error("xru");
- comp_underrun(dev, sources[i], sources[i]->avail,
- md->period_bytes);
- } else if (res > 0) {
- trace_mixer_error("xro");
- comp_overrun(dev, sources[i], sink->free,
- md->period_bytes);
- }
- }
-
- /* mix streams */
- md->mix_func(dev, sink, sources, i, dev->frames);
-
- /* update source buffer pointers for overflow */
- for (i = --num_mix_sources; i >= 0; i--)
- comp_update_buffer_consume(sources[i], md->period_bytes);
-
- /* calc new free and available */
- comp_update_buffer_produce(sink, md->period_bytes);
-
- /* number of frames sent downstream */
- return dev->frames;
-}
-
-static int mixer_reset(struct comp_dev *dev)
-{
- struct list_item * blist;
- struct comp_buffer *source;
-
- trace_mixer("res");
-
- list_for_item(blist, &dev->bsource_list) {
- source = container_of(blist, struct comp_buffer, sink_list);
- /* only mix the sources with the same state with mixer*/
- if (source->source->state > COMP_STATE_READY)
- return 1; /* should not reset the downstream components */
- }
-
- comp_set_state(dev, COMP_TRIGGER_RESET);
- return 0;
-}
-
-/*
- * Prepare the mixer. The mixer may already be running at this point with other
- * sources. Make sure we only prepare the "prepared" source streams and not
- * the active or inactive sources.
- *
- * We should also make sure that we propagate the prepare call to downstream
- * if downstream is not currently active.
- */
-static int mixer_prepare(struct comp_dev *dev)
-{
- struct mixer_data *md = comp_get_drvdata(dev);
- struct list_item * blist;
- struct comp_buffer *source;
- int downstream = 0;
- int ret;
-
- trace_mixer("pre");
-
- /* does mixer already have active source streams ? */
- if (dev->state != COMP_STATE_ACTIVE) {
-
- /* currently inactive so setup mixer */
- md->mix_func = mix_n;
- dev->state = COMP_STATE_PREPARE;
-
- ret = comp_set_state(dev, COMP_TRIGGER_PREPARE);
- if (ret < 0)
- return ret;
- }
-
- /* check each mixer source state */
- list_for_item(blist, &dev->bsource_list) {
- source = container_of(blist, struct comp_buffer, sink_list);
-
- /* only prepare downstream if we have no active sources */
- if (source->source->state == COMP_STATE_PAUSED ||
- source->source->state == COMP_STATE_ACTIVE) {
- downstream = 1;
- }
- }
-
- /* prepare downstream */
- return downstream;
-}
-
-struct comp_driver comp_mixer = {
- .type = SOF_COMP_MIXER,
- .ops = {
- .new = mixer_new,
- .free = mixer_free,
- .params = mixer_params,
- .prepare = mixer_prepare,
- .trigger = mixer_trigger,
- .copy = mixer_copy,
- .reset = mixer_reset,
- },
-};
-
-void sys_comp_mixer_init(void)
-{
- comp_register(&comp_mixer);
-}
diff --git a/src/audio/mux.c b/src/audio/mux.c
deleted file mode 100644
index e96c467..0000000
--- a/src/audio/mux.c
+++ /dev/null
@@ -1,102 +0,0 @@
-/*
- * Copyright (c) 2016, Intel Corporation
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- * * Redistributions of source code must retain the above copyright
- * notice, this list of conditions and the following disclaimer.
- * * Redistributions in binary form must reproduce the above copyright
- * notice, this list of conditions and the following disclaimer in the
- * documentation and/or other materials provided with the distribution.
- * * Neither the name of the Intel Corporation nor the
- * names of its contributors may be used to endorse or promote products
- * derived from this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
- * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
- * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
- * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
- * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
- * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
- * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
- * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
- * POSSIBILITY OF SUCH DAMAGE.
- *
- * Author: Liam Girdwood <liam.r.girdwood@linux.intel.com>
- */
-
-#include <stdint.h>
-#include <stddef.h>
-#include <sof/lock.h>
-#include <sof/list.h>
-#include <sof/stream.h>
-#include <sof/audio/component.h>
-
-/* tracing */
-#define trace_mux(__e) trace_event(TRACE_CLASS_MUX, __e)
-#define trace_mux_error(__e) trace_error(TRACE_CLASS_MUX, __e)
-#define tracev_mux(__e) tracev_event(TRACE_CLASS_MUX, __e)
-
-static struct comp_dev *mux_new(struct sof_ipc_comp *comp)
-{
- trace_mux("new");
-
- return NULL;
-}
-
-static void mux_free(struct comp_dev *dev)
-{
-
-}
-
-/* set component audio stream parameters */
-static int mux_params(struct comp_dev *dev)
-{
-
- return 0;
-}
-
-/* used to pass standard and bespoke commands (with data) to component */
-static int mux_cmd(struct comp_dev *dev, int cmd, void *data)
-{
- /* mux will use buffer "connected" status */
- return 0;
-}
-
-/* copy and process stream data from source to sink buffers */
-static int mux_copy(struct comp_dev *dev)
-{
-
- return 0;
-}
-
-static int mux_reset(struct comp_dev *dev)
-{
- return 0;
-}
-
-static int mux_prepare(struct comp_dev *dev)
-{
- return 0;
-}
-
-struct comp_driver comp_mux = {
- .type = SOF_COMP_MUX,
- .ops = {
- .new = mux_new,
- .free = mux_free,
- .params = mux_params,
- .cmd = mux_cmd,
- .copy = mux_copy,
- .prepare = mux_prepare,
- .reset = mux_reset,
- },
-};
-
-void sys_comp_mux_init(void)
-{
- comp_register(&comp_mux);
-}
diff --git a/src/audio/pipeline.c b/src/audio/pipeline.c
deleted file mode 100644
index ee8cf68..0000000
--- a/src/audio/pipeline.c
+++ /dev/null
@@ -1,1179 +0,0 @@
-/*
- * Copyright (c) 2016, Intel Corporation
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- * * Redistributions of source code must retain the above copyright
- * notice, this list of conditions and the following disclaimer.
- * * Redistributions in binary form must reproduce the above copyright
- * notice, this list of conditions and the following disclaimer in the
- * documentation and/or other materials provided with the distribution.
- * * Neither the name of the Intel Corporation nor the
- * names of its contributors may be used to endorse or promote products
- * derived from this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
- * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
- * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
- * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
- * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
- * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
- * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
- * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
- * POSSIBILITY OF SUCH DAMAGE.
- *
- * Author: Liam Girdwood <liam.r.girdwood@linux.intel.com>
- * Keyon Jie <yang.jie@linux.intel.com>
- */
-
-#include <stdint.h>
-#include <stddef.h>
-#include <errno.h>
-#include <sof/sof.h>
-#include <sof/lock.h>
-#include <sof/list.h>
-#include <sof/stream.h>
-#include <sof/alloc.h>
-#include <sof/debug.h>
-#include <sof/ipc.h>
-#include <sof/lock.h>
-#include <platform/timer.h>
-#include <platform/platform.h>
-#include <sof/audio/component.h>
-#include <sof/audio/pipeline.h>
-
-struct pipeline_data {
- spinlock_t lock;
-};
-
-/* generic operation data used by op graph walk */
-struct op_data {
- int op;
- struct pipeline *p;
- struct stream_params *params;
- int cmd;
- void *cmd_data;
-};
-
-static struct pipeline_data *pipe_data;
-static void pipeline_task(void *arg);
-
-/* call op on all upstream components - locks held by caller */
-static void connect_upstream(struct pipeline *p, struct comp_dev *start,
- struct comp_dev *current)
-{
- struct list_item *clist;
-
- tracev_value(current->comp.id);
-
- /* complete component init */
- current->pipeline = p;
- current->frames = p->ipc_pipe.frames_per_sched;
-
- /* we are an endpoint if we have 0 source components */
- if (list_is_empty(¤t->bsource_list)) {
- current->is_endpoint = 1;
-
- /* pipeline source comp is current */
- p->source_comp = current;
- return;
- }
-
- /* now run this operation upstream */
- list_for_item(clist, ¤t->bsource_list) {
- struct comp_buffer *buffer;
-
- buffer = container_of(clist, struct comp_buffer, sink_list);
-
- /* don't go upstream if this source is from another pipeline */
- if (buffer->source->comp.pipeline_id != p->ipc_pipe.pipeline_id) {
-
- /* pipeline source comp is current unless we go upstream */
- p->source_comp = current;
-
- continue;
- }
-
- connect_upstream(p, start, buffer->source);
- }
-
-}
-
-static void connect_downstream(struct pipeline *p, struct comp_dev *start,
- struct comp_dev *current)
-{
- struct list_item *clist;
-
- tracev_value(current->comp.id);
-
- /* complete component init */
- current->pipeline = p;
- current->frames = p->ipc_pipe.frames_per_sched;
-
- /* we are an endpoint if we have 0 sink components */
- if (list_is_empty(¤t->bsink_list)) {
- current->is_endpoint = 1;
- return;
- }
-
- /* now run this operation downstream */
- list_for_item(clist, ¤t->bsink_list) {
- struct comp_buffer *buffer;
-
- buffer = container_of(clist, struct comp_buffer, source_list);
-
- /* don't go downstream if this sink is from another pipeline */
- if (buffer->sink->comp.pipeline_id != p->ipc_pipe.pipeline_id)
- continue;
-
- connect_downstream(p, start, buffer->sink);
- }
-}
-
-/* call op on all upstream components - locks held by caller */
-static void disconnect_upstream(struct pipeline *p, struct comp_dev *start,
- struct comp_dev *current)
-{
- struct list_item *clist;
-
- tracev_value(current->comp.id);
-
- /* complete component init */
- current->pipeline = NULL;
-
- /* now run this operation upstream */
- list_for_item(clist, ¤t->bsource_list) {
- struct comp_buffer *buffer;
-
- buffer = container_of(clist, struct comp_buffer, sink_list);
-
- /* don't go upstream if this source is from another pipeline */
- if (buffer->source->comp.pipeline_id != p->ipc_pipe.pipeline_id)
- continue;
-
- disconnect_upstream(p, start, buffer->source);
- }
-
- /* disconnect source from buffer */
- spin_lock(¤t->lock);
- list_item_del(¤t->bsource_list);
- spin_unlock(¤t->lock);
-}
-
-static void disconnect_downstream(struct pipeline *p, struct comp_dev *start,
- struct comp_dev *current)
-{
- struct list_item *clist;
-
- tracev_value(current->comp.id);
-
- /* complete component init */
- current->pipeline = NULL;
-
- /* now run this operation downstream */
- list_for_item(clist, ¤t->bsink_list) {
- struct comp_buffer *buffer;
-
- buffer = container_of(clist, struct comp_buffer, source_list);
-
- /* don't go downstream if this sink is from another pipeline */
- if (buffer->sink->comp.pipeline_id != p->ipc_pipe.pipeline_id)
- continue;
-
- disconnect_downstream(p, start, buffer->sink);
- }
-
- /* disconnect source from buffer */
- spin_lock(¤t->lock);
- list_item_del(¤t->bsink_list);
- spin_unlock(¤t->lock);
-}
-
-/* update pipeline state based on cmd */
-static void pipeline_trigger_sched_comp(struct pipeline *p,
- struct comp_dev *comp, int cmd)
-{
- /* only required by the scheduling component */
- if (p->sched_comp != comp)
- return;
-
- switch (cmd) {
- case COMP_TRIGGER_PAUSE:
- case COMP_TRIGGER_STOP:
- pipeline_schedule_cancel(p);
- p->status = COMP_STATE_PAUSED;
- break;
- case COMP_TRIGGER_RELEASE:
- case COMP_TRIGGER_START:
- p->xrun_bytes = 0;
-
- /* playback pipelines need scheduled now, capture pipelines are
- * scheduled once their initial DMA period is filled by the DAI
- * or in resume process
- */
- if (comp->params.direction == SOF_IPC_STREAM_PLAYBACK ||
- p->status == COMP_STATE_PAUSED) {
-
- /* pipelines are either scheduled by timers or DAI/DMA interrupts */
- if (p->ipc_pipe.timer) {
- /* timer - schedule initial copy */
- pipeline_schedule_copy(p, 0);
- } else {
- /* DAI - schedule initial pipeline fill when next idle */
- pipeline_schedule_copy_idle(p);
- }
- }
- p->status = COMP_STATE_ACTIVE;
- break;
- case COMP_TRIGGER_SUSPEND:
- case COMP_TRIGGER_RESUME:
- case COMP_TRIGGER_XRUN:
- default:
- break;
- }
-}
-
-/* create new pipeline - returns pipeline id or negative error */
-struct pipeline *pipeline_new(struct sof_ipc_pipe_new *pipe_desc,
- struct comp_dev *cd)
-{
- struct pipeline *p;
-
- trace_pipe("new");
-
- /* allocate new pipeline */
- p = rzalloc(RZONE_RUNTIME, SOF_MEM_CAPS_RAM, sizeof(*p));
- if (p == NULL) {
- trace_pipe_error("ePN");
- return NULL;
- }
-
- /* init pipeline */
- p->sched_comp = cd;
- p->status = COMP_STATE_INIT;
- schedule_task_init(&p->pipe_task, pipeline_task, p);
- schedule_task_config(&p->pipe_task, pipe_desc->priority,
- pipe_desc->core);
- list_init(&p->comp_list);
- list_init(&p->buffer_list);
- spinlock_init(&p->lock);
- memcpy(&p->ipc_pipe, pipe_desc, sizeof(*pipe_desc));
-
- return p;
-}
-
-/* pipelines must be inactive */
-int pipeline_free(struct pipeline *p)
-{
- trace_pipe("fre");
-
- /* make sure we are not in use */
- if (p->sched_comp->state > COMP_STATE_READY) {
- trace_pipe_error("epb");
- return -EBUSY;
- }
-
- /* remove from any scheduling */
- schedule_task_free(&p->pipe_task);
-
- /* disconnect components */
- disconnect_downstream(p, p->sched_comp, p->sched_comp);
- disconnect_upstream(p, p->sched_comp, p->sched_comp);
-
- /* now free the pipeline */
- rfree(p);
-
- return 0;
-}
-
-int pipeline_complete(struct pipeline *p)
-{
- /* now walk downstream and upstream form "start" component and
- complete component task and pipeline init */
-
- trace_pipe("com");
- trace_value(p->ipc_pipe.pipeline_id);
-
- /* check whether pipeline is already complete */
- if (p->status != COMP_STATE_INIT) {
- trace_pipe_error("epc");
- return -EINVAL;
- }
-
- connect_downstream(p, p->sched_comp, p->sched_comp);
- connect_upstream(p, p->sched_comp, p->sched_comp);
- p->status = COMP_STATE_READY;
- return 0;
-}
-
-/* connect component -> buffer */
-int pipeline_comp_connect(struct pipeline *p, struct comp_dev *source_comp,
- struct comp_buffer *sink_buffer)
-{
- trace_pipe("cnc");
-
- /* connect source to buffer */
- spin_lock(&source_comp->lock);
- list_item_prepend(&sink_buffer->source_list, &source_comp->bsink_list);
- sink_buffer->source = source_comp;
- spin_unlock(&source_comp->lock);
-
- /* connect the components */
- if (sink_buffer->source && sink_buffer->sink)
- sink_buffer->connected = 1;
-
- tracev_value((source_comp->comp.id << 16) |
- sink_buffer->ipc_buffer.comp.id);
- return 0;
-}
-
-/* connect buffer -> component */
-int pipeline_buffer_connect(struct pipeline *p,
- struct comp_buffer *source_buffer, struct comp_dev *sink_comp)
-{
- trace_pipe("cbc");
-
- /* connect sink to buffer */
- spin_lock(&sink_comp->lock);
- list_item_prepend(&source_buffer->sink_list, &sink_comp->bsource_list);
- source_buffer->sink = sink_comp;
- spin_unlock(&sink_comp->lock);
-
- /* connect the components */
- if (source_buffer->source && source_buffer->sink)
- source_buffer->connected = 1;
-
- tracev_value((source_buffer->ipc_buffer.comp.id << 16) |
- sink_comp->comp.id);
- return 0;
-}
-
-/* Walk the graph downstream from start component in any pipeline and perform
- * the operation on each component. Graph walk is stopped on any component
- * returning an error ( < 0) and returns immediately. Components returning a
- * positive error code also stop the graph walk on that branch causing the
- * walk to return to a shallower level in the graph. */
-static int component_op_downstream(struct op_data *op_data,
- struct comp_dev *start, struct comp_dev *current,
- struct comp_dev *previous)
-{
- struct list_item *clist;
- int err = 0;
-
- tracev_pipe("CO-");
- tracev_value(current->comp.id);
-
- /* do operation on this component */
- switch (op_data->op) {
- case COMP_OPS_PARAMS:
-
- /* don't do any params downstream if current is running */
- if (current->state == COMP_STATE_ACTIVE)
- return 0;
-
- /* send params to the component */
- if (current != start && previous != NULL)
- comp_install_params(current, previous);
- err = comp_params(current);
- break;
- case COMP_OPS_TRIGGER:
- /* send command to the component and update pipeline state */
- err = comp_trigger(current, op_data->cmd);
- if (err == 0)
- pipeline_trigger_sched_comp(current->pipeline, current,
- op_data->cmd);
- break;
- case COMP_OPS_PREPARE:
- /* prepare the component */
- err = comp_prepare(current);
- break;
- case COMP_OPS_RESET:
- /* component should reset and free resources */
- err = comp_reset(current);
- break;
- case COMP_OPS_BUFFER: /* handled by other API call */
- default:
- trace_pipe_error("eOi");
- trace_error_value(op_data->op);
- return -EINVAL;
- }
-
- /* don't walk the graph any further if this component fails */
- if (err < 0) {
- trace_pipe_error("eOp");
- return err;
- } else if (err > 0 || (current != start && current->is_endpoint)) {
- /* we finish walking the graph if we reach the DAI or component is
- * currently active and configured already (err > 0).
- */
- tracev_pipe("C-D");
- return err;
- }
-
- /* now run this operation downstream */
- list_for_item(clist, ¤t->bsink_list) {
- struct comp_buffer *buffer;
-
- buffer = container_of(clist, struct comp_buffer, source_list);
-
- /* don't go downstream if this component is not connected */
- if (!buffer->connected)
- continue;
-
- err = component_op_downstream(op_data, start, buffer->sink,
- current);
- if (err < 0)
- break;
- }
-
- return err;
-}
-
-/* Walk the graph upstream from start component in any pipeline and perform
- * the operation on each component. Graph walk is stopped on any component
- * returning an error ( < 0) and returns immediately. Components returning a
- * positive error code also stop the graph walk on that branch causing the
- * walk to return to a shallower level in the graph. */
-static int component_op_upstream(struct op_data *op_data,
- struct comp_dev *start, struct comp_dev *current,
- struct comp_dev *previous)
-{
- struct list_item *clist;
- int err = 0;
-
- tracev_pipe("CO+");
- tracev_value(current->comp.id);
-
- /* do operation on this component */
- switch (op_data->op) {
- case COMP_OPS_PARAMS:
-
- /* don't do any params upstream if current is running */
- if (current->state == COMP_STATE_ACTIVE)
- return 0;
-
- /* send params to the component */
- if (current != start && previous != NULL)
- comp_install_params(current, previous);
- err = comp_params(current);
- break;
- case COMP_OPS_TRIGGER:
- /* send command to the component and update pipeline state */
- err = comp_trigger(current, op_data->cmd);
- if (err == 0)
- pipeline_trigger_sched_comp(current->pipeline, current,
- op_data->cmd);
- break;
- case COMP_OPS_PREPARE:
- /* prepare the component */
- err = comp_prepare(current);
- break;
- case COMP_OPS_RESET:
- /* component should reset and free resources */
- err = comp_reset(current);
- break;
- case COMP_OPS_BUFFER: /* handled by other API call */
- default:
- trace_pipe_error("eOi");
- trace_error_value(op_data->op);
- return -EINVAL;
- }
-
- /* don't walk the graph any further if this component fails */
- if (err < 0) {
- trace_pipe_error("eOp");
- return err;
- } else if (err > 0 || (current != start && current->is_endpoint)) {
- tracev_pipe("C+D");
- return 0;
- }
-
- /* now run this operation upstream */
- list_for_item(clist, ¤t->bsource_list) {
- struct comp_buffer *buffer;
-
- buffer = container_of(clist, struct comp_buffer, sink_list);
-
- /* don't go upstream if this component is not connected */
- if (!buffer->connected)
- continue;
-
- err = component_op_upstream(op_data, start, buffer->source,
- current);
- if (err < 0)
- break;
- }
-
- return err;
-}
-
-/* walk the graph upstream from start component in any pipeline and prepare
- * the buffer context for each inactive component */
-static int component_prepare_buffers_upstream(struct comp_dev *start,
- struct comp_dev *current, struct comp_buffer *buffer)
-{
- struct list_item *clist;
- int err = 0;
-
- /* component copy/process to downstream */
- if (current != start && buffer != NULL) {
-
- buffer_reset_pos(buffer);
-
- /* stop going downstream if we reach an end point in this pipeline */
- if (current->is_endpoint)
- return 0;
- }
-
- /* travel uptream to sink end point(s) */
- list_for_item(clist, ¤t->bsource_list) {
-
- buffer = container_of(clist, struct comp_buffer, sink_list);
-
- /* dont go upstream if this component is not connected or active */
- if (!buffer->connected || buffer->source->state == COMP_STATE_ACTIVE)
- continue;
-
- /* continue downstream */
- err = component_prepare_buffers_upstream(start, buffer->source,
- buffer);
- if (err < 0) {
- trace_pipe_error("eBD");
- break;
- }
- }
-
- /* return back downstream */
- return err;
-}
-
-/* walk the graph downstream from start component in any pipeline and prepare
- * the buffer context for each inactive component */
-static int component_prepare_buffers_downstream(struct comp_dev *start,
- struct comp_dev *current, struct comp_buffer *buffer)
-{
- struct list_item *clist;
- int err = 0;
-
- /* component copy/process to downstream */
- if (current != start && buffer != NULL) {
-
- buffer_reset_pos(buffer);
-
- /* stop going downstream if we reach an end point in this pipeline */
- if (current->is_endpoint)
- return 0;
- }
-
- /* travel downstream to sink end point(s) */
- list_for_item(clist, ¤t->bsink_list) {
-
- buffer = container_of(clist, struct comp_buffer, source_list);
-
- /* dont go downstream if this component is not connected or active */
- if (!buffer->connected || buffer->sink->state == COMP_STATE_ACTIVE)
- continue;
-
- /* continue downstream */
- err = component_prepare_buffers_downstream(start, buffer->sink,
- buffer);
- if (err < 0) {
- trace_pipe_error("eBD");
- break;
- }
- }
-
- /* return back upstream */
- return err;
-}
-
-/* prepare the pipeline for usage - preload host buffers here */
-int pipeline_prepare(struct pipeline *p, struct comp_dev *dev)
-{
- struct op_data op_data;
- int ret = -1;
- uint32_t flags;
-
- trace_pipe("pre");
-
- op_data.p = p;
- op_data.op = COMP_OPS_PREPARE;
-
- spin_lock_irq(&p->lock, flags);
-
- /* playback pipelines can be preloaded from host before trigger */
- if (dev->params.direction == SOF_IPC_STREAM_PLAYBACK) {
-
- ret = component_op_downstream(&op_data, dev, dev, NULL);
- if (ret < 0)
- goto out;
-
- /* set up reader and writer positions */
- component_prepare_buffers_downstream(dev, dev, NULL);
- } else {
- ret = component_op_upstream(&op_data, dev, dev, NULL);
- if (ret < 0)
- goto out;
-
- /* set up reader and writer positions */
- component_prepare_buffers_upstream(dev, dev, NULL);
- }
-
- p->status = COMP_STATE_PREPARE;
-out:
- spin_unlock_irq(&p->lock, flags);
- return ret;
-}
-
-/* send pipeline component/endpoint a command */
-int pipeline_trigger(struct pipeline *p, struct comp_dev *host, int cmd)
-{
- struct op_data op_data;
- int ret;
- uint32_t flags;
-
- trace_pipe("cmd");
-
- op_data.p = p;
- op_data.op = COMP_OPS_TRIGGER;
- op_data.cmd = cmd;
-
- spin_lock_irq(&p->lock, flags);
-
- if (host->params.direction == SOF_IPC_STREAM_PLAYBACK) {
- /* send cmd downstream from host to DAI */
- ret = component_op_downstream(&op_data, host, host, NULL);
- } else {
- /* send cmd upstream from host to DAI */
- ret = component_op_upstream(&op_data, host, host, NULL);
- }
-
- if (ret < 0) {
- trace_ipc_error("pc0");
- trace_error_value(host->comp.id);
- trace_error_value(cmd);
- }
-
- spin_unlock_irq(&p->lock, flags);
- return ret;
-}
-
-/*
- * Send pipeline component params from host to endpoints.
- * Params always start at host (PCM) and go downstream for playback and
- * upstream for capture.
- *
- * Playback params can be re-written by upstream components. e.g. upstream SRC
- * can change sample rate for all downstream components regardless of sample
- * rate from host.
- *
- * Capture params can be re-written by downstream components.
- *
- * Params are always modified in the direction of host PCM to DAI.
- */
-int pipeline_params(struct pipeline *p, struct comp_dev *host,
- struct sof_ipc_pcm_params *params)
-{
- struct op_data op_data;
- int ret;
- uint32_t flags;
-
- trace_pipe("Par");
-
- op_data.p = p;
- op_data.op = COMP_OPS_PARAMS;
-
- spin_lock_irq(&p->lock, flags);
-
- host->params = params->params;
-
- if (host->params.direction == SOF_IPC_STREAM_PLAYBACK) {
- /* send params downstream from host to DAI */
- ret = component_op_downstream(&op_data, host, host, NULL);
- } else {
- /* send params upstream from host to DAI */
- ret = component_op_upstream(&op_data, host, host, NULL);
- }
-
- if (ret < 0) {
- trace_ipc_error("pp0");
- trace_error_value(host->comp.id);
- }
-
- spin_unlock_irq(&p->lock, flags);
- return ret;
-}
-
-/* send pipeline component/endpoint params */
-int pipeline_reset(struct pipeline *p, struct comp_dev *host)
-{
- struct op_data op_data;
- int ret;
- uint32_t flags;
-
- trace_pipe("PRe");
-
- op_data.p = p;
- op_data.op = COMP_OPS_RESET;
-
- spin_lock_irq(&p->lock, flags);
-
- if (host->params.direction == SOF_IPC_STREAM_PLAYBACK) {
- /* send reset downstream from host to DAI */
- ret = component_op_downstream(&op_data, host, host, NULL);
- } else {
- /* send reset upstream from host to DAI */
- ret = component_op_upstream(&op_data, host, host, NULL);
- }
-
- if (ret < 0) {
- trace_ipc_error("pr0");
- trace_error_value(host->comp.id);
- }
-
- spin_unlock_irq(&p->lock, flags);
- return ret;
-}
-
-/*
- * Upstream Copy and Process.
- *
- * Copy period(s) from all upstream sources to this component. The period will
- * be copied and processed by each component from the upstream component
- * end point(s) to the downstream components in a single operation.
- * i.e. the period data is processed from upstream end points to downstream
- * "comp" recursively in a single call to this function.
- *
- * The copy operation is for this pipeline only (as pipelines are scheduled
- * individually) and it stops at pipeline endpoints (where a component has no
- * source or sink components) or where this pipeline joins another pipeline.
- */
-static int pipeline_copy_from_upstream(struct comp_dev *start,
- struct comp_dev *current)
-{
- struct list_item *clist;
- int err = 0;
-
- tracev_pipe("CP+");
- tracev_value(current->comp.id);
-
- /* stop going upstream if we reach an end point in this pipeline */
- if (current->is_endpoint && current != start)
- goto copy;
-
- /* travel upstream to source end point(s) */
- list_for_item(clist, ¤t->bsource_list) {
- struct comp_buffer *buffer;
-
- buffer = container_of(clist, struct comp_buffer, sink_list);
-
- /* don't go upstream if this component is not connected */
- if (!buffer->connected || buffer->source->state != COMP_STATE_ACTIVE)
- continue;
-
- /* don't go upstream if this source is from another pipeline */
- if (buffer->source->pipeline != current->pipeline)
- continue;
-
- /* continue upstream */
- err = pipeline_copy_from_upstream(start, buffer->source);
- if (err < 0) {
- trace_pipe_error("ePU");
- trace_error_value(current->comp.id);
- return err;
- }
- }
-
-copy:
- /* we are at the upstream end point component so copy the buffers */
- err = comp_copy(current);
-
- /* return back downstream */
- tracev_pipe("CD+");
- return err;
-}
-
-/*
- * Downstream Copy and Process.
- *
- * Copy period(s) from this component to all downstream sinks. The period will
- * be copied and processed by each component from this component to all
- * downstream end point component(s) in a single operation.
- * i.e. the period data is processed from this component to downstream
- * end points recursively in a single call to this function.
- *
- * The copy operation is for this pipeline only (as pipelines are scheduled
- * individually) and it stops at pipeline endpoints (where a component has no
- * source or sink components) or where this pipeline joins another pipeline.
- */
-static int pipeline_copy_to_downstream(struct comp_dev *start,
- struct comp_dev *current)
-{
- struct list_item *clist;
- int err = 0;
-
- tracev_pipe("CP-");
- tracev_value(current->comp.id);
-
- /* component copy/process to downstream */
- if (current != start) {
- err = comp_copy(current);
-
- /* stop going downstream if we reach an end point in this pipeline */
- if (current->is_endpoint)
- goto out;
- }
-
- /* travel downstream to sink end point(s) */
- list_for_item(clist, ¤t->bsink_list) {
- struct comp_buffer *buffer;
-
- buffer = container_of(clist, struct comp_buffer, source_list);
-
- /* don't go downstream if this component is not connected */
- if (!buffer->connected || buffer->sink->state != COMP_STATE_ACTIVE)
- continue;
-
- /* don't go downstream if this sink is from another pipeline */
- if (buffer->sink->pipeline != current->pipeline)
- continue;
-
- /* continue downstream */
- err = pipeline_copy_to_downstream(start, buffer->sink);
- if (err < 0) {
- trace_pipe_error("ePD");
- trace_error_value(current->comp.id);
- return err;
- }
- }
-
-out:
- /* return back upstream */
- tracev_pipe("CD-");
- return err;
-}
-
-/* walk the graph to downstream active components in any pipeline to find
- * the first active DAI and return it's timestamp.
- * TODO: consider pipeline with multiple DAIs
- */
-static int timestamp_downstream(struct comp_dev *start,
- struct comp_dev *current, struct sof_ipc_stream_posn *posn)
-{
- struct list_item *clist;
- int res = 0;
-
- /* is component a DAI endpoint ? */
- if (current != start) {
-
- /* go downstream if we are not endpoint */
- if (!current->is_endpoint)
- goto downstream;
-
- if (current->comp.type == SOF_COMP_DAI ||
- current->comp.type == SOF_COMP_SG_DAI) {
- platform_dai_timestamp(current, posn);
- return 1;
- }
- }
-
-downstream:
- /* travel downstream to sink end point(s) */
- list_for_item(clist, ¤t->bsink_list) {
- struct comp_buffer *buffer;
-
- buffer = container_of(clist, struct comp_buffer, source_list);
-
- /* don't go downstream if this component is not connected */
- if (!buffer->connected || buffer->sink->state != COMP_STATE_ACTIVE)
- continue;
-
- /* continue downstream */
- res = timestamp_downstream(start, buffer->sink, posn);
- if (res == 1)
- break;
- }
-
- /* return back upstream */
- return res;
-}
-
-/* walk the graph to upstream active components in any pipeline to find
- * the first active DAI and return it's timestamp.
- * TODO: consider pipeline with multiple DAIs
- */
-static int timestamp_upstream(struct comp_dev *start,
- struct comp_dev *current, struct sof_ipc_stream_posn *posn)
-{
- struct list_item *clist;
- int res = 0;
-
- /* is component a DAI endpoint ? */
- if (current != start) {
-
- /* go downstream if we are not endpoint */
- if (!current->is_endpoint)
- goto upstream;
-
- if (current->comp.type == SOF_COMP_DAI ||
- current->comp.type == SOF_COMP_SG_DAI) {
- platform_dai_timestamp(current, posn);
- return 1;
- }
- }
-
-
-upstream:
- /* travel upstream to source end point(s) */
- list_for_item(clist, ¤t->bsource_list) {
- struct comp_buffer *buffer;
-
- buffer = container_of(clist, struct comp_buffer, sink_list);
-
- /* don't go downstream if this component is not connected */
- if (!buffer->connected || buffer->source->state != COMP_STATE_ACTIVE)
- continue;
-
- /* continue downstream */
- res = timestamp_upstream(start, buffer->source, posn);
- if (res == 1)
- break;
- }
-
- /* return back upstream */
- return res;
-}
-
-/*
- * Get the timestamps for host and first active DAI found.
- */
-void pipeline_get_timestamp(struct pipeline *p, struct comp_dev *host,
- struct sof_ipc_stream_posn *posn)
-{
- platform_host_timestamp(host, posn);
-
- if (host->params.direction == SOF_IPC_STREAM_PLAYBACK) {
- timestamp_downstream(host, host, posn);
- } else {
- timestamp_upstream(host, host, posn);
- }
-}
-
-static void xrun(struct comp_dev *dev, void *data)
-{
- struct sof_ipc_stream_posn *posn = data;
-
- /* get host timestamps */
- platform_host_timestamp(dev, posn);
-
- /* send XRUN to host */
- ipc_stream_send_xrun(dev, posn);
-}
-
-
-/* walk the graph downstream from start component in any pipeline and run
- * function <func> for each component of type <type> */
-static void pipeline_for_each_downstream(struct pipeline *p,
- enum sof_comp_type type, struct comp_dev *current,
- void (*func)(struct comp_dev *, void *), void *data)
-{
- struct list_item *clist;
-
- if (current->comp.type == type)
- func(current, data);
-
- /* travel downstream to sink end point(s) */
- list_for_item(clist, ¤t->bsink_list) {
- struct comp_buffer *buffer;
-
- buffer = container_of(clist, struct comp_buffer, source_list);
-
- /* don't go downstream if this component is not connected */
- if (!buffer->connected)
- continue;
-
- /* continue downstream */
- pipeline_for_each_downstream(p, type, buffer->sink,
- func, data);
- }
-}
-
-/* walk the graph upstream from start component in any pipeline and run
- * function <func> for each component of type <type> */
-static void pipeline_for_each_upstream(struct pipeline *p,
- enum sof_comp_type type, struct comp_dev *current,
- void (*func)(struct comp_dev *, void *), void *data)
-{
- struct list_item *clist;
-
- if (current->comp.type == type)
- func(current, data);
-
- /* travel upstream to sink end point(s) */
- list_for_item(clist, ¤t->bsource_list) {
- struct comp_buffer *buffer;
-
- buffer = container_of(clist, struct comp_buffer, sink_list);
-
- /* don't go downstream if this component is not connected */
- if (!buffer->connected)
- continue;
-
- /* continue downstream */
- pipeline_for_each_upstream(p, type, buffer->source,
- func, data);
- }
-}
-
-/*
- * Send an XRUN to each host for this component.
- */
-void pipeline_xrun(struct pipeline *p, struct comp_dev *dev,
- int32_t bytes)
-{
- struct sof_ipc_stream_posn posn;
-
- /* don't flood host */
- if (p->xrun_bytes)
- return;
-
- /* only send when we are running */
- if (dev->state != COMP_STATE_ACTIVE)
- return;
-
- memset(&posn, 0, sizeof(posn));
- p->xrun_bytes = posn.xrun_size = bytes;
- posn.xrun_comp_id = dev->comp.id;
-
- if (dev->params.direction == SOF_IPC_STREAM_PLAYBACK) {
- pipeline_for_each_upstream(p, SOF_COMP_HOST, dev, xrun, &posn);
- } else {
- pipeline_for_each_downstream(p, SOF_COMP_HOST, dev, xrun, &posn);
- }
-}
-
-/* copy data from upstream source endpoints to downstream endpoints*/
-static int pipeline_copy(struct comp_dev *dev)
-{
- int err;
-
- err = pipeline_copy_from_upstream(dev, dev);
- if (err < 0)
- return err;
-
- err = pipeline_copy_to_downstream(dev, dev);
- if (err < 0)
- return err;
-
- return 0;
-}
-
-/* recover the pipeline from a XRUN condition */
-static int pipeline_xrun_recover(struct pipeline *p)
-{
- int ret;
-
- trace_pipe_error("pxr");
-
- /* notify all pipeline comps we are in XRUN */
- ret = pipeline_trigger(p, p->source_comp, COMP_TRIGGER_XRUN);
- if (ret < 0) {
- trace_pipe_error("px0");
- return ret;
- }
- p->xrun_bytes = 0;
-
- /* prepare the pipeline */
- ret = pipeline_prepare(p, p->source_comp);
- if (ret < 0) {
- trace_pipe_error("px1");
- return ret;
- }
-
- /* restart pipeline comps */
- ret = pipeline_trigger(p, p->source_comp, COMP_TRIGGER_START);
- if (ret < 0) {
- trace_pipe_error("px2");
- return ret;
- }
-
- /* for playback copy it here, because scheduling won't work
- * on this interrupt level
- */
- if (p->sched_comp->params.direction == SOF_IPC_STREAM_PLAYBACK) {
- ret = pipeline_copy(p->sched_comp);
- if (ret < 0) {
- trace_pipe_error("px3");
- return ret;
- }
- }
-
- return 0;
-}
-
-/* notify pipeline that this component requires buffers emptied/filled */
-void pipeline_schedule_copy(struct pipeline *p, uint64_t start)
-{
- if (p->sched_comp->state == COMP_STATE_ACTIVE)
- schedule_task(&p->pipe_task, start, p->ipc_pipe.deadline);
-}
-
-/* notify pipeline that this component requires buffers emptied/filled
- * when DSP is next idle. This is intended to be used to preload pipeline
- * buffers prior to trigger start. */
-void pipeline_schedule_copy_idle(struct pipeline *p)
-{
- schedule_task_idle(&p->pipe_task, p->ipc_pipe.deadline);
-}
-
-void pipeline_schedule_cancel(struct pipeline *p)
-{
- schedule_task_complete(&p->pipe_task);
-}
-
-static void pipeline_task(void *arg)
-{
- struct pipeline *p = arg;
- struct comp_dev *dev = p->sched_comp;
- int err;
-
- tracev_pipe("PWs");
-
- /* are we in xrun ? */
- if (p->xrun_bytes) {
- err = pipeline_xrun_recover(p);
- if (err < 0)
- return; /* failed - host will stop this pipeline */
- goto sched;
- }
-
- err = pipeline_copy(dev);
- if (err < 0) {
- err = pipeline_xrun_recover(p);
- if (err < 0)
- return; /* failed - host will stop this pipeline */
- }
-
-sched:
- tracev_pipe("PWe");
-
- /* now reschedule the task */
- /* TODO: add in scheduling cost and any timer drift */
- if (p->ipc_pipe.timer)
- pipeline_schedule_copy(p, p->ipc_pipe.deadline);
-}
-
-/* init pipeline */
-int pipeline_init(void)
-{
- trace_pipe("PIn");
-
- pipe_data = rzalloc(RZONE_RUNTIME, SOF_MEM_CAPS_RAM,
- sizeof(*pipe_data));
- spinlock_init(&pipe_data->lock);
-
- return 0;
-}
diff --git a/src/audio/pipeline_static.c b/src/audio/pipeline_static.c
deleted file mode 100644
index 5af5420..0000000
--- a/src/audio/pipeline_static.c
+++ /dev/null
@@ -1,446 +0,0 @@
-/*
- * Copyright (c) 2016, Intel Corporation
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- * * Redistributions of source code must retain the above copyright
- * notice, this list of conditions and the following disclaimer.
- * * Redistributions in binary form must reproduce the above copyright
- * notice, this list of conditions and the following disclaimer in the
- * documentation and/or other materials provided with the distribution.
- * * Neither the name of the Intel Corporation nor the
- * names of its contributors may be used to endorse or promote products
- * derived from this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
- * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
- * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
- * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
- * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
- * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
- * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
- * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
- * POSSIBILITY OF SUCH DAMAGE.
- *
- * Author: Liam Girdwood <liam.r.girdwood@linux.intel.com>
- * Keyon Jie <yang.jie@linux.intel.comel.com>
- *
- * Static pipeline definition. This will be the default platform pipeline
- * definition if no pipeline is specified by driver topology.
- */
-
-#include <stdint.h>
-#include <stddef.h>
-#include <sof/sof.h>
-#include <sof/lock.h>
-#include <sof/list.h>
-#include <sof/stream.h>
-#include <sof/dai.h>
-#include <sof/ipc.h>
-#include <platform/clk.h>
-#include <platform/platform.h>
-#include <sof/audio/component.h>
-#include <sof/audio/pipeline.h>
-
-
-/* 2 * 32 bit*/
-#define PLATFORM_INT_FRAME_SIZE 8
-/* 2 * 16 bit*/
-#define PLATFORM_HOST_FRAME_SIZE 4
-/* 2 * 24 (32) bit*/
-#define PLATFORM_DAI_FRAME_SIZE 8
-
-/* Platform Host DMA buffer config - these should align with DMA engine */
-#define PLAT_HOST_PERIOD_FRAMES 48 /* must be multiple of DMA burst size */
-#define PLAT_HOST_PERIODS 2 /* give enough latency for DMA refill */
-
-/* Platform Dev DMA buffer config - these should align with DMA engine */
-#define PLAT_DAI_PERIOD_FRAMES 48 /* must be multiple of DMA+DEV burst size */
-#define PLAT_DAI_PERIODS 2 /* give enough latency for DMA refill */
-#define PLAT_DAI_SCHED 1000 /* scheduling time in usecs */
-
-/* Platform internal buffer config - these should align with DMA engine */
-#define PLAT_INT_PERIOD_FRAMES 48 /* must be multiple of DMA+DEV burst size */
-#define PLAT_INT_PERIODS 2 /* give enough latency for DMA refill */
-
-/* default static pipeline SSP port - not used for dynamic pipes */
-#define PLATFORM_SSP_PORT 2
-
-/* default SSP stream format - need aligned with codec setting*/
-#define PLATFORM_SSP_STREAM_FORMAT SOF_IPC_FRAME_S24_4LE
-
-/*
- * Static Buffer Convenience Constructors.
- */
-#define SPIPE_BUFFER(bid, bsize) \
- {.comp.id = bid, .size = bsize}
-#define SPIPE_COMP_CONNECT(source, sink) \
- {.source_id = source, .sink_id = sink}
-
-/*
- * Static Component Convenience Constructors.
- */
-#define SPIPE_COMP(cid, ctype, csize) \
- {.id = cid, .type = ctype, .hdr.size = sizeof(struct csize)}
-#define SPIPE_HOST(scomp, hno_irq, hdmac, hchan, hconfig) \
- {.comp = scomp, .no_irq = hno_irq, \
- .dmac_config = hconfig}
-#define SPIPE_DAI(scomp, ddai_type, ddai_idx, ddmac, dchan, dconfig) \
- {.comp = scomp, .type = ddai_type, .dai_index = ddai_idx, \
- .dmac_config = dconfig}
-#define SPIPE_VOL(scomp, vmin, vmax) \
- {.comp = scomp, .min_value = vmin, .max_value = vmax}
-#define SPIPE_MIX(scomp) {.comp = scomp}
-#define SPIPE_SRC(scomp) {.comp = scomp}
-#define SPIPE_TONE(scomp) {.comp = scomp}
-
-/*
- * Static Pipeline Convenience Constructor
- */
-#define SPIPE_PIPE(pid, pcore, pdeadline, ppriority) \
- {.pipeline_id = pid, .core = pcore, .deadline = pdeadline, .priority = ppriority}
-#define SPIPE_PIPE_CONNECT(psource, bsource, bid, psink, bsink) \
- {.pipeline_source_id = psource, .comp_source_id = bsource, \
- .buffer_id = bid, .pipeline_sink_id = psink, .comp_sink_id = bsink}
-
-/*
- * Static pipeline container and constructor
- */
-
-struct scomps {
- struct sof_ipc_comp *comps;
- uint32_t num_comps;
-};
-
-#define SCOMP(ccomps) \
- {.comps = (struct sof_ipc_comp *)ccomps, .num_comps = ARRAY_SIZE(ccomps)}
-
-
-struct spipe {
- struct scomps *scomps;
- uint32_t num_scomps;
- struct sof_ipc_buffer *buffer;
- uint32_t num_buffers;
- struct sof_ipc_pipe_comp_connect *connect;
- uint32_t num_connections;
-};
-
-#define SPIPE(ncomp, sbuffer, sconnect) \
- {.scomps = ncomp, .num_scomps = ARRAY_SIZE(ncomp), \
- .buffer = sbuffer, .num_buffers = ARRAY_SIZE(sbuffer), \
- .connect = sconnect, .num_connections = ARRAY_SIZE(sconnect)}
-
-/*
- * Components used in static pipeline 0.
- */
-
-static struct sof_ipc_comp_host host_p0[] = {
- SPIPE_HOST(SPIPE_COMP(0, SOF_COMP_HOST, sof_ipc_comp_host), 0, 0, 1, 0), /* ID = 0 */
- SPIPE_HOST(SPIPE_COMP(2, SOF_COMP_HOST, sof_ipc_comp_host), 0, 0, 2, 0), /* ID = 2 */
- SPIPE_HOST(SPIPE_COMP(9, SOF_COMP_HOST, sof_ipc_comp_host), 0, 0, 3, 0), /* ID = 9 */
-};
-
-static struct sof_ipc_comp_volume volume_p0[] = {
- SPIPE_VOL(SPIPE_COMP(1, SOF_COMP_VOLUME, sof_ipc_comp_volume), 0, 0xffffffff),/* ID = 1 */
- SPIPE_VOL(SPIPE_COMP(3, SOF_COMP_VOLUME, sof_ipc_comp_volume), 0, 0xffffffff),/* ID = 3 */
- SPIPE_VOL(SPIPE_COMP(5, SOF_COMP_VOLUME, sof_ipc_comp_volume), 0, 0xffffffff),/* ID = 5 */
- SPIPE_VOL(SPIPE_COMP(8, SOF_COMP_VOLUME, sof_ipc_comp_volume), 0, 0xffffffff),/* ID = 8 */
-};
-
-static struct sof_ipc_comp_dai dai_p0[] = {
- SPIPE_DAI(SPIPE_COMP(6, SOF_COMP_DAI, sof_ipc_comp_dai),
- SOF_DAI_INTEL_SSP, PLATFORM_SSP_PORT, 1, 0, 0), /* ID = 6 */
- SPIPE_DAI(SPIPE_COMP(7, SOF_COMP_DAI, sof_ipc_comp_dai),
- SOF_DAI_INTEL_SSP, PLATFORM_SSP_PORT, 1, 1, 0), /* ID = 7 */
-};
-
-static struct sof_ipc_comp_mixer mixer_p0[] = {
- SPIPE_MIX(SPIPE_COMP(4, SOF_COMP_MIXER, sof_ipc_comp_mixer)), /* ID = 4 */
-};
-
-static struct scomps pipe0_scomps[] = {
- SCOMP(host_p0),
- SCOMP(volume_p0),
- SCOMP(dai_p0),
- SCOMP(mixer_p0),
-};
-
-/*
- * Components used in static pipeline 1.
- */
-
-static struct sof_ipc_comp_host host_p1[] = {
- SPIPE_HOST(SPIPE_COMP(10, SOF_COMP_HOST, sof_ipc_comp_host), 0, 0, 4, 0), /* ID = 10 */
-};
-
-static struct sof_ipc_comp_volume volume_p1[] = {
- SPIPE_VOL(SPIPE_COMP(12, SOF_COMP_VOLUME, sof_ipc_comp_volume), 0, 0xffffffff),/* ID = 12 */
-};
-
-static struct sof_ipc_comp_src src_p1[] = {
- SPIPE_SRC(SPIPE_COMP(11, SOF_COMP_SRC, sof_ipc_comp_src)), /* ID = 11 */
-};
-
-static struct scomps pipe1_scomps[] = {
- SCOMP(host_p1),
- SCOMP(volume_p1),
- SCOMP(src_p1),
-};
-
-/*
- * Components used in static pipeline 2.
- */
-
-static struct sof_ipc_comp_tone tone_p2[] = {
- SPIPE_TONE(SPIPE_COMP(13, SOF_COMP_HOST, sof_ipc_comp_tone)), /* ID = 13 */
-};
-
-static struct sof_ipc_comp_volume volume_p2[] = {
- SPIPE_VOL(SPIPE_COMP(15, SOF_COMP_VOLUME, sof_ipc_comp_volume), 0, 0xffffffff),/* ID = 15 */
-};
-
-static struct sof_ipc_comp_src src_p2[] = {
- SPIPE_SRC(SPIPE_COMP(14, SOF_COMP_SRC, sof_ipc_comp_src)), /* ID = 14 */
-};
-
-static struct scomps pipe2_scomps[] = {
- SCOMP(tone_p2),
- SCOMP(volume_p2),
- SCOMP(src_p2),
-};
-
-/* Host facing buffer */
-#define HOST_PERIOD_SIZE \
- (PLAT_HOST_PERIOD_FRAMES * PLATFORM_HOST_FRAME_SIZE)
-
-/* Device facing buffer */
-#define DAI_PERIOD_SIZE \
- (PLAT_DAI_PERIOD_FRAMES * PLATFORM_DAI_FRAME_SIZE)
-
-/* Internal buffer */
-#define INT_PERIOD_SIZE \
- (PLAT_INT_PERIOD_FRAMES * PLATFORM_INT_FRAME_SIZE)
-
-/*
- * Buffers used in static pipeline 0.
- */
-static struct sof_ipc_buffer buffer0[] = {
- /* B0 - LL Playback - PCM 0 Host0 -> Volume1 */
- SPIPE_BUFFER(0, HOST_PERIOD_SIZE * 2),
-
- /* B1 - LL Playback - PCM 1 - Host2 -> Volume3 */
- SPIPE_BUFFER(1, HOST_PERIOD_SIZE * 2),
-
- /* B2 Volume1 -> Mixer4 */
- SPIPE_BUFFER(2, INT_PERIOD_SIZE * 1),
-
- /* B3 Volume3 -> Mixer4 */
- SPIPE_BUFFER(3, INT_PERIOD_SIZE * 1),
-
- /* B4 Mixer4 -> Volume 5 */
- SPIPE_BUFFER(4, INT_PERIOD_SIZE * 1),
-
- /* B5 - DAI Playback - Volume5 -> DAI6 */
- SPIPE_BUFFER(5, DAI_PERIOD_SIZE * 2),
-
- /* B6 - DAI Capture - DAI7 - > Volume8 */
- SPIPE_BUFFER(6, DAI_PERIOD_SIZE * 2),
-
- /* B7 - PCM0 - Capture LL - Volume8 -> Host9 */
- SPIPE_BUFFER(7, HOST_PERIOD_SIZE * 1),
-};
-
-/*
- * Buffers used in static pipeline 1.
- */
-static struct sof_ipc_buffer buffer1[] = {
- /* B8 - Playback - PCM 3 - Host10 -> SRC11 */
- SPIPE_BUFFER(8, HOST_PERIOD_SIZE * 16),
-
- /* B9 SRC11 -> Volume12 */
- SPIPE_BUFFER(9, INT_PERIOD_SIZE * 2),
-
- /* B10 Volume12 -> Mixer4 */
- SPIPE_BUFFER(10, INT_PERIOD_SIZE * 2),
-};
-
-/*
- * Buffers used in static pipeline 2.
- */
-static struct sof_ipc_buffer buffer2[] = {
- /* B11 - tone13 -> SRC14 */
- SPIPE_BUFFER(11, HOST_PERIOD_SIZE * 16),
-
- /* B12 SRC14 -> Volume15 */
- SPIPE_BUFFER(12, INT_PERIOD_SIZE * 2),
-
- /* B13 Volume15 -> Mixer4 */
- SPIPE_BUFFER(13, INT_PERIOD_SIZE * 2),
-};
-
-/*
- * Pipeline 0
- *
- * Two Low Latency PCMs mixed into single SSP output.
- *
- * host PCM0(0) --B0--> volume(1) --B2--+
- * |--mixer(4) --B4--> volume(5) --B5--> SSPx(6)
- * host PCM1(2) --B1--> volume(3) --B3--+
- * |
- * pipeline 1 >-----+
- * |
- * pipeline 2 >-----+
- *
- * host PCM0(9) <--B7-- volume(8) <--B6-- SSPx(7)
- *
- *
- * Pipeline 1
- *
- * One PCM with SRC that is a Mixer 4 source
- *
- * host PCM2(10) --B8 --> SRC(11) --B9--> volume(12) --B10 --> Pipeline 0
- *
- *
- * Pipeline 2
- *
- * Test Pipeline
- *
- * tone(13) --- B11 ---> SRC(14) --B12---> volume(15) --B13 ---> Pipeline 0
- */
-
-/* pipeline 0 component/buffer connections */
-static struct sof_ipc_pipe_comp_connect c_connect0[] = {
- SPIPE_COMP_CONNECT(0, 1), /* Host0 -> B0 -> Volume1 */
- SPIPE_COMP_CONNECT(2, 3), /* Host2 -> B1 -> Volume3 */
- SPIPE_COMP_CONNECT(1, 4), /* Volume1 -> B2 -> Mixer4 */
- SPIPE_COMP_CONNECT(3, 4), /* Volume3 -> B3 -> Mixer4 */
- SPIPE_COMP_CONNECT(4, 5), /* Mixer4 -> B4 -> Volume5 */
- SPIPE_COMP_CONNECT(5, 6), /* Volume5 -> B5 -> DAI6 */
- SPIPE_COMP_CONNECT(7, 8), /* DAI7 -> B6 -> Volume8 */
- SPIPE_COMP_CONNECT(8, 9), /* Volume8 -> B7 -> host9 */
-};
-
-/* pipeline 1 component/buffer connections */
-static struct sof_ipc_pipe_comp_connect c_connect1[] = {
- SPIPE_COMP_CONNECT(10, 11), /* Host10 -> B8 -> SRC11 */
- SPIPE_COMP_CONNECT(11, 12), /* SRC11 -> B9 -> Volume12 */
-};
-
-/* pipeline 2 component/buffer connections */
-static struct sof_ipc_pipe_comp_connect c_connect2[] = {
- SPIPE_COMP_CONNECT(13, 14), /* tone13 -> B11 -> SRC14 */
- SPIPE_COMP_CONNECT(14, 15), /* SRC14 -> B12 -> Volume15 */
-};
-
-/* pipeline connections to other pipelines */
-//static struct sof_ipc_pipe_pipe_connect p_connect[] = {
-// SPIPE_PIPE_CONNECT(1, 12, 10, 0, 4), /* p1 volume12 -> B10 -> p0 Mixer4 */
-// SPIPE_PIPE_CONNECT(2, 15, 13, 0, 4), /* p2 Volume15 -> B13 -> p0 Mixer4 */
-//};
-
-/* the static pipelines */
-static struct spipe spipe[] = {
- SPIPE(pipe0_scomps, buffer0, c_connect0),
- SPIPE(pipe1_scomps, buffer1, c_connect1),
- SPIPE(pipe2_scomps, buffer2, c_connect2),
-};
-
-/* pipelines */
-struct sof_ipc_pipe_new pipeline[] = {
- SPIPE_PIPE(0, 0, 1000, TASK_PRI_HIGH), /* high pri - 1ms deadline */
-// SPIPE_PIPE(1, 0, 4000, TASK_PRI_MED), /* med pri - 4ms deadline */
-// SPIPE_PIPE(2, 0, 5000, TASK_PRI_LOW), /* low pri - 5ms deadline */
-};
-
-int init_static_pipeline(struct ipc *ipc)
-{
- struct scomps *sc;
- struct sof_ipc_comp *c;
- int i;
- int j;
- int k;
- int ret;
-
- /* init system pipeline core */
- ret = pipeline_init();
- if (ret < 0)
- return ret;
-
- /* create the pipelines */
- for (i = 0; i < ARRAY_SIZE(pipeline); i++) {
-
- /* create the pipeline */
- ret = ipc_pipeline_new(ipc, &pipeline[i]);
- if (ret < 0)
- goto error;
-
- sc = spipe[i].scomps;
-
- /* register components for this pipeline */
- for (j = 0; j < spipe[i].num_scomps; j++) {
-
- /* all pipeline components have same header */
- c = sc[j].comps;
-
- for (k = 0; k < sc[j].num_comps; k++) {
-
- ret = ipc_comp_new(ipc, c);
- if (ret < 0)
- goto error;
-
- /* next component - sizes not constant */
- c = (void*)c + c->hdr.size;
- }
- }
-
- /* register buffers for this pipeline */
- for (j = 0; j < spipe[i].num_buffers; j++) {
- ret = ipc_buffer_new(ipc, &spipe[i].buffer[j]);
- if (ret < 0)
- goto error;
- }
-
- /* connect components in this pipeline */
- for (j = 0; j < spipe[i].num_connections; j++) {
- ret = ipc_comp_connect(ipc, &spipe[i].connect[j]);
- if (ret < 0)
- goto error;
- }
- }
-
-#if 0
- /* connect the pipelines */
- for (i = 0; i < ARRAY_SIZE(p_connect); i++) {
- ret = ipc_pipe_connect(ipc, &p_connect[i]);
- if (ret < 0)
- goto error;
- }
-#endif
- /* pipelines now ready for params, prepare and cmds */
- return 0;
-
-error:
- trace_pipe_error("ePS");
-
- for (i = 0; i < ARRAY_SIZE(pipeline); i++) {
-
- /* free pipeline */
- ipc_pipeline_free(ipc, pipeline[i].pipeline_id);
-
- /* free components */
- for (j = 0; j < spipe[i].num_scomps; j++) {
- sc = spipe[i].scomps;
- for (k = 0; k < sc->num_comps; k++)
- ipc_comp_free(ipc, spipe[i].scomps[j].comps[k].id);
- }
-
- /* free buffers */
- for (j = 0; j < spipe[i].num_buffers; j++)
- ipc_buffer_free(ipc, spipe[i].buffer[j].comp.id);
- }
-
- return ret;
-}
diff --git a/src/audio/src.c b/src/audio/src.c
deleted file mode 100644
index c19828a..0000000
--- a/src/audio/src.c
+++ /dev/null
@@ -1,867 +0,0 @@
-/*
- * Copyright (c) 2017, Intel Corporation
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- * * Redistributions of source code must retain the above copyright
- * notice, this list of conditions and the following disclaimer.
- * * Redistributions in binary form must reproduce the above copyright
- * notice, this list of conditions and the following disclaimer in the
- * documentation and/or other materials provided with the distribution.
- * * Neither the name of the Intel Corporation nor the
- * names of its contributors may be used to endorse or promote products
- * derived from this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
- * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
- * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
- * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
- * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
- * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
- * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
- * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
- * POSSIBILITY OF SUCH DAMAGE.
- *
- * Author: Seppo Ingalsuo <seppo.ingalsuo@linux.intel.com>
- * Liam Girdwood <liam.r.girdwood@linux.intel.com>
- * Keyon Jie <yang.jie@linux.intel.com>
- */
-
-#include <stdint.h>
-#include <stddef.h>
-#include <errno.h>
-#include <sof/sof.h>
-#include <sof/lock.h>
-#include <sof/list.h>
-#include <sof/stream.h>
-#include <sof/alloc.h>
-#include <sof/work.h>
-#include <sof/clock.h>
-#include <sof/audio/component.h>
-#include <sof/audio/pipeline.h>
-#include <sof/math/numbers.h>
-#include <uapi/ipc.h>
-
-#include "src_config.h"
-#include "src.h"
-
-#if SRC_SHORT
-#include <sof/audio/coefficients/src/src_tiny_int16_define.h>
-#include <sof/audio/coefficients/src/src_tiny_int16_table.h>
-#else
-#include <sof/audio/coefficients/src/src_std_int32_define.h>
-#include <sof/audio/coefficients/src/src_std_int32_table.h>
-#endif
-
-#ifdef MODULE_TEST
-#include <stdio.h>
-#endif
-
-#define trace_src(__e) trace_event(TRACE_CLASS_SRC, __e)
-#define tracev_src(__e) tracev_event(TRACE_CLASS_SRC, __e)
-#define trace_src_error(__e) trace_error(TRACE_CLASS_SRC, __e)
-
-/* The FIR maximum lengths are per channel so need to multiply them */
-#define MAX_FIR_DELAY_SIZE_XNCH (PLATFORM_MAX_CHANNELS * MAX_FIR_DELAY_SIZE)
-#define MAX_OUT_DELAY_SIZE_XNCH (PLATFORM_MAX_CHANNELS * MAX_OUT_DELAY_SIZE)
-
-/* src component private data */
-struct comp_data {
- struct polyphase_src src;
- struct src_param param;
- int32_t *delay_lines;
- uint32_t sink_rate;
- uint32_t source_rate;
- int32_t *sbuf_w_ptr;
- int32_t *sbuf_r_ptr;
- int sbuf_avail;
- void (*src_func)(struct comp_dev *dev,
- struct comp_buffer *source,
- struct comp_buffer *sink,
- size_t *consumed,
- size_t *produced);
- void (*polyphase_func)(struct src_stage_prm *s);
-};
-
-/* Calculate ceil() for integer division */
-int src_ceil_divide(int a, int b)
-{
- int c;
-
- c = a / b;
- if (c * b < a)
- c++;
-
- return c;
-}
-
-/* Calculates the needed FIR delay line length */
-static int src_fir_delay_length(struct src_stage *s)
-{
- return s->subfilter_length + (s->num_of_subfilters - 1) * s->idm
- + s->blk_in;
-}
-
-/* Calculates the FIR output delay line length */
-static int src_out_delay_length(struct src_stage *s)
-{
- return 1 + (s->num_of_subfilters - 1) * s->odm;
-}
-
-/* Returns index of a matching sample rate */
-static int src_find_fs(int fs_list[], int list_length, int fs)
-{
- int i;
-
- for (i = 0; i < list_length; i++) {
- if (fs_list[i] == fs)
- return i;
- }
- return -EINVAL;
-}
-
-/* Calculates buffers to allocate for a SRC mode */
-int src_buffer_lengths(struct src_param *a, int fs_in, int fs_out, int nch,
- int frames, int frames_is_for_source)
-{
- struct src_stage *stage1;
- struct src_stage *stage2;
- int q;
- int den;
- int num;
- int frames2;
-
- if (nch > PLATFORM_MAX_CHANNELS) {
- trace_src_error("che");
- tracev_value(nch);
- return -EINVAL;
- }
-
- a->nch = nch;
- a->idx_in = src_find_fs(src_in_fs, NUM_IN_FS, fs_in);
- a->idx_out = src_find_fs(src_out_fs, NUM_OUT_FS, fs_out);
-
- /* Check that both in and out rates are supported */
- if (a->idx_in < 0 || a->idx_out < 0) {
- trace_src_error("us1");
- tracev_value(fs_in);
- tracev_value(fs_out);
- return -EINVAL;
- }
-
- stage1 = src_table1[a->idx_out][a->idx_in];
- stage2 = src_table2[a->idx_out][a->idx_in];
-
- /* Check from stage1 parameter for a deleted in/out rate combination.*/
- if (stage1->filter_length < 1) {
- trace_src_error("us2");
- tracev_value(fs_in);
- tracev_value(fs_out);
- return -EINVAL;
- }
-
- a->fir_s1 = nch * src_fir_delay_length(stage1);
- a->out_s1 = nch * src_out_delay_length(stage1);
-
- /* Find out how many additional times the SRC can be executed
- * while having block size less or equal to max_frames.
- */
- if (frames_is_for_source) {
- /* Times that stage1 needs to run to input length of frames */
- a->stage1_times_max = src_ceil_divide(frames, stage1->blk_in);
- q = frames / stage1->blk_in;
- a->stage1_times = MAX(q, 1);
- a->blk_in = a->stage1_times * stage1->blk_in;
-
- /* Times that stage2 needs to run */
- den = stage2->blk_in * stage1->blk_in;
- num = frames * stage2->blk_out * stage1->blk_out;
- frames2 = src_ceil_divide(num, den);
- a->stage2_times_max = src_ceil_divide(frames2, stage2->blk_out);
- q = frames2 / stage2->blk_out;
- a->stage2_times = MAX(q, 1);
- a->blk_out = a->stage2_times * stage2->blk_out;
- } else {
- /* Times that stage2 needs to run to output length of frames */
- a->stage2_times_max = src_ceil_divide(frames, stage2->blk_out);
- q = frames / stage2->blk_out;
- a->stage2_times = MAX(q, 1);
- a->blk_out = a->stage2_times * stage2->blk_out;
-
- /* Times that stage1 needs to run */
- num = frames * stage2->blk_in * stage1->blk_in;
- den = stage2->blk_out * stage1->blk_out;
- frames2 = src_ceil_divide(num, den);
- a->stage1_times_max = src_ceil_divide(frames2, stage1->blk_in);
- q = frames2 / stage1->blk_in;
- a->stage1_times = MAX(q, 1);
- a->blk_in = a->stage1_times * stage1->blk_in;
- }
-
- if (stage2->filter_length == 1) {
- a->fir_s2 = 0;
- a->out_s2 = 0;
- a->stage2_times = 0;
- a->stage2_times_max = 0;
- a->sbuf_length = 0;
- } else {
- a->fir_s2 = nch * src_fir_delay_length(stage2);
- a->out_s2 = nch * src_out_delay_length(stage2);
- /* 2x is an empirically tested length. Since the sink buffer
- * capability to receive samples varies a shorter stage 2 output
- * block will create a peak in internal buffer usage.
- */
-
- /* TODO 1: Equation for needed length */
- a->sbuf_length = 2 * nch * stage1->blk_out
- * a->stage1_times_max;
- }
-
- a->src_multich = a->fir_s1 + a->fir_s2 + a->out_s1 + a->out_s2;
- a->total = a->sbuf_length + a->src_multich;
-
- return 0;
-}
-
-static void src_state_reset(struct src_state *state)
-{
- state->fir_delay_size = 0;
- state->out_delay_size = 0;
-}
-
-static int init_stages(struct src_stage *stage1, struct src_stage *stage2,
- struct polyphase_src *src, struct src_param *p,
- int n, int32_t *delay_lines_start)
-{
- /* Clear FIR state */
- src_state_reset(&src->state1);
- src_state_reset(&src->state2);
-
- src->number_of_stages = n;
- src->stage1 = stage1;
- src->stage2 = stage2;
- if (n == 1 && stage1->blk_out == 0)
- return -EINVAL;
-
- /* Optimized SRC requires subfilter length multiple of 4 */
- if (stage1->filter_length > 1 && (stage1->subfilter_length & 0x3) > 0)
- return -EINVAL;
-
- if (stage2->filter_length > 1 && (stage2->subfilter_length & 0x3) > 0)
- return -EINVAL;
-
- /* Delay line sizes */
- src->state1.fir_delay_size = p->fir_s1;
- src->state1.out_delay_size = p->out_s1;
- src->state1.fir_delay = delay_lines_start;
- src->state1.out_delay =
- src->state1.fir_delay + src->state1.fir_delay_size;
- /* Initialize to last ensures that circular wrap cannot happen
- * mid-frame. The size is multiple of channels count.
- */
- src->state1.fir_wp = &src->state1.fir_delay[p->fir_s1 - 1];
- src->state1.out_rp = src->state1.out_delay;
- if (n > 1) {
- src->state2.fir_delay_size = p->fir_s2;
- src->state2.out_delay_size = p->out_s2;
- src->state2.fir_delay =
- src->state1.out_delay + src->state1.out_delay_size;
- src->state2.out_delay =
- src->state2.fir_delay + src->state2.fir_delay_size;
- /* Initialize to last ensures that circular wrap cannot happen
- * mid-frame. The size is multiple of channels count.
- */
- src->state2.fir_wp = &src->state2.fir_delay[p->fir_s2 - 1];
- src->state2.out_rp = src->state2.out_delay;
- } else {
- src->state2.fir_delay_size = 0;
- src->state2.out_delay_size = 0;
- src->state2.fir_delay = NULL;
- src->state2.out_delay = NULL;
- }
-
- /* Check the sizes are less than MAX */
- if (src->state1.fir_delay_size > MAX_FIR_DELAY_SIZE_XNCH ||
- src->state1.out_delay_size > MAX_OUT_DELAY_SIZE_XNCH ||
- src->state2.fir_delay_size > MAX_FIR_DELAY_SIZE_XNCH ||
- src->state2.out_delay_size > MAX_OUT_DELAY_SIZE_XNCH) {
- src->state1.fir_delay = NULL;
- src->state1.out_delay = NULL;
- src->state2.fir_delay = NULL;
- src->state2.out_delay = NULL;
- return -EINVAL;
- }
-
- return 0;
-}
-
-void src_polyphase_reset(struct polyphase_src *src)
-{
- src->number_of_stages = 0;
- src->stage1 = NULL;
- src->stage2 = NULL;
- src_state_reset(&src->state1);
- src_state_reset(&src->state2);
-}
-
-int src_polyphase_init(struct polyphase_src *src, struct src_param *p,
- int32_t *delay_lines_start)
-{
- struct src_stage *stage1;
- struct src_stage *stage2;
- int n_stages;
- int ret;
-
- if (p->idx_in < 0 || p->idx_out < 0)
- return -EINVAL;
-
- /* Get setup for 2 stage conversion */
- stage1 = src_table1[p->idx_out][p->idx_in];
- stage2 = src_table2[p->idx_out][p->idx_in];
- ret = init_stages(stage1, stage2, src, p, 2, delay_lines_start);
- if (ret < 0)
- return -EINVAL;
-
- /* Get number of stages used for optimize opportunity. 2nd
- * stage length is one if conversion needs only one stage.
- * If input and output rate is the same return 0 to
- * use a simple copy function instead of 1 stage FIR with one
- * tap.
- */
- n_stages = (src->stage2->filter_length == 1) ? 1 : 2;
- if (p->idx_in == p->idx_out)
- n_stages = 0;
-
- /* If filter length for first stage is zero this is a deleted
- * mode from in/out matrix. Computing of such SRC mode needs
- * to be prevented.
- */
- if (src->stage1->filter_length == 0)
- return -EINVAL;
-
- return n_stages;
-}
-
-/* Fallback function */
-static void src_fallback(struct comp_dev *dev, struct comp_buffer *source,
- struct comp_buffer *sink, size_t *bytes_read, size_t *bytes_written)
-{
- *bytes_read = 0;
- *bytes_written = 0;
-}
-
-/* Normal 2 stage SRC */
-static void src_2s_s32_default(struct comp_dev *dev,
- struct comp_buffer *source, struct comp_buffer *sink,
- size_t *bytes_read, size_t *bytes_written)
-{
- struct src_stage_prm s1;
- struct src_stage_prm s2;
- int s1_blk_in;
- int s1_blk_out;
- int s2_blk_in;
- int s2_blk_out;
- struct comp_data *cd = comp_get_drvdata(dev);
- int32_t *dest = (int32_t *)sink->w_ptr;
- int32_t *src = (int32_t *)source->r_ptr;
- int32_t *sbuf_addr = cd->delay_lines;
- int32_t *sbuf_end_addr = &cd->delay_lines[cd->param.sbuf_length];
- int32_t sbuf_size = cd->param.sbuf_length * sizeof(int32_t);
- int nch = dev->params.channels;
- int sbuf_free = cd->param.sbuf_length - cd->sbuf_avail;
- int n_read = 0;
- int n_written = 0;
- int n1 = 0;
- int n2 = 0;
- int avail_b = source->avail;
- int free_b = sink->free;
- int sz = sizeof(int32_t);
-
- s1.x_end_addr = source->end_addr;
- s1.x_size = source->size;
- s1.y_addr = sbuf_addr;
- s1.y_end_addr = sbuf_end_addr;
- s1.y_size = sbuf_size;
- s1.state = &cd->src.state1;
- s1.stage = cd->src.stage1;
- s1.x_rptr = src;
- s1.y_wptr = cd->sbuf_w_ptr;
- s1.nch = nch;
-
- s2.x_end_addr = sbuf_end_addr;
- s2.x_size = sbuf_size;
- s2.y_addr = sink->addr;
- s2.y_end_addr = sink->end_addr;
- s2.y_size = sink->size;
- s2.state = &cd->src.state2;
- s2.stage = cd->src.stage2;
- s2.x_rptr = cd->sbuf_r_ptr;
- s2.y_wptr = dest;
- s2.nch = nch;
-
- /* Test if 1st stage can be run with default block length to reach
- * the period length or just under it.
- */
- s1.times = cd->param.stage1_times;
- s1_blk_in = s1.times * cd->src.stage1->blk_in * nch;
- s1_blk_out = s1.times * cd->src.stage1->blk_out * nch;
- if (avail_b >= s1_blk_in * sz && sbuf_free >= s1_blk_out) {
- cd->polyphase_func(&s1);
-
- cd->sbuf_w_ptr = s1.y_wptr;
- cd->sbuf_avail += s1_blk_out;
- n_read += s1_blk_in;
- avail_b -= s1_blk_in * sz;
- sbuf_free -= s1_blk_out;
- n1 = s1.times;
- }
-
- /* Run one block at time the remaining data for 1st stage. */
- s1.times = 1;
- s1_blk_in = cd->src.stage1->blk_in * nch;
- s1_blk_out = cd->src.stage1->blk_out * nch;
- while (n1 < cd->param.stage1_times_max &&
- avail_b >= s1_blk_in * sz &&
- sbuf_free >= s1_blk_out) {
- cd->polyphase_func(&s1);
-
- cd->sbuf_w_ptr = s1.y_wptr;
- cd->sbuf_avail += s1_blk_out;
- n_read += s1_blk_in;
- avail_b -= s1_blk_in * sz;
- sbuf_free -= s1_blk_out;
- n1 += s1.times;
- }
-
- /* Test if 2nd stage can be run with default block length. */
- s2.times = cd->param.stage2_times;
- s2_blk_in = s2.times * cd->src.stage2->blk_in * nch;
- s2_blk_out = s2.times * cd->src.stage2->blk_out * nch;
- if (cd->sbuf_avail >= s2_blk_in && free_b >= s2_blk_out * sz) {
- cd->polyphase_func(&s2);
-
- cd->sbuf_r_ptr = s2.x_rptr;
- cd->sbuf_avail -= s2_blk_in;
- free_b -= s2_blk_out * sz;
- n_written += s2_blk_out;
- n2 = s2.times;
- }
-
- /* Run one block at time the remaining 2nd stage output */
- s2.times = 1;
- s2_blk_in = cd->src.stage2->blk_in * nch;
- s2_blk_out = cd->src.stage2->blk_out * nch;
- while (n2 < cd->param.stage2_times_max &&
- cd->sbuf_avail >= s2_blk_in &&
- free_b >= s2_blk_out * sz) {
- cd->polyphase_func(&s2);
-
- cd->sbuf_r_ptr = s2.x_rptr;
- cd->sbuf_avail -= s2_blk_in;
- free_b -= s2_blk_out * sz;
- n_written += s2_blk_out;
- n2 += s2.times;
- }
- *bytes_read = sizeof(int32_t) * n_read;
- *bytes_written = sizeof(int32_t) * n_written;
-}
-
-/* 1 stage SRC for simple conversions */
-static void src_1s_s32_default(struct comp_dev *dev,
- struct comp_buffer *source, struct comp_buffer *sink,
- size_t *bytes_read, size_t *bytes_written)
-{
- struct src_stage_prm s1;
- struct comp_data *cd = comp_get_drvdata(dev);
- int nch = dev->params.channels;
- int n_read = 0;
- int n_written = 0;
-
- s1.times = cd->param.stage1_times;
- s1.x_rptr = (int32_t *)source->r_ptr;
- s1.x_end_addr = source->end_addr;
- s1.x_size = source->size;
- s1.y_wptr = (int32_t *)sink->w_ptr;
- s1.y_end_addr = sink->end_addr;
- s1.y_size = sink->size;
- s1.state = &cd->src.state1;
- s1.stage = cd->src.stage1;
- s1.nch = dev->params.channels;
-
- cd->polyphase_func(&s1);
-
- n_read += nch * cd->param.blk_in;
- n_written += nch * cd->param.blk_out;
- *bytes_read = n_read * sizeof(int32_t);
- *bytes_written = n_written * sizeof(int32_t);
-}
-
-/* A fast copy function for same in and out rate */
-static void src_copy_s32_default(struct comp_dev *dev,
- struct comp_buffer *source, struct comp_buffer *sink,
- size_t *bytes_read, size_t *bytes_written)
-{
- struct comp_data *cd = comp_get_drvdata(dev);
- int32_t *src = (int32_t *)source->r_ptr;
- int32_t *snk = (int32_t *)sink->w_ptr;
- int nch = dev->params.channels;
- int frames = cd->param.blk_in;
- int n;
- int n_wrap_src;
- int n_wrap_snk;
- int n_wrap_min;
- int n_copy;
-
- n = frames * nch;
- while (n > 0) {
- n_wrap_src = (int32_t *)source->end_addr - src;
- n_wrap_snk = (int32_t *)sink->end_addr - snk;
- n_wrap_min = (n_wrap_src < n_wrap_snk) ?
- n_wrap_src : n_wrap_snk;
- n_copy = (n < n_wrap_min) ? n : n_wrap_min;
- memcpy(snk, src, n_copy * sizeof(int32_t));
-
- /* Update and check both source and destination for wrap */
- n -= n_copy;
- src += n_copy;
- snk += n_copy;
- src_circ_inc_wrap(&src, source->end_addr, source->size);
- src_circ_inc_wrap(&snk, sink->end_addr, sink->size);
- }
- *bytes_read = frames * nch * sizeof(int32_t);
- *bytes_written = frames * nch * sizeof(int32_t);
-}
-
-static struct comp_dev *src_new(struct sof_ipc_comp *comp)
-{
- struct comp_dev *dev;
- struct sof_ipc_comp_src *src;
- struct sof_ipc_comp_src *ipc_src = (struct sof_ipc_comp_src *)comp;
- struct comp_data *cd;
-
- trace_src("new");
-
- /* validate init data - either SRC sink or source rate must be set */
- if (ipc_src->source_rate == 0 && ipc_src->sink_rate == 0) {
- trace_src_error("sn1");
- return NULL;
- }
-
- dev = rzalloc(RZONE_RUNTIME, SOF_MEM_CAPS_RAM,
- COMP_SIZE(struct sof_ipc_comp_src));
- if (!dev)
- return NULL;
-
- src = (struct sof_ipc_comp_src *)&dev->comp;
- memcpy(src, ipc_src, sizeof(struct sof_ipc_comp_src));
-
- cd = rzalloc(RZONE_RUNTIME, SOF_MEM_CAPS_RAM, sizeof(*cd));
- if (!cd) {
- rfree(dev);
- return NULL;
- }
-
- comp_set_drvdata(dev, cd);
-
- cd->delay_lines = NULL;
- cd->src_func = src_2s_s32_default;
- cd->polyphase_func = src_polyphase_stage_cir;
- src_polyphase_reset(&cd->src);
-
- dev->state = COMP_STATE_READY;
- return dev;
-}
-
-static void src_free(struct comp_dev *dev)
-{
- struct comp_data *cd = comp_get_drvdata(dev);
-
- trace_src("fre");
-
- /* Free dynamically reserved buffers for SRC algorithm */
- if (!cd->delay_lines)
- rfree(cd->delay_lines);
-
- rfree(cd);
- rfree(dev);
-}
-
-/* set component audio stream parameters */
-static int src_params(struct comp_dev *dev)
-{
- struct sof_ipc_stream_params *params = &dev->params;
- struct sof_ipc_comp_src *src = COMP_GET_IPC(dev, sof_ipc_comp_src);
- struct sof_ipc_comp_config *config = COMP_GET_CONFIG(dev);
- struct comp_data *cd = comp_get_drvdata(dev);
- struct comp_buffer *sink;
- struct comp_buffer *source;
- size_t delay_lines_size;
- uint32_t source_rate;
- uint32_t sink_rate;
- int32_t *buffer_start;
- int n = 0;
- int err;
- int frames_is_for_source;
- int q;
-
- trace_src("par");
-
- /* SRC supports S24_4LE and S32_LE formats */
- switch (config->frame_fmt) {
- case SOF_IPC_FRAME_S24_4LE:
- cd->polyphase_func = src_polyphase_stage_cir_s24;
- break;
- case SOF_IPC_FRAME_S32_LE:
- cd->polyphase_func = src_polyphase_stage_cir;
- break;
- default:
- trace_src_error("sr0");
- return -EINVAL;
- }
-
- /* Calculate source and sink rates, one rate will come from IPC new
- * and the other from params.
- */
- if (src->source_rate == 0) {
- /* params rate is source rate */
- source_rate = params->rate;
- sink_rate = src->sink_rate;
- /* re-write our params with output rate for next component */
- params->rate = sink_rate;
- frames_is_for_source = 0;
- } else {
- /* params rate is sink rate */
- source_rate = src->source_rate;
- sink_rate = params->rate;
- /* re-write our params with output rate for next component */
- params->rate = source_rate;
- frames_is_for_source = 1;
- }
-
- /* Allocate needed memory for delay lines */
- err = src_buffer_lengths(&cd->param, source_rate, sink_rate,
- params->channels, dev->frames, frames_is_for_source);
- if (err < 0) {
- trace_src_error("sr1");
- trace_error_value(source_rate);
- trace_error_value(sink_rate);
- trace_error_value(params->channels);
- trace_error_value(dev->frames);
- return err;
- }
-
- delay_lines_size = sizeof(int32_t) * cd->param.total;
- if (delay_lines_size == 0) {
- trace_src_error("sr2");
- return -EINVAL;
- }
-
- /* free any existing delay lines. TODO reuse if same size */
- if (!cd->delay_lines)
- rfree(cd->delay_lines);
-
- cd->delay_lines = rballoc(RZONE_RUNTIME, SOF_MEM_CAPS_RAM,
- delay_lines_size);
- if (!cd->delay_lines) {
- trace_src_error("sr3");
- trace_error_value(delay_lines_size);
- return -EINVAL;
- }
-
- /* Clear all delay lines here */
- memset(cd->delay_lines, 0, delay_lines_size);
- buffer_start = cd->delay_lines + cd->param.sbuf_length;
-
- /* Initialize SRC for actual sample rate */
- n = src_polyphase_init(&cd->src, &cd->param, buffer_start);
-
- /* Reset stage buffer */
- cd->sbuf_r_ptr = cd->delay_lines;
- cd->sbuf_w_ptr = cd->delay_lines;
- cd->sbuf_avail = 0;
-
- switch (n) {
- case 0:
- cd->src_func = src_copy_s32_default; /* 1:1 fast copy */
- break;
- case 1:
- cd->src_func = src_1s_s32_default; /* Simpler 1 stage SRC */
- break;
- case 2:
- cd->src_func = src_2s_s32_default; /* Default 2 stage SRC */
- break;
- default:
- /* This is possibly due to missing coefficients for
- * requested rates combination. Sink audio will be
- * muted if copy() is run.
- */
- trace_src("SFa");
- cd->src_func = src_fallback;
- return -EINVAL;
- }
-
- /* Calculate period size based on config. First make sure that
- * frame_bytes is set.
- */
- dev->frame_bytes =
- dev->params.sample_container_bytes * dev->params.channels;
-
- /* The downstream buffer must be at least length of blk_out plus
- * a dev->frames and an integer multiple of dev->frames. The
- * buffer_set_size will return an error if the required length would
- * be too long.
- */
- q = src_ceil_divide(cd->param.blk_out, (int)dev->frames) + 1;
-
- /* Configure downstream buffer */
- sink = list_first_item(&dev->bsink_list, struct comp_buffer,
- source_list);
- err = buffer_set_size(sink, q * dev->frames * dev->frame_bytes);
- if (err < 0) {
- trace_src_error("eSz");
- trace_error_value(sink->alloc_size);
- trace_error_value(q * dev->frames * dev->frame_bytes);
- return err;
- }
-
- /* Check that source buffer has sufficient size */
- source = list_first_item(&dev->bsource_list, struct comp_buffer,
- sink_list);
- if (source->size < cd->param.blk_in * dev->frame_bytes) {
- trace_src_error("eSy");
- return -EINVAL;
- }
-
- return 0;
-}
-
-static int src_ctrl_cmd(struct comp_dev *dev, struct sof_ipc_ctrl_data *cdata)
-{
- trace_src_error("ec1");
- return -EINVAL;
-}
-
-/* used to pass standard and bespoke commands (with data) to component */
-static int src_cmd(struct comp_dev *dev, int cmd, void *data)
-{
- struct sof_ipc_ctrl_data *cdata = data;
- int ret = 0;
-
- trace_src("cmd");
-
- if (cmd == COMP_CMD_SET_VALUE)
- ret = src_ctrl_cmd(dev, cdata);
-
- return ret;
-}
-
-static int src_trigger(struct comp_dev *dev, int cmd)
-{
- trace_src("trg");
-
- return comp_set_state(dev, cmd);
-}
-
-/* copy and process stream data from source to sink buffers */
-static int src_copy(struct comp_dev *dev)
-{
- struct comp_data *cd = comp_get_drvdata(dev);
- struct comp_buffer *source;
- struct comp_buffer *sink;
- int need_source;
- int need_sink;
- size_t consumed = 0;
- size_t produced = 0;
-
- trace_src("SRC");
-
- /* src component needs 1 source and 1 sink buffer */
- source = list_first_item(&dev->bsource_list, struct comp_buffer,
- sink_list);
- sink = list_first_item(&dev->bsink_list, struct comp_buffer,
- source_list);
-
- /* Calculate needed amount of source buffer and sink buffer
- * for one SRC run. The blk_in and blk are minimum condition to
- * call copy. Copy can consume or produce a slightly larger block
- * with the rates where block sizes are not constant. E.g. for
- * 1 ms scheduling the blocks can be under or above 1 ms when the
- * SRC interval block size constraint prevents exact 1 ms blocks.
- */
- need_source = cd->param.blk_in * dev->frame_bytes;
- need_sink = cd->param.blk_out * dev->frame_bytes;
-
- /* make sure source component buffer has enough data available and that
- * the sink component buffer has enough free bytes for copy. Also
- * check for XRUNs.
- */
- if (source->avail < need_source) {
- trace_src_error("xru");
- return -EIO; /* xrun */
- }
- if (sink->free < need_sink) {
- trace_src_error("xro");
- return -EIO; /* xrun */
- }
-
- cd->src_func(dev, source, sink, &consumed, &produced);
-
- tracev_value(consumed >> 3);
- tracev_value(produced >> 3);
-
- /* Calc new free and available if data was processed. These
- * functions must not be called with 0 consumed/produced.
- */
- if (consumed > 0)
- comp_update_buffer_consume(source, consumed);
-
- if (produced > 0) {
- comp_update_buffer_produce(sink, produced);
- return cd->param.blk_out;
- }
-
- /* produced no data */
- return 0;
-}
-
-static int src_prepare(struct comp_dev *dev)
-{
- trace_src("pre");
-
- return comp_set_state(dev, COMP_TRIGGER_PREPARE);
-}
-
-static int src_reset(struct comp_dev *dev)
-{
- struct comp_data *cd = comp_get_drvdata(dev);
-
- trace_src("SRe");
-
- cd->src_func = src_2s_s32_default;
- src_polyphase_reset(&cd->src);
-
- comp_set_state(dev, COMP_TRIGGER_RESET);
- return 0;
-}
-
-struct comp_driver comp_src = {
- .type = SOF_COMP_SRC,
- .ops = {
- .new = src_new,
- .free = src_free,
- .params = src_params,
- .cmd = src_cmd,
- .trigger = src_trigger,
- .copy = src_copy,
- .prepare = src_prepare,
- .reset = src_reset,
- },
-};
-
-void sys_comp_src_init(void)
-{
- comp_register(&comp_src);
-}
diff --git a/src/audio/src.h b/src/audio/src.h
deleted file mode 100644
index 5268a66..0000000
--- a/src/audio/src.h
+++ /dev/null
@@ -1,131 +0,0 @@
-/*
- * Copyright (c) 2017, Intel Corporation
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- * * Redistributions of source code must retain the above copyright
- * notice, this list of conditions and the following disclaimer.
- * * Redistributions in binary form must reproduce the above copyright
- * notice, this list of conditions and the following disclaimer in the
- * documentation and/or other materials provided with the distribution.
- * * Neither the name of the Intel Corporation nor the
- * names of its contributors may be used to endorse or promote products
- * derived from this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
- * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
- * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
- * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
- * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
- * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
- * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
- * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
- * POSSIBILITY OF SUCH DAMAGE.
- *
- * Author: Seppo Ingalsuo <seppo.ingalsuo@linux.intel.com>
- *
- */
-
-#ifndef SRC_H
-#define SRC_H
-
-struct src_param {
- int fir_s1;
- int fir_s2;
- int out_s1;
- int out_s2;
- int sbuf_length;
- int src_multich;
- int total;
- int blk_in;
- int blk_out;
- int stage1_times;
- int stage2_times;
- int stage1_times_max;
- int stage2_times_max;
- int idx_in;
- int idx_out;
- int nch;
-};
-
-struct src_stage {
- const int idm;
- const int odm;
- const int num_of_subfilters;
- const int subfilter_length;
- const int filter_length;
- const int blk_in;
- const int blk_out;
- const int halfband;
- const int shift;
- const void *coefs; /* Can be int16_t or int32_t depending on config */
-};
-
-struct src_state {
- int fir_delay_size; /* samples */
- int out_delay_size; /* samples */
- int32_t *fir_delay;
- int32_t *out_delay;
- int32_t *fir_wp;
- int32_t *out_rp;
-};
-
-struct polyphase_src {
- int number_of_stages;
- struct src_stage *stage1;
- struct src_stage *stage2;
- struct src_state state1;
- struct src_state state2;
-};
-
-struct src_stage_prm {
- int nch;
- int times;
- int32_t *x_rptr;
- int32_t *x_end_addr;
- size_t x_size;
- int32_t *y_wptr;
- int32_t *y_addr;
- int32_t *y_end_addr;
- size_t y_size;
- struct src_state *state;
- struct src_stage *stage;
-};
-
-static inline void src_circ_inc_wrap(int32_t **ptr, int32_t *end, size_t size)
-{
- if (*ptr >= end)
- *ptr = (int32_t *)((size_t)*ptr - size);
-}
-
-static inline void src_circ_dec_wrap(int32_t **ptr, int32_t *addr, size_t size)
-{
- if (*ptr < addr)
- *ptr = (int32_t *)((size_t)*ptr + size);
-}
-
-void src_polyphase_reset(struct polyphase_src *src);
-
-int src_polyphase_init(struct polyphase_src *src, struct src_param *p,
- int32_t *delay_lines_start);
-
-int src_polyphase(struct polyphase_src *src, int32_t x[], int32_t y[],
- int n_in);
-
-void src_polyphase_stage_cir(struct src_stage_prm *s);
-
-void src_polyphase_stage_cir_s24(struct src_stage_prm *s);
-
-int src_buffer_lengths(struct src_param *p, int fs_in, int fs_out, int nch,
- int frames, int frames_is_for_source);
-
-int32_t src_input_rates(void);
-
-int32_t src_output_rates(void);
-
-int src_ceil_divide(int a, int b);
-
-#endif
diff --git a/src/audio/src_config.h b/src/audio/src_config.h
deleted file mode 100644
index 65d6247..0000000
--- a/src/audio/src_config.h
+++ /dev/null
@@ -1,90 +0,0 @@
-/*
- * Copyright (c) 2017, Intel Corporation
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- * * Redistributions of source code must retain the above copyright
- * notice, this list of conditions and the following disclaimer.
- * * Redistributions in binary form must reproduce the above copyright
- * notice, this list of conditions and the following disclaimer in the
- * documentation and/or other materials provided with the distribution.
- * * Neither the name of the Intel Corporation nor the
- * names of its contributors may be used to endorse or promote products
- * derived from this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
- * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
- * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
- * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
- * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
- * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
- * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
- * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
- * POSSIBILITY OF SUCH DAMAGE.
- *
- * Author: Seppo Ingalsuo <seppo.ingalsuo@linux.intel.com>
- *
- */
-
-#ifndef SRC_CONFIG_H
-#define SRC_CONFIG_H
-
-#include <config.h>
-
-/* If next defines are set to 1 the SRC is configured automatically. Setting
- * to zero temporarily is useful is for testing needs.
- * Setting SRC_AUTODSP to 0 allows to manually set the code variant.
- * Setting SRC_AUTOCOEF to 0 allows to select the coefficient type.
- */
-#define SRC_AUTOARCH 1
-#define SRC_AUTOCOEF 1
-
-/* Force manually some code variant when SRC_AUTODSP is set to zero. These
- * are useful in code debugging.
- */
-#if SRC_AUTOARCH == 0
-#define SRC_GENERIC 1
-#define SRC_HIFIEP 0
-#define SRC_HIFI3 0
-#endif
-#if SRC_AUTOCOEF == 0
-#define SRC_SHORT 0
-#endif
-
-/* Select 16 bit coefficients for specific platforms.
- * Otherwise 32 bits is the default.
- */
-#if SRC_AUTOCOEF == 1
-#if defined CONFIG_BAYTRAIL || defined CONFIG_CHERRYTRAIL \
- || defined CONFIG_BROADWELL || defined CONFIG_HASWELL
-#define SRC_SHORT 1 /* Use int16_t filter coefficients */
-#else
-#define SRC_SHORT 0 /* Use int32_t filter coefficients */
-#endif
-#endif
-
-/* Select optimized code variant when xt-xcc compiler is used */
-#if SRC_AUTOARCH == 1
-#if defined __XCC__
-#include <xtensa/config/core-isa.h>
-#define SRC_GENERIC 0
-#if XCHAL_HAVE_HIFI2EP == 1
-#define SRC_HIFIEP 1
-#define SRC_HIFI3 0
-#endif
-#if XCHAL_HAVE_HIFI3 == 1
-#define SRC_HIFI3 1
-#define SRC_HIFIEP 0
-#endif
-#else
-/* GCC */
-#define SRC_GENERIC 1
-#define SRC_HIFIEP 0
-#define SRC_HIFI3 0
-#endif
-#endif
-
-#endif
diff --git a/src/audio/src_generic.c b/src/audio/src_generic.c
deleted file mode 100644
index d410277..0000000
--- a/src/audio/src_generic.c
+++ /dev/null
@@ -1,435 +0,0 @@
-/*
- * Copyright (c) 2016, Intel Corporation
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- * * Redistributions of source code must retain the above copyright
- * notice, this list of conditions and the following disclaimer.
- * * Redistributions in binary form must reproduce the above copyright
- * notice, this list of conditions and the following disclaimer in the
- * documentation and/or other materials provided with the distribution.
- * * Neither the name of the Intel Corporation nor the
- * names of its contributors may be used to endorse or promote products
- * derived from this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
- * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
- * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
- * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
- * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
- * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
- * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
- * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
- * POSSIBILITY OF SUCH DAMAGE.
- *
- * Author: Seppo Ingalsuo <seppo.ingalsuo@linux.intel.com>
- *
- */
-
-/* Default C implementation guaranteed to work on any
- * architecture.
- */
-
-#include <stdint.h>
-#include <sof/alloc.h>
-#include <sof/audio/format.h>
-#include <sof/math/numbers.h>
-
-#include "src_config.h"
-#include "src.h"
-
-#if SRC_GENERIC
-
-#if SRC_SHORT /* 16 bit coefficients version */
-
-static inline void fir_filter_generic(int32_t *rp, const void *cp, int32_t *wp0,
- int32_t *fir_start, int32_t *fir_end, const int fir_delay_length,
- const int taps_x_nch, const int shift, const int nch)
-{
- int64_t y0;
- int64_t y1;
- int32_t *data;
- const int16_t *coef;
- int i;
- int j;
- int n1;
- int n2;
- int frames;
- const int qshift = 15 + shift; /* Q2.46 -> Q2.31 */
- const int32_t rnd = 1 << (qshift - 1); /* Half LSB */
- int32_t *d = rp;
- int32_t *wp = wp0;
-
- /* Check for 2ch FIR case */
- if (nch == 2) {
- /* Decrement data pointer to next channel start. Note that
- * initialization code ensures that circular wrap does not
- * happen mid-frame.
- */
- data = d - 1;
-
- /* Initialize to half LSB for rounding, prepare for FIR core */
- y0 = rnd;
- y1 = rnd;
- coef = (const int16_t *)cp;
- frames = fir_end - data; /* Frames until wrap */
- n1 = ((taps_x_nch < frames) ? taps_x_nch : frames) >> 1;
- n2 = (taps_x_nch >> 1) - n1;
-
- /* The FIR is calculated as Q1.15 x Q1.31 -> Q2.46. The
- * output shift includes the shift by 15 for Qx.46 to
- * Qx.31.
- */
- for (i = 0; i < n1; i++) {
- y0 += (int64_t)(*coef) * (*data);
- data++;
- y1 += (int64_t)(*coef) * (*data);
- data++;
- coef++;
- }
- if (data == fir_end)
- data = fir_start;
-
- for (i = 0; i < n2; i++) {
- y0 += (int64_t)(*coef) * (*data);
- data++;
- y1 += (int64_t)(*coef) * (*data);
- data++;
- coef++;
- }
-
- *wp = sat_int32(y1 >> qshift);
- *(wp + 1) = sat_int32(y0 >> qshift);
- return;
- }
-
- for (j = 0; j < nch; j++) {
- /* Decrement data pointer to next channel start. Note that
- * initialization code ensures that circular wrap does not
- * happen mid-frame.
- */
- data = d--;
-
- /* Initialize to half LSB for rounding, prepare for FIR core */
- y0 = rnd;
- coef = (const int16_t *)cp;
- frames = fir_end - data + nch - j - 1; /* Frames until wrap */
- n1 = (taps_x_nch < frames) ? taps_x_nch : frames;
- n2 = taps_x_nch - n1;
-
- /* The FIR is calculated as Q1.15 x Q1.31 -> Q2.46. The
- * output shift includes the shift by 15 for Qx.46 to
- * Qx.31.
- */
- for (i = 0; i < n1; i += nch) {
- y0 += (int64_t)(*coef) * (*data);
- coef++;
- data += nch;
- }
- if (data >= fir_end)
- data -= fir_delay_length;
-
- for (i = 0; i < n2; i += nch) {
- y0 += (int64_t)(*coef) * (*data);
- coef++;
- data += nch;
- }
-
- *wp = sat_int32(y0 >> qshift);
- wp++;
- }
-}
-
-#else /* 32bit coefficients version */
-
-static inline void fir_filter_generic(int32_t *rp, const void *cp, int32_t *wp0,
- int32_t *fir_start, int32_t *fir_end, int fir_delay_length,
- const int taps_x_nch, const int shift, const int nch)
-{
- int64_t y0;
- int64_t y1;
- int32_t *data;
- const int32_t *coef;
- int i;
- int j;
- int frames;
- int n1;
- int n2;
-
- const int qshift = 23 + shift; /* Qx.54 -> Qx.31 */
- const int32_t rnd = 1 << (qshift - 1); /* Half LSB */
- int32_t *d = rp;
- int32_t *wp = wp0;
-
- /* Check for 2ch FIR case */
- if (nch == 2) {
- /* Decrement data pointer to next channel start. Note that
- * initialization code ensures that circular wrap does not
- * happen mid-frame.
- */
- data = d - 1;
-
- /* Initialize to half LSB for rounding, prepare for FIR core */
- y0 = rnd;
- y1 = rnd;
- coef = (const int32_t *)cp;
- frames = fir_end - data; /* Frames until wrap */
- n1 = ((taps_x_nch < frames) ? taps_x_nch : frames) >> 1;
- n2 = (taps_x_nch >> 1) - n1;
-
- /* The FIR is calculated as Q1.23 x Q1.31 -> Q2.54. The
- * output shift includes the shift by 23 for Qx.54 to
- * Qx.31.
- */
- for (i = 0; i < n1; i++) {
- y0 += (int64_t)(*coef >> 8) * (*data);
- data++;
- y1 += (int64_t)(*coef >> 8) * (*data);
- data++;
- coef++;
- }
- if (data == fir_end)
- data = fir_start;
-
- for (i = 0; i < n2; i++) {
- y0 += (int64_t)(*coef >> 8) * (*data);
- data++;
- y1 += (int64_t)(*coef >> 8) * (*data);
- data++;
- coef++;
- }
- *wp = sat_int32(y1 >> qshift);
- *(wp + 1) = sat_int32(y0 >> qshift);
- return;
- }
-
- for (j = 0; j < nch; j++) {
- /* Decrement data pointer to next channel start. Note that
- * initialization code ensures that circular wrap does not
- * happen mid-frame.
- */
- data = d--;
-
- /* Initialize to half LSB for rounding, prepare for FIR core */
- y0 = rnd;
- coef = (const int32_t *)cp;
- frames = fir_end - data + nch - j - 1; /* Frames until wrap */
- n1 = (taps_x_nch < frames) ? taps_x_nch : frames;
- n2 = taps_x_nch - n1;
-
- /* The FIR is calculated as Q1.23 x Q1.31 -> Q2.54. The
- * output shift includes the shift by 23 for Qx.54 to
- * Qx.31.
- */
- for (i = 0; i < n1; i += nch) {
- y0 += (int64_t)(*coef >> 8) * (*data);
- coef++;
- data += nch;
- }
- if (data >= fir_end)
- data -= fir_delay_length;
-
- for (i = 0; i < n2; i += nch) {
- y0 += (int64_t)(*coef >> 8) * (*data);
- coef++;
- data += nch;
- }
- *wp = sat_int32(y0 >> qshift);
- wp++;
- }
-}
-
-#endif /* 32bit coefficients version */
-
-void src_polyphase_stage_cir(struct src_stage_prm *s)
-{
- int i;
- int n;
- int m;
- int n_wrap_buf;
- int n_wrap_fir;
- int n_min;
- int32_t *rp;
- int32_t *wp;
-
- struct src_state *fir = s->state;
- struct src_stage *cfg = s->stage;
- int32_t *fir_delay = fir->fir_delay;
- int32_t *fir_end = &fir->fir_delay[fir->fir_delay_size];
- int32_t *out_delay_end = &fir->out_delay[fir->out_delay_size];
- const void *cp; /* Can be int32_t or int16_t */
- const size_t out_size = fir->out_delay_size * sizeof(int32_t);
- const int nch = s->nch;
- const int nch_x_odm = cfg->odm * nch;
- const int blk_in_words = nch * cfg->blk_in;
- const int blk_out_words = nch * cfg->num_of_subfilters;
- const int fir_length = fir->fir_delay_size;
- const int rewind = nch * (cfg->blk_in
- + (cfg->num_of_subfilters - 1) * cfg->idm) - nch;
- const int nch_x_idm = nch * cfg->idm;
- const size_t fir_size = fir->fir_delay_size * sizeof(int32_t);
- const int taps_x_nch = cfg->subfilter_length * nch;
-
-#if SRC_SHORT
- const size_t subfilter_size = cfg->subfilter_length * sizeof(int16_t);
-#else
- const size_t subfilter_size = cfg->subfilter_length * sizeof(int32_t);
-#endif
-
- for (n = 0; n < s->times; n++) {
- /* Input data */
- m = blk_in_words;
- while (m > 0) {
- /* Number of words without circular wrap */
- n_wrap_buf = s->x_end_addr - s->x_rptr;
- n_wrap_fir = fir->fir_wp - fir->fir_delay + 1;
- n_min = (n_wrap_fir < n_wrap_buf)
- ? n_wrap_fir : n_wrap_buf;
- n_min = (m < n_min) ? m : n_min;
- m -= n_min;
- for (i = 0; i < n_min; i++) {
- *fir->fir_wp = *s->x_rptr;
- fir->fir_wp--;
- s->x_rptr++;
- }
- /* Check for wrap */
- src_circ_dec_wrap(&fir->fir_wp, fir_delay, fir_size);
- src_circ_inc_wrap(&s->x_rptr, s->x_end_addr, s->x_size);
- }
-
- /* Filter */
- cp = cfg->coefs; /* Reset to 1st coefficient */
- rp = fir->fir_wp + rewind;
- src_circ_inc_wrap(&rp, fir_end, fir_size);
- wp = fir->out_rp;
- for (i = 0; i < cfg->num_of_subfilters; i++) {
- fir_filter_generic(rp, cp, wp,
- fir_delay, fir_end, fir_length,
- taps_x_nch, cfg->shift, nch);
- wp += nch_x_odm;
- cp += subfilter_size;
- src_circ_inc_wrap(&wp, out_delay_end, out_size);
- rp -= nch_x_idm; /* Next sub-filter start */
- src_circ_dec_wrap(&rp, fir_delay, fir_size);
- }
-
- /* Output */
- m = blk_out_words;
- while (m > 0) {
- n_wrap_fir = out_delay_end - fir->out_rp;
- n_wrap_buf = s->y_end_addr - s->y_wptr;
- n_min = (n_wrap_fir < n_wrap_buf)
- ? n_wrap_fir : n_wrap_buf;
- n_min = (m < n_min) ? m : n_min;
- m -= n_min;
- for (i = 0; i < n_min; i++) {
- *s->y_wptr = *fir->out_rp;
- s->y_wptr++;
- fir->out_rp++;
- }
- /* Check wrap */
- src_circ_inc_wrap(&s->y_wptr, s->y_end_addr, s->y_size);
- src_circ_inc_wrap(&fir->out_rp, out_delay_end,
- out_size);
- }
- }
-}
-
-void src_polyphase_stage_cir_s24(struct src_stage_prm *s)
-{
- int i;
- int n;
- int m;
- int n_wrap_buf;
- int n_wrap_fir;
- int n_min;
- int32_t *rp;
- int32_t *wp;
-
- struct src_state *fir = s->state;
- struct src_stage *cfg = s->stage;
- int32_t *fir_delay = fir->fir_delay;
- int32_t *fir_end = &fir->fir_delay[fir->fir_delay_size];
- int32_t *out_delay_end = &fir->out_delay[fir->out_delay_size];
- const void *cp; /* Can be int32_t or int16_t */
- const size_t out_size = fir->out_delay_size * sizeof(int32_t);
- const int nch = s->nch;
- const int nch_x_odm = cfg->odm * nch;
- const int blk_in_words = nch * cfg->blk_in;
- const int blk_out_words = nch * cfg->num_of_subfilters;
- const int fir_length = fir->fir_delay_size;
- const int rewind = nch * (cfg->blk_in
- + (cfg->num_of_subfilters - 1) * cfg->idm) - nch;
- const int nch_x_idm = nch * cfg->idm;
- const size_t fir_size = fir->fir_delay_size * sizeof(int32_t);
- const int taps_x_nch = cfg->subfilter_length * nch;
-
-#if SRC_SHORT
- const size_t subfilter_size = cfg->subfilter_length * sizeof(int16_t);
-#else
- const size_t subfilter_size = cfg->subfilter_length * sizeof(int32_t);
-#endif
-
- for (n = 0; n < s->times; n++) {
- /* Input data */
- m = blk_in_words;
- while (m > 0) {
- /* Number of words without circular wrap */
- n_wrap_buf = s->x_end_addr - s->x_rptr;
- n_wrap_fir = fir->fir_wp - fir->fir_delay + 1;
- n_min = (n_wrap_fir < n_wrap_buf)
- ? n_wrap_fir : n_wrap_buf;
- n_min = (m < n_min) ? m : n_min;
- m -= n_min;
- for (i = 0; i < n_min; i++) {
- *fir->fir_wp = *s->x_rptr << 8;
- fir->fir_wp--;
- s->x_rptr++;
- }
- /* Check for wrap */
- src_circ_dec_wrap(&fir->fir_wp, fir_delay, fir_size);
- src_circ_inc_wrap(&s->x_rptr, s->x_end_addr, s->x_size);
- }
-
- /* Filter */
- cp = cfg->coefs; /* Reset to 1st coefficient */
- rp = fir->fir_wp + rewind;
- src_circ_inc_wrap(&rp, fir_end, fir_size);
- wp = fir->out_rp;
- for (i = 0; i < cfg->num_of_subfilters; i++) {
- fir_filter_generic(rp, cp, wp,
- fir_delay, fir_end, fir_length,
- taps_x_nch, cfg->shift, nch);
- wp += nch_x_odm;
- cp += subfilter_size;
- src_circ_inc_wrap(&wp, out_delay_end, out_size);
- rp -= nch_x_idm; /* Next sub-filter start */
- src_circ_dec_wrap(&rp, fir_delay, fir_size);
- }
-
- /* Output */
- m = blk_out_words;
- while (m > 0) {
- n_wrap_fir = out_delay_end - fir->out_rp;
- n_wrap_buf = s->y_end_addr - s->y_wptr;
- n_min = (n_wrap_fir < n_wrap_buf)
- ? n_wrap_fir : n_wrap_buf;
- n_min = (m < n_min) ? m : n_min;
- m -= n_min;
- for (i = 0; i < n_min; i++) {
- *s->y_wptr = *fir->out_rp >> 8;
- s->y_wptr++;
- fir->out_rp++;
- }
- /* Check wrap */
- src_circ_inc_wrap(&s->y_wptr, s->y_end_addr, s->y_size);
- src_circ_inc_wrap(&fir->out_rp, out_delay_end,
- out_size);
- }
- }
-}
-
-#endif
diff --git a/src/audio/src_hifi2ep.c b/src/audio/src_hifi2ep.c
deleted file mode 100644
index cf919a3..0000000
--- a/src/audio/src_hifi2ep.c
+++ /dev/null
@@ -1,562 +0,0 @@
-/*
- * Copyright (c) 2017, Intel Corporation
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- * * Redistributions of source code must retain the above copyright
- * notice, this list of conditions and the following disclaimer.
- * * Redistributions in binary form must reproduce the above copyright
- * notice, this list of conditions and the following disclaimer in the
- * documentation and/or other materials provided with the distribution.
- * * Neither the name of the Intel Corporation nor the
- * names of its contributors may be used to endorse or promote products
- * derived from this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
- * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
- * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
- * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
- * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
- * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
- * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
- * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
- * POSSIBILITY OF SUCH DAMAGE.
- *
- * Author: Seppo Ingalsuo <seppo.ingalsuo@linux.intel.com>
- *
- */
-
-/* HiFi EP optimized code parts for SRC */
-
-#include <stdint.h>
-#include <sof/alloc.h>
-#include <sof/audio/format.h>
-#include <sof/math/numbers.h>
-
-#include "src_config.h"
-#include "src.h"
-
-#if SRC_HIFIEP
-
-#include <xtensa/config/defs.h>
-#include <xtensa/tie/xt_hifi2.h>
-
-/* HiFi EP has
- * 4x 56 bit registers in register file Q
- * 8x 48 bit registers in register file P
- */
-
-#if SRC_SHORT /* 16 bit coefficients version */
-
-static inline void fir_filter(ae_q32s *rp, const void *cp, ae_q32s *wp0,
- const int taps_div_4, const int shift, const int nch)
-{
- /* This function uses
- * 2x 56 bit registers Q,
- * 4x 48 bit registers P
- * 3x integers
- * 4x address pointers,
- */
- ae_q56s a0;
- ae_q56s a1;
- ae_p24x2f data2;
- ae_p24x2f coef2;
- ae_p24x2f p0;
- ae_p24x2f p1;
- ae_p16x2s *coefp;
- ae_p24x2f *dp = (ae_p24x2f *)rp;
- ae_p24x2f *dp0;
- ae_q32s *wp = wp0;
- int i;
- int j;
- const int inc = sizeof(ae_p24x2f);
-
- /* 2ch FIR case */
- if (nch == 2) {
- /* Move data pointer back by one sample to start from right
- * channel sample. Discard read value p0.
- */
- AE_LP24F_C(p0, dp, -sizeof(ae_p24f));
-
- /* Reset coefficient pointer and clear accumulator */
- coefp = (ae_p16x2s *)cp;
- a0 = AE_ZEROQ56();
- a1 = AE_ZEROQ56();
-
- /* Compute FIR filter for current channel with four
- * taps per every loop iteration. Two coefficients
- * are loaded simultaneously. Data is read
- * from interleaved buffer with stride of channels
- * count.
- */
- for (i = 0; i < taps_div_4; i++) {
- /* Load two coefficients. Coef2_h contains tap *coefp
- * and coef2_l contains the next tap.
- */
- coef2 = AE_LP16X2F_I(coefp, 0);
- coefp++;
-
- /* Load two data samples from two channels */
- AE_LP24X2F_C(p0, dp, inc); /* r0, l0 */
- AE_LP24X2F_C(p1, dp, inc); /* r1, l1 */
-
- /* Select to d0 successive left channel samples, to d1
- * successive right channel samples. Then accumulate
- * data2_h * coef2_h + data2_l * coef2_l. The Q1.31
- * data and Q1.15 coefficients are used as 24 bits as
- * Q1.23 values.
- */
- data2 = AE_SELP24_LL(p0, p1);
- AE_MULAAFP24S_HH_LL(a0, data2, coef2);
- data2 = AE_SELP24_HH(p0, p1);
- AE_MULAAFP24S_HH_LL(a1, data2, coef2);
-
- /* Repeat for next two taps */
- coef2 = AE_LP16X2F_I(coefp, 0);
- coefp++;
- AE_LP24X2F_C(p0, dp, inc); /* r2, l2 */
- AE_LP24X2F_C(p1, dp, inc); /* r3, l3 */
- data2 = AE_SELP24_LL(p0, p1);
- AE_MULAAFP24S_HH_LL(a0, data2, coef2);
- data2 = AE_SELP24_HH(p0, p1);
- AE_MULAAFP24S_HH_LL(a1, data2, coef2);
- }
-
- /* Scale FIR output with right shifts, round/saturate
- * to Q1.31, and store 32 bit output.
- */
- AE_SQ32F_I(AE_ROUNDSQ32SYM(AE_SRAAQ56(a0, shift)), wp, 0);
- AE_SQ32F_I(AE_ROUNDSQ32SYM(AE_SRAAQ56(a1, shift)), wp,
- sizeof(int32_t));
- return;
- }
-
- for (j = 0; j < nch; j++) {
- /* Copy pointer and advance to next ch with dummy load */
- dp0 = dp;
- AE_LP24F_C(p0, dp, -sizeof(ae_p24f));
-
- /* Reset coefficient pointer and clear accumulator */
- coefp = (ae_p16x2s *)cp;
- a0 = AE_ZEROQ56();
-
- /* Compute FIR filter for current channel with four
- * taps per every loop iteration. Two coefficients
- * are loaded simultaneously. Data is read
- * from interleaved buffer with stride of channels
- * count.
- */
- for (i = 0; i < taps_div_4; i++) {
- /* Load two coefficients */
- coef2 = *coefp++;
-
- /* Load two data samples */
- AE_LP24F_C(p0, dp0, inc);
- AE_LP24F_C(p1, dp0, inc);
-
- /* Pack p0 and p1 to data2_h and data2_l */
- data2 = AE_SELP24_LL(p0, p1);
-
- /* Accumulate data2_h * coef2_h + data2_l * coef2_l */
- AE_MULAAFP24S_HH_LL(a0, data2, coef2);
-
- /* Repeat for next two filter taps */
- coef2 = *coefp++;
- AE_LP24F_C(p0, dp0, inc);
- AE_LP24F_C(p1, dp0, inc);
- data2 = AE_SELP24_LL(p0, p1);
- AE_MULAAFP24S_HH_LL(a0, data2, coef2);
- }
-
- /* Scale FIR output with right shifts, round/saturate
- * to Q1.31, and store 32 bit output. Advance write
- * pointer to next sample.
- */
- AE_SQ32F_I(AE_ROUNDSQ32SYM(AE_SRAAQ56(a0, shift)), wp, 0);
- wp++;
- }
-}
-
-#else /* 32bit coefficients version */
-
-static inline void fir_filter(ae_q32s *rp, const void *cp, ae_q32s *wp0,
- const int taps_div_4, const int shift, const int nch)
-{
- /* This function uses
- * 2x 56 bit registers Q,
- * 4x 48 bit registers P
- * 3x integers
- * 4x address pointers,
- */
- ae_q56s a0;
- ae_q56s a1;
- ae_p24x2f p0;
- ae_p24x2f p1;
- ae_p24x2f data2;
- ae_p24x2f coef2;
- ae_p24x2f *coefp;
- ae_p24x2f *dp = (ae_p24x2f *)rp;
- ae_p24x2f *dp0;
- ae_q32s *wp = wp0;
- int i;
- int j;
- const int inc = sizeof(ae_p24x2f);
-
- /* 2ch FIR case */
- if (nch == 2) {
- /* Move data pointer back by one sample to start from right
- * channel sample. Discard read value p0.
- */
- AE_LP24F_C(p0, dp, -sizeof(ae_p24f));
-
- /* Reset coefficient pointer and clear accumulator */
- coefp = (ae_p24x2f *)cp;
- a0 = AE_ZEROQ56();
- a1 = AE_ZEROQ56();
-
- /* Compute FIR filter for current channel with four
- * taps per every loop iteration. Two coefficients
- * are loaded simultaneously. Data is read
- * from interleaved buffer with stride of channels
- * count.
- */
- for (i = 0; i < taps_div_4; i++) {
- /* Load two coefficients. Coef2_h contains tap *coefp
- * and coef2_l contains the next tap.
- */
- /* TODO: Ensure coefficients are 64 bits aligned */
- coef2 = AE_LP24X2F_I(coefp, 0);
- coefp++;
-
- /* Load two data samples from two channels */
- AE_LP24X2F_C(p0, dp, inc); /* r0, l0 */
- AE_LP24X2F_C(p1, dp, inc); /* r1, l1 */
-
- /* Select to d0 successive left channel samples, to d1
- * successive right channel samples.
- */
-
- /* Accumulate to m
- * data2_h * coef2_h + data2_l * coef2_l. The Q1.31
- * data and Q1.15 coefficients are used as 24 bits as
- * Q1.23 values.
- */
- data2 = AE_SELP24_LL(p0, p1);
- AE_MULAAFP24S_HH_LL(a0, data2, coef2);
- data2 = AE_SELP24_HH(p0, p1);
- AE_MULAAFP24S_HH_LL(a1, data2, coef2);
-
- /* Repeat for next two taps */
- coef2 = AE_LP24X2F_I(coefp, 0);
- coefp++;
- AE_LP24X2F_C(p0, dp, inc); /* r2, l2 */
- AE_LP24X2F_C(p1, dp, inc); /* r3, l3 */
- data2 = AE_SELP24_LL(p0, p1);
- AE_MULAAFP24S_HH_LL(a0, data2, coef2);
- data2 = AE_SELP24_HH(p0, p1);
- AE_MULAAFP24S_HH_LL(a1, data2, coef2);
- }
-
- /* Scale FIR output with right shifts, round/saturate
- * to Q1.31, and store 32 bit output.
- */
- AE_SQ32F_I(AE_ROUNDSQ32SYM(AE_SRAAQ56(a0, shift)), wp, 0);
- AE_SQ32F_I(AE_ROUNDSQ32SYM(AE_SRAAQ56(a1, shift)), wp,
- sizeof(int32_t));
- return;
- }
-
- for (j = 0; j < nch; j++) {
- /* Copy pointer and advance to next ch with dummy load */
- dp0 = dp;
- AE_LP24F_C(p0, dp, -sizeof(ae_p24f));
-
- /* Reset coefficient pointer and clear accumulator */
- coefp = (ae_p24x2f *)cp;
- a0 = AE_ZEROQ56();
-
- /* Compute FIR filter for current channel with four
- * taps per every loop iteration. Two coefficients
- * are loaded simultaneously. Data is read
- * from interleaved buffer with stride of channels
- * count.
- */
- for (i = 0; i < taps_div_4; i++) {
- /* Load two coefficients */
- coef2 = *coefp++;
-
- /* Load two data samples and place them to L and H of
- * data2.
- */
- AE_LP24F_C(p0, dp0, inc);
- AE_LP24F_C(p1, dp0, inc);
- data2 = AE_SELP24_LH(p0, p1);
-
- /* Accumulate to m
- * data2_h * coef2_h + data2_l * coef2_l. The Q1.31
- * data and coefficients are used as the most
- * significant 24 bits as Q1.23 values.
- */
- AE_MULAAFP24S_HH_LL(a0, data2, coef2);
-
- /* Repeat for next two filter taps */
- coef2 = *coefp++;
- AE_LP24F_C(p0, dp0, inc);
- AE_LP24F_C(p1, dp0, inc);
- data2 = AE_SELP24_LH(p0, p1);
- AE_MULAAFP24S_HH_LL(a0, data2, coef2);
- }
-
- /* Scale FIR output with right shifts, round/saturate
- * to Q1.31, and store 32 bit output. Advance write
- * pointer to next sample.
- */
- AE_SQ32F_I(AE_ROUNDSQ32SYM(AE_SRAAQ56(a0, shift)), wp, 0);
- wp++;
- }
-}
-#endif /* 32bit coefficients version */
-
-void src_polyphase_stage_cir(struct src_stage_prm *s)
-{
- /* This function uses
- * 1x 56 bit registers Q,
- * 0x 48 bit registers P,
- * 16x integers
- * 7x address pointers,
- */
- ae_q56s q;
- ae_q32s *rp;
- ae_q32s *wp;
- int i;
- int n;
- int m;
- int n_wrap_buf;
- int n_min;
- struct src_state *fir = s->state;
- struct src_stage *cfg = s->stage;
- int32_t *fir_end = &fir->fir_delay[fir->fir_delay_size];
- int32_t *out_delay_end = &fir->out_delay[fir->out_delay_size];
- const void *cp; /* Can be int32_t or int16_t */
- const size_t out_size = fir->out_delay_size * sizeof(int32_t);
- const int nch = s->nch;
- const int nch_x_odm = cfg->odm * nch;
- const int blk_in_words = nch * cfg->blk_in;
- const int blk_out_words = nch * cfg->num_of_subfilters;
- const int sz = sizeof(int32_t);
- const int n_sz = -sizeof(int32_t);
- const int rewind_sz = sz * (nch * (cfg->blk_in
- + (cfg->num_of_subfilters - 1) * cfg->idm) - nch);
- const int nch_x_idm_sz = -nch * cfg->idm * sizeof(int32_t);
- const int taps_div_4 = cfg->subfilter_length >> 2;
-
-#if SRC_SHORT
- const size_t subfilter_size = cfg->subfilter_length * sizeof(int16_t);
-#else
- const size_t subfilter_size = cfg->subfilter_length * sizeof(int32_t);
-#endif
-
- for (n = 0; n < s->times; n++) {
- /* Input data to filter */
- m = blk_in_words;
-
- /* Setup circular buffer for FIR input data delay */
- AE_SETCBEGIN0(fir->fir_delay);
- AE_SETCEND0(fir_end);
-
- while (m > 0) {
- /* Number of words until circular wrap */
- n_wrap_buf = s->x_end_addr - s->x_rptr;
- n_min = (m < n_wrap_buf) ? m : n_wrap_buf;
- m -= n_min;
- for (i = 0; i < n_min; i++) {
- /* Load 32 bits sample to accumulator */
- q = AE_LQ32F_I((ae_q32s *)s->x_rptr++, 0);
-
- /* Store to circular buffer, advance pointer */
- AE_SQ32F_C(q, (ae_q32s *)fir->fir_wp, n_sz);
- }
-
- /* Check for wrap */
- src_circ_inc_wrap(&s->x_rptr, s->x_end_addr, s->x_size);
- }
-
- /* Do filter */
- cp = cfg->coefs; /* Reset to 1st coefficient */
- rp = (ae_q32s *)fir->fir_wp;
-
- /* Do circular modification to pointer rp by amount of
- * rewind to to data start. Loaded value q is discarded.
- */
- AE_LQ32F_C(q, (ae_q32s *)rp, rewind_sz);
-
- /* Reset FIR write pointer and compute all polyphase
- * sub-filters.
- */
- wp = (ae_q32s *)fir->out_rp;
- for (i = 0; i < cfg->num_of_subfilters; i++) {
- fir_filter(rp, cp, wp, taps_div_4, cfg->shift, nch);
- wp += nch_x_odm;
- cp += subfilter_size;
- src_circ_inc_wrap((int32_t **)&wp, out_delay_end,
- out_size);
-
- /* Circular advance pointer rp by number of
- * channels x input delay multiplier. Loaded value q
- * is discarded.
- */
- AE_LQ32F_C(q, rp, nch_x_idm_sz);
- }
-
- /* Output */
-
- /* Setup circular buffer for SRC out delay access */
- AE_SETCBEGIN0(fir->out_delay);
- AE_SETCEND0(out_delay_end);
- m = blk_out_words;
- while (m > 0) {
- n_wrap_buf = s->y_end_addr - s->y_wptr;
- n_min = (m < n_wrap_buf) ? m : n_wrap_buf;
- m -= n_min;
- for (i = 0; i < n_min; i++) {
- /* Circular load followed by linear store */
- AE_LQ32F_C(q, (ae_q32s *)fir->out_rp, sz);
- AE_SQ32F_I(q, (ae_q32s *)s->y_wptr, 0);
- s->y_wptr++;
- }
- /* Check wrap */
- src_circ_inc_wrap(&s->y_wptr, s->y_end_addr, s->y_size);
- }
- }
-}
-
-void src_polyphase_stage_cir_s24(struct src_stage_prm *s)
-{
- /* This function uses
- * 1x 56 bit registers Q,
- * 0x 48 bit registers P,
- * 16x integers
- * 7x address pointers,
- */
- ae_q56s q;
- ae_q32s *rp;
- ae_q32s *wp;
- int i;
- int n;
- int m;
- int n_wrap_buf;
- int n_min;
- struct src_state *fir = s->state;
- struct src_stage *cfg = s->stage;
- int32_t *fir_end = &fir->fir_delay[fir->fir_delay_size];
- int32_t *out_delay_end = &fir->out_delay[fir->out_delay_size];
- const void *cp; /* Can be int32_t or int16_t */
- const size_t out_size = fir->out_delay_size * sizeof(int32_t);
- const int nch = s->nch;
- const int nch_x_odm = cfg->odm * nch;
- const int blk_in_words = nch * cfg->blk_in;
- const int blk_out_words = nch * cfg->num_of_subfilters;
- const int sz = sizeof(int32_t);
- const int n_sz = -sizeof(int32_t);
- const int rewind_sz = sz * (nch * (cfg->blk_in
- + (cfg->num_of_subfilters - 1) * cfg->idm) - nch);
- const int nch_x_idm_sz = -nch * cfg->idm * sizeof(int32_t);
- const int taps_div_4 = cfg->subfilter_length >> 2;
-
-#if SRC_SHORT
- const size_t subfilter_size = cfg->subfilter_length * sizeof(int16_t);
-#else
- const size_t subfilter_size = cfg->subfilter_length * sizeof(int32_t);
-#endif
-
- for (n = 0; n < s->times; n++) {
- /* Input data to filter */
- m = blk_in_words;
-
- /* Setup circular buffer for FIR input data delay */
- AE_SETCBEGIN0(fir->fir_delay);
- AE_SETCEND0(fir_end);
-
- while (m > 0) {
- /* Number of words without circular wrap */
- n_wrap_buf = s->x_end_addr - s->x_rptr;
- n_min = (m < n_wrap_buf) ? m : n_wrap_buf;
- m -= n_min;
- for (i = 0; i < n_min; i++) {
- /* Load 32 bits sample to accumulator
- * and left shift by 8, advance read
- * pointer.
- */
- q = AE_SLLIQ56(AE_LQ32F_I(
- (ae_q32s *)s->x_rptr++, 0), 8);
-
- /* Store to circular buffer, advance
- * write pointer.
- */
- AE_SQ32F_C(q, (ae_q32s *)fir->fir_wp, n_sz);
- }
-
- /* Check for wrap */
- src_circ_inc_wrap(&s->x_rptr, s->x_end_addr, s->x_size);
- }
-
- /* Do filter */
- cp = cfg->coefs; /* Reset to 1st coefficient */
- rp = (ae_q32s *)fir->fir_wp;
-
- /* Do circular modification to pointer rp by amount of
- * rewind to to data start. Loaded value q is discarded.
- */
- AE_LQ32F_C(q, (ae_q32s *)rp, rewind_sz);
-
- /* Reset FIR output write pointer and compute all polyphase
- * sub-filters.
- */
- wp = (ae_q32s *)fir->out_rp;
- for (i = 0; i < cfg->num_of_subfilters; i++) {
- fir_filter(rp, cp, wp, taps_div_4, cfg->shift, nch);
- wp += nch_x_odm;
- cp += subfilter_size;
- src_circ_inc_wrap((int32_t **)&wp, out_delay_end,
- out_size);
-
- /* Circular advance pointer rp by number of
- * channels x input delay multiplier. Loaded value q
- * is discarded.
- */
- AE_LQ32F_C(q, rp, nch_x_idm_sz);
- }
-
- /* Output */
-
- /* Setup circular buffer for SRC out delay access */
- AE_SETCBEGIN0(fir->out_delay);
- AE_SETCEND0(out_delay_end);
- m = blk_out_words;
- while (m > 0) {
- n_wrap_buf = s->y_end_addr - s->y_wptr;
- n_min = (m < n_wrap_buf) ? m : n_wrap_buf;
- m -= n_min;
- for (i = 0; i < n_min; i++) {
- /* Circular load for 32 bit sample,
- * advance pointer.
- */
- AE_LQ32F_C(q, (ae_q32s *)fir->out_rp, sz);
-
- /* Store value as shifted right by 8 for
- * sign extended 24 bit value, advance pointer.
- */
- AE_SQ32F_I(AE_SRAIQ56(q, 8),
- (ae_q32s *)s->y_wptr, 0);
- s->y_wptr++;
- }
- /* Check wrap */
- src_circ_inc_wrap(&s->y_wptr, s->y_end_addr, s->y_size);
- }
- }
-}
-
-#endif
diff --git a/src/audio/src_hifi3.c b/src/audio/src_hifi3.c
deleted file mode 100644
index d2dfab0..0000000
--- a/src/audio/src_hifi3.c
+++ /dev/null
@@ -1,567 +0,0 @@
-/*
- * Copyright (c) 2016, Intel Corporation
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- * * Redistributions of source code must retain the above copyright
- * notice, this list of conditions and the following disclaimer.
- * * Redistributions in binary form must reproduce the above copyright
- * notice, this list of conditions and the following disclaimer in the
- * documentation and/or other materials provided with the distribution.
- * * Neither the name of the Intel Corporation nor the
- * names of its contributors may be used to endorse or promote products
- * derived from this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
- * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
- * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
- * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
- * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
- * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
- * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
- * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
- * POSSIBILITY OF SUCH DAMAGE.
- *
- * Author: Seppo Ingalsuo <seppo.ingalsuo@linux.intel.com>
- *
- */
-
-/* HiFi3 optimized code parts for SRC */
-
-#include <stdint.h>
-#include <sof/alloc.h>
-#include <sof/audio/format.h>
-#include <sof/math/numbers.h>
-
-#include "src_config.h"
-#include "src.h"
-
-#if SRC_HIFI3
-
-#include <xtensa/config/defs.h>
-#include <xtensa/tie/xt_hifi3.h>
-
-/* HiFi3 has
- * 16x 64 bit registers in register file AE_DR
- */
-
-#if SRC_SHORT /* 16 bit coefficients version */
-
-static inline void fir_filter(ae_f32 *rp, const void *cp, ae_f32 *wp0,
- const int taps_div_4, const int shift, const int nch)
-{
- /* This function uses
- * 6x 64 bit registers
- * 3x integers
- * 5x address pointers,
- */
- ae_f64 a0;
- ae_f64 a1;
- ae_valign u;
- ae_f16x4 coef4;
- ae_f32x2 d0;
- ae_f32x2 d1;
- ae_f32x2 data2;
- ae_f16x4 *coefp;
- ae_f32x2 *dp;
- ae_f32 *dp0;
- ae_f32 *dp1;
- int i;
- int j;
- ae_f32 *wp = wp0;
- const int inc = nch * sizeof(int32_t);
-
- if (nch == 2) {
- /* Move data pointer back by one sample to start from right
- * channel sample. Discard read value p0.
- */
- dp = (ae_f32x2 *)rp;
- AE_L32_XC(d0, (ae_f32 *)dp, -sizeof(ae_f32));
-
- /* Reset coefficient pointer and clear accumulator */
- coefp = (ae_f16x4 *)cp;
- a0 = AE_ZERO64();
- a1 = AE_ZERO64();
-
- /* Compute FIR filter for current channel with four
- * taps per every loop iteration. Four coefficients
- * are loaded simultaneously. Data is read
- * from interleaved buffer with stride of channels
- * count.
- */
- for (i = 0; i < taps_div_4; i++) {
- /* Load four coefficients */
- AE_LA16X4_IP(coef4, u, coefp);
-
- /* Load two data samples from two channels */
- AE_L32X2_XC(d0, dp, inc); /* r0, l0 */
- AE_L32X2_XC(d1, dp, inc); /* r1, l1 */
-
- /* Select to data2 sequential samples from a channel
- * and then accumulate to a0 and a1
- * data2_h * coef4_3 + data2_l * coef4_2.
- * The data is 32 bits Q1.31 and coefficient 16 bits
- * Q1.15. The accumulators are Q17.47.
- */
- data2 = AE_SEL32_LL(d0, d1); /* l0, l1 */
- AE_MULAAFD32X16_H3_L2(a0, data2, coef4);
- data2 = AE_SEL32_HH(d0, d1); /* r0, r1 */
- AE_MULAAFD32X16_H3_L2(a1, data2, coef4);
-
- /* Load two data samples from two channels */
- AE_L32X2_XC(d0, dp, inc); /* r2, l2 */
- AE_L32X2_XC(d1, dp, inc); /* r3, l3 */
-
- /* Accumulate
- * data2_h * coef4_1 + data2_l * coef4_0.
- */
- data2 = AE_SEL32_LL(d0, d1); /* l2, l3 */
- AE_MULAAFD32X16_H1_L0(a0, data2, coef4);
- data2 = AE_SEL32_HH(d0, d1); /* r2, r3 */
- AE_MULAAFD32X16_H1_L0(a1, data2, coef4);
- }
-
- /* Scale FIR output with right shifts, round/saturate
- * to Q1.31, and store 32 bit output.
- */
- AE_S32_L_XP(AE_ROUND32F48SSYM(AE_SRAA64(a0, shift)), wp,
- sizeof(int32_t));
- AE_S32_L_XP(AE_ROUND32F48SSYM(AE_SRAA64(a1, shift)), wp,
- sizeof(int32_t));
-
- return;
- }
-
- dp1 = (ae_f32 *)rp;
- for (j = 0; j < nch; j++) {
- /* Copy pointer and advance to next ch with dummy load */
- dp0 = dp1;
- AE_L32_XC(d0, dp1, -sizeof(ae_f32));
-
- /* Reset coefficient pointer and clear accumulator */
- coefp = (ae_f16x4 *)cp;
- a0 = AE_ZERO64();
-
- /* Compute FIR filter for current channel with four
- * taps per every loop iteration. Data is read from
- * interleaved buffer with stride of channels count.
- */
- for (i = 0; i < taps_div_4; i++) {
- /* Load four coefficients */
- AE_LA16X4_IP(coef4, u, coefp);
-
- /* Load two data samples, place to high and
- * low of data2.
- */
- AE_L32_XC(d0, dp0, inc);
- AE_L32_XC(d1, dp0, inc);
- data2 = AE_SEL32_LL(d0, d1);
-
- /* Accumulate
- * data2_h * coef4_3 + data2_l* coef4_2.
- * The data is 32 bits Q1.31 and coefficient 16 bits
- * Q1.15. The accumulator is Q17.47.
- */
- AE_MULAAFD32X16_H3_L2(a0, data2, coef4);
-
- /* Repeat with next two samples */
- AE_L32_XC(d0, dp0, inc);
- AE_L32_XC(d1, dp0, inc);
- data2 = AE_SEL32_LL(d0, d1);
-
- /* Accumulate
- * data2_h * coef4_1 + data2_l * coef4_0.
- */
- AE_MULAAFD32X16_H1_L0(a0, data2, coef4);
- }
-
- /* Scale FIR output with right shifts, round/saturate Q17.47
- * to Q1.31, and store 32 bit output. Advance write
- * pointer to next sample.
- */
- AE_S32_L_XP(AE_ROUND32F48SSYM(AE_SRAA64(a0, shift)), wp,
- sizeof(int32_t));
- }
-}
-
-#else /* 32bit coefficients version */
-
-static inline void fir_filter(ae_f32 *rp, const void *cp, ae_f32 *wp0,
- const int taps_div_4, const int shift, const int nch)
-{
- /* This function uses
- * 6x 64 bit registers
- * 3x integers
- * 5x address pointers,
- */
- ae_f64 a0;
- ae_f64 a1;
- ae_f24x2 data2 = AE_ZERO24();
- ae_f24x2 coef2 = AE_ZERO24();
- ae_f24x2 d0 = AE_ZERO24();
- ae_f24x2 d1 = AE_ZERO24();
- ae_f24x2 *coefp;
- ae_f24x2 *dp;
- ae_f24 *dp1;
- ae_f24 *dp0;
- int i;
- int j;
- ae_f32 *wp = wp0;
- const int inc = nch * sizeof(int32_t);
-
- if (nch == 2) {
- /* Move data pointer back by one sample to start from right
- * channel sample. Discard read value p0.
- */
- dp = (ae_f24x2 *)rp;
- AE_L32F24_XC(d0, (ae_f24 *)dp, -sizeof(ae_f24));
-
- /* Reset coefficient pointer and clear accumulator */
- coefp = (ae_f24x2 *)cp;
- a0 = AE_ZERO64();
- a1 = AE_ZERO64();
-
- /* Compute FIR filter for current channel with four
- * taps per every loop iteration. Two coefficients
- * are loaded simultaneously. Data is read
- * from interleaved buffer with stride of channels
- * count.
- */
- for (i = 0; i < taps_div_4; i++) {
- /* Load two coefficients. Coef2_h contains tap *coefp
- * and coef2_l contains the next tap.
- */
- /* TODO: Ensure coefficients are 64 bits aligned */
- AE_L32X2F24_IP(coef2, coefp, sizeof(ae_f24x2));
-
- /* Load two data samples from two channels */
- AE_L32X2F24_XC(d0, dp, inc); /* r0, l0 */
- AE_L32X2F24_XC(d1, dp, inc); /* r1, l1 */
-
- /* Select to d0 successive left channel samples, to d1
- * successive right channel samples. Then Accumulate
- * to a0 and a1
- * data2_h * coef2_h + data2_l * coef2_l. The Q1.31
- * data and Q1.15 coefficients are used as 24 bits as
- * Q1.23 values.
- */
- data2 = AE_SELP24_LL(d0, d1);
- AE_MULAAFP24S_HH_LL(a0, data2, coef2);
- data2 = AE_SELP24_HH(d0, d1);
- AE_MULAAFP24S_HH_LL(a1, data2, coef2);
-
- /* Repeat for next two taps */
- AE_L32X2F24_IP(coef2, coefp, sizeof(ae_f24x2));
- AE_L32X2F24_XC(d0, dp, inc); /* r2, l2 */
- AE_L32X2F24_XC(d1, dp, inc); /* r3, l3 */
- data2 = AE_SELP24_LL(d0, d1);
- AE_MULAAFP24S_HH_LL(a0, data2, coef2);
- data2 = AE_SELP24_HH(d0, d1);
- AE_MULAAFP24S_HH_LL(a1, data2, coef2);
- }
-
- /* Scale FIR output with right shifts, round/saturate
- * to Q1.31, and store 32 bit output.
- */
- AE_S32_L_XP(AE_ROUND32F48SSYM(AE_SRAA64(a0, shift)), wp,
- sizeof(int32_t));
- AE_S32_L_XP(AE_ROUND32F48SSYM(AE_SRAA64(a1, shift)), wp,
- sizeof(int32_t));
-
- return;
- }
-
- dp1 = (ae_f24 *)rp;
- for (j = 0; j < nch; j++) {
- /* Copy pointer and advance to next ch with dummy load */
- dp0 = dp1;
- AE_L32F24_XC(data2, dp1, -sizeof(ae_f24));
-
- /* Reset coefficient pointer and clear accumulator */
- coefp = (ae_f24x2 *)cp;
- a0 = AE_ZERO64();
-
- /* Compute FIR filter for current channel with four
- * taps per every loop iteration. Data is read from
- * interleaved buffer with stride of channels count.
- */
- for (i = 0; i < taps_div_4; i++) {
- /* Load two coefficients */
- coef2 = *coefp++;
-
- /* Load two data samples, place to high and
- * low of data2.
- */
- AE_L32F24_XC(d0, dp0, inc);
- AE_L32F24_XC(d1, dp0, inc);
- data2 = AE_SELP24_LL(d0, d1);
-
- /* Accumulate to data2_h * coef2_h +
- * data2_l*coef2_l. The Q1.31 bit data is used
- * as Q1.23 from MSB side bits of the 32 bit
- * word. The accumulator m is Q17.47.
- */
- AE_MULAAFD24_HH_LL(a0, data2, coef2);
-
- /* Repeat the same for next two filter taps */
- coef2 = *coefp++;
- AE_L32F24_XC(d0, dp0, inc);
- AE_L32F24_XC(d1, dp0, inc);
- data2 = AE_SELP24_LL(d0, d1);
- AE_MULAAFD24_HH_LL(a0, data2, coef2);
- }
-
- /* Scale FIR output with right shifts, round/saturate Q17.47
- * to Q1.31, and store 32 bit output. Advance write
- * pointer to next sample.
- */
- AE_S32_L_XP(AE_ROUND32F48SSYM(AE_SRAA64(a0, shift)), wp,
- sizeof(int32_t));
- }
-}
-
-#endif /* 32bit coefficients version */
-
-void src_polyphase_stage_cir(struct src_stage_prm *s)
-{
- /* This function uses
- * 1x 64 bit registers
- * 16x integers
- * 7x address pointers,
- */
- ae_int32x2 q = AE_ZERO32();
- ae_f32 *rp;
- ae_f32 *wp;
- int i;
- int n;
- int m;
- int n_wrap_buf;
- int n_min;
- struct src_state *fir = s->state;
- struct src_stage *cfg = s->stage;
- int32_t *fir_end = &fir->fir_delay[fir->fir_delay_size];
- int32_t *out_delay_end = &fir->out_delay[fir->out_delay_size];
- const void *cp; /* Can be int32_t or int16_t */
- const size_t out_size = fir->out_delay_size * sizeof(int32_t);
- const int nch = s->nch;
- const int nch_x_odm = cfg->odm * nch;
- const int blk_in_words = nch * cfg->blk_in;
- const int blk_out_words = nch * cfg->num_of_subfilters;
- const int sz = sizeof(int32_t);
- const int n_sz = -sizeof(int32_t);
- const int rewind_sz = sz * (nch * (cfg->blk_in
- + (cfg->num_of_subfilters - 1) * cfg->idm) - nch);
- const int nch_x_idm_sz = -nch * cfg->idm * sizeof(int32_t);
- const int taps_div_4 = cfg->subfilter_length >> 2;
-
-#if SRC_SHORT
- const size_t subfilter_size = cfg->subfilter_length * sizeof(int16_t);
-#else
- const size_t subfilter_size = cfg->subfilter_length * sizeof(int32_t);
-#endif
-
- for (n = 0; n < s->times; n++) {
- /* Input data to filter */
- m = blk_in_words;
-
- /* Setup circular buffer for FIR input data delay */
- AE_SETCBEGIN0(fir->fir_delay);
- AE_SETCEND0(fir_end);
-
- while (m > 0) {
- /* Number of words until circular wrap */
- n_wrap_buf = s->x_end_addr - s->x_rptr;
- n_min = (m < n_wrap_buf) ? m : n_wrap_buf;
- m -= n_min;
- for (i = 0; i < n_min; i++) {
- /* Load 32 bits sample to accumulator,
- * advance pointer.
- */
- AE_L32_XP(q, (ae_int32 *)s->x_rptr, sz);
-
- /* Store to circular buffer, advance pointer */
- AE_S32_L_XC(q, (ae_int32 *)fir->fir_wp, n_sz);
- }
-
- /* Check for wrap */
- src_circ_inc_wrap(&s->x_rptr, s->x_end_addr, s->x_size);
- }
-
- /* Do filter */
- cp = cfg->coefs; /* Reset to 1st coefficient */
- rp = (ae_f32 *)fir->fir_wp;
-
- /* Do circular modification to pointer rp by amount of
- * rewind to to data start. Loaded value q is discarded.
- */
- AE_L32_XC(q, rp, rewind_sz);
-
- /* Reset FIR write pointer and compute all polyphase
- * sub-filters.
- */
- wp = (ae_f32 *)fir->out_rp;
- for (i = 0; i < cfg->num_of_subfilters; i++) {
- fir_filter(rp, cp, wp, taps_div_4, cfg->shift, nch);
- wp += nch_x_odm;
- cp += subfilter_size;
- src_circ_inc_wrap((int32_t **)&wp, out_delay_end,
- out_size);
-
- /* Circular advance pointer rp by number of
- * channels x input delay multiplier. Loaded value q
- * is discarded.
- */
- AE_L32_XC(q, rp, nch_x_idm_sz);
- }
-
- /* Output */
-
- /* Setup circular buffer for SRC out delay access */
- AE_SETCBEGIN0(fir->out_delay);
- AE_SETCEND0(out_delay_end);
- m = blk_out_words;
- while (m > 0) {
- n_wrap_buf = s->y_end_addr - s->y_wptr;
- n_min = (m < n_wrap_buf) ? m : n_wrap_buf;
- m -= n_min;
- for (i = 0; i < n_min; i++) {
- /* Circular load followed by linear store,
- * advance read and write pointers.
- */
- AE_L32_XC(q, (ae_int32 *)fir->out_rp, sz);
- AE_S32_L_XP(q, (ae_int32 *)s->y_wptr, sz);
- }
-
- /* Check wrap */
- src_circ_inc_wrap(&s->y_wptr, s->y_end_addr, s->y_size);
- }
- }
-}
-
-void src_polyphase_stage_cir_s24(struct src_stage_prm *s)
-{
- /* This function uses
- * 1x 64 bit registers
- * 16x integers
- * 7x address pointers,
- */
- ae_int32x2 q = AE_ZERO32();
- ae_f32 *rp;
- ae_f32 *wp;
- int i;
- int n;
- int m;
- int n_wrap_buf;
- int n_min;
-
- struct src_state *fir = s->state;
- struct src_stage *cfg = s->stage;
- int32_t *fir_end = &fir->fir_delay[fir->fir_delay_size];
- int32_t *out_delay_end = &fir->out_delay[fir->out_delay_size];
- const void *cp; /* Can be int32_t or int16_t */
- const size_t out_size = fir->out_delay_size * sizeof(int32_t);
- const int nch = s->nch;
- const int nch_x_odm = cfg->odm * nch;
- const int blk_in_words = nch * cfg->blk_in;
- const int blk_out_words = nch * cfg->num_of_subfilters;
- const int sz = sizeof(int32_t);
- const int n_sz = -sizeof(int32_t);
- const int rewind_sz = sz * (nch * (cfg->blk_in
- + (cfg->num_of_subfilters - 1) * cfg->idm) - nch);
- const int nch_x_idm_sz = -nch * cfg->idm * sizeof(int32_t);
- const int taps_div_4 = cfg->subfilter_length >> 2;
-
-#if SRC_SHORT
- const size_t subfilter_size = cfg->subfilter_length * sizeof(int16_t);
-#else
- const size_t subfilter_size = cfg->subfilter_length * sizeof(int32_t);
-#endif
-
- for (n = 0; n < s->times; n++) {
- /* Input data */
- m = blk_in_words;
-
- /* Setup circular buffer for FIR input data delay */
- AE_SETCBEGIN0(fir->fir_delay);
- AE_SETCEND0(fir_end);
-
- while (m > 0) {
- /* Number of words without circular wrap */
- n_wrap_buf = s->x_end_addr - s->x_rptr;
- n_min = (m < n_wrap_buf) ? m : n_wrap_buf;
- m -= n_min;
- for (i = 0; i < n_min; i++) {
- /* Load 32 bits sample to accumulator
- * and left shift by 8, advance read
- * pointer.
- */
- AE_L32_XP(q, (ae_int32 *)s->x_rptr, sz);
- AE_S32_L_XC(AE_SLAI32(q, 8),
- (ae_int32 *)fir->fir_wp, n_sz);
- }
-
- /* Check for wrap */
- src_circ_inc_wrap(&s->x_rptr, s->x_end_addr, s->x_size);
- }
-
- /* Do filter */
- cp = cfg->coefs; /* Reset to 1st coefficient */
- rp = (ae_f32 *)fir->fir_wp;
-
- /* Do circular modification to pointer rp by amount of
- * rewind to to data start. Loaded value q is discarded.
- */
- AE_L32_XC(q, rp, rewind_sz);
-
- /* Reset FIR output write pointer and compute all polyphase
- * sub-filters.
- */
- wp = (ae_f32 *)fir->out_rp;
- for (i = 0; i < cfg->num_of_subfilters; i++) {
- fir_filter(rp, cp, wp, taps_div_4, cfg->shift, nch);
- wp += nch_x_odm;
- cp += subfilter_size;
- src_circ_inc_wrap((int32_t **)&wp, out_delay_end,
- out_size);
-
- /* Circular advance pointer rp by number of
- * channels x input delay multiplier. Loaded value q
- * is discarded.
- */
- AE_L32_XC(q, rp, nch_x_idm_sz);
- }
-
- /* Output */
-
- /* Setup circular buffer for SRC out delay access */
- AE_SETCBEGIN0(fir->out_delay);
- AE_SETCEND0(out_delay_end);
- m = blk_out_words;
- while (m > 0) {
- n_wrap_buf = s->y_end_addr - s->y_wptr;
- n_min = (m < n_wrap_buf) ? m : n_wrap_buf;
- m -= n_min;
- for (i = 0; i < n_min; i++) {
- /* Circular load for 32 bit sample,
- * advance read pointer.
- */
- AE_L32_XC(q, (ae_int32 *)fir->out_rp, sz);
-
- /* Store value as shifted right by 8
- * for sign extended 24 bit value,
- * advance write pointer.
- */
- AE_S32_L_XP(AE_SRAI32(q, 8),
- (ae_int32 *)s->y_wptr, sz);
- }
-
- /* Check wrap */
- src_circ_inc_wrap(&s->y_wptr, s->y_end_addr, s->y_size);
- }
- }
-}
-
-#endif
diff --git a/src/audio/switch.c b/src/audio/switch.c
deleted file mode 100644
index cde300b..0000000
--- a/src/audio/switch.c
+++ /dev/null
@@ -1,102 +0,0 @@
-/*
- * Copyright (c) 2016, Intel Corporation
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- * * Redistributions of source code must retain the above copyright
- * notice, this list of conditions and the following disclaimer.
- * * Redistributions in binary form must reproduce the above copyright
- * notice, this list of conditions and the following disclaimer in the
- * documentation and/or other materials provided with the distribution.
- * * Neither the name of the Intel Corporation nor the
- * names of its contributors may be used to endorse or promote products
- * derived from this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
- * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
- * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
- * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
- * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
- * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
- * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
- * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
- * POSSIBILITY OF SUCH DAMAGE.
- *
- * Author: Liam Girdwood <liam.r.girdwood@linux.intel.com>
- */
-
-#include <stdint.h>
-#include <stddef.h>
-#include <sof/lock.h>
-#include <sof/list.h>
-#include <sof/stream.h>
-#include <sof/audio/component.h>
-
-/* tracing */
-#define trace_switch(__e) trace_event(TRACE_CLASS_SWITCH, __e)
-#define trace_switch_error(__e) trace_error(TRACE_CLASS_SWITCH, __e)
-#define tracev_switch(__e) tracev_event(TRACE_CLASS_SWITCH, __e)
-
-static struct comp_dev *switch_new(struct sof_ipc_comp *comp)
-{
- trace_switch("new");
-
- return NULL;
-}
-
-static void switch_free(struct comp_dev *dev)
-{
-
-}
-
-/* set component audio stream parameters */
-static int switch_params(struct comp_dev *dev)
-{
-
- return 0;
-}
-
-/* used to pass standard and bespoke commands (with data) to component */
-static int switch_cmd(struct comp_dev *dev, int cmd, void *data)
-{
- /* switch will use buffer "connected" status */
- return 0;
-}
-
-/* copy and process stream data from source to sink buffers */
-static int switch_copy(struct comp_dev *dev)
-{
-
- return 0;
-}
-
-static int switch_reset(struct comp_dev *dev)
-{
- return 0;
-}
-
-static int switch_prepare(struct comp_dev *dev)
-{
- return 0;
-}
-
-struct comp_driver comp_switch = {
- .type = SOF_COMP_SWITCH,
- .ops = {
- .new = switch_new,
- .free = switch_free,
- .params = switch_params,
- .cmd = switch_cmd,
- .copy = switch_copy,
- .prepare = switch_prepare,
- .reset = switch_reset,
- },
-};
-
-void sys_comp_switch_init(void)
-{
- comp_register(&comp_switch);
-}
diff --git a/src/audio/tone.c b/src/audio/tone.c
deleted file mode 100644
index f98e5e0..0000000
--- a/src/audio/tone.c
+++ /dev/null
@@ -1,719 +0,0 @@
-/*
- * Copyright (c) 2016, Intel Corporation
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- * * Redistributions of source code must retain the above copyright
- * notice, this list of conditions and the following disclaimer.
- * * Redistributions in binary form must reproduce the above copyright
- * notice, this list of conditions and the following disclaimer in the
- * documentation and/or other materials provided with the distribution.
- * * Neither the name of the Intel Corporation nor the
- * names of its contributors may be used to endorse or promote products
- * derived from this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
- * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
- * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
- * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
- * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
- * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
- * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
- * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
- * POSSIBILITY OF SUCH DAMAGE.
- *
- * Author: Seppo Ingalsuo <seppo.ingalsuo@linux.intel.com>
- * Liam Girdwood <liam.r.girdwood@linux.intel.com>
- * Keyon Jie <yang.jie@linux.intel.com>
- */
-
-#include <stdint.h>
-#include <stddef.h>
-#include <errno.h>
-#include <stdbool.h>
-#include <sof/sof.h>
-#include <sof/lock.h>
-#include <sof/list.h>
-#include <sof/stream.h>
-#include <sof/alloc.h>
-#include <sof/work.h>
-#include <sof/clock.h>
-#include <sof/audio/component.h>
-#include <sof/audio/format.h>
-#include <sof/audio/pipeline.h>
-#include <sof/math/trig.h>
-#include <uapi/ipc.h>
-#include <uapi/tone.h>
-
-#ifdef MODULE_TEST
-#include <stdio.h>
-#endif
-
-#define trace_tone(__e) trace_event(TRACE_CLASS_TONE, __e)
-#define tracev_tone(__e) tracev_event(TRACE_CLASS_TONE, __e)
-#define trace_tone_error(__e) trace_error(TRACE_CLASS_TONE, __e)
-
-/* Convert float frequency in Hz to Q16.16 fractional format */
-#define TONE_FREQ(f) Q_CONVERT_FLOAT(f, 16)
-
-/* Convert float gain to Q1.31 fractional format */
-#define TONE_GAIN(v) Q_CONVERT_FLOAT(v, 31)
-
-/* Set default tone amplitude and frequency */
-#define TONE_AMPLITUDE_DEFAULT TONE_GAIN(0.1) /* -20 dB */
-#define TONE_FREQUENCY_DEFAULT TONE_FREQ(997.0)
-#define TONE_NUM_FS 13 /* Table size for 8-192 kHz range */
-
-/* 2*pi/Fs lookup tables in Q1.31 for each Fs */
-static const int32_t tone_fs_list[TONE_NUM_FS] = {
- 8000, 11025, 16000, 22050, 24000, 32000, 44100, 48000,
- 64000, 88200, 96000, 176400, 192000
-};
-static const int32_t tone_pi2_div_fs[TONE_NUM_FS] = {
- 1686630, 1223858, 843315, 611929, 562210, 421657, 305965,
- 281105, 210829, 152982, 140552, 76491, 70276
-};
-
-/* tone component private data */
-
-struct tone_state {
- int mute;
- int32_t a; /* Current amplitude Q1.31 */
- int32_t a_target; /* Target amplitude Q1.31 */
- int32_t ampl_coef; /* Amplitude multiplier Q2.30 */
- int32_t c; /* Coefficient 2*pi/Fs Q1.31 */
- int32_t f; /* Frequency Q16.16 */
- int32_t freq_coef; /* Frequency multiplier Q2.30 */
- int32_t fs; /* Sample rate in Hertz Q32.0 */
- int32_t ramp_step; /* Amplitude ramp step Q1.31 */
- int32_t w; /* Angle radians Q4.28 */
- int32_t w_step; /* Angle step Q4.28 */
- uint32_t block_count;
- uint32_t repeat_count;
- uint32_t repeats; /* Number of repeats for tone (sweep steps) */
- uint32_t sample_count;
- uint32_t samples_in_block; /* Samples in 125 us block */
- uint32_t tone_length; /* Active length in 125 us blocks */
- uint32_t tone_period; /* Active + idle time in 125 us blocks */
-};
-
-struct comp_data {
- uint32_t period_bytes;
- uint32_t channels;
- uint32_t frame_bytes;
- uint32_t rate;
- struct tone_state sg[PLATFORM_MAX_CHANNELS];
- void (*tone_func)(struct comp_dev *dev, struct comp_buffer *sink,
- uint32_t frames);
-};
-
-static int32_t tonegen(struct tone_state *sg);
-static void tonegen_control(struct tone_state *sg);
-static void tonegen_update_f(struct tone_state *sg, int32_t f);
-
-/*
- * Tone generator algorithm code
- */
-
-static inline void tone_circ_inc_wrap(int32_t **ptr, int32_t *end, size_t size)
-{
- if (*ptr >= end)
- *ptr = (int32_t *) ((size_t) * ptr - size);
-}
-
-static void tone_s32_default(struct comp_dev *dev, struct comp_buffer *sink,
- uint32_t frames)
-{
- struct comp_data *cd = comp_get_drvdata(dev);
- int32_t *dest = (int32_t*) sink->w_ptr;
- int i;
- int n;
- int n_wrap_dest;
- int n_min;
- int nch = cd->channels;
-
- n = frames * nch;
- while (n > 0) {
- n_wrap_dest = (int32_t *) sink->end_addr - dest;
- n_min = (n < n_wrap_dest) ? n : n_wrap_dest;
- /* Process until wrap or completed n */
- while (n_min > 0) {
- n -= nch;
- n_min -= nch;
- for (i = 0; i < nch; i++) {
- tonegen_control(&cd->sg[i]);
- *dest = tonegen(&cd->sg[i]);
- dest++;
- }
- }
- tone_circ_inc_wrap(&dest, sink->end_addr, sink->size);
- }
-}
-
-static int32_t tonegen(struct tone_state *sg)
-{
- int64_t sine;
- int64_t w;
-
- /* sg->w is angle in Q4.28 radians format, sin() returns Q1.31 */
- /* sg->a is amplitude as Q1.31 */
- sine =
- q_mults_32x32(sin_fixed(sg->w), sg->a,
- Q_SHIFT_BITS_64(31, 31, 31));
-
- /* Next point */
- w = (int64_t) sg->w + sg->w_step;
- sg->w = (w > PI_MUL2_Q4_28)
- ? (int32_t) (w - PI_MUL2_Q4_28) : (int32_t) w;
-
- if (sg->mute)
- return 0;
- else
- return(int32_t) sine; /* Q1.31 no saturation need */
-}
-
-static void tonegen_control(struct tone_state *sg)
-{
- int64_t a;
- int64_t p;
-
- /* Count samples, 125 us blocks */
- sg->sample_count++;
- if (sg->sample_count < sg->samples_in_block)
- return;
-
- sg->sample_count = 0;
- if (sg->block_count < INT32_MAX)
- sg->block_count++;
-
- /* Fade-in ramp during tone */
- if (sg->block_count < sg->tone_length) {
- if (sg->a == 0)
- sg->w = 0; /* Reset phase to have less clicky ramp */
-
- if (sg->a > sg->a_target) {
- a = (int64_t) sg->a - sg->ramp_step;
- if (a < sg->a_target)
- a = sg->a_target;
-
- } else {
- a = (int64_t) sg->a + sg->ramp_step;
- if (a > sg->a_target)
- a = sg->a_target;
- }
- sg->a = (int32_t) a;
- }
-
- /* Fade-out ramp after tone*/
- if (sg->block_count > sg->tone_length) {
- a = (int64_t) sg->a - sg->ramp_step;
- if (a < 0)
- a = 0;
-
- sg->a = (int32_t) a;
- }
-
- /* New repeated tone, update for frequency or amplitude sweep */
- if ((sg->block_count > sg->tone_period)
- && (sg->repeat_count + 1 < sg->repeats)) {
- sg->block_count = 0;
- if (sg->ampl_coef > 0) {
- sg->a_target =
- sat_int32(q_multsr_32x32(sg->a_target,
- sg->ampl_coef, Q_SHIFT_BITS_64(31, 30, 31)));
- sg->a = (sg->ramp_step > sg->a_target)
- ? sg->a_target : sg->ramp_step;
- }
- if (sg->freq_coef > 0) {
- /* f is Q16.16, freq_coef is Q2.30 */
- p = q_multsr_32x32(sg->f, sg->freq_coef,
- Q_SHIFT_BITS_64(16, 30, 16));
- tonegen_update_f(sg, (int32_t) p); /* No saturation */
- }
- sg->repeat_count++;
- }
-}
-
-/* Set sine amplitude */
-static inline void tonegen_set_a(struct tone_state *sg, int32_t a)
-{
- sg->a_target = a;
-}
-
-/* Repeated number of beeps */
-static void tonegen_set_repeats(struct tone_state *sg, uint32_t r)
-{
- sg->repeats = r;
-}
-
-/* The next functions support zero as shortcut for defaults to get
- * make a nicer API without need to remember the neutral steady
- * non-swept tone settings.
- */
-
-/* Multiplication factor for frequency as Q2.30 for logarithmic change */
-static void tonegen_set_freq_mult(struct tone_state *sg, int32_t fm)
-{
- sg->freq_coef = (fm > 0) ? fm : ONE_Q2_30; /* Set freq mult to 1.0 */
-}
-
-/* Multiplication factor for amplitude as Q2.30 for logarithmic change */
-static void tonegen_set_ampl_mult(struct tone_state *sg, int32_t am)
-{
- sg->ampl_coef = (am > 0) ? am : ONE_Q2_30; /* Set ampl mult to 1.0 */
-}
-
-/* Tone length in samples, this is the active length of tone */
-static void tonegen_set_length(struct tone_state *sg, uint32_t tl)
-{
- sg->tone_length = (tl > 0) ? tl : INT32_MAX; /* Count rate 125 us */
-}
-
-/* Tone period in samples, this is the length including the pause after beep */
-static void tonegen_set_period(struct tone_state *sg, uint32_t tp)
-{
- sg->tone_period = (tp > 0) ? tp : INT32_MAX; /* Count rate 125 us */
-}
-
-/* Tone ramp parameters:
- * step - Value that is added or subtracted to amplitude. A zero or negative
- * number disables the ramp and amplitude is immediately modified to
- * final value.
- */
-
-static inline void tonegen_set_linramp(struct tone_state *sg, int32_t step)
-{
- sg->ramp_step = (step > 0) ? step : INT32_MAX;
-}
-
-static inline int32_t tonegen_get_f(struct tone_state *sg)
-{
- return sg->f;
-}
-
-static inline int32_t tonegen_get_a(struct tone_state *sg)
-{
- return sg->a_target;
-}
-
-static inline void tonegen_mute(struct tone_state *sg)
-{
- sg->mute = 1;
-}
-
-static inline void tonegen_unmute(struct tone_state *sg)
-{
- sg->mute = 0;
-}
-
-static void tonegen_update_f(struct tone_state *sg, int32_t f)
-{
- int64_t w_tmp;
- int64_t f_max;
-
- /* Calculate Fs/2, fs is Q32.0, f is Q16.16 */
- f_max = Q_SHIFT_LEFT((int64_t) sg->fs, 0, 16 - 1);
- f_max = (f_max > INT32_MAX) ? INT32_MAX : f_max;
- sg->f = (f > f_max) ? f_max : f;
- /* Q16 x Q31 -> Q28 */
- w_tmp = q_multsr_32x32(sg->f, sg->c, Q_SHIFT_BITS_64(16, 31, 28));
- w_tmp = (w_tmp > PI_Q4_28) ? PI_Q4_28 : w_tmp; /* Limit to pi Q4.28 */
- sg->w_step = (int32_t) w_tmp;
-
-#ifdef MODULE_TEST
- printf("Fs=%d, f_max=%d, f_new=%.3f\n",
- sg->fs, (int32_t) (f_max >> 16), sg->f / 65536.0);
-#endif
-}
-
-static void tonegen_reset(struct tone_state *sg)
-{
- sg->mute = 1;
- sg->a = 0;
- sg->a_target = TONE_AMPLITUDE_DEFAULT;
- sg->c = 0;
- sg->f = TONE_FREQUENCY_DEFAULT;
- sg->w = 0;
- sg->w_step = 0;
-
- sg->block_count = 0;
- sg->repeat_count = 0;
- sg->repeats = 0;
- sg->sample_count = 0;
- sg->samples_in_block = 0;
-
- /* Continuous tone */
- sg->freq_coef = ONE_Q2_30; /* Set freq multiplier to 1.0 */
- sg->ampl_coef = ONE_Q2_30; /* Set ampl multiplier to 1.0 */
- sg->tone_length = INT32_MAX;
- sg->tone_period = INT32_MAX;
- sg->ramp_step = ONE_Q1_31; /* Set lin ramp modification to max */
-}
-
-static int tonegen_init(struct tone_state *sg, int32_t fs, int32_t f, int32_t a)
-{
- int idx;
- int i;
-
- sg->a_target = a;
- sg->a = (sg->ramp_step > sg->a_target) ? sg->a_target : sg->ramp_step;
-
- idx = -1;
- sg->mute = 1;
- sg->fs = 0;
-
- /* Find index of current sample rate and then get from lookup table the
- * corresponding 2*pi/Fs value.
- */
- for (i = 0; i < TONE_NUM_FS; i++) {
- if (fs == tone_fs_list[i])
- idx = i;
- }
-
- if (idx < 0) {
- sg->w_step = 0;
- return -EINVAL;
- }
-
- sg->fs = fs;
- sg->c = tone_pi2_div_fs[idx]; /* Store 2*pi/Fs */
- sg->mute = 0;
- tonegen_update_f(sg, f);
-
- /* 125us as Q1.31 is 268435, calculate fs * 125e-6 in Q31.0 */
- sg->samples_in_block =
- (int32_t) q_multsr_32x32(fs, 268435, Q_SHIFT_BITS_64(0, 31, 0));
-
- return 0;
-}
-
-/*
- * End of algorithm code. Next the standard component methods.
- */
-
-static struct comp_dev *tone_new(struct sof_ipc_comp *comp)
-{
- struct comp_dev *dev;
- struct sof_ipc_comp_tone *tone;
- struct sof_ipc_comp_tone *ipc_tone = (struct sof_ipc_comp_tone *) comp;
- struct comp_data *cd;
- int i;
-
- trace_tone("new");
-
- dev = rzalloc(RZONE_RUNTIME, SOF_MEM_CAPS_RAM,
- COMP_SIZE(struct sof_ipc_comp_tone));
- if (dev == NULL)
- return NULL;
-
- tone = (struct sof_ipc_comp_tone *) &dev->comp;
- memcpy(tone, ipc_tone, sizeof(struct sof_ipc_comp_tone));
-
- cd = rzalloc(RZONE_RUNTIME, SOF_MEM_CAPS_RAM, sizeof(*cd));
- if (cd == NULL) {
- rfree(dev);
- return NULL;
- }
-
- comp_set_drvdata(dev, cd);
- cd->tone_func = tone_s32_default;
-
- cd->rate = ipc_tone->sample_rate;
-
- /* Reset tone generator and set channels volumes to default */
- for (i = 0; i < PLATFORM_MAX_CHANNELS; i++)
- tonegen_reset(&cd->sg[i]);
-
- dev->state = COMP_STATE_READY;
- return dev;
-}
-
-static void tone_free(struct comp_dev *dev)
-{
- struct tone_data *td = comp_get_drvdata(dev);
-
- trace_tone("fre");
-
- rfree(td);
- rfree(dev);
-}
-
-/* set component audio stream parameters */
-static int tone_params(struct comp_dev *dev)
-{
- struct comp_data *cd = comp_get_drvdata(dev);
- struct sof_ipc_comp_config *config = COMP_GET_CONFIG(dev);
-
- trace_tone("par");
-
- /* Tone supports only S32_LE PCM format atm */
- if (config->frame_fmt != SOF_IPC_FRAME_S32_LE)
- return -EINVAL;
-
- trace_value(config->frame_fmt);
- dev->params.frame_fmt = config->frame_fmt;
-
- /* Need to compute this in non-host endpoint */
- dev->frame_bytes = comp_frame_bytes(dev);
-
- /* calculate period size based on config */
- cd->period_bytes = dev->frames * dev->frame_bytes;
-
- return 0;
-}
-
-static int tone_cmd_get_value(struct comp_dev *dev,
- struct sof_ipc_ctrl_data *cdata)
-{
- struct comp_data *cd = comp_get_drvdata(dev);
- int j;
-
- trace_tone("mgt");
-
- if (cdata->cmd == SOF_CTRL_CMD_SWITCH) {
- for (j = 0; j < cdata->num_elems; j++) {
- cdata->chanv[j].channel = j;
- cdata->chanv[j].value = !cd->sg[j].mute;
- trace_value(j);
- trace_value(cd->sg[j].mute);
- }
- }
- return 0;
-}
-
-static int tone_cmd_set_value(struct comp_dev *dev, struct sof_ipc_ctrl_data *cdata)
-{
- struct comp_data *cd = comp_get_drvdata(dev);
- int j;
- uint32_t ch;
- bool val;
-
- if (cdata->cmd == SOF_CTRL_CMD_SWITCH) {
- trace_tone("mst");
- for (j = 0; j < cdata->num_elems; j++) {
- ch = cdata->chanv[j].channel;
- val = cdata->chanv[j].value;
- tracev_value(ch);
- tracev_value(val);
- if (ch >= PLATFORM_MAX_CHANNELS) {
- trace_tone_error("che");
- return -EINVAL;
- }
-
- if (val)
- tonegen_unmute(&cd->sg[ch]);
- else
- tonegen_mute(&cd->sg[ch]);
-
- }
- } else {
- trace_tone_error("ste");
- return -EINVAL;
- }
-
- return 0;
-}
-
-static int tone_cmd_set_data(struct comp_dev *dev,
- struct sof_ipc_ctrl_data *cdata)
-{
- struct comp_data *cd = comp_get_drvdata(dev);
- struct sof_ipc_ctrl_value_comp *compv;
- int i;
- uint32_t ch;
- uint32_t val;
-
- trace_tone("tri");
-
- /* Check version from ABI header */
- if (cdata->data->comp_abi != SOF_TONE_ABI_VERSION) {
- trace_tone_error("abi");
- return -EINVAL;
- }
-
- switch (cdata->cmd) {
- case SOF_CTRL_CMD_ENUM:
- trace_tone("ten");
- trace_value(cdata->index);
- compv = (struct sof_ipc_ctrl_value_comp *) cdata->data->data;
- for (i = 0; i < (int) cdata->num_elems; i++) {
- ch = compv[i].index;
- val = compv[i].svalue;
- tracev_value(ch);
- tracev_value(val);
- switch (cdata->index) {
- case SOF_TONE_IDX_FREQUENCY:
- trace_tone("tfr");
- tonegen_update_f(&cd->sg[ch], val);
- break;
- case SOF_TONE_IDX_AMPLITUDE:
- trace_tone("tam");
- tonegen_set_a(&cd->sg[ch], val);
- break;
- case SOF_TONE_IDX_FREQ_MULT:
- trace_tone("tfx");
- tonegen_set_freq_mult(&cd->sg[ch], val);
- break;
- case SOF_TONE_IDX_AMPL_MULT:
- trace_tone("tax");
- tonegen_set_ampl_mult(&cd->sg[ch], val);
- break;
- case SOF_TONE_IDX_LENGTH:
- trace_tone("tle");
- tonegen_set_length(&cd->sg[ch], val);
- break;
- case SOF_TONE_IDX_PERIOD:
- trace_tone("tpe");
- tonegen_set_period(&cd->sg[ch], val);
- break;
- case SOF_TONE_IDX_REPEATS:
- trace_tone("trp");
- tonegen_set_repeats(&cd->sg[ch], val);
- break;
- case SOF_TONE_IDX_LIN_RAMP_STEP:
- trace_tone("trs");
- tonegen_set_linramp(&cd->sg[ch], val);
- break;
- default:
- trace_tone_error("ier");
- return -EINVAL;
- }
- }
- break;
- default:
- trace_tone_error("ec1");
- return -EINVAL;
- }
-
- return 0;
-}
-
-/* used to pass standard and bespoke commands (with data) to component */
-static int tone_cmd(struct comp_dev *dev, int cmd, void *data)
-{
- struct sof_ipc_ctrl_data *cdata = data;
- int ret = 0;
-
- trace_tone("cmd");
-
- switch (cmd) {
- case COMP_CMD_SET_DATA:
- ret = tone_cmd_set_data(dev, cdata);
- break;
- case COMP_CMD_SET_VALUE:
- ret = tone_cmd_set_value(dev, cdata);
- break;
- case COMP_CMD_GET_VALUE:
- ret = tone_cmd_get_value(dev, cdata);
- break;
- }
-
- return ret;
-}
-
-static int tone_trigger(struct comp_dev *dev, int cmd)
-{
- trace_tone("trg");
-
- return comp_set_state(dev, cmd);
-}
-
-/* copy and process stream data from source to sink buffers */
-static int tone_copy(struct comp_dev * dev)
-{
- struct comp_buffer *sink;
- struct comp_data *cd = comp_get_drvdata(dev);
-
- tracev_comp("cpy");
-
- /* tone component sink buffer */
- sink = list_first_item(&dev->bsink_list, struct comp_buffer,
- source_list);
-
- /* Test that sink has enough free frames. Then run once to maintain
- * low latency and steady load for tones.
- */
- if (sink->free >= cd->period_bytes) {
- /* create tone */
- cd->tone_func(dev, sink, dev->frames);
-
- /* calc new free and available */
- comp_update_buffer_produce(sink, cd->period_bytes);
-
- return dev->frames;
- } else {
- /* XRUN */
- trace_tone_error("xrn");
- comp_overrun(dev, sink, cd->period_bytes, sink->free);
- return -EIO;
- }
-}
-
-static int tone_prepare(struct comp_dev * dev)
-{
- struct comp_data *cd = comp_get_drvdata(dev);
- int32_t f;
- int32_t a;
- int ret;
- int i;
-
- trace_tone("TPp");
-
- ret = comp_set_state(dev, COMP_TRIGGER_PREPARE);
- if (ret < 0)
- return ret;
-
- cd->channels = dev->params.channels;
- tracev_value(cd->channels);
- tracev_value(cd->rate);
-
- for (i = 0; i < cd->channels; i++) {
- f = tonegen_get_f(&cd->sg[i]);
- a = tonegen_get_a(&cd->sg[i]);
- if (tonegen_init(&cd->sg[i], cd->rate, f, a) < 0) {
- comp_set_state(dev, COMP_TRIGGER_RESET);
- return -EINVAL;
- }
- }
-
- return 0;
-}
-
-static int tone_reset(struct comp_dev * dev)
-{
-
- struct comp_data *cd = comp_get_drvdata(dev);
- int i;
-
- trace_tone("TRe");
-
- /* Initialize with the defaults */
- for (i = 0; i < PLATFORM_MAX_CHANNELS; i++)
- tonegen_reset(&cd->sg[i]);
-
- comp_set_state(dev, COMP_TRIGGER_RESET);
-
- return 0;
-}
-
-struct comp_driver comp_tone = {
- .type = SOF_COMP_TONE,
- .ops = {
- .new = tone_new,
- .free = tone_free,
- .params = tone_params,
- .cmd = tone_cmd,
- .trigger = tone_trigger,
- .copy = tone_copy,
- .prepare = tone_prepare,
- .reset = tone_reset,
- },
-};
-
-void sys_comp_tone_init(void)
-{
- comp_register(&comp_tone);
-}
diff --git a/src/audio/volume.c b/src/audio/volume.c
deleted file mode 100644
index c07de51..0000000
--- a/src/audio/volume.c
+++ /dev/null
@@ -1,629 +0,0 @@
-/*
- * Copyright (c) 2016, Intel Corporation
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- * * Redistributions of source code must retain the above copyright
- * notice, this list of conditions and the following disclaimer.
- * * Redistributions in binary form must reproduce the above copyright
- * notice, this list of conditions and the following disclaimer in the
- * documentation and/or other materials provided with the distribution.
- * * Neither the name of the Intel Corporation nor the
- * names of its contributors may be used to endorse or promote products
- * derived from this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
- * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
- * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
- * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
- * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
- * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
- * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
- * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
- * POSSIBILITY OF SUCH DAMAGE.
- *
- * Author: Liam Girdwood <liam.r.girdwood@linux.intel.com>
- * Keyon Jie <yang.jie@linux.intel.com>
- * Tomasz Lauda <tomasz.lauda@linux.intel.com>
- */
-
-/**
- * \file audio/volume.c
- * \brief Volume component implementation
- * \authors Liam Girdwood <liam.r.girdwood@linux.intel.com>\n
- * Keyon Jie <yang.jie@linux.intel.com>\n
- * Tomasz Lauda <tomasz.lauda@linux.intel.com>
- */
-
-#include <stddef.h>
-#include <errno.h>
-#include <sof/sof.h>
-#include <sof/lock.h>
-#include <sof/list.h>
-#include <sof/stream.h>
-#include <sof/alloc.h>
-#include <sof/work.h>
-#include <sof/clock.h>
-#include "volume.h"
-
-/**
- * \brief Synchronize host mmap() volume with real value.
- * \param[in,out] cd Volume component private data.
- * \param[in] chan Channel number.
- */
-static void vol_sync_host(struct comp_data *cd, uint32_t chan)
-{
- if (cd->hvol == NULL)
- return;
-
- if (chan < SOF_IPC_MAX_CHANNELS)
- cd->hvol[chan].value = cd->volume[chan];
- else {
- trace_volume_error("veh");
- tracev_value(chan);
- }
-}
-
-/**
- * \brief Update volume with target value.
- * \param[in,out] cd Volume component private data.
- * \param[in] chan Channel number.
- */
-static void vol_update(struct comp_data *cd, uint32_t chan)
-{
- cd->volume[chan] = cd->tvolume[chan];
- vol_sync_host(cd, chan);
-}
-
-/**
- * \brief Ramps volume changes over time.
- * \param[in,out] data Volume base component device.
- * \param[in] delay Update time.
- * \return Time until next work.
- */
-static uint64_t vol_work(void *data, uint64_t delay)
-{
- struct comp_dev *dev = (struct comp_dev *)data;
- struct comp_data *cd = comp_get_drvdata(dev);
- uint32_t vol;
- int again = 0;
- int i, new_vol;
-
- /* inc/dec each volume if it's not at target */
- for (i = 0; i < PLATFORM_MAX_CHANNELS; i++) {
-
- /* skip if target reached */
- if (cd->volume[i] == cd->tvolume[i])
- continue;
-
- vol = cd->volume[i];
-
- if (cd->volume[i] < cd->tvolume[i]) {
- /* ramp up */
- vol += VOL_RAMP_STEP;
-
- /* ramp completed ? */
- if (vol >= cd->tvolume[i] || vol >= cd->max_volume)
- vol_update(cd, i);
- else {
- cd->volume[i] = vol;
- again = 1;
- }
- } else {
- /* ramp down */
- new_vol = vol - VOL_RAMP_STEP;
- if (new_vol <= 0) {
- /* cannot ramp down below 0 */
- vol_update(cd, i);
- } else {
- /* ramp completed ? */
- if (new_vol <= cd->tvolume[i] ||
- new_vol <= cd->min_volume) {
- vol_update(cd, i);
- } else {
- cd->volume[i] = new_vol;
- again = 1;
- }
- }
- }
-
- /* sync host with new value */
- vol_sync_host(cd, i);
- }
-
- /* do we need to continue ramping */
- if (again)
- return VOL_RAMP_US;
- else
- return 0;
-}
-
-/**
- * \brief Validates and sets minimum and maximum volume levels.
- * \details If max_vol < min_vol or it's equals 0 then set max_vol = VOL_MAX
- * \param[in,out] cd Volume component private data.
- * \param[in] min_vol Minimum volume level
- * \param[in] max_vol Maximum volume level
- */
-static void vol_set_min_max_levels(struct comp_data *cd,
- uint32_t min_vol, uint32_t max_vol)
-{
- if (max_vol < min_vol || max_vol == 0)
- cd->max_volume = VOL_ZERO_DB;
- else
- cd->max_volume = max_vol;
- cd->min_volume = min_vol;
-}
-
-/**
- * \brief Creates volume component.
- * \param[in,out] data Volume base component device.
- * \param[in] delay Update time.
- * \return Pointer to volume base component device.
- */
-static struct comp_dev *volume_new(struct sof_ipc_comp *comp)
-{
- struct comp_dev *dev;
- struct sof_ipc_comp_volume *vol;
- struct sof_ipc_comp_volume *ipc_vol =
- (struct sof_ipc_comp_volume *)comp;
- struct comp_data *cd;
- int i;
-
- trace_volume("new");
-
- dev = rzalloc(RZONE_RUNTIME, SOF_MEM_CAPS_RAM,
- COMP_SIZE(struct sof_ipc_comp_volume));
- if (dev == NULL)
- return NULL;
-
- vol = (struct sof_ipc_comp_volume *)&dev->comp;
- memcpy(vol, ipc_vol, sizeof(struct sof_ipc_comp_volume));
-
- cd = rzalloc(RZONE_RUNTIME, SOF_MEM_CAPS_RAM, sizeof(*cd));
- if (cd == NULL) {
- rfree(dev);
- return NULL;
- }
-
- comp_set_drvdata(dev, cd);
- work_init(&cd->volwork, vol_work, dev, WORK_ASYNC);
-
- /* set the default volumes */
- for (i = 0; i < PLATFORM_MAX_CHANNELS; i++) {
- cd->volume[i] = VOL_ZERO_DB;
- cd->tvolume[i] = VOL_ZERO_DB;
- }
-
- /* set volume min/max levels */
- vol_set_min_max_levels(cd, ipc_vol->min_value, ipc_vol->max_value);
-
- dev->state = COMP_STATE_READY;
- return dev;
-}
-
-/**
- * \brief Frees volume component.
- * \param[in,out] dev Volume base component device.
- */
-static void volume_free(struct comp_dev *dev)
-{
- struct comp_data *cd = comp_get_drvdata(dev);
-
- trace_volume("fre");
-
- rfree(cd);
- rfree(dev);
-}
-
-/**
- * \brief Sets volume component audio stream parameters.
- * \param[in,out] dev Volume base component device.
- * \return Error code.
- *
- * All done in prepare() since we need to know source and sink component params.
- */
-static int volume_params(struct comp_dev *dev)
-{
- struct comp_data *cd = comp_get_drvdata(dev);
-
- trace_volume("par");
-
- /* rewrite params format for all downstream */
- dev->params.frame_fmt = cd->sink_format;
-
- return 0;
-}
-
-/**
- * \brief Sets channel target volume.
- * \param[in,out] dev Volume base component device.
- * \param[in] chan Channel number.
- * \param[in] vol Target volume.
- */
-static inline void volume_set_chan(struct comp_dev *dev, int chan, uint32_t vol)
-{
- struct comp_data *cd = comp_get_drvdata(dev);
- uint32_t v = vol;
-
- /* Limit received volume gain to MIN..MAX range before applying it.
- * MAX is needed for now for the generic C gain arithmetics to prevent
- * multiplication overflow with the 32 bit value. Non-zero MIN option
- * can be useful to prevent totally muted small volume gain.
- */
- if (v <= cd->min_volume)
- v = cd->min_volume;
-
- if (v > cd->max_volume)
- v = cd->max_volume;
-
- cd->tvolume[chan] = v;
-}
-
-/**
- * \brief Mutes channel.
- * \param[in,out] dev Volume base component device.
- * \param[in] chan Channel number.
- */
-static inline void volume_set_chan_mute(struct comp_dev *dev, int chan)
-{
- struct comp_data *cd = comp_get_drvdata(dev);
-
- /* Check if not muted already */
- if (cd->volume[chan] != 0)
- cd->mvolume[chan] = cd->volume[chan];
- cd->tvolume[chan] = 0;
-}
-
-/**
- * \brief Unmutes channel.
- * \param[in,out] dev Volume base component device.
- * \param[in] chan Channel number.
- */
-static inline void volume_set_chan_unmute(struct comp_dev *dev, int chan)
-{
- struct comp_data *cd = comp_get_drvdata(dev);
-
- /* Check if muted */
- if (cd->volume[chan] == 0)
- cd->tvolume[chan] = cd->mvolume[chan];
-}
-
-/**
- * \brief Sets volume control command.
- * \param[in,out] dev Volume base component device.
- * \param[in,out] cdata Control command data.
- * \return Error code.
- */
-static int volume_ctrl_set_cmd(struct comp_dev *dev,
- struct sof_ipc_ctrl_data *cdata)
-{
- struct comp_data *cd = comp_get_drvdata(dev);
- int i;
- int j;
-
- /* validate */
- if (cdata->num_elems == 0 || cdata->num_elems > SOF_IPC_MAX_CHANNELS) {
- trace_volume_error("gs0");
- return -EINVAL;
- }
-
- switch (cdata->cmd) {
- case SOF_CTRL_CMD_VOLUME:
- trace_volume("vst");
- trace_value(cdata->comp_id);
- for (j = 0; j < cdata->num_elems; j++) {
- trace_value(cdata->chanv[j].channel);
- trace_value(cdata->chanv[j].value);
- i = cdata->chanv[j].channel;
- if ((i >= 0) && (i < SOF_IPC_MAX_CHANNELS))
- volume_set_chan(dev, i, cdata->chanv[j].value);
- else {
- trace_volume_error("gs2");
- tracev_value(i);
- }
- }
- work_schedule_default(&cd->volwork, VOL_RAMP_US);
- break;
-
- case SOF_CTRL_CMD_SWITCH:
- trace_volume("mst");
- trace_value(cdata->comp_id);
- for (j = 0; j < cdata->num_elems; j++) {
- trace_value(cdata->chanv[j].channel);
- trace_value(cdata->chanv[j].value);
- i = cdata->chanv[j].channel;
- if ((i >= 0) && (i < SOF_IPC_MAX_CHANNELS)) {
- if (cdata->chanv[j].value)
- volume_set_chan_unmute(dev, i);
- else
- volume_set_chan_mute(dev, i);
- } else {
- trace_volume_error("gs3");
- tracev_value(i);
- }
- }
- work_schedule_default(&cd->volwork, VOL_RAMP_US);
- break;
-
- default:
- trace_volume_error("gs1");
- return -EINVAL;
- }
-
- return 0;
-}
-
-/**
- * \brief Gets volume control command.
- * \param[in,out] dev Volume base component device.
- * \param[in,out] cdata Control command data.
- * \return Error code.
- */
-static int volume_ctrl_get_cmd(struct comp_dev *dev,
- struct sof_ipc_ctrl_data *cdata)
-{
- struct comp_data *cd = comp_get_drvdata(dev);
- int j;
-
- /* validate */
- if (cdata->num_elems == 0 || cdata->num_elems > SOF_IPC_MAX_CHANNELS) {
- trace_volume_error("gc0");
- tracev_value(cdata->num_elems);
- return -EINVAL;
- }
-
- if (cdata->cmd == SOF_CTRL_CMD_VOLUME ||
- cdata->cmd == SOF_CTRL_CMD_SWITCH) {
- trace_volume("vgt");
- trace_value(cdata->comp_id);
- for (j = 0; j < cdata->num_elems; j++) {
- cdata->chanv[j].channel = j;
- cdata->chanv[j].value = cd->tvolume[j];
- trace_value(cdata->chanv[j].channel);
- trace_value(cdata->chanv[j].value);
- }
- } else {
- trace_volume_error("ec2");
- return -EINVAL;
- }
-
- return 0;
-}
-
-/**
- * \brief Used to pass standard and bespoke commands (with data) to component.
- * \param[in,out] dev Volume base component device.
- * \param[in] cmd Command type.
- * \param[in,out] data Control command data.
- * \return Error code.
- */
-static int volume_cmd(struct comp_dev *dev, int cmd, void *data)
-{
- struct sof_ipc_ctrl_data *cdata = data;
-
- trace_volume("cmd");
-
- switch (cmd) {
- case COMP_CMD_SET_VALUE:
- return volume_ctrl_set_cmd(dev, cdata);
- case COMP_CMD_GET_VALUE:
- return volume_ctrl_get_cmd(dev, cdata);
- default:
- return -EINVAL;
- }
-}
-
-/**
- * \brief Sets volume component state.
- * \param[in,out] dev Volume base component device.
- * \param[in] cmd Command type.
- * \return Error code.
- */
-static int volume_trigger(struct comp_dev *dev, int cmd)
-{
- trace_volume("trg");
-
- return comp_set_state(dev, cmd);
-}
-
-/**
- * \brief Copies and processes stream data.
- * \param[in,out] dev Volume base component device.
- * \return Error code.
- */
-static int volume_copy(struct comp_dev *dev)
-{
- struct comp_data *cd = comp_get_drvdata(dev);
- struct comp_buffer *sink;
- struct comp_buffer *source;
-
- tracev_volume("cpy");
-
- /* volume components will only ever have 1 source and 1 sink buffer */
- source = list_first_item(&dev->bsource_list,
- struct comp_buffer, sink_list);
- sink = list_first_item(&dev->bsink_list,
- struct comp_buffer, source_list);
-
- /* make sure source component buffer has enough data available and that
- * the sink component buffer has enough free bytes for copy. Also
- * check for XRUNs
- */
- if (source->avail < cd->source_period_bytes) {
- trace_volume_error("xru");
- comp_underrun(dev, source, cd->source_period_bytes, 0);
- return -EIO; /* xrun */
- }
- if (sink->free < cd->sink_period_bytes) {
- trace_volume_error("xro");
- comp_overrun(dev, sink, cd->sink_period_bytes, 0);
- return -EIO; /* xrun */
- }
-
- /* copy and scale volume */
- cd->scale_vol(dev, sink, source);
-
- /* calc new free and available */
- comp_update_buffer_produce(sink, cd->sink_period_bytes);
- comp_update_buffer_consume(source, cd->source_period_bytes);
-
- return dev->frames;
-}
-
-/**
- * \brief Prepares volume component for processing.
- * \param[in,out] dev Volume base component device.
- * \return Error code.
- *
- * Volume component is usually first and last in pipelines so it makes sense
- * to also do some type of conversion here.
- */
-static int volume_prepare(struct comp_dev *dev)
-{
- struct comp_data *cd = comp_get_drvdata(dev);
- struct comp_buffer *sinkb;
- struct comp_buffer *sourceb;
- struct sof_ipc_comp_config *sconfig;
- struct sof_ipc_comp_config *config = COMP_GET_CONFIG(dev);
- int i;
- int ret;
-
- trace_volume("pre");
-
- ret = comp_set_state(dev, COMP_TRIGGER_PREPARE);
- if (ret < 0)
- return ret;
-
- /* volume components will only ever have 1 source and 1 sink buffer */
- sourceb = list_first_item(&dev->bsource_list,
- struct comp_buffer, sink_list);
- sinkb = list_first_item(&dev->bsink_list,
- struct comp_buffer, source_list);
-
- /* get source data format */
- switch (sourceb->source->comp.type) {
- case SOF_COMP_HOST:
- case SOF_COMP_SG_HOST:
- /* source format comes from IPC params */
- cd->source_format = sourceb->source->params.frame_fmt;
- cd->source_period_bytes = dev->frames *
- comp_frame_bytes(sourceb->source);
- break;
- case SOF_COMP_DAI:
- case SOF_COMP_SG_DAI:
- default:
- /* source format comes from DAI/comp config */
- sconfig = COMP_GET_CONFIG(sourceb->source);
- cd->source_format = sconfig->frame_fmt;
- cd->source_period_bytes = dev->frames *
- comp_frame_bytes(sourceb->source);
- break;
- }
-
- /* get sink data format */
- switch (sinkb->sink->comp.type) {
- case SOF_COMP_HOST:
- case SOF_COMP_SG_HOST:
- /* sink format come from IPC params */
- cd->sink_format = sinkb->sink->params.frame_fmt;
- cd->sink_period_bytes = dev->frames *
- comp_frame_bytes(sinkb->sink);
- break;
- case SOF_COMP_DAI:
- case SOF_COMP_SG_DAI:
- default:
- /* sink format comes from DAI/comp config */
- sconfig = COMP_GET_CONFIG(sinkb->sink);
- cd->sink_format = sconfig->frame_fmt;
- cd->sink_period_bytes = dev->frames *
- comp_frame_bytes(sinkb->sink);
- break;
- }
- /* rewrite params format for all downstream */
- dev->params.frame_fmt = cd->sink_format;
-
- dev->frame_bytes = cd->sink_period_bytes / dev->frames;
-
- /* set downstream buffer size */
- ret = buffer_set_size(sinkb, cd->sink_period_bytes *
- config->periods_sink);
- if (ret < 0) {
- trace_volume_error("vp0");
- goto err;
- }
-
- /* validate */
- if (cd->sink_period_bytes == 0) {
- trace_volume_error("vp1");
- trace_error_value(dev->frames);
- trace_error_value(sinkb->sink->frame_bytes);
- ret = -EINVAL;
- goto err;
- }
- if (cd->source_period_bytes == 0) {
- trace_volume_error("vp2");
- trace_error_value(dev->frames);
- trace_error_value(sourceb->source->frame_bytes);
- ret = -EINVAL;
- goto err;
- }
-
- cd->scale_vol = vol_get_processing_function(dev);
- if (!cd->scale_vol) {
- trace_volume_error("vp3");
- trace_error_value(cd->source_format);
- trace_error_value(cd->sink_format);
- trace_error_value(dev->params.channels);
- ret = -EINVAL;
- goto err;
- }
-
- for (i = 0; i < PLATFORM_MAX_CHANNELS; i++)
- vol_sync_host(cd, i);
-
- return 0;
-
-err:
- comp_set_state(dev, COMP_TRIGGER_RESET);
- return ret;
-}
-
-/**
- * \brief Resets volume component.
- * \param[in,out] dev Volume base component device.
- * \return Error code.
- */
-static int volume_reset(struct comp_dev *dev)
-{
- trace_volume("res");
-
- comp_set_state(dev, COMP_TRIGGER_RESET);
- return 0;
-}
-
-/** \brief Volume component definition. */
-struct comp_driver comp_volume = {
- .type = SOF_COMP_VOLUME,
- .ops = {
- .new = volume_new,
- .free = volume_free,
- .params = volume_params,
- .cmd = volume_cmd,
- .trigger = volume_trigger,
- .copy = volume_copy,
- .prepare = volume_prepare,
- .reset = volume_reset,
- },
-};
-
-/**
- * \brief Initializes volume component.
- */
-void sys_comp_volume_init(void)
-{
- comp_register(&comp_volume);
-}
diff --git a/src/audio/volume.h b/src/audio/volume.h
deleted file mode 100644
index 631a857..0000000
--- a/src/audio/volume.h
+++ /dev/null
@@ -1,144 +0,0 @@
-/*
- * Copyright (c) 2018, Intel Corporation
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- * * Redistributions of source code must retain the above copyright
- * notice, this list of conditions and the following disclaimer.
- * * Redistributions in binary form must reproduce the above copyright
- * notice, this list of conditions and the following disclaimer in the
- * documentation and/or other materials provided with the distribution.
- * * Neither the name of the Intel Corporation nor the
- * names of its contributors may be used to endorse or promote products
- * derived from this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
- * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
- * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
- * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
- * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
- * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
- * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
- * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
- * POSSIBILITY OF SUCH DAMAGE.
- *
- * Author: Tomasz Lauda <tomasz.lauda@linux.intel.com>
- */
-
-/**
- * \file audio/volume.h
- * \brief Volume component header file
- * \authors Liam Girdwood <liam.r.girdwood@linux.intel.com>\n
- * Keyon Jie <yang.jie@linux.intel.com>\n
- * Tomasz Lauda <tomasz.lauda@linux.intel.com>
- */
-
-#ifndef VOLUME_H
-#define VOLUME_H
-
-#include <stdint.h>
-#include <sof/audio/component.h>
-#include <sof/audio/pipeline.h>
-#include <sof/audio/format.h>
-
-#define CONFIG_GENERIC
-
-#if defined(__XCC__)
-#include <xtensa/config/core-isa.h>
-
-#if XCHAL_HAVE_HIFI3
-#undef CONFIG_GENERIC
-#endif
-
-#endif
-
-/** \brief Volume trace function. */
-#define trace_volume(__e) trace_event(TRACE_CLASS_VOLUME, __e)
-
-/** \brief Volume trace value function. */
-#define tracev_volume(__e) tracev_event(TRACE_CLASS_VOLUME, __e)
-
-/** \brief Volume trace error function. */
-#define trace_volume_error(__e) trace_error(TRACE_CLASS_VOLUME, __e)
-
-//** \brief Volume gain Qx.y integer x number of bits including sign bit. */
-#define VOL_QXY_X 2
-
-//** \brief Volume gain Qx.y fractional y number of bits. */
-#define VOL_QXY_Y 16
-
-/**
- * \brief Volume ramp update rate in microseconds.
- * Update volume gain value every 1 ms.
- */
-#define VOL_RAMP_US 1000
-
-/**
- * \brief Volume linear ramp length in milliseconds.
- * Use linear ramp length of 250 ms from mute to unity gain. The linear ramp
- * step in Q1.16 to use in vol_work function is computed from the length.
- */
-#define VOL_RAMP_LENGTH_MS 250
-#define VOL_RAMP_STEP Q_CONVERT_FLOAT(1.0 / 1000 * \
- VOL_RAMP_US / VOL_RAMP_LENGTH_MS, \
- VOL_QXY_Y)
-
-/**
- * \brief Volume maximum value.
- * TODO: This should be 1 << (VOL_QX_BITS + VOL_QY_BITS - 1) - 1 but
- * the current volume code cannot handle the full Q1.16 range correctly.
- */
-#define VOL_MAX (1 << VOL_QXY_Y)
-
-/** \brief Volume 0dB value. */
-#define VOL_ZERO_DB (1 << 16)
-
-/** \brief Volume minimum value. */
-#define VOL_MIN 0
-
-/**
- * \brief Volume component private data.
- *
- * Gain amplitude value is between 0 (mute) ... 2^16 (0dB) ... 2^24 (~+48dB).
- */
-struct comp_data {
- uint32_t source_period_bytes; /**< source number of period bytes */
- uint32_t sink_period_bytes; /**< sink number of period bytes */
- enum sof_ipc_frame source_format; /**< source frame format */
- enum sof_ipc_frame sink_format; /**< sink frame format */
- uint32_t volume[SOF_IPC_MAX_CHANNELS]; /**< current volume */
- uint32_t tvolume[SOF_IPC_MAX_CHANNELS]; /**< target volume */
- uint32_t mvolume[SOF_IPC_MAX_CHANNELS]; /**< mute volume */
- uint32_t min_volume; /**< minimum volume level */
- uint32_t max_volume; /**< maximum volume level */
- void (*scale_vol)(struct comp_dev *dev, struct comp_buffer *sink,
- struct comp_buffer *source); /**< volume processing function */
- struct work volwork; /**< volume scheduled work function */
- struct sof_ipc_ctrl_value_chan *hvol; /**< host volume readback */
-};
-
-/** \brief Volume processing functions map. */
-struct comp_func_map {
- uint16_t source; /**< source frame format */
- uint16_t sink; /**< sink frame format */
- uint16_t channels; /**< number of stream channels */
- void (*func)(struct comp_dev *dev, struct comp_buffer *sink,
- struct comp_buffer *source); /**< volume processing function */
-};
-
-/** \brief Map of formats with dedicated processing functions. */
-extern const struct comp_func_map func_map[];
-
-typedef void (*scale_vol)(struct comp_dev *, struct comp_buffer *,
- struct comp_buffer *);
-
-/**
- * \brief Retrievies volume processing function.
- * \param[in,out] dev Volume base component device.
- */
-scale_vol vol_get_processing_function(struct comp_dev *dev);
-
-#endif /* VOLUME_H */
diff --git a/src/audio/volume_generic.c b/src/audio/volume_generic.c
deleted file mode 100644
index 01172d7..0000000
--- a/src/audio/volume_generic.c
+++ /dev/null
@@ -1,1005 +0,0 @@
-/*
- * Copyright (c) 2018, Intel Corporation
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- * * Redistributions of source code must retain the above copyright
- * notice, this list of conditions and the following disclaimer.
- * * Redistributions in binary form must reproduce the above copyright
- * notice, this list of conditions and the following disclaimer in the
- * documentation and/or other materials provided with the distribution.
- * * Neither the name of the Intel Corporation nor the
- * names of its contributors may be used to endorse or promote products
- * derived from this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
- * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
- * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
- * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
- * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
- * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
- * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
- * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
- * POSSIBILITY OF SUCH DAMAGE.
- *
- * Author: Liam Girdwood <liam.r.girdwood@linux.intel.com>
- * Keyon Jie <yang.jie@linux.intel.com>
- * Tomasz Lauda <tomasz.lauda@linux.intel.com>
- */
-
-/**
- * \file audio/volume_generic.c
- * \brief Volume generic processing implementation
- * \authors Liam Girdwood <liam.r.girdwood@linux.intel.com>\n
- * Keyon Jie <yang.jie@linux.intel.com>\n
- * Tomasz Lauda <tomasz.lauda@linux.intel.com>
- */
-
-#include "volume.h"
-
-#ifdef CONFIG_GENERIC
-
-/**
- * \brief Volume processing from 16 bit to 32 bit in 2 channels.
- * \param[in,out] dev Volume base component device.
- * \param[in,out] sink Destination buffer.
- * \param[in,out] source Source buffer.
- *
- * Copy and scale volume from 16 bit source buffer
- * to 32 bit destination buffer for 2 channels.
- */
-static void vol_s16_to_s32_2ch(struct comp_dev *dev, struct comp_buffer *sink,
- struct comp_buffer *source)
-{
- struct comp_data *cd = comp_get_drvdata(dev);
- int16_t *src = (int16_t *)source->r_ptr;
- int32_t *dest = (int32_t *)sink->w_ptr;
- int32_t i;
-
- /* buffer sizes are always divisible by period frames */
- /* Samples are Q1.15 --> Q1.31 and volume is Q1.16 */
- for (i = 0; i < dev->frames * 2; i += 2) {
- dest[i] = (int32_t)src[i] * cd->volume[0];
- dest[i + 1] = (int32_t)src[i + 1] * cd->volume[1];
- }
-}
-
-/**
- * \brief Volume processing from 32 bit to 16 bit in 2 channels.
- * \param[in,out] dev Volume base component device.
- * \param[in,out] sink Destination buffer.
- * \param[in,out] source Source buffer.
- *
- * Copy and scale volume from 32 bit source buffer
- * to 16 bit destination buffer for 2 channels.
- */
-static void vol_s32_to_s16_2ch(struct comp_dev *dev, struct comp_buffer *sink,
- struct comp_buffer *source)
-{
- struct comp_data *cd = comp_get_drvdata(dev);
- int32_t *src = (int32_t *)source->r_ptr;
- int16_t *dest = (int16_t *)sink->w_ptr;
- int32_t i;
-
- /* buffer sizes are always divisible by period frames */
- /* Samples are Q1.31 --> Q1.15 and volume is Q1.16 */
- for (i = 0; i < dev->frames * 2; i += 2) {
- dest[i] = (int16_t)q_multsr_sat_32x32(
- src[i], cd->volume[0], Q_SHIFT_BITS_64(31, 16, 15));
- dest[i + 1] = (int16_t)q_multsr_sat_32x32(
- src[i + 1], cd->volume[1], Q_SHIFT_BITS_64(31, 16, 15));
- }
-}
-
-/**
- * \brief Volume processing from 32 bit to 32 bit in 2 channels.
- * \param[in,out] dev Volume base component device.
- * \param[in,out] sink Destination buffer.
- * \param[in,out] source Source buffer.
- *
- * Copy and scale volume from 32 bit source buffer
- * to 32 bit destination buffer for 2 channels.
- */
-static void vol_s32_to_s32_2ch(struct comp_dev *dev, struct comp_buffer *sink,
- struct comp_buffer *source)
-{
- struct comp_data *cd = comp_get_drvdata(dev);
- int32_t *src = (int32_t *)source->r_ptr;
- int32_t *dest = (int32_t *)sink->w_ptr;
- int32_t i;
-
- /* buffer sizes are always divisible by period frames */
- /* Samples are Q1.31 --> Q1.31 and volume is Q1.16 */
- for (i = 0; i < dev->frames * 2; i += 2) {
- dest[i] = q_multsr_sat_32x32(
- src[i], cd->volume[0], Q_SHIFT_BITS_64(31, 16, 31));
- dest[i + 1] = q_multsr_sat_32x32(
- src[i + 1], cd->volume[1], Q_SHIFT_BITS_64(31, 16, 31));
- }
-}
-
-/**
- * \brief Volume processing from 16 bit to 16 bit in 2 channels.
- * \param[in,out] dev Volume base component device.
- * \param[in,out] sink Destination buffer.
- * \param[in,out] source Source buffer.
- *
- * Copy and scale volume from 16 bit source buffer
- * to 16 bit destination buffer for 2 channels.
- */
-static void vol_s16_to_s16_2ch(struct comp_dev *dev, struct comp_buffer *sink,
- struct comp_buffer *source)
-{
- struct comp_data *cd = comp_get_drvdata(dev);
- int16_t *src = (int16_t *)source->r_ptr;
- int16_t *dest = (int16_t *)sink->w_ptr;
- int32_t i;
-
- /* buffer sizes are always divisible by period frames */
- /* Samples are Q1.15 --> Q1.15 and volume is Q1.16 */
- for (i = 0; i < dev->frames * 2; i += 2) {
- dest[i] = q_multsr_sat_16x16(
- src[i], cd->volume[0], Q_SHIFT_BITS_32(15, 16, 15));
- dest[i + 1] = q_multsr_sat_16x16(
- src[i + 1], cd->volume[1], Q_SHIFT_BITS_32(15, 16, 15));
- }
-}
-
-/**
- * \brief Volume processing from 16 bit to 24/32 bit in 2 channels.
- * \param[in,out] dev Volume base component device.
- * \param[in,out] sink Destination buffer.
- * \param[in,out] source Source buffer.
- *
- * Copy and scale volume from 16 bit source buffer
- * to 24/32 bit destination buffer for 2 channels.
- */
-static void vol_s16_to_s24_2ch(struct comp_dev *dev, struct comp_buffer *sink,
- struct comp_buffer *source)
-{
- struct comp_data *cd = comp_get_drvdata(dev);
- int16_t *src = (int16_t *)source->r_ptr;
- int32_t *dest = (int32_t *)sink->w_ptr;
- int32_t i;
-
- /* buffer sizes are always divisible by period frames */
- /* Samples are Q1.15 and volume is Q1.16 */
- for (i = 0; i < dev->frames * 2; i += 2) {
- dest[i] = q_multsr_sat_32x32(
- src[i], cd->volume[0], Q_SHIFT_BITS_64(15, 16, 23));
- dest[i + 1] = q_multsr_sat_32x32(
- src[i + 1], cd->volume[1], Q_SHIFT_BITS_64(15, 16, 23));
- }
-}
-
-/**
- * \brief Volume processing from 24/32 bit to 16 bit in 2 channels.
- * \param[in,out] dev Volume base component device.
- * \param[in,out] sink Destination buffer.
- * \param[in,out] source Source buffer.
- *
- * Copy and scale volume from 24/32 bit source buffer
- * to 16 bit destination buffer for 2 channels.
- */
-static void vol_s24_to_s16_2ch(struct comp_dev *dev, struct comp_buffer *sink,
- struct comp_buffer *source)
-{
- struct comp_data *cd = comp_get_drvdata(dev);
- int32_t *src = (int32_t *)source->r_ptr;
- int16_t *dest = (int16_t *)sink->w_ptr;
- int32_t i;
-
- /* buffer sizes are always divisible by period frames */
- /* Samples are Q1.23 --> Q1.15 and volume is Q1.16 */
- for (i = 0; i < dev->frames * 2; i += 2) {
- dest[i] = (int16_t)q_multsr_sat_32x32(
- sign_extend_s24(src[i]), cd->volume[0],
- Q_SHIFT_BITS_64(23, 16, 15));
- dest[i + 1] = (int16_t)q_multsr_sat_32x32(
- sign_extend_s24(src[i + 1]), cd->volume[1],
- Q_SHIFT_BITS_64(23, 16, 15));
- }
-}
-
-/**
- * \brief Volume processing from 32 bit to 24/32 bit in 2 channels.
- * \param[in,out] dev Volume base component device.
- * \param[in,out] sink Destination buffer.
- * \param[in,out] source Source buffer.
- *
- * Copy and scale volume from 32 bit source buffer
- * to 24/32 bit destination buffer for 2 channels.
- */
-static void vol_s32_to_s24_2ch(struct comp_dev *dev, struct comp_buffer *sink,
- struct comp_buffer *source)
-{
- struct comp_data *cd = comp_get_drvdata(dev);
- int32_t *src = (int32_t *)source->r_ptr;
- int32_t *dest = (int32_t *)sink->w_ptr;
- int32_t i;
-
- /* buffer sizes are always divisible by period frames */
- /* Samples are Q1.31 --> Q1.23 and volume is Q1.16 */
- for (i = 0; i < dev->frames * 2; i += 2) {
- dest[i] = q_multsr_sat_32x32(
- src[i], cd->volume[0], Q_SHIFT_BITS_64(31, 16, 23));
- dest[i + 1] = q_multsr_sat_32x32(
- src[i + 1], cd->volume[1], Q_SHIFT_BITS_64(31, 16, 23));
- }
-}
-
-/**
- * \brief Volume processing from 24/32 bit to 32 bit in 2 channels.
- * \param[in,out] dev Volume base component device.
- * \param[in,out] sink Destination buffer.
- * \param[in,out] source Source buffer.
- *
- * Copy and scale volume from 24/32 bit source buffer
- * to 32 bit destination buffer for 2 channels.
- */
-static void vol_s24_to_s32_2ch(struct comp_dev *dev, struct comp_buffer *sink,
- struct comp_buffer *source)
-{
- struct comp_data *cd = comp_get_drvdata(dev);
- int32_t *src = (int32_t *)source->r_ptr;
- int32_t *dest = (int32_t *)sink->w_ptr;
- int32_t i;
-
- /* buffer sizes are always divisible by period frames */
- /* Samples are Q1.23 --> Q1.31 and volume is Q1.16 */
- for (i = 0; i < dev->frames * 2; i += 2) {
- dest[i] = q_multsr_sat_32x32(
- sign_extend_s24(src[i]), cd->volume[0],
- Q_SHIFT_BITS_64(23, 16, 31));
- dest[i + 1] = q_multsr_sat_32x32(
- sign_extend_s24(src[i + 1]), cd->volume[1],
- Q_SHIFT_BITS_64(23, 16, 31));
- }
-}
-
-/**
- * \brief Volume processing from 24/32 bit to 24/32 bit in 2 channels.
- * \param[in,out] dev Volume base component device.
- * \param[in,out] sink Destination buffer.
- * \param[in,out] source Source buffer.
- *
- * Copy and scale volume from 24/32 bit source buffer
- * to 24/32 bit destination buffer for 2 channels.
- */
-static void vol_s24_to_s24_2ch(struct comp_dev *dev, struct comp_buffer *sink,
- struct comp_buffer *source)
-{
- struct comp_data *cd = comp_get_drvdata(dev);
- int32_t i, *src = (int32_t *)source->r_ptr;
- int32_t *dest = (int32_t *)sink->w_ptr;
-
- /* buffer sizes are always divisible by period frames */
- /* Samples are Q1.23 --> Q1.23 and volume is Q1.16 */
- for (i = 0; i < dev->frames * 2; i += 2) {
- dest[i] = q_multsr_sat_32x32(
- sign_extend_s24(src[i]), cd->volume[0],
- Q_SHIFT_BITS_64(23, 16, 23));
- dest[i + 1] = q_multsr_sat_32x32(
- sign_extend_s24(src[i + 1]), cd->volume[1],
- Q_SHIFT_BITS_64(23, 16, 23));
- }
-}
-
-#if PLATFORM_MAX_CHANNELS >= 4
-/**
- * \brief Volume processing from 16 bit to 32 bit in 4 channels.
- * \param[in,out] dev Volume base component device.
- * \param[in,out] sink Destination buffer.
- * \param[in,out] source Source buffer.
- *
- * Copy and scale volume from 16 bit source buffer
- * to 32 bit destination buffer for 4 channels.
- */
-static void vol_s16_to_s32_4ch(struct comp_dev *dev, struct comp_buffer *sink,
- struct comp_buffer *source)
-{
- struct comp_data *cd = comp_get_drvdata(dev);
- int16_t *src = (int16_t *)source->r_ptr;
- int32_t *dest = (int32_t *)sink->w_ptr;
- int32_t i;
-
- /* buffer sizes are always divisible by period frames */
- /* Samples are Q1.15 --> Q1.31 and volume is Q1.16 */
- for (i = 0; i < dev->frames * 4; i += 4) {
- dest[i] = (int32_t)src[i] * cd->volume[0];
- dest[i + 1] = (int32_t)src[i + 1] * cd->volume[1];
- dest[i + 2] = (int32_t)src[i + 2] * cd->volume[2];
- dest[i + 3] = (int32_t)src[i + 3] * cd->volume[3];
- }
-}
-
-/**
- * \brief Volume processing from 32 bit to 16 bit in 4 channels.
- * \param[in,out] dev Volume base component device.
- * \param[in,out] sink Destination buffer.
- * \param[in,out] source Source buffer.
- *
- * Copy and scale volume from 32 bit source buffer
- * to 16 bit destination buffer for 4 channels.
- */
-static void vol_s32_to_s16_4ch(struct comp_dev *dev, struct comp_buffer *sink,
- struct comp_buffer *source)
-{
- struct comp_data *cd = comp_get_drvdata(dev);
- int32_t *src = (int32_t *)source->r_ptr;
- int16_t *dest = (int16_t *)sink->w_ptr;
- int32_t i;
-
- /* buffer sizes are always divisible by period frames */
- /* Samples are Q1.31 --> Q1.15 and volume is Q1.16 */
- for (i = 0; i < dev->frames * 4; i += 4) {
- dest[i] = (int16_t)q_multsr_sat_32x32(src[i], cd->volume[0],
- Q_SHIFT_BITS_64(31, 16,
- 15));
- dest[i + 1] = (int16_t)q_multsr_sat_32x32(src[i + 1],
- cd->volume[1],
- Q_SHIFT_BITS_64(31,
- 16,
- 15));
- dest[i + 2] = (int16_t)q_multsr_sat_32x32(src[i + 2],
- cd->volume[2],
- Q_SHIFT_BITS_64(31,
- 16,
- 15));
- dest[i + 3] = (int16_t)q_multsr_sat_32x32(src[i + 3],
- cd->volume[3],
- Q_SHIFT_BITS_64(31,
- 16,
- 15));
- }
-}
-
-/**
- * \brief Volume processing from 32 bit to 32 bit in 4 channels.
- * \param[in,out] dev Volume base component device.
- * \param[in,out] sink Destination buffer.
- * \param[in,out] source Source buffer.
- *
- * Copy and scale volume from 32 bit source buffer
- * to 32 bit destination buffer for 4 channels.
- */
-static void vol_s32_to_s32_4ch(struct comp_dev *dev, struct comp_buffer *sink,
- struct comp_buffer *source)
-{
- struct comp_data *cd = comp_get_drvdata(dev);
- int32_t *src = (int32_t *)source->r_ptr;
- int32_t *dest = (int32_t *)sink->w_ptr;
- int32_t i;
-
- /* buffer sizes are always divisible by period frames */
- /* Samples are Q1.31 --> Q1.31 and volume is Q1.16 */
- for (i = 0; i < dev->frames * 4; i += 4) {
- dest[i] = q_multsr_sat_32x32(src[i], cd->volume[0],
- Q_SHIFT_BITS_64(31, 16, 31));
- dest[i + 1] = q_multsr_sat_32x32(src[i + 1], cd->volume[1],
- Q_SHIFT_BITS_64(31, 16, 31));
- dest[i + 2] = q_multsr_sat_32x32(src[i + 2], cd->volume[2],
- Q_SHIFT_BITS_64(31, 16, 31));
- dest[i + 3] = q_multsr_sat_32x32(src[i + 3], cd->volume[3],
- Q_SHIFT_BITS_64(31, 16, 31));
- }
-}
-
-/**
- * \brief Volume processing from 16 bit to 16 bit in 4 channels.
- * \param[in,out] dev Volume base component device.
- * \param[in,out] sink Destination buffer.
- * \param[in,out] source Source buffer.
- *
- * Copy and scale volume from 16 bit source buffer
- * to 16 bit destination buffer for 4 channels.
- */
-static void vol_s16_to_s16_4ch(struct comp_dev *dev, struct comp_buffer *sink,
- struct comp_buffer *source)
-{
- struct comp_data *cd = comp_get_drvdata(dev);
- int16_t *src = (int16_t *)source->r_ptr;
- int16_t *dest = (int16_t *)sink->w_ptr;
- int32_t i;
-
- /* buffer sizes are always divisible by period frames */
- /* Samples are Q1.15 --> Q1.15 and volume is Q1.16 */
- for (i = 0; i < dev->frames * 4; i += 4) {
- dest[i] = q_multsr_sat_16x16(src[i], cd->volume[0],
- Q_SHIFT_BITS_32(15, 16, 15));
- dest[i + 1] = q_multsr_sat_16x16(src[i + 1], cd->volume[1],
- Q_SHIFT_BITS_32(15, 16, 15));
- dest[i + 2] = q_multsr_sat_16x16(src[i + 2], cd->volume[2],
- Q_SHIFT_BITS_32(15, 16, 15));
- dest[i + 3] = q_multsr_sat_16x16(src[i + 3], cd->volume[3],
- Q_SHIFT_BITS_32(15, 16, 15));
- }
-}
-
-/**
- * \brief Volume processing from 16 bit to 24/32 bit in 4 channels.
- * \param[in,out] dev Volume base component device.
- * \param[in,out] sink Destination buffer.
- * \param[in,out] source Source buffer.
- *
- * Copy and scale volume from 16 bit source buffer
- * to 24/32 bit destination buffer for 4 channels.
- */
-static void vol_s16_to_s24_4ch(struct comp_dev *dev, struct comp_buffer *sink,
- struct comp_buffer *source)
-{
- struct comp_data *cd = comp_get_drvdata(dev);
- int16_t *src = (int16_t *)source->r_ptr;
- int32_t *dest = (int32_t *)sink->w_ptr;
- int32_t i;
-
- /* buffer sizes are always divisible by period frames */
- /* Samples are Q1.15 and volume is Q1.16 */
- for (i = 0; i < dev->frames * 4; i += 4) {
- dest[i] = q_multsr_sat_32x32(src[i], cd->volume[0],
- Q_SHIFT_BITS_64(15, 16, 23));
- dest[i + 1] = q_multsr_sat_32x32(src[i + 1], cd->volume[1],
- Q_SHIFT_BITS_64(15, 16, 23));
- dest[i + 2] = q_multsr_sat_32x32(src[i + 2], cd->volume[2],
- Q_SHIFT_BITS_64(15, 16, 23));
- dest[i + 3] = q_multsr_sat_32x32(src[i + 3], cd->volume[3],
- Q_SHIFT_BITS_64(15, 16, 23));
- }
-}
-
-/**
- * \brief Volume processing from 24/32 bit to 16 bit in 4 channels.
- * \param[in,out] dev Volume base component device.
- * \param[in,out] sink Destination buffer.
- * \param[in,out] source Source buffer.
- *
- * Copy and scale volume from 24/32 bit source buffer
- * to 16 bit destination buffer for 4 channels.
- */
-static void vol_s24_to_s16_4ch(struct comp_dev *dev, struct comp_buffer *sink,
- struct comp_buffer *source)
-{
- struct comp_data *cd = comp_get_drvdata(dev);
- int32_t *src = (int32_t *)source->r_ptr;
- int16_t *dest = (int16_t *)sink->w_ptr;
- int32_t i, sample;
-
- /* buffer sizes are always divisible by period frames */
- /* Samples are Q1.23 --> Q1.15 and volume is Q1.16 */
- for (i = 0; i < dev->frames * 4; i += 4) {
- sample = sign_extend_s24(src[i]);
- dest[i] = (int16_t)q_multsr_sat_32x32(sample, cd->volume[0],
- Q_SHIFT_BITS_64(23, 16,
- 15));
- sample = sign_extend_s24(src[i + 1]);
- dest[i + 1] = (int16_t)q_multsr_sat_32x32(sample,
- cd->volume[1],
- Q_SHIFT_BITS_64(23,
- 16,
- 15));
- sample = sign_extend_s24(src[i + 2]);
- dest[i + 2] = (int16_t)q_multsr_sat_32x32(sample,
- cd->volume[2],
- Q_SHIFT_BITS_64(23,
- 16,
- 15));
- sample = sign_extend_s24(src[i + 3]);
- dest[i + 3] = (int16_t)q_multsr_sat_32x32(sample,
- cd->volume[3],
- Q_SHIFT_BITS_64(23,
- 16,
- 15));
- }
-}
-
-/**
- * \brief Volume processing from 32 bit to 24/32 bit in 4 channels.
- * \param[in,out] dev Volume base component device.
- * \param[in,out] sink Destination buffer.
- * \param[in,out] source Source buffer.
- *
- * Copy and scale volume from 32 bit source buffer
- * to 24/32 bit destination buffer for 4 channels.
- */
-static void vol_s32_to_s24_4ch(struct comp_dev *dev, struct comp_buffer *sink,
- struct comp_buffer *source)
-{
- struct comp_data *cd = comp_get_drvdata(dev);
- int32_t *src = (int32_t *)source->r_ptr;
- int32_t *dest = (int32_t *)sink->w_ptr;
- int32_t i;
-
- /* buffer sizes are always divisible by period frames */
- /* Samples are Q1.31 --> Q1.23 and volume is Q1.16 */
- for (i = 0; i < dev->frames * 4; i += 4) {
- dest[i] = q_multsr_sat_32x32(src[i], cd->volume[0],
- Q_SHIFT_BITS_64(31, 16, 23));
- dest[i + 1] = q_multsr_sat_32x32(src[i + 1], cd->volume[1],
- Q_SHIFT_BITS_64(31, 16, 23));
- dest[i + 2] = q_multsr_sat_32x32(src[i + 2], cd->volume[2],
- Q_SHIFT_BITS_64(31, 16, 23));
- dest[i + 3] = q_multsr_sat_32x32(src[i + 3], cd->volume[3],
- Q_SHIFT_BITS_64(31, 16, 23));
- }
-}
-
-/**
- * \brief Volume processing from 24/32 bit to 32 bit in 4 channels.
- * \param[in,out] dev Volume base component device.
- * \param[in,out] sink Destination buffer.
- * \param[in,out] source Source buffer.
- *
- * Copy and scale volume from 24/32 bit source buffer
- * to 32 bit destination buffer for 4 channels.
- */
-static void vol_s24_to_s32_4ch(struct comp_dev *dev, struct comp_buffer *sink,
- struct comp_buffer *source)
-{
- struct comp_data *cd = comp_get_drvdata(dev);
- int32_t *src = (int32_t *)source->r_ptr;
- int32_t *dest = (int32_t *)sink->w_ptr;
- int32_t i;
-
- /* buffer sizes are always divisible by period frames */
- /* Samples are Q1.23 --> Q1.31 and volume is Q1.16 */
- for (i = 0; i < dev->frames * 4; i += 4) {
- dest[i] = q_multsr_sat_32x32(sign_extend_s24(src[i]),
- cd->volume[0],
- Q_SHIFT_BITS_64(23, 16, 31));
- dest[i + 1] = q_multsr_sat_32x32(sign_extend_s24(src[i + 1]),
- cd->volume[1],
- Q_SHIFT_BITS_64(23, 16, 31));
- dest[i + 2] = q_multsr_sat_32x32(sign_extend_s24(src[i + 2]),
- cd->volume[2],
- Q_SHIFT_BITS_64(23, 16, 31));
- dest[i + 3] = q_multsr_sat_32x32(sign_extend_s24(src[i + 3]),
- cd->volume[3],
- Q_SHIFT_BITS_64(23, 16, 31));
- }
-}
-
-/**
- * \brief Volume processing from 24/32 bit to 24/32 bit in 4 channels.
- * \param[in,out] dev Volume base component device.
- * \param[in,out] sink Destination buffer.
- * \param[in,out] source Source buffer.
- *
- * Copy and scale volume from 24/32 bit source buffer
- * to 24/32 bit destination buffer for 4 channels.
- */
-static void vol_s24_to_s24_4ch(struct comp_dev *dev, struct comp_buffer *sink,
- struct comp_buffer *source)
-{
- struct comp_data *cd = comp_get_drvdata(dev);
- int32_t i, *src = (int32_t *)source->r_ptr;
- int32_t *dest = (int32_t *)sink->w_ptr;
-
- /* buffer sizes are always divisible by period frames */
- /* Samples are Q1.23 --> Q1.23 and volume is Q1.16 */
- for (i = 0; i < dev->frames * 4; i += 4) {
- dest[i] = q_multsr_sat_32x32(sign_extend_s24(src[i]),
- cd->volume[0],
- Q_SHIFT_BITS_64(23, 16, 23));
- dest[i + 1] = q_multsr_sat_32x32(sign_extend_s24(src[i + 1]),
- cd->volume[1],
- Q_SHIFT_BITS_64(23, 16, 23));
- dest[i + 2] = q_multsr_sat_32x32(sign_extend_s24(src[i + 2]),
- cd->volume[2],
- Q_SHIFT_BITS_64(23, 16, 23));
- dest[i + 3] = q_multsr_sat_32x32(sign_extend_s24(src[i + 3]),
- cd->volume[3],
- Q_SHIFT_BITS_64(23, 16, 23));
- }
-}
-#endif
-
-#if PLATFORM_MAX_CHANNELS >= 8
-/* volume scaling functions for 8-channel input */
-
-/* copy and scale volume from 16 bit source buffer to 32 bit dest buffer */
-static void vol_s16_to_s32_8ch(struct comp_dev *dev, struct comp_buffer *sink,
- struct comp_buffer *source)
-{
- struct comp_data *cd = comp_get_drvdata(dev);
- int16_t *src = (int16_t *)source->r_ptr;
- int32_t *dest = (int32_t *)sink->w_ptr;
- int32_t i;
-
- /* buffer sizes are always divisible by period frames */
- /* Samples are Q1.15 --> Q1.31 and volume is Q1.16 */
- for (i = 0; i < dev->frames * 8; i += 8) {
- dest[i] = (int32_t)src[i] * cd->volume[0];
- dest[i + 1] = (int32_t)src[i + 1] * cd->volume[1];
- dest[i + 2] = (int32_t)src[i + 2] * cd->volume[2];
- dest[i + 3] = (int32_t)src[i + 3] * cd->volume[3];
- dest[i + 4] = (int32_t)src[i + 4] * cd->volume[4];
- dest[i + 5] = (int32_t)src[i + 5] * cd->volume[5];
- dest[i + 6] = (int32_t)src[i + 6] * cd->volume[6];
- dest[i + 7] = (int32_t)src[i + 7] * cd->volume[7];
- }
-}
-
-/* copy and scale volume from 32 bit source buffer to 16 bit dest buffer */
-static void vol_s32_to_s16_8ch(struct comp_dev *dev, struct comp_buffer *sink,
- struct comp_buffer *source)
-{
- struct comp_data *cd = comp_get_drvdata(dev);
- int32_t *src = (int32_t *)source->r_ptr;
- int16_t *dest = (int16_t *)sink->w_ptr;
- int32_t i;
-
- /* buffer sizes are always divisible by period frames */
- /* Samples are Q1.31 --> Q1.15 and volume is Q1.16 */
- for (i = 0; i < dev->frames * 8; i += 8) {
- dest[i] = (int16_t)q_multsr_sat_32x32(src[i], cd->volume[0],
- Q_SHIFT_BITS_64(31, 16,
- 15));
- dest[i + 1] = (int16_t)q_multsr_sat_32x32(src[i + 1],
- cd->volume[1],
- Q_SHIFT_BITS_64(31,
- 16,
- 15));
- dest[i + 2] = (int16_t)q_multsr_sat_32x32(src[i + 2],
- cd->volume[2],
- Q_SHIFT_BITS_64(31,
- 16,
- 15));
- dest[i + 3] = (int16_t)q_multsr_sat_32x32(src[i + 3],
- cd->volume[3],
- Q_SHIFT_BITS_64(31,
- 16,
- 15));
- dest[i + 4] = (int16_t)q_multsr_sat_32x32(src[i + 4],
- cd->volume[4],
- Q_SHIFT_BITS_64(31,
- 16,
- 15));
- dest[i + 5] = (int16_t)q_multsr_sat_32x32(src[i + 5],
- cd->volume[5],
- Q_SHIFT_BITS_64(31,
- 16,
- 15));
- dest[i + 6] = (int16_t)q_multsr_sat_32x32(src[i + 6],
- cd->volume[6],
- Q_SHIFT_BITS_64(31,
- 16,
- 15));
- dest[i + 7] = (int16_t)q_multsr_sat_32x32(src[i + 7],
- cd->volume[7],
- Q_SHIFT_BITS_64(31,
- 16,
- 15));
- }
-}
-
-/* copy and scale volume from 32 bit source buffer to 32 bit dest buffer */
-static void vol_s32_to_s32_8ch(struct comp_dev *dev, struct comp_buffer *sink,
- struct comp_buffer *source)
-{
- struct comp_data *cd = comp_get_drvdata(dev);
- int32_t *src = (int32_t *)source->r_ptr;
- int32_t *dest = (int32_t *)sink->w_ptr;
- int32_t i;
-
- /* buffer sizes are always divisible by period frames */
- /* Samples are Q1.31 --> Q1.31 and volume is Q1.16 */
- for (i = 0; i < dev->frames * 8; i += 8) {
- dest[i] = q_multsr_sat_32x32(src[i], cd->volume[0],
- Q_SHIFT_BITS_64(31, 16, 31));
- dest[i + 1] = q_multsr_sat_32x32(src[i + 1], cd->volume[1],
- Q_SHIFT_BITS_64(31, 16, 31));
- dest[i + 2] = q_multsr_sat_32x32(src[i + 2], cd->volume[2],
- Q_SHIFT_BITS_64(31, 16, 31));
- dest[i + 3] = q_multsr_sat_32x32(src[i + 3], cd->volume[3],
- Q_SHIFT_BITS_64(31, 16, 31));
- dest[i + 4] = q_multsr_sat_32x32(src[i + 4], cd->volume[4],
- Q_SHIFT_BITS_64(31, 16, 31));
- dest[i + 5] = q_multsr_sat_32x32(src[i + 5], cd->volume[5],
- Q_SHIFT_BITS_64(31, 16, 31));
- dest[i + 6] = q_multsr_sat_32x32(src[i + 6], cd->volume[6],
- Q_SHIFT_BITS_64(31, 16, 31));
- dest[i + 7] = q_multsr_sat_32x32(src[i + 7], cd->volume[7],
- Q_SHIFT_BITS_64(31, 16, 31));
- }
-}
-
-/* copy and scale volume from 16 bit source buffer to 16 bit dest buffer */
-static void vol_s16_to_s16_8ch(struct comp_dev *dev, struct comp_buffer *sink,
- struct comp_buffer *source)
-{
- struct comp_data *cd = comp_get_drvdata(dev);
- int16_t *src = (int16_t *)source->r_ptr;
- int16_t *dest = (int16_t *)sink->w_ptr;
- int32_t i;
-
- /* buffer sizes are always divisible by period frames */
- /* Samples are Q1.15 --> Q1.15 and volume is Q1.16 */
- for (i = 0; i < dev->frames * 8; i += 8) {
- dest[i] = q_multsr_sat_16x16(src[i], cd->volume[0],
- Q_SHIFT_BITS_32(15, 16, 15));
- dest[i + 1] = q_multsr_sat_16x16(src[i + 1], cd->volume[1],
- Q_SHIFT_BITS_32(15, 16, 15));
- dest[i + 2] = q_multsr_sat_16x16(src[i + 2], cd->volume[2],
- Q_SHIFT_BITS_32(15, 16, 15));
- dest[i + 3] = q_multsr_sat_16x16(src[i + 3], cd->volume[3],
- Q_SHIFT_BITS_32(15, 16, 15));
- dest[i + 4] = q_multsr_sat_16x16(src[i + 4], cd->volume[4],
- Q_SHIFT_BITS_32(15, 16, 15));
- dest[i + 5] = q_multsr_sat_16x16(src[i + 5], cd->volume[5],
- Q_SHIFT_BITS_32(15, 16, 15));
- dest[i + 6] = q_multsr_sat_16x16(src[i + 6], cd->volume[6],
- Q_SHIFT_BITS_32(15, 16, 15));
- dest[i + 7] = q_multsr_sat_16x16(src[i + 7], cd->volume[7],
- Q_SHIFT_BITS_32(15, 16, 15));
- }
-}
-
-/* copy and scale volume from 16 bit source buffer to 24 bit
- * on 32 bit boundary buffer
- */
-static void vol_s16_to_s24_8ch(struct comp_dev *dev, struct comp_buffer *sink,
- struct comp_buffer *source)
-{
- struct comp_data *cd = comp_get_drvdata(dev);
- int16_t *src = (int16_t *)source->r_ptr;
- int32_t *dest = (int32_t *)sink->w_ptr;
- int32_t i;
-
- /* buffer sizes are always divisible by period frames */
- /* Samples are Q1.15 and volume is Q1.16 */
- for (i = 0; i < dev->frames * 8; i += 8) {
- dest[i] = q_multsr_sat_32x32(src[i], cd->volume[0],
- Q_SHIFT_BITS_64(15, 16, 23));
- dest[i + 1] = q_multsr_sat_32x32(src[i + 1], cd->volume[1],
- Q_SHIFT_BITS_64(15, 16, 23));
- dest[i + 2] = q_multsr_sat_32x32(src[i + 2], cd->volume[2],
- Q_SHIFT_BITS_64(15, 16, 23));
- dest[i + 3] = q_multsr_sat_32x32(src[i + 3], cd->volume[3],
- Q_SHIFT_BITS_64(15, 16, 23));
- dest[i + 4] = q_multsr_sat_32x32(src[i + 4], cd->volume[4],
- Q_SHIFT_BITS_64(15, 16, 23));
- dest[i + 5] = q_multsr_sat_32x32(src[i + 5], cd->volume[5],
- Q_SHIFT_BITS_64(15, 16, 23));
- dest[i + 6] = q_multsr_sat_32x32(src[i + 6], cd->volume[6],
- Q_SHIFT_BITS_64(15, 16, 23));
- dest[i + 7] = q_multsr_sat_32x32(src[i + 7], cd->volume[7],
- Q_SHIFT_BITS_64(15, 16, 23));
- }
-}
-
-/* copy and scale volume from 16 bit source buffer to 24 bit
- * on 32 bit boundary dest buffer
- */
-static void vol_s24_to_s16_8ch(struct comp_dev *dev, struct comp_buffer *sink,
- struct comp_buffer *source)
-{
- struct comp_data *cd = comp_get_drvdata(dev);
- int32_t *src = (int32_t *)source->r_ptr;
- int16_t *dest = (int16_t *)sink->w_ptr;
- int32_t i, sample;
-
- /* buffer sizes are always divisible by period frames */
- /* Samples are Q1.23 --> Q1.15 and volume is Q1.16 */
- for (i = 0; i < dev->frames * 8; i += 8) {
- sample = sign_extend_s24(src[i]);
- dest[i] = (int16_t)q_multsr_sat_32x32(sample, cd->volume[0],
- Q_SHIFT_BITS_64(23, 16,
- 15));
- sample = sign_extend_s24(src[i + 1]);
- dest[i + 1] = (int16_t)q_multsr_sat_32x32(sample,
- cd->volume[1],
- Q_SHIFT_BITS_64(23,
- 16,
- 15));
- sample = sign_extend_s24(src[i + 2]);
- dest[i + 2] = (int16_t)q_multsr_sat_32x32(sample,
- cd->volume[2],
- Q_SHIFT_BITS_64(23,
- 16,
- 15));
- sample = sign_extend_s24(src[i + 3]);
- dest[i + 3] = (int16_t)q_multsr_sat_32x32(sample,
- cd->volume[3],
- Q_SHIFT_BITS_64(23,
- 16,
- 15));
- sample = sign_extend_s24(src[i + 4]);
- dest[i + 4] = (int16_t)q_multsr_sat_32x32(sample,
- cd->volume[4],
- Q_SHIFT_BITS_64(23,
- 16,
- 15));
- sample = sign_extend_s24(src[i + 5]);
- dest[i + 5] = (int16_t)q_multsr_sat_32x32(sample,
- cd->volume[5],
- Q_SHIFT_BITS_64(23,
- 16,
- 15));
- sample = sign_extend_s24(src[i + 6]);
- dest[i + 6] = (int16_t)q_multsr_sat_32x32(sample,
- cd->volume[6],
- Q_SHIFT_BITS_64(23,
- 16,
- 15));
- sample = sign_extend_s24(src[i + 7]);
- dest[i + 7] = (int16_t)q_multsr_sat_32x32(sample,
- cd->volume[7],
- Q_SHIFT_BITS_64(23,
- 16,
- 15));
- }
-}
-
-/* copy and scale volume from 32 bit source buffer to 24 bit
- * on 32 bit boundary dest buffer
- */
-static void vol_s32_to_s24_8ch(struct comp_dev *dev, struct comp_buffer *sink,
- struct comp_buffer *source)
-{
- struct comp_data *cd = comp_get_drvdata(dev);
- int32_t *src = (int32_t *)source->r_ptr;
- int32_t *dest = (int32_t *)sink->w_ptr;
- int32_t i;
-
- /* buffer sizes are always divisible by period frames */
- /* Samples are Q1.31 --> Q1.23 and volume is Q1.16 */
- for (i = 0; i < dev->frames * 8; i += 8) {
- dest[i] = q_multsr_sat_32x32(src[i], cd->volume[0],
- Q_SHIFT_BITS_64(31, 16, 23));
- dest[i + 1] = q_multsr_sat_32x32(src[i + 1], cd->volume[1],
- Q_SHIFT_BITS_64(31, 16, 23));
- dest[i + 2] = q_multsr_sat_32x32(src[i + 2], cd->volume[2],
- Q_SHIFT_BITS_64(31, 16, 23));
- dest[i + 3] = q_multsr_sat_32x32(src[i + 3], cd->volume[3],
- Q_SHIFT_BITS_64(31, 16, 23));
- dest[i + 4] = q_multsr_sat_32x32(src[i + 4], cd->volume[4],
- Q_SHIFT_BITS_64(31, 16, 23));
- dest[i + 5] = q_multsr_sat_32x32(src[i + 5], cd->volume[5],
- Q_SHIFT_BITS_64(31, 16, 23));
- dest[i + 6] = q_multsr_sat_32x32(src[i + 6], cd->volume[6],
- Q_SHIFT_BITS_64(31, 16, 23));
- dest[i + 7] = q_multsr_sat_32x32(src[i + 7], cd->volume[7],
- Q_SHIFT_BITS_64(31, 16, 23));
- }
-}
-
-/* copy and scale volume from 16 bit source buffer to 24 bit
- * on 32 bit boundary dest buffer
- */
-static void vol_s24_to_s32_8ch(struct comp_dev *dev, struct comp_buffer *sink,
- struct comp_buffer *source)
-{
- struct comp_data *cd = comp_get_drvdata(dev);
- int32_t *src = (int32_t *)source->r_ptr;
- int32_t *dest = (int32_t *)sink->w_ptr;
- int32_t i;
-
- /* buffer sizes are always divisible by period frames */
- /* Samples are Q1.23 --> Q1.31 and volume is Q1.16 */
- for (i = 0; i < dev->frames * 8; i += 8) {
- dest[i] = q_multsr_sat_32x32(sign_extend_s24(src[i]),
- cd->volume[0],
- Q_SHIFT_BITS_64(23, 16, 31));
- dest[i + 1] = q_multsr_sat_32x32(sign_extend_s24(src[i + 1]),
- cd->volume[1],
- Q_SHIFT_BITS_64(23, 16, 31));
- dest[i + 2] = q_multsr_sat_32x32(sign_extend_s24(src[i + 2]),
- cd->volume[2],
- Q_SHIFT_BITS_64(23, 16, 31));
- dest[i + 3] = q_multsr_sat_32x32(sign_extend_s24(src[i + 3]),
- cd->volume[3],
- Q_SHIFT_BITS_64(23, 16, 31));
- dest[i + 4] = q_multsr_sat_32x32(sign_extend_s24(src[i + 4]),
- cd->volume[4],
- Q_SHIFT_BITS_64(23, 16, 31));
- dest[i + 5] = q_multsr_sat_32x32(sign_extend_s24(src[i + 5]),
- cd->volume[5],
- Q_SHIFT_BITS_64(23, 16, 31));
- dest[i + 6] = q_multsr_sat_32x32(sign_extend_s24(src[i + 6]),
- cd->volume[6],
- Q_SHIFT_BITS_64(23, 16, 31));
- dest[i + 7] = q_multsr_sat_32x32(sign_extend_s24(src[i + 7]),
- cd->volume[7],
- Q_SHIFT_BITS_64(23, 16, 31));
- }
-}
-
-/* Copy and scale volume from 24 bit source buffer to 24 bit on 32 bit boundary
- * dest buffer.
- */
-static void vol_s24_to_s24_8ch(struct comp_dev *dev, struct comp_buffer *sink,
- struct comp_buffer *source)
-{
- struct comp_data *cd = comp_get_drvdata(dev);
- int32_t i, *src = (int32_t *)source->r_ptr;
- int32_t *dest = (int32_t *)sink->w_ptr;
-
- /* buffer sizes are always divisible by period frames */
- /* Samples are Q1.23 --> Q1.23 and volume is Q1.16 */
- for (i = 0; i < dev->frames * 8; i += 8) {
- dest[i] = q_multsr_sat_32x32(sign_extend_s24(src[i]),
- cd->volume[0],
- Q_SHIFT_BITS_64(23, 16, 23));
- dest[i + 1] = q_multsr_sat_32x32(sign_extend_s24(src[i + 1]),
- cd->volume[1],
- Q_SHIFT_BITS_64(23, 16, 23));
- dest[i + 2] = q_multsr_sat_32x32(sign_extend_s24(src[i + 2]),
- cd->volume[2],
- Q_SHIFT_BITS_64(23, 16, 23));
- dest[i + 3] = q_multsr_sat_32x32(sign_extend_s24(src[i + 3]),
- cd->volume[3],
- Q_SHIFT_BITS_64(23, 16, 23));
- dest[i + 4] = q_multsr_sat_32x32(sign_extend_s24(src[i + 4]),
- cd->volume[4],
- Q_SHIFT_BITS_64(23, 16, 23));
- dest[i + 5] = q_multsr_sat_32x32(sign_extend_s24(src[i + 5]),
- cd->volume[5],
- Q_SHIFT_BITS_64(23, 16, 23));
- dest[i + 6] = q_multsr_sat_32x32(sign_extend_s24(src[i + 6]),
- cd->volume[6],
- Q_SHIFT_BITS_64(23, 16, 23));
- dest[i + 7] = q_multsr_sat_32x32(sign_extend_s24(src[i + 7]),
- cd->volume[7],
- Q_SHIFT_BITS_64(23, 16, 23));
- }
-}
-#endif
-
-const struct comp_func_map func_map[] = {
- {SOF_IPC_FRAME_S16_LE, SOF_IPC_FRAME_S16_LE, 2, vol_s16_to_s16_2ch},
- {SOF_IPC_FRAME_S16_LE, SOF_IPC_FRAME_S32_LE, 2, vol_s16_to_s32_2ch},
- {SOF_IPC_FRAME_S32_LE, SOF_IPC_FRAME_S16_LE, 2, vol_s32_to_s16_2ch},
- {SOF_IPC_FRAME_S32_LE, SOF_IPC_FRAME_S32_LE, 2, vol_s32_to_s32_2ch},
- {SOF_IPC_FRAME_S16_LE, SOF_IPC_FRAME_S24_4LE, 2, vol_s16_to_s24_2ch},
- {SOF_IPC_FRAME_S24_4LE, SOF_IPC_FRAME_S16_LE, 2, vol_s24_to_s16_2ch},
- {SOF_IPC_FRAME_S32_LE, SOF_IPC_FRAME_S24_4LE, 2, vol_s32_to_s24_2ch},
- {SOF_IPC_FRAME_S24_4LE, SOF_IPC_FRAME_S32_LE, 2, vol_s24_to_s32_2ch},
- {SOF_IPC_FRAME_S24_4LE, SOF_IPC_FRAME_S24_4LE, 2, vol_s24_to_s24_2ch},
-#if PLATFORM_MAX_CHANNELS >= 4
- {SOF_IPC_FRAME_S16_LE, SOF_IPC_FRAME_S16_LE, 4, vol_s16_to_s16_4ch},
- {SOF_IPC_FRAME_S16_LE, SOF_IPC_FRAME_S32_LE, 4, vol_s16_to_s32_4ch},
- {SOF_IPC_FRAME_S32_LE, SOF_IPC_FRAME_S16_LE, 4, vol_s32_to_s16_4ch},
- {SOF_IPC_FRAME_S32_LE, SOF_IPC_FRAME_S32_LE, 4, vol_s32_to_s32_4ch},
- {SOF_IPC_FRAME_S16_LE, SOF_IPC_FRAME_S24_4LE, 4, vol_s16_to_s24_4ch},
- {SOF_IPC_FRAME_S24_4LE, SOF_IPC_FRAME_S16_LE, 4, vol_s24_to_s16_4ch},
- {SOF_IPC_FRAME_S32_LE, SOF_IPC_FRAME_S24_4LE, 4, vol_s32_to_s24_4ch},
- {SOF_IPC_FRAME_S24_4LE, SOF_IPC_FRAME_S32_LE, 4, vol_s24_to_s32_4ch},
- {SOF_IPC_FRAME_S24_4LE, SOF_IPC_FRAME_S24_4LE, 4, vol_s24_to_s24_4ch},
-#endif
-#if PLATFORM_MAX_CHANNELS >= 8
- {SOF_IPC_FRAME_S16_LE, SOF_IPC_FRAME_S16_LE, 8, vol_s16_to_s16_8ch},
- {SOF_IPC_FRAME_S16_LE, SOF_IPC_FRAME_S32_LE, 8, vol_s16_to_s32_8ch},
- {SOF_IPC_FRAME_S32_LE, SOF_IPC_FRAME_S16_LE, 8, vol_s32_to_s16_8ch},
- {SOF_IPC_FRAME_S32_LE, SOF_IPC_FRAME_S32_LE, 8, vol_s32_to_s32_8ch},
- {SOF_IPC_FRAME_S16_LE, SOF_IPC_FRAME_S24_4LE, 8, vol_s16_to_s24_8ch},
- {SOF_IPC_FRAME_S24_4LE, SOF_IPC_FRAME_S16_LE, 8, vol_s24_to_s16_8ch},
- {SOF_IPC_FRAME_S32_LE, SOF_IPC_FRAME_S24_4LE, 8, vol_s32_to_s24_8ch},
- {SOF_IPC_FRAME_S24_4LE, SOF_IPC_FRAME_S32_LE, 8, vol_s24_to_s32_8ch},
- {SOF_IPC_FRAME_S24_4LE, SOF_IPC_FRAME_S24_4LE, 8, vol_s24_to_s24_8ch},
-#endif
-};
-
-scale_vol vol_get_processing_function(struct comp_dev *dev)
-{
- struct comp_data *cd = comp_get_drvdata(dev);
- int i;
-
- /* map the volume function for source and sink buffers */
- for (i = 0; i < ARRAY_SIZE(func_map); i++) {
- if (cd->source_format != func_map[i].source)
- continue;
- if (cd->sink_format != func_map[i].sink)
- continue;
- if (dev->params.channels != func_map[i].channels)
- continue;
-
- return func_map[i].func;
- }
-
- return NULL;
-}
-
-#endif
diff --git a/src/audio/volume_hifi3.c b/src/audio/volume_hifi3.c
deleted file mode 100644
index 4b1518e..0000000
--- a/src/audio/volume_hifi3.c
+++ /dev/null
@@ -1,339 +0,0 @@
-/*
- * Copyright (c) 2018, Intel Corporation
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- * * Redistributions of source code must retain the above copyright
- * notice, this list of conditions and the following disclaimer.
- * * Redistributions in binary form must reproduce the above copyright
- * notice, this list of conditions and the following disclaimer in the
- * documentation and/or other materials provided with the distribution.
- * * Neither the name of the Intel Corporation nor the
- * names of its contributors may be used to endorse or promote products
- * derived from this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
- * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
- * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
- * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
- * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
- * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
- * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
- * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
- * POSSIBILITY OF SUCH DAMAGE.
- *
- * Author: Tomasz Lauda <tomasz.lauda@linux.intel.com>
- */
-
-/**
- * \file audio/volume_hifi3.c
- * \brief Volume HiFi3 processing implementation
- * \authors Tomasz Lauda <tomasz.lauda@linux.intel.com>
- */
-
-#include "volume.h"
-
-#if defined(__XCC__) && XCHAL_HAVE_HIFI3
-
-#include <xtensa/tie/xt_hifi3.h>
-
-/** \brief Volume scale ratio. */
-#define VOL_SCALE (uint32_t)((double)INT32_MAX / VOL_MAX)
-
-/**
- * \brief HiFi3 enabled volume processing from 16 bit to 16 bit.
- * \param[in,out] dev Volume base component device.
- * \param[in,out] sink Destination buffer.
- * \param[in,out] source Source buffer.
- */
-static void vol_s16_to_s16(struct comp_dev *dev, struct comp_buffer *sink,
- struct comp_buffer *source)
-{
- struct comp_data *cd = comp_get_drvdata(dev);
- uint32_t vol_scaled[SOF_IPC_MAX_CHANNELS];
- ae_f32x2 volume;
- ae_f32x2 mult;
- ae_f32x2 out_sample;
- ae_f16x4 in_sample = AE_ZERO16();
- size_t channel;
- int i;
- ae_int16 *in = (ae_int16 *)source->r_ptr;
- ae_int16 *out = (ae_int16 *)sink->w_ptr;
-
- /* Scale to VOL_MAX */
- for (channel = 0; channel < dev->params.channels; channel++)
- vol_scaled[channel] = cd->volume[channel] * VOL_SCALE;
-
- /* Main processing loop */
- for (i = 0; i < dev->frames; i++) {
- /* Processing per channel */
- for (channel = 0; channel < dev->params.channels; channel++) {
- /* Load the input sample */
- AE_L16_XP(in_sample, in, sizeof(ae_int16));
-
- /* Get gain coefficients */
- volume = *((ae_f32 *)&vol_scaled[channel]);
-
- /* Multiply the input sample */
- mult = AE_MULFP32X16X2RS_L(volume, in_sample);
-
- /* Shift right and round to get 16 in 32 bits */
- out_sample = AE_SRAA32RS(mult, 16);
-
- /* Store the output sample */
- AE_S16_0_XP(AE_MOVF16X4_FROMF32X2(out_sample),
- out, sizeof(ae_int16));
- }
- }
-}
-
-/**
- * \brief HiFi3 enabled volume processing from 16 bit to x bit.
- * \param[in,out] dev Volume base component device.
- * \param[in,out] sink Destination buffer.
- * \param[in,out] source Source buffer.
- */
-static void vol_s16_to_sX(struct comp_dev *dev, struct comp_buffer *sink,
- struct comp_buffer *source)
-{
- struct comp_data *cd = comp_get_drvdata(dev);
- uint32_t vol_scaled[SOF_IPC_MAX_CHANNELS];
- ae_f32x2 volume;
- ae_f32x2 mult;
- ae_f32x2 out_sample;
- ae_f16x4 in_sample = AE_ZERO16();
- size_t channel;
- uint8_t shift_left = 0;
- int i;
- ae_int16 *in = (ae_int16 *)source->r_ptr;
- ae_int32 *out = (ae_int32 *)sink->w_ptr;
-
- /* Get value of shift left */
- if (cd->sink_format == SOF_IPC_FRAME_S24_4LE)
- shift_left = 8;
- else if (cd->sink_format == SOF_IPC_FRAME_S32_LE)
- shift_left = 16;
-
- /* Scale to VOL_MAX */
- for (channel = 0; channel < dev->params.channels; channel++)
- vol_scaled[channel] = cd->volume[channel] * VOL_SCALE;
-
- /* Main processing loop */
- for (i = 0; i < dev->frames; i++) {
- /* Processing per channel */
- for (channel = 0; channel < dev->params.channels; channel++) {
- /* Load the input sample */
- AE_L16_XP(in_sample, in, sizeof(ae_int16));
-
- /* Get gain coefficients */
- volume = *((ae_f32 *)&vol_scaled[channel]);
-
- /* Multiply the input sample */
- mult = AE_MULFP32X16X2RS_L(volume, in_sample);
-
- /* Shift right and round to get 16 in 32 bits */
- out_sample = AE_SRAA32RS(mult, 16);
-
- /* Shift left to get the right alignment */
- out_sample = AE_SLAA32(out_sample, shift_left);
-
- /* Store the output sample */
- AE_S32_L_XP(out_sample, out, sizeof(ae_int32));
- }
- }
-}
-
-/**
- * \brief HiFi3 enabled volume processing from x bit to 16 bit.
- * \param[in,out] dev Volume base component device.
- * \param[in,out] sink Destination buffer.
- * \param[in,out] source Source buffer.
- */
-static void vol_sX_to_s16(struct comp_dev *dev, struct comp_buffer *sink,
- struct comp_buffer *source)
-{
- struct comp_data *cd = comp_get_drvdata(dev);
- uint32_t vol_scaled[SOF_IPC_MAX_CHANNELS];
- ae_f32x2 volume;
- ae_f32x2 mult;
- ae_f32x2 in_sample = AE_ZERO32();
- ae_f16x4 out_sample;
- size_t channel;
- uint8_t shift_left = 0;
- int i;
- ae_int32 *in = (ae_int32 *)source->r_ptr;
- ae_int16 *out = (ae_int16 *)sink->w_ptr;
-
- /* Get value of shift left */
- if (cd->source_format == SOF_IPC_FRAME_S24_4LE)
- shift_left = 8;
-
- /* Scale to VOL_MAX */
- for (channel = 0; channel < dev->params.channels; channel++)
- vol_scaled[channel] = cd->volume[channel] * VOL_SCALE;
-
- /* Main processing loop */
- for (i = 0; i < dev->frames; i++) {
- /* Processing per channel */
- for (channel = 0; channel < dev->params.channels; channel++) {
- /* Load the input sample */
- AE_L32_XP(in_sample, in, sizeof(ae_int32));
-
- /* Shift left to get the right alignment */
- in_sample = AE_SLAA32(in_sample, shift_left);
-
- /* Get gain coefficients */
- volume = *((ae_f32 *)&vol_scaled[channel]);
-
- /* Multiply the input sample */
- mult = AE_MULFP32X2RS(volume, in_sample);
-
- /* Shift right to get 16 in 32 bits */
- out_sample = AE_MOVF16X4_FROMF32X2
- (AE_SRLA32(mult, 16));
-
- /* Store the output sample */
- AE_S16_0_XP(out_sample, out, sizeof(ae_int16));
- }
- }
-}
-
-/**
- * \brief HiFi3 enabled volume processing from 24/32 bit to 24/32 or 32 bit.
- * \param[in,out] dev Volume base component device.
- * \param[in,out] sink Destination buffer.
- * \param[in,out] source Source buffer.
- */
-static void vol_s24_to_s24_s32(struct comp_dev *dev, struct comp_buffer *sink,
- struct comp_buffer *source)
-{
- struct comp_data *cd = comp_get_drvdata(dev);
- uint32_t vol_scaled[SOF_IPC_MAX_CHANNELS];
- ae_f32x2 volume;
- ae_f32x2 in_sample = AE_ZERO32();
- ae_f32x2 out_sample;
- ae_f32x2 mult;
- size_t channel;
- uint8_t shift_left = 0;
- int i;
- ae_int32 *in = (ae_int32 *)source->r_ptr;
- ae_int32 *out = (ae_int32 *)sink->w_ptr;
-
- /* Get value of shift left */
- if (cd->sink_format == SOF_IPC_FRAME_S32_LE)
- shift_left = 8;
-
- /* Scale to VOL_MAX */
- for (channel = 0; channel < dev->params.channels; channel++)
- vol_scaled[channel] = cd->volume[channel] * VOL_SCALE;
-
- /* Main processing loop */
- for (i = 0; i < dev->frames; i++) {
- /* Processing per channel */
- for (channel = 0; channel < dev->params.channels; channel++) {
- /* Load the input sample */
- AE_L32_XP(in_sample, in, sizeof(ae_int32));
-
- /* Get gain coefficients */
- volume = *((ae_f32 *)&vol_scaled[channel]);
-
- /* Multiply the input sample */
- mult = AE_MULFP32X2RS(volume, AE_SLAA32(in_sample, 8));
-
- /* Shift right to get 24 in 32 bits (LSB) */
- out_sample = AE_SRLA32(mult, 8);
-
- /* Shift left to get the right alignment */
- out_sample = AE_SLAA32(out_sample, shift_left);
-
- /* Store the output sample */
- AE_S32_L_XP(out_sample, out, sizeof(ae_int32));
- }
- }
-}
-
-/**
- * \brief HiFi3 enabled volume processing from 32 bit to 24/32 or 32 bit.
- * \param[in,out] dev Volume base component device.
- * \param[in,out] sink Destination buffer.
- * \param[in,out] source Source buffer.
- */
-static void vol_s32_to_s24_s32(struct comp_dev *dev, struct comp_buffer *sink,
- struct comp_buffer *source)
-{
- struct comp_data *cd = comp_get_drvdata(dev);
- uint32_t vol_scaled[SOF_IPC_MAX_CHANNELS];
- ae_f32x2 volume;
- ae_f32x2 in_sample = AE_ZERO32();
- ae_f32x2 out_sample;
- ae_f32x2 mult;
- size_t channel;
- uint8_t shift_right = 0;
- int i;
- ae_int32 *in = (ae_int32 *)source->r_ptr;
- ae_int32 *out = (ae_int32 *)sink->w_ptr;
-
- /* Get value of shift right */
- if (cd->sink_format == SOF_IPC_FRAME_S24_4LE)
- shift_right = 8;
-
- /* Scale to VOL_MAX */
- for (channel = 0; channel < dev->params.channels; channel++)
- vol_scaled[channel] = cd->volume[channel] * VOL_SCALE;
-
- /* Main processing loop */
- for (i = 0; i < dev->frames; i++) {
- /* Processing per channel */
- for (channel = 0; channel < dev->params.channels; channel++) {
- /* Load the input sample */
- AE_L32_XP(in_sample, in, sizeof(ae_int32));
-
- /* Get gain coefficients */
- volume = *((ae_f32 *)&vol_scaled[channel]);
-
- /* Multiply the input sample */
- mult = AE_MULFP32X2RS(volume, in_sample);
-
- /* Shift right to get the right alignment */
- out_sample = AE_SRLA32(mult, shift_right);
-
- /* Store the output sample */
- AE_S32_L_XP(out_sample, out, sizeof(ae_int32));
- }
- }
-}
-
-const struct comp_func_map func_map[] = {
- {SOF_IPC_FRAME_S16_LE, SOF_IPC_FRAME_S16_LE, 0, vol_s16_to_s16},
- {SOF_IPC_FRAME_S16_LE, SOF_IPC_FRAME_S24_4LE, 0, vol_s16_to_sX},
- {SOF_IPC_FRAME_S16_LE, SOF_IPC_FRAME_S32_LE, 0, vol_s16_to_sX},
- {SOF_IPC_FRAME_S24_4LE, SOF_IPC_FRAME_S16_LE, 0, vol_sX_to_s16},
- {SOF_IPC_FRAME_S24_4LE, SOF_IPC_FRAME_S24_4LE, 0, vol_s24_to_s24_s32},
- {SOF_IPC_FRAME_S24_4LE, SOF_IPC_FRAME_S32_LE, 0, vol_s24_to_s24_s32},
- {SOF_IPC_FRAME_S32_LE, SOF_IPC_FRAME_S16_LE, 0, vol_sX_to_s16},
- {SOF_IPC_FRAME_S32_LE, SOF_IPC_FRAME_S24_4LE, 0, vol_s32_to_s24_s32},
- {SOF_IPC_FRAME_S32_LE, SOF_IPC_FRAME_S32_LE, 0, vol_s32_to_s24_s32},
-};
-
-scale_vol vol_get_processing_function(struct comp_dev *dev)
-{
- struct comp_data *cd = comp_get_drvdata(dev);
- int i;
-
- /* map the volume function for source and sink buffers */
- for (i = 0; i < ARRAY_SIZE(func_map); i++) {
- if (cd->source_format != func_map[i].source)
- continue;
- if (cd->sink_format != func_map[i].sink)
- continue;
-
- return func_map[i].func;
- }
-
- return NULL;
-}
-
-#endif
diff --git a/src/drivers/Makefile.am b/src/drivers/Makefile.am
deleted file mode 100644
index 0a85b02..0000000
--- a/src/drivers/Makefile.am
+++ /dev/null
@@ -1,47 +0,0 @@
-noinst_LIBRARIES = libdrivers.a
-
-libdrivers_a_SOURCES = \
- dw-dma.c
-
-if BUILD_BAYTRAIL
-libdrivers_a_SOURCES += \
- byt-ssp.c
-endif
-
-if BUILD_CHERRYTRAIL
-libdrivers_a_SOURCES += \
- byt-ssp.c
-endif
-
-if BUILD_HASWELL
-libdrivers_a_SOURCES += \
- hsw-ssp.c
-endif
-
-if BUILD_BROADWELL
-libdrivers_a_SOURCES += \
- hsw-ssp.c
-endif
-
-if BUILD_APOLLOLAKE
-libdrivers_a_SOURCES += \
- apl-ssp.c \
- hda-dma.c \
- cavs-hda.c \
- dmic.c
-endif
-
-if BUILD_CANNONLAKE
-libdrivers_a_SOURCES += \
- apl-ssp.c \
- hda-dma.c \
- cavs-hda.c \
- dmic.c
-endif
-
-libdrivers_a_CFLAGS = \
- $(AM_CFLAGS) \
- $(ARCH_CFLAGS) \
- $(PLATFORM_INCDIR) \
- $(SOF_INCDIR) \
- $(ARCH_INCDIR)
diff --git a/src/drivers/apl-ssp.c b/src/drivers/apl-ssp.c
deleted file mode 100644
index 53207f2..0000000
--- a/src/drivers/apl-ssp.c
+++ /dev/null
@@ -1,839 +0,0 @@
-/*
- * Copyright (c) 2016, Intel Corporation
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- * * Redistributions of source code must retain the above copyright
- * notice, this list of conditions and the following disclaimer.
- * * Redistributions in binary form must reproduce the above copyright
- * notice, this list of conditions and the following disclaimer in the
- * documentation and/or other materials provided with the distribution.
- * * Neither the name of the Intel Corporation nor the
- * names of its contributors may be used to endorse or promote products
- * derived from this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
- * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
- * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
- * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
- * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
- * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
- * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
- * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
- * POSSIBILITY OF SUCH DAMAGE.
- *
- * Author: Liam Girdwood <liam.r.girdwood@linux.intel.com>
- * Keyon Jie <yang.jie@linux.intel.com>
- * Rander Wang <rander.wang@linux.intel.com>
- */
-
-#include <errno.h>
-#include <stdbool.h>
-#include <sof/stream.h>
-#include <sof/ssp.h>
-#include <sof/alloc.h>
-#include <sof/interrupt.h>
-#include <sof/math/numbers.h>
-#include <config.h>
-
-/* tracing */
-#define trace_ssp(__e) trace_event(TRACE_CLASS_SSP, __e)
-#define trace_ssp_error(__e) trace_error(TRACE_CLASS_SSP, __e)
-#define tracev_ssp(__e) tracev_event(TRACE_CLASS_SSP, __e)
-
-#define F_19200_kHz 19200000
-#define F_24000_kHz 24000000
-#define F_24576_kHz 24576000
-
-/* FIXME: move this to a helper and optimize */
-static int hweight_32(uint32_t mask)
-{
- int i;
- int count = 0;
-
- for (i = 0; i < 32; i++) {
- count += mask & 1;
- mask >>= 1;
- }
- return count;
-}
-
-/* empty SSP receive FIFO */
-static void ssp_empty_rx_fifo(struct dai *dai)
-{
- struct ssp_pdata *ssp = dai_get_drvdata(dai);
- uint32_t sssr;
- uint32_t entries;
- uint32_t i;
-
- spin_lock(&ssp->lock);
-
- sssr = ssp_read(dai, SSSR);
-
- /* clear interrupt */
- if (sssr & SSSR_ROR)
- ssp_write(dai, SSSR, sssr);
-
- /* empty fifo */
- if (sssr & SSSR_RNE) {
- entries = (ssp_read(dai, SSCR3) & SSCR3_RFL_MASK) >> 8;
- for (i = 0; i < entries + 1; i++)
- ssp_read(dai, SSDR);
- }
-
- spin_unlock(&ssp->lock);
-}
-
-/* save SSP context prior to entering D3 */
-static int ssp_context_store(struct dai *dai)
-{
- struct ssp_pdata *ssp = dai_get_drvdata(dai);
-
- ssp->sscr0 = ssp_read(dai, SSCR0);
- ssp->sscr1 = ssp_read(dai, SSCR1);
-
- /* FIXME: need to store sscr2,3,4,5 */
- ssp->psp = ssp_read(dai, SSPSP);
-
- return 0;
-}
-
-/* restore SSP context after leaving D3 */
-static int ssp_context_restore(struct dai *dai)
-{
- struct ssp_pdata *ssp = dai_get_drvdata(dai);
-
- ssp_write(dai, SSCR0, ssp->sscr0);
- ssp_write(dai, SSCR1, ssp->sscr1);
- /* FIXME: need to restore sscr2,3,4,5 */
- ssp_write(dai, SSPSP, ssp->psp);
-
- return 0;
-}
-
-/* Digital Audio interface formatting */
-static inline int ssp_set_config(struct dai *dai,
- struct sof_ipc_dai_config *config)
-{
- struct ssp_pdata *ssp = dai_get_drvdata(dai);
- uint32_t sscr0;
- uint32_t sscr1;
- uint32_t sscr2;
- uint32_t sscr3;
- uint32_t sspsp;
- uint32_t sspsp2;
- uint32_t sstsa;
- uint32_t ssrsa;
- uint32_t ssto;
- uint32_t ssioc;
- uint32_t mdiv;
- uint32_t bdiv;
- uint32_t mdivc;
- uint32_t mdivr;
- uint32_t mdivr_val;
- uint32_t i2s_m;
- uint32_t i2s_n;
- uint32_t data_size;
- uint32_t frame_end_padding;
- uint32_t slot_end_padding;
- uint32_t frame_len = 0;
- uint32_t bdiv_min;
- uint32_t tft;
- uint32_t rft;
- uint32_t active_tx_slots = 2;
- uint32_t active_rx_slots = 2;
- uint32_t sample_width = 2;
-
- bool inverted_frame = false;
- bool cfs = false;
- bool start_delay = false;
- int ret = 0;
-
- spin_lock(&ssp->lock);
-
- /* is playback/capture already running */
- if (ssp->state[DAI_DIR_PLAYBACK] == COMP_STATE_ACTIVE ||
- ssp->state[DAI_DIR_CAPTURE] == COMP_STATE_ACTIVE) {
- trace_ssp_error("ec1");
- ret = -EINVAL;
- goto out;
- }
-
- trace_ssp("cos");
- trace_value(config->format);
-
- /* reset SSP settings */
- /* sscr0 dynamic settings are DSS, EDSS, SCR, FRDC, ECS */
- /*
- * FIXME: MOD, ACS, NCS are not set,
- * no support for network mode for now
- */
- sscr0 = SSCR0_PSP | SSCR0_RIM | SSCR0_TIM;
-
- /* sscr1 dynamic settings are SFRMDIR, SCLKDIR, SCFR */
- sscr1 = SSCR1_TTE | SSCR1_TTELP | SSCR1_TRAIL | SSCR1_RSRE | SSCR1_TSRE;
-
- /* sscr2 dynamic setting is LJDFD */
- sscr2 = SSCR2_SDFD | SSCR2_TURM1;
-
- /* sscr3 dynamic settings are TFT, RFT */
- sscr3 = 0;
-
- /* sspsp dynamic settings are SCMODE, SFRMP, DMYSTRT, SFRMWDTH */
- sspsp = 0;
-
- ssp->config = *config;
- ssp->params = config->ssp;
-
- /* sspsp2 no dynamic setting */
- sspsp2 = 0x0;
-
- /* ssioc dynamic setting is SFCR */
- ssioc = SSIOC_SCOE;
-
- /* i2s_m M divider setting, default 1 */
- i2s_m = 0x1;
-
- /* i2s_n N divider setting, default 1 */
- i2s_n = 0x1;
-
- /* ssto no dynamic setting */
- ssto = 0x0;
-
- /* sstsa dynamic setting is TTSA, default 2 slots */
- sstsa = config->ssp.tx_slots;
-
- /* ssrsa dynamic setting is RTSA, default 2 slots */
- ssrsa = config->ssp.rx_slots;
-
- trace_value(config->format);
- switch (config->format & SOF_DAI_FMT_MASTER_MASK) {
- case SOF_DAI_FMT_CBM_CFM:
- sscr1 |= SSCR1_SCLKDIR | SSCR1_SFRMDIR;
- break;
- case SOF_DAI_FMT_CBS_CFS:
- sscr1 |= SSCR1_SCFR;
- cfs = true;
- break;
- case SOF_DAI_FMT_CBM_CFS:
- sscr1 |= SSCR1_SCLKDIR;
- /* FIXME: this mode has not been tested */
-
- cfs = true;
- break;
- case SOF_DAI_FMT_CBS_CFM:
- sscr1 |= SSCR1_SCFR | SSCR1_SFRMDIR;
- /* FIXME: this mode has not been tested */
- break;
- default:
- trace_ssp_error("ec2");
- ret = -EINVAL;
- goto out;
- }
-
- /* clock signal polarity */
- switch (config->format & SOF_DAI_FMT_INV_MASK) {
- case SOF_DAI_FMT_NB_NF:
- break;
- case SOF_DAI_FMT_NB_IF:
- inverted_frame = true; /* handled later with format */
- break;
- case SOF_DAI_FMT_IB_IF:
- sspsp |= SSPSP_SCMODE(2);
- inverted_frame = true; /* handled later with format */
- break;
- case SOF_DAI_FMT_IB_NF:
- sspsp |= SSPSP_SCMODE(2);
- break;
- default:
- trace_ssp_error("ec3");
- ret = -EINVAL;
- goto out;
- }
-
- sscr0 |= SSCR0_MOD | SSCR0_ACS;
-
- mdivc = mn_reg_read(0x0);
- mdivc |= 0x1;
-
- /* Additional hardware settings */
-
- /* Receiver Time-out Interrupt Disabled/Enabled */
- sscr1 |= (ssp->params.quirks & SOF_DAI_INTEL_SSP_QUIRK_TINTE) ?
- SSCR1_TINTE : 0;
-
- /* Peripheral Trailing Byte Interrupts Disable/Enable */
- sscr1 |= (ssp->params.quirks & SOF_DAI_INTEL_SSP_QUIRK_PINTE) ?
- SSCR1_PINTE : 0;
-
- /* Transmit data are driven at the same/opposite clock edge specified
- * in SSPSP.SCMODE[1:0]
- */
- sscr2 |= (ssp->params.quirks & SOF_DAI_INTEL_SSP_QUIRK_SMTATF) ?
- SSCR2_SMTATF : 0;
-
- /* Receive data are sampled at the same/opposite clock edge specified
- * in SSPSP.SCMODE[1:0]
- */
- sscr2 |= (ssp->params.quirks & SOF_DAI_INTEL_SSP_QUIRK_MMRATF) ?
- SSCR2_MMRATF : 0;
-
- /* Enable/disable the fix for PSP slave mode TXD wait for frame
- * de-assertion before starting the second channel
- */
- sscr2 |= (ssp->params.quirks & SOF_DAI_INTEL_SSP_QUIRK_PSPSTWFDFD) ?
- SSCR2_PSPSTWFDFD : 0;
-
- /* Enable/disable the fix for PSP master mode FSRT with dummy stop &
- * frame end padding capability
- */
- sscr2 |= (ssp->params.quirks & SOF_DAI_INTEL_SSP_QUIRK_PSPSRWFDFD) ?
- SSCR2_PSPSRWFDFD : 0;
-
-#ifdef CONFIG_CANNONLAKE
- if (!config->ssp.mclk_rate || config->ssp.mclk_rate > F_24000_kHz) {
- trace_ssp_error("eci");
- ret = -EINVAL;
- goto out;
- }
- if (!config->ssp.bclk_rate ||
- config->ssp.bclk_rate > config->ssp.mclk_rate) {
- trace_ssp_error("ecj");
- ret = -EINVAL;
- goto out;
- }
-
- if (F_24000_kHz % config->ssp.mclk_rate == 0) {
- mdivr_val = F_24000_kHz / config->ssp.mclk_rate;
- } else {
- trace_ssp_error("eck");
- ret = -EINVAL;
- goto out;
- }
-
- if (F_24000_kHz % config->ssp.bclk_rate == 0) {
- mdiv = F_24000_kHz / config->ssp.bclk_rate;
- } else {
- trace_ssp_error("ecl");
- ret = -EINVAL;
- goto out;
- }
-#else
- if (!config->ssp.mclk_rate || config->ssp.mclk_rate > F_24576_kHz) {
- trace_ssp_error("eci");
- ret = -EINVAL;
- goto out;
- }
- if (!config->ssp.bclk_rate ||
- config->ssp.bclk_rate > config->ssp.mclk_rate) {
- trace_ssp_error("ecj");
- ret = -EINVAL;
- goto out;
- }
- if (F_24576_kHz % config->ssp.mclk_rate == 0) {
- /* select Audio Cardinal clock for MCLK */
- mdivc |= MCDSS(1);
- mdivr_val = F_24576_kHz / config->ssp.mclk_rate;
- } else if (config->ssp.mclk_rate <= F_19200_kHz &&
- F_19200_kHz % config->ssp.mclk_rate == 0) {
- mdivr_val = F_19200_kHz / config->ssp.mclk_rate;
- } else {
- trace_ssp_error("eck");
- ret = -EINVAL;
- goto out;
- }
-
- if (F_24576_kHz % config->ssp.bclk_rate == 0) {
- /* select Audio Cardinal clock for M/N dividers */
- mdivc |= MNDSS(1);
- mdiv = F_24576_kHz / config->ssp.bclk_rate;
- /* select M/N output for bclk */
- sscr0 |= SSCR0_ECS;
- } else if (F_19200_kHz % config->ssp.bclk_rate == 0) {
- mdiv = F_19200_kHz / config->ssp.bclk_rate;
- } else {
- trace_ssp_error("ecl");
- ret = -EINVAL;
- goto out;
- }
-#endif
-
- switch (mdivr_val) {
- case 1:
- mdivr = 0x00000fff; /* bypass divider for MCLK */
- break;
- case 2:
- mdivr = 0x0; /* 1/2 */
- break;
- case 4:
- mdivr = 0x2; /* 1/4 */
- break;
- case 8:
- mdivr = 0x6; /* 1/8 */
- break;
- default:
- trace_ssp_error("ecm");
- ret = -EINVAL;
- goto out;
- }
-
- if (config->ssp.mclk_id > 1) {
- trace_ssp_error("ecn");
- ret = -EINVAL;
- goto out;
- }
-
- /* divisor must be within SCR range */
- mdiv -= 1;
- if (mdiv > (SSCR0_SCR_MASK >> 8)) {
- trace_ssp_error("ec6");
- ret = -EINVAL;
- goto out;
- }
-
- /* set the SCR divisor */
- sscr0 |= SSCR0_SCR(mdiv);
-
- /* calc frame width based on BCLK and rate - must be divisable */
- if (config->ssp.bclk_rate % config->ssp.fsync_rate) {
- trace_ssp_error("ec7");
- ret = -EINVAL;
- goto out;
- }
-
- /* must be enough BCLKs for data */
- bdiv = config->ssp.bclk_rate / config->ssp.fsync_rate;
- if (bdiv < config->ssp.tdm_slot_width * config->ssp.tdm_slots) {
- trace_ssp_error("ec8");
- ret = -EINVAL;
- goto out;
- }
-
- /* tdm_slot_width must be <= 38 for SSP */
- if (config->ssp.tdm_slot_width > 38) {
- trace_ssp_error("ec9");
- ret = -EINVAL;
- goto out;
- }
-
- bdiv_min = config->ssp.tdm_slots * config->ssp.sample_valid_bits;
- if (bdiv < bdiv_min) {
- trace_ssp_error("ecc");
- ret = -EINVAL;
- goto out;
- }
-
- frame_end_padding = bdiv - bdiv_min;
- if (frame_end_padding > SSPSP2_FEP_MASK) {
- trace_ssp_error("ecd");
- ret = -EINVAL;
- goto out;
- }
-
- /* format */
- switch (config->format & SOF_DAI_FMT_FORMAT_MASK) {
- case SOF_DAI_FMT_I2S:
-
- start_delay = true;
-
- sscr0 |= SSCR0_FRDC(config->ssp.tdm_slots);
-
- if (bdiv % 2) {
- trace_ssp_error("eca");
- ret = -EINVAL;
- goto out;
- }
-
- /* set asserted frame length to half frame length */
- frame_len = bdiv / 2;
-
- /*
- * handle frame polarity, I2S default is falling/active low,
- * non-inverted(inverted_frame=0) -- active low(SFRMP=0),
- * inverted(inverted_frame=1) -- rising/active high(SFRMP=1),
- * so, we should set SFRMP to inverted_frame.
- */
- sspsp |= SSPSP_SFRMP(inverted_frame);
-
- /*
- * for I2S/LEFT_J, the padding has to happen at the end
- * of each slot
- */
- if (frame_end_padding % 2) {
- trace_ssp_error("ece");
- ret = -EINVAL;
- goto out;
- }
-
- slot_end_padding = frame_end_padding / 2;
-
- if (slot_end_padding > 15) {
- /* can't handle padding over 15 bits */
- trace_ssp_error("ecf");
- ret = -EINVAL;
- goto out;
- }
-
- sspsp |= SSPSP_DMYSTOP(slot_end_padding & SSPSP_DMYSTOP_MASK);
- slot_end_padding >>= SSPSP_DMYSTOP_BITS;
- sspsp |= SSPSP_EDMYSTOP(slot_end_padding & SSPSP_EDMYSTOP_MASK);
-
- break;
-
- case SOF_DAI_FMT_LEFT_J:
-
- /* default start_delay value is set to false */
-
- sscr0 |= SSCR0_FRDC(config->ssp.tdm_slots);
-
- /* LJDFD enable */
- sscr2 &= ~SSCR2_LJDFD;
-
- if (bdiv % 2) {
- trace_ssp_error("ecb");
- ret = -EINVAL;
- goto out;
- }
-
- /* set asserted frame length to half frame length */
- frame_len = bdiv / 2;
-
- /*
- * handle frame polarity, LEFT_J default is rising/active high,
- * non-inverted(inverted_frame=0) -- active high(SFRMP=1),
- * inverted(inverted_frame=1) -- falling/active low(SFRMP=0),
- * so, we should set SFRMP to !inverted_frame.
- */
- sspsp |= SSPSP_SFRMP(!inverted_frame);
-
- /*
- * for I2S/LEFT_J, the padding has to happen at the end
- * of each slot
- */
- if (frame_end_padding % 2) {
- trace_ssp_error("ecg");
- ret = -EINVAL;
- goto out;
- }
-
- slot_end_padding = frame_end_padding / 2;
-
- if (slot_end_padding > 15) {
- /* can't handle padding over 15 bits */
- trace_ssp_error("ech");
- ret = -EINVAL;
- goto out;
- }
-
- sspsp |= SSPSP_DMYSTOP(slot_end_padding & SSPSP_DMYSTOP_MASK);
- slot_end_padding >>= SSPSP_DMYSTOP_BITS;
- sspsp |= SSPSP_EDMYSTOP(slot_end_padding & SSPSP_EDMYSTOP_MASK);
-
- break;
- case SOF_DAI_FMT_DSP_A:
-
- start_delay = true;
-
- /* fallthrough */
-
- case SOF_DAI_FMT_DSP_B:
-
- /* default start_delay value is set to false */
-
- sscr0 |= SSCR0_MOD | SSCR0_FRDC(config->ssp.tdm_slots);
-
- /* set asserted frame length */
- frame_len = 1; /* default */
-
- if (cfs && ssp->params.frame_pulse_width > 0 &&
- ssp->params.frame_pulse_width <=
- SOF_DAI_INTEL_SSP_FRAME_PULSE_WIDTH_MAX) {
- frame_len = ssp->params.frame_pulse_width;
- }
-
- /* frame_pulse_width must less or equal 38 */
- if (ssp->params.frame_pulse_width >
- SOF_DAI_INTEL_SSP_FRAME_PULSE_WIDTH_MAX) {
- trace_ssp_error("efb");
- ret = -EINVAL;
- goto out;
- }
- /*
- * handle frame polarity, DSP_B default is rising/active high,
- * non-inverted(inverted_frame=0) -- active high(SFRMP=1),
- * inverted(inverted_frame=1) -- falling/active low(SFRMP=0),
- * so, we should set SFRMP to !inverted_frame.
- */
- sspsp |= SSPSP_SFRMP(!inverted_frame);
-
- active_tx_slots = hweight_32(config->ssp.tx_slots);
- active_rx_slots = hweight_32(config->ssp.rx_slots);
-
- /*
- * handle TDM mode, TDM mode has padding at the end of
- * each slot. The amount of padding is equal to result of
- * subtracting slot width and valid bits per slot.
- */
- if (ssp->params.tdm_per_slot_padding_flag) {
- frame_end_padding = bdiv - config->ssp.tdm_slots *
- config->ssp.tdm_slot_width;
-
- slot_end_padding = config->ssp.tdm_slot_width -
- config->ssp.sample_valid_bits;
-
- if (slot_end_padding >
- SOF_DAI_INTEL_SSP_SLOT_PADDING_MAX) {
- trace_ssp_error("esb");
- ret = -EINVAL;
- goto out;
- }
-
- sspsp |= SSPSP_DMYSTOP(slot_end_padding &
- SSPSP_DMYSTOP_MASK);
- slot_end_padding >>= SSPSP_DMYSTOP_BITS;
- sspsp |= SSPSP_EDMYSTOP(slot_end_padding &
- SSPSP_EDMYSTOP_MASK);
- }
-
- sspsp2 |= (frame_end_padding & SSPSP2_FEP_MASK);
-
- break;
- default:
- trace_ssp_error("eca");
- ret = -EINVAL;
- goto out;
- }
-
- if (start_delay)
- sspsp |= SSPSP_FSRT;
-
- sspsp |= SSPSP_SFRMWDTH(frame_len);
-
- data_size = config->ssp.sample_valid_bits;
-
- if (data_size > 16)
- sscr0 |= (SSCR0_EDSS | SSCR0_DSIZE(data_size - 16));
- else
- sscr0 |= SSCR0_DSIZE(data_size);
-
- /* setting TFT and RFT */
- switch (config->ssp.sample_valid_bits) {
- case 16:
- /* use 2 bytes for each slot */
- sample_width = 2;
- break;
- case 24:
- case 32:
- /* use 4 bytes for each slot */
- sample_width = 4;
- break;
- default:
- trace_ssp_error("ecd");
- ret = -EINVAL;
- goto out;
- }
-
- tft = MIN(SSP_FIFO_DEPTH - SSP_FIFO_WATERMARK,
- sample_width * active_tx_slots);
- rft = MIN(SSP_FIFO_DEPTH - SSP_FIFO_WATERMARK,
- sample_width * active_rx_slots);
-
- sscr3 |= SSCR3_TX(tft) | SSCR3_RX(rft);
-
- trace_ssp("coe");
- ssp_write(dai, SSCR0, sscr0);
- ssp_write(dai, SSCR1, sscr1);
- ssp_write(dai, SSCR2, sscr2);
- ssp_write(dai, SSCR3, sscr3);
- ssp_write(dai, SSPSP, sspsp);
- ssp_write(dai, SSPSP2, sspsp2);
- ssp_write(dai, SSIOC, ssioc);
- ssp_write(dai, SSTO, ssto);
- ssp_write(dai, SSTSA, sstsa);
- ssp_write(dai, SSRSA, ssrsa);
-
- trace_value(sscr0);
- trace_value(sscr1);
- trace_value(ssto);
- trace_value(sspsp);
- trace_value(sstsa);
- trace_value(ssrsa);
- trace_value(sscr2);
- trace_value(sspsp2);
- trace_value(sscr3);
- trace_value(ssioc);
-
- /* TODO: move this into M/N driver */
- mn_reg_write(0x0, mdivc);
- mn_reg_write(0x80 + config->ssp.mclk_id * 0x4, mdivr);
- mn_reg_write(0x100 + config->dai_index * 0x8 + 0x0, i2s_m);
- mn_reg_write(0x100 + config->dai_index * 0x8 + 0x4, i2s_n);
-
- ssp->state[DAI_DIR_PLAYBACK] = COMP_STATE_PREPARE;
- ssp->state[DAI_DIR_CAPTURE] = COMP_STATE_PREPARE;
-
-out:
- spin_unlock(&ssp->lock);
-
- return ret;
-}
-
-/* Digital Audio interface formatting */
-static inline int ssp_set_loopback_mode(struct dai *dai, uint32_t lbm)
-{
- struct ssp_pdata *ssp = dai_get_drvdata(dai);
-
- trace_ssp("loo");
- spin_lock(&ssp->lock);
-
- ssp_update_bits(dai, SSCR1, SSCR1_LBM, lbm ? SSCR1_LBM : 0);
-
- spin_unlock(&ssp->lock);
-
- return 0;
-}
-
-/* start the SSP for either playback or capture */
-static void ssp_start(struct dai *dai, int direction)
-{
- struct ssp_pdata *ssp = dai_get_drvdata(dai);
-
- spin_lock(&ssp->lock);
-
- /* enable port */
- ssp_update_bits(dai, SSCR0, SSCR0_SSE, SSCR0_SSE);
- ssp->state[direction] = COMP_STATE_ACTIVE;
-
- trace_ssp("sta");
-
- /* enable DMA */
- if (direction == DAI_DIR_PLAYBACK) {
- ssp_update_bits(dai, SSCR1, SSCR1_TSRE, SSCR1_TSRE);
- ssp_update_bits(dai, SSTSA, 0x1 << 8, 0x1 << 8);
- } else {
- ssp_update_bits(dai, SSCR1, SSCR1_RSRE, SSCR1_RSRE);
- ssp_update_bits(dai, SSRSA, 0x1 << 8, 0x1 << 8);
- }
-
- spin_unlock(&ssp->lock);
-}
-
-/* stop the SSP for either playback or capture */
-static void ssp_stop(struct dai *dai, int direction)
-{
- struct ssp_pdata *ssp = dai_get_drvdata(dai);
-
- spin_lock(&ssp->lock);
-
- /* stop Rx if neeed */
- if (direction == DAI_DIR_CAPTURE &&
- ssp->state[SOF_IPC_STREAM_CAPTURE] == COMP_STATE_ACTIVE) {
- ssp_update_bits(dai, SSCR1, SSCR1_RSRE, 0);
- ssp_update_bits(dai, SSRSA, 0x1 << 8, 0x0 << 8);
- ssp_empty_rx_fifo(dai);
- ssp->state[SOF_IPC_STREAM_CAPTURE] = COMP_STATE_PAUSED;
- trace_ssp("Ss0");
- }
-
- /* stop Tx if needed */
- if (direction == DAI_DIR_PLAYBACK &&
- ssp->state[SOF_IPC_STREAM_PLAYBACK] == COMP_STATE_ACTIVE) {
- ssp_update_bits(dai, SSCR1, SSCR1_TSRE, 0);
- ssp_update_bits(dai, SSTSA, 0x1 << 8, 0x0 << 8);
- ssp->state[SOF_IPC_STREAM_PLAYBACK] = COMP_STATE_PAUSED;
- trace_ssp("Ss1");
- }
-
- /* disable SSP port if no users */
- if (ssp->state[SOF_IPC_STREAM_CAPTURE] != COMP_STATE_ACTIVE &&
- ssp->state[SOF_IPC_STREAM_PLAYBACK] != COMP_STATE_ACTIVE) {
- ssp_update_bits(dai, SSCR0, SSCR0_SSE, 0);
- ssp->state[SOF_IPC_STREAM_CAPTURE] = COMP_STATE_PREPARE;
- ssp->state[SOF_IPC_STREAM_PLAYBACK] = COMP_STATE_PREPARE;
- trace_ssp("Ss2");
- }
-
- spin_unlock(&ssp->lock);
-}
-
-static int ssp_trigger(struct dai *dai, int cmd, int direction)
-{
- struct ssp_pdata *ssp = dai_get_drvdata(dai);
-
- trace_ssp("tri");
-
- switch (cmd) {
- case COMP_TRIGGER_START:
- if (ssp->state[direction] == COMP_STATE_PREPARE ||
- ssp->state[direction] == COMP_STATE_PAUSED)
- ssp_start(dai, direction);
- break;
- case COMP_TRIGGER_RELEASE:
- if (ssp->state[direction] == COMP_STATE_PAUSED ||
- ssp->state[direction] == COMP_STATE_PREPARE)
- ssp_start(dai, direction);
- break;
- case COMP_TRIGGER_STOP:
- case COMP_TRIGGER_PAUSE:
- ssp_stop(dai, direction);
- break;
- case COMP_TRIGGER_RESUME:
- ssp_context_restore(dai);
- break;
- case COMP_TRIGGER_SUSPEND:
- ssp_context_store(dai);
- break;
- default:
- break;
- }
-
- return 0;
-}
-
-/* clear IRQ sources atm */
-static void ssp_irq_handler(void *data)
-{
- struct dai *dai = data;
-
- trace_ssp("irq");
- trace_value(ssp_read(dai, SSSR));
-
- /* clear IRQ */
- ssp_write(dai, SSSR, ssp_read(dai, SSSR));
- platform_interrupt_clear(ssp_irq(dai), 1);
-}
-
-static int ssp_probe(struct dai *dai)
-{
- struct ssp_pdata *ssp;
-
- /* allocate private data */
- ssp = rzalloc(RZONE_SYS, SOF_MEM_CAPS_RAM, sizeof(*ssp));
- dai_set_drvdata(dai, ssp);
-
- spinlock_init(&ssp->lock);
-
- ssp->state[DAI_DIR_PLAYBACK] = COMP_STATE_READY;
- ssp->state[DAI_DIR_CAPTURE] = COMP_STATE_READY;
-
- /* register our IRQ handler */
- interrupt_register(ssp_irq(dai), ssp_irq_handler, dai);
- platform_interrupt_unmask(ssp_irq(dai), 1);
- interrupt_enable(ssp_irq(dai));
-
- ssp_empty_rx_fifo(dai);
-
- return 0;
-}
-
-const struct dai_ops ssp_ops = {
- .trigger = ssp_trigger,
- .set_config = ssp_set_config,
- .pm_context_store = ssp_context_store,
- .pm_context_restore = ssp_context_restore,
- .probe = ssp_probe,
- .set_loopback_mode = ssp_set_loopback_mode,
-};
diff --git a/src/drivers/byt-ssp.c b/src/drivers/byt-ssp.c
deleted file mode 100644
index 4759d29..0000000
--- a/src/drivers/byt-ssp.c
+++ /dev/null
@@ -1,639 +0,0 @@
-/*
- * Copyright (c) 2016, Intel Corporation
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- * * Redistributions of source code must retain the above copyright
- * notice, this list of conditions and the following disclaimer.
- * * Redistributions in binary form must reproduce the above copyright
- * notice, this list of conditions and the following disclaimer in the
- * documentation and/or other materials provided with the distribution.
- * * Neither the name of the Intel Corporation nor the
- * names of its contributors may be used to endorse or promote products
- * derived from this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
- * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
- * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
- * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
- * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
- * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
- * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
- * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
- * POSSIBILITY OF SUCH DAMAGE.
- *
- * Author: Liam Girdwood <liam.r.girdwood@linux.intel.com>
- * Keyon Jie <yang.jie@linux.intel.com>
- */
-
-#include <errno.h>
-#include <stdbool.h>
-#include <sof/stream.h>
-#include <sof/ssp.h>
-#include <sof/alloc.h>
-#include <sof/interrupt.h>
-
-/* tracing */
-#define trace_ssp(__e) trace_event(TRACE_CLASS_SSP, __e)
-#define trace_ssp_error(__e) trace_error(TRACE_CLASS_SSP, __e)
-#define tracev_ssp(__e) tracev_event(TRACE_CLASS_SSP, __e)
-
-/* FIXME: move this to a helper and optimize */
-static int hweight_32(uint32_t mask)
-{
- int i;
- int count = 0;
-
- for (i = 0; i < 32; i++) {
- count += mask&1;
- mask >>= 1;
- }
- return count;
-}
-
-/* empty SSP receive FIFO */
-static void ssp_empty_rx_fifo(struct dai *dai)
-{
- struct ssp_pdata *ssp = dai_get_drvdata(dai);
- uint32_t sssr;
- uint32_t entries;
- uint32_t i;
-
- spin_lock(&ssp->lock);
-
- sssr = ssp_read(dai, SSSR);
-
- /* clear interrupt */
- if (sssr & SSSR_ROR)
- ssp_write(dai, SSSR, sssr);
-
- /* empty fifo */
- if (sssr & SSSR_RNE) {
- entries = SFIFOL_RFL(ssp_read(dai, SFIFOL));
- for (i = 0; i < entries + 1; i++)
- ssp_read(dai, SSDR);
- }
-
- spin_unlock(&ssp->lock);
-}
-
-/* save SSP context prior to entering D3 */
-static int ssp_context_store(struct dai *dai)
-{
- struct ssp_pdata *ssp = dai_get_drvdata(dai);
-
- ssp->sscr0 = ssp_read(dai, SSCR0);
- ssp->sscr1 = ssp_read(dai, SSCR1);
-
- /* FIXME: need to store sscr2,3,4,5 */
- ssp->psp = ssp_read(dai, SSPSP);
-
- return 0;
-}
-
-/* restore SSP context after leaving D3 */
-static int ssp_context_restore(struct dai *dai)
-{
- struct ssp_pdata *ssp = dai_get_drvdata(dai);
-
- ssp_write(dai, SSCR0, ssp->sscr0);
- ssp_write(dai, SSCR1, ssp->sscr1);
- /* FIXME: need to restore sscr2,3,4,5 */
- ssp_write(dai, SSPSP, ssp->psp);
-
- return 0;
-}
-
-/* Digital Audio interface formatting */
-static inline int ssp_set_config(struct dai *dai,
- struct sof_ipc_dai_config *config)
-{
- struct ssp_pdata *ssp = dai_get_drvdata(dai);
- uint32_t sscr0;
- uint32_t sscr1;
- uint32_t sscr2;
- uint32_t sscr3;
- uint32_t sscr4;
- uint32_t sscr5;
- uint32_t sspsp;
- uint32_t sfifott;
- uint32_t mdiv;
- uint32_t bdiv;
- uint32_t data_size;
- uint32_t start_delay;
- uint32_t active_tx_slots = 2;
- uint32_t active_rx_slots = 2;
- uint32_t frame_len = 0;
- bool inverted_frame = false;
- bool cfs = false;
- bool cbs = false;
- int ret = 0;
-
- spin_lock(&ssp->lock);
-
- /* is playback/capture already running */
- if (ssp->state[DAI_DIR_PLAYBACK] == COMP_STATE_ACTIVE ||
- ssp->state[DAI_DIR_CAPTURE] == COMP_STATE_ACTIVE) {
- trace_ssp_error("ec1");
- ret = -EINVAL;
- goto out;
- }
-
- trace_ssp("cos");
- trace_value(config->format);
-
- /* reset SSP settings */
- /* sscr0 dynamic settings are DSS, EDSS, SCR, FRDC, ECS */
- /*
- * FIXME: MOD, ACS, NCS are not set,
- * no support for network mode for now
- */
- sscr0 = SSCR0_PSP | SSCR0_RIM | SSCR0_TIM;
-
- /*
- * FIXME: PINTE and RWOT are not set in sscr1
- * sscr1 = SSCR1_PINTE | SSCR1_RWOT;
- */
-
- /* sscr1 dynamic settings are TFT, RFT, SFRMDIR, SCLKDIR, SCFR */
- sscr1 = 0;
-#ifdef ENABLE_SSCR1_TRISTATE
- sscr1 |= SSCR1_TTE; /* make sure SDO line is tri-stated when inactive */
-#endif
-#ifdef ENABLE_TIE_RIE /* FIXME: not enabled, difference with SST driver */
- sscr1 |= SSCR1_TIE | SSCR1_RIE;
-#endif
-
- /* sscr2 dynamic setting is SLV_EXT_CLK_RUN_EN */
- sscr2 = SSCR2_URUN_FIX0;
- sscr2 |= SSCR2_ASRC_INTR_MASK;
-#ifdef ENABLE_SSCR2_FIXES /* FIXME: is this needed ? */
- sscr2 |= SSCR2_UNDRN_FIX_EN | SSCR2_FIFO_EMPTY_FIX_EN;
-#endif
-
-
- /*
- * sscr3 dynamic settings are FRM_MS_EN, I2S_MODE_EN, I2S_FRM_POL,
- * I2S_TX_EN, I2S_RX_EN, I2S_CLK_MST
- */
- sscr3 = SSCR3_SYN_FIX_EN;
-#ifdef ENABLE_SSRC3_FIXES
- /*
- * this seems to prevent DSP modes from working but is harmless for
- * I2S and LEFT_J. Keep with ifdef in case it's ever needed.
- */
- sscr3 |= SSCR3_I2S_TX_SS_FIX_EN | SSCR3_I2S_RX_SS_FIX_EN |
- SSCR3_STRETCH_TX | SSCR3_STRETCH_RX;
-#endif
-
-#ifdef ENABLE_CLK_EDGE_SEL /* FIXME: is this needed ? */
- sscr3 |= SSCR3_CLK_EDGE_SEL;
-#endif
-
- /* sscr4 dynamic settings is TOT_FRAME_PRD */
- sscr4 = 0x0;
-
- /* sscr4 dynamic settings are FRM_ASRT_CLOCKS and FRM_POLARITY */
- sscr5 = 0x0;
-
- /* sspsp dynamic settings are SCMODE, SFRMP, DMYSTRT, SFRMWDTH */
- sspsp = SSPSP_ETDS; /* last value (bit 0) */
-
- ssp->config = *config;
- ssp->params = config->ssp;
-
- /* clock masters */
- /*
- * On TNG/BYT/CHT, the SSP wrapper generates the fs even in master mode,
- * the master/slave choice depends on the clock type
- */
- sscr1 |= SSCR1_SFRMDIR;
-
- switch (config->format & SOF_DAI_FMT_MASTER_MASK) {
- case SOF_DAI_FMT_CBM_CFM:
- sscr0 |= SSCR0_ECS; /* external clock used */
- sscr1 |= SSCR1_SCLKDIR;
- /*
- * FIXME: does SSRC1.SCFR need to be set
- * when codec is master ?
- */
- sscr2 |= SSCR2_SLV_EXT_CLK_RUN_EN;
- break;
- case SOF_DAI_FMT_CBS_CFS:
-#ifdef ENABLE_SSRCR1_SCFR /* FIXME: is this needed ? */
- sscr1 |= SSCR1_SCFR;
-#endif
- sscr3 |= SSCR3_FRM_MST_EN;
- cfs = true;
- cbs = true;
- break;
- case SOF_DAI_FMT_CBM_CFS:
- sscr0 |= SSCR0_ECS; /* external clock used */
- sscr1 |= SSCR1_SCLKDIR;
- /*
- * FIXME: does SSRC1.SCFR need to be set
- * when codec is master ?
- */
- sscr2 |= SSCR2_SLV_EXT_CLK_RUN_EN;
- sscr3 |= SSCR3_FRM_MST_EN;
- cfs = true;
- /* FIXME: this mode has not been tested */
- break;
- case SOF_DAI_FMT_CBS_CFM:
-#ifdef ENABLE_SSRCR1_SCFR /* FIXME: is this needed ? */
- sscr1 |= SSCR1_SCFR;
-#endif
- /* FIXME: this mode has not been tested */
- cbs = true;
- break;
- default:
- trace_ssp_error("ec2");
- ret = -EINVAL;
- goto out;
- }
-
- /* clock signal polarity */
- switch (config->format & SOF_DAI_FMT_INV_MASK) {
- case SOF_DAI_FMT_NB_NF:
- break;
- case SOF_DAI_FMT_NB_IF:
- inverted_frame = true; /* handled later with format */
- break;
- case SOF_DAI_FMT_IB_IF:
- sspsp |= SSPSP_SCMODE(2);
- inverted_frame = true; /* handled later with format */
- break;
- case SOF_DAI_FMT_IB_NF:
- sspsp |= SSPSP_SCMODE(2);
- break;
- default:
- trace_ssp_error("ec3");
- ret = -EINVAL;
- goto out;
- }
-
- /* BCLK is generated from MCLK - must be divisable */
- if (config->ssp.mclk_rate % config->ssp.bclk_rate) {
- trace_ssp_error("ec5");
- ret = -EINVAL;
- goto out;
- }
-
- /* divisor must be within SCR range */
- mdiv = (config->ssp.mclk_rate / config->ssp.bclk_rate) - 1;
- if (mdiv > (SSCR0_SCR_MASK >> 8)) {
- trace_ssp_error("ec6");
- ret = -EINVAL;
- goto out;
- }
-
- /* set the SCR divisor */
- sscr0 |= SSCR0_SCR(mdiv);
-
- /* calc frame width based on BCLK and rate - must be divisable */
- if (config->ssp.bclk_rate % config->ssp.fsync_rate) {
- trace_ssp_error("ec7");
- ret = -EINVAL;
- goto out;
- }
-
- /* must be enouch BCLKs for data */
- bdiv = config->ssp.bclk_rate / config->ssp.fsync_rate;
- if (bdiv < config->ssp.tdm_slot_width *
- config->ssp.tdm_slots) {
- trace_ssp_error("ec8");
- ret = -EINVAL;
- goto out;
- }
-
- /* tdm_slot_width must be <= 38 for SSP */
- if (config->ssp.tdm_slot_width > 38) {
- trace_ssp_error("ec9");
- ret = -EINVAL;
- goto out;
- }
-
- /* format */
- switch (config->format & SOF_DAI_FMT_FORMAT_MASK) {
- case SOF_DAI_FMT_I2S:
-
- start_delay = 1;
-
- /* enable I2S mode */
- sscr3 |= SSCR3_I2S_MODE_EN | SSCR3_I2S_TX_EN | SSCR3_I2S_RX_EN;
-
- /* set asserted frame length */
- frame_len = config->ssp.tdm_slot_width;
-
- /* handle frame polarity, I2S default is falling/active low */
- sspsp |= SSPSP_SFRMP(!inverted_frame);
- sscr3 |= SSCR3_I2S_FRM_POL(!inverted_frame);
-
- if (cbs) {
- /*
- * keep RX functioning on a TX underflow
- * (I2S/LEFT_J master only)
- */
- sscr3 |= SSCR3_MST_CLK_EN;
-
- /*
- * total frame period (both asserted and
- * deasserted time of frame
- */
- sscr4 |= SSCR4_TOT_FRM_PRD(frame_len << 1);
- }
-
- break;
-
- case SOF_DAI_FMT_LEFT_J:
-
- start_delay = 0;
-
- /* apparently we need the same initialization as for I2S */
- sscr3 |= SSCR3_I2S_MODE_EN | SSCR3_I2S_TX_EN | SSCR3_I2S_RX_EN;
-
- /* set asserted frame length */
- frame_len = config->ssp.tdm_slot_width;
-
- /* LEFT_J default is rising/active high, opposite of I2S */
- sspsp |= SSPSP_SFRMP(inverted_frame);
- sscr3 |= SSCR3_I2S_FRM_POL(inverted_frame);
-
- if (cbs) {
- /*
- * keep RX functioning on a TX underflow
- * (I2S/LEFT_J master only)
- */
- sscr3 |= SSCR3_MST_CLK_EN;
-
- /*
- * total frame period (both asserted and
- * deasserted time of frame
- */
- sscr4 |= SSCR4_TOT_FRM_PRD(frame_len << 1);
- }
-
- break;
- case SOF_DAI_FMT_DSP_A:
-
- start_delay = 1;
-
- sscr0 |= SSCR0_MOD | SSCR0_FRDC(config->ssp.tdm_slots);
-
- /* set asserted frame length */
- frame_len = 1;
-
- /* handle frame polarity, DSP_A default is rising/active high */
- sspsp |= SSPSP_SFRMP(!inverted_frame);
- if (cfs) {
- /* set sscr frame polarity in DSP/master mode only */
- sscr5 |= SSCR5_FRM_POLARITY(inverted_frame);
- }
-
- /*
- * total frame period (both asserted and
- * deasserted time of frame)
- */
- if (cbs)
- sscr4 |= SSCR4_TOT_FRM_PRD(config->ssp.tdm_slots *
- config->ssp.tdm_slot_width);
-
- active_tx_slots = hweight_32(config->ssp.tx_slots);
- active_rx_slots = hweight_32(config->ssp.rx_slots);
-
- break;
- case SOF_DAI_FMT_DSP_B:
-
- start_delay = 0;
-
- sscr0 |= SSCR0_MOD | SSCR0_FRDC(config->ssp.tdm_slots);
-
- /* set asserted frame length */
- frame_len = 1;
-
- /* handle frame polarity, DSP_A default is rising/active high */
- sspsp |= SSPSP_SFRMP(!inverted_frame);
- if (cfs) {
- /* set sscr frame polarity in DSP/master mode only */
- sscr5 |= SSCR5_FRM_POLARITY(inverted_frame);
- }
-
- /*
- * total frame period (both asserted and
- * deasserted time of frame
- */
- if (cbs)
- sscr4 |= SSCR4_TOT_FRM_PRD(config->ssp.tdm_slots *
- config->ssp.tdm_slot_width);
-
- active_tx_slots = hweight_32(config->ssp.tx_slots);
- active_rx_slots = hweight_32(config->ssp.rx_slots);
-
- break;
- default:
- trace_ssp_error("eca");
- ret = -EINVAL;
- goto out;
- }
-
- sspsp |= SSPSP_DMYSTRT(start_delay);
- sspsp |= SSPSP_SFRMWDTH(frame_len);
- sscr5 |= SSCR5_FRM_ASRT_CLOCKS(frame_len);
-
- data_size = config->ssp.sample_valid_bits;
-
- if (data_size > 16)
- sscr0 |= (SSCR0_EDSS | SSCR0_DSIZE(data_size - 16));
- else
- sscr0 |= SSCR0_DSIZE(data_size);
-
- /* FIXME:
- * watermarks - (RFT + 1) should equal DMA SRC_MSIZE
- */
- sfifott = (SFIFOTT_TX(2*active_tx_slots) |
- SFIFOTT_RX(2*active_rx_slots));
-
- trace_ssp("coe");
-
- ssp_write(dai, SSCR0, sscr0);
- ssp_write(dai, SSCR1, sscr1);
- ssp_write(dai, SSCR2, sscr2);
- ssp_write(dai, SSCR3, sscr3);
- ssp_write(dai, SSCR4, sscr4);
- ssp_write(dai, SSCR5, sscr5);
- ssp_write(dai, SSPSP, sspsp);
- ssp_write(dai, SFIFOTT, sfifott);
- ssp_write(dai, SSTSA, config->ssp.tx_slots);
- ssp_write(dai, SSRSA, config->ssp.rx_slots);
-
- ssp->state[DAI_DIR_PLAYBACK] = COMP_STATE_PREPARE;
- ssp->state[DAI_DIR_CAPTURE] = COMP_STATE_PREPARE;
-
-out:
- spin_unlock(&ssp->lock);
-
- return ret;
-}
-
-/* Digital Audio interface formatting */
-static inline int ssp_set_loopback_mode(struct dai *dai, uint32_t lbm)
-{
- struct ssp_pdata *ssp = dai_get_drvdata(dai);
-
- trace_ssp("loo");
- spin_lock(&ssp->lock);
-
- ssp_update_bits(dai, SSCR1, SSCR1_LBM, lbm ? SSCR1_LBM : 0);
-
- spin_unlock(&ssp->lock);
-
- return 0;
-}
-
-/* start the SSP for either playback or capture */
-static void ssp_start(struct dai *dai, int direction)
-{
- struct ssp_pdata *ssp = dai_get_drvdata(dai);
-
- spin_lock(&ssp->lock);
-
- /* enable port */
- ssp_update_bits(dai, SSCR0, SSCR0_SSE, SSCR0_SSE);
- ssp->state[direction] = COMP_STATE_ACTIVE;
-
- trace_ssp("sta");
-
- /* enable DMA */
- if (direction == DAI_DIR_PLAYBACK)
- ssp_update_bits(dai, SSCR1, SSCR1_TSRE, SSCR1_TSRE);
- else
- ssp_update_bits(dai, SSCR1, SSCR1_RSRE, SSCR1_RSRE);
-
- spin_unlock(&ssp->lock);
-}
-
-/* stop the SSP for either playback or capture */
-static void ssp_stop(struct dai *dai, int direction)
-{
- struct ssp_pdata *ssp = dai_get_drvdata(dai);
-
- spin_lock(&ssp->lock);
-
- /* stop Rx if neeed */
- if (direction == DAI_DIR_CAPTURE &&
- ssp->state[SOF_IPC_STREAM_CAPTURE] == COMP_STATE_ACTIVE) {
- ssp_update_bits(dai, SSCR1, SSCR1_RSRE, 0);
- ssp_empty_rx_fifo(dai);
- ssp->state[SOF_IPC_STREAM_CAPTURE] = COMP_STATE_PAUSED;
- trace_ssp("Ss0");
- }
-
- /* stop Tx if needed */
- if (direction == DAI_DIR_PLAYBACK &&
- ssp->state[SOF_IPC_STREAM_PLAYBACK] == COMP_STATE_ACTIVE) {
- ssp_update_bits(dai, SSCR1, SSCR1_TSRE, 0);
- ssp->state[SOF_IPC_STREAM_PLAYBACK] = COMP_STATE_PAUSED;
- trace_ssp("Ss1");
- }
-
- /* disable SSP port if no users */
- if (ssp->state[SOF_IPC_STREAM_CAPTURE] != COMP_STATE_ACTIVE &&
- ssp->state[SOF_IPC_STREAM_PLAYBACK] != COMP_STATE_ACTIVE) {
- ssp_update_bits(dai, SSCR0, SSCR0_SSE, 0);
- ssp->state[SOF_IPC_STREAM_CAPTURE] = COMP_STATE_PREPARE;
- ssp->state[SOF_IPC_STREAM_PLAYBACK] = COMP_STATE_PREPARE;
- trace_ssp("Ss2");
- }
-
- spin_unlock(&ssp->lock);
-}
-
-static int ssp_trigger(struct dai *dai, int cmd, int direction)
-{
- struct ssp_pdata *ssp = dai_get_drvdata(dai);
-
- trace_ssp("tri");
-
- switch (cmd) {
- case COMP_TRIGGER_START:
- if (ssp->state[direction] == COMP_STATE_PREPARE ||
- ssp->state[direction] == COMP_STATE_PAUSED)
- ssp_start(dai, direction);
- break;
- case COMP_TRIGGER_RELEASE:
- if (ssp->state[direction] == COMP_STATE_PAUSED ||
- ssp->state[direction] == COMP_STATE_PREPARE)
- ssp_start(dai, direction);
- break;
- case COMP_TRIGGER_STOP:
- case COMP_TRIGGER_PAUSE:
- ssp_stop(dai, direction);
- break;
- case COMP_TRIGGER_RESUME:
- ssp_context_restore(dai);
- break;
- case COMP_TRIGGER_SUSPEND:
- ssp_context_store(dai);
- break;
- default:
- break;
- }
-
- return 0;
-}
-
-/* clear IRQ sources atm */
-static void ssp_irq_handler(void *data)
-{
- struct dai *dai = data;
-
- trace_ssp("irq");
- trace_value(ssp_read(dai, SSSR));
-
- /* clear IRQ */
- ssp_write(dai, SSSR, ssp_read(dai, SSSR));
- platform_interrupt_clear(ssp_irq(dai), 1);
-}
-
-static int ssp_probe(struct dai *dai)
-{
- struct ssp_pdata *ssp;
-
- /* allocate private data */
- ssp = rzalloc(RZONE_SYS, SOF_MEM_CAPS_RAM, sizeof(*ssp));
- dai_set_drvdata(dai, ssp);
-
- spinlock_init(&ssp->lock);
-
- ssp->state[DAI_DIR_PLAYBACK] = COMP_STATE_READY;
- ssp->state[DAI_DIR_CAPTURE] = COMP_STATE_READY;
-
-#if defined CONFIG_CHERRYTRAIL
- /* register our IRQ handler - CHT shares SSP 0,1,2 IRQs with SSP 3,4,5 */
- if (ssp_irq(dai) >= IRQ_CHT_SSP_OFFSET)
- interrupt_register(ssp_irq(dai) - IRQ_CHT_SSP_OFFSET,
- ssp_irq_handler, dai);
- else
- interrupt_register(ssp_irq(dai), ssp_irq_handler, dai);
-#else
- /* register our IRQ handler */
- interrupt_register(ssp_irq(dai), ssp_irq_handler, dai);
-#endif
- platform_interrupt_unmask(ssp_irq(dai), 1);
- interrupt_enable(ssp_irq(dai));
-
- ssp_empty_rx_fifo(dai);
- return 0;
-}
-
-const struct dai_ops ssp_ops = {
- .trigger = ssp_trigger,
- .set_config = ssp_set_config,
- .pm_context_store = ssp_context_store,
- .pm_context_restore = ssp_context_restore,
- .probe = ssp_probe,
- .set_loopback_mode = ssp_set_loopback_mode,
-};
diff --git a/src/drivers/cavs-hda.c b/src/drivers/cavs-hda.c
deleted file mode 100644
index e61e832..0000000
--- a/src/drivers/cavs-hda.c
+++ /dev/null
@@ -1,62 +0,0 @@
-/*
- * Copyright (c) 2018, Intel Corporation
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- * * Redistributions of source code must retain the above copyright
- * notice, this list of conditions and the following disclaimer.
- * * Redistributions in binary form must reproduce the above copyright
- * notice, this list of conditions and the following disclaimer in the
- * documentation and/or other materials provided with the distribution.
- * * Neither the name of the Intel Corporation nor the
- * names of its contributors may be used to endorse or promote products
- * derived from this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
- * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
- * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
- * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
- * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
- * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
- * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
- * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
- * POSSIBILITY OF SUCH DAMAGE.
- *
- * Author: Marcin Maka <marcin.maka@linux.intel.com
- */
-
-#include <errno.h>
-#include <sof/dai.h>
-
-static int hda_trigger(struct dai *dai, int cmd, int direction)
-{
- return 0;
-}
-
-static int hda_set_config(struct dai *dai,
- struct sof_ipc_dai_config *config)
-{
- return 0;
-}
-
-static int hda_dummy(struct dai *dai)
-{
- return 0;
-}
-
-static int hda_set_loopback_mode(struct dai *dai, uint32_t lbm)
-{
- return -EINVAL;
-}
-
-const struct dai_ops hda_ops = {
- .trigger = hda_trigger,
- .set_config = hda_set_config,
- .pm_context_store = hda_dummy,
- .pm_context_restore = hda_dummy,
- .probe = hda_dummy,
- .set_loopback_mode = hda_set_loopback_mode
-};
diff --git a/src/drivers/dmic.c b/src/drivers/dmic.c
deleted file mode 100644
index 69ee2fd..0000000
--- a/src/drivers/dmic.c
+++ /dev/null
@@ -1,1478 +0,0 @@
-/*
- * Copyright (c) 2017, Intel Corporation
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- * * Redistributions of source code must retain the above copyright
- * notice, this list of conditions and the following disclaimer.
- * * Redistributions in binary form must reproduce the above copyright
- * notice, this list of conditions and the following disclaimer in the
- * documentation and/or other materials provided with the distribution.
- * * Neither the name of the Intel Corporation nor the
- * names of its contributors may be used to endorse or promote products
- * derived from this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
- * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
- * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
- * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
- * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
- * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
- * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
- * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
- * POSSIBILITY OF SUCH DAMAGE.
- *
- * Author: Seppo Ingalsuo <seppo.ingalsuo@linux.intel.com>
- */
-
-#include <sof/stream.h>
-#include <sof/dmic.h>
-#include <sof/interrupt.h>
-#include <sof/math/numbers.h>
-#include <sof/audio/format.h>
-
-#if defined DMIC_HW_VERSION
-
-#include <sof/audio/coefficients/pdm_decim/pdm_decim_table.h>
-
-#if defined MODULE_TEST
-#include <stdio.h>
-#endif
-
-#define DMIC_MAX_MODES 50
-
-/* HW FIR pipeline needs 5 additional cycles per channel for internal
- * operations. This is used in MAX filter length check.
- */
-#define DMIC_FIR_PIPELINE_OVERHEAD 5
-
-struct decim_modes {
- int16_t clkdiv[DMIC_MAX_MODES];
- int16_t mcic[DMIC_MAX_MODES];
- int16_t mfir[DMIC_MAX_MODES];
- int num_of_modes;
-};
-
-struct matched_modes {
- int16_t clkdiv[DMIC_MAX_MODES];
- int16_t mcic[DMIC_MAX_MODES];
- int16_t mfir_a[DMIC_MAX_MODES];
- int16_t mfir_b[DMIC_MAX_MODES];
- int num_of_modes;
-};
-
-struct dmic_configuration {
- struct pdm_decim *fir_a;
- struct pdm_decim *fir_b;
- int clkdiv;
- int mcic;
- int mfir_a;
- int mfir_b;
- int cic_shift;
- int fir_a_shift;
- int fir_b_shift;
- int fir_a_length;
- int fir_b_length;
- int32_t fir_a_scale;
- int32_t fir_b_scale;
-};
-
-struct pdm_controllers_configuration {
- uint32_t cic_control;
- uint32_t cic_config;
- uint32_t mic_control;
- uint32_t fir_control_a;
- uint32_t fir_config_a;
- uint32_t dc_offset_left_a;
- uint32_t dc_offset_right_a;
- uint32_t out_gain_left_a;
- uint32_t out_gain_right_a;
- uint32_t fir_control_b;
- uint32_t fir_config_b;
- uint32_t dc_offset_left_b;
- uint32_t dc_offset_right_b;
- uint32_t out_gain_left_b;
- uint32_t out_gain_right_b;
-};
-
-/* Configuration ABI version, increment if not compatible with previous
- * version.
- */
-#define DMIC_IPC_VERSION 1
-
-/* Minimum OSR is always applied for 48 kHz and less sample rates */
-#define DMIC_MIN_OSR 50
-
-/* These are used as guideline for configuring > 48 kHz sample rates. The
- * minimum OSR can be relaxed down to 40 (use 3.84 MHz clock for 96 kHz).
- */
-#define DMIC_HIGH_RATE_MIN_FS 64000
-#define DMIC_HIGH_RATE_OSR_MIN 40
-
-/* Used for scaling FIR coeffcients for HW */
-#define DMIC_HW_FIR_COEF_MAX ((1 << (DMIC_HW_BITS_FIR_COEF - 1)) - 1)
-#define DMIC_HW_FIR_COEF_Q (DMIC_HW_BITS_FIR_COEF - 1)
-
-/* Internal precision in gains computation, e.g. Q4.28 in int32_t */
-#define DMIC_FIR_SCALE_Q 28
-
-/* Used in unmute ramp values calculation */
-#define DMIC_HW_FIR_GAIN_MAX ((1 << (DMIC_HW_BITS_FIR_GAIN - 1)) - 1)
-
-/* Hardwired log ramp parameters. The first value is the initial logarithmic
- * gain and the second value is the multiplier for gain to achieve the linear
- * decibels change over time. Currently the coefficient GM needs to be
- * calculated manually. The 300 ms ramp should ensure clean sounding start with
- * any microphone. However it is likely unnecessarily long for machine hearing.
- * TODO: Add ramp characteristic passing via topology.
- */
-#define LOGRAMP_GI 33954 /* -90 dB, Q2.30*/
-#define LOGRAMP_GM 16959 /* Gives 300 ms ramp for -90..0 dB, Q2.14 */
-
-/* tracing */
-#define trace_dmic(__e) trace_event(TRACE_CLASS_DMIC, __e)
-#define trace_dmic_error(__e) trace_error(TRACE_CLASS_DMIC, __e)
-#define tracev_dmic(__e) tracev_event(TRACE_CLASS_DMIC, __e)
-
-/* Base addresses (in PDM scope) of 2ch PDM controllers and coefficient RAM. */
-static const uint32_t base[4] = {PDM0, PDM1, PDM2, PDM3};
-static const uint32_t coef_base_a[4] = {PDM0_COEFFICIENT_A, PDM1_COEFFICIENT_A,
- PDM2_COEFFICIENT_A, PDM3_COEFFICIENT_A};
-static const uint32_t coef_base_b[4] = {PDM0_COEFFICIENT_B, PDM1_COEFFICIENT_B,
- PDM2_COEFFICIENT_B, PDM3_COEFFICIENT_B};
-
-#if defined MODULE_TEST
-#define IO_BYTES_GLOBAL (PDM0 - OUTCONTROL0)
-#define IO_BYTES_MIDDLE (PDM1 - PDM0)
-#define IO_BYTES_LAST (PDM0_COEFFICIENT_B + PDM_COEF_RAM_B_LENGTH - PDM0)
-#define IO_BYTES (((DMIC_HW_CONTROLLERS) - 1) * (IO_BYTES_MIDDLE) \
- + (IO_BYTES_LAST) + (IO_BYTES_GLOBAL))
-#define IO_LENGTH ((IO_BYTES) >> 2)
-
-static uint32_t dmic_io[IO_LENGTH];
-
-static void dmic_write(struct dai *dai, uint32_t reg, uint32_t value)
-{
- printf("W %04x %08x\n", reg, value);
- dmic_io[reg >> 2] = value;
-}
-
-static uint32_t dmic_read(struct dai *dai, uint32_t reg)
-{
- uint32_t value = dmic_io[reg >> 2];
-
- printf("R %04x %08x\n", reg, value);
- return value;
-}
-
-static void dmic_update_bits(struct dai *dai, uint32_t reg, uint32_t mask,
- uint32_t value)
-{
- uint32_t new_value;
- uint32_t old_value = dmic_io[reg >> 2];
-
- new_value = (old_value & (~mask)) | value;
- dmic_io[reg >> 2] = new_value;
- printf("W %04x %08x\n", reg, new_value);
-}
-#else
-
-static void dmic_write(struct dai *dai, uint32_t reg, uint32_t value)
-{
- io_reg_write(dai_base(dai) + reg, value);
-}
-
-static uint32_t dmic_read(struct dai *dai, uint32_t reg)
-{
- return io_reg_read(dai_base(dai) + reg);
-}
-
-static void dmic_update_bits(struct dai *dai, uint32_t reg, uint32_t mask,
- uint32_t value)
-{
- io_reg_update_bits(dai_base(dai) + reg, mask, value);
-}
-#endif
-
-/* this ramps volume changes over time */
-static uint64_t dmic_work(void *data, uint64_t delay)
-{
- struct dai *dai = (struct dai *)data;
- struct dmic_pdata *dmic = dai_get_drvdata(dai);
- int32_t gval;
- uint32_t val;
- int i;
-
- tracev_dmic("wrk");
- spin_lock(&dmic->lock);
-
- /* Increment gain with logaritmic step.
- * Gain is Q2.30 and gain modifier is Q2.14.
- */
- dmic->startcount++;
- dmic->gain = Q_MULTSR_32X32((int64_t)dmic->gain,
- LOGRAMP_GM, 30, 14, 30);
-
- /* Gain is stored as Q2.30, while HW register is Q1.19 so shift
- * the value right by 11.
- */
- gval = dmic->gain >> 11;
-
- /* Note that DMIC gain value zero has a special purpose. Value zero
- * sets gain bypass mode in HW. Zero value will be applied after ramp
- * is complete. It is because exact 1.0 gain is not possible with Q1.19.
- */
- if (gval > DMIC_HW_FIR_GAIN_MAX)
- gval = 0;
-
- /* Write gain to registers */
- for (i = 0; i < DMIC_HW_CONTROLLERS; i++) {
- if (!dmic->enable[i])
- continue;
-
- if (dmic->startcount == DMIC_UNMUTE_CIC)
- dmic_update_bits(dai, base[i] + CIC_CONTROL,
- CIC_CONTROL_MIC_MUTE_BIT, 0);
-
- if (dmic->startcount == DMIC_UNMUTE_FIR) {
- if (dmic->fifo_a)
- dmic_update_bits(dai, base[i] + FIR_CONTROL_A,
- FIR_CONTROL_A_MUTE_BIT, 0);
-
- if (dmic->fifo_b)
- dmic_update_bits(dai, base[i] + FIR_CONTROL_B,
- FIR_CONTROL_B_MUTE_BIT, 0);
- }
- if (dmic->fifo_a) {
- val = OUT_GAIN_LEFT_A_GAIN(gval);
- dmic_write(dai, base[i] + OUT_GAIN_LEFT_A, val);
- dmic_write(dai, base[i] + OUT_GAIN_RIGHT_A, val);
- }
- if (dmic->fifo_b) {
- val = OUT_GAIN_LEFT_B_GAIN(gval);
- dmic_write(dai, base[i] + OUT_GAIN_LEFT_B, val);
- dmic_write(dai, base[i] + OUT_GAIN_RIGHT_B, val);
- }
- }
- spin_unlock(&dmic->lock);
-
- if (gval)
- return DMIC_UNMUTE_RAMP_US;
- else
- return 0;
-}
-
-/* This function returns a raw list of potential microphone clock and decimation
- * modes for achieving requested sample rates. The search is constrained by
- * decimation HW capabililies and setup parameters. The parameters such as
- * microphone clock min/max and duty cycle requirements need be checked from
- * used microphone component datasheet.
- */
-static void find_modes(struct decim_modes *modes,
- struct sof_ipc_dai_dmic_params *prm, uint32_t fs)
-{
- int clkdiv_min;
- int clkdiv_max;
- int clkdiv;
- int c1;
- int du_min;
- int du_max;
- int pdmclk;
- int osr;
- int mfir;
- int mcic;
- int ioclk_test;
- int osr_min = DMIC_MIN_OSR;
- int i = 0;
-
- /* Defaults, empty result */
- modes->num_of_modes = 0;
-
- /* The FIFO is not requested if sample rate is set to zero. Just
- * return in such case with num_of_modes as zero.
- */
- if (fs == 0)
- return;
-
- /* Override DMIC_MIN_OSR for very high sample rates, use as minimum
- * the nominal clock for the high rates.
- */
- if (fs >= DMIC_HIGH_RATE_MIN_FS)
- osr_min = DMIC_HIGH_RATE_OSR_MIN;
-
- /* Check for sane pdm clock, min 100 kHz, max ioclk/2 */
- if (prm->pdmclk_max < DMIC_HW_PDM_CLK_MIN ||
- prm->pdmclk_max > DMIC_HW_IOCLK / 2) {
- trace_dmic_error("pmx");
- return;
- }
- if (prm->pdmclk_min < DMIC_HW_PDM_CLK_MIN ||
- prm->pdmclk_min > prm->pdmclk_max) {
- trace_dmic_error("pmn");
- return;
- }
-
- /* Check for sane duty cycle */
- if (prm->duty_min > prm->duty_max) {
- trace_dmic_error("pdu");
- return;
- }
- if (prm->duty_min < DMIC_HW_DUTY_MIN ||
- prm->duty_min > DMIC_HW_DUTY_MAX) {
- trace_dmic_error("pdn");
- return;
- }
- if (prm->duty_max < DMIC_HW_DUTY_MIN ||
- prm->duty_max > DMIC_HW_DUTY_MAX) {
- trace_dmic_error("pdx");
- return;
- }
-
- /* Min and max clock dividers */
- clkdiv_min = ceil_divide(DMIC_HW_IOCLK, prm->pdmclk_max);
- clkdiv_min = MAX(clkdiv_min, DMIC_HW_CIC_DECIM_MIN);
- clkdiv_max = DMIC_HW_IOCLK / prm->pdmclk_min;
-
- /* Loop possible clock dividers and check based on resulting
- * oversampling ratio that CIC and FIR decimation ratios are
- * feasible. The ratios need to be integers. Also the mic clock
- * duty cycle need to be within limits.
- */
- for (clkdiv = clkdiv_min; clkdiv <= clkdiv_max; clkdiv++) {
- /* Calculate duty cycle for this clock divider. Note that
- * odd dividers cause non-50% duty cycle.
- */
- c1 = clkdiv >> 1;
- du_min = 100 * c1 / clkdiv;
- du_max = 100 - du_min;
-
- /* Calculate PDM clock rate and oversampling ratio. */
- pdmclk = DMIC_HW_IOCLK / clkdiv;
- osr = pdmclk / fs;
-
- /* Check that OSR constraints is met and clock duty cycle does
- * not exceed microphone specification. If exceed proceed to
- * next clkdiv.
- */
- if (osr < osr_min || du_min < prm->duty_min ||
- du_max > prm->duty_max)
- continue;
-
- /* Loop FIR decimation factors candidates. If the
- * integer divided decimation factors and clock dividers
- * as multiplied with sample rate match the IO clock
- * rate the division was exact and such decimation mode
- * is possible. Then check that CIC decimation constraints
- * are met. The passed decimation modes are added to array.
- */
- for (mfir = DMIC_HW_FIR_DECIM_MIN;
- mfir <= DMIC_HW_FIR_DECIM_MAX; mfir++) {
- mcic = osr / mfir;
- ioclk_test = fs * mfir * mcic * clkdiv;
-
- if (ioclk_test == DMIC_HW_IOCLK &&
- mcic >= DMIC_HW_CIC_DECIM_MIN &&
- mcic <= DMIC_HW_CIC_DECIM_MAX &&
- i < DMIC_MAX_MODES) {
- modes->clkdiv[i] = clkdiv;
- modes->mcic[i] = mcic;
- modes->mfir[i] = mfir;
- i++;
- modes->num_of_modes = i;
- }
- }
- }
-#if defined MODULE_TEST
- printf("# Found %d modes\n", i);
-#endif
-}
-
-/* The previous raw modes list contains sane configuration possibilities. When
- * there is request for both FIFOs A and B operation this function returns
- * list of compatible settings.
- */
-static void match_modes(struct matched_modes *c, struct decim_modes *a,
- struct decim_modes *b)
-{
- int16_t idx[DMIC_MAX_MODES];
- int idx_length;
- int i;
- int n;
- int m;
-
- /* Check if previous search got results. */
- c->num_of_modes = 0;
- if (a->num_of_modes == 0 && b->num_of_modes == 0) {
- /* Nothing to do */
- return;
- }
-
- /* Ensure that num_of_modes is sane. */
- if (a->num_of_modes > DMIC_MAX_MODES ||
- b->num_of_modes > DMIC_MAX_MODES)
- return;
-
- /* Check for request only for FIFO A or B. In such case pass list for
- * A or B as such.
- */
- if (b->num_of_modes == 0) {
- c->num_of_modes = a->num_of_modes;
- for (i = 0; i < a->num_of_modes; i++) {
- c->clkdiv[i] = a->clkdiv[i];
- c->mcic[i] = a->mcic[i];
- c->mfir_a[i] = a->mfir[i];
- c->mfir_b[i] = 0; /* Mark FIR B as non-used */
- }
- return;
- }
-
- if (a->num_of_modes == 0) {
- c->num_of_modes = b->num_of_modes;
- for (i = 0; i < b->num_of_modes; i++) {
- c->clkdiv[i] = b->clkdiv[i];
- c->mcic[i] = b->mcic[i];
- c->mfir_b[i] = b->mfir[i];
- c->mfir_a[i] = 0; /* Mark FIR A as non-used */
- }
- return;
- }
-
- /* Merge a list of compatible modes */
- i = 0;
- for (n = 0; n < a->num_of_modes; n++) {
- /* Find all indices of values a->clkdiv[n] in b->clkdiv[] */
- idx_length = find_equal_int16(idx, b->clkdiv, a->clkdiv[n],
- b->num_of_modes, 0);
- for (m = 0; m < idx_length; m++) {
- if (b->mcic[idx[m]] == a->mcic[n]) {
- c->clkdiv[i] = a->clkdiv[n];
- c->mcic[i] = a->mcic[n];
- c->mfir_a[i] = a->mfir[n];
- c->mfir_b[i] = b->mfir[idx[m]];
- i++;
- }
- }
- c->num_of_modes = i;
- }
-}
-
-/* Finds a suitable FIR decimation filter from the included set */
-static struct pdm_decim *get_fir(struct dmic_configuration *cfg, int mfir)
-{
- int i;
- int fs;
- int cic_fs;
- int fir_max_length;
- struct pdm_decim *fir = NULL;
-
- if (mfir <= 0)
- return fir;
-
- cic_fs = DMIC_HW_IOCLK / cfg->clkdiv / cfg->mcic;
- fs = cic_fs / mfir;
- /* FIR max. length depends on available cycles and coef RAM
- * length. Exceeding this length sets HW overrun status and
- * overwrite of other register.
- */
- fir_max_length = MIN(DMIC_HW_FIR_LENGTH_MAX,
- DMIC_HW_IOCLK / fs / 2 - DMIC_FIR_PIPELINE_OVERHEAD);
-
- for (i = 0; i < DMIC_FIR_LIST_LENGTH; i++) {
- if (fir_list[i]->decim_factor == mfir &&
- fir_list[i]->length <= fir_max_length) {
- /* Store pointer, break from loop to avoid a
- * Possible other mode with lower FIR length.
- */
- fir = fir_list[i];
- break;
- }
- }
-
- return fir;
-}
-
-/* Calculate scale and shift to use for FIR coefficients. Scale is applied
- * before write to HW coef RAM. Shift will be programmed to HW register.
- */
-static int fir_coef_scale(int32_t *fir_scale, int *fir_shift, int add_shift,
- const int32_t coef[], int coef_length, int32_t gain)
-{
- int32_t amax;
- int32_t new_amax;
- int32_t fir_gain;
- int shift;
-
- /* Multiply gain passed from CIC with output full scale. */
- fir_gain = Q_MULTSR_32X32((int64_t)gain, DMIC_HW_SENS_Q28,
- DMIC_FIR_SCALE_Q, 28, DMIC_FIR_SCALE_Q);
-
- /* Find the largest FIR coefficient value. */
- amax = find_max_abs_int32((int32_t *)coef, coef_length);
-
- /* Scale max. tap value with FIR gain. */
- new_amax = Q_MULTSR_32X32((int64_t)amax, fir_gain, 31,
- DMIC_FIR_SCALE_Q, DMIC_FIR_SCALE_Q);
- if (new_amax <= 0)
- return -EINVAL;
-
- /* Get left shifts count to normalize the fractional value as 32 bit.
- * We need right shifts count for scaling so need to invert. The
- * difference of Q31 vs. used Q format is added to get the correct
- * normalization right shift value.
- */
- shift = 31 - DMIC_FIR_SCALE_Q - norm_int32(new_amax);
-
- /* Add to shift for coef raw Q31 format shift and store to
- * configuration. Ensure range (fail should not happen with OK
- * coefficient set).
- */
- *fir_shift = -shift + add_shift;
- if (*fir_shift < DMIC_HW_FIR_SHIFT_MIN ||
- *fir_shift > DMIC_HW_FIR_SHIFT_MAX)
- return -EINVAL;
-
- /* Compensate shift into FIR coef scaler and store as Q4.20. */
- if (shift < 0)
- *fir_scale = (fir_gain << -shift);
- else
- *fir_scale = (fir_gain >> shift);
-
-#if defined MODULE_TEST
- printf("# FIR gain need Q28 = %d (%f)\n", fir_gain,
- Q_CONVERT_QTOF(fir_gain, 28));
- printf("# FIR max coef no gain Q31 = %d (%f)\n", amax,
- Q_CONVERT_QTOF(amax, 31));
- printf("# FIR max coef with gain Q28 = %d (%f)\n", new_amax,
- Q_CONVERT_QTOF(new_amax, 28));
- printf("# FIR coef norm rshift = %d\n", shift);
- printf("# FIR coef old rshift = %d\n", add_shift);
- printf("# FIR coef new rshift = %d\n", *fir_shift);
- printf("# FIR coef scaler Q28 = %d (%f)\n", *fir_scale,
- Q_CONVERT_QTOF(*fir_scale, 28));
-#endif
-
- return 0;
-}
-
-/* This function selects with a simple criteria one mode to set up the
- * decimator. For the settings chosen for FIFOs A and B output a lookup
- * is done for FIR coefficients from the included coefficients tables.
- * For some decimation factors there may be several length coefficient sets.
- * It is due to possible restruction of decimation engine cycles per given
- * sample rate. If the coefficients length is exceeded the lookup continues.
- * Therefore the list of coefficient set must present the filters for a
- * decimation factor in decreasing length order.
- *
- * Note: If there is no filter available an error is returned. The parameters
- * should be reviewed for such case. If still a filter is missing it should be
- * added into the included set. FIR decimation with a high factor usually
- * needs compromizes into specifications and is not desirable.
- */
-static int select_mode(struct dmic_configuration *cfg,
- struct matched_modes *modes)
-{
- int32_t g_cic;
- int32_t fir_in_max;
- int32_t cic_out_max;
- int32_t gain_to_fir;
- int16_t idx[DMIC_MAX_MODES];
- int16_t *mfir;
- int n = 1;
- int mmin;
- int count;
- int mcic;
- int bits_cic;
- int ret;
-
- /* If there are more than one possibilities select a mode with lowest
- * FIR decimation factor. If there are several select mode with highest
- * ioclk divider to minimize microphone power consumption. The highest
- * clock divisors are in the end of list so select the last of list.
- * The minimum OSR criteria used in previous ensures that quality in
- * the candidates should be sufficient.
- */
- if (modes->num_of_modes == 0) {
- trace_dmic_error("nom");
- return -EINVAL;
- }
-
- /* Valid modes presence is indicated with non-zero decimation
- * factor in 1st element. If FIR A is not used get decimation factors
- * from FIR B instead.
- */
- if (modes->mfir_a[0] > 0)
- mfir = modes->mfir_a;
- else
- mfir = modes->mfir_b;
-
- mmin = find_min_int16(mfir, modes->num_of_modes);
- count = find_equal_int16(idx, mfir, mmin, modes->num_of_modes, 0);
- n = idx[count - 1];
-
- /* Get microphone clock and decimation parameters for used mode from
- * the list.
- */
- cfg->clkdiv = modes->clkdiv[n];
- cfg->mfir_a = modes->mfir_a[n];
- cfg->mfir_b = modes->mfir_b[n];
- cfg->mcic = modes->mcic[n];
- cfg->fir_a = NULL;
- cfg->fir_b = NULL;
-
- /* Find raw FIR coefficients to match the decimation factors of FIR
- * A and B.
- */
- if (cfg->mfir_a > 0) {
- cfg->fir_a = get_fir(cfg, cfg->mfir_a);
- if (!cfg->fir_a) {
- trace_dmic_error("fam");
- trace_value(cfg->mfir_a);
- return -EINVAL;
- }
- }
-
- if (cfg->mfir_b > 0) {
- cfg->fir_b = get_fir(cfg, cfg->mfir_b);
- if (!cfg->fir_b) {
- trace_dmic_error("fbm");
- trace_value(cfg->mfir_b);
- return -EINVAL;
- }
- }
-
- /* Calculate CIC shift from the decimation factor specific gain. The
- * gain of HW decimator equals decimation factor to power of 5.
- */
- mcic = cfg->mcic;
- g_cic = mcic * mcic * mcic * mcic * mcic;
- if (g_cic < 0) {
- /* Erroneous decimation factor and CIC gain */
- trace_dmic_error("gci");
- return -EINVAL;
- }
-
- bits_cic = 32 - norm_int32(g_cic);
- cfg->cic_shift = bits_cic - DMIC_HW_BITS_FIR_INPUT;
-
- /* Calculate remaining gain to FIR in Q format used for gain
- * values.
- */
- fir_in_max = (1 << (DMIC_HW_BITS_FIR_INPUT - 1));
- if (cfg->cic_shift >= 0)
- cic_out_max = g_cic >> cfg->cic_shift;
- else
- cic_out_max = g_cic << -cfg->cic_shift;
-
- gain_to_fir = (int32_t)((((int64_t)fir_in_max) << DMIC_FIR_SCALE_Q) /
- cic_out_max);
-
- /* Calculate FIR scale and shift */
- if (cfg->mfir_a > 0) {
- cfg->fir_a_length = cfg->fir_a->length;
- ret = fir_coef_scale(&cfg->fir_a_scale, &cfg->fir_a_shift,
- cfg->fir_a->shift, cfg->fir_a->coef, cfg->fir_a->length,
- gain_to_fir);
- if (ret < 0) {
- /* Invalid coefficient set found, should not happen. */
- trace_dmic_error("ina");
- return -EINVAL;
- }
- } else {
- cfg->fir_a_scale = 0;
- cfg->fir_a_shift = 0;
- cfg->fir_a_length = 0;
- }
-
- if (cfg->mfir_b > 0) {
- cfg->fir_b_length = cfg->fir_b->length;
- ret = fir_coef_scale(&cfg->fir_b_scale, &cfg->fir_b_shift,
- cfg->fir_b->shift, cfg->fir_b->coef, cfg->fir_b->length,
- gain_to_fir);
- if (ret < 0) {
- /* Invalid coefficient set found, should not happen. */
- trace_dmic_error("inb");
- return -EINVAL;
- }
- } else {
- cfg->fir_b_scale = 0;
- cfg->fir_b_shift = 0;
- cfg->fir_b_length = 0;
- }
-
- return 0;
-}
-
-/* The FIFO input packer mode (IPM) settings are somewhat different in
- * HW versions. This helper function returns a suitable IPM bit field
- * value to use.
- */
-
-static inline void ipm_helper1(int *ipm, int stereo[], int swap[],
- struct sof_ipc_dai_dmic_params *dmic)
-{
- int pdm[DMIC_HW_CONTROLLERS] = {0};
- int cnt;
- int i;
-
- /* Loop number of PDM controllers in the configuration. If mic A
- * or B is enabled then a pdm controller is marked as active. Also it
- * is checked whether the controller should operate as stereo or mono
- * left (A) or mono right (B) mode. Mono right mode is setup as channel
- * swapped mono left.
- */
- for (i = 0; i < dmic->num_pdm_active; i++) {
- cnt = 0;
- if (dmic->pdm[i].enable_mic_a > 0)
- cnt++;
-
- if (dmic->pdm[i].enable_mic_b > 0)
- cnt++;
-
- /* A PDM controller is used if at least one mic was enabled. */
- pdm[i] = !!cnt;
-
- /* Set stereo mode if both mic A anc B are enabled. */
- cnt >>= 1;
- stereo[i] = cnt;
-
- /* Swap channels if only mic B is used for mono processing. */
- swap[i] = dmic->pdm[i].enable_mic_b & !cnt;
- }
-
- /* IPM indicates active pdm controllers. */
- *ipm = 0;
-
- if (pdm[0] == 0 && pdm[1] > 0)
- *ipm = 1;
-
- if (pdm[0] > 0 && pdm[1] > 0)
- *ipm = 2;
-}
-
-#if DMIC_HW_VERSION == 2
-
-static inline void ipm_helper2(int source[], int *ipm, int stereo[],
- int swap[], struct sof_ipc_dai_dmic_params *dmic)
-{
- int pdm[DMIC_HW_CONTROLLERS];
- int i;
- int n = 0;
-
- /* Loop number of PDM controllers in the configuration. If mic A
- * or B is enabled then a pdm controller is marked as active. Also it
- * is checked whether the controller should operate as stereo or mono
- * left (A) or mono right (B) mode. Mono right mode is setup as channel
- * swapped mono left. The function returns also in array source[] the
- * indice of enabled pdm controllers to be used for IPM configuration.
- */
- for (i = 0; i < dmic->num_pdm_active; i++) {
- if (dmic->pdm[i].enable_mic_a > 0 ||
- dmic->pdm[i].enable_mic_b > 0) {
- pdm[i] = 1;
- source[n] = i;
- n++;
- } else {
- pdm[i] = 0;
- swap[i] = 0;
- }
-
- if (dmic->pdm[i].enable_mic_a > 0 &&
- dmic->pdm[i].enable_mic_b > 0) {
- stereo[i] = 1;
- swap[i] = 0;
- } else {
- stereo[i] = 0;
- if (dmic->pdm[i].enable_mic_a == 0)
- swap[i] = 1;
- else
- swap[i] = 0;
- }
- }
-
- /* IPM bit field is set to count of active pdm controllers. */
- *ipm = pdm[0];
- for (i = 1; i < dmic->num_pdm_active; i++)
- *ipm += pdm[i];
-}
-#endif
-
-static int configure_registers(struct dai *dai, struct dmic_configuration *cfg,
- struct sof_ipc_dai_dmic_params *dmic)
-{
- int stereo[DMIC_HW_CONTROLLERS];
- int swap[DMIC_HW_CONTROLLERS];
- uint32_t val;
- int32_t ci;
- uint32_t cu;
- int ipm;
- int of0;
- int of1;
- int fir_decim;
- int fir_length;
- int length;
- int edge;
- int dccomp;
- int cic_start_a;
- int cic_start_b;
- int fir_start_a;
- int fir_start_b;
- int soft_reset;
- int i;
- int j;
-
- struct dmic_pdata *pdata = dai_get_drvdata(dai);
- int array_a = 0;
- int array_b = 0;
- int cic_mute = 1;
- int fir_mute = 1;
- int bfth = 3; /* Should be 3 for 8 entries, 1 is 2 entries */
- int th = 0; /* Used with TIE=1 */
-
- /* Normal start sequence */
- dccomp = 1;
- soft_reset = 1;
- cic_start_a = 0;
- cic_start_b = 0;
- fir_start_a = 0;
- fir_start_b = 0;
-
-#if DMIC_HW_VERSION == 2
- int source[4] = {0, 0, 0, 0};
-#endif
-
-#if defined MODULE_TEST
- int32_t fir_a_max = 0;
- int32_t fir_a_min = 0;
- int32_t fir_b_max = 0;
- int32_t fir_b_min = 0;
-#endif
-
- /* pdata is set by dmic_probe(), error if it has not been set */
- if (!pdata) {
- trace_dmic_error("cfr");
- return -EINVAL;
- }
-
- /* Sanity checks */
- if (dmic->num_pdm_active > DMIC_HW_CONTROLLERS) {
- trace_dmic_error("num");
- return -EINVAL;
- }
-
- /* OUTCONTROL0 and OUTCONTROL1 */
- trace_dmic("reg");
- of0 = (dmic->fifo_bits_a == 32) ? 2 : 0;
- of1 = (dmic->fifo_bits_b == 32) ? 2 : 0;
-
-#if DMIC_HW_VERSION == 1
- ipm_helper1(&ipm, stereo, swap, dmic);
- val = OUTCONTROL0_TIE(0) |
- OUTCONTROL0_SIP(0) |
- OUTCONTROL0_FINIT(1) |
- OUTCONTROL0_FCI(0) |
- OUTCONTROL0_BFTH(bfth) |
- OUTCONTROL0_OF(of0) |
- OUTCONTROL0_IPM(ipm) |
- OUTCONTROL0_TH(th);
- dmic_write(dai, OUTCONTROL0, val);
- trace_value(val);
-
- val = OUTCONTROL1_TIE(0) |
- OUTCONTROL1_SIP(0) |
- OUTCONTROL1_FINIT(1) |
- OUTCONTROL1_FCI(0) |
- OUTCONTROL1_BFTH(bfth) |
- OUTCONTROL1_OF(of1) |
- OUTCONTROL1_IPM(ipm) |
- OUTCONTROL1_TH(th);
- dmic_write(dai, OUTCONTROL1, val);
- trace_value(val);
-#endif
-
-#if DMIC_HW_VERSION == 2
-#if DMIC_HW_CONTROLLERS > 2
- ipm_helper2(source, &ipm, stereo, swap, dmic);
-#else
- ipm_helper1(&ipm, stereo, swap, dmic);
-#endif
- val = OUTCONTROL0_TIE(0) |
- OUTCONTROL0_SIP(0) |
- OUTCONTROL0_FINIT(1) |
- OUTCONTROL0_FCI(0) |
- OUTCONTROL0_BFTH(bfth) |
- OUTCONTROL0_OF(of0) |
- OUTCONTROL0_IPM(ipm) |
- OUTCONTROL0_IPM_SOURCE_1(source[0]) |
- OUTCONTROL0_IPM_SOURCE_2(source[1]) |
- OUTCONTROL0_IPM_SOURCE_3(source[2]) |
- OUTCONTROL0_IPM_SOURCE_4(source[3]) |
- OUTCONTROL0_TH(th);
- dmic_write(dai, OUTCONTROL0, val);
- trace_value(val);
-
- val = OUTCONTROL1_TIE(0) |
- OUTCONTROL1_SIP(0) |
- OUTCONTROL1_FINIT(1) |
- OUTCONTROL1_FCI(0) |
- OUTCONTROL1_BFTH(bfth) |
- OUTCONTROL1_OF(of1) |
- OUTCONTROL1_IPM(ipm) |
- OUTCONTROL1_IPM_SOURCE_1(source[0]) |
- OUTCONTROL1_IPM_SOURCE_2(source[1]) |
- OUTCONTROL1_IPM_SOURCE_3(source[2]) |
- OUTCONTROL1_IPM_SOURCE_4(source[3]) |
- OUTCONTROL1_TH(th);
- dmic_write(dai, OUTCONTROL1, val);
- trace_value(val);
-#endif
-
- /* Mark enabled microphones into private data to be later used
- * for starting correct parts of the HW.
- */
- for (i = 0; i < DMIC_HW_CONTROLLERS; i++) {
- pdata->enable[i] = (dmic->pdm[i].enable_mic_b << 1) |
- dmic->pdm[i].enable_mic_a;
- }
-
- for (i = 0; i < DMIC_HW_CONTROLLERS; i++) {
- /* CIC */
- val = CIC_CONTROL_SOFT_RESET(soft_reset) |
- CIC_CONTROL_CIC_START_B(cic_start_b) |
- CIC_CONTROL_CIC_START_A(cic_start_a) |
- CIC_CONTROL_MIC_B_POLARITY(dmic->pdm[i].polarity_mic_a) |
- CIC_CONTROL_MIC_A_POLARITY(dmic->pdm[i].polarity_mic_b) |
- CIC_CONTROL_MIC_MUTE(cic_mute) |
- CIC_CONTROL_STEREO_MODE(stereo[i]);
- dmic_write(dai, base[i] + CIC_CONTROL, val);
- trace_value(val);
-
- val = CIC_CONFIG_CIC_SHIFT(cfg->cic_shift + 8) |
- CIC_CONFIG_COMB_COUNT(cfg->mcic - 1);
- dmic_write(dai, base[i] + CIC_CONFIG, val);
- trace_value(val);
-
- /* Mono right channel mic usage requires swap of PDM channels
- * since the mono decimation is done with only left channel
- * processing active.
- */
- edge = dmic->pdm[i].clk_edge;
- if (swap[i])
- edge = !edge;
-
- val = MIC_CONTROL_PDM_CLKDIV(cfg->clkdiv - 2) |
- MIC_CONTROL_PDM_SKEW(dmic->pdm[i].skew) |
- MIC_CONTROL_CLK_EDGE(edge) |
- MIC_CONTROL_PDM_EN_B(cic_start_b) |
- MIC_CONTROL_PDM_EN_A(cic_start_a);
- dmic_write(dai, base[i] + MIC_CONTROL, val);
- trace_value(val);
-
- /* FIR A */
- fir_decim = MAX(cfg->mfir_a - 1, 0);
- fir_length = MAX(cfg->fir_a_length - 1, 0);
- val = FIR_CONTROL_A_START(fir_start_a) |
- FIR_CONTROL_A_ARRAY_START_EN(array_a) |
- FIR_CONTROL_A_DCCOMP(dccomp) |
- FIR_CONTROL_A_MUTE(fir_mute) |
- FIR_CONTROL_A_STEREO(stereo[i]);
- dmic_write(dai, base[i] + FIR_CONTROL_A, val);
- trace_value(val);
-
- val = FIR_CONFIG_A_FIR_DECIMATION(fir_decim) |
- FIR_CONFIG_A_FIR_SHIFT(cfg->fir_a_shift) |
- FIR_CONFIG_A_FIR_LENGTH(fir_length);
- dmic_write(dai, base[i] + FIR_CONFIG_A, val);
- trace_value(val);
-
- val = DC_OFFSET_LEFT_A_DC_OFFS(DCCOMP_TC0);
- dmic_write(dai, base[i] + DC_OFFSET_LEFT_A, val);
- trace_value(val);
-
- val = DC_OFFSET_RIGHT_A_DC_OFFS(DCCOMP_TC0);
- dmic_write(dai, base[i] + DC_OFFSET_RIGHT_A, val);
- trace_value(val);
-
- val = OUT_GAIN_LEFT_A_GAIN(0);
- dmic_write(dai, base[i] + OUT_GAIN_LEFT_A, val);
- trace_value(val);
-
- val = OUT_GAIN_RIGHT_A_GAIN(0);
- dmic_write(dai, base[i] + OUT_GAIN_RIGHT_A, val);
- trace_value(val);
-
- /* FIR B */
- fir_decim = MAX(cfg->mfir_b - 1, 0);
- fir_length = MAX(cfg->fir_b_length - 1, 0);
- val = FIR_CONTROL_B_START(fir_start_b) |
- FIR_CONTROL_B_ARRAY_START_EN(array_b) |
- FIR_CONTROL_B_DCCOMP(dccomp) |
- FIR_CONTROL_B_MUTE(fir_mute) |
- FIR_CONTROL_B_STEREO(stereo[i]);
- dmic_write(dai, base[i] + FIR_CONTROL_B, val);
- trace_value(val);
-
- val = FIR_CONFIG_B_FIR_DECIMATION(fir_decim) |
- FIR_CONFIG_B_FIR_SHIFT(cfg->fir_b_shift) |
- FIR_CONFIG_B_FIR_LENGTH(fir_length);
- dmic_write(dai, base[i] + FIR_CONFIG_B, val);
- trace_value(val);
-
- val = DC_OFFSET_LEFT_B_DC_OFFS(DCCOMP_TC0);
- dmic_write(dai, base[i] + DC_OFFSET_LEFT_B, val);
- trace_value(val);
- trace_value(val);
-
- val = DC_OFFSET_RIGHT_B_DC_OFFS(DCCOMP_TC0);
- dmic_write(dai, base[i] + DC_OFFSET_RIGHT_B, val);
- trace_value(val);
-
- val = OUT_GAIN_LEFT_B_GAIN(0);
- dmic_write(dai, base[i] + OUT_GAIN_LEFT_B, val);
- trace_value(val);
-
- val = OUT_GAIN_RIGHT_B_GAIN(0);
- dmic_write(dai, base[i] + OUT_GAIN_RIGHT_B, val);
- trace_value(val);
-
- /* Write coef RAM A with scaled coefficient in reverse order */
- length = cfg->fir_a_length;
- for (j = 0; j < length; j++) {
- ci = (int32_t)Q_MULTSR_32X32(
- (int64_t)cfg->fir_a->coef[j], cfg->fir_a_scale,
- 31, DMIC_FIR_SCALE_Q, DMIC_HW_FIR_COEF_Q);
- cu = FIR_COEF_A(ci);
- dmic_write(dai, coef_base_a[i]
- + ((length - j - 1) << 2), cu);
-#if defined MODULE_TEST
- fir_a_max = MAX(fir_a_max, ci);
- fir_a_min = MIN(fir_a_min, ci);
-#endif
- }
-
- /* Write coef RAM B with scaled coefficient in reverse order */
- length = cfg->fir_b_length;
- for (j = 0; j < length; j++) {
- ci = (int32_t)Q_MULTSR_32X32(
- (int64_t)cfg->fir_b->coef[j], cfg->fir_b_scale,
- 31, DMIC_FIR_SCALE_Q, DMIC_HW_FIR_COEF_Q);
- cu = FIR_COEF_B(ci);
- dmic_write(dai, coef_base_b[i]
- + ((length - j - 1) << 2), cu);
-#if defined MODULE_TEST
- fir_b_max = MAX(fir_b_max, ci);
- fir_b_min = MIN(fir_b_min, ci);
-#endif
- }
- }
-
-#if defined MODULE_TEST
- printf("# FIR A max Q19 = %d (%f)\n", fir_a_max,
- Q_CONVERT_QTOF(fir_a_max, 19));
- printf("# FIR A min Q19 = %d (%f)\n", fir_a_min,
- Q_CONVERT_QTOF(fir_a_min, 19));
- printf("# FIR B max Q19 = %d (%f)\n", fir_b_max,
- Q_CONVERT_QTOF(fir_b_max, 19));
- printf("# FIR B min Q19 = %d (%f)\n", fir_b_min,
- Q_CONVERT_QTOF(fir_b_min, 19));
-#endif
-
- /* Function dmic_start() uses these to start the used FIFOs */
- if (cfg->mfir_a > 0)
- pdata->fifo_a = 1;
- else
- pdata->fifo_a = 0;
-
- if (cfg->mfir_b > 0)
- pdata->fifo_b = 1;
- else
- pdata->fifo_b = 0;
-
- return 0;
-}
-
-static int dmic_set_config(struct dai *dai, struct sof_ipc_dai_config *config)
-{
- struct dmic_pdata *dmic = dai_get_drvdata(dai);
- struct sof_ipc_dai_dmic_params *prm;
- struct matched_modes modes_ab;
- struct dmic_configuration cfg;
- struct decim_modes modes_a;
- struct decim_modes modes_b;
- int num_pdm_active = config->dmic.num_pdm_active;
- size_t size;
- int i, j, ret = 0;
-
- trace_dmic("dsc");
-
- /* Initialize start sequence handler */
- work_init(&dmic->dmicwork, dmic_work, dai, WORK_ASYNC);
-
- /*
- * "config" might contain pdm controller params for only
- * the active controllers
- * "prm" is initialized with default params for all HW controllers
- */
- size = sizeof(*prm) + DMIC_HW_CONTROLLERS
- * sizeof(struct sof_ipc_dai_dmic_pdm_ctrl);
- prm = rzalloc(RZONE_SYS, SOF_MEM_CAPS_RAM, size);
-
- /* copy the DMIC params */
- memcpy(prm, &config->dmic, sizeof(struct sof_ipc_dai_dmic_params));
-
- /* copy the pdm controller params from ipc */
- for (i = 0; i < DMIC_HW_CONTROLLERS; i++) {
- prm->pdm[i].id = i;
- for (j = 0; j < num_pdm_active; j++) {
- /* copy the pdm controller params id the id's match */
- if (prm->pdm[i].id == config->dmic.pdm[j].id)
- memcpy(&prm->pdm[i], &config->dmic.pdm[j],
- sizeof(prm->pdm[i]));
- }
- }
-
- trace_value(prm->driver_ipc_version);
- trace_value(prm->pdmclk_min);
- trace_value(prm->pdmclk_max);
- trace_value(prm->fifo_fs_a);
- trace_value(prm->fifo_fs_b);
- trace_value(prm->fifo_bits_a);
- trace_value(prm->fifo_bits_b);
- trace_value(prm->duty_min);
- trace_value(prm->duty_max);
- trace_value(prm->num_pdm_active);
-
- if (prm->driver_ipc_version != DMIC_IPC_VERSION) {
- trace_dmic_error("ver");
- ret = -EINVAL;
- goto finish;
- }
-
- if (prm->fifo_bits_a != 16 && prm->fifo_bits_a != 32) {
- trace_dmic_error("fba");
- ret = -EINVAL;
- goto finish;
- }
-
- if (prm->fifo_bits_b != 16 && prm->fifo_bits_b != 32) {
- trace_dmic_error("fbb");
- ret = -EINVAL;
- goto finish;
- }
-
- /* Match and select optimal decimators configuration for FIFOs A and B
- * paths. This setup phase is still abstract. Successful completion
- * points struct cfg to FIR coefficients and contains the scale value
- * to use for FIR coefficient RAM write as well as the CIC and FIR
- * shift values.
- */
- find_modes(&modes_a, prm, prm->fifo_fs_a);
- if (modes_a.num_of_modes == 0 && prm->fifo_fs_a > 0) {
- trace_dmic_error("amo");
- ret = -EINVAL;
- goto finish;
- }
-
- find_modes(&modes_b, prm, prm->fifo_fs_b);
- if (modes_b.num_of_modes == 0 && prm->fifo_fs_b > 0) {
- trace_dmic_error("bmo");
- ret = -EINVAL;
- goto finish;
- }
-
- match_modes(&modes_ab, &modes_a, &modes_b);
- ret = select_mode(&cfg, &modes_ab);
- if (ret < 0) {
- trace_dmic_error("smo");
- ret = -EINVAL;
- goto finish;
- }
-
- trace_dmic("cfg");
- trace_value(cfg.clkdiv);
- trace_value(cfg.mcic);
- trace_value(cfg.mfir_a);
- trace_value(cfg.mfir_b);
- trace_value(cfg.fir_a_length);
- trace_value(cfg.fir_b_length);
- trace_value(cfg.cic_shift);
- trace_value(cfg.fir_a_shift);
- trace_value(cfg.fir_b_shift);
-
- /* Struct reg contains a mirror of actual HW registers. Determine
- * register bits configuration from decimator configuration and the
- * requested parameters.
- */
- ret = configure_registers(dai, &cfg, prm);
- if (ret < 0) {
- trace_dmic_error("cor");
- ret = -EINVAL;
- goto finish;
- }
-
- dmic->state = COMP_STATE_PREPARE;
-
-finish:
- /* free config params */
- rfree(prm);
-
- return ret;
-}
-
-/* start the DMIC for capture */
-static void dmic_start(struct dai *dai)
-{
- struct dmic_pdata *dmic = dai_get_drvdata(dai);
- int i;
- int mic_a;
- int mic_b;
- int fir_a;
- int fir_b;
-
- /* enable port */
- spin_lock(&dmic->lock);
- trace_dmic("sta");
- dmic->state = COMP_STATE_ACTIVE;
- dmic->startcount = 0;
- dmic->gain = LOGRAMP_GI; /* Initial gain value */
-
- if (dmic->fifo_a) {
- trace_dmic("ffa");
- /* Clear FIFO A initialize, Enable interrupts to DSP,
- * Start FIFO A packer.
- */
- dmic_update_bits(dai, OUTCONTROL0,
- OUTCONTROL0_FINIT_BIT | OUTCONTROL0_SIP_BIT,
- OUTCONTROL0_SIP_BIT);
- }
- if (dmic->fifo_b) {
- trace_dmic("ffb");
- /* Clear FIFO B initialize, Enable interrupts to DSP,
- * Start FIFO B packer.
- */
- dmic_update_bits(dai, OUTCONTROL1,
- OUTCONTROL1_FINIT_BIT | OUTCONTROL1_SIP_BIT,
- OUTCONTROL1_SIP_BIT);
- }
-
- for (i = 0; i < DMIC_HW_CONTROLLERS; i++) {
- mic_a = dmic->enable[i] & 1;
- mic_b = (dmic->enable[i] & 2) >> 1;
- if (dmic->fifo_a)
- fir_a = (dmic->enable[i] > 0) ? 1 : 0;
- else
- fir_a = 0;
- if (dmic->fifo_b)
- fir_b = (dmic->enable[i] > 0) ? 1 : 0;
- else
- fir_b = 0;
-
- trace_dmic("mfn");
- trace_value(mic_a);
- trace_value(mic_b);
- trace_value(fir_a);
- trace_value(fir_b);
-
- dmic_update_bits(dai, base[i] + CIC_CONTROL,
- CIC_CONTROL_CIC_START_A_BIT |
- CIC_CONTROL_CIC_START_B_BIT,
- CIC_CONTROL_CIC_START_A(mic_a) |
- CIC_CONTROL_CIC_START_B(mic_b));
- dmic_update_bits(dai, base[i] + MIC_CONTROL,
- MIC_CONTROL_PDM_EN_A_BIT |
- MIC_CONTROL_PDM_EN_B_BIT,
- MIC_CONTROL_PDM_EN_A(mic_a) |
- MIC_CONTROL_PDM_EN_B(mic_b));
-
- dmic_update_bits(dai, base[i] + FIR_CONTROL_A,
- FIR_CONTROL_A_START_BIT, FIR_CONTROL_A_START(fir_a));
- dmic_update_bits(dai, base[i] + FIR_CONTROL_B,
- FIR_CONTROL_B_START_BIT, FIR_CONTROL_B_START(fir_b));
- }
-
- /* Clear soft reset for all/used PDM controllers. This should
- * start capture in sync.
- */
- trace_dmic("unr");
- for (i = 0; i < DMIC_HW_CONTROLLERS; i++) {
- dmic_update_bits(dai, base[i] + CIC_CONTROL,
- CIC_CONTROL_SOFT_RESET_BIT, 0);
- }
-
- spin_unlock(&dmic->lock);
-
- /* Currently there's no DMIC HW internal mutings and wait times
- * applied into this start sequence. It can be implemented here if
- * start of audio capture would contain clicks and/or noise and it
- * is not suppressed by gain ramp somewhere in the capture pipe.
- */
-
- work_schedule_default(&dmic->dmicwork, DMIC_UNMUTE_RAMP_US);
-
- trace_dmic("run");
-}
-/* stop the DMIC for capture */
-static void dmic_stop(struct dai *dai)
-{
- struct dmic_pdata *dmic = dai_get_drvdata(dai);
- int i;
-
- trace_dmic("sto")
- spin_lock(&dmic->lock);
- dmic->state = COMP_STATE_PREPARE;
-
- /* Stop FIFO packers and set FIFO initialize bits */
- dmic_update_bits(dai, OUTCONTROL0,
- OUTCONTROL0_SIP_BIT | OUTCONTROL0_FINIT_BIT,
- OUTCONTROL0_FINIT_BIT);
- dmic_update_bits(dai, OUTCONTROL1,
- OUTCONTROL1_SIP_BIT | OUTCONTROL1_FINIT_BIT,
- OUTCONTROL1_FINIT_BIT);
-
- /* Set soft reset and mute on for all PDM controllers.
- */
- trace_dmic("sre");
- for (i = 0; i < DMIC_HW_CONTROLLERS; i++) {
- dmic_update_bits(dai, base[i] + CIC_CONTROL,
- CIC_CONTROL_SOFT_RESET_BIT |
- CIC_CONTROL_MIC_MUTE_BIT,
- CIC_CONTROL_SOFT_RESET_BIT |
- CIC_CONTROL_MIC_MUTE_BIT);
- dmic_update_bits(dai, base[i] + FIR_CONTROL_A,
- FIR_CONTROL_A_MUTE_BIT,
- FIR_CONTROL_A_MUTE_BIT);
- dmic_update_bits(dai, base[i] + FIR_CONTROL_B,
- FIR_CONTROL_B_MUTE_BIT,
- FIR_CONTROL_B_MUTE_BIT);
- }
-
- spin_unlock(&dmic->lock);
-}
-
-/* save DMIC context prior to entering D3 */
-static int dmic_context_store(struct dai *dai)
-{
- /* TODO: Nothing stored at the moment. Could read the registers into
- * persisten memory if needed but the large coef RAM is not desirable
- * to copy. It would be better to store selected mode parametesr from
- * previous configuration request and re-program registers from
- * scratch.
- */
- return 0;
-}
-
-/* restore DMIC context after leaving D3 */
-static int dmic_context_restore(struct dai *dai)
-{
- /* Nothing restored at the moment. */
- return 0;
-}
-
-static int dmic_trigger(struct dai *dai, int cmd, int direction)
-{
- struct dmic_pdata *dmic = dai_get_drvdata(dai);
-
- trace_dmic("tri");
-
- /* dai private is set in dmic_probe(), error if not set */
- if (!dmic) {
- trace_dmic_error("trn");
- return -EINVAL;
- }
-
- if (direction != DAI_DIR_CAPTURE) {
- trace_dmic_error("cap");
- return -EINVAL;
- }
-
- switch (cmd) {
- case COMP_TRIGGER_RELEASE:
- case COMP_TRIGGER_START:
- if (dmic->state == COMP_STATE_PREPARE ||
- dmic->state == COMP_STATE_PAUSED) {
- dmic_start(dai);
- } else {
- trace_dmic_error("cst");
- trace_value(dmic->state);
- }
- break;
- case COMP_TRIGGER_STOP:
- case COMP_TRIGGER_PAUSE:
- dmic_stop(dai);
- break;
- case COMP_TRIGGER_RESUME:
- dmic_context_restore(dai);
- break;
- case COMP_TRIGGER_SUSPEND:
- dmic_context_store(dai);
- break;
- default:
- break;
- }
-
- return 0;
-}
-
-/* On DMIC IRQ event trace the status register that contains the status and
- * error bit fields.
- */
-static void dmic_irq_handler(void *data)
-{
- struct dai *dai = data;
- uint32_t val;
-
- /* Trace OUTSTAT0 register */
- val = dmic_read(dai, OUTSTAT0);
- trace_dmic("irq");
-
- if (val & OUTSTAT0_ROR_BIT)
- trace_dmic_error("eor"); /* Full fifo or PDM overrrun */
-
- trace_value(val);
-
- /* clear IRQ */
- platform_interrupt_clear(dmic_irq(dai), 1);
-}
-
-static int dmic_probe(struct dai *dai)
-{
- struct dmic_pdata *dmic;
-
- trace_dmic("pro");
-
- /* allocate private data */
- dmic = rzalloc(RZONE_SYS, SOF_MEM_CAPS_RAM, sizeof(*dmic));
- dai_set_drvdata(dai, dmic);
-
- spinlock_init(&dmic->lock);
-
- /* Set state, note there is no playback direction support */
- dmic->state = COMP_STATE_READY;
-
- /* register our IRQ handler */
- interrupt_register(dmic_irq(dai), dmic_irq_handler, dai);
-
- platform_interrupt_unmask(dmic_irq(dai), 1);
- interrupt_enable(dmic_irq(dai));
-
- return 0;
-}
-
-/* DMIC has no loopback support */
-static inline int dmic_set_loopback_mode(struct dai *dai, uint32_t lbm)
-{
- return -EINVAL;
-}
-
-const struct dai_ops dmic_ops = {
- .trigger = dmic_trigger,
- .set_config = dmic_set_config,
- .pm_context_store = dmic_context_store,
- .pm_context_restore = dmic_context_restore,
- .probe = dmic_probe,
- .set_loopback_mode = dmic_set_loopback_mode,
-};
-
-#endif
diff --git a/src/drivers/dw-dma.c b/src/drivers/dw-dma.c
deleted file mode 100644
index 4d8da7e..0000000
--- a/src/drivers/dw-dma.c
+++ /dev/null
@@ -1,1263 +0,0 @@
-/*
- * Copyright (c) 2016, Intel Corporation
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- * * Redistributions of source code must retain the above copyright
- * notice, this list of conditions and the following disclaimer.
- * * Redistributions in binary form must reproduce the above copyright
- * notice, this list of conditions and the following disclaimer in the
- * documentation and/or other materials provided with the distribution.
- * * Neither the name of the Intel Corporation nor the
- * names of its contributors may be used to endorse or promote products
- * derived from this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
- * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
- * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
- * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
- * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
- * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
- * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
- * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
- * POSSIBILITY OF SUCH DAMAGE.
- *
- * Author: Liam Girdwood <liam.r.girdwood@linux.intel.com>
- * Keyon Jie <yang.jie@linux.intel.com>
- *
- *
- * This driver API will only be called by 3 clients in sof :-
- *
- * 1. Host audio component. This component represents the ALSA PCM device
- * and involves copying data to/from the host ALSA audio buffer to/from the
- * the DSP buffer.
- *
- * 2. DAI audio component. This component represents physical DAIs and involves
- * copying data to/from the DSP buffers to/from the DAI FIFOs.
- *
- * 3. IPC Layer. Some IPC needs DMA to copy audio buffer page table information
- * from the host DRAM into DSP DRAM. This page table information is then
- * used to construct the DMA configuration for the host client 1 above.
- */
-
-#include <sof/atomic.h>
-#include <sof/debug.h>
-#include <sof/sof.h>
-#include <sof/dma.h>
-#include <sof/dw-dma.h>
-#include <sof/io.h>
-#include <sof/stream.h>
-#include <sof/timer.h>
-#include <sof/alloc.h>
-#include <sof/interrupt.h>
-#include <sof/work.h>
-#include <sof/lock.h>
-#include <sof/trace.h>
-#include <sof/wait.h>
-#include <sof/audio/component.h>
-#include <platform/dma.h>
-#include <platform/platform.h>
-#include <platform/interrupt.h>
-#include <errno.h>
-#include <stdint.h>
-#include <string.h>
-#include <config.h>
-
-/* channel registers */
-#define DW_MAX_CHAN 8
-#define DW_CH_SIZE 0x58
-#define BYT_CHAN_OFFSET(chan) \
- (DW_CH_SIZE * chan)
-
-#define DW_SAR(chan) \
- (0x0000 + BYT_CHAN_OFFSET(chan))
-#define DW_DAR(chan) \
- (0x0008 + BYT_CHAN_OFFSET(chan))
-#define DW_LLP(chan) \
- (0x0010 + BYT_CHAN_OFFSET(chan))
-#define DW_CTRL_LOW(chan) \
- (0x0018 + BYT_CHAN_OFFSET(chan))
-#define DW_CTRL_HIGH(chan) \
- (0x001C + BYT_CHAN_OFFSET(chan))
-#define DW_CFG_LOW(chan) \
- (0x0040 + BYT_CHAN_OFFSET(chan))
-#define DW_CFG_HIGH(chan) \
- (0x0044 + BYT_CHAN_OFFSET(chan))
-
-/* registers */
-#define DW_RAW_TFR 0x02C0
-#define DW_RAW_BLOCK 0x02C8
-#define DW_RAW_SRC_TRAN 0x02D0
-#define DW_RAW_DST_TRAN 0x02D8
-#define DW_RAW_ERR 0x02E0
-#define DW_STATUS_TFR 0x02E8
-#define DW_STATUS_BLOCK 0x02F0
-#define DW_STATUS_SRC_TRAN 0x02F8
-#define DW_STATUS_DST_TRAN 0x0300
-#define DW_STATUS_ERR 0x0308
-#define DW_MASK_TFR 0x0310
-#define DW_MASK_BLOCK 0x0318
-#define DW_MASK_SRC_TRAN 0x0320
-#define DW_MASK_DST_TRAN 0x0328
-#define DW_MASK_ERR 0x0330
-#define DW_CLEAR_TFR 0x0338
-#define DW_CLEAR_BLOCK 0x0340
-#define DW_CLEAR_SRC_TRAN 0x0348
-#define DW_CLEAR_DST_TRAN 0x0350
-#define DW_CLEAR_ERR 0x0358
-#define DW_INTR_STATUS 0x0360
-#define DW_DMA_CFG 0x0398
-#define DW_DMA_CHAN_EN 0x03A0
-
-/* channel bits */
-#define INT_MASK(chan) (0x100 << chan)
-#define INT_UNMASK(chan) (0x101 << chan)
-#define INT_MASK_ALL 0xFF00
-#define INT_UNMASK_ALL 0xFFFF
-#define CHAN_ENABLE(chan) (0x101 << chan)
-#define CHAN_DISABLE(chan) (0x100 << chan)
-
-#define DW_CFG_CH_SUSPEND 0x100
-#define DW_CFG_CH_FIFO_EMPTY 0x200
-
-/* CTL_LO */
-#define DW_CTLL_INT_EN (1 << 0)
-#define DW_CTLL_DST_WIDTH(x) ((x) << 1)
-#define DW_CTLL_SRC_WIDTH(x) ((x) << 4)
-#define DW_CTLL_DST_INC (0 << 7)
-#define DW_CTLL_DST_DEC (1 << 7)
-#define DW_CTLL_DST_FIX (2 << 7)
-#define DW_CTLL_SRC_INC (0 << 9)
-#define DW_CTLL_SRC_DEC (1 << 9)
-#define DW_CTLL_SRC_FIX (2 << 9)
-#define DW_CTLL_DST_MSIZE(x) ((x) << 11)
-#define DW_CTLL_SRC_MSIZE(x) ((x) << 14)
-#define DW_CTLL_FC(x) ((x) << 20)
-#define DW_CTLL_FC_M2M (0 << 20)
-#define DW_CTLL_FC_M2P (1 << 20)
-#define DW_CTLL_FC_P2M (2 << 20)
-#define DW_CTLL_FC_P2P (3 << 20)
-#define DW_CTLL_DMS(x) ((x) << 23)
-#define DW_CTLL_SMS(x) ((x) << 25)
-#define DW_CTLL_LLP_D_EN (1 << 27)
-#define DW_CTLL_LLP_S_EN (1 << 28)
-#define DW_CTLL_RELOAD_SRC (1 << 30)
-#define DW_CTLL_RELOAD_DST (1 << 31)
-
-/* Haswell / Broadwell specific registers */
-#if defined (CONFIG_HASWELL) || defined (CONFIG_BROADWELL)
-
-/* CTL_HI */
-#define DW_CTLH_DONE(x) ((x) << 12)
-#define DW_CTLH_BLOCK_TS_MASK 0x00000fff
-
-/* CFG_LO */
-#define DW_CFG_CLASS(x) (x << 5)
-
-/* CFG_HI */
-#define DW_CFGH_SRC_PER(x) (x << 7)
-#define DW_CFGH_DST_PER(x) (x << 11)
-
-/* default initial setup register values */
-#define DW_CFG_LOW_DEF 0x0
-#define DW_CFG_HIGH_DEF 0x4
-
-#elif defined (CONFIG_BAYTRAIL) || defined (CONFIG_CHERRYTRAIL)
-/* baytrail specific registers */
-
-/* CTL_LO */
-#define DW_CTLL_S_GATH_EN (1 << 17)
-#define DW_CTLL_D_SCAT_EN (1 << 18)
-
-/* CTL_HI */
-#define DW_CTLH_DONE(x) ((x) << 17)
-#define DW_CTLH_BLOCK_TS_MASK 0x0001ffff
-#define DW_CTLH_CLASS(x) ((x) << 29)
-#define DW_CTLH_WEIGHT(x) ((x) << 18)
-
-/* CFG_LO */
-#define DW_CFG_CH_DRAIN 0x400
-
-/* CFG_HI */
-#define DW_CFGH_SRC_PER(x) ((x) << 0)
-#define DW_CFGH_DST_PER(x) ((x) << 4)
-
-/* FIFO Partition */
-#define DW_FIFO_PARTITION
-#define DW_FIFO_PART0_LO 0x0400
-#define DW_FIFO_PART0_HI 0x0404
-#define DW_FIFO_PART1_LO 0x0408
-#define DW_FIFO_PART1_HI 0x040C
-#define DW_CH_SAI_ERR 0x0410
-
-/* default initial setup register values */
-#define DW_CFG_LOW_DEF 0x00000003
-#define DW_CFG_HIGH_DEF 0x0
-
-#elif defined (CONFIG_APOLLOLAKE) || defined (CONFIG_CANNONLAKE)
-
-/* CTL_LO */
-#define DW_CTLL_S_GATH_EN (1 << 17)
-#define DW_CTLL_D_SCAT_EN (1 << 18)
-
-/* CTL_HI */
-#define DW_CTLH_DONE(x) ((x) << 17)
-#define DW_CTLH_BLOCK_TS_MASK 0x0001ffff
-#define DW_CTLH_CLASS(x) ((x) << 29)
-#define DW_CTLH_WEIGHT(x) ((x) << 18)
-
-/* CFG_LO */
-#define DW_CFG_CTL_HI_UPD_EN (1 << 5)
-#define DW_CFG_CH_DRAIN (1 << 10)
-#define DW_CFG_RELOAD_SRC (1 << 30)
-#define DW_CFG_RELOAD_DST (1 << 31)
-
-/* CFG_HI */
-#define DW_CFGH_SRC_PER(x) (x << 0)
-#define DW_CFGH_DST_PER(x) (x << 4)
-
-/* FIFO Partition */
-#define DW_FIFO_PARTITION
-#define DW_FIFO_PART0_LO 0x0400
-#define DW_FIFO_PART0_HI 0x0404
-#define DW_FIFO_PART1_LO 0x0408
-#define DW_FIFO_PART1_HI 0x040C
-#define DW_CH_SAI_ERR 0x0410
-#define DW_DMA_GLB_CFG 0x0418
-
-/* default initial setup register values */
-#define DW_CFG_LOW_DEF 0x00000003
-#define DW_CFG_HIGH_DEF 0x0
-
-#define DW_REG_MAX DW_DMA_GLB_CFG
-#endif
-
-/* tracing */
-#define trace_dma(__e) trace_event(TRACE_CLASS_DMA, __e)
-#define trace_dma_error(__e) trace_error(TRACE_CLASS_DMA, __e)
-#define tracev_dma(__e) tracev_event(TRACE_CLASS_DMA, __e)
-
-/* HW Linked list support, only enabled for APL/CNL at the moment */
-#if defined CONFIG_APOLLOLAKE || defined CONFIG_CANNONLAKE
-#define DW_USE_HW_LLI 1
-#else
-#define DW_USE_HW_LLI 0
-#endif
-
-/* number of tries to wait for reset */
-#define DW_DMA_CFG_TRIES 10000
-
-/* data for each DMA channel */
-struct dma_chan_data {
- uint32_t status;
- uint32_t direction;
- struct dw_lli2 *lli;
- struct dw_lli2 *lli_current;
- uint32_t desc_count;
- uint32_t cfg_lo;
- uint32_t cfg_hi;
- struct dma *dma;
- int32_t channel;
-
- void (*cb)(void *data, uint32_t type, struct dma_sg_elem *next); /* client callback function */
- void *cb_data; /* client callback data */
- int cb_type; /* callback type */
-};
-
-/* private data for DW DMA engine */
-struct dma_pdata {
- struct dma_chan_data chan[DW_MAX_CHAN];
- uint32_t class; /* channel class - set for controller atm */
-};
-
-static inline void dw_dma_chan_reload_lli(struct dma *dma, int channel);
-static inline void dw_dma_chan_reload_next(struct dma *dma, int channel,
- struct dma_sg_elem *next);
-
-static inline void dw_write(struct dma *dma, uint32_t reg, uint32_t value)
-{
- io_reg_write(dma_base(dma) + reg, value);
-}
-
-static inline uint32_t dw_read(struct dma *dma, uint32_t reg)
-{
- return io_reg_read(dma_base(dma) + reg);
-}
-
-static inline void dw_update_bits(struct dma *dma, uint32_t reg, uint32_t mask,
- uint32_t value)
-{
- io_reg_update_bits(dma_base(dma) + reg, mask, value);
-}
-
-/* allocate next free DMA channel */
-static int dw_dma_channel_get(struct dma *dma, int req_chan)
-{
- struct dma_pdata *p = dma_get_drvdata(dma);
- uint32_t flags;
- int i;
-
- spin_lock_irq(&dma->lock, flags);
-
- trace_dma("Dgt");
-
- /* find first free non draining channel */
- for (i = 0; i < DW_MAX_CHAN; i++) {
-
- /* use channel if it's free */
- if (p->chan[i].status != COMP_STATE_INIT)
- continue;
-
- p->chan[i].status = COMP_STATE_READY;
-
- atomic_add(&dma->num_channels_busy, 1);
-
- /* unmask block, transfer and error interrupts for channel */
- dw_write(dma, DW_MASK_TFR, INT_UNMASK(i));
- dw_write(dma, DW_MASK_BLOCK, INT_UNMASK(i));
- dw_write(dma, DW_MASK_ERR, INT_UNMASK(i));
-
- /* return channel */
- spin_unlock_irq(&dma->lock, flags);
- return i;
- }
-
- /* DMAC has no free channels */
- spin_unlock_irq(&dma->lock, flags);
- trace_dma_error("eG0");
- return -ENODEV;
-}
-
-/* channel must not be running when this is called */
-static void dw_dma_channel_put_unlocked(struct dma *dma, int channel)
-{
- struct dma_pdata *p = dma_get_drvdata(dma);
-
- tracev_dma("Dpt");
-
- /* mask block, transfer and error interrupts for channel */
- dw_write(dma, DW_MASK_TFR, INT_MASK(channel));
- dw_write(dma, DW_MASK_BLOCK, INT_MASK(channel));
- dw_write(dma, DW_MASK_ERR, INT_MASK(channel));
-
- /* free the lli allocated by set_config*/
- if (p->chan[channel].lli) {
- rfree(p->chan[channel].lli);
- p->chan[channel].lli = NULL;
- }
-
- /* set new state */
- p->chan[channel].status = COMP_STATE_INIT;
- p->chan[channel].cb = NULL;
- p->chan[channel].desc_count = 0;
-
- atomic_sub(&dma->num_channels_busy, 1);
-}
-
-/* channel must not be running when this is called */
-static void dw_dma_channel_put(struct dma *dma, int channel)
-{
- uint32_t flags;
-
- spin_lock_irq(&dma->lock, flags);
- dw_dma_channel_put_unlocked(dma, channel);
- spin_unlock_irq(&dma->lock, flags);
-}
-
-static int dw_dma_start(struct dma *dma, int channel)
-{
- struct dma_pdata *p = dma_get_drvdata(dma);
- uint32_t flags;
- int ret = 0;
-
- spin_lock_irq(&dma->lock, flags);
-
- tracev_dma("DEn");
-
- /* is channel idle, disabled and ready ? */
- if (p->chan[channel].status != COMP_STATE_PREPARE ||
- (dw_read(dma, DW_DMA_CHAN_EN) & (0x1 << channel))) {
- ret = -EBUSY;
- trace_dma_error("eS0");
- trace_error_value(dw_read(dma, DW_DMA_CHAN_EN));
- trace_error_value(dw_read(dma, DW_CFG_LOW(channel)));
- trace_error_value(p->chan[channel].status);
- goto out;
- }
-
- /* valid stream ? */
- if (p->chan[channel].lli == NULL) {
- ret = -EINVAL;
- trace_dma_error("eS1");
- goto out;
- }
-
- /* write interrupt clear registers for the channel:
- ClearTfr, ClearBlock, ClearSrcTran, ClearDstTran, ClearErr*/
- dw_write(dma, DW_CLEAR_TFR, 0x1 << channel);
- dw_write(dma, DW_CLEAR_BLOCK, 0x1 << channel);
- dw_write(dma, DW_CLEAR_SRC_TRAN, 0x1 << channel);
- dw_write(dma, DW_CLEAR_DST_TRAN, 0x1 << channel);
- dw_write(dma, DW_CLEAR_ERR, 0x1 << channel);
-
- /* clear platform interrupt */
- platform_interrupt_clear(dma_irq(dma), 1 << channel);
-
-#if DW_USE_HW_LLI
- /* TODO: Revisit: are we using LLP mode or single transfer ? */
- if (p->chan[channel].lli_current) {
- /* LLP mode - write LLP pointer */
- dw_write(dma, DW_LLP(channel),
- (uint32_t)p->chan[channel].lli_current);
- }
-#endif
- /* channel needs started from scratch, so write SARn, DARn */
- dw_write(dma, DW_SAR(channel), p->chan[channel].lli_current->sar);
- dw_write(dma, DW_DAR(channel), p->chan[channel].lli_current->dar);
-
- /* program CTLn */
- dw_write(dma, DW_CTRL_LOW(channel),
- p->chan[channel].lli_current->ctrl_lo);
- dw_write(dma, DW_CTRL_HIGH(channel),
- p->chan[channel].lli_current->ctrl_hi);
-
- /* write channel config */
- dw_write(dma, DW_CFG_LOW(channel), p->chan[channel].cfg_lo);
- dw_write(dma, DW_CFG_HIGH(channel), p->chan[channel].cfg_hi);
-
- /* enable the channel */
- p->chan[channel].status = COMP_STATE_ACTIVE;
- dw_write(dma, DW_DMA_CHAN_EN, CHAN_ENABLE(channel));
-
-out:
- spin_unlock_irq(&dma->lock, flags);
- return ret;
-}
-
-static int dw_dma_release(struct dma *dma, int channel)
-{
- struct dma_pdata *p = dma_get_drvdata(dma);
- struct dw_lli2 *lli;
- uint32_t flags;
-
- spin_lock_irq(&dma->lock, flags);
-
- trace_dma("Dpr");
-
- /* get current lli */
-#if DW_USE_HW_LLI
- lli = (struct dw_lli2 *)dw_read(dma, DW_LLP(channel));
-#else
- lli = p->chan[channel].lli_current;
-#endif
- /* get next lli and recover the lli to head for restart */
- lli = (struct dw_lli2 *)lli->llp;
- p->chan[channel].lli = lli;
-
- spin_unlock_irq(&dma->lock, flags);
- return 0;
-}
-
-static int dw_dma_pause(struct dma *dma, int channel)
-{
- struct dma_pdata *p = dma_get_drvdata(dma);
- uint32_t flags;
-
- spin_lock_irq(&dma->lock, flags);
-
- trace_dma("Dpa");
-
- if (p->chan[channel].status != COMP_STATE_ACTIVE)
- goto out;
-
- /* pause the channel */
- p->chan[channel].status = COMP_STATE_PAUSED;
-
-out:
- spin_unlock_irq(&dma->lock, flags);
- return 0;
-}
-
-static int dw_dma_stop(struct dma *dma, int channel)
-{
- struct dma_pdata *p = dma_get_drvdata(dma);
- int ret = 0;
- uint32_t flags;
-#if DW_USE_HW_LLI
- int i = 0;
- struct dw_lli2 *lli;
-#endif
-
- spin_lock_irq(&dma->lock, flags);
-
- trace_dma("DDi");
-
- dw_write(dma, DW_DMA_CHAN_EN, CHAN_DISABLE(channel));
-
-#if DW_USE_HW_LLI
- for (i = 0; i < p->chan[channel].desc_count; i++) {
- lli = p->chan[channel].lli;
- lli->ctrl_hi &= ~DW_CTLH_DONE(1);
- lli++;
- }
-
- dcache_writeback_region(p->chan[channel].lli,
- sizeof(struct dw_lli2) * p->chan[channel].desc_count);
-#endif
-
- dw_write(dma, DW_CLEAR_BLOCK, 0x1 << channel);
-
- p->chan[channel].status = COMP_STATE_PREPARE;
-
- spin_unlock_irq(&dma->lock, flags);
- return ret;
-}
-
-/* fill in "status" with current DMA channel state and position */
-static int dw_dma_status(struct dma *dma, int channel,
- struct dma_chan_status *status, uint8_t direction)
-{
- struct dma_pdata *p = dma_get_drvdata(dma);
-
- status->state = p->chan[channel].status;
- status->r_pos = dw_read(dma, DW_SAR(channel));
- status->w_pos = dw_read(dma, DW_DAR(channel));
- status->timestamp = timer_get_system(platform_timer);
-
- return 0;
-}
-
-/*
- * use array to get burst_elems for specific slot number setting.
- * the relation between msize and burst_elems should be
- * 2 ^ burst_elems = burst_elems
- */
-static const uint32_t burst_elems[] = {1, 2, 4, 8};
-
-/* set the DMA channel configuration, source/target address, buffer sizes */
-static int dw_dma_set_config(struct dma *dma, int channel,
- struct dma_sg_config *config)
-{
- struct dma_pdata *p = dma_get_drvdata(dma);
- struct list_item *plist;
- struct dma_sg_elem *sg_elem;
- struct dw_lli2 *lli_desc;
- struct dw_lli2 *lli_desc_head;
- struct dw_lli2 *lli_desc_tail;
- uint32_t desc_count = 0;
- uint32_t flags;
- uint32_t msize = 3;/* default msize */
- int i, ret = 0;
-
- spin_lock_irq(&dma->lock, flags);
-
- tracev_dma("Dsc");
-
- /* default channel config */
- p->chan[channel].direction = config->direction;
- p->chan[channel].cfg_lo = DW_CFG_LOW_DEF;
- p->chan[channel].cfg_hi = DW_CFG_HIGH_DEF;
-
- /* get number of SG elems */
- list_for_item(plist, &config->elem_list)
- desc_count++;
-
- if (desc_count == 0) {
- trace_dma_error("eD0");
- ret = -EINVAL;
- goto out;
- }
-
- /* do we need to realloc descriptors */
- if (desc_count != p->chan[channel].desc_count) {
-
- p->chan[channel].desc_count = desc_count;
-
- /* allocate descriptors for channel */
- if (p->chan[channel].lli)
- rfree(p->chan[channel].lli);
- p->chan[channel].lli = rzalloc(RZONE_RUNTIME,
- SOF_MEM_CAPS_RAM | SOF_MEM_CAPS_DMA,
- sizeof(struct dw_lli2) * p->chan[channel].desc_count);
- if (p->chan[channel].lli == NULL) {
- trace_dma_error("eD1");
- ret = -ENOMEM;
- goto out;
- }
- }
-
- /* initialise descriptors */
- bzero(p->chan[channel].lli, sizeof(struct dw_lli2) *
- p->chan[channel].desc_count);
- lli_desc = lli_desc_head = p->chan[channel].lli;
- lli_desc_tail = p->chan[channel].lli + p->chan[channel].desc_count - 1;
-
- /* configure msize if burst_elems is set */
- if (config->burst_elems) {
- /* burst_elems set, configure msize */
- for (i = 0; i < ARRAY_SIZE(burst_elems); i++) {
- if (burst_elems[i] == config->burst_elems) {
- msize = i;
- break;
- }
- }
- }
-
- /* fill in lli for the elem in the list */
- list_for_item(plist, &config->elem_list) {
-
- sg_elem = container_of(plist, struct dma_sg_elem, list);
-
- /* write CTL_LOn for each lli */
- switch (config->src_width) {
- case 2:
- /* non peripheral copies are optimal using words */
- switch (config->direction) {
- case DMA_DIR_LMEM_TO_HMEM:
- case DMA_DIR_HMEM_TO_LMEM:
- case DMA_DIR_MEM_TO_MEM:
- /* config the src tr width for 32 bit words */
- lli_desc->ctrl_lo |= DW_CTLL_SRC_WIDTH(2);
- break;
- default:
- /* config the src width for 16 bit samples */
- lli_desc->ctrl_lo |= DW_CTLL_SRC_WIDTH(1);
- break;
- }
- break;
- case 4:
- /* config the src tr width for 24, 32 bit samples */
- lli_desc->ctrl_lo |= DW_CTLL_SRC_WIDTH(2);
- break;
- default:
- trace_dma_error("eD2");
- ret = -EINVAL;
- goto out;
- }
-
- switch (config->dest_width) {
- case 2:
- /* non peripheral copies are optimal using words */
- switch (config->direction) {
- case DMA_DIR_LMEM_TO_HMEM:
- case DMA_DIR_HMEM_TO_LMEM:
- case DMA_DIR_MEM_TO_MEM:
- /* config the dest tr width for 32 bit words */
- lli_desc->ctrl_lo |= DW_CTLL_DST_WIDTH(2);
- break;
- default:
- /* config the dest width for 16 bit samples */
- lli_desc->ctrl_lo |= DW_CTLL_DST_WIDTH(1);
- break;
- }
- break;
- case 4:
- /* config the dest tr width for 24, 32 bit samples */
- lli_desc->ctrl_lo |= DW_CTLL_DST_WIDTH(2);
- break;
- default:
- trace_dma_error("eD3");
- ret = -EINVAL;
- goto out;
- }
-
- lli_desc->ctrl_lo |= DW_CTLL_SRC_MSIZE(msize);
- lli_desc->ctrl_lo |= DW_CTLL_DST_MSIZE(msize);
- lli_desc->ctrl_lo |= DW_CTLL_INT_EN; /* enable interrupt */
-
- /* config the SINC and DINC field of CTL_LOn, SRC/DST_PER filed of CFGn */
- switch (config->direction) {
- case DMA_DIR_LMEM_TO_HMEM:
- lli_desc->ctrl_lo |= DW_CTLL_FC_M2M;
- lli_desc->ctrl_lo |= DW_CTLL_SRC_INC | DW_CTLL_DST_INC;
-#if DW_USE_HW_LLI
- lli_desc->ctrl_lo |=
- DW_CTLL_LLP_S_EN | DW_CTLL_LLP_D_EN;
-#endif
- lli_desc->sar =
- (uint32_t)sg_elem->src | PLATFORM_HOST_DMA_MASK;
- lli_desc->dar = (uint32_t)sg_elem->dest;
- break;
- case DMA_DIR_HMEM_TO_LMEM:
- lli_desc->ctrl_lo |= DW_CTLL_FC_M2M;
- lli_desc->ctrl_lo |= DW_CTLL_SRC_INC | DW_CTLL_DST_INC;
-#if DW_USE_HW_LLI
- lli_desc->ctrl_lo |=
- DW_CTLL_LLP_S_EN | DW_CTLL_LLP_D_EN;
-#endif
- lli_desc->dar =
- (uint32_t)sg_elem->dest | PLATFORM_HOST_DMA_MASK;
- lli_desc->sar = (uint32_t)sg_elem->src;
- break;
- case DMA_DIR_MEM_TO_MEM:
- lli_desc->ctrl_lo |= DW_CTLL_FC_M2M;
- lli_desc->ctrl_lo |= DW_CTLL_SRC_INC | DW_CTLL_DST_INC;
-#if DW_USE_HW_LLI
- lli_desc->ctrl_lo |=
- DW_CTLL_LLP_S_EN | DW_CTLL_LLP_D_EN;
-#endif
- lli_desc->sar = (uint32_t)sg_elem->src | PLATFORM_HOST_DMA_MASK;
- lli_desc->dar = (uint32_t)sg_elem->dest | PLATFORM_HOST_DMA_MASK;
- break;
- case DMA_DIR_MEM_TO_DEV:
- lli_desc->ctrl_lo |= DW_CTLL_FC_M2P;
- lli_desc->ctrl_lo |= DW_CTLL_SRC_INC | DW_CTLL_DST_FIX;
-#if DW_USE_HW_LLI
- lli_desc->ctrl_lo |= DW_CTLL_LLP_S_EN;
- lli_desc->ctrl_hi |= DW_CTLH_DONE(1);
- p->chan[channel].cfg_lo |= DW_CFG_RELOAD_DST;
-#endif
- p->chan[channel].cfg_hi |=
- DW_CFGH_DST_PER(config->dest_dev);
- lli_desc->sar = (uint32_t)sg_elem->src | PLATFORM_HOST_DMA_MASK;
- lli_desc->dar = (uint32_t)sg_elem->dest;
- break;
- case DMA_DIR_DEV_TO_MEM:
- lli_desc->ctrl_lo |= DW_CTLL_FC_P2M;
- lli_desc->ctrl_lo |= DW_CTLL_SRC_FIX | DW_CTLL_DST_INC;
-#if DW_USE_HW_LLI
- lli_desc->ctrl_lo |= DW_CTLL_LLP_D_EN;
- lli_desc->ctrl_hi |= DW_CTLH_DONE(0);
- p->chan[channel].cfg_lo |= DW_CFG_RELOAD_SRC;
-#endif
- p->chan[channel].cfg_hi |=
- DW_CFGH_SRC_PER(config->src_dev);
- lli_desc->sar = (uint32_t)sg_elem->src;
- lli_desc->dar = (uint32_t)sg_elem->dest | PLATFORM_HOST_DMA_MASK;
- break;
- case DMA_DIR_DEV_TO_DEV:
- lli_desc->ctrl_lo |= DW_CTLL_FC_P2P;
- lli_desc->ctrl_lo |= DW_CTLL_SRC_FIX | DW_CTLL_DST_FIX;
-#if DW_USE_HW_LLI
- lli_desc->ctrl_lo |=
- DW_CTLL_LLP_S_EN | DW_CTLL_LLP_D_EN;
-#endif
- p->chan[channel].cfg_hi |=
- DW_CFGH_SRC_PER(config->src_dev) |
- DW_CFGH_DST_PER(config->dest_dev);
- lli_desc->sar = (uint32_t)sg_elem->src;
- lli_desc->dar = (uint32_t)sg_elem->dest;
- break;
- default:
- trace_dma_error("eD4");
- ret = -EINVAL;
- goto out;
- }
-
- if (sg_elem->size > DW_CTLH_BLOCK_TS_MASK) {
- trace_dma_error("eD5");
- ret = -EINVAL;
- goto out;
- }
-
- /* set transfer size of element */
-#if defined CONFIG_BAYTRAIL || defined CONFIG_CHERRYTRAIL \
- || defined CONFIG_APOLLOLAKE || defined CONFIG_CANNONLAKE
- lli_desc->ctrl_hi = DW_CTLH_CLASS(p->class) |
- (sg_elem->size & DW_CTLH_BLOCK_TS_MASK);
-#elif defined CONFIG_BROADWELL || defined CONFIG_HASWELL
- /* for bdw, the unit is transaction--TR_WIDTH. */
- lli_desc->ctrl_hi = (sg_elem->size / (1 << (lli_desc->ctrl_lo >> 4 & 0x7)))
- & DW_CTLH_BLOCK_TS_MASK;
-#endif
-
- /* set next descriptor in list */
- lli_desc->llp = (uint32_t)(lli_desc + 1);
-
- /* next descriptor */
- lli_desc++;
- }
-
-#if DW_USE_HW_LLI
- p->chan[channel].cfg_lo |= DW_CFG_CTL_HI_UPD_EN;
-#endif
-
- /* end of list or cyclic buffer ? */
- if (config->cyclic) {
- lli_desc_tail->llp = (uint32_t)lli_desc_head;
- } else {
- lli_desc_tail->llp = 0x0;
-#if DW_USE_HW_LLI
- lli_desc_tail->ctrl_lo &=
- ~(DW_CTLL_LLP_S_EN | DW_CTLL_LLP_D_EN);
-#endif
- }
-
- /* write back descriptors so DMA engine can read them directly */
- dcache_writeback_region(p->chan[channel].lli,
- sizeof(struct dw_lli2) * p->chan[channel].desc_count);
-
- p->chan[channel].status = COMP_STATE_PREPARE;
- p->chan[channel].lli_current = p->chan[channel].lli;
-out:
- spin_unlock_irq(&dma->lock, flags);
- return ret;
-}
-
-/* restore DMA conext after leaving D3 */
-static int dw_dma_pm_context_restore(struct dma *dma)
-{
- return 0;
-}
-
-/* store DMA conext after leaving D3 */
-static int dw_dma_pm_context_store(struct dma *dma)
-{
- /* disable the DMA controller */
- dw_write(dma, DW_DMA_CFG, 0);
-
- return 0;
-}
-
-static int dw_dma_set_cb(struct dma *dma, int channel, int type,
- void (*cb)(void *data, uint32_t type, struct dma_sg_elem *next),
- void *data)
-{
- struct dma_pdata *p = dma_get_drvdata(dma);
- uint32_t flags;
-
- spin_lock_irq(&dma->lock, flags);
- p->chan[channel].cb = cb;
- p->chan[channel].cb_data = data;
- p->chan[channel].cb_type = type;
- spin_unlock_irq(&dma->lock, flags);
-
- return 0;
-}
-
-/* reload using LLI data */
-static inline void dw_dma_chan_reload_lli(struct dma *dma, int channel)
-{
- struct dma_pdata *p = dma_get_drvdata(dma);
- struct dw_lli2 *lli = p->chan[channel].lli_current;
-
- /* only need to reload if this is a block transfer */
- if (!lli || lli->llp == 0) {
- p->chan[channel].status = COMP_STATE_PREPARE;
- return;
- }
-
- /* get current and next block pointers */
- lli = (struct dw_lli2 *)lli->llp;
- p->chan[channel].lli_current = lli;
-
- /* channel needs started from scratch, so write SARn, DARn */
- dw_write(dma, DW_SAR(channel), lli->sar);
- dw_write(dma, DW_DAR(channel), lli->dar);
-
- /* program CTLn */
- dw_write(dma, DW_CTRL_LOW(channel), lli->ctrl_lo);
- dw_write(dma, DW_CTRL_HIGH(channel), lli->ctrl_hi);
-
- /* program CFGn */
- dw_write(dma, DW_CFG_LOW(channel), p->chan[channel].cfg_lo);
- dw_write(dma, DW_CFG_HIGH(channel), p->chan[channel].cfg_hi);
-
- /* enable the channel */
- dw_write(dma, DW_DMA_CHAN_EN, CHAN_ENABLE(channel));
-}
-
-/* reload using callback data */
-static inline void dw_dma_chan_reload_next(struct dma *dma, int channel,
- struct dma_sg_elem *next)
-{
- struct dma_pdata *p = dma_get_drvdata(dma);
- struct dw_lli2 *lli = p->chan[channel].lli_current;
-
- /* channel needs started from scratch, so write SARn, DARn */
- dw_write(dma, DW_SAR(channel), next->src);
- dw_write(dma, DW_DAR(channel), next->dest);
-
- /* set transfer size of element */
-#if defined CONFIG_BAYTRAIL || defined CONFIG_CHERRYTRAIL \
- || defined CONFIG_APOLLOLAKE || defined CONFIG_CANNONLAKE
- lli->ctrl_hi = DW_CTLH_CLASS(p->class) |
- (next->size & DW_CTLH_BLOCK_TS_MASK);
-#elif defined CONFIG_BROADWELL || defined CONFIG_HASWELL
- /* for the unit is transaction--TR_WIDTH. */
- lli->ctrl_hi = (next->size / (1 << (lli->ctrl_lo >> 4 & 0x7)))
- & DW_CTLH_BLOCK_TS_MASK;
-#endif
-
- /* program CTLn */
- dw_write(dma, DW_CTRL_LOW(channel), lli->ctrl_lo);
- dw_write(dma, DW_CTRL_HIGH(channel), lli->ctrl_hi);
-
- /* program CFGn */
- dw_write(dma, DW_CFG_LOW(channel), p->chan[channel].cfg_lo);
- dw_write(dma, DW_CFG_HIGH(channel), p->chan[channel].cfg_hi);
-
- /* enable the channel */
- dw_write(dma, DW_DMA_CHAN_EN, CHAN_ENABLE(channel));
-}
-
-static void dw_dma_setup(struct dma *dma)
-{
- struct dw_drv_plat_data *dp = dma->plat_data.drv_plat_data;
- int i;
-
- /* we cannot config DMAC if DMAC has been already enabled by host */
- if (dw_read(dma, DW_DMA_CFG) != 0)
- dw_write(dma, DW_DMA_CFG, 0x0);
-
- /* now check that it's 0 */
- for (i = DW_DMA_CFG_TRIES; i > 0; i--) {
- if (dw_read(dma, DW_DMA_CFG) == 0)
- goto found;
- }
- trace_dma_error("eDs");
- return;
-
-found:
- for (i = 0; i < DW_MAX_CHAN; i++)
- dw_read(dma, DW_DMA_CHAN_EN);
-
-#ifdef HAVE_HDDA
- /* enable HDDA before DMAC */
- shim_write(SHIM_HMDC, SHIM_HMDC_HDDA_ALLCH);
-#endif
-
- /* enable the DMA controller */
- dw_write(dma, DW_DMA_CFG, 1);
-
- /* mask all interrupts for all 8 channels */
- dw_write(dma, DW_MASK_TFR, INT_MASK_ALL);
- dw_write(dma, DW_MASK_BLOCK, INT_MASK_ALL);
- dw_write(dma, DW_MASK_SRC_TRAN, INT_MASK_ALL);
- dw_write(dma, DW_MASK_DST_TRAN, INT_MASK_ALL);
- dw_write(dma, DW_MASK_ERR, INT_MASK_ALL);
-
-#ifdef DW_FIFO_PARTITION
- /* TODO: we cannot config DMA FIFOs if DMAC has been already */
- /* allocate FIFO partitions, 128 bytes for each ch */
- dw_write(dma, DW_FIFO_PART1_LO, 0x100080);
- dw_write(dma, DW_FIFO_PART1_HI, 0x100080);
- dw_write(dma, DW_FIFO_PART0_HI, 0x100080);
- dw_write(dma, DW_FIFO_PART0_LO, 0x100080 | (1 << 26));
- dw_write(dma, DW_FIFO_PART0_LO, 0x100080);
-#endif
-
- /* set channel priorities */
- for (i = 0; i < DW_MAX_CHAN; i++) {
-#if defined CONFIG_BAYTRAIL || defined CONFIG_CHERRYTRAIL ||\
- defined CONFIG_APOLLOLAKE || defined CONFIG_CANNONLAKE
- dw_write(dma, DW_CTRL_HIGH(i),
- DW_CTLH_CLASS(dp->chan[i].class));
-#elif defined CONFIG_BROADWELL || defined CONFIG_HASWELL
- dw_write(dma, DW_CFG_LOW(i),
- DW_CFG_CLASS(dp->chan[i].class));
-#endif
- }
-}
-
-#ifdef CONFIG_APOLLOLAKE
-/* external layer 2 interrupt for dmac */
-static void dw_dma_irq_handler(void *data)
-{
- struct dma_int *dma_int = (struct dma_int *)data;
- struct dma *dma = dma_int->dma;
- struct dma_pdata *p = dma_get_drvdata(dma);
- struct dma_sg_elem next;
- uint32_t status_tfr = 0, status_block = 0, status_err = 0, status_intr;
- uint32_t mask;
- int i = dma_int->channel;
-
- status_intr = dw_read(dma, DW_INTR_STATUS);
- if (!status_intr) {
- trace_dma_error("eDI");
- trace_error_value(status_intr);
- }
-
- tracev_dma("irq");
-
- /* get the source of our IRQ. */
- status_block = dw_read(dma, DW_STATUS_BLOCK);
- status_tfr = dw_read(dma, DW_STATUS_TFR);
-
- /* TODO: handle errors, just clear them atm */
- status_err = dw_read(dma, DW_STATUS_ERR);
- if (status_err) {
- trace_dma_error("eDi");
- dw_write(dma, DW_CLEAR_ERR, status_err & i);
- }
-
- mask = 0x1 << i;
-
- /* clear interrupts for channel*/
- dw_write(dma, DW_CLEAR_BLOCK, status_block & mask);
- dw_write(dma, DW_CLEAR_TFR, status_tfr & mask);
-
- /* skip if channel is not running */
- if (p->chan[i].status != COMP_STATE_ACTIVE) {
- trace_dma_error("eDs");
- return;
- }
-
-#if DW_USE_HW_LLI
- /* end of a LLI block */
- if (status_block & mask &&
- p->chan[i].cb_type & DMA_IRQ_TYPE_BLOCK) {
- next.src = DMA_RELOAD_LLI;
- next.dest = DMA_RELOAD_LLI;
- /* will reload lli by default */
- next.size = DMA_RELOAD_LLI;
- p->chan[i].cb(p->chan[i].cb_data,
- DMA_IRQ_TYPE_BLOCK, &next);
- if (next.size == DMA_RELOAD_END) {
- trace_dma("LSo");
- /* disable channel, finished */
- dw_write(dma, DW_DMA_CHAN_EN, CHAN_DISABLE(i));
- p->chan[i].status = COMP_STATE_PREPARE;
- }
-
- p->chan[i].lli_current->ctrl_hi &= ~DW_CTLH_DONE(1);
- dcache_writeback_region(p->chan[i].lli_current,
- sizeof(*p->chan[i].lli_current));
-
- p->chan[i].lli_current =
- (struct dw_lli2 *)p->chan[i].lli_current->llp;
- }
-#endif
- /* end of a transfer */
- if ((status_tfr & mask) &&
- (p->chan[i].cb_type & DMA_IRQ_TYPE_LLIST)) {
- trace_value(status_tfr);
-
- next.src = DMA_RELOAD_LLI;
- next.dest = DMA_RELOAD_LLI;
- next.size = DMA_RELOAD_LLI; /* will reload lli by default */
- if (p->chan[i].cb)
- p->chan[i].cb(p->chan[i].cb_data,
- DMA_IRQ_TYPE_LLIST, &next);
-
- /* check for reload channel:
- * next.size is DMA_RELOAD_END, stop this dma copy;
- * next.size > 0 but not DMA_RELOAD_LLI, use next
- * element for next copy;
- * if we are waiting for pause, pause it;
- * otherwise, reload lli
- */
- switch (next.size) {
- case DMA_RELOAD_END:
- p->chan[i].status = COMP_STATE_PREPARE;
- break;
- case DMA_RELOAD_LLI:
- /* reload lli, but let's check if it is paused */
- if (p->chan[i].status != COMP_STATE_PAUSED)
- dw_dma_chan_reload_lli(dma, i);
- break;
- default:
- dw_dma_chan_reload_next(dma, i, &next);
- break;
- }
- }
-}
-
-static int dw_dma_probe(struct dma *dma)
-{
- struct dma_int *dma_int[DW_MAX_CHAN];
- struct dma_pdata *dw_pdata;
- int i;
-
- /* allocate private data */
- dw_pdata = rzalloc(RZONE_SYS, SOF_MEM_CAPS_RAM, sizeof(*dw_pdata));
- dma_set_drvdata(dma, dw_pdata);
-
- spinlock_init(&dma->lock);
-
- dw_dma_setup(dma);
-
- /* init work */
- for (i = 0; i < dma->plat_data.channels; i++) {
- dw_pdata->chan[i].dma = dma;
- dw_pdata->chan[i].channel = i;
- dw_pdata->chan[i].status = COMP_STATE_INIT;
-
- dma_int[i] = rzalloc(RZONE_SYS, SOF_MEM_CAPS_RAM,
- sizeof(struct dma_int));
-
- dma_int[i]->dma = dma;
- dma_int[i]->channel = i;
- dma_int[i]->irq = dma->plat_data.irq +
- (i << SOF_IRQ_BIT_SHIFT);
-
- /* register our IRQ handler */
- interrupt_register(dma_int[i]->irq,
- dw_dma_irq_handler,
- dma_int[i]);
- interrupt_enable(dma_int[i]->irq);
- }
-
- /* init number of channels draining */
- atomic_init(&dma->num_channels_busy, 0);
-
- return 0;
-}
-
-#else
-
-/* this will probably be called at the end of every period copied */
-static void dw_dma_irq_handler(void *data)
-{
- struct dma *dma = (struct dma *)data;
- struct dma_pdata *p = dma_get_drvdata(dma);
- struct dma_sg_elem next;
- uint32_t status_tfr = 0;
- uint32_t status_block = 0;
- uint32_t status_block_new = 0;
- uint32_t status_err = 0;
- uint32_t status_intr;
- uint32_t mask;
- uint32_t pmask;
- int i;
-
- status_intr = dw_read(dma, DW_INTR_STATUS);
- if (!status_intr) {
- return;
- }
-
- tracev_dma("DIr");
-
- /* get the source of our IRQ. */
- status_block = dw_read(dma, DW_STATUS_BLOCK);
- status_tfr = dw_read(dma, DW_STATUS_TFR);
-
- /* clear interrupts */
- dw_write(dma, DW_CLEAR_BLOCK, status_block);
- dw_write(dma, DW_CLEAR_TFR, status_tfr);
-
- /* TODO: handle errors, just clear them atm */
- status_err = dw_read(dma, DW_STATUS_ERR);
- dw_write(dma, DW_CLEAR_ERR, status_err);
- if (status_err) {
- trace_dma_error("eI1");
- }
-
- /* clear platform and DSP interrupt */
- pmask = status_block | status_tfr | status_err;
- platform_interrupt_clear(dma_irq(dma), pmask);
-
- /* confirm IRQ cleared */
- status_block_new = dw_read(dma, DW_STATUS_BLOCK);
- if (status_block_new) {
- trace_dma_error("eI2");
- trace_error_value(status_block_new);
- }
-
- for (i = 0; i < DW_MAX_CHAN; i++) {
-
- /* skip if channel is not running */
- if (p->chan[i].status != COMP_STATE_ACTIVE)
- continue;
-
- mask = 0x1 << i;
-
-#if DW_USE_HW_LLI
- /* end of a LLI block */
- if (status_block & mask &&
- p->chan[i].cb_type & DMA_IRQ_TYPE_BLOCK) {
- next.src = DMA_RELOAD_LLI;
- next.dest = DMA_RELOAD_LLI;
- next.size = DMA_RELOAD_LLI;
- p->chan[i].cb(p->chan[i].cb_data,
- DMA_IRQ_TYPE_BLOCK, &next);
- if (next.size == DMA_RELOAD_END) {
- trace_dma("LSo");
- /* disable channel, finished */
- dw_write(dma, DW_DMA_CHAN_EN, CHAN_DISABLE(i));
- p->chan[i].status = COMP_STATE_PREPARE;
- }
-
- p->chan[i].lli_current->ctrl_hi &= ~DW_CTLH_DONE(1);
- dcache_writeback_region(p->chan[i].lli_current,
- sizeof(*p->chan[i].lli_current));
-
- p->chan[i].lli_current =
- (struct dw_lli2 *)p->chan[i].lli_current->llp;
- }
-#endif
- /* end of a transfer */
- if ((status_tfr & mask) &&
- (p->chan[i].cb_type & DMA_IRQ_TYPE_LLIST)) {
-
- next.src = DMA_RELOAD_LLI;
- next.dest = DMA_RELOAD_LLI;
- /* will reload lli by default */
- next.size = DMA_RELOAD_LLI;
- if (p->chan[i].cb)
- p->chan[i].cb(p->chan[i].cb_data,
- DMA_IRQ_TYPE_LLIST, &next);
-
- /* check for reload channel:
- * next.size is DMA_RELOAD_END, stop this dma copy;
- * next.size > 0 but not DMA_RELOAD_LLI, use next
- * element for next copy;
- * if we are waiting for pause, pause it;
- * otherwise, reload lli
- */
- switch (next.size) {
- case DMA_RELOAD_END:
- p->chan[i].status = COMP_STATE_PREPARE;
- p->chan[i].lli_current =
- (struct dw_lli2 *)p->chan[i].lli_current->llp;
- break;
- case DMA_RELOAD_LLI:
- dw_dma_chan_reload_lli(dma, i);
- break;
- default:
- dw_dma_chan_reload_next(dma, i, &next);
- break;
- }
- }
- }
-}
-
-static int dw_dma_probe(struct dma *dma)
-{
- struct dma_pdata *dw_pdata;
- int i;
-
- /* allocate private data */
- dw_pdata = rzalloc(RZONE_SYS, SOF_MEM_CAPS_RAM,
- sizeof(*dw_pdata));
- dma_set_drvdata(dma, dw_pdata);
-
- spinlock_init(&dma->lock);
-
- dw_dma_setup(dma);
-
- /* init work */
- for (i = 0; i < DW_MAX_CHAN; i++) {
- dw_pdata->chan[i].dma = dma;
- dw_pdata->chan[i].channel = i;
- dw_pdata->chan[i].status = COMP_STATE_INIT;
- }
-
- /* register our IRQ handler */
- interrupt_register(dma_irq(dma), dw_dma_irq_handler, dma);
- interrupt_enable(dma_irq(dma));
-
- /* init number of channels draining */
- atomic_init(&dma->num_channels_busy, 0);
-
- return 0;
-}
-#endif
-
-const struct dma_ops dw_dma_ops = {
- .channel_get = dw_dma_channel_get,
- .channel_put = dw_dma_channel_put,
- .start = dw_dma_start,
- .stop = dw_dma_stop,
- .pause = dw_dma_pause,
- .release = dw_dma_release,
- .status = dw_dma_status,
- .set_config = dw_dma_set_config,
- .set_cb = dw_dma_set_cb,
- .pm_context_restore = dw_dma_pm_context_restore,
- .pm_context_store = dw_dma_pm_context_store,
- .probe = dw_dma_probe,
-};
diff --git a/src/drivers/hda-dma.c b/src/drivers/hda-dma.c
deleted file mode 100644
index 6545bc7..0000000
--- a/src/drivers/hda-dma.c
+++ /dev/null
@@ -1,679 +0,0 @@
-/*
- * Copyright (c) 2018, Intel Corporation
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- * * Redistributions of source code must retain the above copyright
- * notice, this list of conditions and the following disclaimer.
- * * Redistributions in binary form must reproduce the above copyright
- * notice, this list of conditions and the following disclaimer in the
- * documentation and/or other materials provided with the distribution.
- * * Neither the name of the Intel Corporation nor the
- * names of its contributors may be used to endorse or promote products
- * derived from this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
- * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
- * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
- * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
- * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
- * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
- * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
- * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
- * POSSIBILITY OF SUCH DAMAGE.
- *
- * Author: Keyon Jie <yang.jie@linux.intel.com>
- * Liam Girdwood <liam.r.girdwood@linux.intel.com>
- */
-
-#include <sof/atomic.h>
-#include <stdint.h>
-#include <stddef.h>
-#include <errno.h>
-#include <sof/sof.h>
-#include <sof/lock.h>
-#include <sof/list.h>
-#include <sof/stream.h>
-#include <sof/alloc.h>
-#include <sof/trace.h>
-#include <sof/dma.h>
-#include <sof/io.h>
-#include <sof/ipc.h>
-#include <sof/pm_runtime.h>
-#include <sof/wait.h>
-#include <sof/audio/format.h>
-#include <platform/dma.h>
-#include <platform/platform.h>
-#include <arch/cache.h>
-#include <uapi/ipc.h>
-
-#define trace_host(__e) trace_event(TRACE_CLASS_HOST, __e)
-#define tracev_host(__e) tracev_event(TRACE_CLASS_HOST, __e)
-#define trace_host_error(__e) trace_error(TRACE_CLASS_HOST, __e)
-
-/* Gateway Stream Registers */
-#define DGCS 0x00
-#define DGBBA 0x04
-#define DGBS 0x08
-#define DGBFPI 0x0c /* firmware need to update this when DGCS.FWCB=1 */
-#define DGBRP 0x10 /* Read Only, read pointer */
-#define DGBWP 0x14 /* Read Only, write pointer */
-#define DGBSP 0x18
-#define DGMBS 0x1c
-#define DGLLPI 0x24
-#define DGLPIBI 0x28
-
-/* DGCS */
-#define DGCS_SCS BIT(31)
-#define DGCS_GEN BIT(26)
-#define DGCS_FWCB BIT(23)
-#define DGCS_BSC BIT(11)
-#define DGCS_BOR BIT(10) /* buffer overrun */
-#define DGCS_BF BIT(9) /* buffer full */
-#define DGCS_BNE BIT(8) /* buffer not empty */
-#define DGCS_FIFORDY BIT(5) /* enable FIFO */
-
-/* DGBBA */
-#define DGBBA_MASK 0xffff80
-
-/* DGBS */
-#define DGBS_MASK 0xfffff0
-
-#define HDA_DMA_MAX_CHANS 9
-
-#define HDA_LINK_1MS_US 1000
-
-#define HDA_STATE_PRELOAD BIT(0)
-#define HDA_STATE_BF_WAIT BIT(1)
-
-struct hda_chan_data {
- struct dma *dma;
- uint32_t index;
- uint32_t stream_id;
- uint32_t status; /* common status */
- uint32_t state; /* hda specific additional state */
- uint32_t desc_count;
- uint32_t desc_avail;
- uint32_t direction;
-
- uint32_t period_bytes;
- uint32_t buffer_bytes;
- struct work dma_ch_work;
-
- void (*cb)(void *data, uint32_t type,
- struct dma_sg_elem *next); /* client callback */
- void *cb_data; /* client callback data */
- int cb_type; /* callback type */
-};
-
-struct dma_pdata {
- struct dma *dma;
- int32_t num_channels;
- struct hda_chan_data chan[HDA_DMA_MAX_CHANS];
-};
-
-static int hda_dma_stop(struct dma *dma, int channel);
-
-static inline uint32_t host_dma_reg_read(struct dma *dma, uint32_t chan,
- uint32_t reg)
-{
- return io_reg_read(dma_chan_base(dma, chan) + reg);
-}
-
-static inline void host_dma_reg_write(struct dma *dma, uint32_t chan,
- uint32_t reg, uint32_t value)
-{
- io_reg_write(dma_chan_base(dma, chan) + reg, value);
-}
-
-static inline void hda_update_bits(struct dma *dma, uint32_t chan,
- uint32_t reg, uint32_t mask, uint32_t value)
-{
- io_reg_update_bits(dma_chan_base(dma, chan) + reg, mask, value);
-}
-
-static inline void hda_dma_inc_fp(struct dma *dma, uint32_t chan,
- uint32_t value)
-{
- host_dma_reg_write(dma, chan, DGBFPI, value);
- /* TODO: wp update, not rp should inc LLPI and LPIBI in the
- * coupled input DMA
- */
- host_dma_reg_write(dma, chan, DGLLPI, value);
- host_dma_reg_write(dma, chan, DGLPIBI, value);
-}
-
-static inline void hda_dma_inc_link_fp(struct dma *dma, uint32_t chan,
- uint32_t value)
-{
- host_dma_reg_write(dma, chan, DGBFPI, value);
- /* TODO: wp update should inc LLPI and LPIBI in the input DMA */
-}
-
-/* TODO: might be implemented as buffer_size - get_data_size() */
-static inline uint32_t hda_dma_get_free_size(struct dma *dma, uint32_t chan)
-{
- const uint32_t cs = host_dma_reg_read(dma, chan, DGCS);
- const uint32_t bs = host_dma_reg_read(dma, chan, DGBS);
- const uint32_t rp = host_dma_reg_read(dma, chan, DGBRP);
- const uint32_t wp = host_dma_reg_read(dma, chan, DGBRP);
- int32_t fs;
-
- if (cs & DGCS_BF)
- return 0; /* buffer is full */
- if (!(cs & DGCS_BNE))
- return bs; /* buffer is empty */
- fs = rp - wp;
- if (wp >= rp)
- fs += bs;
- return fs;
-}
-
-static inline uint32_t hda_dma_get_data_size(struct dma *dma, uint32_t chan)
-{
- const uint32_t cs = host_dma_reg_read(dma, chan, DGCS);
- const uint32_t bs = host_dma_reg_read(dma, chan, DGBS);
- const uint32_t rp = host_dma_reg_read(dma, chan, DGBRP);
- const uint32_t wp = host_dma_reg_read(dma, chan, DGBRP);
-
- uint32_t ds;
-
- if (!(cs & DGCS_BNE))
- return 0; /* buffer is empty */
- ds = wp - rp;
- if (ds <= 0)
- ds += bs;
-
- return ds;
-}
-
-static int hda_dma_preload(struct dma *dma, struct hda_chan_data *chan)
-{
- struct dma_sg_elem next = {
- .src = DMA_RELOAD_LLI,
- .dest = DMA_RELOAD_LLI,
- .size = DMA_RELOAD_LLI
- };
- int i;
- int period_cnt;
-
- /* waiting for buffer full after start
- * first try is unblocking, then blocking
- */
- while (!(host_dma_reg_read(dma, chan->index, DGCS) & DGCS_BF) &&
- (chan->state & HDA_STATE_BF_WAIT))
- ;
-
- if (host_dma_reg_read(dma, chan->index, DGCS) & DGCS_BF) {
- chan->state &= ~(HDA_STATE_PRELOAD | HDA_STATE_BF_WAIT);
- if (chan->cb) {
- /* loop over each period */
- period_cnt = chan->buffer_bytes /
- chan->period_bytes;
- for (i = 0; i < period_cnt; i++)
- chan->cb(chan->cb_data,
- DMA_IRQ_TYPE_LLIST, &next);
- /* do not need to test out next in this path */
- }
- } else {
- /* next call in pre-load state will be blocking */
- chan->state |= HDA_STATE_BF_WAIT;
- }
-
- return 0;
-}
-
-static int hda_dma_copy_ch(struct dma *dma, struct hda_chan_data *chan,
- int bytes)
-{
- struct dma_sg_elem next = {
- .src = DMA_RELOAD_LLI,
- .dest = DMA_RELOAD_LLI,
- .size = DMA_RELOAD_LLI
- };
- uint32_t flags;
- uint32_t dgcs = 0;
-
- tracev_host("GwU");
-
- /* clear link xruns */
- dgcs = host_dma_reg_read(dma, chan->index, DGCS);
- if (dgcs & DGCS_BOR)
- hda_update_bits(dma, chan->index,
- DGCS, DGCS_BOR, DGCS_BOR);
-
- /* make sure that previous transfer is complete */
- if (chan->direction == DMA_DIR_MEM_TO_DEV) {
- while (hda_dma_get_free_size(dma, chan->index) <
- bytes)
- idelay(PLATFORM_DEFAULT_DELAY);
- }
-
- /*
- * set BFPI to let host gateway knows we have read size,
- * which will trigger next copy start.
- */
- if (chan->direction == DMA_DIR_MEM_TO_DEV)
- hda_dma_inc_link_fp(dma, chan->index, bytes);
- else
- hda_dma_inc_fp(dma, chan->index, bytes);
-
- spin_lock_irq(&dma->lock, flags);
- if (chan->cb) {
- next.src = DMA_RELOAD_LLI;
- next.dest = DMA_RELOAD_LLI;
- next.size = DMA_RELOAD_LLI;
- chan->cb(chan->cb_data, DMA_IRQ_TYPE_LLIST, &next);
- if (next.size == DMA_RELOAD_END) {
- /* disable channel, finished */
- hda_dma_stop(dma, chan->index);
- }
- }
- spin_unlock_irq(&dma->lock, flags);
-
- /* Force Host DMA to exit L1 */
- pm_runtime_put(PM_RUNTIME_HOST_DMA_L1);
-
- return 0;
-}
-
-static uint64_t hda_dma_work(void *data, uint64_t delay)
-{
- struct hda_chan_data *chan = (struct hda_chan_data *)data;
-
- hda_dma_copy_ch(chan->dma, chan, chan->period_bytes);
- /* next time to re-arm */
- return HDA_LINK_1MS_US;
-}
-
-/* notify DMA to copy bytes */
-static int hda_dma_copy(struct dma *dma, int channel, int bytes, uint32_t flags)
-{
- struct dma_pdata *p = dma_get_drvdata(dma);
- struct hda_chan_data *chan = p->chan + channel;
-
- if (flags & DMA_COPY_PRELOAD)
- chan->state |= HDA_STATE_PRELOAD;
-
- if (chan->state & HDA_STATE_PRELOAD)
- return hda_dma_preload(dma, chan);
- else
- return hda_dma_copy_ch(dma, chan, bytes);
-}
-
-/* acquire the specific DMA channel */
-static int hda_dma_channel_get(struct dma *dma, int channel)
-{
- struct dma_pdata *p = dma_get_drvdata(dma);
- uint32_t flags;
-
- spin_lock_irq(&dma->lock, flags);
-
- trace_host("Dgt");
-
- /* use channel if it's free */
- if (p->chan[channel].status == COMP_STATE_INIT) {
- p->chan[channel].status = COMP_STATE_READY;
-
- atomic_add(&dma->num_channels_busy, 1);
-
- /* return channel */
- spin_unlock_irq(&dma->lock, flags);
- return channel;
- }
-
- /* DMAC has no free channels */
- spin_unlock_irq(&dma->lock, flags);
- trace_host_error("eG0");
- return -ENODEV;
-}
-
-/* channel must not be running when this is called */
-static void hda_dma_channel_put_unlocked(struct dma *dma, int channel)
-{
- struct dma_pdata *p = dma_get_drvdata(dma);
-
- /* set new state */
- p->chan[channel].status = COMP_STATE_INIT;
- p->chan[channel].state = 0;
- p->chan[channel].period_bytes = 0;
- p->chan[channel].buffer_bytes = 0;
- p->chan[channel].cb = NULL;
- p->chan[channel].cb_type = 0;
- p->chan[channel].cb_data = NULL;
- work_init(&p->chan[channel].dma_ch_work, NULL, NULL, 0);
-}
-
-/* channel must not be running when this is called */
-static void hda_dma_channel_put(struct dma *dma, int channel)
-{
- uint32_t flags;
-
- spin_lock_irq(&dma->lock, flags);
- hda_dma_channel_put_unlocked(dma, channel);
- spin_unlock_irq(&dma->lock, flags);
-
- atomic_sub(&dma->num_channels_busy, 1);
-}
-
-static int hda_dma_start(struct dma *dma, int channel)
-{
- struct dma_pdata *p = dma_get_drvdata(dma);
- uint32_t flags;
- uint32_t dgcs;
- int ret = 0;
-
- spin_lock_irq(&dma->lock, flags);
-
- trace_host("DEn");
-
- /* is channel idle, disabled and ready ? */
- dgcs = host_dma_reg_read(dma, channel, DGCS);
- if (p->chan[channel].status != COMP_STATE_PREPARE ||
- (dgcs & DGCS_GEN)) {
- ret = -EBUSY;
- trace_host_error("eS0");
- trace_error_value(dgcs);
- trace_error_value(p->chan[channel].status);
- goto out;
- }
-
- /* enable the channel */
- hda_update_bits(dma, channel, DGCS, DGCS_GEN | DGCS_FIFORDY,
- DGCS_GEN | DGCS_FIFORDY);
-
- /* full buffer is copied at startup */
- p->chan[channel].desc_avail = p->chan[channel].desc_count;
-
- pm_runtime_put(PM_RUNTIME_HOST_DMA_L1);
-
- /* activate timer if configured in cyclic mode */
- if (p->chan[channel].dma_ch_work.cb) {
- work_schedule_default(&p->chan[channel].dma_ch_work,
- HDA_LINK_1MS_US);
- }
-
- /* start link output transfer now */
- if (p->chan[channel].direction == DMA_DIR_MEM_TO_DEV)
- hda_dma_inc_link_fp(dma, channel,
- p->chan[channel].buffer_bytes);
-
-out:
- spin_unlock_irq(&dma->lock, flags);
- return ret;
-}
-
-static int hda_dma_release(struct dma *dma, int channel)
-{
- /* TODO: to be removed, no longer called by anyone */
- struct dma_pdata *p = dma_get_drvdata(dma);
- uint32_t flags;
-
- spin_lock_irq(&dma->lock, flags);
-
- trace_host("Dpr");
-
- /* resume and reload DMA */
- p->chan[channel].status = COMP_STATE_ACTIVE;
-
- spin_unlock_irq(&dma->lock, flags);
- return 0;
-}
-
-static int hda_dma_pause(struct dma *dma, int channel)
-{
- struct dma_pdata *p = dma_get_drvdata(dma);
- uint32_t flags;
-
- spin_lock_irq(&dma->lock, flags);
-
- trace_host("Dpa");
-
- if (p->chan[channel].status != COMP_STATE_ACTIVE)
- goto out;
-
- /* pause the channel */
- p->chan[channel].status = COMP_STATE_PAUSED;
-
-out:
- spin_unlock_irq(&dma->lock, flags);
- return 0;
-}
-
-static int hda_dma_stop(struct dma *dma, int channel)
-{
- struct dma_pdata *p = dma_get_drvdata(dma);
- uint32_t flags;
-
- spin_lock_irq(&dma->lock, flags);
-
- trace_host("DDi");
-
- if (p->chan[channel].dma_ch_work.cb)
- work_cancel_default(&p->chan[channel].dma_ch_work);
-
- /* disable the channel */
- hda_update_bits(dma, channel, DGCS, DGCS_GEN | DGCS_FIFORDY, 0);
- p->chan[channel].status = COMP_STATE_PREPARE;
-
- spin_unlock_irq(&dma->lock, flags);
- return 0;
-}
-
-/* fill in "status" with current DMA channel state and position */
-static int hda_dma_status(struct dma *dma, int channel,
- struct dma_chan_status *status, uint8_t direction)
-{
- struct dma_pdata *p = dma_get_drvdata(dma);
-
- status->state = p->chan[channel].status;
- status->r_pos = host_dma_reg_read(dma, channel, DGBRP);
- status->w_pos = host_dma_reg_read(dma, channel, DGBWP);
- status->timestamp = timer_get_system(platform_timer);
-
- return 0;
-}
-
-/* set the DMA channel configuration, source/target address, buffer sizes */
-static int hda_dma_set_config(struct dma *dma, int channel,
- struct dma_sg_config *config)
-{
- struct dma_pdata *p = dma_get_drvdata(dma);
- struct list_item *plist;
- struct dma_sg_elem *sg_elem;
- uint32_t buffer_addr = 0;
- uint32_t period_bytes = 0;
- uint32_t buffer_bytes = 0;
- uint32_t desc_count = 0;
- uint32_t flags;
- uint32_t addr;
- uint32_t dgcs;
- int ret = 0;
-
- spin_lock_irq(&dma->lock, flags);
-
- trace_host("Dsc");
-
- /* get number of SG elems */
- list_for_item(plist, &config->elem_list)
- desc_count++;
-
- if (desc_count == 0) {
- trace_host_error("eD1");
- ret = -EINVAL;
- goto out;
- }
-
- /* default channel config */
- p->chan[channel].direction = config->direction;
- p->chan[channel].desc_count = desc_count;
-
- /* validate - HDA only supports continuous elems of same size */
- list_for_item(plist, &config->elem_list) {
- sg_elem = container_of(plist, struct dma_sg_elem, list);
-
- if (config->direction == DMA_DIR_HMEM_TO_LMEM ||
- config->direction == DMA_DIR_DEV_TO_MEM)
- addr = sg_elem->dest;
- else
- addr = sg_elem->src;
-
- /* make sure elem is continuous */
- if (buffer_addr && (buffer_addr + buffer_bytes) != addr) {
- trace_host_error("eD2");
- ret = -EINVAL;
- goto out;
- }
-
- /* make sure period_bytes are constant */
- if (period_bytes && period_bytes != sg_elem->size) {
- trace_host_error("eD3");
- ret = -EINVAL;
- goto out;
- }
-
- /* update counters */
- period_bytes = sg_elem->size;
- buffer_bytes += period_bytes;
-
- if (buffer_addr == 0)
- buffer_addr = addr;
- }
- /* buffer size must be multiple of hda dma burst size */
- if (buffer_bytes % PLATFORM_HDA_BUFFER_ALIGNMENT) {
- ret = -EINVAL;
- goto out;
- }
-
- p->chan[channel].period_bytes = period_bytes;
- p->chan[channel].buffer_bytes = buffer_bytes;
-
- /* initialize timer */
- if (config->cyclic) {
- work_init(&p->chan[channel].dma_ch_work, hda_dma_work,
- &p->chan[channel], WORK_SYNC);
- }
-
- /* init channel in HW */
- host_dma_reg_write(dma, channel, DGBBA, buffer_addr);
- host_dma_reg_write(dma, channel, DGBS, buffer_bytes);
-
- if (config->direction == DMA_DIR_LMEM_TO_HMEM ||
- config->direction == DMA_DIR_HMEM_TO_LMEM)
- host_dma_reg_write(dma, channel, DGMBS,
- ALIGN_UP(buffer_bytes,
- PLATFORM_HDA_BUFFER_ALIGNMENT));
-
- /* firmware control buffer */
- dgcs = DGCS_FWCB;
-
- /* set DGCS.SCS bit to 1 for 16bit(2B) container */
- if ((config->direction & (DMA_DIR_HMEM_TO_LMEM | DMA_DIR_DEV_TO_MEM) &&
- config->dest_width <= 2) ||
- (config->direction & (DMA_DIR_LMEM_TO_HMEM | DMA_DIR_MEM_TO_DEV) &&
- config->src_width <= 2))
- dgcs |= DGCS_SCS;
-
- /* set DGCS.FIFORDY for output dma */
- if ((config->cyclic && config->direction == DMA_DIR_MEM_TO_DEV) ||
- (!config->cyclic && config->direction == DMA_DIR_LMEM_TO_HMEM))
- dgcs |= DGCS_FIFORDY;
-
- host_dma_reg_write(dma, channel, DGCS, dgcs);
-
- p->chan[channel].status = COMP_STATE_PREPARE;
-out:
- spin_unlock_irq(&dma->lock, flags);
- return ret;
-}
-
-/* restore DMA conext after leaving D3 */
-static int hda_dma_pm_context_restore(struct dma *dma)
-{
- return 0;
-}
-
-/* store DMA conext after leaving D3 */
-static int hda_dma_pm_context_store(struct dma *dma)
-{
- return 0;
-}
-
-static int hda_dma_set_cb(struct dma *dma, int channel, int type,
- void (*cb)(void *data, uint32_t type, struct dma_sg_elem *next),
- void *data)
-{
- struct dma_pdata *p = dma_get_drvdata(dma);
- uint32_t flags;
-
- spin_lock_irq(&dma->lock, flags);
- p->chan[channel].cb = cb;
- p->chan[channel].cb_data = data;
- p->chan[channel].cb_type = type;
- spin_unlock_irq(&dma->lock, flags);
-
- return 0;
-}
-
-static int hda_dma_probe(struct dma *dma)
-{
- struct dma_pdata *hda_pdata;
- int i;
- struct hda_chan_data *chan;
-
- /* allocate private data */
- hda_pdata = rzalloc(RZONE_SYS, SOF_MEM_CAPS_RAM, sizeof(*hda_pdata));
- dma_set_drvdata(dma, hda_pdata);
-
- spinlock_init(&dma->lock);
-
- /* init channel status */
- chan = hda_pdata->chan;
-
- for (i = 0; i < HDA_DMA_MAX_CHANS; i++, chan++) {
- chan->dma = dma;
- chan->index = i;
- chan->status = COMP_STATE_INIT;
- }
-
- /* init number of channels draining */
- atomic_init(&dma->num_channels_busy, 0);
-
- return 0;
-}
-
-const struct dma_ops hda_host_dma_ops = {
- .channel_get = hda_dma_channel_get,
- .channel_put = hda_dma_channel_put,
- .start = hda_dma_start,
- .stop = hda_dma_stop,
- .copy = hda_dma_copy,
- .pause = hda_dma_pause,
- .release = hda_dma_release,
- .status = hda_dma_status,
- .set_config = hda_dma_set_config,
- .set_cb = hda_dma_set_cb,
- .pm_context_restore = hda_dma_pm_context_restore,
- .pm_context_store = hda_dma_pm_context_store,
- .probe = hda_dma_probe,
-};
-
-const struct dma_ops hda_link_dma_ops = {
- .channel_get = hda_dma_channel_get,
- .channel_put = hda_dma_channel_put,
- .start = hda_dma_start,
- .stop = hda_dma_stop,
- .copy = hda_dma_copy,
- .pause = hda_dma_pause,
- .release = hda_dma_release,
- .status = hda_dma_status,
- .set_config = hda_dma_set_config,
- .set_cb = hda_dma_set_cb,
- .pm_context_restore = hda_dma_pm_context_restore,
- .pm_context_store = hda_dma_pm_context_store,
- .probe = hda_dma_probe,
-};
-
diff --git a/src/drivers/hsw-ssp.c b/src/drivers/hsw-ssp.c
deleted file mode 100644
index 479ae27..0000000
--- a/src/drivers/hsw-ssp.c
+++ /dev/null
@@ -1,528 +0,0 @@
-/*
- * Copyright (c) 2018, Intel Corporation
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- * * Redistributions of source code must retain the above copyright
- * notice, this list of conditions and the following disclaimer.
- * * Redistributions in binary form must reproduce the above copyright
- * notice, this list of conditions and the following disclaimer in the
- * documentation and/or other materials provided with the distribution.
- * * Neither the name of the Intel Corporation nor the
- * names of its contributors may be used to endorse or promote products
- * derived from this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
- * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
- * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
- * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
- * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
- * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
- * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
- * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
- * POSSIBILITY OF SUCH DAMAGE.
- *
- * Author: Liam Girdwood <liam.r.girdwood@linux.intel.com>
- * Keyon Jie <yang.jie@linux.intel.com>
- */
-
-#include <errno.h>
-#include <stdbool.h>
-#include <sof/stream.h>
-#include <sof/ssp.h>
-#include <sof/alloc.h>
-#include <sof/interrupt.h>
-
-/* tracing */
-#define trace_ssp(__e) trace_event(TRACE_CLASS_SSP, __e)
-#define trace_ssp_error(__e) trace_error(TRACE_CLASS_SSP, __e)
-#define tracev_ssp(__e) tracev_event(TRACE_CLASS_SSP, __e)
-
-/* save SSP context prior to entering D3 */
-static int ssp_context_store(struct dai *dai)
-{
- struct ssp_pdata *ssp = dai_get_drvdata(dai);
-
- ssp->sscr0 = ssp_read(dai, SSCR0);
- ssp->sscr1 = ssp_read(dai, SSCR1);
-
- /* FIXME: need to store sscr2,3,4,5 */
- ssp->psp = ssp_read(dai, SSPSP);
-
- return 0;
-}
-
-/* restore SSP context after leaving D3 */
-static int ssp_context_restore(struct dai *dai)
-{
- struct ssp_pdata *ssp = dai_get_drvdata(dai);
-
- ssp_write(dai, SSCR0, ssp->sscr0);
- ssp_write(dai, SSCR1, ssp->sscr1);
- /* FIXME: need to restore sscr2,3,4,5 */
- ssp_write(dai, SSPSP, ssp->psp);
-
- return 0;
-}
-
-/* Digital Audio interface formatting */
-static inline int ssp_set_config(struct dai *dai,
- struct sof_ipc_dai_config *config)
-{
- struct ssp_pdata *ssp = dai_get_drvdata(dai);
- uint32_t sscr0;
- uint32_t sscr1;
- uint32_t sscr2;
- uint32_t sspsp;
- uint32_t sspsp2;
- uint32_t mdiv;
- uint32_t bdiv;
- uint32_t data_size;
- uint32_t start_delay;
- uint32_t frame_end_padding;
- uint32_t slot_end_padding;
- uint32_t frame_len = 0;
- uint32_t bdiv_min;
- uint32_t format;
- bool inverted_frame = false;
- int ret = 0;
-
- spin_lock(&ssp->lock);
-
- /* is playback/capture already running */
- if (ssp->state[DAI_DIR_PLAYBACK] == COMP_STATE_ACTIVE ||
- ssp->state[DAI_DIR_CAPTURE] == COMP_STATE_ACTIVE) {
- trace_ssp_error("ec1");
- ret = -EINVAL;
- goto out;
- }
-
- trace_ssp("cos");
-
- /* disable clock */
- shim_update_bits(SHIM_CLKCTL, SHIM_CLKCTL_EN_SSP(dai->index), 0);
-
- /* enable MCLK */
- shim_update_bits(SHIM_CLKCTL, SHIM_CLKCTL_SMOS(0x3),
- SHIM_CLKCTL_SMOS(0x3));
-
- /* reset SSP settings */
- /* sscr0 dynamic settings are DSS, EDSS, SCR, FRDC, ECS */
- sscr0 = SSCR0_MOD | SSCR0_PSP;
-
- /* sscr1 dynamic settings are TFT, RFT, SFRMDIR, SCLKDIR, SCFR */
- sscr1 = SSCR1_TTE | SSCR1_TTELP;
-
- /* enable Transmit underrun mode 1 */
- sscr2 = SSCR2_TURM1;
-
- /* sspsp dynamic settings are SCMODE, SFRMP, DMYSTRT, SFRMWDTH */
- sspsp = 0x0;
-
- /* sspsp2 no dynamic setting */
- sspsp2 = 0x0;
-
- ssp->config = *config;
- ssp->params = config->ssp;
-
- switch (config->format & SOF_DAI_FMT_MASTER_MASK) {
- case SOF_DAI_FMT_CBM_CFM:
- sscr1 |= SSCR1_SCLKDIR | SSCR1_SFRMDIR;
-#ifdef ENABLE_SSRCR1_SCFR
- sscr1 |= SSCR1_SCFR;
-#endif
- break;
- case SOF_DAI_FMT_CBS_CFS:
- break;
- case SOF_DAI_FMT_CBM_CFS:
- sscr1 |= SSCR1_SCLKDIR;
-#ifdef ENABLE_SSRCR1_SCFR
- sscr1 |= SSCR1_SCFR;
-#endif
- break;
- case SOF_DAI_FMT_CBS_CFM:
- sscr1 |= SSCR1_SFRMDIR;
- break;
- default:
- trace_ssp_error("ec2");
- ret = -EINVAL;
- goto out;
- }
-
- /* clock signal polarity */
- switch (config->format & SOF_DAI_FMT_INV_MASK) {
- case SOF_DAI_FMT_NB_NF:
- break;
- case SOF_DAI_FMT_NB_IF:
- inverted_frame = true; /* handled later with format */
- break;
- case SOF_DAI_FMT_IB_IF:
- sspsp |= SSPSP_SCMODE(2);
- inverted_frame = true; /* handled later with format */
- break;
- case SOF_DAI_FMT_IB_NF:
- sspsp |= SSPSP_SCMODE(2);
- break;
- default:
- trace_ssp_error("ec3");
- ret = -EINVAL;
- goto out;
- }
-
- /* BCLK is generated from MCLK - must be divisable */
- if (config->ssp.mclk_rate % config->ssp.bclk_rate) {
- trace_ssp_error("ec5");
- ret = -EINVAL;
- goto out;
- }
-
- /* divisor must be within SCR range */
- mdiv = (config->ssp.mclk_rate / config->ssp.bclk_rate) - 1;
- if (mdiv > (SSCR0_SCR_MASK >> 8)) {
- trace_ssp_error("ec6");
- ret = -EINVAL;
- goto out;
- }
-
- /* set the SCR divisor */
- sscr0 |= SSCR0_SCR(mdiv);
-
- /* calc frame width based on BCLK and rate - must be divisable */
- if (config->ssp.bclk_rate % config->ssp.fsync_rate) {
- trace_ssp_error("ec7");
- ret = -EINVAL;
- goto out;
- }
-
- /* must be enouch BCLKs for data */
- bdiv = config->ssp.bclk_rate / config->ssp.fsync_rate;
- if (bdiv < config->ssp.tdm_slot_width *
- config->ssp.tdm_slots) {
- trace_ssp_error("ec8");
- ret = -EINVAL;
- goto out;
- }
-
- /* tdm_slot_width must be <= 38 for SSP */
- if (config->ssp.tdm_slot_width > 38) {
- trace_ssp_error("ec9");
- ret = -EINVAL;
- goto out;
- }
-
- bdiv_min = config->ssp.tdm_slots * config->ssp.sample_valid_bits;
- if (bdiv < bdiv_min) {
- trace_ssp_error("ecc");
- ret = -EINVAL;
- goto out;
- }
-
- frame_end_padding = bdiv - bdiv_min;
- if (frame_end_padding > SSPSP2_FEP_MASK) {
- trace_ssp_error("ecd");
- ret = -EINVAL;
- goto out;
- }
-
- /* format */
- format = config->format & SOF_DAI_FMT_FORMAT_MASK;
- switch (format) {
- case SOF_DAI_FMT_I2S:
- case SOF_DAI_FMT_LEFT_J:
-
- if (format == SOF_DAI_FMT_I2S) {
- start_delay = 1;
-
- /*
- * handle frame polarity, I2S default is falling/active low,
- * non-inverted(inverted_frame=0) -- active low(SFRMP=0),
- * inverted(inverted_frame=1) -- rising/active high(SFRMP=1),
- * so, we should set SFRMP to inverted_frame.
- */
- sspsp |= SSPSP_SFRMP(inverted_frame);
- sspsp |= SSPSP_FSRT;
-
- } else {
- start_delay = 0;
-
- /*
- * handle frame polarity, LEFT_J default is rising/active high,
- * non-inverted(inverted_frame=0) -- active high(SFRMP=1),
- * inverted(inverted_frame=1) -- falling/active low(SFRMP=0),
- * so, we should set SFRMP to !inverted_frame.
- */
- sspsp |= SSPSP_SFRMP(!inverted_frame);
- }
-
- sscr0 |= SSCR0_FRDC(config->ssp.tdm_slots);
-
- if (bdiv % 2) {
- trace_ssp_error("eca");
- ret = -EINVAL;
- goto out;
- }
-
- /* set asserted frame length to half frame length */
- frame_len = bdiv / 2;
-
- /*
- * for I2S/LEFT_J, the padding has to happen at the end
- * of each slot
- */
- if (frame_end_padding % 2) {
- trace_ssp_error("ece");
- ret = -EINVAL;
- goto out;
- }
-
- slot_end_padding = frame_end_padding / 2;
-
- if (slot_end_padding > 15) {
- /* can't handle padding over 15 bits */
- trace_ssp_error("ecf");
- ret = -EINVAL;
- goto out;
- }
-
- sspsp |= SSPSP_DMYSTOP(slot_end_padding & SSPSP_DMYSTOP_MASK);
- slot_end_padding >>= SSPSP_DMYSTOP_BITS;
- sspsp |= SSPSP_EDMYSTOP(slot_end_padding & SSPSP_EDMYSTOP_MASK);
-
- break;
- case SOF_DAI_FMT_DSP_A:
-
- start_delay = 1;
-
- sscr0 |= SSCR0_FRDC(config->ssp.tdm_slots);
-
- /* set asserted frame length */
- frame_len = 1;
-
- /* handle frame polarity, DSP_A default is rising/active high */
- sspsp |= SSPSP_SFRMP(!inverted_frame);
- sspsp2 |= (frame_end_padding & SSPSP2_FEP_MASK);
-
- break;
- case SOF_DAI_FMT_DSP_B:
-
- start_delay = 0;
-
- sscr0 |= SSCR0_FRDC(config->ssp.tdm_slots);
-
- /* set asserted frame length */
- frame_len = 1;
-
- /* handle frame polarity, DSP_B default is rising/active high */
- sspsp |= SSPSP_SFRMP(!inverted_frame);
- sspsp2 |= (frame_end_padding & SSPSP2_FEP_MASK);
-
- break;
- default:
- trace_ssp_error("eca");
- ret = -EINVAL;
- goto out;
- }
-
- sspsp |= SSPSP_DMYSTRT(start_delay);
- sspsp |= SSPSP_SFRMWDTH(frame_len);
-
- data_size = config->ssp.sample_valid_bits;
-
- if (data_size > 16)
- sscr0 |= (SSCR0_EDSS | SSCR0_DSIZE(data_size - 16));
- else
- sscr0 |= SSCR0_DSIZE(data_size);
-
- sscr1 |= SSCR1_TFT(0x7) | SSCR1_RFT(0x7);
-
- trace_ssp("coe");
-
- ssp_write(dai, SSCR0, sscr0);
- ssp_write(dai, SSCR1, sscr1);
- ssp_write(dai, SSCR2, sscr2);
- ssp_write(dai, SSPSP, sspsp);
- ssp_write(dai, SSTSA, config->ssp.tx_slots);
- ssp_write(dai, SSRSA, config->ssp.rx_slots);
- ssp_write(dai, SSPSP2, sspsp2);
-
- ssp->state[DAI_DIR_PLAYBACK] = COMP_STATE_PREPARE;
- ssp->state[DAI_DIR_CAPTURE] = COMP_STATE_PREPARE;
-
- /* enable clock */
- shim_update_bits(SHIM_CLKCTL, SHIM_CLKCTL_EN_SSP(dai->index),
- SHIM_CLKCTL_EN_SSP(dai->index));
-
- /* enable free running clock */
- ssp_update_bits(dai, SSCR0, SSCR0_SSE, SSCR0_SSE);
- ssp_update_bits(dai, SSCR0, SSCR0_SSE, 0);
-
-out:
- spin_unlock(&ssp->lock);
-
- return ret;
-}
-
-/* Digital Audio interface formatting */
-static inline int ssp_set_loopback_mode(struct dai *dai, uint32_t lbm)
-{
- struct ssp_pdata *ssp = dai_get_drvdata(dai);
-
- trace_ssp("loo");
- spin_lock(&ssp->lock);
-
- ssp_update_bits(dai, SSCR1, SSCR1_LBM, lbm ? SSCR1_LBM : 0);
-
- spin_unlock(&ssp->lock);
-
- return 0;
-}
-
-/* start the SSP for either playback or capture */
-static void ssp_start(struct dai *dai, int direction)
-{
- struct ssp_pdata *ssp = dai_get_drvdata(dai);
-
- spin_lock(&ssp->lock);
-
- trace_ssp("sta");
-
- /* enable DMA */
- if (direction == DAI_DIR_PLAYBACK) {
- ssp_update_bits(dai, SSCR1, SSCR1_TSRE | SSCR1_EBCEI,
- SSCR1_TSRE | SSCR1_EBCEI);
- ssp_update_bits(dai, SSCR0, SSCR0_SSE, SSCR0_SSE);
- ssp_update_bits(dai, SSCR0, SSCR0_TIM, 0);
- ssp_update_bits(dai, SSTSA, SSTSA_TSEN, SSTSA_TSEN);
- } else {
- ssp_update_bits(dai, SSCR1, SSCR1_RSRE | SSCR1_EBCEI,
- SSCR1_RSRE | SSCR1_EBCEI);
- ssp_update_bits(dai, SSCR0, SSCR0_SSE, SSCR0_SSE);
- ssp_update_bits(dai, SSCR0, SSCR0_RIM, 0);
- ssp_update_bits(dai, SSRSA, SSRSA_RSEN, SSRSA_RSEN);
- }
-
- /* enable port */
- ssp->state[direction] = COMP_STATE_ACTIVE;
-
-
- spin_unlock(&ssp->lock);
-}
-
-/* stop the SSP for either playback or capture */
-static void ssp_stop(struct dai *dai, int direction)
-{
- struct ssp_pdata *ssp = dai_get_drvdata(dai);
-
- spin_lock(&ssp->lock);
-
- /* stop Rx if neeed */
- if (direction == DAI_DIR_CAPTURE &&
- ssp->state[SOF_IPC_STREAM_CAPTURE] == COMP_STATE_ACTIVE) {
- ssp_update_bits(dai, SSCR1, SSCR1_RSRE, 0);
- ssp_update_bits(dai, SSCR0, SSCR0_RIM, SSCR0_RIM);
- ssp->state[SOF_IPC_STREAM_CAPTURE] = COMP_STATE_PAUSED;
- trace_ssp("Ss0");
- }
-
- /* stop Tx if needed */
- if (direction == DAI_DIR_PLAYBACK &&
- ssp->state[SOF_IPC_STREAM_PLAYBACK] == COMP_STATE_ACTIVE) {
- ssp_update_bits(dai, SSCR1, SSCR1_TSRE, 0);
- ssp_update_bits(dai, SSCR0, SSCR0_TIM, SSCR0_TIM);
- ssp->state[SOF_IPC_STREAM_PLAYBACK] = COMP_STATE_PAUSED;
- trace_ssp("Ss1");
- }
-
- /* disable SSP port if no users */
- if (ssp->state[SOF_IPC_STREAM_CAPTURE] != COMP_STATE_ACTIVE &&
- ssp->state[SOF_IPC_STREAM_PLAYBACK] != COMP_STATE_ACTIVE) {
- ssp_update_bits(dai, SSCR0, SSCR0_SSE, 0);
- ssp->state[SOF_IPC_STREAM_CAPTURE] = COMP_STATE_PREPARE;
- ssp->state[SOF_IPC_STREAM_PLAYBACK] = COMP_STATE_PREPARE;
- trace_ssp("Ss2");
- }
-
- spin_unlock(&ssp->lock);
-}
-
-static int ssp_trigger(struct dai *dai, int cmd, int direction)
-{
- struct ssp_pdata *ssp = dai_get_drvdata(dai);
-
- trace_ssp("tri");
-
- switch (cmd) {
- case COMP_TRIGGER_START:
- if (ssp->state[direction] == COMP_STATE_PREPARE ||
- ssp->state[direction] == COMP_STATE_PAUSED)
- ssp_start(dai, direction);
- break;
- case COMP_TRIGGER_RELEASE:
- if (ssp->state[direction] == COMP_STATE_PAUSED ||
- ssp->state[direction] == COMP_STATE_PREPARE)
- ssp_start(dai, direction);
- break;
- case COMP_TRIGGER_STOP:
- case COMP_TRIGGER_PAUSE:
- ssp_stop(dai, direction);
- break;
- case COMP_TRIGGER_RESUME:
- ssp_context_restore(dai);
- break;
- case COMP_TRIGGER_SUSPEND:
- ssp_context_store(dai);
- break;
- default:
- break;
- }
-
- return 0;
-}
-
-/* clear IRQ sources atm */
-static void ssp_irq_handler(void *data)
-{
- struct dai *dai = data;
-
- trace_ssp("irq");
- trace_value(ssp_read(dai, SSSR));
-
- /* clear IRQ */
- ssp_write(dai, SSSR, ssp_read(dai, SSSR));
- platform_interrupt_clear(ssp_irq(dai), 1);
-}
-
-static int ssp_probe(struct dai *dai)
-{
- struct ssp_pdata *ssp;
-
- /* allocate private data */
- ssp = rzalloc(RZONE_SYS, SOF_MEM_CAPS_RAM, sizeof(*ssp));
- dai_set_drvdata(dai, ssp);
-
- spinlock_init(&ssp->lock);
-
- ssp->state[DAI_DIR_PLAYBACK] = COMP_STATE_READY;
- ssp->state[DAI_DIR_CAPTURE] = COMP_STATE_READY;
-
-
- /* register our IRQ handler */
- interrupt_register(ssp_irq(dai), ssp_irq_handler, dai);
-
- platform_interrupt_unmask(ssp_irq(dai), 1);
- interrupt_enable(ssp_irq(dai));
-
- return 0;
-}
-
-const struct dai_ops ssp_ops = {
- .trigger = ssp_trigger,
- .set_config = ssp_set_config,
- .pm_context_store = ssp_context_store,
- .pm_context_restore = ssp_context_restore,
- .probe = ssp_probe,
- .set_loopback_mode = ssp_set_loopback_mode,
-};
diff --git a/src/host/Makefile.am b/src/host/Makefile.am
deleted file mode 100644
index cfd89f6..0000000
--- a/src/host/Makefile.am
+++ /dev/null
@@ -1,29 +0,0 @@
-AUTOMAKE_OPTIONS = subdir-objects
-
-SOF_INC = $(prefix)/include/sof
-DEFINE = -DSOF_INC=\"$(SOF_INC)\"
-
-AM_CPPFLAGS = -I $(SOF_INC) $(COMMON_INCDIR) $(DEFINE)
-AM_CFLAGS += -g -Wall
-AM_LDFLAGS += -L../ipc -L../audio/.libs
-
-bin_PROGRAMS = testbench
-
-testbench_SOURCES = \
- testbench.c
-
-testbench_LDADD = \
- -ldl -lm -lsof_ipc \
- libtb_common.a \
- -lsof
-
-noinst_LIBRARIES = libtb_common.a
-
-libtb_common_a_SOURCES = \
- common_test.c \
- topology.c \
- file.c \
- trace.c \
- ipc.c \
- schedule.c \
- alloc.c
diff --git a/src/host/alloc.c b/src/host/alloc.c
deleted file mode 100644
index e7e2863..0000000
--- a/src/host/alloc.c
+++ /dev/null
@@ -1,60 +0,0 @@
-/*
- * Copyright (c) 2018, Intel Corporation
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- * * Redistributions of source code must retain the above copyright
- * notice, this list of conditions and the following disclaimer.
- * * Redistributions in binary form must reproduce the above copyright
- * notice, this list of conditions and the following disclaimer in the
- * documentation and/or other materials provided with the distribution.
- * * Neither the name of the Intel Corporation nor the
- * names of its contributors may be used to endorse or promote products
- * derived from this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
- * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
- * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
- * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
- * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
- * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
- * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
- * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
- * POSSIBILITY OF SUCH DAMAGE.
- *
- * Author: Seppo Ingalsuo <seppo.ingalsuo@linux.intel.com>
- * Liam Girdwood <liam.r.girdwood@linux.intel.com>
- * Keyon Jie <yang.jie@linux.intel.com>
- * Ranjani Sridharan <ranjani.sridharan@linux.intel.com>
-
- */
-#include <stdlib.h>
-#include <stdint.h>
-#include <stdio.h>
-#include <sof/alloc.h>
-#include "host/common_test.h"
-
-/* testbench mem alloc definition */
-
-void *rmalloc(int zone, uint32_t caps, size_t bytes)
-{
- return malloc(bytes);
-}
-
-void *rzalloc(int zone, uint32_t caps, size_t bytes)
-{
- return calloc(bytes, 1);
-}
-
-void rfree(void *ptr)
-{
- free(ptr);
-}
-
-void *rballoc(int zone, uint32_t caps, size_t bytes)
-{
- return malloc(bytes);
-}
diff --git a/src/host/common_test.c b/src/host/common_test.c
deleted file mode 100644
index 1065336..0000000
--- a/src/host/common_test.c
+++ /dev/null
@@ -1,233 +0,0 @@
-/*
- * Copyright (c) 2018, Intel Corporation
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- * * Redistributions of source code must retain the above copyright
- * notice, this list of conditions and the following disclaimer.
- * * Redistributions in binary form must reproduce the above copyright
- * notice, this list of conditions and the following disclaimer in the
- * documentation and/or other materials provided with the distribution.
- * * Neither the name of the Intel Corporation nor the
- * names of its contributors may be used to endorse or promote products
- * derived from this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
- * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
- * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
- * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
- * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
- * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
- * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
- * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
- * POSSIBILITY OF SUCH DAMAGE.
- *
- * Author(s): Seppo Ingalsuo <seppo.ingalsuo@linux.intel.com>
- * Liam Girdwood <liam.r.girdwood@linux.intel.com>
- * Keyon Jie <yang.jie@linux.intel.com>
- * Ranjani Sridharan <ranjani.sridharan@linux.intel.com>
- */
-
-#include <stdint.h>
-#include <stddef.h>
-#include <time.h>
-#include <stdio.h>
-#include <stdlib.h>
-#include <string.h>
-#include <math.h>
-#include <sof/task.h>
-#include <sof/alloc.h>
-#include <sof/ipc.h>
-#include <sof/dai.h>
-#include <sof/dma.h>
-#include <sof/work.h>
-#include <sof/wait.h>
-#include <sof/intel-ipc.h>
-#include <sof/audio/pipeline.h>
-#include "host/common_test.h"
-#include "host/topology.h"
-
-/* print debug messages */
-void debug_print(char *message)
-{
- if (debug)
- printf("debug: %s", message);
-}
-
-/* testbench helper functions for pipeline setup and trigger */
-
-int tb_pipeline_setup(struct sof *sof)
-{
- /* init components */
- sys_comp_init();
-
- /* init IPC */
- if (ipc_init(sof) < 0) {
- fprintf(stderr, "error: IPC init\n");
- return -EINVAL;
- }
-
- /* init scheduler */
- if (scheduler_init(sof) < 0) {
- fprintf(stderr, "error: scheduler init\n");
- return -EINVAL;
- }
-
- debug_print("ipc and scheduler initialized\n");
-
- return 0;
-}
-
-/* set up pcm params, prepare and trigger pipeline */
-int tb_pipeline_start(struct ipc *ipc, int nch, char *bits_in,
- struct sof_ipc_pipe_new *ipc_pipe)
-{
- struct ipc_comp_dev *pcm_dev;
- struct pipeline *p;
- struct comp_dev *cd;
- int ret;
-
- /* set up pipeline params */
- ret = tb_pipeline_params(ipc, nch, bits_in, ipc_pipe);
- if (ret < 0) {
- fprintf(stderr, "error: pipeline params\n");
- return -EINVAL;
- }
-
- /* Get IPC component device for pipeline */
- pcm_dev = ipc_get_comp(ipc, ipc_pipe->sched_id);
- if (!pcm_dev) {
- fprintf(stderr, "error: ipc get comp\n");
- return -EINVAL;
- }
-
- /* Point to pipeline */
- cd = pcm_dev->cd;
- p = pcm_dev->cd->pipeline;
-
- /* Component prepare */
- ret = pipeline_prepare(p, cd);
-
- /* Start the pipeline */
- ret = pipeline_trigger(p, cd, COMP_TRIGGER_START);
- if (ret < 0)
- printf("Warning: Failed start pipeline command.\n");
-
- return ret;
-}
-
-/* pipeline pcm params */
-int tb_pipeline_params(struct ipc *ipc, int nch, char *bits_in,
- struct sof_ipc_pipe_new *ipc_pipe)
-{
- int fs_period, ret = 0;
- struct ipc_comp_dev *pcm_dev;
- struct pipeline *p;
- struct comp_dev *cd;
- struct sof_ipc_pcm_params params;
- int deadline;
- char message[DEBUG_MSG_LEN];
-
- deadline = ipc_pipe->deadline;
-
- /* Compute period from sample rates */
- fs_period = (int)(0.9999 + fs_in * deadline / 1e6);
- sprintf(message, "period sample count %d\n", fs_period);
- debug_print(message);
-
- /* set pcm params */
- params.comp_id = ipc_pipe->comp_id;
- params.params.buffer_fmt = SOF_IPC_BUFFER_INTERLEAVED;
- params.params.frame_fmt = find_format(bits_in);
- params.params.direction = SOF_IPC_STREAM_PLAYBACK;
- params.params.rate = fs_in;
- params.params.channels = nch;
- switch (params.params.frame_fmt) {
- case(SOF_IPC_FRAME_S16_LE):
- params.params.sample_container_bytes = 2;
- params.params.sample_valid_bytes = 2;
- params.params.host_period_bytes = fs_period * nch *
- params.params.sample_container_bytes;
- break;
- case(SOF_IPC_FRAME_S24_4LE):
- params.params.sample_container_bytes = 4;
- params.params.sample_valid_bytes = 3;
- params.params.host_period_bytes = fs_period * nch *
- params.params.sample_container_bytes;
- break;
- case(SOF_IPC_FRAME_S32_LE):
- params.params.sample_container_bytes = 4;
- params.params.sample_valid_bytes = 4;
- params.params.host_period_bytes = fs_period * nch *
- params.params.sample_container_bytes;
- break;
- default:
- fprintf(stderr, "error: invalid frame format\n");
- return -EINVAL;
- }
-
- /* get scheduling component device for pipeline*/
- pcm_dev = ipc_get_comp(ipc, ipc_pipe->sched_id);
- if (!pcm_dev) {
- fprintf(stderr, "error: ipc get comp\n");
- return -EINVAL;
- }
-
- /* point to pipeline */
- cd = pcm_dev->cd;
- p = pcm_dev->cd->pipeline;
- if (!p) {
- fprintf(stderr, "error: pipeline NULL\n");
- return -EINVAL;
- }
-
- /* pipeline params */
- ret = pipeline_params(p, cd, ¶ms);
- if (ret < 0)
- fprintf(stderr, "error: pipeline_params\n");
-
- return ret;
-}
-
-/* getindex of shared library from table */
-int get_index_by_name(char *comp_type,
- struct shared_lib_table *lib_table)
-{
- int i;
-
- for (i = 0; i < NUM_WIDGETS_SUPPORTED; i++) {
- if (!strcmp(comp_type, lib_table[i].comp_name))
- return i;
- }
-
- return -EINVAL;
-}
-
-/* getindex of shared library from table by widget type*/
-int get_index_by_type(uint32_t comp_type,
- struct shared_lib_table *lib_table)
-{
- int i;
-
- for (i = 0; i < NUM_WIDGETS_SUPPORTED; i++) {
- if (comp_type == lib_table[i].widget_type)
- return i;
- }
-
- return -EINVAL;
-}
-
-/* The following definitions are to satisfy libsof linker errors */
-
-struct dai *dai_get(uint32_t type, uint32_t index)
-{
- return NULL;
-}
-
-struct dma *dma_get(uint32_t dir, uint32_t caps, uint32_t dev, uint32_t flags)
-{
- return NULL;
-}
diff --git a/src/host/file.c b/src/host/file.c
deleted file mode 100644
index 8525b2b..0000000
--- a/src/host/file.c
+++ /dev/null
@@ -1,720 +0,0 @@
-/*
- * Copyright (c) 2018, Intel Corporation
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- * * Redistributions of source code must retain the above copyright
- * notice, this list of conditions and the following disclaimer.
- * * Redistributions in binary form must reproduce the above copyright
- * notice, this list of conditions and the following disclaimer in the
- * documentation and/or other materials provided with the distribution.
- * * Neither the name of the Intel Corporation nor the
- * names of its contributors may be used to endorse or promote products
- * derived from this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
- * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
- * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
- * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
- * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
- * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
- * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
- * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
- * POSSIBILITY OF SUCH DAMAGE.
- *
- * Author(s): Seppo Ingalsuo <seppo.ingalsuo@linux.intel.com>
- * Ranjani Sridharan <ranjani.sridharan@linux.intel.com>
- */
-
-/* file component for reading/writing pcm samples to/from a file */
-
-#include <stdio.h>
-#include <stdint.h>
-#include <stddef.h>
-#include <errno.h>
-#include <inttypes.h>
-#include <sof/sof.h>
-#include <sof/lock.h>
-#include <sof/list.h>
-#include <sof/stream.h>
-#include <sof/work.h>
-#include <sof/clock.h>
-#include <sof/audio/component.h>
-#include <sof/audio/format.h>
-#include <sof/audio/pipeline.h>
-#include <uapi/ipc.h>
-#include "host/common_test.h"
-#include "host/file.h"
-
-static inline void buffer_check_wrap_32(int32_t **ptr, int32_t *end,
- size_t size)
-{
- if (*ptr >= end)
- *ptr = (int32_t *)((size_t)*ptr - size);
-}
-
-static inline void buffer_check_wrap_16(int16_t **ptr, int16_t *end,
- size_t size)
-{
- if (*ptr >= end)
- *ptr = (int16_t *)((size_t)*ptr - size);
-}
-
-/*
- * Read 32-bit samples from file
- * currently only supports txt files
- */
-static int read_samples_32(struct comp_dev *dev, struct comp_buffer *sink,
- int n, int fmt, int nch)
-{
- struct file_comp_data *cd = comp_get_drvdata(dev);
- int32_t *dest = (int32_t *)sink->w_ptr;
- int32_t sample;
- int n_samples = 0;
- int i, n_wrap, n_min, ret;
-
- while (n > 0) {
- n_wrap = (int32_t *)sink->end_addr - dest;
-
- /* check for buffer wrap and copy to the end of the buffer */
- n_min = (n < n_wrap) ? n : n_wrap;
- while (n_min > 0) {
- n -= nch;
- n_min -= nch;
-
- /* copy sample per channel */
- for (i = 0; i < nch; i++) {
- /* read sample from file */
- switch (cd->fs.f_format) {
- /* text input file */
- case FILE_TEXT:
- if (fmt == SOF_IPC_FRAME_S32_LE)
- ret = fscanf(cd->fs.rfh, "%d",
- dest);
-
- /* mask bits if 24-bit samples */
- if (fmt == SOF_IPC_FRAME_S24_4LE) {
- ret = fscanf(cd->fs.rfh, "%d",
- &sample);
- *dest = sample & 0x00ffffff;
- }
- /* quit if eof is reached */
- if (ret == EOF) {
- cd->fs.reached_eof = 1;
- goto quit;
- }
- break;
-
- /* raw input file */
- default:
- if (fmt == SOF_IPC_FRAME_S32_LE)
- ret = fread(dest,
- sizeof(int32_t),
- 1, cd->fs.rfh);
-
- /* mask bits if 24-bit samples */
- if (fmt == SOF_IPC_FRAME_S24_4LE) {
- ret = fread(&sample,
- sizeof(int32_t),
- 1, cd->fs.rfh);
- *dest = sample & 0x00ffffff;
- }
- /* quit if eof is reached */
- if (ret != 1) {
- cd->fs.reached_eof = 1;
- goto quit;
- }
- break;
- }
- dest++;
- n_samples++;
- }
- }
- /* check for buffer wrap and update pointer */
- buffer_check_wrap_32(&dest, sink->end_addr,
- sink->size);
- }
-quit:
- return n_samples;
-}
-
-/*
- * Read 16-bit samples from file
- * currently only supports txt files
- */
-static int read_samples_16(struct comp_dev *dev, struct comp_buffer *sink,
- int n, int nch)
-{
- struct file_comp_data *cd = comp_get_drvdata(dev);
- int16_t *dest = (int16_t *)sink->w_ptr;
- int i, n_wrap, n_min, ret;
- int n_samples = 0;
-
- /* copy samples */
- while (n > 0) {
- n_wrap = (int16_t *)sink->end_addr - dest;
-
- /* check for buffer wrap and copy to the end of the buffer */
- n_min = (n < n_wrap) ? n : n_wrap;
- while (n_min > 0) {
- n -= nch;
- n_min -= nch;
-
- /* copy sample per channel */
- for (i = 0; i < nch; i++) {
- /* read sample from file */
- ret = fscanf(cd->fs.rfh, "%hd", dest);
- switch (cd->fs.f_format) {
- /* text input file */
- case FILE_TEXT:
- ret = fscanf(cd->fs.rfh, "%hd", dest);
- if (ret == EOF) {
- cd->fs.reached_eof = 1;
- goto quit;
- }
- break;
-
- /* rw pcm input file */
- default:
- ret = fread(dest, sizeof(int16_t), 1,
- cd->fs.rfh);
- if (ret != 1) {
- cd->fs.reached_eof = 1;
- goto quit;
- }
- break;
- }
-
- dest++;
- n_samples++;
- }
- }
- /* check for buffer wrap and update pointer */
- buffer_check_wrap_16(&dest, sink->end_addr,
- sink->size);
- }
-
-quit:
- return n_samples;
-}
-
-/*
- * Write 16-bit samples from file
- * currently only supports txt files
- */
-static int write_samples_16(struct comp_dev *dev, struct comp_buffer *source,
- int n, int nch)
-{
- struct file_comp_data *cd = comp_get_drvdata(dev);
- int16_t *src = (int16_t *)source->r_ptr;
- int i, n_wrap, n_min, ret;
- int n_samples = 0;
-
- /* copy samples */
- while (n > 0) {
- n_wrap = (int16_t *)source->end_addr - src;
-
- /* check for buffer wrap and copy to the end of the buffer */
- n_min = (n < n_wrap) ? n : n_wrap;
- while (n_min > 0) {
- n -= nch;
- n_min -= nch;
-
- /* copy sample per channel */
- for (i = 0; i < nch; i++) {
- switch (cd->fs.f_format) {
- /* text output file */
- case FILE_TEXT:
- ret = fprintf(cd->fs.wfh,
- "%d\n", *src);
- if (ret < 0)
- goto quit;
- break;
-
- /* raw pcm output file */
- default:
- ret = fwrite(src,
- sizeof(int16_t),
- 1, cd->fs.wfh);
- if (ret != 1)
- goto quit;
- break;
- }
-
- src++;
- n_samples++;
- }
- }
- /* check for buffer wrap and update pointer */
- buffer_check_wrap_16(&src, source->end_addr,
- source->size);
- }
-quit:
- return n_samples;
-}
-
-/*
- * Write 32-bit samples from file
- * currently only supports txt files
- */
-static int write_samples_32(struct comp_dev *dev, struct comp_buffer *source,
- int n, int fmt, int nch)
-{
- struct file_comp_data *cd = comp_get_drvdata(dev);
- int32_t *src = (int32_t *)source->r_ptr;
- int i, n_wrap, n_min, ret;
- int n_samples = 0;
- int32_t sample;
-
- /* copy samples */
- while (n > 0) {
- n_wrap = (int32_t *)source->end_addr - src;
-
- /* check for buffer wrap and copy to the end of the buffer */
- n_min = (n < n_wrap) ? n : n_wrap;
- while (n_min > 0) {
- n -= nch;
- n_min -= nch;
-
- /* copy sample per channel */
- for (i = 0; i < nch; i++) {
- switch (cd->fs.f_format) {
- /* text output file */
- case FILE_TEXT:
- if (fmt == SOF_IPC_FRAME_S32_LE)
- ret = fprintf(cd->fs.wfh,
- "%d\n", *src);
- if (fmt == SOF_IPC_FRAME_S24_4LE) {
- sample = *src << 8;
- ret = fprintf(cd->fs.wfh,
- "%d\n",
- sample >> 8);
- }
- if (ret < 0)
- goto quit;
- break;
-
- /* raw pcm output file */
- default:
- if (fmt == SOF_IPC_FRAME_S32_LE)
- ret = fwrite(src,
- sizeof(int32_t),
- 1, cd->fs.wfh);
- if (fmt == SOF_IPC_FRAME_S24_4LE) {
- sample = *src << 8;
- sample >>= 8;
- ret = fwrite(&sample,
- sizeof(int32_t),
- 1, cd->fs.wfh);
- }
- if (ret != 1)
- goto quit;
- break;
- }
-
- /* increment read pointer */
- src++;
-
- /* increment number of samples written */
- n_samples++;
- }
- }
- /* check for buffer wrap and update pointer */
- buffer_check_wrap_32(&src, source->end_addr,
- source->size);
- }
-quit:
- return n_samples;
-}
-
-/* function for processing 32-bit samples */
-static int file_s32_default(struct comp_dev *dev, struct comp_buffer *sink,
- struct comp_buffer *source, uint32_t frames)
-{
- struct file_comp_data *cd = comp_get_drvdata(dev);
- int nch = dev->params.channels;
- int n_samples = 0;
-
- switch (cd->fs.mode) {
- case FILE_READ:
- /* read samples */
- n_samples = read_samples_32(dev, sink, frames * nch,
- SOF_IPC_FRAME_S32_LE, nch);
- break;
- case FILE_WRITE:
- /* write samples */
- n_samples = write_samples_32(dev, source, frames * nch,
- SOF_IPC_FRAME_S32_LE, nch);
- break;
- default:
- /* TODO: duplex mode */
- break;
- }
-
- cd->fs.n += n_samples;
- return n_samples;
-}
-
-/* function for processing 16-bit samples */
-static int file_s16(struct comp_dev *dev, struct comp_buffer *sink,
- struct comp_buffer *source, uint32_t frames)
-{
- struct file_comp_data *cd = comp_get_drvdata(dev);
- int nch = dev->params.channels;
- int n_samples = 0;
-
- switch (cd->fs.mode) {
- case FILE_READ:
- /* read samples */
- n_samples = read_samples_16(dev, sink, frames * nch, nch);
- break;
- case FILE_WRITE:
- /* write samples */
- n_samples = write_samples_16(dev, source, frames * nch, nch);
- break;
- default:
- /* TODO: duplex mode */
- break;
- }
-
- cd->fs.n += n_samples;
- return n_samples;
-}
-
-/* function for processing 24-bit samples */
-static int file_s24(struct comp_dev *dev, struct comp_buffer *sink,
- struct comp_buffer *source, uint32_t frames)
-{
- struct file_comp_data *cd = comp_get_drvdata(dev);
- int nch = dev->params.channels;
- int n_samples = 0;
-
- switch (cd->fs.mode) {
- case FILE_READ:
- /* read samples */
- n_samples = read_samples_32(dev, sink, frames * nch,
- SOF_IPC_FRAME_S24_4LE, nch);
- break;
- case FILE_WRITE:
- /* write samples */
- n_samples = write_samples_32(dev, source, frames * nch,
- SOF_IPC_FRAME_S24_4LE, nch);
- break;
- default:
- /* TODO: duplex mode */
- break;
- }
-
- cd->fs.n += n_samples;
- return n_samples;
-}
-
-static enum file_format get_file_format(char *filename)
-{
- char *ext = strrchr(filename, '.');
-
- if (!strcmp(ext, ".txt"))
- return FILE_TEXT;
-
- return FILE_RAW;
-}
-
-static struct comp_dev *file_new(struct sof_ipc_comp *comp)
-{
- struct comp_dev *dev;
- struct sof_ipc_comp_file *file;
- struct sof_ipc_comp_file *ipc_file =
- (struct sof_ipc_comp_file *)comp;
- struct file_comp_data *cd;
-
- /* allocate memory for file comp */
- dev = malloc(COMP_SIZE(struct sof_ipc_comp_file));
- if (!dev)
- return NULL;
-
- /* copy file comp config */
- file = (struct sof_ipc_comp_file *)&dev->comp;
- memcpy(file, ipc_file, sizeof(struct sof_ipc_comp_file));
-
- /* allocate memory for file comp data */
- cd = rzalloc(RZONE_RUNTIME, SOF_MEM_CAPS_RAM, sizeof(*cd));
- if (!cd) {
- free(dev);
- return NULL;
- }
-
- comp_set_drvdata(dev, cd);
-
- /* default function for processing samples */
- cd->file_func = file_s32_default;
-
- /* get filename from IPC and open file */
- cd->fs.fn = strdup(ipc_file->fn);
-
- /* set file format */
- cd->fs.f_format = get_file_format(cd->fs.fn);
-
- /* set file comp mode */
- cd->fs.mode = ipc_file->mode;
-
- /* open file handle(s) depending on mode */
- switch (cd->fs.mode) {
- case FILE_READ:
- cd->fs.rfh = fopen(cd->fs.fn, "r");
- if (!cd->fs.rfh) {
- fprintf(stderr, "error: opening file %s\n", cd->fs.fn);
- free(cd);
- free(dev);
- return NULL;
- }
- break;
- case FILE_WRITE:
- cd->fs.wfh = fopen(cd->fs.fn, "w");
- if (!cd->fs.wfh) {
- fprintf(stderr, "error: opening file %s\n", cd->fs.fn);
- free(cd);
- free(dev);
- return NULL;
- }
- break;
- default:
- /* TODO: duplex mode */
- break;
- }
-
- cd->fs.reached_eof = 0;
- cd->fs.n = 0;
-
- dev->state = COMP_STATE_READY;
-
- return dev;
-}
-
-static void file_free(struct comp_dev *dev)
-{
- struct file_comp_data *cd = comp_get_drvdata(dev);
-
- if (cd->fs.mode == FILE_READ)
- fclose(cd->fs.rfh);
- else
- fclose(cd->fs.wfh);
-
- free(cd->fs.fn);
- free(cd);
- free(dev);
-
- debug_print("free file component\n");
-}
-
-/* set component audio stream parameters */
-static int file_params(struct comp_dev *dev)
-{
- struct file_comp_data *cd = comp_get_drvdata(dev);
- struct sof_ipc_comp_config *config = COMP_GET_CONFIG(dev);
-
- /* for file endpoint set the following from topology config */
- if (cd->fs.mode == FILE_WRITE) {
- dev->params.frame_fmt = config->frame_fmt;
- if (dev->params.frame_fmt == SOF_IPC_FRAME_S16_LE)
- dev->params.sample_container_bytes = 2;
- else
- dev->params.sample_container_bytes = 4;
- }
-
- /* Need to compute this in non-host endpoint */
- dev->frame_bytes =
- dev->params.sample_container_bytes * dev->params.channels;
-
- /* calculate period size based on config */
- cd->period_bytes = dev->frames * dev->frame_bytes;
-
- /* File to sink supports only S32_LE/S16_LE/S24_4LE PCM formats */
- if (config->frame_fmt != SOF_IPC_FRAME_S32_LE &&
- config->frame_fmt != SOF_IPC_FRAME_S24_4LE &&
- config->frame_fmt != SOF_IPC_FRAME_S16_LE)
- return -EINVAL;
-
- return 0;
-}
-
-static int fr_cmd(struct comp_dev *dev, struct sof_ipc_ctrl_data *cdata)
-{
- return -EINVAL;
-}
-
-static int file_trigger(struct comp_dev *dev, int cmd)
-{
- return comp_set_state(dev, cmd);
-}
-
-/* used to pass standard and bespoke commands (with data) to component */
-static int file_cmd(struct comp_dev *dev, int cmd, void *data)
-{
- struct sof_ipc_ctrl_data *cdata = data;
- int ret = 0;
-
- switch (cmd) {
- case COMP_CMD_SET_DATA:
- ret = fr_cmd(dev, cdata);
- break;
- default:
- break;
- }
-
- return ret;
-}
-
-/*
- * copy and process stream samples
- * returns the number of bytes copied
- */
-static int file_copy(struct comp_dev *dev)
-{
- struct comp_buffer *buffer;
- struct file_comp_data *cd = comp_get_drvdata(dev);
- int ret = 0, bytes;
-
- switch (cd->fs.mode) {
- case FILE_READ:
- /* file component sink buffer */
- buffer = list_first_item(&dev->bsink_list, struct comp_buffer,
- source_list);
-
- /* test sink has enough free frames */
- if (buffer->free >= cd->period_bytes && !cd->fs.reached_eof) {
- /* read PCM samples from file */
- ret = cd->file_func(dev, buffer, NULL, dev->frames);
-
- /* update sink buffer pointers */
- bytes = dev->params.sample_container_bytes;
- if (ret > 0)
- comp_update_buffer_produce(buffer,
- ret * bytes);
- }
- break;
- case FILE_WRITE:
- /* file component source buffer */
- buffer = list_first_item(&dev->bsource_list,
- struct comp_buffer, sink_list);
-
- /* test source has enough free frames */
- if (buffer->avail >= cd->period_bytes) {
- /* write PCM samples into file */
- ret = cd->file_func(dev, NULL, buffer, dev->frames);
-
- /* update source buffer pointers */
- bytes = dev->params.sample_container_bytes;
- if (ret > 0)
- comp_update_buffer_consume(buffer,
- ret * bytes);
- }
- break;
- default:
- /* TODO: duplex mode */
- break;
- }
-
- return ret;
-}
-
-static int file_prepare(struct comp_dev *dev)
-{
- struct sof_ipc_comp_config *config = COMP_GET_CONFIG(dev);
- struct comp_buffer *buffer = NULL;
- struct file_comp_data *cd = comp_get_drvdata(dev);
- int ret = 0, periods;
-
- /* file component sink/source buffer period count */
- switch (cd->fs.mode) {
- case FILE_READ:
- buffer = list_first_item(&dev->bsink_list, struct comp_buffer,
- source_list);
- periods = config->periods_sink;
- break;
- case FILE_WRITE:
- buffer = list_first_item(&dev->bsource_list,
- struct comp_buffer, sink_list);
- periods = config->periods_source;
- break;
- default:
- /* TODO: duplex mode */
- break;
- }
-
- if (!buffer) {
- fprintf(stderr, "error: no sink/source buffer\n");
- return -EINVAL;
- }
-
- /* set downstream buffer size */
- switch (config->frame_fmt) {
- case(SOF_IPC_FRAME_S16_LE):
- ret = buffer_set_size(buffer, dev->frames * 2 *
- periods * dev->params.channels);
- if (ret < 0) {
- fprintf(stderr, "error: file buffer size set\n");
- return ret;
- }
- buffer_reset_pos(buffer);
-
- /* set file function */
- cd->file_func = file_s16;
- break;
- case(SOF_IPC_FRAME_S24_4LE):
- ret = buffer_set_size(buffer, dev->frames * 4 *
- periods * dev->params.channels);
- if (ret < 0) {
- fprintf(stderr, "error: file buffer size set\n");
- return ret;
- }
- buffer_reset_pos(buffer);
-
- /* set file function */
- cd->file_func = file_s24;
- break;
- case(SOF_IPC_FRAME_S32_LE):
- ret = buffer_set_size(buffer, dev->frames * 4 *
- periods * dev->params.channels);
- if (ret < 0) {
- fprintf(stderr, "error: file buffer size set\n");
- return ret;
- }
- buffer_reset_pos(buffer);
- break;
- default:
- return -EINVAL;
- }
-
- dev->state = COMP_STATE_PREPARE;
-
- return ret;
-}
-
-static int file_reset(struct comp_dev *dev)
-{
- dev->state = COMP_STATE_INIT;
-
- return 0;
-}
-
-struct comp_driver comp_file = {
- .type = SOF_COMP_FILEREAD,
- .ops = {
- .new = file_new,
- .free = file_free,
- .params = file_params,
- .cmd = file_cmd,
- .trigger = file_trigger,
- .copy = file_copy,
- .prepare = file_prepare,
- .reset = file_reset,
- },
-};
-
-void sys_comp_file_init(void)
-{
- comp_register(&comp_file);
-}
diff --git a/src/host/ipc.c b/src/host/ipc.c
deleted file mode 100644
index 0cbb61a..0000000
--- a/src/host/ipc.c
+++ /dev/null
@@ -1,81 +0,0 @@
-/*
- * Copyright (c) 2018, Intel Corporation
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- * * Redistributions of source code must retain the above copyright
- * notice, this list of conditions and the following disclaimer.
- * * Redistributions in binary form must reproduce the above copyright
- * notice, this list of conditions and the following disclaimer in the
- * documentation and/or other materials provided with the distribution.
- * * Neither the name of the Intel Corporation nor the
- * names of its contributors may be used to endorse or promote products
- * derived from this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
- * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
- * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
- * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
- * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
- * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
- * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
- * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
- * POSSIBILITY OF SUCH DAMAGE.
- *
- * Author: Seppo Ingalsuo <seppo.ingalsuo@linux.intel.com>
- * Liam Girdwood <liam.r.girdwood@linux.intel.com>
- * Keyon Jie <yang.jie@linux.intel.com>
- * Ranjani Sridharan <ranjani.sridharan@linux.intel.com>
- */
-
-#include <sof/ipc.h>
-#include <sof/intel-ipc.h>
-
-/* testbench ipc */
-struct ipc *_ipc;
-
-int platform_ipc_init(struct ipc *ipc)
-{
- struct intel_ipc_data *iipc;
- int i;
-
- _ipc = ipc;
-
- /* init ipc data */
- iipc = malloc(sizeof(struct intel_ipc_data));
- ipc_set_drvdata(_ipc, iipc);
- _ipc->dsp_msg = NULL;
- list_init(&ipc->empty_list);
- list_init(&ipc->msg_list);
- spinlock_init(&ipc->lock);
-
- for (i = 0; i < MSG_QUEUE_SIZE; i++)
- list_item_prepend(&ipc->message[i].list, &ipc->empty_list);
-
- /* allocate page table buffer */
- iipc->page_table = malloc(HOST_PAGE_SIZE);
- if (iipc->page_table)
- bzero(iipc->page_table, HOST_PAGE_SIZE);
-
- /* PM */
- iipc->pm_prepare_D3 = 0;
-
- return 0;
-}
-
-/* The following definitions are to satisfy libsof linker errors */
-
-int ipc_stream_send_position(struct comp_dev *cdev,
- struct sof_ipc_stream_posn *posn)
-{
- return 0;
-}
-
-int ipc_stream_send_xrun(struct comp_dev *cdev,
- struct sof_ipc_stream_posn *posn)
-{
- return 0;
-}
diff --git a/src/host/schedule.c b/src/host/schedule.c
deleted file mode 100644
index 614a2b6..0000000
--- a/src/host/schedule.c
+++ /dev/null
@@ -1,98 +0,0 @@
-/*
- * Copyright (c) 2018, Intel Corporation
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- * * Redistributions of source code must retain the above copyright
- * notice, this list of conditions and the following disclaimer.
- * * Redistributions in binary form must reproduce the above copyright
- * notice, this list of conditions and the following disclaimer in the
- * documentation and/or other materials provided with the distribution.
- * * Neither the name of the Intel Corporation nor the
- * names of its contributors may be used to endorse or promote products
- * derived from this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
- * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
- * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
- * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
- * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
- * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
- * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
- * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
- * POSSIBILITY OF SUCH DAMAGE.
- *
- * Author: Seppo Ingalsuo <seppo.ingalsuo@linux.intel.com>
- * Liam Girdwood <liam.r.girdwood@linux.intel.com>
- * Keyon Jie <yang.jie@linux.intel.com>
- * Ranjani Sridharan <ranjani.sridharan@linux.intel.com>
- */
-
-#include <sof/audio/component.h>
-#include <sof/task.h>
-#include <stdint.h>
-#include <sof/wait.h>
-
-/* scheduler testbench definition */
-
-struct schedule_data {
- spinlock_t lock;
- struct list_item list; /* list of tasks in priority queue */
- uint32_t clock;
-};
-
-static struct schedule_data *sch;
-
-void schedule_task_complete(struct task *task)
-{
- list_item_del(&task->list);
- task->state = TASK_STATE_COMPLETED;
-}
-
-/* schedule task */
-void schedule_task(struct task *task, uint64_t start, uint64_t deadline)
-{
- task->deadline = deadline;
- list_item_prepend(&task->list, &sch->list);
- task->state = TASK_STATE_QUEUED;
-
- if (task->func)
- task->func(task->data);
-
- schedule_task_complete(task);
-}
-
-/* initialize scheduler */
-int scheduler_init(struct sof *sof)
-{
- trace_pipe("ScI");
-
- sch = malloc(sizeof(*sch));
- list_init(&sch->list);
- spinlock_init(&sch->lock);
-
- return 0;
-}
-
-/* The following definitions are to satisfy libsof linker errors */
-
-void schedule(void)
-{
-}
-
-void schedule_task_idle(struct task *task, uint64_t deadline)
-{
-}
-
-/* testbench work definition */
-
-void work_schedule_default(struct work *w, uint64_t timeout)
-{
-}
-
-void work_cancel_default(struct work *work)
-{
-}
diff --git a/src/host/testbench.c b/src/host/testbench.c
deleted file mode 100644
index 3f27299..0000000
--- a/src/host/testbench.c
+++ /dev/null
@@ -1,363 +0,0 @@
-/*
- * Copyright (c) 2018, Intel Corporation
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- * * Redistributions of source code must retain the above copyright
- * notice, this list of conditions and the following disclaimer.
- * * Redistributions in binary form must reproduce the above copyright
- * notice, this list of conditions and the following disclaimer in the
- * documentation and/or other materials provided with the distribution.
- * * Neither the name of the Intel Corporation nor the
- * names of its contributors may be used to endorse or promote products
- * derived from this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
- * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
- * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
- * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
- * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
- * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
- * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
- * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
- * POSSIBILITY OF SUCH DAMAGE.
- *
- * Author: Seppo Ingalsuo <seppo.ingalsuo@linux.intel.com>
- * Ranjani Sridharan <ranjani.sridharan@linux.intel.com>
- */
-
-#include <sof/ipc.h>
-#include <sof/list.h>
-#include <getopt.h>
-#include <dlfcn.h>
-#include "host/common_test.h"
-#include "host/topology.h"
-#include "host/trace.h"
-#include "host/file.h"
-
-#define TESTBENCH_NCH 2 /* Stereo */
-
-/* shared library look up table */
-struct shared_lib_table lib_table[NUM_WIDGETS_SUPPORTED] = {
-{"file", "", SND_SOC_TPLG_DAPM_AIF_IN, "", 0, NULL},
-{"vol", "libsof_volume.so", SND_SOC_TPLG_DAPM_PGA, "sys_comp_volume_init", 0,
- NULL},
-{"src", "libsof_src.so", SND_SOC_TPLG_DAPM_SRC, "sys_comp_src_init", 0, NULL},
-};
-
-/* main firmware context */
-static struct sof sof;
-static int fr_id; /* comp id for fileread */
-static int fw_id; /* comp id for filewrite */
-static int sched_id; /* comp id for scheduling comp */
-
-int debug;
-
-/*
- * Parse shared library from user input
- * Currently only handles volume and src comp
- * This function takes in the libraries to be used as an input in the format:
- * "vol=libsof_volume.so,src=libsof_src.so,..."
- * The function parses the above string to identify the following:
- * component type and the library name and sets up the library handle
- * for the component and stores it in the shared library table
- */
-static void parse_libraries(char *libs)
-{
- char *lib_token, *comp_token;
- char *token = strtok_r(libs, ",", &lib_token);
- char message[DEBUG_MSG_LEN];
- int index;
-
- while (token) {
-
- /* get component type */
- char *token1 = strtok_r(token, "=", &comp_token);
-
- /* get shared library index from library table */
- index = get_index_by_name(token1, lib_table);
-
- if (index < 0) {
- fprintf(stderr, "error: unsupported comp type\n");
- break;
- }
-
- /* get shared library name */
- token1 = strtok_r(NULL, "=", &comp_token);
- if (!token1)
- break;
-
- /* close default shared library object */
- if (lib_table[index].handle)
- dlclose(lib_table[index].handle);
-
- /* open volume shared library object */
- lib_table[index].handle = dlopen(token1, RTLD_LAZY);
- if (!lib_table[index].handle) {
- fprintf(stderr, "error: %s\n", dlerror());
- exit(EXIT_FAILURE);
- }
-
- sprintf(message, "opening shared lib %s\n", token1);
- debug_print(message);
-
- /* next library */
- token = strtok_r(NULL, ",", &lib_token);
- }
-}
-
-/* print usage for testbench */
-static void print_usage(char *executable)
-{
- printf("Usage: %s -i <input_file> -o <output_file> ", executable);
- printf("-t <tplg_file> -b <input_format> ");
- printf("-a <comp1=comp1_library,comp2=comp2_library>\n");
- printf("input_format should be S16_LE, S32_LE, S24_LE or FLOAT_LE\n");
- printf("Example Usage:\n");
- printf("%s -i in.txt -o out.txt -t test.tplg ", executable);
- printf("-r 48000 -R 96000 ");
- printf("-b S16_LE -a vol=libsof_volume.so\n");
-}
-
-/* free components */
-static void free_comps(void)
-{
- struct list_item *clist;
- struct list_item *temp;
- struct ipc_comp_dev *icd = NULL;
-
- list_for_item_safe(clist, temp, &sof.ipc->comp_list) {
- icd = container_of(clist, struct ipc_comp_dev, list);
- switch (icd->type) {
- case COMP_TYPE_COMPONENT:
- comp_free(icd->cd);
- list_item_del(&icd->list);
- rfree(icd);
- break;
- case COMP_TYPE_BUFFER:
- rfree(icd->cb->addr);
- rfree(icd->cb);
- list_item_del(&icd->list);
- rfree(icd);
- break;
- default:
- rfree(icd->pipeline);
- list_item_del(&icd->list);
- rfree(icd);
- break;
- }
- }
-}
-
-static int set_up_library_table(void)
-{
- int i;
-
- /* set up default shared libraries */
- for (i = 1; i < NUM_WIDGETS_SUPPORTED; i++) {
-
- /* open default shared library */
- lib_table[i].handle =
- dlopen(lib_table[i].library_name, RTLD_LAZY);
- if (!lib_table[i].handle) {
- fprintf(stderr, "error: %s\n", dlerror());
- return -EINVAL;
- }
- }
-
- return 0;
-}
-
-static void parse_input_args(int argc, char **argv)
-{
- int option = 0;
-
- while ((option = getopt(argc, argv, "hdi:o:t:b:a:r:R:")) != -1) {
- switch (option) {
- /* input sample file */
- case 'i':
- input_file = strdup(optarg);
- break;
-
- /* output sample file */
- case 'o':
- output_file = strdup(optarg);
- break;
-
- /* topology file */
- case 't':
- tplg_file = strdup(optarg);
- break;
-
- /* input samples bit format */
- case 'b':
- bits_in = strdup(optarg);
- break;
-
- /* override default libraries */
- case 'a':
- parse_libraries(optarg);
- break;
-
- /* input sample rate */
- case 'r':
- fs_in = atoi(optarg);
- break;
-
- /* output sample rate */
- case 'R':
- fs_out = atoi(optarg);
- break;
-
- /* enable debug prints */
- case 'd':
- debug = 1;
- break;
-
- /* print usage */
- case 'h':
- default:
- print_usage(argv[0]);
- exit(EXIT_FAILURE);
- }
- }
-}
-
-int main(int argc, char **argv)
-{
- struct ipc_comp_dev *pcm_dev;
- struct pipeline *p;
- struct sof_ipc_pipe_new *ipc_pipe;
- struct comp_dev *cd;
- struct file_comp_data *frcd, *fwcd;
- char pipeline[DEBUG_MSG_LEN];
- clock_t tic, toc;
- double c_realtime, t_exec;
- int n_in, n_out, ret;
- int i;
-
- /* initialize input and output sample rates */
- fs_in = 0;
- fs_out = 0;
-
- /* set up shared library look up table */
- ret = set_up_library_table();
- if (ret < 0) {
- fprintf(stderr, "error: setting up shared libraried\n");
- exit(EXIT_FAILURE);
- }
-
- /* set up trace class definition table from trace header */
- ret = setup_trace_table();
- if (ret < 0) {
- fprintf(stderr, "error: setting up trace header table\n");
- exit(EXIT_FAILURE);
- }
- /* command line arguments*/
- parse_input_args(argc, argv);
-
- /* check args */
- if (!tplg_file || !input_file || !output_file || !bits_in) {
- print_usage(argv[0]);
- exit(EXIT_FAILURE);
- }
-
- /* initialize ipc and scheduler */
- if (tb_pipeline_setup(&sof) < 0) {
- fprintf(stderr, "error: pipeline init\n");
- exit(EXIT_FAILURE);
- }
-
- /* parse topology file and create pipeline */
- if (parse_topology(tplg_file, &sof, &fr_id, &fw_id, &sched_id, bits_in,
- input_file, output_file, lib_table, pipeline) < 0) {
- fprintf(stderr, "error: parsing topology\n");
- exit(EXIT_FAILURE);
- }
-
- /* Get pointers to fileread and filewrite */
- pcm_dev = ipc_get_comp(sof.ipc, fw_id);
- fwcd = comp_get_drvdata(pcm_dev->cd);
- pcm_dev = ipc_get_comp(sof.ipc, fr_id);
- frcd = comp_get_drvdata(pcm_dev->cd);
-
- /* Run pipeline until EOF from fileread */
- pcm_dev = ipc_get_comp(sof.ipc, sched_id);
- p = pcm_dev->cd->pipeline;
- ipc_pipe = &p->ipc_pipe;
-
- /* input and output sample rate */
- if (!fs_in)
- fs_in = ipc_pipe->deadline * ipc_pipe->frames_per_sched;
-
- if (!fs_out)
- fs_out = ipc_pipe->deadline * ipc_pipe->frames_per_sched;
-
- /* set pipeline params and trigger start */
- if (tb_pipeline_start(sof.ipc, TESTBENCH_NCH, bits_in, ipc_pipe) < 0) {
- fprintf(stderr, "error: pipeline params\n");
- exit(EXIT_FAILURE);
- }
-
- cd = pcm_dev->cd;
- tb_enable_trace(false); /* reduce trace output */
- tic = clock();
-
- while (frcd->fs.reached_eof == 0)
- pipeline_schedule_copy(p, 0);
-
- if (!frcd->fs.reached_eof)
- printf("warning: possible pipeline xrun\n");
-
- /* reset and free pipeline */
- toc = clock();
- tb_enable_trace(true);
- ret = pipeline_reset(p, cd);
- if (ret < 0) {
- fprintf(stderr, "error: pipeline reset\n");
- exit(EXIT_FAILURE);
- }
-
- n_in = frcd->fs.n;
- n_out = fwcd->fs.n;
- t_exec = (double)(toc - tic) / CLOCKS_PER_SEC;
- c_realtime = (double)n_out / TESTBENCH_NCH / fs_out / t_exec;
-
- /* free all components/buffers in pipeline */
- free_comps();
-
- /* free trace class defs */
- free_trace_table();
-
- /* print test summary */
- printf("==========================================================\n");
- printf(" Test Summary\n");
- printf("==========================================================\n");
- printf("Test Pipeline:\n");
- printf("%s\n", pipeline);
- printf("Input bit format: %s\n", bits_in);
- printf("Input sample rate: %d\n", fs_in);
- printf("Output sample rate: %d\n", fs_out);
- printf("Output written to file: \"%s\"\n", output_file);
- printf("Input sample count: %d\n", n_in);
- printf("Output sample count: %d\n", n_out);
- printf("Total execution time: %.2f us, %.2f x realtime\n",
- 1e3 * t_exec, c_realtime);
-
- /* free all other data */
- free(bits_in);
- free(input_file);
- free(tplg_file);
- free(output_file);
-
- /* close shared library objects */
- for (i = 0; i < NUM_WIDGETS_SUPPORTED; i++) {
- if (lib_table[i].handle)
- dlclose(lib_table[i].handle);
- }
-
- return EXIT_SUCCESS;
-}
diff --git a/src/host/topology.c b/src/host/topology.c
deleted file mode 100644
index 831c5cf..0000000
--- a/src/host/topology.c
+++ /dev/null
@@ -1,1041 +0,0 @@
-/*
- * Copyright (c) 2018, Intel Corporation
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- * * Redistributions of source code must retain the above copyright
- * notice, this list of conditions and the following disclaimer.
- * * Redistributions in binary form must reproduce the above copyright
- * notice, this list of conditions and the following disclaimer in the
- * documentation and/or other materials provided with the distribution.
- * * Neither the name of the Intel Corporation nor the
- * names of its contributors may be used to endorse or promote products
- * derived from this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
- * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
- * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
- * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
- * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
- * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
- * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
- * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
- * POSSIBILITY OF SUCH DAMAGE.
- *
- * Author: Ranjani Sridharan <ranjani.sridharan@linux.intel.com>
- * Liam Girdwood <liam.r.girdwood@linux.intel.com>
- */
-
-/*
- * Topology parser to parse topology bin file
- * and set up components and pipeline
- */
-
-#include <sof/ipc.h>
-#include <stdio.h>
-#include <string.h>
-#include <dlfcn.h>
-#include <sof/audio/component.h>
-#include "host/topology.h"
-#include "host/file.h"
-
-FILE *file;
-char pipeline_string[DEBUG_MSG_LEN];
-struct shared_lib_table *lib_table;
-
-/*
- * Register component driver
- * Only needed once per component type
- */
-static void register_comp(int comp_type)
-{
- int index;
- char message[DEBUG_MSG_LEN];
-
- /* register file comp driver (no shared library needed) */
- if (comp_type == SND_SOC_TPLG_DAPM_DAI_IN ||
- comp_type == SND_SOC_TPLG_DAPM_AIF_IN) {
- if (!lib_table[0].register_drv) {
- sys_comp_file_init();
- lib_table[0].register_drv = 1;
- debug_print("registered file comp driver\n");
- }
- return;
- }
-
- /* get index of comp in shared library table */
- index = get_index_by_type(comp_type, lib_table);
- if (index < 0)
- return;
-
- /* register comp driver if not already registered */
- if (!lib_table[index].register_drv) {
- sprintf(message, "registered comp driver for %s\n",
- lib_table[index].comp_name);
- debug_print(message);
-
- /* register comp driver */
- void (*comp_init)() =
- (void (*)(void))dlsym(lib_table[index].handle,
- lib_table[index].comp_init);
- comp_init();
- lib_table[index].register_drv = 1;
- }
-
-}
-
-/* read vendor tuples array from topology */
-static int read_array(struct snd_soc_tplg_vendor_array *array)
-{
- struct snd_soc_tplg_vendor_uuid_elem uuid;
- struct snd_soc_tplg_vendor_string_elem string;
- struct snd_soc_tplg_vendor_value_elem value;
- int j, ret = 0;
- size_t size;
-
- switch (array->type) {
- case SND_SOC_TPLG_TUPLE_TYPE_UUID:
-
- /* copy uuid elems into array */
- for (j = 0; j < array->num_elems; j++) {
- size = sizeof(struct snd_soc_tplg_vendor_uuid_elem);
- ret = fread(&uuid, size, 1, file);
- if (ret != 1)
- return -EINVAL;
- memcpy(&array->uuid[j], &uuid, size);
- }
- break;
- case SND_SOC_TPLG_TUPLE_TYPE_STRING:
-
- /* copy string elems into array */
- for (j = 0; j < array->num_elems; j++) {
- size = sizeof(struct snd_soc_tplg_vendor_string_elem);
- ret = fread(&string, size, 1, file);
- if (ret != 1)
- return -EINVAL;
- memcpy(&array->string[j], &string, size);
- }
- break;
- case SND_SOC_TPLG_TUPLE_TYPE_BOOL:
- case SND_SOC_TPLG_TUPLE_TYPE_BYTE:
- case SND_SOC_TPLG_TUPLE_TYPE_WORD:
- case SND_SOC_TPLG_TUPLE_TYPE_SHORT:
- /* copy value elems into array */
- for (j = 0; j < array->num_elems; j++) {
- size = sizeof(struct snd_soc_tplg_vendor_value_elem);
- ret = fread(&value, size, 1, file);
- if (ret != 1)
- return -EINVAL;
- memcpy(&array->value[j], &value, size);
- }
- break;
- default:
- fprintf(stderr, "error: unknown token type %d\n", array->type);
- return -EINVAL;
- }
- return 0;
-}
-
-/* load pipeline graph DAPM widget*/
-static int load_graph(struct sof *sof, struct comp_info *temp_comp_list,
- int count, int num_comps, int pipeline_id)
-{
- struct sof_ipc_pipe_comp_connect connection;
- struct snd_soc_tplg_dapm_graph_elem *graph_elem;
- size_t size;
- int i, j, ret = 0;
-
- /* allocate memory for graph elem */
- size = sizeof(struct snd_soc_tplg_dapm_graph_elem);
- graph_elem = (struct snd_soc_tplg_dapm_graph_elem *)malloc(size);
- if (!graph_elem) {
- fprintf(stderr, "error: mem alloc\n");
- return -EINVAL;
- }
-
- /* set up component connections */
- connection.source_id = -1;
- connection.sink_id = -1;
- for (i = 0; i < count; i++) {
- size = sizeof(struct snd_soc_tplg_dapm_graph_elem);
- ret = fread(graph_elem, size, 1, file);
- if (ret != 1)
- return -EINVAL;
-
- /* look up component id from the component list */
- for (j = 0; j < num_comps; j++) {
- if (strcmp(temp_comp_list[j].name,
- graph_elem->source) == 0)
- connection.source_id = temp_comp_list[j].id;
-
- if (strcmp(temp_comp_list[j].name,
- graph_elem->sink) == 0)
- connection.sink_id = temp_comp_list[j].id;
- }
-
- strcat(pipeline_string, graph_elem->source);
- strcat(pipeline_string, "->");
-
- if (i == (count - 1))
- strcat(pipeline_string, graph_elem->sink);
-
- /* connect source and sink */
- if (connection.source_id != -1 && connection.sink_id != -1)
- if (ipc_comp_connect(sof->ipc, &connection) < 0) {
- fprintf(stderr, "error: comp connect\n");
- return -EINVAL;
- }
- }
-
- /* pipeline complete after pipeline connections are established */
- for (i = 0; i < num_comps; i++) {
- if (temp_comp_list[i].pipeline_id == pipeline_id &&
- temp_comp_list[i].type == SND_SOC_TPLG_DAPM_SCHEDULER)
- ipc_pipeline_complete(sof->ipc, temp_comp_list[i].id);
- }
-
- free(graph_elem);
- return 0;
-}
-
-/* load buffer DAPM widget */
-static int load_buffer(struct sof *sof, int comp_id, int pipeline_id, int size)
-{
- struct sof_ipc_buffer buffer;
- struct snd_soc_tplg_vendor_array *array = NULL;
- int ret = 0;
-
- /* configure buffer */
- buffer.comp.id = comp_id;
- buffer.comp.pipeline_id = pipeline_id;
-
- /* allocate memory for vendor tuple array */
- array = (struct snd_soc_tplg_vendor_array *)malloc(size);
- ret = fread(array, sizeof(struct snd_soc_tplg_vendor_array), 1, file);
- if (ret != 1)
- return -EINVAL;
-
- read_array(array);
- /* parse buffer tokens */
- ret = sof_parse_tokens(&buffer, buffer_tokens,
- ARRAY_SIZE(buffer_tokens), array,
- size);
-
- /* create buffer component */
- if (ipc_buffer_new(sof->ipc, &buffer) < 0) {
- fprintf(stderr, "error: buffer new\n");
- return -EINVAL;
- }
- free(array);
- return 0;
-}
-
-/* load fileread component */
-static int load_fileread(struct sof *sof, int comp_id, int pipeline_id,
- int size, char *bits_in, int *fr_id, int *sched_id)
-{
- struct sof_ipc_comp_file fileread;
- struct snd_soc_tplg_vendor_array *array = NULL;
- size_t total_array_size = 0, read_size;
- int ret = 0;
-
- fileread.config.frame_fmt = find_format(bits_in);
-
- /* allocate memory for vendor tuple array */
- array = (struct snd_soc_tplg_vendor_array *)malloc(size);
- if (!array) {
- fprintf(stderr, "error: mem alloc\n");
- return -EINVAL;
- }
-
- /* read vendor tokens */
- while (total_array_size < size) {
- read_size = sizeof(struct snd_soc_tplg_vendor_array);
- ret = fread(array, read_size, 1, file);
- if (ret != 1)
- return -EINVAL;
- read_array(array);
-
- /* parse comp tokens */
- ret = sof_parse_tokens(&fileread.config, comp_tokens,
- ARRAY_SIZE(comp_tokens), array,
- array->size);
- if (ret != 0) {
- fprintf(stderr, "error: parse fileread tokens %d\n",
- size);
- return -EINVAL;
- }
- total_array_size += array->size;
- }
-
- /* configure fileread */
- fileread.fn = strdup(input_file);
- fileread.mode = FILE_READ;
- fileread.comp.id = comp_id;
-
- /* use fileread comp as scheduling comp */
- *fr_id = *sched_id = comp_id;
- fileread.comp.hdr.size = sizeof(struct sof_ipc_comp_file);
- fileread.comp.type = SOF_COMP_FILEREAD;
- fileread.comp.pipeline_id = pipeline_id;
-
- /* create fileread component */
- if (ipc_comp_new(sof->ipc, (struct sof_ipc_comp *)&fileread) < 0) {
- fprintf(stderr, "error: comp register\n");
- return -EINVAL;
- }
-
- free(array);
- free(fileread.fn);
- return 0;
-}
-
-/* load filewrite component */
-static int load_filewrite(struct sof *sof, int comp_id, int pipeline_id,
- int size, int *fw_id)
-{
- struct sof_ipc_comp_file filewrite;
- struct snd_soc_tplg_vendor_array *array = NULL;
- size_t total_array_size = 0, read_size;
- int ret = 0;
-
- /* allocate memory for vendor tuple array */
- array = (struct snd_soc_tplg_vendor_array *)malloc(size);
- if (!array) {
- fprintf(stderr, "error: mem alloc\n");
- return -EINVAL;
- }
-
- /* read vendor tokens */
- while (total_array_size < size) {
- read_size = sizeof(struct snd_soc_tplg_vendor_array);
- ret = fread(array, read_size, 1, file);
- if (ret != 1)
- return -EINVAL;
-
- read_array(array);
-
- /* parse comp tokens */
- ret = sof_parse_tokens(&filewrite.config, comp_tokens,
- ARRAY_SIZE(comp_tokens), array,
- array->size);
- if (ret != 0) {
- fprintf(stderr, "error: parse filewrite tokens %d\n",
- size);
- return -EINVAL;
- }
- total_array_size += array->size;
- }
-
- /* configure filewrite */
- filewrite.fn = strdup(output_file);
- filewrite.comp.id = comp_id;
- filewrite.mode = FILE_WRITE;
- *fw_id = comp_id;
- filewrite.comp.hdr.size = sizeof(struct sof_ipc_comp_file);
- filewrite.comp.type = SOF_COMP_FILEREAD;
- filewrite.comp.pipeline_id = pipeline_id;
-
- /* create filewrite component */
- if (ipc_comp_new(sof->ipc, (struct sof_ipc_comp *)&filewrite) < 0) {
- fprintf(stderr, "error: comp register\n");
- return -EINVAL;
- }
-
- free(array);
- free(filewrite.fn);
- return 0;
-}
-
-/* load pda dapm widget */
-static int load_pga(struct sof *sof, int comp_id, int pipeline_id,
- int size)
-{
- struct sof_ipc_comp_volume volume;
- struct snd_soc_tplg_vendor_array *array = NULL;
- size_t total_array_size = 0, read_size;
- int ret = 0;
-
- /* allocate memory for vendor tuple array */
- array = (struct snd_soc_tplg_vendor_array *)malloc(size);
- if (!array) {
- fprintf(stderr, "error: mem alloc\n");
- return -EINVAL;
- }
-
- /* read vendor tokens */
- while (total_array_size < size) {
- read_size = sizeof(struct snd_soc_tplg_vendor_array);
- ret = fread(array, read_size, 1, file);
- if (ret != 1)
- return -EINVAL;
- read_array(array);
-
- /* parse volume tokens */
- ret = sof_parse_tokens(&volume.config, comp_tokens,
- ARRAY_SIZE(comp_tokens), array,
- array->size);
- if (ret != 0) {
- fprintf(stderr, "error: parse pga tokens %d\n", size);
- return -EINVAL;
- }
- total_array_size += array->size;
- }
-
- /* configure volume */
- volume.comp.id = comp_id;
- volume.comp.hdr.size = sizeof(struct sof_ipc_comp_volume);
- volume.comp.type = SOF_COMP_VOLUME;
- volume.comp.pipeline_id = pipeline_id;
-
- /* load volume component */
- if (ipc_comp_new(sof->ipc, (struct sof_ipc_comp *)&volume) < 0) {
- fprintf(stderr, "error: comp register\n");
- return -EINVAL;
- }
-
- free(array);
- return 0;
-}
-
-/* load scheduler dapm widget */
-static int load_pipeline(struct sof *sof, struct sof_ipc_pipe_new *pipeline,
- int comp_id, int pipeline_id, int size, int *sched_id)
-{
- struct snd_soc_tplg_vendor_array *array = NULL;
- size_t total_array_size = 0, read_size;
- int ret = 0;
-
- /* configure pipeline */
- pipeline->sched_id = *sched_id;
- pipeline->comp_id = comp_id;
- pipeline->pipeline_id = pipeline_id;
-
- /* allocate memory for vendor tuple array */
- array = (struct snd_soc_tplg_vendor_array *)malloc(size);
- if (!array) {
- fprintf(stderr, "error: mem alloc\n");
- return -EINVAL;
- }
-
- /* read vendor arrays */
- while (total_array_size < size) {
- read_size = sizeof(struct snd_soc_tplg_vendor_array);
- ret = fread(array, read_size, 1, file);
- if (ret != 1)
- return -EINVAL;
-
- ret = read_array(array);
- if (ret < 0)
- return -EINVAL;
-
- /* parse scheduler tokens */
- ret = sof_parse_tokens(pipeline, sched_tokens,
- ARRAY_SIZE(sched_tokens), array,
- array->size);
- if (ret != 0) {
- fprintf(stderr, "error: parse pipeline tokens %d\n",
- size);
- return -EINVAL;
- }
- total_array_size += array->size;
- }
-
- /* Create pipeline */
- if (ipc_pipeline_new(sof->ipc, pipeline) < 0) {
- fprintf(stderr, "error: pipeline new\n");
- return -EINVAL;
- }
-
- free(array);
- return 0;
-}
-
-/* load dapm widget kcontrols
- * we dont use controls in the testbench atm.
- * so just skip to the next dapm widget
- */
-static int load_controls(struct sof *sof, int num_kcontrols)
-{
- struct snd_soc_tplg_ctl_hdr *ctl_hdr;
- struct snd_soc_tplg_mixer_control *mixer_ctl;
- struct snd_soc_tplg_enum_control *enum_ctl;
- struct snd_soc_tplg_bytes_control *bytes_ctl;
- size_t read_size, size;
- int j, ret = 0;
-
- /* allocate memory */
- size = sizeof(struct snd_soc_tplg_ctl_hdr);
- ctl_hdr = (struct snd_soc_tplg_ctl_hdr *)malloc(size);
- if (!ctl_hdr) {
- fprintf(stderr, "error: mem alloc\n");
- return -EINVAL;
- }
-
- size = sizeof(struct snd_soc_tplg_mixer_control);
- mixer_ctl = (struct snd_soc_tplg_mixer_control *)malloc(size);
- if (!mixer_ctl) {
- fprintf(stderr, "error: mem alloc\n");
- return -EINVAL;
- }
-
- size = sizeof(struct snd_soc_tplg_enum_control);
- enum_ctl = (struct snd_soc_tplg_enum_control *)malloc(size);
- if (!enum_ctl) {
- fprintf(stderr, "error: mem alloc\n");
- return -EINVAL;
- }
-
- size = sizeof(struct snd_soc_tplg_bytes_control);
- bytes_ctl = (struct snd_soc_tplg_bytes_control *)malloc(size);
- if (!bytes_ctl) {
- fprintf(stderr, "error: mem alloc\n");
- return -EINVAL;
- }
-
- for (j = 0; j < num_kcontrols; j++) {
- /* read control header */
- read_size = sizeof(struct snd_soc_tplg_ctl_hdr);
- ret = fread(ctl_hdr, read_size, 1, file);
- if (ret != 1)
- return -EINVAL;
-
- /* load control based on type */
- switch (ctl_hdr->ops.info) {
- case SND_SOC_TPLG_CTL_VOLSW:
- case SND_SOC_TPLG_CTL_STROBE:
- case SND_SOC_TPLG_CTL_VOLSW_SX:
- case SND_SOC_TPLG_CTL_VOLSW_XR_SX:
- case SND_SOC_TPLG_CTL_RANGE:
- case SND_SOC_TPLG_DAPM_CTL_VOLSW:
-
- /* load mixer type control */
- read_size = sizeof(struct snd_soc_tplg_ctl_hdr);
- fseek(file, read_size * -1, SEEK_CUR);
- read_size = sizeof(struct snd_soc_tplg_mixer_control);
- ret = fread(mixer_ctl, read_size, 1, file);
- if (ret != 1)
- return -EINVAL;
-
- /* skip mixer private data */
- fseek(file, mixer_ctl->priv.size, SEEK_CUR);
- break;
- case SND_SOC_TPLG_CTL_ENUM:
- case SND_SOC_TPLG_CTL_ENUM_VALUE:
- case SND_SOC_TPLG_DAPM_CTL_ENUM_DOUBLE:
- case SND_SOC_TPLG_DAPM_CTL_ENUM_VIRT:
- case SND_SOC_TPLG_DAPM_CTL_ENUM_VALUE:
-
- /* load enum type control */
- read_size = sizeof(struct snd_soc_tplg_ctl_hdr);
- fseek(file, read_size * -1, SEEK_CUR);
- read_size = sizeof(struct snd_soc_tplg_enum_control);
- ret = fread(enum_ctl, read_size, 1, file);
- if (ret != 1)
- return -EINVAL;
-
- /* skip enum private data */
- fseek(file, enum_ctl->priv.size, SEEK_CUR);
- break;
- case SND_SOC_TPLG_CTL_BYTES:
-
- /* load bytes type controls */
- read_size = sizeof(struct snd_soc_tplg_ctl_hdr);
- fseek(file, read_size * -1, SEEK_CUR);
- read_size = sizeof(struct snd_soc_tplg_bytes_control);
- ret = fread(bytes_ctl, read_size, 1, file);
- if (ret != 1)
- return -EINVAL;
-
- /* skip bytes private data */
- fseek(file, bytes_ctl->priv.size, SEEK_CUR);
- break;
- default:
- printf("info: control type not supported\n");
- return -EINVAL;
- }
- }
-
- /* free all data */
- free(mixer_ctl);
- free(enum_ctl);
- free(bytes_ctl);
- free(ctl_hdr);
- return 0;
-}
-
-/* load src dapm widget */
-static int load_src(struct sof *sof, int comp_id, int pipeline_id,
- int size)
-{
- struct sof_ipc_comp_src src = {0};
- struct snd_soc_tplg_vendor_array *array = NULL;
- size_t total_array_size = 0, read_size;
- int ret = 0;
-
- /* allocate memory for vendor tuple array */
- array = (struct snd_soc_tplg_vendor_array *)malloc(size);
- if (!array) {
- fprintf(stderr, "error: mem alloc for src vendor array\n");
- return -EINVAL;
- }
-
- /* read vendor tokens */
- while (total_array_size < size) {
- read_size = sizeof(struct snd_soc_tplg_vendor_array);
- ret = fread(array, read_size, 1, file);
- if (ret != 1)
- return -EINVAL;
- read_array(array);
-
- /* parse comp tokens */
- ret = sof_parse_tokens(&src.config, comp_tokens,
- ARRAY_SIZE(comp_tokens), array,
- array->size);
- if (ret != 0) {
- fprintf(stderr, "error: parse src comp_tokens %d\n",
- size);
- return -EINVAL;
- }
-
- /* parse src tokens */
- ret = sof_parse_tokens(&src, src_tokens,
- ARRAY_SIZE(src_tokens), array,
- array->size);
- if (ret != 0) {
- fprintf(stderr, "error: parse src tokens %d\n", size);
- return -EINVAL;
- }
-
- total_array_size += array->size;
-
- /* read next array */
- array = (void *)array + array->size;
- }
-
- array = (void *)array - size;
-
- /* set testbench input and output sample rate from topology */
- if (!fs_out) {
- fs_out = src.sink_rate;
-
- if (!fs_in)
- fs_in = src.source_rate;
- else
- src.source_rate = fs_in;
- } else {
- src.sink_rate = fs_out;
- }
-
- /* configure src */
- src.comp.id = comp_id;
- src.comp.hdr.size = sizeof(struct sof_ipc_comp_src);
- src.comp.type = SOF_COMP_SRC;
- src.comp.pipeline_id = pipeline_id;
-
- /* load src component */
- if (ipc_comp_new(sof->ipc, (struct sof_ipc_comp *)&src) < 0) {
- fprintf(stderr, "error: new src comp\n");
- return -EINVAL;
- }
-
- free(array);
- return 0;
-}
-
-/* load dapm widget */
-static int load_widget(struct sof *sof, int *fr_id, int *fw_id,
- int *sched_id, char *bits_in,
- struct comp_info *temp_comp_list,
- struct sof_ipc_pipe_new *pipeline, int comp_id,
- int comp_index, int pipeline_id)
-{
- struct snd_soc_tplg_dapm_widget *widget;
- char message[DEBUG_MSG_LEN];
- size_t read_size, size;
- int ret = 0;
-
- /* allocate memory for widget */
- size = sizeof(struct snd_soc_tplg_dapm_widget);
- widget = (struct snd_soc_tplg_dapm_widget *)malloc(size);
- if (!widget) {
- fprintf(stderr, "error: mem alloc\n");
- return -EINVAL;
- }
-
- /* read widget data */
- read_size = sizeof(struct snd_soc_tplg_dapm_widget);
- ret = fread(widget, read_size, 1, file);
- if (ret != 1)
- return -EINVAL;
-
- /*
- * create a list with all widget info
- * containing mapping between component names and ids
- * which will be used for setting up component connections
- */
- temp_comp_list[comp_index].id = comp_id;
- temp_comp_list[comp_index].name = strdup(widget->name);
- temp_comp_list[comp_index].type = widget->id;
- temp_comp_list[comp_index].pipeline_id = pipeline_id;
-
- sprintf(message, "loading widget %s id %d\n",
- temp_comp_list[comp_index].name,
- temp_comp_list[comp_index].id);
- debug_print(message);
-
- /* register comp driver */
- register_comp(temp_comp_list[comp_index].type);
-
- /* load widget based on type */
- switch (temp_comp_list[comp_index].type) {
- /* load pga widget */
- case(SND_SOC_TPLG_DAPM_PGA):
- if (load_pga(sof, temp_comp_list[comp_index].id,
- pipeline_id, widget->priv.size) < 0) {
- fprintf(stderr, "error: load pga\n");
- return -EINVAL;
- }
- break;
-
- /* replace pcm playback component with fileread in testbench */
- case(SND_SOC_TPLG_DAPM_AIF_IN):
- if (load_fileread(sof, temp_comp_list[comp_index].id,
- pipeline_id, widget->priv.size, bits_in,
- fr_id, sched_id) < 0) {
- fprintf(stderr, "error: load fileread\n");
- return -EINVAL;
- }
- break;
-
- /* replace dai in component with filewrite in testbench */
- case(SND_SOC_TPLG_DAPM_DAI_IN):
- if (load_filewrite(sof, temp_comp_list[comp_index].id,
- pipeline_id, widget->priv.size,
- fw_id) < 0) {
- fprintf(stderr, "error: load filewrite\n");
- return -EINVAL;
- }
- break;
-
- /* load buffer */
- case(SND_SOC_TPLG_DAPM_BUFFER):
- if (load_buffer(sof, temp_comp_list[comp_index].id,
- pipeline_id, widget->priv.size) < 0) {
- fprintf(stderr, "error: load buffer\n");
- return -EINVAL;
- }
- break;
-
- /* load pipeline */
- case(SND_SOC_TPLG_DAPM_SCHEDULER):
- if (load_pipeline(sof, pipeline,
- temp_comp_list[comp_index].id,
- pipeline_id,
- widget->priv.size,
- sched_id) < 0) {
- fprintf(stderr, "error: load buffer\n");
- return -EINVAL;
- }
- break;
-
- /* load src widget */
- case(SND_SOC_TPLG_DAPM_SRC):
- if (load_src(sof, temp_comp_list[comp_index].id,
- pipeline_id, widget->priv.size) < 0) {
- fprintf(stderr, "error: load src\n");
- return -EINVAL;
- }
- break;
-
- /* unsupported widgets */
- default:
- printf("info: Widget type not supported %d\n",
- widget->id);
- break;
- }
-
- /* load widget kcontrols */
- if (widget->num_kcontrols > 0)
- if (load_controls(sof, widget->num_kcontrols) < 0) {
- fprintf(stderr, "error: load buffer\n");
- return -EINVAL;
- }
-
- free(widget);
- return 0;
-}
-
-/* parse topology file and set up pipeline */
-int parse_topology(char *filename, struct sof *sof, int *fr_id, int *fw_id,
- int *sched_id, char *bits_in, char *in_file,
- char *out_file, struct shared_lib_table *library_table,
- char *pipeline_msg)
-{
- struct snd_soc_tplg_hdr *hdr;
-
- struct comp_info *temp_comp_list = NULL;
- struct sof_ipc_pipe_new pipeline;
- char message[DEBUG_MSG_LEN];
- int next_comp_id = 0, num_comps = 0;
- int i, ret = 0;
- size_t file_size, size;
-
- /* open topology file */
- file = fopen(tplg_file, "rb");
- if (!file) {
- fprintf(stderr, "error: opening file %s\n", tplg_file);
- return -EINVAL;
- }
-
- lib_table = library_table;
-
- /* file size */
- fseek(file, 0, SEEK_END);
- file_size = ftell(file);
- fseek(file, 0, SEEK_SET);
-
- /* allocate memory */
- size = sizeof(struct snd_soc_tplg_hdr);
- hdr = (struct snd_soc_tplg_hdr *)malloc(size);
- if (!hdr) {
- fprintf(stderr, "error: mem alloc\n");
- return -EINVAL;
- }
-
- debug_print("topology parsing start\n");
- while (1) {
- /* read topology header */
- ret = fread(hdr, sizeof(struct snd_soc_tplg_hdr), 1, file);
- if (ret != 1)
- return -EINVAL;
-
- sprintf(message, "type: %x, size: 0x%x count: %d index: %d\n",
- hdr->type, hdr->payload_size, hdr->count, hdr->index);
- debug_print(message);
-
- /* parse header and load the next block based on type */
- switch (hdr->type) {
- /* load dapm widget */
- case SND_SOC_TPLG_TYPE_DAPM_WIDGET:
- sprintf(message, "number of DAPM widgets %d\n",
- hdr->count);
- debug_print(message);
- size = sizeof(struct comp_info) * hdr->count;
- temp_comp_list = (struct comp_info *)malloc(size);
- num_comps = hdr->count;
-
- for (i = 0; i < hdr->count; i++)
- load_widget(sof, fr_id, fw_id, sched_id,
- bits_in, temp_comp_list,
- &pipeline, next_comp_id++,
- i, hdr->index);
- break;
-
- /* set up component connections from pipeline graph */
- case SND_SOC_TPLG_TYPE_DAPM_GRAPH:
- if (load_graph(sof, temp_comp_list, hdr->count,
- num_comps, hdr->index) < 0) {
- fprintf(stderr, "error: pipeline graph\n");
- return -EINVAL;
- }
-
- if (ftell(file) == file_size)
- goto finish;
- break;
- default:
- fseek(file, hdr->payload_size, SEEK_CUR);
- if (ftell(file) == file_size)
- goto finish;
- break;
- }
- }
-finish:
- debug_print("topology parsing end\n");
- strcpy(pipeline_msg, pipeline_string);
-
- /* free all data */
- free(hdr);
-
- for (i = 0; i < num_comps; i++)
- free(temp_comp_list[i].name);
-
- free(temp_comp_list);
- fclose(file);
- return 0;
-}
-
-/* parse vendor tokens in topology */
-int sof_parse_tokens(void *object, const struct sof_topology_token *tokens,
- int count, struct snd_soc_tplg_vendor_array *array,
- int priv_size)
-{
- int asize;
-
- while (priv_size > 0) {
- asize = array->size;
-
- /* validate asize */
- if (asize < 0) { /* FIXME: A zero-size array makes no sense */
- fprintf(stderr, "error: invalid array size 0x%x\n",
- asize);
- return -EINVAL;
- }
-
- /* make sure there is enough data before parsing */
- priv_size -= asize;
-
- if (priv_size < 0) {
- fprintf(stderr, "error: invalid array size 0x%x\n",
- asize);
- return -EINVAL;
- }
-
- /* call correct parser depending on type */
- switch (array->type) {
- case SND_SOC_TPLG_TUPLE_TYPE_UUID:
- sof_parse_uuid_tokens(object, tokens, count,
- array);
- break;
- case SND_SOC_TPLG_TUPLE_TYPE_STRING:
- sof_parse_string_tokens(object, tokens, count,
- array);
- break;
- case SND_SOC_TPLG_TUPLE_TYPE_BOOL:
- case SND_SOC_TPLG_TUPLE_TYPE_BYTE:
- case SND_SOC_TPLG_TUPLE_TYPE_WORD:
- case SND_SOC_TPLG_TUPLE_TYPE_SHORT:
- sof_parse_word_tokens(object, tokens, count,
- array);
- break;
- default:
- fprintf(stderr, "error: unknown token type %d\n",
- array->type);
- return -EINVAL;
- }
- }
- return 0;
-}
-
-void sof_parse_word_tokens(void *object,
- const struct sof_topology_token *tokens,
- int count,
- struct snd_soc_tplg_vendor_array *array)
-{
- struct snd_soc_tplg_vendor_value_elem *elem;
- int i, j;
-
- /* parse element by element */
- for (i = 0; i < array->num_elems; i++) {
- elem = &array->value[i];
-
- /* search for token */
- for (j = 0; j < count; j++) {
- /* match token type */
- if (tokens[j].type != SND_SOC_TPLG_TUPLE_TYPE_WORD)
- continue;
-
- /* match token id */
- if (tokens[j].token != elem->token)
- continue;
-
- /* matched - now load token */
- tokens[j].get_token(elem, object, tokens[j].offset,
- tokens[j].size);
- }
- }
-}
-
-void sof_parse_uuid_tokens(void *object,
- const struct sof_topology_token *tokens,
- int count,
- struct snd_soc_tplg_vendor_array *array)
-{
- struct snd_soc_tplg_vendor_uuid_elem *elem;
- int i, j;
-
- /* parse element by element */
- for (i = 0; i < array->num_elems; i++) {
- elem = &array->uuid[i];
-
- /* search for token */
- for (j = 0; j < count; j++) {
- /* match token type */
- if (tokens[j].type != SND_SOC_TPLG_TUPLE_TYPE_UUID)
- continue;
-
- /* match token id */
- if (tokens[j].token != elem->token)
- continue;
-
- /* matched - now load token */
- tokens[j].get_token(elem, object, tokens[j].offset,
- tokens[j].size);
- }
- }
-}
-
-void sof_parse_string_tokens(void *object,
- const struct sof_topology_token *tokens,
- int count,
- struct snd_soc_tplg_vendor_array *array)
-{
- struct snd_soc_tplg_vendor_string_elem *elem;
- int i, j;
-
- /* parse element by element */
- for (i = 0; i < array->num_elems; i++) {
- elem = &array->string[i];
-
- /* search for token */
- for (j = 0; j < count; j++) {
- /* match token type */
- if (tokens[j].type != SND_SOC_TPLG_TUPLE_TYPE_STRING)
- continue;
-
- /* match token id */
- if (tokens[j].token != elem->token)
- continue;
-
- /* matched - now load token */
- tokens[j].get_token(elem, object, tokens[j].offset,
- tokens[j].size);
- }
- }
-}
-
-enum sof_ipc_frame find_format(const char *name)
-{
- int i;
-
- for (i = 0; i < ARRAY_SIZE(sof_frames); i++) {
- if (strcmp(name, sof_frames[i].name) == 0)
- return sof_frames[i].frame;
- }
-
- /* use s32le if nothing is specified */
- return SOF_IPC_FRAME_S32_LE;
-}
-
-int get_token_uint32_t(void *elem, void *object, uint32_t offset,
- uint32_t size)
-{
- struct snd_soc_tplg_vendor_value_elem *velem = elem;
- uint32_t *val = object + offset;
-
- *val = velem->value;
- return 0;
-}
-
-int get_token_comp_format(void *elem, void *object, uint32_t offset,
- uint32_t size)
-{
- struct snd_soc_tplg_vendor_string_elem *velem = elem;
- uint32_t *val = object + offset;
-
- *val = find_format(velem->string);
- return 0;
-}
diff --git a/src/host/trace.c b/src/host/trace.c
deleted file mode 100644
index 2a82c8d..0000000
--- a/src/host/trace.c
+++ /dev/null
@@ -1,183 +0,0 @@
-/*
- * Copyright (c) 2018, Intel Corporation
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- * * Redistributions of source code must retain the above copyright
- * notice, this list of conditions and the following disclaimer.
- * * Redistributions in binary form must reproduce the above copyright
- * notice, this list of conditions and the following disclaimer in the
- * documentation and/or other materials provided with the distribution.
- * * Neither the name of the Intel Corporation nor the
- * names of its contributors may be used to endorse or promote products
- * derived from this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
- * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
- * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
- * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
- * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
- * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
- * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
- * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
- * POSSIBILITY OF SUCH DAMAGE.
- *
- * Author: Seppo Ingalsuo <seppo.ingalsuo@linux.intel.com>
- * Liam Girdwood <liam.r.girdwood@linux.intel.com>
- * Keyon Jie <yang.jie@linux.intel.com>
- * Ranjani Sridharan <ranjani.sridharan@linux.intel.com>
- */
-
-#include <stdint.h>
-#include <stdio.h>
-#include <string.h>
-#include "host/common_test.h"
-#include "host/trace.h"
-
-#define MAX_TRACE_CLASSES 255
-/* testbench trace definition */
-
-/* enable trace by default in testbench */
-static int test_bench_trace = 1;
-int num_trace_classes;
-
-/* set up trace class identifier table based on SOF trace header file */
-int setup_trace_table(void)
-{
- char buffer[2048];
- char *trace = "sof/trace.h";
- char *trace_filename = malloc(strlen(SOF_INC) + strlen(trace) + 2);
- char *token;
- int ret, i = 0;
- size_t size;
- FILE *fp;
-
- /* set up trace file name using include directory prefix */
- sprintf(trace_filename, "%s/%s", SOF_INC, trace);
-
- fp = fopen(trace_filename, "r");
- if (!fp) {
- fprintf(stderr, "error: opening trace include file %s\n",
- trace_filename);
- return -EINVAL;
- }
-
- /* find number of trace classes defined */
- while (fgets(buffer, sizeof(buffer), fp)) {
- char identifier[1024];
- int value = 0, shift = 0;
-
- ret = sscanf(buffer, "#define %s (%d << %d)", identifier,
- &value, &shift);
- if (ret == 3) {
- /* if TRACE_CLASS definition */
- if (strstr(identifier, "TRACE_CLASS"))
- i++;
- }
- }
-
- num_trace_classes = i;
-
- /* allocate memory for trace table */
- size = sizeof(struct trace_class_table);
- trace_table = (struct trace_class_table *)malloc(size *
- num_trace_classes);
-
- /* rewind file pointer */
- fseek(fp, 0, SEEK_SET);
-
- i = 0;
-
- /* read lines from header */
- while (fgets(buffer, sizeof(buffer), fp)) {
- char identifier[1024];
- int value = 0, shift = 0;
-
- ret = sscanf(buffer, "#define %s (%d << %d)", identifier,
- &value, &shift);
- if (ret == 3) {
- /* if TRACE_CLASS definition */
- if (strstr(identifier, "TRACE_CLASS")) {
- /* extract subsystem name */
- token = strtok(identifier, "_");
- token = strtok(NULL, "_");
- token = strtok(NULL, "_");
-
- /* add trace class entry */
- trace_table[i].trace_class = value;
- trace_table[i].class_name = strdup(token);
- i++;
- }
- }
- }
- fclose(fp);
- free(trace_filename);
- return 0;
-}
-
-void free_trace_table(void)
-{
- int i;
-
- for (i = 0; i < num_trace_classes; i++)
- free(trace_table[i].class_name);
-
- free(trace_table);
-}
-
-/* look up subsystem class name from table */
-static char *get_trace_class(uint32_t trace_class)
-{
- int i;
-
- /* look up trace class table and return subsystem name */
- for (i = 0; i < num_trace_classes; i++) {
- if (trace_table[i].trace_class == trace_class)
- return trace_table[i].class_name;
- }
-
- return "value";
-}
-
-/* print trace event */
-void _trace_event(uint32_t event)
-{
- char a, b, c;
- char *trace_class = NULL;
-
- if (test_bench_trace > 0) {
- a = event & 0xff;
- b = (event >> 8) & 0xff;
- c = (event >> 16) & 0xff;
-
- /* look up subsystem from trace class table */
- trace_class = strdup(get_trace_class(event >> 24));
-
- /* print trace event stderr*/
- if (strcmp(trace_class, "value") == 0)
- fprintf(stderr, "Trace value %d\n", event);
- else
- fprintf(stderr, "Trace %s %c%c%c\n", trace_class,
- c, b, a);
- }
-
- free(trace_class);
-}
-
-void _trace_event_mbox_atomic(uint32_t event)
-{
- _trace_event(event);
-}
-
-/* enable trace in testbench */
-void tb_enable_trace(bool enable)
-{
- test_bench_trace = enable;
- if (enable)
- debug_print("trace print enabled\n");
- else
- debug_print("trace print disabled\n");
-}
diff --git a/src/include/Makefile.am b/src/include/Makefile.am
deleted file mode 100644
index e7ba93b..0000000
--- a/src/include/Makefile.am
+++ /dev/null
@@ -1,8 +0,0 @@
-SUBDIRS = sof uapi
-
-version.h:
- $(top_srcdir)/version.sh $(top_srcdir)
-
-noinst_HEADERS = \
- config.h \
- version.h
diff --git a/src/include/host/common_test.h b/src/include/host/common_test.h
deleted file mode 100644
index 32e6057..0000000
--- a/src/include/host/common_test.h
+++ /dev/null
@@ -1,97 +0,0 @@
-/*
- * Copyright (c) 2018, Intel Corporation
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- * * Redistributions of source code must retain the above copyright
- * notice, this list of conditions and the following disclaimer.
- * * Redistributions in binary form must reproduce the above copyright
- * notice, this list of conditions and the following disclaimer in the
- * documentation and/or other materials provided with the distribution.
- * * Neither the name of the Intel Corporation nor the
- * names of its contributors may be used to endorse or promote products
- * derived from this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
- * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
- * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
- * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
- * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
- * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
- * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
- * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
- * POSSIBILITY OF SUCH DAMAGE.
- *
- * Author(s): Seppo Ingalsuo <seppo.ingalsuo@linux.intel.com>
- * Liam Girdwood <liam.r.girdwood@linux.intel.com>
- * Keyon Jie <yang.jie@linux.intel.com>
- * Ranjani Sridharan <ranjani.sridharan@linux.intel.com>
- */
-#ifndef _COMMON_TEST_H
-#define _COMMON_TEST_H
-
-#include <stdint.h>
-#include <stddef.h>
-#include <time.h>
-#include <stdio.h>
-#include <uapi/ipc.h>
-#include <sof/sof.h>
-#include <sof/audio/component.h>
-#include <sof/audio/format.h>
-
-/* common input parameters for the testbench */
-char *tplg_file; /* topology file to use */
-char *input_file; /* input file name */
-char *output_file; /* output file name */
-char *bits_in; /* input bit format */
-
-/*
- * input and output sample rate parameters
- * By default, these are calculated from pipeline frames_per_sched and deadline
- * But they can also be overridden via input arguments to the testbench
- */
-uint32_t fs_in;
-uint32_t fs_out;
-
-#define DEBUG_MSG_LEN 256
-#define MAX_LIB_NAME_LEN 256
-
-/* number of widgets types supported in testbench */
-#define NUM_WIDGETS_SUPPORTED 3
-
-struct shared_lib_table {
- char *comp_name;
- char library_name[MAX_LIB_NAME_LEN];
- uint32_t widget_type;
- const char *comp_init;
- int register_drv;
- void *handle;
-};
-
-extern int debug;
-
-int scheduler_init(struct sof *sof);
-
-void sys_comp_file_init(void);
-
-void sys_comp_filewrite_init(void);
-
-int tb_pipeline_setup(struct sof *sof);
-
-int tb_pipeline_start(struct ipc *ipc, int nch, char *bits_in,
- struct sof_ipc_pipe_new *ipc_pipe);
-
-int tb_pipeline_params(struct ipc *ipc, int nch, char *bits_in,
- struct sof_ipc_pipe_new *ipc_pipe);
-
-void debug_print(char *message);
-
-int get_index_by_name(char *comp_name,
- struct shared_lib_table *lib_table);
-
-int get_index_by_type(uint32_t comp_type,
- struct shared_lib_table *lib_table);
-#endif
diff --git a/src/include/host/file.h b/src/include/host/file.h
deleted file mode 100644
index 777b26d..0000000
--- a/src/include/host/file.h
+++ /dev/null
@@ -1,77 +0,0 @@
-/*
- * Copyright (c) 2018, Intel Corporation
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- * * Redistributions of source code must retain the above copyright
- * notice, this list of conditions and the following disclaimer.
- * * Redistributions in binary form must reproduce the above copyright
- * notice, this list of conditions and the following disclaimer in the
- * documentation and/or other materials provided with the distribution.
- * * Neither the name of the Intel Corporation nor the
- * names of its contributors may be used to endorse or promote products
- * derived from this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
- * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
- * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
- * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
- * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
- * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
- * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
- * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
- * POSSIBILITY OF SUCH DAMAGE.
- *
- * Author: Seppo Ingalsuo <seppo.ingalsuo@linux.intel.com>
- * Liam Girdwood <liam.r.girdwood@linux.intel.com>
- * Keyon Jie <yang.jie@linux.intel.com>
- * Ranjani Sridharan <ranjani.sridharan@linux.intel.com>
- */
-#ifndef _FILE_H
-#define _FILE_H
-
-/* file component modes */
-enum file_mode {
- FILE_READ = 0,
- FILE_WRITE,
- FILE_DUPLEX,
-};
-
-enum file_format {
- FILE_TEXT = 0,
- FILE_RAW,
-};
-
-/* file component state */
-struct file_state {
- char *fn;
- FILE *rfh, *wfh; /* read/write file handle */
- int reached_eof;
- int n;
- enum file_mode mode;
- enum file_format f_format;
-};
-
-/* file comp data */
-struct file_comp_data {
- uint32_t period_bytes;
- uint32_t channels;
- uint32_t frame_bytes;
- uint32_t rate;
- struct file_state fs;
- int (*file_func)(struct comp_dev *dev, struct comp_buffer *sink,
- struct comp_buffer *source, uint32_t frames);
-
-};
-
-/* file IO ipc comp */
-struct sof_ipc_comp_file {
- struct sof_ipc_comp comp;
- struct sof_ipc_comp_config config;
- char *fn;
- enum file_mode mode;
-};
-#endif
diff --git a/src/include/host/topology.h b/src/include/host/topology.h
deleted file mode 100644
index 03a6c04..0000000
--- a/src/include/host/topology.h
+++ /dev/null
@@ -1,202 +0,0 @@
-/*
- * Copyright (c) 2018, Intel Corporation
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- * * Redistributions of source code must retain the above copyright
- * notice, this list of conditions and the following disclaimer.
- * * Redistributions in binary form must reproduce the above copyright
- * notice, this list of conditions and the following disclaimer in the
- * documentation and/or other materials provided with the distribution.
- * * Neither the name of the Intel Corporation nor the
- * names of its contributors may be used to endorse or promote products
- * derived from this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
- * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
- * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
- * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
- * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
- * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
- * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
- * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
- * POSSIBILITY OF SUCH DAMAGE.
- *
- * Author: Liam Girdwood <liam.r.girdwood@linux.intel.com>
- * Ranjani Sridharan <ranjani.sridharan@linux.intel.com>
- */
-#ifndef _COMMON_TPLG_H
-#define _COMMON_TPLG_H
-
-#include <sound/asoc.h>
-#include "common_test.h"
-
-/*
- * TODO: include these token from kernel uapi header
- * Tokens - must match values in topology configurations
- */
-
-/* buffers */
-#define SOF_TKN_BUF_SIZE 100
-#define SOF_TKN_BUF_CAPS 101
-
-/* scheduling */
-#define SOF_TKN_SCHED_DEADLINE 200
-#define SOF_TKN_SCHED_PRIORITY 201
-#define SOF_TKN_SCHED_MIPS 202
-#define SOF_TKN_SCHED_CORE 203
-#define SOF_TKN_SCHED_FRAMES 204
-#define SOF_TKN_SCHED_TIMER 205
-
-/* volume */
-#define SOF_TKN_VOLUME_RAMP_STEP_TYPE 250
-#define SOF_TKN_VOLUME_RAMP_STEP_MS 251
-
-/* SRC */
-#define SOF_TKN_SRC_RATE_IN 300
-#define SOF_TKN_SRC_RATE_OUT 301
-
-/* Generic components */
-#define SOF_TKN_COMP_PERIOD_SINK_COUNT 400
-#define SOF_TKN_COMP_PERIOD_SOURCE_COUNT 401
-#define SOF_TKN_COMP_FORMAT 402
-#define SOF_TKN_COMP_PRELOAD_COUNT 403
-
-struct comp_info {
- char *name;
- int id;
- int type;
- int pipeline_id;
-};
-
-struct frame_types {
- char *name;
- enum sof_ipc_frame frame;
-};
-
-static const struct frame_types sof_frames[] = {
- /* TODO: fix topology to use ALSA formats */
- {"s16le", SOF_IPC_FRAME_S16_LE},
- {"s24le", SOF_IPC_FRAME_S24_4LE},
- {"s32le", SOF_IPC_FRAME_S32_LE},
- {"float", SOF_IPC_FRAME_FLOAT},
- /* ALSA formats */
- {"S16_LE", SOF_IPC_FRAME_S16_LE},
- {"S24_LE", SOF_IPC_FRAME_S24_4LE},
- {"S32_LE", SOF_IPC_FRAME_S32_LE},
- {"FLOAT_LE", SOF_IPC_FRAME_FLOAT},
-};
-
-struct sof_topology_token {
- uint32_t token;
- uint32_t type;
- int (*get_token)(void *elem, void *object, uint32_t offset,
- uint32_t size);
- uint32_t offset;
- uint32_t size;
-};
-
-enum sof_ipc_frame find_format(const char *name);
-
-int get_token_uint32_t(void *elem, void *object, uint32_t offset,
- uint32_t size);
-
-int get_token_comp_format(void *elem, void *object, uint32_t offset,
- uint32_t size);
-
-/* Buffers */
-static const struct sof_topology_token buffer_tokens[] = {
- {SOF_TKN_BUF_SIZE, SND_SOC_TPLG_TUPLE_TYPE_WORD, get_token_uint32_t,
- offsetof(struct sof_ipc_buffer, size), 0},
- {SOF_TKN_BUF_CAPS, SND_SOC_TPLG_TUPLE_TYPE_WORD, get_token_uint32_t,
- offsetof(struct sof_ipc_buffer, caps), 0},
-};
-
-/* scheduling */
-static const struct sof_topology_token sched_tokens[] = {
- {SOF_TKN_SCHED_DEADLINE, SND_SOC_TPLG_TUPLE_TYPE_WORD,
- get_token_uint32_t,
- offsetof(struct sof_ipc_pipe_new, deadline), 0},
- {SOF_TKN_SCHED_PRIORITY, SND_SOC_TPLG_TUPLE_TYPE_WORD,
- get_token_uint32_t,
- offsetof(struct sof_ipc_pipe_new, priority), 0},
- {SOF_TKN_SCHED_MIPS, SND_SOC_TPLG_TUPLE_TYPE_WORD,
- get_token_uint32_t,
- offsetof(struct sof_ipc_pipe_new, mips), 0},
- {SOF_TKN_SCHED_CORE, SND_SOC_TPLG_TUPLE_TYPE_WORD,
- get_token_uint32_t,
- offsetof(struct sof_ipc_pipe_new, core), 0},
- {SOF_TKN_SCHED_FRAMES, SND_SOC_TPLG_TUPLE_TYPE_WORD,
- get_token_uint32_t,
- offsetof(struct sof_ipc_pipe_new, frames_per_sched), 0},
- {SOF_TKN_SCHED_TIMER, SND_SOC_TPLG_TUPLE_TYPE_WORD,
- get_token_uint32_t,
- offsetof(struct sof_ipc_pipe_new, timer), 0},
-};
-
-/* volume */
-static const struct sof_topology_token volume_tokens[] = {
- {SOF_TKN_VOLUME_RAMP_STEP_TYPE, SND_SOC_TPLG_TUPLE_TYPE_WORD,
- get_token_uint32_t,
- offsetof(struct sof_ipc_comp_volume, ramp), 0},
- {SOF_TKN_VOLUME_RAMP_STEP_MS,
- SND_SOC_TPLG_TUPLE_TYPE_WORD, get_token_uint32_t,
- offsetof(struct sof_ipc_comp_volume, initial_ramp), 0},
-};
-
-/* SRC */
-static const struct sof_topology_token src_tokens[] = {
- {SOF_TKN_SRC_RATE_IN, SND_SOC_TPLG_TUPLE_TYPE_WORD,
- get_token_uint32_t,
- offsetof(struct sof_ipc_comp_src, source_rate), 0},
- {SOF_TKN_SRC_RATE_OUT, SND_SOC_TPLG_TUPLE_TYPE_WORD,
- get_token_uint32_t,
- offsetof(struct sof_ipc_comp_src, sink_rate), 0},
-};
-
-/* Tone */
-static const struct sof_topology_token tone_tokens[] = {
-};
-
-/* Generic components */
-static const struct sof_topology_token comp_tokens[] = {
- {SOF_TKN_COMP_PERIOD_SINK_COUNT,
- SND_SOC_TPLG_TUPLE_TYPE_WORD, get_token_uint32_t,
- offsetof(struct sof_ipc_comp_config, periods_sink), 0},
- {SOF_TKN_COMP_PERIOD_SOURCE_COUNT,
- SND_SOC_TPLG_TUPLE_TYPE_WORD, get_token_uint32_t,
- offsetof(struct sof_ipc_comp_config, periods_source), 0},
- {SOF_TKN_COMP_FORMAT,
- SND_SOC_TPLG_TUPLE_TYPE_STRING, get_token_comp_format,
- offsetof(struct sof_ipc_comp_config, frame_fmt), 0},
- {SOF_TKN_COMP_PRELOAD_COUNT,
- SND_SOC_TPLG_TUPLE_TYPE_WORD, get_token_uint32_t,
- offsetof(struct sof_ipc_comp_config, preload_count), 0},
-};
-
-int sof_parse_tokens(void *object,
- const struct sof_topology_token *tokens,
- int count, struct snd_soc_tplg_vendor_array *array,
- int priv_size);
-void sof_parse_string_tokens(void *object,
- const struct sof_topology_token *tokens,
- int count,
- struct snd_soc_tplg_vendor_array *array);
-void sof_parse_uuid_tokens(void *object,
- const struct sof_topology_token *tokens,
- int count,
- struct snd_soc_tplg_vendor_array *array);
-void sof_parse_word_tokens(void *object,
- const struct sof_topology_token *tokens,
- int count,
- struct snd_soc_tplg_vendor_array *array);
-
-int parse_topology(char *filename, struct sof *sof, int *fr_id, int *fw_id,
- int *sched_id, char *bits_in, char *in_file,
- char *out_file, struct shared_lib_table *library_table,
- char *pipeline_msg);
-
-#endif
diff --git a/src/include/host/trace.h b/src/include/host/trace.h
deleted file mode 100644
index a0a7b0d..0000000
--- a/src/include/host/trace.h
+++ /dev/null
@@ -1,49 +0,0 @@
-/*
- * Copyright (c) 2018, Intel Corporation
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- * * Redistributions of source code must retain the above copyright
- * notice, this list of conditions and the following disclaimer.
- * * Redistributions in binary form must reproduce the above copyright
- * notice, this list of conditions and the following disclaimer in the
- * documentation and/or other materials provided with the distribution.
- * * Neither the name of the Intel Corporation nor the
- * names of its contributors may be used to endorse or promote products
- * derived from this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
- * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
- * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
- * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
- * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
- * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
- * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
- * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
- * POSSIBILITY OF SUCH DAMAGE.
- *
- * Author: Seppo Ingalsuo <seppo.ingalsuo@linux.intel.com>
- * Ranjani Sridharan <ranjani.sridharan@linux.intel.com>
- */
-#include <stdbool.h>
-
-#ifndef _TRACE_H
-#define _TRACE_H
-
-struct trace_class_table {
- int trace_class;
- char *class_name;
-};
-
-struct trace_class_table *trace_table;
-
-void tb_enable_trace(bool enable);
-
-int setup_trace_table(void);
-
-void free_trace_table(void);
-
-#endif
diff --git a/src/include/sof/Makefile.am b/src/include/sof/Makefile.am
deleted file mode 100644
index a69cffc..0000000
--- a/src/include/sof/Makefile.am
+++ /dev/null
@@ -1,40 +0,0 @@
-SUBDIRS = audio math
-
-noinst_HEADERS = \
- agent.h
-
-includedir = $(prefix)/include/sof/sof
-
-include_HEADERS = \
- alloc.h \
- atomic.h \
- clock.h \
- cpu.h \
- dai.h \
- debug.h \
- dma.h \
- dma-trace.h \
- dw-dma.h \
- init.h \
- intel-ipc.h \
- interrupt.h \
- interrupt-map.h \
- io.h \
- ipc.h \
- list.h \
- lock.h \
- mailbox.h \
- notifier.h \
- panic.h \
- sof.h \
- schedule.h \
- ssp.h \
- stream.h \
- task.h \
- timer.h \
- trace.h \
- wait.h \
- string.h \
- hda-dma.h \
- work.h \
- pm_runtime.h
diff --git a/src/include/sof/agent.h b/src/include/sof/agent.h
deleted file mode 100644
index 3d94c35..0000000
--- a/src/include/sof/agent.h
+++ /dev/null
@@ -1,50 +0,0 @@
-/*
- * Copyright (c) 2017, Intel Corporation
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- * * Redistributions of source code must retain the above copyright
- * notice, this list of conditions and the following disclaimer.
- * * Redistributions in binary form must reproduce the above copyright
- * notice, this list of conditions and the following disclaimer in the
- * documentation and/or other materials provided with the distribution.
- * * Neither the name of the Intel Corporation nor the
- * names of its contributors may be used to endorse or promote products
- * derived from this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
- * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
- * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
- * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
- * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
- * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
- * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
- * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
- * POSSIBILITY OF SUCH DAMAGE.
- *
- * Author: Liam Girdwood <liam.r.girdwood@linux.intel.com>
- */
-
-#ifndef __INCLUDE_SOF_AGENT__
-#define __INCLUDE_SOF_AGENT__
-
-#include <stdint.h>
-#include <stddef.h>
-#include <sof/work.h>
-
-struct sof;
-
-/* simple agent */
-struct sa {
- uint64_t last_idle; /* time of last idle */
- uint64_t ticks;
- struct work work;
-};
-
-void sa_enter_idle(struct sof *sof);
-void sa_init(struct sof *sof);
-
-#endif
diff --git a/src/include/sof/alloc.h b/src/include/sof/alloc.h
deleted file mode 100644
index d5fc1c2..0000000
--- a/src/include/sof/alloc.h
+++ /dev/null
@@ -1,125 +0,0 @@
-/*
- * Copyright (c) 2016, Intel Corporation
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- * * Redistributions of source code must retain the above copyright
- * notice, this list of conditions and the following disclaimer.
- * * Redistributions in binary form must reproduce the above copyright
- * notice, this list of conditions and the following disclaimer in the
- * documentation and/or other materials provided with the distribution.
- * * Neither the name of the Intel Corporation nor the
- * names of its contributors may be used to endorse or promote products
- * derived from this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
- * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
- * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
- * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
- * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
- * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
- * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
- * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
- * POSSIBILITY OF SUCH DAMAGE.
- *
- * Author: Liam Girdwood <liam.r.girdwood@linux.intel.com>
- * Keyon Jie <yang.jie@linux.intel.com>
- */
-
-#ifndef __INCLUDE_ALLOC__
-#define __INCLUDE_ALLOC__
-
-#include <string.h>
-#include <stdint.h>
-#include <sof/dma.h>
-#include <platform/memory.h>
-
-struct sof;
-
-/* Heap Memory Zones
- *
- * The heap has three different zones from where memory can be allocated :-
- *
- * 1) System Zone. Fixed size heap where alloc always succeeds and is never
- * freed. Used by any init code that will never give up the memory.
- *
- * 2) Runtime Zone. Main and larger heap zone where allocs are not guaranteed to
- * succeed. Memory can be freed here.
- *
- * 3) Buffer Zone. Largest heap zone intended for audio buffers.
- *
- * See platform/memory.h for heap size configuration and mappings.
- */
-#define RZONE_SYS 0
-#define RZONE_RUNTIME 1
-#define RZONE_BUFFER 2
-
-struct mm_info {
- uint32_t used;
- uint32_t free;
-};
-
-struct block_hdr {
- uint16_t size; /* size in blocks for continuous allocation */
- uint16_t used; /* usage flags for page */
-} __attribute__ ((packed));
-
-struct block_map {
- uint16_t block_size; /* size of block in bytes */
- uint16_t count; /* number of blocks in map */
- uint16_t free_count; /* number of free blocks */
- uint16_t first_free; /* index of first free block */
- struct block_hdr *block; /* base block header */
- uint32_t base; /* base address of space */
-} __attribute__ ((packed));
-
-#define BLOCK_DEF(sz, cnt, hdr) \
- {.block_size = sz, .count = cnt, .free_count = cnt, .block = hdr}
-
-struct mm_heap {
- uint32_t blocks;
- struct block_map *map;
- uint32_t heap;
- uint32_t size;
- uint32_t caps;
- struct mm_info info;
-};
-
-/* heap block memory map */
-struct mm {
- /* system heap - used during init cannot be freed */
- struct mm_heap system;
- /* general heap for components */
- struct mm_heap runtime[PLATFORM_HEAP_RUNTIME];
- /* general component buffer heap */
- struct mm_heap buffer[PLATFORM_HEAP_BUFFER];
-
- struct mm_info total;
- spinlock_t lock; /* all allocs and frees are atomic */
-};
-
-/* heap allocation and free */
-void *rmalloc(int zone, uint32_t caps, size_t bytes);
-void *rzalloc(int zone, uint32_t caps, size_t bytes);
-void rfree(void *ptr);
-
-/* heap allocation and free for buffers on 1k boundary */
-void *rballoc(int zone, uint32_t flags, size_t bytes);
-
-/* utility */
-void bzero(void *s, size_t n);
-void *memset(void *s, int c, size_t n);
-int rstrlen(const char *s);
-int rstrcmp(const char *s1, const char *s2);
-
-/* Heap save/restore contents and context for PM D0/D3 events */
-uint32_t mm_pm_context_size(void);
-int mm_pm_context_save(struct dma_copy *dc, struct dma_sg_config *sg);
-int mm_pm_context_restore(struct dma_copy *dc, struct dma_sg_config *sg);
-
-/* heap initialisation */
-void init_heap(struct sof *sof);
-#endif
diff --git a/src/include/sof/atomic.h b/src/include/sof/atomic.h
deleted file mode 100644
index 6561215..0000000
--- a/src/include/sof/atomic.h
+++ /dev/null
@@ -1,63 +0,0 @@
-/*
- * Copyright (c) 2018, Intel Corporation
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- * * Redistributions of source code must retain the above copyright
- * notice, this list of conditions and the following disclaimer.
- * * Redistributions in binary form must reproduce the above copyright
- * notice, this list of conditions and the following disclaimer in the
- * documentation and/or other materials provided with the distribution.
- * * Neither the name of the Intel Corporation nor the
- * names of its contributors may be used to endorse or promote products
- * derived from this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
- * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
- * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
- * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
- * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
- * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
- * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
- * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
- * POSSIBILITY OF SUCH DAMAGE.
- *
- * Author: Liam Girdwood <liam.r.girdwood@linux.intel.com>
- *
- */
-
-#ifndef __INCLUDE_ATOMIC_H_
-#define __INCLUDE_ATOMIC_H_
-
-#include <stdint.h>
-#include <arch/atomic.h>
-
-static inline void atomic_init(atomic_t *a, int32_t value)
-{
- arch_atomic_init(a, value);
-}
-
-static inline int32_t atomic_read(const atomic_t *a)
-{
- return arch_atomic_read(a);
-}
-
-static inline void atomic_set(atomic_t *a, int32_t value)
-{
- arch_atomic_set(a, value);
-}
-
-static inline void atomic_add(atomic_t *a, int32_t value)
-{
- arch_atomic_add(a, value);
-}
-
-static inline void atomic_sub(atomic_t *a, int32_t value)
-{
- arch_atomic_sub(a, value);
-}
-
-#endif
diff --git a/src/include/sof/audio/Makefile.am b/src/include/sof/audio/Makefile.am
deleted file mode 100644
index 0717617..0000000
--- a/src/include/sof/audio/Makefile.am
+++ /dev/null
@@ -1,9 +0,0 @@
-SUBDIRS = coefficients
-
-includedir = $(prefix)/include/sof/sof/audio
-
-include_HEADERS = \
- component.h \
- pipeline.h \
- format.h \
- buffer.h
diff --git a/src/include/sof/audio/buffer.h b/src/include/sof/audio/buffer.h
deleted file mode 100644
index 4e2c43a..0000000
--- a/src/include/sof/audio/buffer.h
+++ /dev/null
@@ -1,151 +0,0 @@
-/*
- * Copyright (c) 2017, Intel Corporation
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- * * Redistributions of source code must retain the above copyright
- * notice, this list of conditions and the following disclaimer.
- * * Redistributions in binary form must reproduce the above copyright
- * notice, this list of conditions and the following disclaimer in the
- * documentation and/or other materials provided with the distribution.
- * * Neither the name of the Intel Corporation nor the
- * names of its contributors may be used to endorse or promote products
- * derived from this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
- * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
- * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
- * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
- * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
- * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
- * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
- * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
- * POSSIBILITY OF SUCH DAMAGE.
- *
- * Author: Liam Girdwood <liam.r.girdwood@linux.intel.com>
- */
-
-#ifndef __INCLUDE_AUDIO_BUFFER_H__
-#define __INCLUDE_AUDIO_BUFFER_H__
-
-#include <stdint.h>
-#include <stddef.h>
-#include <sof/lock.h>
-#include <sof/list.h>
-#include <sof/stream.h>
-#include <sof/dma.h>
-#include <sof/audio/component.h>
-#include <sof/trace.h>
-#include <sof/schedule.h>
-#include <uapi/ipc.h>
-
-/* pipeline tracing */
-#define trace_buffer(__e) trace_event(TRACE_CLASS_BUFFER, __e)
-#define trace_buffer_error(__e) trace_error(TRACE_CLASS_BUFFER, __e)
-#define tracev_buffer(__e) tracev_event(TRACE_CLASS_BUFFER, __e)
-
-/* audio component buffer - connects 2 audio components together in pipeline */
-struct comp_buffer {
-
- /* runtime data */
- uint32_t connected; /* connected in path */
- uint32_t size; /* runtime buffer size in bytes (period multiple) */
- uint32_t alloc_size; /* allocated size in bytes */
- uint32_t avail; /* available bytes for reading */
- uint32_t free; /* free bytes for writing */
- void *w_ptr; /* buffer write pointer */
- void *r_ptr; /* buffer read position */
- void *addr; /* buffer base address */
- void *end_addr; /* buffer end address */
-
- /* IPC configuration */
- struct sof_ipc_buffer ipc_buffer;
-
- /* connected components */
- struct comp_dev *source; /* source component */
- struct comp_dev *sink; /* sink component */
-
- /* lists */
- struct list_item source_list; /* list in comp buffers */
- struct list_item sink_list; /* list in comp buffers */
-
- spinlock_t lock;
-};
-
-/* pipeline buffer creation and destruction */
-struct comp_buffer *buffer_new(struct sof_ipc_buffer *desc);
-void buffer_free(struct comp_buffer *buffer);
-
-/* called by a component after producing data into this buffer */
-void comp_update_buffer_produce(struct comp_buffer *buffer, uint32_t bytes);
-
-/* called by a component after consuming data from this buffer */
-void comp_update_buffer_consume(struct comp_buffer *buffer, uint32_t bytes);
-
-static inline void buffer_zero(struct comp_buffer *buffer)
-{
- tracev_buffer("BZr");
-
- bzero(buffer->addr, buffer->size);
- if (buffer->ipc_buffer.caps & SOF_MEM_CAPS_DMA)
- dcache_writeback_region(buffer->addr, buffer->size);
-}
-
-/* get the max number of bytes that can be copied between sink and source */
-static inline int comp_buffer_can_copy_bytes(struct comp_buffer *source,
- struct comp_buffer *sink, uint32_t bytes)
-{
- /* check for underrun */
- if (source->avail < bytes)
- return -1;
-
- /* check for overrun */
- if (sink->free < bytes)
- return 1;
-
- /* we are good to copy */
- return 0;
-}
-
-static inline uint32_t comp_buffer_get_copy_bytes(struct comp_buffer *source,
- struct comp_buffer *sink)
-{
- if (source->avail > sink->free)
- return sink->free;
- else
- return source->avail;
-}
-
-static inline void buffer_reset_pos(struct comp_buffer *buffer)
-{
- /* reset read and write pointer to buffer bas */
- buffer->w_ptr = buffer->r_ptr = buffer->addr;
-
- /* free space is buffer size */
- buffer->free = buffer->size;
-
- /* ther are no avail samples at reset */
- buffer->avail = 0;
-
- /* clear buffer contents */
- buffer_zero(buffer);
-}
-
-/* set the runtime size of a buffer in bytes and improve the data cache */
-/* performance by only using minimum space needed for runtime params */
-static inline int buffer_set_size(struct comp_buffer *buffer, uint32_t size)
-{
- if (size > buffer->alloc_size)
- return -ENOMEM;
- if (size == 0)
- return -EINVAL;
-
- buffer->end_addr = buffer->addr + size;
- buffer->size = size;
- return 0;
-}
-
-#endif
diff --git a/src/include/sof/audio/coefficients/Makefile.am b/src/include/sof/audio/coefficients/Makefile.am
deleted file mode 100644
index af437a6..0000000
--- a/src/include/sof/audio/coefficients/Makefile.am
+++ /dev/null
@@ -1 +0,0 @@
-SUBDIRS = src
diff --git a/src/include/sof/audio/coefficients/pdm_decim/pdm_decim_fir.h b/src/include/sof/audio/coefficients/pdm_decim/pdm_decim_fir.h
deleted file mode 100644
index 788bf8c..0000000
--- a/src/include/sof/audio/coefficients/pdm_decim/pdm_decim_fir.h
+++ /dev/null
@@ -1,43 +0,0 @@
-/*
- * Copyright (c) 2018, Intel Corporation
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- * * Redistributions of source code must retain the above copyright
- * notice, this list of conditions and the following disclaimer.
- * * Redistributions in binary form must reproduce the above copyright
- * notice, this list of conditions and the following disclaimer in the
- * documentation and/or other materials provided with the distribution.
- * * Neither the name of the Intel Corporation nor the
- * names of its contributors may be used to endorse or promote products
- * derived from this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
- * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
- * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
- * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
- * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
- * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
- * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
- * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
- * POSSIBILITY OF SUCH DAMAGE.
- *
- * Author: Seppo Ingalsuo <seppo.ingalsuo@linux.intel.com>
- *
- */
-
-/* Format for generated coefficients tables */
-
-struct pdm_decim {
- int decim_factor;
- int length;
- int shift;
- int relative_passband;
- int relative_stopband;
- int passband_ripple;
- int stopband_ripple;
- const int32_t *coef;
-};
diff --git a/src/include/sof/audio/coefficients/pdm_decim/pdm_decim_int32_02_4288_5100_010_095.h b/src/include/sof/audio/coefficients/pdm_decim/pdm_decim_int32_02_4288_5100_010_095.h
deleted file mode 100644
index 389a0a8..0000000
--- a/src/include/sof/audio/coefficients/pdm_decim/pdm_decim_int32_02_4288_5100_010_095.h
+++ /dev/null
@@ -1,98 +0,0 @@
-const int32_t fir_int32_02_4288_5100_010_095[91] = {
- -193886,
- 104552,
- 2140521,
- 5355562,
- 5945318,
- 1216991,
- -4511367,
- -3527243,
- 3415937,
- 5526880,
- -1935806,
- -7515849,
- -386524,
- 9252379,
- 3862172,
- -10093681,
- -8251552,
- 9738620,
- 13536988,
- -7464432,
- -19100785,
- 2935187,
- 24375729,
- 4314479,
- -28271418,
- -14141458,
- 29999307,
- 26636531,
- -28180625,
- -41208987,
- 21649022,
- 57264356,
- -8757879,
- -73520802,
- -12043366,
- 88868414,
- 43784598,
- -101162825,
- -91853580,
- 106519993,
- 169110273,
- -94206010,
- -317139630,
- 5894310,
- 739661049,
- 1132200744,
- 739661049,
- 5894310,
- -317139630,
- -94206010,
- 169110273,
- 106519993,
- -91853580,
- -101162825,
- 43784598,
- 88868414,
- -12043366,
- -73520802,
- -8757879,
- 57264356,
- 21649022,
- -41208987,
- -28180625,
- 26636531,
- 29999307,
- -14141458,
- -28271418,
- 4314479,
- 24375729,
- 2935187,
- -19100785,
- -7464432,
- 13536988,
- 9738620,
- -8251552,
- -10093681,
- 3862172,
- 9252379,
- -386524,
- -7515849,
- -1935806,
- 5526880,
- 3415937,
- -3527243,
- -4511367,
- 1216991,
- 5945318,
- 5355562,
- 2140521,
- 104552,
- -193886
-
-};
-
-struct pdm_decim pdm_decim_int32_02_4288_5100_010_095 = {
- 2, 91, 0, 4288, 5100, 10, 95, fir_int32_02_4288_5100_010_095
-};
diff --git a/src/include/sof/audio/coefficients/pdm_decim/pdm_decim_int32_02_4375_5100_010_095.h b/src/include/sof/audio/coefficients/pdm_decim/pdm_decim_int32_02_4375_5100_010_095.h
deleted file mode 100644
index 3825593..0000000
--- a/src/include/sof/audio/coefficients/pdm_decim/pdm_decim_int32_02_4375_5100_010_095.h
+++ /dev/null
@@ -1,108 +0,0 @@
-const int32_t fir_int32_02_4375_5100_010_095[101] = {
- -587830,
- -2653881,
- -5154608,
- -4845367,
- -226473,
- 4220832,
- 2571159,
- -3184701,
- -4043579,
- 2206821,
- 5554546,
- -750496,
- -6923900,
- -1268584,
- 8073360,
- 4085183,
- -8546477,
- -7505364,
- 8176185,
- 11533751,
- -6471060,
- -15704256,
- 3359707,
- 19852409,
- 1635593,
- -23144509,
- -8252640,
- 25285013,
- 16574479,
- -25723227,
- -26663304,
- 23549736,
- 38139664,
- -17943366,
- -50446983,
- 8141043,
- 63090267,
- 7051351,
- -75166959,
- -29039894,
- 85772627,
- 60568979,
- -93167356,
- -106799776,
- 94198973,
- 180962815,
- -78385592,
- -324820245,
- -12243140,
- 742491441,
- 1151461281,
- 742491441,
- -12243140,
- -324820245,
- -78385592,
- 180962815,
- 94198973,
- -106799776,
- -93167356,
- 60568979,
- 85772627,
- -29039894,
- -75166959,
- 7051351,
- 63090267,
- 8141043,
- -50446983,
- -17943366,
- 38139664,
- 23549736,
- -26663304,
- -25723227,
- 16574479,
- 25285013,
- -8252640,
- -23144509,
- 1635593,
- 19852409,
- 3359707,
- -15704256,
- -6471060,
- 11533751,
- 8176185,
- -7505364,
- -8546477,
- 4085183,
- 8073360,
- -1268584,
- -6923900,
- -750496,
- 5554546,
- 2206821,
- -4043579,
- -3184701,
- 2571159,
- 4220832,
- -226473,
- -4845367,
- -5154608,
- -2653881,
- -587830
-
-};
-
-struct pdm_decim pdm_decim_int32_02_4375_5100_010_095 = {
- 2, 101, 0, 4375, 5100, 10, 95, fir_int32_02_4375_5100_010_095
-};
diff --git a/src/include/sof/audio/coefficients/pdm_decim/pdm_decim_int32_03_3850_5100_010_095.h b/src/include/sof/audio/coefficients/pdm_decim/pdm_decim_int32_03_3850_5100_010_095.h
deleted file mode 100644
index 9b98d7e..0000000
--- a/src/include/sof/audio/coefficients/pdm_decim/pdm_decim_int32_03_3850_5100_010_095.h
+++ /dev/null
@@ -1,100 +0,0 @@
-const int32_t fir_int32_03_3850_5100_010_095[93] = {
- 44212,
- -302176,
- -1360920,
- -3291119,
- -5495374,
- -6588668,
- -5102927,
- -753403,
- 4644861,
- 7677973,
- 5490212,
- -1618066,
- -9302333,
- -11445730,
- -4732005,
- 7709057,
- 17063964,
- 14699335,
- -457541,
- -18980508,
- -26202607,
- -13319132,
- 13695670,
- 35545996,
- 32740745,
- 1994202,
- -37267233,
- -54079734,
- -29355959,
- 25448678,
- 71128406,
- 67328423,
- 5964667,
- -74773313,
- -111583346,
- -62643893,
- 52737606,
- 154899783,
- 153311689,
- 16759099,
- -184962926,
- -304661987,
- -201939017,
- 160731847,
- 673585388,
- 1122541471,
- 1300561761,
- 1122541471,
- 673585388,
- 160731847,
- -201939017,
- -304661987,
- -184962926,
- 16759099,
- 153311689,
- 154899783,
- 52737606,
- -62643893,
- -111583346,
- -74773313,
- 5964667,
- 67328423,
- 71128406,
- 25448678,
- -29355959,
- -54079734,
- -37267233,
- 1994202,
- 32740745,
- 35545996,
- 13695670,
- -13319132,
- -26202607,
- -18980508,
- -457541,
- 14699335,
- 17063964,
- 7709057,
- -4732005,
- -11445730,
- -9302333,
- -1618066,
- 5490212,
- 7677973,
- 4644861,
- -753403,
- -5102927,
- -6588668,
- -5495374,
- -3291119,
- -1360920,
- -302176,
- 44212
-
-};
-
-struct pdm_decim pdm_decim_int32_03_3850_5100_010_095 = {
- 3, 93, 1, 3850, 5100, 10, 95, fir_int32_03_3850_5100_010_095
-};
diff --git a/src/include/sof/audio/coefficients/pdm_decim/pdm_decim_int32_03_4375_5100_010_095.h b/src/include/sof/audio/coefficients/pdm_decim/pdm_decim_int32_03_4375_5100_010_095.h
deleted file mode 100644
index d8f2f27..0000000
--- a/src/include/sof/audio/coefficients/pdm_decim/pdm_decim_int32_03_4375_5100_010_095.h
+++ /dev/null
@@ -1,164 +0,0 @@
-const int32_t fir_int32_03_4375_5100_010_095[157] = {
- 350904,
- 1127891,
- 2233546,
- 3059556,
- 2752177,
- 818057,
- -2252661,
- -4944515,
- -5550704,
- -3466227,
- 53089,
- 2496755,
- 1904111,
- -1421730,
- -4818556,
- -5204443,
- -1721082,
- 3155305,
- 5311444,
- 2454515,
- -3518616,
- -7589471,
- -5713308,
- 1327821,
- 7901341,
- 7958087,
- 527903,
- -8633996,
- -11354795,
- -4214518,
- 7627116,
- 13970242,
- 8263364,
- -5861946,
- -16549651,
- -13529964,
- 2213919,
- 17870757,
- 19056207,
- 2854066,
- -18029728,
- -24979102,
- -9860164,
- 16175117,
- 30545984,
- 18605951,
- -11894271,
- -35172531,
- -28918160,
- 4746528,
- 38201092,
- 40590666,
- 5825429,
- -38712951,
- -53159148,
- -20283384,
- 35723256,
- 66120531,
- 39265868,
- -27910967,
- -78795928,
- -63663750,
- 13458962,
- 90416047,
- 95193346,
- 10755142,
- -99897049,
- -137497231,
- -51075841,
- 105457455,
- 200047804,
- 124561003,
- -101612190,
- -313384381,
- -297343743,
- 53701878,
- 639681661,
- 1187800564,
- 1411050887,
- 1187800564,
- 639681661,
- 53701878,
- -297343743,
- -313384381,
- -101612190,
- 124561003,
- 200047804,
- 105457455,
- -51075841,
- -137497231,
- -99897049,
- 10755142,
- 95193346,
- 90416047,
- 13458962,
- -63663750,
- -78795928,
- -27910967,
- 39265868,
- 66120531,
- 35723256,
- -20283384,
- -53159148,
- -38712951,
- 5825429,
- 40590666,
- 38201092,
- 4746528,
- -28918160,
- -35172531,
- -11894271,
- 18605951,
- 30545984,
- 16175117,
- -9860164,
- -24979102,
- -18029728,
- 2854066,
- 19056207,
- 17870757,
- 2213919,
- -13529964,
- -16549651,
- -5861946,
- 8263364,
- 13970242,
- 7627116,
- -4214518,
- -11354795,
- -8633996,
- 527903,
- 7958087,
- 7901341,
- 1327821,
- -5713308,
- -7589471,
- -3518616,
- 2454515,
- 5311444,
- 3155305,
- -1721082,
- -5204443,
- -4818556,
- -1421730,
- 1904111,
- 2496755,
- 53089,
- -3466227,
- -5550704,
- -4944515,
- -2252661,
- 818057,
- 2752177,
- 3059556,
- 2233546,
- 1127891,
- 350904
-
-};
-
-struct pdm_decim pdm_decim_int32_03_4375_5100_010_095 = {
- 3, 157, 1, 4375, 5100, 10, 95, fir_int32_03_4375_5100_010_095
-};
diff --git a/src/include/sof/audio/coefficients/pdm_decim/pdm_decim_int32_04_4375_5100_010_095.h b/src/include/sof/audio/coefficients/pdm_decim/pdm_decim_int32_04_4375_5100_010_095.h
deleted file mode 100644
index a2a64fa..0000000
--- a/src/include/sof/audio/coefficients/pdm_decim/pdm_decim_int32_04_4375_5100_010_095.h
+++ /dev/null
@@ -1,218 +0,0 @@
-const int32_t fir_int32_04_4375_5100_010_095[211] = {
- 126017,
- 745791,
- 1735783,
- 3250059,
- 4963537,
- 6400069,
- 6949502,
- 6142229,
- 3902336,
- 705842,
- -2485787,
- -4540607,
- -4626085,
- -2636100,
- 646448,
- 3784383,
- 5275090,
- 4259502,
- 1015665,
- -3045153,
- -5950963,
- -6099091,
- -3115593,
- 1807814,
- 6342508,
- 8093924,
- 5838000,
- 296533,
- -6011752,
- -9879686,
- -9013045,
- -3339610,
- 4700101,
- 11152288,
- 12461593,
- 7387989,
- -2085667,
- -11448775,
- -15769545,
- -12252662,
- -1940150,
- 10437445,
- 18576639,
- 17768944,
- 7550319,
- -7626200,
- -20251921,
- -23428157,
- -14572076,
- 2797464,
- 20329234,
- 28790530,
- 22864155,
- 4330980,
- -18201801,
- -33211863,
- -32081436,
- -13923851,
- 13233081,
- 35870337,
- 41620943,
- 25914222,
- -4896316,
- -35895437,
- -50712381,
- -40042952,
- -7212823,
- 32428935,
- 58525317,
- 56015029,
- 23582638,
- -24374765,
- -63897455,
- -73234460,
- -44550852,
- 10604843,
- 65540282,
- 91054416,
- 70624752,
- 10408242,
- -61706258,
- -108584856,
- -102490195,
- -40744453,
- 50090298,
- 124919090,
- 141743373,
- 84173003,
- -26760833,
- -138851415,
- -191966143,
- -148464813,
- -16173880,
- 148695193,
- 262835505,
- 254088691,
- 100293640,
- -149816104,
- -385869984,
- -474827254,
- -315628113,
- 112831849,
- 731720961,
- 1381072959,
- 1872325415,
- 2055132469,
- 1872325415,
- 1381072959,
- 731720961,
- 112831849,
- -315628113,
- -474827254,
- -385869984,
- -149816104,
- 100293640,
- 254088691,
- 262835505,
- 148695193,
- -16173880,
- -148464813,
- -191966143,
- -138851415,
- -26760833,
- 84173003,
- 141743373,
- 124919090,
- 50090298,
- -40744453,
- -102490195,
- -108584856,
- -61706258,
- 10408242,
- 70624752,
- 91054416,
- 65540282,
- 10604843,
- -44550852,
- -73234460,
- -63897455,
- -24374765,
- 23582638,
- 56015029,
- 58525317,
- 32428935,
- -7212823,
- -40042952,
- -50712381,
- -35895437,
- -4896316,
- 25914222,
- 41620943,
- 35870337,
- 13233081,
- -13923851,
- -32081436,
- -33211863,
- -18201801,
- 4330980,
- 22864155,
- 28790530,
- 20329234,
- 2797464,
- -14572076,
- -23428157,
- -20251921,
- -7626200,
- 7550319,
- 17768944,
- 18576639,
- 10437445,
- -1940150,
- -12252662,
- -15769545,
- -11448775,
- -2085667,
- 7387989,
- 12461593,
- 11152288,
- 4700101,
- -3339610,
- -9013045,
- -9879686,
- -6011752,
- 296533,
- 5838000,
- 8093924,
- 6342508,
- 1807814,
- -3115593,
- -6099091,
- -5950963,
- -3045153,
- 1015665,
- 4259502,
- 5275090,
- 3784383,
- 646448,
- -2636100,
- -4626085,
- -4540607,
- -2485787,
- 705842,
- 3902336,
- 6142229,
- 6949502,
- 6400069,
- 4963537,
- 3250059,
- 1735783,
- 745791,
- 126017
-
-};
-
-struct pdm_decim pdm_decim_int32_04_4375_5100_010_095 = {
- 4, 211, 2, 4375, 5100, 10, 95, fir_int32_04_4375_5100_010_095
-};
diff --git a/src/include/sof/audio/coefficients/pdm_decim/pdm_decim_int32_05_4331_5100_010_095.h b/src/include/sof/audio/coefficients/pdm_decim/pdm_decim_int32_05_4331_5100_010_095.h
deleted file mode 100644
index 25bb9eb..0000000
--- a/src/include/sof/audio/coefficients/pdm_decim/pdm_decim_int32_05_4331_5100_010_095.h
+++ /dev/null
@@ -1,258 +0,0 @@
-const int32_t fir_int32_05_4331_5100_010_095[251] = {
- -250963,
- -530472,
- -956449,
- -1440505,
- -1861966,
- -2058350,
- -1862594,
- -1155766,
- 78930,
- 1719645,
- 3501958,
- 5061143,
- 6013975,
- 6066039,
- 5113131,
- 3303104,
- 1032343,
- -1135681,
- -2614668,
- -2968117,
- -2057986,
- -118896,
- 2276521,
- 4363476,
- 5409644,
- 4953617,
- 2982225,
- -20415,
- -3181416,
- -5487913,
- -6107986,
- -4685208,
- -1505051,
- 2535666,
- 6167372,
- 8134966,
- 7619351,
- 4554012,
- -280001,
- -5435156,
- -9220394,
- -10246686,
- -7922490,
- -2726786,
- 3853867,
- 9734139,
- 12878468,
- 11991508,
- 7020539,
- -717311,
- -8859727,
- -14705610,
- -16097433,
- -12195790,
- -3874308,
- 6431337,
- 15415517,
- 19946809,
- 18139792,
- 10093658,
- -1980159,
- -14334496,
- -22829097,
- -24298020,
- -17696570,
- -4621840,
- 11019276,
- 24149376,
- 30144976,
- 26434112,
- 13524367,
- -4930822,
- -23124320,
- -34892082,
- -35768599,
- -24626114,
- -4311380,
- 19011680,
- 37690383,
- 45054463,
- 37744852,
- 17102968,
- -10919933,
- -37416293,
- -53300866,
- -52364722,
- -33596881,
- -1935268,
- 32928131,
- 59438198,
- 67925581,
- 54022129,
- 20569914,
- -22737901,
- -62048140,
- -83661289,
- -78659667,
- -46330665,
- 4859442,
- 59276671,
- 98707953,
- 108233225,
- 81552245,
- 23955872,
- -48257755,
- -112070264,
- -144691658,
- -131171943,
- -70276392,
- 23448172,
- 122479978,
- 193637242,
- 208100323,
- 151336952,
- 29895897,
- -127299559,
- -274102498,
- -357874627,
- -333256339,
- -175377009,
- 111180608,
- 490397234,
- 900786668,
- 1268179136,
- 1522305381,
- 1613059887,
- 1522305381,
- 1268179136,
- 900786668,
- 490397234,
- 111180608,
- -175377009,
- -333256339,
- -357874627,
- -274102498,
- -127299559,
- 29895897,
- 151336952,
- 208100323,
- 193637242,
- 122479978,
- 23448172,
- -70276392,
- -131171943,
- -144691658,
- -112070264,
- -48257755,
- 23955872,
- 81552245,
- 108233225,
- 98707953,
- 59276671,
- 4859442,
- -46330665,
- -78659667,
- -83661289,
- -62048140,
- -22737901,
- 20569914,
- 54022129,
- 67925581,
- 59438198,
- 32928131,
- -1935268,
- -33596881,
- -52364722,
- -53300866,
- -37416293,
- -10919933,
- 17102968,
- 37744852,
- 45054463,
- 37690383,
- 19011680,
- -4311380,
- -24626114,
- -35768599,
- -34892082,
- -23124320,
- -4930822,
- 13524367,
- 26434112,
- 30144976,
- 24149376,
- 11019276,
- -4621840,
- -17696570,
- -24298020,
- -22829097,
- -14334496,
- -1980159,
- 10093658,
- 18139792,
- 19946809,
- 15415517,
- 6431337,
- -3874308,
- -12195790,
- -16097433,
- -14705610,
- -8859727,
- -717311,
- 7020539,
- 11991508,
- 12878468,
- 9734139,
- 3853867,
- -2726786,
- -7922490,
- -10246686,
- -9220394,
- -5435156,
- -280001,
- 4554012,
- 7619351,
- 8134966,
- 6167372,
- 2535666,
- -1505051,
- -4685208,
- -6107986,
- -5487913,
- -3181416,
- -20415,
- 2982225,
- 4953617,
- 5409644,
- 4363476,
- 2276521,
- -118896,
- -2057986,
- -2968117,
- -2614668,
- -1135681,
- 1032343,
- 3303104,
- 5113131,
- 6066039,
- 6013975,
- 5061143,
- 3501958,
- 1719645,
- 78930,
- -1155766,
- -1862594,
- -2058350,
- -1861966,
- -1440505,
- -956449,
- -530472,
- -250963
-
-};
-
-struct pdm_decim pdm_decim_int32_05_4331_5100_010_095 = {
- 5, 251, 2, 4331, 5100, 10, 95, fir_int32_05_4331_5100_010_095
-};
diff --git a/src/include/sof/audio/coefficients/pdm_decim/pdm_decim_int32_06_4156_5100_010_095.h b/src/include/sof/audio/coefficients/pdm_decim/pdm_decim_int32_06_4156_5100_010_095.h
deleted file mode 100644
index 01d149b..0000000
--- a/src/include/sof/audio/coefficients/pdm_decim/pdm_decim_int32_06_4156_5100_010_095.h
+++ /dev/null
@@ -1,256 +0,0 @@
-const int32_t fir_int32_06_4156_5100_010_095[249] = {
- -145670,
- -159762,
- -183049,
- -132077,
- 40047,
- 375196,
- 897258,
- 1599108,
- 2433074,
- 3308273,
- 4097062,
- 4651618,
- 4829700,
- 4525669,
- 3700263,
- 2402258,
- 776038,
- -950161,
- -2496541,
- -3579851,
- -3970442,
- -3547641,
- -2337956,
- -529617,
- 1547925,
- 3476297,
- 4827277,
- 5253398,
- 4572039,
- 2823110,
- 284249,
- -2564887,
- -5127174,
- -6808166,
- -7148614,
- -5940791,
- -3300873,
- 324045,
- 4222816,
- 7553233,
- 9518313,
- 9550081,
- 7459490,
- 3515883,
- -1570147,
- -6764980,
- -10915019,
- -12995804,
- -12355318,
- -8895306,
- -3143626,
- 3808819,
- 10504528,
- 15416643,
- 17288185,
- 15439779,
- 9973227,
- 1815303,
- -7421871,
- -15747713,
- -21211963,
- -22349384,
- -18551421,
- -10274491,
- 976318,
- 12902423,
- 22867792,
- 28468157,
- 28093650,
- 21356476,
- 9275878,
- -5840836,
- -20818261,
- -32262581,
- -37311768,
- -34324420,
- -23346677,
- -6234152,
- 13625405,
- 31957173,
- 44495096,
- 47945809,
- 40808741,
- 23856504,
- 140921,
- -25513494,
- -47455167,
- -60412143,
- -60710132,
- -47229950,
- -21869611,
- 10631696,
- 43519737,
- 69370312,
- 81696614,
- 76484113,
- 53307373,
- 15747228,
- -29042608,
- -71597234,
- -102026296,
- -112167649,
- -97565632,
- -58831316,
- -2036750,
- 62029440,
- 119693403,
- 157031723,
- 162840122,
- 131357475,
- 64171528,
- -29147598,
- -131921532,
- -222701994,
- -278742412,
- -280032642,
- -213184166,
- -74440208,
- 128790505,
- 378234661,
- 646928572,
- 902966510,
- 1114231037,
- 1253321369,
- 1301843153,
- 1253321369,
- 1114231037,
- 902966510,
- 646928572,
- 378234661,
- 128790505,
- -74440208,
- -213184166,
- -280032642,
- -278742412,
- -222701994,
- -131921532,
- -29147598,
- 64171528,
- 131357475,
- 162840122,
- 157031723,
- 119693403,
- 62029440,
- -2036750,
- -58831316,
- -97565632,
- -112167649,
- -102026296,
- -71597234,
- -29042608,
- 15747228,
- 53307373,
- 76484113,
- 81696614,
- 69370312,
- 43519737,
- 10631696,
- -21869611,
- -47229950,
- -60710132,
- -60412143,
- -47455167,
- -25513494,
- 140921,
- 23856504,
- 40808741,
- 47945809,
- 44495096,
- 31957173,
- 13625405,
- -6234152,
- -23346677,
- -34324420,
- -37311768,
- -32262581,
- -20818261,
- -5840836,
- 9275878,
- 21356476,
- 28093650,
- 28468157,
- 22867792,
- 12902423,
- 976318,
- -10274491,
- -18551421,
- -22349384,
- -21211963,
- -15747713,
- -7421871,
- 1815303,
- 9973227,
- 15439779,
- 17288185,
- 15416643,
- 10504528,
- 3808819,
- -3143626,
- -8895306,
- -12355318,
- -12995804,
- -10915019,
- -6764980,
- -1570147,
- 3515883,
- 7459490,
- 9550081,
- 9518313,
- 7553233,
- 4222816,
- 324045,
- -3300873,
- -5940791,
- -7148614,
- -6808166,
- -5127174,
- -2564887,
- 284249,
- 2823110,
- 4572039,
- 5253398,
- 4827277,
- 3476297,
- 1547925,
- -529617,
- -2337956,
- -3547641,
- -3970442,
- -3579851,
- -2496541,
- -950161,
- 776038,
- 2402258,
- 3700263,
- 4525669,
- 4829700,
- 4651618,
- 4097062,
- 3308273,
- 2433074,
- 1599108,
- 897258,
- 375196,
- 40047,
- -132077,
- -183049,
- -159762,
- -145670
-
-};
-
-struct pdm_decim pdm_decim_int32_06_4156_5100_010_095 = {
- 6, 249, 2, 4156, 5100, 10, 95, fir_int32_06_4156_5100_010_095
-};
diff --git a/src/include/sof/audio/coefficients/pdm_decim/pdm_decim_int32_08_4156_5380_010_090.h b/src/include/sof/audio/coefficients/pdm_decim/pdm_decim_int32_08_4156_5380_010_090.h
deleted file mode 100644
index b18df3d..0000000
--- a/src/include/sof/audio/coefficients/pdm_decim/pdm_decim_int32_08_4156_5380_010_090.h
+++ /dev/null
@@ -1,254 +0,0 @@
-const int32_t fir_int32_08_4156_5380_010_090[247] = {
- -337052,
- -90075,
- 37780,
- 310298,
- 762602,
- 1418014,
- 2279975,
- 3324413,
- 4495298,
- 5703536,
- 6831280,
- 7740936,
- 8289504,
- 8346168,
- 7812523,
- 6641741,
- 4854841,
- 2549644,
- -98570,
- -2847418,
- -5407472,
- -7472951,
- -8758755,
- -9040926,
- -8192669,
- -6213693,
- -3246278,
- 424677,
- 4395972,
- 8180309,
- 11265189,
- 13176475,
- 13545386,
- 12170147,
- 9059463,
- 4454447,
- -1180491,
- -7196755,
- -12830960,
- -17296055,
- -19885729,
- -20077500,
- -17621714,
- -12601266,
- -5452197,
- 3062539,
- 11925735,
- 19980775,
- 26075722,
- 29220338,
- 28734576,
- 24368837,
- 16375791,
- 5519930,
- -6982346,
- -19587960,
- -30609997,
- -38433685,
- -41741838,
- -39718804,
- -32202058,
- -19758650,
- -3667506,
- 14195787,
- 31565234,
- 46060011,
- 55497992,
- 58207057,
- 53292128,
- 40817642,
- 21874421,
- -1487369,
- -26460171,
- -49799428,
- -68227825,
- -78875217,
- -79697543,
- -69816864,
- -49730377,
- -21350328,
- 12143051,
- 46630130,
- 77532435,
- 100390923,
- 111473843,
- 108334402,
- 90240198,
- 58408793,
- 16001822,
- -32138446,
- -79996329,
- -121085165,
- -149268412,
- -159601418,
- -149086287,
- -117235239,
- -66355092,
- -1494553,
- 69965597,
- 139055884,
- 196228005,
- 232526458,
- 240790250,
- 216740138,
- 159811182,
- 73611998,
- -34070591,
- -151754583,
- -265210746,
- -358796902,
- -417052464,
- -426388521,
- -376691518,
- -262659116,
- -84707915,
- 150664267,
- 431125422,
- 739363099,
- 1054476937,
- 1353781691,
- 1614844650,
- 1817552687,
- 1945997296,
- 1989982406,
- 1945997296,
- 1817552687,
- 1614844650,
- 1353781691,
- 1054476937,
- 739363099,
- 431125422,
- 150664267,
- -84707915,
- -262659116,
- -376691518,
- -426388521,
- -417052464,
- -358796902,
- -265210746,
- -151754583,
- -34070591,
- 73611998,
- 159811182,
- 216740138,
- 240790250,
- 232526458,
- 196228005,
- 139055884,
- 69965597,
- -1494553,
- -66355092,
- -117235239,
- -149086287,
- -159601418,
- -149268412,
- -121085165,
- -79996329,
- -32138446,
- 16001822,
- 58408793,
- 90240198,
- 108334402,
- 111473843,
- 100390923,
- 77532435,
- 46630130,
- 12143051,
- -21350328,
- -49730377,
- -69816864,
- -79697543,
- -78875217,
- -68227825,
- -49799428,
- -26460171,
- -1487369,
- 21874421,
- 40817642,
- 53292128,
- 58207057,
- 55497992,
- 46060011,
- 31565234,
- 14195787,
- -3667506,
- -19758650,
- -32202058,
- -39718804,
- -41741838,
- -38433685,
- -30609997,
- -19587960,
- -6982346,
- 5519930,
- 16375791,
- 24368837,
- 28734576,
- 29220338,
- 26075722,
- 19980775,
- 11925735,
- 3062539,
- -5452197,
- -12601266,
- -17621714,
- -20077500,
- -19885729,
- -17296055,
- -12830960,
- -7196755,
- -1180491,
- 4454447,
- 9059463,
- 12170147,
- 13545386,
- 13176475,
- 11265189,
- 8180309,
- 4395972,
- 424677,
- -3246278,
- -6213693,
- -8192669,
- -9040926,
- -8758755,
- -7472951,
- -5407472,
- -2847418,
- -98570,
- 2549644,
- 4854841,
- 6641741,
- 7812523,
- 8346168,
- 8289504,
- 7740936,
- 6831280,
- 5703536,
- 4495298,
- 3324413,
- 2279975,
- 1418014,
- 762602,
- 310298,
- 37780,
- -90075,
- -337052
-
-};
-
-struct pdm_decim pdm_decim_int32_08_4156_5380_010_090 = {
- 8, 247, 3, 4156, 5380, 10, 90, fir_int32_08_4156_5380_010_090
-};
diff --git a/src/include/sof/audio/coefficients/pdm_decim/pdm_decim_table.h b/src/include/sof/audio/coefficients/pdm_decim/pdm_decim_table.h
deleted file mode 100644
index 8237252..0000000
--- a/src/include/sof/audio/coefficients/pdm_decim/pdm_decim_table.h
+++ /dev/null
@@ -1,60 +0,0 @@
-/*
- * Copyright (c) 2018, Intel Corporation
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- * * Redistributions of source code must retain the above copyright
- * notice, this list of conditions and the following disclaimer.
- * * Redistributions in binary form must reproduce the above copyright
- * notice, this list of conditions and the following disclaimer in the
- * documentation and/or other materials provided with the distribution.
- * * Neither the name of the Intel Corporation nor the
- * names of its contributors may be used to endorse or promote products
- * derived from this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
- * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
- * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
- * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
- * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
- * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
- * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
- * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
- * POSSIBILITY OF SUCH DAMAGE.
- *
- * Author: Seppo Ingalsuo <seppo.ingalsuo@linux.intel.com>
- *
- */
-
-/* PDM decimation FIR filters */
-
-#include "pdm_decim_fir.h"
-#include "pdm_decim_int32_02_4288_5100_010_095.h"
-#include "pdm_decim_int32_02_4375_5100_010_095.h"
-#include "pdm_decim_int32_03_3850_5100_010_095.h"
-#include "pdm_decim_int32_03_4375_5100_010_095.h"
-#include "pdm_decim_int32_04_4375_5100_010_095.h"
-#include "pdm_decim_int32_05_4331_5100_010_095.h"
-#include "pdm_decim_int32_06_4156_5100_010_095.h"
-#include "pdm_decim_int32_08_4156_5380_010_090.h"
-
-#define DMIC_FIR_LIST_LENGTH 8
-
-/* Note: Higher spec filter must be before lower spec filter
- * if there are multiple filters for a decimation factor. The naming
- * scheme of coefficients set is:
- * <type>_<decim factor>_<rel passband>_<rel stopband>_<ripple>_<attenuation>
- */
-struct pdm_decim *fir_list[DMIC_FIR_LIST_LENGTH] = {
- &pdm_decim_int32_02_4375_5100_010_095,
- &pdm_decim_int32_02_4288_5100_010_095,
- &pdm_decim_int32_03_4375_5100_010_095,
- &pdm_decim_int32_03_3850_5100_010_095,
- &pdm_decim_int32_04_4375_5100_010_095,
- &pdm_decim_int32_05_4331_5100_010_095,
- &pdm_decim_int32_06_4156_5100_010_095,
- &pdm_decim_int32_08_4156_5380_010_090,
-};
diff --git a/src/include/sof/audio/coefficients/src/Makefile.am b/src/include/sof/audio/coefficients/src/Makefile.am
deleted file mode 100644
index 88eb5aa..0000000
--- a/src/include/sof/audio/coefficients/src/Makefile.am
+++ /dev/null
@@ -1,44 +0,0 @@
-noinst_HEADERS = \
- src_std_int32_10_21_4583_5000.h \
- src_std_int32_10_9_4583_5000.h \
- src_std_int32_1_2_2292_5000.h \
- src_std_int32_1_2_4583_5000.h \
- src_std_int32_1_3_2292_5000.h \
- src_std_int32_1_3_4583_5000.h \
- src_std_int32_16_7_4125_5000.h \
- src_std_int32_20_21_4211_5000.h \
- src_std_int32_20_7_3008_5000.h \
- src_std_int32_21_20_4211_5000.h \
- src_std_int32_2_1_2292_5000.h \
- src_std_int32_21_40_4010_5000.h \
- src_std_int32_2_1_4583_5000.h \
- src_std_int32_21_80_4010_5000.h \
- src_std_int32_2_3_4583_5000.h \
- src_std_int32_3_1_2292_5000.h \
- src_std_int32_3_1_4583_5000.h \
- src_std_int32_32_21_4583_5000.h \
- src_std_int32_3_2_4583_5000.h \
- src_std_int32_3_4_4583_5000.h \
- src_std_int32_40_21_4010_5000.h \
- src_std_int32_4_3_4583_5000.h \
- src_std_int32_5_7_4583_5000.h \
- src_std_int32_7_8_4583_5000.h \
- src_std_int32_8_21_3274_5000.h \
- src_std_int32_8_7_2494_5000.h \
- src_std_int32_8_7_4583_5000.h \
- src_std_int32_define.h \
- src_std_int32_table.h \
- src_tiny_int16_1_2_3281_5000.h \
- src_tiny_int16_1_3_1641_5000.h \
- src_tiny_int16_1_3_3281_5000.h \
- src_tiny_int16_20_21_3015_5000.h \
- src_tiny_int16_21_20_3015_5000.h \
- src_tiny_int16_2_1_3281_5000.h \
- src_tiny_int16_2_3_3281_5000.h \
- src_tiny_int16_3_1_1641_5000.h \
- src_tiny_int16_3_1_3281_5000.h \
- src_tiny_int16_3_2_3281_5000.h \
- src_tiny_int16_7_8_3281_5000.h \
- src_tiny_int16_8_7_3281_5000.h \
- src_tiny_int16_define.h \
- src_tiny_int16_table.h
diff --git a/src/include/sof/audio/coefficients/src/src_std_int32_10_21_4583_5000.h b/src/include/sof/audio/coefficients/src/src_std_int32_10_21_4583_5000.h
deleted file mode 100644
index a41547e..0000000
--- a/src/include/sof/audio/coefficients/src/src_std_int32_10_21_4583_5000.h
+++ /dev/null
@@ -1,2086 +0,0 @@
-const int32_t src_int32_10_21_4583_5000_fir[2080] = {
- -81599,
- 52956,
- 141581,
- -29670,
- -210743,
- -28158,
- 277227,
- 127254,
- -324275,
- -268996,
- 331554,
- 447186,
- -277512,
- -646421,
- 142690,
- 841505,
- 86314,
- -998263,
- -412661,
- 1076018,
- 825468,
- -1031762,
- -1297051,
- 825849,
- 1781878,
- -428748,
- -2217805,
- -171853,
- 2529970,
- 964478,
- -2637419,
- -1908876,
- 2462212,
- 2933612,
- -1940340,
- -3937149,
- 1033441,
- 4793013,
- 260007,
- -5359256,
- -1895536,
- 5491937,
- 3777098,
- -5061768,
- -5756439,
- 3972581,
- 7638445,
- -2179774,
- -9192987,
- -293376,
- 10173084,
- 3343762,
- -10338492,
- -6782957,
- 9483071,
- 10339875,
- -7463605,
- -13672655,
- 4227297,
- 16389989,
- 165126,
- -18081181,
- -5523670,
- 18353210,
- 11523302,
- -16872182,
- -17710049,
- 13405809,
- 23519885,
- -7863131,
- -28310156,
- 327619,
- 31402022,
- 8919846,
- -32131161,
- -19390809,
- 29902914,
- 30393362,
- -24247267,
- -41050335,
- 14868623,
- 50329233,
- -1685365,
- -57078969,
- -15145396,
- 60064793,
- 35221731,
- -57987133,
- -57912468,
- 49459230,
- 82397017,
- -32894043,
- -107733351,
- 6187314,
- 132964924,
- 34107888,
- -157303801,
- -95109190,
- 180538735,
- 195630045,
- -204441623,
- -406835253,
- 242343378,
- 1406072798,
- 1952694807,
- 1298208719,
- 139113161,
- -419633625,
- -158789174,
- 216570340,
- 156314757,
- -116500318,
- -145071483,
- 53831944,
- 128538290,
- -10928180,
- -108637720,
- -18858429,
- 86888949,
- 38688744,
- -64638969,
- -50451537,
- 43089803,
- 55560846,
- -23271459,
- -55267353,
- 6005141,
- 50771852,
- 8126264,
- -43248523,
- -18793129,
- 33825584,
- 25916751,
- -23547799,
- -29649913,
- 13335146,
- 30342475,
- -3946570,
- -28495576,
- -4045662,
- 24708865,
- 10268015,
- -19625551,
- -14543303,
- 13879915,
- 16874704,
- -8051350,
- -17418384,
- 2628103,
- 16447890,
- 2017281,
- -14314003,
- -5639984,
- 11403848,
- 8122839,
- -8102767,
- -9465591,
- 4761883,
- 9765758,
- -1673437,
- -9193872,
- -944953,
- 7966069,
- 2956919,
- -6316890,
- -4305555,
- 4474759,
- 5004592,
- -2642057,
- -5124437,
- 980967,
- 4775192,
- 394424,
- -4088776,
- -1419991,
- 3202061,
- 2078198,
- -2242531,
- -2390694,
- 1317507,
- 2408309,
- -507431,
- -2199944,
- -136793,
- 1841703,
- 592848,
- -1407401,
- -863187,
- 961209,
- 969308,
- -552851,
- -945097,
- 215415,
- 830196,
- 34498,
- -664116,
- -194743,
- 481666,
- 274349,
- -309956,
- -289630,
- 167014,
- 260286,
- -61865,
- -205995,
- -4263,
- 143808,
- 35999,
- -74664,
- 69491,
- 136249,
- -55351,
- -211197,
- 7191,
- 288843,
- 83718,
- -353060,
- -221376,
- 383241,
- 402580,
- -356380,
- -614901,
- 250207,
- 835581,
- -47147,
- -1031767,
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-};
-struct src_stage src_int32_10_21_4583_5000 = {
- 2, 1, 10, 208, 2080, 21, 10, 0, 1,
- src_int32_10_21_4583_5000_fir};
diff --git a/src/include/sof/audio/coefficients/src/src_std_int32_10_9_4583_5000.h b/src/include/sof/audio/coefficients/src/src_std_int32_10_9_4583_5000.h
deleted file mode 100644
index 77a65c9..0000000
--- a/src/include/sof/audio/coefficients/src/src_std_int32_10_9_4583_5000.h
+++ /dev/null
@@ -1,1046 +0,0 @@
-const int32_t src_int32_10_9_4583_5000_fir[1040] = {
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-};
-struct src_stage src_int32_10_9_4583_5000 = {
- 8, 9, 10, 104, 1040, 9, 10, 0, 0,
- src_int32_10_9_4583_5000_fir};
diff --git a/src/include/sof/audio/coefficients/src/src_std_int32_16_7_4125_5000.h b/src/include/sof/audio/coefficients/src/src_std_int32_16_7_4125_5000.h
deleted file mode 100644
index fbd7a70..0000000
--- a/src/include/sof/audio/coefficients/src/src_std_int32_16_7_4125_5000.h
+++ /dev/null
@@ -1,902 +0,0 @@
-const int32_t src_int32_16_7_4125_5000_fir[896] = {
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-
-};
-struct src_stage src_int32_16_7_4125_5000 = {
- 3, 7, 16, 56, 896, 7, 16, 0, 0,
- src_int32_16_7_4125_5000_fir};
diff --git a/src/include/sof/audio/coefficients/src/src_std_int32_1_2_2292_5000.h b/src/include/sof/audio/coefficients/src/src_std_int32_1_2_2292_5000.h
deleted file mode 100644
index c758593..0000000
--- a/src/include/sof/audio/coefficients/src/src_std_int32_1_2_2292_5000.h
+++ /dev/null
@@ -1,46 +0,0 @@
-const int32_t src_int32_1_2_2292_5000_fir[40] = {
- -145826,
- 1042622,
- 2533728,
- -7519,
- -7345199,
- -9384005,
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- 25866299,
- 5186764,
- -9384005,
- -7345199,
- -7519,
- 2533728,
- 1042622,
- -145826
-
-};
-struct src_stage src_int32_1_2_2292_5000 = {
- 1, 0, 1, 40, 40, 2, 1, 0, 1,
- src_int32_1_2_2292_5000_fir};
diff --git a/src/include/sof/audio/coefficients/src/src_std_int32_1_2_4583_5000.h b/src/include/sof/audio/coefficients/src/src_std_int32_1_2_4583_5000.h
deleted file mode 100644
index d298f8d..0000000
--- a/src/include/sof/audio/coefficients/src/src_std_int32_1_2_4583_5000.h
+++ /dev/null
@@ -1,210 +0,0 @@
-const int32_t src_int32_1_2_4583_5000_fir[204] = {
- 96836,
- 21743,
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- 3230015,
- 2734561,
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- -2689087,
- 1790526,
- 2551427,
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- -2347016,
- 746549,
- 2098864,
- -370344,
- -1827101,
- 83038,
- 1548705,
- 124515,
- -1277392,
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- 1023648,
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- 21743,
- 96836
-
-};
-struct src_stage src_int32_1_2_4583_5000 = {
- 1, 0, 1, 204, 204, 2, 1, 0, 1,
- src_int32_1_2_4583_5000_fir};
diff --git a/src/include/sof/audio/coefficients/src/src_std_int32_1_3_2292_5000.h b/src/include/sof/audio/coefficients/src/src_std_int32_1_3_2292_5000.h
deleted file mode 100644
index 2ff4f06..0000000
--- a/src/include/sof/audio/coefficients/src/src_std_int32_1_3_2292_5000.h
+++ /dev/null
@@ -1,62 +0,0 @@
-const int32_t src_int32_1_3_2292_5000_fir[56] = {
- 649372,
- 1473953,
- 1384024,
- -919724,
- -5320411,
- -9096696,
- -7689901,
- 2033391,
- 17674531,
- 29781227,
- 25821331,
- -862781,
- -42233558,
- -74299097,
- -67991881,
- -9051809,
- 84476999,
- 161152154,
- 158628552,
- 42722226,
- -157570845,
- -343110822,
- -378159261,
- -154718428,
- 342664462,
- 1007809627,
- 1641021687,
- 2026926412,
- 2026926412,
- 1641021687,
- 1007809627,
- 342664462,
- -154718428,
- -378159261,
- -343110822,
- -157570845,
- 42722226,
- 158628552,
- 161152154,
- 84476999,
- -9051809,
- -67991881,
- -74299097,
- -42233558,
- -862781,
- 25821331,
- 29781227,
- 17674531,
- 2033391,
- -7689901,
- -9096696,
- -5320411,
- -919724,
- 1384024,
- 1473953,
- 649372
-
-};
-struct src_stage src_int32_1_3_2292_5000 = {
- 1, 0, 1, 56, 56, 3, 1, 0, 2,
- src_int32_1_3_2292_5000_fir};
diff --git a/src/include/sof/audio/coefficients/src/src_std_int32_1_3_4583_5000.h b/src/include/sof/audio/coefficients/src/src_std_int32_1_3_4583_5000.h
deleted file mode 100644
index 7f294f9..0000000
--- a/src/include/sof/audio/coefficients/src/src_std_int32_1_3_4583_5000.h
+++ /dev/null
@@ -1,306 +0,0 @@
-const int32_t src_int32_1_3_4583_5000_fir[300] = {
- -59364,
- -58842,
- 6638,
- 85996,
- 96862,
- 7746,
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-
-};
-struct src_stage src_int32_1_3_4583_5000 = {
- 1, 0, 1, 300, 300, 3, 1, 0, 1,
- src_int32_1_3_4583_5000_fir};
diff --git a/src/include/sof/audio/coefficients/src/src_std_int32_20_21_4211_5000.h b/src/include/sof/audio/coefficients/src/src_std_int32_20_21_4211_5000.h
deleted file mode 100644
index a169f31..0000000
--- a/src/include/sof/audio/coefficients/src/src_std_int32_20_21_4211_5000.h
+++ /dev/null
@@ -1,1126 +0,0 @@
-const int32_t src_int32_20_21_4211_5000_fir[1120] = {
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-
-};
-struct src_stage src_int32_20_21_4211_5000 = {
- 1, 1, 20, 56, 1120, 21, 20, 0, 0,
- src_int32_20_21_4211_5000_fir};
diff --git a/src/include/sof/audio/coefficients/src/src_std_int32_20_7_3008_5000.h b/src/include/sof/audio/coefficients/src/src_std_int32_20_7_3008_5000.h
deleted file mode 100644
index b4657a1..0000000
--- a/src/include/sof/audio/coefficients/src/src_std_int32_20_7_3008_5000.h
+++ /dev/null
@@ -1,486 +0,0 @@
-const int32_t src_int32_20_7_3008_5000_fir[480] = {
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- -26460511,
- 41313007,
- -28585464,
- 10944487,
- -318876,
- -2427337,
- 1463845,
- -310180
-
-};
-struct src_stage src_int32_20_7_3008_5000 = {
- 1, 3, 20, 24, 480, 7, 20, 0, 0,
- src_int32_20_7_3008_5000_fir};
diff --git a/src/include/sof/audio/coefficients/src/src_std_int32_21_20_4211_5000.h b/src/include/sof/audio/coefficients/src/src_std_int32_21_20_4211_5000.h
deleted file mode 100644
index 48d81ac..0000000
--- a/src/include/sof/audio/coefficients/src/src_std_int32_21_20_4211_5000.h
+++ /dev/null
@@ -1,1098 +0,0 @@
-const int32_t src_int32_21_20_4211_5000_fir[1092] = {
- -114538,
- 151923,
- -84166,
- -178697,
- 734429,
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- 10714080,
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- 33265423,
- -51925454,
- 73231834,
- -96345372,
- 120260060,
- -144001051,
- 167057166,
- -190775672,
- 227517672,
- 1965117948,
- 129033951,
- -146934314,
- 143375885,
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- 114744201,
- -95495083,
- 75387984,
- -55848396,
- 38013130,
- -22697516,
- 10378123,
- -1204217,
- -4961511,
- 8479094,
- -9853982,
- 9657070,
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- 6737839,
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- 3246542,
- -1903878,
- 939038,
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- 95041,
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- 209306,
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- -14834,
- 507575,
- -1391149,
- 2734431,
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- 12792534,
- -10983480,
- 6537022,
- 1147130,
- -12515973,
- 27793919,
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- 69639505,
- -95381156,
- 123617740,
- -154179826,
- 188375293,
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- 331695057,
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- 37067409,
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-
-};
-struct src_stage src_int32_21_20_4211_5000 = {
- 19, 20, 21, 52, 1092, 20, 21, 0, 0,
- src_int32_21_20_4211_5000_fir};
diff --git a/src/include/sof/audio/coefficients/src/src_std_int32_21_40_4010_5000.h b/src/include/sof/audio/coefficients/src/src_std_int32_21_40_4010_5000.h
deleted file mode 100644
index 784088d..0000000
--- a/src/include/sof/audio/coefficients/src/src_std_int32_21_40_4010_5000.h
+++ /dev/null
@@ -1,1686 +0,0 @@
-const int32_t src_int32_21_40_4010_5000_fir[1680] = {
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-};
-struct src_stage src_int32_21_40_4010_5000 = {
- 19, 10, 21, 80, 1680, 40, 21, 0, 1,
- src_int32_21_40_4010_5000_fir};
diff --git a/src/include/sof/audio/coefficients/src/src_std_int32_21_80_4010_5000.h b/src/include/sof/audio/coefficients/src/src_std_int32_21_80_4010_5000.h
deleted file mode 100644
index 1035d11..0000000
--- a/src/include/sof/audio/coefficients/src/src_std_int32_21_80_4010_5000.h
+++ /dev/null
@@ -1,3282 +0,0 @@
-const int32_t src_int32_21_80_4010_5000_fir[3276] = {
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-};
-struct src_stage src_int32_21_80_4010_5000 = {
- 19, 5, 21, 156, 3276, 80, 21, 0, 2,
- src_int32_21_80_4010_5000_fir};
diff --git a/src/include/sof/audio/coefficients/src/src_std_int32_2_1_2292_5000.h b/src/include/sof/audio/coefficients/src/src_std_int32_2_1_2292_5000.h
deleted file mode 100644
index 348c832..0000000
--- a/src/include/sof/audio/coefficients/src/src_std_int32_2_1_2292_5000.h
+++ /dev/null
@@ -1,46 +0,0 @@
-const int32_t src_int32_2_1_2292_5000_fir[40] = {
- -145826,
- 2533728,
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- 19560083,
- 5186764,
- -7345199,
- 2533728,
- -145826
-
-};
-struct src_stage src_int32_2_1_2292_5000 = {
- 0, 1, 2, 20, 40, 1, 2, 0, 0,
- src_int32_2_1_2292_5000_fir};
diff --git a/src/include/sof/audio/coefficients/src/src_std_int32_2_1_4583_5000.h b/src/include/sof/audio/coefficients/src/src_std_int32_2_1_4583_5000.h
deleted file mode 100644
index 87eb344..0000000
--- a/src/include/sof/audio/coefficients/src/src_std_int32_2_1_4583_5000.h
+++ /dev/null
@@ -1,214 +0,0 @@
-const int32_t src_int32_2_1_4583_5000_fir[208] = {
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- 10688906,
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- 9240876,
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- 143965,
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-
-};
-struct src_stage src_int32_2_1_4583_5000 = {
- 0, 1, 2, 104, 208, 1, 2, 0, 0,
- src_int32_2_1_4583_5000_fir};
diff --git a/src/include/sof/audio/coefficients/src/src_std_int32_2_3_4583_5000.h b/src/include/sof/audio/coefficients/src/src_std_int32_2_3_4583_5000.h
deleted file mode 100644
index 2d53b5b..0000000
--- a/src/include/sof/audio/coefficients/src/src_std_int32_2_3_4583_5000.h
+++ /dev/null
@@ -1,310 +0,0 @@
-const int32_t src_int32_2_3_4583_5000_fir[304] = {
- 43929,
- -78502,
- 8449,
- 119833,
- -137194,
- -41590,
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-
-};
-struct src_stage src_int32_2_3_4583_5000 = {
- 1, 1, 2, 152, 304, 3, 2, 0, 0,
- src_int32_2_3_4583_5000_fir};
diff --git a/src/include/sof/audio/coefficients/src/src_std_int32_32_21_4583_5000.h b/src/include/sof/audio/coefficients/src/src_std_int32_32_21_4583_5000.h
deleted file mode 100644
index 669d86c..0000000
--- a/src/include/sof/audio/coefficients/src/src_std_int32_32_21_4583_5000.h
+++ /dev/null
@@ -1,3206 +0,0 @@
-const int32_t src_int32_32_21_4583_5000_fir[3200] = {
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- 27564904,
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- 858220,
- -2827052,
- 4322609,
- -5385809,
- 6063371,
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- 6465606,
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- 3649216,
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- 224282,
- -73762,
- -28282,
- 90160,
- -120263,
- 126606,
- -116485,
- 96232,
- -71074
-
-};
-struct src_stage src_int32_32_21_4583_5000 = {
- 19, 29, 32, 100, 3200, 21, 32, 0, 0,
- src_int32_32_21_4583_5000_fir};
diff --git a/src/include/sof/audio/coefficients/src/src_std_int32_3_1_2292_5000.h b/src/include/sof/audio/coefficients/src/src_std_int32_3_1_2292_5000.h
deleted file mode 100644
index d9c8142..0000000
--- a/src/include/sof/audio/coefficients/src/src_std_int32_3_1_2292_5000.h
+++ /dev/null
@@ -1,66 +0,0 @@
-const int32_t src_int32_3_1_2292_5000_fir[60] = {
- -221419,
- 2634255,
- -6524336,
- 2088343,
- 23768236,
- -63471741,
- 68467776,
- 33377758,
- -288416102,
- 758538371,
- 1520635619,
- 258755541,
- -263459098,
- 125267023,
- -7451354,
- -36881538,
- 28294944,
- -8292137,
- -1232880,
- 1536684,
- 318564,
- 2087777,
- -10394465,
- 17410740,
- -772318,
- -56956359,
- 128821853,
- -121963980,
- -117347361,
- 1232454962,
- 1232454962,
- -117347361,
- -121963980,
- 128821853,
- -56956359,
- -772318,
- 17410740,
- -10394465,
- 2087777,
- 318564,
- 1536684,
- -1232880,
- -8292137,
- 28294944,
- -36881538,
- -7451354,
- 125267023,
- -263459098,
- 258755541,
- 1520635619,
- 758538371,
- -288416102,
- 33377758,
- 68467776,
- -63471741,
- 23768236,
- 2088343,
- -6524336,
- 2634255,
- -221419
-
-};
-struct src_stage src_int32_3_1_2292_5000 = {
- 0, 1, 3, 20, 60, 1, 3, 0, 0,
- src_int32_3_1_2292_5000_fir};
diff --git a/src/include/sof/audio/coefficients/src/src_std_int32_3_1_4583_5000.h b/src/include/sof/audio/coefficients/src/src_std_int32_3_1_4583_5000.h
deleted file mode 100644
index 84f2ceb..0000000
--- a/src/include/sof/audio/coefficients/src/src_std_int32_3_1_4583_5000.h
+++ /dev/null
@@ -1,306 +0,0 @@
-const int32_t src_int32_3_1_4583_5000_fir[300] = {
- -89046,
- 128995,
- -170056,
- 207786,
- -236355,
- 248563,
- -235952,
- 189020,
- -97551,
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- 1915288,
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- 3257404,
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- 17755528,
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- 31421132,
- -39445069,
- 48291419,
- -58007344,
- 68685720,
- -80503739,
- 93794057,
- -109187001,
- 127926251,
- -152674240,
- 190016796,
- -261154775,
- 489554026,
- 1966703310,
- -206075947,
- 68433746,
- -17013112,
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- 25425397,
- -35229476,
- 41252062,
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- 46108010,
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- 44918643,
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- 40122318,
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- 18178784,
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- 11413619,
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- 3591736,
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- 3279021,
- -2991952,
- 2656507,
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- 1934718,
- -1585336,
- 1261475,
- -971694,
- 721095,
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- 343306,
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- 117960,
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- -420536,
- 543432,
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- 810704,
- -938996,
- 1048991,
- -1126672,
- 1155882,
- -1118689,
- 995927,
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- 415181,
- 80275,
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- -85754537,
- 61060689,
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- 16955274,
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- 10000987,
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- 6606947,
- -5095018,
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- 1558489,
- -734145,
- 80275,
- 415181,
- -767887,
- 995927,
- -1118689,
- 1155882,
- -1126672,
- 1048991,
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- 810704,
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- 543432,
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- 311722,
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- -213312,
- 343306,
- -511771,
- 721095,
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- 1261475,
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- 1934718,
- -2297248,
- 2656507,
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- 3279021,
- -3489438,
- 3591736,
- -3552004,
- 3334856,
- -2904604,
- 2226618,
- -1268831,
- 3357,
- 1591834,
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- 5820222,
- -8453455,
- 11413619,
- -14670239,
- 18178784,
- -21879995,
- 25699441,
- -29547218,
- 33317691,
- -36889045,
- 40122318,
- -42859342,
- 44918643,
- -46087628,
- 46108010,
- -44648478,
- 41252062,
- -35229476,
- 25425397,
- -9644612,
- -17013112,
- 68433746,
- -206075947,
- 1966703310,
- 489554026,
- -261154775,
- 190016796,
- -152674240,
- 127926251,
- -109187001,
- 93794057,
- -80503739,
- 68685720,
- -58007344,
- 48291419,
- -39445069,
- 31421132,
- -24195867,
- 17755528,
- -12088088,
- 7178195,
- -3004245,
- -463069,
- 3261148,
- -5435119,
- 7036901,
- -8123898,
- 8757436,
- -9001081,
- 8918933,
- -8573976,
- 8026567,
- -7333113,
- 6544982,
- -5707662,
- 4860208,
- -4034939,
- 3257404,
- -2546584,
- 1915288,
- -1370725,
- 915197,
- -546885,
- 260664,
- -48942,
- -97551,
- 189020,
- -235952,
- 248563,
- -236355,
- 207786,
- -170056,
- 128995,
- -89046
-
-};
-struct src_stage src_int32_3_1_4583_5000 = {
- 0, 1, 3, 100, 300, 1, 3, 0, 0,
- src_int32_3_1_4583_5000_fir};
diff --git a/src/include/sof/audio/coefficients/src/src_std_int32_3_2_4583_5000.h b/src/include/sof/audio/coefficients/src/src_std_int32_3_2_4583_5000.h
deleted file mode 100644
index 1a16d39..0000000
--- a/src/include/sof/audio/coefficients/src/src_std_int32_3_2_4583_5000.h
+++ /dev/null
@@ -1,306 +0,0 @@
-const int32_t src_int32_3_2_4583_5000_fir[300] = {
- -89046,
- 128995,
- -170056,
- 207786,
- -236355,
- 248563,
- -235952,
- 189020,
- -97551,
- -48942,
- 260664,
- -546885,
- 915197,
- -1370725,
- 1915288,
- -2546584,
- 3257404,
- -4034939,
- 4860208,
- -5707662,
- 6544982,
- -7333113,
- 8026567,
- -8573976,
- 8918933,
- -9001081,
- 8757436,
- -8123898,
- 7036901,
- -5435119,
- 3261148,
- -463069,
- -3004245,
- 7178195,
- -12088088,
- 17755528,
- -24195867,
- 31421132,
- -39445069,
- 48291419,
- -58007344,
- 68685720,
- -80503739,
- 93794057,
- -109187001,
- 127926251,
- -152674240,
- 190016796,
- -261154775,
- 489554026,
- 1966703310,
- -206075947,
- 68433746,
- -17013112,
- -9644612,
- 25425397,
- -35229476,
- 41252062,
- -44648478,
- 46108010,
- -46087628,
- 44918643,
- -42859342,
- 40122318,
- -36889045,
- 33317691,
- -29547218,
- 25699441,
- -21879995,
- 18178784,
- -14670239,
- 11413619,
- -8453455,
- 5820222,
- -3531244,
- 1591834,
- 3357,
- -1268831,
- 2226618,
- -2904604,
- 3334856,
- -3552004,
- 3591736,
- -3489438,
- 3279021,
- -2991952,
- 2656507,
- -2297248,
- 1934718,
- -1585336,
- 1261475,
- -971694,
- 721095,
- -511771,
- 343306,
- -213312,
- 117960,
- -52479,
- 11618,
- 9958,
- -88263,
- 145292,
- -219650,
- 311722,
- -420536,
- 543432,
- -675773,
- 810704,
- -938996,
- 1048991,
- -1126672,
- 1155882,
- -1118689,
- 995927,
- -767887,
- 415181,
- 80275,
- -734145,
- 1558489,
- -2560524,
- 3741400,
- -5095018,
- 6606947,
- -8253500,
- 10000987,
- -11805215,
- 13611226,
- -15353310,
- 16955274,
- -18330940,
- 19384806,
- -20012799,
- 20102951,
- -19535833,
- 18184439,
- -15913122,
- 12574966,
- -8006627,
- 2019081,
- 5618407,
- -15205985,
- 27161943,
- -42111796,
- 61060689,
- -85754537,
- 119522690,
- -169564070,
- 254717058,
- -444301706,
- 1363041030,
- 1363041030,
- -444301706,
- 254717058,
- -169564070,
- 119522690,
- -85754537,
- 61060689,
- -42111796,
- 27161943,
- -15205985,
- 5618407,
- 2019081,
- -8006627,
- 12574966,
- -15913122,
- 18184439,
- -19535833,
- 20102951,
- -20012799,
- 19384806,
- -18330940,
- 16955274,
- -15353310,
- 13611226,
- -11805215,
- 10000987,
- -8253500,
- 6606947,
- -5095018,
- 3741400,
- -2560524,
- 1558489,
- -734145,
- 80275,
- 415181,
- -767887,
- 995927,
- -1118689,
- 1155882,
- -1126672,
- 1048991,
- -938996,
- 810704,
- -675773,
- 543432,
- -420536,
- 311722,
- -219650,
- 145292,
- -88263,
- 9958,
- 11618,
- -52479,
- 117960,
- -213312,
- 343306,
- -511771,
- 721095,
- -971694,
- 1261475,
- -1585336,
- 1934718,
- -2297248,
- 2656507,
- -2991952,
- 3279021,
- -3489438,
- 3591736,
- -3552004,
- 3334856,
- -2904604,
- 2226618,
- -1268831,
- 3357,
- 1591834,
- -3531244,
- 5820222,
- -8453455,
- 11413619,
- -14670239,
- 18178784,
- -21879995,
- 25699441,
- -29547218,
- 33317691,
- -36889045,
- 40122318,
- -42859342,
- 44918643,
- -46087628,
- 46108010,
- -44648478,
- 41252062,
- -35229476,
- 25425397,
- -9644612,
- -17013112,
- 68433746,
- -206075947,
- 1966703310,
- 489554026,
- -261154775,
- 190016796,
- -152674240,
- 127926251,
- -109187001,
- 93794057,
- -80503739,
- 68685720,
- -58007344,
- 48291419,
- -39445069,
- 31421132,
- -24195867,
- 17755528,
- -12088088,
- 7178195,
- -3004245,
- -463069,
- 3261148,
- -5435119,
- 7036901,
- -8123898,
- 8757436,
- -9001081,
- 8918933,
- -8573976,
- 8026567,
- -7333113,
- 6544982,
- -5707662,
- 4860208,
- -4034939,
- 3257404,
- -2546584,
- 1915288,
- -1370725,
- 915197,
- -546885,
- 260664,
- -48942,
- -97551,
- 189020,
- -235952,
- 248563,
- -236355,
- 207786,
- -170056,
- 128995,
- -89046
-
-};
-struct src_stage src_int32_3_2_4583_5000 = {
- 1, 2, 3, 100, 300, 2, 3, 0, 0,
- src_int32_3_2_4583_5000_fir};
diff --git a/src/include/sof/audio/coefficients/src/src_std_int32_3_4_4583_5000.h b/src/include/sof/audio/coefficients/src/src_std_int32_3_4_4583_5000.h
deleted file mode 100644
index 767b020..0000000
--- a/src/include/sof/audio/coefficients/src/src_std_int32_3_4_4583_5000.h
+++ /dev/null
@@ -1,402 +0,0 @@
-const int32_t src_int32_3_4_4583_5000_fir[396] = {
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-};
-struct src_stage src_int32_3_4_4583_5000 = {
- 1, 1, 3, 132, 396, 4, 3, 0, 0,
- src_int32_3_4_4583_5000_fir};
diff --git a/src/include/sof/audio/coefficients/src/src_std_int32_40_21_4010_5000.h b/src/include/sof/audio/coefficients/src/src_std_int32_40_21_4010_5000.h
deleted file mode 100644
index eea6325..0000000
--- a/src/include/sof/audio/coefficients/src/src_std_int32_40_21_4010_5000.h
+++ /dev/null
@@ -1,1766 +0,0 @@
-const int32_t src_int32_40_21_4010_5000_fir[1760] = {
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- 217362,
- 608526,
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- 11657340,
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- 15531966,
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- 304764993,
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- 42695401,
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- -17997094,
- 18351267,
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- 11726967,
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- 4020000,
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- 30697,
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- 8248690,
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- 49608386,
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- 178691758,
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- 1912934819,
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- 114585119,
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- 4305952,
- -1765736,
- 228976,
- 468538,
- -600747,
- 445779,
- -217887
-
-};
-struct src_stage src_int32_40_21_4010_5000 = {
- 11, 21, 40, 44, 1760, 21, 40, 0, 0,
- src_int32_40_21_4010_5000_fir};
diff --git a/src/include/sof/audio/coefficients/src/src_std_int32_4_3_4583_5000.h b/src/include/sof/audio/coefficients/src/src_std_int32_4_3_4583_5000.h
deleted file mode 100644
index 8c8a47f..0000000
--- a/src/include/sof/audio/coefficients/src/src_std_int32_4_3_4583_5000.h
+++ /dev/null
@@ -1,406 +0,0 @@
-const int32_t src_int32_4_3_4583_5000_fir[400] = {
- -85832,
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- -225919,
- 239422,
- -228238,
- 200809,
- -164306,
- 124516,
- -85832
-
-};
-struct src_stage src_int32_4_3_4583_5000 = {
- 2, 3, 4, 100, 400, 3, 4, 0, 0,
- src_int32_4_3_4583_5000_fir};
diff --git a/src/include/sof/audio/coefficients/src/src_std_int32_5_7_4583_5000.h b/src/include/sof/audio/coefficients/src/src_std_int32_5_7_4583_5000.h
deleted file mode 100644
index 8b0e9c7..0000000
--- a/src/include/sof/audio/coefficients/src/src_std_int32_5_7_4583_5000.h
+++ /dev/null
@@ -1,686 +0,0 @@
-const int32_t src_int32_5_7_4583_5000_fir[680] = {
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-
-};
-struct src_stage src_int32_5_7_4583_5000 = {
- 4, 3, 5, 136, 680, 7, 5, 0, 0,
- src_int32_5_7_4583_5000_fir};
diff --git a/src/include/sof/audio/coefficients/src/src_std_int32_7_8_4583_5000.h b/src/include/sof/audio/coefficients/src/src_std_int32_7_8_4583_5000.h
deleted file mode 100644
index 0a21713..0000000
--- a/src/include/sof/audio/coefficients/src/src_std_int32_7_8_4583_5000.h
+++ /dev/null
@@ -1,846 +0,0 @@
-const int32_t src_int32_7_8_4583_5000_fir[840] = {
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- -5025198,
- 10841010,
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- 11170322,
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- 1570012,
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- -6257039,
- 7116750,
- -5955710,
- 3462116,
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- -3645000,
- 2895950,
- -1548019,
- 94500,
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- 167729,
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- 19740,
- 24705,
- -38348
-
-};
-struct src_stage src_int32_7_8_4583_5000 = {
- 1, 1, 7, 120, 840, 8, 7, 0, 0,
- src_int32_7_8_4583_5000_fir};
diff --git a/src/include/sof/audio/coefficients/src/src_std_int32_8_21_3274_5000.h b/src/include/sof/audio/coefficients/src/src_std_int32_8_21_3274_5000.h
deleted file mode 100644
index 98f32d4..0000000
--- a/src/include/sof/audio/coefficients/src/src_std_int32_8_21_3274_5000.h
+++ /dev/null
@@ -1,518 +0,0 @@
-const int32_t src_int32_8_21_3274_5000_fir[512] = {
- -178494,
- -568271,
- -519183,
- 535412,
- 2055848,
- 2208117,
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- 40275621,
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-
-};
-struct src_stage src_int32_8_21_3274_5000 = {
- 13, 5, 8, 64, 512, 21, 8, 0, 1,
- src_int32_8_21_3274_5000_fir};
diff --git a/src/include/sof/audio/coefficients/src/src_std_int32_8_7_2494_5000.h b/src/include/sof/audio/coefficients/src/src_std_int32_8_7_2494_5000.h
deleted file mode 100644
index a51b44b..0000000
--- a/src/include/sof/audio/coefficients/src/src_std_int32_8_7_2494_5000.h
+++ /dev/null
@@ -1,166 +0,0 @@
-const int32_t src_int32_8_7_2494_5000_fir[160] = {
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-
-};
-struct src_stage src_int32_8_7_2494_5000 = {
- 6, 7, 8, 20, 160, 7, 8, 0, 0,
- src_int32_8_7_2494_5000_fir};
diff --git a/src/include/sof/audio/coefficients/src/src_std_int32_8_7_4583_5000.h b/src/include/sof/audio/coefficients/src/src_std_int32_8_7_4583_5000.h
deleted file mode 100644
index 963a1e6..0000000
--- a/src/include/sof/audio/coefficients/src/src_std_int32_8_7_4583_5000.h
+++ /dev/null
@@ -1,838 +0,0 @@
-const int32_t src_int32_8_7_4583_5000_fir[832] = {
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-
-};
-struct src_stage src_int32_8_7_4583_5000 = {
- 6, 7, 8, 104, 832, 7, 8, 0, 0,
- src_int32_8_7_4583_5000_fir};
diff --git a/src/include/sof/audio/coefficients/src/src_std_int32_define.h b/src/include/sof/audio/coefficients/src/src_std_int32_define.h
deleted file mode 100644
index 33fbe6d..0000000
--- a/src/include/sof/audio/coefficients/src/src_std_int32_define.h
+++ /dev/null
@@ -1,11 +0,0 @@
-/* SRC constants */
-#define MAX_FIR_DELAY_SIZE 710
-#define MAX_OUT_DELAY_SIZE 900
-#define MAX_BLK_IN 80
-#define MAX_BLK_OUT 40
-#define NUM_IN_FS 15
-#define NUM_OUT_FS 10
-#define STAGE1_TIMES_MAX 21
-#define STAGE2_TIMES_MAX 32
-#define STAGE_BUF_SIZE 224
-#define NUM_ALL_COEFFICIENTS 22256
diff --git a/src/include/sof/audio/coefficients/src/src_std_int32_table.h b/src/include/sof/audio/coefficients/src/src_std_int32_table.h
deleted file mode 100644
index fc84d80..0000000
--- a/src/include/sof/audio/coefficients/src/src_std_int32_table.h
+++ /dev/null
@@ -1,211 +0,0 @@
-/* SRC conversions */
-#include <sof/audio/coefficients/src/src_std_int32_1_2_2292_5000.h>
-#include <sof/audio/coefficients/src/src_std_int32_1_2_4583_5000.h>
-#include <sof/audio/coefficients/src/src_std_int32_1_3_2292_5000.h>
-#include <sof/audio/coefficients/src/src_std_int32_1_3_4583_5000.h>
-#include <sof/audio/coefficients/src/src_std_int32_2_1_2292_5000.h>
-#include <sof/audio/coefficients/src/src_std_int32_2_1_4583_5000.h>
-#include <sof/audio/coefficients/src/src_std_int32_2_3_4583_5000.h>
-#include <sof/audio/coefficients/src/src_std_int32_3_1_2292_5000.h>
-#include <sof/audio/coefficients/src/src_std_int32_3_1_4583_5000.h>
-#include <sof/audio/coefficients/src/src_std_int32_3_2_4583_5000.h>
-#include <sof/audio/coefficients/src/src_std_int32_3_4_4583_5000.h>
-#include <sof/audio/coefficients/src/src_std_int32_4_3_4583_5000.h>
-#include <sof/audio/coefficients/src/src_std_int32_5_7_4583_5000.h>
-#include <sof/audio/coefficients/src/src_std_int32_7_8_4583_5000.h>
-#include <sof/audio/coefficients/src/src_std_int32_8_7_2494_5000.h>
-#include <sof/audio/coefficients/src/src_std_int32_8_7_4583_5000.h>
-#include <sof/audio/coefficients/src/src_std_int32_8_21_3274_5000.h>
-#include <sof/audio/coefficients/src/src_std_int32_10_9_4583_5000.h>
-#include <sof/audio/coefficients/src/src_std_int32_10_21_4583_5000.h>
-#include <sof/audio/coefficients/src/src_std_int32_16_7_4125_5000.h>
-#include <sof/audio/coefficients/src/src_std_int32_20_7_3008_5000.h>
-#include <sof/audio/coefficients/src/src_std_int32_20_21_4211_5000.h>
-#include <sof/audio/coefficients/src/src_std_int32_21_20_4211_5000.h>
-#include <sof/audio/coefficients/src/src_std_int32_21_40_4010_5000.h>
-#include <sof/audio/coefficients/src/src_std_int32_21_80_4010_5000.h>
-#include <sof/audio/coefficients/src/src_std_int32_32_21_4583_5000.h>
-#include <sof/audio/coefficients/src/src_std_int32_40_21_4010_5000.h>
-
-/* SRC table */
-int32_t fir_one = 1073741824;
-struct src_stage src_int32_1_1_0_0 = { 0, 0, 1, 1, 1, 1, 1, 0, -1, &fir_one };
-struct src_stage src_int32_0_0_0_0 = { 0, 0, 0, 0, 0, 0, 0, 0, 0, &fir_one };
-int src_in_fs[15] = { 8000, 11025, 12000, 16000, 18900, 22050, 24000, 32000,
- 44100, 48000, 64000, 88200, 96000, 176400, 192000};
-int src_out_fs[10] = { 8000, 11025, 12000, 16000, 18900, 22050, 24000, 32000,
- 44100, 48000};
-struct src_stage *src_table1[10][15] = {
- { &src_int32_1_1_0_0, &src_int32_0_0_0_0,
- &src_int32_0_0_0_0, &src_int32_1_2_4583_5000,
- &src_int32_0_0_0_0, &src_int32_0_0_0_0,
- &src_int32_1_3_4583_5000, &src_int32_1_2_2292_5000,
- &src_int32_0_0_0_0, &src_int32_1_3_2292_5000,
- &src_int32_0_0_0_0, &src_int32_0_0_0_0,
- &src_int32_0_0_0_0, &src_int32_0_0_0_0,
- &src_int32_0_0_0_0},
- { &src_int32_0_0_0_0,
- &src_int32_1_1_0_0, &src_int32_0_0_0_0,
- &src_int32_0_0_0_0, &src_int32_0_0_0_0,
- &src_int32_0_0_0_0, &src_int32_0_0_0_0,
- &src_int32_0_0_0_0, &src_int32_0_0_0_0,
- &src_int32_21_80_4010_5000, &src_int32_0_0_0_0,
- &src_int32_0_0_0_0, &src_int32_0_0_0_0,
- &src_int32_0_0_0_0, &src_int32_0_0_0_0
- },
- { &src_int32_0_0_0_0, &src_int32_0_0_0_0,
- &src_int32_1_1_0_0, &src_int32_0_0_0_0,
- &src_int32_0_0_0_0, &src_int32_0_0_0_0,
- &src_int32_0_0_0_0, &src_int32_0_0_0_0,
- &src_int32_0_0_0_0, &src_int32_1_2_2292_5000,
- &src_int32_0_0_0_0, &src_int32_0_0_0_0,
- &src_int32_0_0_0_0, &src_int32_0_0_0_0,
- &src_int32_0_0_0_0},
- { &src_int32_2_1_4583_5000,
- &src_int32_0_0_0_0, &src_int32_0_0_0_0,
- &src_int32_1_1_0_0, &src_int32_0_0_0_0,
- &src_int32_0_0_0_0, &src_int32_2_3_4583_5000,
- &src_int32_1_2_4583_5000, &src_int32_0_0_0_0,
- &src_int32_1_3_4583_5000, &src_int32_0_0_0_0,
- &src_int32_0_0_0_0, &src_int32_0_0_0_0,
- &src_int32_0_0_0_0, &src_int32_0_0_0_0
- },
- { &src_int32_0_0_0_0, &src_int32_0_0_0_0,
- &src_int32_0_0_0_0, &src_int32_0_0_0_0,
- &src_int32_1_1_0_0, &src_int32_0_0_0_0,
- &src_int32_0_0_0_0, &src_int32_0_0_0_0,
- &src_int32_0_0_0_0, &src_int32_0_0_0_0,
- &src_int32_0_0_0_0, &src_int32_0_0_0_0,
- &src_int32_0_0_0_0, &src_int32_0_0_0_0,
- &src_int32_0_0_0_0},
- { &src_int32_0_0_0_0,
- &src_int32_0_0_0_0, &src_int32_0_0_0_0,
- &src_int32_0_0_0_0, &src_int32_0_0_0_0,
- &src_int32_1_1_0_0, &src_int32_0_0_0_0,
- &src_int32_0_0_0_0, &src_int32_0_0_0_0,
- &src_int32_21_40_4010_5000, &src_int32_0_0_0_0,
- &src_int32_0_0_0_0, &src_int32_0_0_0_0,
- &src_int32_0_0_0_0, &src_int32_0_0_0_0
- },
- { &src_int32_3_1_4583_5000, &src_int32_0_0_0_0,
- &src_int32_0_0_0_0, &src_int32_3_2_4583_5000,
- &src_int32_0_0_0_0, &src_int32_0_0_0_0,
- &src_int32_1_1_0_0, &src_int32_3_4_4583_5000,
- &src_int32_0_0_0_0, &src_int32_1_2_4583_5000,
- &src_int32_0_0_0_0, &src_int32_0_0_0_0,
- &src_int32_0_0_0_0, &src_int32_0_0_0_0,
- &src_int32_0_0_0_0},
- { &src_int32_2_1_4583_5000,
- &src_int32_0_0_0_0, &src_int32_0_0_0_0,
- &src_int32_2_1_4583_5000, &src_int32_0_0_0_0,
- &src_int32_0_0_0_0, &src_int32_4_3_4583_5000,
- &src_int32_1_1_0_0, &src_int32_0_0_0_0,
- &src_int32_2_3_4583_5000, &src_int32_0_0_0_0,
- &src_int32_0_0_0_0, &src_int32_0_0_0_0,
- &src_int32_0_0_0_0, &src_int32_0_0_0_0
- },
- { &src_int32_0_0_0_0, &src_int32_0_0_0_0,
- &src_int32_0_0_0_0, &src_int32_0_0_0_0,
- &src_int32_0_0_0_0, &src_int32_0_0_0_0,
- &src_int32_0_0_0_0, &src_int32_0_0_0_0,
- &src_int32_1_1_0_0, &src_int32_21_20_4211_5000,
- &src_int32_0_0_0_0, &src_int32_0_0_0_0,
- &src_int32_0_0_0_0, &src_int32_0_0_0_0,
- &src_int32_0_0_0_0},
- { &src_int32_2_1_4583_5000,
- &src_int32_32_21_4583_5000, &src_int32_2_1_4583_5000,
- &src_int32_3_1_4583_5000, &src_int32_10_9_4583_5000,
- &src_int32_8_7_4583_5000, &src_int32_2_1_4583_5000,
- &src_int32_3_2_4583_5000, &src_int32_8_7_4583_5000,
- &src_int32_1_1_0_0, &src_int32_3_4_4583_5000,
- &src_int32_8_7_2494_5000, &src_int32_1_2_4583_5000,
- &src_int32_8_21_3274_5000, &src_int32_1_2_2292_5000
- }
-};
-struct src_stage *src_table2[10][15] = {
- { &src_int32_1_1_0_0, &src_int32_0_0_0_0,
- &src_int32_0_0_0_0, &src_int32_1_1_0_0,
- &src_int32_0_0_0_0, &src_int32_0_0_0_0,
- &src_int32_1_1_0_0, &src_int32_1_2_4583_5000,
- &src_int32_0_0_0_0, &src_int32_1_2_4583_5000,
- &src_int32_0_0_0_0, &src_int32_0_0_0_0,
- &src_int32_0_0_0_0, &src_int32_0_0_0_0,
- &src_int32_0_0_0_0},
- { &src_int32_0_0_0_0,
- &src_int32_1_1_0_0, &src_int32_0_0_0_0,
- &src_int32_0_0_0_0, &src_int32_0_0_0_0,
- &src_int32_0_0_0_0, &src_int32_0_0_0_0,
- &src_int32_0_0_0_0, &src_int32_0_0_0_0,
- &src_int32_7_8_4583_5000, &src_int32_0_0_0_0,
- &src_int32_0_0_0_0, &src_int32_0_0_0_0,
- &src_int32_0_0_0_0, &src_int32_0_0_0_0
- },
- { &src_int32_0_0_0_0, &src_int32_0_0_0_0,
- &src_int32_1_1_0_0, &src_int32_0_0_0_0,
- &src_int32_0_0_0_0, &src_int32_0_0_0_0,
- &src_int32_0_0_0_0, &src_int32_0_0_0_0,
- &src_int32_0_0_0_0, &src_int32_1_2_4583_5000,
- &src_int32_0_0_0_0, &src_int32_0_0_0_0,
- &src_int32_0_0_0_0, &src_int32_0_0_0_0,
- &src_int32_0_0_0_0},
- { &src_int32_1_1_0_0,
- &src_int32_0_0_0_0, &src_int32_0_0_0_0,
- &src_int32_1_1_0_0, &src_int32_0_0_0_0,
- &src_int32_0_0_0_0, &src_int32_1_1_0_0,
- &src_int32_1_1_0_0, &src_int32_0_0_0_0,
- &src_int32_1_1_0_0, &src_int32_0_0_0_0,
- &src_int32_0_0_0_0, &src_int32_0_0_0_0,
- &src_int32_0_0_0_0, &src_int32_0_0_0_0
- },
- { &src_int32_0_0_0_0, &src_int32_0_0_0_0,
- &src_int32_0_0_0_0, &src_int32_0_0_0_0,
- &src_int32_1_1_0_0, &src_int32_0_0_0_0,
- &src_int32_0_0_0_0, &src_int32_0_0_0_0,
- &src_int32_0_0_0_0, &src_int32_0_0_0_0,
- &src_int32_0_0_0_0, &src_int32_0_0_0_0,
- &src_int32_0_0_0_0, &src_int32_0_0_0_0,
- &src_int32_0_0_0_0},
- { &src_int32_0_0_0_0,
- &src_int32_0_0_0_0, &src_int32_0_0_0_0,
- &src_int32_0_0_0_0, &src_int32_0_0_0_0,
- &src_int32_1_1_0_0, &src_int32_0_0_0_0,
- &src_int32_0_0_0_0, &src_int32_0_0_0_0,
- &src_int32_7_8_4583_5000, &src_int32_0_0_0_0,
- &src_int32_0_0_0_0, &src_int32_0_0_0_0,
- &src_int32_0_0_0_0, &src_int32_0_0_0_0
- },
- { &src_int32_1_1_0_0, &src_int32_0_0_0_0,
- &src_int32_0_0_0_0, &src_int32_1_1_0_0,
- &src_int32_0_0_0_0, &src_int32_0_0_0_0,
- &src_int32_1_1_0_0, &src_int32_1_1_0_0,
- &src_int32_0_0_0_0, &src_int32_1_1_0_0,
- &src_int32_0_0_0_0, &src_int32_0_0_0_0,
- &src_int32_0_0_0_0, &src_int32_0_0_0_0,
- &src_int32_0_0_0_0},
- { &src_int32_2_1_2292_5000,
- &src_int32_0_0_0_0, &src_int32_0_0_0_0,
- &src_int32_1_1_0_0, &src_int32_0_0_0_0,
- &src_int32_0_0_0_0, &src_int32_1_1_0_0,
- &src_int32_1_1_0_0, &src_int32_0_0_0_0,
- &src_int32_1_1_0_0, &src_int32_0_0_0_0,
- &src_int32_0_0_0_0, &src_int32_0_0_0_0,
- &src_int32_0_0_0_0, &src_int32_0_0_0_0
- },
- { &src_int32_0_0_0_0, &src_int32_0_0_0_0,
- &src_int32_0_0_0_0, &src_int32_0_0_0_0,
- &src_int32_0_0_0_0, &src_int32_0_0_0_0,
- &src_int32_0_0_0_0, &src_int32_0_0_0_0,
- &src_int32_1_1_0_0, &src_int32_7_8_4583_5000,
- &src_int32_0_0_0_0, &src_int32_0_0_0_0,
- &src_int32_0_0_0_0, &src_int32_0_0_0_0,
- &src_int32_0_0_0_0},
- { &src_int32_3_1_2292_5000,
- &src_int32_20_7_3008_5000, &src_int32_2_1_2292_5000,
- &src_int32_1_1_0_0, &src_int32_16_7_4125_5000,
- &src_int32_40_21_4010_5000, &src_int32_1_1_0_0,
- &src_int32_1_1_0_0, &src_int32_20_21_4211_5000,
- &src_int32_1_1_0_0, &src_int32_1_1_0_0,
- &src_int32_10_21_4583_5000, &src_int32_1_1_0_0,
- &src_int32_5_7_4583_5000, &src_int32_1_2_4583_5000
- }
-};
diff --git a/src/include/sof/audio/coefficients/src/src_tiny_int16_1_2_3281_5000.h b/src/include/sof/audio/coefficients/src/src_tiny_int16_1_2_3281_5000.h
deleted file mode 100644
index 2f50660..0000000
--- a/src/include/sof/audio/coefficients/src/src_tiny_int16_1_2_3281_5000.h
+++ /dev/null
@@ -1,66 +0,0 @@
-const int16_t src_int16_1_2_3281_5000_fir[60] = {
- 2,
- -8,
- -16,
- 5,
- 41,
- 21,
- -64,
- -85,
- 52,
- 181,
- 39,
- -261,
- -236,
- 240,
- 510,
- -21,
- -755,
- -457,
- 784,
- 1154,
- -371,
- -1884,
- -688,
- 2301,
- 2564,
- -1849,
- -5621,
- -837,
- 12830,
- 25184,
- 25184,
- 12830,
- -837,
- -5621,
- -1849,
- 2564,
- 2301,
- -688,
- -1884,
- -371,
- 1154,
- 784,
- -457,
- -755,
- -21,
- 510,
- 240,
- -236,
- -261,
- 39,
- 181,
- 52,
- -85,
- -64,
- 21,
- 41,
- 5,
- -16,
- -8,
- 2
-
-};
-struct src_stage src_int16_1_2_3281_5000 = {
- 1, 0, 1, 60, 60, 2, 1, 0, 1,
- src_int16_1_2_3281_5000_fir};
diff --git a/src/include/sof/audio/coefficients/src/src_tiny_int16_1_3_1641_5000.h b/src/include/sof/audio/coefficients/src/src_tiny_int16_1_3_1641_5000.h
deleted file mode 100644
index 78cc850..0000000
--- a/src/include/sof/audio/coefficients/src/src_tiny_int16_1_3_1641_5000.h
+++ /dev/null
@@ -1,54 +0,0 @@
-const int16_t src_int16_1_3_1641_5000_fir[48] = {
- -7,
- 5,
- 42,
- 95,
- 118,
- 51,
- -136,
- -393,
- -563,
- -445,
- 79,
- 900,
- 1632,
- 1723,
- 750,
- -1249,
- -3563,
- -4921,
- -3944,
- 215,
- 7318,
- 15901,
- 23660,
- 28268,
- 28268,
- 23660,
- 15901,
- 7318,
- 215,
- -3944,
- -4921,
- -3563,
- -1249,
- 750,
- 1723,
- 1632,
- 900,
- 79,
- -445,
- -563,
- -393,
- -136,
- 51,
- 118,
- 95,
- 42,
- 5,
- -7
-
-};
-struct src_stage src_int16_1_3_1641_5000 = {
- 1, 0, 1, 48, 48, 3, 1, 0, 2,
- src_int16_1_3_1641_5000_fir};
diff --git a/src/include/sof/audio/coefficients/src/src_tiny_int16_1_3_3281_5000.h b/src/include/sof/audio/coefficients/src/src_tiny_int16_1_3_3281_5000.h
deleted file mode 100644
index 2b1b5cf..0000000
--- a/src/include/sof/audio/coefficients/src/src_tiny_int16_1_3_3281_5000.h
+++ /dev/null
@@ -1,94 +0,0 @@
-const int16_t src_int16_1_3_3281_5000_fir[88] = {
- -1,
- -6,
- -9,
- -5,
- 7,
- 21,
- 23,
- 4,
- -31,
- -56,
- -42,
- 16,
- 86,
- 111,
- 49,
- -78,
- -185,
- -173,
- -12,
- 212,
- 330,
- 212,
- -115,
- -443,
- -503,
- -172,
- 389,
- 788,
- 659,
- -36,
- -890,
- -1259,
- -713,
- 568,
- 1770,
- 1900,
- 498,
- -1849,
- -3604,
- -3045,
- 682,
- 6863,
- 13333,
- 17459,
- 17459,
- 13333,
- 6863,
- 682,
- -3045,
- -3604,
- -1849,
- 498,
- 1900,
- 1770,
- 568,
- -713,
- -1259,
- -890,
- -36,
- 659,
- 788,
- 389,
- -172,
- -503,
- -443,
- -115,
- 212,
- 330,
- 212,
- -12,
- -173,
- -185,
- -78,
- 49,
- 111,
- 86,
- 16,
- -42,
- -56,
- -31,
- 4,
- 23,
- 21,
- 7,
- -5,
- -9,
- -6,
- -1
-
-};
-struct src_stage src_int16_1_3_3281_5000 = {
- 1, 0, 1, 88, 88, 3, 1, 0, 1,
- src_int16_1_3_3281_5000_fir};
diff --git a/src/include/sof/audio/coefficients/src/src_tiny_int16_20_21_3015_5000.h b/src/include/sof/audio/coefficients/src/src_tiny_int16_20_21_3015_5000.h
deleted file mode 100644
index 641148c..0000000
--- a/src/include/sof/audio/coefficients/src/src_tiny_int16_20_21_3015_5000.h
+++ /dev/null
@@ -1,486 +0,0 @@
-const int16_t src_int16_20_21_3015_5000_fir[480] = {
- 1,
- 12,
- -59,
- 112,
- -53,
- -247,
- 719,
- -937,
- 246,
- 1768,
- -4802,
- 7954,
- 24354,
- 6745,
- -4683,
- 1969,
- 34,
- -832,
- 713,
- -280,
- -23,
- 100,
- -58,
- 13,
- 2,
- 10,
- -60,
- 124,
- -84,
- -208,
- 716,
- -1033,
- 463,
- 1531,
- -4859,
- 9182,
- 24241,
- 5563,
- -4508,
- 2135,
- -168,
- -720,
- 695,
- -308,
- 5,
- 87,
- -56,
- 14,
- 3,
- 7,
- -59,
- 135,
- -115,
- -162,
- 703,
- -1119,
- 683,
- 1260,
- -4849,
- 10421,
- 24015,
- 4418,
- -4280,
- 2263,
- -360,
- -603,
- 669,
- -330,
- 32,
- 73,
- -52,
- 15,
- 4,
- 5,
- -57,
- 144,
- -147,
- -114,
- 678,
- -1192,
- 904,
- 958,
- -4769,
- 11661,
- 23678,
- 3317,
- -4007,
- 2354,
- -538,
- -483,
- 635,
- -347,
- 57,
- 60,
- -50,
- 15,
- 5,
- 2,
- -55,
- 151,
- -178,
- -61,
- 643,
- -1251,
- 1122,
- 628,
- -4615,
- 12891,
- 23234,
- 2267,
- -3694,
- 2409,
- -701,
- -361,
- 593,
- -357,
- 79,
- 46,
- -47,
- 15,
- 6,
- -2,
- -51,
- 157,
- -209,
- -4,
- 596,
- -1295,
- 1333,
- 271,
- -4383,
- 14104,
- 22686,
- 1274,
- -3348,
- 2428,
- -847,
- -240,
- 546,
- -362,
- 99,
- 33,
- -42,
- 15,
- 8,
- -6,
- -46,
- 161,
- -238,
- 56,
- 539,
- -1322,
- 1535,
- -108,
- -4072,
- 15289,
- 22039,
- 344,
- -2974,
- 2413,
- -975,
- -121,
- 493,
- -361,
- 116,
- 20,
- -38,
- 15,
- 9,
- -10,
- -39,
- 162,
- -265,
- 119,
- 471,
- -1332,
- 1725,
- -504,
- -3682,
- 16436,
- 21299,
- -517,
- -2580,
- 2366,
- -1085,
- -6,
- 435,
- -356,
- 131,
- 8,
- -33,
- 14,
- 10,
- -14,
- -32,
- 161,
- -290,
- 183,
- 392,
- -1322,
- 1897,
- -914,
- -3208,
- 17537,
- 20471,
- -1306,
- -2171,
- 2288,
- -1174,
- 103,
- 375,
- -346,
- 142,
- -3,
- -28,
- 13,
- 11,
- -19,
- -24,
- 159,
- -312,
- 247,
- 305,
- -1293,
- 2051,
- -1332,
- -2653,
- 18582,
- 19563,
- -2019,
- -1752,
- 2182,
- -1244,
- 208,
- 312,
- -331,
- 151,
- -14,
- -23,
- 12,
- 12,
- -23,
- -14,
- 151,
- -331,
- 312,
- 208,
- -1244,
- 2182,
- -1752,
- -2019,
- 19563,
- 18582,
- -2653,
- -1332,
- 2051,
- -1293,
- 305,
- 247,
- -312,
- 159,
- -24,
- -19,
- 11,
- 13,
- -28,
- -3,
- 142,
- -346,
- 375,
- 103,
- -1174,
- 2288,
- -2171,
- -1306,
- 20471,
- 17537,
- -3208,
- -914,
- 1897,
- -1322,
- 392,
- 183,
- -290,
- 161,
- -32,
- -14,
- 10,
- 14,
- -33,
- 8,
- 131,
- -356,
- 435,
- -6,
- -1085,
- 2366,
- -2580,
- -517,
- 21299,
- 16436,
- -3682,
- -504,
- 1725,
- -1332,
- 471,
- 119,
- -265,
- 162,
- -39,
- -10,
- 9,
- 15,
- -38,
- 20,
- 116,
- -361,
- 493,
- -121,
- -975,
- 2413,
- -2974,
- 344,
- 22039,
- 15289,
- -4072,
- -108,
- 1535,
- -1322,
- 539,
- 56,
- -238,
- 161,
- -46,
- -6,
- 8,
- 15,
- -42,
- 33,
- 99,
- -362,
- 546,
- -240,
- -847,
- 2428,
- -3348,
- 1274,
- 22686,
- 14104,
- -4383,
- 271,
- 1333,
- -1295,
- 596,
- -4,
- -209,
- 157,
- -51,
- -2,
- 6,
- 15,
- -47,
- 46,
- 79,
- -357,
- 593,
- -361,
- -701,
- 2409,
- -3694,
- 2267,
- 23234,
- 12891,
- -4615,
- 628,
- 1122,
- -1251,
- 643,
- -61,
- -178,
- 151,
- -55,
- 2,
- 5,
- 15,
- -50,
- 60,
- 57,
- -347,
- 635,
- -483,
- -538,
- 2354,
- -4007,
- 3317,
- 23678,
- 11661,
- -4769,
- 958,
- 904,
- -1192,
- 678,
- -114,
- -147,
- 144,
- -57,
- 5,
- 4,
- 15,
- -52,
- 73,
- 32,
- -330,
- 669,
- -603,
- -360,
- 2263,
- -4280,
- 4418,
- 24015,
- 10421,
- -4849,
- 1260,
- 683,
- -1119,
- 703,
- -162,
- -115,
- 135,
- -59,
- 7,
- 3,
- 14,
- -56,
- 87,
- 5,
- -308,
- 695,
- -720,
- -168,
- 2135,
- -4508,
- 5563,
- 24241,
- 9182,
- -4859,
- 1531,
- 463,
- -1033,
- 716,
- -208,
- -84,
- 124,
- -60,
- 10,
- 2,
- 13,
- -58,
- 100,
- -23,
- -280,
- 713,
- -832,
- 34,
- 1969,
- -4683,
- 6745,
- 24354,
- 7954,
- -4802,
- 1768,
- 246,
- -937,
- 719,
- -247,
- -53,
- 112,
- -59,
- 12,
- 1
-
-};
-struct src_stage src_int16_20_21_3015_5000 = {
- 1, 1, 20, 24, 480, 21, 20, 0, 0,
- src_int16_20_21_3015_5000_fir};
diff --git a/src/include/sof/audio/coefficients/src/src_tiny_int16_21_20_3015_5000.h b/src/include/sof/audio/coefficients/src/src_tiny_int16_21_20_3015_5000.h
deleted file mode 100644
index fe2a56f..0000000
--- a/src/include/sof/audio/coefficients/src/src_tiny_int16_21_20_3015_5000.h
+++ /dev/null
@@ -1,510 +0,0 @@
-const int16_t src_int16_21_20_3015_5000_fir[504] = {
- -4,
- 22,
- -36,
- -5,
- 166,
- -433,
- 628,
- -403,
- -586,
- 2425,
- -4775,
- 7097,
- 25571,
- 5855,
- -4536,
- 2524,
- -765,
- -268,
- 568,
- -428,
- 181,
- -19,
- -29,
- 20,
- -6,
- 24,
- -44,
- 11,
- 147,
- -433,
- 681,
- -538,
- -392,
- 2286,
- -4959,
- 8367,
- 25452,
- 4651,
- -4247,
- 2585,
- -925,
- -136,
- 502,
- -416,
- 193,
- -33,
- -22,
- 18,
- -5,
- 25,
- -50,
- 27,
- 124,
- -426,
- 728,
- -671,
- -183,
- 2106,
- -5082,
- 9658,
- 25216,
- 3493,
- -3918,
- 2607,
- -1066,
- -7,
- 433,
- -399,
- 202,
- -45,
- -17,
- 16,
- -5,
- 26,
- -57,
- 44,
- 99,
- -413,
- 765,
- -800,
- 37,
- 1890,
- -5141,
- 10959,
- 24863,
- 2387,
- -3553,
- 2593,
- -1187,
- 117,
- 361,
- -378,
- 207,
- -55,
- -9,
- 14,
- -4,
- 27,
- -64,
- 62,
- 71,
- -392,
- 794,
- -923,
- 267,
- 1636,
- -5129,
- 12260,
- 24398,
- 1342,
- -3158,
- 2544,
- -1286,
- 234,
- 287,
- -352,
- 209,
- -64,
- -3,
- 12,
- -4,
- 28,
- -69,
- 80,
- 40,
- -366,
- 812,
- -1039,
- 502,
- 1346,
- -5042,
- 13552,
- 23825,
- 363,
- -2740,
- 2462,
- -1364,
- 343,
- 212,
- -323,
- 208,
- -72,
- 3,
- 9,
- -4,
- 28,
- -75,
- 98,
- 7,
- -332,
- 819,
- -1144,
- 741,
- 1023,
- -4876,
- 14825,
- 23146,
- -545,
- -2308,
- 2350,
- -1419,
- 442,
- 138,
- -290,
- 204,
- -79,
- 8,
- 6,
- -3,
- 27,
- -79,
- 116,
- -29,
- -291,
- 815,
- -1237,
- 979,
- 669,
- -4630,
- 16068,
- 22369,
- -1377,
- -1863,
- 2211,
- -1452,
- 531,
- 66,
- -255,
- 197,
- -82,
- 12,
- 5,
- -2,
- 26,
- -82,
- 132,
- -67,
- -245,
- 798,
- -1317,
- 1214,
- 289,
- -4300,
- 17271,
- 21502,
- -2129,
- -1417,
- 2047,
- -1464,
- 608,
- -5,
- -218,
- 188,
- -85,
- 16,
- 4,
- -1,
- 24,
- -85,
- 148,
- -104,
- -192,
- 769,
- -1381,
- 1442,
- -115,
- -3884,
- 18426,
- 20550,
- -2799,
- -973,
- 1863,
- -1456,
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- -72,
- -181,
- 176,
- -86,
- 19,
- 2,
- 1,
- 23,
- -86,
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- -142,
- -134,
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- -1428,
- 1659,
- -537,
- -3385,
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- 19522,
- -3385,
- -537,
- 1659,
- -1428,
- 728,
- -134,
- -142,
- 163,
- -86,
- 23,
- 1,
- 2,
- 19,
- -86,
- 176,
- -181,
- -72,
- 674,
- -1456,
- 1863,
- -973,
- -2799,
- 20550,
- 18426,
- -3884,
- -115,
- 1442,
- -1381,
- 769,
- -192,
- -104,
- 148,
- -85,
- 24,
- -1,
- 4,
- 16,
- -85,
- 188,
- -218,
- -5,
- 608,
- -1464,
- 2047,
- -1417,
- -2129,
- 21502,
- 17270,
- -4300,
- 289,
- 1214,
- -1317,
- 798,
- -245,
- -67,
- 132,
- -82,
- 26,
- -2,
- 5,
- 12,
- -82,
- 197,
- -255,
- 66,
- 531,
- -1452,
- 2211,
- -1863,
- -1377,
- 22369,
- 16068,
- -4630,
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- 979,
- -1237,
- 815,
- -291,
- -29,
- 116,
- -79,
- 27,
- -3,
- 6,
- 8,
- -79,
- 204,
- -290,
- 138,
- 442,
- -1419,
- 2350,
- -2307,
- -545,
- 23146,
- 14825,
- -4876,
- 1023,
- 741,
- -1144,
- 819,
- -332,
- 7,
- 98,
- -75,
- 28,
- -4,
- 9,
- 3,
- -72,
- 208,
- -323,
- 212,
- 343,
- -1364,
- 2462,
- -2740,
- 363,
- 23825,
- 13552,
- -5042,
- 1346,
- 502,
- -1039,
- 812,
- -366,
- 40,
- 80,
- -69,
- 28,
- -4,
- 12,
- -3,
- -64,
- 209,
- -352,
- 287,
- 234,
- -1286,
- 2544,
- -3158,
- 1342,
- 24398,
- 12260,
- -5129,
- 1636,
- 267,
- -923,
- 794,
- -392,
- 71,
- 62,
- -64,
- 27,
- -4,
- 14,
- -9,
- -55,
- 207,
- -378,
- 361,
- 117,
- -1187,
- 2593,
- -3553,
- 2387,
- 24863,
- 10959,
- -5141,
- 1890,
- 37,
- -800,
- 765,
- -413,
- 99,
- 44,
- -57,
- 26,
- -5,
- 16,
- -17,
- -45,
- 202,
- -399,
- 433,
- -7,
- -1066,
- 2607,
- -3918,
- 3493,
- 25215,
- 9658,
- -5084,
- 2106,
- -183,
- -671,
- 728,
- -426,
- 124,
- 27,
- -50,
- 25,
- -5,
- 18,
- -22,
- -33,
- 193,
- -416,
- 502,
- -136,
- -925,
- 2585,
- -4248,
- 4651,
- 25452,
- 8367,
- -4959,
- 2286,
- -392,
- -538,
- 681,
- -433,
- 147,
- 11,
- -44,
- 24,
- -6,
- 20,
- -29,
- -19,
- 181,
- -428,
- 568,
- -268,
- -765,
- 2524,
- -4536,
- 5855,
- 25571,
- 7097,
- -4775,
- 2425,
- -586,
- -403,
- 628,
- -433,
- 166,
- -5,
- -36,
- 22,
- -4
-
-};
-struct src_stage src_int16_21_20_3015_5000 = {
- 19, 20, 21, 24, 504, 20, 21, 0, 0,
- src_int16_21_20_3015_5000_fir};
diff --git a/src/include/sof/audio/coefficients/src/src_tiny_int16_2_1_3281_5000.h b/src/include/sof/audio/coefficients/src/src_tiny_int16_2_1_3281_5000.h
deleted file mode 100644
index 5ebc376..0000000
--- a/src/include/sof/audio/coefficients/src/src_tiny_int16_2_1_3281_5000.h
+++ /dev/null
@@ -1,70 +0,0 @@
-const int16_t src_int16_2_1_3281_5000_fir[64] = {
- 1,
- 8,
- -31,
- 67,
- -92,
- 67,
- 49,
- -278,
- 576,
- -825,
- 834,
- -387,
- -706,
- 2599,
- -5651,
- 12843,
- 25187,
- -839,
- -1866,
- 2345,
- -1948,
- 1215,
- -494,
- -23,
- 276,
- -314,
- 230,
- -118,
- 33,
- 9,
- -16,
- 9,
- 9,
- -16,
- 9,
- 33,
- -118,
- 230,
- -314,
- 276,
- -23,
- -494,
- 1215,
- -1948,
- 2345,
- -1866,
- -839,
- 25187,
- 12843,
- -5651,
- 2599,
- -706,
- -387,
- 834,
- -825,
- 576,
- -278,
- 49,
- 67,
- -92,
- 67,
- -31,
- 8,
- 1
-
-};
-struct src_stage src_int16_2_1_3281_5000 = {
- 0, 1, 2, 32, 64, 1, 2, 0, 0,
- src_int16_2_1_3281_5000_fir};
diff --git a/src/include/sof/audio/coefficients/src/src_tiny_int16_2_3_3281_5000.h b/src/include/sof/audio/coefficients/src/src_tiny_int16_2_3_3281_5000.h
deleted file mode 100644
index 3b09530..0000000
--- a/src/include/sof/audio/coefficients/src/src_tiny_int16_2_3_3281_5000.h
+++ /dev/null
@@ -1,94 +0,0 @@
-const int16_t src_int16_2_3_3281_5000_fir[88] = {
- -1,
- -8,
- 7,
- 24,
- -30,
- -42,
- 86,
- 49,
- -185,
- -11,
- 330,
- -115,
- -503,
- 389,
- 659,
- -890,
- -713,
- 1770,
- 498,
- -3604,
- 682,
- 13333,
- 17459,
- 6863,
- -3045,
- -1848,
- 1900,
- 568,
- -1259,
- -36,
- 788,
- -172,
- -443,
- 212,
- 212,
- -173,
- -78,
- 110,
- 16,
- -55,
- 5,
- 21,
- -5,
- -5,
- -5,
- -5,
- 21,
- 5,
- -55,
- 16,
- 110,
- -78,
- -173,
- 212,
- 212,
- -443,
- -172,
- 788,
- -36,
- -1259,
- 568,
- 1900,
- -1849,
- -3045,
- 6862,
- 17459,
- 13333,
- 682,
- -3603,
- 498,
- 1770,
- -713,
- -890,
- 659,
- 389,
- -503,
- -115,
- 330,
- -12,
- -185,
- 49,
- 86,
- -42,
- -30,
- 24,
- 7,
- -8,
- -1
-
-};
-struct src_stage src_int16_2_3_3281_5000 = {
- 1, 1, 2, 44, 88, 3, 2, 0, 0,
- src_int16_2_3_3281_5000_fir};
diff --git a/src/include/sof/audio/coefficients/src/src_tiny_int16_3_1_1641_5000.h b/src/include/sof/audio/coefficients/src/src_tiny_int16_3_1_1641_5000.h
deleted file mode 100644
index f0b58a4..0000000
--- a/src/include/sof/audio/coefficients/src/src_tiny_int16_3_1_1641_5000.h
+++ /dev/null
@@ -1,54 +0,0 @@
-const int16_t src_int16_3_1_1641_5000_fir[48] = {
- -5,
- 72,
- -102,
- -333,
- 1223,
- -937,
- -2957,
- 11926,
- 21201,
- 5489,
- -3691,
- 562,
- 675,
- -422,
- 39,
- 32,
- 4,
- 89,
- -294,
- 59,
- 1292,
- -2672,
- 162,
- 17745,
- 17745,
- 162,
- -2672,
- 1292,
- 59,
- -294,
- 89,
- 4,
- 32,
- 39,
- -422,
- 675,
- 562,
- -3691,
- 5489,
- 21201,
- 11926,
- -2957,
- -937,
- 1223,
- -333,
- -102,
- 72,
- -5
-
-};
-struct src_stage src_int16_3_1_1641_5000 = {
- 0, 1, 3, 16, 48, 1, 3, 0, 0,
- src_int16_3_1_1641_5000_fir};
diff --git a/src/include/sof/audio/coefficients/src/src_tiny_int16_3_1_3281_5000.h b/src/include/sof/audio/coefficients/src/src_tiny_int16_3_1_3281_5000.h
deleted file mode 100644
index 93971b2..0000000
--- a/src/include/sof/audio/coefficients/src/src_tiny_int16_3_1_3281_5000.h
+++ /dev/null
@@ -1,102 +0,0 @@
-const int16_t src_int16_3_1_3281_5000_fir[96] = {
- 0,
- 11,
- -33,
- 63,
- -76,
- 35,
- 98,
- -324,
- 587,
- -752,
- 637,
- -58,
- -1109,
- 2907,
- -5450,
- 10312,
- 26192,
- 1027,
- -2805,
- 2722,
- -1972,
- 1057,
- -285,
- -198,
- 384,
- -355,
- 228,
- -97,
- 12,
- 23,
- -22,
- 12,
- 6,
- -2,
- -18,
- 66,
- -132,
- 183,
- -154,
- -20,
- 371,
- -844,
- 1277,
- -1405,
- 879,
- 759,
- -4593,
- 20013,
- 20013,
- -4593,
- 759,
- 879,
- -1405,
- 1277,
- -844,
- 371,
- -20,
- -154,
- 183,
- -132,
- 66,
- -18,
- -2,
- 6,
- 12,
- -22,
- 23,
- 12,
- -97,
- 228,
- -355,
- 384,
- -198,
- -285,
- 1057,
- -1972,
- 2722,
- -2805,
- 1027,
- 26192,
- 10312,
- -5450,
- 2907,
- -1109,
- -58,
- 637,
- -752,
- 587,
- -324,
- 98,
- 35,
- -76,
- 63,
- -33,
- 11,
- 0
-
-};
-struct src_stage src_int16_3_1_3281_5000 = {
- 0, 1, 3, 32, 96, 1, 3, 0, 0,
- src_int16_3_1_3281_5000_fir};
diff --git a/src/include/sof/audio/coefficients/src/src_tiny_int16_3_2_3281_5000.h b/src/include/sof/audio/coefficients/src/src_tiny_int16_3_2_3281_5000.h
deleted file mode 100644
index fc75ee8..0000000
--- a/src/include/sof/audio/coefficients/src/src_tiny_int16_3_2_3281_5000.h
+++ /dev/null
@@ -1,102 +0,0 @@
-const int16_t src_int16_3_2_3281_5000_fir[96] = {
- 0,
- 11,
- -33,
- 63,
- -76,
- 34,
- 98,
- -325,
- 587,
- -753,
- 638,
- -57,
- -1109,
- 2906,
- -5450,
- 10312,
- 26192,
- 1027,
- -2805,
- 2722,
- -1972,
- 1057,
- -284,
- -198,
- 384,
- -356,
- 229,
- -98,
- 11,
- 22,
- -22,
- 11,
- 4,
- -2,
- -19,
- 66,
- -133,
- 184,
- -155,
- -21,
- 371,
- -844,
- 1277,
- -1404,
- 879,
- 758,
- -4593,
- 20013,
- 20013,
- -4593,
- 758,
- 879,
- -1404,
- 1277,
- -844,
- 371,
- -21,
- -155,
- 184,
- -133,
- 66,
- -19,
- -2,
- 4,
- 11,
- -22,
- 22,
- 11,
- -98,
- 229,
- -356,
- 384,
- -198,
- -284,
- 1057,
- -1972,
- 2722,
- -2805,
- 1027,
- 26192,
- 10312,
- -5450,
- 2906,
- -1109,
- -57,
- 638,
- -753,
- 587,
- -325,
- 98,
- 34,
- -76,
- 63,
- -33,
- 11,
- 0
-
-};
-struct src_stage src_int16_3_2_3281_5000 = {
- 1, 2, 3, 32, 96, 2, 3, 0, 0,
- src_int16_3_2_3281_5000_fir};
diff --git a/src/include/sof/audio/coefficients/src/src_tiny_int16_7_8_3281_5000.h b/src/include/sof/audio/coefficients/src/src_tiny_int16_7_8_3281_5000.h
deleted file mode 100644
index d926a4b..0000000
--- a/src/include/sof/audio/coefficients/src/src_tiny_int16_7_8_3281_5000.h
+++ /dev/null
@@ -1,230 +0,0 @@
-const int16_t src_int16_7_8_3281_5000_fir[224] = {
- -4,
- 12,
- -1,
- -51,
- 110,
- -85,
- -107,
- 390,
- -480,
- 69,
- 811,
- -1551,
- 1176,
- 1010,
- -4828,
- 9624,
- 23409,
- 6367,
- -4772,
- 1812,
- 504,
- -1348,
- 972,
- -183,
- -334,
- 385,
- -172,
- -28,
- 91,
- -56,
- 10,
- 6,
- -6,
- 17,
- -12,
- -38,
- 120,
- -141,
- -22,
- 351,
- -587,
- 338,
- 546,
- -1604,
- 1790,
- -4,
- -4346,
- 12905,
- 22595,
- 3311,
- -4261,
- 2348,
- -155,
- -1029,
- 1021,
- -393,
- -169,
- 342,
- -212,
- 24,
- 65,
- -55,
- 18,
- 2,
- -4,
- 20,
- -26,
- -18,
- 117,
- -186,
- 75,
- 269,
- -639,
- 596,
- 195,
- -1485,
- 2273,
- -1151,
- -3277,
- 16019,
- 21018,
- 610,
- -3405,
- 2595,
- -737,
- -635,
- 963,
- -545,
- -2,
- 270,
- -226,
- 68,
- 36,
- -48,
- 21,
- -2,
- -4,
- 22,
- -39,
- 7,
- 99,
- -217,
- 176,
- 149,
- -628,
- 814,
- -212,
- -1191,
- 2559,
- -2325,
- -1613,
- 18780,
- 18780,
- -1613,
- -2325,
- 2559,
- -1191,
- -212,
- 814,
- -628,
- 149,
- 176,
- -216,
- 99,
- 7,
- -39,
- 22,
- -4,
- -2,
- 21,
- -48,
- 36,
- 68,
- -226,
- 269,
- -2,
- -545,
- 963,
- -635,
- -737,
- 2595,
- -3404,
- 610,
- 21018,
- 16019,
- -3277,
- -1151,
- 2273,
- -1485,
- 195,
- 596,
- -639,
- 270,
- 75,
- -186,
- 117,
- -18,
- -26,
- 20,
- -4,
- 2,
- 18,
- -55,
- 65,
- 24,
- -212,
- 342,
- -169,
- -393,
- 1021,
- -1029,
- -155,
- 2348,
- -4260,
- 3311,
- 22595,
- 12905,
- -4346,
- -5,
- 1790,
- -1604,
- 546,
- 338,
- -587,
- 351,
- -22,
- -141,
- 120,
- -38,
- -12,
- 17,
- -6,
- 6,
- 10,
- -56,
- 91,
- -28,
- -173,
- 385,
- -334,
- -183,
- 972,
- -1348,
- 504,
- 1812,
- -4771,
- 6367,
- 23409,
- 9625,
- -4828,
- 1010,
- 1176,
- -1551,
- 811,
- 69,
- -480,
- 390,
- -107,
- -85,
- 110,
- -51,
- -1,
- 12,
- -4
-
-};
-struct src_stage src_int16_7_8_3281_5000 = {
- 1, 1, 7, 32, 224, 8, 7, 0, 0,
- src_int16_7_8_3281_5000_fir};
diff --git a/src/include/sof/audio/coefficients/src/src_tiny_int16_8_7_3281_5000.h b/src/include/sof/audio/coefficients/src/src_tiny_int16_8_7_3281_5000.h
deleted file mode 100644
index baf6bcf..0000000
--- a/src/include/sof/audio/coefficients/src/src_tiny_int16_8_7_3281_5000.h
+++ /dev/null
@@ -1,230 +0,0 @@
-const int16_t src_int16_8_7_3281_5000_fir[224] = {
- -5,
- 19,
- -29,
- 8,
- 78,
- -242,
- 440,
- -548,
- 386,
- 223,
- -1361,
- 2965,
- -4869,
- 7277,
- 26753,
- 3784,
- -3890,
- 2924,
- -1697,
- 624,
- 78,
- -382,
- 391,
- -259,
- 114,
- -21,
- -14,
- 14,
- -6,
- 23,
- -44,
- 41,
- 28,
- -196,
- 445,
- -671,
- 681,
- -242,
- -842,
- 2683,
- -5453,
- 11000,
- 25822,
- 697,
- -2657,
- 2598,
- -1834,
- 927,
- -209,
- -193,
- 307,
- -247,
- 134,
- -43,
- 0,
- 8,
- -5,
- 25,
- -56,
- 74,
- -32,
- -122,
- 401,
- -732,
- 930,
- -725,
- -177,
- 2070,
- -5518,
- 14749,
- 24021,
- -1844,
- -1316,
- 2046,
- -1773,
- 1111,
- -449,
- -3,
- 201,
- -212,
- 137,
- -58,
- 11,
- 3,
- -4,
- 24,
- -63,
- 104,
- -97,
- -25,
- 308,
- -718,
- 1101,
- -1176,
- 575,
- 1154,
- -4967,
- 18308,
- 21463,
- -3745,
- -6,
- 1344,
- -1541,
- 1167,
- -623,
- 170,
- 86,
- -160,
- 126,
- -65,
- 19,
- 0,
- 0,
- 19,
- -64,
- 126,
- -160,
- 86,
- 170,
- -623,
- 1167,
- -1541,
- 1344,
- -6,
- -3745,
- 21463,
- 18308,
- -4967,
- 1154,
- 575,
- -1176,
- 1101,
- -718,
- 308,
- -25,
- -97,
- 104,
- -63,
- 24,
- -4,
- 3,
- 11,
- -58,
- 137,
- -212,
- 201,
- -3,
- -449,
- 1111,
- -1773,
- 2046,
- -1316,
- -1844,
- 24021,
- 14749,
- -5518,
- 2070,
- -178,
- -725,
- 930,
- -732,
- 401,
- -122,
- -32,
- 74,
- -56,
- 25,
- -5,
- 8,
- 0,
- -43,
- 134,
- -247,
- 307,
- -193,
- -209,
- 927,
- -1834,
- 2598,
- -2657,
- 697,
- 25822,
- 11000,
- -5453,
- 2683,
- -842,
- -242,
- 681,
- -671,
- 445,
- -196,
- 28,
- 41,
- -44,
- 23,
- -6,
- 14,
- -14,
- -21,
- 114,
- -259,
- 391,
- -382,
- 78,
- 624,
- -1697,
- 2924,
- -3890,
- 3784,
- 26753,
- 7277,
- -4869,
- 2965,
- -1361,
- 223,
- 386,
- -548,
- 440,
- -242,
- 78,
- 8,
- -29,
- 19,
- -5
-
-};
-struct src_stage src_int16_8_7_3281_5000 = {
- 6, 7, 8, 28, 224, 7, 8, 0, 0,
- src_int16_8_7_3281_5000_fir};
diff --git a/src/include/sof/audio/coefficients/src/src_tiny_int16_define.h b/src/include/sof/audio/coefficients/src/src_tiny_int16_define.h
deleted file mode 100644
index dd8d4e3..0000000
--- a/src/include/sof/audio/coefficients/src/src_tiny_int16_define.h
+++ /dev/null
@@ -1,11 +0,0 @@
-/* SRC constants */
-#define MAX_FIR_DELAY_SIZE 424
-#define MAX_OUT_DELAY_SIZE 401
-#define MAX_BLK_IN 21
-#define MAX_BLK_OUT 21
-#define NUM_IN_FS 6
-#define NUM_OUT_FS 6
-#define STAGE1_TIMES_MAX 21
-#define STAGE2_TIMES_MAX 21
-#define STAGE_BUF_SIZE 168
-#define NUM_ALL_COEFFICIENTS 2020
diff --git a/src/include/sof/audio/coefficients/src/src_tiny_int16_table.h b/src/include/sof/audio/coefficients/src/src_tiny_int16_table.h
deleted file mode 100644
index 63eddae..0000000
--- a/src/include/sof/audio/coefficients/src/src_tiny_int16_table.h
+++ /dev/null
@@ -1,72 +0,0 @@
-/* SRC conversions */
-#include <sof/audio/coefficients/src/src_tiny_int16_1_2_3281_5000.h>
-#include <sof/audio/coefficients/src/src_tiny_int16_1_3_1641_5000.h>
-#include <sof/audio/coefficients/src/src_tiny_int16_1_3_3281_5000.h>
-#include <sof/audio/coefficients/src/src_tiny_int16_2_1_3281_5000.h>
-#include <sof/audio/coefficients/src/src_tiny_int16_2_3_3281_5000.h>
-#include <sof/audio/coefficients/src/src_tiny_int16_3_1_1641_5000.h>
-#include <sof/audio/coefficients/src/src_tiny_int16_3_1_3281_5000.h>
-#include <sof/audio/coefficients/src/src_tiny_int16_3_2_3281_5000.h>
-#include <sof/audio/coefficients/src/src_tiny_int16_7_8_3281_5000.h>
-#include <sof/audio/coefficients/src/src_tiny_int16_8_7_3281_5000.h>
-#include <sof/audio/coefficients/src/src_tiny_int16_20_21_3015_5000.h>
-#include <sof/audio/coefficients/src/src_tiny_int16_21_20_3015_5000.h>
-
-/* SRC table */
-int16_t fir_one = 16384;
-struct src_stage src_int16_1_1_0_0 = { 0, 0, 1, 1, 1, 1, 1, 0, -1, &fir_one };
-struct src_stage src_int16_0_0_0_0 = { 0, 0, 0, 0, 0, 0, 0, 0, 0, &fir_one };
-int src_in_fs[6] = { 8000, 16000, 24000, 32000, 44100, 48000};
-int src_out_fs[6] = { 8000, 16000, 24000, 32000, 44100, 48000};
-struct src_stage *src_table1[6][6] = {
- { &src_int16_1_1_0_0, &src_int16_0_0_0_0,
- &src_int16_0_0_0_0, &src_int16_0_0_0_0,
- &src_int16_0_0_0_0, &src_int16_1_3_1641_5000
- },
- { &src_int16_0_0_0_0, &src_int16_1_1_0_0,
- &src_int16_0_0_0_0, &src_int16_0_0_0_0,
- &src_int16_0_0_0_0, &src_int16_1_3_3281_5000
- },
- { &src_int16_0_0_0_0, &src_int16_0_0_0_0,
- &src_int16_1_1_0_0, &src_int16_0_0_0_0,
- &src_int16_0_0_0_0, &src_int16_1_2_3281_5000
- },
- { &src_int16_0_0_0_0, &src_int16_0_0_0_0,
- &src_int16_0_0_0_0, &src_int16_1_1_0_0,
- &src_int16_0_0_0_0, &src_int16_2_3_3281_5000
- },
- { &src_int16_0_0_0_0, &src_int16_0_0_0_0,
- &src_int16_0_0_0_0, &src_int16_0_0_0_0,
- &src_int16_1_1_0_0, &src_int16_21_20_3015_5000
- },
- { &src_int16_2_1_3281_5000, &src_int16_3_1_3281_5000,
- &src_int16_2_1_3281_5000, &src_int16_3_2_3281_5000,
- &src_int16_8_7_3281_5000, &src_int16_1_1_0_0
- }
-};
-struct src_stage *src_table2[6][6] = {
- { &src_int16_1_1_0_0, &src_int16_0_0_0_0,
- &src_int16_0_0_0_0, &src_int16_0_0_0_0,
- &src_int16_0_0_0_0, &src_int16_1_2_3281_5000
- },
- { &src_int16_0_0_0_0, &src_int16_1_1_0_0,
- &src_int16_0_0_0_0, &src_int16_0_0_0_0,
- &src_int16_0_0_0_0, &src_int16_1_1_0_0
- },
- { &src_int16_0_0_0_0, &src_int16_0_0_0_0,
- &src_int16_1_1_0_0, &src_int16_0_0_0_0,
- &src_int16_0_0_0_0, &src_int16_1_1_0_0
- },
- { &src_int16_0_0_0_0, &src_int16_0_0_0_0,
- &src_int16_0_0_0_0, &src_int16_1_1_0_0,
- &src_int16_0_0_0_0, &src_int16_1_1_0_0
- },
- { &src_int16_0_0_0_0, &src_int16_0_0_0_0,
- &src_int16_0_0_0_0, &src_int16_0_0_0_0,
- &src_int16_1_1_0_0, &src_int16_7_8_3281_5000
- },
- { &src_int16_3_1_1641_5000, &src_int16_1_1_0_0,
- &src_int16_1_1_0_0, &src_int16_1_1_0_0,
- &src_int16_20_21_3015_5000, &src_int16_1_1_0_0
- }
-};
diff --git a/src/include/sof/audio/component.h b/src/include/sof/audio/component.h
deleted file mode 100644
index 471332c..0000000
--- a/src/include/sof/audio/component.h
+++ /dev/null
@@ -1,400 +0,0 @@
-/*
- * Copyright (c) 2016, Intel Corporation
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- * * Redistributions of source code must retain the above copyright
- * notice, this list of conditions and the following disclaimer.
- * * Redistributions in binary form must reproduce the above copyright
- * notice, this list of conditions and the following disclaimer in the
- * documentation and/or other materials provided with the distribution.
- * * Neither the name of the Intel Corporation nor the
- * names of its contributors may be used to endorse or promote products
- * derived from this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
- * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
- * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
- * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
- * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
- * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
- * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
- * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
- * POSSIBILITY OF SUCH DAMAGE.
- *
- * Author: Liam Girdwood <liam.r.girdwood@linux.intel.com>
- * Keyon Jie <yang.jie@linux.intel.com>
- */
-
-#ifndef __INCLUDE_AUDIO_COMPONENT_H__
-#define __INCLUDE_AUDIO_COMPONENT_H__
-
-#include <stdint.h>
-#include <stddef.h>
-#include <sof/lock.h>
-#include <sof/list.h>
-#include <sof/sof.h>
-#include <sof/alloc.h>
-#include <sof/dma.h>
-#include <sof/stream.h>
-#include <sof/audio/buffer.h>
-#include <sof/audio/pipeline.h>
-#include <uapi/ipc.h>
-
-/*
- * Audio Component States
- *
- * States may transform as below:-
- *
- *
- * -------------
- * pause | | stop/xrun
- * +-------------| ACTIVITY |---------------+
- * | | | | prepare
- * | ------------- | +-----------+
- * | ^ ^ | | |
- * | | | | | |
- * v | | v | |
- * ------------- | | ------------- |
- * | | release | | start | | |
- * | PAUSED |-----------+ +-------------| PREPARE |<-------+
- * | | | |
- * ------------- -------------
- * | ^ ^
- * | stop/xrun | |
- * +--------------------------------------+ |
- * | prepare
- * ------------- |
- * | | |
- * ----------->| READY |------------------+
- * reset | |
- * -------------
- *
- *
- */
-
-#define COMP_STATE_INIT 0 /* component being initialised */
-#define COMP_STATE_READY 1 /* component inactive, but ready */
-#define COMP_STATE_SUSPEND 2 /* component suspended */
-#define COMP_STATE_PREPARE 3 /* component prepared */
-#define COMP_STATE_PAUSED 4 /* component paused */
-#define COMP_STATE_ACTIVE 5 /* component active */
-
-/*
- * standard component stream commands
- * TODO: use IPC versions after 1.1
- */
-
-#define COMP_TRIGGER_STOP 0 /* stop component stream */
-#define COMP_TRIGGER_START 1 /* start component stream */
-#define COMP_TRIGGER_PAUSE 2 /* pause the component stream */
-#define COMP_TRIGGER_RELEASE 3 /* release paused component stream */
-#define COMP_TRIGGER_SUSPEND 4 /* suspend component */
-#define COMP_TRIGGER_RESUME 5 /* resume component */
-#define COMP_TRIGGER_RESET 6 /* reset component */
-#define COMP_TRIGGER_PREPARE 7 /* prepare component */
-#define COMP_TRIGGER_XRUN 8 /* XRUN component */
-
-/*
- * standard component control commands
- */
-
-#define COMP_CMD_SET_VALUE 100
-#define COMP_CMD_GET_VALUE 101
-#define COMP_CMD_SET_DATA 102
-#define COMP_CMD_GET_DATA 103
-
-
-/* MMAP IPC status */
-#define COMP_CMD_IPC_MMAP_RPOS 200 /* host read position */
-#define COMP_CMD_IPC_MMAP_PPOS 201 /* DAI presentation position */
-
-#define COMP_CMD_IPC_MMAP_VOL(chan) (216 + chan) /* Volume */
-
-/* component operations */
-#define COMP_OPS_PARAMS 0
-#define COMP_OPS_TRIGGER 1
-#define COMP_OPS_PREPARE 2
-#define COMP_OPS_COPY 3
-#define COMP_OPS_BUFFER 4
-#define COMP_OPS_RESET 5
-
-#define trace_comp(__e) trace_event(TRACE_CLASS_COMP, __e)
-#define trace_comp_error(__e) trace_error(TRACE_CLASS_COMP, __e)
-#define tracev_comp(__e) tracev_event(TRACE_CLASS_COMP, __e)
-
-struct comp_dev;
-struct comp_buffer;
-struct dai_config;
-struct pipeline;
-
-/*
- * Audio component operations - all mandatory.
- *
- * All component operations must return 0 for success, negative values for
- * errors and 1 to stop the pipeline walk operation.
- */
-struct comp_ops {
- /* component creation and destruction */
- struct comp_dev *(*new)(struct sof_ipc_comp *comp);
- void (*free)(struct comp_dev *dev);
-
- /* set component audio stream parameters */
- int (*params)(struct comp_dev *dev);
-
- /* set component audio stream parameters */
- int (*dai_config)(struct comp_dev *dev,
- struct sof_ipc_dai_config *dai_config);
-
- /* used to pass standard and bespoke commands (with optional data) */
- int (*cmd)(struct comp_dev *dev, int cmd, void *data);
-
- /* atomic - used to start/stop/pause stream operations */
- int (*trigger)(struct comp_dev *dev, int cmd);
-
- /* prepare component after params are set */
- int (*prepare)(struct comp_dev *dev);
-
- /* reset component */
- int (*reset)(struct comp_dev *dev);
-
- /* copy and process stream data from source to sink buffers */
- int (*copy)(struct comp_dev *dev);
-
- /* host buffer config */
- int (*host_buffer)(struct comp_dev *dev, struct dma_sg_elem *elem,
- uint32_t host_size);
-
- /* position */
- int (*position)(struct comp_dev *dev,
- struct sof_ipc_stream_posn *posn);
-};
-
-
-/* audio component base driver "class" - used by all other component types */
-struct comp_driver {
- uint32_t type; /* SOF_COMP_ for driver */
- uint32_t module_id;
-
- struct comp_ops ops; /* component operations */
-
- struct list_item list; /* list of component drivers */
-};
-
-/* audio component base device "class" - used by other component types */
-struct comp_dev {
-
- /* runtime */
- uint16_t state; /* COMP_STATE_ */
- uint16_t is_endpoint; /* component is end point in pipeline */
- uint16_t is_dma_connected; /* component is connected to DMA */
- spinlock_t lock; /* lock for this component */
- uint64_t position; /* component rendering position */
- uint32_t frames; /* number of frames we copy to sink */
- uint32_t frame_bytes; /* frames size copied to sink in bytes */
- struct pipeline *pipeline; /* pipeline we belong to */
-
- /* common runtime configuration for downstream/upstream */
- struct sof_ipc_stream_params params;
-
- /* driver */
- struct comp_driver *drv;
-
- /* lists */
- struct list_item bsource_list; /* list of source buffers */
- struct list_item bsink_list; /* list of sink buffers */
-
- /* private data - core does not touch this */
- void *private; /* private data */
-
- /* IPC config object header - MUST be at end as it's variable size/type */
- struct sof_ipc_comp comp;
-};
-
-#define COMP_SIZE(x) \
- (sizeof(struct comp_dev) - sizeof(struct sof_ipc_comp) + sizeof(x))
-#define COMP_GET_IPC(dev, type) \
- (struct type *)(&dev->comp)
-#define COMP_GET_PARAMS(dev) \
- (struct type *)(&dev->params)
-#define COMP_GET_CONFIG(dev) \
- (struct sof_ipc_comp_config *)((void*)&dev->comp + sizeof(struct sof_ipc_comp))
-
-#define comp_set_drvdata(c, data) \
- c->private = data
-#define comp_get_drvdata(c) \
- c->private;
-
-void sys_comp_init(void);
-
-/* component registration */
-int comp_register(struct comp_driver *drv);
-void comp_unregister(struct comp_driver *drv);
-
-/* component creation and destruction - mandatory */
-struct comp_dev *comp_new(struct sof_ipc_comp *comp);
-static inline void comp_free(struct comp_dev *dev)
-{
- dev->drv->ops.free(dev);
-}
-
-/* component state set */
-int comp_set_state(struct comp_dev *dev, int cmd);
-
-/* component parameter init - mandatory */
-static inline int comp_params(struct comp_dev *dev)
-{
- return dev->drv->ops.params(dev);
-}
-
-/* component host buffer config
- * mandatory for host components, optional for the others.
- */
-static inline int comp_host_buffer(struct comp_dev *dev,
- struct dma_sg_elem *elem, uint32_t host_size)
-{
- if (dev->drv->ops.host_buffer)
- return dev->drv->ops.host_buffer(dev, elem, host_size);
- return 0;
-}
-
-/* send component command - mandatory */
-static inline int comp_cmd(struct comp_dev *dev, int cmd, void *data)
-{
- struct sof_ipc_ctrl_data *cdata = data;
-
- if ((cmd == COMP_CMD_SET_DATA)
- && ((cdata->data->magic != SOF_ABI_MAGIC)
- || (cdata->data->abi != SOF_ABI_VERSION))) {
- trace_comp_error("abi");
- trace_error_value(cdata->data->magic);
- trace_error_value(cdata->data->abi);
- return -EINVAL;
- }
-
- return dev->drv->ops.cmd(dev, cmd, data);
-}
-
-/* trigger component - mandatory and atomic */
-static inline int comp_trigger(struct comp_dev *dev, int cmd)
-{
- return dev->drv->ops.trigger(dev, cmd);
-}
-
-/* prepare component - mandatory */
-static inline int comp_prepare(struct comp_dev *dev)
-{
- return dev->drv->ops.prepare(dev);
-}
-
-/* copy component buffers - mandatory */
-static inline int comp_copy(struct comp_dev *dev)
-{
- return dev->drv->ops.copy(dev);
-}
-
-/* component reset and free runtime resources -mandatory */
-static inline int comp_reset(struct comp_dev *dev)
-{
- return dev->drv->ops.reset(dev);
-}
-
-/* DAI configuration - only mandatory for DAI components */
-static inline int comp_dai_config(struct comp_dev *dev,
- struct sof_ipc_dai_config *config)
-{
- if (dev->drv->ops.dai_config)
- return dev->drv->ops.dai_config(dev, config);
- return 0;
-}
-
-/* component rendering position */
-static inline int comp_position(struct comp_dev *dev,
- struct sof_ipc_stream_posn *posn)
-{
- if (dev->drv->ops.position)
- return dev->drv->ops.position(dev, posn);
- return 0;
-}
-
-/* default base component initialisations */
-void sys_comp_dai_init(void);
-void sys_comp_host_init(void);
-void sys_comp_mixer_init(void);
-void sys_comp_mux_init(void);
-void sys_comp_switch_init(void);
-void sys_comp_volume_init(void);
-void sys_comp_src_init(void);
-void sys_comp_tone_init(void);
-void sys_comp_eq_iir_init(void);
-void sys_comp_eq_fir_init(void);
-
-/*
- * Convenience functions to install upstream/downstream common params. Only
- * applicable to single upstream source. Components with > 1 source or sink
- * must do this manually.
- *
- * This allows params to propagate from the host PCM component downstream on
- * playback and upstream on capture.
- */
-static inline void comp_install_params(struct comp_dev *dev,
- struct comp_dev *previous)
-{
- dev->params = previous->params;
-}
-
-static inline uint32_t comp_frame_bytes(struct comp_dev *dev)
-{
- /* calculate period size based on params */
- switch (dev->params.frame_fmt) {
- case SOF_IPC_FRAME_S16_LE:
- return 2 * dev->params.channels;
- case SOF_IPC_FRAME_S24_4LE:
- case SOF_IPC_FRAME_S32_LE:
- case SOF_IPC_FRAME_FLOAT:
- return 4 * dev->params.channels;
- default:
- return 0;
- }
-}
-
-static inline uint32_t comp_sample_bytes(struct comp_dev *dev)
-{
- /* calculate period size based on params */
- switch (dev->params.frame_fmt) {
- case SOF_IPC_FRAME_S16_LE:
- return 2;
- case SOF_IPC_FRAME_S24_4LE:
- case SOF_IPC_FRAME_S32_LE:
- case SOF_IPC_FRAME_FLOAT:
- return 4;
- default:
- return 0;
- }
-}
-
-/* XRUN handling */
-static inline void comp_underrun(struct comp_dev *dev, struct comp_buffer *source,
- uint32_t copy_bytes, uint32_t min_bytes)
-{
- trace_comp("Xun");
- trace_value((dev->comp.id << 16) | source->avail);
- trace_value((min_bytes << 16) | copy_bytes);
-
- pipeline_xrun(dev->pipeline, dev, (int32_t)source->avail - copy_bytes);
-}
-
-static inline void comp_overrun(struct comp_dev *dev, struct comp_buffer *sink,
- uint32_t copy_bytes, uint32_t min_bytes)
-{
- trace_comp("Xov");
- trace_value((dev->comp.id << 16) | sink->free);
- trace_value((min_bytes << 16) | copy_bytes);
-
- pipeline_xrun(dev->pipeline, dev, (int32_t)copy_bytes - sink->free);
-}
-
-#endif
diff --git a/src/include/sof/audio/format.h b/src/include/sof/audio/format.h
deleted file mode 100644
index 67c1632..0000000
--- a/src/include/sof/audio/format.h
+++ /dev/null
@@ -1,184 +0,0 @@
-/*
- * Copyright (c) 2016, Intel Corporation
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- * * Redistributions of source code must retain the above copyright
- * notice, this list of conditions and the following disclaimer.
- * * Redistributions in binary form must reproduce the above copyright
- * notice, this list of conditions and the following disclaimer in the
- * documentation and/or other materials provided with the distribution.
- * * Neither the name of the Intel Corporation nor the
- * names of its contributors may be used to endorse or promote products
- * derived from this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
- * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
- * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
- * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
- * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
- * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
- * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
- * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
- * POSSIBILITY OF SUCH DAMAGE.
- *
- * Author: Seppo Ingalsuo <seppo.ingalsuo@linux.intel.com>
- * Liam Girdwood <liam.r.girdwood@linux.intel.com>
- * Keyon Jie <yang.jie@linux.intel.com>
- */
-
-#ifndef AUDIO_FORMAT_H
-#define AUDIO_FORMAT_H
-
-/* Maximum and minimum values for 24 bit */
-#define INT24_MAXVALUE 8388607
-#define INT24_MINVALUE -8388608
-
-
-/* Collection of common fractional numbers */
-#define ONE_Q2_30 1073741824 /* Q2.30 1.0 */
-#define ONE_Q1_31 2147483647 /* Q1.31 ~1.0 */
-#define MINUS_3DB_Q1_31 1520301996 /* 10^(-3/20) */
-#define MINUS_6DB_Q1_31 1076291389 /* 10^(-6/20) */
-#define MINUS_10DB_Q1_31 679093957 /* 10^(-10/20) */
-#define MINUS_20DB_Q1_31 214748365 /* 10^(-20/20) */
-#define MINUS_30DB_Q1_31 67909396 /* 10^(-30/20) */
-#define MINUS_40DB_Q1_31 21474836 /* 10^(-40/20) */
-#define MINUS_50DB_Q1_31 6790940 /* 10^(-50/20) */
-#define MINUS_60DB_Q1_31 2147484 /* 10^(-60/20) */
-#define MINUS_70DB_Q1_31 679094 /* 10^(-70/20) */
-#define MINUS_80DB_Q1_31 214748 /* 10^(-80/20) */
-#define MINUS_90DB_Q1_31 67909 /* 10^(-90/20) */
-
-/* Align the number to the nearest alignment value */
-#define ALIGN_UP(size, alignment) \
- (((size) % (alignment) == 0) ? (size) : \
- ((size) - ((size) % (alignment)) + (alignment)))
-#define ALIGN_DOWN(size, alignment) \
- ((size) - ((size) % (alignment)))
-
-/* Compute the number of shifts
- * This will result in a compiler overflow error if shift bits are out of
- * range as INT64_MAX/MIN is greater than 32 bit Q shift parameter
- */
-#define Q_SHIFT_BITS_64(qx, qy, qz) \
- ((qx + qy - qz) <= 63 ? (((qx + qy - qz) >= 0) ? \
- (qx + qy - qz) : INT64_MIN) : INT64_MAX)
-
-#define Q_SHIFT_BITS_32(qx, qy, qz) \
- ((qx + qy - qz) <= 31 ? (((qx + qy - qz) >= 0) ? \
- (qx + qy - qz) : INT32_MIN) : INT32_MAX)
-
-/* Convert a float number to fractional Qnx.ny format. Note that there is no
- * check for nx+ny number of bits to fit the word length of int.
- */
-#define Q_CONVERT_FLOAT(f, qy) ((int)((f) * (1 << qy) + 0.5)) /* f is float */
-
-/* Convert fractional Qnx.ny number x to float */
-#define Q_CONVERT_QTOF(x, ny) ((float)(x) / ((int64_t)1 << (ny)))
-
-/* A more clever macro for Q-shifts */
-#define Q_SHIFT(x, src_q, dst_q) ((x)>>((src_q)-(dst_q)))
-#define Q_SHIFT_RND(x, src_q, dst_q) ((((x) >> ((src_q)-(dst_q) -1)) +1) >> 1)
-
-/* Alternative version since compiler does not allow (x >> -1) */
-#define Q_SHIFT_LEFT(x, src_q, dst_q) ((x)<<((dst_q)-(src_q)))
-
-/* Fractional multiplication with shift
- * Note that the parameters px and py must be cast to (int64_t) if other type.
- */
-#define Q_MULTS_32X32(px, py, qx, qy, qp) ((px) * (py) >> (((qx)+(qy)-(qp))))
-
-/* Fractional multiplication with shift and round
- * Note that the parameters px and py must be cast to (int64_t) if other type.
- */
-#define Q_MULTSR_32X32(px, py, qx, qy, qp) \
- ((((px) * (py) >> ((qx)+(qy)-(qp)-1)) + 1) >> 1)
-
-/* Saturation */
-#define SATP_INT32(x) (((x) > INT32_MAX) ? INT32_MAX : (x))
-#define SATM_INT32(x) (((x) < INT32_MIN) ? INT32_MIN : (x))
-
-static inline int64_t q_mults_32x32(int32_t x, int32_t y, const int shift_bits)
-{
- return ((int64_t)x * y) >> shift_bits;
-}
-
-static inline int64_t q_multsr_32x32(int32_t x, int32_t y, const int shift_bits)
-{
- return ((((int64_t)x * y) >> (shift_bits - 1)) + 1) >> 1;
-}
-
-static inline int32_t q_mults_16x16(int16_t x, int32_t y, const int shift_bits)
-{
- return ((int32_t)x * y) >> shift_bits;
-}
-
-static inline int16_t q_multsr_16x16(int16_t x, int32_t y, const int shift_bits)
-{
- return ((((int32_t)x * y) >> (shift_bits - 1)) + 1) >> 1;
-}
-
-/* Saturation inline functions */
-
-static inline int32_t sat_int32(int64_t x)
-{
-#if 1
- /* TODO: Is this faster */
- if (x > INT32_MAX)
- return INT32_MAX;
- else if (x < INT32_MIN)
- return INT32_MIN;
- else
- return (int32_t)x;
-#else
- /* Or this */
- int64_t y;
- y = SATP_INT32(x);
- return (int32_t)SATM_INT32(y);
-
-#endif
-}
-
-static inline int32_t sat_int24(int32_t x)
-{
- if (x > INT24_MAXVALUE)
- return INT24_MAXVALUE;
- else if (x < INT24_MINVALUE)
- return INT24_MINVALUE;
- else
- return x;
-}
-
-static inline int16_t sat_int16(int32_t x)
-{
- if (x > INT16_MAX)
- return INT16_MAX;
- else if (x < INT16_MIN)
- return INT16_MIN;
- else
- return (int16_t)x;
-}
-
-/* Fractional multiplication with shift and saturation */
-static inline int32_t q_multsr_sat_32x32(int32_t x, int32_t y,
- const int shift_bits)
-{
- return sat_int32(((((int64_t)x * y) >> (shift_bits - 1)) + 1) >> 1);
-}
-
-static inline int16_t q_multsr_sat_16x16(int16_t x, int32_t y,
- const int shift_bits)
-{
- return sat_int16(((((int32_t)x * y) >> (shift_bits - 1)) + 1) >> 1);
-}
-
-static inline int32_t sign_extend_s24(int32_t x)
-{
- return (x << 8) >> 8;
-}
-
-#endif
diff --git a/src/include/sof/audio/pipeline.h b/src/include/sof/audio/pipeline.h
deleted file mode 100644
index 57d2488..0000000
--- a/src/include/sof/audio/pipeline.h
+++ /dev/null
@@ -1,132 +0,0 @@
-/*
- * Copyright (c) 2016, Intel Corporation
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- * * Redistributions of source code must retain the above copyright
- * notice, this list of conditions and the following disclaimer.
- * * Redistributions in binary form must reproduce the above copyright
- * notice, this list of conditions and the following disclaimer in the
- * documentation and/or other materials provided with the distribution.
- * * Neither the name of the Intel Corporation nor the
- * names of its contributors may be used to endorse or promote products
- * derived from this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
- * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
- * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
- * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
- * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
- * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
- * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
- * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
- * POSSIBILITY OF SUCH DAMAGE.
- *
- * Author: Liam Girdwood <liam.r.girdwood@linux.intel.com>
- */
-
-#ifndef __INCLUDE_AUDIO_PIPELINE_H__
-#define __INCLUDE_AUDIO_PIPELINE_H__
-
-#include <stdint.h>
-#include <stddef.h>
-#include <sof/lock.h>
-#include <sof/list.h>
-#include <sof/stream.h>
-#include <sof/dma.h>
-#include <sof/audio/component.h>
-#include <sof/trace.h>
-#include <sof/schedule.h>
-#include <uapi/ipc.h>
-
-/* pipeline tracing */
-#define trace_pipe(__e) trace_event(TRACE_CLASS_PIPE, __e)
-#define trace_pipe_error(__e) trace_error(TRACE_CLASS_PIPE, __e)
-#define tracev_pipe(__e) tracev_event(TRACE_CLASS_PIPE, __e)
-
-struct ipc_pipeline_dev;
-struct ipc;
-
-/*
- * Audio pipeline.
- */
-struct pipeline {
- spinlock_t lock;
- struct sof_ipc_pipe_new ipc_pipe;
-
- /* runtime status */
- int32_t xrun_bytes; /* last xrun length */
- uint32_t status; /* pipeline status */
-
- /* lists */
- struct list_item comp_list; /* list of components */
- struct list_item buffer_list; /* list of buffers */
-
- /* scheduling */
- struct task pipe_task; /* pipeline processing task */
- struct comp_dev *sched_comp; /* component that drives scheduling in this pipe */
- struct comp_dev *source_comp; /* source component for this pipe */
-
- /* position update */
- uint32_t posn_offset; /* position update array offset*/
-};
-
-/* static pipeline */
-extern struct pipeline *pipeline_static;
-
-/* pipeline creation and destruction */
-struct pipeline *pipeline_new(struct sof_ipc_pipe_new *pipe_desc,
- struct comp_dev *cd);
-int pipeline_free(struct pipeline *p);
-
-/* pipeline buffer creation and destruction */
-struct comp_buffer *buffer_new(struct sof_ipc_buffer *desc);
-void buffer_free(struct comp_buffer *buffer);
-
-/* insert component in pipeline */
-int pipeline_comp_connect(struct pipeline *p, struct comp_dev *source_comp,
- struct comp_buffer *sink_buffer);
-int pipeline_buffer_connect(struct pipeline *p,
- struct comp_buffer *source_buffer, struct comp_dev *sink_comp);
-int pipeline_complete(struct pipeline *p);
-
-/* pipeline parameters */
-int pipeline_params(struct pipeline *p, struct comp_dev *cd,
- struct sof_ipc_pcm_params *params);
-
-/* prepare the pipeline for usage */
-int pipeline_prepare(struct pipeline *p, struct comp_dev *cd);
-
-/* reset the pipeline and free resources */
-int pipeline_reset(struct pipeline *p, struct comp_dev *host_cd);
-
-/* trigger pipeline - atomic */
-int pipeline_trigger(struct pipeline *p, struct comp_dev *host_cd, int cmd);
-
-/* initialise pipeline subsys */
-int pipeline_init(void);
-
-/* static pipeline creation */
-int init_static_pipeline(struct ipc *ipc);
-
-/* pipeline creation */
-int init_pipeline(void);
-
-/* schedule a copy operation for this pipeline */
-void pipeline_schedule_copy(struct pipeline *p, uint64_t start);
-void pipeline_schedule_copy_idle(struct pipeline *p);
-void pipeline_schedule_cancel(struct pipeline *p);
-
-/* get time pipeline timestamps from host to dai */
-void pipeline_get_timestamp(struct pipeline *p, struct comp_dev *host_dev,
- struct sof_ipc_stream_posn *posn);
-
-void pipeline_schedule(void *arg);
-
-/* notify host that we have XRUN */
-void pipeline_xrun(struct pipeline *p, struct comp_dev *dev, int32_t bytes);
-
-#endif
diff --git a/src/include/sof/bit.h b/src/include/sof/bit.h
deleted file mode 100644
index 9f39353..0000000
--- a/src/include/sof/bit.h
+++ /dev/null
@@ -1,40 +0,0 @@
-/*
- * Copyright (c) 2018, Intel Corporation
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- * * Redistributions of source code must retain the above copyright
- * notice, this list of conditions and the following disclaimer.
- * * Redistributions in binary form must reproduce the above copyright
- * notice, this list of conditions and the following disclaimer in the
- * documentation and/or other materials provided with the distribution.
- * * Neither the name of the Intel Corporation nor the
- * names of its contributors may be used to endorse or promote products
- * derived from this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
- * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
- * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
- * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
- * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
- * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
- * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
- * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
- * POSSIBILITY OF SUCH DAMAGE.
- *
- * Author: Liam Girdwood <liam.r.girdwood@linux.intel.com>
- */
-
-#ifndef __INCLUDE_BIT__
-#define __INCLUDE_BIT__
-
-#define BIT(b) (1 << (b))
-#define MASK(b_hi, b_lo) ((1 << ((b_hi) - (b_lo) + 1)) - 1)
-#define SET_BIT(b, x) (((x) & 1) << (b))
-#define SET_BITS(b_hi, b_lo, x) \
- (((x) & ((1 << ((b_hi) - (b_lo) + 1)) - 1)) << (b_lo))
-
-#endif
diff --git a/src/include/sof/clock.h b/src/include/sof/clock.h
deleted file mode 100644
index 109beec..0000000
--- a/src/include/sof/clock.h
+++ /dev/null
@@ -1,63 +0,0 @@
-/*
- * Copyright (c) 2016, Intel Corporation
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- * * Redistributions of source code must retain the above copyright
- * notice, this list of conditions and the following disclaimer.
- * * Redistributions in binary form must reproduce the above copyright
- * notice, this list of conditions and the following disclaimer in the
- * documentation and/or other materials provided with the distribution.
- * * Neither the name of the Intel Corporation nor the
- * names of its contributors may be used to endorse or promote products
- * derived from this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
- * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
- * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
- * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
- * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
- * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
- * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
- * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
- * POSSIBILITY OF SUCH DAMAGE.
- *
- * Author: Liam Girdwood <liam.r.girdwood@linux.intel.com>
- */
-
-#ifndef __INCLUDE_CLOCK__
-#define __INCLUDE_CLOCK__
-
-#include <sof/notifier.h>
-#include <stdint.h>
-
-#define CLOCK_NOTIFY_PRE 0
-#define CLOCK_NOTIFY_POST 1
-
-struct clock_notify_data {
- uint32_t old_freq;
- uint32_t old_ticks_per_usec;
- uint32_t freq;
- uint32_t ticks_per_usec;
-};
-
-void clock_enable(int clock);
-void clock_disable(int clock);
-
-uint32_t clock_set_freq(int clock, unsigned int hz);
-
-uint32_t clock_get_freq(int clock);
-
-uint64_t clock_us_to_ticks(int clock, uint64_t us);
-uint64_t clock_ms_to_ticks(int clock, uint64_t ms);
-
-uint64_t clock_time_elapsed(int clock, uint64_t previous, uint64_t *current);
-
-void clock_register_notifier(int clock, struct notifier *notifier);
-
-int clock_init();
-
-#endif
diff --git a/src/include/sof/cpu.h b/src/include/sof/cpu.h
deleted file mode 100644
index d6cfb3b..0000000
--- a/src/include/sof/cpu.h
+++ /dev/null
@@ -1,62 +0,0 @@
-/*
- * Copyright (c) 2018, Intel Corporation
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- * * Redistributions of source code must retain the above copyright
- * notice, this list of conditions and the following disclaimer.
- * * Redistributions in binary form must reproduce the above copyright
- * notice, this list of conditions and the following disclaimer in the
- * documentation and/or other materials provided with the distribution.
- * * Neither the name of the Intel Corporation nor the
- * names of its contributors may be used to endorse or promote products
- * derived from this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
- * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
- * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
- * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
- * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
- * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
- * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
- * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
- * POSSIBILITY OF SUCH DAMAGE.
- *
- * Author: Tomasz Lauda <tomasz.lauda@linux.intel.com>
- */
-
-/**
- * \file include/sof/cpu.h
- * \brief CPU header file
- * \authors Tomasz Lauda <tomasz.lauda@linux.intel.com>
- */
-
-#ifndef __SOF_CPU_H__
-#define __SOF_CPU_H__
-
-#include <arch/cpu.h>
-
-static inline int cpu_get_id(void)
-{
- return arch_cpu_get_id();
-}
-
-static inline void cpu_enable_core(int id)
-{
- arch_cpu_enable_core(id);
-}
-
-static inline void cpu_disable_core(int id)
-{
- arch_cpu_disable_core(id);
-}
-
-static inline int cpu_is_core_enabled(int id)
-{
- return arch_cpu_is_core_enabled(id);
-}
-
-#endif
diff --git a/src/include/sof/dai.h b/src/include/sof/dai.h
deleted file mode 100644
index 5fd4452..0000000
--- a/src/include/sof/dai.h
+++ /dev/null
@@ -1,191 +0,0 @@
-/*
- * Copyright (c) 2016, Intel Corporation
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- * * Redistributions of source code must retain the above copyright
- * notice, this list of conditions and the following disclaimer.
- * * Redistributions in binary form must reproduce the above copyright
- * notice, this list of conditions and the following disclaimer in the
- * documentation and/or other materials provided with the distribution.
- * * Neither the name of the Intel Corporation nor the
- * names of its contributors may be used to endorse or promote products
- * derived from this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
- * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
- * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
- * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
- * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
- * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
- * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
- * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
- * POSSIBILITY OF SUCH DAMAGE.
- *
- * Author: Liam Girdwood <liam.r.girdwood@linux.intel.com>
- * Keyon Jie <yang.jie@linux.intel.com>
- */
-
- /**
- * \file include/sof/dai.h
- * \brief DAI Drivers definition
- * \author Liam Girdwood <liam.r.girdwood@linux.intel.com>
- * \author Keyon Jie <yang.jie@linux.intel.com>
- */
-
-#ifndef __INCLUDE_DAI_H__
-#define __INCLUDE_DAI_H__
-
-#include <stdint.h>
-#include <sof/audio/component.h>
-
-/** \addtogroup sof_dai_drivers DAI Drivers
- * DAI Drivers API specification.
- * @{
- */
-
-#define DAI_CLOCK_IN 0
-#define DAI_CLOCK_OUT 1
-
-#define DAI_DIR_PLAYBACK 0
-#define DAI_DIR_CAPTURE 1
-
-#define DAI_TRIGGER_START COMP_CMD_START
-#define DAI_TRIGGER_STOP COMP_CMD_STOP
-#define DAI_TRIGGER_PAUSE_PUSH COMP_CMD_PAUSE
-#define DAI_TRIGGER_PAUSE_RELEASE COMP_CMD_RELEASE
-#define DAI_TRIGGER_SUSPEND COMP_CMD_SUSPEND
-#define DAI_TRIGGER_RESUME COMP_CMD_RESUME
-
-#define DAI_NUM_SLOT_MAPS 8
-
-/* DAI flags */
-#define DAI_FLAGS_IRQ_CB (1 << 0) /* irq used for copy() timer */
-
-
-struct dai;
-
-/**
- * \brief DAI operations - all optional
- */
-struct dai_ops {
- int (*set_config)(struct dai *dai, struct sof_ipc_dai_config *config);
- int (*trigger)(struct dai *dai, int cmd, int direction);
- int (*pm_context_restore)(struct dai *dai);
- int (*pm_context_store)(struct dai *dai);
- int (*probe)(struct dai *dai);
- int (*set_loopback_mode)(struct dai *dai, uint32_t lbm);
-};
-
-/**
- * \brief DAI slot map to audio channel
- */
-struct dai_slot_map {
- uint32_t channel; /**< channel ID - CHAN_ID_ */
- uint32_t slot; /**< physical slot index */
-};
-
-/**
- * \brief DAI Type.
- */
-enum dai_type {
- DAI_TYPE_INTEL_SSP = 0, /**< Intel SSP */
- DAI_TYPE_INTEL_HDA, /**< Intel HD/A */
- DAI_TYPE_INTEL_DMIC, /**< Intel DMIC */
-};
-
-
-struct dai_plat_fifo_data {
- uint32_t offset;
- uint32_t width;
- uint32_t depth;
- uint32_t watermark;
- uint32_t handshake;
-};
-
-/**
- * \brief DAI platform data
- */
-struct dai_plat_data {
- uint32_t base;
- uint32_t irq;
- uint32_t flags;
- struct dai_plat_fifo_data fifo[2];
-};
-
-struct dai {
- uint32_t type;
- uint32_t index;
- struct dai_plat_data plat_data;
- const struct dai_ops *ops;
- void *private;
-};
-
-struct dai *dai_get(uint32_t type, uint32_t index);
-
-#define dai_set_drvdata(dai, data) \
- dai->private = data
-#define dai_get_drvdata(dai) \
- dai->private;
-#define dai_base(dai) \
- dai->plat_data.base
-#define dai_irq(dai) \
- dai->plat_data.irq
-#define dai_fifo(dai, direction) \
- dai->plat_data.fifo[direction].offset
-
-/**
- * \brief Digital Audio interface formatting
- */
-static inline int dai_set_config(struct dai *dai,
- struct sof_ipc_dai_config *config)
-{
- return dai->ops->set_config(dai, config);
-}
-
-/**
- * \brief Digital Audio interface formatting
- */
-static inline int dai_set_loopback_mode(struct dai *dai, uint32_t lbm)
-{
- return dai->ops->set_loopback_mode(dai, lbm);
-}
-
-/**
- * \brief Digital Audio interface trigger
- */
-static inline int dai_trigger(struct dai *dai, int cmd, int direction)
-{
- return dai->ops->trigger(dai, cmd, direction);
-}
-
-/**
- * \brief Digital Audio interface PM context store
- */
-static inline int dai_pm_context_store(struct dai *dai)
-{
- return dai->ops->pm_context_store(dai);
-}
-
-/**
- * \brief Digital Audio interface PM context restore
- */
-static inline int dai_pm_context_restore(struct dai *dai)
-{
- return dai->ops->pm_context_restore(dai);
-}
-
-/**
- * \brief Digital Audio interface Probe
- */
-static inline int dai_probe(struct dai *dai)
-{
- return dai->ops->probe(dai);
-}
-
-/** @}*/
-
-#endif
diff --git a/src/include/sof/debug.h b/src/include/sof/debug.h
deleted file mode 100644
index 437e773..0000000
--- a/src/include/sof/debug.h
+++ /dev/null
@@ -1,158 +0,0 @@
-/*
- * Copyright (c) 2016, Intel Corporation
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- * * Redistributions of source code must retain the above copyright
- * notice, this list of conditions and the following disclaimer.
- * * Redistributions in binary form must reproduce the above copyright
- * notice, this list of conditions and the following disclaimer in the
- * documentation and/or other materials provided with the distribution.
- * * Neither the name of the Intel Corporation nor the
- * names of its contributors may be used to endorse or promote products
- * derived from this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
- * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
- * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
- * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
- * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
- * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
- * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
- * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
- * POSSIBILITY OF SUCH DAMAGE.
- *
- * Author: Liam Girdwood <liam.r.girdwood@linux.intel.com>
- * Keyon Jie <yang.jie@linux.intel.com>
- */
-
-#ifndef __INCLUDE_DEBUG__
-#define __INCLUDE_DEBUG__
-
-#include <sof/sof.h>
-#include <sof/mailbox.h>
-#include <uapi/ipc.h>
-#include <platform/platform.h>
-#include <stdint.h>
-#include <stdlib.h>
-
-
-#define DEBUG
-
-#ifdef DEBUG
-
-/* dump file and line to start of mailbox or shared memory */
-#define dbg() \
- do { \
- volatile uint32_t *__m = (uint32_t*)mailbox_get_debug_base(); \
- *(__m++) = (__FILE__[0] << 24) + (__FILE__[1] << 16) +\
- (__FILE__[2] << 8) + (__FILE__[3]); \
- *(__m++) = (__func__[0] << 24) + (__func__[1] << 16) + \
- (__func__[2] << 8) + (__func__[3]); \
- *__m = __LINE__; \
- } while (0);
-
-/* dump file and line to offset in mailbox or shared memory */
-#define dbg_at(__x) \
- do { \
- volatile uint32_t *__m = (uint32_t*)mailbox_get_debug_base() + __x; \
- *(__m++) = (__FILE__[0] << 24) + (__FILE__[1] << 16) +\
- (__FILE__[2] << 8) + (__FILE__[3]); \
- *(__m++) = (__func__[0] << 24) + (__func__[1] << 16) + \
- (__func__[2] << 8) + (__func__[3]); \
- *__m = __LINE__; \
- } while (0);
-
-/* dump value to start of mailbox or shared memory */
-#define dbg_val(__v) \
- do { \
- volatile uint32_t *__m = \
- (volatile uint32_t*)mailbox_get_debug_base(); \
- *__m = __v; \
- } while (0);
-
-/* dump value to offset in mailbox or shared memory */
-#define dbg_val_at(__v, __x) \
- do { \
- volatile uint32_t *__m = \
- (volatile uint32_t*)mailbox_get_debug_base() + __x; \
- *__m = __v; \
- } while (0);
-
-/* dump data area at addr and size count to start of mailbox or shared memory */
-#define dump(addr, count) \
- do { \
- volatile uint32_t *__m = (uint32_t*)mailbox_get_debug_base(); \
- volatile uint32_t *__a = (uint32_t*)addr; \
- volatile int __c = count; \
- while (__c--) \
- *(__m++) = *(__a++); \
- } while (0);
-
-/* dump data area at addr and size count at mailbox offset or shared memory */
-#define dump_at(addr, count, offset) \
- do { \
- volatile uint32_t *__m = (uint32_t*)mailbox_get_debug_base() + offset; \
- volatile uint32_t *__a = (uint32_t*)addr; \
- volatile int __c = count; \
- while (__c--) \
- *(__m++) = *(__a++); \
- } while (0);
-
-/* dump object to start of mailbox */
-#define dump_object(__o) \
- dbg(); \
- dump(&__o, sizeof(__o) >> 2);
-
-/* dump object from pointer at start of mailbox */
-#define dump_object_ptr(__o) \
- dbg(); \
- dump(__o, sizeof(*(__o)) >> 2);
-
-#define dump_object_ptr_at(__o, __at) \
- dbg(); \
- dump_at(__o, sizeof(*(__o)) >> 2, __at);
-
-#else
-
-#define dbg()
-#define dbg_at(__x)
-#define dbg_val(__v)
-#define dbg_val_at(__v, __x)
-#define dump(addr, count)
-#define dump_object(__o)
-#define dump_object_ptr(__o)
-#endif
-
-/* dump stack as part of panic */
-static inline uint32_t dump_stack(uint32_t p, void *addr, size_t offset,
- size_t limit)
-{
- extern void *__stack;
- extern void *_stack_sentry;
- void *stack_bottom = (void *)&__stack - sizeof(void *);
- void *stack_limit = (void *)&_stack_sentry;
- void *stack_top = arch_get_stack_ptr() + offset;
- size_t size = stack_bottom - stack_top;
-
- /* is stack smashed ? */
- if (stack_top - offset <= stack_limit) {
- stack_bottom = stack_limit;
- p = SOF_IPC_PANIC_STACK;
- return p;
- }
-
- /* make sure stack size won't overflow dump area */
- if (size > limit)
- size = limit;
-
- /* copy stack contents and writeback */
- rmemcpy(addr, stack_top, size - sizeof(void *));
- dcache_writeback_region(addr, size - sizeof(void *));
- return p;
-}
-
-#endif
diff --git a/src/include/sof/dma-trace.h b/src/include/sof/dma-trace.h
deleted file mode 100644
index 81ce0a2..0000000
--- a/src/include/sof/dma-trace.h
+++ /dev/null
@@ -1,81 +0,0 @@
-/*
- * Copyright (c) 2016, Intel Corporation
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- * * Redistributions of source code must retain the above copyright
- * notice, this list of conditions and the following disclaimer.
- * * Redistributions in binary form must reproduce the above copyright
- * notice, this list of conditions and the following disclaimer in the
- * documentation and/or other materials provided with the distribution.
- * * Neither the name of the Intel Corporation nor the
- * names of its contributors may be used to endorse or promote products
- * derived from this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
- * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
- * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
- * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
- * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
- * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
- * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
- * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
- * POSSIBILITY OF SUCH DAMAGE.
- *
- * Author: Yan Wang <yan.wang@linux.intel.com>
- */
-
-#ifndef __INCLUDE_DMA_TRACE__
-#define __INCLUDE_DMA_TRACE__
-
-#include <stdint.h>
-#include <stdlib.h>
-#include <sof/sof.h>
-#include <sof/list.h>
-#include <sof/mailbox.h>
-#include <sof/debug.h>
-#include <sof/timer.h>
-#include <sof/dma.h>
-#include <sof/work.h>
-#include <platform/platform.h>
-#include <platform/timer.h>
-
-struct dma_trace_buf {
- void *w_ptr; /* buffer write pointer */
- void *r_ptr; /* buffer read position */
- void *addr; /* buffer base address */
- void *end_addr; /* buffer end address */
- uint32_t size; /* size of buffer in bytes */
- uint32_t avail; /* avail bytes in buffer */
-};
-
-struct dma_trace_data {
- struct dma_sg_config config;
- struct dma_trace_buf dmatb;
- struct dma_copy dc;
- uint32_t old_host_offset;
- uint32_t host_offset;
- uint32_t overflow;
- uint32_t messages;
- uint32_t host_size;
- struct work dmat_work;
- uint32_t enabled;
- uint32_t copy_in_progress;
- uint32_t stream_tag;
- spinlock_t lock;
-};
-
-int dma_trace_init_early(struct sof *sof);
-int dma_trace_init_complete(struct dma_trace_data *d);
-int dma_trace_host_buffer(struct dma_trace_data *d, struct dma_sg_elem *elem,
- uint32_t host_size);
-int dma_trace_enable(struct dma_trace_data *d);
-void dma_trace_flush(void *t);
-
-void dtrace_event(const char *e, uint32_t size);
-void dtrace_event_atomic(const char *e, uint32_t length);
-
-#endif
diff --git a/src/include/sof/dma.h b/src/include/sof/dma.h
deleted file mode 100644
index 197ed33..0000000
--- a/src/include/sof/dma.h
+++ /dev/null
@@ -1,323 +0,0 @@
-/*
- * Copyright (c) 2016, Intel Corporation
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- * * Redistributions of source code must retain the above copyright
- * notice, this list of conditions and the following disclaimer.
- * * Redistributions in binary form must reproduce the above copyright
- * notice, this list of conditions and the following disclaimer in the
- * documentation and/or other materials provided with the distribution.
- * * Neither the name of the Intel Corporation nor the
- * names of its contributors may be used to endorse or promote products
- * derived from this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
- * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
- * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
- * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
- * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
- * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
- * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
- * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
- * POSSIBILITY OF SUCH DAMAGE.
- *
- * Author: Liam Girdwood <liam.r.girdwood@linux.intel.com>
- * Keyon Jie <yang.jie@linux.intel.com>
- */
-
-/**
- * \file include/sof/dma.h
- * \brief DMA Drivers definition
- * \author Liam Girdwood <liam.r.girdwood@linux.intel.com>
- * \author Keyon Jie <yang.jie@linux.intel.com>
- */
-
-#ifndef __INCLUDE_DMA_H__
-#define __INCLUDE_DMA_H__
-
-#include <stdint.h>
-#include <sof/list.h>
-#include <sof/lock.h>
-#include <sof/sof.h>
-#include <sof/wait.h>
-#include <sof/bit.h>
-#include <arch/atomic.h>
-
-/** \addtogroup sof_dma_drivers DMA Drivers
- * DMA Drivers API specification.
- * @{
- */
-
-/* DMA direction bitmasks used to define DMA copy direction */
-#define DMA_DIR_MEM_TO_MEM BIT(0) /**< local memory copy */
-#define DMA_DIR_HMEM_TO_LMEM BIT(1) /**< host memory to local mem copy */
-#define DMA_DIR_LMEM_TO_HMEM BIT(2) /**< local mem to host mem copy */
-#define DMA_DIR_MEM_TO_DEV BIT(3) /**< local mem to dev copy */
-#define DMA_DIR_DEV_TO_MEM BIT(4) /**< dev to local mem copy */
-#define DMA_DIR_DEV_TO_DEV BIT(5) /**< dev to dev copy */
-
-/* DMA capabilities bitmasks used to define the type of DMA */
-#define DMA_CAP_HDA BIT(0) /**< HDA DMA */
-#define DMA_CAP_GP_LP BIT(1) /**< GP LP DMA */
-#define DMA_CAP_GP_HP BIT(2) /**< GP HP DMA */
-
-/* DMA dev type bitmasks used to define the type of DMA */
-
-#define DMA_DEV_HOST BIT(0) /**< connectable to host */
-#define DMA_DEV_HDA BIT(1) /**< connectable to HD/A link */
-#define DMA_DEV_SSP BIT(2) /**< connectable to SSP fifo */
-#define DMA_DEV_DMIC BIT(3) /**< connectable to DMIC fifo */
-
-/* DMA access privilege flag */
-#define DMA_ACCESS_EXCLUSIVE 1
-#define DMA_ACCESS_SHARED 0
-
-/* DMA IRQ types */
-#define DMA_IRQ_TYPE_BLOCK BIT(0)
-#define DMA_IRQ_TYPE_LLIST BIT(1)
-
-/* DMA copy flags */
-#define DMA_COPY_PRELOAD BIT(0)
-
-/* We will use this macro in cb handler to inform dma that
- * we need to stop the reload for special purpose
- */
-#define DMA_RELOAD_END 0
-#define DMA_RELOAD_LLI 0xFFFFFFFF
-
-struct dma;
-
-struct dma_sg_elem {
- uint32_t src;
- uint32_t dest;
- uint32_t size;
- struct list_item list;
-};
-
-/* DMA physical SG params */
-struct dma_sg_config {
- uint32_t src_width; /* in bytes */
- uint32_t dest_width; /* in bytes */
- uint32_t burst_elems;
- uint32_t direction;
- uint32_t src_dev;
- uint32_t dest_dev;
- uint32_t cyclic; /* circular buffer */
- struct list_item elem_list; /* list of dma_sg elems */
-};
-
-struct dma_chan_status {
- uint32_t state;
- uint32_t flags;
- uint32_t w_pos;
- uint32_t r_pos;
- uint32_t timestamp;
-};
-
-/* DMA operations */
-struct dma_ops {
-
- int (*channel_get)(struct dma *dma, int req_channel);
- void (*channel_put)(struct dma *dma, int channel);
-
- int (*start)(struct dma *dma, int channel);
- int (*stop)(struct dma *dma, int channel);
- int (*copy)(struct dma *dma, int channel, int bytes, uint32_t flags);
- int (*pause)(struct dma *dma, int channel);
- int (*release)(struct dma *dma, int channel);
- int (*status)(struct dma *dma, int channel,
- struct dma_chan_status *status, uint8_t direction);
-
- int (*set_config)(struct dma *dma, int channel,
- struct dma_sg_config *config);
-
- int (*set_cb)(struct dma *dma, int channel, int type,
- void (*cb)(void *data, uint32_t type, struct dma_sg_elem *next),
- void *data);
-
- int (*pm_context_restore)(struct dma *dma);
- int (*pm_context_store)(struct dma *dma);
-
- int (*probe)(struct dma *dma);
-};
-
-/* DMA platform data */
-struct dma_plat_data {
- uint32_t id;
- uint32_t dir; /* bitmask of supported copy directions */
- uint32_t caps; /* bitmask of supported capabilities */
- uint32_t devs; /* bitmask of supported devs */
- uint32_t base;
- uint32_t channels;
- uint32_t irq;
- uint32_t chan_size;
- void *drv_plat_data;
-};
-
-struct dma {
- struct dma_plat_data plat_data;
- spinlock_t lock;
- const struct dma_ops *ops;
- atomic_t num_channels_busy; /* number of busy channels */
- void *private;
-};
-
-struct dma_int {
- struct dma *dma;
- uint32_t channel;
- uint32_t irq;
-};
-
-struct dma *dma_get(uint32_t dir, uint32_t caps, uint32_t dev, uint32_t flags);
-
-/* initialize all platform DMAC's */
-int dmac_init(void);
-
-#define dma_set_drvdata(dma, data) \
- dma->private = data
-#define dma_get_drvdata(dma) \
- dma->private;
-#define dma_base(dma) \
- dma->plat_data.base
-#define dma_irq(dma) \
- dma->plat_data.irq
-#define dma_chan_size(dma) \
- dma->plat_data.chan_size
-#define dma_chan_base(dma, chan) \
- (dma->plat_data.base + chan * dma->plat_data.chan_size)
-
-/* DMA API
- * Programming flow is :-
- *
- * 1) dma_channel_get()
- * 2) dma_set_cb()
- * 3) dma_set_config()
- * 4) dma_start()
- * ... DMA now running ...
- * 5) dma_stop()
- * 6) dma_channel_put()
- */
-
-static inline int dma_channel_get(struct dma *dma, int req_channel)
-{
- return dma->ops->channel_get(dma, req_channel);
-}
-
-static inline void dma_channel_put(struct dma *dma, int channel)
-{
- dma->ops->channel_put(dma, channel);
-}
-
-static inline int dma_set_cb(struct dma *dma, int channel, int type,
- void (*cb)(void *data, uint32_t type, struct dma_sg_elem *next), void *data)
-{
- return dma->ops->set_cb(dma, channel, type, cb, data);
-}
-
-static inline int dma_start(struct dma *dma, int channel)
-{
- return dma->ops->start(dma, channel);
-}
-
-static inline int dma_stop(struct dma *dma, int channel)
-{
- return dma->ops->stop(dma, channel);
-}
-
-static inline int dma_copy(struct dma *dma, int channel, int bytes,
- uint32_t flags)
-{
- return dma->ops->copy(dma, channel, bytes, flags);
-}
-
-static inline int dma_pause(struct dma *dma, int channel)
-{
- return dma->ops->pause(dma, channel);
-}
-
-static inline int dma_release(struct dma *dma, int channel)
-{
- return dma->ops->release(dma, channel);
-}
-
-static inline int dma_status(struct dma *dma, int channel,
- struct dma_chan_status *status, uint8_t direction)
-{
- return dma->ops->status(dma, channel, status, direction);
-}
-
-static inline int dma_set_config(struct dma *dma, int channel,
- struct dma_sg_config *config)
-{
- return dma->ops->set_config(dma, channel, config);
-}
-
-static inline int dma_pm_context_restore(struct dma *dma)
-{
- return dma->ops->pm_context_restore(dma);
-}
-
-static inline int dma_pm_context_store(struct dma *dma)
-{
- return dma->ops->pm_context_store(dma);
-}
-
-static inline int dma_probe(struct dma *dma)
-{
- return dma->ops->probe(dma);
-}
-
-/* get the size of SG buffer */
-static inline uint32_t dma_sg_get_size(struct dma_sg_config *sg)
-{
- struct dma_sg_elem *sg_elem;
- struct list_item *plist;
- uint32_t size = 0;
-
- list_for_item(plist, &sg->elem_list) {
-
- sg_elem = container_of(plist, struct dma_sg_elem, list);
- size += sg_elem->size;
- }
-
- return size;
-}
-
-/* generic DMA DSP <-> Host copier */
-
-struct dma_copy {
- int chan;
- struct dma *dmac;
- completion_t complete;
-};
-
-/* init dma copy context */
-int dma_copy_new(struct dma_copy *dc);
-
-/* free dma copy context resources */
-static inline void dma_copy_free(struct dma_copy *dc)
-{
- dma_channel_put(dc->dmac, dc->chan);
-}
-
-/* DMA copy data from host to DSP */
-int dma_copy_from_host(struct dma_copy *dc, struct dma_sg_config *host_sg,
- int32_t host_offset, void *local_ptr, int32_t size);
-int dma_copy_from_host_nowait(struct dma_copy *dc, struct dma_sg_config *host_sg,
- int32_t host_offset, void *local_ptr, int32_t size);
-
-/* DMA copy data from DSP to host */
-int dma_copy_to_host(struct dma_copy *dc, struct dma_sg_config *host_sg,
- int32_t host_offset, void *local_ptr, int32_t size);
-int dma_copy_to_host_nowait(struct dma_copy *dc, struct dma_sg_config *host_sg,
- int32_t host_offset, void *local_ptr, int32_t size);
-
-int dma_copy_set_stream_tag(struct dma_copy *dc, uint32_t stream_tag);
-
-/** @}*/
-
-#endif
diff --git a/src/include/sof/dmic.h b/src/include/sof/dmic.h
deleted file mode 100644
index 4cd0fab..0000000
--- a/src/include/sof/dmic.h
+++ /dev/null
@@ -1,330 +0,0 @@
-/*
- * Copyright (c) 2017, Intel Corporation
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- * * Redistributions of source code must retain the above copyright
- * notice, this list of conditions and the following disclaimer.
- * * Redistributions in binary form must reproduce the above copyright
- * notice, this list of conditions and the following disclaimer in the
- * documentation and/or other materials provided with the distribution.
- * * Neither the name of the Intel Corporation nor the
- * names of its contributors may be used to endorse or promote products
- * derived from this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
- * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
- * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
- * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
- * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
- * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
- * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
- * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
- * POSSIBILITY OF SUCH DAMAGE.
- *
- * Author: Seppo Ingalsuo <seppo.ingalsuo@linux.intel.com>
- */
-
-#ifndef __INCLUDE_DMIC__
-#define __INCLUDE_DMIC__
-
-#include <config.h>
-#include <sof/dai.h>
-#include <sof/io.h>
-
-#if defined CONFIG_DMIC
-
-/* The microphones create a low frequecy thump sound when clock is enabled.
- * The unmute linear gain ramp chacteristic is defined here.
- * NOTE: Do not set any of these to 0.
- */
-#define DMIC_UNMUTE_RAMP_US 1000 /* 1 ms (in microseconds) */
-#define DMIC_UNMUTE_CIC 1 /* Unmute CIC at 1 ms */
-#define DMIC_UNMUTE_FIR 2 /* Unmute FIR at 2 ms */
-
-#if defined CONFIG_APOLLOLAKE
-#define DMIC_HW_VERSION 1
-#define DMIC_HW_CONTROLLERS 2
-#define DMIC_HW_IOCLK 19200000
-#endif
-
-#if defined CONFIG_CANNONLAKE
-#define DMIC_HW_VERSION 1
-#define DMIC_HW_CONTROLLERS 2
-#define DMIC_HW_IOCLK 24000000
-#endif
-
-#endif
-
-#if defined DMIC_HW_VERSION
-
-/* Parameters used in modes computation */
-#define DMIC_HW_BITS_CIC 26
-#define DMIC_HW_BITS_FIR_COEF 20
-#define DMIC_HW_BITS_FIR_GAIN 20
-#define DMIC_HW_BITS_FIR_INPUT 22
-#define DMIC_HW_BITS_FIR_OUTPUT 24
-#define DMIC_HW_BITS_FIR_INTERNAL 26
-#define DMIC_HW_BITS_GAIN_OUTPUT 22
-#define DMIC_HW_FIR_LENGTH_MAX 250
-#define DMIC_HW_CIC_SHIFT_MIN -8
-#define DMIC_HW_CIC_SHIFT_MAX 4
-#define DMIC_HW_FIR_SHIFT_MIN 0
-#define DMIC_HW_FIR_SHIFT_MAX 8
-#define DMIC_HW_CIC_DECIM_MIN 5
-#define DMIC_HW_CIC_DECIM_MAX 31 /* Note: Limited by BITS_CIC */
-#define DMIC_HW_FIR_DECIM_MIN 2
-#define DMIC_HW_FIR_DECIM_MAX 20 /* Note: Practical upper limit */
-#define DMIC_HW_SENS_Q28 Q_CONVERT_FLOAT(1.0, 28) /* Q1.28 */
-#define DMIC_HW_PDM_CLK_MIN 100000 /* Note: Practical min value */
-#define DMIC_HW_DUTY_MIN 20 /* Note: Practical min value */
-#define DMIC_HW_DUTY_MAX 80 /* Note: Practical max value */
-
-/* DMIC register offsets */
-
-/* Global registers */
-#define OUTCONTROL0 0x0000
-#define OUTSTAT0 0x0004
-#define OUTDATA0 0x0008
-#define OUTCONTROL1 0x0100
-#define OUTSTAT1 0x0104
-#define OUTDATA1 0x0108
-#define PDM0 0x1000
-#define PDM0_COEFFICIENT_A 0x1400
-#define PDM0_COEFFICIENT_B 0x1800
-#define PDM1 0x2000
-#define PDM1_COEFFICIENT_A 0x2400
-#define PDM1_COEFFICIENT_B 0x2800
-#define PDM2 0x3000
-#define PDM2_COEFFICIENT_A 0x3400
-#define PDM2_COEFFICIENT_B 0x3800
-#define PDM3 0x4000
-#define PDM3_COEFFICIENT_A 0x4400
-#define PDM3_COEFFICIENT_B 0x4800
-#define PDM_COEF_RAM_A_LENGTH 0x0400
-#define PDM_COEF_RAM_B_LENGTH 0x0400
-
-/* Local registers in each PDMx */
-#define CIC_CONTROL 0x000
-#define CIC_CONFIG 0x004
-#define MIC_CONTROL 0x00c
-#define FIR_CONTROL_A 0x020
-#define FIR_CONFIG_A 0x024
-#define DC_OFFSET_LEFT_A 0x028
-#define DC_OFFSET_RIGHT_A 0x02c
-#define OUT_GAIN_LEFT_A 0x030
-#define OUT_GAIN_RIGHT_A 0x034
-#define FIR_CONTROL_B 0x040
-#define FIR_CONFIG_B 0x044
-#define DC_OFFSET_LEFT_B 0x048
-#define DC_OFFSET_RIGHT_B 0x04c
-#define OUT_GAIN_LEFT_B 0x050
-#define OUT_GAIN_RIGHT_B 0x054
-
-/* Register bits */
-
-#if DMIC_HW_VERSION == 1
-/* OUTCONTROL0 bits */
-#define OUTCONTROL0_TIE_BIT BIT(27)
-#define OUTCONTROL0_SIP_BIT BIT(26)
-#define OUTCONTROL0_FINIT_BIT BIT(25)
-#define OUTCONTROL0_FCI_BIT BIT(24)
-#define OUTCONTROL0_TIE(x) SET_BIT(27, x)
-#define OUTCONTROL0_SIP(x) SET_BIT(26, x)
-#define OUTCONTROL0_FINIT(x) SET_BIT(25, x)
-#define OUTCONTROL0_FCI(x) SET_BIT(24, x)
-#define OUTCONTROL0_BFTH(x) SET_BITS(23, 20, x)
-#define OUTCONTROL0_OF(x) SET_BITS(19, 18, x)
-#define OUTCONTROL0_IPM(x) SET_BITS(17, 16, x)
-#define OUTCONTROL0_TH(x) SET_BITS(5, 0, x)
-
-/* OUTCONTROL1 bits */
-#define OUTCONTROL1_TIE_BIT BIT(27)
-#define OUTCONTROL1_SIP_BIT BIT(26)
-#define OUTCONTROL1_FINIT_BIT BIT(25)
-#define OUTCONTROL1_FCI_BIT BIT(24)
-#define OUTCONTROL1_TIE(x) SET_BIT(27, x)
-#define OUTCONTROL1_SIP(x) SET_BIT(26, x)
-#define OUTCONTROL1_FINIT(x) SET_BIT(25, x)
-#define OUTCONTROL1_FCI(x) SET_BIT(24, x)
-#define OUTCONTROL1_BFTH(x) SET_BITS(23, 20, x)
-#define OUTCONTROL1_OF(x) SET_BITS(19, 18, x)
-#define OUTCONTROL1_IPM(x) SET_BITS(17, 16, x)
-#define OUTCONTROL1_TH(x) SET_BITS(5, 0, x)
-#endif
-
-#if DMIC_HW_VERSION == 2
-/* OUTCONTROL0 bits */
-#define OUTCONTROL0_TIE_BIT BIT(27)
-#define OUTCONTROL0_SIP_BIT BIT(26)
-#define OUTCONTROL0_FINIT_BIT BIT(25)
-#define OUTCONTROL0_FCI_BIT BIT(24)
-#define OUTCONTROL0_TIE(x) SET_BIT(27, x)
-#define OUTCONTROL0_SIP(x) SET_BIT(26, x)
-#define OUTCONTROL0_FINIT(x) SET_BIT(25, x)
-#define OUTCONTROL0_FCI(x) SET_BIT(24, x)
-#define OUTCONTROL0_BFTH(x) SET_BITS(23, 20, x)
-#define OUTCONTROL0_OF(x) SET_BITS(19, 18, x)
-#define OUTCONTROL0_IPM(x) SET_BITS(17, 15, x)
-#define OUTCONTROL0_IPM_SOURCE_1(x) SET_BITS(14, 13, x)
-#define OUTCONTROL0_IPM_SOURCE_2(x) SET_BITS(12, 11, x)
-#define OUTCONTROL0_IPM_SOURCE_3(x) SET_BITS(10, 9, x)
-#define OUTCONTROL0_IPM_SOURCE_4(x) SET_BITS(8, 7, x)
-#define OUTCONTROL0_TH(x) SET_BITS(5, 0, x)
-
-/* OUTCONTROL1 bits */
-#define OUTCONTROL1_TIE_BIT BIT(27)
-#define OUTCONTROL1_SIP_BIT BIT(26)
-#define OUTCONTROL1_FINIT_BIT BIT(25)
-#define OUTCONTROL1_FCI_BIT BIT(24)
-#define OUTCONTROL1_TIE(x) SET_BIT(27, x)
-#define OUTCONTROL1_SIP(x) SET_BIT(26, x)
-#define OUTCONTROL1_FINIT(x) SET_BIT(25, x)
-#define OUTCONTROL1_FCI(x) SET_BIT(24, x)
-#define OUTCONTROL1_BFTH(x) SET_BITS(23, 20, x)
-#define OUTCONTROL1_OF(x) SET_BITS(19, 18, x)
-#define OUTCONTROL1_IPM(x) SET_BITS(17, 15, x)
-#define OUTCONTROL1_IPM_SOURCE_1(x) SET_BITS(14, 13, x)
-#define OUTCONTROL1_IPM_SOURCE_2(x) SET_BITS(12, 11, x)
-#define OUTCONTROL1_IPM_SOURCE_3(x) SET_BITS(10, 9, x)
-#define OUTCONTROL1_IPM_SOURCE_4(x) SET_BITS(8, 7, x)
-#define OUTCONTROL1_TH(x) SET_BITS(5, 0, x)
-#endif
-
-/* OUTSTAT0 bits */
-#define OUTSTAT0_AFE_BIT BIT(31)
-#define OUTSTAT0_ASNE_BIT BIT(29)
-#define OUTSTAT0_RFS_BIT BIT(28)
-#define OUTSTAT0_ROR_BIT BIT(27)
-#define OUTSTAT0_FL_MASK MASK(6, 0)
-
-/* OUTSTAT1 bits */
-#define OUTSTAT1_AFE_BIT BIT(31)
-#define OUTSTAT1_ASNE_BIT BIT(29)
-#define OUTSTAT1_RFS_BIT BIT(28)
-#define OUTSTAT1_ROR_BIT BIT(27)
-#define OUTSTAT1_FL_MASK MASK(6, 0)
-
-/* CIC_CONTROL bits */
-#define CIC_CONTROL_SOFT_RESET_BIT BIT(16)
-#define CIC_CONTROL_CIC_START_B_BIT BIT(15)
-#define CIC_CONTROL_CIC_START_A_BIT BIT(14)
-#define CIC_CONTROL_MIC_B_POLARITY_BIT BIT(3)
-#define CIC_CONTROL_MIC_A_POLARITY_BIT BIT(2)
-#define CIC_CONTROL_MIC_MUTE_BIT BIT(1)
-#define CIC_CONTROL_STEREO_MODE_BIT BIT(0)
-
-#define CIC_CONTROL_SOFT_RESET(x) SET_BIT(16, x)
-#define CIC_CONTROL_CIC_START_B(x) SET_BIT(15, x)
-#define CIC_CONTROL_CIC_START_A(x) SET_BIT(14, x)
-#define CIC_CONTROL_MIC_B_POLARITY(x) SET_BIT(3, x)
-#define CIC_CONTROL_MIC_A_POLARITY(x) SET_BIT(2, x)
-#define CIC_CONTROL_MIC_MUTE(x) SET_BIT(1, x)
-#define CIC_CONTROL_STEREO_MODE(x) SET_BIT(0, x)
-
-/* CIC_CONFIG bits */
-#define CIC_CONFIG_CIC_SHIFT(x) SET_BITS(27, 24, x)
-#define CIC_CONFIG_COMB_COUNT(x) SET_BITS(15, 8, x)
-
-/* MIC_CONTROL bits */
-#define MIC_CONTROL_PDM_EN_B_BIT BIT(1)
-#define MIC_CONTROL_PDM_EN_A_BIT BIT(0)
-#define MIC_CONTROL_PDM_CLKDIV(x) SET_BITS(15, 8, x)
-#define MIC_CONTROL_PDM_SKEW(x) SET_BITS(7, 4, x)
-#define MIC_CONTROL_CLK_EDGE(x) SET_BIT(3, x)
-#define MIC_CONTROL_PDM_EN_B(x) SET_BIT(1, x)
-#define MIC_CONTROL_PDM_EN_A(x) SET_BIT(0, x)
-
-/* FIR_CONTROL_A bits */
-#define FIR_CONTROL_A_START_BIT BIT(7)
-#define FIR_CONTROL_A_ARRAY_START_EN_BIT BIT(6)
-#define FIR_CONTROL_A_MUTE_BIT BIT(1)
-#define FIR_CONTROL_A_START(x) SET_BIT(7, x)
-#define FIR_CONTROL_A_ARRAY_START_EN(x) SET_BIT(6, x)
-#define FIR_CONTROL_A_DCCOMP(x) SET_BIT(4, x)
-#define FIR_CONTROL_A_MUTE(x) SET_BIT(1, x)
-#define FIR_CONTROL_A_STEREO(x) SET_BIT(0, x)
-
-/* FIR_CONFIG_A bits */
-#define FIR_CONFIG_A_FIR_DECIMATION(x) SET_BITS(20, 16, x)
-#define FIR_CONFIG_A_FIR_SHIFT(x) SET_BITS(11, 8, x)
-#define FIR_CONFIG_A_FIR_LENGTH(x) SET_BITS(7, 0, x)
-
-/* DC offset compensation time constants */
-#define DCCOMP_TC0 0
-#define DCCOMP_TC1 1
-#define DCCOMP_TC2 2
-#define DCCOMP_TC3 3
-#define DCCOMP_TC4 4
-#define DCCOMP_TC5 5
-#define DCCOMP_TC6 6
-#define DCCOMP_TC7 7
-
-/* DC_OFFSET_LEFT_A bits */
-#define DC_OFFSET_LEFT_A_DC_OFFS(x) SET_BITS(21, 0, x)
-
-/* DC_OFFSET_RIGHT_A bits */
-#define DC_OFFSET_RIGHT_A_DC_OFFS(x) SET_BITS(21, 0, x)
-
-/* OUT_GAIN_LEFT_A bits */
-#define OUT_GAIN_LEFT_A_GAIN(x) SET_BITS(19, 0, x)
-
-/* OUT_GAIN_RIGHT_A bits */
-#define OUT_GAIN_RIGHT_A_GAIN(x) SET_BITS(19, 0, x)
-
-/* FIR_CONTROL_B bits */
-#define FIR_CONTROL_B_START_BIT BIT(7)
-#define FIR_CONTROL_B_ARRAY_START_EN_BIT BIT(6)
-#define FIR_CONTROL_B_MUTE_BIT BIT(1)
-#define FIR_CONTROL_B_START(x) SET_BIT(7, x)
-#define FIR_CONTROL_B_ARRAY_START_EN(x) SET_BIT(6, x)
-#define FIR_CONTROL_B_DCCOMP(x) SET_BIT(4, x)
-#define FIR_CONTROL_B_MUTE(x) SET_BIT(1, x)
-#define FIR_CONTROL_B_STEREO(x) SET_BIT(0, x)
-
-/* FIR_CONFIG_B bits */
-#define FIR_CONFIG_B_FIR_DECIMATION(x) SET_BITS(20, 16, x)
-#define FIR_CONFIG_B_FIR_SHIFT(x) SET_BITS(11, 8, x)
-#define FIR_CONFIG_B_FIR_LENGTH(x) SET_BITS(7, 0, x)
-
-/* DC_OFFSET_LEFT_B bits */
-#define DC_OFFSET_LEFT_B_DC_OFFS(x) SET_BITS(21, 0, x)
-
-/* DC_OFFSET_RIGHT_B bits */
-#define DC_OFFSET_RIGHT_B_DC_OFFS(x) SET_BITS(21, 0, x)
-
-/* OUT_GAIN_LEFT_B bits */
-#define OUT_GAIN_LEFT_B_GAIN(x) SET_BITS(19, 0, x)
-
-/* OUT_GAIN_RIGHT_B bits */
-#define OUT_GAIN_RIGHT_B_GAIN(x) SET_BITS(19, 0, x)
-
-/* FIR coefficients */
-#define FIR_COEF_A(x) SET_BITS(19, 0, x)
-#define FIR_COEF_B(x) SET_BITS(19, 0, x)
-
-#define dmic_irq(dmic) \
- dmic->plat_data.irq
-
-/* DMIC private data */
-struct dmic_pdata {
- spinlock_t lock; /* Spinlock that's used in registers IO */
- uint16_t fifo_a;
- uint16_t fifo_b;
- uint16_t enable[DMIC_HW_CONTROLLERS];
- uint32_t state;
- completion_t drain_complete;
- struct sof_ipc_dai_config config;
- struct sof_ipc_dai_dmic_params params;
- struct work dmicwork;
- int32_t startcount;
- int32_t gain;
-};
-
-extern const struct dai_ops dmic_ops;
-
-#endif /* DMIC_HW_VERSION */
-#endif /* __INCLUDE_DMIC__ */
diff --git a/src/include/sof/dw-dma.h b/src/include/sof/dw-dma.h
deleted file mode 100644
index 90c4553..0000000
--- a/src/include/sof/dw-dma.h
+++ /dev/null
@@ -1,71 +0,0 @@
-/*
- * Copyright (c) 2016, Intel Corporation
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- * * Redistributions of source code must retain the above copyright
- * notice, this list of conditions and the following disclaimer.
- * * Redistributions in binary form must reproduce the above copyright
- * notice, this list of conditions and the following disclaimer in the
- * documentation and/or other materials provided with the distribution.
- * * Neither the name of the Intel Corporation nor the
- * names of its contributors may be used to endorse or promote products
- * derived from this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
- * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
- * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
- * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
- * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
- * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
- * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
- * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
- * POSSIBILITY OF SUCH DAMAGE.
- *
- * Author: Liam Girdwood <liam.r.girdwood@linux.intel.com>
- * Keyon Jie <yang.jie@linux.intel.com>
- */
-
-#ifndef __SOF_DW_DMA_H__
-#define __SOF_DW_DMA_H__
-
-#include <stdint.h>
-
-#define DW_DMA_MAX_NR_CHANNELS 8
-
-/* TODO: add FIFO sizes */
-struct dw_chan_data {
- uint16_t class;
- uint16_t weight;
-};
-
-struct dw_drv_plat_data {
- struct dw_chan_data chan[DW_DMA_MAX_NR_CHANNELS];
-};
-
-/* DMA descriptor used by the HW version 1 */
-struct dw_lli1 {
- uint32_t sar;
- uint32_t dar;
- uint32_t llp;
- uint32_t ctrl_lo;
- uint32_t ctrl_hi;
-} __attribute__ ((packed));
-
-/* DMA descriptor used by HW version 2 */
-struct dw_lli2 {
- uint32_t sar;
- uint32_t dar;
- uint32_t llp;
- uint32_t ctrl_lo;
- uint32_t ctrl_hi;
- uint32_t sstat;
- uint32_t dstat;
-} __attribute__ ((packed));
-
-extern const struct dma_ops dw_dma_ops;
-
-#endif
diff --git a/src/include/sof/hda-dma.h b/src/include/sof/hda-dma.h
deleted file mode 100644
index 5fb8fa5..0000000
--- a/src/include/sof/hda-dma.h
+++ /dev/null
@@ -1,38 +0,0 @@
-/*
- * Copyright (c) 2017, Intel Corporation
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- * * Redistributions of source code must retain the above copyright
- * notice, this list of conditions and the following disclaimer.
- * * Redistributions in binary form must reproduce the above copyright
- * notice, this list of conditions and the following disclaimer in the
- * documentation and/or other materials provided with the distribution.
- * * Neither the name of the Intel Corporation nor the
- * names of its contributors may be used to endorse or promote products
- * derived from this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
- * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
- * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
- * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
- * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
- * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
- * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
- * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
- * POSSIBILITY OF SUCH DAMAGE.
- *
- * Author: Keyon Jie <yang.jie@linux.intel.com>
- * Rander Wang <rander.wang@intel.com>
- */
-
-#ifndef __INCLUDE_HDA_DMA_H__
-#define __INCLUDE_HDA_DMA_H__
-
-extern const struct dma_ops hda_host_dma_ops;
-extern const struct dma_ops hda_link_dma_ops;
-
-#endif
diff --git a/src/include/sof/init.h b/src/include/sof/init.h
deleted file mode 100644
index f9e4405..0000000
--- a/src/include/sof/init.h
+++ /dev/null
@@ -1,45 +0,0 @@
-/*
- * Copyright (c) 2016, Intel Corporation
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- * * Redistributions of source code must retain the above copyright
- * notice, this list of conditions and the following disclaimer.
- * * Redistributions in binary form must reproduce the above copyright
- * notice, this list of conditions and the following disclaimer in the
- * documentation and/or other materials provided with the distribution.
- * * Neither the name of the Intel Corporation nor the
- * names of its contributors may be used to endorse or promote products
- * derived from this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
- * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
- * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
- * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
- * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
- * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
- * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
- * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
- * POSSIBILITY OF SUCH DAMAGE.
- *
- * Author: Liam Girdwood <liam.r.girdwood@linux.intel.com>
- */
-
-#ifndef __INCLUDE_INIT_H__
-#define __INCLUDE_INIT_H__
-
-struct sof;
-
-/* main firmware entry point - argc and argv not currently used */
-int main(int argc, char *argv[]);
-
-int master_core_init(struct sof *sof);
-
-int slave_core_init(struct sof *sof);
-
-int arch_init(struct sof *sof);
-
-#endif
diff --git a/src/include/sof/intel-ipc.h b/src/include/sof/intel-ipc.h
deleted file mode 100644
index a59c106..0000000
--- a/src/include/sof/intel-ipc.h
+++ /dev/null
@@ -1,48 +0,0 @@
-/*
- * Copyright (c) 2016, Intel Corporation
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- * * Redistributions of source code must retain the above copyright
- * notice, this list of conditions and the following disclaimer.
- * * Redistributions in binary form must reproduce the above copyright
- * notice, this list of conditions and the following disclaimer in the
- * documentation and/or other materials provided with the distribution.
- * * Neither the name of the Intel Corporation nor the
- * names of its contributors may be used to endorse or promote products
- * derived from this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
- * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
- * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
- * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
- * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
- * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
- * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
- * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
- * POSSIBILITY OF SUCH DAMAGE.
- *
- * Author: Liam Girdwood <liam.r.girdwood@linux.intel.com>
- */
-
-#ifndef __INCLUDE_INTEL_IPC_H__
-#define __INCLUDE_INTEL_IPC_H__
-
-#include <stdint.h>
-
-/* private data for IPC */
-struct intel_ipc_data {
- /* DMA */
- struct dma *dmac;
- uint8_t *page_table;
-
- /* PM */
- int pm_prepare_D3; /* do we need to prepare for D3 */
-};
-
-int ipc_cmd(void);
-
-#endif
diff --git a/src/include/sof/interrupt-map.h b/src/include/sof/interrupt-map.h
deleted file mode 100644
index cec85df..0000000
--- a/src/include/sof/interrupt-map.h
+++ /dev/null
@@ -1,95 +0,0 @@
-/*
- * Copyright (c) 2016, Intel Corporation
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- * * Redistributions of source code must retain the above copyright
- * notice, this list of conditions and the following disclaimer.
- * * Redistributions in binary form must reproduce the above copyright
- * notice, this list of conditions and the following disclaimer in the
- * documentation and/or other materials provided with the distribution.
- * * Neither the name of the Intel Corporation nor the
- * names of its contributors may be used to endorse or promote products
- * derived from this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
- * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
- * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
- * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
- * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
- * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
- * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
- * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
- * POSSIBILITY OF SUCH DAMAGE.
- *
- * Author: Liam Girdwood <liam.r.girdwood@linux.intel.com>
- */
-
-#ifndef __INCLUDE_INTERRUPT_MAP__
-#define __INCLUDE_INTERRUPT_MAP__
-
-#include <config.h>
-
-#define SOF_IRQ_ID_SHIFT 29
-#define SOF_IRQ_BIT_SHIFT 24
-#define SOF_IRQ_LEVEL_SHIFT 16
-#define SOF_IRQ_CPU_SHIFT 8
-#define SOF_IRQ_NUM_SHIFT 0
-#define SOF_IRQ_NUM_MASK 0xff
-#define SOF_IRQ_LEVEL_MASK 0xff
-#define SOF_IRQ_BIT_MASK 0x1f
-#define SOF_IRQ_CPU_MASK 0xff
-#define SOF_IRQ_ID_MASK 0x7
-
-#define SOF_IRQ(_bit, _level, _cpu, _number) \
- (((_bit) << SOF_IRQ_BIT_SHIFT) \
- | ((_level) << SOF_IRQ_LEVEL_SHIFT) \
- | ((_cpu) << SOF_IRQ_CPU_SHIFT) \
- | ((_number) << SOF_IRQ_NUM_SHIFT))
-
-/*
- * for chip CNL or later, a group of HW IP(GP-DMA) share
- * the same IRQ. So add id in IRQ to identify each HW IP
- * for this case, it will be 5 levels
- */
-#define SOF_ID_IRQ(_id, _bit, _level, _cpu, _number) \
- (((_id) << SOF_IRQ_ID_SHIFT) \
- | ((_bit) << SOF_IRQ_BIT_SHIFT) \
- | ((_level) << SOF_IRQ_LEVEL_SHIFT) \
- | ((_cpu) << SOF_IRQ_CPU_SHIFT) \
- | ((_number) << SOF_IRQ_NUM_SHIFT))
-
-#ifdef CONFIG_IRQ_MAP
-/*
- * IRQs are mapped on 4 levels.
- *
- * 1. Peripheral Register bit offset.
- * 2. CPU interrupt level.
- * 3. CPU number.
- * 4. CPU interrupt number.
- */
-#define SOF_IRQ_NUMBER(_irq) \
- (((_irq) >> SOF_IRQ_NUM_SHIFT) & SOF_IRQ_NUM_MASK)
-#define SOF_IRQ_LEVEL(_level) \
- (((_level) >> SOF_IRQ_LEVEL_SHIFT) & SOF_IRQ_LEVEL_MASK)
-#define SOF_IRQ_BIT(_bit) \
- (((_bit) >> SOF_IRQ_BIT_SHIFT) & SOF_IRQ_BIT_MASK)
-#define SOF_IRQ_CPU(_cpu) \
- (((_cpu) >> SOF_IRQ_CPU_SHIFT) & SOF_IRQ_CPU_MASK)
-#define SOF_IRQ_ID(_bit) \
- (((_bit) >> SOF_IRQ_ID_SHIFT) & SOF_IRQ_ID_MASK)
-#else
-/*
- * IRQs are directly mapped onto a single level, bit and level.
- */
-#define SOF_IRQ_NUMBER(_irq) (_irq)
-#define SOF_IRQ_LEVEL(_level) 0
-#define SOF_IRQ_BIT(_bit) 0
-#define SOF_IRQ_CPU(_cpu) 0
-#define SOF_IRQ_ID(_bit) 0
-#endif
-
-#endif
diff --git a/src/include/sof/interrupt.h b/src/include/sof/interrupt.h
deleted file mode 100644
index bbda635..0000000
--- a/src/include/sof/interrupt.h
+++ /dev/null
@@ -1,91 +0,0 @@
-/*
- * Copyright (c) 2016, Intel Corporation
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- * * Redistributions of source code must retain the above copyright
- * notice, this list of conditions and the following disclaimer.
- * * Redistributions in binary form must reproduce the above copyright
- * notice, this list of conditions and the following disclaimer in the
- * documentation and/or other materials provided with the distribution.
- * * Neither the name of the Intel Corporation nor the
- * names of its contributors may be used to endorse or promote products
- * derived from this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
- * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
- * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
- * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
- * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
- * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
- * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
- * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
- * POSSIBILITY OF SUCH DAMAGE.
- *
- * Author: Liam Girdwood <liam.r.girdwood@linux.intel.com>
- */
-
-#ifndef __INCLUDE_INTERRUPT__
-#define __INCLUDE_INTERRUPT__
-
-#include <stdint.h>
-#include <arch/interrupt.h>
-#include <platform/interrupt.h>
-#include <sof/trace.h>
-#include <sof/debug.h>
-#include <sof/lock.h>
-#include <sof/list.h>
-
-#define trace_irq(__e) trace_event(TRACE_CLASS_IRQ, __e)
-#define trace_irq_error(__e) trace_error(TRACE_CLASS_IRQ, __e)
-
-struct irq_desc {
- /* irq must be first for constructor */
- int irq; /* logical IRQ number */
-
- /* handler is optional for constructor */
- void (*handler)(void *arg);
- void *handler_arg;
-
- /* to identify interrupt with the same IRQ */
- int id;
- spinlock_t lock;
- uint32_t enabled_count;
-
- /* to link to other irq_desc */
- struct list_item irq_list;
-
- uint32_t num_children;
- struct list_item child[PLATFORM_IRQ_CHILDREN];
-};
-
-int interrupt_register(uint32_t irq,
- void(*handler)(void *arg), void *arg);
-void interrupt_unregister(uint32_t irq);
-uint32_t interrupt_enable(uint32_t irq);
-uint32_t interrupt_disable(uint32_t irq);
-
-static inline void interrupt_set(int irq)
-{
- arch_interrupt_set(SOF_IRQ_NUMBER(irq));
-}
-
-static inline void interrupt_clear(int irq)
-{
- arch_interrupt_clear(SOF_IRQ_NUMBER(irq));
-}
-
-static inline uint32_t interrupt_global_disable(void)
-{
- return arch_interrupt_global_disable();
-}
-
-static inline void interrupt_global_enable(uint32_t flags)
-{
- arch_interrupt_global_enable(flags);
-}
-
-#endif
diff --git a/src/include/sof/io.h b/src/include/sof/io.h
deleted file mode 100644
index 07acc80..0000000
--- a/src/include/sof/io.h
+++ /dev/null
@@ -1,62 +0,0 @@
-/*
- * Copyright (c) 2016, Intel Corporation
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- * * Redistributions of source code must retain the above copyright
- * notice, this list of conditions and the following disclaimer.
- * * Redistributions in binary form must reproduce the above copyright
- * notice, this list of conditions and the following disclaimer in the
- * documentation and/or other materials provided with the distribution.
- * * Neither the name of the Intel Corporation nor the
- * names of its contributors may be used to endorse or promote products
- * derived from this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
- * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
- * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
- * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
- * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
- * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
- * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
- * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
- * POSSIBILITY OF SUCH DAMAGE.
- *
- * Author: Liam Girdwood <liam.r.girdwood@linux.intel.com>
- */
-
-#ifndef __INCLUDE_IO__
-#define __INCLUDE_IO__
-
-#include <stdint.h>
-#include <sof/bit.h>
-
-static inline uint32_t io_reg_read(uint32_t reg)
-{
- return *((volatile uint32_t*)reg);
-}
-
-static inline void io_reg_write(uint32_t reg, uint32_t val)
-{
- *((volatile uint32_t*)reg) = val;
-}
-
-static inline void io_reg_update_bits(uint32_t reg, uint32_t mask, uint32_t value)
-{
- io_reg_write(reg, (io_reg_read(reg) & (~mask)) | (value & mask));
-}
-
-static inline uint16_t io_reg_read16(uint32_t reg)
-{
- return *((volatile uint16_t*)reg);
-}
-
-static inline void io_reg_write16(uint32_t reg, uint16_t val)
-{
- *((volatile uint16_t*)reg) = val;
-}
-
-#endif
diff --git a/src/include/sof/ipc.h b/src/include/sof/ipc.h
deleted file mode 100644
index 06425b3..0000000
--- a/src/include/sof/ipc.h
+++ /dev/null
@@ -1,185 +0,0 @@
-/*
- * Copyright (c) 2016, Intel Corporation
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- * * Redistributions of source code must retain the above copyright
- * notice, this list of conditions and the following disclaimer.
- * * Redistributions in binary form must reproduce the above copyright
- * notice, this list of conditions and the following disclaimer in the
- * documentation and/or other materials provided with the distribution.
- * * Neither the name of the Intel Corporation nor the
- * names of its contributors may be used to endorse or promote products
- * derived from this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
- * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
- * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
- * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
- * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
- * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
- * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
- * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
- * POSSIBILITY OF SUCH DAMAGE.
- *
- * Author: Liam Girdwood <liam.r.girdwood@linux.intel.com>
- * Keyon Jie <yang.jie@linux.intel.com>
- */
-
-#ifndef __INCLUDE_IPC_H__
-#define __INCLUDE_IPC_H__
-
-#include <stdint.h>
-#include <sof/trace.h>
-#include <sof/dai.h>
-#include <sof/lock.h>
-#include <platform/platform.h>
-#include <uapi/ipc.h>
-#include <sof/audio/pipeline.h>
-#include <sof/audio/component.h>
-#include <sof/dma-trace.h>
-
-struct sof;
-struct dai_config;
-
-#define trace_ipc(__e) trace_event(TRACE_CLASS_IPC, __e)
-#define tracev_ipc(__e) tracev_event(TRACE_CLASS_IPC, __e)
-#define trace_ipc_error(__e) trace_error(TRACE_CLASS_IPC, __e)
-
-#define MSG_QUEUE_SIZE 12
-
-#define COMP_TYPE_COMPONENT 1
-#define COMP_TYPE_BUFFER 2
-#define COMP_TYPE_PIPELINE 3
-
-/* IPC generic component device */
-struct ipc_comp_dev {
- uint16_t type; /* COMP_TYPE_ */
- uint16_t state;
-
- /* component type data */
- union {
- struct comp_dev *cd;
- struct comp_buffer *cb;
- struct pipeline *pipeline;
- };
-
- /* lists */
- struct list_item list; /* list in components */
-};
-
-struct ipc_msg {
- uint32_t header; /* specific to platform */
- uint32_t tx_size; /* payload size in bytes */
- uint8_t tx_data[SOF_IPC_MSG_MAX_SIZE]; /* pointer to payload data */
- uint32_t rx_size; /* payload size in bytes */
- uint8_t rx_data[SOF_IPC_MSG_MAX_SIZE]; /* pointer to payload data */
- struct list_item list;
- void (*cb)(void *cb_data, void *mailbox_data);
- void *cb_data;
-};
-
-struct ipc {
- /* messaging */
- uint32_t host_msg; /* current message from host */
- struct ipc_msg *dsp_msg; /* current message to host */
- uint32_t host_pending;
- uint32_t dsp_pending;
- struct list_item msg_list;
- struct list_item empty_list;
- spinlock_t lock;
- struct ipc_msg message[MSG_QUEUE_SIZE];
- void *comp_data;
-
- /* RX call back */
- int (*cb)(struct ipc_msg *msg);
-
- /* pipelines, components and buffers */
- struct list_item comp_list; /* list of component devices */
-
- /* DMA for Trace*/
- struct dma_trace_data *dmat;
-
- /* mmap for posn_offset */
- struct pipeline *posn_map[PLATFORM_MAX_STREAMS];
-
- void *private;
-};
-
-#define ipc_set_drvdata(ipc, data) \
- (ipc)->private = data
-#define ipc_get_drvdata(ipc) \
- (ipc)->private;
-
-
-int ipc_init(struct sof *sof);
-int platform_ipc_init(struct ipc *ipc);
-void ipc_free(struct ipc *ipc);
-
-int ipc_process_msg_queue(void);
-
-int ipc_stream_send_position(struct comp_dev *cdev,
- struct sof_ipc_stream_posn *posn);
-int ipc_stream_send_xrun(struct comp_dev *cdev,
- struct sof_ipc_stream_posn *posn);
-
-int ipc_queue_host_message(struct ipc *ipc, uint32_t header,
- void *tx_data, size_t tx_bytes, void *rx_data,
- size_t rx_bytes, void (*cb)(void*, void*), void *cb_data, uint32_t replace);
-int ipc_send_short_msg(uint32_t msg);
-
-void ipc_platform_do_cmd(struct ipc *ipc);
-void ipc_platform_send_msg(struct ipc *ipc);
-
-/* create a SG page table eme list from a compressed page table */
-int ipc_parse_page_descriptors(uint8_t *page_table,
- struct sof_ipc_host_buffer *ring,
- struct list_item *elem_list,
- uint32_t direction);
-int ipc_get_page_descriptors(struct dma *dmac, uint8_t *page_table,
- struct sof_ipc_host_buffer *ring);
-
-/*
- * IPC Component creation and destruction.
- */
-int ipc_comp_new(struct ipc *ipc, struct sof_ipc_comp *new);
-int ipc_comp_free(struct ipc *ipc, uint32_t comp_id);
-
-/*
- * IPC Buffer creation and destruction.
- */
-int ipc_buffer_new(struct ipc *ipc, struct sof_ipc_buffer *buffer);
-int ipc_buffer_free(struct ipc *ipc, uint32_t buffer_id);
-
-/*
- * IPC Pipeline creation and destruction.
- */
-int ipc_pipeline_new(struct ipc *ipc, struct sof_ipc_pipe_new *pipeline);
-int ipc_pipeline_free(struct ipc *ipc, uint32_t comp_id);
-int ipc_pipeline_complete(struct ipc *ipc, uint32_t comp_id);
-
-/*
- * Pipeline component and buffer connections.
- */
-int ipc_comp_connect(struct ipc *ipc,
- struct sof_ipc_pipe_comp_connect *connect);
-
-/*
- * Get component by ID.
- */
-struct ipc_comp_dev *ipc_get_comp(struct ipc *ipc, uint32_t id);
-
-/*
- * Configure all DAI components attached to DAI.
- */
-int ipc_comp_dai_config(struct ipc *ipc, struct sof_ipc_dai_config *config);
-
-/* send DMA trace host buffer position to host */
-int ipc_dma_trace_send_position(void);
-
-/* get posn offset by pipeline. */
-int ipc_get_posn_offset(struct ipc *ipc, struct pipeline *pipe);
-#endif
diff --git a/src/include/sof/list.h b/src/include/sof/list.h
deleted file mode 100644
index 15bb266..0000000
--- a/src/include/sof/list.h
+++ /dev/null
@@ -1,122 +0,0 @@
-/*
- * Copyright (c) 2016, Intel Corporation
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- * * Redistributions of source code must retain the above copyright
- * notice, this list of conditions and the following disclaimer.
- * * Redistributions in binary form must reproduce the above copyright
- * notice, this list of conditions and the following disclaimer in the
- * documentation and/or other materials provided with the distribution.
- * * Neither the name of the Intel Corporation nor the
- * names of its contributors may be used to endorse or promote products
- * derived from this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
- * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
- * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
- * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
- * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
- * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
- * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
- * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
- * POSSIBILITY OF SUCH DAMAGE.
- *
- * Author: Liam Girdwood <liam.r.girdwood@linux.intel.com>
- * Keyon Jie <yang.jie@linux.intel.com>
- */
-
-#ifndef __INCLUDE_LIST__
-#define __INCLUDE_LIST__
-
-/* Really simple list manipulation */
-
-struct list_item;
-
-struct list_item {
- struct list_item *next;
- struct list_item *prev;
-};
-
-/* initialise list before any use - list will point to itself */
-static inline void list_init(struct list_item *list)
-{
- list->next = list;
- list->prev = list;
-}
-
-/* add new item to the start or head of the list */
-static inline void list_item_prepend(struct list_item *item,
- struct list_item *list)
-{
- struct list_item *next = list->next;
-
- next->prev = item;
- item->next = next;
- item->prev = list;
- list->next = item;
-}
-
-/* add new item to the end or tail of the list */
-static inline void list_item_append(struct list_item *item,
- struct list_item *list)
-{
- struct list_item *tail = list->prev;
-
- tail->next = item;
- item->next = list;
- item->prev = tail;
- list->prev = item;
-}
-
-/* delete item from the list */
-static inline void list_item_del(struct list_item *item)
-{
- item->next->prev = item->prev;
- item->prev->next = item->next;
-}
-
-/* is list item the last item in list ? */
-static inline int list_item_is_last(struct list_item *item,
- struct list_item *list)
-{
- return item->next == list;
-}
-
-/* is list empty ? */
-#define list_is_empty(item) \
- ((item)->next == item)
-
-#define __list_object(item, type, offset) \
- ((type *)((char *)(item) - (offset)))
-
-/* get the container object of the list item */
-#define list_item(item, type, member) \
- __list_object(item, type, offsetof(type, member))
-
-/* get the container object of the first item in the list */
-#define list_first_item(list, type, member) \
- __list_object((list)->next, type, offsetof(type, member))
-
-/* get the next container object in the list */
-#define list_next_item(object, member) \
- list_item((object)->member.next, typeof(*(object)), member)
-
-/* list iterator */
-#define list_for_item(item, list) \
- for (item = (list)->next; item != (list); item = item->next)
-
-/* list iterator */
-#define list_for_item_prev(item, list) \
- for (item = (list)->prev; item != (list); item = item->prev)
-
-/* list iterator - safe to delete items */
-#define list_for_item_safe(item, tmp, list) \
- for (item = (list)->next, tmp = item->next;\
- item != (list); \
- item = tmp, tmp = item->next)
-
-#endif
diff --git a/src/include/sof/lock.h b/src/include/sof/lock.h
deleted file mode 100644
index a6c9d14..0000000
--- a/src/include/sof/lock.h
+++ /dev/null
@@ -1,213 +0,0 @@
-/*
- * Copyright (c) 2016, Intel Corporation
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- * * Redistributions of source code must retain the above copyright
- * notice, this list of conditions and the following disclaimer.
- * * Redistributions in binary form must reproduce the above copyright
- * notice, this list of conditions and the following disclaimer in the
- * documentation and/or other materials provided with the distribution.
- * * Neither the name of the Intel Corporation nor the
- * names of its contributors may be used to endorse or promote products
- * derived from this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
- * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
- * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
- * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
- * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
- * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
- * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
- * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
- * POSSIBILITY OF SUCH DAMAGE.
- *
- * Author: Liam Girdwood <liam.r.girdwood@linux.intel.com>
- * Keyon Jie <yang.jie@linux.intel.com>
- *
- * Simple spinlock implementation for SOF.
- */
-
-#ifndef __INCLUDE_LOCK__
-#define __INCLUDE_LOCK__
-
-#define DEBUG_LOCKS 0
-#define DEBUG_LOCKS_VERBOSE 0
-
-#include <stdint.h>
-#include <arch/spinlock.h>
-#include <sof/interrupt.h>
-#include <sof/trace.h>
-
-/*
- * Lock debugging provides a simple interface to debug deadlocks. The rmbox
- * trace output will show an output :-
- *
- * 0xd70 [41.306406] delta [0.359638] lock eal
- * 0xd80 [41.306409] delta [0.000002] value 0x00000000000001b7
- * 0xd90 [41.306411] delta [0.000002] value 0x0000000000000001
- * 0xda0 [41.306413] delta [0.000002] value 0x0000000001000348
- *
- * "eal" indicates we are holding a lock with interrupts OFF. The next value
- * is the line number of where the lock was aquired. The second number is the
- * number of other locks held whilst this lock is held and the subsequent
- * numbers list each lock and the line number of it's holder. e.g. to find
- * the locks :-
- *
- * grep -rn lock --include *.c | grep 840 (search for lock at line 0x348)
- * src/drivers/dw-dma.c:840: spinlock_init(&dma->lock);
- *
- * grep -rn lock --include *.c | grep 439
- * src/lib/alloc.c:439: spin_lock_irq(&memmap.lock, flags);
- *
- * Every lock entry and exit shows LcE and LcX in trace alongside the lock
- * line numbers in hex. e.g.
- *
- * 0xfd60 [11032.730567] delta [0.000004] lock LcE
- * 0xfd70 [11032.730569] delta [0.000002] value 0x00000000000000ae
- *
- * Deadlock can be confirmed in rmbox :-
- *
- * Debug log:
- * debug: 0x0 (00) = 0xdead0007 (-559087609) |....|
- * ....
- * Error log:
- * using 19.20MHz timestamp clock
- * 0xc30 [26.247240] delta [26.245851] lock DED
- * 0xc40 [26.247242] delta [0.000002] value 0x00000000000002b4
- * 0xc50 [26.247244] delta [0.000002] value 0x0000000000000109
- *
- * DED means deadlock has been detected and the DSP is now halted. The first
- * value after DEA is the line number where deadlock occurs and the second
- * number is the line number where the lock is allocated. These can be grepped
- * like above.
- */
-
-#if DEBUG_LOCKS
-
-#define DBG_LOCK_USERS 8
-#define DBG_LOCK_TRIES 10000
-
-#define trace_lock(__e) trace_error_atomic(TRACE_CLASS_LOCK, __e)
-#define tracev_lock(__e) tracev_event_atomic(TRACE_CLASS_LOCK, __e)
-#define trace_lock_error(__e) trace_error_atomic(TRACE_CLASS_LOCK, __e)
-#define trace_lock_value(__e) _trace_error_atomic(__e)
-
-extern uint32_t lock_dbg_atomic;
-extern uint32_t lock_dbg_user[DBG_LOCK_USERS];
-
-/* all SMP spinlocks need init, nothing todo on UP */
-#define spinlock_init(lock) \
- arch_spinlock_init(lock); \
- (lock)->user = __LINE__;
-
-/* panic on deadlock */
-#define spin_try_lock_dbg(lock) \
- do { \
- int __tries; \
- for (__tries = DBG_LOCK_TRIES; __tries > 0; __tries--) { \
- if (arch_try_lock(lock)) \
- break; /* lock acquired */ \
- } \
- if (__tries == 0) { \
- trace_lock_error("DED"); \
- trace_lock_value(__LINE__); \
- trace_lock_value((lock)->user); \
- panic(SOF_IPC_PANIC_DEADLOCK); /* lock not acquired */ \
- } \
- } while (0);
-
-#if DEBUG_LOCKS_VERBOSE
-#define spin_lock_log(lock) \
- if (lock_dbg_atomic) { \
- int __i = 0; \
- int __count = lock_dbg_atomic >= DBG_LOCK_USERS \
- ? DBG_LOCK_USERS : lock_dbg_atomic; \
- trace_lock_error("eal"); \
- trace_lock_value(__LINE__); \
- trace_lock_value(lock_dbg_atomic); \
- for (__i = 0; __i < __count; __i++) { \
- trace_lock_value((lock_dbg_atomic << 24) | \
- lock_dbg_user[__i]); \
- } \
- }
-
-#define spin_lock_dbg() \
- trace_lock("LcE"); \
- trace_lock_value(__LINE__);
-
-#define spin_unlock_dbg() \
- trace_lock("LcX"); \
- trace_lock_value(__LINE__);
-
-#else
-#define spin_lock_log(lock)
-#define spin_lock_dbg()
-#define spin_unlock_dbg()
-#endif
-
-/* does nothing on UP systems */
-#define spin_lock(lock) \
- spin_lock_dbg(); \
- spin_lock_log(lock); \
- spin_try_lock_dbg(lock);
-
-#define spin_unlock(lock) \
- arch_spin_unlock(lock); \
- spin_unlock_dbg();
-
-/* disables all IRQ sources and takes lock - enter atomic context */
-#define spin_lock_irq(lock, flags) \
- flags = interrupt_global_disable(); \
- lock_dbg_atomic++; \
- spin_lock(lock); \
- if (lock_dbg_atomic < DBG_LOCK_USERS) \
- lock_dbg_user[lock_dbg_atomic - 1] = (lock)->user;
-
-/* re-enables current IRQ sources and releases lock - leave atomic context */
-#define spin_unlock_irq(lock, flags) \
- spin_unlock(lock); \
- lock_dbg_atomic--; \
- interrupt_global_enable(flags);
-
-#else
-
-#define trace_lock(__e)
-#define tracev_lock(__e)
-
-#define spin_lock_dbg()
-#define spin_unlock_dbg()
-
-/* all SMP spinlocks need init, nothing todo on UP */
-#define spinlock_init(lock) \
- arch_spinlock_init(lock)
-
-/* does nothing on UP systems */
-#define spin_lock(lock) \
- spin_lock_dbg(); \
- arch_spin_lock(lock);
-
-#define spin_try_lock(lock) \
- spin_lock_dbg(); \
- arch_try_lock(lock);
-
-#define spin_unlock(lock) \
- arch_spin_unlock(lock); \
- spin_unlock_dbg();
-
-/* disables all IRQ sources and takes lock - enter atomic context */
-#define spin_lock_irq(lock, flags) \
- flags = interrupt_global_disable(); \
- spin_lock(lock);
-
-/* re-enables current IRQ sources and releases lock - leave atomic context */
-#define spin_unlock_irq(lock, flags) \
- spin_unlock(lock); \
- interrupt_global_enable(flags);
-
-#endif
-
-#endif
diff --git a/src/include/sof/mailbox.h b/src/include/sof/mailbox.h
deleted file mode 100644
index 17d9daa..0000000
--- a/src/include/sof/mailbox.h
+++ /dev/null
@@ -1,117 +0,0 @@
-/*
- * Copyright (c) 2016, Intel Corporation
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- * * Redistributions of source code must retain the above copyright
- * notice, this list of conditions and the following disclaimer.
- * * Redistributions in binary form must reproduce the above copyright
- * notice, this list of conditions and the following disclaimer in the
- * documentation and/or other materials provided with the distribution.
- * * Neither the name of the Intel Corporation nor the
- * names of its contributors may be used to endorse or promote products
- * derived from this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
- * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
- * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
- * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
- * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
- * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
- * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
- * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
- * POSSIBILITY OF SUCH DAMAGE.
- *
- * Author: Liam Girdwood <liam.r.girdwood@linux.intel.com>
- * Xiuli Pan <xiuli.pan@linux.intel.com>
- */
-
-#ifndef __INCLUDE_MAILBOX__
-#define __INCLUDE_MAILBOX__
-
-#include <platform/mailbox.h>
-#include <arch/cache.h>
-#include <stdint.h>
-#include <sof/string.h>
-
-/* For those platform did not have SW_REG window, use DEBUG at now */
-#ifndef MAILBOX_SW_REG_BASE
-#define MAILBOX_SW_REG_BASE MAILBOX_DEBUG_BASE
-#endif /* MAILBOX_SW_REG_BASE */
-
-/* 4k should be enough for everyone ..... */
-#define IPC_MAX_MAILBOX_BYTES 0x1000
-
-#define mailbox_get_exception_base() \
- MAILBOX_EXCEPTION_BASE
-
-#define mailbox_get_exception_size() \
- MAILBOX_EXCEPTION_SIZE
-
-#define mailbox_get_dspbox_base() \
- MAILBOX_DSPBOX_BASE
-
-#define mailbox_get_dspbox_size() \
- MAILBOX_DSPBOX_SIZE
-
-#define mailbox_get_hostbox_base() \
- MAILBOX_HOSTBOX_BASE
-
-#define mailbox_get_hostbox_size() \
- MAILBOX_HOSTBOX_SIZE
-
-#define mailbox_get_debug_base() \
- MAILBOX_DEBUG_BASE
-
-#define mailbox_get_debug_size() \
- MAILBOX_DEBUG_SIZE
-
-static inline
-void mailbox_dspbox_write(size_t offset, const void *src, size_t bytes)
-{
- rmemcpy((void *)(MAILBOX_DSPBOX_BASE + offset), src, bytes);
- dcache_writeback_region((void *)(MAILBOX_DSPBOX_BASE + offset), bytes);
-}
-
-static inline
-void mailbox_dspbox_read(void *dest, size_t offset, size_t bytes)
-{
- dcache_invalidate_region((void *)(MAILBOX_DSPBOX_BASE + offset), bytes);
- rmemcpy(dest, (void *)(MAILBOX_DSPBOX_BASE + offset), bytes);
-}
-
-static inline
-void mailbox_hostbox_write(size_t offset, const void *src, size_t bytes)
-{
- rmemcpy((void *)(MAILBOX_HOSTBOX_BASE + offset), src, bytes);
- dcache_writeback_region((void *)(MAILBOX_HOSTBOX_BASE + offset), bytes);
-}
-
-static inline
-void mailbox_hostbox_read(void *dest, size_t offset, size_t bytes)
-{
- dcache_invalidate_region((void *)(MAILBOX_HOSTBOX_BASE + offset),
- bytes);
- rmemcpy(dest, (void *)(MAILBOX_HOSTBOX_BASE + offset), bytes);
-}
-
-static inline
-void mailbox_stream_write(size_t offset, const void *src, size_t bytes)
-{
- rmemcpy((void *)(MAILBOX_STREAM_BASE + offset), src, bytes);
- dcache_writeback_region((void *)(MAILBOX_STREAM_BASE + offset),
- bytes);
-}
-
-static inline
-void mailbox_sw_reg_write(size_t offset, uint32_t src)
-{
- *((volatile uint32_t*)(MAILBOX_SW_REG_BASE + offset)) = src;
- dcache_writeback_region((void *)(MAILBOX_SW_REG_BASE + offset),
- sizeof(src));
-}
-
-#endif
diff --git a/src/include/sof/math/Makefile.am b/src/include/sof/math/Makefile.am
deleted file mode 100644
index fcd1d2f..0000000
--- a/src/include/sof/math/Makefile.am
+++ /dev/null
@@ -1,3 +0,0 @@
-noinst_HEADERS = \
- numbers.h \
- trig.h
diff --git a/src/include/sof/math/numbers.h b/src/include/sof/math/numbers.h
deleted file mode 100644
index 4ba812a..0000000
--- a/src/include/sof/math/numbers.h
+++ /dev/null
@@ -1,80 +0,0 @@
-/*
- * Copyright (c) 2016, Intel Corporation
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- * * Redistributions of source code must retain the above copyright
- * notice, this list of conditions and the following disclaimer.
- * * Redistributions in binary form must reproduce the above copyright
- * notice, this list of conditions and the following disclaimer in the
- * documentation and/or other materials provided with the distribution.
- * * Neither the name of the Intel Corporation nor the
- * names of its contributors may be used to endorse or promote products
- * derived from this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
- * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
- * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
- * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
- * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
- * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
- * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
- * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
- * POSSIBILITY OF SUCH DAMAGE.
- *
- * Author: Seppo Ingalsuo <seppo.ingalsuo@linux.intel.com>
- * Liam Girdwood <liam.r.girdwood@linux.intel.com>
- * Keyon Jie <yang.jie@linux.intel.com>
- */
-
-#ifndef NUMBERS_H
-#define NUMBERS_H
-
-#include <stdint.h>
-
-#define MIN(a, b) (((a) < (b)) ? (a) : (b))
-#define MAX(a, b) (((a) > (b)) ? (a) : (b))
-
-int gcd(int a, int b); /* Calculate greatest common divisor for a and b */
-
-/* This is a divide function that returns ceil of the quotient.
- * E.g. ceil_divide(9, 3) returns 3, ceil_divide(10, 3) returns 4.
- */
-static inline int ceil_divide(int a, int b)
-{
- int c;
-
- c = a / b;
-
- /* First, we check whether the signs of the params are different.
- * If they are, we already know the result is going to be negative and
- * therefore, is going to be already rounded up (truncated).
- *
- * If the signs are the same, we check if there was any remainder in
- * the division by multiplying the number back.
- */
- if (!((a ^ b) & (1 << ((sizeof(int) * 8) - 1))) && c * b != a)
- c++;
-
- return c;
-}
-
-/* Find indices of equal values in a vector of integer values */
-int find_equal_int16(int16_t idx[], int16_t vec[], int n, int vec_length,
- int max_results);
-
-/* Return the smallest value found in a vector */
-int16_t find_min_int16(int16_t vec[], int vec_length);
-
-/* Return the largest absolute value found in a vector */
-int32_t find_max_abs_int32(int32_t vec[], int vec_length);
-
-/* Count the left shift amount to normalize a 32 bit signed integer value
- * without causing overflow. Input value 0 will result to 31.
- */
-int norm_int32(int32_t val);
-
-#endif /* NUMBERS_H */
diff --git a/src/include/sof/math/trig.h b/src/include/sof/math/trig.h
deleted file mode 100644
index 2ac05c6..0000000
--- a/src/include/sof/math/trig.h
+++ /dev/null
@@ -1,42 +0,0 @@
-/*
- * Copyright (c) 2016, Intel Corporation
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- * * Redistributions of source code must retain the above copyright
- * notice, this list of conditions and the following disclaimer.
- * * Redistributions in binary form must reproduce the above copyright
- * notice, this list of conditions and the following disclaimer in the
- * documentation and/or other materials provided with the distribution.
- * * Neither the name of the Intel Corporation nor the
- * names of its contributors may be used to endorse or promote products
- * derived from this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
- * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
- * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
- * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
- * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
- * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
- * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
- * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
- * POSSIBILITY OF SUCH DAMAGE.
- *
- * Author: Seppo Ingalsuo <seppo.ingalsuo@linux.intel.com>
- * Liam Girdwood <liam.r.girdwood@linux.intel.com>
- * Keyon Jie <yang.jie@linux.intel.com>
- */
-
-#ifndef TRIG_H
-#define TRIG_H
-
-#define PI_DIV2_Q4_28 421657428
-#define PI_Q4_28 843314857
-#define PI_MUL2_Q4_28 1686629713
-
-int32_t sin_fixed(int32_t w); /* Input is Q4.28, output is Q1.31 */
-
-#endif
diff --git a/src/include/sof/notifier.h b/src/include/sof/notifier.h
deleted file mode 100644
index 82086c9..0000000
--- a/src/include/sof/notifier.h
+++ /dev/null
@@ -1,57 +0,0 @@
-/*
- * Copyright (c) 2016, Intel Corporation
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- * * Redistributions of source code must retain the above copyright
- * notice, this list of conditions and the following disclaimer.
- * * Redistributions in binary form must reproduce the above copyright
- * notice, this list of conditions and the following disclaimer in the
- * documentation and/or other materials provided with the distribution.
- * * Neither the name of the Intel Corporation nor the
- * names of its contributors may be used to endorse or promote products
- * derived from this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
- * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
- * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
- * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
- * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
- * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
- * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
- * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
- * POSSIBILITY OF SUCH DAMAGE.
- *
- * Author: Liam Girdwood <liam.r.girdwood@linux.intel.com>
- */
-
-#ifndef __INCLUDE_NOTIFIER__
-#define __INCLUDE_NOTIFIER__
-
-#include <stdint.h>
-#include <sof/list.h>
-
-struct sof;
-
-/* notifier general IDs */
-#define NOTIFIER_ID_CPU_FREQ 0
-#define NOTIFIER_ID_SSP_FREQ 1
-
-struct notifier {
- uint32_t id;
- struct list_item list;
- void *cb_data;
- void (*cb)(int message, void *cb_data, void *event_data);
-};
-
-void notifier_register(struct notifier *notifier);
-void notifier_unregister(struct notifier *notifier);
-
-void notifier_event(int id, int message, void *event_data);
-
-void init_system_notify(struct sof *sof);
-
-#endif
diff --git a/src/include/sof/panic.h b/src/include/sof/panic.h
deleted file mode 100644
index 7c19939..0000000
--- a/src/include/sof/panic.h
+++ /dev/null
@@ -1,76 +0,0 @@
-/*
- * Copyright (c) 2018, Intel Corporation
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- * * Redistributions of source code must retain the above copyright
- * notice, this list of conditions and the following disclaimer.
- * * Redistributions in binary form must reproduce the above copyright
- * notice, this list of conditions and the following disclaimer in the
- * documentation and/or other materials provided with the distribution.
- * * Neither the name of the Intel Corporation nor the
- * names of its contributors may be used to endorse or promote products
- * derived from this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
- * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
- * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
- * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
- * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
- * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
- * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
- * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
- * POSSIBILITY OF SUCH DAMAGE.
- *
- * Author: Liam Girdwood <liam.r.girdwood@linux.intel.com>
- */
-
-#ifndef __INCLUDE_SOF_IPC_PANIC__
-#define __INCLUDE_SOF_IPC_PANIC__
-
-#include <sof/sof.h>
-#include <sof/mailbox.h>
-#include <sof/interrupt.h>
-#include <sof/trace.h>
-#include <platform/platform.h>
-#include <uapi/ipc.h>
-#include <stdint.h>
-#include <stdlib.h>
-
-/* panic and rewind stack */
-static inline void panic_rewind(uint32_t p, uint32_t stack_rewind_frames)
-{
- void *ext_offset;
- size_t count;
-
- /* disable all IRQs */
- interrupt_global_disable();
-
- /* dump DSP core registers */
- ext_offset = arch_dump_regs();
- count = MAILBOX_EXCEPTION_SIZE -
- (size_t)(ext_offset - mailbox_get_exception_base());
-
- /* dump stack frames */
- p = dump_stack(p, ext_offset, stack_rewind_frames,
- count * sizeof(uint32_t));
-
- /* panic - send IPC oops message to host */
- platform_panic(p);
-
- /* flush last trace messages */
- trace_flush();
-
- /* and loop forever */
- while (1) {};
-}
-
-static inline void panic(uint32_t p)
-{
- panic_rewind(p, 0);
-}
-
-#endif
diff --git a/src/include/sof/platform.h b/src/include/sof/platform.h
deleted file mode 100644
index 0996c66..0000000
--- a/src/include/sof/platform.h
+++ /dev/null
@@ -1,73 +0,0 @@
-/*
- * Copyright (c) 2018, Intel Corporation
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- * * Redistributions of source code must retain the above copyright
- * notice, this list of conditions and the following disclaimer.
- * * Redistributions in binary form must reproduce the above copyright
- * notice, this list of conditions and the following disclaimer in the
- * documentation and/or other materials provided with the distribution.
- * * Neither the name of the Intel Corporation nor the
- * names of its contributors may be used to endorse or promote products
- * derived from this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
- * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
- * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
- * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
- * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
- * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
- * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
- * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
- * POSSIBILITY OF SUCH DAMAGE.
- *
- * Author: Marcin Maka <marcin.maka@linux.intel.com>
- */
-
- /**
- * \file include/sof/platform.h
- * \brief Platform API definition
- * \author Marcin Maka <marcin.maka@linux.intel.com>
- */
-
-#ifndef __INCLUDE_SOF_PLATFORM_H__
-#define __INCLUDE_SOF_PLATFORM_H__
-
-#include <sof/sof.h>
-
-/** \addtogroup platform_api Platform API
- * Platform API specification.
- * @{
- */
-
-/*
- * APIs declared here are defined for every platform.
- */
-
-/**
- * \brief Platform specific implementation of the On Boot Complete handler.
- * \param[in] boot_message Boot status code.
- * \return 0 if successful, error code otherwise.
- */
-int platform_boot_complete(uint32_t boot_message);
-
-/**
- * \brief Platform initialization entry, called during FW initialization.
- * \param[in] sof Context.
- * \return 0 if successful, error code otherwise.
- */
-int platform_init(struct sof *sof);
-
-/**
- * \brief Called by the panic handler.
- * \param[in] p Panic cause, one of SOF_IPC_PANIC_... codes (see ipc.h).
- */
-static inline void platform_panic(uint32_t p);
-
-/** @}*/
-
-#endif
diff --git a/src/include/sof/pm_runtime.h b/src/include/sof/pm_runtime.h
deleted file mode 100644
index 166d89e..0000000
--- a/src/include/sof/pm_runtime.h
+++ /dev/null
@@ -1,78 +0,0 @@
-/*
- * Copyright (c) 2018, Intel Corporation
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- * * Redistributions of source code must retain the above copyright
- * notice, this list of conditions and the following disclaimer.
- * * Redistributions in binary form must reproduce the above copyright
- * notice, this list of conditions and the following disclaimer in the
- * documentation and/or other materials provided with the distribution.
- * * Neither the name of the Intel Corporation nor the
- * names of its contributors may be used to endorse or promote products
- * derived from this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
- * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
- * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
- * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
- * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
- * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
- * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
- * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
- * POSSIBILITY OF SUCH DAMAGE.
- *
- * Author: Tomasz Lauda <tomasz.lauda@linux.intel.com>
- */
-
-/**
- * \file include/sof/pm_runtime.h
- * \brief Runtime power management header file
- * \author Tomasz Lauda <tomasz.lauda@linux.intel.com>
- */
-
-#ifndef __INCLUDE_PM_RUNTIME__
-#define __INCLUDE_PM_RUNTIME__
-
-#include <sof/lock.h>
-#include <sof/trace.h>
-
-/** \brief Power management trace function. */
-#define trace_pm(__e) trace_event(TRACE_CLASS_POWER, __e)
-#define tracev_pm(__e) tracev_event(TRACE_CLASS_POWER, __e)
-
-/** \brief Power management trace value function. */
-#define tracev_pm_value(__e) tracev_value(__e)
-
-/** \brief Runtime power management context */
-enum pm_runtime_context {
- PM_RUNTIME_HOST_DMA_L1 = 0, /**< Host DMA L1 Exit */
-};
-
-/** \brief Runtime power management data. */
-struct pm_runtime_data {
- spinlock_t lock; /**< lock mechanism */
- void *platform_data; /**< platform specific data */
-};
-
-/**
- * \brief Initializes runtime power management.
- */
-void pm_runtime_init(void);
-
-/**
- * \brief Retrieves power management resource.
- * \param[in] context Type of power management context.
- */
-void pm_runtime_get(enum pm_runtime_context context);
-
-/**
- * \brief Releases power management resource.
- * \param[in] context Type of power management context.
- */
-void pm_runtime_put(enum pm_runtime_context context);
-
-#endif /* __INCLUDE_PM_RUNTIME__ */
diff --git a/src/include/sof/schedule.h b/src/include/sof/schedule.h
deleted file mode 100644
index 875fe06..0000000
--- a/src/include/sof/schedule.h
+++ /dev/null
@@ -1,115 +0,0 @@
-/*
- * Copyright (c) 2017, Intel Corporation
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- * * Redistributions of source code must retain the above copyright
- * notice, this list of conditions and the following disclaimer.
- * * Redistributions in binary form must reproduce the above copyright
- * notice, this list of conditions and the following disclaimer in the
- * documentation and/or other materials provided with the distribution.
- * * Neither the name of the Intel Corporation nor the
- * names of its contributors may be used to endorse or promote products
- * derived from this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
- * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
- * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
- * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
- * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
- * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
- * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
- * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
- * POSSIBILITY OF SUCH DAMAGE.
- *
- * Author: Liam Girdwood <liam.r.girdwood@linux.intel.com>
- */
-
-#ifndef __INCLUDE_SOF_SCHEDULE_H__
-#define __INCLUDE_SOF_SCHEDULE_H__
-
-#include <stdint.h>
-#include <stddef.h>
-#include <errno.h>
-#include <sof/sof.h>
-#include <sof/lock.h>
-#include <sof/list.h>
-#include <sof/work.h>
-
-struct schedule_data;
-struct sof;
-
-/* task states */
-#define TASK_STATE_INIT 0
-#define TASK_STATE_QUEUED 1
-#define TASK_STATE_RUNNING 2
-#define TASK_STATE_PREEMPTED 3
-#define TASK_STATE_COMPLETED 4
-#define TASK_STATE_FREE 5
-#define TASK_STATE_CANCEL 6
-
-/* task priorities - values same as Linux processes, gives scope for future.*/
-#define TASK_PRI_LOW 19
-#define TASK_PRI_MED 0
-#define TASK_PRI_HIGH -20
-
-
-/* task descriptor */
-struct task {
- uint16_t core; /* core id to run on */
- int16_t priority; /* scheduling priority TASK_PRI_ */
- uint64_t start; /* scheduling earliest start time */
- uint64_t deadline; /* scheduling deadline */
- uint32_t state; /* TASK_STATE_ */
- struct list_item list; /* list in scheduler */
- struct list_item irq_list; /* list for assigned irq level */
-
- /* task function and private data */
- void *data;
- void (*func)(void *arg);
-
- /* runtime duration in scheduling clock base */
- uint64_t max_rtime; /* max time taken to run */
-};
-
-struct schedule_data **arch_schedule_get(void);
-
-void schedule(void);
-
-void schedule_task(struct task *task, uint64_t start, uint64_t deadline);
-
-void schedule_task_idle(struct task *task, uint64_t deadline);
-
-void schedule_task_complete(struct task *task);
-
-static inline void schedule_task_init(struct task *task, void (*func)(void *),
- void *data)
-{
- task->core = 0;
- task->state = TASK_STATE_INIT;
- task->func = func;
- task->data = data;
-}
-
-static inline void schedule_task_free(struct task *task)
-{
- task->state = TASK_STATE_FREE;
- task->func = NULL;
- task->data = NULL;
-}
-
-static inline void schedule_task_config(struct task *task, uint16_t priority,
- uint16_t core)
-{
- task->priority = priority;
- task->core = core;
-}
-
-int scheduler_init(struct sof *sof);
-
-void scheduler_free(void);
-
-#endif
diff --git a/src/include/sof/sof.h b/src/include/sof/sof.h
deleted file mode 100644
index b9d7aff..0000000
--- a/src/include/sof/sof.h
+++ /dev/null
@@ -1,63 +0,0 @@
-/*
- * Copyright (c) 2016, Intel Corporation
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- * * Redistributions of source code must retain the above copyright
- * notice, this list of conditions and the following disclaimer.
- * * Redistributions in binary form must reproduce the above copyright
- * notice, this list of conditions and the following disclaimer in the
- * documentation and/or other materials provided with the distribution.
- * * Neither the name of the Intel Corporation nor the
- * names of its contributors may be used to endorse or promote products
- * derived from this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
- * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
- * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
- * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
- * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
- * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
- * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
- * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
- * POSSIBILITY OF SUCH DAMAGE.
- *
- * Author: Liam Girdwood <liam.r.girdwood@linux.intel.com>
- */
-
-#ifndef __INCLUDE_SOF_SOF__
-#define __INCLUDE_SOF_SOF__
-
-#include <stdint.h>
-#include <stddef.h>
-#include <arch/sof.h>
-
-struct ipc;
-struct sa;
-
-/* use same syntax as Linux for simplicity */
-#define ARRAY_SIZE(x) (sizeof(x) / sizeof(x[0]))
-#define container_of(ptr, type, member) \
- ({const typeof(((type *)0)->member) *__memberptr = (ptr); \
- (type *)((char *)__memberptr - offsetof(type, member));})
-
-/* general firmware context */
-struct sof {
- /* init data */
- int argc;
- char **argv;
-
- /* ipc */
- struct ipc *ipc;
-
- /* system agent */
- struct sa *sa;
-
- /* DMA for Trace*/
- struct dma_trace_data *dmat;
-};
-
-#endif
diff --git a/src/include/sof/ssp.h b/src/include/sof/ssp.h
deleted file mode 100644
index e57aa84..0000000
--- a/src/include/sof/ssp.h
+++ /dev/null
@@ -1,270 +0,0 @@
-/*
- * Copyright (c) 2016, Intel Corporation
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- * * Redistributions of source code must retain the above copyright
- * notice, this list of conditions and the following disclaimer.
- * * Redistributions in binary form must reproduce the above copyright
- * notice, this list of conditions and the following disclaimer in the
- * documentation and/or other materials provided with the distribution.
- * * Neither the name of the Intel Corporation nor the
- * names of its contributors may be used to endorse or promote products
- * derived from this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
- * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
- * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
- * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
- * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
- * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
- * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
- * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
- * POSSIBILITY OF SUCH DAMAGE.
- *
- * Author: Liam Girdwood <liam.r.girdwood@linux.intel.com>
- */
-
-#ifndef __INCLUDE_SSP__
-#define __INCLUDE_SSP__
-
-#include <sof/dai.h>
-#include <sof/io.h>
-#include <sof/lock.h>
-#include <sof/work.h>
-#include <sof/trace.h>
-#include <sof/wait.h>
-
-#define SSP_CLK_AUDIO 0
-#define SSP_CLK_NET_PLL 1
-#define SSP_CLK_EXT 2
-#define SSP_CLK_NET 3
-#define SSP_CLK_DEFAULT 4
-
-/* SSP register offsets */
-#define SSCR0 0x00
-#define SSCR1 0x04
-#define SSSR 0x08
-#define SSITR 0x0C
-#define SSDR 0x10
-#define SSTO 0x28
-#define SSPSP 0x2C
-#define SSTSA 0x30
-#define SSRSA 0x34
-#define SSTSS 0x38
-#define SSCR2 0x40
-
-#if defined CONFIG_BAYTRAIL ||\
- defined CONFIG_CHERRYTRAIL ||\
- defined CONFIG_BROADWELL ||\
- defined CONFIG_HASWELL
-#define SFIFOL 0x68
-#define SFIFOTT 0x6C
-#define SSCR3 0x70
-#define SSCR4 0x74
-#define SSCR5 0x78
-#endif
-
-extern const struct dai_ops ssp_ops;
-
-/* SSCR0 bits */
-#define SSCR0_DSS_MASK (0x0000000f)
-#define SSCR0_DSIZE(x) ((x) - 1)
-#define SSCR0_FRF (0x00000030)
-#define SSCR0_MOT (00 << 4)
-#define SSCR0_TI (1 << 4)
-#define SSCR0_NAT (2 << 4)
-#define SSCR0_PSP (3 << 4)
-#define SSCR0_ECS (1 << 6)
-#define SSCR0_SSE (1 << 7)
-#define SSCR0_SCR_MASK (0x000fff00)
-#define SSCR0_SCR(x) ((x) << 8)
-#define SSCR0_EDSS (1 << 20)
-#define SSCR0_NCS (1 << 21)
-#define SSCR0_RIM (1 << 22)
-#define SSCR0_TIM (1 << 23)
-#define SSCR0_FRDC(x) (((x) - 1) << 24)
-#define SSCR0_ACS (1 << 30)
-#define SSCR0_MOD (1 << 31)
-
-/* SSCR1 bits */
-#define SSCR1_RIE (1 << 0)
-#define SSCR1_TIE (1 << 1)
-#define SSCR1_LBM (1 << 2)
-#define SSCR1_SPO (1 << 3)
-#define SSCR1_SPH (1 << 4)
-#define SSCR1_MWDS (1 << 5)
-#define SSCR1_TFT_MASK (0x000003c0)
-#define SSCR1_TFT(x) (((x) - 1) << 6)
-#define SSCR1_RFT_MASK (0x00003c00)
-#define SSCR1_RFT(x) (((x) - 1) << 10)
-#define SSCR1_EFWR (1 << 14)
-#define SSCR1_STRF (1 << 15)
-#define SSCR1_IFS (1 << 16)
-#define SSCR1_PINTE (1 << 18)
-#define SSCR1_TINTE (1 << 19)
-#define SSCR1_RSRE (1 << 20)
-#define SSCR1_TSRE (1 << 21)
-#define SSCR1_TRAIL (1 << 22)
-#define SSCR1_RWOT (1 << 23)
-#define SSCR1_SFRMDIR (1 << 24)
-#define SSCR1_SCLKDIR (1 << 25)
-#define SSCR1_ECRB (1 << 26)
-#define SSCR1_ECRA (1 << 27)
-#define SSCR1_SCFR (1 << 28)
-#define SSCR1_EBCEI (1 << 29)
-#define SSCR1_TTE (1 << 30)
-#define SSCR1_TTELP (1 << 31)
-
-#if defined CONFIG_BAYTRAIL || defined CONFIG_CHERRYTRAIL
-/* SSCR2 bits */
-#define SSCR2_URUN_FIX0 BIT(0)
-#define SSCR2_URUN_FIX1 BIT(1)
-#define SSCR2_SLV_EXT_CLK_RUN_EN BIT(2)
-#define SSCR2_CLK_DEL_EN BIT(3)
-#define SSCR2_UNDRN_FIX_EN BIT(6)
-#define SSCR2_FIFO_EMPTY_FIX_EN BIT(7)
-#define SSCR2_ASRC_CNTR_EN BIT(8)
-#define SSCR2_ASRC_CNTR_CLR BIT(9)
-#define SSCR2_ASRC_FRM_CNRT_EN BIT(10)
-#define SSCR2_ASRC_INTR_MASK BIT(11)
-#elif defined CONFIG_APOLLOLAKE || defined CONFIG_CANNONLAKE \
- || defined CONFIG_HASWELL || defined CONFIG_BROADWELL
-#define SSCR2_TURM1 BIT(1)
-#define SSCR2_PSPSRWFDFD BIT(3)
-#define SSCR2_PSPSTWFDFD BIT(4)
-#define SSCR2_SDFD BIT(14)
-#define SSCR2_SDPM BIT(16)
-#define SSCR2_LJDFD BIT(17)
-#define SSCR2_MMRATF BIT(18)
-#define SSCR2_SMTATF BIT(19)
-#endif
-
-
-/* SSR bits */
-#define SSSR_TNF (1 << 2)
-#define SSSR_RNE (1 << 3)
-#define SSSR_BSY (1 << 4)
-#define SSSR_TFS (1 << 5)
-#define SSSR_RFS (1 << 6)
-#define SSSR_ROR (1 << 7)
-
-/* SSPSP bits */
-#define SSPSP_SCMODE(x) ((x) << 0)
-#define SSPSP_SFRMP(x) ((x) << 2)
-#define SSPSP_ETDS (1 << 3)
-#define SSPSP_STRTDLY(x) ((x) << 4)
-#define SSPSP_DMYSTRT(x) ((x) << 7)
-#define SSPSP_SFRMDLY(x) ((x) << 9)
-#define SSPSP_SFRMWDTH(x) ((x) << 16)
-#define SSPSP_DMYSTOP(x) ((x) << 23)
-#define SSPSP_DMYSTOP_BITS 2
-#define SSPSP_DMYSTOP_MASK ((0x1 << SSPSP_DMYSTOP_BITS) - 1)
-#define SSPSP_FSRT (1 << 25)
-#define SSPSP_EDMYSTOP(x) ((x) << 26)
-#define SSPSP_EDMYSTOP_MASK 0x7
-
-#define SSPSP2 0x44
-#define SSPSP2_FEP_MASK 0xff
-
-#if defined CONFIG_APOLLOLAKE || defined CONFIG_CANNONLAKE
-#define SSCR3 0x48
-#define SSIOC 0x4C
-
-#define SSP_REG_MAX SSIOC
-#endif
-
-/* SSCR3 bits */
-#define SSCR3_FRM_MST_EN (1 << 0)
-#define SSCR3_I2S_MODE_EN (1 << 1)
-#define SSCR3_I2S_FRM_POL(x) ((x) << 2)
-#define SSCR3_I2S_TX_SS_FIX_EN (1 << 3)
-#define SSCR3_I2S_RX_SS_FIX_EN (1 << 4)
-#define SSCR3_I2S_TX_EN (1 << 9)
-#define SSCR3_I2S_RX_EN (1 << 10)
-#define SSCR3_CLK_EDGE_SEL (1 << 12)
-#define SSCR3_STRETCH_TX (1 << 14)
-#define SSCR3_STRETCH_RX (1 << 15)
-#define SSCR3_MST_CLK_EN (1 << 16)
-#define SSCR3_SYN_FIX_EN (1 << 17)
-
-
-/* SSCR4 bits */
-#define SSCR4_TOT_FRM_PRD(x) ((x) << 7)
-
-/* SSCR5 bits */
-#define SSCR5_FRM_ASRT_CLOCKS(x) (((x) - 1) << 1)
-#define SSCR5_FRM_POLARITY(x) ((x) << 0)
-
-/* SFIFOTT bits */
-#define SFIFOTT_TX(x) ((x) - 1)
-#define SFIFOTT_RX(x) (((x) - 1) << 16)
-
-/* SFIFOL bits */
-#define SFIFOL_TFL(x) ((x) & 0xFFFF)
-#define SFIFOL_RFL(x) ((x) >> 16)
-
-#if defined CONFIG_APOLLOLAKE || defined CONFIG_CANNONLAKE ||\
- defined CONFIG_HASWELL || defined CONFIG_BROADWELL
-#define SSTSA_TSEN BIT(8)
-#define SSRSA_RSEN BIT(8)
-
-#define SSCR3_TFL_MASK (0x0000003f)
-#define SSCR3_RFL_MASK (0x00003f00)
-#define SSCR3_TFT_MASK (0x003f0000)
-#define SSCR3_TX(x) (((x) - 1) << 16)
-#define SSCR3_RFT_MASK (0x3f000000)
-#define SSCR3_RX(x) (((x) - 1) << 24)
-
-#define SSIOC_TXDPDEB BIT(1)
-#define SSIOC_SFCR BIT(4)
-#define SSIOC_SCOE BIT(5)
-#endif
-
-#if defined CONFIG_APOLLOLAKE || defined CONFIG_CANNONLAKE
-#define MNDSS(x) ((x) << 20)
-#define MCDSS(x) ((x) << 16)
-#endif
-
-/* tracing */
-#define trace_ssp(__e) trace_event(TRACE_CLASS_SSP, __e)
-#define trace_ssp_error(__e) trace_error(TRACE_CLASS_SSP, __e)
-#define tracev_ssp(__e) tracev_event(TRACE_CLASS_SSP, __e)
-
-
-#define ssp_irq(ssp) \
- ssp->plat_data.irq
-
-/* SSP private data */
-struct ssp_pdata {
- uint32_t sscr0;
- uint32_t sscr1;
- uint32_t psp;
- spinlock_t lock;
- uint32_t state[2]; /* SSP_STATE_ for each direction */
- completion_t drain_complete;
- struct sof_ipc_dai_config config;
- struct sof_ipc_dai_ssp_params params;
-};
-
-static inline void ssp_write(struct dai *dai, uint32_t reg, uint32_t value)
-{
- io_reg_write(dai_base(dai) + reg, value);
-}
-
-static inline uint32_t ssp_read(struct dai *dai, uint32_t reg)
-{
- return io_reg_read(dai_base(dai) + reg);
-}
-
-static inline void ssp_update_bits(struct dai *dai, uint32_t reg, uint32_t mask,
- uint32_t value)
-{
- io_reg_update_bits(dai_base(dai) + reg, mask, value);
-}
-
-
-#endif
diff --git a/src/include/sof/stream.h b/src/include/sof/stream.h
deleted file mode 100644
index 04fe2de..0000000
--- a/src/include/sof/stream.h
+++ /dev/null
@@ -1,53 +0,0 @@
-/*
- * Copyright (c) 2016, Intel Corporation
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- * * Redistributions of source code must retain the above copyright
- * notice, this list of conditions and the following disclaimer.
- * * Redistributions in binary form must reproduce the above copyright
- * notice, this list of conditions and the following disclaimer in the
- * documentation and/or other materials provided with the distribution.
- * * Neither the name of the Intel Corporation nor the
- * names of its contributors may be used to endorse or promote products
- * derived from this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
- * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
- * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
- * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
- * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
- * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
- * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
- * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
- * POSSIBILITY OF SUCH DAMAGE.
- *
- * Author: Liam Girdwood <liam.r.girdwood@linux.intel.com>
- * Keyon Jie <yang.jie@linux.intel.com>
- */
-
-#ifndef __INCLUDE_SOF_STREAM__
-#define __INCLUDE_SOF_STREAM__
-
-#include <stdint.h>
-#include <platform/platform.h>
-#include <uapi/ipc.h>
-
-enum stream_type {
- STREAM_TYPE_PCM = 0,
- STREAM_TYPE_VORBIS = 1,
-};
-
-struct stream_params
-{
- enum stream_type type;
- union {
- struct sof_ipc_pcm_params *pcm;
- struct sof_ipc_vorbis_params *vorbis;
- };
-};
-
-#endif
diff --git a/src/include/sof/string.h b/src/include/sof/string.h
deleted file mode 100644
index f4b1f24..0000000
--- a/src/include/sof/string.h
+++ /dev/null
@@ -1,47 +0,0 @@
-/*
- * Copyright (c) 2018, Intel Corporation
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- * * Redistributions of source code must retain the above copyright
- * notice, this list of conditions and the following disclaimer.
- * * Redistributions in binary form must reproduce the above copyright
- * notice, this list of conditions and the following disclaimer in the
- * documentation and/or other materials provided with the distribution.
- * * Neither the name of the Intel Corporation nor the
- * names of its contributors may be used to endorse or promote products
- * derived from this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
- * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
- * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
- * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
- * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
- * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
- * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
- * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
- * POSSIBILITY OF SUCH DAMAGE.
- *
- * Author: Liam Girdwood <liam.r.girdwood@linux.intel.com>
- */
-
-#ifndef __INCLUDE_STRING_SOF__
-#define __INCLUDE_STRING_SOF__
-
-#include <arch/string.h>
-
-/* C memcpy for arch that don't have arch_memcpy() */
-void cmemcpy(void *dest, void *src, size_t size);
-
-#if defined(arch_memcpy)
-#define rmemcpy(dest, src, size) \
- arch_memcpy(dest, src, size)
-#else
-#define rmemcpy(dest, src, size) \
- cmemcpy(dest, src, size)
-#endif
-
-#endif
diff --git a/src/include/sof/task.h b/src/include/sof/task.h
deleted file mode 100644
index 15fe0d0..0000000
--- a/src/include/sof/task.h
+++ /dev/null
@@ -1,53 +0,0 @@
-/*
- * Copyright (c) 2016, Intel Corporation
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- * * Redistributions of source code must retain the above copyright
- * notice, this list of conditions and the following disclaimer.
- * * Redistributions in binary form must reproduce the above copyright
- * notice, this list of conditions and the following disclaimer in the
- * documentation and/or other materials provided with the distribution.
- * * Neither the name of the Intel Corporation nor the
- * names of its contributors may be used to endorse or promote products
- * derived from this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
- * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
- * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
- * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
- * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
- * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
- * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
- * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
- * POSSIBILITY OF SUCH DAMAGE.
- *
- * Author: Liam Girdwood <liam.r.girdwood@linux.intel.com>
- */
-
-#ifndef __INCLUDE_TASK_H__
-#define __INCLUDE_TASK_H__
-
-#include <arch/task.h>
-
-struct sof;
-struct task;
-
-int do_task_master_core(struct sof *sof);
-
-int do_task_slave_core(struct sof *sof);
-
-static inline int allocate_tasks(void)
-{
- return arch_allocate_tasks();
-}
-
-static inline void run_task(struct task *task)
-{
- arch_run_task(task);
-}
-
-#endif
diff --git a/src/include/sof/test b/src/include/sof/test
deleted file mode 100644
index e69de29..0000000
--- a/src/include/sof/test
+++ /dev/null
diff --git a/src/include/sof/timer.h b/src/include/sof/timer.h
deleted file mode 100644
index 50d0825..0000000
--- a/src/include/sof/timer.h
+++ /dev/null
@@ -1,64 +0,0 @@
-/*
- * Copyright (c) 2016, Intel Corporation
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- * * Redistributions of source code must retain the above copyright
- * notice, this list of conditions and the following disclaimer.
- * * Redistributions in binary form must reproduce the above copyright
- * notice, this list of conditions and the following disclaimer in the
- * documentation and/or other materials provided with the distribution.
- * * Neither the name of the Intel Corporation nor the
- * names of its contributors may be used to endorse or promote products
- * derived from this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
- * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
- * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
- * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
- * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
- * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
- * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
- * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
- * POSSIBILITY OF SUCH DAMAGE.
- *
- * Author: Liam Girdwood <liam.r.girdwood@linux.intel.com>
- */
-
-#ifndef __INCLUDE_TIMER__
-#define __INCLUDE_TIMER__
-
-#include <arch/timer.h>
-#include <stdint.h>
-
-int timer_register(struct timer *timer,
- void(*handler)(void *arg), void *arg);
-void timer_unregister(struct timer *timer);
-void timer_enable(struct timer *timer);
-void timer_disable(struct timer *timer);
-
-static inline int timer_set(struct timer *timer, uint64_t ticks)
-{
- return arch_timer_set(timer, ticks);
-}
-
-void timer_set_ms(struct timer *timer, unsigned int ms);
-
-static inline void timer_clear(struct timer *timer)
-{
- arch_timer_clear(timer);
-}
-
-unsigned int timer_get_count(struct timer *timer);
-
-unsigned int timer_get_count_delta(struct timer *timer);
-
-static inline uint64_t timer_get_system(struct timer *timer)
-{
- return arch_timer_get_system(timer);
-}
-
-#endif
diff --git a/src/include/sof/trace.h b/src/include/sof/trace.h
deleted file mode 100644
index 76011e9..0000000
--- a/src/include/sof/trace.h
+++ /dev/null
@@ -1,181 +0,0 @@
-/*
- * Copyright (c) 2016, Intel Corporation
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- * * Redistributions of source code must retain the above copyright
- * notice, this list of conditions and the following disclaimer.
- * * Redistributions in binary form must reproduce the above copyright
- * notice, this list of conditions and the following disclaimer in the
- * documentation and/or other materials provided with the distribution.
- * * Neither the name of the Intel Corporation nor the
- * names of its contributors may be used to endorse or promote products
- * derived from this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
- * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
- * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
- * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
- * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
- * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
- * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
- * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
- * POSSIBILITY OF SUCH DAMAGE.
- *
- * Author: Liam Girdwood <liam.r.girdwood@linux.intel.com>
- * Keyon Jie <yang.jie@linux.intel.com>
- */
-
-#ifndef __INCLUDE_TRACE__
-#define __INCLUDE_TRACE__
-
-#include <stdint.h>
-#include <stdlib.h>
-#include <sof/sof.h>
-#include <sof/mailbox.h>
-#include <sof/debug.h>
-#include <sof/timer.h>
-#include <platform/platform.h>
-#include <platform/timer.h>
-
-/* bootloader trace values */
-#define TRACE_BOOT_LDR_ENTRY 0x100
-#define TRACE_BOOT_LDR_HPSRAM 0x110
-#define TRACE_BOOT_LDR_MANIFEST 0x120
-#define TRACE_BOOT_LDR_JUMP 0x150
-
-#define TRACE_BOOT_LDR_PARSE_MODULE 0x210
-#define TRACE_BOOT_LDR_PARSE_SEGMENT 0x220
-
-/* general trace init codes - only used at boot when main trace is not available */
-#define TRACE_BOOT_START 0x1000
-#define TRACE_BOOT_ARCH 0x2000
-#define TRACE_BOOT_SYS 0x3000
-#define TRACE_BOOT_PLATFORM 0x4000
-
-/* system specific codes */
-#define TRACE_BOOT_SYS_WORK (TRACE_BOOT_SYS + 0x100)
-#define TRACE_BOOT_SYS_CPU_FREQ (TRACE_BOOT_SYS + 0x200)
-#define TRACE_BOOT_SYS_HEAP (TRACE_BOOT_SYS + 0x300)
-#define TRACE_BOOT_SYS_NOTE (TRACE_BOOT_SYS + 0x400)
-#define TRACE_BOOT_SYS_SCHED (TRACE_BOOT_SYS + 0x500)
-#define TRACE_BOOT_SYS_POWER (TRACE_BOOT_SYS + 0x600)
-
-/* platform/device specific codes */
-#define TRACE_BOOT_PLATFORM_ENTRY (TRACE_BOOT_PLATFORM + 0x100)
-#define TRACE_BOOT_PLATFORM_MBOX (TRACE_BOOT_PLATFORM + 0x110)
-#define TRACE_BOOT_PLATFORM_SHIM (TRACE_BOOT_PLATFORM + 0x120)
-#define TRACE_BOOT_PLATFORM_PMC (TRACE_BOOT_PLATFORM + 0x130)
-#define TRACE_BOOT_PLATFORM_TIMER (TRACE_BOOT_PLATFORM + 0x140)
-#define TRACE_BOOT_PLATFORM_CLOCK (TRACE_BOOT_PLATFORM + 0x150)
-#define TRACE_BOOT_PLATFORM_SSP_FREQ (TRACE_BOOT_PLATFORM + 0x160)
-#define TRACE_BOOT_PLATFORM_IPC (TRACE_BOOT_PLATFORM + 0x170)
-#define TRACE_BOOT_PLATFORM_DMA (TRACE_BOOT_PLATFORM + 0x180)
-#define TRACE_BOOT_PLATFORM_SSP (TRACE_BOOT_PLATFORM + 0x190)
-#define TRACE_BOOT_PLATFORM_DMIC (TRACE_BOOT_PLATFORM + 0x1a0)
-#define TRACE_BOOT_PLATFORM_IDC (TRACE_BOOT_PLATFORM + 0x1b0)
-
-/* trace event classes - high 8 bits*/
-#define TRACE_CLASS_IRQ (1 << 24)
-#define TRACE_CLASS_IPC (2 << 24)
-#define TRACE_CLASS_PIPE (3 << 24)
-#define TRACE_CLASS_HOST (4 << 24)
-#define TRACE_CLASS_DAI (5 << 24)
-#define TRACE_CLASS_DMA (6 << 24)
-#define TRACE_CLASS_SSP (7 << 24)
-#define TRACE_CLASS_COMP (8 << 24)
-#define TRACE_CLASS_WAIT (9 << 24)
-#define TRACE_CLASS_LOCK (10 << 24)
-#define TRACE_CLASS_MEM (11 << 24)
-#define TRACE_CLASS_MIXER (12 << 24)
-#define TRACE_CLASS_BUFFER (13 << 24)
-#define TRACE_CLASS_VOLUME (14 << 24)
-#define TRACE_CLASS_SWITCH (15 << 24)
-#define TRACE_CLASS_MUX (16 << 24)
-#define TRACE_CLASS_SRC (17 << 24)
-#define TRACE_CLASS_TONE (18 << 24)
-#define TRACE_CLASS_EQ_FIR (19 << 24)
-#define TRACE_CLASS_EQ_IIR (20 << 24)
-#define TRACE_CLASS_SA (21 << 24)
-#define TRACE_CLASS_DMIC (22 << 24)
-#define TRACE_CLASS_POWER (23 << 24)
-#define TRACE_CLASS_IDC (24 << 24)
-
-/* move to config.h */
-#define TRACE 1
-#define TRACEV 0
-#define TRACEE 1
-#define TRACEM 0 /* send all trace messages to mbox and local trace buffer */
-
-void _trace_event(uint32_t event);
-void _trace_event_mbox(uint32_t event);
-void _trace_event_atomic(uint32_t event);
-void _trace_event_mbox_atomic(uint32_t event);
-void trace_flush(void);
-void trace_off(void);
-void trace_init(struct sof *sof);
-
-#if TRACE
-
-/* send all trace to mbox and local trace buffer */
-#if TRACEM
-#define trace_event(__c, __e) \
- _trace_event_mbox(__c | (__e[0] << 16) | (__e[1] << 8) | __e[2])
-#define trace_event_atomic(__c, __e) \
- _trace_event_mbox_atomic(__c | (__e[0] << 16) | (__e[1] << 8) | __e[2])
-/* send trace events only to the local trace buffer */
-#else
-#define trace_event(__c, __e) \
- _trace_event(__c | (__e[0] << 16) | (__e[1] <<8) | __e[2])
-#define trace_event_atomic(__c, __e) \
- _trace_event_atomic(__c | (__e[0] << 16) | (__e[1] <<8) | __e[2])
-#endif
-#define trace_value(x) _trace_event(x)
-#define trace_value_atomic(x) _trace_event_atomic(x)
-
-#define trace_point(x) platform_trace_point(x)
-
-/* verbose tracing */
-#if TRACEV
-#define tracev_event(__c, __e) trace_event(__c, __e)
-#define tracev_value(x) _trace_event(x)
-#define tracev_event_atomic(__c, __e) trace_event_atomic(__c, __e)
-#define tracev_value_atomic(x) _trace_event_atomic(x)
-#else
-#define tracev_event(__c, __e)
-#define tracev_value(x)
-#define tracev_event_atomic(__c, __e)
-#define tracev_value_atomic(x)
-#endif
-
-/* error tracing */
-#if TRACEE
-#define trace_error(__c, __e) \
- _trace_event_mbox_atomic(__c | (__e[0] << 16) | (__e[1] << 8) | __e[2])
-#define trace_error_atomic(__c, __e) \
- _trace_event_mbox_atomic(__c | (__e[0] << 16) | (__e[1] << 8) | __e[2])
-/* write back error value to mbox */
-#define trace_error_value(x) _trace_event_mbox_atomic(x)
-#define trace_error_value_atomic(x) _trace_event_mbox_atomic(x)
-#else
-#define trace_error(__c, __e)
-#define trace_error_atomic(__c, __e)
-#define trace_error_value(x)
-#define trace_error_value_atomic(x)
-#endif
-
-#else
-
-#define trace_event(x, e)
-#define trace_error(c, e)
-#define trace_value(x)
-#define trace_point(x)
-#define tracev_event(__c, __e)
-#define tracev_value(x)
-
-#endif
-
-#endif
diff --git a/src/include/sof/wait.h b/src/include/sof/wait.h
deleted file mode 100644
index feb8b29..0000000
--- a/src/include/sof/wait.h
+++ /dev/null
@@ -1,160 +0,0 @@
-/*
- * Copyright (c) 2016, Intel Corporation
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- * * Redistributions of source code must retain the above copyright
- * notice, this list of conditions and the following disclaimer.
- * * Redistributions in binary form must reproduce the above copyright
- * notice, this list of conditions and the following disclaimer in the
- * documentation and/or other materials provided with the distribution.
- * * Neither the name of the Intel Corporation nor the
- * names of its contributors may be used to endorse or promote products
- * derived from this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
- * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
- * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
- * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
- * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
- * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
- * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
- * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
- * POSSIBILITY OF SUCH DAMAGE.
- *
- * Author: Liam Girdwood <liam.r.girdwood@linux.intel.com>
- *
- * Simple wait for event completion and signaling with timeouts.
- */
-
-#ifndef __INCLUDE_WAIT__
-#define __INCLUDE_WAIT__
-
-#include <stdint.h>
-#include <errno.h>
-#include <arch/wait.h>
-#include <sof/debug.h>
-#include <sof/work.h>
-#include <sof/timer.h>
-#include <sof/interrupt.h>
-#include <sof/trace.h>
-#include <sof/lock.h>
-#include <platform/interrupt.h>
-
-#if DEBUG_LOCKS
-#define wait_atomic_check \
- if (lock_dbg_atomic) { \
- trace_error_atomic(TRACE_CLASS_WAIT, "atm"); \
- }
-#else
-#define wait_atomic_check
-#endif
-
-typedef struct {
- uint32_t complete;
- struct work work;
- uint64_t timeout;
-} completion_t;
-
-void arch_wait_for_interrupt(int level);
-
-static inline void wait_for_interrupt(int level)
-{
- tracev_event(TRACE_CLASS_WAIT, "WFE");
- wait_atomic_check;
- arch_wait_for_interrupt(level);
- tracev_event(TRACE_CLASS_WAIT, "WFX");
-}
-
-static uint64_t _wait_cb(void *data, uint64_t delay)
-{
- volatile completion_t *wc = (volatile completion_t*)data;
-
- wc->timeout = 1;
- return 0;
-}
-
-static inline uint32_t wait_is_completed(completion_t *comp)
-{
- volatile completion_t *c = (volatile completion_t *)comp;
-
- return c->complete;
-}
-
-static inline void wait_completed(completion_t *comp)
-{
- volatile completion_t *c = (volatile completion_t *)comp;
-
- c->complete = 1;
-}
-
-static inline void wait_init(completion_t *comp)
-{
- volatile completion_t *c = (volatile completion_t *)comp;
-
- c->complete = 0;
- work_init(&comp->work, _wait_cb, comp, WORK_ASYNC);
-}
-
-static inline void wait_clear(completion_t *comp)
-{
- volatile completion_t *c = (volatile completion_t *)comp;
-
- c->complete = 0;
-}
-
-/* simple interrupt based wait for completion */
-static inline void wait_for_completion(completion_t *comp)
-{
- /* check for completion after every wake from IRQ */
- while (comp->complete == 0)
- wait_for_interrupt(0);
-}
-
-
-/* simple interrupt based wait for completion with timeout */
-static inline int wait_for_completion_timeout(completion_t *comp)
-{
- volatile completion_t *c = (volatile completion_t *)comp;
-
- work_schedule_default(&comp->work, comp->timeout);
- comp->timeout = 0;
-
- /* check for completion after every wake from IRQ */
- while (1) {
-
- if (c->complete || c->timeout)
- break;
-
- wait_for_interrupt(0);
- }
-
- /* did we complete */
- if (c->complete) {
- /* no timeout so cancel work and return 0 */
- work_cancel_default(&comp->work);
- return 0;
- } else {
- /* timeout */
- trace_error_value(c->timeout);
- trace_error_value(c->complete);
- return -ETIME;
- }
-}
-
-/**
- * \brief Waits at least passed number of clocks.
- * \param[in] number_of_clks Minimum number of clocks to wait.
- */
-static inline void wait_delay(uint64_t number_of_clks)
-{
- uint64_t current = platform_timer_get(platform_timer);
-
- while ((platform_timer_get(platform_timer) - current) < number_of_clks)
- idelay(PLATFORM_DEFAULT_DELAY);
-}
-
-#endif
diff --git a/src/include/sof/work.h b/src/include/sof/work.h
deleted file mode 100644
index a4493a7..0000000
--- a/src/include/sof/work.h
+++ /dev/null
@@ -1,88 +0,0 @@
-/*
- * Copyright (c) 2016, Intel Corporation
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- * * Redistributions of source code must retain the above copyright
- * notice, this list of conditions and the following disclaimer.
- * * Redistributions in binary form must reproduce the above copyright
- * notice, this list of conditions and the following disclaimer in the
- * documentation and/or other materials provided with the distribution.
- * * Neither the name of the Intel Corporation nor the
- * names of its contributors may be used to endorse or promote products
- * derived from this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
- * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
- * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
- * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
- * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
- * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
- * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
- * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
- * POSSIBILITY OF SUCH DAMAGE.
- *
- * Author: Liam Girdwood <liam.r.girdwood@linux.intel.com>
- *
- * Delayed or scheduled work. Work runs in the same context as it's timer
- * interrupt source. It should execute quickly and must not sleep or wait.
- */
-
-#ifndef __INCLUDE_WORK__
-#define __INCLUDE_WORK__
-
-#include <stdint.h>
-#include <sof/list.h>
-#include <sof/timer.h>
-
-struct work_queue;
-
-/* flags */
-#define WORK_ASYNC (0 << 0) /* default - work is scheduled asynchronously */
-#define WORK_SYNC (1 << 0) /* work is scheduled synchronously */
-
-struct work {
- uint64_t (*cb)(void*, uint64_t udelay); /* returns reschedule timeout in msecs */
- void *cb_data;
- struct list_item list;
- uint64_t timeout;
- uint32_t pending;
- uint32_t flags;
-};
-
-struct work_queue_timesource {
- struct timer timer;
- int clk;
- int notifier;
- int (*timer_set)(struct timer *, uint64_t ticks);
- void (*timer_clear)(struct timer *);
- uint64_t (*timer_get)(struct timer *);
-};
-
-/* initialise our work */
-#define work_init(w, x, xd, xflags) \
- (w)->cb = x; \
- (w)->cb_data = xd; \
- (w)->flags = xflags;
-
-/* schedule/cancel work on work queue */
-void work_schedule(struct work_queue *queue, struct work *w, uint64_t timeout);
-void work_reschedule(struct work_queue *queue, struct work *w, uint64_t timeout);
-void work_cancel(struct work_queue *queue, struct work *work);
-
-/* schedule/cancel work on default system work queue */
-void work_schedule_default(struct work *work, uint64_t timeout);
-void work_reschedule_default(struct work *work, uint64_t timeout);
-void work_reschedule_default_at(struct work *w, uint64_t time);
-void work_cancel_default(struct work *work);
-
-/* create new work queue */
-struct work_queue *work_new_queue(struct work_queue_timesource *ts);
-
-/* init system workq */
-void init_system_workq(struct work_queue_timesource *ts);
-
-#endif
diff --git a/src/include/uapi/Makefile.am b/src/include/uapi/Makefile.am
deleted file mode 100644
index 327f97d..0000000
--- a/src/include/uapi/Makefile.am
+++ /dev/null
@@ -1,8 +0,0 @@
-includedir = $(prefix)/include/sof/uapi
-
-include_HEADERS = \
- ipc.h \
- abi.h \
- eq.h \
- tone.h \
- manifest.h
diff --git a/src/include/uapi/abi.h b/src/include/uapi/abi.h
deleted file mode 100644
index cb28aea..0000000
--- a/src/include/uapi/abi.h
+++ /dev/null
@@ -1,62 +0,0 @@
-/*
- * Copyright (c) 2016, Intel Corporation
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- * * Redistributions of source code must retain the above copyright
- * notice, this list of conditions and the following disclaimer.
- * * Redistributions in binary form must reproduce the above copyright
- * notice, this list of conditions and the following disclaimer in the
- * documentation and/or other materials provided with the distribution.
- * * Neither the name of the Intel Corporation nor the
- * names of its contributors may be used to endorse or promote products
- * derived from this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
- * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
- * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
- * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
- * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
- * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
- * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
- * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
- * POSSIBILITY OF SUCH DAMAGE.
- *
- * Author: Liam Girdwood <liam.r.girdwood@linux.intel.com>
- */
-
-/**
- * \file include/uapi/abi.h
- * \brief ABI definitions
- * \author Liam Girdwood <liam.r.girdwood@linux.intel.com>
- */
-
-#ifndef __INCLUDE_UAPI_ABI_H__
-#define __INCLUDE_UAPI_ABI_H__
-
-/** \brief SOF ABI version number. */
-#define SOF_ABI_VERSION 1
-
-/** \brief SOF ABI magic number "SOF\0". */
-#define SOF_ABI_MAGIC 0x00464F53
-
-/**
- * \brief Header for all non IPC ABI data.
- *
- * Identifies data type, size and ABI.
- * Used by any bespoke component data structures or binary blobs.
- */
-struct sof_abi_hdr {
- uint32_t magic; /**< 'S', 'O', 'F', '\0' */
- uint32_t type; /**< component specific type */
- uint32_t size; /**< size in bytes of data excl. this struct */
- uint32_t abi; /**< SOF ABI version */
- uint32_t comp_abi; /**< component specific ABI version */
- char data[0]; /**< data */
-} __attribute__((packed));
-
-#endif
-
diff --git a/src/include/uapi/eq.h b/src/include/uapi/eq.h
deleted file mode 100644
index 0be012c..0000000
--- a/src/include/uapi/eq.h
+++ /dev/null
@@ -1,148 +0,0 @@
-/*
- * Copyright (c) 2017, Intel Corporation
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- * * Redistributions of source code must retain the above copyright
- * notice, this list of conditions and the following disclaimer.
- * * Redistributions in binary form must reproduce the above copyright
- * notice, this list of conditions and the following disclaimer in the
- * documentation and/or other materials provided with the distribution.
- * * Neither the name of the Intel Corporation nor the
- * names of its contributors may be used to endorse or promote products
- * derived from this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
- * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
- * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
- * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
- * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
- * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
- * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
- * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
- * POSSIBILITY OF SUCH DAMAGE.
- *
- * Author: Seppo Ingalsuo <seppo.ingalsuo@linux.intel.com>
- */
-
-#ifndef EQ_H
-#define EQ_H
-
-/* FIR EQ type */
-
-/* Component will reject non-matching configuration. The version number need
- * to be incremented with any ABI changes in function fir_cmd().
- */
-#define SOF_EQ_FIR_ABI_VERSION 1
-
-#define SOF_EQ_FIR_IDX_SWITCH 0
-
-#define SOF_EQ_FIR_MAX_SIZE 4096 /* Max size allowed for coef data in bytes */
-
-#define SOF_EQ_FIR_MAX_LENGTH 192 /* Max length for individual filter */
-
-/*
- * eq_fir_configuration data structure contains this information
- * uint32_t size
- * This is the number of bytes need to store the received EQ
- * configuration.
- * uint16_t channels_in_config
- * This describes the number of channels in this EQ config data. It
- * can be different from PLATFORM_MAX_CHANNELS.
- * uint16_t number_of_responses
- * 0=no responses, 1=one response defined, 2=two responses defined, etc.
- * int16_t data[]
- * assign_response[channels_in_config]
- * 0 = use first response, 1 = use 2nd response, etc.
- * E.g. {0, 0, 0, 0, 1, 1, 1, 1} would apply to channels 0-3 the
- * same first defined response and for to channels 4-7 the second.
- * coef_data[]
- * Repeated data
- * { filter_length, output_shift, h[] }
- * for every EQ response defined where vector h has filter_length
- * number of coefficients. Coefficients in h[] are in Q1.15 format.
- * E.g. 16384 (Q1.15) = 0.5. The shifts are number of right shifts.
- *
- * NOTE: The channels_in_config must be even to have coef_data aligned to
- * 32 bit word in RAM. Therefore a mono EQ assign must be duplicated to 2ch
- * even if it would never used. Similarly a 5ch EQ assign must be increased
- * to 6ch. EQ init will return an error if this is not met.
- *
- * NOTE: The filter_length must be multiple of four. Therefore the filter must
- * be padded from the end with zeros have this condition met.
- */
-
-struct sof_eq_fir_config {
- uint32_t size;
- uint16_t channels_in_config;
- uint16_t number_of_responses;
- int16_t data[];
-};
-
-struct sof_eq_fir_coef_data {
- int16_t length; /* Number of FIR taps */
- int16_t out_shift; /* Amount of right shifts at output */
- int16_t coef[]; /* FIR coefficients */
-};
-
-/* In the struct above there's two words (length, shift) before the actual
- * FIR coefficients. This information is used in parsing of the config blob.
- */
-#define SOF_EQ_FIR_COEF_NHEADER 2
-
-/* IIR EQ type */
-
-/* Component will reject non-matching configuration. The version number need
- * to be incremented with any ABI changes in function fir_cmd().
- */
-#define SOF_EQ_IIR_ABI_VERSION 1
-
-#define SOF_EQ_IIR_IDX_SWITCH 0
-
-#define SOF_EQ_IIR_MAX_SIZE 1024 /* Max size allowed for coef data in bytes */
-
-/* eq_iir_configuration
- * uint32_t channels_in_config
- * This describes the number of channels in this EQ config data. It
- * can be different from PLATFORM_MAX_CHANNELS.
- * uint32_t number_of_responses_defined
- * 0=no responses, 1=one response defined, 2=two responses defined, etc.
- * int32_t data[]
- * Data consist of two parts. First is the response assign vector that
- * has length of channels_in_config. The latter part is coefficient
- * data.
- * uint32_t assign_response[channels_in_config]
- * -1 = not defined, 0 = use first response, 1 = use 2nd, etc.
- * E.g. {0, 0, 0, 0, -1, -1, -1, -1} would apply to channels 0-3 the
- * same first defined response and leave channels 4-7 unequalized.
- * coefficient_data[]
- * <1st EQ>
- * uint32_t num_biquads
- * uint32_t num_biquads_in_series
- * <1st biquad>
- * int32_t coef_a2 Q2.30 format
- * int32_t coef_a1 Q2.30 format
- * int32_t coef_b2 Q2.30 format
- * int32_t coef_b1 Q2.30 format
- * int32_t coef_b0 Q2.30 format
- * int32_t output_shift number of shifts right, shift left is negative
- * int32_t output_gain Q2.14 format
- * <2nd biquad>
- * ...
- * <2nd EQ>
- *
- * Note: A flat response biquad can be made with a section set to
- * b0 = 1.0, gain = 1.0, and other parameters set to 0
- * {0, 0, 0, 0, 1073741824, 0, 16484}
- */
-
-struct sof_eq_iir_config {
- uint32_t channels_in_config;
- uint32_t number_of_responses;
- int32_t data[];
-};
-
-#endif /* EQ_H */
diff --git a/src/include/uapi/ipc.h b/src/include/uapi/ipc.h
deleted file mode 100644
index 48fb43c..0000000
--- a/src/include/uapi/ipc.h
+++ /dev/null
@@ -1,979 +0,0 @@
-/*
- * Copyright (c) 2016, Intel Corporation
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- * * Redistributions of source code must retain the above copyright
- * notice, this list of conditions and the following disclaimer.
- * * Redistributions in binary form must reproduce the above copyright
- * notice, this list of conditions and the following disclaimer in the
- * documentation and/or other materials provided with the distribution.
- * * Neither the name of the Intel Corporation nor the
- * names of its contributors may be used to endorse or promote products
- * derived from this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
- * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
- * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
- * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
- * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
- * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
- * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
- * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
- * POSSIBILITY OF SUCH DAMAGE.
- *
- * Author: Liam Girdwood <liam.r.girdwood@linux.intel.com>
- * Keyon Jie <yang.jie@linux.intel.com>
- */
-
-/**
- * \file include/uapi/ipc.h
- * \brief IPC definitions
- * \author Liam Girdwood <liam.r.girdwood@linux.intel.com>
- * \author Keyon Jie <yang.jie@linux.intel.com>
- */
-
-#ifndef __INCLUDE_UAPI_IPC_H__
-#define __INCLUDE_UAPI_IPC_H__
-
-#include <uapi/abi.h>
-
-/** \addtogroup sof_uapi uAPI
- * SOF uAPI specification.
- * @{
- */
-
-/*
- * IPC messages have a prefixed 32 bit identifier made up as follows :-
- *
- * 0xGCCCNNNN where
- * G is global cmd type (4 bits)
- * C is command type (12 bits)
- * I is the ID number (16 bits) - monotonic and overflows
- *
- * This is sent at the start of the IPM message in the mailbox. Messages should
- * not be sent in the doorbell (special exceptions for firmware .
- */
-
-/* Global Message - Generic */
-#define SOF_GLB_TYPE_SHIFT 28
-#define SOF_GLB_TYPE_MASK (0xf << SOF_GLB_TYPE_SHIFT)
-#define SOF_GLB_TYPE(x) ((x) << SOF_GLB_TYPE_SHIFT)
-
-/* Command Message - Generic */
-#define SOF_CMD_TYPE_SHIFT 16
-#define SOF_CMD_TYPE_MASK (0xfff << SOF_CMD_TYPE_SHIFT)
-#define SOF_CMD_TYPE(x) ((x) << SOF_CMD_TYPE_SHIFT)
-
-/* Global Message Types */
-#define SOF_IPC_GLB_REPLY SOF_GLB_TYPE(0x1U)
-#define SOF_IPC_GLB_COMPOUND SOF_GLB_TYPE(0x2U)
-#define SOF_IPC_GLB_TPLG_MSG SOF_GLB_TYPE(0x3U)
-#define SOF_IPC_GLB_PM_MSG SOF_GLB_TYPE(0x4U)
-#define SOF_IPC_GLB_COMP_MSG SOF_GLB_TYPE(0x5U)
-#define SOF_IPC_GLB_STREAM_MSG SOF_GLB_TYPE(0x6U)
-#define SOF_IPC_FW_READY SOF_GLB_TYPE(0x7U)
-#define SOF_IPC_GLB_DAI_MSG SOF_GLB_TYPE(0x8U)
-#define SOF_IPC_GLB_TRACE_MSG SOF_GLB_TYPE(0x9U)
-
-/*
- * DSP Command Message Types
- */
-
-/* topology */
-#define SOF_IPC_TPLG_COMP_NEW SOF_CMD_TYPE(0x001)
-#define SOF_IPC_TPLG_COMP_FREE SOF_CMD_TYPE(0x002)
-#define SOF_IPC_TPLG_COMP_CONNECT SOF_CMD_TYPE(0x003)
-#define SOF_IPC_TPLG_PIPE_NEW SOF_CMD_TYPE(0x010)
-#define SOF_IPC_TPLG_PIPE_FREE SOF_CMD_TYPE(0x011)
-#define SOF_IPC_TPLG_PIPE_CONNECT SOF_CMD_TYPE(0x012)
-#define SOF_IPC_TPLG_PIPE_COMPLETE SOF_CMD_TYPE(0x013)
-#define SOF_IPC_TPLG_BUFFER_NEW SOF_CMD_TYPE(0x020)
-#define SOF_IPC_TPLG_BUFFER_FREE SOF_CMD_TYPE(0x021)
-
-/* PM */
-#define SOF_IPC_PM_CTX_SAVE SOF_CMD_TYPE(0x001)
-#define SOF_IPC_PM_CTX_RESTORE SOF_CMD_TYPE(0x002)
-#define SOF_IPC_PM_CTX_SIZE SOF_CMD_TYPE(0x003)
-#define SOF_IPC_PM_CLK_SET SOF_CMD_TYPE(0x004)
-#define SOF_IPC_PM_CLK_GET SOF_CMD_TYPE(0x005)
-#define SOF_IPC_PM_CLK_REQ SOF_CMD_TYPE(0x006)
-#define SOF_IPC_PM_CORE_ENABLE SOF_CMD_TYPE(0x007)
-
-/* component runtime config - multiple different types */
-#define SOF_IPC_COMP_SET_VALUE SOF_CMD_TYPE(0x001)
-#define SOF_IPC_COMP_GET_VALUE SOF_CMD_TYPE(0x002)
-#define SOF_IPC_COMP_SET_DATA SOF_CMD_TYPE(0x003)
-#define SOF_IPC_COMP_GET_DATA SOF_CMD_TYPE(0x004)
-
-/* DAI messages */
-#define SOF_IPC_DAI_CONFIG SOF_CMD_TYPE(0x001)
-#define SOF_IPC_DAI_LOOPBACK SOF_CMD_TYPE(0x002)
-
-/* stream */
-#define SOF_IPC_STREAM_PCM_PARAMS SOF_CMD_TYPE(0x001)
-#define SOF_IPC_STREAM_PCM_PARAMS_REPLY SOF_CMD_TYPE(0x002)
-#define SOF_IPC_STREAM_PCM_FREE SOF_CMD_TYPE(0x003)
-#define SOF_IPC_STREAM_TRIG_START SOF_CMD_TYPE(0x004)
-#define SOF_IPC_STREAM_TRIG_STOP SOF_CMD_TYPE(0x005)
-#define SOF_IPC_STREAM_TRIG_PAUSE SOF_CMD_TYPE(0x006)
-#define SOF_IPC_STREAM_TRIG_RELEASE SOF_CMD_TYPE(0x007)
-#define SOF_IPC_STREAM_TRIG_DRAIN SOF_CMD_TYPE(0x008)
-#define SOF_IPC_STREAM_TRIG_XRUN SOF_CMD_TYPE(0x009)
-#define SOF_IPC_STREAM_POSITION SOF_CMD_TYPE(0x00a)
-#define SOF_IPC_STREAM_VORBIS_PARAMS SOF_CMD_TYPE(0x010)
-#define SOF_IPC_STREAM_VORBIS_FREE SOF_CMD_TYPE(0x011)
-
-/* trace and debug */
-#define SOF_IPC_TRACE_DMA_PARAMS SOF_CMD_TYPE(0x001)
-#define SOF_IPC_TRACE_DMA_POSITION SOF_CMD_TYPE(0x002)
-
-/* Get message component id */
-#define SOF_IPC_MESSAGE_ID(x) ((x) & 0xffff)
-
-/* maximum message size for mailbox Tx/Rx */
-#define SOF_IPC_MSG_MAX_SIZE 128
-
-/*
- * SOF panic codes
- */
-#define SOF_IPC_PANIC_MAGIC 0x0dead000
-#define SOF_IPC_PANIC_MAGIC_MASK 0x0ffff000
-#define SOF_IPC_PANIC_CODE_MASK 0x00000fff
-#define SOF_IPC_PANIC_MEM (SOF_IPC_PANIC_MAGIC | 0)
-#define SOF_IPC_PANIC_WORK (SOF_IPC_PANIC_MAGIC | 1)
-#define SOF_IPC_PANIC_IPC (SOF_IPC_PANIC_MAGIC | 2)
-#define SOF_IPC_PANIC_ARCH (SOF_IPC_PANIC_MAGIC | 3)
-#define SOF_IPC_PANIC_PLATFORM (SOF_IPC_PANIC_MAGIC | 4)
-#define SOF_IPC_PANIC_TASK (SOF_IPC_PANIC_MAGIC | 5)
-#define SOF_IPC_PANIC_EXCEPTION (SOF_IPC_PANIC_MAGIC | 6)
-#define SOF_IPC_PANIC_DEADLOCK (SOF_IPC_PANIC_MAGIC | 7)
-#define SOF_IPC_PANIC_STACK (SOF_IPC_PANIC_MAGIC | 8)
-#define SOF_IPC_PANIC_IDLE (SOF_IPC_PANIC_MAGIC | 9)
-
-/*
- * SOF memory capabilities, add new ones at the end
- */
-#define SOF_MEM_CAPS_RAM (1 << 0)
-#define SOF_MEM_CAPS_ROM (1 << 1)
-#define SOF_MEM_CAPS_EXT (1 << 2) /* external */
-#define SOF_MEM_CAPS_LP (1 << 3) /* low power */
-#define SOF_MEM_CAPS_HP (1 << 4) /* high performance */
-#define SOF_MEM_CAPS_DMA (1 << 5) /* DMA'able */
-#define SOF_MEM_CAPS_CACHE (1 << 6) /* cacheable */
-#define SOF_MEM_CAPS_EXEC (1 << 7) /* executable */
-
-/*
- * Command Header - Header for all IPC. Identifies IPC message.
- * The size can be greater than the structure size and that means there is
- * extended bespoke data beyond the end of the structure including variable
- * arrays.
- */
-
-struct sof_ipc_hdr {
- uint32_t cmd; /* SOF_IPC_GLB_ + cmd */
- uint32_t size; /* size of structure */
-} __attribute__((packed));
-
-/*
- * Generic reply message. Some commands override this with their own reply
- * types that must include this at start.
- */
-struct sof_ipc_reply {
- struct sof_ipc_hdr hdr;
- int32_t error; /* negative error numbers */
-} __attribute__((packed));
-
-/*
- * Compound commands - SOF_IPC_GLB_COMPOUND.
- *
- * Compound commands are sent to the DSP as a single IPC operation. The
- * commands are split into blocks and each block has a header. This header
- * identifies the command type and the number of commands before the next
- * header.
- */
-
-struct sof_ipc_compound_hdr {
- struct sof_ipc_hdr hdr;
- uint32_t count; /* count of 0 means end of compound sequence */
-} __attribute__((packed));
-
-/*
- * DAI Configuration.
- *
- * Each different DAI type will have it's own structure and IPC cmd.
- */
-
-#define SOF_DAI_FMT_I2S 1 /* I2S mode */
-#define SOF_DAI_FMT_RIGHT_J 2 /* Right Justified mode */
-#define SOF_DAI_FMT_LEFT_J 3 /* Left Justified mode */
-#define SOF_DAI_FMT_DSP_A 4 /* L data MSB after FRM LRC */
-#define SOF_DAI_FMT_DSP_B 5 /* L data MSB during FRM LRC */
-#define SOF_DAI_FMT_PDM 6 /* Pulse density modulation */
-
-#define SOF_DAI_FMT_CONT (1 << 4) /* continuous clock */
-#define SOF_DAI_FMT_GATED (0 << 4) /* clock is gated */
-
-#define SOF_DAI_FMT_NB_NF (0 << 8) /* normal bit clock + frame */
-#define SOF_DAI_FMT_NB_IF (2 << 8) /* normal BCLK + inv FRM */
-#define SOF_DAI_FMT_IB_NF (3 << 8) /* invert BCLK + nor FRM */
-#define SOF_DAI_FMT_IB_IF (4 << 8) /* invert BCLK + FRM */
-
-#define SOF_DAI_FMT_CBM_CFM (0 << 12) /* codec clk & FRM master */
-#define SOF_DAI_FMT_CBS_CFM (2 << 12) /* codec clk slave & FRM master */
-#define SOF_DAI_FMT_CBM_CFS (3 << 12) /* codec clk master & frame slave */
-#define SOF_DAI_FMT_CBS_CFS (4 << 12) /* codec clk & FRM slave */
-
-#define SOF_DAI_FMT_FORMAT_MASK 0x000f
-#define SOF_DAI_FMT_CLOCK_MASK 0x00f0
-#define SOF_DAI_FMT_INV_MASK 0x0f00
-#define SOF_DAI_FMT_MASTER_MASK 0xf000
-
- /* ssc1: TINTE */
-#define SOF_DAI_INTEL_SSP_QUIRK_TINTE (1 << 0)
- /* ssc1: PINTE */
-#define SOF_DAI_INTEL_SSP_QUIRK_PINTE (1 << 1)
- /* ssc2: SMTATF */
-#define SOF_DAI_INTEL_SSP_QUIRK_SMTATF (1 << 2)
- /* ssc2: MMRATF */
-#define SOF_DAI_INTEL_SSP_QUIRK_MMRATF (1 << 3)
- /* ssc2: PSPSTWFDFD */
-#define SOF_DAI_INTEL_SSP_QUIRK_PSPSTWFDFD (1 << 4)
- /* ssc2: PSPSRWFDFD */
-#define SOF_DAI_INTEL_SSP_QUIRK_PSPSRWFDFD (1 << 5)
- /* here is the possibility to define others aux macros */
-
-#define SOF_DAI_INTEL_SSP_FRAME_PULSE_WIDTH_MAX 38
-#define SOF_DAI_INTEL_SSP_SLOT_PADDING_MAX 31
-
-/** \brief Types of DAI */
-enum sof_ipc_dai_type {
- SOF_DAI_INTEL_NONE = 0, /**< None */
- SOF_DAI_INTEL_SSP, /**< Intel SSP */
- SOF_DAI_INTEL_DMIC, /**< Intel DMIC */
- SOF_DAI_INTEL_HDA, /**< Intel HD/A */
-};
-
-/* SSP Configuration Request - SOF_IPC_DAI_SSP_CONFIG */
-struct sof_ipc_dai_ssp_params {
- uint16_t mode; // FIXME: do we need this?
- uint16_t mclk_id;
-
- uint32_t mclk_rate; /* mclk frequency in Hz */
- uint32_t fsync_rate; /* fsync frequency in Hz */
- uint32_t bclk_rate; /* bclk frequency in Hz */
-
- /* TDM */
- uint32_t tdm_slots;
- uint32_t rx_slots;
- uint32_t tx_slots;
-
- /* data */
- uint32_t sample_valid_bits;
- uint16_t tdm_slot_width;
- uint16_t reserved2; /* alignment */
-
- /* MCLK */
- uint32_t mclk_direction;
- uint32_t mclk_keep_active;
- uint32_t bclk_keep_active;
- uint32_t fs_keep_active;
-
- uint16_t frame_pulse_width;
- uint32_t quirks; // FIXME: is 32 bits enough ?
-
- uint16_t tdm_per_slot_padding_flag;
- /* private data, e.g. for quirks */
- //uint32_t pdata[10]; // FIXME: would really need ~16 u32
-} __attribute__((packed));
-
-/* HDA Configuration Request - SOF_IPC_DAI_HDA_CONFIG */
-struct sof_ipc_dai_hda_params {
- struct sof_ipc_hdr hdr;
- /* TODO */
-} __attribute__((packed));
-
-/* DMIC Configuration Request - SOF_IPC_DAI_DMIC_CONFIG */
-
-/* This struct is defined per 2ch PDM controller available in the platform.
- * Normally it is sufficient to set the used microphone specific enables to 1
- * and keep other parameters as zero. The customizations are:
- *
- * 1. If a device mixes different microphones types with different polarity
- * and/or the absolute polarity matters the PCM signal from a microphone
- * can be inverted with the controls.
- *
- * 2. If the microphones in a stereo pair do not appear in captured stream
- * in desired order due to board schematics choises they can be swapped with
- * the clk_edge parameter.
- *
- * 3. If PDM bit errors are seen in capture (poor quality) the skew parameter
- * that delays the sampling time of data by half cycles of DMIC source clock
- * can be tried for improvement. However there is no guarantee for this to fix
- * data integrity problems.
- */
-struct sof_ipc_dai_dmic_pdm_ctrl {
- uint16_t id; /* PDM controller ID */
- uint16_t enable_mic_a; /* Use A (left) channel mic (0 or 1)*/
- uint16_t enable_mic_b; /* Use B (right) channel mic (0 or 1)*/
- uint16_t polarity_mic_a; /* Optionally invert mic A signal (0 or 1) */
- uint16_t polarity_mic_b; /* Optionally invert mic B signal (0 or 1) */
- uint16_t clk_edge; /* Optionally swap data clock edge (0 or 1) */
- uint16_t skew; /* Adjust PDM data sampling vs. clock (0..15) */
- uint16_t pad; /* Make sure the total size is 4 bytes aligned */
-} __attribute__((packed));
-
-/* This struct contains the global settings for all 2ch PDM controllers. The
- * version number used in configuration data is checked vs. version used by
- * device driver src/drivers/dmic.c need to match. It is incremented from
- * initial value 1 if updates done for the to driver would alter the operation
- * of the microhone.
- *
- * Note: The microphone clock (pdmclk_min, pdmclk_max, duty_min, duty_max)
- * parameters need to be set as defined in microphone data sheet. E.g. clock
- * range 1.0 - 3.2 MHz is usually supported microphones. Some microphones are
- * multi-mode capable and there may be denied mic clock frequencies between
- * the modes. In such case set the clock range limits of the desired mode to
- * avoid the driver to set clock to an illegal rate.
- *
- * The duty cycle could be set to 48-52% if not known. Generally these
- * parameters can be altered within data sheet specified limits to match
- * required audio application performance power.
- *
- * The microphone clock needs to be usually about 50-80 times the used audio
- * sample rate. With highest sample rates above 48 kHz this can relaxed
- * somewhat.
- */
-struct sof_ipc_dai_dmic_params {
- uint32_t driver_ipc_version; /* Version (1..N) */
- uint32_t pdmclk_min; /* Minimum microphone clock in Hz (100000..N) */
- uint32_t pdmclk_max; /* Maximum microphone clock in Hz (min...N) */
- uint32_t fifo_fs_a; /* FIFO A sample rate in Hz (8000..96000) */
- uint32_t fifo_fs_b; /* FIFO B sample rate in Hz (8000..96000) */
- uint16_t fifo_bits_a; /* FIFO A word length (16 or 32) */
- uint16_t fifo_bits_b; /* FIFO B word length (16 or 32) */
- uint16_t duty_min; /* Min. mic clock duty cycle in % (20..80) */
- uint16_t duty_max; /* Max. mic clock duty cycle in % (min..80) */
- uint32_t num_pdm_active; /* Number of active pdm controllers */
- /* variable number of pdm controller config */
- struct sof_ipc_dai_dmic_pdm_ctrl pdm[0];
-} __attribute__((packed));
-
-/* general purpose DAI configuration */
-struct sof_ipc_dai_config {
- struct sof_ipc_hdr hdr;
- enum sof_ipc_dai_type type;
- uint32_t dai_index; /* index of this type dai */
-
- /* physical protocol and clocking */
- uint16_t format; /* SOF_DAI_FMT_ */
- uint16_t reserved; /* alignment */
-
- /* HW specific data */
- union {
- struct sof_ipc_dai_ssp_params ssp;
- struct sof_ipc_dai_hda_params hda;
- struct sof_ipc_dai_dmic_params dmic;
- };
-};
-
-/*
- * Stream configuration.
- */
-
-#define SOF_IPC_MAX_CHANNELS 8
-
-/* channel positions - uses same values as ALSA */
-enum sof_ipc_chmap {
- SOF_CHMAP_UNKNOWN = 0,
- SOF_CHMAP_NA, /* N/A, silent */
- SOF_CHMAP_MONO, /* mono stream */
- SOF_CHMAP_FL, /* front left */
- SOF_CHMAP_FR, /* front right */
- SOF_CHMAP_RL, /* rear left */
- SOF_CHMAP_RR, /* rear right */
- SOF_CHMAP_FC, /* front centre */
- SOF_CHMAP_LFE, /* LFE */
- SOF_CHMAP_SL, /* side left */
- SOF_CHMAP_SR, /* side right */
- SOF_CHMAP_RC, /* rear centre */
- SOF_CHMAP_FLC, /* front left centre */
- SOF_CHMAP_FRC, /* front right centre */
- SOF_CHMAP_RLC, /* rear left centre */
- SOF_CHMAP_RRC, /* rear right centre */
- SOF_CHMAP_FLW, /* front left wide */
- SOF_CHMAP_FRW, /* front right wide */
- SOF_CHMAP_FLH, /* front left high */
- SOF_CHMAP_FCH, /* front centre high */
- SOF_CHMAP_FRH, /* front right high */
- SOF_CHMAP_TC, /* top centre */
- SOF_CHMAP_TFL, /* top front left */
- SOF_CHMAP_TFR, /* top front right */
- SOF_CHMAP_TFC, /* top front centre */
- SOF_CHMAP_TRL, /* top rear left */
- SOF_CHMAP_TRR, /* top rear right */
- SOF_CHMAP_TRC, /* top rear centre */
- SOF_CHMAP_TFLC, /* top front left centre */
- SOF_CHMAP_TFRC, /* top front right centre */
- SOF_CHMAP_TSL, /* top side left */
- SOF_CHMAP_TSR, /* top side right */
- SOF_CHMAP_LLFE, /* left LFE */
- SOF_CHMAP_RLFE, /* right LFE */
- SOF_CHMAP_BC, /* bottom centre */
- SOF_CHMAP_BLC, /* bottom left centre */
- SOF_CHMAP_BRC, /* bottom right centre */
- SOF_CHMAP_LAST = SOF_CHMAP_BRC,
-};
-
-/* common sample rates for use in masks */
-#define SOF_RATE_8000 (1 << 0) /* 8000Hz */
-#define SOF_RATE_11025 (1 << 1) /* 11025Hz */
-#define SOF_RATE_12000 (1 << 2) /* 12000Hz */
-#define SOF_RATE_16000 (1 << 3) /* 16000Hz */
-#define SOF_RATE_22050 (1 << 4) /* 22050Hz */
-#define SOF_RATE_24000 (1 << 5) /* 24000Hz */
-#define SOF_RATE_32000 (1 << 6) /* 32000Hz */
-#define SOF_RATE_44100 (1 << 7) /* 44100Hz */
-#define SOF_RATE_48000 (1 << 8) /* 48000Hz */
-#define SOF_RATE_64000 (1 << 9) /* 64000Hz */
-#define SOF_RATE_88200 (1 << 10) /* 88200Hz */
-#define SOF_RATE_96000 (1 << 11) /* 96000Hz */
-#define SOF_RATE_176400 (1 << 12) /* 176400Hz */
-#define SOF_RATE_192000 (1 << 13) /* 192000Hz */
-
-/* continuous and non-standard rates for flexibility */
-#define SOF_RATE_CONTINUOUS (1 << 30) /* range */
-#define SOF_RATE_KNOT (1 << 31) /* non-continuous */
-
-/* stream PCM frame format */
-enum sof_ipc_frame {
- SOF_IPC_FRAME_S16_LE = 0,
- SOF_IPC_FRAME_S24_4LE,
- SOF_IPC_FRAME_S32_LE,
- SOF_IPC_FRAME_FLOAT,
- /* other formats here */
-};
-
-/* stream buffer format */
-enum sof_ipc_buffer_format {
- SOF_IPC_BUFFER_INTERLEAVED,
- SOF_IPC_BUFFER_NONINTERLEAVED,
- /* other formats here */
-};
-
-/* stream direction */
-enum sof_ipc_stream_direction {
- SOF_IPC_STREAM_PLAYBACK = 0,
- SOF_IPC_STREAM_CAPTURE,
-};
-
-/* stream ring info */
-struct sof_ipc_host_buffer {
- uint32_t phy_addr;
- uint32_t pages;
- uint32_t size;
- uint32_t offset;
-} __attribute__((packed));
-
-struct sof_ipc_stream_params {
- struct sof_ipc_host_buffer buffer;
- enum sof_ipc_stream_direction direction;
- enum sof_ipc_frame frame_fmt;
- enum sof_ipc_buffer_format buffer_fmt;
- uint32_t stream_tag;
- uint32_t rate;
- uint32_t channels;
- uint32_t sample_valid_bytes;
- uint32_t sample_container_bytes;
- /* for notifying host period has completed - 0 means no period IRQ */
- uint32_t host_period_bytes;
- enum sof_ipc_chmap chmap[SOF_IPC_MAX_CHANNELS]; /* channel map */
-} __attribute__((packed));
-
-/* PCM params info - SOF_IPC_STREAM_PCM_PARAMS */
-struct sof_ipc_pcm_params {
- struct sof_ipc_hdr hdr;
- uint32_t comp_id;
- struct sof_ipc_stream_params params;
-} __attribute__((packed));
-
-/* PCM params info reply - SOF_IPC_STREAM_PCM_PARAMS_REPLY */
-struct sof_ipc_pcm_params_reply {
- struct sof_ipc_reply rhdr;
- uint32_t comp_id;
- uint32_t posn_offset;
-} __attribute__((packed));
-
-/* compressed vorbis params - SOF_IPC_STREAM_VORBIS_PARAMS */
-struct sof_ipc_vorbis_params {
- struct sof_ipc_hdr hdr;
- uint32_t comp_id;
- struct sof_ipc_stream_params params;
- /* TODO */
-} __attribute__((packed));
-
-/* free stream - SOF_IPC_STREAM_PCM_PARAMS */
-struct sof_ipc_stream {
- struct sof_ipc_hdr hdr;
- uint32_t comp_id;
-} __attribute__((packed));
-
-/* flags indicating which time stamps are in sync with each other */
-#define SOF_TIME_HOST_SYNC (1 << 0)
-#define SOF_TIME_DAI_SYNC (1 << 1)
-#define SOF_TIME_WALL_SYNC (1 << 2)
-#define SOF_TIME_STAMP_SYNC (1 << 3)
-
-/* flags indicating which time stamps are valid */
-#define SOF_TIME_HOST_VALID (1 << 8)
-#define SOF_TIME_DAI_VALID (1 << 9)
-#define SOF_TIME_WALL_VALID (1 << 10)
-#define SOF_TIME_STAMP_VALID (1 << 11)
-
-/* flags indicating time stamps are 64bit else 3use low 32bit */
-#define SOF_TIME_HOST_64 (1 << 16)
-#define SOF_TIME_DAI_64 (1 << 17)
-#define SOF_TIME_WALL_64 (1 << 18)
-#define SOF_TIME_STAMP_64 (1 << 19)
-
-struct sof_ipc_stream_posn {
- struct sof_ipc_reply rhdr;
- uint32_t comp_id; /* host component ID */
- uint32_t flags; /* SOF_TIME_ */
- uint32_t wallclock_hz; /* frequency of wallclock in Hz */
- uint32_t timestamp_ns; /* resolution of timestamp in ns */
- uint64_t host_posn; /* host DMA position in bytes */
- uint64_t dai_posn; /* DAI DMA position in bytes */
- uint64_t comp_posn; /* comp position in bytes */
- uint64_t wallclock; /* audio wall clock */
- uint64_t timestamp; /* system time stamp */
- uint32_t xrun_comp_id; /* comp ID of XRUN component */
- int32_t xrun_size; /* XRUN size in bytes */
-} __attribute__((packed));
-
-/*
- * Component Mixers and Controls
- */
-
-/* control data type and direction */
-enum sof_ipc_ctrl_type {
- /* per channel data - uses struct sof_ipc_ctrl_value_chan */
- SOF_CTRL_TYPE_VALUE_CHAN_GET = 0,
- SOF_CTRL_TYPE_VALUE_CHAN_SET,
- /* component data - uses struct sof_ipc_ctrl_value_comp */
- SOF_CTRL_TYPE_VALUE_COMP_GET,
- SOF_CTRL_TYPE_VALUE_COMP_SET,
- /* bespoke data - struct struct sof_abi_hdr */
- SOF_CTRL_TYPE_DATA_GET,
- SOF_CTRL_TYPE_DATA_SET,
-};
-
-/* control command type */
-enum sof_ipc_ctrl_cmd {
- SOF_CTRL_CMD_VOLUME = 0, /* maps to ALSA volume style controls */
- SOF_CTRL_CMD_ENUM, /* maps to ALSA enum style controls */
- SOF_CTRL_CMD_SWITCH, /* maps to ALSA switch style controls */
- SOF_CTRL_CMD_BINARY, /* maps to ALSA binary style controls */
-};
-
-/* generic channel mapped value data */
-struct sof_ipc_ctrl_value_chan {
- enum sof_ipc_chmap channel;
- uint32_t value;
-} __attribute__((packed));
-
-/* generic component mapped value data */
-struct sof_ipc_ctrl_value_comp {
- uint32_t index; /* component source/sink/control index in control */
- union {
- uint32_t uvalue;
- int32_t svalue;
- };
-} __attribute__((packed));
-
-/* generic control data */
-struct sof_ipc_ctrl_data {
- struct sof_ipc_reply rhdr;
- uint32_t comp_id;
-
- /* control access and data type */
- enum sof_ipc_ctrl_type type;
- enum sof_ipc_ctrl_cmd cmd;
- uint32_t index; /* control index for comps > 1 control */
-
- /* control data - can either be appended or DMAed from host */
- struct sof_ipc_host_buffer buffer;
- uint32_t num_elems; /* in array elems or bytes */
-
- /* control data - add new types if needed */
- union {
- /* channel values can be used by volume type controls */
- struct sof_ipc_ctrl_value_chan chanv[0];
- /* component values used by routing controls like mux, mixer */
- struct sof_ipc_ctrl_value_comp compv[0];
- /* data can be used by binary controls */
- struct sof_abi_hdr data[0];
- };
-} __attribute__((packed));
-
-/*
- * Component
- */
-
-/* types of component */
-enum sof_comp_type {
- SOF_COMP_NONE = 0,
- SOF_COMP_HOST,
- SOF_COMP_DAI,
- SOF_COMP_SG_HOST, /* scatter gather variant */
- SOF_COMP_SG_DAI, /* scatter gather variant */
- SOF_COMP_VOLUME,
- SOF_COMP_MIXER,
- SOF_COMP_MUX,
- SOF_COMP_SRC,
- SOF_COMP_SPLITTER,
- SOF_COMP_TONE,
- SOF_COMP_SWITCH,
- SOF_COMP_BUFFER,
- SOF_COMP_EQ_IIR,
- SOF_COMP_EQ_FIR,
- SOF_COMP_FILEREAD, /* host test based file IO */
- SOF_COMP_FILEWRITE, /* host test based file IO */
-};
-
-/* XRUN action for component */
-#define SOF_XRUN_STOP 1 /* stop stream */
-#define SOF_XRUN_UNDER_ZERO 2 /* send 0s to sink */
-#define SOF_XRUN_OVER_NULL 4 /* send data to NULL */
-
-/* create new generic component - SOF_IPC_TPLG_COMP_NEW */
-struct sof_ipc_comp {
- struct sof_ipc_hdr hdr;
- uint32_t id;
- enum sof_comp_type type;
- uint32_t pipeline_id;
-} __attribute__((packed));
-
-/*
- * Component Buffers
- */
-
-/* create new component buffer - SOF_IPC_TPLG_BUFFER_NEW */
-struct sof_ipc_buffer {
- struct sof_ipc_comp comp;
- uint32_t size; /* buffer size in bytes */
- uint32_t caps; /* SOF_MEM_CAPS_ */
-} __attribute__((packed));
-
-/* generic component config data - must always be after struct sof_ipc_comp */
-struct sof_ipc_comp_config {
- uint32_t periods_sink; /* 0 means variable */
- uint32_t periods_source; /* 0 means variable */
- uint32_t preload_count; /* how many periods to preload */
- enum sof_ipc_frame frame_fmt;
- uint32_t xrun_action;
-} __attribute__((packed));
-
-/* generic host component */
-struct sof_ipc_comp_host {
- struct sof_ipc_comp comp;
- struct sof_ipc_comp_config config;
- enum sof_ipc_stream_direction direction;
- uint32_t no_irq; /* don't send periodic IRQ to host/DSP */
- uint32_t dmac_config; /* DMA engine specific */
-} __attribute__((packed));
-
-/* generic DAI component */
-struct sof_ipc_comp_dai {
- struct sof_ipc_comp comp;
- struct sof_ipc_comp_config config;
- enum sof_ipc_stream_direction direction;
- uint32_t dai_index; /* index of this type dai */
- enum sof_ipc_dai_type type;
- uint32_t dmac_config; /* DMA engine specific */
-} __attribute__((packed));
-
-/* generic mixer component */
-struct sof_ipc_comp_mixer {
- struct sof_ipc_comp comp;
- struct sof_ipc_comp_config config;
-} __attribute__((packed));
-
-/* volume ramping types */
-enum sof_volume_ramp {
- SOF_VOLUME_LINEAR = 0,
- SOF_VOLUME_LOG,
- SOF_VOLUME_LINEAR_ZC,
- SOF_VOLUME_LOG_ZC,
-};
-
-/* generic volume component */
-struct sof_ipc_comp_volume {
- struct sof_ipc_comp comp;
- struct sof_ipc_comp_config config;
- uint32_t channels;
- uint32_t min_value;
- uint32_t max_value;
- enum sof_volume_ramp ramp;
- uint32_t initial_ramp; /* ramp space in ms */
-} __attribute__((packed));
-
-/* generic SRC component */
-struct sof_ipc_comp_src {
- struct sof_ipc_comp comp;
- struct sof_ipc_comp_config config;
- /* either source or sink rate must be non zero */
- uint32_t source_rate; /* source rate or 0 for variable */
- uint32_t sink_rate; /* sink rate or 0 for variable */
- uint32_t rate_mask; /* SOF_RATE_ supported rates */
-} __attribute__((packed));
-
-/* generic MUX component */
-struct sof_ipc_comp_mux {
- struct sof_ipc_comp comp;
- struct sof_ipc_comp_config config;
-} __attribute__((packed));
-
-/* generic tone generator component */
-struct sof_ipc_comp_tone {
- struct sof_ipc_comp comp;
- struct sof_ipc_comp_config config;
- int32_t sample_rate;
- int32_t frequency;
- int32_t amplitude;
- int32_t freq_mult;
- int32_t ampl_mult;
- int32_t length;
- int32_t period;
- int32_t repeats;
- int32_t ramp_step;
-} __attribute__((packed));
-
-/* FIR equalizer component */
-struct sof_ipc_comp_eq_fir {
- struct sof_ipc_comp comp;
- struct sof_ipc_comp_config config;
-} __attribute__((packed));
-
-/* IIR equalizer component */
-struct sof_ipc_comp_eq_iir {
- struct sof_ipc_comp comp;
- struct sof_ipc_comp_config config;
-} __attribute__((packed));
-
-/* frees components, buffers and pipelines
- * SOF_IPC_TPLG_COMP_FREE, SOF_IPC_TPLG_PIPE_FREE, SOF_IPC_TPLG_BUFFER_FREE
- */
-struct sof_ipc_free {
- struct sof_ipc_hdr hdr;
- uint32_t id;
-} __attribute__((packed));
-
-struct sof_ipc_comp_reply {
- struct sof_ipc_reply rhdr;
- uint32_t id;
- uint32_t offset;
-} __attribute__((packed));
-
-/*
- * Pipeline
- */
-
-/* new pipeline - SOF_IPC_TPLG_PIPE_NEW */
-struct sof_ipc_pipe_new {
- struct sof_ipc_hdr hdr;
- uint32_t comp_id; /* component id for pipeline */
- uint32_t pipeline_id; /* pipeline id */
- uint32_t sched_id; /* sheduling component id */
- uint32_t core; /* core we run on */
- uint32_t deadline; /* execution completion deadline in us*/
- uint32_t priority; /* priority level 0 (low) to 10 (max) */
- uint32_t mips; /* worst case instruction count per period */
- uint32_t frames_per_sched;/* output frames of pipeline, 0 is variable */
- uint32_t xrun_limit_usecs; /* report xruns greater than limit */
- uint32_t timer;/* non zero if timer scheduled otherwise DAI scheduled */
-} __attribute__((packed));
-
-/* pipeline construction complete - SOF_IPC_TPLG_PIPE_COMPLETE */
-struct sof_ipc_pipe_ready {
- struct sof_ipc_hdr hdr;
- uint32_t comp_id;
-} __attribute__((packed));
-
-struct sof_ipc_pipe_free {
- struct sof_ipc_hdr hdr;
- uint32_t comp_id;
-} __attribute__((packed));
-
-/* connect two components in pipeline - SOF_IPC_TPLG_COMP_CONNECT */
-struct sof_ipc_pipe_comp_connect {
- struct sof_ipc_hdr hdr;
- uint32_t source_id;
- uint32_t sink_id;
-} __attribute__((packed));
-
-/*
- * PM
- */
-
-/* PM context element */
-struct sof_ipc_pm_ctx_elem {
- uint32_t type;
- uint32_t size;
- uint64_t addr;
-} __attribute__((packed));
-
-/*
- * PM context - SOF_IPC_PM_CTX_SAVE, SOF_IPC_PM_CTX_RESTORE,
- * SOF_IPC_PM_CTX_SIZE
- */
-struct sof_ipc_pm_ctx {
- struct sof_ipc_hdr hdr;
- struct sof_ipc_host_buffer buffer;
- uint32_t num_elems;
- uint32_t size;
- struct sof_ipc_pm_ctx_elem elems[];
-};
-
-/* enable or disable cores - SOF_IPC_PM_CORE_ENABLE */
-struct sof_ipc_pm_core_config {
- struct sof_ipc_hdr hdr;
- uint32_t enable_mask;
-};
-
-/*
- * Firmware boot and version
- */
-
-#define SOF_IPC_MAX_ELEMS 16
-
-/* extended data types that can be appended onto end of sof_ipc_fw_ready */
-enum sof_ipc_ext_data {
- SOF_IPC_EXT_DMA_BUFFER = 0,
- SOF_IPC_EXT_WINDOW,
-};
-
-/* FW version - SOF_IPC_GLB_VERSION */
-struct sof_ipc_fw_version {
- uint16_t major;
- uint16_t minor;
- uint16_t build;
- uint8_t date[12];
- uint8_t time[10];
- uint8_t tag[6];
- uint8_t pad[2]; /* Make sure the total size is 4 bytes aligned */
-} __attribute__((packed));
-
-/* FW ready Message - sent by firmware when boot has completed */
-struct sof_ipc_fw_ready {
- struct sof_ipc_hdr hdr;
- uint32_t dspbox_offset; /* dsp initiated IPC mailbox */
- uint32_t hostbox_offset; /* host initiated IPC mailbox */
- uint32_t dspbox_size;
- uint32_t hostbox_size;
- struct sof_ipc_fw_version version;
-} __attribute__((packed));
-
-/*
- * Extended Firmware data. All optional, depends on platform/arch.
- */
-
-enum sof_ipc_region {
- SOF_IPC_REGION_DOWNBOX = 0,
- SOF_IPC_REGION_UPBOX,
- SOF_IPC_REGION_TRACE,
- SOF_IPC_REGION_DEBUG,
- SOF_IPC_REGION_STREAM,
- SOF_IPC_REGION_REGS,
- SOF_IPC_REGION_EXCEPTION,
-};
-
-struct sof_ipc_ext_data_hdr {
- struct sof_ipc_hdr hdr;
- enum sof_ipc_ext_data type; /* SOF_IPC_EXT_ */
-};
-
-struct sof_ipc_dma_buffer_elem {
- enum sof_ipc_region type;
- uint32_t id; /* platform specific - used to map to host memory */
- struct sof_ipc_host_buffer buffer;
-};
-
-/* extended data DMA buffers for IPC, trace and debug */
-struct sof_ipc_dma_buffer_data {
- struct sof_ipc_ext_data_hdr ext_hdr;
- uint32_t num_buffers;
- /* host files in buffer[n].buffer */
- struct sof_ipc_dma_buffer_elem buffer[];
-} __attribute__((packed));
-
-struct sof_ipc_window_elem {
- enum sof_ipc_region type;
- uint32_t id; /* platform specific - used to map to host memory */
- uint32_t flags; /* R, W, RW, etc - to define */
- uint32_t size; /* size of region in bytes */
- /* offset in window region as windows can be partitioned */
- uint32_t offset;
-};
-
-/* extended data memory windows for IPC, trace and debug */
-struct sof_ipc_window {
- struct sof_ipc_ext_data_hdr ext_hdr;
- uint32_t num_windows;
- struct sof_ipc_window_elem window[];
-} __attribute__((packed));
-
-/*
- * DMA for Trace
- */
-
-/* DMA for Trace params info - SOF_IPC_DEBUG_DMA_PARAMS */
-struct sof_ipc_dma_trace_params {
- struct sof_ipc_hdr hdr;
- struct sof_ipc_host_buffer buffer;
- uint32_t stream_tag;
-} __attribute__((packed));
-
-/* DMA for Trace params info - SOF_IPC_DEBUG_DMA_PARAMS */
-struct sof_ipc_dma_trace_posn {
- struct sof_ipc_reply rhdr;
- uint32_t host_offset; /* Offset of DMA host buffer */
- uint32_t overflow; /* overflow bytes if any */
- uint32_t messages; /* total trace messages */
-} __attribute__((packed));
-
-/*
- * Architecture specific debug
- */
-
-/* Xtensa Firmware Oops data */
-struct sof_ipc_dsp_oops_xtensa {
- uint32_t exccause;
- uint32_t excvaddr;
- uint32_t ps;
- uint32_t epc1;
- uint32_t epc2;
- uint32_t epc3;
- uint32_t epc4;
- uint32_t epc5;
- uint32_t epc6;
- uint32_t epc7;
- uint32_t eps2;
- uint32_t eps3;
- uint32_t eps4;
- uint32_t eps5;
- uint32_t eps6;
- uint32_t eps7;
- uint32_t depc;
- uint32_t intenable;
- uint32_t interrupt;
- uint32_t sar;
- uint32_t stack;
-} __attribute__((packed));
-
-/** @}*/
-
-#endif
diff --git a/src/include/uapi/manifest.h b/src/include/uapi/manifest.h
deleted file mode 100644
index c1dce92..0000000
--- a/src/include/uapi/manifest.h
+++ /dev/null
@@ -1,235 +0,0 @@
-/*
- * Copyright (c) 2017, Intel Corporation
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- * * Redistributions of source code must retain the above copyright
- * notice, this list of conditions and the following disclaimer.
- * * Redistributions in binary form must reproduce the above copyright
- * notice, this list of conditions and the following disclaimer in the
- * documentation and/or other materials provided with the distribution.
- * * Neither the name of the Intel Corporation nor the
- * names of its contributors may be used to endorse or promote products
- * derived from this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
- * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
- * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
- * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
- * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
- * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
- * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
- * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
- * POSSIBILITY OF SUCH DAMAGE.
- *
- * Author: Liam Girdwood <liam.r.girdwood@linux.intel.com>
- */
-
-/**
- * \file include/uapi/ipc.h
- * \brief FW Image Manifest definitions.
- * \author Liam Girdwood <liam.r.girdwood@linux.intel.com>
- */
-
-#ifndef SOF_UAPI_MANIFEST_H
-#define SOF_UAPI_MANIFEST_H
-
-#include <stdint.h>
-
-/* start offset for base FW module */
-#define SOF_MAN_ELF_TEXT_OFFSET 0x2000
-
-/* FW Extended Manifest Header id = $AE1 */
-#define SOF_MAN_EXT_HEADER_MAGIC 0x31454124
-
-/* module type load type */
-#define SOF_MAN_MOD_TYPE_BUILTIN 0
-#define SOF_MAN_MOD_TYPE_MODULE 1
-
-struct sof_man_module_type {
- uint32_t load_type:4; /* SOF_MAN_MOD_TYPE_ */
- uint32_t auto_start:1;
- uint32_t domain_ll:1;
- uint32_t domain_dp:1;
- uint32_t rsvd_:25;
-};
-
-/* segment flags.type */
-#define SOF_MAN_SEGMENT_TEXT 0
-#define SOF_MAN_SEGMENT_RODATA 1
-#define SOF_MAN_SEGMENT_DATA 1
-#define SOF_MAN_SEGMENT_BSS 2
-#define SOF_MAN_SEGMENT_EMPTY 15
-
-union sof_man_segment_flags {
- uint32_t ul;
- struct {
- uint32_t contents:1;
- uint32_t alloc:1;
- uint32_t load:1;
- uint32_t readonly:1;
- uint32_t code:1;
- uint32_t data:1;
- uint32_t _rsvd0:2;
- uint32_t type:4; /* MAN_SEGMENT_ */
- uint32_t _rsvd1:4;
- uint32_t length:16; /* of segment in pages */
- } r;
-} __attribute__((packed));
-
-/*
- * Module segment descriptor. Used by ROM - Immutable.
- */
-struct sof_man_segment_desc {
- union sof_man_segment_flags flags;
- uint32_t v_base_addr;
- uint32_t file_offset;
-} __attribute__((packed));
-
-/*
- * The firmware binary can be split into several modules.
- */
-
-#define SOF_MAN_MOD_ID_LEN 4
-#define SOF_MAN_MOD_NAME_LEN 8
-#define SOF_MAN_MOD_SHA256_LEN 32
-#define SOF_MAN_MOD_ID {'$', 'A', 'M', 'E'}
-
-/*
- * Each module has an entry in the FW header. Used by ROM - Immutable.
- */
-struct sof_man_module {
- uint8_t struct_id[SOF_MAN_MOD_ID_LEN]; /* SOF_MAN_MOD_ID */
- uint8_t name[SOF_MAN_MOD_NAME_LEN];
- uint8_t uuid[16];
- struct sof_man_module_type type;
- uint8_t hash[SOF_MAN_MOD_SHA256_LEN];
- uint32_t entry_point;
- uint16_t cfg_offset;
- uint16_t cfg_count;
- uint32_t affinity_mask;
- uint16_t instance_max_count; /* max number of instances */
- uint16_t instance_bss_size; /* instance (pages) */
- struct sof_man_segment_desc segment[3];
-} __attribute__((packed));
-
-/*
- * Each module has a configuration in the FW header. Used by ROM - Immutable.
- */
-struct sof_man_mod_config {
- uint32_t par[4]; /* module parameters */
- uint32_t is_pages; /* actual size of instance .bss (pages) */
- uint32_t cps; /* cycles per second */
- uint32_t ibs; /* input buffer size (bytes) */
- uint32_t obs; /* output buffer size (bytes) */
- uint32_t module_flags; /* flags, reserved for future use */
- uint32_t cpc; /* cycles per single run */
- uint32_t obls; /* output block size, reserved for future use */
-} __attribute__((packed));
-
-
-/*
- * FW Manifest Header
- */
-
-#define SOF_MAN_FW_HDR_FW_NAME_LEN 8
-#define SOF_MAN_FW_HDR_ID {'$', 'A', 'M', '1'}
-#define SOF_MAN_FW_HDR_NAME "ADSPFW"
-#define SOF_MAN_FW_HDR_FLAGS 0x0
-#define SOF_MAN_FW_HDR_FEATURES 0x1f
-
-/*
- * The firmware has a standard header that is checked by the ROM on firmware
- * loading. preload_page_count is used by DMA code loader and is entire
- * image size on CNL. i.e. CNL: total size of the binary’s .text and .rodata
- * Used by ROM - Immutable.
- */
-struct sof_man_fw_header {
- uint8_t header_id[4];
- uint32_t header_len;
- uint8_t name[SOF_MAN_FW_HDR_FW_NAME_LEN];
- /* number of pages of preloaded image loaded by driver */
- uint32_t preload_page_count;
- uint32_t fw_image_flags;
- uint32_t feature_mask;
- uint16_t major_version;
- uint16_t minor_version;
- uint16_t hotfix_version;
- uint16_t build_version;
- uint32_t num_module_entries;
- uint32_t hw_buf_base_addr;
- uint32_t hw_buf_length;
- /* target address for binary loading as offset in IMR - must be == base offset */
- uint32_t load_offset;
-} __attribute__((packed));
-
-/*
- * Firmware manifest descriptor. This can contain N modules and N module
- * configs. Used by ROM - Immutable.
- */
-struct sof_man_fw_desc {
- struct sof_man_fw_header header;
-
- /* Warning - hack for module arrays. For some unknown reason the we
- * have a variable size array of struct man_module followed by a
- * variable size array of struct mod_config. These should have been
- * merged into a variable array of a parent structure. We have to hack
- * around this in many places....
- *
- * struct sof_man_module man_module[];
- * struct sof_man_mod_config mod_config[];
- */
-
-} __attribute__((packed));
-
-/*
- * Component Descriptor. Used by ROM - Immutable.
- */
-struct sof_man_component_desc {
- uint32_t reserved[2]; /* all 0 */
- uint32_t version;
- uint8_t hash[SOF_MAN_MOD_SHA256_LEN];
- uint32_t base_offset;
- uint32_t limit_offset;
- uint32_t attributes[4];
-} __attribute__((packed));
-
-
-/*
- * Audio DSP extended metadata. Used by ROM - Immutable.
- */
-struct sof_man_adsp_meta_file_ext {
- uint32_t ext_type; /* always 17 for ADSP extension */
- uint32_t ext_len;
- uint32_t imr_type;
- uint8_t reserved[16]; /* all 0 */
- struct sof_man_component_desc comp_desc[1];
-} __attribute__((packed));
-
-/*
- * Module Manifest for rimage module metadata. Not used by ROM.
- */
-struct sof_man_module_manifest {
- struct sof_man_module module;
- uint32_t text_size;
-};
-
-/**
- * \brief Utility to get module pointer from position.
- * \param [in,out] desc FW descriptor in manifest.
- * \param [in] index Index of the module.
- * \return Pointer to module descriptor.
- *
- * Note that index is not verified against OOB.
- */
-static inline struct sof_man_module *sof_man_get_module(
- struct sof_man_fw_desc *desc, int index)
-{
- return (void *)desc + sizeof(struct sof_man_fw_header) +
- index * sizeof(struct sof_man_module);
-}
-
-#endif
diff --git a/src/include/uapi/tone.h b/src/include/uapi/tone.h
deleted file mode 100644
index b04e7dc..0000000
--- a/src/include/uapi/tone.h
+++ /dev/null
@@ -1,48 +0,0 @@
-/*
- * Copyright (c) 2017, Intel Corporation
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- * * Redistributions of source code must retain the above copyright
- * notice, this list of conditions and the following disclaimer.
- * * Redistributions in binary form must reproduce the above copyright
- * notice, this list of conditions and the following disclaimer in the
- * documentation and/or other materials provided with the distribution.
- * * Neither the name of the Intel Corporation nor the
- * names of its contributors may be used to endorse or promote products
- * derived from this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
- * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
- * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
- * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
- * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
- * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
- * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
- * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
- * POSSIBILITY OF SUCH DAMAGE.
- *
- * Author: Seppo Ingalsuo <seppo.ingalsuo@linux.intel.com>
- */
-
-#ifndef TONE_H
-#define TONE_H
-
-/* Component will reject non-matching configuration. The version number need
- * to be incremented with any ABI changes in function fir_cmd().
- */
-#define SOF_TONE_ABI_VERSION 1
-
-#define SOF_TONE_IDX_FREQUENCY 0
-#define SOF_TONE_IDX_AMPLITUDE 1
-#define SOF_TONE_IDX_FREQ_MULT 2
-#define SOF_TONE_IDX_AMPL_MULT 3
-#define SOF_TONE_IDX_LENGTH 4
-#define SOF_TONE_IDX_PERIOD 5
-#define SOF_TONE_IDX_REPEATS 6
-#define SOF_TONE_IDX_LIN_RAMP_STEP 7
-
-#endif /* TONE_ABI_H */
diff --git a/src/init/Makefile.am b/src/init/Makefile.am
deleted file mode 100644
index f2fed48..0000000
--- a/src/init/Makefile.am
+++ /dev/null
@@ -1,11 +0,0 @@
-noinst_LIBRARIES = libinit.a
-
-libinit_a_SOURCES = \
- init.c
-
-libinit_a_CFLAGS = \
- $(AM_CFLAGS) \
- $(ARCH_CFLAGS) \
- $(ARCH_INCDIR) \
- $(PLATFORM_INCDIR) \
- $(SOF_INCDIR)
diff --git a/src/init/init.c b/src/init/init.c
deleted file mode 100644
index 03683df..0000000
--- a/src/init/init.c
+++ /dev/null
@@ -1,136 +0,0 @@
-/*
- * Copyright (c) 2016, Intel Corporation
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- * * Redistributions of source code must retain the above copyright
- * notice, this list of conditions and the following disclaimer.
- * * Redistributions in binary form must reproduce the above copyright
- * notice, this list of conditions and the following disclaimer in the
- * documentation and/or other materials provided with the distribution.
- * * Neither the name of the Intel Corporation nor the
- * names of its contributors may be used to endorse or promote products
- * derived from this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
- * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
- * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
- * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
- * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
- * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
- * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
- * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
- * POSSIBILITY OF SUCH DAMAGE.
- *
- * Author: Liam Girdwood <liam.r.girdwood@linux.intel.com>
- *
- * Generic DSP initialisation. This calls architecture and platform specific
- * initialisation functions.
- */
-
-#include <stddef.h>
-#include <sof/init.h>
-#include <sof/task.h>
-#include <sof/debug.h>
-#include <sof/panic.h>
-#include <sof/alloc.h>
-#include <sof/notifier.h>
-#include <sof/work.h>
-#include <sof/trace.h>
-#include <sof/schedule.h>
-#include <sof/dma-trace.h>
-#include <sof/pm_runtime.h>
-#include <sof/cpu.h>
-#include <platform/idc.h>
-#include <platform/platform.h>
-
-/* main firmware context */
-static struct sof sof;
-
-int master_core_init(struct sof *sof)
-{
- int err;
-
- /* init architecture */
- trace_point(TRACE_BOOT_ARCH);
- err = arch_init(sof);
- if (err < 0)
- panic(SOF_IPC_PANIC_ARCH);
-
- /* initialise system services */
- trace_point(TRACE_BOOT_SYS_HEAP);
- init_heap(sof);
-
- trace_init(sof);
-
- trace_point(TRACE_BOOT_SYS_NOTE);
- init_system_notify(sof);
-
- trace_point(TRACE_BOOT_SYS_SCHED);
- scheduler_init(sof);
-
- trace_point(TRACE_BOOT_SYS_POWER);
- pm_runtime_init();
-
- /* init the platform */
- err = platform_init(sof);
- if (err < 0)
- panic(SOF_IPC_PANIC_PLATFORM);
-
- trace_point(TRACE_BOOT_PLATFORM);
-
- /* should not return */
- err = do_task_master_core(sof);
-
- return err;
-}
-
-int slave_core_init(struct sof *sof)
-{
- int err;
-
- /* init architecture */
- trace_point(TRACE_BOOT_ARCH);
- err = arch_init(sof);
- if (err < 0)
- panic(SOF_IPC_PANIC_ARCH);
-
- trace_point(TRACE_BOOT_SYS_SCHED);
- scheduler_init(sof);
-
- platform_interrupt_init();
-
- /* initialize IDC mechanism */
- trace_point(TRACE_BOOT_PLATFORM_IDC);
- idc_init();
-
- trace_point(TRACE_BOOT_PLATFORM);
-
- /* should not return */
- err = do_task_slave_core(sof);
-
- return err;
-}
-
-int main(int argc, char *argv[])
-{
- int err;
-
- trace_point(TRACE_BOOT_START);
-
- /* setup context */
- sof.argc = argc;
- sof.argv = argv;
-
- if (cpu_get_id() == PLATFORM_MASTER_CORE_ID)
- err = master_core_init(&sof);
- else
- err = slave_core_init(&sof);
-
- /* should never get here */
- panic(SOF_IPC_PANIC_TASK);
- return err;
-}
diff --git a/src/ipc/Makefile.am b/src/ipc/Makefile.am
deleted file mode 100644
index 69d7ea1..0000000
--- a/src/ipc/Makefile.am
+++ /dev/null
@@ -1,76 +0,0 @@
-if BUILD_LIB
-lib_LTLIBRARIES = libsof_ipc.la
-
-libsof_ipc_la_SOURCES = \
- ipc.c
-
-libsof_ipc_la_LDFLAGS = \
- $(AM_LDFLAGS) \
- -version-info `echo $(VERSION) | cut -d '.' -f 1 | cut -d '0' -f 2` \
- -no-undefined \
- -export-dynamic
-
-libsof_ipc_la_CFLAGS = \
- $(AM_CFLAGS) \
- $(ARCH_CFLAGS) \
- $(COMMON_INCDIR)
-else
-noinst_LIBRARIES = libsof_ipc.a
-
-if BUILD_BAYTRAIL
-libsof_ipc_a_SOURCES = \
- ipc.c \
- handler.c \
- byt-ipc.c \
- pmc-ipc.c \
- dma-copy.c
-endif
-
-if BUILD_CHERRYTRAIL
-libsof_ipc_a_SOURCES = \
- ipc.c \
- handler.c \
- byt-ipc.c \
- pmc-ipc.c \
- dma-copy.c
-endif
-
-if BUILD_BROADWELL
-libsof_ipc_a_SOURCES = \
- ipc.c \
- handler.c \
- hsw-ipc.c \
- dma-copy.c
-endif
-
-if BUILD_HASWELL
-libsof_ipc_a_SOURCES = \
- ipc.c \
- handler.c \
- hsw-ipc.c \
- dma-copy.c
-endif
-
-
-if BUILD_APOLLOLAKE
-libsof_ipc_a_SOURCES = \
- ipc.c \
- handler.c \
- apl-ipc.c \
- dma-copy.c
-endif
-
-if BUILD_CANNONLAKE
-libsof_ipc_a_SOURCES = \
- ipc.c \
- handler.c \
- cnl-ipc.c \
- dma-copy.c
-endif
-
-libsof_ipc_a_CFLAGS = \
- $(AM_CFLAGS) \
- $(ARCH_CFLAGS) \
- $(COMMON_INCDIR)
-endif
-
diff --git a/src/ipc/apl-ipc.c b/src/ipc/apl-ipc.c
deleted file mode 100644
index 814ece8..0000000
--- a/src/ipc/apl-ipc.c
+++ /dev/null
@@ -1,220 +0,0 @@
-/*
- * Copyright (c) 2016, Intel Corporation
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- * * Redistributions of source code must retain the above copyright
- * notice, this list of conditions and the following disclaimer.
- * * Redistributions in binary form must reproduce the above copyright
- * notice, this list of conditions and the following disclaimer in the
- * documentation and/or other materials provided with the distribution.
- * * Neither the name of the Intel Corporation nor the
- * names of its contributors may be used to endorse or promote products
- * derived from this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
- * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
- * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
- * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
- * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
- * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
- * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
- * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
- * POSSIBILITY OF SUCH DAMAGE.
- *
- * Author: Liam Girdwood <liam.r.girdwood@linux.intel.com>
- * Keyon Jie <yang.jie@linux.intel.com>
- */
-
-#include <sof/debug.h>
-#include <sof/timer.h>
-#include <sof/interrupt.h>
-#include <sof/ipc.h>
-#include <sof/mailbox.h>
-#include <sof/sof.h>
-#include <sof/stream.h>
-#include <sof/dai.h>
-#include <sof/dma.h>
-#include <sof/alloc.h>
-#include <sof/wait.h>
-#include <sof/trace.h>
-#include <sof/ssp.h>
-#include <platform/interrupt.h>
-#include <platform/mailbox.h>
-#include <platform/shim.h>
-#include <platform/dma.h>
-#include <platform/platform.h>
-#include <sof/audio/component.h>
-#include <sof/audio/pipeline.h>
-#include <uapi/ipc.h>
-#include <sof/intel-ipc.h>
-#include <platform/pm_runtime.h>
-
-extern struct ipc *_ipc;
-
-/* test code to check working IRQ */
-static void irq_handler(void *arg)
-{
- uint32_t dipct;
- uint32_t dipcie;
- uint32_t msg = 0;
-
- tracev_ipc("IRQ");
-
- dipct = ipc_read(IPC_DIPCT);
- dipcie = ipc_read(IPC_DIPCIE);
-
- /* new message from host */
- if (dipct & IPC_DIPCT_BUSY) {
- tracev_ipc("Nms");
-
- /* mask Busy interrupt */
- ipc_write(IPC_DIPCCTL, ipc_read(IPC_DIPCCTL) & ~IPC_DIPCCTL_IPCTBIE);
-
- msg = dipct & IPC_DIPCT_MSG_MASK;
-
- /* TODO: place message in Q and process later */
- /* It's not Q ATM, may overwrite */
- if (_ipc->host_pending)
- trace_ipc_error("Pen");
- _ipc->host_msg = msg;
- _ipc->host_pending = 1;
-
- }
-
- /* reply message(done) from host */
- if (dipcie & IPC_DIPCIE_DONE) {
- tracev_ipc("Rpy");
- /* mask Done interrupt */
- ipc_write(IPC_DIPCCTL, ipc_read(IPC_DIPCCTL) & ~IPC_DIPCCTL_IPCIDIE);
-
- /* clear DONE bit - tell host we have completed the operation */
- ipc_write(IPC_DIPCIE, ipc_read(IPC_DIPCIE) |IPC_DIPCIE_DONE);
-
- /* unmask Done interrupt */
- ipc_write(IPC_DIPCCTL, ipc_read(IPC_DIPCCTL) | IPC_DIPCCTL_IPCIDIE);
- }
-
-}
-
-void ipc_platform_do_cmd(struct ipc *ipc)
-{
- struct intel_ipc_data *iipc = ipc_get_drvdata(ipc);
- struct sof_ipc_reply reply;
- int32_t err;
-
- trace_ipc("Cmd");
-
- /* perform command and return any error */
- err = ipc_cmd();
- if (err > 0) {
- goto done; /* reply created and copied by cmd() */
- } else if (err < 0) {
- /* send std error reply */
- reply.error = err;
- } else if (err == 0) {
- /* send std reply */
- reply.error = 0;
- }
-
- /* send std error/ok reply */
- reply.hdr.cmd = SOF_IPC_GLB_REPLY;
- reply.hdr.size = sizeof(reply);
- mailbox_hostbox_write(0, &reply, sizeof(reply));
-
-done:
- ipc->host_pending = 0;
-
- /* write 1 to clear busy, and trigger interrupt to host*/
- ipc_write(IPC_DIPCT, ipc_read(IPC_DIPCT) |IPC_DIPCT_BUSY );
-
- /* unmask Busy interrupt */
- ipc_write(IPC_DIPCCTL, ipc_read(IPC_DIPCCTL) | IPC_DIPCCTL_IPCTBIE);
-
- // TODO: signal audio work to enter D3 in normal context
- /* are we about to enter D3 ? */
- if (iipc->pm_prepare_D3) {
- /* no return - memory will be powered off */
- platform_pm_runtime_power_off();
- }
-
- tracev_ipc("CmD");
-
-}
-
-void ipc_platform_send_msg(struct ipc *ipc)
-{
- struct ipc_msg *msg;
- uint32_t flags;
-
- spin_lock_irq(&ipc->lock, flags);
-
- /* any messages to send ? */
- if (list_is_empty(&ipc->msg_list)) {
- ipc->dsp_pending = 0;
- goto out;
- }
-
- /* now send the message */
- msg = list_first_item(&ipc->msg_list, struct ipc_msg, list);
- mailbox_dspbox_write(0, msg->tx_data, msg->tx_size);
- list_item_del(&msg->list);
- ipc->dsp_msg = msg;
- tracev_ipc("Msg");
-
- /* now interrupt host to tell it we have message sent */
- ipc_write(IPC_DIPCIE, 0);
- ipc_write(IPC_DIPCI, 0x80000000 | msg->header);
-
- list_item_append(&msg->list, &ipc->empty_list);
-
-out:
- spin_unlock_irq(&ipc->lock, flags);
-}
-
-int platform_ipc_init(struct ipc *ipc)
-{
- struct intel_ipc_data *iipc;
- uint32_t dir, caps, dev;
- int i;
-
- _ipc = ipc;
-
- /* init ipc data */
- iipc = rzalloc(RZONE_SYS, SOF_MEM_CAPS_RAM,
- sizeof(struct intel_ipc_data));
- ipc_set_drvdata(_ipc, iipc);
- _ipc->dsp_msg = NULL;
- list_init(&ipc->empty_list);
- list_init(&ipc->msg_list);
- spinlock_init(&ipc->lock);
- for (i = 0; i < MSG_QUEUE_SIZE; i++)
- list_item_prepend(&ipc->message[i].list, &ipc->empty_list);
-
- /* allocate page table buffer */
- iipc->page_table = rballoc(RZONE_SYS, SOF_MEM_CAPS_RAM,
- HOST_PAGE_SIZE);
- if (iipc->page_table)
- bzero(iipc->page_table, HOST_PAGE_SIZE);
-
- /* request HDA DMA with shared access privilege */
- caps = 0;
- dir = DMA_DIR_HMEM_TO_LMEM;
- dev = DMA_DEV_HOST;
- iipc->dmac = dma_get(dir, caps, dev, DMA_ACCESS_SHARED);
-
- /* PM */
- iipc->pm_prepare_D3 = 0;
-
- /* configure interrupt */
- interrupt_register(PLATFORM_IPC_INTERUPT, irq_handler, NULL);
- interrupt_enable(PLATFORM_IPC_INTERUPT);
-
- /* enable IPC interrupts from host */
- ipc_write(IPC_DIPCCTL, IPC_DIPCCTL_IPCIDIE | IPC_DIPCCTL_IPCTBIE);
-
- return 0;
-}
diff --git a/src/ipc/byt-ipc.c b/src/ipc/byt-ipc.c
deleted file mode 100644
index dccf1c4..0000000
--- a/src/ipc/byt-ipc.c
+++ /dev/null
@@ -1,248 +0,0 @@
-/*
- * Copyright (c) 2016, Intel Corporation
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- * * Redistributions of source code must retain the above copyright
- * notice, this list of conditions and the following disclaimer.
- * * Redistributions in binary form must reproduce the above copyright
- * notice, this list of conditions and the following disclaimer in the
- * documentation and/or other materials provided with the distribution.
- * * Neither the name of the Intel Corporation nor the
- * names of its contributors may be used to endorse or promote products
- * derived from this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
- * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
- * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
- * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
- * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
- * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
- * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
- * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
- * POSSIBILITY OF SUCH DAMAGE.
- *
- * Author: Liam Girdwood <liam.r.girdwood@linux.intel.com>
- * Keyon Jie <yang.jie@linux.intel.com>
- */
-
-#include <sof/debug.h>
-#include <sof/timer.h>
-#include <sof/interrupt.h>
-#include <sof/ipc.h>
-#include <sof/mailbox.h>
-#include <sof/sof.h>
-#include <sof/stream.h>
-#include <sof/dai.h>
-#include <sof/dma.h>
-#include <sof/alloc.h>
-#include <sof/wait.h>
-#include <sof/trace.h>
-#include <sof/ssp.h>
-#include <platform/interrupt.h>
-#include <platform/mailbox.h>
-#include <platform/shim.h>
-#include <platform/dma.h>
-#include <platform/platform.h>
-#include <sof/audio/component.h>
-#include <sof/audio/pipeline.h>
-#include <uapi/ipc.h>
-#include <sof/intel-ipc.h>
-
-extern struct ipc *_ipc;
-
-static void do_notify(void)
-{
- uint32_t flags;
- struct ipc_msg *msg;
-
- tracev_ipc("Not");
-
- spin_lock_irq(&_ipc->lock, flags);
- msg = _ipc->dsp_msg;
- if (msg == NULL)
- goto out;
-
- /* copy the data returned from DSP */
- if (msg->rx_size && msg->rx_size < SOF_IPC_MSG_MAX_SIZE)
- mailbox_dspbox_read(msg->rx_data, 0, msg->rx_size);
-
- /* any callback ? */
- if (msg->cb)
- msg->cb(msg->cb_data, msg->rx_data);
-
- list_item_append(&msg->list, &_ipc->empty_list);
-
-out:
- spin_unlock_irq(&_ipc->lock, flags);
-
- /* clear DONE bit - tell Host we have completed */
- shim_write(SHIM_IPCDH, shim_read(SHIM_IPCDH) & ~SHIM_IPCDH_DONE);
-
- /* unmask Done interrupt */
- shim_write(SHIM_IMRD, shim_read(SHIM_IMRD) & ~SHIM_IMRD_DONE);
-}
-
-static void irq_handler(void *arg)
-{
- uint32_t isr;
-
- tracev_ipc("IRQ");
-
- /* Interrupt arrived, check src */
- isr = shim_read(SHIM_ISRD);
-
- if (isr & SHIM_ISRD_DONE) {
-
- /* Mask Done interrupt before return */
- shim_write(SHIM_IMRD, shim_read(SHIM_IMRD) | SHIM_IMRD_DONE);
- interrupt_clear(PLATFORM_IPC_INTERUPT);
- do_notify();
- }
-
- if (isr & SHIM_ISRD_BUSY) {
-
- /* Mask Busy interrupt before return */
- shim_write(SHIM_IMRD, shim_read(SHIM_IMRD) | SHIM_IMRD_BUSY);
- interrupt_clear(PLATFORM_IPC_INTERUPT);
-
- /* TODO: place message in Q and process later */
- /* It's not Q ATM, may overwrite */
- if (_ipc->host_pending)
- trace_ipc_error("Pen");
- _ipc->host_msg = shim_read(SHIM_IPCXL);
- _ipc->host_pending = 1;
- }
-}
-
-void ipc_platform_do_cmd(struct ipc *ipc)
-{
- struct intel_ipc_data *iipc = ipc_get_drvdata(ipc);
- struct sof_ipc_reply reply;
- uint32_t ipcxh;
- int32_t err;
-
- tracev_ipc("Cmd");
-
- /* perform command and return any error */
- err = ipc_cmd();
- if (err > 0) {
- goto done; /* reply created and copied by cmd() */
- } else {
- /* send std error reply */
- reply.error = err;
- }
-
- /* send std error/ok reply */
- reply.hdr.cmd = SOF_IPC_GLB_REPLY;
- reply.hdr.size = sizeof(reply);
- mailbox_hostbox_write(0, &reply, sizeof(reply));
-
-done:
- ipc->host_pending = 0;
-
- /* clear BUSY bit and set DONE bit - accept new messages */
- ipcxh = shim_read(SHIM_IPCXH);
- ipcxh &= ~SHIM_IPCXH_BUSY;
- ipcxh |= SHIM_IPCXH_DONE;
- shim_write(SHIM_IPCXH, ipcxh);
-
- /* unmask busy interrupt */
- shim_write(SHIM_IMRD, shim_read(SHIM_IMRD) & ~SHIM_IMRD_BUSY);
-
- // TODO: signal audio work to enter D3 in normal context
- /* are we about to enter D3 ? */
- if (iipc->pm_prepare_D3) {
- while (1) {
- trace_ipc("pme");
- wait_for_interrupt(0);
- }
- }
-
- tracev_ipc("CmD");
-}
-
-void ipc_platform_send_msg(struct ipc *ipc)
-{
- struct ipc_msg *msg;
- uint32_t flags;
-
- spin_lock_irq(&ipc->lock, flags);
-
- /* any messages to send ? */
- if (list_is_empty(&ipc->msg_list)) {
- ipc->dsp_pending = 0;
- goto out;
- }
-
- /* can't send notification when one is in progress */
- if (shim_read(SHIM_IPCDH) & (SHIM_IPCDH_BUSY | SHIM_IPCDH_DONE))
- goto out;
-
- /* now send the message */
- msg = list_first_item(&ipc->msg_list, struct ipc_msg, list);
- mailbox_dspbox_write(0, msg->tx_data, msg->tx_size);
- list_item_del(&msg->list);
- ipc->dsp_msg = msg;
- tracev_ipc("Msg");
-
- /* now interrupt host to tell it we have message sent */
- shim_write(SHIM_IPCDL, msg->header);
- shim_write(SHIM_IPCDH, SHIM_IPCDH_BUSY);
-
- list_item_append(&msg->list, &ipc->empty_list);
-
-out:
- spin_unlock_irq(&ipc->lock, flags);
-}
-
-int platform_ipc_init(struct ipc *ipc)
-{
- struct intel_ipc_data *iipc;
- uint32_t imrd, dir, caps, dev;
- int i;
-
- _ipc = ipc;
-
- /* init ipc data */
- iipc = rzalloc(RZONE_SYS, SOF_MEM_CAPS_RAM,
- sizeof(struct intel_ipc_data));
- ipc_set_drvdata(_ipc, iipc);
- _ipc->dsp_msg = NULL;
- list_init(&ipc->empty_list);
- list_init(&ipc->msg_list);
- spinlock_init(&ipc->lock);
-
- for (i = 0; i < MSG_QUEUE_SIZE; i++)
- list_item_prepend(&ipc->message[i].list, &ipc->empty_list);
-
- /* allocate page table buffer */
- iipc->page_table = rzalloc(RZONE_SYS, SOF_MEM_CAPS_RAM,
- PLATFORM_PAGE_TABLE_SIZE);
- if (iipc->page_table)
- bzero(iipc->page_table, PLATFORM_PAGE_TABLE_SIZE);
-
- /* request HDA DMA with shared access privilege */
- caps = 0;
- dir = DMA_DIR_HMEM_TO_LMEM;
- dev = DMA_DEV_HOST;
- iipc->dmac = dma_get(dir, caps, dev, DMA_ACCESS_SHARED);
-
- /* PM */
- iipc->pm_prepare_D3 = 0;
-
- /* configure interrupt */
- interrupt_register(PLATFORM_IPC_INTERUPT, irq_handler, NULL);
- interrupt_enable(PLATFORM_IPC_INTERUPT);
-
- /* Unmask Busy and Done interrupts */
- imrd = shim_read(SHIM_IMRD);
- imrd &= ~(SHIM_IMRD_BUSY | SHIM_IMRD_DONE);
- shim_write(SHIM_IMRD, imrd);
-
- return 0;
-}
-
diff --git a/src/ipc/cnl-ipc.c b/src/ipc/cnl-ipc.c
deleted file mode 100644
index 71cd5de..0000000
--- a/src/ipc/cnl-ipc.c
+++ /dev/null
@@ -1,219 +0,0 @@
-/*
- * Copyright (c) 2017, Intel Corporation
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- * * Redistributions of source code must retain the above copyright
- * notice, this list of conditions and the following disclaimer.
- * * Redistributions in binary form must reproduce the above copyright
- * notice, this list of conditions and the following disclaimer in the
- * documentation and/or other materials provided with the distribution.
- * * Neither the name of the Intel Corporation nor the
- * names of its contributors may be used to endorse or promote products
- * derived from this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
- * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
- * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
- * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
- * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
- * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
- * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
- * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
- * POSSIBILITY OF SUCH DAMAGE.
- *
- * Author: Liam Girdwood <liam.r.girdwood@linux.intel.com>
- * Keyon Jie <yang.jie@linux.intel.com>
- Rander Wang <rander.wang@intel.com>
- */
-
-#include <sof/debug.h>
-#include <sof/timer.h>
-#include <sof/interrupt.h>
-#include <sof/ipc.h>
-#include <sof/mailbox.h>
-#include <sof/sof.h>
-#include <sof/stream.h>
-#include <sof/dai.h>
-#include <sof/dma.h>
-#include <sof/alloc.h>
-#include <sof/wait.h>
-#include <sof/trace.h>
-#include <sof/ssp.h>
-#include <platform/interrupt.h>
-#include <platform/mailbox.h>
-#include <platform/shim.h>
-#include <platform/dma.h>
-#include <platform/platform.h>
-#include <sof/audio/component.h>
-#include <sof/audio/pipeline.h>
-#include <uapi/ipc.h>
-#include <sof/intel-ipc.h>
-
-extern struct ipc *_ipc;
-
-/* test code to check working IRQ */
-static void irq_handler(void *arg)
-{
- uint32_t dipctdr;
- uint32_t dipcida;
- uint32_t msg = 0;
-
- tracev_ipc("IRQ");
-
- dipctdr = ipc_read(IPC_DIPCTDR);
- dipcida = ipc_read(IPC_DIPCIDA);
-
- /* new message from host */
- if (dipctdr & IPC_DIPCTDR_BUSY) {
- tracev_ipc("Nms");
-
- /* mask Busy interrupt */
- ipc_write(IPC_DIPCCTL, ipc_read(IPC_DIPCCTL) & ~IPC_DIPCCTL_IPCTBIE);
-
- msg = dipctdr & IPC_DIPCTDR_MSG_MASK;
-
- /* TODO: place message in Q and process later */
- /* It's not Q ATM, may overwrite */
- if (_ipc->host_pending)
- trace_ipc_error("Pen");
- _ipc->host_msg = msg;
- _ipc->host_pending = 1;
- }
-
- /* reply message(done) from host */
- if (dipcida & IPC_DIPCIDA_DONE) {
- tracev_ipc("Rpy");
- /* mask Done interrupt */
- ipc_write(IPC_DIPCCTL, ipc_read(IPC_DIPCCTL) & ~IPC_DIPCCTL_IPCIDIE);
-
- /* clear DONE bit - tell host we have completed the operation */
- ipc_write(IPC_DIPCIDA, ipc_read(IPC_DIPCIDA) |IPC_DIPCIDA_DONE);
-
- /* unmask Done interrupt */
- ipc_write(IPC_DIPCCTL, ipc_read(IPC_DIPCCTL) | IPC_DIPCCTL_IPCIDIE);
- }
-
-}
-
-void ipc_platform_do_cmd(struct ipc *ipc)
-{
- struct intel_ipc_data *iipc = ipc_get_drvdata(ipc);
- struct sof_ipc_reply reply;
- int32_t err;
-
- trace_ipc("Cmd");
-
- /* perform command and return any error */
- err = ipc_cmd();
- if (err > 0) {
- goto done; /* reply created and copied by cmd() */
- } else if (err < 0) {
- /* send std error reply */
- reply.error = err;
- } else if (err == 0) {
- /* send std reply */
- reply.error = 0;
- }
-
- /* send std error/ok reply */
- reply.hdr.cmd = SOF_IPC_GLB_REPLY;
- reply.hdr.size = sizeof(reply);
- mailbox_hostbox_write(0, &reply, sizeof(reply));
-
-done:
- ipc->host_pending = 0;
-
- /* write 1 to clear busy, and trigger interrupt to host*/
- ipc_write(IPC_DIPCTDR, ipc_read(IPC_DIPCTDR) |IPC_DIPCTDR_BUSY);
- ipc_write(IPC_DIPCTDA, ipc_read(IPC_DIPCTDA) |IPC_DIPCTDA_BUSY );
-
- /* unmask Busy interrupt */
- ipc_write(IPC_DIPCCTL, ipc_read(IPC_DIPCCTL) | IPC_DIPCCTL_IPCTBIE);
-
- // TODO: signal audio work to enter D3 in normal context
- /* are we about to enter D3 ? */
- if (iipc->pm_prepare_D3) {
- while (1)
- wait_for_interrupt(0);
- }
-
- tracev_ipc("CmD");
-}
-
-void ipc_platform_send_msg(struct ipc *ipc)
-{
- struct ipc_msg *msg;
- uint32_t flags;
-
- spin_lock_irq(&ipc->lock, flags);
-
- /* any messages to send ? */
- if (list_is_empty(&ipc->msg_list)) {
- ipc->dsp_pending = 0;
- goto out;
- }
-
- /* now send the message */
- msg = list_first_item(&ipc->msg_list, struct ipc_msg, list);
- mailbox_dspbox_write(0, msg->tx_data, msg->tx_size);
- list_item_del(&msg->list);
- ipc->dsp_msg = msg;
- tracev_ipc("Msg");
-
- /* now interrupt host to tell it we have message sent */
- ipc_write(IPC_DIPCIDD, 0);
- ipc_write(IPC_DIPCIDR, 0x80000000 | msg->header);
-
- list_item_append(&msg->list, &ipc->empty_list);
-
-out:
- spin_unlock_irq(&ipc->lock, flags);
-}
-
-int platform_ipc_init(struct ipc *ipc)
-{
- struct intel_ipc_data *iipc;
- uint32_t dir, caps, dev;
- int i;
-
- _ipc = ipc;
-
- /* init ipc data */
- iipc = rzalloc(RZONE_SYS, SOF_MEM_CAPS_RAM,
- sizeof(struct intel_ipc_data));
- ipc_set_drvdata(_ipc, iipc);
- _ipc->dsp_msg = NULL;
- list_init(&ipc->empty_list);
- list_init(&ipc->msg_list);
- spinlock_init(&ipc->lock);
- for (i = 0; i < MSG_QUEUE_SIZE; i++)
- list_item_prepend(&ipc->message[i].list, &ipc->empty_list);
-
- /* allocate page table buffer */
- iipc->page_table = rballoc(RZONE_SYS, SOF_MEM_CAPS_RAM,
- HOST_PAGE_SIZE);
- if (iipc->page_table)
- bzero(iipc->page_table, HOST_PAGE_SIZE);
-
- /* request HDA DMA with shared access privilege */
- caps = 0;
- dir = DMA_DIR_HMEM_TO_LMEM;
- dev = DMA_DEV_HOST;
- iipc->dmac = dma_get(dir, caps, dev, DMA_ACCESS_SHARED);
-
- /* PM */
- iipc->pm_prepare_D3 = 0;
-
- /* configure interrupt */
- interrupt_register(PLATFORM_IPC_INTERUPT, irq_handler, NULL);
- interrupt_enable(PLATFORM_IPC_INTERUPT);
-
- /* enable IPC interrupts from host */
- ipc_write(IPC_DIPCCTL, IPC_DIPCCTL_IPCIDIE | IPC_DIPCCTL_IPCTBIE);
-
- return 0;
-}
diff --git a/src/ipc/dma-copy.c b/src/ipc/dma-copy.c
deleted file mode 100644
index c7e18b0..0000000
--- a/src/ipc/dma-copy.c
+++ /dev/null
@@ -1,420 +0,0 @@
-/*
- * Copyright (c) 2016, Intel Corporation
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- * * Redistributions of source code must retain the above copyright
- * notice, this list of conditions and the following disclaimer.
- * * Redistributions in binary form must reproduce the above copyright
- * notice, this list of conditions and the following disclaimer in the
- * documentation and/or other materials provided with the distribution.
- * * Neither the name of the Intel Corporation nor the
- * names of its contributors may be used to endorse or promote products
- * derived from this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
- * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
- * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
- * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
- * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
- * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
- * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
- * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
- * POSSIBILITY OF SUCH DAMAGE.
- *
- * Author: Liam Girdwood <liam.r.girdwood@linux.intel.com>
- * Keyon Jie <yang.jie@linux.intel.com>
- */
-
-#include <stdint.h>
-#include <uapi/ipc.h>
-#include <sof/sof.h>
-#include <sof/debug.h>
-#include <sof/trace.h>
-#include <sof/ipc.h>
-#include <sof/dma.h>
-#include <sof/wait.h>
-#include <platform/dma.h>
-
-/* tracing */
-#define trace_dma(__e) trace_event(TRACE_CLASS_DMA, __e)
-#define trace_dma_error(__e) trace_error(TRACE_CLASS_DMA, __e)
-#define tracev_dma(__e) tracev_event(TRACE_CLASS_DMA, __e)
-
-static struct dma_sg_elem *sg_get_elem_at(struct dma_sg_config *host_sg,
- int32_t *offset)
-{
- struct dma_sg_elem *host_sg_elem;
- struct list_item *plist;
- int32_t _offset = *offset;
-
- /* find host element with host_offset */
- list_for_item(plist, &host_sg->elem_list) {
-
- host_sg_elem = container_of(plist, struct dma_sg_elem, list);
-
- /* is offset in this elem ? */
- if (_offset >= 0 && _offset < host_sg_elem->size) {
- *offset = _offset;
- return host_sg_elem;
- }
-
- _offset -= host_sg_elem->size;
- }
-
- /* host offset in beyond end of SG buffer */
- trace_dma_error("ex0");
- return NULL;
-}
-
-#if !defined CONFIG_DMA_GW
-
-static void dma_complete(void *data, uint32_t type, struct dma_sg_elem *next)
-{
- completion_t *comp = (completion_t *)data;
-
- if (type == DMA_IRQ_TYPE_LLIST)
- wait_completed(comp);
-
- ipc_dma_trace_send_position();
-
- next->size = DMA_RELOAD_END;
-}
-
-#endif
-
-/* Copy DSP memory to host memory.
- * copies DSP memory to host in PAGE_SIZE or smaller blocks and waits/sleeps
- * between blocks. Can't be used in IRQ context.
- */
-int dma_copy_to_host(struct dma_copy *dc, struct dma_sg_config *host_sg,
- int32_t host_offset, void *local_ptr, int32_t size)
-{
- struct dma_sg_config config;
- struct dma_sg_elem *host_sg_elem;
- struct dma_sg_elem local_sg_elem;
- int32_t err;
- int32_t offset = host_offset;
- int32_t bytes_copied = 0;
-
- if (size <= 0)
- return 0;
-
- /* find host element with host_offset */
- host_sg_elem = sg_get_elem_at(host_sg, &offset);
- if (host_sg_elem == NULL)
- return -EINVAL;
-
- /* set up DMA configuration */
- config.direction = DMA_DIR_LMEM_TO_HMEM;
- config.src_width = sizeof(uint32_t);
- config.dest_width = sizeof(uint32_t);
- config.cyclic = 0;
- list_init(&config.elem_list);
-
- /* configure local DMA elem */
- local_sg_elem.dest = host_sg_elem->dest + offset;
- local_sg_elem.src = (uint32_t)local_ptr;
- if (size >= HOST_PAGE_SIZE - offset)
- local_sg_elem.size = HOST_PAGE_SIZE - offset;
- else
- local_sg_elem.size = size;
-
- list_item_prepend(&local_sg_elem.list, &config.elem_list);
-
- /* transfer max PAGE size at a time to SG buffer */
- while (size > 0) {
-
- /* start the DMA */
- wait_init(&dc->complete);
- err = dma_set_config(dc->dmac, dc->chan, &config);
- if (err < 0)
- return err;
-
- err = dma_start(dc->dmac, dc->chan);
- if (err < 0)
- return err;
-
- /* wait for DMA to complete */
- err = wait_for_completion_timeout(&dc->complete);
- if (err < 0) {
- trace_dma_error("ex1");
- return -EIO;
- }
-
- /* update offset and bytes remaining */
- size -= local_sg_elem.size;
- host_offset += local_sg_elem.size;
-
- /* next dest host address is in next host elem */
-
- host_sg_elem = list_next_item(host_sg_elem, list);
- local_sg_elem.dest = host_sg_elem->dest;
-
- /* local address is continuous */
- local_sg_elem.src = (uint32_t)local_ptr + local_sg_elem.size;
-
- bytes_copied += local_sg_elem.size;
-
- /* do we have less than 1 PAGE to copy ? */
- if (size >= HOST_PAGE_SIZE)
- local_sg_elem.size = HOST_PAGE_SIZE;
- else
- local_sg_elem.size = size;
- }
-
- /* bytes copied */
- return bytes_copied;
-}
-
-/* Copy DSP memory to host memory.
- * Copies DSP memory to host in a single PAGE_SIZE or smaller block. Does not
- * waits/sleeps and can be used in IRQ context.
- */
-#if defined CONFIG_DMA_GW
-
-int dma_copy_to_host_nowait(struct dma_copy *dc, struct dma_sg_config *host_sg,
- int32_t host_offset, void *local_ptr, int32_t size)
-{
- int ret;
-
- /* tell gateway to copy */
- ret = dma_copy(dc->dmac, dc->chan, size, 0);
- if (ret < 0)
- return ret;
-
- /* bytes copied */
- return size;
-}
-
-#else
-
-int dma_copy_to_host_nowait(struct dma_copy *dc, struct dma_sg_config *host_sg,
- int32_t host_offset, void *local_ptr, int32_t size)
-{
- struct dma_sg_config config;
- struct dma_sg_elem *host_sg_elem;
- struct dma_sg_elem local_sg_elem;
- int32_t err;
- int32_t offset = host_offset;
-
- if (size <= 0)
- return 0;
-
- /* find host element with host_offset */
- host_sg_elem = sg_get_elem_at(host_sg, &offset);
- if (host_sg_elem == NULL)
- return -EINVAL;
-
- /* set up DMA configuration */
- config.direction = DMA_DIR_LMEM_TO_HMEM;
- config.src_width = sizeof(uint32_t);
- config.dest_width = sizeof(uint32_t);
- config.cyclic = 0;
- list_init(&config.elem_list);
-
- /* configure local DMA elem */
- local_sg_elem.dest = host_sg_elem->dest + offset;
- local_sg_elem.src = (uint32_t)local_ptr;
- if (size >= HOST_PAGE_SIZE - offset)
- local_sg_elem.size = HOST_PAGE_SIZE - offset;
- else
- local_sg_elem.size = size;
-
- list_item_prepend(&local_sg_elem.list, &config.elem_list);
-
- /* start the DMA */
- err = dma_set_config(dc->dmac, dc->chan, &config);
- if (err < 0)
- return err;
-
- err = dma_start(dc->dmac, dc->chan);
- if (err < 0)
- return err;
-
- /* bytes copied */
- return local_sg_elem.size;
-}
-
-#endif
-
-/* Copy host memory to DSP memory.
- * Copies host memory to host in PAGE_SIZE or smaller blocks and waits/sleeps
- * between blocks. Cant be used in IRQ context.
- */
-int dma_copy_from_host(struct dma_copy *dc, struct dma_sg_config *host_sg,
- int32_t host_offset, void *local_ptr, int32_t size)
-{
- struct dma_sg_config config;
- struct dma_sg_elem *host_sg_elem;
- struct dma_sg_elem local_sg_elem;
- int32_t err;
- int32_t offset = host_offset;
- int32_t bytes_copied = 0;
-
- if (size <= 0)
- return 0;
-
- /* find host element with host_offset */
- host_sg_elem = sg_get_elem_at(host_sg, &offset);
- if (host_sg_elem == NULL)
- return -EINVAL;
-
- /* set up DMA configuration */
- config.direction = DMA_DIR_HMEM_TO_LMEM;
- config.src_width = sizeof(uint32_t);
- config.dest_width = sizeof(uint32_t);
- config.cyclic = 0;
- list_init(&config.elem_list);
-
- /* configure local DMA elem */
- local_sg_elem.dest = (uint32_t)local_ptr;
- local_sg_elem.src = host_sg_elem->src + offset;
- if (size >= HOST_PAGE_SIZE - offset)
- local_sg_elem.size = HOST_PAGE_SIZE - offset;
- else
- local_sg_elem.size = size;
- list_item_prepend(&local_sg_elem.list, &config.elem_list);
-
- /* transfer max PAGE size at a time to SG buffer */
- while (size > 0) {
-
- /* start the DMA */
- wait_init(&dc->complete);
- err = dma_set_config(dc->dmac, dc->chan, &config);
- if (err < 0)
- return err;
-
- err = dma_start(dc->dmac, dc->chan);
- if (err < 0)
- return err;
-
- /* wait for DMA to complete */
- err = wait_for_completion_timeout(&dc->complete);
- if (err < 0) {
- trace_dma_error("ex2");
- return -EIO;
- }
-
- /* update offset and bytes remaining */
- size -= local_sg_elem.size;
- host_offset += local_sg_elem.size;
-
- /* next dest host address is in next host elem */
- host_sg_elem = list_next_item(host_sg_elem, list);
- local_sg_elem.src = host_sg_elem->src;
-
- /* local address is continuous */
- local_sg_elem.dest = (uint32_t)local_ptr + local_sg_elem.size;
-
- bytes_copied += local_sg_elem.size;
-
- /* do we have less than 1 PAGE to copy ? */
- if (size >= HOST_PAGE_SIZE)
- local_sg_elem.size = HOST_PAGE_SIZE;
- else
- local_sg_elem.size = size;
- }
-
- /* bytes copied */
- return bytes_copied;
-}
-
-/* Copy host memory to DSP memory.
- * Copies host memory to DSP in a single PAGE_SIZE or smaller block. Does not
- * waits/sleeps and can be used in IRQ context.
- */
-int dma_copy_from_host_nowait(struct dma_copy *dc, struct dma_sg_config *host_sg,
- int32_t host_offset, void *local_ptr, int32_t size)
-{
- struct dma_sg_config config;
- struct dma_sg_elem *host_sg_elem;
- struct dma_sg_elem local_sg_elem;
- int32_t err;
- int32_t offset = host_offset;
-
- if (size <= 0)
- return 0;
-
- /* find host element with host_offset */
- host_sg_elem = sg_get_elem_at(host_sg, &offset);
- if (host_sg_elem == NULL)
- return -EINVAL;
-
- /* set up DMA configuration */
- config.direction = DMA_DIR_HMEM_TO_LMEM;
- config.src_width = sizeof(uint32_t);
- config.dest_width = sizeof(uint32_t);
- config.cyclic = 0;
- list_init(&config.elem_list);
-
- /* configure local DMA elem */
- local_sg_elem.dest = (uint32_t)local_ptr;
- local_sg_elem.src = host_sg_elem->src + offset;
- if (size >= HOST_PAGE_SIZE - offset)
- local_sg_elem.size = HOST_PAGE_SIZE - offset;
- else
- local_sg_elem.size = size;
- list_item_prepend(&local_sg_elem.list, &config.elem_list);
-
- /* start the DMA */
- err = dma_set_config(dc->dmac, dc->chan, &config);
- if (err < 0)
- return err;
-
- err = dma_start(dc->dmac, dc->chan);
- if (err < 0)
- return err;
-
- /* bytes copied */
- return local_sg_elem.size;
-}
-
-int dma_copy_new(struct dma_copy *dc)
-{
- uint32_t dir, cap, dev;
-
- /* request HDA DMA in the dir LMEM->HMEM with shared access */
- dir = DMA_DIR_LMEM_TO_HMEM;
- dev = DMA_DEV_HOST;
- cap = 0;
- dc->dmac = dma_get(dir, cap, dev, DMA_ACCESS_SHARED);
- if (dc->dmac == NULL) {
- trace_dma_error("ec0");
- return -ENODEV;
- }
-
-#if !defined CONFIG_DMA_GW
- /* get DMA channel from DMAC0 */
- dc->chan = dma_channel_get(dc->dmac, 0);
- if (dc->chan < 0) {
- trace_dma_error("ec1");
- return dc->chan;
- }
-
- dc->complete.timeout = 100; /* wait 100 usecs for DMA to finish */
- dma_set_cb(dc->dmac, dc->chan, DMA_IRQ_TYPE_LLIST, dma_complete,
- &dc->complete);
-#endif
-
- return 0;
-}
-
-#if defined CONFIG_DMA_GW
-
-int dma_copy_set_stream_tag(struct dma_copy *dc, uint32_t stream_tag)
-{
- /* get DMA channel from DMAC */
- dc->chan = dma_channel_get(dc->dmac, stream_tag - 1);
- if (dc->chan < 0) {
- trace_dma_error("ec1");
- return -EINVAL;
- }
-
- return 0;
-}
-
-#endif
diff --git a/src/ipc/handler.c b/src/ipc/handler.c
deleted file mode 100644
index 207f176..0000000
--- a/src/ipc/handler.c
+++ /dev/null
@@ -1,1153 +0,0 @@
-/*
- * Copyright (c) 2016, Intel Corporation
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- * * Redistributions of source code must retain the above copyright
- * notice, this list of conditions and the following disclaimer.
- * * Redistributions in binary form must reproduce the above copyright
- * notice, this list of conditions and the following disclaimer in the
- * documentation and/or other materials provided with the distribution.
- * * Neither the name of the Intel Corporation nor the
- * names of its contributors may be used to endorse or promote products
- * derived from this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
- * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
- * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
- * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
- * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
- * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
- * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
- * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
- * POSSIBILITY OF SUCH DAMAGE.
- *
- * Author: Liam Girdwood <liam.r.girdwood@linux.intel.com>
- * Keyon Jie <yang.jie@linux.intel.com>
- *
- * IPC (InterProcessor Communication) provides a method of two way
- * communication between the host processor and the DSP. The IPC used here
- * utilises a shared mailbox and door bell between the host and DSP.
- *
- */
-
-#include <stdbool.h>
-#include <sof/debug.h>
-#include <sof/timer.h>
-#include <sof/interrupt.h>
-#include <sof/ipc.h>
-#include <sof/mailbox.h>
-#include <sof/sof.h>
-#include <sof/stream.h>
-#include <sof/dai.h>
-#include <sof/dma.h>
-#include <sof/alloc.h>
-#include <sof/wait.h>
-#include <sof/trace.h>
-#include <sof/ssp.h>
-#include <platform/interrupt.h>
-#include <platform/mailbox.h>
-#include <platform/shim.h>
-#include <platform/dma.h>
-#include <platform/timer.h>
-#include <sof/audio/component.h>
-#include <sof/audio/pipeline.h>
-#include <uapi/ipc.h>
-#include <sof/intel-ipc.h>
-#include <sof/dma-trace.h>
-#include <sof/cpu.h>
-#include <config.h>
-
-#define iGS(x) ((x >> SOF_GLB_TYPE_SHIFT) & 0xf)
-#define iCS(x) ((x >> SOF_CMD_TYPE_SHIFT) & 0xfff)
-
-#define IPC_INVALID_SIZE(ipc) \
- (sizeof(*(ipc)) != ipc->hdr.size)
-
-/* IPC context - shared with platform IPC driver */
-struct ipc *_ipc;
-
-static inline struct sof_ipc_hdr *mailbox_validate(void)
-{
- struct sof_ipc_hdr *hdr = _ipc->comp_data;
-
- /* read component values from the inbox */
- mailbox_hostbox_read(hdr, 0, sizeof(*hdr));
-
- /* validate component header */
- if (hdr->size > SOF_IPC_MSG_MAX_SIZE) {
- trace_ipc_error("ebg");
- return NULL;
- }
-
- /* read rest of component data */
- mailbox_hostbox_read(hdr + 1, sizeof(*hdr), hdr->size - sizeof(*hdr));
- return hdr;
-}
-
-#ifdef CONFIG_HOST_PTABLE
-/* check if a pipeline is hostless when walking downstream */
-static bool is_hostless_downstream(struct comp_dev *current)
-{
- struct list_item *clist;
-
- /* check if current is a HOST comp */
- if (current->comp.type == SOF_COMP_HOST ||
- current->comp.type == SOF_COMP_SG_HOST)
- return false;
-
- /* check if the pipeline has a HOST comp downstream */
- list_for_item(clist, ¤t->bsink_list) {
- struct comp_buffer *buffer;
-
- buffer = container_of(clist, struct comp_buffer, source_list);
-
- /* don't go downstream if this component is not connected */
- if (!buffer->connected)
- continue;
-
- /* dont go downstream if this comp belongs to another pipe */
- if (buffer->sink->comp.pipeline_id != current->comp.pipeline_id)
- continue;
-
- /* return if there's a host comp downstream */
- if (!is_hostless_downstream(buffer->sink))
- return false;
- }
-
- return true;
-}
-
-/* check if a pipeline is hostless when walking upstream */
-static bool is_hostless_upstream(struct comp_dev *current)
-{
- struct list_item *clist;
-
- /* check if current is a HOST comp */
- if (current->comp.type == SOF_COMP_HOST ||
- current->comp.type == SOF_COMP_SG_HOST)
- return false;
-
- /* check if the pipeline has a HOST comp upstream */
- list_for_item(clist, ¤t->bsource_list) {
- struct comp_buffer *buffer;
-
- buffer = container_of(clist, struct comp_buffer, sink_list);
-
- /* don't go upstream if this component is not connected */
- if (!buffer->connected)
- continue;
-
- /* dont go upstream if this comp belongs to another pipeline */
- if (buffer->source->comp.pipeline_id !=
- current->comp.pipeline_id)
- continue;
-
- /* return if there is a host comp upstream */
- if (!is_hostless_upstream(buffer->source))
- return false;
- }
-
- return true;
-}
-#endif
-
-/*
- * Stream IPC Operations.
- */
-
-/* allocate a new stream */
-static int ipc_stream_pcm_params(uint32_t stream)
-{
-#ifdef CONFIG_HOST_PTABLE
- struct intel_ipc_data *iipc = ipc_get_drvdata(_ipc);
- struct sof_ipc_comp_host *host = NULL;
- struct list_item elem_list;
- struct dma_sg_elem *elem;
- struct list_item *plist;
- uint32_t ring_size;
-#endif
- struct sof_ipc_pcm_params *pcm_params = _ipc->comp_data;
- struct sof_ipc_pcm_params_reply reply;
- struct ipc_comp_dev *pcm_dev;
- struct comp_dev *cd;
- int err, posn_offset;
-
- trace_ipc("SAl");
-
- /* sanity check size */
- if (IPC_INVALID_SIZE(pcm_params)) {
- trace_ipc_error("eAS");
- return -EINVAL;
- }
-
- /* get the pcm_dev */
- pcm_dev = ipc_get_comp(_ipc, pcm_params->comp_id);
- if (pcm_dev == NULL) {
- trace_ipc_error("eAC");
- trace_error_value(pcm_params->comp_id);
- return -ENODEV;
- }
-
- /* sanity check comp */
- if (pcm_dev->cd->pipeline == NULL) {
- trace_ipc_error("eA1");
- trace_error_value(pcm_params->comp_id);
- return -EINVAL;
- }
-
- /* set params component params */
- cd = pcm_dev->cd;
- cd->params = pcm_params->params;
-
-#ifdef CONFIG_HOST_PTABLE
- list_init(&elem_list);
-
- /*
- * walk in both directions to check if the pipeline is hostless
- * skip page table set up if it is
- */
- if (is_hostless_downstream(cd) && is_hostless_upstream(cd))
- goto pipe_params;
-
- /* use DMA to read in compressed page table ringbuffer from host */
- err = ipc_get_page_descriptors(iipc->dmac, iipc->page_table,
- &pcm_params->params.buffer);
- if (err < 0) {
- trace_ipc_error("eAp");
- goto error;
- }
-
- /* Parse host tables */
- host = (struct sof_ipc_comp_host *)&cd->comp;
- ring_size = pcm_params->params.buffer.size;
-
- err = ipc_parse_page_descriptors(iipc->page_table,
- &pcm_params->params.buffer,
- &elem_list, host->direction);
- if (err < 0) {
- trace_ipc_error("eAP");
- goto error;
- }
-
- list_for_item(plist, &elem_list) {
- elem = container_of(plist, struct dma_sg_elem, list);
-
- err = comp_host_buffer(cd, elem, ring_size);
- if (err < 0) {
- trace_ipc_error("ePb");
- goto error;
- }
-
- list_item_del(&elem->list);
- rfree(elem);
- }
-
-pipe_params:
-#endif
-
- /* configure pipeline audio params */
- err = pipeline_params(pcm_dev->cd->pipeline, pcm_dev->cd, pcm_params);
- if (err < 0) {
- trace_ipc_error("eAa");
- goto error;
- }
-
- /* prepare pipeline audio params */
- err = pipeline_prepare(pcm_dev->cd->pipeline, pcm_dev->cd);
- if (err < 0) {
- trace_ipc_error("eAr");
- goto error;
- }
-
- posn_offset = ipc_get_posn_offset(_ipc, pcm_dev->cd->pipeline);
- if (posn_offset < 0) {
- trace_ipc_error("eAo");
- goto error;
- }
- /* write component values to the outbox */
- reply.rhdr.hdr.size = sizeof(reply);
- reply.rhdr.hdr.cmd = stream;
- reply.rhdr.error = 0;
- reply.comp_id = pcm_params->comp_id;
- reply.posn_offset = posn_offset;
- mailbox_hostbox_write(0, &reply, sizeof(reply));
- return 1;
-
-error:
-#ifdef CONFIG_HOST_PTABLE
- list_for_item(plist, &elem_list) {
- elem = container_of(plist, struct dma_sg_elem, list);
- list_item_del(&elem->list);
- rfree(elem);
- }
-#endif
-
- err = pipeline_reset(pcm_dev->cd->pipeline, pcm_dev->cd);
- if (err < 0)
- trace_ipc_error("eA!");
- return -EINVAL;
-}
-
-/* free stream resources */
-static int ipc_stream_pcm_free(uint32_t header)
-{
- struct sof_ipc_stream *free_req = _ipc->comp_data;
- struct ipc_comp_dev *pcm_dev;
-
- trace_ipc("SFr");
-
- /* sanity check size */
- if (IPC_INVALID_SIZE(free_req)) {
- trace_ipc_error("eFs");
- return -EINVAL;
- }
-
- /* get the pcm_dev */
- pcm_dev = ipc_get_comp(_ipc, free_req->comp_id);
- if (pcm_dev == NULL) {
- trace_ipc_error("eFr");
- return -ENODEV;
- }
-
- /* sanity check comp */
- if (pcm_dev->cd->pipeline == NULL) {
- trace_ipc_error("eF1");
- trace_error_value(free_req->comp_id);
- return -EINVAL;
- }
-
- /* reset the pipeline */
- return pipeline_reset(pcm_dev->cd->pipeline, pcm_dev->cd);
-}
-
-/* get stream position */
-static int ipc_stream_position(uint32_t header)
-{
- struct sof_ipc_stream *stream = _ipc->comp_data;
- struct sof_ipc_stream_posn posn;
- struct ipc_comp_dev *pcm_dev;
-
- trace_ipc("pos");
-
- memset(&posn, 0, sizeof(posn));
-
- /* sanity check size */
- if (IPC_INVALID_SIZE(stream)) {
- trace_ipc_error("ePs");
- return -EINVAL;
- }
-
- /* get the pcm_dev */
- pcm_dev = ipc_get_comp(_ipc, stream->comp_id);
- if (pcm_dev == NULL) {
- trace_ipc_error("epo");
- return -ENODEV;
- }
-
- /* set message fields - TODO; get others */
- posn.rhdr.hdr.cmd = SOF_IPC_GLB_STREAM_MSG | SOF_IPC_STREAM_POSITION |
- stream->comp_id;
- posn.rhdr.hdr.size = sizeof(posn);
- posn.comp_id = stream->comp_id;
-
- /* get the stream positions and timestamps */
- pipeline_get_timestamp(pcm_dev->cd->pipeline, pcm_dev->cd, &posn);
-
- /* copy positions to stream region */
- mailbox_stream_write(pcm_dev->cd->pipeline->posn_offset,
- &posn, sizeof(posn));
-
- return 1;
-}
-
-/* send stream position */
-int ipc_stream_send_position(struct comp_dev *cdev,
- struct sof_ipc_stream_posn *posn)
-{
- struct sof_ipc_hdr hdr;
-
- tracev_ipc("Pos");
- posn->rhdr.hdr.cmd = SOF_IPC_GLB_STREAM_MSG | SOF_IPC_STREAM_POSITION |
- cdev->comp.id;
- posn->rhdr.hdr.size = sizeof(*posn);
- posn->comp_id = cdev->comp.id;
-
- hdr.cmd = posn->rhdr.hdr.cmd;
- hdr.size = sizeof(hdr);
-
- mailbox_stream_write(cdev->pipeline->posn_offset, posn, sizeof(*posn));
- return ipc_queue_host_message(_ipc, posn->rhdr.hdr.cmd, &hdr,
- sizeof(hdr), NULL, 0, NULL, NULL, 0);
-}
-
-/* send stream position TODO: send compound message */
-int ipc_stream_send_xrun(struct comp_dev *cdev,
- struct sof_ipc_stream_posn *posn)
-{
- struct sof_ipc_hdr hdr;
-
- posn->rhdr.hdr.cmd = SOF_IPC_GLB_STREAM_MSG | SOF_IPC_STREAM_TRIG_XRUN;
- posn->rhdr.hdr.size = sizeof(*posn);
- posn->comp_id = cdev->comp.id;
-
- hdr.cmd = posn->rhdr.hdr.cmd;
- hdr.size = sizeof(hdr);
-
- mailbox_stream_write(cdev->pipeline->posn_offset, posn, sizeof(*posn));
- return ipc_queue_host_message(_ipc, posn->rhdr.hdr.cmd, &hdr,
- sizeof(hdr), NULL, 0, NULL, NULL, 0);
-}
-
-static int ipc_stream_trigger(uint32_t header)
-{
- struct ipc_comp_dev *pcm_dev;
- uint32_t cmd = COMP_TRIGGER_RELEASE;
- struct sof_ipc_stream *stream = _ipc->comp_data;
- uint32_t ipc_cmd = (header & SOF_CMD_TYPE_MASK) >> SOF_CMD_TYPE_SHIFT;
- int ret;
-
- trace_ipc("tri");
-
- /* sanity check size */
- if (IPC_INVALID_SIZE(stream)) {
- trace_ipc_error("eRs");
- return -EINVAL;
- }
-
- /* get the pcm_dev */
- pcm_dev = ipc_get_comp(_ipc, stream->comp_id);
- if (pcm_dev == NULL) {
- trace_ipc_error("eRg");
- return -ENODEV;
- }
-
- switch (ipc_cmd) {
- case iCS(SOF_IPC_STREAM_TRIG_START):
- cmd = COMP_TRIGGER_START;
- break;
- case iCS(SOF_IPC_STREAM_TRIG_STOP):
- cmd = COMP_TRIGGER_STOP;
- break;
- case iCS(SOF_IPC_STREAM_TRIG_PAUSE):
- cmd = COMP_TRIGGER_PAUSE;
- break;
- case iCS(SOF_IPC_STREAM_TRIG_RELEASE):
- cmd = COMP_TRIGGER_RELEASE;
- break;
- /* XRUN is special case- TODO */
- case iCS(SOF_IPC_STREAM_TRIG_XRUN):
- return 0;
- }
-
- /* trigger the component */
- ret = pipeline_trigger(pcm_dev->cd->pipeline, pcm_dev->cd, cmd);
- if (ret < 0) {
- trace_ipc_error("eRc");
- trace_error_value(ipc_cmd);
- }
-
- return ret;
-}
-
-static int ipc_glb_stream_message(uint32_t header)
-{
- uint32_t cmd = (header & SOF_CMD_TYPE_MASK) >> SOF_CMD_TYPE_SHIFT;
-
- switch (cmd) {
- case iCS(SOF_IPC_STREAM_PCM_PARAMS):
- return ipc_stream_pcm_params(header);
- case iCS(SOF_IPC_STREAM_PCM_FREE):
- return ipc_stream_pcm_free(header);
- case iCS(SOF_IPC_STREAM_TRIG_START):
- case iCS(SOF_IPC_STREAM_TRIG_STOP):
- case iCS(SOF_IPC_STREAM_TRIG_PAUSE):
- case iCS(SOF_IPC_STREAM_TRIG_RELEASE):
- case iCS(SOF_IPC_STREAM_TRIG_DRAIN):
- case iCS(SOF_IPC_STREAM_TRIG_XRUN):
- return ipc_stream_trigger(header);
- case iCS(SOF_IPC_STREAM_POSITION):
- return ipc_stream_position(header);
- default:
- trace_ipc_error("es1");
- return -EINVAL;
- }
-}
-
-/*
- * DAI IPC Operations.
- */
-
-static int ipc_dai_config(uint32_t header)
-{
- struct sof_ipc_dai_config *config = _ipc->comp_data;
- struct dai *dai;
- int ret;
-
- trace_ipc("DsF");
-
- /* get DAI */
- dai = dai_get(config->type, config->dai_index);
- if (dai == NULL) {
- trace_ipc_error("eDi");
- trace_error_value(config->type);
- trace_error_value(config->dai_index);
- return -ENODEV;
- }
-
- /* configure DAI */
- ret = dai_set_config(dai, config);
- if (ret < 0) {
- trace_ipc_error("eDC");
- return ret;
- }
-
- /* now send params to all DAI components who use that physical DAI */
- return ipc_comp_dai_config(_ipc, config);
-}
-
-static int ipc_glb_dai_message(uint32_t header)
-{
- uint32_t cmd = (header & SOF_CMD_TYPE_MASK) >> SOF_CMD_TYPE_SHIFT;
-
- switch (cmd) {
- case iCS(SOF_IPC_DAI_CONFIG):
- return ipc_dai_config(header);
- case iCS(SOF_IPC_DAI_LOOPBACK):
- //return ipc_comp_set_value(header, COMP_CMD_LOOPBACK);
- default:
- trace_ipc_error("eDc");
- trace_error_value(header);
- return -EINVAL;
- }
-}
-
-/*
- * PM IPC Operations.
- */
-
-static int ipc_pm_context_size(uint32_t header)
-{
- struct sof_ipc_pm_ctx pm_ctx;
-
- trace_ipc("PMs");
-
- bzero(&pm_ctx, sizeof(pm_ctx));
-
- /* TODO: calculate the context and size of host buffers required */
-
- /* write the context to the host driver */
- mailbox_hostbox_write(0, &pm_ctx, sizeof(pm_ctx));
- return 1;
-}
-
-static int ipc_pm_context_save(uint32_t header)
-{
- struct sof_ipc_pm_ctx *pm_ctx = _ipc->comp_data;
- struct intel_ipc_data *iipc = ipc_get_drvdata(_ipc);
-
- trace_ipc("PMs");
-
- /* TODO: check we are inactive - all streams are suspended */
-
- /* TODO: mask ALL platform interrupts except DMA */
-
- /* TODO now save the context - create SG buffer config using */
- //mm_pm_context_save(struct dma_sg_config *sg);
-
- /* mask all DSP interrupts */
- arch_interrupt_disable_mask(0xffff);
-
- /* TODO: mask ALL platform interrupts inc DMA */
-
- /* TODO: clear any outstanding platform IRQs - TODO refine */
-
- /* TODO: stop ALL timers */
- platform_timer_stop(platform_timer);
-
- /* TODO: disable SSP and DMA HW */
-
- /* TODO: save the context */
- //reply.entries_no = 0;
-
- /* write the context to the host driver */
- mailbox_hostbox_write(0, pm_ctx, sizeof(*pm_ctx));
-
- iipc->pm_prepare_D3 = 1;
-
- return 1;
-}
-
-static int ipc_pm_context_restore(uint32_t header)
-{
- struct sof_ipc_pm_ctx *pm_ctx = _ipc->comp_data;
-
- trace_ipc("PMr");
-
- /* restore context placeholder */
- mailbox_hostbox_write(0, pm_ctx, sizeof(*pm_ctx));
-
- return 1;
-}
-
-static int ipc_pm_core_enable(uint32_t header)
-{
- struct sof_ipc_pm_core_config *pm_core_config = _ipc->comp_data;
- int i = 0;
-
- trace_ipc("PMc");
-
- for (i = 0; i < PLATFORM_CORE_COUNT; i++) {
- if (i != PLATFORM_MASTER_CORE_ID) {
- if (pm_core_config->enable_mask & (1 << i))
- cpu_enable_core(i);
- else
- cpu_disable_core(i);
- }
- }
-
- return 0;
-}
-
-static int ipc_glb_pm_message(uint32_t header)
-{
- uint32_t cmd = (header & SOF_CMD_TYPE_MASK) >> SOF_CMD_TYPE_SHIFT;
-
- switch (cmd) {
- case iCS(SOF_IPC_PM_CTX_SAVE):
- return ipc_pm_context_save(header);
- case iCS(SOF_IPC_PM_CTX_RESTORE):
- return ipc_pm_context_restore(header);
- case iCS(SOF_IPC_PM_CTX_SIZE):
- return ipc_pm_context_size(header);
- case iCS(SOF_IPC_PM_CORE_ENABLE):
- return ipc_pm_core_enable(header);
- case iCS(SOF_IPC_PM_CLK_SET):
- case iCS(SOF_IPC_PM_CLK_GET):
- case iCS(SOF_IPC_PM_CLK_REQ):
- default:
- return -EINVAL;
- }
-}
-
-/*
- * Debug IPC Operations.
- */
-
-static int ipc_dma_trace_config(uint32_t header)
-{
-#ifdef CONFIG_HOST_PTABLE
- struct intel_ipc_data *iipc = ipc_get_drvdata(_ipc);
- struct list_item elem_list;
- struct dma_sg_elem *elem;
- struct list_item *plist;
- uint32_t ring_size;
-#endif
- struct sof_ipc_dma_trace_params *params = _ipc->comp_data;
- struct sof_ipc_reply reply;
- int err;
-
- trace_ipc("DA1");
-
- /* sanity check size */
- if (IPC_INVALID_SIZE(params)) {
- trace_ipc_error("DAs");
- return -EINVAL;
- }
-
-#ifdef CONFIG_HOST_PTABLE
-
- list_init(&elem_list);
-
- /* use DMA to read in compressed page table ringbuffer from host */
- err = ipc_get_page_descriptors(iipc->dmac, iipc->page_table,
- ¶ms->buffer);
- if (err < 0) {
- trace_ipc_error("eCp");
- goto error;
- }
-
- trace_ipc("DAg");
-
- /* Parse host tables */
- ring_size = params->buffer.size;
-
- err = ipc_parse_page_descriptors(iipc->page_table, ¶ms->buffer,
- &elem_list, SOF_IPC_STREAM_CAPTURE);
- if (err < 0) {
- trace_ipc_error("ePP");
- goto error;
- }
-
- list_for_item(plist, &elem_list) {
- elem = container_of(plist, struct dma_sg_elem, list);
-
- err = dma_trace_host_buffer(_ipc->dmat, elem, ring_size);
- if (err < 0) {
- trace_ipc_error("ePb");
- goto error;
- }
-
- list_item_del(&elem->list);
- rfree(elem);
- }
-#else
- /* stream tag of capture stream for DMA trace */
- _ipc->dmat->stream_tag = params->stream_tag;
-
- /* host buffer size for DMA trace */
- _ipc->dmat->host_size = params->buffer.size;
-#endif
- trace_ipc("DAp");
-
- err = dma_trace_enable(_ipc->dmat);
- if (err < 0)
- goto error;
-
- /* write component values to the outbox */
- reply.hdr.size = sizeof(reply);
- reply.hdr.cmd = header;
- reply.error = 0;
- mailbox_hostbox_write(0, &reply, sizeof(reply));
- return 0;
-
-error:
-#ifdef CONFIG_HOST_PTABLE
- list_for_item(plist, &elem_list) {
- elem = container_of(plist, struct dma_sg_elem, list);
- list_item_del(&elem->list);
- rfree(elem);
- }
-#endif
-
- if (err < 0)
- trace_ipc_error("eA!");
- return -EINVAL;
-}
-
-/* send DMA trace host buffer position to host */
-int ipc_dma_trace_send_position(void)
-{
- struct sof_ipc_dma_trace_posn posn;
-
- posn.rhdr.hdr.cmd = SOF_IPC_GLB_TRACE_MSG | SOF_IPC_TRACE_DMA_POSITION;
- posn.host_offset = _ipc->dmat->host_offset;
- posn.overflow = _ipc->dmat->overflow;
- posn.messages = _ipc->dmat->messages;
- posn.rhdr.hdr.size = sizeof(posn);
-
- return ipc_queue_host_message(_ipc, posn.rhdr.hdr.cmd, &posn,
- sizeof(posn), NULL, 0, NULL, NULL, 1);
-}
-
-static int ipc_glb_debug_message(uint32_t header)
-{
- uint32_t cmd = (header & SOF_CMD_TYPE_MASK) >> SOF_CMD_TYPE_SHIFT;
-
- trace_ipc("Idn");
-
- switch (cmd) {
- case iCS(SOF_IPC_TRACE_DMA_PARAMS):
- return ipc_dma_trace_config(header);
- default:
- trace_ipc_error("eDc");
- trace_error_value(header);
- return -EINVAL;
- }
-}
-
-/*
- * Topology IPC Operations.
- */
-
-/* get/set component values or runtime data */
-static int ipc_comp_value(uint32_t header, uint32_t cmd)
-{
- struct ipc_comp_dev *comp_dev;
- struct sof_ipc_ctrl_data *data = _ipc->comp_data;
- int ret;
-
- trace_ipc("VoG");
-
- /* get the component */
- comp_dev = ipc_get_comp(_ipc, data->comp_id);
- if (comp_dev == NULL){
- trace_ipc_error("eVg");
- trace_error_value(data->comp_id);
- return -ENODEV;
- }
-
- /* get component values */
- ret = comp_cmd(comp_dev->cd, cmd, data);
- if (ret < 0) {
- trace_ipc_error("eVG");
- return ret;
- }
-
- /* write component values to the outbox */
- mailbox_hostbox_write(0, data, data->rhdr.hdr.size);
- return 1;
-}
-
-static int ipc_glb_comp_message(uint32_t header)
-{
- uint32_t cmd = (header & SOF_CMD_TYPE_MASK) >> SOF_CMD_TYPE_SHIFT;
-
- switch (cmd) {
- case iCS(SOF_IPC_COMP_SET_VALUE):
- return ipc_comp_value(header, COMP_CMD_SET_VALUE);
- case iCS(SOF_IPC_COMP_GET_VALUE):
- return ipc_comp_value(header, COMP_CMD_GET_VALUE);
- case iCS(SOF_IPC_COMP_SET_DATA):
- return ipc_comp_value(header, COMP_CMD_SET_DATA);
- case iCS(SOF_IPC_COMP_GET_DATA):
- return ipc_comp_value(header, COMP_CMD_GET_DATA);
- default:
- trace_ipc_error("eCc");
- trace_error_value(header);
- return -EINVAL;
- }
-}
-
-static int ipc_glb_tplg_comp_new(uint32_t header)
-{
- struct sof_ipc_comp *comp = _ipc->comp_data;
- struct sof_ipc_comp_reply reply;
- int ret;
-
- trace_ipc("tcn");
-
- /* register component */
- ret = ipc_comp_new(_ipc, comp);
- if (ret < 0) {
- trace_ipc_error("cn1");
- return ret;
- }
-
- /* write component values to the outbox */
- reply.rhdr.hdr.size = sizeof(reply);
- reply.rhdr.hdr.cmd = header;
- reply.rhdr.error = 0;
- reply.offset = 0; /* TODO: set this up for mmaped components */
- mailbox_hostbox_write(0, &reply, sizeof(reply));
- return 1;
-}
-
-static int ipc_glb_tplg_buffer_new(uint32_t header)
-{
- struct sof_ipc_buffer *ipc_buffer = _ipc->comp_data;
- struct sof_ipc_comp_reply reply;
- int ret;
-
- trace_ipc("Ibn");
-
- ret = ipc_buffer_new(_ipc, ipc_buffer);
- if (ret < 0) {
- trace_ipc_error("bn1");
- return ret;
- }
-
- /* write component values to the outbox */
- reply.rhdr.hdr.size = sizeof(reply);
- reply.rhdr.hdr.cmd = header;
- reply.rhdr.error = 0;
- reply.offset = 0; /* TODO: set this up for mmaped components */
- mailbox_hostbox_write(0, &reply, sizeof(reply));
- return 1;
-}
-
-static int ipc_glb_tplg_pipe_new(uint32_t header)
-{
- struct sof_ipc_pipe_new *ipc_pipeline = _ipc->comp_data;
- struct sof_ipc_comp_reply reply;
- int ret;
-
- trace_ipc("Ipn");
-
- /* sanity check size */
- if (IPC_INVALID_SIZE(ipc_pipeline)) {
- trace_ipc_error("Ips");
- return -EINVAL;
- }
-
- ret = ipc_pipeline_new(_ipc, ipc_pipeline);
- if (ret < 0) {
- trace_ipc_error("pn1");
- return ret;
- }
-
- /* write component values to the outbox */
- reply.rhdr.hdr.size = sizeof(reply);
- reply.rhdr.hdr.cmd = header;
- reply.rhdr.error = 0;
- reply.offset = 0; /* TODO: set this up for mmaped components */
- mailbox_hostbox_write(0, &reply, sizeof(reply));
- return 1;
-}
-
-static int ipc_glb_tplg_pipe_complete(uint32_t header)
-{
- struct sof_ipc_pipe_ready *ipc_pipeline = _ipc->comp_data;
-
- trace_ipc("Ipc");
-
- return ipc_pipeline_complete(_ipc, ipc_pipeline->comp_id);
-}
-
-static int ipc_glb_tplg_comp_connect(uint32_t header)
-{
- struct sof_ipc_pipe_comp_connect *connect = _ipc->comp_data;
-
- trace_ipc("Icn");
-
- /* sanity check size */
- if (IPC_INVALID_SIZE(connect)) {
- trace_ipc_error("Ics");
- return -EINVAL;
- }
-
- return ipc_comp_connect(_ipc, connect);
-}
-
-static int ipc_glb_tplg_free(uint32_t header,
- int (*free_func)(struct ipc *ipc, uint32_t id))
-{
- struct sof_ipc_free *ipc_free = _ipc->comp_data;
-
- trace_ipc("Tcf");
-
- /* sanity check size */
- if (IPC_INVALID_SIZE(ipc_free)) {
- trace_ipc_error("Tcs");
- return -EINVAL;
- }
-
- /* free the object */
- free_func(_ipc, ipc_free->id);
-
- return 0;
-}
-
-static int ipc_glb_tplg_message(uint32_t header)
-{
- uint32_t cmd = (header & SOF_CMD_TYPE_MASK) >> SOF_CMD_TYPE_SHIFT;
-
- switch (cmd) {
- case iCS(SOF_IPC_TPLG_COMP_NEW):
- return ipc_glb_tplg_comp_new(header);
- case iCS(SOF_IPC_TPLG_COMP_FREE):
- return ipc_glb_tplg_free(header, ipc_comp_free);
- case iCS(SOF_IPC_TPLG_COMP_CONNECT):
- return ipc_glb_tplg_comp_connect(header);
- case iCS(SOF_IPC_TPLG_PIPE_NEW):
- return ipc_glb_tplg_pipe_new(header);
- case iCS(SOF_IPC_TPLG_PIPE_COMPLETE):
- return ipc_glb_tplg_pipe_complete(header);
- case iCS(SOF_IPC_TPLG_PIPE_FREE):
- return ipc_glb_tplg_free(header, ipc_pipeline_free);
- case iCS(SOF_IPC_TPLG_BUFFER_NEW):
- return ipc_glb_tplg_buffer_new(header);
- case iCS(SOF_IPC_TPLG_BUFFER_FREE):
- return ipc_glb_tplg_free(header, ipc_buffer_free);
- default:
- trace_ipc_error("eTc");
- trace_error_value(header);
- return -EINVAL;
- }
-}
-
-/*
- * Global IPC Operations.
- */
-
-int ipc_cmd(void)
-{
- struct sof_ipc_hdr *hdr;
- uint32_t type;
-
- hdr = mailbox_validate();
- if (hdr == NULL) {
- trace_ipc_error("hdr");
- return -EINVAL;
- }
-
- type = (hdr->cmd & SOF_GLB_TYPE_MASK) >> SOF_GLB_TYPE_SHIFT;
-
- switch (type) {
- case iGS(SOF_IPC_GLB_REPLY):
- return 0;
- case iGS(SOF_IPC_GLB_COMPOUND):
- return -EINVAL; /* TODO */
- case iGS(SOF_IPC_GLB_TPLG_MSG):
- return ipc_glb_tplg_message(hdr->cmd);
- case iGS(SOF_IPC_GLB_PM_MSG):
- return ipc_glb_pm_message(hdr->cmd);
- case iGS(SOF_IPC_GLB_COMP_MSG):
- return ipc_glb_comp_message(hdr->cmd);
- case iGS(SOF_IPC_GLB_STREAM_MSG):
- return ipc_glb_stream_message(hdr->cmd);
- case iGS(SOF_IPC_GLB_DAI_MSG):
- return ipc_glb_dai_message(hdr->cmd);
- case iGS(SOF_IPC_GLB_TRACE_MSG):
- return ipc_glb_debug_message(hdr->cmd);
- default:
- trace_ipc_error("eGc");
- trace_error_value(type);
- return -EINVAL;
- }
-}
-
-/* locks held by caller */
-static inline struct ipc_msg *msg_get_empty(struct ipc *ipc)
-{
- struct ipc_msg *msg = NULL;
-
- if (!list_is_empty(&ipc->empty_list)) {
- msg = list_first_item(&ipc->empty_list, struct ipc_msg, list);
- list_item_del(&msg->list);
- }
-
- return msg;
-}
-
-static inline struct ipc_msg *ipc_glb_stream_message_find(struct ipc *ipc,
- struct sof_ipc_stream_posn *posn)
-{
- struct list_item *plist;
- struct ipc_msg *msg = NULL;
- struct sof_ipc_stream_posn *old_posn = NULL;
- uint32_t cmd;
-
- /* Check whether the command is expected */
- cmd = (posn->rhdr.hdr.cmd & SOF_CMD_TYPE_MASK) >> SOF_CMD_TYPE_SHIFT;
-
- switch (cmd) {
- case iCS(SOF_IPC_STREAM_TRIG_XRUN):
- case iCS(SOF_IPC_STREAM_POSITION):
-
- /* iterate host message list for searching */
- list_for_item(plist, &ipc->msg_list) {
- msg = container_of(plist, struct ipc_msg, list);
- if (msg->header == posn->rhdr.hdr.cmd) {
- old_posn = (struct sof_ipc_stream_posn *)msg->tx_data;
- if (old_posn->comp_id == posn->comp_id)
- return msg;
- }
- }
- break;
- default:
- break;
- }
-
- /* no match */
- return NULL;
-}
-
-static inline struct ipc_msg *ipc_glb_trace_message_find(struct ipc *ipc,
- struct sof_ipc_dma_trace_posn *posn)
-{
- struct list_item *plist;
- struct ipc_msg *msg = NULL;
- uint32_t cmd;
-
- /* Check whether the command is expected */
- cmd = (posn->rhdr.hdr.cmd & SOF_CMD_TYPE_MASK) >> SOF_CMD_TYPE_SHIFT;
-
- switch (cmd) {
- case iCS(SOF_IPC_TRACE_DMA_POSITION):
- /* iterate host message list for searching */
- list_for_item(plist, &ipc->msg_list) {
- msg = container_of(plist, struct ipc_msg, list);
- if (msg->header == posn->rhdr.hdr.cmd)
- return msg;
- }
- break;
- default:
- break;
- }
-
- /* no match */
- return NULL;
-}
-
-static inline struct ipc_msg *msg_find(struct ipc *ipc, uint32_t header,
- void *tx_data)
-{
- uint32_t type;
-
- /* use different sub function for different global message type */
- type = (header & SOF_GLB_TYPE_MASK) >> SOF_GLB_TYPE_SHIFT;
-
- switch (type) {
- case iGS(SOF_IPC_GLB_STREAM_MSG):
- return ipc_glb_stream_message_find(ipc,
- (struct sof_ipc_stream_posn *)tx_data);
- case iGS(SOF_IPC_GLB_TRACE_MSG):
- return ipc_glb_trace_message_find(ipc,
- (struct sof_ipc_dma_trace_posn *)tx_data);
- default:
- /* not found */
- return NULL;
- }
-}
-
-int ipc_queue_host_message(struct ipc *ipc, uint32_t header,
- void *tx_data, size_t tx_bytes, void *rx_data,
- size_t rx_bytes, void (*cb)(void*, void*), void *cb_data, uint32_t replace)
-{
- struct ipc_msg *msg = NULL;
- uint32_t flags, found = 0;
- int ret = 0;
-
- spin_lock_irq(&ipc->lock, flags);
-
- /* do we need to replace an existing message? */
- if (replace)
- msg = msg_find(ipc, header, tx_data);
-
- /* do we need to use a new empty message? */
- if (msg)
- found = 1;
- else
- msg = msg_get_empty(ipc);
-
- if (msg == NULL) {
- trace_ipc_error("eQb");
- ret = -EBUSY;
- goto out;
- }
-
- /* prepare the message */
- msg->header = header;
- msg->tx_size = tx_bytes;
- msg->rx_size = rx_bytes;
- msg->cb_data = cb_data;
- msg->cb = cb;
-
- /* copy mailbox data to message */
- if (tx_bytes > 0 && tx_bytes < SOF_IPC_MSG_MAX_SIZE)
- rmemcpy(msg->tx_data, tx_data, tx_bytes);
-
- if (!found) {
- /* now queue the message */
- ipc->dsp_pending = 1;
- list_item_append(&msg->list, &ipc->msg_list);
- }
-
-out:
- spin_unlock_irq(&ipc->lock, flags);
- return ret;
-}
-
-/* process current message */
-int ipc_process_msg_queue(void)
-{
- if (_ipc->host_pending)
- ipc_platform_do_cmd(_ipc);
- if (_ipc->dsp_pending)
- ipc_platform_send_msg(_ipc);
- return 0;
-}
diff --git a/src/ipc/hsw-ipc.c b/src/ipc/hsw-ipc.c
deleted file mode 100644
index a90b7a1..0000000
--- a/src/ipc/hsw-ipc.c
+++ /dev/null
@@ -1,244 +0,0 @@
-/*
- * Copyright (c) 2016, Intel Corporation
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- * * Redistributions of source code must retain the above copyright
- * notice, this list of conditions and the following disclaimer.
- * * Redistributions in binary form must reproduce the above copyright
- * notice, this list of conditions and the following disclaimer in the
- * documentation and/or other materials provided with the distribution.
- * * Neither the name of the Intel Corporation nor the
- * names of its contributors may be used to endorse or promote products
- * derived from this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
- * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
- * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
- * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
- * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
- * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
- * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
- * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
- * POSSIBILITY OF SUCH DAMAGE.
- *
- * Author: Liam Girdwood <liam.r.girdwood@linux.intel.com>
- */
-
-#include <sof/debug.h>
-#include <sof/timer.h>
-#include <sof/interrupt.h>
-#include <sof/ipc.h>
-#include <sof/mailbox.h>
-#include <sof/sof.h>
-#include <sof/stream.h>
-#include <sof/dai.h>
-#include <sof/dma.h>
-#include <sof/alloc.h>
-#include <sof/wait.h>
-#include <sof/trace.h>
-#include <sof/ssp.h>
-#include <platform/interrupt.h>
-#include <platform/mailbox.h>
-#include <platform/shim.h>
-#include <platform/dma.h>
-#include <platform/platform.h>
-#include <sof/audio/component.h>
-#include <sof/audio/pipeline.h>
-#include <sof/panic.h>
-#include <uapi/ipc.h>
-#include <sof/intel-ipc.h>
-
-extern struct ipc *_ipc;
-
-static void do_notify(void)
-{
- uint32_t flags;
- struct ipc_msg *msg;
-
- tracev_ipc("Not");
-
- spin_lock_irq(&_ipc->lock, flags);
- msg = _ipc->dsp_msg;
- if (msg == NULL)
- goto out;
-
- /* copy the data returned from DSP */
- if (msg->rx_size && msg->rx_size < SOF_IPC_MSG_MAX_SIZE)
- mailbox_dspbox_read(msg->rx_data, 0, msg->rx_size);
-
- /* any callback ? */
- if (msg->cb)
- msg->cb(msg->cb_data, msg->rx_data);
-
- list_item_append(&msg->list, &_ipc->empty_list);
-
-out:
- spin_unlock_irq(&_ipc->lock, flags);
-
- /* clear DONE bit - tell Host we have completed */
- shim_write(SHIM_IPCD, 0);
-
- /* unmask Done interrupt */
- shim_write(SHIM_IMRD, shim_read(SHIM_IMRD) & ~SHIM_IMRD_DONE);
-}
-
-static void irq_handler(void *arg)
-{
- uint32_t isr;
-
- tracev_ipc("IRQ");
-
- /* Interrupt arrived, check src */
- isr = shim_read(SHIM_ISRD);
-
- if (isr & SHIM_ISRD_DONE) {
-
- /* Mask Done interrupt before return */
- shim_write(SHIM_IMRD, shim_read(SHIM_IMRD) | SHIM_IMRD_DONE);
- interrupt_clear(PLATFORM_IPC_INTERUPT);
- do_notify();
- }
-
- if (isr & SHIM_ISRD_BUSY) {
-
- /* Mask Busy interrupt before return */
- shim_write(SHIM_IMRD, shim_read(SHIM_IMRD) | SHIM_IMRD_BUSY);
- interrupt_clear(PLATFORM_IPC_INTERUPT);
-
- /* TODO: place message in Q and process later */
- /* It's not Q ATM, may overwrite */
- if (_ipc->host_pending)
- trace_ipc_error("Pen");
-
- _ipc->host_msg = shim_read(SHIM_IPCX);
- _ipc->host_pending = 1;
- }
-}
-
-void ipc_platform_do_cmd(struct ipc *ipc)
-{
- struct intel_ipc_data *iipc = ipc_get_drvdata(ipc);
- struct sof_ipc_reply reply;
- int32_t err;
-
- tracev_ipc("Cmd");
-
- /* perform command and return any error */
- err = ipc_cmd();
- if (err > 0) {
- goto done; /* reply created and copied by cmd() */
- } else {
- /* send std error reply */
- reply.error = err;
- }
-
- /* send std error/ok reply */
- reply.hdr.cmd = SOF_IPC_GLB_REPLY;
- reply.hdr.size = sizeof(reply);
- mailbox_hostbox_write(0, &reply, sizeof(reply));
-
-done:
- ipc->host_pending = 0;
-
- /* clear BUSY bit and set DONE bit - accept new messages */
- shim_write(SHIM_IPCX, SHIM_IPCX_DONE);
-
- /* unmask busy interrupt */
- shim_write(SHIM_IMRD, shim_read(SHIM_IMRD) & ~SHIM_IMRD_BUSY);
-
- // TODO: signal audio work to enter D3 in normal context
- /* are we about to enter D3 ? */
- if (iipc->pm_prepare_D3) {
- while (1) {
- trace_ipc("pme");
- wait_for_interrupt(0);
- }
- }
-
- tracev_ipc("CmD");
-}
-
-void ipc_platform_send_msg(struct ipc *ipc)
-{
- struct ipc_msg *msg;
- uint32_t flags;
-
- spin_lock_irq(&ipc->lock, flags);
-
- /* any messages to send ? */
- if (list_is_empty(&ipc->msg_list)) {
- ipc->dsp_pending = 0;
- goto out;
- }
-
- /* can't send nofication when one is in progress */
- if (shim_read(SHIM_IPCD) & (SHIM_IPCD_BUSY | SHIM_IPCD_DONE))
- goto out;
-
- /* now send the message */
- msg = list_first_item(&ipc->msg_list, struct ipc_msg, list);
- mailbox_dspbox_write(0, msg->tx_data, msg->tx_size);
- list_item_del(&msg->list);
- ipc->dsp_msg = msg;
- tracev_ipc("Msg");
-
- /* now interrupt host to tell it we have message sent */
- shim_write(SHIM_IPCD, SHIM_IPCD_BUSY);
-
- list_item_append(&msg->list, &ipc->empty_list);
-
-out:
- spin_unlock_irq(&ipc->lock, flags);
-}
-
-int platform_ipc_init(struct ipc *ipc)
-{
- struct intel_ipc_data *iipc;
- uint32_t imrd, dir, caps, dev;
- int i;
-
- _ipc = ipc;
-
- /* init ipc data */
- iipc = rzalloc(RZONE_SYS, SOF_MEM_CAPS_RAM,
- sizeof(struct intel_ipc_data));
- ipc_set_drvdata(_ipc, iipc);
- _ipc->dsp_msg = NULL;
- list_init(&ipc->empty_list);
- list_init(&ipc->msg_list);
- spinlock_init(&ipc->lock);
-
- for (i = 0; i < MSG_QUEUE_SIZE; i++)
- list_item_prepend(&ipc->message[i].list, &ipc->empty_list);
-
- /* allocate page table buffer */
- iipc->page_table = rzalloc(RZONE_SYS, SOF_MEM_CAPS_RAM,
- PLATFORM_PAGE_TABLE_SIZE);
- if (iipc->page_table)
- bzero(iipc->page_table, PLATFORM_PAGE_TABLE_SIZE);
-
- /* request GP DMA with shared access privilege */
- caps = 0;
- dir = DMA_DIR_HMEM_TO_LMEM;
- dev = DMA_DEV_HOST;
- iipc->dmac = dma_get(dir, caps, dev, DMA_ACCESS_SHARED);
-
- /* PM */
- iipc->pm_prepare_D3 = 0;
-
- /* configure interrupt */
- interrupt_register(PLATFORM_IPC_INTERUPT, irq_handler, NULL);
- interrupt_enable(PLATFORM_IPC_INTERUPT);
-
- /* Unmask Busy and Done interrupts */
- imrd = shim_read(SHIM_IMRD);
- imrd &= ~(SHIM_IMRD_BUSY | SHIM_IMRD_DONE);
- shim_write(SHIM_IMRD, imrd);
-
- return 0;
-}
-
diff --git a/src/ipc/ipc.c b/src/ipc/ipc.c
deleted file mode 100644
index 25d4471..0000000
--- a/src/ipc/ipc.c
+++ /dev/null
@@ -1,531 +0,0 @@
-/*
- * Copyright (c) 2016, Intel Corporation
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- * * Redistributions of source code must retain the above copyright
- * notice, this list of conditions and the following disclaimer.
- * * Redistributions in binary form must reproduce the above copyright
- * notice, this list of conditions and the following disclaimer in the
- * documentation and/or other materials provided with the distribution.
- * * Neither the name of the Intel Corporation nor the
- * names of its contributors may be used to endorse or promote products
- * derived from this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
- * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
- * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
- * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
- * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
- * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
- * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
- * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
- * POSSIBILITY OF SUCH DAMAGE.
- *
- * Author: Liam Girdwood <liam.r.girdwood@linux.intel.com>
- * Keyon Jie <yang.jie@linux.intel.com>
- */
-
-#include <stdint.h>
-#include <stddef.h>
-#include <errno.h>
-#include <sof/sof.h>
-#include <sof/lock.h>
-#include <sof/list.h>
-#include <sof/stream.h>
-#include <sof/alloc.h>
-#include <sof/ipc.h>
-#include <sof/debug.h>
-#include <platform/platform.h>
-#include <sof/audio/component.h>
-#include <sof/audio/pipeline.h>
-#include <sof/audio/buffer.h>
-
-/*
- * Components, buffers and pipelines all use the same set of monotonic ID
- * numbers passed in by the host. They are stored in different lists, hence
- * more than 1 list may need to be searched for the corresponding component.
- */
-
-struct ipc_comp_dev *ipc_get_comp(struct ipc *ipc, uint32_t id)
-{
- struct ipc_comp_dev *icd;
- struct list_item *clist;
-
- list_for_item(clist, &ipc->comp_list) {
- icd = container_of(clist, struct ipc_comp_dev, list);
- switch (icd->type) {
- case COMP_TYPE_COMPONENT:
- if (icd->cd->comp.id == id)
- return icd;
- break;
- case COMP_TYPE_BUFFER:
- if (icd->cb->ipc_buffer.comp.id == id)
- return icd;
- break;
- case COMP_TYPE_PIPELINE:
- if (icd->pipeline->ipc_pipe.comp_id == id)
- return icd;
- break;
- default:
- break;
- }
- }
-
- return NULL;
-}
-
-int ipc_get_posn_offset(struct ipc *ipc, struct pipeline *pipe)
-{
- int i;
- uint32_t posn_size = sizeof(struct sof_ipc_stream_posn);
-
- for (i = 0; i < PLATFORM_MAX_STREAMS; i++) {
- if (ipc->posn_map[i] == pipe)
- return pipe->posn_offset;
- }
-
- for (i = 0; i < PLATFORM_MAX_STREAMS; i++) {
- if (ipc->posn_map[i] == NULL) {
- ipc->posn_map[i] = pipe;
- pipe->posn_offset = i * posn_size;
- return pipe->posn_offset;
- }
- }
-
- return -EINVAL;
-}
-
-int ipc_comp_new(struct ipc *ipc, struct sof_ipc_comp *comp)
-{
- struct comp_dev *cd;
- struct ipc_comp_dev *icd;
- int ret = 0;
-
- /* check whether component already exists */
- icd = ipc_get_comp(ipc, comp->id);
- if (icd != NULL) {
- trace_ipc_error("eCe");
- trace_error_value(comp->id);
- return -EINVAL;
- }
-
- /* create component */
- cd = comp_new(comp);
- if (cd == NULL) {
- trace_ipc_error("eCn");
- return -EINVAL;
- }
-
- /* allocate the IPC component container */
- icd = rzalloc(RZONE_RUNTIME, SOF_MEM_CAPS_RAM,
- sizeof(struct ipc_comp_dev));
- if (icd == NULL) {
- trace_ipc_error("eCm");
- rfree(cd);
- return -ENOMEM;
- }
- icd->cd = cd;
- icd->type = COMP_TYPE_COMPONENT;
-
- /* add new component to the list */
- list_item_append(&icd->list, &ipc->comp_list);
- return ret;
-}
-
-int ipc_comp_free(struct ipc *ipc, uint32_t comp_id)
-{
- struct ipc_comp_dev *icd;
-
- /* check whether component exists */
- icd = ipc_get_comp(ipc, comp_id);
- if (icd == NULL)
- return -ENODEV;
-
- /* free component and remove from list */
- comp_free(icd->cd);
- list_item_del(&icd->list);
- rfree(icd);
-
- return 0;
-}
-
-int ipc_buffer_new(struct ipc *ipc, struct sof_ipc_buffer *desc)
-{
- struct ipc_comp_dev *ibd;
- struct comp_buffer *buffer;
- int ret = 0;
-
- /* check whether buffer already exists */
- ibd = ipc_get_comp(ipc, desc->comp.id);
- if (ibd != NULL) {
- trace_ipc_error("eBe");
- trace_error_value(desc->comp.id);
- return -EINVAL;
- }
-
- /* register buffer with pipeline */
- buffer = buffer_new(desc);
- if (buffer == NULL) {
- trace_ipc_error("eBn");
- rfree(ibd);
- return -ENOMEM;
- }
-
- ibd = rzalloc(RZONE_RUNTIME, SOF_MEM_CAPS_RAM,
- sizeof(struct ipc_comp_dev));
- if (ibd == NULL) {
- rfree(buffer);
- return -ENOMEM;
- }
- ibd->cb = buffer;
- ibd->type = COMP_TYPE_BUFFER;
-
- /* add new buffer to the list */
- list_item_append(&ibd->list, &ipc->comp_list);
- return ret;
-}
-
-int ipc_buffer_free(struct ipc *ipc, uint32_t buffer_id)
-{
- struct ipc_comp_dev *ibd;
-
- /* check whether buffer exists */
- ibd = ipc_get_comp(ipc, buffer_id);
- if (ibd == NULL)
- return -ENODEV;
-
- /* free buffer and remove from list */
- buffer_free(ibd->cb);
- list_item_del(&ibd->list);
- rfree(ibd);
-
- return 0;
-}
-
-int ipc_comp_connect(struct ipc *ipc,
- struct sof_ipc_pipe_comp_connect *connect)
-{
- struct ipc_comp_dev *icd_source;
- struct ipc_comp_dev *icd_sink;
-
- /* check whether the components already exist */
- icd_source = ipc_get_comp(ipc, connect->source_id);
- if (icd_source == NULL) {
- trace_ipc_error("eCr");
- trace_error_value(connect->source_id);
- return -EINVAL;
- }
-
- icd_sink = ipc_get_comp(ipc, connect->sink_id);
- if (icd_sink == NULL) {
- trace_ipc_error("eCn");
- trace_error_value(connect->sink_id);
- return -EINVAL;
- }
-
- /* check source and sink types */
- if (icd_source->type == COMP_TYPE_BUFFER &&
- icd_sink->type == COMP_TYPE_COMPONENT)
- return pipeline_buffer_connect(icd_source->pipeline,
- icd_source->cb, icd_sink->cd);
- else if (icd_source->type == COMP_TYPE_COMPONENT &&
- icd_sink->type == COMP_TYPE_BUFFER)
- return pipeline_comp_connect(icd_source->pipeline,
- icd_source->cd, icd_sink->cb);
- else {
- trace_ipc_error("eCt");
- trace_error_value(connect->source_id);
- trace_error_value(connect->sink_id);
- return -EINVAL;
- }
-}
-
-
-int ipc_pipeline_new(struct ipc *ipc,
- struct sof_ipc_pipe_new *pipe_desc)
-{
- struct ipc_comp_dev *ipc_pipe;
- struct pipeline *pipe;
- struct ipc_comp_dev *icd;
-
- /* check whether the pipeline already exists */
- ipc_pipe = ipc_get_comp(ipc, pipe_desc->comp_id);
- if (ipc_pipe != NULL) {
- trace_ipc_error("ePi");
- trace_error_value(pipe_desc->comp_id);
- return -EINVAL;
- }
-
- /* find the scheduling component */
- icd = ipc_get_comp(ipc, pipe_desc->sched_id);
- if (icd == NULL) {
- trace_ipc_error("ePs");
- trace_error_value(pipe_desc->sched_id);
- return -EINVAL;
- }
- if (icd->type != COMP_TYPE_COMPONENT) {
- trace_ipc_error("ePc");
- return -EINVAL;
- }
-
- /* create the pipeline */
- pipe = pipeline_new(pipe_desc, icd->cd);
- if (pipe == NULL) {
- trace_ipc_error("ePn");
- return -ENOMEM;
- }
-
- /* allocate the IPC pipeline container */
- ipc_pipe = rzalloc(RZONE_RUNTIME, SOF_MEM_CAPS_RAM,
- sizeof(struct ipc_comp_dev));
- if (ipc_pipe == NULL) {
- pipeline_free(pipe);
- return -ENOMEM;
- }
-
- ipc_pipe->pipeline = pipe;
- ipc_pipe->type = COMP_TYPE_PIPELINE;
-
- /* add new pipeline to the list */
- list_item_append(&ipc_pipe->list, &ipc->comp_list);
- return 0;
-}
-
-int ipc_pipeline_free(struct ipc *ipc, uint32_t comp_id)
-{
- struct ipc_comp_dev *ipc_pipe;
- int ret;
-
- /* check whether pipeline exists */
- ipc_pipe = ipc_get_comp(ipc, comp_id);
- if (ipc_pipe == NULL)
- return -ENODEV;
-
- /* free buffer and remove from list */
- ret = pipeline_free(ipc_pipe->pipeline);
- if (ret < 0) {
- trace_ipc_error("ePf");
- return ret;
- }
-
- list_item_del(&ipc_pipe->list);
- rfree(ipc_pipe);
-
- return 0;
-}
-
-int ipc_pipeline_complete(struct ipc *ipc, uint32_t comp_id)
-{
- struct ipc_comp_dev *ipc_pipe;
-
- /* check whether pipeline exists */
- ipc_pipe = ipc_get_comp(ipc, comp_id);
- if (ipc_pipe == NULL)
- return -EINVAL;
-
- /* free buffer and remove from list */
- return pipeline_complete(ipc_pipe->pipeline);
-}
-
-int ipc_comp_dai_config(struct ipc *ipc, struct sof_ipc_dai_config *config)
-{
- struct sof_ipc_comp_dai *dai;
- struct ipc_comp_dev *icd;
- struct list_item *clist;
- struct comp_dev *dev;
- int ret = 0;
-
- /* for each component */
- list_for_item(clist, &ipc->comp_list) {
- icd = container_of(clist, struct ipc_comp_dev, list);
- switch (icd->type) {
- case COMP_TYPE_COMPONENT:
-
- /* make sure we only config DAI comps */
- switch (icd->cd->comp.type) {
- case SOF_COMP_DAI:
- case SOF_COMP_SG_DAI:
- dev = icd->cd;
- dai = (struct sof_ipc_comp_dai *)&dev->comp;
-
- /*
- * set config if comp dai_index matches
- * config dai_index.
- */
- if (dai->dai_index == config->dai_index &&
- dai->type == config->type) {
- ret = comp_dai_config(dev, config);
- if (ret < 0) {
- trace_ipc_error("eCD");
- return ret;
- }
- }
- break;
- default:
- break;
- }
-
- break;
- /* ignore non components */
- default:
- break;
- }
- }
-
- return ret;
-}
-
-#ifdef CONFIG_HOST_PTABLE
-/*
- * Parse the host page tables and create the audio DMA SG configuration
- * for host audio DMA buffer. This involves creating a dma_sg_elem for each
- * page table entry and adding each elem to a list in struct dma_sg_config.
- */
-int ipc_parse_page_descriptors(uint8_t *page_table,
- struct sof_ipc_host_buffer *ring,
- struct list_item *elem_list,
- uint32_t direction)
-{
- int i;
- uint32_t idx;
- uint32_t phy_addr;
- struct dma_sg_elem *e;
-
- /* the ring size may be not multiple of the page size, the last
- * page may be not full used. The used size should be in range
- * of (ring->pages - 1, ring->pages] * PAGES.
- */
- if ((ring->size <= HOST_PAGE_SIZE * (ring->pages - 1)) ||
- (ring->size > HOST_PAGE_SIZE * ring->pages)) {
- /* error buffer size */
- trace_ipc_error("eBs");
- return -EINVAL;
- }
-
- for (i = 0; i < ring->pages; i++) {
- idx = (((i << 2) + i)) >> 1;
- phy_addr = page_table[idx] | (page_table[idx + 1] << 8)
- | (page_table[idx + 2] << 16);
-
- if (i & 0x1)
- phy_addr <<= 8;
- else
- phy_addr <<= 12;
- phy_addr &= 0xfffff000;
-
- /* allocate new host DMA elem and add it to our list */
- e = rzalloc(RZONE_RUNTIME, SOF_MEM_CAPS_RAM, sizeof(*e));
- if (!e)
- return -ENOMEM;
-
- if (direction == SOF_IPC_STREAM_PLAYBACK)
- e->src = phy_addr;
- else
- e->dest = phy_addr;
-
- /* the last page may be not full used */
- if (i == (ring->pages - 1))
- e->size = ring->size - HOST_PAGE_SIZE * i;
- else
- e->size = HOST_PAGE_SIZE;
-
- list_item_append(&e->list, elem_list);
- }
-
- return 0;
-}
-
-static void dma_complete(void *data, uint32_t type, struct dma_sg_elem *next)
-{
- completion_t *complete = data;
-
- if (type == DMA_IRQ_TYPE_LLIST)
- wait_completed(complete);
-}
-
-/*
- * Copy the audio buffer page tables from the host to the DSP max of 4K.
- */
-int ipc_get_page_descriptors(struct dma *dmac, uint8_t *page_table,
- struct sof_ipc_host_buffer *ring)
-{
- struct dma_sg_config config;
- struct dma_sg_elem elem;
- completion_t complete;
- int chan;
- int ret = 0;
-
- /* get DMA channel from DMAC */
- chan = dma_channel_get(dmac, 0);
- if (chan < 0) {
- trace_ipc_error("ePC");
- return chan;
- }
-
- /* set up DMA configuration */
- config.direction = DMA_DIR_HMEM_TO_LMEM;
- config.src_width = sizeof(uint32_t);
- config.dest_width = sizeof(uint32_t);
- config.cyclic = 0;
- list_init(&config.elem_list);
-
- /* set up DMA descriptor */
- elem.dest = (uint32_t)page_table;
- elem.src = ring->phy_addr;
-
- /* source buffer size is always PAGE_SIZE bytes */
- /* 20 bits for each page, round up to 32 */
- elem.size = (ring->pages * 5 * 16 + 31) / 32;
- list_item_prepend(&elem.list, &config.elem_list);
-
- ret = dma_set_config(dmac, chan, &config);
- if (ret < 0) {
- trace_ipc_error("ePs");
- goto out;
- }
-
- /* set up callback */
- dma_set_cb(dmac, chan, DMA_IRQ_TYPE_LLIST, dma_complete, &complete);
-
- wait_init(&complete);
-
- /* start the copy of page table to DSP */
- ret = dma_start(dmac, chan);
- if (ret < 0) {
- trace_ipc_error("ePt");
- goto out;
- }
-
- /* wait for DMA to complete */
- complete.timeout = PLATFORM_HOST_DMA_TIMEOUT;
- ret = wait_for_completion_timeout(&complete);
-
- /* compressed page tables now in buffer at _ipc->page_table */
-out:
- dma_channel_put(dmac, chan);
- return ret;
-}
-#endif
-
-int ipc_init(struct sof *sof)
-{
- int i;
- trace_ipc("IPI");
-
- /* init ipc data */
- sof->ipc = rzalloc(RZONE_SYS, SOF_MEM_CAPS_RAM, sizeof(*sof->ipc));
- sof->ipc->comp_data = rzalloc(RZONE_SYS, SOF_MEM_CAPS_RAM,
- SOF_IPC_MSG_MAX_SIZE);
- sof->ipc->dmat = sof->dmat;
-
- for (i = 0; i < PLATFORM_MAX_STREAMS; i++)
- sof->ipc->posn_map[i] = NULL;
-
- list_init(&sof->ipc->comp_list);
-
- return platform_ipc_init(sof->ipc);
-}
diff --git a/src/ipc/pmc-ipc.c b/src/ipc/pmc-ipc.c
deleted file mode 100644
index 9a30555..0000000
--- a/src/ipc/pmc-ipc.c
+++ /dev/null
@@ -1,184 +0,0 @@
-/*
- * Copyright (c) 2016, Intel Corporation
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- * * Redistributions of source code must retain the above copyright
- * notice, this list of conditions and the following disclaimer.
- * * Redistributions in binary form must reproduce the above copyright
- * notice, this list of conditions and the following disclaimer in the
- * documentation and/or other materials provided with the distribution.
- * * Neither the name of the Intel Corporation nor the
- * names of its contributors may be used to endorse or promote products
- * derived from this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
- * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
- * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
- * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
- * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
- * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
- * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
- * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
- * POSSIBILITY OF SUCH DAMAGE.
- *
- * Author: Liam Girdwood <liam.r.girdwood@linux.intel.com>
- */
-
-#include <sof/debug.h>
-#include <sof/timer.h>
-#include <sof/interrupt.h>
-#include <sof/ipc.h>
-#include <sof/sof.h>
-#include <sof/alloc.h>
-#include <sof/wait.h>
-#include <sof/trace.h>
-#include <platform/interrupt.h>
-#include <platform/pmc.h>
-#include <platform/shim.h>
-
-
-
-/* private data for IPC */
-struct intel_ipc_pmc_data {
- uint32_t msg_l;
- uint32_t msg_h;
- uint32_t pending;
-};
-
-
-static struct intel_ipc_pmc_data *_pmc;
-
-static void do_cmd(void)
-{
- uint32_t ipcsc;
- uint32_t status = 0;
-
- trace_ipc("SCm");
- trace_value(_pmc->msg_l);
-
- //status = ipc_cmd();
- _pmc->pending = 0;
-
- /* clear BUSY bit and set DONE bit - accept new messages */
- ipcsc = shim_read(SHIM_IPCSCH);
- ipcsc &= ~SHIM_IPCSCH_BUSY;
- ipcsc |= SHIM_IPCSCH_DONE | status;
- shim_write(SHIM_IPCSCH, ipcsc);
-
- /* unmask busy interrupt */
- shim_write(SHIM_IMRLPESC, shim_read(SHIM_IMRLPESC) & ~SHIM_IMRLPESC_BUSY);
-}
-
-
-/* process current message */
-int pmc_process_msg_queue(void)
-{
- if (_pmc->pending)
- do_cmd();
- return 0;
-}
-
-static void do_notify(void)
-{
- trace_ipc("SNo");
-
- /* clear DONE bit */
- shim_write(SHIM_IPCLPESCH, shim_read(SHIM_IPCLPESCH) & ~SHIM_IPCLPESCH_DONE);
-
- /* unmask Done interrupt */
- shim_write(SHIM_IMRLPESC, shim_read(SHIM_IMRLPESC) & ~SHIM_IMRLPESC_DONE);
-}
-
-static void irq_handler(void *arg)
-{
- uint32_t isrlpesc;
-
- trace_ipc("SIQ");
-
- /* Interrupt arrived, check src */
- isrlpesc = shim_read(SHIM_ISRLPESC);
-
- if (isrlpesc & SHIM_ISRLPESC_DONE) {
-
- /* Mask Done interrupt before return */
- shim_write(SHIM_IMRLPESC, shim_read(SHIM_IMRLPESC) | SHIM_IMRLPESC_DONE);
- interrupt_clear(IRQ_NUM_EXT_PMC);
- do_notify();
- }
-
- if (isrlpesc & SHIM_ISRLPESC_BUSY) {
-
- /* Mask Busy interrupt before return */
- shim_write(SHIM_IMRLPESC, shim_read(SHIM_IMRLPESC) | SHIM_IMRLPESC_BUSY);
- interrupt_clear(IRQ_NUM_EXT_PMC);
-
- /* place message in Q and process later */
- _pmc->msg_l = shim_read(SHIM_IPCSCL);
- _pmc->msg_h = shim_read(SHIM_IPCSCH);
- _pmc->pending = 1;
- }
-}
-
-int ipc_pmc_send_msg(uint32_t message)
-{
- uint32_t ipclpesch;
- uint32_t irq_mask;
-
- trace_ipc("SMs");
-
- ipclpesch = shim_read(SHIM_IPCLPESCH);
-
- /* we can only send new messages if the SC is not busy */
- if (ipclpesch & SHIM_IPCLPESCH_BUSY) {
- trace_ipc_error("ePb");
- return -EAGAIN;
- }
-
- /* disable all interrupts except for SCU */
- irq_mask = arch_interrupt_disable_mask(~(1 << IRQ_NUM_EXT_PMC));
-
- /* send the new message */
- shim_write(SHIM_IPCLPESCL, 0);
- shim_write(SHIM_IPCLPESCH, SHIM_IPCLPESCH_BUSY | message);
-
- /* now wait for clock change */
- wait_for_interrupt(0);
-
- /* enable other IRQs */
- arch_interrupt_enable_mask(irq_mask);
-
- /* check status */
- ipclpesch = shim_read(SHIM_IPCLPESCH);
-
- /* did command succeed */
- if (ipclpesch & SHIM_IPCLPESCH_BUSY) {
- trace_ipc_error("ePf");
- return -EINVAL;
- }
-
- return 0;
-}
-
-int platform_ipc_pmc_init(void)
-{
- uint32_t imrlpesc;
-
- /* init ipc data */
- _pmc = rmalloc(RZONE_SYS, SOF_MEM_CAPS_RAM,
- sizeof(struct intel_ipc_pmc_data));
-
- /* configure interrupt */
- interrupt_register(IRQ_NUM_EXT_PMC, irq_handler, NULL);
- interrupt_enable(IRQ_NUM_EXT_PMC);
-
- /* Unmask Busy and Done interrupts */
- imrlpesc = shim_read(SHIM_IMRLPESC);
- imrlpesc &= ~(SHIM_IMRLPESC_BUSY | SHIM_IMRLPESC_DONE);
- shim_write(SHIM_IMRLPESC, imrlpesc);
-
- return 0;
-}
diff --git a/src/lib/Makefile.am b/src/lib/Makefile.am
deleted file mode 100644
index 7cc1830..0000000
--- a/src/lib/Makefile.am
+++ /dev/null
@@ -1,30 +0,0 @@
-noinst_LIBRARIES = libcore.a libdma.a
-
-libcore_a_SOURCES = \
- lib.c \
- alloc.c \
- work.c \
- notifier.c \
- trace.c \
- schedule.c \
- agent.c \
- interrupt.c \
- dma-trace.c \
- pm_runtime.c
-
-libcore_a_CFLAGS = \
- $(AM_CFLAGS) \
- $(ARCH_CFLAGS) \
- $(ARCH_INCDIR) \
- $(PLATFORM_INCDIR) \
- $(SOF_INCDIR)
-
-libdma_a_SOURCES = \
- dma.c
-
-libdma_a_CFLAGS = \
- $(AM_CFLAGS) \
- $(ARCH_CFLAGS) \
- $(ARCH_INCDIR) \
- $(PLATFORM_INCDIR) \
- $(SOF_INCDIR)
diff --git a/src/lib/agent.c b/src/lib/agent.c
deleted file mode 100644
index b672f23..0000000
--- a/src/lib/agent.c
+++ /dev/null
@@ -1,97 +0,0 @@
-/*
- * Copyright (c) 2017, Intel Corporation
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- * * Redistributions of source code must retain the above copyright
- * notice, this list of conditions and the following disclaimer.
- * * Redistributions in binary form must reproduce the above copyright
- * notice, this list of conditions and the following disclaimer in the
- * documentation and/or other materials provided with the distribution.
- * * Neither the name of the Intel Corporation nor the
- * names of its contributors may be used to endorse or promote products
- * derived from this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
- * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
- * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
- * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
- * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
- * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
- * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
- * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
- * POSSIBILITY OF SUCH DAMAGE.
- *
- * Author: Liam Girdwood <liam.r.girdwood@linux.intel.com>
- *
- * System Agent - Simple FW Monitor that can notify host drivers in the event
- * of any FW errors. The SA assumes that each core will enter the idle state
- * from time to time (within a period of PLATFORM_IDLE_TIME). If the core does
- * not enter the idle loop through looping forever or scheduling some work
- * continuously then the SA will emit trace and panic().
- */
-
-#include <sof/sof.h>
-#include <sof/agent.h>
-#include <sof/debug.h>
-#include <sof/panic.h>
-#include <sof/alloc.h>
-#include <sof/clock.h>
-#include <sof/trace.h>
-#include <platform/timer.h>
-#include <platform/platform.h>
-#include <platform/clk.h>
-
-#define trace_sa(__e) trace_event_atomic(TRACE_CLASS_SA, __e)
-#define trace_sa_value(__e) trace_value_atomic(__e)
-
-/*
- * Notify the SA that we are about to enter idle state (WFI).
- */
-void sa_enter_idle(struct sof *sof)
-{
- struct sa *sa = sof->sa;
-
- sa->last_idle = platform_timer_get(platform_timer);
-}
-
-static uint64_t validate(void *data, uint64_t delay)
-{
- struct sa *sa = data;
- uint64_t current;
- uint64_t delta;
-
- current = platform_timer_get(platform_timer);
- delta = current - sa->last_idle;
-
- /* were we last idle longer than timeout */
- if (delta > sa->ticks) {
- trace_sa("tim");
- trace_sa_value(delta);
- panic(SOF_IPC_PANIC_IDLE);
- }
-
- return PLATFORM_IDLE_TIME;
-}
-
-void sa_init(struct sof *sof)
-{
- struct sa *sa;
-
- trace_sa("ini");
-
- sa = rzalloc(RZONE_SYS, SOF_MEM_CAPS_RAM, sizeof(*sa));
- sof->sa = sa;
-
- /* set default tick timout */
- sa->ticks = clock_us_to_ticks(PLATFORM_WORKQ_CLOCK, PLATFORM_IDLE_TIME);
- trace_sa_value(sa->ticks);
-
- /* set lst idle time to now to give time for boot completion */
- sa->last_idle = platform_timer_get(platform_timer) + sa->ticks;
- work_init(&sa->work, validate, sa, WORK_ASYNC);
- work_schedule_default(&sa->work, PLATFORM_IDLE_TIME);
-}
diff --git a/src/lib/alloc.c b/src/lib/alloc.c
deleted file mode 100644
index 0826cc1..0000000
--- a/src/lib/alloc.c
+++ /dev/null
@@ -1,672 +0,0 @@
-/*
- * Copyright (c) 2016, Intel Corporation
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- * * Redistributions of source code must retain the above copyright
- * notice, this list of conditions and the following disclaimer.
- * * Redistributions in binary form must reproduce the above copyright
- * notice, this list of conditions and the following disclaimer in the
- * documentation and/or other materials provided with the distribution.
- * * Neither the name of the Intel Corporation nor the
- * names of its contributors may be used to endorse or promote products
- * derived from this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
- * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
- * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
- * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
- * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
- * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
- * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
- * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
- * POSSIBILITY OF SUCH DAMAGE.
- *
- * Author: Liam Girdwood <liam.r.girdwood@linux.intel.com>
- * Keyon Jie <yang.jie@linux.intel.com>
- */
-
-#include <sof/alloc.h>
-#include <sof/sof.h>
-#include <sof/debug.h>
-#include <sof/panic.h>
-#include <sof/trace.h>
-#include <sof/lock.h>
-#include <sof/cpu.h>
-#include <platform/memory.h>
-#include <stdint.h>
-
-/* debug to set memory value on every allocation */
-#define DEBUG_BLOCK_ALLOC 0
-#define DEBUG_BLOCK_ALLOC_VALUE 0x6b6b6b6b
-
-/* debug to set memory value on every free TODO: not working atm */
-#define DEBUG_BLOCK_FREE 0
-#define DEBUG_BLOCK_FREE_VALUE 0x5a5a5a5a
-
-/* memory tracing support */
-#if DEBUG_BLOCK_ALLOC || DEBUG_BLOCK_FREE
-#define trace_mem(__e) trace_event(TRACE_CLASS_MEM, __e)
-#else
-#define trace_mem(__e)
-#endif
-
-#define trace_mem_error(__e) trace_error(TRACE_CLASS_MEM, __e)
-
-extern struct mm memmap;
-
-/* We have 3 memory pools
- *
- * 1) System memory pool does not have a map and it's size is fixed at build
- * time. Memory cannot be freed from this pool. Used by device drivers
- * and any system core. Saved as part of PM context.
- * 2) Runtime memory pool has variable size allocation map and memory is freed
- * on calls to rfree(). Saved as part of PM context. Global size
- * set at build time.
- * 3) Buffer memory pool has fixed size allocation map and can be freed on
- * module removal or calls to rfree(). Saved as part of PM context.
- */
-
-
-/* total size of block */
-static inline uint32_t block_get_size(struct block_map *map)
-{
- return sizeof(*map) + map->count *
- (map->block_size + sizeof(struct block_hdr));
-}
-
-/* total size of heap */
-static inline uint32_t heap_get_size(struct mm_heap *heap)
-{
- uint32_t size = sizeof(struct mm_heap);
- int i;
-
- for (i = 0; i < heap->blocks; i++) {
- size += block_get_size(&heap->map[i]);
- }
-
- return size;
-}
-
-#if DEBUG_BLOCK_ALLOC || DEBUG_BLOCK_FREE
-static void alloc_memset_region(void *ptr, uint32_t bytes, uint32_t val)
-{
- uint32_t count = bytes >> 2;
- uint32_t *dest = ptr, i;
-
- for (i = 0; i < count; i++)
- dest[i] = val;
-}
-#endif
-
-/* allocate from system memory pool */
-static void *rmalloc_sys(size_t bytes)
-{
- void *ptr;
-
- /* system memory reserved only for master core */
- if (cpu_get_id() != PLATFORM_MASTER_CORE_ID) {
- trace_mem_error("eM0");
- return NULL;
- }
-
- ptr = (void *)memmap.system.heap;
-
- /* always succeeds or panics */
- memmap.system.heap += bytes;
- if (memmap.system.heap >= HEAP_SYSTEM_BASE + HEAP_SYSTEM_SIZE) {
- trace_mem_error("eM1");
- panic(SOF_IPC_PANIC_MEM);
- }
-
-#if DEBUG_BLOCK_ALLOC
- alloc_memset_region(ptr, bytes, DEBUG_BLOCK_ALLOC_VALUE);
-#endif
-
- return ptr;
-}
-
-/* allocate single block */
-static void *alloc_block(struct mm_heap *heap, int level,
- uint32_t caps)
-{
- struct block_map *map = &heap->map[level];
- struct block_hdr *hdr = &map->block[map->first_free];
- void *ptr;
- int i;
-
- map->free_count--;
- ptr = (void *)(map->base + map->first_free * map->block_size);
- hdr->size = 1;
- hdr->used = 1;
- heap->info.used += map->block_size;
- heap->info.free -= map->block_size;
- dcache_writeback_invalidate_region(hdr, sizeof(*hdr));
-
- /* find next free */
- for (i = map->first_free; i < map->count; ++i) {
-
- hdr = &map->block[i];
-
- if (hdr->used == 0) {
- map->first_free = i;
- break;
- }
- }
-
-#if DEBUG_BLOCK_ALLOC
- alloc_memset_region(ptr, map->block_size, DEBUG_BLOCK_ALLOC_VALUE);
-#endif
-
- dcache_writeback_invalidate_region(map, sizeof(*map));
- dcache_writeback_invalidate_region(heap, sizeof(*heap));
-
- return ptr;
-}
-
-/* allocates continuous blocks */
-static void *alloc_cont_blocks(struct mm_heap *heap, int level,
- uint32_t caps, size_t bytes)
-{
- struct block_map *map = &heap->map[level];
- struct block_hdr *hdr = &map->block[map->first_free];
- void *ptr;
- unsigned int start;
- unsigned int current;
- unsigned int count = bytes / map->block_size;
- unsigned int i;
- unsigned int remaining = map->count - count;
- unsigned int end;
-
- if (bytes % map->block_size)
- count++;
-
- /* check for continuous blocks from "start" */
- for (start = map->first_free; start < remaining; start++) {
-
- /* check that we have enough free blocks from start pos */
- end = start + count;
- for (current = start; current < end; current++) {
- hdr = &map->block[current];
-
- /* is block used */
- if (hdr->used)
- break;
- }
-
- /* enough free blocks ? */
- if (current == end)
- goto found;
- }
-
- /* not found */
- trace_mem_error("eCb");
- return NULL;
-
-found:
- /* found some free blocks */
- map->free_count -= count;
- ptr = (void *)(map->base + start * map->block_size);
- hdr = &map->block[start];
- hdr->size = count;
- heap->info.used += count * map->block_size;
- heap->info.free -= count * map->block_size;
- dcache_writeback_invalidate_region(hdr, sizeof(*hdr));
-
- /* allocate each block */
- for (current = start; current < end; current++) {
- hdr = &map->block[current];
- hdr->used = 1;
- dcache_writeback_invalidate_region(hdr, sizeof(*hdr));
- }
-
- /* do we need to find a new first free block ? */
- if (start == map->first_free) {
-
- /* find next free */
- for (i = map->first_free + count; i < map->count; ++i) {
-
- hdr = &map->block[i];
-
- if (hdr->used == 0) {
- map->first_free = i;
- break;
- }
- }
- }
-
-#if DEBUG_BLOCK_ALLOC
- alloc_memset_region(ptr, bytes, DEBUG_BLOCK_ALLOC_VALUE);
-#endif
-
- dcache_writeback_invalidate_region(map, sizeof(*map));
- dcache_writeback_invalidate_region(heap, sizeof(*heap));
-
- return ptr;
-}
-
-static struct mm_heap *get_heap_from_ptr(void *ptr)
-{
- struct mm_heap *heap;
- int i;
-
- /* find mm_heap that ptr belongs to */
- for (i = 0; i < PLATFORM_HEAP_RUNTIME; i++) {
- heap = &memmap.runtime[i];
-
- if ((uint32_t)ptr >= heap->heap &&
- (uint32_t)ptr < heap->heap + heap->size)
- return heap;
- }
-
- for (i = 0; i < PLATFORM_HEAP_BUFFER; i++) {
- heap = &memmap.buffer[i];
-
- if ((uint32_t)ptr >= heap->heap &&
- (uint32_t)ptr < heap->heap + heap->size)
- return heap;
- }
-
- return NULL;
-}
-
-static struct mm_heap *get_runtime_heap_from_caps(uint32_t caps)
-{
- struct mm_heap *heap;
- uint32_t mask;
- int i;
-
- /* find first heap that support type */
- for (i = 0; i < PLATFORM_HEAP_RUNTIME; i++) {
- heap = &memmap.runtime[i];
- mask = heap->caps & caps;
- if (mask == caps)
- return heap;
- }
-
- return NULL;
-}
-
-static struct mm_heap *get_buffer_heap_from_caps(uint32_t caps)
-{
- struct mm_heap *heap;
- uint32_t mask;
- int i;
-
- /* find first heap that support type */
- for (i = 0; i < PLATFORM_HEAP_BUFFER; i++) {
- heap = &memmap.buffer[i];
- mask = heap->caps & caps;
- if (mask == caps)
- return heap;
- }
-
- return NULL;
-}
-
-/* free block(s) */
-static void free_block(void *ptr)
-{
- struct mm_heap *heap;
- struct block_map *block_map;
- struct block_hdr *hdr;
- int i;
- int block;
-
- /* sanity check */
- if (ptr == NULL)
- return;
-
- heap = get_heap_from_ptr(ptr);
- if (heap == NULL)
- return;
-
- /* find block that ptr belongs to */
- for (i = 0; i < heap->blocks; i++) {
- block_map = &heap->map[i];
- /* is ptr in this block */
- if ((uint32_t)ptr < (block_map->base +
- (block_map->block_size * block_map->count)))
- goto found;
- }
-
- /* not found */
- trace_mem_error("eMF");
- return;
-
-found:
- /* calculate block header */
- block = ((uint32_t)ptr - block_map->base) / block_map->block_size;
- hdr = &block_map->block[block];
-
- /* free block header and continuous blocks */
- for (i = block; i < block + hdr->size; i++) {
- hdr = &block_map->block[i];
- hdr->size = 0;
- hdr->used = 0;
- block_map->free_count++;
- heap->info.used -= block_map->block_size;
- heap->info.free += block_map->block_size;
- dcache_writeback_invalidate_region(hdr, sizeof(*hdr));
- }
-
- /* set first free block */
- if (block < block_map->first_free)
- block_map->first_free = block;
-
-#if DEBUG_BLOCK_FREE
- alloc_memset_region(ptr, block_map->block_size * (i - 1), DEBUG_BLOCK_FREE_VALUE);
-#endif
-
- dcache_writeback_invalidate_region(block_map, sizeof(*block_map));
- dcache_writeback_invalidate_region(heap, sizeof(*heap));
-}
-
-/* allocate single block for runtime */
-static void *rmalloc_runtime(uint32_t caps, size_t bytes)
-{
- struct mm_heap *heap;
- int i;
-
- /* check runtime heap for capabilities */
- heap = get_runtime_heap_from_caps(caps);
- if (heap)
- goto find;
-
- /* next check buffer heap for capabilities */
- heap = get_buffer_heap_from_caps(caps);
- if (heap == NULL)
- goto error;
-
-find:
- for (i = 0; i < heap->blocks; i++) {
-
- /* is block big enough */
- if (heap->map[i].block_size < bytes)
- continue;
-
- /* does block have free space */
- if (heap->map[i].free_count == 0)
- continue;
-
- /* free block space exists */
- return alloc_block(heap, i, caps);
- }
-
-error:
- trace_mem_error("eMm");
- trace_error_value(bytes);
- trace_error_value(caps);
- return NULL;
-}
-
-void *rmalloc(int zone, uint32_t caps, size_t bytes)
-{
- uint32_t flags;
- void *ptr = NULL;
-
- spin_lock_irq(&memmap.lock, flags);
-
- switch (zone) {
- case RZONE_SYS:
- ptr = rmalloc_sys(bytes);
- break;
- case RZONE_RUNTIME:
- ptr = rmalloc_runtime(caps, bytes);
- break;
- default:
- trace_mem_error("eMz");
- break;
- }
-
- spin_unlock_irq(&memmap.lock, flags);
- return ptr;
-}
-
-void *rzalloc(int zone, uint32_t caps, size_t bytes)
-{
- void *ptr = NULL;
-
- ptr = rmalloc(zone, caps, bytes);
- if (ptr != NULL) {
- bzero(ptr, bytes);
- }
-
- return ptr;
-}
-
-/* allocates continuous buffers */
-void *rballoc(int zone, uint32_t caps, size_t bytes)
-{
- struct mm_heap *heap;
- int i;
- uint32_t flags;
- void *ptr = NULL;
-
- spin_lock_irq(&memmap.lock, flags);
-
- heap = get_buffer_heap_from_caps(caps);
- if (heap == NULL)
- goto out;
-
- /* will request fit in single block */
- for (i = 0; i < heap->blocks; i++) {
-
- /* is block big enough */
- if (heap->map[i].block_size < bytes)
- continue;
-
- /* does block have free space */
- if (heap->map[i].free_count == 0)
- continue;
-
- /* allocate block */
- ptr = alloc_block(heap, i, caps);
- goto out;
- }
-
- /* request spans > 1 block */
-
- /* only 1 choice for block size */
- if (heap->blocks == 1) {
- ptr = alloc_cont_blocks(heap, 0, caps, bytes);
- goto out;
- } else {
-
- /* find best block size for request */
- for (i = 0; i < heap->blocks; i++) {
-
- /* allocate is block size smaller than request */
- if (heap->map[i].block_size < bytes)
- alloc_cont_blocks(heap, i, caps, bytes);
- }
- }
-
- ptr = alloc_cont_blocks(heap, heap->blocks - 1, caps, bytes);
-
-out:
- spin_unlock_irq(&memmap.lock, flags);
- return ptr;
-}
-
-void rfree(void *ptr)
-{
- uint32_t flags;
-
- spin_lock_irq(&memmap.lock, flags);
- free_block(ptr);
- spin_unlock_irq(&memmap.lock, flags);
-}
-
-uint32_t mm_pm_context_size(void)
-{
- uint32_t size = 0;
- int i;
-
- /* calc context size for each area */
- for (i = 0; i < PLATFORM_HEAP_BUFFER; i++)
- size += memmap.buffer[i].info.used;
- for (i = 0; i < PLATFORM_HEAP_RUNTIME; i++)
- size += memmap.runtime[i].info.used;
- size += memmap.system.info.used;
-
- /* add memory maps */
- for (i = 0; i < PLATFORM_HEAP_BUFFER; i++)
- size += heap_get_size(&memmap.buffer[i]);
- for (i = 0; i < PLATFORM_HEAP_RUNTIME; i++)
- size += heap_get_size(&memmap.runtime[i]);
- size += heap_get_size(&memmap.system);
-
- /* recalc totals */
- memmap.total.free = memmap.system.info.free;
- memmap.total.used = memmap.system.info.used;
-
- for (i = 0; i < PLATFORM_HEAP_BUFFER; i++) {
- memmap.total.free += memmap.buffer[i].info.free;
- memmap.total.used += memmap.buffer[i].info.used;
- }
-
- for (i = 0; i < PLATFORM_HEAP_RUNTIME; i++) {
- memmap.total.free = memmap.runtime[i].info.free;
- memmap.total.used = memmap.runtime[i].info.used;
- }
-
- return size;
-}
-
-/*
- * Save the DSP memories that are in use the system and modules. All pipeline and modules
- * must be disabled before calling this functions. No allocations are permitted after
- * calling this and before calling restore.
- */
-int mm_pm_context_save(struct dma_copy *dc, struct dma_sg_config *sg)
-{
- uint32_t used;
- int32_t offset = 0;
- int32_t ret;
-
- /* first make sure SG buffer has enough space on host for DSP context */
- used = mm_pm_context_size();
- if (used > dma_sg_get_size(sg))
- return -EINVAL;
-
- /* copy memory maps to SG */
- ret = dma_copy_to_host(dc, sg, offset,
- (void *)&memmap, sizeof(memmap));
- if (ret < 0)
- return ret;
-
- /* copy system memory contents to SG */
- ret = dma_copy_to_host(dc, sg, offset + ret,
- (void *)memmap.system.heap, (int32_t)(memmap.system.size));
- if (ret < 0)
- return ret;
-
- /* copy module memory contents to SG */
- // TODO: iterate over module block map and copy contents of each block
- // to the host.
-
- /* copy buffer memory contents to SG */
- // TODO: iterate over buffer block map and copy contents of each block
- // to the host.
-
- return ret;
-}
-
-/*
- * Restore the DSP memories to modules and the system. This must be called immediately
- * after booting before any pipeline work.
- */
-int mm_pm_context_restore(struct dma_copy *dc, struct dma_sg_config *sg)
-{
- int32_t offset = 0;
- int32_t ret;
-
- /* copy memory maps from SG */
- ret = dma_copy_from_host(dc, sg, offset,
- (void *)&memmap, sizeof(memmap));
- if (ret < 0)
- return ret;
-
- /* copy system memory contents from SG */
- ret = dma_copy_to_host(dc, sg, offset + ret,
- (void *)memmap.system.heap, (int32_t)(memmap.system.size));
- if (ret < 0)
- return ret;
-
- /* copy module memory contents from SG */
- // TODO: iterate over module block map and copy contents of each block
- // to the host. This is the same block order used by the context store
-
- /* copy buffer memory contents from SG */
- // TODO: iterate over buffer block map and copy contents of each block
- // to the host. This is the same block order used by the context store
-
- return 0;
-}
-
-/* initialise map */
-void init_heap(struct sof *sof)
-{
- struct mm_heap *heap;
- struct block_map *next_map;
- struct block_map *current_map;
- int i;
- int j;
- int k;
-
- /* sanity check for malformed images or loader issues */
- if (memmap.system.heap != HEAP_SYSTEM_BASE)
- panic(SOF_IPC_PANIC_MEM);
-
- spinlock_init(&memmap.lock);
-
- /* initialise buffer map */
- for (i = 0; i < PLATFORM_HEAP_BUFFER; i++) {
- heap = &memmap.buffer[i];
-
- for (j = 0; j < heap->blocks; j++) {
-
- current_map = &heap->map[j];
- current_map->base = heap->heap;
- dcache_writeback_region(current_map,
- sizeof(*current_map));
-
- for (k = 1; k < heap->blocks; k++) {
- next_map = &heap->map[k];
- next_map->base = current_map->base +
- current_map->block_size *
- current_map->count;
- current_map = &heap->map[k];
- dcache_writeback_region(current_map,
- sizeof(*current_map));
- }
- }
- }
-
- /* initialise runtime map */
- for (i = 0; i < PLATFORM_HEAP_RUNTIME; i++) {
- heap = &memmap.runtime[i];
-
- for (j = 0; j < heap->blocks; j++) {
-
- current_map = &heap->map[j];
- current_map->base = heap->heap;
- dcache_writeback_region(current_map,
- sizeof(*current_map));
-
- for (k = 1; k < heap->blocks; k++) {
- next_map = &heap->map[k];
- next_map->base = current_map->base +
- current_map->block_size *
- current_map->count;
- current_map = &heap->map[k];
- dcache_writeback_region(current_map,
- sizeof(*current_map));
- }
- }
- }
-}
diff --git a/src/lib/dma-trace.c b/src/lib/dma-trace.c
deleted file mode 100644
index 18b09aa..0000000
--- a/src/lib/dma-trace.c
+++ /dev/null
@@ -1,441 +0,0 @@
-/*
- * Copyright (c) 2016, Intel Corporation
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- * * Redistributions of source code must retain the above copyright
- * notice, this list of conditions and the following disclaimer.
- * * Redistributions in binary form must reproduce the above copyright
- * notice, this list of conditions and the following disclaimer in the
- * documentation and/or other materials provided with the distribution.
- * * Neither the name of the Intel Corporation nor the
- * names of its contributors may be used to endorse or promote products
- * derived from this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
- * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
- * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
- * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
- * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
- * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
- * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
- * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
- * POSSIBILITY OF SUCH DAMAGE.
- *
- * Author: Yan Wang <yan.wang@linux.intel.com>
- */
-
-#include <sof/trace.h>
-#include <sof/dma-trace.h>
-#include <sof/ipc.h>
-#include <sof/sof.h>
-#include <sof/alloc.h>
-#include <arch/cache.h>
-#include <platform/timer.h>
-#include <platform/dma.h>
-#include <platform/platform.h>
-#include <sof/lock.h>
-#include <stdint.h>
-
-static struct dma_trace_data *trace_data = NULL;
-
-static int dma_trace_get_avali_data(struct dma_trace_data *d,
- struct dma_trace_buf *buffer,
- int avail);
-
-static uint64_t trace_work(void *data, uint64_t delay)
-{
- struct dma_trace_data *d = (struct dma_trace_data *)data;
- struct dma_trace_buf *buffer = &d->dmatb;
- struct dma_sg_config *config = &d->config;
- unsigned long flags;
- uint32_t avail = buffer->avail;
- int32_t size;
- uint32_t overflow;
-
- /* make sure we don't write more than buffer */
- if (avail > DMA_TRACE_LOCAL_SIZE) {
- overflow = avail - DMA_TRACE_LOCAL_SIZE;
- avail = DMA_TRACE_LOCAL_SIZE;
- } else {
- overflow = 0;
- }
-
- /* dma gateway supports wrap mode copy, but GPDMA doesn't*/
- /* support, so do it differently based on HW features */
- size = dma_trace_get_avali_data(d, buffer, avail);
-
- /* any data to copy ? */
- if (size == 0)
- return DMA_TRACE_PERIOD;
-
- d->overflow = overflow;
-
- /* DMA trace copying is working */
- d->copy_in_progress = 1;
-
- /* copy this section to host */
- size = dma_copy_to_host_nowait(&d->dc, config, d->host_offset,
- buffer->r_ptr, size);
- if (size < 0) {
- trace_buffer_error("ebb");
- goto out;
- }
-
- /* update host pointer and check for wrap */
- d->host_offset += size;
- if (d->host_offset >= d->host_size)
- d->host_offset -= d->host_size;
-
- /* update local pointer and check for wrap */
- buffer->r_ptr += size;
- if (buffer->r_ptr >= buffer->end_addr)
- buffer->r_ptr -= DMA_TRACE_LOCAL_SIZE;
-
-out:
- spin_lock_irq(&d->lock, flags);
-
- /* disregard any old messages and dont resend them if we overflow */
- if (size > 0) {
- if (d->overflow)
- buffer->avail = DMA_TRACE_LOCAL_SIZE - size;
- else
- buffer->avail -= size;
- }
-
- /* DMA trace copying is done, allow reschedule */
- d->copy_in_progress = 0;
-
- spin_unlock_irq(&d->lock, flags);
-
- /* reschedule the trace copying work */
- return DMA_TRACE_PERIOD;
-}
-
-int dma_trace_init_early(struct sof *sof)
-{
- struct dma_trace_buf *buffer;
-
- trace_data = rzalloc(RZONE_SYS, SOF_MEM_CAPS_RAM, sizeof(*trace_data));
- buffer = &trace_data->dmatb;
-
- /* allocate new buffer */
- buffer->addr = rballoc(RZONE_RUNTIME,
- SOF_MEM_CAPS_RAM | SOF_MEM_CAPS_DMA,
- DMA_TRACE_LOCAL_SIZE);
- if (buffer->addr == NULL) {
- trace_buffer_error("ebm");
- return -ENOMEM;
- }
-
- bzero(buffer->addr, DMA_TRACE_LOCAL_SIZE);
-
- /* initialise the DMA buffer */
- buffer->size = DMA_TRACE_LOCAL_SIZE;
- buffer->w_ptr = buffer->r_ptr = buffer->addr;
- buffer->end_addr = buffer->addr + buffer->size;
- buffer->avail = 0;
-
- list_init(&trace_data->config.elem_list);
- spinlock_init(&trace_data->lock);
- sof->dmat = trace_data;
-
- return 0;
-}
-
-int dma_trace_init_complete(struct dma_trace_data *d)
-{
- struct dma_trace_buf *buffer = &d->dmatb;
- int ret;
-
- trace_buffer("dtn");
-
- /* init DMA copy context */
- ret = dma_copy_new(&d->dc);
- if (ret < 0) {
- trace_buffer_error("edm");
- rfree(buffer->addr);
- return ret;
- }
-
- work_init(&d->dmat_work, trace_work, d, WORK_ASYNC);
-
- return 0;
-}
-
-int dma_trace_host_buffer(struct dma_trace_data *d, struct dma_sg_elem *elem,
- uint32_t host_size)
-{
- struct dma_sg_elem *e;
-
- /* allocate new host DMA elem and add it to our list */
- e = rzalloc(RZONE_RUNTIME, SOF_MEM_CAPS_RAM, sizeof(*e));
- if (e == NULL)
- return -ENOMEM;
-
- /* copy fields - excluding possibly non-initialized elem->src */
- e->dest = elem->dest;
- e->size = elem->size;
-
- d->host_size = host_size;
-
- list_item_append(&e->list, &d->config.elem_list);
- return 0;
-}
-
-#if defined CONFIG_DMA_GW
-
-static int dma_trace_start(struct dma_trace_data *d)
-{
- struct dma_sg_config config;
- struct dma_sg_elem *e;
- uint32_t elem_size, elem_addr, elem_num;
- int err = 0;
- int i;
-
- err = dma_copy_set_stream_tag(&d->dc, d->stream_tag);
- if (err < 0)
- return err;
-
- /* size of every trace record */
- elem_size = sizeof(uint64_t) * 2;
-
- /* Initialize address of local elem */
- elem_addr = (uint32_t)d->dmatb.addr;
-
- /* the number of elem list */
- elem_num = DMA_TRACE_LOCAL_SIZE / elem_size;
-
- config.direction = DMA_DIR_LMEM_TO_HMEM;
- config.src_width = sizeof(uint32_t);
- config.dest_width = sizeof(uint32_t);
- config.cyclic = 0;
- list_init(&config.elem_list);
-
- /* generate local elem list for local trace buffer */
- e = rzalloc(RZONE_SYS, SOF_MEM_CAPS_RAM, sizeof(*e) * elem_num);
- if (!e)
- return -ENOMEM;
-
- for (i = 0; i < elem_num; i++) {
- e[i].dest = 0;
- e[i].src = elem_addr;
- e[i].size = elem_size; /* the minimum size of DMA copy */
-
- list_item_append(&e[i].list, &config.elem_list);
- elem_addr += elem_size;
- }
-
- err = dma_set_config(d->dc.dmac, d->dc.chan, &config);
- if (err < 0) {
- rfree(e);
- return err;
- }
-
- err = dma_start(d->dc.dmac, d->dc.chan);
-
- rfree(e);
- return err;
-}
-
-static int dma_trace_get_avali_data(struct dma_trace_data *d,
- struct dma_trace_buf *buffer,
- int avail)
-{
- int size;
-
- /* there isn't DMA completion callback in GW DMA copying.
- * so we send previous position always before the next copying
- * for guaranteeing previous DMA copying is finished.
- * This function will be called once every 500ms at least even
- * if no new trace is filled.
- */
- if (d->old_host_offset != d->host_offset) {
- ipc_dma_trace_send_position();
- d->old_host_offset = d->host_offset;
- }
-
- if (avail == 0)
- return 0;
-
- /* writeback trace data */
- if (buffer->r_ptr + avail <= buffer->end_addr) {
- dcache_writeback_region((void *)buffer->r_ptr, avail);
- } else {
- size = buffer->end_addr - buffer->r_ptr + 1;
-
- /* warp case, flush tail and head of trace buffer */
- dcache_writeback_region((void *)buffer->r_ptr, size);
- dcache_writeback_region((void *)buffer->addr, avail - size);
- }
-
- return avail;
-}
-#else
-static int dma_trace_get_avali_data(struct dma_trace_data *d,
- struct dma_trace_buf *buffer,
- int avail)
-{
- uint32_t hsize;
- uint32_t lsize;
- int32_t size;
-
- /* copy to host in sections if we wrap */
- lsize = avail;
- hsize = avail;
-
- if (avail == 0)
- return 0;
-
- /* host buffer wrap ? */
- if (d->host_offset + avail > d->host_size)
- hsize = d->host_size - d->host_offset;
-
- /* local buffer wrap ? */
- if (buffer->r_ptr + avail > buffer->end_addr)
- lsize = buffer->end_addr - buffer->r_ptr;
-
- /* get smallest size */
- if (hsize < lsize)
- size = hsize;
- else
- size = lsize;
-
- /* writeback trace data */
- dcache_writeback_region((void *)buffer->r_ptr, size);
-
- return size;
-}
-#endif
-
-int dma_trace_enable(struct dma_trace_data *d)
-{
-#if defined CONFIG_DMA_GW
- int err;
-
- /*
- * GW DMA need finish DMA config and start before
- * host driver trigger start DMA
- */
- err = dma_trace_start(d);
- if (err < 0)
- return err;
-#endif
-
- /* validate DMA context */
- if (d->dc.dmac == NULL || d->dc.chan < 0) {
- trace_error_atomic(TRACE_CLASS_BUFFER, "eem");
- return -ENODEV;
- }
-
- d->enabled = 1;
- work_schedule_default(&d->dmat_work, DMA_TRACE_PERIOD);
- return 0;
-}
-
-void dma_trace_flush(void *t)
-{
- struct dma_trace_buf *buffer = &trace_data->dmatb;
- uint32_t avail = buffer->avail;
- int32_t size;
- int32_t wrap_count;
-
- /* number of bytes to flush */
- if (avail > DMA_FLUSH_TRACE_SIZE) {
- size = DMA_FLUSH_TRACE_SIZE;
- } else {
- /* check for buffer wrap */
- if (buffer->w_ptr > buffer->r_ptr)
- size = buffer->w_ptr - buffer->r_ptr;
- else
- size = buffer->end_addr - buffer->r_ptr +
- buffer->w_ptr - buffer->addr;
- }
-
- /* check for buffer wrap */
- if (buffer->w_ptr - size < buffer->addr) {
- wrap_count = buffer->w_ptr - buffer->addr;
- memcpy(t, buffer->end_addr - (size - wrap_count),
- size - wrap_count);
- memcpy(t + (size - wrap_count), buffer->addr,
- wrap_count);
- } else {
- memcpy(t, buffer->w_ptr - size, size);
- }
-
- /* writeback trace data */
- dcache_writeback_region(t, size);
-}
-
-static void dtrace_add_event(const char *e, uint32_t length)
-{
- struct dma_trace_buf *buffer = &trace_data->dmatb;
- int margin;
-
- margin = buffer->end_addr - buffer->w_ptr;
-
- /* check for buffer wrap */
- if (margin > length) {
- /* no wrap */
- memcpy(buffer->w_ptr, e, length);
- buffer->w_ptr += length;
- } else {
-
- /* data is bigger than remaining margin so we wrap */
- memcpy(buffer->w_ptr, e, margin);
- buffer->w_ptr = buffer->addr;
-
- memcpy(buffer->w_ptr, e + margin, length - margin);
- buffer->w_ptr += length - margin;
- }
-
- buffer->avail += length;
- trace_data->messages++;
-}
-
-void dtrace_event(const char *e, uint32_t length)
-{
- struct dma_trace_buf *buffer = NULL;
- unsigned long flags;
-
- if (trace_data == NULL ||
- length > DMA_TRACE_LOCAL_SIZE / 8 || length == 0)
- return;
-
- buffer = &trace_data->dmatb;
-
- spin_lock_irq(&trace_data->lock, flags);
- dtrace_add_event(e, length);
-
- /* if DMA trace copying is working */
- /* don't check if local buffer is half full */
- if (trace_data->copy_in_progress) {
- spin_unlock_irq(&trace_data->lock, flags);
- return;
- }
-
- spin_unlock_irq(&trace_data->lock, flags);
-
- /* schedule copy now if buffer > 50% full */
- if (trace_data->enabled &&
- buffer->avail >= (DMA_TRACE_LOCAL_SIZE / 2)) {
- work_reschedule_default(&trace_data->dmat_work,
- DMA_TRACE_RESCHEDULE_TIME);
- /* reschedule should not be intrrupted */
- /* just like we are in copy progress */
- trace_data->copy_in_progress = 1;
- }
-
-}
-
-void dtrace_event_atomic(const char *e, uint32_t length)
-{
- if (trace_data == NULL ||
- length > DMA_TRACE_LOCAL_SIZE / 8 || length == 0)
- return;
-
- dtrace_add_event(e, length);
-}
diff --git a/src/lib/dma.c b/src/lib/dma.c
deleted file mode 100644
index 29028f4..0000000
--- a/src/lib/dma.c
+++ /dev/null
@@ -1,89 +0,0 @@
-/*
- * Copyright (c) 2016, Intel Corporation
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- * * Redistributions of source code must retain the above copyright
- * notice, this list of conditions and the following disclaimer.
- * * Redistributions in binary form must reproduce the above copyright
- * notice, this list of conditions and the following disclaimer in the
- * documentation and/or other materials provided with the distribution.
- * * Neither the name of the Intel Corporation nor the
- * names of its contributors may be used to endorse or promote products
- * derived from this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
- * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
- * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
- * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
- * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
- * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
- * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
- * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
- * POSSIBILITY OF SUCH DAMAGE.
- *
- * Author: Ranjani Sridharan <ranjani.sridharan@linux.intel.com>
- */
-
-#include <sof/dma.h>
-#include <sof/atomic.h>
-#include <platform/dma.h>
-
-/*
- * API to request a platform DMAC.
- * Users can request DMAC based on dev type, copy direction, capabilities
- * and access privilege.
- * For exclusive access, ret DMAC with no channels draining.
- * For shared access, ret DMAC with the least number of channels draining.
- */
-
-struct dma *dma_get(uint32_t dir, uint32_t cap, uint32_t dev, uint32_t flags)
-{
- int i, ch_count;
- int min_ch_count = INT32_MAX;
- int dma_index = -1;
-
- for (i = 0; i < PLATFORM_NUM_DMACS; i++) {
-
- /* skip if this DMAC does not support the requested dir */
- if (dir && (dma[i].plat_data.dir & dir) == 0)
- continue;
-
- /* skip if this DMAC does not support the requested caps */
- if (cap && (dma[i].plat_data.caps & cap) == 0)
- continue;
-
- /* skip if this DMAC does not support the requested dev */
- if (dev && (dma[i].plat_data.devs & dev) == 0)
- continue;
-
- /* if exclusive access is requested */
- if (flags & DMA_ACCESS_EXCLUSIVE) {
-
- /* ret DMA with no channels draining */
- if (!atomic_read(&dma[i].num_channels_busy))
- return &dma[i];
- } else {
-
- /* get number of channels draining in this DMAC*/
- ch_count = atomic_read(&dma[i].num_channels_busy);
-
- /* pick DMAC with the least num of channels draining */
- if (ch_count < min_ch_count) {
- dma_index = i;
- min_ch_count = ch_count;
- }
- }
- }
-
- /* return DMAC */
- if (dma_index >= 0) {
- tracev_value(dma[dma_index].plat_data.id);
- return &dma[dma_index];
- }
-
- return NULL;
-}
diff --git a/src/lib/interrupt.c b/src/lib/interrupt.c
deleted file mode 100644
index e059c6c..0000000
--- a/src/lib/interrupt.c
+++ /dev/null
@@ -1,221 +0,0 @@
-/*
- * Copyright (c) 2017, Intel Corporation
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- * * Redistributions of source code must retain the above copyright
- * notice, this list of conditions and the following disclaimer.
- * * Redistributions in binary form must reproduce the above copyright
- * notice, this list of conditions and the following disclaimer in the
- * documentation and/or other materials provided with the distribution.
- * * Neither the name of the Intel Corporation nor the
- * names of its contributors may be used to endorse or promote products
- * derived from this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
- * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
- * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
- * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
- * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
- * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
- * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
- * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
- * POSSIBILITY OF SUCH DAMAGE.
- *
- * Author: Keyon Jie <yang.jie@linux.intel.com>
- * Liam Girdwood <liam.r.girdwood@linux.intel.com>
- *
- */
-
-#include <sof/interrupt.h>
-#include <sof/interrupt-map.h>
-#include <sof/alloc.h>
-#include <arch/interrupt.h>
-#include <platform/interrupt.h>
-#include <stdint.h>
-#include <stdlib.h>
-
-static int irq_register_child(struct irq_desc *parent, int irq,
- void (*handler)(void *arg), void *arg);
-static void irq_unregister_child(struct irq_desc *parent, int irq);
-static uint32_t irq_enable_child(struct irq_desc *parent, int irq);
-static uint32_t irq_disable_child(struct irq_desc *parent, int irq);
-
-static int irq_register_child(struct irq_desc *parent, int irq,
- void (*handler)(void *arg), void *arg)
-{
- int ret = 0;
- struct irq_desc *child;
-
- if (parent == NULL)
- return -EINVAL;
-
- spin_lock(&parent->lock);
-
- /* init child */
- child = rzalloc(RZONE_RUNTIME, SOF_MEM_CAPS_RAM,
- sizeof(struct irq_desc));
- if (!child) {
- ret = -ENOMEM;
- goto finish;
- }
-
- child->enabled_count = 0;
- child->handler = handler;
- child->handler_arg = arg;
- child->id = SOF_IRQ_ID(irq);
-
- list_item_append(&child->irq_list, &parent->child[SOF_IRQ_BIT(irq)]);
-
- /* do we need to register parent ? */
- if (parent->num_children == 0) {
- ret = arch_interrupt_register(parent->irq,
- parent->handler, parent);
- }
-
- /* increment number of children */
- parent->num_children++;
-
-finish:
- spin_unlock(&parent->lock);
- return ret;
-}
-
-static void irq_unregister_child(struct irq_desc *parent, int irq)
-{
- spin_lock(&parent->lock);
- struct irq_desc *child;
- struct list_item *clist;
-
- /* does child already exist ? */
- if (list_is_empty(&parent->child[SOF_IRQ_BIT(irq)]))
- goto finish;
-
- list_for_item(clist, &parent->child[SOF_IRQ_BIT(irq)]) {
- child = container_of(clist, struct irq_desc, irq_list);
-
- if (SOF_IRQ_ID(irq) == child->id) {
- list_item_del(&child->irq_list);
- rfree(child);
- parent->num_children--;
- }
- }
-
- /*
- * unregister the root interrupt if the this l2 is
- * the last registered one.
- */
- if (parent->num_children == 0)
- arch_interrupt_unregister(parent->irq);
-
-finish:
- spin_unlock(&parent->lock);
-}
-
-static uint32_t irq_enable_child(struct irq_desc *parent, int irq)
-{
- struct irq_desc *child;
- struct list_item *clist;
-
- spin_lock(&parent->lock);
-
- /* enable the parent interrupt */
- if (parent->enabled_count == 0)
- arch_interrupt_enable_mask(1 << SOF_IRQ_NUMBER(irq));
-
- list_for_item(clist, &parent->child[SOF_IRQ_BIT(irq)]) {
- child = container_of(clist, struct irq_desc, irq_list);
-
- if ((SOF_IRQ_ID(irq) == child->id) &&
- !child->enabled_count) {
- child->enabled_count = 1;
- parent->enabled_count++;
-
- /* enable the child interrupt */
- platform_interrupt_unmask(irq, 0);
- }
- }
-
- spin_unlock(&parent->lock);
- return 0;
-
-}
-
-static uint32_t irq_disable_child(struct irq_desc *parent, int irq)
-{
- struct irq_desc *child;
- struct list_item *clist;
-
- spin_lock(&parent->lock);
-
- list_for_item(clist, &parent->child[SOF_IRQ_BIT(irq)]) {
- child = container_of(clist, struct irq_desc, irq_list);
-
- if ((SOF_IRQ_ID(irq) == child->id) &&
- child->enabled_count) {
- child->enabled_count = 0;
- parent->enabled_count--;
- }
- }
-
- if (parent->enabled_count == 0) {
- /* disable the child interrupt */
- platform_interrupt_mask(irq, 0);
- arch_interrupt_disable_mask(1 << SOF_IRQ_NUMBER(irq));
- }
-
- spin_unlock(&parent->lock);
- return 0;
-}
-
-int interrupt_register(uint32_t irq,
- void (*handler)(void *arg), void *arg)
-{
- struct irq_desc *parent;
-
- /* no parent means we are registering DSP internal IRQ */
- parent = platform_irq_get_parent(irq);
- if (parent == NULL)
- return arch_interrupt_register(irq, handler, arg);
- else
- return irq_register_child(parent, irq, handler, arg);
-}
-
-void interrupt_unregister(uint32_t irq)
-{
- struct irq_desc *parent;
-
- /* no parent means we are unregistering DSP internal IRQ */
- parent = platform_irq_get_parent(irq);
- if (parent == NULL)
- arch_interrupt_unregister(irq);
- else
- irq_unregister_child(parent, irq);
-}
-
-uint32_t interrupt_enable(uint32_t irq)
-{
- struct irq_desc *parent;
-
- /* no parent means we are enabling DSP internal IRQ */
- parent = platform_irq_get_parent(irq);
- if (parent == NULL)
- return arch_interrupt_enable_mask(1 << irq);
- else
- return irq_enable_child(parent, irq);
-}
-
-uint32_t interrupt_disable(uint32_t irq)
-{
- struct irq_desc *parent;
-
- /* no parent means we are disabling DSP internal IRQ */
- parent = platform_irq_get_parent(irq);
- if (parent == NULL)
- return arch_interrupt_disable_mask(1 << irq);
- else
- return irq_disable_child(parent, irq);
-}
diff --git a/src/lib/lib.c b/src/lib/lib.c
deleted file mode 100644
index d5961b5..0000000
--- a/src/lib/lib.c
+++ /dev/null
@@ -1,131 +0,0 @@
-/*
- * Copyright (c) 2016, Intel Corporation
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- * * Redistributions of source code must retain the above copyright
- * notice, this list of conditions and the following disclaimer.
- * * Redistributions in binary form must reproduce the above copyright
- * notice, this list of conditions and the following disclaimer in the
- * documentation and/or other materials provided with the distribution.
- * * Neither the name of the Intel Corporation nor the
- * names of its contributors may be used to endorse or promote products
- * derived from this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
- * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
- * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
- * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
- * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
- * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
- * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
- * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
- * POSSIBILITY OF SUCH DAMAGE.
- *
- * Author: Liam Girdwood <liam.r.girdwood@linux.intel.com>
- */
-
-#include <stdint.h>
-#include <stdlib.h>
-#include <sof/sof.h>
-#include <sof/alloc.h>
-
-#if 0 // TODO: only compile if no arch memcpy is available.
-
-void cmemcpy(void *dest, void *src, size_t size)
-{
- uint32_t *d32;
- uint32_t *s32;
- uint8_t *d8;
- uint8_t *s8;
- int i;
- int d = size / 4;
- int r = size % 4;
-
- /* copy word at a time */
- d32 = dest;
- s32 = src;
- for (i = 0; i < d; i++)
- d32[i] = s32[i];
-
- /* copy remaining bytes */
- d8 = (uint8_t*) d32[i];
- s8 = (uint8_t*) s32[i];
- for (i = 0; i < r; i++)
- d8[i] = s8[i];
-}
-#endif
-
-/* used by gcc - but uses arch_memcpy internally */
-void *memcpy(void *dest, const void *src, size_t n)
-{
- arch_memcpy(dest, src, n);
- return dest;
-}
-
-/* generic bzero - TODO: can be optimsed for ARCH ? */
-void bzero(void *s, size_t n)
-{
- uint32_t *d32 = s;
- uint8_t *d8;
- int i;
- int d = n >> 2;
- int r = n % 4;
-
- /* zero word at a time */
- for (i = 0; i < d; i++)
- d32[i] = 0;
-
- /* zero remaining bytes */
- d8 = (uint8_t*) &d32[i];
- for (i = 0; i < r; i++)
- d8[i] = 0;
-}
-
-/* generic memset - TODO: can be optimsed for ARCH ? */
-void *memset(void *s, int c, size_t n)
-{
- uint8_t *d8 = s;
- uint8_t v = c;
- int i;
-
- for (i = 0; i < n; i++)
- d8[i] = v;
-
- return s;
-}
-
-/* generic strlen - TODO: can be optimsed for ARCH ? */
-int rstrlen(const char *s)
-{
- const char *p = s;
-
- while(*p++ != 0);
- return (p - s) - 1;
-}
-
-/* generic string compare */
-int rstrcmp(const char *s1, const char *s2)
-{
- while (*s1 != 0 && *s2 != 0) {
- if (*s1 < *s2)
- return -1;
- if (*s1 > *s2)
- return 1;
- s1++;
- s2++;
- }
-
- /* did both string end */
- if (*s1 != 0)
- return 1;
- if (*s2 != 0)
- return -1;
-
- /* match */
- return 0;
-}
-
diff --git a/src/lib/notifier.c b/src/lib/notifier.c
deleted file mode 100644
index 8a8068b..0000000
--- a/src/lib/notifier.c
+++ /dev/null
@@ -1,85 +0,0 @@
-/*
- * Copyright (c) 2016, Intel Corporation
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- * * Redistributions of source code must retain the above copyright
- * notice, this list of conditions and the following disclaimer.
- * * Redistributions in binary form must reproduce the above copyright
- * notice, this list of conditions and the following disclaimer in the
- * documentation and/or other materials provided with the distribution.
- * * Neither the name of the Intel Corporation nor the
- * names of its contributors may be used to endorse or promote products
- * derived from this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
- * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
- * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
- * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
- * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
- * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
- * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
- * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
- * POSSIBILITY OF SUCH DAMAGE.
- *
- * Author: Liam Girdwood <liam.r.girdwood@linux.intel.com>
- */
-
-#include <sof/notifier.h>
-#include <sof/sof.h>
-#include <sof/lock.h>
-#include <sof/list.h>
-
-/* General purpose notifiers */
-
-struct notify {
- spinlock_t lock;
- struct list_item list; /* list of notifiers */
-};
-
-static struct notify _notify;
-
-void notifier_register(struct notifier *notifier)
-{
- spin_lock(&_notify.lock);
- list_item_prepend(¬ifier->list, &_notify.list);
- spin_unlock(&_notify.lock);
-}
-
-void notifier_unregister(struct notifier *notifier)
-{
- spin_lock(&_notify.lock);
- list_item_del(¬ifier->list);
- spin_unlock(&_notify.lock);
-}
-
-void notifier_event(int id, int message, void *event_data)
-{
- struct list_item *wlist;
- struct notifier *n;
-
- spin_lock(&_notify.lock);
-
- if (list_is_empty(&_notify.list))
- goto out;
-
- /* iterate through notifiers and send event to interested clients */
- list_for_item(wlist, &_notify.list) {
-
- n = container_of(wlist, struct notifier, list);
- if (n->id == id)
- n->cb(message, n->cb_data, event_data);
- }
-
-out:
- spin_unlock(&_notify.lock);
-}
-
-void init_system_notify(struct sof *sof)
-{
- list_init(&_notify.list);
- spinlock_init(&_notify.lock);
-}
diff --git a/src/lib/pm_runtime.c b/src/lib/pm_runtime.c
deleted file mode 100644
index f4287ea..0000000
--- a/src/lib/pm_runtime.c
+++ /dev/null
@@ -1,74 +0,0 @@
-/*
- * Copyright (c) 2018, Intel Corporation
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- * * Redistributions of source code must retain the above copyright
- * notice, this list of conditions and the following disclaimer.
- * * Redistributions in binary form must reproduce the above copyright
- * notice, this list of conditions and the following disclaimer in the
- * documentation and/or other materials provided with the distribution.
- * * Neither the name of the Intel Corporation nor the
- * names of its contributors may be used to endorse or promote products
- * derived from this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
- * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
- * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
- * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
- * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
- * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
- * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
- * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
- * POSSIBILITY OF SUCH DAMAGE.
- *
- * Author: Tomasz Lauda <tomasz.lauda@linux.intel.com>
- */
-
-/**
- * \file lib/pm_runtime.c
- * \brief Runtime power management implementation
- * \author Tomasz Lauda <tomasz.lauda@linux.intel.com>
- */
-
-#include <sof/pm_runtime.h>
-#include <sof/alloc.h>
-#include <platform/pm_runtime.h>
-
-/** \brief Runtime power management data pointer. */
-static struct pm_runtime_data *prd;
-
-void pm_runtime_init(void)
-{
- trace_pm("ini");
-
- prd = rzalloc(RZONE_SYS, SOF_MEM_CAPS_RAM, sizeof(*prd));
- spinlock_init(&prd->lock);
-
- platform_pm_runtime_init(prd);
-}
-
-void pm_runtime_get(enum pm_runtime_context context)
-{
- tracev_pm("get");
-
- switch (context) {
- default:
- platform_pm_runtime_get(context);
- break;
- }
-}
-
-void pm_runtime_put(enum pm_runtime_context context)
-{
- tracev_pm("put");
-
- switch (context) {
- default:
- platform_pm_runtime_put(context);
- break;
- }
-}
diff --git a/src/lib/schedule.c b/src/lib/schedule.c
deleted file mode 100644
index e5a220c..0000000
--- a/src/lib/schedule.c
+++ /dev/null
@@ -1,418 +0,0 @@
-/*
- * Copyright (c) 2017, Intel Corporation
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- * * Redistributions of source code must retain the above copyright
- * notice, this list of conditions and the following disclaimer.
- * * Redistributions in binary form must reproduce the above copyright
- * notice, this list of conditions and the following disclaimer in the
- * documentation and/or other materials provided with the distribution.
- * * Neither the name of the Intel Corporation nor the
- * names of its contributors may be used to endorse or promote products
- * derived from this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
- * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
- * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
- * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
- * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
- * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
- * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
- * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
- * POSSIBILITY OF SUCH DAMAGE.
- *
- * Author: Liam Girdwood <liam.r.girdwood@linux.intel.com>
- */
-
-#include <stdint.h>
-#include <stddef.h>
-#include <errno.h>
-#include <sof/sof.h>
-#include <sof/lock.h>
-#include <sof/list.h>
-#include <sof/stream.h>
-#include <sof/alloc.h>
-#include <sof/debug.h>
-#include <sof/clock.h>
-#include <sof/schedule.h>
-#include <sof/work.h>
-#include <platform/timer.h>
-#include <platform/clk.h>
-#include <sof/audio/component.h>
-#include <sof/audio/pipeline.h>
-#include <sof/task.h>
-
-struct schedule_data {
- spinlock_t lock;
- struct list_item list; /* list of tasks in priority queue */
- uint32_t clock;
- struct work work;
-};
-
-#define SLOT_ALIGN_TRIES 10
-
-/*
- * Simple rescheduler to calculate tasks new start time and deadline if
- * prevoius deadline was missed. Tries to align at first with current task
- * timing, but will just add onto current if too far behind current.
- * XRUNs will be propagated upto the host if we have to reschedule.
- */
-static inline void edf_reschedule(struct task *task, uint64_t current)
-{
- uint64_t delta = (task->deadline - task->start) << 1;
- int i;
-
- /* try and align task with current scheduling slots */
- for (i = 0; i < SLOT_ALIGN_TRIES; i++) {
-
- task->start += delta;
-
- if (task->start > current + delta) {
- task->deadline = task->start + delta;
- return;
- }
- }
-
- /* task has slipped a lot, so just add delay to current */
- task->start = current + delta;
- task->deadline = task->start + delta;
-}
-
-/*
- * Find the first non running task with the earliest deadline.
- * TODO: Reduce cache invalidations by checking if the currently
- * running task AND the earliest queued task will both complete before their
- * deadlines. If so, then schedule the earlier queued task after the currently
- * running task has completed.
- */
-static inline struct task *edf_get_next(uint64_t current,
- struct task *ignore)
-{
- struct schedule_data *sch = *arch_schedule_get();
- struct task *task;
- struct task *next_task = NULL;
- struct list_item *clist;
- struct list_item *tlist;
- uint64_t next_delta = UINT64_MAX;
- uint64_t delta;
- uint64_t deadline;
- int reschedule = 0;
- uint32_t flags;
-
- spin_lock_irq(&sch->lock, flags);
-
- /* any tasks in the scheduler ? */
- if (list_is_empty(&sch->list)) {
- spin_unlock_irq(&sch->lock, flags);
- return NULL;
- }
-
- /* check every queued or running task in list */
- list_for_item_safe(clist, tlist, &sch->list) {
- task = container_of(clist, struct task, list);
-
- /* only check queued tasks */
- if (task->state != TASK_STATE_QUEUED)
- continue;
-
- /* ignore the ignored tasks */
- if (task == ignore)
- continue;
-
- /* include the length of task in deadline calc */
- deadline = task->deadline - task->max_rtime;
-
- /* get earliest deadline */
- if (current < deadline) {
- delta = deadline - current;
-
- if (delta < next_delta) {
- next_delta = delta;
- next_task = task;
- }
-
- } else {
- /* missed scheduling - will be rescheduled */
- trace_pipe("ed!");
-
- /* have we already tried to rescheule ? */
- if (reschedule++)
- edf_reschedule(task, current);
- else {
- /* reschedule failed */
- list_item_del(&task->list);
- task->state = TASK_STATE_CANCEL;
- }
- }
- }
-
- spin_unlock_irq(&sch->lock, flags);
- return next_task;
-}
-
-/* work set in the future when next task can be scheduled */
-static uint64_t sch_work(void *data, uint64_t delay)
-{
- tracev_pipe("wrk");
- schedule();
- return 0;
-}
-
-/*
- * EDF Scheduler - Earliest Deadline First Scheduler.
- *
- * Schedule task with the earliest deadline from task list.
- * Can run in IRQ context.
- */
-static struct task *schedule_edf(void)
-{
- struct task *task;
- struct task *future_task = NULL;
- uint64_t current;
-
- tracev_pipe("edf");
-
- /* get the current time */
- current = platform_timer_get(platform_timer);
-
- /* get next task to be scheduled */
- task = edf_get_next(current, NULL);
-
- interrupt_clear(PLATFORM_SCHEDULE_IRQ);
-
- /* any tasks ? */
- if (task == NULL)
- return NULL;
-
- /* can task be started now ? */
- if (task->start > current) {
- /* no, then schedule wake up */
- future_task = task;
- } else {
- /* yes, run current task */
- task->start = current;
- task->state = TASK_STATE_RUNNING;
- run_task(task);
- }
-
- /* tell caller about future task */
- return future_task;
-}
-
-#if 0 /* FIXME: is this needed ? */
-/* delete task from scheduler */
-static int schedule_task_del(struct task *task)
-{
- struct schedule_data *sch = *arch_schedule_get();
- uint32_t flags;
- int ret = 0;
-
- tracev_pipe("del");
-
- /* add task to list */
- spin_lock_irq(&sch->lock, flags);
-
- /* is task already running ? */
- if (task->state == TASK_STATE_RUNNING) {
- ret = -EAGAIN;
- goto out;
- }
-
- list_item_del(&task->list);
- task->state = TASK_STATE_COMPLETED;
-
-out:
- spin_unlock_irq(&sch->lock, flags);
- return ret;
-}
-#endif
-
-
-static int _schedule_task(struct task *task, uint64_t start, uint64_t deadline)
-{
- struct schedule_data *sch = *arch_schedule_get();
- uint32_t flags;
- uint64_t current;
-
- tracev_pipe("ad!");
-
- spin_lock_irq(&sch->lock, flags);
-
- /* is task already running ? - not enough MIPS to complete ? */
- if (task->state == TASK_STATE_RUNNING) {
- trace_pipe("tsk");
- spin_unlock_irq(&sch->lock, flags);
- return 0;
- }
-
- /* get the current time */
- current = platform_timer_get(platform_timer);
-
- /* calculate start time - TODO: include MIPS */
- if (start == 0)
- task->start = current;
- else
- task->start = task->start + clock_us_to_ticks(sch->clock, start) -
- PLATFORM_SCHEDULE_COST;
-
- /* calculate deadline - TODO: include MIPS */
- task->deadline = task->start + clock_us_to_ticks(sch->clock, deadline);
-
- /* add task to list */
- list_item_append(&task->list, &sch->list);
- task->state = TASK_STATE_QUEUED;
- spin_unlock_irq(&sch->lock, flags);
-
- return 1;
-}
-
-/*
- * Add a new task to the scheduler to be run and define a scheduling
- * deadline in time for the task to be ran. Do not invoke the scheduler
- * immediately to run task, but wait intil schedule is next called.
- *
- * deadline is in microseconds relative to start.
- */
-void schedule_task_idle(struct task *task, uint64_t deadline)
-{
- _schedule_task(task, 0, deadline);
-}
-
-/*
- * Add a new task to the scheduler to be run and define a scheduling
- * window in time for the task to be ran. i.e. task will run between start and
- * deadline times.
- *
- * start is in microseconds relative to last task start time.
- * deadline is in microseconds relative to start.
- */
-void schedule_task(struct task *task, uint64_t start, uint64_t deadline)
-{
- int need_sched;
-
- need_sched = _schedule_task(task, start, deadline);
-
- /* need to run scheduler if task not already running */
- if (need_sched) {
- /* rerun scheduler */
- schedule();
- }
-}
-
-/* Remove a task from the scheduler when complete */
-void schedule_task_complete(struct task *task)
-{
- struct schedule_data *sch = *arch_schedule_get();
- uint32_t flags;
-
- tracev_pipe("com");
-
- spin_lock_irq(&sch->lock, flags);
- list_item_del(&task->list);
- task->state = TASK_STATE_COMPLETED;
- spin_unlock_irq(&sch->lock, flags);
-}
-
-static void scheduler_run(void *unused)
-{
- struct task *future_task;
-
- tracev_pipe("run");
-
- /* EDF is only scheduler supported atm */
- future_task = schedule_edf();
- if (future_task)
- work_reschedule_default_at(&((*arch_schedule_get())->work),
- future_task->start);
-}
-
-/* run the scheduler */
-void schedule(void)
-{
- struct schedule_data *sch = *arch_schedule_get();
- struct list_item *tlist;
- struct task *task;
- uint32_t flags;
-
- tracev_pipe("sch");
-
- spin_lock_irq(&sch->lock, flags);
-
- /* make sure we have a queued task in the list first before we
- start scheduling as contexts switches are not free. */
- list_for_item(tlist, &sch->list) {
- task = container_of(tlist, struct task, list);
-
- /* schedule if we find any queued tasks */
- if (task->state == TASK_STATE_QUEUED) {
- spin_unlock_irq(&sch->lock, flags);
- goto schedule;
- }
- }
-
- /* no task to schedule */
- spin_unlock_irq(&sch->lock, flags);
- return;
-
-schedule:
- /* TODO: detect current IRQ context and call scheduler_run if both
- * current context matches scheduler context. saves a DSP context
- * switch.
- */
-
- /* the scheduler is run in IRQ context */
- interrupt_set(PLATFORM_SCHEDULE_IRQ);
-}
-
-/* Initialise the scheduler */
-int scheduler_init(struct sof *sof)
-{
- trace_pipe("ScI");
-
- struct schedule_data **sch = arch_schedule_get();
- *sch = rzalloc(RZONE_RUNTIME, SOF_MEM_CAPS_RAM, sizeof(**sch));
-
- if (!*sch)
- return -ENOMEM;
-
- list_init(&((*sch)->list));
- spinlock_init(&((*sch)->lock));
- (*sch)->clock = PLATFORM_SCHED_CLOCK;
- work_init(&((*sch)->work), sch_work, *sch, WORK_ASYNC);
-
- /* configure scheduler interrupt */
- interrupt_register(PLATFORM_SCHEDULE_IRQ, scheduler_run, NULL);
- interrupt_enable(PLATFORM_SCHEDULE_IRQ);
-
- /* allocate arch tasks */
- int tasks_result = allocate_tasks();
-
- return tasks_result;
-}
-
-/* Frees scheduler */
-void scheduler_free(void)
-{
- struct schedule_data **sch = arch_schedule_get();
- uint32_t flags;
-
- spin_lock_irq(&(*sch)->lock, flags);
-
- /* disable and unregister scheduler interrupt */
- interrupt_disable(PLATFORM_SCHEDULE_IRQ);
- interrupt_unregister(PLATFORM_SCHEDULE_IRQ);
-
- /* free arch tasks */
- arch_free_tasks();
-
- work_cancel_default(&(*sch)->work);
- list_item_del(&(*sch)->list);
-
- spin_unlock_irq(&(*sch)->lock, flags);
-
- rfree(*sch);
-}
diff --git a/src/lib/trace.c b/src/lib/trace.c
deleted file mode 100644
index 0c37858..0000000
--- a/src/lib/trace.c
+++ /dev/null
@@ -1,161 +0,0 @@
-/*
- * Copyright (c) 2016, Intel Corporation
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- * * Redistributions of source code must retain the above copyright
- * notice, this list of conditions and the following disclaimer.
- * * Redistributions in binary form must reproduce the above copyright
- * notice, this list of conditions and the following disclaimer in the
- * documentation and/or other materials provided with the distribution.
- * * Neither the name of the Intel Corporation nor the
- * names of its contributors may be used to endorse or promote products
- * derived from this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
- * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
- * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
- * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
- * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
- * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
- * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
- * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
- * POSSIBILITY OF SUCH DAMAGE.
- *
- * Author: Liam Girdwood <liam.r.girdwood@linux.intel.com>
- */
-
-#include <sof/trace.h>
-#include <sof/sof.h>
-#include <sof/alloc.h>
-#include <arch/cache.h>
-#include <platform/timer.h>
-#include <sof/lock.h>
-#include <sof/dma-trace.h>
-#include <stdint.h>
-
-struct trace {
- uint32_t pos ; /* trace position */
- uint32_t enable;
- spinlock_t lock;
-};
-
-static struct trace trace;
-
-/* send trace events only to the local trace buffer */
-void _trace_event(uint32_t event)
-{
- uint64_t dt[2];
-
- if (!trace.enable)
- return;
-
- dt[0] = platform_timer_get(platform_timer);
- dt[1] = event;
- dtrace_event((const char *)dt, sizeof(uint64_t) * 2);
-}
-
-void _trace_event_atomic(uint32_t event)
-{
- uint64_t dt[2];
-
- if (!trace.enable)
- return;
-
- dt[0] = platform_timer_get(platform_timer);
- dt[1] = event;
- dtrace_event_atomic((const char *)dt, sizeof(uint64_t) * 2);
-}
-
-/* send trace events to the local trace buffer and the mailbox */
-void _trace_event_mbox(uint32_t event)
-{
- unsigned long flags;
- uint64_t dt[2];
- uint64_t time;
-
- volatile uint64_t *t;
-
- if (!trace.enable)
- return;
-
- time = platform_timer_get(platform_timer);
-
- dt[0] = time;
- dt[1] = event;
- dtrace_event((const char *)dt, sizeof(uint64_t) * 2);
-
- /* send event by mail box too. */
- spin_lock_irq(&trace.lock, flags);
-
- /* write timestamp and event to trace buffer */
- t = (volatile uint64_t *)(MAILBOX_TRACE_BASE + trace.pos);
- trace.pos += (sizeof(uint64_t) << 1);
-
- if (trace.pos > MAILBOX_TRACE_SIZE - sizeof(uint64_t) * 2)
- trace.pos = 0;
-
- spin_unlock_irq(&trace.lock, flags);
-
- t[0] = time;
- t[1] = event;
-
- /* writeback trace data */
- dcache_writeback_region((void *)t, sizeof(uint64_t) * 2);
-}
-
-void _trace_event_mbox_atomic(uint32_t event)
-{
- volatile uint64_t *t;
- uint64_t dt[2];
- uint64_t time;
-
- if (!trace.enable)
- return;
-
- time = platform_timer_get(platform_timer);
-
- dt[0] = time;
- dt[1] = event;
- dtrace_event_atomic((const char *)dt, sizeof(uint64_t) * 2);
-
- /* write timestamp and event to trace buffer */
- t = (volatile uint64_t *)(MAILBOX_TRACE_BASE + trace.pos);
- trace.pos += (sizeof(uint64_t) << 1);
-
- if (trace.pos > MAILBOX_TRACE_SIZE - sizeof(uint64_t) * 2)
- trace.pos = 0;
-
- t[0] = time;
- t[1] = event;
-
- /* writeback trace data */
- dcache_writeback_region((void *)t, sizeof(uint64_t) * 2);
-}
-
-void trace_flush(void)
-{
- volatile uint64_t *t;
-
- /* get mailbox position */
- t = (volatile uint64_t *)(MAILBOX_TRACE_BASE + trace.pos);
-
- /* flush dma trace messages */
- dma_trace_flush((void *)t);
-}
-
-void trace_off(void)
-{
- trace.enable = 0;
-}
-
-void trace_init(struct sof *sof)
-{
- dma_trace_init_early(sof);
- trace.enable = 1;
- trace.pos = 0;
- spinlock_init(&trace.lock);
-}
diff --git a/src/lib/work.c b/src/lib/work.c
deleted file mode 100644
index af9c5a1..0000000
--- a/src/lib/work.c
+++ /dev/null
@@ -1,483 +0,0 @@
-/*
- * Copyright (c) 2016, Intel Corporation
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- * * Redistributions of source code must retain the above copyright
- * notice, this list of conditions and the following disclaimer.
- * * Redistributions in binary form must reproduce the above copyright
- * notice, this list of conditions and the following disclaimer in the
- * documentation and/or other materials provided with the distribution.
- * * Neither the name of the Intel Corporation nor the
- * names of its contributors may be used to endorse or promote products
- * derived from this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
- * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
- * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
- * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
- * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
- * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
- * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
- * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
- * POSSIBILITY OF SUCH DAMAGE.
- *
- * Author: Liam Girdwood <liam.r.girdwood@linux.intel.com>
- * Keyon Jie <yang.jie@linux.intel.com>
- */
-
-#include <sof/work.h>
-#include <sof/timer.h>
-#include <sof/list.h>
-#include <sof/clock.h>
-#include <sof/alloc.h>
-#include <sof/sof.h>
-#include <sof/lock.h>
-#include <sof/notifier.h>
-#include <sof/debug.h>
-#include <platform/clk.h>
-#include <platform/platform.h>
-#include <limits.h>
-
-/*
- * Generic delayed work queue support.
- *
- * Work can be queued to run after a microsecond timeout on either the system
- * work queue or a private work queue. It's expected most users will use the
- * system work queue as private work queues depend on available architecture
- * timers.
- *
- * The work on the system work queue should be short duration and not delay
- * any other work on this queue. If you have longer duration work (like audio
- * processing) then use a private work queue.
- *
- * The generic work queues are intended to stay in time synchronisation with
- * any CPU clock changes. i.e. timeouts will remain constant regardless of CPU
- * frequency changes.
- */
-
-struct work_queue {
- struct list_item work; /* list of work */
- uint64_t timeout; /* timeout for next queue run */
- uint32_t window_size; /* window size for pending work */
- spinlock_t lock;
- struct notifier notifier; /* notify CPU freq changes */
- struct work_queue_timesource *ts; /* time source for work queue */
- uint32_t ticks_per_usec; /* ticks per usec */
- uint32_t ticks_per_msec; /* ticks per msec */
- uint64_t run_ticks; /* ticks when last run */
-};
-
-/* generic system work queue */
-static struct work_queue *queue_;
-
-static inline int work_set_timer(struct work_queue *queue, uint64_t ticks)
-{
- int ret;
-
- ret = queue->ts->timer_set(&queue->ts->timer, ticks);
- timer_enable(&queue->ts->timer);
-
- return ret;
-}
-
-static inline void work_clear_timer(struct work_queue *queue)
-{
- queue->ts->timer_clear(&queue->ts->timer);
- timer_disable(&queue->ts->timer);
-}
-
-static inline uint64_t work_get_timer(struct work_queue *queue)
-{
- return queue->ts->timer_get(&queue->ts->timer);
-}
-
-/* is there any work pending in the current time window ? */
-static int is_work_pending(struct work_queue *queue)
-{
- struct list_item *wlist;
- struct work *work;
- uint64_t win_end;
- uint64_t win_start;
- int pending_count = 0;
-
- /* get the current valid window of work */
- win_end = work_get_timer(queue);
- win_start = win_end - queue->window_size;
-
- /* correct the pending flag window for overflow */
- if (win_end > win_start) {
-
- /* mark each valid work item in this time period as pending */
- list_for_item(wlist, &queue->work) {
-
- work = container_of(wlist, struct work, list);
-
- /* if work has timed out then mark it as pending to run */
- if (work->timeout >= win_start && work->timeout <= win_end) {
- work->pending = 1;
- pending_count++;
- } else {
- work->pending = 0;
- }
- }
- } else {
-
- /* mark each valid work item in this time period as pending */
- list_for_item(wlist, &queue->work) {
-
- work = container_of(wlist, struct work, list);
-
- /* if work has timed out then mark it as pending to run */
- if (work->timeout <= win_end ||
- (work->timeout >= win_start &&
- work->timeout < ULONG_LONG_MAX)) {
- work->pending = 1;
- pending_count++;
- } else {
- work->pending = 0;
- }
- }
- }
-
- return pending_count;
-}
-
-static inline void work_next_timeout(struct work_queue *queue,
- struct work *work, uint64_t reschedule_usecs)
-{
- /* reschedule work */
- uint64_t next_d = 0;
-
- if (reschedule_usecs % 1000)
- next_d = queue->ticks_per_usec * reschedule_usecs;
- else
- next_d = queue->ticks_per_msec * (reschedule_usecs / 1000);
-
- if (work->flags & WORK_SYNC) {
- work->timeout += next_d;
- } else {
- /* calc next run based on work request */
- work->timeout = next_d + queue->run_ticks;
- }
-}
-
-/* run all pending work */
-static void run_work(struct work_queue *queue, uint32_t *flags)
-{
- struct list_item *wlist;
- struct list_item *tlist;
- struct work *work;
- uint64_t reschedule_usecs;
- uint64_t udelay;
-
- /* check each work item in queue for pending */
- list_for_item_safe(wlist, tlist, &queue->work) {
-
- work = container_of(wlist, struct work, list);
-
- /* run work if its pending and remove from the queue */
- if (work->pending) {
-
- udelay = (work_get_timer(queue) - work->timeout) /
- queue->ticks_per_usec;
-
- /* work can run in non atomic context */
- spin_unlock_irq(&queue->lock, *flags);
- reschedule_usecs = work->cb(work->cb_data, udelay);
- spin_lock_irq(&queue->lock, *flags);
-
- /* do we need reschedule this work ? */
- if (reschedule_usecs == 0)
- list_item_del(&work->list);
- else {
- /* get next work timeout */
- work_next_timeout(queue, work, reschedule_usecs);
- }
- }
- }
-}
-
-static inline uint64_t calc_delta_ticks(uint64_t current, uint64_t work)
-{
- uint64_t max = ULONG_LONG_MAX;
-
- /* does work run in next cycle ? */
- if (work < current) {
- max -= current;
- max += work;
- return max;
- } else
- return work - current;
-}
-
-/* calculate next timeout */
-static void queue_get_next_timeout(struct work_queue *queue)
-{
- struct list_item *wlist;
- struct work *work;
- uint64_t delta = ULONG_LONG_MAX;
- uint64_t current;
- uint64_t d;
- uint64_t ticks;
-
- /* only recalc if work list not empty */
- if (list_is_empty(&queue->work)) {
- queue->timeout = 0;
- return;
- }
-
- ticks = current = work_get_timer(queue);
-
- /* find time for next work */
- list_for_item(wlist, &queue->work) {
-
- work = container_of(wlist, struct work, list);
-
- d = calc_delta_ticks(current, work->timeout);
-
- /* is work next ? */
- if (d < delta) {
- ticks = work->timeout;
- delta = d;
- }
- }
-
- queue->timeout = ticks;
-}
-
-/* re calculate timers for queue after CPU frequency change */
-static void queue_recalc_timers(struct work_queue *queue,
- struct clock_notify_data *clk_data)
-{
- struct list_item *wlist;
- struct work *work;
- uint64_t delta_ticks;
- uint64_t delta_usecs;
- uint64_t current;
-
- /* get current time */
- current = work_get_timer(queue);
-
- /* re calculate timers for each work item */
- list_for_item(wlist, &queue->work) {
-
- work = container_of(wlist, struct work, list);
-
- delta_ticks = calc_delta_ticks(current, work->timeout);
- delta_usecs = delta_ticks / clk_data->old_ticks_per_usec;
-
- /* is work within next msec, then schedule it now */
- if (delta_usecs > 0)
- work->timeout = current + queue->ticks_per_usec * delta_usecs;
- else
- work->timeout = current + (queue->ticks_per_usec >> 3);
- }
-}
-
-static void queue_reschedule(struct work_queue *queue)
-{
- queue_get_next_timeout(queue);
-
- if (queue->timeout)
- work_set_timer(queue, queue->timeout);
-}
-
-/* run the work queue */
-static void queue_run(void *data)
-{
- struct work_queue *queue = (struct work_queue *)data;
- uint32_t flags;
-
- /* clear interrupt */
- work_clear_timer(queue);
-
- spin_lock_irq(&queue->lock, flags);
-
- queue->run_ticks = work_get_timer(queue);
-
- /* work can take variable time to complete so we re-check the
- queue after running all the pending work to make sure no new work
- is pending */
- while (is_work_pending(queue))
- run_work(queue, &flags);
-
- /* re-calc timer and re-arm */
- queue_reschedule(queue);
-
- spin_unlock_irq(&queue->lock, flags);
-}
-
-/* notification of CPU frequency changes - atomic PRE and POST sequence */
-static void work_notify(int message, void *data, void *event_data)
-{
- struct work_queue *queue = (struct work_queue *)data;
- struct clock_notify_data *clk_data =
- (struct clock_notify_data *)event_data;
- uint32_t flags;
-
- spin_lock_irq(&queue->lock, flags);
-
- /* we need to re-calculate timer when CPU frequency changes */
- if (message == CLOCK_NOTIFY_POST) {
-
- /* CPU frequency update complete */
- /* scale the window size to clock speed */
- queue->ticks_per_usec = clock_us_to_ticks(queue->ts->clk, 1);
- queue->window_size =
- queue->ticks_per_usec * PLATFORM_WORKQ_WINDOW;
- queue_recalc_timers(queue, clk_data);
- queue_reschedule(queue);
- } else if (message == CLOCK_NOTIFY_PRE) {
- /* CPU frequency update pending */
- }
-
- spin_unlock_irq(&queue->lock, flags);
-}
-
-void work_schedule(struct work_queue *queue, struct work *w, uint64_t timeout)
-{
- struct work *work;
- struct list_item *wlist;
- uint32_t flags;
-
- spin_lock_irq(&queue->lock, flags);
-
- /* check to see if we are already scheduled ? */
- list_for_item(wlist, &queue->work) {
- work = container_of(wlist, struct work, list);
-
- /* keep original timeout */
- if (work == w)
- goto out;
- }
-
- /* convert timeout micro seconds to CPU clock ticks */
- if (timeout % 1000)
- w->timeout = queue->ticks_per_usec * timeout +
- work_get_timer(queue);
- else
- w->timeout = queue->ticks_per_msec * (timeout / 1000) +
- work_get_timer(queue);
-
- /* insert work into list */
- list_item_prepend(&w->list, &queue->work);
-
- /* re-calc timer and re-arm */
- queue_reschedule(queue);
-
-out:
- spin_unlock_irq(&queue->lock, flags);
-}
-
-void work_schedule_default(struct work *w, uint64_t timeout)
-{
- work_schedule(queue_, w, timeout);
-}
-
-static void reschedule(struct work_queue *queue, struct work *w, uint64_t time)
-{
- struct work *work;
- struct list_item *wlist;
- uint32_t flags;
-
- spin_lock_irq(&queue->lock, flags);
-
- /* check to see if we are already scheduled ? */
- list_for_item(wlist, &queue->work) {
- work = container_of(wlist, struct work, list);
-
- /* found it */
- if (work == w)
- goto found;
- }
-
- /* not found insert work into list */
- list_item_prepend(&w->list, &queue->work);
-
-found:
- /* re-calc timer and re-arm */
- w->timeout = time;
- queue_reschedule(queue);
-
- spin_unlock_irq(&queue->lock, flags);
-}
-
-void work_reschedule(struct work_queue *queue, struct work *w, uint64_t timeout)
-{
- uint64_t time;
-
- /* convert timeout micro seconds to CPU clock ticks */
- time = queue->ticks_per_usec * timeout + work_get_timer(queue);
-
- reschedule(queue, w, time);
-}
-
-void work_reschedule_default(struct work *w, uint64_t timeout)
-{
- uint64_t time;
-
- /* convert timeout micro seconds to CPU clock ticks */
- time = queue_->ticks_per_usec * timeout + work_get_timer(queue_);
-
- reschedule(queue_, w, time);
-}
-
-void work_reschedule_default_at(struct work *w, uint64_t time)
-{
- reschedule(queue_, w, time);
-}
-
-void work_cancel(struct work_queue *queue, struct work *w)
-{
- uint32_t flags;
-
- spin_lock_irq(&queue->lock, flags);
-
- /* remove work from list */
- list_item_del(&w->list);
-
- /* re-calc timer and re-arm */
- queue_reschedule(queue);
-
- spin_unlock_irq(&queue->lock, flags);
-}
-
-void work_cancel_default(struct work *w)
-{
- work_cancel(queue_, w);
-}
-
-struct work_queue *work_new_queue(struct work_queue_timesource *ts)
-{
- struct work_queue *queue;
-
- /* init work queue */
- queue = rmalloc(RZONE_SYS, SOF_MEM_CAPS_RAM, sizeof(*queue_));
-
- list_init(&queue->work);
- spinlock_init(&queue->lock);
- queue->ts = ts;
- queue->ticks_per_usec = clock_us_to_ticks(queue->ts->clk, 1);
- queue->ticks_per_msec = clock_ms_to_ticks(queue->ts->clk, 1);
- queue->window_size = queue->ticks_per_usec * PLATFORM_WORKQ_WINDOW;
-
- /* notification of clk changes */
- queue->notifier.cb = work_notify;
- queue->notifier.cb_data = queue;
- queue->notifier.id = ts->notifier;
- notifier_register(&queue->notifier);
-
- /* register system timer */
- timer_register(&queue->ts->timer, queue_run, queue);
-
- return queue;
-}
-
-void init_system_workq(struct work_queue_timesource *ts)
-{
- queue_ = work_new_queue(ts);
-}
diff --git a/src/library/Makefile.am b/src/library/Makefile.am
deleted file mode 100644
index 7b92e00..0000000
--- a/src/library/Makefile.am
+++ /dev/null
@@ -1 +0,0 @@
-SUBDIRS = include
diff --git a/src/library/include/Makefile.am b/src/library/include/Makefile.am
deleted file mode 100644
index 912728c..0000000
--- a/src/library/include/Makefile.am
+++ /dev/null
@@ -1 +0,0 @@
-SUBDIRS = platform
diff --git a/src/library/include/platform/Makefile.am b/src/library/include/platform/Makefile.am
deleted file mode 100644
index 5a735ae..0000000
--- a/src/library/include/platform/Makefile.am
+++ /dev/null
@@ -1,12 +0,0 @@
-includedir = $(prefix)/include/sof/platform
-
-include_HEADERS = \
- clk.h \
- dma.h \
- interrupt.h \
- mailbox.h \
- memory.h \
- platform.h \
- pmc.h \
- shim.h \
- timer.h
diff --git a/src/library/include/platform/clk.h b/src/library/include/platform/clk.h
deleted file mode 100644
index 0dd11e6..0000000
--- a/src/library/include/platform/clk.h
+++ /dev/null
@@ -1,42 +0,0 @@
-/*
- * Copyright (c) 2016, Intel Corporation
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- * * Redistributions of source code must retain the above copyright
- * notice, this list of conditions and the following disclaimer.
- * * Redistributions in binary form must reproduce the above copyright
- * notice, this list of conditions and the following disclaimer in the
- * documentation and/or other materials provided with the distribution.
- * * Neither the name of the Intel Corporation nor the
- * names of its contributors may be used to endorse or promote products
- * derived from this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
- * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
- * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
- * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
- * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
- * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
- * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
- * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
- * POSSIBILITY OF SUCH DAMAGE.
- *
- * Author: Liam Girdwood <liam.r.girdwood@linux.intel.com>
- */
-
-#ifndef __PLATFORM_HOST_CLOCK__
-#define __PLATFORM_HOST_CLOCK__
-
-#define CLK_CPU 0
-#define CLK_SSP 1
-
-#define CLK_DEFAULT_CPU_HZ 50000000
-#define CLK_MAX_CPU_HZ 343000000
-
-void init_platform_clocks(void);
-
-#endif
diff --git a/src/library/include/platform/dma.h b/src/library/include/platform/dma.h
deleted file mode 100644
index 457da8a..0000000
--- a/src/library/include/platform/dma.h
+++ /dev/null
@@ -1,42 +0,0 @@
-/*
- * Copyright (c) 2016, Intel Corporation
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- * * Redistributions of source code must retain the above copyright
- * notice, this list of conditions and the following disclaimer.
- * * Redistributions in binary form must reproduce the above copyright
- * notice, this list of conditions and the following disclaimer in the
- * documentation and/or other materials provided with the distribution.
- * * Neither the name of the Intel Corporation nor the
- * names of its contributors may be used to endorse or promote products
- * derived from this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
- * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
- * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
- * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
- * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
- * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
- * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
- * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
- * POSSIBILITY OF SUCH DAMAGE.
- *
- * Author: Liam Girdwood <liam.r.girdwood@linux.intel.com>
- */
-
-#ifndef __PLATFORM_HOST_DMA_H__
-#define __PLATFORM_HOST_DMA_H__
-
-#include <stdint.h>
-
-#define DMA_ID_DMAC0 0
-#define DMA_ID_DMAC1 1
-
-#define DMA_DEV_PCM 0
-#define DMA_DEV_WAV 1
-
-#endif
diff --git a/src/library/include/platform/interrupt.h b/src/library/include/platform/interrupt.h
deleted file mode 100644
index 9586f77..0000000
--- a/src/library/include/platform/interrupt.h
+++ /dev/null
@@ -1,78 +0,0 @@
-/*
- * Copyright (c) 2016, Intel Corporation
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- * * Redistributions of source code must retain the above copyright
- * notice, this list of conditions and the following disclaimer.
- * * Redistributions in binary form must reproduce the above copyright
- * notice, this list of conditions and the following disclaimer in the
- * documentation and/or other materials provided with the distribution.
- * * Neither the name of the Intel Corporation nor the
- * names of its contributors may be used to endorse or promote products
- * derived from this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
- * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
- * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
- * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
- * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
- * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
- * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
- * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
- * POSSIBILITY OF SUCH DAMAGE.
- *
- * Author: Liam Girdwood <liam.r.girdwood@linux.intel.com>
- */
-
-#ifndef __INCLUDE_PLATFORM_HOST_INTERRUPT__
-#define __INCLUDE_PLATFORM_HOST_INTERRUPT__
-
-#include <stdint.h>
-#include <sof/interrupt-map.h>
-
-/* IRQ numbers */
-#define IRQ_NUM_SOFTWARE0 0 /* Level 1 */
-#define IRQ_NUM_TIMER1 1 /* Level 1 */
-#define IRQ_NUM_SOFTWARE1 2 /* Level 1 */
-#define IRQ_NUM_SOFTWARE2 3 /* Level 1 */
-#define IRQ_NUM_TIMER2 5 /* Level 2 */
-#define IRQ_NUM_SOFTWARE3 6 /* Level 2 */
-#define IRQ_NUM_TIMER3 7 /* Level 3 */
-#define IRQ_NUM_SOFTWARE4 8 /* Level 3 */
-#define IRQ_NUM_SOFTWARE5 9 /* Level 3 */
-#define IRQ_NUM_EXT_IA 10 /* Level 4 */
-#define IRQ_NUM_EXT_PMC 11 /* Level 4 */
-#define IRQ_NUM_SOFTWARE6 12 /* Level 5 */
-#define IRQ_NUM_EXT_DMAC0 13 /* Level 5 */
-#define IRQ_NUM_EXT_DMAC1 14 /* Level 5 */
-#define IRQ_NUM_EXT_TIMER 15 /* Level 5 */
-#define IRQ_NUM_EXT_SSP0 16 /* Level 5 */
-#define IRQ_NUM_EXT_SSP1 17 /* Level 5 */
-#define IRQ_NUM_EXT_SSP2 18 /* Level 5 */
-#define IRQ_NUM_NMI 20 /* Level 7 */
-
-/* IRQ Masks */
-#define IRQ_MASK_SOFTWARE0 (1 << IRQ_NUM_SOFTWARE0)
-#define IRQ_MASK_TIMER1 (1 << IRQ_NUM_TIMER1)
-#define IRQ_MASK_SOFTWARE1 (1 << IRQ_NUM_SOFTWARE1)
-#define IRQ_MASK_SOFTWARE2 (1 << IRQ_NUM_SOFTWARE2)
-#define IRQ_MASK_TIMER2 (1 << IRQ_NUM_TIMER2)
-#define IRQ_MASK_SOFTWARE3 (1 << IRQ_NUM_SOFTWARE3)
-#define IRQ_MASK_TIMER3 (1 << IRQ_NUM_TIMER3)
-#define IRQ_MASK_SOFTWARE4 (1 << IRQ_NUM_SOFTWARE4)
-#define IRQ_MASK_SOFTWARE5 (1 << IRQ_NUM_SOFTWARE5)
-#define IRQ_MASK_EXT_IA (1 << IRQ_NUM_EXT_IA)
-#define IRQ_MASK_EXT_PMC (1 << IRQ_NUM_EXT_PMC)
-#define IRQ_MASK_SOFTWARE6 (1 << IRQ_NUM_SOFTWARE6)
-#define IRQ_MASK_EXT_DMAC0 (1 << IRQ_NUM_EXT_DMAC0)
-#define IRQ_MASK_EXT_DMAC1 (1 << IRQ_NUM_EXT_DMAC1)
-#define IRQ_MASK_EXT_TIMER (1 << IRQ_NUM_EXT_TIMER)
-#define IRQ_MASK_EXT_SSP0 (1 << IRQ_NUM_EXT_SSP0)
-#define IRQ_MASK_EXT_SSP1 (1 << IRQ_NUM_EXT_SSP1)
-#define IRQ_MASK_EXT_SSP2 (1 << IRQ_NUM_EXT_SSP2)
-
-#endif
diff --git a/src/library/include/platform/mailbox.h b/src/library/include/platform/mailbox.h
deleted file mode 100644
index 650ab47..0000000
--- a/src/library/include/platform/mailbox.h
+++ /dev/null
@@ -1,72 +0,0 @@
-/*
- * Copyright (c) 2016, Intel Corporation
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- * * Redistributions of source code must retain the above copyright
- * notice, this list of conditions and the following disclaimer.
- * * Redistributions in binary form must reproduce the above copyright
- * notice, this list of conditions and the following disclaimer in the
- * documentation and/or other materials provided with the distribution.
- * * Neither the name of the Intel Corporation nor the
- * names of its contributors may be used to endorse or promote products
- * derived from this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
- * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
- * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
- * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
- * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
- * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
- * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
- * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
- * POSSIBILITY OF SUCH DAMAGE.
- *
- * Author: Liam Girdwood <liam.r.girdwood@linux.intel.com>
- */
-
-#ifndef __INCLUDE_PLATFORM_HOST_MAILBOX__
-#define __INCLUDE_PLATFORM_HOST_MAILBOX__
-
-#include <platform/memory.h>
-
-#define MAILBOX_HOST_OFFSET 0x144000
-
-#define MAILBOX_OUTBOX_OFFSET 0x0
-#define MAILBOX_OUTBOX_SIZE 0x400
-#define MAILBOX_OUTBOX_BASE \
- (MAILBOX_BASE + MAILBOX_OUTBOX_OFFSET)
-
-#define MAILBOX_INBOX_OFFSET MAILBOX_OUTBOX_SIZE
-#define MAILBOX_INBOX_SIZE 0x400
-#define MAILBOX_INBOX_BASE \
- (MAILBOX_BASE + MAILBOX_INBOX_OFFSET)
-
-#define MAILBOX_EXCEPTION_OFFSET \
- (MAILBOX_INBOX_SIZE + MAILBOX_OUTBOX_SIZE)
-#define MAILBOX_EXCEPTION_SIZE 0x100
-#define MAILBOX_EXCEPTION_BASE \
- (MAILBOX_BASE + MAILBOX_EXCEPTION_OFFSET)
-
-#define MAILBOX_DEBUG_OFFSET \
- (MAILBOX_EXCEPTION_SIZE + MAILBOX_EXCEPTION_OFFSET)
-#define MAILBOX_DEBUG_SIZE 0x100
-#define MAILBOX_DEBUG_BASE \
- (MAILBOX_BASE + MAILBOX_DEBUG_OFFSET)
-
-#define MAILBOX_STREAM_OFFSET \
- (MAILBOX_DEBUG_SIZE + MAILBOX_DEBUG_OFFSET)
-#define MAILBOX_STREAM_SIZE 0x200
-#define MAILBOX_STREAM_BASE \
- (MAILBOX_BASE + MAILBOX_STREAM_OFFSET)
-
-#define MAILBOX_TRACE_OFFSET \
- (MAILBOX_STREAM_SIZE + MAILBOX_STREAM_OFFSET)
-#define MAILBOX_TRACE_SIZE 0x380
-#define MAILBOX_TRACE_BASE \
- (MAILBOX_BASE + MAILBOX_TRACE_OFFSET)
-
-#endif
diff --git a/src/library/include/platform/memory.h b/src/library/include/platform/memory.h
deleted file mode 100644
index 4e5cc70..0000000
--- a/src/library/include/platform/memory.h
+++ /dev/null
@@ -1,94 +0,0 @@
-/*
- * Copyright (c) 2016, Intel Corporation
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- * * Redistributions of source code must retain the above copyright
- * notice, this list of conditions and the following disclaimer.
- * * Redistributions in binary form must reproduce the above copyright
- * notice, this list of conditions and the following disclaimer in the
- * documentation and/or other materials provided with the distribution.
- * * Neither the name of the Intel Corporation nor the
- * names of its contributors may be used to endorse or promote products
- * derived from this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
- * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
- * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
- * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
- * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
- * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
- * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
- * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
- * POSSIBILITY OF SUCH DAMAGE.
- *
- * Author: Liam Girdwood <liam.r.girdwood@linux.intel.com>
- */
-
-#ifndef __PLATFORM_HOST_MEMORY_H__
-#define __PLATFORM_HOST_MEMORY_H__
-
-#include <config.h>
-
-#if CONFIG_HT_BAYTRAIL
-#include <baytrail/include/platform/memory.h>
-#endif
-
-#define HEAP_BUFFER_SIZE (1024 * 128)
-#define PLATFORM_HEAP_RUNTIME 1
-#define PLATFORM_HEAP_BUFFER 3
-
-#if 0
-/* physical DSP addresses */
-
-#define IRAM_BASE 0xFF2C0000
-#define IRAM_SIZE 0x00014000
-
-#define DRAM0_BASE 0xFF300000
-#define DRAM0_SIZE 0x00028000
-#define DRAM0_VBASE 0xC0000000
-
-#define MAILBOX_BASE (DRAM0_BASE + DRAM0_SIZE - 0x2000)
-
-
-/* HEAP Constants - WARNING this MUST be aligned with the linker script */
-/* TODO:preproces linker script with this header to align automatically. */
-
-/* Heap section sizes for module pool */
-#define HEAP_MOD_COUNT8 0
-#define HEAP_MOD_COUNT16 256
-#define HEAP_MOD_COUNT32 128
-#define HEAP_MOD_COUNT64 64
-#define HEAP_MOD_COUNT128 32
-#define HEAP_MOD_COUNT256 16
-#define HEAP_MOD_COUNT512 8
-#define HEAP_MOD_COUNT1024 4
-
-/* total Heap for modules - must be aligned with linker script !!! */
-#define HEAP_MOD_SIZE \
- (HEAP_MOD_COUNT8 * 8 + HEAP_MOD_COUNT16 * 16 + \
- HEAP_MOD_COUNT32 * 32 + HEAP_MOD_COUNT64 * 64 + \
- HEAP_MOD_COUNT128 * 128 + HEAP_MOD_COUNT256 * 256 + \
- HEAP_MOD_COUNT512 * 512 + HEAP_MOD_COUNT1024 * 1024)
-
-/* Heap for buffers */
-#define HEAP_BUF_BLOCK_SIZE 1024
-#define HEAP_BUF_COUNT 111
-#define HEAP_BUF_SIZE (HEAP_BUF_BLOCK_SIZE * HEAP_BUF_COUNT)
-
-/* Remaining DRAM for Stack, data and BSS.
- * TODO: verify no overflow during build
- */
-#define SYSTEM_MEM \
- (DRAM0_SIZE - HEAP_MOD_SIZE - HEAP_BUF_SIZE)
-
-#endif
-
-#define MAILBOX_DSPBOX_BASE 0
-#define MAILBOX_HOSTBOX_BASE 0
-#define MAILBOX_BASE 0
-
-#endif
diff --git a/src/library/include/platform/platform.h b/src/library/include/platform/platform.h
deleted file mode 100644
index 7801794..0000000
--- a/src/library/include/platform/platform.h
+++ /dev/null
@@ -1,60 +0,0 @@
-/*
- * Copyright (c) 2016, Intel Corporation
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- * * Redistributions of source code must retain the above copyright
- * notice, this list of conditions and the following disclaimer.
- * * Redistributions in binary form must reproduce the above copyright
- * notice, this list of conditions and the following disclaimer in the
- * documentation and/or other materials provided with the distribution.
- * * Neither the name of the Intel Corporation nor the
- * names of its contributors may be used to endorse or promote products
- * derived from this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
- * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
- * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
- * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
- * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
- * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
- * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
- * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
- * POSSIBILITY OF SUCH DAMAGE.
- *
- * Author: Liam Girdwood <liam.r.girdwood@linux.intel.com>
- * Keyon Jie <yang.jie@linux.intel.com>
- */
-
-#ifndef __PLATFORM_HOST_PLATFORM_H__
-#define __PLATFORM_HOST_PLATFORM_H__
-
-#include <platform/shim.h>
-#include <platform/interrupt.h>
-#include <stdio.h>
-#include <stdlib.h>
-
-/* Host page size */
-#define HOST_PAGE_SIZE 4096
-
-/* Platform stream capabilities */
-#define PLATFORM_MAX_CHANNELS 4
-#define PLATFORM_MAX_STREAMS 5
-
-/* DMA channel drain timeout in microseconds */
-#define PLATFORM_DMA_TIMEOUT 1333
-
-/* IPC page data copy timeout */
-#define PLATFORM_IPC_DMA_TIMEOUT 2000
-
-/* DSP default delay in cycles */
-#define PLATFORM_DEFAULT_DELAY 12
-
-static inline void platform_panic(uint32_t p) {}
-
-extern struct timer *platform_timer;
-
-#endif
diff --git a/src/library/include/platform/pmc.h b/src/library/include/platform/pmc.h
deleted file mode 100644
index d54fc1c..0000000
--- a/src/library/include/platform/pmc.h
+++ /dev/null
@@ -1,41 +0,0 @@
-/*
- * Copyright (c) 2016, Intel Corporation
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- * * Redistributions of source code must retain the above copyright
- * notice, this list of conditions and the following disclaimer.
- * * Redistributions in binary form must reproduce the above copyright
- * notice, this list of conditions and the following disclaimer in the
- * documentation and/or other materials provided with the distribution.
- * * Neither the name of the Intel Corporation nor the
- * names of its contributors may be used to endorse or promote products
- * derived from this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
- * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
- * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
- * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
- * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
- * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
- * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
- * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
- * POSSIBILITY OF SUCH DAMAGE.
- *
- * Author: Liam Girdwood <liam.r.girdwood@linux.intel.com>
- */
-
-#ifndef __PLATFORM_HOST_PMC_H__
-#define __PLATFORM_HOST_PMC_H__
-
-#include <stdint.h>
-
-
-int platform_ipc_pmc_init(void);
-int ipc_pmc_send_msg(uint32_t message);
-int pmc_process_msg_queue(void);
-
-#endif
diff --git a/src/library/include/platform/shim.h b/src/library/include/platform/shim.h
deleted file mode 100644
index d6d94d4..0000000
--- a/src/library/include/platform/shim.h
+++ /dev/null
@@ -1,40 +0,0 @@
-/*
- * Copyright (c) 2016, Intel Corporation
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- * * Redistributions of source code must retain the above copyright
- * notice, this list of conditions and the following disclaimer.
- * * Redistributions in binary form must reproduce the above copyright
- * notice, this list of conditions and the following disclaimer in the
- * documentation and/or other materials provided with the distribution.
- * * Neither the name of the Intel Corporation nor the
- * names of its contributors may be used to endorse or promote products
- * derived from this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
- * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
- * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
- * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
- * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
- * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
- * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
- * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
- * POSSIBILITY OF SUCH DAMAGE.
- *
- * Author: Liam Girdwood <liam.r.girdwood@linux.intel.com>
- */
-
-#ifndef __PLATFORM_HOST_SHIM_H__
-#define __PLATFORM_HOST_SHIM_H__
-
-#include <platform/memory.h>
-#include <stdint.h>
-
-static inline uint32_t shim_read(uint32_t reg) {return 0; }
-static inline void shim_write(uint32_t reg, uint32_t val) {}
-
-#endif
diff --git a/src/library/include/platform/timer.h b/src/library/include/platform/timer.h
deleted file mode 100644
index ca3cba2..0000000
--- a/src/library/include/platform/timer.h
+++ /dev/null
@@ -1,62 +0,0 @@
-/*
- * Copyright (c) 2016, Intel Corporation
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- * * Redistributions of source code must retain the above copyright
- * notice, this list of conditions and the following disclaimer.
- * * Redistributions in binary form must reproduce the above copyright
- * notice, this list of conditions and the following disclaimer in the
- * documentation and/or other materials provided with the distribution.
- * * Neither the name of the Intel Corporation nor the
- * names of its contributors may be used to endorse or promote products
- * derived from this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
- * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
- * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
- * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
- * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
- * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
- * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
- * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
- * POSSIBILITY OF SUCH DAMAGE.
- *
- * Author: Liam Girdwood <liam.r.girdwood@linux.intel.com>
- */
-
-
-#ifndef __PLATFORM_HOST_TIMER_H__
-#define __PLATFORM_HOST_TIMER_H__
-
-#include <stdint.h>
-#include <sof/timer.h>
-#include <platform/interrupt.h>
-
-struct comp_dev;
-struct sof_ipc_stream_posn;
-
-int platform_timer_set(struct timer *timer, uint64_t ticks);
-void platform_timer_clear(struct timer *timer);
-uint64_t platform_timer_get(struct timer *timer);
-void platform_timer_start(struct timer *timer);
-void platform_timer_stop(struct timer *timer);
-int platform_timer_register(struct timer *timer,
- void (*handler)(void *arg), void *arg);
-
-/* get timestamp for host stream DMA position */
-static inline void platform_host_timestamp(struct comp_dev *host,
- struct sof_ipc_stream_posn *posn) {}
-
-/* get timestamp for DAI stream DMA position */
-static inline void platform_dai_timestamp(struct comp_dev *dai,
- struct sof_ipc_stream_posn *posn) {}
-
-/* get current wallclock for componnent */
-static inline void platform_dai_wallclock(struct comp_dev *dai,
- uint64_t *wallclock) {}
-
-#endif
diff --git a/src/math/Makefile.am b/src/math/Makefile.am
deleted file mode 100644
index 7497c95..0000000
--- a/src/math/Makefile.am
+++ /dev/null
@@ -1,23 +0,0 @@
-if BUILD_LIB
-lib_LTLIBRARIES = libsof_math.la
-
-libsof_math_la_SOURCES = \
- trig.c \
- numbers.c
-
-libsof_math_la_CFLAGS = \
- $(AM_CFLAGS) \
- $(ARCH_CFLAGS) \
- $(COMMON_INCDIR)
-else
-noinst_LIBRARIES = libsof_math.a
-
-libsof_math_a_SOURCES = \
- trig.c \
- numbers.c
-
-libsof_math_a_CFLAGS = \
- $(AM_CFLAGS) \
- $(ARCH_CFLAGS) \
- $(COMMON_INCDIR)
-endif
diff --git a/src/math/numbers.c b/src/math/numbers.c
deleted file mode 100644
index e26e4cd..0000000
--- a/src/math/numbers.c
+++ /dev/null
@@ -1,131 +0,0 @@
-/*
- * Copyright (c) 2016, Intel Corporation
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- * * Redistributions of source code must retain the above copyright
- * notice, this list of conditions and the following disclaimer.
- * * Redistributions in binary form must reproduce the above copyright
- * notice, this list of conditions and the following disclaimer in the
- * documentation and/or other materials provided with the distribution.
- * * Neither the name of the Intel Corporation nor the
- * names of its contributors may be used to endorse or promote products
- * derived from this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
- * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
- * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
- * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
- * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
- * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
- * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
- * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
- * POSSIBILITY OF SUCH DAMAGE.
- *
- * Author: Seppo Ingalsuo <seppo.ingalsuo@linux.intel.com>
- * Liam Girdwood <liam.r.girdwood@linux.intel.com>
- * Keyon Jie <yang.jie@linux.intel.com>
- */
-
-/* Euclidean algorithm for greatest common denominator from
- * pseudocode in
- * https://en.wikipedia.org/wiki/Euclidean_algorithm#Implementations
- */
-
-#include <sof/math/numbers.h>
-#include <sof/audio/format.h>
-
-int gcd(int a, int b)
-{
- int t;
- while (b != 0) {
- t = b;
- b = a % b;
- a = t;
- }
- return a;
-}
-
-/* This function searches from vec[] (of length vec_length) integer values
- * of n. The indexes to equal values is returned in idx[]. The function
- * returns the number of found matches. The max_results should be set to
- * 0 (or negative) or vec_length get all the matches. The max_result can be set
- * to 1 to receive only the first match in ascending order. It avoids need
- * for an array for idx.
- */
-int find_equal_int16(int16_t idx[], int16_t vec[], int n, int vec_length,
- int max_results)
-{
- int nresults = 0;
- int i;
-
- for (i = 0; i < vec_length; i++) {
- if (vec[i] == n) {
- idx[nresults++] = i;
- if (nresults == max_results)
- break;
- }
- }
-
- return nresults;
-}
-
-/* Return the smallest value found in the vector */
-int16_t find_min_int16(int16_t vec[], int vec_length)
-{
- int i;
- int min = vec[0];
-
- for (i = 1; i < vec_length; i++)
- min = (vec[i] < min) ? vec[i] : min;
-
- return min;
-}
-
-/* Return the largest absolute value found in the vector. Note that
- * smallest negative value need to be saturated to preset as int32_t.
- */
-int32_t find_max_abs_int32(int32_t vec[], int vec_length)
-{
- int i;
- int64_t amax = (vec[0] > 0) ? vec[0] : -vec[0];
-
- for (i = 1; i < vec_length; i++) {
- amax = (vec[i] > amax) ? vec[i] : amax;
- amax = (-vec[i] > amax) ? -vec[i] : amax;
- }
-
- return SATP_INT32(amax); /* Amax is always a positive value */
-}
-
-/* Count the left shift amount to normalize a 32 bit signed integer value
- * without causing overflow. Input value 0 will result to 31.
- */
-int norm_int32(int32_t val)
-{
- int s;
- int32_t n;
-
- if (!val)
- return 31;
-
- if (val > 0) {
- n = val << 1;
- s = 0;
- while (n > 0) {
- n = n << 1;
- s++;
- }
- } else {
- n = val << 1;
- s = 0;
- while (n < 0) {
- n = n << 1;
- s++;
- }
- }
- return s;
-}
diff --git a/src/math/trig.c b/src/math/trig.c
deleted file mode 100644
index 47770a1..0000000
--- a/src/math/trig.c
+++ /dev/null
@@ -1,600 +0,0 @@
-/*
- * Copyright (c) 2016, Intel Corporation
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- * * Redistributions of source code must retain the above copyright
- * notice, this list of conditions and the following disclaimer.
- * * Redistributions in binary form must reproduce the above copyright
- * notice, this list of conditions and the following disclaimer in the
- * documentation and/or other materials provided with the distribution.
- * * Neither the name of the Intel Corporation nor the
- * names of its contributors may be used to endorse or promote products
- * derived from this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
- * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
- * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
- * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
- * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
- * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
- * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
- * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
- * POSSIBILITY OF SUCH DAMAGE.
- *
- * Author: Seppo Ingalsuo <seppo.ingalsuo@linux.intel.com>
- * Liam Girdwood <liam.r.girdwood@linux.intel.com>
- * Keyon Jie <yang.jie@linux.intel.com>
- */
-
-#include <stdint.h>
-#include <sof/audio/format.h>
-#include <sof/math/trig.h>
-
-
-#define SINE_C_Q20 341782638 /* 2*SINE_NQUART/pi in Q12.20 */
-#define SINE_NQUART 512 /* Must be 2^N */
-#define SINE_TABLE_SIZE (SINE_NQUART+1)
-
-/* An 1/4 period of sine wave as Q1.31 */
-const int32_t sine_table[SINE_TABLE_SIZE] = {
- 0,
- 6588387,
- 13176712,
- 19764913,
- 26352928,
- 32940695,
- 39528151,
- 46115236,
- 52701887,
- 59288042,
- 65873638,
- 72458615,
- 79042909,
- 85626460,
- 92209205,
- 98791081,
- 105372028,
- 111951983,
- 118530885,
- 125108670,
- 131685278,
- 138260647,
- 144834714,
- 151407418,
- 157978697,
- 164548489,
- 171116732,
- 177683365,
- 184248325,
- 190811551,
- 197372981,
- 203932553,
- 210490206,
- 217045877,
- 223599506,
- 230151030,
- 236700388,
- 243247517,
- 249792358,
- 256334847,
- 262874923,
- 269412525,
- 275947592,
- 282480061,
- 289009871,
- 295536961,
- 302061269,
- 308582734,
- 315101294,
- 321616889,
- 328129457,
- 334638936,
- 341145265,
- 347648383,
- 354148229,
- 360644742,
- 367137860,
- 373627523,
- 380113669,
- 386596237,
- 393075166,
- 399550396,
- 406021864,
- 412489512,
- 418953276,
- 425413098,
- 431868915,
- 438320667,
- 444768293,
- 451211734,
- 457650927,
- 464085813,
- 470516330,
- 476942419,
- 483364019,
- 489781069,
- 496193509,
- 502601279,
- 509004318,
- 515402566,
- 521795963,
- 528184448,
- 534567963,
- 540946445,
- 547319836,
- 553688076,
- 560051103,
- 566408860,
- 572761285,
- 579108319,
- 585449903,
- 591785976,
- 598116478,
- 604441351,
- 610760535,
- 617073970,
- 623381597,
- 629683357,
- 635979190,
- 642269036,
- 648552837,
- 654830534,
- 661102068,
- 667367379,
- 673626408,
- 679879097,
- 686125386,
- 692365218,
- 698598533,
- 704825272,
- 711045377,
- 717258790,
- 723465451,
- 729665303,
- 735858287,
- 742044345,
- 748223418,
- 754395449,
- 760560379,
- 766718151,
- 772868706,
- 779011986,
- 785147934,
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- 797397602,
- 803511207,
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- 815715670,
- 821806413,
- 827889421,
- 833964637,
- 840032003,
- 846091463,
- 852142959,
- 858186434,
- 864221832,
- 870249095,
- 876268167,
- 882278991,
- 888281511,
- 894275670,
- 900261412,
- 906238681,
- 912207419,
- 918167571,
- 924119082,
- 930061894,
- 935995952,
- 941921200,
- 947837582,
- 953745043,
- 959643527,
- 965532978,
- 971413341,
- 977284561,
- 983146583,
- 988999351,
- 994842809,
- 1000676905,
- 1006501581,
- 1012316784,
- 1018122458,
- 1023918549,
- 1029705003,
- 1035481765,
- 1041248781,
- 1047005996,
- 1052753356,
- 1058490807,
- 1064218296,
- 1069935767,
- 1075643168,
- 1081340445,
- 1087027543,
- 1092704410,
- 1098370992,
- 1104027236,
- 1109673088,
- 1115308496,
- 1120933406,
- 1126547765,
- 1132151521,
- 1137744620,
- 1143327011,
- 1148898640,
- 1154459455,
- 1160009404,
- 1165548435,
- 1171076495,
- 1176593532,
- 1182099495,
- 1187594332,
- 1193077990,
- 1198550419,
- 1204011566,
- 1209461381,
- 1214899812,
- 1220326808,
- 1225742318,
- 1231146290,
- 1236538675,
- 1241919421,
- 1247288477,
- 1252645793,
- 1257991319,
- 1263325005,
- 1268646799,
- 1273956652,
- 1279254515,
- 1284540337,
- 1289814068,
- 1295075658,
- 1300325059,
- 1305562221,
- 1310787095,
- 1315999631,
- 1321199780,
- 1326387493,
- 1331562722,
- 1336725418,
- 1341875532,
- 1347013016,
- 1352137822,
- 1357249900,
- 1362349204,
- 1367435684,
- 1372509294,
- 1377569985,
- 1382617710,
- 1387652421,
- 1392674071,
- 1397682613,
- 1402677999,
- 1407660183,
- 1412629117,
- 1417584755,
- 1422527050,
- 1427455956,
- 1432371426,
- 1437273414,
- 1442161874,
- 1447036759,
- 1451898025,
- 1456745625,
- 1461579513,
- 1466399644,
- 1471205973,
- 1475998455,
- 1480777044,
- 1485541695,
- 1490292364,
- 1495029005,
- 1499751575,
- 1504460029,
- 1509154322,
- 1513834410,
- 1518500249,
- 1523151796,
- 1527789006,
- 1532411836,
- 1537020243,
- 1541614182,
- 1546193612,
- 1550758488,
- 1555308767,
- 1559844407,
- 1564365366,
- 1568871600,
- 1573363067,
- 1577839726,
- 1582301533,
- 1586748446,
- 1591180425,
- 1595597427,
- 1599999410,
- 1604386334,
- 1608758157,
- 1613114837,
- 1617456334,
- 1621782607,
- 1626093615,
- 1630389318,
- 1634669675,
- 1638934646,
- 1643184190,
- 1647418268,
- 1651636840,
- 1655839867,
- 1660027308,
- 1664199124,
- 1668355276,
- 1672495724,
- 1676620431,
- 1680729357,
- 1684822463,
- 1688899710,
- 1692961061,
- 1697006478,
- 1701035921,
- 1705049354,
- 1709046738,
- 1713028036,
- 1716993211,
- 1720942224,
- 1724875039,
- 1728791619,
- 1732691927,
- 1736575926,
- 1740443580,
- 1744294852,
- 1748129706,
- 1751948106,
- 1755750016,
- 1759535401,
- 1763304223,
- 1767056449,
- 1770792043,
- 1774510970,
- 1778213194,
- 1781898680,
- 1785567395,
- 1789219304,
- 1792854372,
- 1796472564,
- 1800073848,
- 1803658188,
- 1807225552,
- 1810775906,
- 1814309215,
- 1817825448,
- 1821324571,
- 1824806551,
- 1828271355,
- 1831718951,
- 1835149305,
- 1838562387,
- 1841958164,
- 1845336603,
- 1848697673,
- 1852041343,
- 1855367580,
- 1858676354,
- 1861967633,
- 1865241387,
- 1868497585,
- 1871736195,
- 1874957188,
- 1878160534,
- 1881346201,
- 1884514160,
- 1887664382,
- 1890796836,
- 1893911493,
- 1897008324,
- 1900087300,
- 1903148391,
- 1906191569,
- 1909216806,
- 1912224072,
- 1915213339,
- 1918184580,
- 1921137766,
- 1924072870,
- 1926989863,
- 1929888719,
- 1932769410,
- 1935631909,
- 1938476189,
- 1941302224,
- 1944109986,
- 1946899450,
- 1949670588,
- 1952423376,
- 1955157787,
- 1957873795,
- 1960571374,
- 1963250500,
- 1965911147,
- 1968553291,
- 1971176905,
- 1973781966,
- 1976368449,
- 1978936330,
- 1981485584,
- 1984016188,
- 1986528117,
- 1989021349,
- 1991495859,
- 1993951624,
- 1996388621,
- 1998806828,
- 2001206221,
- 2003586778,
- 2005948477,
- 2008291295,
- 2010615209,
- 2012920200,
- 2015206244,
- 2017473320,
- 2019721407,
- 2021950483,
- 2024160528,
- 2026351521,
- 2028523441,
- 2030676268,
- 2032809981,
- 2034924561,
- 2037019987,
- 2039096240,
- 2041153301,
- 2043191149,
- 2045209766,
- 2047209132,
- 2049189230,
- 2051150040,
- 2053091543,
- 2055013722,
- 2056916559,
- 2058800035,
- 2060664132,
- 2062508835,
- 2064334123,
- 2066139982,
- 2067926393,
- 2069693341,
- 2071440807,
- 2073168776,
- 2074877232,
- 2076566159,
- 2078235539,
- 2079885359,
- 2081515602,
- 2083126253,
- 2084717297,
- 2086288719,
- 2087840504,
- 2089372637,
- 2090885104,
- 2092377891,
- 2093850984,
- 2095304369,
- 2096738031,
- 2098151959,
- 2099546138,
- 2100920555,
- 2102275198,
- 2103610053,
- 2104925108,
- 2106220351,
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- 2108751351,
- 2109987084,
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- 2112398959,
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- 2114731304,
- 2115867625,
- 2116984030,
- 2118080510,
- 2119157053,
- 2120213650,
- 2121250291,
- 2122266966,
- 2123263665,
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- 2125197099,
- 2126133816,
- 2127050521,
- 2127947205,
- 2128823861,
- 2129680479,
- 2130517051,
- 2131333571,
- 2132130029,
- 2132906419,
- 2133662733,
- 2134398965,
- 2135115106,
- 2135811152,
- 2136487094,
- 2137142926,
- 2137778643,
- 2138394239,
- 2138989707,
- 2139565042,
- 2140120239,
- 2140655292,
- 2141170196,
- 2141664947,
- 2142139540,
- 2142593970,
- 2143028233,
- 2143442325,
- 2143836243,
- 2144209981,
- 2144563538,
- 2144896909,
- 2145210091,
- 2145503082,
- 2145775879,
- 2146028479,
- 2146260880,
- 2146473079,
- 2146665075,
- 2146836865,
- 2146988449,
- 2147119824,
- 2147230990,
- 2147321945,
- 2147392689,
- 2147443221,
- 2147473541,
- 2147483647
-};
-
-/* Sine lookup table read */
-static inline int32_t sine_lookup(int idx) {
- int32_t s;
- int i1;
-
- i1 = idx & (2 * SINE_NQUART - 1);
- if (i1 > SINE_NQUART)
- i1 = 2 * SINE_NQUART - i1;
-
- if (idx > 2 * SINE_NQUART)
- s = -sine_table[i1];
- else
- s = sine_table[i1];
-
- return (s);
-}
-
-/* Compute fixed point sine with table lookup and interpolation */
-int32_t sin_fixed(int32_t w) {
- int idx;
- int32_t frac;
- int32_t s0;
- int32_t s1;
- int32_t delta;
- int64_t sine;
- int64_t idx_tmp;
-
- /* Q4.28 x Q12.20 -> Q16.48 */
- idx_tmp = (int64_t) w * SINE_C_Q20;
- idx = (int) (idx_tmp >> 48); /* Shift to Q0 */
- idx_tmp = idx_tmp >> 17; /* Shift to Q16.31 */
- idx_tmp = idx_tmp - (idx << 31); /* Get fraction */
- frac = (int32_t) idx_tmp; /* Q1.31 */
- s0 = sine_lookup(idx); /* Q1.31 */
- s1 = sine_lookup(idx + 1); /* Q1.31 */
- delta = s1 - s0; /* Q1.31 */
- //sine = (int64_t) frac*delta; /* Q1.31 x Q1.31 -> Q2.62 */
- //sine = (sine >> 31) + s0; /* Q2.31 */
- /* All Q1.31 */
- sine = s0 + q_mults_32x32(frac, delta, Q_SHIFT_BITS_64(31, 31, 31));
- return (int32_t) sine;
-}
diff --git a/src/platform/Makefile.am b/src/platform/Makefile.am
deleted file mode 100644
index 6a41c47..0000000
--- a/src/platform/Makefile.am
+++ /dev/null
@@ -1,25 +0,0 @@
-SUBDIRS = intel
-
-if BUILD_BAYTRAIL
-SUBDIRS += baytrail
-endif
-
-if BUILD_CHERRYTRAIL
-SUBDIRS += baytrail
-endif
-
-if BUILD_APOLLOLAKE
-SUBDIRS += apollolake
-endif
-
-if BUILD_HASWELL
-SUBDIRS += haswell
-endif
-
-if BUILD_BROADWELL
-SUBDIRS += haswell
-endif
-
-if BUILD_CANNONLAKE
-SUBDIRS += cannonlake
-endif
diff --git a/src/platform/apollolake/Makefile.am b/src/platform/apollolake/Makefile.am
deleted file mode 100644
index cab3db7..0000000
--- a/src/platform/apollolake/Makefile.am
+++ /dev/null
@@ -1,43 +0,0 @@
-SUBDIRS = include
-
-EXTRA_DIST = \
- apollolake.x.in \
- boot_ldr.x.in
-
-noinst_LTLIBRARIES = libplatform.la
-
-libplatform_la_LIBADD = ../intel/cavs/libcavsplatform.la
-
-libplatform_la_SOURCES = power_down.S
-
-libplatform_la_CFLAGS = \
- $(ARCH_CFLAGS) \
- $(ARCH_INCDIR) \
- $(PLATFORM_INCDIR) \
- $(SOF_INCDIR)
-
-libplatform_la_CCASFLAGS = \
- $(ARCH_INCDIR) \
- $(ASFLAGS) \
- $(ARCH_ASFLAGS) \
- $(PLATFORM_INCDIR)
-
-noinst_PROGRAMS = module boot_module
-
-module_SOURCES = \
- base_module.c
-
-module_CFLAGS = \
- $(AM_CFLAGS) \
- $(ARCH_INCDIR) \
- $(PLATFORM_INCDIR) \
- $(SOF_INCDIR)
-
-boot_module_SOURCES = \
- boot_module.c
-
-boot_module_CFLAGS = \
- $(AM_CFLAGS) \
- $(ARCH_INCDIR) \
- $(PLATFORM_INCDIR) \
- $(SOF_INCDIR)
diff --git a/src/platform/apollolake/apollolake.x.in b/src/platform/apollolake/apollolake.x.in
deleted file mode 100644
index 5802cc5..0000000
--- a/src/platform/apollolake/apollolake.x.in
+++ /dev/null
@@ -1,573 +0,0 @@
-/*
- * Linker Script for Apololake.
- *
- * This script is run through the GNU C preprocessor to align the memory
- * offsets with headers.
- *
- * Use spaces for formatting as cpp ignore tab sizes.
- */
-
-#include <platform/memory.h>
-#include <xtensa/config/core-isa.h>
-
-OUTPUT_ARCH(xtensa)
-
-MEMORY
-{
- vector_memory_lit :
- org = XCHAL_MEMERROR_VECTOR_PADDR + SOF_MEM_ERROR_LIT_SIZE,
- len = SOF_MEM_ERROR_LIT_SIZE
- vector_memory_text :
- org = XCHAL_MEMERROR_VECTOR_PADDR,
- len = SOF_MEM_ERROR_TEXT_SIZE
- vector_base_text :
- org = SOF_MEM_VECBASE,
- len = SOF_MEM_VECBASE_LIT_SIZE
- vector_int2_lit :
- org = SOF_MEM_VECBASE + XCHAL_INTLEVEL2_VECOFS - SOF_MEM_VECT_LIT_SIZE,
- len = SOF_MEM_VECT_LIT_SIZE
- vector_int2_text :
- org = SOF_MEM_VECBASE + XCHAL_INTLEVEL2_VECOFS,
- len = SOF_MEM_VECT_TEXT_SIZE
- vector_int3_lit :
- org = SOF_MEM_VECBASE + XCHAL_INTLEVEL3_VECOFS - SOF_MEM_VECT_LIT_SIZE,
- len = SOF_MEM_VECT_LIT_SIZE
- vector_int3_text :
- org = SOF_MEM_VECBASE + XCHAL_INTLEVEL3_VECOFS,
- len = SOF_MEM_VECT_TEXT_SIZE
- vector_int4_lit :
- org = SOF_MEM_VECBASE + XCHAL_INTLEVEL4_VECOFS - SOF_MEM_VECT_LIT_SIZE,
- len = SOF_MEM_VECT_LIT_SIZE
- vector_int4_text :
- org = SOF_MEM_VECBASE + XCHAL_INTLEVEL4_VECOFS,
- len = SOF_MEM_VECT_TEXT_SIZE
- vector_int5_lit :
- org = SOF_MEM_VECBASE + XCHAL_INTLEVEL5_VECOFS - SOF_MEM_VECT_LIT_SIZE,
- len = SOF_MEM_VECT_LIT_SIZE
- vector_int5_text :
- org = SOF_MEM_VECBASE + XCHAL_INTLEVEL5_VECOFS,
- len = SOF_MEM_VECT_TEXT_SIZE
- vector_int6_lit :
- org = SOF_MEM_VECBASE + XCHAL_INTLEVEL6_VECOFS - SOF_MEM_VECT_LIT_SIZE,
- len = SOF_MEM_VECT_LIT_SIZE
- vector_int6_text :
- org = SOF_MEM_VECBASE + XCHAL_INTLEVEL6_VECOFS,
- len = SOF_MEM_VECT_TEXT_SIZE
- vector_int7_lit :
- org = SOF_MEM_VECBASE + XCHAL_INTLEVEL7_VECOFS - SOF_MEM_VECT_LIT_SIZE,
- len = SOF_MEM_VECT_LIT_SIZE
- vector_int7_text :
- org = SOF_MEM_VECBASE + XCHAL_INTLEVEL7_VECOFS,
- len = SOF_MEM_VECT_TEXT_SIZE
- vector_kernel_lit :
- org = SOF_MEM_VECBASE + XCHAL_KERNEL_VECOFS - SOF_MEM_VECT_LIT_SIZE,
- len = SOF_MEM_VECT_LIT_SIZE
- vector_kernel_text :
- org = SOF_MEM_VECBASE + XCHAL_KERNEL_VECOFS,
- len = SOF_MEM_VECT_TEXT_SIZE
- vector_user_lit :
- org = SOF_MEM_VECBASE + XCHAL_USER_VECOFS - SOF_MEM_VECT_LIT_SIZE,
- len = SOF_MEM_VECT_LIT_SIZE
- vector_user_text :
- org = SOF_MEM_VECBASE + XCHAL_USER_VECOFS,
- len = SOF_MEM_VECT_TEXT_SIZE
- vector_double_lit :
- org = SOF_MEM_VECBASE + XCHAL_DOUBLEEXC_VECOFS - SOF_MEM_VECT_LIT_SIZE,
- len = SOF_MEM_VECT_LIT_SIZE
- vector_double_text :
- org = SOF_MEM_VECBASE + XCHAL_DOUBLEEXC_VECOFS,
- len = SOF_MEM_VECT_TEXT_SIZE
- sof_text :
- org = SOF_TEXT_BASE,
- len = SOF_TEXT_SIZE,
- sof_data :
- org = SOF_TEXT_BASE + SOF_TEXT_SIZE,
- len = SOF_DATA_SIZE
- sof_bss_data :
- org = SOF_TEXT_BASE + SOF_TEXT_SIZE + SOF_DATA_SIZE,
- len = SOF_BSS_DATA_SIZE
- system_heap :
- org = HEAP_SYSTEM_BASE,
- len = HEAP_SYSTEM_SIZE
- runtime_heap :
- org = HEAP_RUNTIME_BASE,
- len = HEAP_RUNTIME_SIZE
- buffer_heap :
- org = HEAP_BUFFER_BASE,
- len = HEAP_BUFFER_SIZE
- sof_stack :
- org = SOF_STACK_END,
- len = SOF_STACK_BASE - SOF_STACK_END
- buffer_hp_heap :
- org = HEAP_HP_BUFFER_BASE,
- len = HEAP_HP_BUFFER_SIZE
- wnd0 :
- org = HP_SRAM_WIN0_BASE,
- len = HP_SRAM_WIN0_SIZE
- wnd1 :
- org = HP_SRAM_WIN1_BASE,
- len = HP_SRAM_WIN1_SIZE
- wnd2 :
- org = HP_SRAM_WIN2_BASE,
- len = HP_SRAM_WIN2_SIZE
- wnd3 :
- org = HP_SRAM_WIN3_BASE,
- len = HP_SRAM_WIN3_SIZE
-}
-
-PHDRS
-{
- vector_reset_text_phdr PT_LOAD;
- vector_reset_lit_phdr PT_LOAD;
- vector_memory_lit_phdr PT_LOAD;
- vector_memory_text_phdr PT_LOAD;
- vector_base_text_phdr PT_LOAD;
- vector_int2_lit_phdr PT_LOAD;
- vector_int2_text_phdr PT_LOAD;
- vector_int3_lit_phdr PT_LOAD;
- vector_int3_text_phdr PT_LOAD;
- vector_int4_lit_phdr PT_LOAD;
- vector_int4_text_phdr PT_LOAD;
- vector_int5_lit_phdr PT_LOAD;
- vector_int5_text_phdr PT_LOAD;
- vector_int6_lit_phdr PT_LOAD;
- vector_int6_text_phdr PT_LOAD;
- vector_int7_lit_phdr PT_LOAD;
- vector_int7_text_phdr PT_LOAD;
- vector_kernel_lit_phdr PT_LOAD;
- vector_kernel_text_phdr PT_LOAD;
- vector_user_lit_phdr PT_LOAD;
- vector_user_text_phdr PT_LOAD;
- vector_double_lit_phdr PT_LOAD;
- vector_double_text_phdr PT_LOAD;
- sof_text_phdr PT_LOAD;
- sof_data_phdr PT_LOAD;
- sof_bss_data_phdr PT_LOAD;
- system_heap_phdr PT_LOAD;
- runtime_heap_phdr PT_LOAD;
- buffer_heap_phdr PT_LOAD;
- sof_stack_phdr PT_LOAD;
- buffer_hp_heap_phdr PT_LOAD;
- wnd0_phdr PT_LOAD;
- wnd1_phdr PT_LOAD;
- wnd2_phdr PT_LOAD;
- wnd3_phdr PT_LOAD;
-}
-
-/* Default entry point: */
-ENTRY(_MainEntry)
-_rom_store_table = 0;
-
-/* ABI0 does not use Window base */
-PROVIDE(_memmap_vecbase_reset = XCHAL_VECBASE_RESET_PADDR);
-
-/* Various memory-map dependent cache attribute settings: */
-_memmap_cacheattr_wb_base = 0x44024000;
-_memmap_cacheattr_wt_base = 0x11021000;
-_memmap_cacheattr_bp_base = 0x22022000;
-_memmap_cacheattr_unused_mask = 0x00F00FFF;
-_memmap_cacheattr_wb_trapnull = 0x4422422F;
-_memmap_cacheattr_wba_trapnull = 0x4422422F;
-_memmap_cacheattr_wbna_trapnull = 0x25222222;
-_memmap_cacheattr_wt_trapnull = 0x1122122F;
-_memmap_cacheattr_bp_trapnull = 0x2222222F;
-_memmap_cacheattr_wb_strict = 0x44F24FFF;
-_memmap_cacheattr_wt_strict = 0x11F21FFF;
-_memmap_cacheattr_bp_strict = 0x22F22FFF;
-_memmap_cacheattr_wb_allvalid = 0x44224222;
-_memmap_cacheattr_wt_allvalid = 0x11221222;
-_memmap_cacheattr_bp_allvalid = 0x22222222;
-PROVIDE(_memmap_cacheattr_reset = _memmap_cacheattr_wbna_trapnull);
-
-SECTIONS
-{
- .MemoryExceptionVector.literal : ALIGN(4)
- {
- _MemoryExceptionVector_literal_start = ABSOLUTE(.);
- KEEP (*(.MemoryExceptionVector.literal))
- _MemoryExceptionVector_literal_end = ABSOLUTE(.);
- } >vector_memory_lit :vector_memory_lit_phdr
-
- .MemoryExceptionVector.text : ALIGN(4)
- {
- _MemoryExceptionVector_text_start = ABSOLUTE(.);
- KEEP (*(.MemoryExceptionVector.text))
- _MemoryExceptionVector_text_end = ABSOLUTE(.);
- } >vector_memory_text :vector_memory_text_phdr
-
- .buffer_hp_heap (NOLOAD) : ALIGN(8)
- {
- . = ALIGN (32);
- _buffer_hp_heap_start = ABSOLUTE(.);
- . = . + HEAP_HP_BUFFER_SIZE;
- _buffer_hp_heap_end = ABSOLUTE(.);
- } >buffer_hp_heap :buffer_hp_heap_phdr
-
- .wnd0 (NOLOAD) : ALIGN(8)
- {
- . = ALIGN (32);
- _wnd0_start = ABSOLUTE(.);
- . = . + HP_SRAM_WIN0_SIZE;
- _wnd0_end = ABSOLUTE(.);
- } >wnd0 :wnd0_phdr
-
- .wnd1 (NOLOAD) : ALIGN(8)
- {
- . = ALIGN (32);
- _wnd1_start = ABSOLUTE(.);
- . = . + HP_SRAM_WIN1_SIZE;
- _wnd1_end = ABSOLUTE(.);
- } >wnd1 :wnd1_phdr
-
- .wnd2 (NOLOAD) : ALIGN(8)
- {
- . = ALIGN (32);
- _wnd2_start = ABSOLUTE(.);
- . = . + HP_SRAM_WIN2_SIZE;
- _wnd2_end = ABSOLUTE(.);
- } >wnd2 :wnd2_phdr
-
- .wnd3 (NOLOAD) : ALIGN(8)
- {
- . = ALIGN (32);
- _wnd3_start = ABSOLUTE(.);
- . = . + HP_SRAM_WIN3_SIZE;
- _wnd3_end = ABSOLUTE(.);
- } >wnd3 :wnd3_phdr
-
- .WindowVectors.text : ALIGN(4)
- {
- _WindowVectors_text_start = ABSOLUTE(.);
- KEEP (*(.WindowVectors.text))
- _WindowVectors_text_end = ABSOLUTE(.);
- } >vector_base_text :vector_base_text_phdr
-
- .Level2InterruptVector.literal : ALIGN(4)
- {
- _Level2InterruptVector_literal_start = ABSOLUTE(.);
- *(.Level2InterruptVector.literal)
- _Level2InterruptVector_literal_end = ABSOLUTE(.);
- } >vector_int2_lit :vector_int2_lit_phdr
-
- .Level2InterruptVector.text : ALIGN(4)
- {
- _Level2InterruptVector_text_start = ABSOLUTE(.);
- KEEP (*(.Level2InterruptVector.text))
- _Level2InterruptVector_text_end = ABSOLUTE(.);
- } >vector_int2_text :vector_int2_text_phdr
-
- .Level3InterruptVector.literal : ALIGN(4)
- {
- _Level3InterruptVector_literal_start = ABSOLUTE(.);
- *(.Level3InterruptVector.literal)
- _Level3InterruptVector_literal_end = ABSOLUTE(.);
- } >vector_int3_lit :vector_int3_lit_phdr
-
- .Level3InterruptVector.text : ALIGN(4)
- {
- _Level3InterruptVector_text_start = ABSOLUTE(.);
- KEEP (*(.Level3InterruptVector.text))
- _Level3InterruptVector_text_end = ABSOLUTE(.);
- } >vector_int3_text :vector_int3_text_phdr
-
- .Level4InterruptVector.literal : ALIGN(4)
- {
- _Level4InterruptVector_literal_start = ABSOLUTE(.);
- *(.Level4InterruptVector.literal)
- _Level4InterruptVector_literal_end = ABSOLUTE(.);
- } >vector_int4_lit :vector_int4_lit_phdr
-
- .Level4InterruptVector.text : ALIGN(4)
- {
- _Level4InterruptVector_text_start = ABSOLUTE(.);
- KEEP (*(.Level4InterruptVector.text))
- _Level4InterruptVector_text_end = ABSOLUTE(.);
- } >vector_int4_text :vector_int4_text_phdr
-
- .Level5InterruptVector.literal : ALIGN(4)
- {
- _Level5InterruptVector_literal_start = ABSOLUTE(.);
- *(.Level5InterruptVector.literal)
- _Level5InterruptVector_literal_end = ABSOLUTE(.);
- } >vector_int5_lit :vector_int5_lit_phdr
-
- .Level5InterruptVector.text : ALIGN(4)
- {
- _Level5InterruptVector_text_start = ABSOLUTE(.);
- KEEP (*(.Level5InterruptVector.text))
- _Level5InterruptVector_text_end = ABSOLUTE(.);
- } >vector_int5_text :vector_int5_text_phdr
-
- .DebugExceptionVector.literal : ALIGN(4)
- {
- _DebugExceptionVector_literal_start = ABSOLUTE(.);
- *(.DebugExceptionVector.literal)
- _DebugExceptionVector_literal_end = ABSOLUTE(.);
- } >vector_int6_lit :vector_int6_lit_phdr
-
- .DebugExceptionVector.text : ALIGN(4)
- {
- _DebugExceptionVector_text_start = ABSOLUTE(.);
- KEEP (*(.DebugExceptionVector.text))
- _DebugExceptionVector_text_end = ABSOLUTE(.);
- } >vector_int6_text :vector_int6_text_phdr
-
- .NMIExceptionVector.literal : ALIGN(4)
- {
- _NMIExceptionVector_literal_start = ABSOLUTE(.);
- *(.NMIExceptionVector.literal)
- _NMIExceptionVector_literal_end = ABSOLUTE(.);
- } >vector_int7_lit :vector_int7_lit_phdr
-
- .NMIExceptionVector.text : ALIGN(4)
- {
- _NMIExceptionVector_text_start = ABSOLUTE(.);
- KEEP (*(.NMIExceptionVector.text))
- _NMIExceptionVector_text_end = ABSOLUTE(.);
- } >vector_int7_text :vector_int7_text_phdr
-
- .KernelExceptionVector.literal : ALIGN(4)
- {
- _KernelExceptionVector_literal_start = ABSOLUTE(.);
- *(.KernelExceptionVector.literal)
- _KernelExceptionVector_literal_end = ABSOLUTE(.);
- } >vector_kernel_lit :vector_kernel_lit_phdr
-
- .KernelExceptionVector.text : ALIGN(4)
- {
- _KernelExceptionVector_text_start = ABSOLUTE(.);
- KEEP (*(.KernelExceptionVector.text))
- _KernelExceptionVector_text_end = ABSOLUTE(.);
- } >vector_kernel_text :vector_kernel_text_phdr
-
- .UserExceptionVector.literal : ALIGN(4)
- {
- _UserExceptionVector_literal_start = ABSOLUTE(.);
- *(.UserExceptionVector.literal)
- _UserExceptionVector_literal_end = ABSOLUTE(.);
- } >vector_user_lit :vector_user_lit_phdr
-
- .UserExceptionVector.text : ALIGN(4)
- {
- _UserExceptionVector_text_start = ABSOLUTE(.);
- KEEP (*(.UserExceptionVector.text))
- _UserExceptionVector_text_end = ABSOLUTE(.);
- } >vector_user_text :vector_user_text_phdr
-
- .DoubleExceptionVector.literal : ALIGN(4)
- {
- _DoubleExceptionVector_literal_start = ABSOLUTE(.);
- *(.DoubleExceptionVector.literal)
- _DoubleExceptionVector_literal_end = ABSOLUTE(.);
- } >vector_double_lit :vector_double_lit_phdr
-
- .DoubleExceptionVector.text : ALIGN(4)
- {
- _DoubleExceptionVector_text_start = ABSOLUTE(.);
- KEEP (*(.DoubleExceptionVector.text))
- _DoubleExceptionVector_text_end = ABSOLUTE(.);
- } >vector_double_text :vector_double_text_phdr
-
- .text : ALIGN(4)
- {
- _stext = .;
- _text_start = ABSOLUTE(.);
- KEEP (*(.MainEntry.text))
- *(.entry.text)
- *(.init.literal)
- KEEP(*(.init))
- *(.literal .text .literal.* .text.* .stub .gnu.warning .gnu.linkonce.literal.* .gnu.linkonce.t.*.literal .gnu.linkonce.t.*)
- *(.fini.literal)
- KEEP(*(.fini))
- *(.gnu.version)
- _text_end = ABSOLUTE(.);
- _etext = .;
- } >sof_text :sof_text_phdr
-
- .rodata : ALIGN(4)
- {
- _rodata_start = ABSOLUTE(.);
- *(.rodata)
- *(.rodata.*)
- *(.gnu.linkonce.r.*)
- *(.rodata1)
- __XT_EXCEPTION_TABLE__ = ABSOLUTE(.);
- KEEP (*(.xt_except_table))
- KEEP (*(.gcc_except_table))
- *(.gnu.linkonce.e.*)
- *(.gnu.version_r)
- KEEP (*(.eh_frame))
- /* C++ constructor and destructor tables, properly ordered: */
- KEEP (*crtbegin.o(.ctors))
- KEEP (*(EXCLUDE_FILE (*crtend.o) .ctors))
- KEEP (*(SORT(.ctors.*)))
- KEEP (*(.ctors))
- KEEP (*crtbegin.o(.dtors))
- KEEP (*(EXCLUDE_FILE (*crtend.o) .dtors))
- KEEP (*(SORT(.dtors.*)))
- KEEP (*(.dtors))
- /* C++ exception handlers table: */
- __XT_EXCEPTION_DESCS__ = ABSOLUTE(.);
- *(.xt_except_desc)
- *(.gnu.linkonce.h.*)
- __XT_EXCEPTION_DESCS_END__ = ABSOLUTE(.);
- *(.xt_except_desc_end)
- *(.dynamic)
- *(.gnu.version_d)
- . = ALIGN(4); /* this table MUST be 4-byte aligned */
- _bss_table_start = ABSOLUTE(.);
- LONG(_bss_start)
- LONG(_bss_end)
- _bss_table_end = ABSOLUTE(.);
- _rodata_end = ABSOLUTE(.);
- } >sof_data :sof_data_phdr
-
- .data : ALIGN(4)
- {
- _data_start = ABSOLUTE(.);
- *(.data)
- *(.data.*)
- *(.gnu.linkonce.d.*)
- KEEP(*(.gnu.linkonce.d.*personality*))
- *(.data1)
- *(.sdata)
- *(.sdata.*)
- *(.gnu.linkonce.s.*)
- *(.sdata2)
- *(.sdata2.*)
- *(.gnu.linkonce.s2.*)
- KEEP(*(.jcr))
- _data_end = ABSOLUTE(.);
- } >sof_data :sof_data_phdr
-
- .lit4 : ALIGN(4)
- {
- _lit4_start = ABSOLUTE(.);
- *(*.lit4)
- *(.lit4.*)
- *(.gnu.linkonce.lit4.*)
- _lit4_end = ABSOLUTE(.);
- } >sof_data :sof_data_phdr
-
- .bss (NOLOAD) : ALIGN(8)
- {
- . = ALIGN (8);
- _bss_start = ABSOLUTE(.);
- *(.dynsbss)
- *(.sbss)
- *(.sbss.*)
- *(.gnu.linkonce.sb.*)
- *(.scommon)
- *(.sbss2)
- *(.sbss2.*)
- *(.gnu.linkonce.sb2.*)
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- *(.bss)
- *(.bss.*)
- *(.gnu.linkonce.b.*)
- *(COMMON)
- . = ALIGN (8);
- _bss_end = ABSOLUTE(.);
- } >sof_bss_data :sof_bss_data_phdr
-
- /* stack */
- _end = SOF_STACK_END;
- PROVIDE(end = SOF_STACK_END);
- _stack_sentry = SOF_STACK_END;
- __stack = SOF_STACK_BASE;
-
- /* System Heap */
- _system_heap = HEAP_SYSTEM_BASE;
-
-
- /* module heap */
- _module_heap = HEAP_RUNTIME_BASE;
-
- /* buffer heap */
- _buffer_heap = HEAP_BUFFER_BASE;
- _buffer_heap_end = _stack_sentry;
-
- .debug 0 : { *(.debug) }
- .line 0 : { *(.line) }
- .debug_srcinfo 0 : { *(.debug_srcinfo) }
- .debug_sfnames 0 : { *(.debug_sfnames) }
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- .debug_funcnames 0 : { *(.debug_funcnames) }
- .debug_typenames 0 : { *(.debug_typenames) }
- .debug_varnames 0 : { *(.debug_varnames) }
-
- .xt.insn 0 :
- {
- KEEP (*(.xt.insn))
- KEEP (*(.gnu.linkonce.x.*))
- }
- .xt.prop 0 :
- {
- KEEP (*(.xt.prop))
- KEEP (*(.xt.prop.*))
- KEEP (*(.gnu.linkonce.prop.*))
- }
- .xt.lit 0 :
- {
- KEEP (*(.xt.lit))
- KEEP (*(.xt.lit.*))
- KEEP (*(.gnu.linkonce.p.*))
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- KEEP (*(.gnu.linkonce.profile_range.*))
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- {
- KEEP (*(.xt.profile_ranges))
- KEEP (*(.gnu.linkonce.xt.profile_ranges.*))
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- .xt.profile_files 0 :
- {
- KEEP (*(.xt.profile_files))
- KEEP (*(.gnu.linkonce.xt.profile_files.*))
- }
-
- .system_heap (NOLOAD) : ALIGN(8)
- {
- . = ALIGN (32);
- _system_heap_start = ABSOLUTE(.);
- . = . + HEAP_SYSTEM_SIZE;
- _system_heap_end = ABSOLUTE(.);
- } >system_heap :system_heap_phdr
-
- .runtime_heap (NOLOAD) : ALIGN(8)
- {
- . = ALIGN (32);
- _runtime_heap_start = ABSOLUTE(.);
- . = . + HEAP_RUNTIME_SIZE;
- _runtime_heap_end = ABSOLUTE(.);
- } >runtime_heap :runtime_heap_phdr
-
- .buffer_heap (NOLOAD) : ALIGN(8)
- {
- . = ALIGN (32);
- _system_heap_start = ABSOLUTE(.);
- . = . + HEAP_BUFFER_SIZE;
- _system_heap_end = ABSOLUTE(.);
- } >buffer_heap :buffer_heap_phdr
-
- .sof_stack (NOLOAD) : ALIGN(8)
- {
- . = ALIGN (4096);
- _sof_stack_start = ABSOLUTE(.);
- . = . + SOF_STACK_SIZE;
- _sof_stack_end = ABSOLUTE(.);
- } >sof_stack :sof_stack_phdr
-
-}
diff --git a/src/platform/apollolake/base_module.c b/src/platform/apollolake/base_module.c
deleted file mode 100644
index 38ec50f..0000000
--- a/src/platform/apollolake/base_module.c
+++ /dev/null
@@ -1,55 +0,0 @@
-/*
- * Copyright (c) 2018, Intel Corporation
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- * * Redistributions of source code must retain the above copyright
- * notice, this list of conditions and the following disclaimer.
- * * Redistributions in binary form must reproduce the above copyright
- * notice, this list of conditions and the following disclaimer in the
- * documentation and/or other materials provided with the distribution.
- * * Neither the name of the Intel Corporation nor the
- * names of its contributors may be used to endorse or promote products
- * derived from this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
- * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
- * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
- * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
- * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
- * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
- * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
- * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
- * POSSIBILITY OF SUCH DAMAGE.
- *
- * Author: Liam Girdwood <liam.r.girdwood@linux.intel.com>
- */
-
-#include <uapi/manifest.h>
-#include <platform/memory.h>
-
-/*
- * Each module has an entry in the FW manifest header. This is NOT part of
- * the SOF executable image but is inserted by object copy as a ELF section
- * for parsing by rimage (to genrate the manifest).
- */
-struct sof_man_module_manifest apl_manifest = {
- .module = {
- .name = "BASEFW",
- .uuid = {0x2e, 0x9e, 0x86, 0xfc, 0xf8, 0x45, 0x45, 0x40,
- 0xa4, 0x16, 0x89, 0x88, 0x0a, 0xe3, 0x20, 0xa9},
- .entry_point = SOF_TEXT_START,
- .type = {
- .load_type = SOF_MAN_MOD_TYPE_MODULE,
- .domain_ll = 1,
- },
- .affinity_mask = 3,
- },
- .text_size = SOF_TEXT_SIZE + L2_VECTOR_SIZE,
-};
-
-/* not used, but stops linker complaining */
-int _start;
diff --git a/src/platform/apollolake/boot_ldr.x.in b/src/platform/apollolake/boot_ldr.x.in
deleted file mode 100644
index 7465f9f..0000000
--- a/src/platform/apollolake/boot_ldr.x.in
+++ /dev/null
@@ -1,236 +0,0 @@
-/*
- * Linker Script for Apollolake Bootloader.
- *
- * This script is run through the GNU C preprocessor to align the memory
- * offsets with headers.
- *
- * Use spaces for formatting as cpp ignore tab sizes.
- */
-
-#include <platform/memory.h>
-#include <xtensa/config/core-isa.h>
-
-OUTPUT_ARCH(xtensa)
-
-MEMORY
-{
- boot_entry_text :
- org = IMR_BOOT_LDR_TEXT_ENTRY_BASE,
- len = IMR_BOOT_LDR_TEXT_ENTRY_SIZE
- boot_entry_lit :
- org = IMR_BOOT_LDR_LIT_BASE,
- len = IMR_BOOT_LDR_LIT_SIZE
- sof_text :
- org = IMR_BOOT_LDR_TEXT_BASE,
- len = IMR_BOOT_LDR_TEXT_SIZE,
- sof_data :
- org = IMR_BOOT_LDR_DATA_BASE,
- len = IMR_BOOT_LDR_DATA_SIZE
- sof_bss_data :
- org = IMR_BOOT_LDR_BSS_BASE,
- len = IMR_BOOT_LDR_BSS_SIZE
- sof_stack :
- org = SOF_STACK_END,
- len = SOF_STACK_BASE - SOF_STACK_END
- wnd0 :
- org = HP_SRAM_WIN0_BASE,
- len = HP_SRAM_WIN0_SIZE
-}
-
-PHDRS
-{
- boot_entry_text_phdr PT_LOAD;
- boot_entry_lit_phdr PT_LOAD;
- sof_text_phdr PT_LOAD;
- sof_data_phdr PT_LOAD;
- sof_bss_data_phdr PT_LOAD;
- sof_stack_phdr PT_LOAD;
- wnd0_phdr PT_LOAD;
-}
-
-/* Default entry point: */
-ENTRY(boot_entry)
-EXTERN(reset_vector)
-
-SECTIONS
-{
- .boot_entry.text : ALIGN(4)
- {
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- *(.literal .literal.* .stub .gnu.warning .gnu.linkonce.literal.* .gnu.linkonce.t.*.literal .gnu.linkonce.t.*)
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- *(.fini.literal)
- KEEP(*(.fini))
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- KEEP (*(.ResetVector.text))
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diff --git a/src/platform/apollolake/boot_module.c b/src/platform/apollolake/boot_module.c
deleted file mode 100644
index a4dfe1e..0000000
--- a/src/platform/apollolake/boot_module.c
+++ /dev/null
@@ -1,54 +0,0 @@
-/*
- * Copyright (c) 2018, Intel Corporation
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- * * Redistributions of source code must retain the above copyright
- * notice, this list of conditions and the following disclaimer.
- * * Redistributions in binary form must reproduce the above copyright
- * notice, this list of conditions and the following disclaimer in the
- * documentation and/or other materials provided with the distribution.
- * * Neither the name of the Intel Corporation nor the
- * names of its contributors may be used to endorse or promote products
- * derived from this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
- * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
- * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
- * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
- * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
- * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
- * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
- * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
- * POSSIBILITY OF SUCH DAMAGE.
- *
- * Author: Marcin Maka <marcin.maka@linux.intel.com>
- */
-
-#include <uapi/manifest.h>
-#include <platform/memory.h>
-
-/*
- * Each module has an entry in the FW manifest header. This is NOT part of
- * the SOF executable image but is inserted by object copy as a ELF section
- * for parsing by rimage (to generate the manifest).
- */
-struct sof_man_module_manifest apl_bootldr_manifest = {
- .module = {
- .name = "BRNGUP",
- .uuid = {0xcc, 0x48, 0x7b, 0x0d, 0xa9, 0x1e, 0x0a, 0x47,
- 0xa8, 0xc1, 0x53, 0x34, 0x24, 0x52, 0x8a, 0x17},
- .entry_point = IMR_BOOT_LDR_TEXT_ENTRY_BASE,
- .type = {
- .load_type = SOF_MAN_MOD_TYPE_MODULE,
- .domain_ll = 1,
- },
- .affinity_mask = 3,
- },
-};
-
-/* not used, but stops linker complaining */
-int _start;
diff --git a/src/platform/apollolake/include/Makefile.am b/src/platform/apollolake/include/Makefile.am
deleted file mode 100644
index c5113a4..0000000
--- a/src/platform/apollolake/include/Makefile.am
+++ /dev/null
@@ -1 +0,0 @@
-SUBDIRS = arch platform
diff --git a/src/platform/apollolake/include/arch/Makefile.am b/src/platform/apollolake/include/arch/Makefile.am
deleted file mode 100644
index 63616bf..0000000
--- a/src/platform/apollolake/include/arch/Makefile.am
+++ /dev/null
@@ -1 +0,0 @@
-SUBDIRS = xtensa
diff --git a/src/platform/apollolake/include/arch/xtensa/Makefile.am b/src/platform/apollolake/include/arch/xtensa/Makefile.am
deleted file mode 100644
index a85a5bb..0000000
--- a/src/platform/apollolake/include/arch/xtensa/Makefile.am
+++ /dev/null
@@ -1 +0,0 @@
-SUBDIRS = config
diff --git a/src/platform/apollolake/include/arch/xtensa/config/Makefile.am b/src/platform/apollolake/include/arch/xtensa/config/Makefile.am
deleted file mode 100644
index 99c21a5..0000000
--- a/src/platform/apollolake/include/arch/xtensa/config/Makefile.am
+++ /dev/null
@@ -1,8 +0,0 @@
-noinst_HEADERS = \
- core-isa.h \
- core-matmap.h \
- defs.h \
- specreg.h \
- system.h \
- tie.h \
- tie-asm.h
diff --git a/src/platform/apollolake/include/arch/xtensa/config/core-isa.h b/src/platform/apollolake/include/arch/xtensa/config/core-isa.h
deleted file mode 100644
index eedbd1c..0000000
--- a/src/platform/apollolake/include/arch/xtensa/config/core-isa.h
+++ /dev/null
@@ -1,610 +0,0 @@
-/*
- * xtensa/config/core-isa.h -- HAL definitions that are dependent on Xtensa
- * processor CORE configuration
- *
- * See <xtensa/config/core.h>, which includes this file, for more details.
- */
-
-/* Xtensa processor core configuration information.
-
- Customer ID=4313; Build=0x5483b; Copyright (c) 1999-2015 Tensilica Inc.
-
- Permission is hereby granted, free of charge, to any person obtaining
- a copy of this software and associated documentation files (the
- "Software"), to deal in the Software without restriction, including
- without limitation the rights to use, copy, modify, merge, publish,
- distribute, sublicense, and/or sell copies of the Software, and to
- permit persons to whom the Software is furnished to do so, subject to
- the following conditions:
-
- The above copyright notice and this permission notice shall be included
- in all copies or substantial portions of the Software.
-
- THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
- EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
- MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
- IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY
- CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
- TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
- SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. */
-
-#if !defined __XCC__
-
-#ifndef _XTENSA_CORE_CONFIGURATION_H
-#define _XTENSA_CORE_CONFIGURATION_H
-
-
-/****************************************************************************
- Parameters Useful for Any Code, USER or PRIVILEGED
- ****************************************************************************/
-
-/*
- * Note: Macros of the form XCHAL_HAVE_*** have a value of 1 if the option is
- * configured, and a value of 0 otherwise. These macros are always defined.
- */
-
-
-/*----------------------------------------------------------------------
- ISA
- ----------------------------------------------------------------------*/
-
-#define XCHAL_HAVE_BE 0 /* big-endian byte ordering */
-#define XCHAL_HAVE_WINDOWED 1 /* windowed registers option */
-#define XCHAL_NUM_AREGS 64 /* num of physical addr regs */
-#define XCHAL_NUM_AREGS_LOG2 6 /* log2(XCHAL_NUM_AREGS) */
-#define XCHAL_MAX_INSTRUCTION_SIZE 8 /* max instr bytes (3..8) */
-#define XCHAL_HAVE_DEBUG 1 /* debug option */
-#define XCHAL_HAVE_DENSITY 1 /* 16-bit instructions */
-#define XCHAL_HAVE_LOOPS 1 /* zero-overhead loops */
-#define XCHAL_LOOP_BUFFER_SIZE 0 /* zero-ov. loop instr buffer size */
-#define XCHAL_HAVE_NSA 1 /* NSA/NSAU instructions */
-#define XCHAL_HAVE_MINMAX 1 /* MIN/MAX instructions */
-#define XCHAL_HAVE_SEXT 1 /* SEXT instruction */
-#define XCHAL_HAVE_DEPBITS 0 /* DEPBITS instruction */
-#define XCHAL_HAVE_CLAMPS 1 /* CLAMPS instruction */
-#define XCHAL_HAVE_MUL16 1 /* MUL16S/MUL16U instructions */
-#define XCHAL_HAVE_MUL32 1 /* MULL instruction */
-#define XCHAL_HAVE_MUL32_HIGH 1 /* MULUH/MULSH instructions */
-#define XCHAL_HAVE_DIV32 1 /* QUOS/QUOU/REMS/REMU instructions */
-#define XCHAL_HAVE_L32R 1 /* L32R instruction */
-#define XCHAL_HAVE_ABSOLUTE_LITERALS 0 /* non-PC-rel (extended) L32R */
-#define XCHAL_HAVE_CONST16 0 /* CONST16 instruction */
-#define XCHAL_HAVE_ADDX 1 /* ADDX#/SUBX# instructions */
-#define XCHAL_HAVE_WIDE_BRANCHES 0 /* B*.W18 or B*.W15 instr's */
-#define XCHAL_HAVE_PREDICTED_BRANCHES 0 /* B[EQ/EQZ/NE/NEZ]T instr's */
-#define XCHAL_HAVE_CALL4AND12 1 /* (obsolete option) */
-#define XCHAL_HAVE_ABS 1 /* ABS instruction */
-/*#define XCHAL_HAVE_POPC 0*/ /* POPC instruction */
-/*#define XCHAL_HAVE_CRC 0*/ /* CRC instruction */
-#define XCHAL_HAVE_RELEASE_SYNC 1 /* L32AI/S32RI instructions */
-#define XCHAL_HAVE_S32C1I 1 /* S32C1I instruction */
-#define XCHAL_HAVE_SPECULATION 0 /* speculation */
-#define XCHAL_HAVE_FULL_RESET 1 /* all regs/state reset */
-#define XCHAL_NUM_CONTEXTS 1 /* */
-#define XCHAL_NUM_MISC_REGS 0 /* num of scratch regs (0..4) */
-#define XCHAL_HAVE_TAP_MASTER 0 /* JTAG TAP control instr's */
-#define XCHAL_HAVE_PRID 1 /* processor ID register */
-#define XCHAL_HAVE_EXTERN_REGS 1 /* WER/RER instructions */
-#define XCHAL_HAVE_MX 0 /* MX core (Tensilica internal) */
-#define XCHAL_HAVE_MP_INTERRUPTS 0 /* interrupt distributor port */
-#define XCHAL_HAVE_MP_RUNSTALL 0 /* core RunStall control port */
-#define XCHAL_HAVE_PSO 0 /* Power Shut-Off */
-#define XCHAL_HAVE_PSO_CDM 0 /* core/debug/mem pwr domains */
-#define XCHAL_HAVE_PSO_FULL_RETENTION 0 /* all regs preserved on PSO */
-#define XCHAL_HAVE_THREADPTR 1 /* THREADPTR register */
-#define XCHAL_HAVE_BOOLEANS 1 /* boolean registers */
-#define XCHAL_HAVE_CP 0 /* CPENABLE reg (coprocessor) */
-#define XCHAL_CP_MAXCFG 2 /* max allowed cp id plus one */
-
-
-#define XCHAL_HAVE_MAC16 0 /* MAC16 package */
-
-#define XCHAL_HAVE_FUSION 0 /* Fusion*/
-#define XCHAL_HAVE_FUSION_FP 0 /* Fusion FP option */
-#define XCHAL_HAVE_FUSION_LOW_POWER 0 /* Fusion Low Power option */
-#define XCHAL_HAVE_FUSION_AES 0 /* Fusion BLE/Wifi AES-128 CCM option */
-#define XCHAL_HAVE_FUSION_CONVENC 0 /* Fusion Conv Encode option */
-#define XCHAL_HAVE_FUSION_LFSR_CRC 0 /* Fusion LFSR-CRC option */
-#define XCHAL_HAVE_FUSION_BITOPS 0 /* Fusion Bit Operations Support option */
-#define XCHAL_HAVE_FUSION_AVS 0 /* Fusion AVS option */
-#define XCHAL_HAVE_FUSION_16BIT_BASEBAND 0 /* Fusion 16-bit Baseband option */
-#define XCHAL_HAVE_HIFIPRO 0 /* HiFiPro Audio Engine pkg */
-#define XCHAL_HAVE_HIFI4 0 /* HiFi4 Audio Engine pkg */
-#define XCHAL_HAVE_HIFI4_VFPU 0 /* HiFi4 Audio Engine VFPU option */
-#define XCHAL_HAVE_HIFI3 1 /* HiFi3 Audio Engine pkg */
-#define XCHAL_HAVE_HIFI3_VFPU 0 /* HiFi3 Audio Engine VFPU option */
-#define XCHAL_HAVE_HIFI2 0 /* HiFi2 Audio Engine pkg */
-#define XCHAL_HAVE_HIFI2EP 0 /* HiFi2EP */
-#define XCHAL_HAVE_HIFI2_MUL32X24 0 /* HiFi2 and 32x24 MACs */
-#define XCHAL_HAVE_HIFI_MINI 0
-
-
-#define XCHAL_HAVE_VECTORFPU2005 0 /* vector or user floating-point pkg */
-#define XCHAL_HAVE_USER_DPFPU 0 /* user DP floating-point pkg */
-#define XCHAL_HAVE_USER_SPFPU 0 /* user DP floating-point pkg */
-#define XCHAL_HAVE_FP 1 /* single prec floating point */
-#define XCHAL_HAVE_FP_DIV 0 /* FP with DIV instructions */
-#define XCHAL_HAVE_FP_RECIP 0 /* FP with RECIP instructions */
-#define XCHAL_HAVE_FP_SQRT 0 /* FP with SQRT instructions */
-#define XCHAL_HAVE_FP_RSQRT 0 /* FP with RSQRT instructions */
-#define XCHAL_HAVE_DFP 0 /* double precision FP pkg */
-#define XCHAL_HAVE_DFP_DIV 0 /* DFP with DIV instructions */
-#define XCHAL_HAVE_DFP_RECIP 0 /* DFP with RECIP instructions*/
-#define XCHAL_HAVE_DFP_SQRT 0 /* DFP with SQRT instructions */
-#define XCHAL_HAVE_DFP_RSQRT 0 /* DFP with RSQRT instructions*/
-#define XCHAL_HAVE_DFP_ACCEL 0 /* double precision FP acceleration pkg */
-#define XCHAL_HAVE_DFP_accel XCHAL_HAVE_DFP_ACCEL /* for backward compatibility */
-
-#define XCHAL_HAVE_DFPU_SINGLE_ONLY 0 /* DFPU Coprocessor, single precision only */
-#define XCHAL_HAVE_DFPU_SINGLE_DOUBLE 0 /* DFPU Coprocessor, single and double precision */
-#define XCHAL_HAVE_VECTRA1 0 /* Vectra I pkg */
-#define XCHAL_HAVE_VECTRALX 0 /* Vectra LX pkg */
-#define XCHAL_HAVE_PDX4 0 /* PDX4 */
-#define XCHAL_HAVE_CONNXD2 0 /* ConnX D2 pkg */
-#define XCHAL_HAVE_CONNXD2_DUALLSFLIX 0 /* ConnX D2 & Dual LoadStore Flix */
-#define XCHAL_HAVE_BBE16 0 /* ConnX BBE16 pkg */
-#define XCHAL_HAVE_BBE16_RSQRT 0 /* BBE16 & vector recip sqrt */
-#define XCHAL_HAVE_BBE16_VECDIV 0 /* BBE16 & vector divide */
-#define XCHAL_HAVE_BBE16_DESPREAD 0 /* BBE16 & despread */
-#define XCHAL_HAVE_BBENEP 0 /* ConnX BBENEP pkgs */
-#define XCHAL_HAVE_BSP3 0 /* ConnX BSP3 pkg */
-#define XCHAL_HAVE_BSP3_TRANSPOSE 0 /* BSP3 & transpose32x32 */
-#define XCHAL_HAVE_SSP16 0 /* ConnX SSP16 pkg */
-#define XCHAL_HAVE_SSP16_VITERBI 0 /* SSP16 & viterbi */
-#define XCHAL_HAVE_TURBO16 0 /* ConnX Turbo16 pkg */
-#define XCHAL_HAVE_BBP16 0 /* ConnX BBP16 pkg */
-#define XCHAL_HAVE_FLIX3 0 /* basic 3-way FLIX option */
-#define XCHAL_HAVE_GRIVPEP 0 /* GRIVPEP is General Release of IVPEP */
-#define XCHAL_HAVE_GRIVPEP_HISTOGRAM 0 /* Histogram option on GRIVPEP */
-
-
-/*----------------------------------------------------------------------
- MISC
- ----------------------------------------------------------------------*/
-
-#define XCHAL_NUM_LOADSTORE_UNITS 2 /* load/store units */
-#define XCHAL_NUM_WRITEBUFFER_ENTRIES 8 /* size of write buffer */
-#define XCHAL_INST_FETCH_WIDTH 8 /* instr-fetch width in bytes */
-#define XCHAL_DATA_WIDTH 8 /* data width in bytes */
-#define XCHAL_DATA_PIPE_DELAY 1 /* d-side pipeline delay
- (1 = 5-stage, 2 = 7-stage) */
-#define XCHAL_CLOCK_GATING_GLOBAL 1 /* global clock gating */
-#define XCHAL_CLOCK_GATING_FUNCUNIT 1 /* funct. unit clock gating */
-/* In T1050, applies to selected core load and store instructions (see ISA): */
-#define XCHAL_UNALIGNED_LOAD_EXCEPTION 0 /* unaligned loads cause exc. */
-#define XCHAL_UNALIGNED_STORE_EXCEPTION 0 /* unaligned stores cause exc.*/
-#define XCHAL_UNALIGNED_LOAD_HW 1 /* unaligned loads work in hw */
-#define XCHAL_UNALIGNED_STORE_HW 1 /* unaligned stores work in hw*/
-
-#define XCHAL_SW_VERSION 1100002 /* sw version of this header */
-
-#define XCHAL_CORE_ID "hifi3" /* alphanum core name
- (CoreID) set in the Xtensa
- Processor Generator */
-
-#define XCHAL_BUILD_UNIQUE_ID 0x0005483B /* 22-bit sw build ID */
-
-/*
- * These definitions describe the hardware targeted by this software.
- */
-#define XCHAL_HW_CONFIGID0 0xC3F3FBFE /* ConfigID hi 32 bits*/
-#define XCHAL_HW_CONFIGID1 0x1544813C /* ConfigID lo 32 bits*/
-#define XCHAL_HW_VERSION_NAME "LX4.0.5" /* full version name */
-#define XCHAL_HW_VERSION_MAJOR 2400 /* major ver# of targeted hw */
-#define XCHAL_HW_VERSION_MINOR 5 /* minor ver# of targeted hw */
-#define XCHAL_HW_VERSION 240005 /* major*100+minor */
-#define XCHAL_HW_REL_LX6 1
-#define XCHAL_HW_REL_LX6_0 1
-#define XCHAL_HW_REL_LX6_0_2 1
-#define XCHAL_HW_CONFIGID_RELIABLE 1
-/* If software targets a *range* of hardware versions, these are the bounds: */
-#define XCHAL_HW_MIN_VERSION_MAJOR 2600 /* major v of earliest tgt hw */
-#define XCHAL_HW_MIN_VERSION_MINOR 2 /* minor v of earliest tgt hw */
-#define XCHAL_HW_MIN_VERSION 260002 /* earliest targeted hw */
-#define XCHAL_HW_MAX_VERSION_MAJOR 2600 /* major v of latest tgt hw */
-#define XCHAL_HW_MAX_VERSION_MINOR 2 /* minor v of latest tgt hw */
-#define XCHAL_HW_MAX_VERSION 260002 /* latest targeted hw */
-
-
-/*----------------------------------------------------------------------
- CACHE
- ----------------------------------------------------------------------*/
-
-#define XCHAL_ICACHE_LINESIZE 64 /* I-cache line size in bytes */
-#define XCHAL_DCACHE_LINESIZE 64 /* D-cache line size in bytes */
-#define XCHAL_ICACHE_LINEWIDTH 6 /* log2(I line size in bytes) */
-#define XCHAL_DCACHE_LINEWIDTH 6 /* log2(D line size in bytes) */
-
-#define XCHAL_ICACHE_SIZE 16384 /* I-cache size in bytes or 0 */
-#define XCHAL_DCACHE_SIZE 49152 /* D-cache size in bytes or 0 */
-
-#define XCHAL_DCACHE_IS_WRITEBACK 1 /* writeback feature */
-#define XCHAL_DCACHE_IS_COHERENT 0 /* MP coherence feature */
-
-#define XCHAL_HAVE_PREFETCH 1 /* PREFCTL register */
-#define XCHAL_HAVE_PREFETCH_L1 1 /* prefetch to L1 dcache */
-#define XCHAL_PREFETCH_CASTOUT_LINES 2 /* dcache pref. castout bufsz */
-#define XCHAL_PREFETCH_ENTRIES 8 /* cache prefetch entries */
-#define XCHAL_PREFETCH_BLOCK_ENTRIES 0 /* prefetch block streams */
-#define XCHAL_HAVE_CACHE_BLOCKOPS 0 /* block prefetch for caches */
-#define XCHAL_HAVE_ICACHE_TEST 0 /* Icache test instructions */
-#define XCHAL_HAVE_DCACHE_TEST 0 /* Dcache test instructions */
-#define XCHAL_HAVE_ICACHE_DYN_WAYS 0 /* Icache dynamic way support */
-#define XCHAL_HAVE_DCACHE_DYN_WAYS 0 /* Dcache dynamic way support */
-
-
-
-
-/****************************************************************************
- Parameters Useful for PRIVILEGED (Supervisory or Non-Virtualized) Code
- ****************************************************************************/
-
-
-#ifndef XTENSA_HAL_NON_PRIVILEGED_ONLY
-
-/*----------------------------------------------------------------------
- CACHE
- ----------------------------------------------------------------------*/
-
-#define XCHAL_HAVE_PIF 1 /* any outbound PIF present */
-
-/* If present, cache size in bytes == (ways * 2^(linewidth + setwidth)). */
-
-/* Number of cache sets in log2(lines per way): */
-#define XCHAL_ICACHE_SETWIDTH 7
-#define XCHAL_DCACHE_SETWIDTH 8
-
-/* Cache set associativity (number of ways): */
-#define XCHAL_ICACHE_WAYS 2
-#define XCHAL_DCACHE_WAYS 3
-
-/* Cache features: */
-#define XCHAL_ICACHE_LINE_LOCKABLE 1
-#define XCHAL_DCACHE_LINE_LOCKABLE 1
-#define XCHAL_ICACHE_ECC_PARITY XTHAL_MEMEP_ECC
-#define XCHAL_DCACHE_ECC_PARITY XTHAL_MEMEP_ECC
-
-/* Cache access size in bytes (affects operation of SICW instruction): */
-#define XCHAL_ICACHE_ACCESS_SIZE 8
-#define XCHAL_DCACHE_ACCESS_SIZE 8
-
-#define XCHAL_DCACHE_BANKS 2 /* number of banks */
-
-/* Number of encoded cache attr bits (see <xtensa/hal.h> for decoded bits): */
-#define XCHAL_CA_BITS 4
-
-/* Whether MEMCTL register has anything useful */
-#define XCHAL_USE_MEMCTL (((XCHAL_LOOP_BUFFER_SIZE > 0) || \
- XCHAL_DCACHE_IS_COHERENT || \
- XCHAL_HAVE_ICACHE_DYN_WAYS || \
- XCHAL_HAVE_DCACHE_DYN_WAYS) && \
- (XCHAL_HW_MIN_VERSION >= XTENSA_HWVERSION_RE_2012_0))
-
-
-/*----------------------------------------------------------------------
- INTERNAL I/D RAM/ROMs and XLMI
- ----------------------------------------------------------------------*/
-
-#define XCHAL_NUM_INSTROM 0 /* number of core instr. ROMs */
-#define XCHAL_NUM_INSTRAM 0 /* number of core instr. RAMs */
-#define XCHAL_NUM_DATAROM 0 /* number of core data ROMs */
-#define XCHAL_NUM_DATARAM 0 /* number of core data RAMs */
-#define XCHAL_NUM_URAM 0 /* number of core unified RAMs*/
-#define XCHAL_NUM_XLMI 0 /* number of core XLMI ports */
-
-/* Instruction RAM 0: */
-#define XCHAL_INSTRAM0_VADDR 0x80000000 /* virtual address */
-#define XCHAL_INSTRAM0_PADDR 0x80000000 /* physical address */
-#define XCHAL_INSTRAM0_SIZE 0x20000 /* size in bytes */
-#define XCHAL_INSTRAM0_ECC_PARITY 1 /* ECC/parity type, 0=none */
-
-/* Data RAM 0: */
-#define XCHAL_DATARAM0_VADDR 0xbefe0000 /* virtual address */
-#define XCHAL_DATARAM0_PADDR 0xbefe0000 /* physical address */
-#define XCHAL_DATARAM0_SIZE 0x28000 /* size in bytes */
-#define XCHAL_DATARAM0_ECC_PARITY 0 /* ECC/parity type, 0=none */
-#define XCHAL_DATARAM0_BANKS 1 /* number of banks */
-
-
-#define XCHAL_HAVE_IMEM_LOADSTORE 1 /* can load/store to IROM/IRAM*/
-
-
-/*----------------------------------------------------------------------
- INTERRUPTS and TIMERS
- ----------------------------------------------------------------------*/
-
-#define XCHAL_HAVE_INTERRUPTS 1 /* interrupt option */
-#define XCHAL_HAVE_HIGHPRI_INTERRUPTS 1 /* med/high-pri. interrupts */
-#define XCHAL_HAVE_NMI 1 /* non-maskable interrupt */
-#define XCHAL_HAVE_CCOUNT 1 /* CCOUNT reg. (timer option) */
-#define XCHAL_NUM_TIMERS 3 /* number of CCOMPAREn regs */
-#define XCHAL_NUM_INTERRUPTS 21 /* number of interrupts */
-#define XCHAL_NUM_INTERRUPTS_LOG2 5 /* ceil(log2(NUM_INTERRUPTS)) */
-#define XCHAL_NUM_EXTINTERRUPTS 8 /* num of external interrupts */
-#define XCHAL_NUM_INTLEVELS 6 /* number of interrupt levels
- (not including level zero) */
-#define XCHAL_EXCM_LEVEL 5 /* level masked by PS.EXCM */
- /* (always 1 in XEA1; levels 2 .. EXCM_LEVEL are "medium priority") */
-
-/* Masks of interrupts at each interrupt level: */
-#define XCHAL_INTLEVEL1_MASK 0x0000000F
-#define XCHAL_INTLEVEL2_MASK 0x000000F0
-#define XCHAL_INTLEVEL3_MASK 0x00000F00
-#define XCHAL_INTLEVEL4_MASK 0x00007000
-#define XCHAL_INTLEVEL5_MASK 0x000F8000
-#define XCHAL_INTLEVEL6_MASK 0x00000000
-#define XCHAL_INTLEVEL7_MASK 0x00100000
-
-/* Masks of interrupts at each range 1..n of interrupt levels: */
-#define XCHAL_INTLEVEL1_ANDBELOW_MASK 0x0000000F
-#define XCHAL_INTLEVEL2_ANDBELOW_MASK 0x000000FF
-#define XCHAL_INTLEVEL3_ANDBELOW_MASK 0x00000FFF
-#define XCHAL_INTLEVEL4_ANDBELOW_MASK 0x00007FFF
-#define XCHAL_INTLEVEL5_ANDBELOW_MASK 0x000FFFFF
-#define XCHAL_INTLEVEL6_ANDBELOW_MASK 0x000FFFFF
-#define XCHAL_INTLEVEL7_ANDBELOW_MASK 0x001FFFFF
-
-/* Level of each interrupt: */
-#define XCHAL_INT0_LEVEL 1
-#define XCHAL_INT1_LEVEL 1
-#define XCHAL_INT2_LEVEL 1
-#define XCHAL_INT3_LEVEL 1
-
-#define XCHAL_INT4_LEVEL 2
-#define XCHAL_INT5_LEVEL 2
-#define XCHAL_INT6_LEVEL 2
-#define XCHAL_INT7_LEVEL 2
-
-#define XCHAL_INT8_LEVEL 3
-#define XCHAL_INT9_LEVEL 3
-#define XCHAL_INT10_LEVEL 3
-#define XCHAL_INT11_LEVEL 3
-
-#define XCHAL_INT12_LEVEL 4
-#define XCHAL_INT13_LEVEL 4
-#define XCHAL_INT14_LEVEL 4
-#define XCHAL_INT15_LEVEL 5
-
-#define XCHAL_INT16_LEVEL 5
-#define XCHAL_INT17_LEVEL 5
-#define XCHAL_INT18_LEVEL 5
-#define XCHAL_INT19_LEVEL 5
-
-#define XCHAL_INT20_LEVEL 7
-
-
-#define XCHAL_DEBUGLEVEL 6 /* debug interrupt level */
-#define XCHAL_HAVE_DEBUG_EXTERN_INT 1 /* OCD external db interrupt */
-#define XCHAL_NMILEVEL 7 /* NMI "level" (for use with
- EXCSAVE/EPS/EPC_n, RFI n) */
-
-/* Type of each interrupt: */
-#define XCHAL_INT0_TYPE XTHAL_INTTYPE_SOFTWARE
-#define XCHAL_INT1_TYPE XTHAL_INTTYPE_TIMER
-#define XCHAL_INT2_TYPE XTHAL_INTTYPE_EXTERN_LEVEL
-#define XCHAL_INT3_TYPE XTHAL_INTTYPE_SOFTWARE
-#define XCHAL_INT4_TYPE XTHAL_INTTYPE_SOFTWARE
-#define XCHAL_INT5_TYPE XTHAL_INTTYPE_TIMER
-#define XCHAL_INT6_TYPE XTHAL_INTTYPE_EXTERN_LEVEL
-#define XCHAL_INT7_TYPE XTHAL_INTTYPE_SOFTWARE
-#define XCHAL_INT8_TYPE XTHAL_INTTYPE_SOFTWARE
-#define XCHAL_INT9_TYPE XTHAL_INTTYPE_TIMER
-#define XCHAL_INT10_TYPE XTHAL_INTTYPE_EXTERN_LEVEL
-#define XCHAL_INT11_TYPE XTHAL_INTTYPE_SOFTWARE
-#define XCHAL_INT12_TYPE XTHAL_INTTYPE_SOFTWARE
-#define XCHAL_INT13_TYPE XTHAL_INTTYPE_EXTERN_LEVEL
-#define XCHAL_INT14_TYPE XTHAL_INTTYPE_SOFTWARE
-#define XCHAL_INT15_TYPE XTHAL_INTTYPE_SOFTWARE
-#define XCHAL_INT16_TYPE XTHAL_INTTYPE_EXTERN_LEVEL
-#define XCHAL_INT17_TYPE XTHAL_INTTYPE_EXTERN_LEVEL
-#define XCHAL_INT18_TYPE XTHAL_INTTYPE_EXTERN_LEVEL
-#define XCHAL_INT19_TYPE XTHAL_INTTYPE_SOFTWARE
-#define XCHAL_INT20_TYPE XTHAL_INTTYPE_NMI
-
-/* Masks of interrupts for each type of interrupt: */
-#define XCHAL_INTTYPE_MASK_UNCONFIGURED 0xFFE00000
-#define XCHAL_INTTYPE_MASK_SOFTWARE 0x0008D999
-#define XCHAL_INTTYPE_MASK_EXTERN_EDGE 0x00000000
-#define XCHAL_INTTYPE_MASK_EXTERN_LEVEL 0x00072444
-#define XCHAL_INTTYPE_MASK_TIMER 0x00000222
-#define XCHAL_INTTYPE_MASK_NMI 0x00100000
-#define XCHAL_INTTYPE_MASK_WRITE_ERROR 0x00000000
-#define XCHAL_INTTYPE_MASK_PROFILING 0x00000000
-
-/* Interrupt numbers assigned to specific interrupt sources: */
-#define XCHAL_TIMER0_INTERRUPT 1 /* CCOMPARE0 */
-#define XCHAL_TIMER1_INTERRUPT 5 /* CCOMPARE1 */
-#define XCHAL_TIMER2_INTERRUPT 9 /* CCOMPARE2 */
-#define XCHAL_TIMER3_INTERRUPT XTHAL_TIMER_UNCONFIGURED
-#define XCHAL_NMI_INTERRUPT 20 /* non-maskable interrupt */
-
-/* Interrupt numbers for levels at which only one interrupt is configured: */
-//#define XCHAL_INTLEVEL2_NUM 8
-//#define XCHAL_INTLEVEL4_NUM 12
-//#define XCHAL_INTLEVEL5_NUM 13
-#define XCHAL_INTLEVEL7_NUM 20
-/* (There are many interrupts each at level(s) 1, 3.) */
-
-
-/*
- * External interrupt mapping.
- * These macros describe how Xtensa processor interrupt numbers
- * (as numbered internally, eg. in INTERRUPT and INTENABLE registers)
- * map to external BInterrupt<n> pins, for those interrupts
- * configured as external (level-triggered, edge-triggered, or NMI).
- * See the Xtensa processor databook for more details.
- */
-
-/* Core interrupt numbers mapped to each EXTERNAL BInterrupt pin number: */
-#define XCHAL_EXTINT0_NUM 0 /* (intlevel 1) */
-#define XCHAL_EXTINT1_NUM 1 /* (intlevel 1) */
-#define XCHAL_EXTINT2_NUM 2 /* (intlevel 1) */
-#define XCHAL_EXTINT3_NUM 3 /* (intlevel 1) */
-#define XCHAL_EXTINT4_NUM 4 /* (intlevel 1) */
-#define XCHAL_EXTINT5_NUM 5 /* (intlevel 1) */
-#define XCHAL_EXTINT6_NUM 8 /* (intlevel 2) */
-#define XCHAL_EXTINT7_NUM 9 /* (intlevel 3) */
-#define XCHAL_EXTINT8_NUM 12 /* (intlevel 4) */
-#define XCHAL_EXTINT9_NUM 14 /* (intlevel 7) */
-#define XCHAL_EXTINT10_NUM 15 /* (intlevel 1) */
-#define XCHAL_EXTINT11_NUM 16 /* (intlevel 1) */
-#define XCHAL_EXTINT12_NUM 17 /* (intlevel 1) */
-#define XCHAL_EXTINT13_NUM 18 /* (intlevel 1) */
-#define XCHAL_EXTINT14_NUM 19 /* (intlevel 1) */
-#define XCHAL_EXTINT15_NUM 20 /* (intlevel 1) */
-#define XCHAL_EXTINT16_NUM 21 /* (intlevel 3) */
-/* EXTERNAL BInterrupt pin numbers mapped to each core interrupt number: */
-#define XCHAL_INT0_EXTNUM 0 /* (intlevel 1) */
-#define XCHAL_INT1_EXTNUM 1 /* (intlevel 1) */
-#define XCHAL_INT2_EXTNUM 2 /* (intlevel 1) */
-#define XCHAL_INT3_EXTNUM 3 /* (intlevel 1) */
-#define XCHAL_INT4_EXTNUM 4 /* (intlevel 1) */
-#define XCHAL_INT5_EXTNUM 5 /* (intlevel 1) */
-#define XCHAL_INT8_EXTNUM 6 /* (intlevel 2) */
-#define XCHAL_INT9_EXTNUM 7 /* (intlevel 3) */
-#define XCHAL_INT12_EXTNUM 8 /* (intlevel 4) */
-#define XCHAL_INT14_EXTNUM 9 /* (intlevel 7) */
-#define XCHAL_INT15_EXTNUM 10 /* (intlevel 1) */
-#define XCHAL_INT16_EXTNUM 11 /* (intlevel 1) */
-#define XCHAL_INT17_EXTNUM 12 /* (intlevel 1) */
-#define XCHAL_INT18_EXTNUM 13 /* (intlevel 1) */
-#define XCHAL_INT19_EXTNUM 14 /* (intlevel 1) */
-#define XCHAL_INT20_EXTNUM 15 /* (intlevel 1) */
-#define XCHAL_INT21_EXTNUM 16 /* (intlevel 3) */
-
-
-/*----------------------------------------------------------------------
- EXCEPTIONS and VECTORS
- ----------------------------------------------------------------------*/
-
-#define XCHAL_XEA_VERSION 2 /* Xtensa Exception Architecture
- number: 1 == XEA1 (old)
- 2 == XEA2 (new)
- 0 == XEAX (extern) or TX */
-#define XCHAL_HAVE_XEA1 0 /* Exception Architecture 1 */
-#define XCHAL_HAVE_XEA2 1 /* Exception Architecture 2 */
-#define XCHAL_HAVE_XEAX 0 /* External Exception Arch. */
-#define XCHAL_HAVE_EXCEPTIONS 1 /* exception option */
-#define XCHAL_HAVE_HALT 0 /* halt architecture option */
-#define XCHAL_HAVE_BOOTLOADER 0 /* boot loader (for TX) */
-#define XCHAL_HAVE_MEM_ECC_PARITY 1 /* local memory ECC/parity */
-#define XCHAL_HAVE_VECTOR_SELECT 1 /* relocatable vectors */
-#define XCHAL_HAVE_VECBASE 1 /* relocatable vectors */
-#define XCHAL_VECBASE_RESET_VADDR 0xBEFE0800 /* VECBASE reset value */
-#define XCHAL_VECBASE_RESET_PADDR 0xBEFE0800
-#define XCHAL_RESET_VECBASE_OVERLAP 0
-
-#define XCHAL_RESET_VECTOR0_VADDR 0xBEFE0000
-#define XCHAL_RESET_VECTOR0_PADDR 0xBEFE0000
-#define XCHAL_RESET_VECTOR1_VADDR 0xBE800000
-#define XCHAL_RESET_VECTOR1_PADDR 0xBE800000
-#define XCHAL_RESET_VECTOR_VADDR 0xBEFE0000
-#define XCHAL_RESET_VECTOR_PADDR 0xBEFE0000
-#define XCHAL_MEMERROR_VECTOR0_VADDR 0xBEFE0400
-#define XCHAL_MEMERROR_VECTOR0_PADDR 0xBEFE0400
-#define XCHAL_MEMERROR_VECTOR1_VADDR 0xBE800400
-#define XCHAL_MEMERROR_VECTOR1_PADDR 0xBE800400
-#define XCHAL_MEMERROR_VECTOR_VADDR 0xBEFE0400
-#define XCHAL_MEMERROR_VECTOR_PADDR 0xBEFE0400
-#define XCHAL_USER_VECOFS 0x00000340
-#define XCHAL_USER_VECTOR_VADDR 0xBEFE0B40
-#define XCHAL_USER_VECTOR_PADDR 0xBEFE0B40
-#define XCHAL_KERNEL_VECOFS 0x00000300
-#define XCHAL_KERNEL_VECTOR_VADDR 0xBEFE0B00
-#define XCHAL_KERNEL_VECTOR_PADDR 0xBEFE0B00
-#define XCHAL_DOUBLEEXC_VECOFS 0x000003C0
-#define XCHAL_DOUBLEEXC_VECTOR_VADDR 0xBEFE0BC0
-#define XCHAL_DOUBLEEXC_VECTOR_PADDR 0xBEFE0BC0
-#define XCHAL_WINDOW_OF4_VECOFS 0x00000000
-#define XCHAL_WINDOW_UF4_VECOFS 0x00000040
-#define XCHAL_WINDOW_OF8_VECOFS 0x00000080
-#define XCHAL_WINDOW_UF8_VECOFS 0x000000C0
-#define XCHAL_WINDOW_OF12_VECOFS 0x00000100
-#define XCHAL_WINDOW_UF12_VECOFS 0x00000140
-#define XCHAL_WINDOW_VECTORS_VADDR 0xBEFE0800
-#define XCHAL_WINDOW_VECTORS_PADDR 0xBEFE0800
-#define XCHAL_INTLEVEL2_VECOFS 0x00000180
-#define XCHAL_INTLEVEL2_VECTOR_VADDR 0xBEFE0980
-#define XCHAL_INTLEVEL2_VECTOR_PADDR 0xBEFE0980
-#define XCHAL_INTLEVEL3_VECOFS 0x000001C0
-#define XCHAL_INTLEVEL3_VECTOR_VADDR 0xBEFE09C0
-#define XCHAL_INTLEVEL3_VECTOR_PADDR 0xBEFE09C0
-#define XCHAL_INTLEVEL4_VECOFS 0x00000200
-#define XCHAL_INTLEVEL4_VECTOR_VADDR 0xBEFE0A00
-#define XCHAL_INTLEVEL4_VECTOR_PADDR 0xBEFE0A00
-#define XCHAL_INTLEVEL5_VECOFS 0x00000240
-#define XCHAL_INTLEVEL5_VECTOR_VADDR 0xBEFE0A40
-#define XCHAL_INTLEVEL5_VECTOR_PADDR 0xBEFE0A40
-#define XCHAL_INTLEVEL6_VECOFS 0x00000280
-#define XCHAL_INTLEVEL6_VECTOR_VADDR 0xBEFE0A80
-#define XCHAL_INTLEVEL6_VECTOR_PADDR 0xBEFE0A80
-#define XCHAL_DEBUG_VECOFS XCHAL_INTLEVEL6_VECOFS
-#define XCHAL_DEBUG_VECTOR_VADDR XCHAL_INTLEVEL6_VECTOR_VADDR
-#define XCHAL_DEBUG_VECTOR_PADDR XCHAL_INTLEVEL6_VECTOR_PADDR
-#define XCHAL_NMI_VECOFS 0x000002C0
-#define XCHAL_NMI_VECTOR_VADDR 0xBEFE0AC0
-#define XCHAL_NMI_VECTOR_PADDR 0xBEFE0AC0
-#define XCHAL_INTLEVEL7_VECOFS XCHAL_NMI_VECOFS
-#define XCHAL_INTLEVEL7_VECTOR_VADDR XCHAL_NMI_VECTOR_VADDR
-#define XCHAL_INTLEVEL7_VECTOR_PADDR XCHAL_NMI_VECTOR_PADDR
-
-
-/*----------------------------------------------------------------------
- DEBUG MODULE
- ----------------------------------------------------------------------*/
-
-/* Misc */
-#define XCHAL_HAVE_DEBUG_ERI 0 /* ERI to debug module */
-#define XCHAL_HAVE_DEBUG_APB 0 /* APB to debug module */
-#define XCHAL_HAVE_DEBUG_JTAG 1 /* JTAG to debug module */
-
-/* On-Chip Debug (OCD) */
-#define XCHAL_HAVE_OCD 1 /* OnChipDebug option */
-#define XCHAL_NUM_IBREAK 2 /* number of IBREAKn regs */
-#define XCHAL_NUM_DBREAK 2 /* number of DBREAKn regs */
-#define XCHAL_HAVE_OCD_DIR_ARRAY 1 /* faster OCD option (to LX4) */
-#define XCHAL_HAVE_OCD_LS32DDR 1 /* L32DDR/S32DDR (faster OCD) */
-
-/* TRAX (in core) */
-#define XCHAL_HAVE_TRAX 0 /* TRAX in debug module */
-#define XCHAL_TRAX_MEM_SIZE 0 /* TRAX memory size in bytes */
-#define XCHAL_TRAX_MEM_SHAREABLE 0 /* start/end regs; ready sig. */
-#define XCHAL_TRAX_ATB_WIDTH 0 /* ATB width (bits), 0=no ATB */
-#define XCHAL_TRAX_TIME_WIDTH 0 /* timestamp bitwidth, 0=none */
-
-/* Perf counters */
-#define XCHAL_NUM_PERF_COUNTERS 0 /* performance counters */
-
-
-/*----------------------------------------------------------------------
- MMU
- ----------------------------------------------------------------------*/
-
-/* See core-matmap.h header file for more details. */
-
-#define XCHAL_HAVE_TLBS 1 /* inverse of HAVE_CACHEATTR */
-#define XCHAL_HAVE_SPANNING_WAY 1 /* one way maps I+D 4GB vaddr */
-#define XCHAL_SPANNING_WAY 0 /* TLB spanning way number */
-#define XCHAL_HAVE_IDENTITY_MAP 0 /* vaddr == paddr always */
-#define XCHAL_HAVE_CACHEATTR 0 /* CACHEATTR register present */
-#define XCHAL_HAVE_MIMIC_CACHEATTR 0 /* region protection */
-#define XCHAL_HAVE_XLT_CACHEATTR 1 /* region prot. w/translation */
-#define XCHAL_HAVE_PTP_MMU 0 /* full MMU (with page table
- [autorefill] and protection)
- usable for an MMU-based OS */
-/* If none of the above last 4 are set, it's a custom TLB configuration. */
-
-#define XCHAL_MMU_ASID_BITS 0 /* number of bits in ASIDs */
-#define XCHAL_MMU_RINGS 1 /* number of rings (1..4) */
-#define XCHAL_MMU_RING_BITS 0 /* num of bits in RING field */
-
-#endif /* !XTENSA_HAL_NON_PRIVILEGED_ONLY */
-
-
-#endif /* _XTENSA_CORE_CONFIGURATION_H */
-
-#else
-
-#error "xcc should not use this header"
-
-#endif /* __XCC__ */
diff --git a/src/platform/apollolake/include/arch/xtensa/config/core-matmap.h b/src/platform/apollolake/include/arch/xtensa/config/core-matmap.h
deleted file mode 100644
index ad0f0d7..0000000
--- a/src/platform/apollolake/include/arch/xtensa/config/core-matmap.h
+++ /dev/null
@@ -1,320 +0,0 @@
-/*
- * xtensa/config/core-matmap.h -- Memory access and translation mapping
- * parameters (CHAL) of the Xtensa processor core configuration.
- *
- * If you are using Xtensa Tools, see <xtensa/config/core.h> (which includes
- * this file) for more details.
- *
- * In the Xtensa processor products released to date, all parameters
- * defined in this file are derivable (at least in theory) from
- * information contained in the core-isa.h header file.
- * In particular, the following core configuration parameters are relevant:
- * XCHAL_HAVE_CACHEATTR
- * XCHAL_HAVE_MIMIC_CACHEATTR
- * XCHAL_HAVE_XLT_CACHEATTR
- * XCHAL_HAVE_PTP_MMU
- * XCHAL_ITLB_ARF_ENTRIES_LOG2
- * XCHAL_DTLB_ARF_ENTRIES_LOG2
- * XCHAL_DCACHE_IS_WRITEBACK
- * XCHAL_ICACHE_SIZE (presence of I-cache)
- * XCHAL_DCACHE_SIZE (presence of D-cache)
- * XCHAL_HW_VERSION_MAJOR
- * XCHAL_HW_VERSION_MINOR
- */
-
-/* Customer ID=4313; Build=0x5483b; Copyright (c) 1999-2015 Tensilica Inc.
-
- Permission is hereby granted, free of charge, to any person obtaining
- a copy of this software and associated documentation files (the
- "Software"), to deal in the Software without restriction, including
- without limitation the rights to use, copy, modify, merge, publish,
- distribute, sublicense, and/or sell copies of the Software, and to
- permit persons to whom the Software is furnished to do so, subject to
- the following conditions:
-
- The above copyright notice and this permission notice shall be included
- in all copies or substantial portions of the Software.
-
- THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
- EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
- MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
- IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY
- CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
- TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
- SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. */
-
-#if !defined __XCC__
-
-#ifndef XTENSA_CONFIG_CORE_MATMAP_H
-#define XTENSA_CONFIG_CORE_MATMAP_H
-
-
-/*----------------------------------------------------------------------
- CACHE (MEMORY ACCESS) ATTRIBUTES
- ----------------------------------------------------------------------*/
-
-
-/* Cache Attribute encodings -- lists of access modes for each cache attribute: */
-#define XCHAL_FCA_LIST XTHAL_FAM_EXCEPTION XCHAL_SEP \
- XTHAL_FAM_CACHED XCHAL_SEP \
- XTHAL_FAM_BYPASS XCHAL_SEP \
- XTHAL_FAM_CACHED XCHAL_SEP \
- XTHAL_FAM_CACHED XCHAL_SEP \
- XTHAL_FAM_CACHED XCHAL_SEP \
- XTHAL_FAM_BYPASS XCHAL_SEP \
- XTHAL_FAM_EXCEPTION XCHAL_SEP \
- XTHAL_FAM_EXCEPTION XCHAL_SEP \
- XTHAL_FAM_EXCEPTION XCHAL_SEP \
- XTHAL_FAM_EXCEPTION XCHAL_SEP \
- XTHAL_FAM_EXCEPTION XCHAL_SEP \
- XTHAL_FAM_EXCEPTION XCHAL_SEP \
- XTHAL_FAM_EXCEPTION XCHAL_SEP \
- XTHAL_FAM_EXCEPTION XCHAL_SEP \
- XTHAL_FAM_EXCEPTION
-#define XCHAL_LCA_LIST XTHAL_LAM_CACHED_NOALLOC XCHAL_SEP \
- XTHAL_LAM_CACHED XCHAL_SEP \
- XTHAL_LAM_BYPASSG XCHAL_SEP \
- XTHAL_LAM_EXCEPTION XCHAL_SEP \
- XTHAL_LAM_CACHED XCHAL_SEP \
- XTHAL_LAM_CACHED XCHAL_SEP \
- XTHAL_LAM_BYPASSG XCHAL_SEP \
- XTHAL_LAM_EXCEPTION XCHAL_SEP \
- XTHAL_LAM_EXCEPTION XCHAL_SEP \
- XTHAL_LAM_EXCEPTION XCHAL_SEP \
- XTHAL_LAM_EXCEPTION XCHAL_SEP \
- XTHAL_LAM_EXCEPTION XCHAL_SEP \
- XTHAL_LAM_EXCEPTION XCHAL_SEP \
- XTHAL_LAM_EXCEPTION XCHAL_SEP \
- XTHAL_LAM_ISOLATE XCHAL_SEP \
- XTHAL_LAM_EXCEPTION
-#define XCHAL_SCA_LIST XTHAL_SAM_WRITETHRU XCHAL_SEP \
- XTHAL_SAM_WRITETHRU XCHAL_SEP \
- XTHAL_SAM_BYPASS XCHAL_SEP \
- XTHAL_SAM_EXCEPTION XCHAL_SEP \
- XTHAL_SAM_WRITEBACK XCHAL_SEP \
- XTHAL_SAM_WRITEBACK_NOALLOC XCHAL_SEP \
- XTHAL_SAM_BYPASS XCHAL_SEP \
- XTHAL_SAM_EXCEPTION XCHAL_SEP \
- XTHAL_SAM_EXCEPTION XCHAL_SEP \
- XTHAL_SAM_EXCEPTION XCHAL_SEP \
- XTHAL_SAM_EXCEPTION XCHAL_SEP \
- XTHAL_SAM_EXCEPTION XCHAL_SEP \
- XTHAL_SAM_EXCEPTION XCHAL_SEP \
- XTHAL_SAM_EXCEPTION XCHAL_SEP \
- XTHAL_SAM_ISOLATE XCHAL_SEP \
- XTHAL_SAM_EXCEPTION
-
-
-/*
- * Specific encoded cache attribute values of general interest.
- * If a specific cache mode is not available, the closest available
- * one is returned instead (eg. writethru instead of writeback,
- * bypass instead of writethru).
- */
-#define XCHAL_CA_BYPASS 2 /* cache disabled (bypassed) mode */
-#define XCHAL_CA_BYPASSBUF 6 /* cache disabled (bypassed) bufferable mode */
-#define XCHAL_CA_WRITETHRU 1 /* cache enabled (write-through) mode */
-#define XCHAL_CA_WRITEBACK 4 /* cache enabled (write-back) mode */
-#define XCHAL_HAVE_CA_WRITEBACK_NOALLOC 1 /* write-back no-allocate availability */
-#define XCHAL_CA_WRITEBACK_NOALLOC 5 /* cache enabled (write-back no-allocate) mode */
-#define XCHAL_CA_ILLEGAL 15 /* no access allowed (all cause exceptions) mode */
-#define XCHAL_CA_ISOLATE 14 /* cache isolate (accesses go to cache not memory) mode */
-
-
-/*----------------------------------------------------------------------
- MMU
- ----------------------------------------------------------------------*/
-
-/*
- * General notes on MMU parameters.
- *
- * Terminology:
- * ASID = address-space ID (acts as an "extension" of virtual addresses)
- * VPN = virtual page number
- * PPN = physical page number
- * CA = encoded cache attribute (access modes)
- * TLB = translation look-aside buffer (term is stretched somewhat here)
- * I = instruction (fetch accesses)
- * D = data (load and store accesses)
- * way = each TLB (ITLB and DTLB) consists of a number of "ways"
- * that simultaneously match the virtual address of an access;
- * a TLB successfully translates a virtual address if exactly
- * one way matches the vaddr; if none match, it is a miss;
- * if multiple match, one gets a "multihit" exception;
- * each way can be independently configured in terms of number of
- * entries, page sizes, which fields are writable or constant, etc.
- * set = group of contiguous ways with exactly identical parameters
- * ARF = auto-refill; hardware services a 1st-level miss by loading a PTE
- * from the page table and storing it in one of the auto-refill ways;
- * if this PTE load also misses, a miss exception is posted for s/w.
- * min-wired = a "min-wired" way can be used to map a single (minimum-sized)
- * page arbitrarily under program control; it has a single entry,
- * is non-auto-refill (some other way(s) must be auto-refill),
- * all its fields (VPN, PPN, ASID, CA) are all writable, and it
- * supports the XCHAL_MMU_MIN_PTE_PAGE_SIZE page size (a current
- * restriction is that this be the only page size it supports).
- *
- * TLB way entries are virtually indexed.
- * TLB ways that support multiple page sizes:
- * - must have all writable VPN and PPN fields;
- * - can only use one page size at any given time (eg. setup at startup),
- * selected by the respective ITLBCFG or DTLBCFG special register,
- * whose bits n*4+3 .. n*4 index the list of page sizes for way n
- * (XCHAL_xTLB_SETm_PAGESZ_LOG2_LIST for set m corresponding to way n);
- * this list may be sparse for auto-refill ways because auto-refill
- * ways have independent lists of supported page sizes sharing a
- * common encoding with PTE entries; the encoding is the index into
- * this list; unsupported sizes for a given way are zero in the list;
- * selecting unsupported sizes results in undefined hardware behaviour;
- * - is only possible for ways 0 thru 7 (due to ITLBCFG/DTLBCFG definition).
- */
-
-#define XCHAL_MMU_ASID_INVALID 0 /* ASID value indicating invalid address space */
-#define XCHAL_MMU_ASID_KERNEL 0 /* ASID value indicating kernel (ring 0) address space */
-#define XCHAL_MMU_SR_BITS 0 /* number of size-restriction bits supported */
-#define XCHAL_MMU_CA_BITS 4 /* number of bits needed to hold cache attribute encoding */
-#define XCHAL_MMU_MAX_PTE_PAGE_SIZE 29 /* max page size in a PTE structure (log2) */
-#define XCHAL_MMU_MIN_PTE_PAGE_SIZE 29 /* min page size in a PTE structure (log2) */
-
-
-/*** Instruction TLB: ***/
-
-#define XCHAL_ITLB_WAY_BITS 0 /* number of bits holding the ways */
-#define XCHAL_ITLB_WAYS 1 /* number of ways (n-way set-associative TLB) */
-#define XCHAL_ITLB_ARF_WAYS 0 /* number of auto-refill ways */
-#define XCHAL_ITLB_SETS 1 /* number of sets (groups of ways with identical settings) */
-
-/* Way set to which each way belongs: */
-#define XCHAL_ITLB_WAY0_SET 0
-
-/* Ways sets that are used by hardware auto-refill (ARF): */
-#define XCHAL_ITLB_ARF_SETS 0 /* number of auto-refill sets */
-
-/* Way sets that are "min-wired" (see terminology comment above): */
-#define XCHAL_ITLB_MINWIRED_SETS 0 /* number of "min-wired" sets */
-
-
-/* ITLB way set 0 (group of ways 0 thru 0): */
-#define XCHAL_ITLB_SET0_WAY 0 /* index of first way in this way set */
-#define XCHAL_ITLB_SET0_WAYS 1 /* number of (contiguous) ways in this way set */
-#define XCHAL_ITLB_SET0_ENTRIES_LOG2 3 /* log2(number of entries in this way) */
-#define XCHAL_ITLB_SET0_ENTRIES 8 /* number of entries in this way (always a power of 2) */
-#define XCHAL_ITLB_SET0_ARF 0 /* 1=autorefill by h/w, 0=non-autorefill (wired/constant/static) */
-#define XCHAL_ITLB_SET0_PAGESIZES 1 /* number of supported page sizes in this way */
-#define XCHAL_ITLB_SET0_PAGESZ_BITS 0 /* number of bits to encode the page size */
-#define XCHAL_ITLB_SET0_PAGESZ_LOG2_MIN 29 /* log2(minimum supported page size) */
-#define XCHAL_ITLB_SET0_PAGESZ_LOG2_MAX 29 /* log2(maximum supported page size) */
-#define XCHAL_ITLB_SET0_PAGESZ_LOG2_LIST 29 /* list of log2(page size)s, separated by XCHAL_SEP;
- 2^PAGESZ_BITS entries in list, unsupported entries are zero */
-#define XCHAL_ITLB_SET0_ASID_CONSTMASK 0 /* constant ASID bits; 0 if all writable */
-#define XCHAL_ITLB_SET0_VPN_CONSTMASK 0x00000000 /* constant VPN bits, not including entry index bits; 0 if all writable */
-#define XCHAL_ITLB_SET0_PPN_CONSTMASK 0xE0000000 /* constant PPN bits, including entry index bits; 0 if all writable */
-#define XCHAL_ITLB_SET0_CA_CONSTMASK 0 /* constant CA bits; 0 if all writable */
-#define XCHAL_ITLB_SET0_ASID_RESET 0 /* 1 if ASID reset values defined (and all writable); 0 otherwise */
-#define XCHAL_ITLB_SET0_VPN_RESET 0 /* 1 if VPN reset values defined (and all writable); 0 otherwise */
-#define XCHAL_ITLB_SET0_PPN_RESET 0 /* 1 if PPN reset values defined (and all writable); 0 otherwise */
-#define XCHAL_ITLB_SET0_CA_RESET 1 /* 1 if CA reset values defined (and all writable); 0 otherwise */
-/* Constant VPN values for each entry of ITLB way set 0 (because VPN_CONSTMASK is non-zero): */
-#define XCHAL_ITLB_SET0_E0_VPN_CONST 0x00000000
-#define XCHAL_ITLB_SET0_E1_VPN_CONST 0x20000000
-#define XCHAL_ITLB_SET0_E2_VPN_CONST 0x40000000
-#define XCHAL_ITLB_SET0_E3_VPN_CONST 0x60000000
-#define XCHAL_ITLB_SET0_E4_VPN_CONST 0x80000000
-#define XCHAL_ITLB_SET0_E5_VPN_CONST 0xA0000000
-#define XCHAL_ITLB_SET0_E6_VPN_CONST 0xC0000000
-#define XCHAL_ITLB_SET0_E7_VPN_CONST 0xE0000000
-/* Constant PPN values for each entry of ITLB way set 0 (because PPN_CONSTMASK is non-zero): */
-#define XCHAL_ITLB_SET0_E0_PPN_CONST 0x00000000
-#define XCHAL_ITLB_SET0_E1_PPN_CONST 0x20000000
-#define XCHAL_ITLB_SET0_E2_PPN_CONST 0x40000000
-#define XCHAL_ITLB_SET0_E3_PPN_CONST 0x60000000
-#define XCHAL_ITLB_SET0_E4_PPN_CONST 0x80000000
-#define XCHAL_ITLB_SET0_E5_PPN_CONST 0xA0000000
-#define XCHAL_ITLB_SET0_E6_PPN_CONST 0xC0000000
-#define XCHAL_ITLB_SET0_E7_PPN_CONST 0xE0000000
-/* Reset CA values for each entry of ITLB way set 0 (because SET0_CA_RESET is non-zero): */
-#define XCHAL_ITLB_SET0_E0_CA_RESET 0x02
-#define XCHAL_ITLB_SET0_E1_CA_RESET 0x02
-#define XCHAL_ITLB_SET0_E2_CA_RESET 0x02
-#define XCHAL_ITLB_SET0_E3_CA_RESET 0x02
-#define XCHAL_ITLB_SET0_E4_CA_RESET 0x02
-#define XCHAL_ITLB_SET0_E5_CA_RESET 0x02
-#define XCHAL_ITLB_SET0_E6_CA_RESET 0x02
-#define XCHAL_ITLB_SET0_E7_CA_RESET 0x02
-
-
-/*** Data TLB: ***/
-
-#define XCHAL_DTLB_WAY_BITS 0 /* number of bits holding the ways */
-#define XCHAL_DTLB_WAYS 1 /* number of ways (n-way set-associative TLB) */
-#define XCHAL_DTLB_ARF_WAYS 0 /* number of auto-refill ways */
-#define XCHAL_DTLB_SETS 1 /* number of sets (groups of ways with identical settings) */
-
-/* Way set to which each way belongs: */
-#define XCHAL_DTLB_WAY0_SET 0
-
-/* Ways sets that are used by hardware auto-refill (ARF): */
-#define XCHAL_DTLB_ARF_SETS 0 /* number of auto-refill sets */
-
-/* Way sets that are "min-wired" (see terminology comment above): */
-#define XCHAL_DTLB_MINWIRED_SETS 0 /* number of "min-wired" sets */
-
-
-/* DTLB way set 0 (group of ways 0 thru 0): */
-#define XCHAL_DTLB_SET0_WAY 0 /* index of first way in this way set */
-#define XCHAL_DTLB_SET0_WAYS 1 /* number of (contiguous) ways in this way set */
-#define XCHAL_DTLB_SET0_ENTRIES_LOG2 3 /* log2(number of entries in this way) */
-#define XCHAL_DTLB_SET0_ENTRIES 8 /* number of entries in this way (always a power of 2) */
-#define XCHAL_DTLB_SET0_ARF 0 /* 1=autorefill by h/w, 0=non-autorefill (wired/constant/static) */
-#define XCHAL_DTLB_SET0_PAGESIZES 1 /* number of supported page sizes in this way */
-#define XCHAL_DTLB_SET0_PAGESZ_BITS 0 /* number of bits to encode the page size */
-#define XCHAL_DTLB_SET0_PAGESZ_LOG2_MIN 29 /* log2(minimum supported page size) */
-#define XCHAL_DTLB_SET0_PAGESZ_LOG2_MAX 29 /* log2(maximum supported page size) */
-#define XCHAL_DTLB_SET0_PAGESZ_LOG2_LIST 29 /* list of log2(page size)s, separated by XCHAL_SEP;
- 2^PAGESZ_BITS entries in list, unsupported entries are zero */
-#define XCHAL_DTLB_SET0_ASID_CONSTMASK 0 /* constant ASID bits; 0 if all writable */
-#define XCHAL_DTLB_SET0_VPN_CONSTMASK 0x00000000 /* constant VPN bits, not including entry index bits; 0 if all writable */
-#define XCHAL_DTLB_SET0_PPN_CONSTMASK 0xE0000000 /* constant PPN bits, including entry index bits; 0 if all writable */
-#define XCHAL_DTLB_SET0_CA_CONSTMASK 0 /* constant CA bits; 0 if all writable */
-#define XCHAL_DTLB_SET0_ASID_RESET 0 /* 1 if ASID reset values defined (and all writable); 0 otherwise */
-#define XCHAL_DTLB_SET0_VPN_RESET 0 /* 1 if VPN reset values defined (and all writable); 0 otherwise */
-#define XCHAL_DTLB_SET0_PPN_RESET 0 /* 1 if PPN reset values defined (and all writable); 0 otherwise */
-#define XCHAL_DTLB_SET0_CA_RESET 1 /* 1 if CA reset values defined (and all writable); 0 otherwise */
-/* Constant VPN values for each entry of DTLB way set 0 (because VPN_CONSTMASK is non-zero): */
-#define XCHAL_DTLB_SET0_E0_VPN_CONST 0x00000000
-#define XCHAL_DTLB_SET0_E1_VPN_CONST 0x20000000
-#define XCHAL_DTLB_SET0_E2_VPN_CONST 0x40000000
-#define XCHAL_DTLB_SET0_E3_VPN_CONST 0x60000000
-#define XCHAL_DTLB_SET0_E4_VPN_CONST 0x80000000
-#define XCHAL_DTLB_SET0_E5_VPN_CONST 0xA0000000
-#define XCHAL_DTLB_SET0_E6_VPN_CONST 0xC0000000
-#define XCHAL_DTLB_SET0_E7_VPN_CONST 0xE0000000
-/* Constant PPN values for each entry of DTLB way set 0 (because PPN_CONSTMASK is non-zero): */
-#define XCHAL_DTLB_SET0_E0_PPN_CONST 0x00000000
-#define XCHAL_DTLB_SET0_E1_PPN_CONST 0x20000000
-#define XCHAL_DTLB_SET0_E2_PPN_CONST 0x40000000
-#define XCHAL_DTLB_SET0_E3_PPN_CONST 0x60000000
-#define XCHAL_DTLB_SET0_E4_PPN_CONST 0x80000000
-#define XCHAL_DTLB_SET0_E5_PPN_CONST 0xA0000000
-#define XCHAL_DTLB_SET0_E6_PPN_CONST 0xC0000000
-#define XCHAL_DTLB_SET0_E7_PPN_CONST 0xE0000000
-/* Reset CA values for each entry of DTLB way set 0 (because SET0_CA_RESET is non-zero): */
-#define XCHAL_DTLB_SET0_E0_CA_RESET 0x02
-#define XCHAL_DTLB_SET0_E1_CA_RESET 0x02
-#define XCHAL_DTLB_SET0_E2_CA_RESET 0x02
-#define XCHAL_DTLB_SET0_E3_CA_RESET 0x02
-#define XCHAL_DTLB_SET0_E4_CA_RESET 0x02
-#define XCHAL_DTLB_SET0_E5_CA_RESET 0x02
-#define XCHAL_DTLB_SET0_E6_CA_RESET 0x02
-#define XCHAL_DTLB_SET0_E7_CA_RESET 0x02
-
-
-
-
-#endif /*XTENSA_CONFIG_CORE_MATMAP_H*/
-
-#else
-
-#error "xcc should not use this header"
-
-#endif /* __XCC__ */
diff --git a/src/platform/apollolake/include/arch/xtensa/config/defs.h b/src/platform/apollolake/include/arch/xtensa/config/defs.h
deleted file mode 100644
index c2ef1d9..0000000
--- a/src/platform/apollolake/include/arch/xtensa/config/defs.h
+++ /dev/null
@@ -1,46 +0,0 @@
-/* Definitions for Xtensa instructions, types, and protos. */
-
-/* Customer ID=4313; Build=0x5483b; Copyright (c) 2003-2004 Tensilica Inc.
-
- Permission is hereby granted, free of charge, to any person obtaining
- a copy of this software and associated documentation files (the
- "Software"), to deal in the Software without restriction, including
- without limitation the rights to use, copy, modify, merge, publish,
- distribute, sublicense, and/or sell copies of the Software, and to
- permit persons to whom the Software is furnished to do so, subject to
- the following conditions:
-
- The above copyright notice and this permission notice shall be included
- in all copies or substantial portions of the Software.
-
- THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
- EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
- MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
- IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY
- CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
- TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
- SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. */
-
-/* NOTE: This file exists only for backward compatibility with T1050
- and earlier Xtensa releases. It includes only a subset of the
- available header files. */
-
-#if !defined __XCC__
-
-#ifndef _XTENSA_BASE_HEADER
-#define _XTENSA_BASE_HEADER
-
-#ifdef __XTENSA__
-
-#include <xtensa/tie/xt_core.h>
-#include <xtensa/tie/xt_misc.h>
-#include <xtensa/tie/xt_booleans.h>
-
-#endif /* __XTENSA__ */
-#endif /* !_XTENSA_BASE_HEADER */
-
-#else
-
-#error "xcc should not use this header"
-
-#endif /* __XCC__ */
diff --git a/src/platform/apollolake/include/arch/xtensa/config/specreg.h b/src/platform/apollolake/include/arch/xtensa/config/specreg.h
deleted file mode 100644
index c99cda6..0000000
--- a/src/platform/apollolake/include/arch/xtensa/config/specreg.h
+++ /dev/null
@@ -1,114 +0,0 @@
-/*
- * Xtensa Special Register symbolic names
- */
-
-/* $Id: //depot/rel/Eaglenest/Xtensa/SWConfig/hal/specreg.h.tpp#1 $ */
-
-/* Customer ID=4313; Build=0x5483b; Copyright (c) 1998-2002 Tensilica Inc.
-
- Permission is hereby granted, free of charge, to any person obtaining
- a copy of this software and associated documentation files (the
- "Software"), to deal in the Software without restriction, including
- without limitation the rights to use, copy, modify, merge, publish,
- distribute, sublicense, and/or sell copies of the Software, and to
- permit persons to whom the Software is furnished to do so, subject to
- the following conditions:
-
- The above copyright notice and this permission notice shall be included
- in all copies or substantial portions of the Software.
-
- THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
- EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
- MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
- IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY
- CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
- TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
- SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. */
-
-#if !defined __XCC__
-
-#ifndef XTENSA_SPECREG_H
-#define XTENSA_SPECREG_H
-
-/* Include these special register bitfield definitions, for historical reasons: */
-#include <xtensa/corebits.h>
-
-
-/* Special registers: */
-#define LBEG 0
-#define LEND 1
-#define LCOUNT 2
-#define SAR 3
-#define BR 4
-#define SCOMPARE1 12
-#define WINDOWBASE 72
-#define WINDOWSTART 73
-#define IBREAKENABLE 96
-#define ATOMCTL 99
-#define DDR 104
-#define IBREAKA_0 128
-#define IBREAKA_1 129
-#define DBREAKA_0 144
-#define DBREAKA_1 145
-#define DBREAKC_0 160
-#define DBREAKC_1 161
-#define EPC_1 177
-#define EPC_2 178
-#define EPC_3 179
-#define EPC_4 180
-#define EPC_5 181
-#define EPC_6 182
-#define EPC_7 183
-#define DEPC 192
-#define EPS_2 194
-#define EPS_3 195
-#define EPS_4 196
-#define EPS_5 197
-#define EPS_6 198
-#define EPS_7 199
-#define EXCSAVE_1 209
-#define EXCSAVE_2 210
-#define EXCSAVE_3 211
-#define EXCSAVE_4 212
-#define EXCSAVE_5 213
-#define EXCSAVE_6 214
-#define EXCSAVE_7 215
-#define CPENABLE 224
-#define INTERRUPT 226
-#define INTENABLE 228
-#define PS 230
-#define VECBASE 231
-#define EXCCAUSE 232
-#define DEBUGCAUSE 233
-#define CCOUNT 234
-#define PRID 235
-#define ICOUNT 236
-#define ICOUNTLEVEL 237
-#define EXCVADDR 238
-#define CCOMPARE_0 240
-#define CCOMPARE_1 241
-#define CCOMPARE_2 242
-#define MISC_REG_0 244
-#define MISC_REG_1 245
-
-/* Special cases (bases of special register series): */
-#define IBREAKA 128
-#define DBREAKA 144
-#define DBREAKC 160
-#define EPC 176
-#define EPS 192
-#define EXCSAVE 208
-#define CCOMPARE 240
-
-/* Special names for read-only and write-only interrupt registers: */
-#define INTREAD 226
-#define INTSET 226
-#define INTCLEAR 227
-
-#endif /* XTENSA_SPECREG_H */
-
-#else
-
-#error "xcc should not use this header"
-
-#endif /* __XCC__ */
diff --git a/src/platform/apollolake/include/arch/xtensa/config/system.h b/src/platform/apollolake/include/arch/xtensa/config/system.h
deleted file mode 100644
index f1fd8a0..0000000
--- a/src/platform/apollolake/include/arch/xtensa/config/system.h
+++ /dev/null
@@ -1,278 +0,0 @@
-/*
- * xtensa/config/system.h -- HAL definitions that are dependent on SYSTEM configuration
- *
- * NOTE: The location and contents of this file are highly subject to change.
- *
- * Source for configuration-independent binaries (which link in a
- * configuration-specific HAL library) must NEVER include this file.
- * The HAL itself has historically included this file in some instances,
- * but this is not appropriate either, because the HAL is meant to be
- * core-specific but system independent.
- */
-
-/* Customer ID=4313; Build=0x5483b; Copyright (c) 2000-2010 Tensilica Inc.
-
- Permission is hereby granted, free of charge, to any person obtaining
- a copy of this software and associated documentation files (the
- "Software"), to deal in the Software without restriction, including
- without limitation the rights to use, copy, modify, merge, publish,
- distribute, sublicense, and/or sell copies of the Software, and to
- permit persons to whom the Software is furnished to do so, subject to
- the following conditions:
-
- The above copyright notice and this permission notice shall be included
- in all copies or substantial portions of the Software.
-
- THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
- EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
- MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
- IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY
- CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
- TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
- SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. */
-
-#if !defined __XCC__
-
-#ifndef XTENSA_CONFIG_SYSTEM_H
-#define XTENSA_CONFIG_SYSTEM_H
-
-/*#include <xtensa/hal.h>*/
-
-
-
-/*----------------------------------------------------------------------
- CONFIGURED SOFTWARE OPTIONS
- ----------------------------------------------------------------------*/
-
-#define XSHAL_USE_ABSOLUTE_LITERALS 0 /* (sw-only option, whether software uses absolute literals) */
-#define XSHAL_HAVE_TEXT_SECTION_LITERALS 1 /* Set if there is some memory that allows both code and literals. */
-
-#define XSHAL_ABI XTHAL_ABI_CALL0 /* (sw-only option, selected ABI) */
-/* The above maps to one of the following constants: */
-#define XTHAL_ABI_WINDOWED 0
-#define XTHAL_ABI_CALL0 1
-/* Alternatives: */
-/*#define XSHAL_WINDOWED_ABI 1*/ /* set if windowed ABI selected */
-/*#define XSHAL_CALL0_ABI 0*/ /* set if call0 ABI selected */
-
-#define XSHAL_CLIB XTHAL_CLIB_NEWLIB /* (sw-only option, selected C library) */
-/* The above maps to one of the following constants: */
-#define XTHAL_CLIB_NEWLIB 0
-#define XTHAL_CLIB_UCLIBC 1
-#define XTHAL_CLIB_XCLIB 2
-/* Alternatives: */
-/*#define XSHAL_NEWLIB 1*/ /* set if newlib C library selected */
-/*#define XSHAL_UCLIBC 0*/ /* set if uCLibC C library selected */
-/*#define XSHAL_XCLIB 0*/ /* set if Xtensa C library selected */
-
-#define XSHAL_USE_FLOATING_POINT 1
-
-#define XSHAL_FLOATING_POINT_ABI 0
-
-/*----------------------------------------------------------------------
- DEVICE ADDRESSES
- ----------------------------------------------------------------------*/
-
-/*
- * Strange place to find these, but the configuration GUI
- * allows moving these around to account for various core
- * configurations. Specific boards (and their BSP software)
- * will have specific meanings for these components.
- */
-
-/* I/O Block areas: */
-#define XSHAL_IOBLOCK_CACHED_VADDR 0x70000000
-#define XSHAL_IOBLOCK_CACHED_PADDR 0x70000000
-#define XSHAL_IOBLOCK_CACHED_SIZE 0x0E000000
-
-#define XSHAL_IOBLOCK_BYPASS_VADDR 0x90000000
-#define XSHAL_IOBLOCK_BYPASS_PADDR 0x90000000
-#define XSHAL_IOBLOCK_BYPASS_SIZE 0x0E000000
-
-/* System ROM: */
-#define XSHAL_ROM_VADDR 0x50000000
-#define XSHAL_ROM_PADDR 0x50000000
-#define XSHAL_ROM_SIZE 0x01000000
-/* Largest available area (free of vectors): */
-#define XSHAL_ROM_AVAIL_VADDR 0x50000300
-#define XSHAL_ROM_AVAIL_VSIZE 0x00FFFD00
-
-/* System RAM: */
-#define XSHAL_RAM_VADDR 0x60000000
-#define XSHAL_RAM_PADDR 0x60000000
-#define XSHAL_RAM_VSIZE 0x04000000
-#define XSHAL_RAM_PSIZE 0x04000000
-#define XSHAL_RAM_SIZE XSHAL_RAM_PSIZE
-/* Largest available area (free of vectors): */
-#define XSHAL_RAM_AVAIL_VADDR 0x60000400
-#define XSHAL_RAM_AVAIL_VSIZE 0x03FFFC00
-
-/*
- * Shadow system RAM (same device as system RAM, at different address).
- * (Emulation boards need this for the SONIC Ethernet driver
- * when data caches are configured for writeback mode.)
- * NOTE: on full MMU configs, this points to the BYPASS virtual address
- * of system RAM, ie. is the same as XSHAL_RAM_* except that virtual
- * addresses are viewed through the BYPASS static map rather than
- * the CACHED static map.
- */
-#define XSHAL_RAM_BYPASS_VADDR 0xA0000000
-#define XSHAL_RAM_BYPASS_PADDR 0xA0000000
-#define XSHAL_RAM_BYPASS_PSIZE 0x04000000
-
-/* Alternate system RAM (different device than system RAM): */
-/*#define XSHAL_ALTRAM_[VP]ADDR ...not configured...*/
-/*#define XSHAL_ALTRAM_SIZE ...not configured...*/
-
-/* Some available location in which to place devices in a simulation (eg. XTMP): */
-#define XSHAL_SIMIO_CACHED_VADDR 0xC0000000
-#define XSHAL_SIMIO_BYPASS_VADDR 0xC0000000
-#define XSHAL_SIMIO_PADDR 0xC0000000
-#define XSHAL_SIMIO_SIZE 0x20000000
-
-
-/*----------------------------------------------------------------------
- * For use by reference testbench exit and diagnostic routines.
- */
-#define XSHAL_MAGIC_EXIT 0x0
-
-/*----------------------------------------------------------------------
- * DEVICE-ADDRESS DEPENDENT...
- *
- * Values written to CACHEATTR special register (or its equivalent)
- * to enable and disable caches in various modes.
- *----------------------------------------------------------------------*/
-
-/*----------------------------------------------------------------------
- BACKWARD COMPATIBILITY ...
- ----------------------------------------------------------------------*/
-
-/*
- * NOTE: the following two macros are DEPRECATED. Use the latter
- * board-specific macros instead, which are specially tuned for the
- * particular target environments' memory maps.
- */
-#define XSHAL_CACHEATTR_BYPASS XSHAL_XT2000_CACHEATTR_BYPASS /* disable caches in bypass mode */
-#define XSHAL_CACHEATTR_DEFAULT XSHAL_XT2000_CACHEATTR_DEFAULT /* default setting to enable caches (no writeback!) */
-
-/*----------------------------------------------------------------------
- GENERIC
- ----------------------------------------------------------------------*/
-
-/* For the following, a 512MB region is used if it contains a system (PIF) RAM,
- * system (PIF) ROM, local memory, or XLMI. */
-
-/* These set any unused 512MB region to cache-BYPASS attribute: */
-#define XSHAL_ALLVALID_CACHEATTR_WRITEBACK 0x22224442 /* enable caches in write-back mode */
-#define XSHAL_ALLVALID_CACHEATTR_WRITEALLOC 0x22221112 /* enable caches in write-allocate mode */
-#define XSHAL_ALLVALID_CACHEATTR_WRITETHRU 0x22221112 /* enable caches in write-through mode */
-#define XSHAL_ALLVALID_CACHEATTR_BYPASS 0x22222222 /* disable caches in bypass mode */
-#define XSHAL_ALLVALID_CACHEATTR_DEFAULT XSHAL_ALLVALID_CACHEATTR_WRITEBACK /* default setting to enable caches */
-
-/* These set any unused 512MB region to ILLEGAL attribute: */
-#define XSHAL_STRICT_CACHEATTR_WRITEBACK 0xFFFF444F /* enable caches in write-back mode */
-#define XSHAL_STRICT_CACHEATTR_WRITEALLOC 0xFFFF111F /* enable caches in write-allocate mode */
-#define XSHAL_STRICT_CACHEATTR_WRITETHRU 0xFFFF111F /* enable caches in write-through mode */
-#define XSHAL_STRICT_CACHEATTR_BYPASS 0xFFFF222F /* disable caches in bypass mode */
-#define XSHAL_STRICT_CACHEATTR_DEFAULT XSHAL_STRICT_CACHEATTR_WRITEBACK /* default setting to enable caches */
-
-/* These set the first 512MB, if unused, to ILLEGAL attribute to help catch
- * NULL-pointer dereference bugs; all other unused 512MB regions are set
- * to cache-BYPASS attribute: */
-#define XSHAL_TRAPNULL_CACHEATTR_WRITEBACK 0x2222444F /* enable caches in write-back mode */
-#define XSHAL_TRAPNULL_CACHEATTR_WRITEALLOC 0x2222111F /* enable caches in write-allocate mode */
-#define XSHAL_TRAPNULL_CACHEATTR_WRITETHRU 0x2222111F /* enable caches in write-through mode */
-#define XSHAL_TRAPNULL_CACHEATTR_BYPASS 0x2222222F /* disable caches in bypass mode */
-#define XSHAL_TRAPNULL_CACHEATTR_DEFAULT XSHAL_TRAPNULL_CACHEATTR_WRITEBACK /* default setting to enable caches */
-
-/*----------------------------------------------------------------------
- ISS (Instruction Set Simulator) SPECIFIC ...
- ----------------------------------------------------------------------*/
-
-/* For now, ISS defaults to the TRAPNULL settings: */
-#define XSHAL_ISS_CACHEATTR_WRITEBACK XSHAL_TRAPNULL_CACHEATTR_WRITEBACK
-#define XSHAL_ISS_CACHEATTR_WRITEALLOC XSHAL_TRAPNULL_CACHEATTR_WRITEALLOC
-#define XSHAL_ISS_CACHEATTR_WRITETHRU XSHAL_TRAPNULL_CACHEATTR_WRITETHRU
-#define XSHAL_ISS_CACHEATTR_BYPASS XSHAL_TRAPNULL_CACHEATTR_BYPASS
-#define XSHAL_ISS_CACHEATTR_DEFAULT XSHAL_TRAPNULL_CACHEATTR_WRITEBACK
-
-#define XSHAL_ISS_PIPE_REGIONS 0
-#define XSHAL_ISS_SDRAM_REGIONS 0
-
-
-/*----------------------------------------------------------------------
- XT2000 BOARD SPECIFIC ...
- ----------------------------------------------------------------------*/
-
-/* For the following, a 512MB region is used if it contains any system RAM,
- * system ROM, local memory, XLMI, or other XT2000 board device or memory.
- * Regions containing devices are forced to cache-BYPASS mode regardless
- * of whether the macro is _WRITEBACK vs. _BYPASS etc. */
-
-/* These set any 512MB region unused on the XT2000 to ILLEGAL attribute: */
-#define XSHAL_XT2000_CACHEATTR_WRITEBACK 0xFF22444F /* enable caches in write-back mode */
-#define XSHAL_XT2000_CACHEATTR_WRITEALLOC 0xFF22111F /* enable caches in write-allocate mode */
-#define XSHAL_XT2000_CACHEATTR_WRITETHRU 0xFF22111F /* enable caches in write-through mode */
-#define XSHAL_XT2000_CACHEATTR_BYPASS 0xFF22222F /* disable caches in bypass mode */
-#define XSHAL_XT2000_CACHEATTR_DEFAULT XSHAL_XT2000_CACHEATTR_WRITEBACK /* default setting to enable caches */
-
-#define XSHAL_XT2000_PIPE_REGIONS 0x00000000 /* BusInt pipeline regions */
-#define XSHAL_XT2000_SDRAM_REGIONS 0x00000440 /* BusInt SDRAM regions */
-
-
-/*----------------------------------------------------------------------
- VECTOR INFO AND SIZES
- ----------------------------------------------------------------------*/
-
-#define XSHAL_VECTORS_PACKED 0
-#define XSHAL_STATIC_VECTOR_SELECT 0
-#define XSHAL_RESET_VECTOR_VADDR 0x50000000
-#define XSHAL_RESET_VECTOR_PADDR 0x50000000
-
-/*
- * Sizes allocated to vectors by the system (memory map) configuration.
- * These sizes are constrained by core configuration (eg. one vector's
- * code cannot overflow into another vector) but are dependent on the
- * system or board (or LSP) memory map configuration.
- *
- * Whether or not each vector happens to be in a system ROM is also
- * a system configuration matter, sometimes useful, included here also:
- */
-#define XSHAL_RESET_VECTOR_SIZE 0x00000300
-#define XSHAL_RESET_VECTOR_ISROM 1
-#define XSHAL_USER_VECTOR_SIZE 0x00000038
-#define XSHAL_USER_VECTOR_ISROM 0
-#define XSHAL_PROGRAMEXC_VECTOR_SIZE XSHAL_USER_VECTOR_SIZE /* for backward compatibility */
-#define XSHAL_USEREXC_VECTOR_SIZE XSHAL_USER_VECTOR_SIZE /* for backward compatibility */
-#define XSHAL_KERNEL_VECTOR_SIZE 0x00000038
-#define XSHAL_KERNEL_VECTOR_ISROM 0
-#define XSHAL_STACKEDEXC_VECTOR_SIZE XSHAL_KERNEL_VECTOR_SIZE /* for backward compatibility */
-#define XSHAL_KERNELEXC_VECTOR_SIZE XSHAL_KERNEL_VECTOR_SIZE /* for backward compatibility */
-#define XSHAL_DOUBLEEXC_VECTOR_SIZE 0x00000040
-#define XSHAL_DOUBLEEXC_VECTOR_ISROM 0
-#define XSHAL_WINDOW_VECTORS_SIZE 0x00000178
-#define XSHAL_WINDOW_VECTORS_ISROM 0
-#define XSHAL_INTLEVEL2_VECTOR_SIZE 0x00000038
-#define XSHAL_INTLEVEL2_VECTOR_ISROM 0
-#define XSHAL_INTLEVEL3_VECTOR_SIZE 0x00000038
-#define XSHAL_INTLEVEL3_VECTOR_ISROM 0
-#define XSHAL_INTLEVEL4_VECTOR_SIZE 0x00000038
-#define XSHAL_INTLEVEL4_VECTOR_ISROM 0
-#define XSHAL_INTLEVEL5_VECTOR_SIZE 0x00000038
-#define XSHAL_INTLEVEL5_VECTOR_ISROM 0
-#define XSHAL_INTLEVEL6_VECTOR_SIZE 0x00000038
-#define XSHAL_INTLEVEL6_VECTOR_ISROM 0
-#define XSHAL_DEBUG_VECTOR_SIZE XSHAL_INTLEVEL6_VECTOR_SIZE
-#define XSHAL_DEBUG_VECTOR_ISROM XSHAL_INTLEVEL6_VECTOR_ISROM
-#define XSHAL_NMI_VECTOR_SIZE 0x00000038
-#define XSHAL_NMI_VECTOR_ISROM 0
-#define XSHAL_INTLEVEL7_VECTOR_SIZE XSHAL_NMI_VECTOR_SIZE
-
-
-#endif /*XTENSA_CONFIG_SYSTEM_H*/
-
-#else
-
-#error "xcc should not use this header"
-
-#endif /* __XCC__ */
diff --git a/src/platform/apollolake/include/arch/xtensa/config/tie-asm.h b/src/platform/apollolake/include/arch/xtensa/config/tie-asm.h
deleted file mode 100644
index 706545a..0000000
--- a/src/platform/apollolake/include/arch/xtensa/config/tie-asm.h
+++ /dev/null
@@ -1,247 +0,0 @@
-/*
- * tie-asm.h -- compile-time HAL assembler definitions dependent on CORE & TIE
- *
- * NOTE: This header file is not meant to be included directly.
- */
-
-/* This header file contains assembly-language definitions (assembly
- macros, etc.) for this specific Xtensa processor's TIE extensions
- and options. It is customized to this Xtensa processor configuration.
-
- Copyright (c) 1999-2015 Cadence Design Systems Inc.
-
- Permission is hereby granted, free of charge, to any person obtaining
- a copy of this software and associated documentation files (the
- "Software"), to deal in the Software without restriction, including
- without limitation the rights to use, copy, modify, merge, publish,
- distribute, sublicense, and/or sell copies of the Software, and to
- permit persons to whom the Software is furnished to do so, subject to
- the following conditions:
-
- The above copyright notice and this permission notice shall be included
- in all copies or substantial portions of the Software.
-
- THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
- EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
- MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
- IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY
- CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
- TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
- SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. */
-
-#if !defined __XCC__
-
-#ifndef _XTENSA_CORE_TIE_ASM_H
-#define _XTENSA_CORE_TIE_ASM_H
-
-/* Selection parameter values for save-area save/restore macros: */
-/* Option vs. TIE: */
-#define XTHAL_SAS_TIE 0x0001 /* custom extension or coprocessor */
-#define XTHAL_SAS_OPT 0x0002 /* optional (and not a coprocessor) */
-#define XTHAL_SAS_ANYOT 0x0003 /* both of the above */
-/* Whether used automatically by compiler: */
-#define XTHAL_SAS_NOCC 0x0004 /* not used by compiler w/o special opts/code */
-#define XTHAL_SAS_CC 0x0008 /* used by compiler without special opts/code */
-#define XTHAL_SAS_ANYCC 0x000C /* both of the above */
-/* ABI handling across function calls: */
-#define XTHAL_SAS_CALR 0x0010 /* caller-saved */
-#define XTHAL_SAS_CALE 0x0020 /* callee-saved */
-#define XTHAL_SAS_GLOB 0x0040 /* global across function calls (in thread) */
-#define XTHAL_SAS_ANYABI 0x0070 /* all of the above three */
-/* Misc */
-#define XTHAL_SAS_ALL 0xFFFF /* include all default NCP contents */
-#define XTHAL_SAS3(optie,ccuse,abi) ( ((optie) & XTHAL_SAS_ANYOT) \
- | ((ccuse) & XTHAL_SAS_ANYCC) \
- | ((abi) & XTHAL_SAS_ANYABI) )
-
-
- /*
- * Macro to store all non-coprocessor (extra) custom TIE and optional state
- * (not including zero-overhead loop registers).
- * Required parameters:
- * ptr Save area pointer address register (clobbered)
- * (register must contain a 4 byte aligned address).
- * at1..at4 Four temporary address registers (first XCHAL_NCP_NUM_ATMPS
- * registers are clobbered, the remaining are unused).
- * Optional parameters:
- * continue If macro invoked as part of a larger store sequence, set to 1
- * if this is not the first in the sequence. Defaults to 0.
- * ofs Offset from start of larger sequence (from value of first ptr
- * in sequence) at which to store. Defaults to next available space
- * (or 0 if <continue> is 0).
- * select Select what category(ies) of registers to store, as a bitmask
- * (see XTHAL_SAS_xxx constants). Defaults to all registers.
- * alloc Select what category(ies) of registers to allocate; if any
- * category is selected here that is not in <select>, space for
- * the corresponding registers is skipped without doing any store.
- */
- .macro xchal_ncp_store ptr at1 at2 at3 at4 continue=0 ofs=-1 select=XTHAL_SAS_ALL alloc=0
- xchal_sa_start \continue, \ofs
- // Optional caller-saved registers not used by default by the compiler:
- .ifeq (XTHAL_SAS_OPT | XTHAL_SAS_NOCC | XTHAL_SAS_CALR) & ~(\select)
- xchal_sa_align \ptr, 0, 1016, 4, 4
- rsr.BR \at1 // boolean option
- s32i \at1, \ptr, .Lxchal_ofs_+0
- rsr.SCOMPARE1 \at1 // conditional store option
- s32i \at1, \ptr, .Lxchal_ofs_+4
- .set .Lxchal_ofs_, .Lxchal_ofs_ + 8
- .elseif ((XTHAL_SAS_OPT | XTHAL_SAS_NOCC | XTHAL_SAS_CALR) & ~(\alloc)) == 0
- xchal_sa_align \ptr, 0, 1016, 4, 4
- .set .Lxchal_ofs_, .Lxchal_ofs_ + 8
- .endif
- .endm // xchal_ncp_store
-
- /*
- * Macro to load all non-coprocessor (extra) custom TIE and optional state
- * (not including zero-overhead loop registers).
- * Required parameters:
- * ptr Save area pointer address register (clobbered)
- * (register must contain a 4 byte aligned address).
- * at1..at4 Four temporary address registers (first XCHAL_NCP_NUM_ATMPS
- * registers are clobbered, the remaining are unused).
- * Optional parameters:
- * continue If macro invoked as part of a larger load sequence, set to 1
- * if this is not the first in the sequence. Defaults to 0.
- * ofs Offset from start of larger sequence (from value of first ptr
- * in sequence) at which to load. Defaults to next available space
- * (or 0 if <continue> is 0).
- * select Select what category(ies) of registers to load, as a bitmask
- * (see XTHAL_SAS_xxx constants). Defaults to all registers.
- * alloc Select what category(ies) of registers to allocate; if any
- * category is selected here that is not in <select>, space for
- * the corresponding registers is skipped without doing any load.
- */
- .macro xchal_ncp_load ptr at1 at2 at3 at4 continue=0 ofs=-1 select=XTHAL_SAS_ALL alloc=0
- xchal_sa_start \continue, \ofs
- // Optional caller-saved registers not used by default by the compiler:
- .ifeq (XTHAL_SAS_OPT | XTHAL_SAS_NOCC | XTHAL_SAS_CALR) & ~(\select)
- xchal_sa_align \ptr, 0, 1016, 4, 4
- l32i \at1, \ptr, .Lxchal_ofs_+0
- wsr.BR \at1 // boolean option
- l32i \at1, \ptr, .Lxchal_ofs_+4
- wsr.SCOMPARE1 \at1 // conditional store option
- .set .Lxchal_ofs_, .Lxchal_ofs_ + 8
- .elseif ((XTHAL_SAS_OPT | XTHAL_SAS_NOCC | XTHAL_SAS_CALR) & ~(\alloc)) == 0
- xchal_sa_align \ptr, 0, 1016, 4, 4
- .set .Lxchal_ofs_, .Lxchal_ofs_ + 8
- .endif
- .endm // xchal_ncp_load
-
-
-#define XCHAL_NCP_NUM_ATMPS 1
-
- /*
- * Macro to store the state of TIE coprocessor AudioEngineLX.
- * Required parameters:
- * ptr Save area pointer address register (clobbered)
- * (register must contain a 8 byte aligned address).
- * at1..at4 Four temporary address registers (first XCHAL_CP1_NUM_ATMPS
- * registers are clobbered, the remaining are unused).
- * Optional parameters are the same as for xchal_ncp_store.
- */
-#define xchal_cp_AudioEngineLX_store xchal_cp1_store
- .macro xchal_cp1_store ptr at1 at2 at3 at4 continue=0 ofs=-1 select=XTHAL_SAS_ALL alloc=0
- xchal_sa_start \continue, \ofs
- // Custom caller-saved registers not used by default by the compiler:
- .ifeq (XTHAL_SAS_TIE | XTHAL_SAS_NOCC | XTHAL_SAS_CALR) & ~(\select)
- xchal_sa_align \ptr, 0, 0, 8, 8
- rur.AE_OVF_SAR \at1 // ureg 240
- s32i \at1, \ptr, .Lxchal_ofs_+0
- rur.AE_BITHEAD \at1 // ureg 241
- s32i \at1, \ptr, .Lxchal_ofs_+4
- rur.AE_TS_FTS_BU_BP \at1 // ureg 242
- s32i \at1, \ptr, .Lxchal_ofs_+8
- rur.AE_SD_NO \at1 // ureg 243
- s32i \at1, \ptr, .Lxchal_ofs_+12
- ae_sp24x2s.i aep0, \ptr, .Lxchal_ofs_+16
- ae_sp24x2s.i aep1, \ptr, .Lxchal_ofs_+24
- ae_sp24x2s.i aep2, \ptr, .Lxchal_ofs_+32
- ae_sp24x2s.i aep3, \ptr, .Lxchal_ofs_+40
- ae_sp24x2s.i aep4, \ptr, .Lxchal_ofs_+48
- ae_sp24x2s.i aep5, \ptr, .Lxchal_ofs_+56
- addi \ptr, \ptr, 64
- ae_sp24x2s.i aep6, \ptr, .Lxchal_ofs_+0
- ae_sp24x2s.i aep7, \ptr, .Lxchal_ofs_+8
- ae_sq56s.i aeq0, \ptr, .Lxchal_ofs_+16
- ae_sq56s.i aeq1, \ptr, .Lxchal_ofs_+24
- ae_sq56s.i aeq2, \ptr, .Lxchal_ofs_+32
- ae_sq56s.i aeq3, \ptr, .Lxchal_ofs_+40
- .set .Lxchal_pofs_, .Lxchal_pofs_ + 64
- .set .Lxchal_ofs_, .Lxchal_ofs_ + 48
- .elseif ((XTHAL_SAS_TIE | XTHAL_SAS_NOCC | XTHAL_SAS_CALR) & ~(\alloc)) == 0
- xchal_sa_align \ptr, 0, 0, 8, 8
- .set .Lxchal_ofs_, .Lxchal_ofs_ + 112
- .endif
- .endm // xchal_cp1_store
-
- /*
- * Macro to load the state of TIE coprocessor AudioEngineLX.
- * Required parameters:
- * ptr Save area pointer address register (clobbered)
- * (register must contain a 8 byte aligned address).
- * at1..at4 Four temporary address registers (first XCHAL_CP1_NUM_ATMPS
- * registers are clobbered, the remaining are unused).
- * Optional parameters are the same as for xchal_ncp_load.
- */
-#define xchal_cp_AudioEngineLX_load xchal_cp1_load
- .macro xchal_cp1_load ptr at1 at2 at3 at4 continue=0 ofs=-1 select=XTHAL_SAS_ALL alloc=0
- xchal_sa_start \continue, \ofs
- // Custom caller-saved registers not used by default by the compiler:
- .ifeq (XTHAL_SAS_TIE | XTHAL_SAS_NOCC | XTHAL_SAS_CALR) & ~(\select)
- xchal_sa_align \ptr, 0, 0, 8, 8
- l32i \at1, \ptr, .Lxchal_ofs_+0
- wur.AE_OVF_SAR \at1 // ureg 240
- l32i \at1, \ptr, .Lxchal_ofs_+4
- wur.AE_BITHEAD \at1 // ureg 241
- l32i \at1, \ptr, .Lxchal_ofs_+8
- wur.AE_TS_FTS_BU_BP \at1 // ureg 242
- l32i \at1, \ptr, .Lxchal_ofs_+12
- wur.AE_SD_NO \at1 // ureg 243
- ae_lp24x2.i aep0, \ptr, .Lxchal_ofs_+16
- ae_lp24x2.i aep1, \ptr, .Lxchal_ofs_+24
- ae_lp24x2.i aep2, \ptr, .Lxchal_ofs_+32
- ae_lp24x2.i aep3, \ptr, .Lxchal_ofs_+40
- ae_lp24x2.i aep4, \ptr, .Lxchal_ofs_+48
- ae_lp24x2.i aep5, \ptr, .Lxchal_ofs_+56
- addi \ptr, \ptr, 64
- ae_lp24x2.i aep6, \ptr, .Lxchal_ofs_+0
- ae_lp24x2.i aep7, \ptr, .Lxchal_ofs_+8
- addi \ptr, \ptr, 16
- ae_lq56.i aeq0, \ptr, .Lxchal_ofs_+0
- ae_lq56.i aeq1, \ptr, .Lxchal_ofs_+8
- ae_lq56.i aeq2, \ptr, .Lxchal_ofs_+16
- ae_lq56.i aeq3, \ptr, .Lxchal_ofs_+24
- .set .Lxchal_pofs_, .Lxchal_pofs_ + 80
- .set .Lxchal_ofs_, .Lxchal_ofs_ + 32
- .elseif ((XTHAL_SAS_TIE | XTHAL_SAS_NOCC | XTHAL_SAS_CALR) & ~(\alloc)) == 0
- xchal_sa_align \ptr, 0, 0, 8, 8
- .set .Lxchal_ofs_, .Lxchal_ofs_ + 112
- .endif
- .endm // xchal_cp1_load
-
-#define XCHAL_CP1_NUM_ATMPS 1
-#define XCHAL_SA_NUM_ATMPS 1
-
- /* Empty macros for unconfigured coprocessors: */
- .macro xchal_cp0_store p a b c d continue=0 ofs=-1 select=-1 ; .endm
- .macro xchal_cp0_load p a b c d continue=0 ofs=-1 select=-1 ; .endm
- .macro xchal_cp2_store p a b c d continue=0 ofs=-1 select=-1 ; .endm
- .macro xchal_cp2_load p a b c d continue=0 ofs=-1 select=-1 ; .endm
- .macro xchal_cp3_store p a b c d continue=0 ofs=-1 select=-1 ; .endm
- .macro xchal_cp3_load p a b c d continue=0 ofs=-1 select=-1 ; .endm
- .macro xchal_cp4_store p a b c d continue=0 ofs=-1 select=-1 ; .endm
- .macro xchal_cp4_load p a b c d continue=0 ofs=-1 select=-1 ; .endm
- .macro xchal_cp5_store p a b c d continue=0 ofs=-1 select=-1 ; .endm
- .macro xchal_cp5_load p a b c d continue=0 ofs=-1 select=-1 ; .endm
- .macro xchal_cp6_store p a b c d continue=0 ofs=-1 select=-1 ; .endm
- .macro xchal_cp6_load p a b c d continue=0 ofs=-1 select=-1 ; .endm
- .macro xchal_cp7_store p a b c d continue=0 ofs=-1 select=-1 ; .endm
- .macro xchal_cp7_load p a b c d continue=0 ofs=-1 select=-1 ; .endm
-
-#endif /*_XTENSA_CORE_TIE_ASM_H*/
-
-#else
-
-#error "xcc should not use this header"
-
-#endif /* __XCC__ */
diff --git a/src/platform/apollolake/include/arch/xtensa/config/tie.h b/src/platform/apollolake/include/arch/xtensa/config/tie.h
deleted file mode 100644
index b5fd4c9..0000000
--- a/src/platform/apollolake/include/arch/xtensa/config/tie.h
+++ /dev/null
@@ -1,177 +0,0 @@
-/*
- * tie.h -- compile-time HAL definitions dependent on CORE & TIE configuration
- *
- * NOTE: This header file is not meant to be included directly.
- */
-
-/* This header file describes this specific Xtensa processor's TIE extensions
- that extend basic Xtensa core functionality. It is customized to this
- Xtensa processor configuration.
-
- Copyright (c) 1999-2015 Cadence Design Systems Inc.
-
- Permission is hereby granted, free of charge, to any person obtaining
- a copy of this software and associated documentation files (the
- "Software"), to deal in the Software without restriction, including
- without limitation the rights to use, copy, modify, merge, publish,
- distribute, sublicense, and/or sell copies of the Software, and to
- permit persons to whom the Software is furnished to do so, subject to
- the following conditions:
-
- The above copyright notice and this permission notice shall be included
- in all copies or substantial portions of the Software.
-
- THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
- EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
- MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
- IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY
- CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
- TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
- SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. */
-
-#if !defined __XCC__
-
-#ifndef _XTENSA_CORE_TIE_H
-#define _XTENSA_CORE_TIE_H
-
-#define XCHAL_CP_NUM 1 /* number of coprocessors */
-#define XCHAL_CP_MAX 2 /* max CP ID + 1 (0 if none) */
-#define XCHAL_CP_MASK 0x02 /* bitmask of all CPs by ID */
-#define XCHAL_CP_PORT_MASK 0x00 /* bitmask of only port CPs */
-
-/* Basic parameters of each coprocessor: */
-#define XCHAL_CP1_NAME "AudioEngineLX"
-#define XCHAL_CP1_IDENT AudioEngineLX
-#define XCHAL_CP1_SA_SIZE 112 /* size of state save area */
-#define XCHAL_CP1_SA_ALIGN 8 /* min alignment of save area */
-#define XCHAL_CP_ID_AUDIOENGINELX 1 /* coprocessor ID (0..7) */
-
-/* Filler info for unassigned coprocessors, to simplify arrays etc: */
-#define XCHAL_CP0_SA_SIZE 0
-#define XCHAL_CP0_SA_ALIGN 1
-#define XCHAL_CP2_SA_SIZE 0
-#define XCHAL_CP2_SA_ALIGN 1
-#define XCHAL_CP3_SA_SIZE 0
-#define XCHAL_CP3_SA_ALIGN 1
-#define XCHAL_CP4_SA_SIZE 0
-#define XCHAL_CP4_SA_ALIGN 1
-#define XCHAL_CP5_SA_SIZE 0
-#define XCHAL_CP5_SA_ALIGN 1
-#define XCHAL_CP6_SA_SIZE 0
-#define XCHAL_CP6_SA_ALIGN 1
-#define XCHAL_CP7_SA_SIZE 0
-#define XCHAL_CP7_SA_ALIGN 1
-
-/* Save area for non-coprocessor optional and custom (TIE) state: */
-#define XCHAL_NCP_SA_SIZE 8
-#define XCHAL_NCP_SA_ALIGN 4
-
-/* Total save area for optional and custom state (NCP + CPn): */
-#define XCHAL_TOTAL_SA_SIZE 128 /* with 16-byte align padding */
-#define XCHAL_TOTAL_SA_ALIGN 8 /* actual minimum alignment */
-
-/*
- * Detailed contents of save areas.
- * NOTE: caller must define the XCHAL_SA_REG macro (not defined here)
- * before expanding the XCHAL_xxx_SA_LIST() macros.
- *
- * XCHAL_SA_REG(s,ccused,abikind,kind,opt,name,galign,align,asize,
- * dbnum,base,regnum,bitsz,gapsz,reset,x...)
- *
- * s = passed from XCHAL_*_LIST(s), eg. to select how to expand
- * ccused = set if used by compiler without special options or code
- * abikind = 0 (caller-saved), 1 (callee-saved), or 2 (thread-global)
- * kind = 0 (special reg), 1 (TIE user reg), or 2 (TIE regfile reg)
- * opt = 0 (custom TIE extension or coprocessor), or 1 (optional reg)
- * name = lowercase reg name (no quotes)
- * galign = group byte alignment (power of 2) (galign >= align)
- * align = register byte alignment (power of 2)
- * asize = allocated size in bytes (asize*8 == bitsz + gapsz + padsz)
- * (not including any pad bytes required to galign this or next reg)
- * dbnum = unique target number f/debug (see <xtensa-libdb-macros.h>)
- * base = reg shortname w/o index (or sr=special, ur=TIE user reg)
- * regnum = reg index in regfile, or special/TIE-user reg number
- * bitsz = number of significant bits (regfile width, or ur/sr mask bits)
- * gapsz = intervening bits, if bitsz bits not stored contiguously
- * (padsz = pad bits at end [TIE regfile] or at msbits [ur,sr] of asize)
- * reset = register reset value (or 0 if undefined at reset)
- * x = reserved for future use (0 until then)
- *
- * To filter out certain registers, e.g. to expand only the non-global
- * registers used by the compiler, you can do something like this:
- *
- * #define XCHAL_SA_REG(s,ccused,p...) SELCC##ccused(p)
- * #define SELCC0(p...)
- * #define SELCC1(abikind,p...) SELAK##abikind(p)
- * #define SELAK0(p...) REG(p)
- * #define SELAK1(p...) REG(p)
- * #define SELAK2(p...)
- * #define REG(kind,tie,name,galn,aln,asz,csz,dbnum,base,rnum,bsz,rst,x...) \
- * ...what you want to expand...
- */
-
-#define XCHAL_NCP_SA_NUM 2
-#define XCHAL_NCP_SA_LIST(s) \
- XCHAL_SA_REG(s,0,0,0,1, br, 4, 4, 4,0x0204, sr,4 , 16,0,0,0) \
- XCHAL_SA_REG(s,0,0,0,1, scompare1, 4, 4, 4,0x020C, sr,12 , 32,0,0,0)
-
-#define XCHAL_CP0_SA_NUM 0
-#define XCHAL_CP0_SA_LIST(s) /* empty */
-
-#define XCHAL_CP1_SA_NUM 16
-#define XCHAL_CP1_SA_LIST(s) \
- XCHAL_SA_REG(s,0,0,1,0, ae_ovf_sar, 8, 4, 4,0x03F0, ur,240, 7,0,0,0) \
- XCHAL_SA_REG(s,0,0,1,0, ae_bithead, 4, 4, 4,0x03F1, ur,241, 32,0,0,0) \
- XCHAL_SA_REG(s,0,0,1,0,ae_ts_fts_bu_bp, 4, 4, 4,0x03F2, ur,242, 16,0,0,0) \
- XCHAL_SA_REG(s,0,0,1,0, ae_sd_no, 4, 4, 4,0x03F3, ur,243, 28,0,0,0) \
- XCHAL_SA_REG(s,0,0,2,0, aep0, 8, 8, 8,0x0060, aep,0 , 48,0,0,0) \
- XCHAL_SA_REG(s,0,0,2,0, aep1, 8, 8, 8,0x0061, aep,1 , 48,0,0,0) \
- XCHAL_SA_REG(s,0,0,2,0, aep2, 8, 8, 8,0x0062, aep,2 , 48,0,0,0) \
- XCHAL_SA_REG(s,0,0,2,0, aep3, 8, 8, 8,0x0063, aep,3 , 48,0,0,0) \
- XCHAL_SA_REG(s,0,0,2,0, aep4, 8, 8, 8,0x0064, aep,4 , 48,0,0,0) \
- XCHAL_SA_REG(s,0,0,2,0, aep5, 8, 8, 8,0x0065, aep,5 , 48,0,0,0) \
- XCHAL_SA_REG(s,0,0,2,0, aep6, 8, 8, 8,0x0066, aep,6 , 48,0,0,0) \
- XCHAL_SA_REG(s,0,0,2,0, aep7, 8, 8, 8,0x0067, aep,7 , 48,0,0,0) \
- XCHAL_SA_REG(s,0,0,2,0, aeq0, 8, 8, 8,0x0068, aeq,0 , 56,0,0,0) \
- XCHAL_SA_REG(s,0,0,2,0, aeq1, 8, 8, 8,0x0069, aeq,1 , 56,0,0,0) \
- XCHAL_SA_REG(s,0,0,2,0, aeq2, 8, 8, 8,0x006A, aeq,2 , 56,0,0,0) \
- XCHAL_SA_REG(s,0,0,2,0, aeq3, 8, 8, 8,0x006B, aeq,3 , 56,0,0,0)
-
-#define XCHAL_CP2_SA_NUM 0
-#define XCHAL_CP2_SA_LIST(s) /* empty */
-
-#define XCHAL_CP3_SA_NUM 0
-#define XCHAL_CP3_SA_LIST(s) /* empty */
-
-#define XCHAL_CP4_SA_NUM 0
-#define XCHAL_CP4_SA_LIST(s) /* empty */
-
-#define XCHAL_CP5_SA_NUM 0
-#define XCHAL_CP5_SA_LIST(s) /* empty */
-
-#define XCHAL_CP6_SA_NUM 0
-#define XCHAL_CP6_SA_LIST(s) /* empty */
-
-#define XCHAL_CP7_SA_NUM 0
-#define XCHAL_CP7_SA_LIST(s) /* empty */
-
-/* Byte length of instruction from its first nibble (op0 field), per FLIX. */
-#define XCHAL_OP0_FORMAT_LENGTHS 3,3,3,3,3,3,3,3,2,2,2,2,2,2,3,8
-/* Byte length of instruction from its first byte, per FLIX. */
-#define XCHAL_BYTE0_FORMAT_LENGTHS \
- 3,3,3,3,3,3,3,3,2,2,2,2,2,2,3,8, 3,3,3,3,3,3,3,3,2,2,2,2,2,2,3,8,\
- 3,3,3,3,3,3,3,3,2,2,2,2,2,2,3,8, 3,3,3,3,3,3,3,3,2,2,2,2,2,2,3,8,\
- 3,3,3,3,3,3,3,3,2,2,2,2,2,2,3,8, 3,3,3,3,3,3,3,3,2,2,2,2,2,2,3,8,\
- 3,3,3,3,3,3,3,3,2,2,2,2,2,2,3,8, 3,3,3,3,3,3,3,3,2,2,2,2,2,2,3,8,\
- 3,3,3,3,3,3,3,3,2,2,2,2,2,2,3,8, 3,3,3,3,3,3,3,3,2,2,2,2,2,2,3,8,\
- 3,3,3,3,3,3,3,3,2,2,2,2,2,2,3,8, 3,3,3,3,3,3,3,3,2,2,2,2,2,2,3,8,\
- 3,3,3,3,3,3,3,3,2,2,2,2,2,2,3,8, 3,3,3,3,3,3,3,3,2,2,2,2,2,2,3,8,\
- 3,3,3,3,3,3,3,3,2,2,2,2,2,2,3,8, 3,3,3,3,3,3,3,3,2,2,2,2,2,2,3,8
-
-#endif /*_XTENSA_CORE_TIE_H*/
-
-#else
-
-#error "xcc should not use this header"
-
-#endif /* __XCC__ */
diff --git a/src/platform/apollolake/include/platform/Makefile.am b/src/platform/apollolake/include/platform/Makefile.am
deleted file mode 100644
index 5149055..0000000
--- a/src/platform/apollolake/include/platform/Makefile.am
+++ /dev/null
@@ -1,14 +0,0 @@
-noinst_HEADERS = \
- clk.h \
- dma.h \
- idc.h \
- interrupt.h \
- mailbox.h \
- memory.h \
- platcfg.h \
- platform.h \
- pm_runtime.h \
- shim.h \
- timer.h \
- asm_memory_management.h \
- power_down.h
\ No newline at end of file
diff --git a/src/platform/apollolake/include/platform/asm_memory_management.h b/src/platform/apollolake/include/platform/asm_memory_management.h
deleted file mode 100644
index 7ef9cb2..0000000
--- a/src/platform/apollolake/include/platform/asm_memory_management.h
+++ /dev/null
@@ -1,95 +0,0 @@
-/*
- * Copyright (c) 2018, Intel Corporation
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- * * Redistributions of source code must retain the above copyright
- * notice, this list of conditions and the following disclaimer.
- * * Redistributions in binary form must reproduce the above copyright
- * notice, this list of conditions and the following disclaimer in the
- * documentation and/or other materials provided with the distribution.
- * * Neither the name of the Intel Corporation nor the
- * names of its contributors may be used to endorse or promote products
- * derived from this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
- * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
- * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
- * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
- * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
- * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
- * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
- * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
- * POSSIBILITY OF SUCH DAMAGE.
- *
- * Author: Lech Betlej <lech.betlej@linux.intel.com>
- */
-
-/**
- * \file platform/apollolake/include/platform/asm_memory_management.h
- * \brief Macros for power gating memory banks specific for Apollolake
- * \author Lech Betlej <lech.betlej@linux.intel.com>
- */
-#ifndef ASM_MEMORY_MANAGEMENT_H
-#define ASM_MEMORY_MANAGEMENT_H
-
-#ifndef ASSEMBLY
-#warning "ASSEMBLY macro not defined."
-#endif
-
-#include <platform/shim.h>
-#include <platform/platcfg.h>
-
-#define HPSRAM_MASK ((1 << PLATFORM_HPSRAM_EBB_COUNT) - 1)
-#define LPSRAM_MASK ((1 << PLATFORM_LPSRAM_EBB_COUNT) - 1)
-
- /* Macro powers down entire hpsram. on entry literals and code for
- * section from where this code is executed needs to be placed in
- * memory which is not HPSRAM (in case when this code is located in
- * HPSRAM lock memory in L1$ or L1 SRAM)
- */
- .macro m_cavs_hpsram_power_off ax, ay, az
- // SEGMENT #0
- movi \az, (SHIM_BASE + SHIM_HSPGISTS)
- movi \ax, (SHIM_BASE + SHIM_HSPGCTL)
- movi \ay, HPSRAM_MASK
- s32i \ay, \ax, 0
- memw
- /* since HPSRAM EBB bank #0 might be used as buffer for legacy
- * streaming, should not be checked in status
- */
- movi \ax, 0xfffffffe
- and \ay, \ay, \ax
- 1 :
- l32i \ax, \az, 0
- and \ax, \ax, \ay
- bne \ax, \ay, 1b
- /* there is no possibility to check from DSP whether EBB #0 is actually
- * in use therefore wait additional 4K DSP cycles as chicken check -
- * after that time EBB #0 should be already power gated unless is used
- * by other HW components (like HD-A)
- */
- l32i \ax, \az, 0
- beq \ax, \ay, m_cavs_hpsram_power_off_end
- movi \ax, 4096
- 1 :
- addi \ax, \ax, -1
- bnez \ax, 1b
- m_cavs_hpsram_power_off_end :
- .endm
-
- .macro m_cavs_lpsram_power_off ax, ay, az
- movi \az, (SHIM_BASE + SHIM_LSPGISTS)
- movi \ax, (SHIM_BASE + SHIM_LSPGCTL)
- movi \ay, LPSRAM_MASK
- s32i \ay, \ax, 0
- memw
- 1 :
- l32i \ax, \az, 0
- bne \ax, \ay, 1b
- .endm
-
-#endif /* ASM_MEMORY_MANAGEMENT_H */
diff --git a/src/platform/apollolake/include/platform/clk.h b/src/platform/apollolake/include/platform/clk.h
deleted file mode 100644
index 5a15b8a..0000000
--- a/src/platform/apollolake/include/platform/clk.h
+++ /dev/null
@@ -1,43 +0,0 @@
-/*
- * Copyright (c) 2016, Intel Corporation
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- * * Redistributions of source code must retain the above copyright
- * notice, this list of conditions and the following disclaimer.
- * * Redistributions in binary form must reproduce the above copyright
- * notice, this list of conditions and the following disclaimer in the
- * documentation and/or other materials provided with the distribution.
- * * Neither the name of the Intel Corporation nor the
- * names of its contributors may be used to endorse or promote products
- * derived from this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
- * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
- * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
- * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
- * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
- * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
- * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
- * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
- * POSSIBILITY OF SUCH DAMAGE.
- *
- * Author: Liam Girdwood <liam.r.girdwood@linux.intel.com>
- * Keyon Jie <yang.jie@linux.intel.com>
- */
-
-#ifndef __PLATFORM_CLOCK__
-#define __PLATFORM_CLOCK__
-
-#define CLK_CPU 0
-#define CLK_SSP 1
-
-#define CLK_DEFAULT_CPU_HZ 400000000
-#define CLK_MAX_CPU_HZ 400000000
-
-void init_platform_clocks(void);
-
-#endif
diff --git a/src/platform/apollolake/include/platform/dma.h b/src/platform/apollolake/include/platform/dma.h
deleted file mode 100644
index 7243c03..0000000
--- a/src/platform/apollolake/include/platform/dma.h
+++ /dev/null
@@ -1,80 +0,0 @@
-/*
- * Copyright (c) 2016, Intel Corporation
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- * * Redistributions of source code must retain the above copyright
- * notice, this list of conditions and the following disclaimer.
- * * Redistributions in binary form must reproduce the above copyright
- * notice, this list of conditions and the following disclaimer in the
- * documentation and/or other materials provided with the distribution.
- * * Neither the name of the Intel Corporation nor the
- * names of its contributors may be used to endorse or promote products
- * derived from this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
- * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
- * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
- * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
- * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
- * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
- * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
- * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
- * POSSIBILITY OF SUCH DAMAGE.
- *
- * Author: Liam Girdwood <liam.r.girdwood@linux.intel.com>
- * Keyon Jie <yang.jie@linux.intel.com>
- */
-
-#ifndef __PLATFORM_DMA_H__
-#define __PLATFORM_DMA_H__
-
-#include <stdint.h>
-#include <sof/io.h>
-#include <arch/cache.h>
-#include <sof/dma.h>
-
-#define PLATFORM_NUM_DMACS 6
-
-/* available DMACs */
-#define DMA_GP_LP_DMAC0 0
-#define DMA_GP_LP_DMAC1 1
-#define DMA_GP_HP_DMAC0 2
-#define DMA_GP_HP_DMAC1 3
-#define DMA_HOST_IN_DMAC 4
-#define DMA_HOST_OUT_DMAC 5
-#define DMA_LINK_IN_DMAC 6
-#define DMA_LINK_OUT_DMAC 7
-
-/* mappings - TODO improve API to get type */
-#define DMA_ID_DMAC0 DMA_HOST_IN_DMAC
-#define DMA_ID_DMAC1 DMA_GP_LP_DMAC0
-#define DMA_ID_DMAC2 DMA_HOST_OUT_DMAC
-#define DMA_ID_DMAC3 DMA_GP_HP_DMAC0
-#define DMA_ID_DMAC4 DMA_GP_LP_DMAC1
-#define DMA_ID_DMAC5 DMA_GP_HP_DMAC1
-#define DMA_ID_DMAC6 DMA_LINK_IN_DMAC
-#define DMA_ID_DMAC7 DMA_LINK_OUT_DMAC
-
-/* handshakes */
-#define DMA_HANDSHAKE_DMIC_CH0 0
-#define DMA_HANDSHAKE_DMIC_CH1 1
-#define DMA_HANDSHAKE_SSP0_TX 2
-#define DMA_HANDSHAKE_SSP0_RX 3
-#define DMA_HANDSHAKE_SSP1_TX 4
-#define DMA_HANDSHAKE_SSP1_RX 5
-#define DMA_HANDSHAKE_SSP2_TX 6
-#define DMA_HANDSHAKE_SSP2_RX 7
-#define DMA_HANDSHAKE_SSP3_TX 8
-#define DMA_HANDSHAKE_SSP3_RX 9
-#define DMA_HANDSHAKE_SSP4_TX 10
-#define DMA_HANDSHAKE_SSP4_RX 11
-#define DMA_HANDSHAKE_SSP5_TX 12
-#define DMA_HANDSHAKE_SSP5_RX 13
-
-extern struct dma dma[PLATFORM_NUM_DMACS];
-
-#endif
diff --git a/src/platform/apollolake/include/platform/idc.h b/src/platform/apollolake/include/platform/idc.h
deleted file mode 100644
index cc6d4d6..0000000
--- a/src/platform/apollolake/include/platform/idc.h
+++ /dev/null
@@ -1,51 +0,0 @@
-/*
- * Copyright (c) 2018, Intel Corporation
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- * * Redistributions of source code must retain the above copyright
- * notice, this list of conditions and the following disclaimer.
- * * Redistributions in binary form must reproduce the above copyright
- * notice, this list of conditions and the following disclaimer in the
- * documentation and/or other materials provided with the distribution.
- * * Neither the name of the Intel Corporation nor the
- * names of its contributors may be used to endorse or promote products
- * derived from this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
- * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
- * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
- * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
- * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
- * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
- * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
- * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
- * POSSIBILITY OF SUCH DAMAGE.
- *
- * Author: Tomasz Lauda <tomasz.lauda@linux.intel.com>
- */
-
-#ifndef __INCLUDE_PLATFORM_IDC_H__
-#define __INCLUDE_PLATFORM_IDC_H__
-
-#include <arch/idc.h>
-
-static inline int idc_send_msg(struct idc_msg *msg, uint32_t mode)
-{
- return arch_idc_send_msg(msg, mode);
-}
-
-static inline void idc_process_msg_queue(void)
-{
- arch_idc_process_msg_queue();
-}
-
-static inline void idc_init(void)
-{
- arch_idc_init();
-}
-
-#endif
diff --git a/src/platform/apollolake/include/platform/interrupt.h b/src/platform/apollolake/include/platform/interrupt.h
deleted file mode 100644
index 6778661..0000000
--- a/src/platform/apollolake/include/platform/interrupt.h
+++ /dev/null
@@ -1,174 +0,0 @@
-/*
- * Copyright (c) 2016, Intel Corporation
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- * * Redistributions of source code must retain the above copyright
- * notice, this list of conditions and the following disclaimer.
- * * Redistributions in binary form must reproduce the above copyright
- * notice, this list of conditions and the following disclaimer in the
- * documentation and/or other materials provided with the distribution.
- * * Neither the name of the Intel Corporation nor the
- * names of its contributors may be used to endorse or promote products
- * derived from this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
- * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
- * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
- * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
- * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
- * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
- * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
- * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
- * POSSIBILITY OF SUCH DAMAGE.
- *
- * Author: Liam Girdwood <liam.r.girdwood@linux.intel.com>
- * Keyon Jie <yang.jie@linux.intel.com>
- */
-
-#ifndef __INCLUDE_PLATFORM_INTERRUPT__
-#define __INCLUDE_PLATFORM_INTERRUPT__
-
-#include <stdint.h>
-#include <sof/interrupt-map.h>
-
-#define PLATFORM_IRQ_CHILDREN 32
-
-/* IRQ numbers - wrt Tensilica DSP */
-#define IRQ_NUM_SOFTWARE0 0 /* level 1 */
-#define IRQ_NUM_TIMER1 1 /* level 1 */
-#define IRQ_NUM_EXT_LEVEL1 2 /* level 1 */
-#define IRQ_NUM_SOFTWARE1 3 /* level 1 */
-#define IRQ_NUM_SOFTWARE2 4 /* level 2 */
-#define IRQ_NUM_TIMER2 5 /* level 2 */
-#define IRQ_NUM_EXT_LEVEL2 6 /* level 2 */
-#define IRQ_NUM_SOFTWARE3 7 /* level 2 */
-#define IRQ_NUM_SOFTWARE4 8 /* level 3 */
-#define IRQ_NUM_TIMER3 9 /* level 3 */
-#define IRQ_NUM_EXT_LEVEL3 10 /* level 3 */
-#define IRQ_NUM_SOFTWARE5 11 /* level 3 */
-#define IRQ_NUM_SOFTWARE6 12 /* level 4 */
-#define IRQ_NUM_EXT_LEVEL4 13 /* level 4 */
-#define IRQ_NUM_SOFTWARE7 14 /* level 4 */
-#define IRQ_NUM_SOFTWARE8 15 /* level 5 */
-#define IRQ_NUM_EXT_LEVEL5 16 /* level 5 */
-#define IRQ_NUM_EXT_LEVEL6 17 /* level 5 */
-#define IRQ_NUM_EXT_LEVEL7 18 /* level 5 */
-#define IRQ_NUM_SOFTWARE9 19 /* level 5 */
-#define IRQ_NUM_NMI 20 /* level 7 */
-
-/* IRQ Level 2 bits */
-#define IRQ_BIT_LVL2_HP_GP_DMA0(x) (x + 24)
-#define IRQ_BIT_LVL2_WALL_CLK1 23
-#define IRQ_BIT_LVL2_WALL_CLK0 22
-#define IRQ_BIT_LVL2_L2_MEMERR 21
-#define IRQ_BIT_LVL2_SHA256 16
-#define IRQ_BIT_LVL2_L2_CACHE 15
-#define IRQ_BIT_LVL2_IDC 8
-#define IRQ_BIT_LVL2_HOST_IPC 7
-#define IRQ_BIT_LVL2_CSME_IPC 6
-#define IRQ_BIT_LVL2_PMC_IPC 5
-
-/* IRQ Level 3 bits */
-#define IRQ_BIT_LVL3_CODE_LOADER 31
-#define IRQ_BIT_LVL3_HOST_STREAM_OUT(x) (16 + x)
-#define IRQ_BIT_LVL3_HOST_STREAM_IN(x) (0 + x)
-
-/* IRQ Level 4 bits */
-#define IRQ_BIT_LVL4_LINK_STREAM_OUT(x) (16 + x)
-#define IRQ_BIT_LVL4_LINK_STREAM_IN(x) (0 + x)
-
-/* IRQ Level 5 bits */
-#define IRQ_BIT_LVL5_LP_GP_DMA1(x) (24 + x)
-#define IRQ_BIT_LVL5_LP_GP_DMA0(x) (16 + x)
-#define IRQ_BIT_LVL5_DMIC 6
-#define IRQ_BIT_LVL5_SSP(x) (0 + x)
-
-/* Level 2 Peripheral IRQ mappings */
-#define IRQ_EXT_HP_GPDMA_LVL2(xcpu) \
- SOF_IRQ(IRQ_BIT_LVL2_HP_GP_DMA0(0), 2, xcpu, IRQ_NUM_EXT_LEVEL2)
-#define IRQ_EXT_IDC_LVL2(xcpu) \
- SOF_IRQ(IRQ_BIT_LVL2_IDC, 2, xcpu, IRQ_NUM_EXT_LEVEL2)
-#define IRQ_EXT_IPC_LVL2(xcpu) \
- SOF_IRQ(IRQ_BIT_LVL2_HOST_IPC, 2, xcpu, IRQ_NUM_EXT_LEVEL2)
-#define IRQ_EXT_TSTAMP1_LVL2(xcpu) \
- SOF_IRQ(IRQ_BIT_LVL2_WALL_CLK1, 2, xcpu, IRQ_NUM_EXT_LEVEL2)
-#define IRQ_EXT_TSTAMP0_LVL2(xcpu) \
- SOF_IRQ(IRQ_BIT_LVL2_WALL_CLK0, 2, xcpu, IRQ_NUM_EXT_LEVEL2)
-#define IRQ_EXT_MERR_LVL2(xcpu) \
- SOF_IRQ(IRQ_BIT_LVL2_L2_MEMERR, 2, xcpu, IRQ_NUM_EXT_LEVEL2)
-#define IRQ_EXT_L2CACHE_LVL2(xcpu) \
- SOF_IRQ(IRQ_BIT_LVL2_L2_CACHE, 2, xcpu, IRQ_NUM_EXT_LEVEL2)
-#define IRQ_EXT_SHA256_LVL2(xcpu) \
- SOF_IRQ(IRQ_BIT_LVL2_SHA256, 2, xcpu, IRQ_NUM_EXT_LEVEL2)
-
-/* Level 3 Peripheral IRQ mappings */
-#define IRQ_EXT_CODE_DMA_LVL3(xcpu) \
- SOF_IRQ(IRQ_BIT_LVL3_CODE_LOADER, 3, xcpu, IRQ_NUM_EXT_LEVEL3)
-#define IRQ_EXT_HOST_DMA_IN_LVL3(xcpu, channel) \
- SOF_IRQ(IRQ_BIT_LVL3_HOST_STREAM_IN(channel), 3, xcpu, IRQ_NUM_EXT_LEVEL3)
-#define IRQ_EXT_HOST_DMA_OUT_LVL3(xcpu, channel) \
- SOF_IRQ(IRQ_BIT_LVL3_HOST_STREAM_OUT(channel), 3, xcpu, IRQ_NUM_EXT_LEVEL3)
-
-/* Level 4 Peripheral IRQ mappings */
-#define IRQ_EXT_LINK_DMA_IN_LVL4(xcpu, channel) \
- SOF_IRQ(IRQ_BIT_LVL4_LINK_STREAM_IN(channel), 4, xcpu, IRQ_NUM_EXT_LEVEL4)
-#define IRQ_EXT_LINK_DMA_OUT_LVL4(xcpu, channel) \
- SOF_IRQ(IRQ_BIT_LVL4_LINK_STREAM_OUT(channel), 4, xcpu, IRQ_NUM_EXT_LEVEL4)
-
-/* Level 5 Peripheral IRQ mappings */
-#define IRQ_EXT_LP_GPDMA0_LVL5(xcpu, channel) \
- SOF_IRQ(IRQ_BIT_LVL5_LP_GP_DMA0(channel), 5, xcpu, IRQ_NUM_EXT_LEVEL5)
-#define IRQ_EXT_LP_GPDMA1_LVL5(xcpu, channel) \
- SOF_IRQ(IRQ_BIT_LVL5_LP_GP_DMA1(channel), 5, xcpu, IRQ_NUM_EXT_LEVEL5)
-#define IRQ_EXT_SSP0_LVL5(xcpu) \
- SOF_IRQ(IRQ_BIT_LVL5_SSP(0), 5, xcpu, IRQ_NUM_EXT_LEVEL5)
-#define IRQ_EXT_SSP1_LVL5(xcpu) \
- SOF_IRQ(IRQ_BIT_LVL5_SSP(1), 5, xcpu, IRQ_NUM_EXT_LEVEL5)
-#define IRQ_EXT_SSP2_LVL5(xcpu) \
- SOF_IRQ(IRQ_BIT_LVL5_SSP(2), 5, xcpu, IRQ_NUM_EXT_LEVEL5)
-#define IRQ_EXT_SSP3_LVL5(xcpu) \
- SOF_IRQ(IRQ_BIT_LVL5_SSP(3), 5, xcpu, IRQ_NUM_EXT_LEVEL5)
-#define IRQ_EXT_SSP4_LVL5(xcpu) \
- SOF_IRQ(IRQ_BIT_LVL5_SSP(4), 5, xcpu, IRQ_NUM_EXT_LEVEL5)
-#define IRQ_EXT_SSP5_LVL5(xcpu) \
- SOF_IRQ(IRQ_BIT_LVL5_SSP(5), 5, xcpu, IRQ_NUM_EXT_LEVEL5)
-#define IRQ_EXT_DMIC_LVL5(xcpu) \
- SOF_IRQ(IRQ_BIT_LVL5_DMIC, 5, xcpu, IRQ_NUM_EXT_LEVEL5)
-
-
-/* IRQ Masks */
-#define IRQ_MASK_SOFTWARE0 (1 << IRQ_NUM_SOFTWARE0)
-#define IRQ_MASK_TIMER1 (1 << IRQ_NUM_TIMER1)
-#define IRQ_MASK_EXT_LEVEL1 (1 << IRQ_NUM_EXT_LEVEL1)
-#define IRQ_MASK_SOFTWARE1 (1 << IRQ_NUM_SOFTWARE1)
-#define IRQ_MASK_SOFTWARE2 (1 << IRQ_NUM_SOFTWARE2)
-#define IRQ_MASK_TIMER2 (1 << IRQ_NUM_TIMER2)
-#define IRQ_MASK_EXT_LEVEL2 (1 << IRQ_NUM_EXT_LEVEL2)
-#define IRQ_MASK_SOFTWARE3 (1 << IRQ_NUM_SOFTWARE3)
-#define IRQ_MASK_SOFTWARE4 (1 << IRQ_NUM_SOFTWARE4)
-#define IRQ_MASK_TIMER3 (1 << IRQ_NUM_TIMER3)
-#define IRQ_MASK_EXT_LEVEL3 (1 << IRQ_NUM_EXT_LEVEL3)
-#define IRQ_MASK_SOFTWARE5 (1 << IRQ_NUM_SOFTWARE5)
-#define IRQ_MASK_SOFTWARE6 (1 << IRQ_NUM_SOFTWARE6)
-#define IRQ_MASK_EXT_LEVEL4 (1 << IRQ_NUM_EXT_LEVEL4)
-#define IRQ_MASK_SOFTWARE7 (1 << IRQ_NUM_SOFTWARE7)
-#define IRQ_MASK_SOFTWARE8 (1 << IRQ_NUM_SOFTWARE8)
-#define IRQ_MASK_EXT_LEVEL5 (1 << IRQ_NUM_EXT_LEVEL5)
-#define IRQ_MASK_EXT_LEVEL6 (1 << IRQ_NUM_EXT_LEVEL6)
-#define IRQ_MASK_EXT_LEVEL7 (1 << IRQ_NUM_EXT_LEVEL7)
-#define IRQ_MASK_SOFTWARE9 (1 << IRQ_NUM_SOFTWARE9)
-
-void platform_interrupt_init(void);
-
-struct irq_desc *platform_irq_get_parent(uint32_t irq);
-void platform_interrupt_set(int irq);
-void platform_interrupt_clear(uint32_t irq, uint32_t mask);
-uint32_t platform_interrupt_get_enabled(void);
-void platform_interrupt_mask(uint32_t irq, uint32_t mask);
-void platform_interrupt_unmask(uint32_t irq, uint32_t mask);
-
-#endif
diff --git a/src/platform/apollolake/include/platform/mailbox.h b/src/platform/apollolake/include/platform/mailbox.h
deleted file mode 100644
index 92bd089..0000000
--- a/src/platform/apollolake/include/platform/mailbox.h
+++ /dev/null
@@ -1,82 +0,0 @@
-/*
- * Copyright (c) 2016, Intel Corporation
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- * * Redistributions of source code must retain the above copyright
- * notice, this list of conditions and the following disclaimer.
- * * Redistributions in binary form must reproduce the above copyright
- * notice, this list of conditions and the following disclaimer in the
- * documentation and/or other materials provided with the distribution.
- * * Neither the name of the Intel Corporation nor the
- * names of its contributors may be used to endorse or promote products
- * derived from this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
- * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
- * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
- * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
- * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
- * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
- * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
- * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
- * POSSIBILITY OF SUCH DAMAGE.
- *
- * Author: Liam Girdwood <liam.r.girdwood@linux.intel.com>
- * Keyon Jie <yang.jie@linux.intel.com>
- */
-
-#ifndef __INCLUDE_PLATFORM_MAILBOX__
-#define __INCLUDE_PLATFORM_MAILBOX__
-
-#include <platform/memory.h>
-
-
-/*
- * The Window Region on Broxton HPSRAM is organised like this :-
- * +--------------------------------------------------------------------------+
- * | Offset | Region | Size |
- * +---------------------+----------------+-----------------------------------+
- * | SRAM_TRACE_BASE | Trace Buffer W3| SRAM_TRACE_SIZE |
- * +---------------------+----------------+-----------------------------------+
- * | SRAM_DEBUG_BASE | Debug data W2 | SRAM_DEBUG_SIZE |
- * +---------------------+----------------+-----------------------------------+
- * | SRAM_INBOX_BASE | Inbox W1 | SRAM_INBOX_SIZE |
- * +---------------------+----------------+-----------------------------------+
- * | SRAM_OUTBOX_BASE | Outbox W0 | SRAM_MAILBOX_SIZE |
- * +---------------------+----------------+-----------------------------------+
- * | SRAM_SW_REG_BASE | SW Registers W0| SRAM_SW_REG_SIZE |
- * +---------------------+----------------+-----------------------------------+
- */
-
-/* window 3 - trace */
-#define MAILBOX_TRACE_SIZE SRAM_TRACE_SIZE
-#define MAILBOX_TRACE_BASE SRAM_TRACE_BASE
-
-/* window 2 debug, exception and stream */
-#define MAILBOX_DEBUG_SIZE SRAM_DEBUG_SIZE
-#define MAILBOX_DEBUG_BASE SRAM_DEBUG_BASE
-
-#define MAILBOX_EXCEPTION_SIZE SRAM_EXCEPT_SIZE
-#define MAILBOX_EXCEPTION_BASE SRAM_EXCEPT_BASE
-#define MAILBOX_EXCEPTION_OFFSET SRAM_DEBUG_SIZE
-
-#define MAILBOX_STREAM_SIZE SRAM_STREAM_SIZE
-#define MAILBOX_STREAM_BASE SRAM_STREAM_BASE
-#define MAILBOX_STREAM_OFFSET (SRAM_DEBUG_SIZE + SRAM_EXCEPT_SIZE)
-
-/* window 1 inbox/downlink and FW registers */
-#define MAILBOX_HOSTBOX_SIZE SRAM_INBOX_SIZE
-#define MAILBOX_HOSTBOX_BASE SRAM_INBOX_BASE
-
-/* window 0 */
-#define MAILBOX_DSPBOX_SIZE SRAM_OUTBOX_SIZE
-#define MAILBOX_DSPBOX_BASE SRAM_OUTBOX_BASE
-
-#define MAILBOX_SW_REG_SIZE SRAM_SW_REG_SIZE
-#define MAILBOX_SW_REG_BASE SRAM_SW_REG_BASE
-
-#endif
diff --git a/src/platform/apollolake/include/platform/memory.h b/src/platform/apollolake/include/platform/memory.h
deleted file mode 100644
index 7ddab6b..0000000
--- a/src/platform/apollolake/include/platform/memory.h
+++ /dev/null
@@ -1,362 +0,0 @@
-
-/*
- * Copyright (c) 2016, Intel Corporation
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- * * Redistributions of source code must retain the above copyright
- * notice, this list of conditions and the following disclaimer.
- * * Redistributions in binary form must reproduce the above copyright
- * notice, this list of conditions and the following disclaimer in the
- * documentation and/or other materials provided with the distribution.
- * * Neither the name of the Intel Corporation nor the
- * names of its contributors may be used to endorse or promote products
- * derived from this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
- * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
- * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
- * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
- * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
- * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
- * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
- * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
- * POSSIBILITY OF SUCH DAMAGE.
- *
- * Author: Liam Girdwood <liam.r.girdwood@linux.intel.com>
- * Keyon Jie <yang.jie@linux.intel.com>
- */
-
-#ifndef __PLATFORM_MEMORY_H__
-#define __PLATFORM_MEMORY_H__
-
-#include <config.h>
-
-/* physical DSP addresses */
-
-/* shim */
-#define SHIM_BASE 0x00001000
-#define SHIM_SIZE 0x00000100
-
-/* cmd IO to audio codecs */
-#define CMD_BASE 0x00001100
-#define CMD_SIZE 0x00000010
-
-/* resource allocation */
-#define RES_BASE 0x00001110
-#define RES_SIZE 0x00000010
-
-/* IPC to the host */
-#define IPC_HOST_BASE 0x00001180
-#define IPC_HOST_SIZE 0x00000020
-
-/* intra DSP IPC */
-#define IPC_DSP_SIZE 0x00000080
-#define IPC_DSP_BASE(x) (0x00001200 + x * IPC_DSP_SIZE)
-
-/* SRAM window for HOST */
-#define HOST_WIN_SIZE 0x00000008
-#define HOST_WIN_BASE(x) (0x00001580 + x * HOST_WIN_SIZE)
-
-/* IRQ controller */
-#define IRQ_BASE 0x00001600
-#define IRQ_SIZE 0x00000200
-
-/* time stamping */
-#define TIME_BASE 0x00001800
-#define TIME_SIZE 0x00000200
-
-/* M/N dividers */
-#define MN_BASE 0x00008E00
-#define MN_SIZE 0x00000200
-
-/* low power DMA position */
-#define LP_GP_DMA_LINK_SIZE 0x00000080
-#define LP_GP_DMA_LINK_BASE(x) (0x00001C00 + x * LP_GP_DMA_LINK_SIZE)
-
-/* high performance DMA position */
-#define HP_GP_DMA_LINK_SIZE 0x00000800
-#define HP_GP_DMA_LINK_BASE(x) (0x00001D00 + x * HP_GP_DMA_LINK_SIZE)
-
-/* link DMAC stream */
-#define GTW_LINK_OUT_STREAM_SIZE 0x00000020
-#define GTW_LINK_OUT_STREAM_BASE(x) \
- (0x00002400 + x * GTW_LINK_OUT_STREAM_SIZE)
-
-#define GTW_LINK_IN_STREAM_SIZE 0x00000020
-#define GTW_LINK_IN_STREAM_BASE(x) \
- (0x00002600 + x * GTW_LINK_IN_STREAM_SIZE)
-
-/* host DMAC stream */
-#define GTW_HOST_OUT_STREAM_SIZE 0x00000040
-#define GTW_HOST_OUT_STREAM_BASE(x) \
- (0x00002800 + x * GTW_HOST_OUT_STREAM_SIZE)
-
-#define GTW_HOST_IN_STREAM_SIZE 0x00000040
-#define GTW_HOST_IN_STREAM_BASE(x) \
- (0x00002C00 + x * GTW_HOST_IN_STREAM_SIZE)
-
-/* code loader */
-#define GTW_CODE_LDR_SIZE 0x00000040
-#define GTW_CODE_LDR_BASE 0x00002BC0
-
-/* L2 TLBs */
-#define L2_HP_SRAM_TLB_SIZE 0x00001000
-#define L2_HP_SRAM_TLB_BASE 0x00003000
-
-/* DMICs */
-#define DMIC_BASE 0x00004000
-#define DMIC_SIZE 0x00004000
-
-/* SSP */
-#define SSP_SIZE 0x0000200
-#define SSP_BASE(x) (0x00008000 + x * SSP_SIZE)
-
-/* low power DMACs */
-#define LP_GP_DMA_SIZE 0x00001000
-#define LP_GP_DMA_BASE(x) (0x0000C000 + x * LP_GP_DMA_SIZE)
-
-/* high performance DMACs */
-#define HP_GP_DMA_SIZE 0x00001000
-#define HP_GP_DMA_BASE(x) (0x0000E000 + x * HP_GP_DMA_SIZE)
-
-/* ROM */
-#define ROM_BASE 0xBEFE0000
-#define ROM_SIZE 0x00002000
-
-/* IMR accessible via L2$ */
-#define L2_SRAM_BASE 0xA000A000
-#define L2_SRAM_SIZE 0x00056000
-
-/* Heap section sizes for module pool */
-#define HEAP_RT_COUNT64 256
-#define HEAP_RT_COUNT128 32
-#define HEAP_RT_COUNT256 64
-#define HEAP_RT_COUNT512 32
-
-#define L2_VECTOR_SIZE 0x1000
-
-/* Heap configuration */
-#define HEAP_SYSTEM_BASE \
- (SOF_TEXT_BASE + SOF_TEXT_SIZE +\
- SOF_DATA_SIZE + SOF_BSS_DATA_SIZE)
-#define HEAP_SYSTEM_SIZE 0x8000
-
-#define HEAP_RUNTIME_BASE (HEAP_SYSTEM_BASE + HEAP_SYSTEM_SIZE)
-#define HEAP_RUNTIME_SIZE \
- (HEAP_RT_COUNT64 * 64 + HEAP_RT_COUNT128 * 128 + \
- HEAP_RT_COUNT256 * 256 + HEAP_RT_COUNT512 * 512)
-
-#define HEAP_BUFFER_BASE (HEAP_RUNTIME_BASE + HEAP_RUNTIME_SIZE)
-#define HEAP_BUFFER_SIZE (SOF_STACK_END - HEAP_BUFFER_BASE)
-#define HEAP_BUFFER_BLOCK_SIZE 0x180
-#define HEAP_BUFFER_COUNT (HEAP_BUFFER_SIZE / HEAP_BUFFER_BLOCK_SIZE)
-
-
-/*
- * The HP SRAM Region Apololake is organised like this :-
- * +--------------------------------------------------------------------------+
- * | Offset | Region | Size |
- * +---------------------+----------------+-----------------------------------+
- * | HP_SRAM_BASE | DMA | HEAP_HP_BUFFER_SIZE |
- * +---------------------+----------------+-----------------------------------+
- * | SRAM_TRACE_BASE | Trace Buffer W3| SRAM_TRACE_SIZE |
- * +---------------------+----------------+-----------------------------------+
- * | SRAM_DEBUG_BASE | Debug data W2 | SRAM_DEBUG_SIZE |
- * +---------------------+----------------+-----------------------------------+
- * | SRAM_EXCEPT_BASE | Debug data W2 | SRAM_EXCEPT_SIZE |
- * +---------------------+----------------+-----------------------------------+
- * | SRAM_STREAM_BASE | Stream data W2 | SRAM_STREAM_SIZE |
- * +---------------------+----------------+-----------------------------------+
- * | SRAM_INBOX_BASE | Inbox W1 | SRAM_INBOX_SIZE |
- * +---------------------+----------------+-----------------------------------+
- * | SRAM_SW_REG_BASE | SW Registers W0| SRAM_SW_REG_SIZE |
- * +---------------------+----------------+-----------------------------------+
- * | SRAM_OUTBOX_BASE | Outbox W0 | SRAM_MAILBOX_SIZE |
- * +---------------------+----------------+-----------------------------------+
- */
-
-/* HP SRAM */
-#define SRAM_ALIAS_OFFSET 0x20000000
-#define HP_SRAM_BASE 0xBE000000
-#define HP_SRAM_SIZE 0x00080000
-
-/* HP SRAM Heap */
-#define HEAP_HP_BUFFER_BASE HP_SRAM_BASE
-#define HEAP_HP_BUFFER_SIZE 0x8000
-
-#define HEAP_HP_BUFFER_BLOCK_SIZE 0x180
-#define HEAP_HP_BUFFER_COUNT \
- (HEAP_HP_BUFFER_SIZE / HEAP_HP_BUFFER_BLOCK_SIZE)
-
-/* HP SRAM windows */
-
-/* window 3 */
-#define SRAM_TRACE_BASE (HEAP_HP_BUFFER_BASE + HEAP_HP_BUFFER_SIZE)
-#define SRAM_TRACE_SIZE 0x2000
-
-/* window 2 */
-#define SRAM_DEBUG_BASE (SRAM_TRACE_BASE + SRAM_TRACE_SIZE)
-#define SRAM_DEBUG_SIZE 0x800
-
-#define SRAM_EXCEPT_BASE (SRAM_DEBUG_BASE + SRAM_DEBUG_SIZE)
-#define SRAM_EXCEPT_SIZE 0x800
-
-#define SRAM_STREAM_BASE (SRAM_EXCEPT_BASE + SRAM_EXCEPT_SIZE)
-#define SRAM_STREAM_SIZE 0x1000
-
-/* window 1 */
-#define SRAM_INBOX_BASE (SRAM_STREAM_BASE + SRAM_STREAM_SIZE)
-#define SRAM_INBOX_SIZE 0x2000
-
-/* window 0 */
-#define SRAM_SW_REG_BASE (SRAM_INBOX_BASE + SRAM_INBOX_SIZE)
-#define SRAM_SW_REG_SIZE 0x1000
-
-/* SRAM window 0 FW "registers" */
-#define SRAM_REG_ROM_STATUS 0x0
-#define SRAM_REG_FW_STATUS 0x4
-#define SRAM_REG_FW_TRACEP 0x8
-#define SRAM_REG_FW_END 0xc
-
-#define SRAM_OUTBOX_BASE (SRAM_SW_REG_BASE + SRAM_SW_REG_SIZE)
-#define SRAM_OUTBOX_SIZE 0x1000
-
-#define HP_SRAM_WIN0_BASE SRAM_SW_REG_BASE
-#define HP_SRAM_WIN0_SIZE (SRAM_SW_REG_SIZE + SRAM_OUTBOX_SIZE)
-#define HP_SRAM_WIN1_BASE SRAM_INBOX_BASE
-#define HP_SRAM_WIN1_SIZE SRAM_INBOX_SIZE
-#define HP_SRAM_WIN2_BASE SRAM_DEBUG_BASE
-#define HP_SRAM_WIN2_SIZE (SRAM_DEBUG_SIZE + SRAM_EXCEPT_SIZE + \
- SRAM_STREAM_SIZE)
-#define HP_SRAM_WIN3_BASE SRAM_TRACE_BASE
-#define HP_SRAM_WIN3_SIZE SRAM_TRACE_SIZE
-
-#define HP_SRAM_VECBASE_RESET (HP_SRAM_WIN0_BASE + HP_SRAM_WIN0_SIZE)
-
-
-#define SOF_TEXT_START (HP_SRAM_VECBASE_RESET + 0x400)
-#define SOF_TEXT_BASE (SOF_TEXT_START)
-#define SOF_TEXT_SIZE (0x19000 - 0x400)
-
-/* initialized data */
-#if defined CONFIG_DMIC
-#define SOF_DATA_SIZE 0x1b000
-#else
-#define SOF_DATA_SIZE 0x19000
-#endif
-
-/* bss data */
-#define SOF_BSS_DATA_SIZE 0x8700
-
-/* Stack configuration */
-#define SOF_STACK_SIZE 0x1000
-#define SOF_STACK_BASE (HP_SRAM_BASE + HP_SRAM_SIZE)
-#define SOF_STACK_END (SOF_STACK_BASE - SOF_STACK_SIZE)
-
-/*
- * The LP SRAM Heap and Stack on Apollolake are organised like this :-
- *
- * +--------------------------------------------------------------------------+
- * | Offset | Region | Size |
- * +---------------------+----------------+-----------------------------------+
- * | LP_SRAM_BASE | RO Data | SOF_LP_DATA_SIZE |
- * | | Data | |
- * | | BSS | |
- * +---------------------+----------------+-----------------------------------+
- * | HEAP_LP_SYSTEM_BASE | System Heap | HEAP_LP_SYSTEM_SIZE |
- * +---------------------+----------------+-----------------------------------+
- * | HEAP_LP_RUNTIME_BASE| Runtime Heap | HEAP_LP_RUNTIME_SIZE |
- * +---------------------+----------------+-----------------------------------+
- * | HEAP_LP_BUFFER_BASE | Module Buffers | HEAP_LP_BUFFER_SIZE |
- * +---------------------+----------------+-----------------------------------+
- * | SOF_LP_STACK_END | Stack | SOF_LP_STACK_SIZE |
- * +---------------------+----------------+-----------------------------------+
- * | SOF_STACK_BASE | | |
- * +---------------------+----------------+-----------------------------------+
- */
-
-/* LP SRAM */
-#define LP_SRAM_BASE 0xBE800000
-#define LP_SRAM_SIZE 0x00020000
-
-/* Heap section sizes for module pool */
-#define HEAP_RT_LP_COUNT8 0
-#define HEAP_RT_LP_COUNT16 256
-#define HEAP_RT_LP_COUNT32 128
-#define HEAP_RT_LP_COUNT64 64
-#define HEAP_RT_LP_COUNT128 32
-#define HEAP_RT_LP_COUNT256 16
-#define HEAP_RT_LP_COUNT512 8
-#define HEAP_RT_LP_COUNT1024 4
-
-/* Heap configuration */
-#define SOF_LP_DATA_SIZE 0x4000
-
-#define HEAP_LP_SYSTEM_BASE (LP_SRAM_BASE + SOF_LP_DATA_SIZE)
-#define HEAP_LP_SYSTEM_SIZE 0x1000
-
-#define HEAP_LP_RUNTIME_BASE \
- (HEAP_LP_SYSTEM_BASE + HEAP_LP_SYSTEM_SIZE)
-#define HEAP_LP_RUNTIME_SIZE \
- (HEAP_RT_LP_COUNT8 * 8 + HEAP_RT_LP_COUNT16 * 16 + \
- HEAP_RT_LP_COUNT32 * 32 + HEAP_RT_LP_COUNT64 * 64 + \
- HEAP_RT_LP_COUNT128 * 128 + HEAP_RT_LP_COUNT256 * 256 + \
- HEAP_RT_LP_COUNT512 * 512 + HEAP_RT_LP_COUNT1024 * 1024)
-
-#define HEAP_LP_BUFFER_BASE \
- (HEAP_LP_RUNTIME_BASE + HEAP_LP_RUNTIME_SIZE)
-#define HEAP_LP_BUFFER_SIZE \
- (LP_SRAM_SIZE - HEAP_LP_RUNTIME_SIZE - SOF_LP_STACK_SIZE - HEAP_LP_SYSTEM_SIZE)
-
-#define HEAP_LP_BUFFER_BLOCK_SIZE 0x180
-#define HEAP_LP_BUFFER_COUNT \
- (HEAP_LP_BUFFER_SIZE / HEAP_LP_BUFFER_BLOCK_SIZE)
-
-#define PLATFORM_HEAP_RUNTIME 1
-#define PLATFORM_HEAP_BUFFER 3
-
-/* Stack configuration */
-#define SOF_LP_STACK_SIZE 0x1000
-#define SOF_LP_STACK_BASE (LP_SRAM_BASE + LP_SRAM_SIZE)
-#define SOF_LP_STACK_END (SOF_LP_STACK_BASE - SOF_LP_STACK_SIZE)
-
-/* Vector and literal sizes - not in core-isa.h */
-#define SOF_MEM_VECT_LIT_SIZE 0x8
-#define SOF_MEM_VECT_TEXT_SIZE 0x38
-#define SOF_MEM_VECT_SIZE (SOF_MEM_VECT_TEXT_SIZE + SOF_MEM_VECT_LIT_SIZE)
-
-#define SOF_MEM_ERROR_TEXT_SIZE 0x180
-#define SOF_MEM_ERROR_LIT_SIZE 0x8
-
-#define SOF_MEM_VECBASE HP_SRAM_VECBASE_RESET
-#define SOF_MEM_VECBASE_LIT_SIZE 0x178
-
-#define SOF_MEM_RO_SIZE 0x8
-
-/* boot loader in IMR */
-#define IMR_BOOT_LDR_TEXT_ENTRY_BASE 0xB000A000
-#define IMR_BOOT_LDR_TEXT_ENTRY_SIZE 0x86
-#define IMR_BOOT_LDR_LIT_BASE (IMR_BOOT_LDR_TEXT_ENTRY_BASE + \
- IMR_BOOT_LDR_TEXT_ENTRY_SIZE)
-#define IMR_BOOT_LDR_LIT_SIZE 0x70
-#define IMR_BOOT_LDR_TEXT_BASE (IMR_BOOT_LDR_LIT_BASE + \
- IMR_BOOT_LDR_LIT_SIZE)
-#define IMR_BOOT_LDR_TEXT_SIZE 0x1C00
-#define IMR_BOOT_LDR_TEXT1_BASE (IMR_BOOT_LDR_TEXT_BASE + IMR_BOOT_LDR_TEXT_SIZE)
-#define IMR_BOOT_LDR_TEXT1_SIZE 0x2000
-#define IMR_BOOT_LDR_DATA_BASE 0xB0002000
-#define IMR_BOOT_LDR_DATA_SIZE 0x1000
-#define IMR_BOOT_LDR_BSS_BASE 0xB0100000
-#define IMR_BOOT_LDR_BSS_SIZE 0x10000
-
-/** \brief Manifest base address in IMR - used by boot loader copy procedure. */
-#define IMR_BOOT_LDR_MANIFEST_BASE 0xB0004000
-
-/** \brief Manifest size (seems unused). */
-#define IMR_BOOT_LDR_MANIFEST_SIZE 0x6000
-
-#endif
diff --git a/src/platform/apollolake/include/platform/platcfg.h b/src/platform/apollolake/include/platform/platcfg.h
deleted file mode 100644
index f5b9ac8..0000000
--- a/src/platform/apollolake/include/platform/platcfg.h
+++ /dev/null
@@ -1,48 +0,0 @@
-/*
- * Copyright (c) 2018, Intel Corporation
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- * * Redistributions of source code must retain the above copyright
- * notice, this list of conditions and the following disclaimer.
- * * Redistributions in binary form must reproduce the above copyright
- * notice, this list of conditions and the following disclaimer in the
- * documentation and/or other materials provided with the distribution.
- * * Neither the name of the Intel Corporation nor the
- * names of its contributors may be used to endorse or promote products
- * derived from this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
- * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
- * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
- * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
- * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
- * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
- * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
- * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
- * POSSIBILITY OF SUCH DAMAGE.
- *
- * Author: Marcin Maka <marcin.maka@linux.intel.com>
- */
-
-#ifndef __PLATFORM_PLATCFG_H__
-#define __PLATFORM_PLATCFG_H__
-
-#define PLATFORM_RESET_MHE_AT_BOOT 1
-
-#define PLATFORM_DISABLE_L2CACHE_AT_BOOT 1
-
-#define PLATFORM_CORE_COUNT 2
-
-#define PLATFORM_LPSRAM_EBB_COUNT 2
-
-#define PLATFORM_HPSRAM_EBB_COUNT 8
-
-#define PLATFORM_HPSRAM_SEGMENTS 1
-
-#define PLATFORM_MASTER_CORE_ID 0
-
-#endif
diff --git a/src/platform/apollolake/include/platform/platform.h b/src/platform/apollolake/include/platform/platform.h
deleted file mode 100644
index 90f5b56..0000000
--- a/src/platform/apollolake/include/platform/platform.h
+++ /dev/null
@@ -1,159 +0,0 @@
-/*
- * Copyright (c) 2016, Intel Corporation
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- * * Redistributions of source code must retain the above copyright
- * notice, this list of conditions and the following disclaimer.
- * * Redistributions in binary form must reproduce the above copyright
- * notice, this list of conditions and the following disclaimer in the
- * documentation and/or other materials provided with the distribution.
- * * Neither the name of the Intel Corporation nor the
- * names of its contributors may be used to endorse or promote products
- * derived from this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
- * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
- * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
- * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
- * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
- * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
- * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
- * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
- * POSSIBILITY OF SUCH DAMAGE.
- *
- * Author: Liam Girdwood <liam.r.girdwood@linux.intel.com>
- * Keyon Jie <yang.jie@linux.intel.com>
- * Xiuli Pan <xiuli.pan@linux.intel.com>
- */
-
-#ifndef __PLATFORM_PLATFORM_H__
-#define __PLATFORM_PLATFORM_H__
-
-#include <sof/platform.h>
-#include <platform/platcfg.h>
-#include <platform/shim.h>
-#include <platform/interrupt.h>
-#include <uapi/ipc.h>
-
-struct sof;
-
-/* DGMBS align value */
-#define PLATFORM_HDA_BUFFER_ALIGNMENT 0x20
-
-/* Host page size */
-#define HOST_PAGE_SIZE 4096
-#define PLATFORM_PAGE_TABLE_SIZE 256
-
-/* IDC Interrupt */
-#define PLATFORM_IDC_INTERRUPT(x) IRQ_EXT_IDC_LVL2(x)
-
-/* IPC Interrupt */
-#define PLATFORM_IPC_INTERUPT IRQ_EXT_IPC_LVL2(0)
-
-/* pipeline IRQ */
-#define PLATFORM_SCHEDULE_IRQ IRQ_NUM_SOFTWARE4
-
-#define PLATFORM_IRQ_TASK_HIGH IRQ_NUM_SOFTWARE3
-#define PLATFORM_IRQ_TASK_MED IRQ_NUM_SOFTWARE2
-#define PLATFORM_IRQ_TASK_LOW IRQ_NUM_SOFTWARE1
-
-#define PLATFORM_SCHEDULE_COST 200
-
-/* maximum preload pipeline depth */
-#define MAX_PRELOAD_SIZE 20
-
-/* DMA treats PHY addresses as host address unless within DSP region */
-#define PLATFORM_HOST_DMA_MASK 0x00000000
-
-/* Platform stream capabilities */
-#define PLATFORM_MAX_CHANNELS 8
-#define PLATFORM_MAX_STREAMS 16
-
-/* clock source used by scheduler for deadline calculations */
-#define PLATFORM_SCHED_CLOCK CLK_SSP
-
-/* DMA channel drain timeout in microseconds - TODO: caclulate based on topology */
-#define PLATFORM_DMA_TIMEOUT 1333
-
-/* DMA host transfer timeouts in microseconds */
-#define PLATFORM_HOST_DMA_TIMEOUT 50
-
-/* WorkQ window size in microseconds */
-#define PLATFORM_WORKQ_WINDOW 2000
-
-/* platform WorkQ clock */
-#define PLATFORM_WORKQ_CLOCK CLK_SSP
-
-/* Host finish work schedule delay in microseconds */
-#define PLATFORM_HOST_FINISH_DELAY 100
-
-/* Host finish work(drain from host to dai) timeout in microseconds */
-#define PLATFORM_HOST_FINISH_TIMEOUT 50000
-
-/* local buffer size of DMA tracing */
-#define DMA_TRACE_LOCAL_SIZE HOST_PAGE_SIZE
-
-/* trace bytes flushed during panic */
-#define DMA_FLUSH_TRACE_SIZE (MAILBOX_TRACE_SIZE >> 2)
-
-/* the interval of DMA trace copying */
-#define DMA_TRACE_PERIOD 500000
-
-/*
- * the interval of reschedule DMA trace copying in special case like half
- * fullness of local DMA trace buffer
- */
-#define DMA_TRACE_RESCHEDULE_TIME 5
-
-/* DSP should be idle in this time frame */
-#define PLATFORM_IDLE_TIME 750000
-
-/* platform has DMA memory type */
-#define PLATFORM_MEM_HAS_DMA
-
-/* platform has low power memory type */
-#define PLATFORM_MEM_HAS_LP_RAM
-
-/* number of SSP ports in platform */
-#define PLATFORM_NUM_SSP 6
-
-/* DSP default delay in cycles */
-#define PLATFORM_DEFAULT_DELAY 12
-
-/* minimal L1 exit time in cycles */
-#define PLATFORM_FORCE_L1_EXIT_TIME 585
-
-/* the SSP port fifo depth */
-#define SSP_FIFO_DEPTH 16
-
-/* the watermark for the SSP fifo depth setting */
-#define SSP_FIFO_WATERMARK 8
-
-/* Platform defined panic code */
-static inline void platform_panic(uint32_t p)
-{
- mailbox_sw_reg_write(SRAM_REG_FW_STATUS, p & 0x3fffffff);
- ipc_write(IPC_DIPCIE, MAILBOX_EXCEPTION_OFFSET + 2 * 0x20000);
- ipc_write(IPC_DIPCI, 0x80000000 | (p & 0x3fffffff));
-}
-
-/* Platform defined trace code */
-#define platform_trace_point(__x) \
- mailbox_sw_reg_write(SRAM_REG_FW_TRACEP, (__x))
-
-extern struct timer *platform_timer;
-
-/*
- * APIs declared here are defined for every platform and IPC mechanism.
- */
-
-int platform_ssp_set_mn(uint32_t ssp_port, uint32_t source, uint32_t rate,
- uint32_t bclk_fs);
-
-void platform_ssp_disable_mn(uint32_t ssp_port);
-
-#endif
diff --git a/src/platform/apollolake/include/platform/pm_runtime.h b/src/platform/apollolake/include/platform/pm_runtime.h
deleted file mode 100644
index 3c16fe4..0000000
--- a/src/platform/apollolake/include/platform/pm_runtime.h
+++ /dev/null
@@ -1,72 +0,0 @@
-/*
- * Copyright (c) 2018, Intel Corporation
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- * * Redistributions of source code must retain the above copyright
- * notice, this list of conditions and the following disclaimer.
- * * Redistributions in binary form must reproduce the above copyright
- * notice, this list of conditions and the following disclaimer in the
- * documentation and/or other materials provided with the distribution.
- * * Neither the name of the Intel Corporation nor the
- * names of its contributors may be used to endorse or promote products
- * derived from this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
- * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
- * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
- * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
- * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
- * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
- * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
- * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
- * POSSIBILITY OF SUCH DAMAGE.
- *
- * Author: Tomasz Lauda <tomasz.lauda@linux.intel.com>
- */
-
-/**
- * \file platform/apollolake/include/platform/pm_runtime.h
- * \brief Runtime power management header file for Apollolake
- * \author Tomasz Lauda <tomasz.lauda@linux.intel.com>
- */
-
-#ifndef __INCLUDE_PLATFORM_PM_RUNTIME__
-#define __INCLUDE_PLATFORM_PM_RUNTIME__
-
-#include <sof/pm_runtime.h>
-
-/** \brief Platform specific runtime power management data. */
-struct platform_pm_runtime_data {
- /* TBD */
-};
-
-/**
- * \brief Initializes platform specific runtime power management.
- * \param[in,out] prd Runtime power management data.
- */
-void platform_pm_runtime_init(struct pm_runtime_data *prd);
-
-/**
- * \brief Retrieves platform specific power management resource.
- * \param[in] context Type of power management context.
- */
-void platform_pm_runtime_get(enum pm_runtime_context context);
-
-/**
- * \brief Releases platform specific power management resource.
- * \param[in] context Type of power management context.
- */
-void platform_pm_runtime_put(enum pm_runtime_context context);
-
-
-/**
- * \brief Power gates platform specific hardware resources.
- * \param[in] context Type of power management context.
- */
-void platform_pm_runtime_power_off(void);
-
-#endif /* __INCLUDE_PLATFORM_PM_RUNTIME__ */
diff --git a/src/platform/apollolake/include/platform/power_down.h b/src/platform/apollolake/include/platform/power_down.h
deleted file mode 100644
index 63db59d..0000000
--- a/src/platform/apollolake/include/platform/power_down.h
+++ /dev/null
@@ -1,43 +0,0 @@
-/*
- * Copyright (c) 2018, Intel Corporation
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- * * Redistributions of source code must retain the above copyright
- * notice, this list of conditions and the following disclaimer.
- * * Redistributions in binary form must reproduce the above copyright
- * notice, this list of conditions and the following disclaimer in the
- * documentation and/or other materials provided with the distribution.
- * * Neither the name of the Intel Corporation nor the
- * names of its contributors may be used to endorse or promote products
- * derived from this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
- * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
- * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
- * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
- * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
- * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
- * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
- * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
- * POSSIBILITY OF SUCH DAMAGE.
- *
- * Author: Lech Betlej <lech.betlej@linux.intel.com>
- */
-#ifndef POWER_DOWN_H
-#define POWER_DOWN_H
-
-#include <stdbool.h>
-/**
- * Power down procedure.
- * Locks its code in L1 cache and shuts down memories.
- * @param disable_lpsram flag if LPSRAM is to be disabled (whole)
- * @param hpsram_pwrgating_mask pointer to memory segments power gating mask
- * (each bit corresponds to one ebb)
- * @return nothing returned - this function never quits
- */
-void power_down(bool disable_lpsram, uint32_t *hpsram_pwrgating_mask);
-#endif /* POWER_DOWN_H */
diff --git a/src/platform/apollolake/include/platform/shim.h b/src/platform/apollolake/include/platform/shim.h
deleted file mode 100644
index a121410..0000000
--- a/src/platform/apollolake/include/platform/shim.h
+++ /dev/null
@@ -1,303 +0,0 @@
-/*
- * Copyright (c) 2016, Intel Corporation
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- * * Redistributions of source code must retain the above copyright
- * notice, this list of conditions and the following disclaimer.
- * * Redistributions in binary form must reproduce the above copyright
- * notice, this list of conditions and the following disclaimer in the
- * documentation and/or other materials provided with the distribution.
- * * Neither the name of the Intel Corporation nor the
- * names of its contributors may be used to endorse or promote products
- * derived from this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
- * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
- * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
- * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
- * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
- * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
- * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
- * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
- * POSSIBILITY OF SUCH DAMAGE.
- *
- * Author: Liam Girdwood <liam.r.girdwood@linux.intel.com>
- * Keyon Jie <yang.jie@linux.intel.com>
- */
-
-#ifndef __PLATFORM_SHIM_H__
-#define __PLATFORM_SHIM_H__
-
-#include <platform/memory.h>
-
-#ifndef ASSEMBLY
-#include <stdint.h>
-#endif
-
-/* DSP IPC for Host Registers */
-#define IPC_DIPCT 0x00
-#define IPC_DIPCTE 0x04
-#define IPC_DIPCI 0x08
-#define IPC_DIPCIE 0x0c
-#define IPC_DIPCCTL 0x10
-
-/* DIPCT */
-#define IPC_DIPCT_BUSY (1 << 31)
-#define IPC_DIPCT_MSG_MASK 0x7FFFFFFF
-
-/* DIPCTE */
-#define IPC_DIPCTE_MSG_MASK 0x3FFFFFFF
-
-/* DIPCI */
-#define IPC_DIPCI_BUSY (1 << 31)
-#define IPC_DIPCI_MSG_MASK 0x7FFFFFFF
-
-/* DIPCIE */
-#define IPC_DIPCIE_DONE (1 << 30)
-#define IPC_DIPCIE_MSG_MASK 0x3FFFFFFF
-
-/* DIPCCTL */
-#define IPC_DIPCCTL_IPCIDIE (1 << 1)
-#define IPC_DIPCCTL_IPCTBIE (1 << 0)
-
-#define IPC_DSP_OFFSET 0x10
-
-/* DSP IPC for intra DSP communication */
-#define IPC_IDCTFC(x) (0x0 + x * IPC_DSP_OFFSET)
-#define IPC_IDCTEFC(x) (0x4 + x * IPC_DSP_OFFSET)
-#define IPC_IDCITC(x) (0x8 + x * IPC_DSP_OFFSET)
-#define IPC_IDCIETC(x) (0xc + x * IPC_DSP_OFFSET)
-#define IPC_IDCCTL 0x50
-
-/* IDCTFC */
-#define IPC_IDCTFC_BUSY (1 << 31)
-#define IPC_IDCTFC_MSG_MASK 0x7FFFFFFF
-
-/* IDCTEFC */
-#define IPC_IDCTEFC_MSG_MASK 0x3FFFFFFF
-
-/* IDCITC */
-#define IPC_IDCITC_BUSY (1 << 31)
-#define IPC_IDCITC_MSG_MASK 0x7FFFFFFF
-
-/* IDCIETC */
-#define IPC_IDCIETC_DONE (1 << 30)
-#define IPC_IDCIETC_MSG_MASK 0x3FFFFFFF
-
-/* IDCCTL */
-#define IPC_IDCCTL_IDCIDIE(x) (0x100 << (x))
-#define IPC_IDCCTL_IDCTBIE(x) (0x1 << (x))
-
-#define IRQ_CPU_OFFSET 0x40
-
-#define REG_IRQ_IL2MSD(xcpu) (0x0 + (xcpu * IRQ_CPU_OFFSET))
-#define REG_IRQ_IL2MCD(xcpu) (0x4 + (xcpu * IRQ_CPU_OFFSET))
-#define REG_IRQ_IL2MD(xcpu) (0x8 + (xcpu * IRQ_CPU_OFFSET))
-#define REG_IRQ_IL2SD(xcpu) (0xc + (xcpu * IRQ_CPU_OFFSET))
-
-/* all mask valid bits */
-#define REG_IRQ_IL2MD_ALL 0x03F181F0
-
-#define REG_IRQ_IL3MSD(xcpu) (0x10 + (xcpu * IRQ_CPU_OFFSET))
-#define REG_IRQ_IL3MCD(xcpu) (0x14 + (xcpu * IRQ_CPU_OFFSET))
-#define REG_IRQ_IL3MD(xcpu) (0x18 + (xcpu * IRQ_CPU_OFFSET))
-#define REG_IRQ_IL3SD(xcpu) (0x1c + (xcpu * IRQ_CPU_OFFSET))
-
-/* all mask valid bits */
-#define REG_IRQ_IL3MD_ALL 0x807F81FF
-
-#define REG_IRQ_IL4MSD(xcpu) (0x20 + (xcpu * IRQ_CPU_OFFSET))
-#define REG_IRQ_IL4MCD(xcpu) (0x24 + (xcpu * IRQ_CPU_OFFSET))
-#define REG_IRQ_IL4MD(xcpu) (0x28 + (xcpu * IRQ_CPU_OFFSET))
-#define REG_IRQ_IL4SD(xcpu) (0x2c + (xcpu * IRQ_CPU_OFFSET))
-
-/* all mask valid bits */
-#define REG_IRQ_IL4MD_ALL 0x807F81FF
-
-#define REG_IRQ_IL5MSD(xcpu) (0x30 + (xcpu * IRQ_CPU_OFFSET))
-#define REG_IRQ_IL5MCD(xcpu) (0x34 + (xcpu * IRQ_CPU_OFFSET))
-#define REG_IRQ_IL5MD(xcpu) (0x38 + (xcpu * IRQ_CPU_OFFSET))
-#define REG_IRQ_IL5SD(xcpu) (0x3c + (xcpu * IRQ_CPU_OFFSET))
-
-/* all mask valid bits */
-#define REG_IRQ_IL5MD_ALL 0xFFFFC0CF
-
-#define REG_IRQ_IL2RSD 0x100
-#define REG_IRQ_IL3RSD 0x104
-#define REG_IRQ_IL4RSD 0x108
-#define REG_IRQ_IL5RSD 0x10c
-
-#define REG_IRQ_LVL5_LP_GPDMA0_MASK (0xff << 16)
-#define REG_IRQ_LVL5_LP_GPDMA1_MASK (0xff << 24)
-
-/* DSP Shim Registers */
-#define SHIM_DSPWC 0x20 /* DSP Wall Clock */
-#define SHIM_DSPWCTCS 0x28 /* DSP Wall Clock Timer Control & Status */
-#define SHIM_DSPWCT0C 0x30 /* DSP Wall Clock Timer 0 Compare */
-#define SHIM_DSPWCT1C 0x38 /* DSP Wall Clock Timer 1 Compare */
-
-#define SHIM_DSPWCTCS_T1T (0x1 << 5) /* Timer 1 triggered */
-#define SHIM_DSPWCTCS_T0T (0x1 << 4) /* Timer 0 triggered */
-#define SHIM_DSPWCTCS_T1A (0x1 << 1) /* Timer 1 armed */
-#define SHIM_DSPWCTCS_T0A (0x1 << 0) /* Timer 0 armed */
-
-#define SHIM_CLKCTL 0x78
-#define SHIM_CLKSTS 0x7C
-
-#define SHIM_CLKCTL_RAPLLC (0x1 << 31)
-#define SHIM_CLKCTL_RXOSCC (0x1 << 30)
-#define SHIM_CLKCTL_RFROSCC (0x1 << 29)
-
-#define SHIM_LDOCTL 0xA4
-
-/* LP GPDMA Force Dynamic Clock Gating bits, 0--enable */
-#define SHIM_CLKCTL_LPGPDMAFDCGB(x) (0x1 << (26 + x))
-#define SHIM_CLKCTL_DMICFDCGB (0x1 << 24)
-#define SHIM_CLKCTL_I2SFDCGB(x) (0x1 << (20 + x))
-#define SHIM_CLKCTL_I2SEFDCGB(x) (0x1 << (18 + x))
-#define SHIM_CLKCTL_TCPLCG(x) (0x1 << (16 + x))
-
-/* Core clock PLL divisor */
-#define SHIM_CLKCTL_DPCS_MASK(x) (0x3 << (8 + x * 2))
-/* Prevent Audio PLL Shutdown */
-#define SHIM_CLKCTL_TCPAPLLS (0x1 << 7)
-
-/* 0--from PLL, 1--from oscillator */
-#define SHIM_CLKCTL_LDCS (0x1 << 5)
-#define SHIM_CLKCTL_HDCS (0x1 << 4)
-
-/* Oscillator clock select select 0--XTAL, 1--Fast RING*/
-#define SHIM_CLKCTL_LDOCS (0x1 << 3)
-#define SHIM_CLKCTL_HDOCS (0x1 << 2)
-
-/* HP memory clock PLL divisor */
-#define SHIM_CLKCTL_HPMPCS (0x1 << 0)
-
-#define SHIM_PWRCTL 0x90
-#define SHIM_PWRSTS 0x92
-#define SHIM_LPSCTL 0x94
-
-/* HP & LP SRAM Power Gating */
-#define SHIM_HSPGCTL 0x80
-#define SHIM_LSPGCTL 0x84
-#define SHIM_SPSREQ 0xa0
-
-#define SHIM_SPSREQ_RVNNP (0x1 << 0)
-
-#define SHIM_HSPGISTS 0xb0
-#define SHIM_LSPGISTS 0xb4
-
-
-#define SHIM_LPSCTL_FDSPRUN (0X1 << 9)
-#define SHIM_LPSCTL_FDMARUN (0X1 << 8)
-
-#define SHIM_L2_MECS (SHIM_BASE + 0xd0)
-
-#define SHIM_LPGPDMAC(x) (0x1110 + (2 * x))
-#define SHIM_LPGPDMAC_CTLOSEL (1 << 15)
-#define SHIM_LPGPDMAC_CHOSEL (0xFF)
-
-#define SHIM_DSPIOPO 0x1118
-#define SHIM_DSPIOPO_DMICOSEL (1 << 0)
-#define SHIM_DSPIOPO_I2SOSEL (0x3F << 8)
-
-#define SHIM_GENO 0x111C
-#define SHIM_GENO_SHIMOSEL (1 << 0)
-#define SHIM_GENO_MDIVOSEL (1 << 1)
-#define SHIM_GENO_DIOPTOSEL (1 << 2)
-
-#define SHIM_L2_CACHE_CTRL (SHIM_BASE + 0x500)
-#define SHIM_L2_PREF_CFG (SHIM_BASE + 0x508)
-#define SHIM_L2_CACHE_PREF (SHIM_BASE + 0x510)
-
-#define SHIM_SVCFG 0xF4
-#define SHIM_SVCFG_FORCE_L1_EXIT (0x1 << 1)
-
-
-/* host windows */
-#define DMWBA(x) (HOST_WIN_BASE(x) + 0x0)
-#define DMWLO(x) (HOST_WIN_BASE(x) + 0x4)
-
-#define DMWBA_ENABLE (1 << 0)
-#define DMWBA_READONLY (1 << 1)
-
-#ifndef ASSEMBLY
-
-static inline uint32_t shim_read(uint32_t reg)
-{
- return *((volatile uint32_t*)(SHIM_BASE + reg));
-}
-
-static inline void shim_write(uint32_t reg, uint32_t val)
-{
- *((volatile uint32_t*)(SHIM_BASE + reg)) = val;
-}
-
-static inline uint64_t shim_read64(uint32_t reg)
-{
- return *((volatile uint64_t*)(SHIM_BASE + reg));
-}
-
-static inline void shim_write64(uint32_t reg, uint64_t val)
-{
- *((volatile uint64_t*)(SHIM_BASE + reg)) = val;
-}
-
-static inline uint32_t sw_reg_read(uint32_t reg)
-{
- return *((volatile uint32_t*)((SRAM_SW_REG_BASE -
- SRAM_ALIAS_OFFSET) + reg));
-}
-
-static inline void sw_reg_write(uint32_t reg, uint32_t val)
-{
- *((volatile uint32_t*)((SRAM_SW_REG_BASE -
- SRAM_ALIAS_OFFSET) + reg)) = val;
-}
-
-static inline uint32_t mn_reg_read(uint32_t reg)
-{
- return *((volatile uint32_t*)(MN_BASE + reg));
-}
-
-static inline void mn_reg_write(uint32_t reg, uint32_t val)
-{
- *((volatile uint32_t*)(MN_BASE + reg)) = val;
-}
-
-static inline uint32_t irq_read(uint32_t reg)
-{
- return *((volatile uint32_t*)(IRQ_BASE + reg));
-}
-
-static inline void irq_write(uint32_t reg, uint32_t val)
-{
- *((volatile uint32_t*)(IRQ_BASE + reg)) = val;
-}
-
-static inline uint32_t ipc_read(uint32_t reg)
-{
- return *((volatile uint32_t*)(IPC_HOST_BASE + reg));
-}
-
-static inline void ipc_write(uint32_t reg, uint32_t val)
-{
- *((volatile uint32_t*)(IPC_HOST_BASE + reg)) = val;
-}
-
-static inline uint32_t idc_read(uint32_t reg, uint32_t core_id)
-{
- return *((volatile uint32_t*)(IPC_DSP_BASE(core_id) + reg));
-}
-
-static inline void idc_write(uint32_t reg, uint32_t core_id, uint32_t val)
-{
- *((volatile uint32_t*)(IPC_DSP_BASE(core_id) + reg)) = val;
-}
-#endif
-
-#endif
diff --git a/src/platform/apollolake/include/platform/timer.h b/src/platform/apollolake/include/platform/timer.h
deleted file mode 100644
index e4977e4..0000000
--- a/src/platform/apollolake/include/platform/timer.h
+++ /dev/null
@@ -1,69 +0,0 @@
-/*
- * Copyright (c) 2016, Intel Corporation
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- * * Redistributions of source code must retain the above copyright
- * notice, this list of conditions and the following disclaimer.
- * * Redistributions in binary form must reproduce the above copyright
- * notice, this list of conditions and the following disclaimer in the
- * documentation and/or other materials provided with the distribution.
- * * Neither the name of the Intel Corporation nor the
- * names of its contributors may be used to endorse or promote products
- * derived from this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
- * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
- * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
- * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
- * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
- * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
- * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
- * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
- * POSSIBILITY OF SUCH DAMAGE.
- *
- * Author: Liam Girdwood <liam.r.girdwood@linux.intel.com>
- * Keyon Jie <yang.jie@linux.intel.com>
- */
-
-#ifndef __PLATFORM_TIMER_H__
-#define __PLATFORM_TIMER_H__
-
-#include <stdint.h>
-#include <sof/timer.h>
-#include <platform/interrupt.h>
-
-#define TIMER_COUNT 5
-
-/* timer numbers must use associated IRQ number */
-#define TIMER0 IRQ_NUM_TIMER1
-#define TIMER1 IRQ_NUM_TIMER2
-#define TIMER2 IRQ_NUM_TIMER3
-#define TIMER3 IRQ_EXT_TSTAMP0_LVL2(0)
-#define TIMER4 IRQ_EXT_TSTAMP1_LVL2(0)
-
-struct comp_dev;
-struct sof_ipc_stream_posn;
-
-int platform_timer_set(struct timer *timer, uint64_t ticks);
-void platform_timer_clear(struct timer *timer);
-uint64_t platform_timer_get(struct timer *timer);
-void platform_timer_start(struct timer *timer);
-void platform_timer_stop(struct timer *timer);
-int platform_timer_register(struct timer *timer,
- void (*handler)(void *arg), void *arg);
-
-/* get timestamp for host stream DMA position */
-void platform_host_timestamp(struct comp_dev *host,
- struct sof_ipc_stream_posn *posn);
-
-/* get timestamp for DAI stream DMA position */
-void platform_dai_timestamp(struct comp_dev *dai,
- struct sof_ipc_stream_posn *posn);
-
-/* get current wallclock for componnent */
-void platform_dai_wallclock(struct comp_dev *dai, uint64_t *wallclock);
-#endif
diff --git a/src/platform/apollolake/platform.c b/src/platform/apollolake/platform.c
deleted file mode 100644
index 4c5173f..0000000
--- a/src/platform/apollolake/platform.c
+++ /dev/null
@@ -1,302 +0,0 @@
-/*
- * Copyright (c) 2017, Intel Corporation
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- * * Redistributions of source code must retain the above copyright
- * notice, this list of conditions and the following disclaimer.
- * * Redistributions in binary form must reproduce the above copyright
- * notice, this list of conditions and the following disclaimer in the
- * documentation and/or other materials provided with the distribution.
- * * Neither the name of the Intel Corporation nor the
- * names of its contributors may be used to endorse or promote products
- * derived from this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
- * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
- * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
- * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
- * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
- * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
- * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
- * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
- * POSSIBILITY OF SUCH DAMAGE.
- *
- * Author: Liam Girdwood <liam.r.girdwood@linux.intel.com>
- * Keyon Jie <yang.jie@linux.intel.com>
- */
-
-#include <platform/memory.h>
-#include <platform/mailbox.h>
-#include <platform/shim.h>
-#include <platform/dma.h>
-#include <platform/clk.h>
-#include <platform/timer.h>
-#include <platform/interrupt.h>
-#include <uapi/ipc.h>
-#include <sof/mailbox.h>
-#include <sof/dai.h>
-#include <sof/dma.h>
-#include <sof/sof.h>
-#include <sof/agent.h>
-#include <sof/work.h>
-#include <sof/clock.h>
-#include <sof/ipc.h>
-#include <sof/io.h>
-#include <sof/trace.h>
-#include <sof/audio/component.h>
-#include <string.h>
-#include <version.h>
-
-static const struct sof_ipc_fw_ready ready = {
- .hdr = {
- .cmd = SOF_IPC_FW_READY,
- .size = sizeof(struct sof_ipc_fw_ready),
- },
- .version = {
- .build = SOF_BUILD,
- .minor = SOF_MINOR,
- .major = SOF_MAJOR,
- .date = __DATE__,
- .time = __TIME__,
- .tag = SOF_TAG,
- },
-};
-
-#define SRAM_WINDOW_HOST_OFFSET(x) (0x80000 + x * 0x20000)
-
-#define NUM_APL_WINDOWS 7
-
-static const struct sof_ipc_window sram_window = {
- .ext_hdr = {
- .hdr.cmd = SOF_IPC_FW_READY,
- .hdr.size = sizeof(struct sof_ipc_window) +
- sizeof(struct sof_ipc_window_elem) * NUM_APL_WINDOWS,
- .type = SOF_IPC_EXT_WINDOW,
- },
- .num_windows = NUM_APL_WINDOWS,
- .window = {
- {
- .type = SOF_IPC_REGION_REGS,
- .id = 0, /* map to host window 0 */
- .flags = 0, // TODO: set later
- .size = MAILBOX_SW_REG_SIZE,
- .offset = 0,
- },
- {
- .type = SOF_IPC_REGION_UPBOX,
- .id = 0, /* map to host window 0 */
- .flags = 0, // TODO: set later
- .size = MAILBOX_DSPBOX_SIZE,
- .offset = MAILBOX_SW_REG_SIZE,
- },
- {
- .type = SOF_IPC_REGION_DOWNBOX,
- .id = 1, /* map to host window 1 */
- .flags = 0, // TODO: set later
- .size = MAILBOX_HOSTBOX_SIZE,
- .offset = 0,
- },
- {
- .type = SOF_IPC_REGION_DEBUG,
- .id = 2, /* map to host window 2 */
- .flags = 0, // TODO: set later
- .size = MAILBOX_EXCEPTION_SIZE + MAILBOX_DEBUG_SIZE,
- .offset = 0,
- },
- {
- .type = SOF_IPC_REGION_EXCEPTION,
- .id = 2, /* map to host window 2 */
- .flags = 0, // TODO: set later
- .size = MAILBOX_EXCEPTION_SIZE,
- .offset = MAILBOX_EXCEPTION_OFFSET,
- },
- {
- .type = SOF_IPC_REGION_STREAM,
- .id = 2, /* map to host window 2 */
- .flags = 0, // TODO: set later
- .size = MAILBOX_STREAM_SIZE,
- .offset = MAILBOX_STREAM_OFFSET,
- },
- {
- .type = SOF_IPC_REGION_TRACE,
- .id = 3, /* map to host window 3 */
- .flags = 0, // TODO: set later
- .size = MAILBOX_TRACE_SIZE,
- .offset = 0,
- },
- },
-};
-
-static struct work_queue_timesource platform_generic_queue = {
- .timer = {
- .id = TIMER3, /* external timer, XTAL 19.2M */
- .irq = IRQ_EXT_TSTAMP0_LVL2(0),
- },
- .clk = CLK_SSP,
- .notifier = NOTIFIER_ID_SSP_FREQ,
- .timer_set = platform_timer_set,
- .timer_clear = platform_timer_clear,
- .timer_get = platform_timer_get,
-};
-
-struct timer *platform_timer = &platform_generic_queue.timer;
-
-int platform_boot_complete(uint32_t boot_message)
-{
- mailbox_dspbox_write(0, &ready, sizeof(ready));
- mailbox_dspbox_write(sizeof(ready), &sram_window,
- sram_window.ext_hdr.hdr.size);
-
- /* boot now complete so we can relax the CPU */
- clock_set_freq(CLK_CPU, CLK_DEFAULT_CPU_HZ);
-
- /* tell host we are ready */
- ipc_write(IPC_DIPCIE, SRAM_WINDOW_HOST_OFFSET(0) >> 12);
- ipc_write(IPC_DIPCI, 0x80000000 | SOF_IPC_FW_READY);
-
- return 0;
-}
-
-static void platform_memory_windows_init(void)
-{
- /* window0, for fw status & outbox/uplink mbox */
- io_reg_write(DMWLO(0), HP_SRAM_WIN0_SIZE | 0x7);
- io_reg_write(DMWBA(0), HP_SRAM_WIN0_BASE
- | DMWBA_READONLY | DMWBA_ENABLE);
- bzero((void *)(HP_SRAM_WIN0_BASE + SRAM_REG_FW_END),
- HP_SRAM_WIN0_SIZE - SRAM_REG_FW_END);
- dcache_writeback_region((void *)(HP_SRAM_WIN0_BASE + SRAM_REG_FW_END),
- HP_SRAM_WIN0_SIZE - SRAM_REG_FW_END);
-
- /* window1, for inbox/downlink mbox */
- io_reg_write(DMWLO(1), HP_SRAM_WIN1_SIZE | 0x7);
- io_reg_write(DMWBA(1), HP_SRAM_WIN1_BASE
- | DMWBA_ENABLE);
- bzero((void *)HP_SRAM_WIN1_BASE, HP_SRAM_WIN1_SIZE);
- dcache_writeback_region((void *)HP_SRAM_WIN1_BASE, HP_SRAM_WIN1_SIZE);
-
- /* window2, for debug */
- io_reg_write(DMWLO(2), HP_SRAM_WIN2_SIZE | 0x7);
- io_reg_write(DMWBA(2), HP_SRAM_WIN2_BASE
- | DMWBA_READONLY | DMWBA_ENABLE);
- bzero((void *)HP_SRAM_WIN2_BASE, HP_SRAM_WIN2_SIZE);
- dcache_writeback_region((void *)HP_SRAM_WIN2_BASE, HP_SRAM_WIN2_SIZE);
-
- /* window3, for trace */
- io_reg_write(DMWLO(3), HP_SRAM_WIN3_SIZE | 0x7);
- io_reg_write(DMWBA(3), HP_SRAM_WIN3_BASE
- | DMWBA_READONLY | DMWBA_ENABLE);
- bzero((void *)HP_SRAM_WIN3_BASE, HP_SRAM_WIN3_SIZE);
- dcache_writeback_region((void *)HP_SRAM_WIN3_BASE, HP_SRAM_WIN3_SIZE);
-}
-
-/* init HW */
-static void platform_init_hw(void)
-{
- io_reg_write(SHIM_GENO, SHIM_GENO_SHIMOSEL |
- SHIM_GENO_MDIVOSEL | SHIM_GENO_DIOPTOSEL);
-
- io_reg_write(SHIM_DSPIOPO,
- SHIM_DSPIOPO_DMICOSEL | SHIM_DSPIOPO_I2SOSEL);
-
- io_reg_write(SHIM_LPGPDMAC(0),
- SHIM_LPGPDMAC_CHOSEL | SHIM_LPGPDMAC_CTLOSEL);
- io_reg_write(SHIM_LPGPDMAC(1),
- SHIM_LPGPDMAC_CHOSEL | SHIM_LPGPDMAC_CTLOSEL);
-}
-
-int platform_init(struct sof *sof)
-{
- struct dai *ssp;
- struct dai *dmic0;
- int i, ret;
-
- trace_point(TRACE_BOOT_PLATFORM_ENTRY);
- platform_init_hw();
-
- platform_interrupt_init();
-
- trace_point(TRACE_BOOT_PLATFORM_MBOX);
- platform_memory_windows_init();
-
- trace_point(TRACE_BOOT_PLATFORM_SHIM);
-
- /* init work queues and clocks */
- trace_point(TRACE_BOOT_PLATFORM_TIMER);
- platform_timer_start(&platform_generic_queue.timer);
-
- trace_point(TRACE_BOOT_PLATFORM_CLOCK);
- init_platform_clocks();
-
- trace_point(TRACE_BOOT_SYS_WORK);
- init_system_workq(&platform_generic_queue);
-
- /* init the system agent */
- sa_init(sof);
-
- /* Set CPU to default frequency for booting */
- trace_point(TRACE_BOOT_SYS_CPU_FREQ);
- clock_set_freq(CLK_CPU, CLK_MAX_CPU_HZ);
-
- /* set SSP clock to 19.2M */
- trace_point(TRACE_BOOT_PLATFORM_SSP_FREQ);
- clock_set_freq(CLK_SSP, 19200000);
-
- /* initialise the host IPC mechanisms */
- trace_point(TRACE_BOOT_PLATFORM_IPC);
- ipc_init(sof);
-
- /* disable PM for boot */
- shim_write(SHIM_CLKCTL, shim_read(SHIM_CLKCTL) |
- SHIM_CLKCTL_LPGPDMAFDCGB(0) |
- SHIM_CLKCTL_LPGPDMAFDCGB(1) |
- SHIM_CLKCTL_I2SFDCGB(3) |
- SHIM_CLKCTL_I2SFDCGB(2) |
- SHIM_CLKCTL_I2SFDCGB(1) |
- SHIM_CLKCTL_I2SFDCGB(0) |
- SHIM_CLKCTL_DMICFDCGB |
- SHIM_CLKCTL_I2SEFDCGB(1) |
- SHIM_CLKCTL_I2SEFDCGB(0) |
- SHIM_CLKCTL_TCPAPLLS |
- SHIM_CLKCTL_RAPLLC |
- SHIM_CLKCTL_RXOSCC |
- SHIM_CLKCTL_RFROSCC |
- SHIM_CLKCTL_TCPLCG(0) | SHIM_CLKCTL_TCPLCG(1));
-
- shim_write(SHIM_LPSCTL, shim_read(SHIM_LPSCTL));
-
- /* init DMACs */
- trace_point(TRACE_BOOT_PLATFORM_DMA);
- ret = dmac_init();
- if (ret < 0)
- return -ENODEV;
-
-
- /* init SSP ports */
- trace_point(TRACE_BOOT_PLATFORM_SSP);
- for (i = 0; i < PLATFORM_NUM_SSP; i++) {
- ssp = dai_get(SOF_DAI_INTEL_SSP, i);
- if (ssp == NULL)
- return -ENODEV;
- dai_probe(ssp);
- }
-
- /* Init DMIC. Note that the two PDM controllers and four microphones
- * supported max. those are available in platform are handled by dmic0.
- */
- trace_point(TRACE_BOOT_PLATFORM_DMIC);
- dmic0 = dai_get(SOF_DAI_INTEL_DMIC, 0);
- if (!dmic0)
- return -ENODEV;
-
- dai_probe(dmic0);
-
- /* Initialize DMA for Trace*/
- dma_trace_init_complete(sof->dmat);
-
- return 0;
-}
diff --git a/src/platform/apollolake/power_down.S b/src/platform/apollolake/power_down.S
deleted file mode 100644
index b0c04b5..0000000
--- a/src/platform/apollolake/power_down.S
+++ /dev/null
@@ -1,155 +0,0 @@
-/*
- * Copyright (c) 2016, Intel Corporation
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- * * Redistributions of source code must retain the above copyright
- * notice, this list of conditions and the following disclaimer.
- * * Redistributions in binary form must reproduce the above copyright
- * notice, this list of conditions and the following disclaimer in the
- * documentation and/or other materials provided with the distribution.
- * * Neither the name of the Intel Corporation nor the
- * names of its contributors may be used to endorse or promote products
- * derived from this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
- * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
- * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
- * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
- * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
- * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
- * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
- * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
- * POSSIBILITY OF SUCH DAMAGE.
- *
- * Author: Lech Betlej <lech.betlej@linux.intel.com>
- */
-
-/**
- * \file platform/apollolake/power_down.S
- * \brief Power gating memory banks - implementation specific for Apollolake
- * \author Lech Betlej <lech.betlej@linux.intel.com>
- */
-#include <platform/asm_memory_management.h>
-
- .section .text, "ax"
- .align 64
-literals:
- .literal_position
- .global power_down
- .type power_down, @function
-/**
- * Perform power down.
- *
- * Depending on arguments, memories are switched off.
- * A2 - argument for LPSRAM
- * A3 - pointer to array containing power gating mask.
- *
- * Finally, core enters waiti.
- */
-//TODO: add IPC reply sending before core enters waiti
-
-#define b_enable_lpsram a2
-#define pu32_hpsram_mask a3
-#define temp_reg0 a6
-#define temp_reg1 a7
-#define temp_reg2 a8
-#define temp_reg3 a9
-#define pfl_reg a15
-
- .align 64
-power_down:
- entry sp, 32
- // effectively executes:
- // xthal_dcache_region_lock(&literals, 128);
- // xthal_dcache_region_lock(&power_down, 384);
- // xthal_dcache_region_lock(&pu32_hpsram_mask, 64);
- movi pfl_reg, literals
- dpfl pfl_reg, 0
- dpfl pfl_reg, 64
-
- movi pfl_reg, power_down
- ipfl pfl_reg, 0
- ipfl pfl_reg, 64
- ipfl pfl_reg, 128
- ipfl pfl_reg, 192
- addi pfl_reg, pfl_reg, 256
- ipfl pfl_reg, 0
- ipfl pfl_reg, 64
-
- mov pfl_reg, pu32_hpsram_mask
- dpfl pfl_reg, 0
-
- // if b_enable_lpsram = 0 (bool disable_lpsram) - do not disable lpsram.
- beqz b_enable_lpsram, _PD_DISABLE_HPSRAM
-
-
-_PD_DISABLE_LPSRAM:
- m_cavs_lpsram_power_off temp_reg0, temp_reg1, temp_reg2
-
- // DISABLE_HPSRAM is aligned so there can be zeros between it
- // and last instr.
- j _PD_DISABLE_HPSRAM
-
- // workaround for incidental gnu assembler bug - no alignment here
- // (see comment before IPFL) ...
- // .align 64
-_PD_DISABLE_HPSRAM:
- // if value in memory pointed by pu32_hpsram_mask = 0
- // (hpsram_pwrgating_mask) - do not disable hpsram.
- l32i temp_reg0, pu32_hpsram_mask, 0
- beqz temp_reg0, _PD_SLEEP
-
- // TODO: add full support switching off LDO incl. HW W/A
-
- m_cavs_hpsram_power_off temp_reg0, temp_reg1, temp_reg2
-
-
- // For BXT-P we need to deassert VNN request and select slow XTAL
- // as clock source
- // APL specific code _PD_SWITCH_TO_XTAL_CLOCK: and _PD_RELEASE_VNN
-_PD_SWITCH_TO_XTAL_CLOCK:
- // TODO: move to CLOCK hal macros
- movi temp_reg0, (SHIM_BASE + SHIM_CLKCTL)
- movi temp_reg1, ~(SHIM_CLKCTL_HDOCS | SHIM_CLKCTL_LDOCS)
- movi temp_reg2, (SHIM_CLKCTL_LDCS | SHIM_CLKCTL_HDCS)
- l32i temp_reg3, temp_reg0, 0
- // Reset LDOCS & HDOCS bits to select XTAL
- and temp_reg3, temp_reg3, temp_reg1
- // Set LDCS & HDCS so clock selection depends on LDOCS & HDOCS
- or temp_reg3, temp_reg3, temp_reg2
- s32i temp_reg3, temp_reg0, 0
-
-_PD_RELEASE_VNN:
- // TODO: move to VNN/SHIM hal macros
- movi temp_reg0, (SHIM_BASE + SHIM_SPSREQ)
- movi temp_reg1, ~SHIM_SPSREQ_RVNNP
- l32i temp_reg2, temp_reg0, 0
- and temp_reg2, temp_reg2, temp_reg1
- s32i temp_reg2, temp_reg0, 0
- l32i temp_reg2, temp_reg0, 0
- // We cannot wait for VNN to drop since it can be held by something else
- // and never drop
-
- //TODO: add sending IPC reply from L1$ locked code
-
-_PD_SLEEP:
- // effecfively executes:
- // xmp_spin()
- // waiti 5
- movi temp_reg0, 128
-loop:
- addi temp_reg0, temp_reg0, -1
- bnez temp_reg0, loop
-
- extw
- extw
- waiti 5
- j _PD_SLEEP
-
- .size power_down , . - power_down
-
-
diff --git a/src/platform/baytrail/Makefile.am b/src/platform/baytrail/Makefile.am
deleted file mode 100644
index 9c89029..0000000
--- a/src/platform/baytrail/Makefile.am
+++ /dev/null
@@ -1,20 +0,0 @@
-SUBDIRS = include
-
-EXTRA_DIST = baytrail.x.in
-
-noinst_LTLIBRARIES = libplatform.la
-
-libplatform_la_SOURCES = \
- platform.c \
- dai.c \
- dma.c \
- clk.c \
- timer.c \
- memory.c
-
-libplatform_la_CFLAGS = \
- $(AM_CFLAGS) \
- $(ARCH_CFLAGS) \
- $(ARCH_INCDIR) \
- $(PLATFORM_INCDIR) \
- $(SOF_INCDIR)
diff --git a/src/platform/baytrail/baytrail.x.in b/src/platform/baytrail/baytrail.x.in
deleted file mode 100755
index 0dd4505..0000000
--- a/src/platform/baytrail/baytrail.x.in
+++ /dev/null
@@ -1,508 +0,0 @@
-/*
- * Linker Script for Baytrail.
- *
- * This script is run through the GNU C preprocessor to align the memory
- * offsets with headers.
- *
- * Use spaces for formatting as cpp ignore tab sizes.
- */
-
-#include <platform/memory.h>
-#include <xtensa/config/core-isa.h>
-
-OUTPUT_ARCH(xtensa)
-
-MEMORY
-{
- vector_reset_text :
- org = XCHAL_RESET_VECTOR0_PADDR,
- len = SOF_MEM_RESET_TEXT_SIZE
- vector_reset_lit :
- org = XCHAL_RESET_VECTOR0_PADDR + SOF_MEM_RESET_TEXT_SIZE,
- len = SOF_MEM_RESET_LIT_SIZE
- vector_base_text :
- org = XCHAL_VECBASE_RESET_PADDR,
- len = SOF_MEM_VECBASE_LIT_SIZE
- vector_int2_lit :
- org = XCHAL_INTLEVEL2_VECTOR_PADDR - SOF_MEM_VECT_LIT_SIZE,
- len = SOF_MEM_VECT_LIT_SIZE
- vector_int2_text :
- org = XCHAL_INTLEVEL2_VECTOR_PADDR,
- len = SOF_MEM_VECT_TEXT_SIZE
- vector_int3_lit :
- org = XCHAL_INTLEVEL3_VECTOR_PADDR - SOF_MEM_VECT_LIT_SIZE,
- len = SOF_MEM_VECT_LIT_SIZE
- vector_int3_text :
- org = XCHAL_INTLEVEL3_VECTOR_PADDR,
- len = SOF_MEM_VECT_TEXT_SIZE
- vector_int4_lit :
- org = XCHAL_INTLEVEL4_VECTOR_PADDR - SOF_MEM_VECT_LIT_SIZE,
- len = SOF_MEM_VECT_LIT_SIZE
- vector_int4_text :
- org = XCHAL_INTLEVEL4_VECTOR_PADDR,
- len = SOF_MEM_VECT_TEXT_SIZE
- vector_int5_lit :
- org = XCHAL_INTLEVEL5_VECTOR_PADDR - SOF_MEM_VECT_LIT_SIZE,
- len = SOF_MEM_VECT_LIT_SIZE
- vector_int5_text :
- org = XCHAL_INTLEVEL5_VECTOR_PADDR,
- len = SOF_MEM_VECT_TEXT_SIZE
- vector_int6_lit :
- org = XCHAL_INTLEVEL6_VECTOR_PADDR - SOF_MEM_VECT_LIT_SIZE,
- len = SOF_MEM_VECT_LIT_SIZE
- vector_int6_text :
- org = XCHAL_INTLEVEL6_VECTOR_PADDR,
- len = SOF_MEM_VECT_TEXT_SIZE
- vector_int7_lit :
- org = XCHAL_INTLEVEL7_VECTOR_PADDR - SOF_MEM_VECT_LIT_SIZE,
- len = SOF_MEM_VECT_LIT_SIZE
- vector_int7_text :
- org = XCHAL_INTLEVEL7_VECTOR_PADDR,
- len = SOF_MEM_VECT_TEXT_SIZE
- vector_kernel_lit :
- org = XCHAL_KERNEL_VECTOR_PADDR - SOF_MEM_VECT_LIT_SIZE,
- len = SOF_MEM_VECT_LIT_SIZE
- vector_kernel_text :
- org = XCHAL_KERNEL_VECTOR_PADDR,
- len = SOF_MEM_VECT_TEXT_SIZE
- vector_user_lit :
- org = XCHAL_USER_VECTOR_PADDR - SOF_MEM_VECT_LIT_SIZE,
- len = SOF_MEM_VECT_LIT_SIZE
- vector_user_text :
- org = XCHAL_USER_VECTOR_PADDR,
- len = SOF_MEM_VECT_TEXT_SIZE
- vector_double_lit :
- org = XCHAL_DOUBLEEXC_VECTOR_PADDR - SOF_MEM_VECT_LIT_SIZE,
- len = SOF_MEM_VECT_LIT_SIZE
- vector_double_text :
- org = XCHAL_DOUBLEEXC_VECTOR_PADDR,
- len = SOF_MEM_VECT_TEXT_SIZE
- sof_text_start :
- org = XCHAL_DOUBLEEXC_VECTOR_PADDR + SOF_MEM_VECT_SIZE,
- len = (IRAM_BASE + IRAM_SIZE) - (XCHAL_DOUBLEEXC_VECTOR_PADDR + SOF_MEM_VECT_SIZE)
- sof_data_ro :
- org = DRAM0_BASE,
- len = SOF_MEM_RO_SIZE
- sof_data :
- org = DRAM0_BASE + SOF_MEM_RO_SIZE,
- len = HEAP_SYSTEM_BASE - (DRAM0_BASE + SOF_MEM_RO_SIZE)
- system_heap :
- org = HEAP_SYSTEM_BASE,
- len = HEAP_SYSTEM_SIZE
- runtime_heap :
- org = HEAP_RUNTIME_BASE,
- len = HEAP_RUNTIME_SIZE
- buffer_heap :
- org = HEAP_BUFFER_BASE,
- len = HEAP_BUFFER_SIZE
- sof_stack :
- org = SOF_STACK_END,
- len = SOF_STACK_BASE - SOF_STACK_END
-}
-
-PHDRS
-{
- vector_reset_text_phdr PT_LOAD;
- vector_reset_lit_phdr PT_LOAD;
- vector_base_text_phdr PT_LOAD;
- vector_base_lit_phdr PT_LOAD;
- vector_int2_text_phdr PT_LOAD;
- vector_int2_lit_phdr PT_LOAD;
- vector_int3_text_phdr PT_LOAD;
- vector_int3_lit_phdr PT_LOAD;
- vector_int4_text_phdr PT_LOAD;
- vector_int4_lit_phdr PT_LOAD;
- vector_int5_text_phdr PT_LOAD;
- vector_int5_lit_phdr PT_LOAD;
- vector_int6_text_phdr PT_LOAD;
- vector_int6_lit_phdr PT_LOAD;
- vector_int7_text_phdr PT_LOAD;
- vector_int7_lit_phdr PT_LOAD;
- vector_kernel_text_phdr PT_LOAD;
- vector_kernel_lit_phdr PT_LOAD;
- vector_user_text_phdr PT_LOAD;
- vector_user_lit_phdr PT_LOAD;
- vector_double_text_phdr PT_LOAD;
- vector_double_lit_phdr PT_LOAD;
- sof_text_start_phdr PT_LOAD;
- sof_data_ro_phdr PT_LOAD;
- sof_data_phdr PT_LOAD;
- sof_data_bss_phdr PT_LOAD;
- system_heap_phdr PT_LOAD;
- runtime_heap_phdr PT_LOAD;
- buffer_heap_phdr PT_LOAD;
- sof_stack_phdr PT_LOAD;
-}
-
-/* Default entry point: */
-ENTRY(_ResetVector)
-_rom_store_table = 0;
-
-/* ABI0 does not use Window base */
-PROVIDE(_memmap_vecbase_reset = XCHAL_VECBASE_RESET_PADDR);
-
-/* Various memory-map dependent cache attribute settings: */
-_memmap_cacheattr_wb_base = 0x44024000;
-_memmap_cacheattr_wt_base = 0x11021000;
-_memmap_cacheattr_bp_base = 0x22022000;
-_memmap_cacheattr_unused_mask = 0x00F00FFF;
-_memmap_cacheattr_wb_trapnull = 0x4422422F;
-_memmap_cacheattr_wba_trapnull = 0x4422422F;
-_memmap_cacheattr_wbna_trapnull = 0x25222222;
-_memmap_cacheattr_wt_trapnull = 0x1122122F;
-_memmap_cacheattr_bp_trapnull = 0x2222222F;
-_memmap_cacheattr_wb_strict = 0x44F24FFF;
-_memmap_cacheattr_wt_strict = 0x11F21FFF;
-_memmap_cacheattr_bp_strict = 0x22F22FFF;
-_memmap_cacheattr_wb_allvalid = 0x44224222;
-_memmap_cacheattr_wt_allvalid = 0x11221222;
-_memmap_cacheattr_bp_allvalid = 0x22222222;
-PROVIDE(_memmap_cacheattr_reset = _memmap_cacheattr_wbna_trapnull);
-
-SECTIONS
-{
- .ResetVector.text : ALIGN(4)
- {
- _ResetVector_text_start = ABSOLUTE(.);
- KEEP (*(.ResetVector.text))
- _ResetVector_text_end = ABSOLUTE(.);
- } >vector_reset_text :vector_reset_text_phdr
-
- .ResetVector.literal : ALIGN(4)
- {
- _ResetVector_literal_start = ABSOLUTE(.);
- *(.ResetVector.literal)
- _ResetVector_literal_end = ABSOLUTE(.);
- } >vector_reset_lit :vector_reset_lit_phdr
-
- .WindowVectors.text : ALIGN(4)
- {
- _WindowVectors_text_start = ABSOLUTE(.);
- KEEP (*(.WindowVectors.text))
- _WindowVectors_text_end = ABSOLUTE(.);
- } >vector_base_text :vector_base_text_phdr
-
- .Level2InterruptVector.literal : ALIGN(4)
- {
- _Level2InterruptVector_literal_start = ABSOLUTE(.);
- *(.Level2InterruptVector.literal)
- _Level2InterruptVector_literal_end = ABSOLUTE(.);
- } >vector_int2_lit :vector_int2_lit_phdr
-
- .Level2InterruptVector.text : ALIGN(4)
- {
- _Level2InterruptVector_text_start = ABSOLUTE(.);
- KEEP (*(.Level2InterruptVector.text))
- _Level2InterruptVector_text_end = ABSOLUTE(.);
- } >vector_int2_text :vector_int2_text_phdr
-
- .Level3InterruptVector.literal : ALIGN(4)
- {
- _Level3InterruptVector_literal_start = ABSOLUTE(.);
- *(.Level3InterruptVector.literal)
- _Level3InterruptVector_literal_end = ABSOLUTE(.);
- } >vector_int3_lit :vector_int3_lit_phdr
-
- .Level3InterruptVector.text : ALIGN(4)
- {
- _Level3InterruptVector_text_start = ABSOLUTE(.);
- KEEP (*(.Level3InterruptVector.text))
- _Level3InterruptVector_text_end = ABSOLUTE(.);
- } >vector_int3_text :vector_int3_text_phdr
-
- .Level4InterruptVector.literal : ALIGN(4)
- {
- _Level4InterruptVector_literal_start = ABSOLUTE(.);
- *(.Level4InterruptVector.literal)
- _Level4InterruptVector_literal_end = ABSOLUTE(.);
- } >vector_int4_lit :vector_int4_lit_phdr
-
- .Level4InterruptVector.text : ALIGN(4)
- {
- _Level4InterruptVector_text_start = ABSOLUTE(.);
- KEEP (*(.Level4InterruptVector.text))
- _Level4InterruptVector_text_end = ABSOLUTE(.);
- } >vector_int4_text :vector_int4_text_phdr
-
- .Level5InterruptVector.literal : ALIGN(4)
- {
- _Level5InterruptVector_literal_start = ABSOLUTE(.);
- *(.Level5InterruptVector.literal)
- _Level5InterruptVector_literal_end = ABSOLUTE(.);
- } >vector_int5_lit :vector_int5_lit_phdr
-
- .Level5InterruptVector.text : ALIGN(4)
- {
- _Level5InterruptVector_text_start = ABSOLUTE(.);
- KEEP (*(.Level5InterruptVector.text))
- _Level5InterruptVector_text_end = ABSOLUTE(.);
- } >vector_int5_text :vector_int5_text_phdr
-
- .DebugExceptionVector.literal : ALIGN(4)
- {
- _DebugExceptionVector_literal_start = ABSOLUTE(.);
- *(.DebugExceptionVector.literal)
- _DebugExceptionVector_literal_end = ABSOLUTE(.);
- } >vector_int6_lit :vector_int6_lit_phdr
-
- .DebugExceptionVector.text : ALIGN(4)
- {
- _DebugExceptionVector_text_start = ABSOLUTE(.);
- KEEP (*(.DebugExceptionVector.text))
- _DebugExceptionVector_text_end = ABSOLUTE(.);
- } >vector_int6_text :vector_int6_text_phdr
-
- .NMIExceptionVector.literal : ALIGN(4)
- {
- _NMIExceptionVector_literal_start = ABSOLUTE(.);
- *(.NMIExceptionVector.literal)
- _NMIExceptionVector_literal_end = ABSOLUTE(.);
- } >vector_int7_lit :vector_int7_lit_phdr
-
- .NMIExceptionVector.text : ALIGN(4)
- {
- _NMIExceptionVector_text_start = ABSOLUTE(.);
- KEEP (*(.NMIExceptionVector.text))
- _NMIExceptionVector_text_end = ABSOLUTE(.);
- } >vector_int7_text :vector_int7_text_phdr
-
- .KernelExceptionVector.literal : ALIGN(4)
- {
- _KernelExceptionVector_literal_start = ABSOLUTE(.);
- *(.KernelExceptionVector.literal)
- _KernelExceptionVector_literal_end = ABSOLUTE(.);
- } >vector_kernel_lit :vector_kernel_lit_phdr
-
- .KernelExceptionVector.text : ALIGN(4)
- {
- _KernelExceptionVector_text_start = ABSOLUTE(.);
- KEEP (*(.KernelExceptionVector.text))
- _KernelExceptionVector_text_end = ABSOLUTE(.);
- } >vector_kernel_text :vector_kernel_text_phdr
-
- .UserExceptionVector.literal : ALIGN(4)
- {
- _UserExceptionVector_literal_start = ABSOLUTE(.);
- *(.UserExceptionVector.literal)
- _UserExceptionVector_literal_end = ABSOLUTE(.);
- } >vector_user_lit :vector_user_lit_phdr
-
- .UserExceptionVector.text : ALIGN(4)
- {
- _UserExceptionVector_text_start = ABSOLUTE(.);
- KEEP (*(.UserExceptionVector.text))
- _UserExceptionVector_text_end = ABSOLUTE(.);
- } >vector_user_text :vector_user_text_phdr
-
- .DoubleExceptionVector.literal : ALIGN(4)
- {
- _DoubleExceptionVector_literal_start = ABSOLUTE(.);
- *(.DoubleExceptionVector.literal)
- _DoubleExceptionVector_literal_end = ABSOLUTE(.);
- } >vector_double_lit :vector_double_lit_phdr
-
- .DoubleExceptionVector.text : ALIGN(4)
- {
- _DoubleExceptionVector_text_start = ABSOLUTE(.);
- KEEP (*(.DoubleExceptionVector.text))
- _DoubleExceptionVector_text_end = ABSOLUTE(.);
- } >vector_double_text :vector_double_text_phdr
-
- .text : ALIGN(4)
- {
- _stext = .;
- _text_start = ABSOLUTE(.);
- *(.entry.text)
- *(.init.literal)
- KEEP(*(.init))
- *(.literal .text .literal.* .text.* .stub .gnu.warning .gnu.linkonce.literal.* .gnu.linkonce.t.*.literal .gnu.linkonce.t.*)
- *(.fini.literal)
- KEEP(*(.fini))
- *(.gnu.version)
- _text_end = ABSOLUTE(.);
- _etext = .;
- } >sof_text_start :sof_text_start_phdr
-
- .reset.rodata : ALIGN(4)
- {
- _reset_rodata_start = ABSOLUTE(.);
- *(.reset.rodata)
- _reset_rodata_end = ABSOLUTE(.);
- } >sof_data_ro :sof_data_ro_phdr
-
- .rodata : ALIGN(4)
- {
- _rodata_start = ABSOLUTE(.);
- *(.rodata)
- *(.rodata.*)
- *(.gnu.linkonce.r.*)
- *(.rodata1)
- __XT_EXCEPTION_TABLE__ = ABSOLUTE(.);
- KEEP (*(.xt_except_table))
- KEEP (*(.gcc_except_table))
- *(.gnu.linkonce.e.*)
- *(.gnu.version_r)
- KEEP (*(.eh_frame))
- /* C++ constructor and destructor tables, properly ordered: */
- KEEP (*crtbegin.o(.ctors))
- KEEP (*(EXCLUDE_FILE (*crtend.o) .ctors))
- KEEP (*(SORT(.ctors.*)))
- KEEP (*(.ctors))
- KEEP (*crtbegin.o(.dtors))
- KEEP (*(EXCLUDE_FILE (*crtend.o) .dtors))
- KEEP (*(SORT(.dtors.*)))
- KEEP (*(.dtors))
- /* C++ exception handlers table: */
- __XT_EXCEPTION_DESCS__ = ABSOLUTE(.);
- *(.xt_except_desc)
- *(.gnu.linkonce.h.*)
- __XT_EXCEPTION_DESCS_END__ = ABSOLUTE(.);
- *(.xt_except_desc_end)
- *(.dynamic)
- *(.gnu.version_d)
- . = ALIGN(4); /* this table MUST be 4-byte aligned */
- _bss_table_start = ABSOLUTE(.);
- LONG(_bss_start)
- LONG(_bss_end)
- _bss_table_end = ABSOLUTE(.);
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- } >sof_data :sof_data_phdr
-
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- {
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- *(.data.*)
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- *(.gnu.linkonce.s2.*)
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- _data_end = ABSOLUTE(.);
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-
- .lit4 : ALIGN(4)
- {
- _lit4_start = ABSOLUTE(.);
- *(*.lit4)
- *(.lit4.*)
- *(.gnu.linkonce.lit4.*)
- _lit4_end = ABSOLUTE(.);
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-
- .bss (NOLOAD) : ALIGN(8)
- {
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- _bss_start = ABSOLUTE(.);
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- *(.sbss)
- *(.sbss.*)
- *(.gnu.linkonce.sb.*)
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-
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- _end = SOF_STACK_END;
- PROVIDE(end = SOF_STACK_END);
- _stack_sentry = SOF_STACK_END;
- __stack = SOF_STACK_BASE;
-
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-
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- {
- KEEP (*(.xt.insn))
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-
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- _runtime_heap_start = ABSOLUTE(.);
- . = . + HEAP_RUNTIME_SIZE;
- _runtime_heap_end = ABSOLUTE(.);
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-
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- . = ALIGN (32);
- _system_heap_start = ABSOLUTE(.);
- . = . + HEAP_BUFFER_SIZE;
- _system_heap_end = ABSOLUTE(.);
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-
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-
diff --git a/src/platform/baytrail/clk.c b/src/platform/baytrail/clk.c
deleted file mode 100644
index 00baec0..0000000
--- a/src/platform/baytrail/clk.c
+++ /dev/null
@@ -1,281 +0,0 @@
-/*
- * Copyright (c) 2016, Intel Corporation
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- * * Redistributions of source code must retain the above copyright
- * notice, this list of conditions and the following disclaimer.
- * * Redistributions in binary form must reproduce the above copyright
- * notice, this list of conditions and the following disclaimer in the
- * documentation and/or other materials provided with the distribution.
- * * Neither the name of the Intel Corporation nor the
- * names of its contributors may be used to endorse or promote products
- * derived from this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
- * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
- * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
- * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
- * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
- * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
- * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
- * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
- * POSSIBILITY OF SUCH DAMAGE.
- *
- * Author: Liam Girdwood <liam.r.girdwood@linux.intel.com>
- * Keyon Jie <yang.jie@linux.intel.com>
- */
-
-#include <sof/clock.h>
-#include <sof/io.h>
-#include <sof/sof.h>
-#include <sof/list.h>
-#include <sof/alloc.h>
-#include <sof/notifier.h>
-#include <sof/lock.h>
-#include <platform/clk.h>
-#include <platform/shim.h>
-#include <platform/timer.h>
-#include <platform/pmc.h>
-#include <config.h>
-#include <stdint.h>
-#include <limits.h>
-
-#define NUM_CLOCKS 2
-
-struct clk_data {
- uint32_t freq;
- uint32_t ticks_per_usec;
- spinlock_t lock;
-};
-
-struct clk_pdata {
- struct clk_data clk[NUM_CLOCKS];
-};
-
-struct freq_table {
- uint32_t freq;
- uint32_t ticks_per_usec;
- uint32_t enc;
-};
-
-static struct clk_pdata *clk_pdata;
-
-#if defined CONFIG_BAYTRAIL
-/* increasing frequency order */
-static const struct freq_table cpu_freq[] = {
- {25000000, 25, 0x0},
- {25000000, 25, 0x1},
- {50000000, 50, 0x2},
- {50000000, 50, 0x3}, /* default */
- {100000000, 100, 0x4},
- {200000000, 200, 0x5},
- {267000000, 267, 0x6},
- {343000000, 343, 0x7},
-};
-
-static const struct freq_table ssp_freq[] = {
- {19200000, 19, PMC_SET_SSP_19M2},
- {25000000, 25, PMC_SET_SSP_25M}, /* default */
-};
-
-#define CPU_DEFAULT_IDX 3
-#define SSP_DEFAULT_IDX 1
-
-#elif defined CONFIG_CHERRYTRAIL
-
-/* increasing frequency order */
-static const struct freq_table cpu_freq[] = {
- {19200000, 19, 0x0},
- {19200000, 19, 0x1},
- {38400000, 38, 0x2},
- {50000000, 50, 0x3}, /* default */
- {100000000, 100, 0x4},
- {200000000, 200, 0x5},
- {267000000, 267, 0x6},
- {343000000, 343, 0x7},
-};
-
-static const struct freq_table ssp_freq[] = {
- {19200000, 19, PMC_SET_SSP_19M2}, /* default */
- {25000000, 25, PMC_SET_SSP_25M},
-};
-
-#define CPU_DEFAULT_IDX 3
-#define SSP_DEFAULT_IDX 0
-
-#else
-#error No target defined
-#endif
-
-
-
-static inline uint32_t get_freq(const struct freq_table *table, int size,
- unsigned int hz)
-{
- uint32_t i;
-
- /* find lowest available frequency that is >= requested Hz */
- for (i = 0; i < size; i++) {
- if (hz <= table[i].freq)
- return i;
- }
-
- /* not found, so return max frequency */
- return size - 1;
-}
-
-void clock_enable(int clock)
-{
- switch (clock) {
- case CLK_CPU:
- break;
- case CLK_SSP:
- default:
- break;
- }
-}
-
-void clock_disable(int clock)
-{
- switch (clock) {
- case CLK_CPU:
- break;
- case CLK_SSP:
- default:
- break;
- }
-}
-
-uint32_t clock_set_freq(int clock, uint32_t hz)
-{
- struct clock_notify_data notify_data;
- uint32_t idx;
- uint32_t flags;
- int err = 0;
-
- notify_data.old_freq = clk_pdata->clk[clock].freq;
- notify_data.old_ticks_per_usec = clk_pdata->clk[clock].ticks_per_usec;
-
- /* atomic context for chaining clocks */
- spin_lock_irq(&clk_pdata->clk[clock].lock, flags);
-
- switch (clock) {
- case CLK_CPU:
-
- /* get nearest frequency that is >= requested Hz */
- idx = get_freq(cpu_freq, ARRAY_SIZE(cpu_freq), hz);
- notify_data.freq = cpu_freq[idx].freq;
-
- /* tell anyone interested we are about to change CPU freq */
- notifier_event(NOTIFIER_ID_CPU_FREQ, CLOCK_NOTIFY_PRE,
- ¬ify_data);
-
- /* set CPU frequency request for CCU */
- io_reg_update_bits(SHIM_BASE + SHIM_FR_LAT_REQ,
- SHIM_FR_LAT_CLK_MASK, cpu_freq[idx].enc);
-
- /* send freq request to SC */
- err = ipc_pmc_send_msg(PMC_SET_LPECLK);
- if (err == 0) {
-
- /* update clock frequency */
- clk_pdata->clk[clock].freq = cpu_freq[idx].freq;
- clk_pdata->clk[clock].ticks_per_usec =
- cpu_freq[idx].ticks_per_usec;
- }
-
- /* tell anyone interested we have now changed CPU freq */
- notifier_event(NOTIFIER_ID_CPU_FREQ, CLOCK_NOTIFY_POST,
- ¬ify_data);
- break;
- case CLK_SSP:
- /* get nearest frequency that is >= requested Hz */
- idx = get_freq(ssp_freq, ARRAY_SIZE(ssp_freq), hz);
- notify_data.freq = ssp_freq[idx].freq;
-
- /* tell anyone interested we are about to change CPU freq */
- notifier_event(NOTIFIER_ID_SSP_FREQ, CLOCK_NOTIFY_PRE,
- ¬ify_data);
-
- /* send SSP freq request to SC */
- err = ipc_pmc_send_msg(ssp_freq[idx].enc);
- if (err == 0) {
-
- /* update clock frequency */
- clk_pdata->clk[clock].freq = ssp_freq[idx].freq;
- clk_pdata->clk[clock].ticks_per_usec =
- ssp_freq[idx].ticks_per_usec;
- }
-
- /* tell anyone interested we have now changed CPU freq */
- notifier_event(NOTIFIER_ID_SSP_FREQ, CLOCK_NOTIFY_POST,
- ¬ify_data);
- break;
-
- default:
- break;
- }
-
- spin_unlock_irq(&clk_pdata->clk[clock].lock, flags);
- return clk_pdata->clk[clock].freq;
-}
-
-uint32_t clock_get_freq(int clock)
-{
- return clk_pdata->clk[clock].freq;
-}
-
-uint64_t clock_us_to_ticks(int clock, uint64_t us)
-{
- return clk_pdata->clk[clock].ticks_per_usec * us;
-}
-
-uint64_t clock_ms_to_ticks(int clock, uint64_t ms)
-{
- return clk_pdata->clk[clock].ticks_per_usec * ms * 1000;
-}
-
-uint64_t clock_time_elapsed(int clock, uint64_t previous, uint64_t *current)
-{
- uint64_t _current;
-
- // TODO: change timer APIs to clk APIs ??
- switch (clock) {
- case CLK_CPU:
- _current = arch_timer_get_system(NULL);
- break;
- case CLK_SSP:
- _current = platform_timer_get(platform_timer);
- break;
- default:
- return 0;
- }
-
- *current = _current;
- if (_current >= previous)
- return (_current - previous) /
- clk_pdata->clk[clock].ticks_per_usec;
- else
- return (_current + (ULONG_LONG_MAX - previous)) /
- clk_pdata->clk[clock].ticks_per_usec;
-}
-
-void init_platform_clocks(void)
-{
- clk_pdata = rmalloc(RZONE_SYS, SOF_MEM_CAPS_RAM, sizeof(*clk_pdata));
-
- spinlock_init(&clk_pdata->clk[0].lock);
- spinlock_init(&clk_pdata->clk[1].lock);
-
- /* set defaults */
- clk_pdata->clk[CLK_CPU].freq = cpu_freq[CPU_DEFAULT_IDX].freq;
- clk_pdata->clk[CLK_CPU].ticks_per_usec =
- cpu_freq[CPU_DEFAULT_IDX].ticks_per_usec;
- clk_pdata->clk[CLK_SSP].freq = ssp_freq[SSP_DEFAULT_IDX].freq;
- clk_pdata->clk[CLK_SSP].ticks_per_usec =
- ssp_freq[SSP_DEFAULT_IDX].ticks_per_usec;
-}
diff --git a/src/platform/baytrail/dai.c b/src/platform/baytrail/dai.c
deleted file mode 100644
index 9877e9d..0000000
--- a/src/platform/baytrail/dai.c
+++ /dev/null
@@ -1,161 +0,0 @@
-/*
- * Copyright (c) 2016, Intel Corporation
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- * * Redistributions of source code must retain the above copyright
- * notice, this list of conditions and the following disclaimer.
- * * Redistributions in binary form must reproduce the above copyright
- * notice, this list of conditions and the following disclaimer in the
- * documentation and/or other materials provided with the distribution.
- * * Neither the name of the Intel Corporation nor the
- * names of its contributors may be used to endorse or promote products
- * derived from this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
- * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
- * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
- * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
- * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
- * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
- * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
- * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
- * POSSIBILITY OF SUCH DAMAGE.
- *
- * Author: Liam Girdwood <liam.r.girdwood@linux.intel.com>
- */
-
-#include <sof/sof.h>
-#include <sof/dai.h>
-#include <sof/ssp.h>
-#include <sof/stream.h>
-#include <sof/audio/component.h>
-#include <platform/memory.h>
-#include <platform/interrupt.h>
-#include <platform/dma.h>
-#include <uapi/ipc.h>
-#include <stdint.h>
-#include <string.h>
-#include <config.h>
-
-static struct dai ssp[] = {
-{
- .type = SOF_DAI_INTEL_SSP,
- .index = 0,
- .plat_data = {
- .base = SSP0_BASE,
- .irq = IRQ_NUM_EXT_SSP0,
- .fifo[SOF_IPC_STREAM_PLAYBACK] = {
- .offset = SSP0_BASE + SSDR,
- .handshake = DMA_HANDSHAKE_SSP0_TX,
- },
- .fifo[SOF_IPC_STREAM_CAPTURE] = {
- .offset = SSP0_BASE + SSDR,
- .handshake = DMA_HANDSHAKE_SSP0_RX,
- }
- },
- .ops = &ssp_ops,
-},
-{
- .type = SOF_DAI_INTEL_SSP,
- .index = 1,
- .plat_data = {
- .base = SSP1_BASE,
- .irq = IRQ_NUM_EXT_SSP1,
- .fifo[SOF_IPC_STREAM_PLAYBACK] = {
- .offset = SSP1_BASE + SSDR,
- .handshake = DMA_HANDSHAKE_SSP1_TX,
- },
- .fifo[SOF_IPC_STREAM_CAPTURE] = {
- .offset = SSP1_BASE + SSDR,
- .handshake = DMA_HANDSHAKE_SSP1_RX,
- }
- },
- .ops = &ssp_ops,
-},
-{
- .type = SOF_DAI_INTEL_SSP,
- .index = 2,
- .plat_data = {
- .base = SSP2_BASE,
- .irq = IRQ_NUM_EXT_SSP2,
- .fifo[SOF_IPC_STREAM_PLAYBACK] = {
- .offset = SSP2_BASE + SSDR,
- .handshake = DMA_HANDSHAKE_SSP2_TX,
- },
- .fifo[SOF_IPC_STREAM_CAPTURE] = {
- .offset = SSP2_BASE + SSDR,
- .handshake = DMA_HANDSHAKE_SSP2_RX,
- }
- },
- .ops = &ssp_ops,
-},
-#if defined CONFIG_CHERRYTRAIL
-{
- .type = SOF_DAI_INTEL_SSP,
- .index = 3,
- .plat_data = {
- .base = SSP3_BASE,
- .irq = IRQ_NUM_EXT_SSP0,
- .fifo[SOF_IPC_STREAM_PLAYBACK] = {
- .offset = SSP3_BASE + SSDR,
- .handshake = DMA_HANDSHAKE_SSP3_TX,
- },
- .fifo[SOF_IPC_STREAM_CAPTURE] = {
- .offset = SSP0_BASE + SSDR,
- .handshake = DMA_HANDSHAKE_SSP3_RX,
- }
- },
- .ops = &ssp_ops,
-},
-{
- .type = SOF_DAI_INTEL_SSP,
- .index = 4,
- .plat_data = {
- .base = SSP4_BASE,
- .irq = IRQ_NUM_EXT_SSP1,
- .fifo[SOF_IPC_STREAM_PLAYBACK] = {
- .offset = SSP4_BASE + SSDR,
- .handshake = DMA_HANDSHAKE_SSP4_TX,
- },
- .fifo[SOF_IPC_STREAM_CAPTURE] = {
- .offset = SSP4_BASE + SSDR,
- .handshake = DMA_HANDSHAKE_SSP4_RX,
- }
- },
- .ops = &ssp_ops,
-},
-{
- .type = SOF_DAI_INTEL_SSP,
- .index = 5,
- .plat_data = {
- .base = SSP5_BASE,
- .irq = IRQ_NUM_EXT_SSP2,
- .fifo[SOF_IPC_STREAM_PLAYBACK] = {
- .offset = SSP5_BASE + SSDR,
- .handshake = DMA_HANDSHAKE_SSP5_TX,
- },
- .fifo[SOF_IPC_STREAM_CAPTURE] = {
- .offset = SSP5_BASE + SSDR,
- .handshake = DMA_HANDSHAKE_SSP5_RX,
- }
- },
- .ops = &ssp_ops,
-},
-#endif
-};
-
-struct dai *dai_get(enum sof_ipc_dai_type type, uint32_t index)
-{
- int i;
-
- for (i = 0; i < ARRAY_SIZE(ssp); i++) {
- if (ssp[i].type == type && ssp[i].index == index)
- return &ssp[i];
- }
-
- return NULL;
-}
diff --git a/src/platform/baytrail/dma.c b/src/platform/baytrail/dma.c
deleted file mode 100644
index 1069ee5..0000000
--- a/src/platform/baytrail/dma.c
+++ /dev/null
@@ -1,210 +0,0 @@
-/*
- * Copyright (c) 2016, Intel Corporation
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- * * Redistributions of source code must retain the above copyright
- * notice, this list of conditions and the following disclaimer.
- * * Redistributions in binary form must reproduce the above copyright
- * notice, this list of conditions and the following disclaimer in the
- * documentation and/or other materials provided with the distribution.
- * * Neither the name of the Intel Corporation nor the
- * names of its contributors may be used to endorse or promote products
- * derived from this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
- * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
- * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
- * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
- * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
- * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
- * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
- * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
- * POSSIBILITY OF SUCH DAMAGE.
- *
- * Author: Liam Girdwood <liam.r.girdwood@linux.intel.com>
- */
-
-#include <sof/dma.h>
-#include <sof/dw-dma.h>
-#include <platform/memory.h>
-#include <platform/interrupt.h>
-#include <platform/dma.h>
-#include <stdint.h>
-#include <string.h>
-
-static struct dw_drv_plat_data dmac0 = {
- .chan[0] = {
- .class = 6,
- .weight = 0,
- },
- .chan[1] = {
- .class = 6,
- .weight = 0,
- },
- .chan[2] = {
- .class = 6,
- .weight = 0,
- },
- .chan[3] = {
- .class = 6,
- .weight = 0,
- },
- .chan[4] = {
- .class = 6,
- .weight = 0,
- },
- .chan[5] = {
- .class = 6,
- .weight = 0,
- },
- .chan[6] = {
- .class = 6,
- .weight = 0,
- },
- .chan[7] = {
- .class = 6,
- .weight = 0,
- },
-};
-
-static struct dw_drv_plat_data dmac1 = {
- .chan[0] = {
- .class = 7,
- .weight = 0,
- },
- .chan[1] = {
- .class = 7,
- .weight = 0,
- },
- .chan[2] = {
- .class = 7,
- .weight = 0,
- },
- .chan[3] = {
- .class = 7,
- .weight = 0,
- },
- .chan[4] = {
- .class = 7,
- .weight = 0,
- },
- .chan[5] = {
- .class = 7,
- .weight = 0,
- },
- .chan[6] = {
- .class = 7,
- .weight = 0,
- },
- .chan[7] = {
- .class = 7,
- .weight = 0,
- },
-};
-
-#if defined CONFIG_CHERRYTRAIL
-static struct dw_drv_plat_data dmac2 = {
- .chan[0] = {
- .class = 7,
- .weight = 0,
- },
- .chan[1] = {
- .class = 7,
- .weight = 0,
- },
- .chan[2] = {
- .class = 7,
- .weight = 0,
- },
- .chan[3] = {
- .class = 7,
- .weight = 0,
- },
- .chan[4] = {
- .class = 7,
- .weight = 0,
- },
- .chan[5] = {
- .class = 7,
- .weight = 0,
- },
- .chan[6] = {
- .class = 7,
- .weight = 0,
- },
- .chan[7] = {
- .class = 7,
- .weight = 0,
- },
-};
-#endif
-
-struct dma dma[PLATFORM_NUM_DMACS] = {
-{
- .plat_data = {
- .id = DMA_ID_DMAC0,
- .dir = DMA_DIR_MEM_TO_MEM | DMA_DIR_MEM_TO_DEV |
- DMA_DIR_DEV_TO_MEM | DMA_DIR_DEV_TO_DEV |
- DMA_DIR_HMEM_TO_LMEM | DMA_DIR_LMEM_TO_HMEM,
- .caps = DMA_CAP_GP_HP,
- .devs = DMA_DEV_SSP | DMA_DEV_DMIC | DMA_DEV_HOST,
- .base = DMA0_BASE,
- .irq = IRQ_NUM_EXT_DMAC0,
- .drv_plat_data = &dmac0,
- },
- .ops = &dw_dma_ops,
-},
-{
- .plat_data = {
- .id = DMA_ID_DMAC1,
- .dir = DMA_DIR_MEM_TO_MEM | DMA_DIR_MEM_TO_DEV |
- DMA_DIR_DEV_TO_MEM | DMA_DIR_DEV_TO_DEV |
- DMA_DIR_HMEM_TO_LMEM | DMA_DIR_LMEM_TO_HMEM,
- .caps = DMA_CAP_GP_HP,
- .devs = DMA_DEV_SSP | DMA_DEV_DMIC | DMA_DEV_HOST,
- .base = DMA1_BASE,
- .irq = IRQ_NUM_EXT_DMAC1,
- .drv_plat_data = &dmac1,
- },
- .ops = &dw_dma_ops,
-},
-#if defined CONFIG_CHERRYTRAIL
-{
- .plat_data = {
- .id = DMA_ID_DMAC2,
- .dir = DMA_DIR_MEM_TO_MEM | DMA_DIR_MEM_TO_DEV |
- DMA_DIR_DEV_TO_MEM | DMA_DIR_DEV_TO_DEV |
- DMA_DIR_HMEM_TO_LMEM | DMA_DIR_LMEM_TO_HMEM,
- .caps = DMA_CAP_GP_HP,
- .devs = DMA_DEV_SSP | DMA_DEV_DMIC | DMA_DEV_HOST,
- .base = DMA2_BASE,
- .irq = IRQ_NUM_EXT_DMAC2,
- .drv_plat_data = &dmac2,
- },
- .ops = &dw_dma_ops,
-},
-#endif
-};
-
-/* Initialize all platform DMAC's */
-int dmac_init(void)
-{
- int i, ret;
-
- for (i = 0; i < ARRAY_SIZE(dma); i++) {
- ret = dma_probe(&dma[i]);
- if (ret < 0) {
-
- /* trace failed DMAC ID */
- trace_error(TRACE_CLASS_DMA, "edi");
- trace_error_value(dma[i].plat_data.id);
- return ret;
- }
- }
-
- return 0;
-}
diff --git a/src/platform/baytrail/include/Makefile.am b/src/platform/baytrail/include/Makefile.am
deleted file mode 100644
index c5113a4..0000000
--- a/src/platform/baytrail/include/Makefile.am
+++ /dev/null
@@ -1 +0,0 @@
-SUBDIRS = arch platform
diff --git a/src/platform/baytrail/include/arch/Makefile.am b/src/platform/baytrail/include/arch/Makefile.am
deleted file mode 100644
index 63616bf..0000000
--- a/src/platform/baytrail/include/arch/Makefile.am
+++ /dev/null
@@ -1 +0,0 @@
-SUBDIRS = xtensa
diff --git a/src/platform/baytrail/include/arch/xtensa/Makefile.am b/src/platform/baytrail/include/arch/xtensa/Makefile.am
deleted file mode 100644
index a85a5bb..0000000
--- a/src/platform/baytrail/include/arch/xtensa/Makefile.am
+++ /dev/null
@@ -1 +0,0 @@
-SUBDIRS = config
diff --git a/src/platform/baytrail/include/arch/xtensa/config/Makefile.am b/src/platform/baytrail/include/arch/xtensa/config/Makefile.am
deleted file mode 100644
index c68949b..0000000
--- a/src/platform/baytrail/include/arch/xtensa/config/Makefile.am
+++ /dev/null
@@ -1,10 +0,0 @@
-noinst_HEADERS = \
- core-isa.h \
- core-isa-byt.h \
- core-isa-cht.h \
- core-matmap.h \
- defs.h \
- specreg.h \
- system.h \
- tie.h \
- tie-asm.h
diff --git a/src/platform/baytrail/include/arch/xtensa/config/core-isa-byt.h b/src/platform/baytrail/include/arch/xtensa/config/core-isa-byt.h
deleted file mode 100644
index 0657bc3..0000000
--- a/src/platform/baytrail/include/arch/xtensa/config/core-isa-byt.h
+++ /dev/null
@@ -1,598 +0,0 @@
-/*
- * xtensa/config/core-isa.h -- HAL definitions that are dependent on Xtensa
- * processor CORE configuration
- *
- * See <xtensa/config/core.h>, which includes this file, for more details.
- */
-
-/* Xtensa processor core configuration information.
-
- Customer ID=4313; Build=0x5483b; Copyright (c) 1999-2015 Tensilica Inc.
-
- Permission is hereby granted, free of charge, to any person obtaining
- a copy of this software and associated documentation files (the
- "Software"), to deal in the Software without restriction, including
- without limitation the rights to use, copy, modify, merge, publish,
- distribute, sublicense, and/or sell copies of the Software, and to
- permit persons to whom the Software is furnished to do so, subject to
- the following conditions:
-
- The above copyright notice and this permission notice shall be included
- in all copies or substantial portions of the Software.
-
- THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
- EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
- MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
- IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY
- CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
- TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
- SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. */
-
-#ifndef _XTENSA_CORE_CONFIGURATION_H
-#define _XTENSA_CORE_CONFIGURATION_H
-
-
-/****************************************************************************
- Parameters Useful for Any Code, USER or PRIVILEGED
- ****************************************************************************/
-
-/*
- * Note: Macros of the form XCHAL_HAVE_*** have a value of 1 if the option is
- * configured, and a value of 0 otherwise. These macros are always defined.
- */
-
-
-/*----------------------------------------------------------------------
- ISA
- ----------------------------------------------------------------------*/
-
-#define XCHAL_HAVE_BE 0 /* big-endian byte ordering */
-#define XCHAL_HAVE_WINDOWED 1 /* windowed registers option */
-#define XCHAL_NUM_AREGS 32 /* num of physical addr regs */
-#define XCHAL_NUM_AREGS_LOG2 5 /* log2(XCHAL_NUM_AREGS) */
-#define XCHAL_MAX_INSTRUCTION_SIZE 8 /* max instr bytes (3..8) */
-#define XCHAL_HAVE_DEBUG 1 /* debug option */
-#define XCHAL_HAVE_DENSITY 1 /* 16-bit instructions */
-#define XCHAL_HAVE_LOOPS 1 /* zero-overhead loops */
-#define XCHAL_LOOP_BUFFER_SIZE 0 /* zero-ov. loop instr buffer size */
-#define XCHAL_HAVE_NSA 1 /* NSA/NSAU instructions */
-#define XCHAL_HAVE_MINMAX 1 /* MIN/MAX instructions */
-#define XCHAL_HAVE_SEXT 1 /* SEXT instruction */
-#define XCHAL_HAVE_DEPBITS 0 /* DEPBITS instruction */
-#define XCHAL_HAVE_CLAMPS 1 /* CLAMPS instruction */
-#define XCHAL_HAVE_MUL16 1 /* MUL16S/MUL16U instructions */
-#define XCHAL_HAVE_MUL32 1 /* MULL instruction */
-#define XCHAL_HAVE_MUL32_HIGH 1 /* MULUH/MULSH instructions */
-#define XCHAL_HAVE_DIV32 0 /* QUOS/QUOU/REMS/REMU instructions */
-#define XCHAL_HAVE_L32R 1 /* L32R instruction */
-#define XCHAL_HAVE_ABSOLUTE_LITERALS 0 /* non-PC-rel (extended) L32R */
-#define XCHAL_HAVE_CONST16 0 /* CONST16 instruction */
-#define XCHAL_HAVE_ADDX 1 /* ADDX#/SUBX# instructions */
-#define XCHAL_HAVE_WIDE_BRANCHES 0 /* B*.W18 or B*.W15 instr's */
-#define XCHAL_HAVE_PREDICTED_BRANCHES 0 /* B[EQ/EQZ/NE/NEZ]T instr's */
-#define XCHAL_HAVE_CALL4AND12 1 /* (obsolete option) */
-#define XCHAL_HAVE_ABS 1 /* ABS instruction */
-/*#define XCHAL_HAVE_POPC 0*/ /* POPC instruction */
-/*#define XCHAL_HAVE_CRC 0*/ /* CRC instruction */
-#define XCHAL_HAVE_RELEASE_SYNC 1 /* L32AI/S32RI instructions */
-#define XCHAL_HAVE_S32C1I 1 /* S32C1I instruction */
-#define XCHAL_HAVE_SPECULATION 0 /* speculation */
-#define XCHAL_HAVE_FULL_RESET 1 /* all regs/state reset */
-#define XCHAL_NUM_CONTEXTS 1 /* */
-#define XCHAL_NUM_MISC_REGS 0 /* num of scratch regs (0..4) */
-#define XCHAL_HAVE_TAP_MASTER 0 /* JTAG TAP control instr's */
-#define XCHAL_HAVE_PRID 1 /* processor ID register */
-#define XCHAL_HAVE_EXTERN_REGS 1 /* WER/RER instructions */
-#define XCHAL_HAVE_MX 0 /* MX core (Tensilica internal) */
-#define XCHAL_HAVE_MP_INTERRUPTS 0 /* interrupt distributor port */
-#define XCHAL_HAVE_MP_RUNSTALL 0 /* core RunStall control port */
-#define XCHAL_HAVE_PSO 0 /* Power Shut-Off */
-#define XCHAL_HAVE_PSO_CDM 0 /* core/debug/mem pwr domains */
-#define XCHAL_HAVE_PSO_FULL_RETENTION 0 /* all regs preserved on PSO */
-#define XCHAL_HAVE_THREADPTR 1 /* THREADPTR register */
-#define XCHAL_HAVE_BOOLEANS 1 /* boolean registers */
-#define XCHAL_HAVE_CP 1 /* CPENABLE reg (coprocessor) */
-#define XCHAL_CP_MAXCFG 2 /* max allowed cp id plus one */
-
-/* TODO: we have this option but currently our assembler does not support it */
-#define XCHAL_HAVE_MAC16 1 /* MAC16 package */
-
-#define XCHAL_HAVE_FUSION 0 /* Fusion*/
-#define XCHAL_HAVE_FUSION_FP 0 /* Fusion FP option */
-#define XCHAL_HAVE_FUSION_LOW_POWER 0 /* Fusion Low Power option */
-#define XCHAL_HAVE_FUSION_AES 0 /* Fusion BLE/Wifi AES-128 CCM option */
-#define XCHAL_HAVE_FUSION_CONVENC 0 /* Fusion Conv Encode option */
-#define XCHAL_HAVE_FUSION_LFSR_CRC 0 /* Fusion LFSR-CRC option */
-#define XCHAL_HAVE_FUSION_BITOPS 0 /* Fusion Bit Operations Support option */
-#define XCHAL_HAVE_FUSION_AVS 0 /* Fusion AVS option */
-#define XCHAL_HAVE_FUSION_16BIT_BASEBAND 0 /* Fusion 16-bit Baseband option */
-#define XCHAL_HAVE_HIFIPRO 0 /* HiFiPro Audio Engine pkg */
-#define XCHAL_HAVE_HIFI4 0 /* HiFi4 Audio Engine pkg */
-#define XCHAL_HAVE_HIFI4_VFPU 0 /* HiFi4 Audio Engine VFPU option */
-#define XCHAL_HAVE_HIFI3 0 /* HiFi3 Audio Engine pkg */
-#define XCHAL_HAVE_HIFI3_VFPU 0 /* HiFi3 Audio Engine VFPU option */
-#define XCHAL_HAVE_HIFI2 1 /* HiFi2 Audio Engine pkg */
-#define XCHAL_HAVE_HIFI2EP 1 /* HiFi2EP */
-#define XCHAL_HAVE_HIFI2_MUL32X24 1 /* HiFi2 and 32x24 MACs */
-#define XCHAL_HAVE_HIFI_MINI 0
-
-
-#define XCHAL_HAVE_VECTORFPU2005 0 /* vector or user floating-point pkg */
-#define XCHAL_HAVE_USER_DPFPU 0 /* user DP floating-point pkg */
-#define XCHAL_HAVE_USER_SPFPU 0 /* user DP floating-point pkg */
-#define XCHAL_HAVE_FP 0 /* single prec floating point */
-#define XCHAL_HAVE_FP_DIV 0 /* FP with DIV instructions */
-#define XCHAL_HAVE_FP_RECIP 0 /* FP with RECIP instructions */
-#define XCHAL_HAVE_FP_SQRT 0 /* FP with SQRT instructions */
-#define XCHAL_HAVE_FP_RSQRT 0 /* FP with RSQRT instructions */
-#define XCHAL_HAVE_DFP 0 /* double precision FP pkg */
-#define XCHAL_HAVE_DFP_DIV 0 /* DFP with DIV instructions */
-#define XCHAL_HAVE_DFP_RECIP 0 /* DFP with RECIP instructions*/
-#define XCHAL_HAVE_DFP_SQRT 0 /* DFP with SQRT instructions */
-#define XCHAL_HAVE_DFP_RSQRT 0 /* DFP with RSQRT instructions*/
-#define XCHAL_HAVE_DFP_ACCEL 0 /* double precision FP acceleration pkg */
-#define XCHAL_HAVE_DFP_accel XCHAL_HAVE_DFP_ACCEL /* for backward compatibility */
-
-#define XCHAL_HAVE_DFPU_SINGLE_ONLY 0 /* DFPU Coprocessor, single precision only */
-#define XCHAL_HAVE_DFPU_SINGLE_DOUBLE 0 /* DFPU Coprocessor, single and double precision */
-#define XCHAL_HAVE_VECTRA1 0 /* Vectra I pkg */
-#define XCHAL_HAVE_VECTRALX 0 /* Vectra LX pkg */
-#define XCHAL_HAVE_PDX4 0 /* PDX4 */
-#define XCHAL_HAVE_CONNXD2 0 /* ConnX D2 pkg */
-#define XCHAL_HAVE_CONNXD2_DUALLSFLIX 0 /* ConnX D2 & Dual LoadStore Flix */
-#define XCHAL_HAVE_BBE16 0 /* ConnX BBE16 pkg */
-#define XCHAL_HAVE_BBE16_RSQRT 0 /* BBE16 & vector recip sqrt */
-#define XCHAL_HAVE_BBE16_VECDIV 0 /* BBE16 & vector divide */
-#define XCHAL_HAVE_BBE16_DESPREAD 0 /* BBE16 & despread */
-#define XCHAL_HAVE_BBENEP 0 /* ConnX BBENEP pkgs */
-#define XCHAL_HAVE_BSP3 0 /* ConnX BSP3 pkg */
-#define XCHAL_HAVE_BSP3_TRANSPOSE 0 /* BSP3 & transpose32x32 */
-#define XCHAL_HAVE_SSP16 0 /* ConnX SSP16 pkg */
-#define XCHAL_HAVE_SSP16_VITERBI 0 /* SSP16 & viterbi */
-#define XCHAL_HAVE_TURBO16 0 /* ConnX Turbo16 pkg */
-#define XCHAL_HAVE_BBP16 0 /* ConnX BBP16 pkg */
-#define XCHAL_HAVE_FLIX3 0 /* basic 3-way FLIX option */
-#define XCHAL_HAVE_GRIVPEP 0 /* GRIVPEP is General Release of IVPEP */
-#define XCHAL_HAVE_GRIVPEP_HISTOGRAM 0 /* Histogram option on GRIVPEP */
-
-
-/*----------------------------------------------------------------------
- MISC
- ----------------------------------------------------------------------*/
-
-#define XCHAL_NUM_LOADSTORE_UNITS 1 /* load/store units */
-#define XCHAL_NUM_WRITEBUFFER_ENTRIES 16 /* size of write buffer */
-#define XCHAL_INST_FETCH_WIDTH 8 /* instr-fetch width in bytes */
-#define XCHAL_DATA_WIDTH 8 /* data width in bytes */
-#define XCHAL_DATA_PIPE_DELAY 1 /* d-side pipeline delay
- (1 = 5-stage, 2 = 7-stage) */
-#define XCHAL_CLOCK_GATING_GLOBAL 1 /* global clock gating */
-#define XCHAL_CLOCK_GATING_FUNCUNIT 1 /* funct. unit clock gating */
-/* In T1050, applies to selected core load and store instructions (see ISA): */
-#define XCHAL_UNALIGNED_LOAD_EXCEPTION 0 /* unaligned loads cause exc. */
-#define XCHAL_UNALIGNED_STORE_EXCEPTION 0 /* unaligned stores cause exc.*/
-#define XCHAL_UNALIGNED_LOAD_HW 1 /* unaligned loads work in hw */
-#define XCHAL_UNALIGNED_STORE_HW 1 /* unaligned stores work in hw*/
-
-#define XCHAL_SW_VERSION 1100002 /* sw version of this header */
-
-#define XCHAL_CORE_ID "hifiep_bd5" /* alphanum core name
- (CoreID) set in the Xtensa
- Processor Generator */
-
-#define XCHAL_BUILD_UNIQUE_ID 0x0005483B /* 22-bit sw build ID */
-
-/*
- * These definitions describe the hardware targeted by this software.
- */
-#define XCHAL_HW_CONFIGID0 0xC2B3DBFE /* ConfigID hi 32 bits*/
-#define XCHAL_HW_CONFIGID1 0x1C85483E /* ConfigID lo 32 bits*/
-#define XCHAL_HW_VERSION_NAME "LX6.0.2" /* full version name */
-#define XCHAL_HW_VERSION_MAJOR 2600 /* major ver# of targeted hw */
-#define XCHAL_HW_VERSION_MINOR 2 /* minor ver# of targeted hw */
-#define XCHAL_HW_VERSION 260002 /* major*100+minor */
-#define XCHAL_HW_REL_LX6 1
-#define XCHAL_HW_REL_LX6_0 1
-#define XCHAL_HW_REL_LX6_0_2 1
-#define XCHAL_HW_CONFIGID_RELIABLE 1
-/* If software targets a *range* of hardware versions, these are the bounds: */
-#define XCHAL_HW_MIN_VERSION_MAJOR 2600 /* major v of earliest tgt hw */
-#define XCHAL_HW_MIN_VERSION_MINOR 2 /* minor v of earliest tgt hw */
-#define XCHAL_HW_MIN_VERSION 260002 /* earliest targeted hw */
-#define XCHAL_HW_MAX_VERSION_MAJOR 2600 /* major v of latest tgt hw */
-#define XCHAL_HW_MAX_VERSION_MINOR 2 /* minor v of latest tgt hw */
-#define XCHAL_HW_MAX_VERSION 260002 /* latest targeted hw */
-
-
-/*----------------------------------------------------------------------
- CACHE
- ----------------------------------------------------------------------*/
-
-#define XCHAL_ICACHE_LINESIZE 128 /* I-cache line size in bytes */
-#define XCHAL_DCACHE_LINESIZE 128 /* D-cache line size in bytes */
-#define XCHAL_ICACHE_LINEWIDTH 7 /* log2(I line size in bytes) */
-#define XCHAL_DCACHE_LINEWIDTH 7 /* log2(D line size in bytes) */
-
-#define XCHAL_ICACHE_SIZE 0 /* I-cache size in bytes or 0 */
-#define XCHAL_DCACHE_SIZE 0 /* D-cache size in bytes or 0 */
-
-#define XCHAL_DCACHE_IS_WRITEBACK 0 /* writeback feature */
-#define XCHAL_DCACHE_IS_COHERENT 0 /* MP coherence feature */
-
-#define XCHAL_HAVE_PREFETCH 0 /* PREFCTL register */
-#define XCHAL_HAVE_PREFETCH_L1 0 /* prefetch to L1 dcache */
-#define XCHAL_PREFETCH_CASTOUT_LINES 0 /* dcache pref. castout bufsz */
-#define XCHAL_PREFETCH_ENTRIES 0 /* cache prefetch entries */
-#define XCHAL_PREFETCH_BLOCK_ENTRIES 0 /* prefetch block streams */
-#define XCHAL_HAVE_CACHE_BLOCKOPS 0 /* block prefetch for caches */
-#define XCHAL_HAVE_ICACHE_TEST 0 /* Icache test instructions */
-#define XCHAL_HAVE_DCACHE_TEST 0 /* Dcache test instructions */
-#define XCHAL_HAVE_ICACHE_DYN_WAYS 0 /* Icache dynamic way support */
-#define XCHAL_HAVE_DCACHE_DYN_WAYS 0 /* Dcache dynamic way support */
-
-
-
-
-/****************************************************************************
- Parameters Useful for PRIVILEGED (Supervisory or Non-Virtualized) Code
- ****************************************************************************/
-
-
-#ifndef XTENSA_HAL_NON_PRIVILEGED_ONLY
-
-/*----------------------------------------------------------------------
- CACHE
- ----------------------------------------------------------------------*/
-
-#define XCHAL_HAVE_PIF 1 /* any outbound PIF present */
-
-/* If present, cache size in bytes == (ways * 2^(linewidth + setwidth)). */
-
-/* Number of cache sets in log2(lines per way): */
-#define XCHAL_ICACHE_SETWIDTH 7
-#define XCHAL_DCACHE_SETWIDTH 8
-
-/* Cache set associativity (number of ways): */
-#define XCHAL_ICACHE_WAYS 3
-#define XCHAL_DCACHE_WAYS 3
-
-/* Cache features: */
-#define XCHAL_ICACHE_LINE_LOCKABLE 1
-#define XCHAL_DCACHE_LINE_LOCKABLE 1
-#define XCHAL_ICACHE_ECC_PARITY 0
-#define XCHAL_DCACHE_ECC_PARITY 0
-
-/* Cache access size in bytes (affects operation of SICW instruction): */
-#define XCHAL_ICACHE_ACCESS_SIZE 8
-#define XCHAL_DCACHE_ACCESS_SIZE 8
-
-#define XCHAL_DCACHE_BANKS 1 /* number of banks */
-
-/* Number of encoded cache attr bits (see <xtensa/hal.h> for decoded bits): */
-#define XCHAL_CA_BITS 4
-
-/* Whether MEMCTL register has anything useful */
-#define XCHAL_USE_MEMCTL (((XCHAL_LOOP_BUFFER_SIZE > 0) || \
- XCHAL_DCACHE_IS_COHERENT || \
- XCHAL_HAVE_ICACHE_DYN_WAYS || \
- XCHAL_HAVE_DCACHE_DYN_WAYS) && \
- (XCHAL_HW_MIN_VERSION >= XTENSA_HWVERSION_RE_2012_0))
-
-
-/*----------------------------------------------------------------------
- INTERNAL I/D RAM/ROMs and XLMI
- ----------------------------------------------------------------------*/
-
-#define XCHAL_NUM_INSTROM 0 /* number of core instr. ROMs */
-#define XCHAL_NUM_INSTRAM 1 /* number of core instr. RAMs */
-#define XCHAL_NUM_DATAROM 0 /* number of core data ROMs */
-#define XCHAL_NUM_DATARAM 1 /* number of core data RAMs */
-#define XCHAL_NUM_URAM 0 /* number of core unified RAMs*/
-#define XCHAL_NUM_XLMI 0 /* number of core XLMI ports */
-
-/* Instruction RAM 0: */
-#define XCHAL_INSTRAM0_VADDR 0xff2c0000 /* virtual address */
-#define XCHAL_INSTRAM0_PADDR 0xff2c0000 /* physical address */
-#define XCHAL_INSTRAM0_SIZE 0x14000 /* size in bytes */
-#define XCHAL_INSTRAM0_ECC_PARITY 0 /* ECC/parity type, 0=none */
-
-/* Data RAM 0: */
-#define XCHAL_DATARAM0_VADDR 0xff300000 /* virtual address */
-#define XCHAL_DATARAM0_PADDR 0xff300000 /* physical address */
-#define XCHAL_DATARAM0_SIZE 0x28000 /* size in bytes */
-#define XCHAL_DATARAM0_ECC_PARITY 0 /* ECC/parity type, 0=none */
-#define XCHAL_DATARAM0_BANKS 1 /* number of banks */
-
-
-#define XCHAL_HAVE_IMEM_LOADSTORE 1 /* can load/store to IROM/IRAM*/
-
-
-/*----------------------------------------------------------------------
- INTERRUPTS and TIMERS
- ----------------------------------------------------------------------*/
-
-#define XCHAL_HAVE_INTERRUPTS 1 /* interrupt option */
-#define XCHAL_HAVE_HIGHPRI_INTERRUPTS 1 /* med/high-pri. interrupts */
-#define XCHAL_HAVE_NMI 1 /* non-maskable interrupt */
-#define XCHAL_HAVE_CCOUNT 1 /* CCOUNT reg. (timer option) */
-#define XCHAL_NUM_TIMERS 3 /* number of CCOMPAREn regs */
-#define XCHAL_NUM_INTERRUPTS 22 /* number of interrupts */
-#define XCHAL_NUM_INTERRUPTS_LOG2 5 /* ceil(log2(NUM_INTERRUPTS)) */
-#define XCHAL_NUM_EXTINTERRUPTS 12 /* num of external interrupts */
-#define XCHAL_NUM_INTLEVELS 6 /* number of interrupt levels
- (not including level zero) */
-#define XCHAL_EXCM_LEVEL 5 /* level masked by PS.EXCM */
- /* (always 1 in XEA1; levels 2 .. EXCM_LEVEL are "medium priority") */
-
-/* Masks of interrupts at each interrupt level: */
-#define XCHAL_INTLEVEL1_MASK 0x0000000F
-#define XCHAL_INTLEVEL2_MASK 0x00000070
-#define XCHAL_INTLEVEL3_MASK 0x00000380
-#define XCHAL_INTLEVEL4_MASK 0x00200c00
-#define XCHAL_INTLEVEL5_MASK 0x000ff000
-#define XCHAL_INTLEVEL6_MASK 0x00000000
-#define XCHAL_INTLEVEL7_MASK 0x00100000
-
-/* Masks of interrupts at each range 1..n of interrupt levels: */
-#define XCHAL_INTLEVEL1_ANDBELOW_MASK 0x0000000F
-#define XCHAL_INTLEVEL2_ANDBELOW_MASK 0x0000007F
-#define XCHAL_INTLEVEL3_ANDBELOW_MASK 0x000003FF
-#define XCHAL_INTLEVEL4_ANDBELOW_MASK 0x00200FFF
-#define XCHAL_INTLEVEL5_ANDBELOW_MASK 0x002FFFFF
-#define XCHAL_INTLEVEL6_ANDBELOW_MASK 0x002FFFFF
-#define XCHAL_INTLEVEL7_ANDBELOW_MASK 0x003FFFFF
-
-/* Level of each interrupt: */
-#define XCHAL_INT0_LEVEL 1
-#define XCHAL_INT1_LEVEL 1
-#define XCHAL_INT2_LEVEL 1
-#define XCHAL_INT3_LEVEL 1
-
-#define XCHAL_INT4_LEVEL 2
-#define XCHAL_INT5_LEVEL 2
-#define XCHAL_INT6_LEVEL 2
-#define XCHAL_INT7_LEVEL 3
-
-#define XCHAL_INT8_LEVEL 3
-#define XCHAL_INT9_LEVEL 3
-#define XCHAL_INT10_LEVEL 4
-#define XCHAL_INT11_LEVEL 4
-
-#define XCHAL_INT12_LEVEL 5
-#define XCHAL_INT13_LEVEL 5
-#define XCHAL_INT14_LEVEL 5
-#define XCHAL_INT15_LEVEL 5
-
-#define XCHAL_INT16_LEVEL 5
-#define XCHAL_INT17_LEVEL 5
-#define XCHAL_INT18_LEVEL 5
-#define XCHAL_INT19_LEVEL 5
-
-#define XCHAL_INT20_LEVEL 7
-#define XCHAL_INT21_LEVEL 4
-
-#define XCHAL_DEBUGLEVEL 6 /* debug interrupt level */
-#define XCHAL_HAVE_DEBUG_EXTERN_INT 1 /* OCD external db interrupt */
-#define XCHAL_NMILEVEL 7 /* NMI "level" (for use with
- EXCSAVE/EPS/EPC_n, RFI n) */
-
-/* Type of each interrupt: */
-#define XCHAL_INT0_TYPE XTHAL_INTTYPE_SOFTWARE
-#define XCHAL_INT1_TYPE XTHAL_INTTYPE_TIMER
-#define XCHAL_INT2_TYPE XTHAL_INTTYPE_SOFTWARE
-#define XCHAL_INT3_TYPE XTHAL_INTTYPE_SOFTWARE
-#define XCHAL_INT4_TYPE XTHAL_INTTYPE_EXTERN_LEVEL
-#define XCHAL_INT5_TYPE XTHAL_INTTYPE_TIMER
-#define XCHAL_INT6_TYPE XTHAL_INTTYPE_SOFTWARE
-#define XCHAL_INT7_TYPE XTHAL_INTTYPE_TIMER
-#define XCHAL_INT8_TYPE XTHAL_INTTYPE_SOFTWARE
-#define XCHAL_INT9_TYPE XTHAL_INTTYPE_SOFTWARE
-#define XCHAL_INT10_TYPE XTHAL_INTTYPE_EXTERN_LEVEL
-#define XCHAL_INT11_TYPE XTHAL_INTTYPE_EXTERN_LEVEL
-#define XCHAL_INT12_TYPE XTHAL_INTTYPE_SOFTWARE
-#define XCHAL_INT13_TYPE XTHAL_INTTYPE_EXTERN_LEVEL
-#define XCHAL_INT14_TYPE XTHAL_INTTYPE_EXTERN_LEVEL
-#define XCHAL_INT15_TYPE XTHAL_INTTYPE_EXTERN_LEVEL
-#define XCHAL_INT16_TYPE XTHAL_INTTYPE_EXTERN_LEVEL
-#define XCHAL_INT17_TYPE XTHAL_INTTYPE_EXTERN_LEVEL
-#define XCHAL_INT18_TYPE XTHAL_INTTYPE_EXTERN_LEVEL
-#define XCHAL_INT19_TYPE XTHAL_INTTYPE_EXTERN_LEVEL
-#define XCHAL_INT20_TYPE XTHAL_INTTYPE_NMI
-#define XCHAL_INT21_TYPE XTHAL_INTTYPE_EXTERN_LEVEL
-
-/* Masks of interrupts for each type of interrupt: */
-#define XCHAL_INTTYPE_MASK_UNCONFIGURED 0xFFC00000
-#define XCHAL_INTTYPE_MASK_SOFTWARE 0x0000134d
-#define XCHAL_INTTYPE_MASK_EXTERN_EDGE 0x00000000
-#define XCHAL_INTTYPE_MASK_EXTERN_LEVEL 0x002fec10
-#define XCHAL_INTTYPE_MASK_TIMER 0x000000a2
-#define XCHAL_INTTYPE_MASK_NMI 0x00100000
-#define XCHAL_INTTYPE_MASK_WRITE_ERROR 0x00000000
-#define XCHAL_INTTYPE_MASK_PROFILING 0x00000000
-
-/* Interrupt numbers assigned to specific interrupt sources: */
-#define XCHAL_TIMER0_INTERRUPT 1 /* CCOMPARE0 */
-#define XCHAL_TIMER1_INTERRUPT 5 /* CCOMPARE1 */
-#define XCHAL_TIMER2_INTERRUPT 7 /* CCOMPARE2 */
-#define XCHAL_TIMER3_INTERRUPT XTHAL_TIMER_UNCONFIGURED
-#define XCHAL_NMI_INTERRUPT 20 /* non-maskable interrupt */
-
-/* Interrupt numbers for levels at which only one interrupt is configured: */
-//#define XCHAL_INTLEVEL2_NUM 8
-//#define XCHAL_INTLEVEL4_NUM 12
-//#define XCHAL_INTLEVEL5_NUM 13
-#define XCHAL_INTLEVEL7_NUM 20
-/* (There are many interrupts each at level(s) 1, 3.) */
-
-
-/*
- * External interrupt mapping.
- * These macros describe how Xtensa processor interrupt numbers
- * (as numbered internally, eg. in INTERRUPT and INTENABLE registers)
- * map to external BInterrupt<n> pins, for those interrupts
- * configured as external (level-triggered, edge-triggered, or NMI).
- * See the Xtensa processor databook for more details.
- */
-
-/* Core interrupt numbers mapped to each EXTERNAL BInterrupt pin number: */
-#define XCHAL_EXTINT0_NUM 0 /* (intlevel 1) */
-#define XCHAL_EXTINT1_NUM 1 /* (intlevel 1) */
-#define XCHAL_EXTINT2_NUM 2 /* (intlevel 1) */
-#define XCHAL_EXTINT3_NUM 3 /* (intlevel 1) */
-#define XCHAL_EXTINT4_NUM 4 /* (intlevel 1) */
-#define XCHAL_EXTINT5_NUM 5 /* (intlevel 1) */
-#define XCHAL_EXTINT6_NUM 8 /* (intlevel 2) */
-#define XCHAL_EXTINT7_NUM 9 /* (intlevel 3) */
-#define XCHAL_EXTINT8_NUM 12 /* (intlevel 4) */
-#define XCHAL_EXTINT9_NUM 14 /* (intlevel 7) */
-#define XCHAL_EXTINT10_NUM 15 /* (intlevel 1) */
-#define XCHAL_EXTINT11_NUM 16 /* (intlevel 1) */
-#define XCHAL_EXTINT12_NUM 17 /* (intlevel 1) */
-#define XCHAL_EXTINT13_NUM 18 /* (intlevel 1) */
-#define XCHAL_EXTINT14_NUM 19 /* (intlevel 1) */
-#define XCHAL_EXTINT15_NUM 20 /* (intlevel 1) */
-#define XCHAL_EXTINT16_NUM 21 /* (intlevel 3) */
-/* EXTERNAL BInterrupt pin numbers mapped to each core interrupt number: */
-#define XCHAL_INT0_EXTNUM 0 /* (intlevel 1) */
-#define XCHAL_INT1_EXTNUM 1 /* (intlevel 1) */
-#define XCHAL_INT2_EXTNUM 2 /* (intlevel 1) */
-#define XCHAL_INT3_EXTNUM 3 /* (intlevel 1) */
-#define XCHAL_INT4_EXTNUM 4 /* (intlevel 1) */
-#define XCHAL_INT5_EXTNUM 5 /* (intlevel 1) */
-#define XCHAL_INT8_EXTNUM 6 /* (intlevel 2) */
-#define XCHAL_INT9_EXTNUM 7 /* (intlevel 3) */
-#define XCHAL_INT12_EXTNUM 8 /* (intlevel 4) */
-#define XCHAL_INT14_EXTNUM 9 /* (intlevel 7) */
-#define XCHAL_INT15_EXTNUM 10 /* (intlevel 1) */
-#define XCHAL_INT16_EXTNUM 11 /* (intlevel 1) */
-#define XCHAL_INT17_EXTNUM 12 /* (intlevel 1) */
-#define XCHAL_INT18_EXTNUM 13 /* (intlevel 1) */
-#define XCHAL_INT19_EXTNUM 14 /* (intlevel 1) */
-#define XCHAL_INT20_EXTNUM 15 /* (intlevel 1) */
-#define XCHAL_INT21_EXTNUM 16 /* (intlevel 3) */
-
-
-/*----------------------------------------------------------------------
- EXCEPTIONS and VECTORS
- ----------------------------------------------------------------------*/
-
-#define XCHAL_XEA_VERSION 2 /* Xtensa Exception Architecture
- number: 1 == XEA1 (old)
- 2 == XEA2 (new)
- 0 == XEAX (extern) or TX */
-#define XCHAL_HAVE_XEA1 0 /* Exception Architecture 1 */
-#define XCHAL_HAVE_XEA2 1 /* Exception Architecture 2 */
-#define XCHAL_HAVE_XEAX 0 /* External Exception Arch. */
-#define XCHAL_HAVE_EXCEPTIONS 1 /* exception option */
-#define XCHAL_HAVE_HALT 0 /* halt architecture option */
-#define XCHAL_HAVE_BOOTLOADER 0 /* boot loader (for TX) */
-#define XCHAL_HAVE_MEM_ECC_PARITY 0 /* local memory ECC/parity */
-#define XCHAL_HAVE_VECTOR_SELECT 1 /* relocatable vectors */
-#define XCHAL_HAVE_VECBASE 1 /* relocatable vectors */
-#define XCHAL_VECBASE_RESET_VADDR 0xff2c0400 /* VECBASE reset value */
-#define XCHAL_VECBASE_RESET_PADDR 0xff2c0400
-#define XCHAL_RESET_VECBASE_OVERLAP 0
-
-#define XCHAL_RESET_VECTOR0_VADDR 0xff2c0000
-#define XCHAL_RESET_VECTOR0_PADDR 0xff2c0000
-#define XCHAL_RESET_VECTOR1_VADDR 0xff2c0000
-#define XCHAL_RESET_VECTOR1_PADDR 0xff2c0000
-#define XCHAL_RESET_VECTOR_VADDR 0xff2c0000
-#define XCHAL_RESET_VECTOR_PADDR 0xff2c0000
-#define XCHAL_USER_VECOFS 0x0000025c
-#define XCHAL_USER_VECTOR_VADDR 0xff2c065c
-#define XCHAL_USER_VECTOR_PADDR 0xff2c065c
-#define XCHAL_KERNEL_VECOFS 0x0000023c
-#define XCHAL_KERNEL_VECTOR_VADDR 0xff2c063c
-#define XCHAL_KERNEL_VECTOR_PADDR 0xff2c063c
-#define XCHAL_DOUBLEEXC_VECOFS 0x0000027c
-#define XCHAL_DOUBLEEXC_VECTOR_VADDR 0xff2c067c
-#define XCHAL_DOUBLEEXC_VECTOR_PADDR 0xff2c067c
-#define XCHAL_WINDOW_OF4_VECOFS 0x00000000
-#define XCHAL_WINDOW_UF4_VECOFS 0x00000040
-#define XCHAL_WINDOW_OF8_VECOFS 0x00000080
-#define XCHAL_WINDOW_UF8_VECOFS 0x000000C0
-#define XCHAL_WINDOW_OF12_VECOFS 0x00000100
-#define XCHAL_WINDOW_UF12_VECOFS 0x00000140
-#define XCHAL_WINDOW_VECTORS_VADDR 0xff2c0400
-#define XCHAL_WINDOW_VECTORS_PADDR 0xff2c0400
-#define XCHAL_INTLEVEL2_VECOFS 0x0000017c
-#define XCHAL_INTLEVEL2_VECTOR_VADDR 0xff2c057c
-#define XCHAL_INTLEVEL2_VECTOR_PADDR 0xff2c057c
-#define XCHAL_INTLEVEL3_VECOFS 0x0000019c
-#define XCHAL_INTLEVEL3_VECTOR_VADDR 0xff2c059c
-#define XCHAL_INTLEVEL3_VECTOR_PADDR 0xff2c059c
-#define XCHAL_INTLEVEL4_VECOFS 0x000001bc
-#define XCHAL_INTLEVEL4_VECTOR_VADDR 0xff2c05bc
-#define XCHAL_INTLEVEL4_VECTOR_PADDR 0xff2c05bc
-#define XCHAL_INTLEVEL5_VECOFS 0x000001dc
-#define XCHAL_INTLEVEL5_VECTOR_VADDR 0xff2c05dc
-#define XCHAL_INTLEVEL5_VECTOR_PADDR 0xff2c05dc
-#define XCHAL_INTLEVEL6_VECOFS 0x000001fc
-#define XCHAL_INTLEVEL6_VECTOR_VADDR 0xff2c05fc
-#define XCHAL_INTLEVEL6_VECTOR_PADDR 0xff2c05fc
-#define XCHAL_DEBUG_VECOFS XCHAL_INTLEVEL6_VECOFS
-#define XCHAL_DEBUG_VECTOR_VADDR XCHAL_INTLEVEL6_VECTOR_VADDR
-#define XCHAL_DEBUG_VECTOR_PADDR XCHAL_INTLEVEL6_VECTOR_PADDR
-#define XCHAL_NMI_VECOFS 0x0000021c
-#define XCHAL_NMI_VECTOR_VADDR 0xff2c061c
-#define XCHAL_NMI_VECTOR_PADDR 0xff2c061c
-#define XCHAL_INTLEVEL7_VECOFS XCHAL_NMI_VECOFS
-#define XCHAL_INTLEVEL7_VECTOR_VADDR XCHAL_NMI_VECTOR_VADDR
-#define XCHAL_INTLEVEL7_VECTOR_PADDR XCHAL_NMI_VECTOR_PADDR
-
-
-/*----------------------------------------------------------------------
- DEBUG MODULE
- ----------------------------------------------------------------------*/
-
-/* Misc */
-#define XCHAL_HAVE_DEBUG_ERI 0 /* ERI to debug module */
-#define XCHAL_HAVE_DEBUG_APB 0 /* APB to debug module */
-#define XCHAL_HAVE_DEBUG_JTAG 1 /* JTAG to debug module */
-
-/* On-Chip Debug (OCD) */
-#define XCHAL_HAVE_OCD 1 /* OnChipDebug option */
-#define XCHAL_NUM_IBREAK 2 /* number of IBREAKn regs */
-#define XCHAL_NUM_DBREAK 2 /* number of DBREAKn regs */
-#define XCHAL_HAVE_OCD_DIR_ARRAY 1 /* faster OCD option (to LX4) */
-#define XCHAL_HAVE_OCD_LS32DDR 1 /* L32DDR/S32DDR (faster OCD) */
-
-/* TRAX (in core) */
-#define XCHAL_HAVE_TRAX 0 /* TRAX in debug module */
-#define XCHAL_TRAX_MEM_SIZE 0 /* TRAX memory size in bytes */
-#define XCHAL_TRAX_MEM_SHAREABLE 0 /* start/end regs; ready sig. */
-#define XCHAL_TRAX_ATB_WIDTH 0 /* ATB width (bits), 0=no ATB */
-#define XCHAL_TRAX_TIME_WIDTH 0 /* timestamp bitwidth, 0=none */
-
-/* Perf counters */
-#define XCHAL_NUM_PERF_COUNTERS 0 /* performance counters */
-
-
-/*----------------------------------------------------------------------
- MMU
- ----------------------------------------------------------------------*/
-
-/* See core-matmap.h header file for more details. */
-
-#define XCHAL_HAVE_TLBS 1 /* inverse of HAVE_CACHEATTR */
-#define XCHAL_HAVE_SPANNING_WAY 1 /* one way maps I+D 4GB vaddr */
-#define XCHAL_SPANNING_WAY 0 /* TLB spanning way number */
-#define XCHAL_HAVE_IDENTITY_MAP 0 /* vaddr == paddr always */
-#define XCHAL_HAVE_CACHEATTR 0 /* CACHEATTR register present */
-#define XCHAL_HAVE_MIMIC_CACHEATTR 0 /* region protection */
-#define XCHAL_HAVE_XLT_CACHEATTR 1 /* region prot. w/translation */
-#define XCHAL_HAVE_PTP_MMU 0 /* full MMU (with page table
- [autorefill] and protection)
- usable for an MMU-based OS */
-/* If none of the above last 4 are set, it's a custom TLB configuration. */
-
-#define XCHAL_MMU_ASID_BITS 0 /* number of bits in ASIDs */
-#define XCHAL_MMU_RINGS 1 /* number of rings (1..4) */
-#define XCHAL_MMU_RING_BITS 0 /* num of bits in RING field */
-
-#endif /* !XTENSA_HAL_NON_PRIVILEGED_ONLY */
-
-
-#endif /* _XTENSA_CORE_CONFIGURATION_H */
-
diff --git a/src/platform/baytrail/include/arch/xtensa/config/core-isa-cht.h b/src/platform/baytrail/include/arch/xtensa/config/core-isa-cht.h
deleted file mode 100644
index 0657bc3..0000000
--- a/src/platform/baytrail/include/arch/xtensa/config/core-isa-cht.h
+++ /dev/null
@@ -1,598 +0,0 @@
-/*
- * xtensa/config/core-isa.h -- HAL definitions that are dependent on Xtensa
- * processor CORE configuration
- *
- * See <xtensa/config/core.h>, which includes this file, for more details.
- */
-
-/* Xtensa processor core configuration information.
-
- Customer ID=4313; Build=0x5483b; Copyright (c) 1999-2015 Tensilica Inc.
-
- Permission is hereby granted, free of charge, to any person obtaining
- a copy of this software and associated documentation files (the
- "Software"), to deal in the Software without restriction, including
- without limitation the rights to use, copy, modify, merge, publish,
- distribute, sublicense, and/or sell copies of the Software, and to
- permit persons to whom the Software is furnished to do so, subject to
- the following conditions:
-
- The above copyright notice and this permission notice shall be included
- in all copies or substantial portions of the Software.
-
- THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
- EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
- MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
- IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY
- CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
- TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
- SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. */
-
-#ifndef _XTENSA_CORE_CONFIGURATION_H
-#define _XTENSA_CORE_CONFIGURATION_H
-
-
-/****************************************************************************
- Parameters Useful for Any Code, USER or PRIVILEGED
- ****************************************************************************/
-
-/*
- * Note: Macros of the form XCHAL_HAVE_*** have a value of 1 if the option is
- * configured, and a value of 0 otherwise. These macros are always defined.
- */
-
-
-/*----------------------------------------------------------------------
- ISA
- ----------------------------------------------------------------------*/
-
-#define XCHAL_HAVE_BE 0 /* big-endian byte ordering */
-#define XCHAL_HAVE_WINDOWED 1 /* windowed registers option */
-#define XCHAL_NUM_AREGS 32 /* num of physical addr regs */
-#define XCHAL_NUM_AREGS_LOG2 5 /* log2(XCHAL_NUM_AREGS) */
-#define XCHAL_MAX_INSTRUCTION_SIZE 8 /* max instr bytes (3..8) */
-#define XCHAL_HAVE_DEBUG 1 /* debug option */
-#define XCHAL_HAVE_DENSITY 1 /* 16-bit instructions */
-#define XCHAL_HAVE_LOOPS 1 /* zero-overhead loops */
-#define XCHAL_LOOP_BUFFER_SIZE 0 /* zero-ov. loop instr buffer size */
-#define XCHAL_HAVE_NSA 1 /* NSA/NSAU instructions */
-#define XCHAL_HAVE_MINMAX 1 /* MIN/MAX instructions */
-#define XCHAL_HAVE_SEXT 1 /* SEXT instruction */
-#define XCHAL_HAVE_DEPBITS 0 /* DEPBITS instruction */
-#define XCHAL_HAVE_CLAMPS 1 /* CLAMPS instruction */
-#define XCHAL_HAVE_MUL16 1 /* MUL16S/MUL16U instructions */
-#define XCHAL_HAVE_MUL32 1 /* MULL instruction */
-#define XCHAL_HAVE_MUL32_HIGH 1 /* MULUH/MULSH instructions */
-#define XCHAL_HAVE_DIV32 0 /* QUOS/QUOU/REMS/REMU instructions */
-#define XCHAL_HAVE_L32R 1 /* L32R instruction */
-#define XCHAL_HAVE_ABSOLUTE_LITERALS 0 /* non-PC-rel (extended) L32R */
-#define XCHAL_HAVE_CONST16 0 /* CONST16 instruction */
-#define XCHAL_HAVE_ADDX 1 /* ADDX#/SUBX# instructions */
-#define XCHAL_HAVE_WIDE_BRANCHES 0 /* B*.W18 or B*.W15 instr's */
-#define XCHAL_HAVE_PREDICTED_BRANCHES 0 /* B[EQ/EQZ/NE/NEZ]T instr's */
-#define XCHAL_HAVE_CALL4AND12 1 /* (obsolete option) */
-#define XCHAL_HAVE_ABS 1 /* ABS instruction */
-/*#define XCHAL_HAVE_POPC 0*/ /* POPC instruction */
-/*#define XCHAL_HAVE_CRC 0*/ /* CRC instruction */
-#define XCHAL_HAVE_RELEASE_SYNC 1 /* L32AI/S32RI instructions */
-#define XCHAL_HAVE_S32C1I 1 /* S32C1I instruction */
-#define XCHAL_HAVE_SPECULATION 0 /* speculation */
-#define XCHAL_HAVE_FULL_RESET 1 /* all regs/state reset */
-#define XCHAL_NUM_CONTEXTS 1 /* */
-#define XCHAL_NUM_MISC_REGS 0 /* num of scratch regs (0..4) */
-#define XCHAL_HAVE_TAP_MASTER 0 /* JTAG TAP control instr's */
-#define XCHAL_HAVE_PRID 1 /* processor ID register */
-#define XCHAL_HAVE_EXTERN_REGS 1 /* WER/RER instructions */
-#define XCHAL_HAVE_MX 0 /* MX core (Tensilica internal) */
-#define XCHAL_HAVE_MP_INTERRUPTS 0 /* interrupt distributor port */
-#define XCHAL_HAVE_MP_RUNSTALL 0 /* core RunStall control port */
-#define XCHAL_HAVE_PSO 0 /* Power Shut-Off */
-#define XCHAL_HAVE_PSO_CDM 0 /* core/debug/mem pwr domains */
-#define XCHAL_HAVE_PSO_FULL_RETENTION 0 /* all regs preserved on PSO */
-#define XCHAL_HAVE_THREADPTR 1 /* THREADPTR register */
-#define XCHAL_HAVE_BOOLEANS 1 /* boolean registers */
-#define XCHAL_HAVE_CP 1 /* CPENABLE reg (coprocessor) */
-#define XCHAL_CP_MAXCFG 2 /* max allowed cp id plus one */
-
-/* TODO: we have this option but currently our assembler does not support it */
-#define XCHAL_HAVE_MAC16 1 /* MAC16 package */
-
-#define XCHAL_HAVE_FUSION 0 /* Fusion*/
-#define XCHAL_HAVE_FUSION_FP 0 /* Fusion FP option */
-#define XCHAL_HAVE_FUSION_LOW_POWER 0 /* Fusion Low Power option */
-#define XCHAL_HAVE_FUSION_AES 0 /* Fusion BLE/Wifi AES-128 CCM option */
-#define XCHAL_HAVE_FUSION_CONVENC 0 /* Fusion Conv Encode option */
-#define XCHAL_HAVE_FUSION_LFSR_CRC 0 /* Fusion LFSR-CRC option */
-#define XCHAL_HAVE_FUSION_BITOPS 0 /* Fusion Bit Operations Support option */
-#define XCHAL_HAVE_FUSION_AVS 0 /* Fusion AVS option */
-#define XCHAL_HAVE_FUSION_16BIT_BASEBAND 0 /* Fusion 16-bit Baseband option */
-#define XCHAL_HAVE_HIFIPRO 0 /* HiFiPro Audio Engine pkg */
-#define XCHAL_HAVE_HIFI4 0 /* HiFi4 Audio Engine pkg */
-#define XCHAL_HAVE_HIFI4_VFPU 0 /* HiFi4 Audio Engine VFPU option */
-#define XCHAL_HAVE_HIFI3 0 /* HiFi3 Audio Engine pkg */
-#define XCHAL_HAVE_HIFI3_VFPU 0 /* HiFi3 Audio Engine VFPU option */
-#define XCHAL_HAVE_HIFI2 1 /* HiFi2 Audio Engine pkg */
-#define XCHAL_HAVE_HIFI2EP 1 /* HiFi2EP */
-#define XCHAL_HAVE_HIFI2_MUL32X24 1 /* HiFi2 and 32x24 MACs */
-#define XCHAL_HAVE_HIFI_MINI 0
-
-
-#define XCHAL_HAVE_VECTORFPU2005 0 /* vector or user floating-point pkg */
-#define XCHAL_HAVE_USER_DPFPU 0 /* user DP floating-point pkg */
-#define XCHAL_HAVE_USER_SPFPU 0 /* user DP floating-point pkg */
-#define XCHAL_HAVE_FP 0 /* single prec floating point */
-#define XCHAL_HAVE_FP_DIV 0 /* FP with DIV instructions */
-#define XCHAL_HAVE_FP_RECIP 0 /* FP with RECIP instructions */
-#define XCHAL_HAVE_FP_SQRT 0 /* FP with SQRT instructions */
-#define XCHAL_HAVE_FP_RSQRT 0 /* FP with RSQRT instructions */
-#define XCHAL_HAVE_DFP 0 /* double precision FP pkg */
-#define XCHAL_HAVE_DFP_DIV 0 /* DFP with DIV instructions */
-#define XCHAL_HAVE_DFP_RECIP 0 /* DFP with RECIP instructions*/
-#define XCHAL_HAVE_DFP_SQRT 0 /* DFP with SQRT instructions */
-#define XCHAL_HAVE_DFP_RSQRT 0 /* DFP with RSQRT instructions*/
-#define XCHAL_HAVE_DFP_ACCEL 0 /* double precision FP acceleration pkg */
-#define XCHAL_HAVE_DFP_accel XCHAL_HAVE_DFP_ACCEL /* for backward compatibility */
-
-#define XCHAL_HAVE_DFPU_SINGLE_ONLY 0 /* DFPU Coprocessor, single precision only */
-#define XCHAL_HAVE_DFPU_SINGLE_DOUBLE 0 /* DFPU Coprocessor, single and double precision */
-#define XCHAL_HAVE_VECTRA1 0 /* Vectra I pkg */
-#define XCHAL_HAVE_VECTRALX 0 /* Vectra LX pkg */
-#define XCHAL_HAVE_PDX4 0 /* PDX4 */
-#define XCHAL_HAVE_CONNXD2 0 /* ConnX D2 pkg */
-#define XCHAL_HAVE_CONNXD2_DUALLSFLIX 0 /* ConnX D2 & Dual LoadStore Flix */
-#define XCHAL_HAVE_BBE16 0 /* ConnX BBE16 pkg */
-#define XCHAL_HAVE_BBE16_RSQRT 0 /* BBE16 & vector recip sqrt */
-#define XCHAL_HAVE_BBE16_VECDIV 0 /* BBE16 & vector divide */
-#define XCHAL_HAVE_BBE16_DESPREAD 0 /* BBE16 & despread */
-#define XCHAL_HAVE_BBENEP 0 /* ConnX BBENEP pkgs */
-#define XCHAL_HAVE_BSP3 0 /* ConnX BSP3 pkg */
-#define XCHAL_HAVE_BSP3_TRANSPOSE 0 /* BSP3 & transpose32x32 */
-#define XCHAL_HAVE_SSP16 0 /* ConnX SSP16 pkg */
-#define XCHAL_HAVE_SSP16_VITERBI 0 /* SSP16 & viterbi */
-#define XCHAL_HAVE_TURBO16 0 /* ConnX Turbo16 pkg */
-#define XCHAL_HAVE_BBP16 0 /* ConnX BBP16 pkg */
-#define XCHAL_HAVE_FLIX3 0 /* basic 3-way FLIX option */
-#define XCHAL_HAVE_GRIVPEP 0 /* GRIVPEP is General Release of IVPEP */
-#define XCHAL_HAVE_GRIVPEP_HISTOGRAM 0 /* Histogram option on GRIVPEP */
-
-
-/*----------------------------------------------------------------------
- MISC
- ----------------------------------------------------------------------*/
-
-#define XCHAL_NUM_LOADSTORE_UNITS 1 /* load/store units */
-#define XCHAL_NUM_WRITEBUFFER_ENTRIES 16 /* size of write buffer */
-#define XCHAL_INST_FETCH_WIDTH 8 /* instr-fetch width in bytes */
-#define XCHAL_DATA_WIDTH 8 /* data width in bytes */
-#define XCHAL_DATA_PIPE_DELAY 1 /* d-side pipeline delay
- (1 = 5-stage, 2 = 7-stage) */
-#define XCHAL_CLOCK_GATING_GLOBAL 1 /* global clock gating */
-#define XCHAL_CLOCK_GATING_FUNCUNIT 1 /* funct. unit clock gating */
-/* In T1050, applies to selected core load and store instructions (see ISA): */
-#define XCHAL_UNALIGNED_LOAD_EXCEPTION 0 /* unaligned loads cause exc. */
-#define XCHAL_UNALIGNED_STORE_EXCEPTION 0 /* unaligned stores cause exc.*/
-#define XCHAL_UNALIGNED_LOAD_HW 1 /* unaligned loads work in hw */
-#define XCHAL_UNALIGNED_STORE_HW 1 /* unaligned stores work in hw*/
-
-#define XCHAL_SW_VERSION 1100002 /* sw version of this header */
-
-#define XCHAL_CORE_ID "hifiep_bd5" /* alphanum core name
- (CoreID) set in the Xtensa
- Processor Generator */
-
-#define XCHAL_BUILD_UNIQUE_ID 0x0005483B /* 22-bit sw build ID */
-
-/*
- * These definitions describe the hardware targeted by this software.
- */
-#define XCHAL_HW_CONFIGID0 0xC2B3DBFE /* ConfigID hi 32 bits*/
-#define XCHAL_HW_CONFIGID1 0x1C85483E /* ConfigID lo 32 bits*/
-#define XCHAL_HW_VERSION_NAME "LX6.0.2" /* full version name */
-#define XCHAL_HW_VERSION_MAJOR 2600 /* major ver# of targeted hw */
-#define XCHAL_HW_VERSION_MINOR 2 /* minor ver# of targeted hw */
-#define XCHAL_HW_VERSION 260002 /* major*100+minor */
-#define XCHAL_HW_REL_LX6 1
-#define XCHAL_HW_REL_LX6_0 1
-#define XCHAL_HW_REL_LX6_0_2 1
-#define XCHAL_HW_CONFIGID_RELIABLE 1
-/* If software targets a *range* of hardware versions, these are the bounds: */
-#define XCHAL_HW_MIN_VERSION_MAJOR 2600 /* major v of earliest tgt hw */
-#define XCHAL_HW_MIN_VERSION_MINOR 2 /* minor v of earliest tgt hw */
-#define XCHAL_HW_MIN_VERSION 260002 /* earliest targeted hw */
-#define XCHAL_HW_MAX_VERSION_MAJOR 2600 /* major v of latest tgt hw */
-#define XCHAL_HW_MAX_VERSION_MINOR 2 /* minor v of latest tgt hw */
-#define XCHAL_HW_MAX_VERSION 260002 /* latest targeted hw */
-
-
-/*----------------------------------------------------------------------
- CACHE
- ----------------------------------------------------------------------*/
-
-#define XCHAL_ICACHE_LINESIZE 128 /* I-cache line size in bytes */
-#define XCHAL_DCACHE_LINESIZE 128 /* D-cache line size in bytes */
-#define XCHAL_ICACHE_LINEWIDTH 7 /* log2(I line size in bytes) */
-#define XCHAL_DCACHE_LINEWIDTH 7 /* log2(D line size in bytes) */
-
-#define XCHAL_ICACHE_SIZE 0 /* I-cache size in bytes or 0 */
-#define XCHAL_DCACHE_SIZE 0 /* D-cache size in bytes or 0 */
-
-#define XCHAL_DCACHE_IS_WRITEBACK 0 /* writeback feature */
-#define XCHAL_DCACHE_IS_COHERENT 0 /* MP coherence feature */
-
-#define XCHAL_HAVE_PREFETCH 0 /* PREFCTL register */
-#define XCHAL_HAVE_PREFETCH_L1 0 /* prefetch to L1 dcache */
-#define XCHAL_PREFETCH_CASTOUT_LINES 0 /* dcache pref. castout bufsz */
-#define XCHAL_PREFETCH_ENTRIES 0 /* cache prefetch entries */
-#define XCHAL_PREFETCH_BLOCK_ENTRIES 0 /* prefetch block streams */
-#define XCHAL_HAVE_CACHE_BLOCKOPS 0 /* block prefetch for caches */
-#define XCHAL_HAVE_ICACHE_TEST 0 /* Icache test instructions */
-#define XCHAL_HAVE_DCACHE_TEST 0 /* Dcache test instructions */
-#define XCHAL_HAVE_ICACHE_DYN_WAYS 0 /* Icache dynamic way support */
-#define XCHAL_HAVE_DCACHE_DYN_WAYS 0 /* Dcache dynamic way support */
-
-
-
-
-/****************************************************************************
- Parameters Useful for PRIVILEGED (Supervisory or Non-Virtualized) Code
- ****************************************************************************/
-
-
-#ifndef XTENSA_HAL_NON_PRIVILEGED_ONLY
-
-/*----------------------------------------------------------------------
- CACHE
- ----------------------------------------------------------------------*/
-
-#define XCHAL_HAVE_PIF 1 /* any outbound PIF present */
-
-/* If present, cache size in bytes == (ways * 2^(linewidth + setwidth)). */
-
-/* Number of cache sets in log2(lines per way): */
-#define XCHAL_ICACHE_SETWIDTH 7
-#define XCHAL_DCACHE_SETWIDTH 8
-
-/* Cache set associativity (number of ways): */
-#define XCHAL_ICACHE_WAYS 3
-#define XCHAL_DCACHE_WAYS 3
-
-/* Cache features: */
-#define XCHAL_ICACHE_LINE_LOCKABLE 1
-#define XCHAL_DCACHE_LINE_LOCKABLE 1
-#define XCHAL_ICACHE_ECC_PARITY 0
-#define XCHAL_DCACHE_ECC_PARITY 0
-
-/* Cache access size in bytes (affects operation of SICW instruction): */
-#define XCHAL_ICACHE_ACCESS_SIZE 8
-#define XCHAL_DCACHE_ACCESS_SIZE 8
-
-#define XCHAL_DCACHE_BANKS 1 /* number of banks */
-
-/* Number of encoded cache attr bits (see <xtensa/hal.h> for decoded bits): */
-#define XCHAL_CA_BITS 4
-
-/* Whether MEMCTL register has anything useful */
-#define XCHAL_USE_MEMCTL (((XCHAL_LOOP_BUFFER_SIZE > 0) || \
- XCHAL_DCACHE_IS_COHERENT || \
- XCHAL_HAVE_ICACHE_DYN_WAYS || \
- XCHAL_HAVE_DCACHE_DYN_WAYS) && \
- (XCHAL_HW_MIN_VERSION >= XTENSA_HWVERSION_RE_2012_0))
-
-
-/*----------------------------------------------------------------------
- INTERNAL I/D RAM/ROMs and XLMI
- ----------------------------------------------------------------------*/
-
-#define XCHAL_NUM_INSTROM 0 /* number of core instr. ROMs */
-#define XCHAL_NUM_INSTRAM 1 /* number of core instr. RAMs */
-#define XCHAL_NUM_DATAROM 0 /* number of core data ROMs */
-#define XCHAL_NUM_DATARAM 1 /* number of core data RAMs */
-#define XCHAL_NUM_URAM 0 /* number of core unified RAMs*/
-#define XCHAL_NUM_XLMI 0 /* number of core XLMI ports */
-
-/* Instruction RAM 0: */
-#define XCHAL_INSTRAM0_VADDR 0xff2c0000 /* virtual address */
-#define XCHAL_INSTRAM0_PADDR 0xff2c0000 /* physical address */
-#define XCHAL_INSTRAM0_SIZE 0x14000 /* size in bytes */
-#define XCHAL_INSTRAM0_ECC_PARITY 0 /* ECC/parity type, 0=none */
-
-/* Data RAM 0: */
-#define XCHAL_DATARAM0_VADDR 0xff300000 /* virtual address */
-#define XCHAL_DATARAM0_PADDR 0xff300000 /* physical address */
-#define XCHAL_DATARAM0_SIZE 0x28000 /* size in bytes */
-#define XCHAL_DATARAM0_ECC_PARITY 0 /* ECC/parity type, 0=none */
-#define XCHAL_DATARAM0_BANKS 1 /* number of banks */
-
-
-#define XCHAL_HAVE_IMEM_LOADSTORE 1 /* can load/store to IROM/IRAM*/
-
-
-/*----------------------------------------------------------------------
- INTERRUPTS and TIMERS
- ----------------------------------------------------------------------*/
-
-#define XCHAL_HAVE_INTERRUPTS 1 /* interrupt option */
-#define XCHAL_HAVE_HIGHPRI_INTERRUPTS 1 /* med/high-pri. interrupts */
-#define XCHAL_HAVE_NMI 1 /* non-maskable interrupt */
-#define XCHAL_HAVE_CCOUNT 1 /* CCOUNT reg. (timer option) */
-#define XCHAL_NUM_TIMERS 3 /* number of CCOMPAREn regs */
-#define XCHAL_NUM_INTERRUPTS 22 /* number of interrupts */
-#define XCHAL_NUM_INTERRUPTS_LOG2 5 /* ceil(log2(NUM_INTERRUPTS)) */
-#define XCHAL_NUM_EXTINTERRUPTS 12 /* num of external interrupts */
-#define XCHAL_NUM_INTLEVELS 6 /* number of interrupt levels
- (not including level zero) */
-#define XCHAL_EXCM_LEVEL 5 /* level masked by PS.EXCM */
- /* (always 1 in XEA1; levels 2 .. EXCM_LEVEL are "medium priority") */
-
-/* Masks of interrupts at each interrupt level: */
-#define XCHAL_INTLEVEL1_MASK 0x0000000F
-#define XCHAL_INTLEVEL2_MASK 0x00000070
-#define XCHAL_INTLEVEL3_MASK 0x00000380
-#define XCHAL_INTLEVEL4_MASK 0x00200c00
-#define XCHAL_INTLEVEL5_MASK 0x000ff000
-#define XCHAL_INTLEVEL6_MASK 0x00000000
-#define XCHAL_INTLEVEL7_MASK 0x00100000
-
-/* Masks of interrupts at each range 1..n of interrupt levels: */
-#define XCHAL_INTLEVEL1_ANDBELOW_MASK 0x0000000F
-#define XCHAL_INTLEVEL2_ANDBELOW_MASK 0x0000007F
-#define XCHAL_INTLEVEL3_ANDBELOW_MASK 0x000003FF
-#define XCHAL_INTLEVEL4_ANDBELOW_MASK 0x00200FFF
-#define XCHAL_INTLEVEL5_ANDBELOW_MASK 0x002FFFFF
-#define XCHAL_INTLEVEL6_ANDBELOW_MASK 0x002FFFFF
-#define XCHAL_INTLEVEL7_ANDBELOW_MASK 0x003FFFFF
-
-/* Level of each interrupt: */
-#define XCHAL_INT0_LEVEL 1
-#define XCHAL_INT1_LEVEL 1
-#define XCHAL_INT2_LEVEL 1
-#define XCHAL_INT3_LEVEL 1
-
-#define XCHAL_INT4_LEVEL 2
-#define XCHAL_INT5_LEVEL 2
-#define XCHAL_INT6_LEVEL 2
-#define XCHAL_INT7_LEVEL 3
-
-#define XCHAL_INT8_LEVEL 3
-#define XCHAL_INT9_LEVEL 3
-#define XCHAL_INT10_LEVEL 4
-#define XCHAL_INT11_LEVEL 4
-
-#define XCHAL_INT12_LEVEL 5
-#define XCHAL_INT13_LEVEL 5
-#define XCHAL_INT14_LEVEL 5
-#define XCHAL_INT15_LEVEL 5
-
-#define XCHAL_INT16_LEVEL 5
-#define XCHAL_INT17_LEVEL 5
-#define XCHAL_INT18_LEVEL 5
-#define XCHAL_INT19_LEVEL 5
-
-#define XCHAL_INT20_LEVEL 7
-#define XCHAL_INT21_LEVEL 4
-
-#define XCHAL_DEBUGLEVEL 6 /* debug interrupt level */
-#define XCHAL_HAVE_DEBUG_EXTERN_INT 1 /* OCD external db interrupt */
-#define XCHAL_NMILEVEL 7 /* NMI "level" (for use with
- EXCSAVE/EPS/EPC_n, RFI n) */
-
-/* Type of each interrupt: */
-#define XCHAL_INT0_TYPE XTHAL_INTTYPE_SOFTWARE
-#define XCHAL_INT1_TYPE XTHAL_INTTYPE_TIMER
-#define XCHAL_INT2_TYPE XTHAL_INTTYPE_SOFTWARE
-#define XCHAL_INT3_TYPE XTHAL_INTTYPE_SOFTWARE
-#define XCHAL_INT4_TYPE XTHAL_INTTYPE_EXTERN_LEVEL
-#define XCHAL_INT5_TYPE XTHAL_INTTYPE_TIMER
-#define XCHAL_INT6_TYPE XTHAL_INTTYPE_SOFTWARE
-#define XCHAL_INT7_TYPE XTHAL_INTTYPE_TIMER
-#define XCHAL_INT8_TYPE XTHAL_INTTYPE_SOFTWARE
-#define XCHAL_INT9_TYPE XTHAL_INTTYPE_SOFTWARE
-#define XCHAL_INT10_TYPE XTHAL_INTTYPE_EXTERN_LEVEL
-#define XCHAL_INT11_TYPE XTHAL_INTTYPE_EXTERN_LEVEL
-#define XCHAL_INT12_TYPE XTHAL_INTTYPE_SOFTWARE
-#define XCHAL_INT13_TYPE XTHAL_INTTYPE_EXTERN_LEVEL
-#define XCHAL_INT14_TYPE XTHAL_INTTYPE_EXTERN_LEVEL
-#define XCHAL_INT15_TYPE XTHAL_INTTYPE_EXTERN_LEVEL
-#define XCHAL_INT16_TYPE XTHAL_INTTYPE_EXTERN_LEVEL
-#define XCHAL_INT17_TYPE XTHAL_INTTYPE_EXTERN_LEVEL
-#define XCHAL_INT18_TYPE XTHAL_INTTYPE_EXTERN_LEVEL
-#define XCHAL_INT19_TYPE XTHAL_INTTYPE_EXTERN_LEVEL
-#define XCHAL_INT20_TYPE XTHAL_INTTYPE_NMI
-#define XCHAL_INT21_TYPE XTHAL_INTTYPE_EXTERN_LEVEL
-
-/* Masks of interrupts for each type of interrupt: */
-#define XCHAL_INTTYPE_MASK_UNCONFIGURED 0xFFC00000
-#define XCHAL_INTTYPE_MASK_SOFTWARE 0x0000134d
-#define XCHAL_INTTYPE_MASK_EXTERN_EDGE 0x00000000
-#define XCHAL_INTTYPE_MASK_EXTERN_LEVEL 0x002fec10
-#define XCHAL_INTTYPE_MASK_TIMER 0x000000a2
-#define XCHAL_INTTYPE_MASK_NMI 0x00100000
-#define XCHAL_INTTYPE_MASK_WRITE_ERROR 0x00000000
-#define XCHAL_INTTYPE_MASK_PROFILING 0x00000000
-
-/* Interrupt numbers assigned to specific interrupt sources: */
-#define XCHAL_TIMER0_INTERRUPT 1 /* CCOMPARE0 */
-#define XCHAL_TIMER1_INTERRUPT 5 /* CCOMPARE1 */
-#define XCHAL_TIMER2_INTERRUPT 7 /* CCOMPARE2 */
-#define XCHAL_TIMER3_INTERRUPT XTHAL_TIMER_UNCONFIGURED
-#define XCHAL_NMI_INTERRUPT 20 /* non-maskable interrupt */
-
-/* Interrupt numbers for levels at which only one interrupt is configured: */
-//#define XCHAL_INTLEVEL2_NUM 8
-//#define XCHAL_INTLEVEL4_NUM 12
-//#define XCHAL_INTLEVEL5_NUM 13
-#define XCHAL_INTLEVEL7_NUM 20
-/* (There are many interrupts each at level(s) 1, 3.) */
-
-
-/*
- * External interrupt mapping.
- * These macros describe how Xtensa processor interrupt numbers
- * (as numbered internally, eg. in INTERRUPT and INTENABLE registers)
- * map to external BInterrupt<n> pins, for those interrupts
- * configured as external (level-triggered, edge-triggered, or NMI).
- * See the Xtensa processor databook for more details.
- */
-
-/* Core interrupt numbers mapped to each EXTERNAL BInterrupt pin number: */
-#define XCHAL_EXTINT0_NUM 0 /* (intlevel 1) */
-#define XCHAL_EXTINT1_NUM 1 /* (intlevel 1) */
-#define XCHAL_EXTINT2_NUM 2 /* (intlevel 1) */
-#define XCHAL_EXTINT3_NUM 3 /* (intlevel 1) */
-#define XCHAL_EXTINT4_NUM 4 /* (intlevel 1) */
-#define XCHAL_EXTINT5_NUM 5 /* (intlevel 1) */
-#define XCHAL_EXTINT6_NUM 8 /* (intlevel 2) */
-#define XCHAL_EXTINT7_NUM 9 /* (intlevel 3) */
-#define XCHAL_EXTINT8_NUM 12 /* (intlevel 4) */
-#define XCHAL_EXTINT9_NUM 14 /* (intlevel 7) */
-#define XCHAL_EXTINT10_NUM 15 /* (intlevel 1) */
-#define XCHAL_EXTINT11_NUM 16 /* (intlevel 1) */
-#define XCHAL_EXTINT12_NUM 17 /* (intlevel 1) */
-#define XCHAL_EXTINT13_NUM 18 /* (intlevel 1) */
-#define XCHAL_EXTINT14_NUM 19 /* (intlevel 1) */
-#define XCHAL_EXTINT15_NUM 20 /* (intlevel 1) */
-#define XCHAL_EXTINT16_NUM 21 /* (intlevel 3) */
-/* EXTERNAL BInterrupt pin numbers mapped to each core interrupt number: */
-#define XCHAL_INT0_EXTNUM 0 /* (intlevel 1) */
-#define XCHAL_INT1_EXTNUM 1 /* (intlevel 1) */
-#define XCHAL_INT2_EXTNUM 2 /* (intlevel 1) */
-#define XCHAL_INT3_EXTNUM 3 /* (intlevel 1) */
-#define XCHAL_INT4_EXTNUM 4 /* (intlevel 1) */
-#define XCHAL_INT5_EXTNUM 5 /* (intlevel 1) */
-#define XCHAL_INT8_EXTNUM 6 /* (intlevel 2) */
-#define XCHAL_INT9_EXTNUM 7 /* (intlevel 3) */
-#define XCHAL_INT12_EXTNUM 8 /* (intlevel 4) */
-#define XCHAL_INT14_EXTNUM 9 /* (intlevel 7) */
-#define XCHAL_INT15_EXTNUM 10 /* (intlevel 1) */
-#define XCHAL_INT16_EXTNUM 11 /* (intlevel 1) */
-#define XCHAL_INT17_EXTNUM 12 /* (intlevel 1) */
-#define XCHAL_INT18_EXTNUM 13 /* (intlevel 1) */
-#define XCHAL_INT19_EXTNUM 14 /* (intlevel 1) */
-#define XCHAL_INT20_EXTNUM 15 /* (intlevel 1) */
-#define XCHAL_INT21_EXTNUM 16 /* (intlevel 3) */
-
-
-/*----------------------------------------------------------------------
- EXCEPTIONS and VECTORS
- ----------------------------------------------------------------------*/
-
-#define XCHAL_XEA_VERSION 2 /* Xtensa Exception Architecture
- number: 1 == XEA1 (old)
- 2 == XEA2 (new)
- 0 == XEAX (extern) or TX */
-#define XCHAL_HAVE_XEA1 0 /* Exception Architecture 1 */
-#define XCHAL_HAVE_XEA2 1 /* Exception Architecture 2 */
-#define XCHAL_HAVE_XEAX 0 /* External Exception Arch. */
-#define XCHAL_HAVE_EXCEPTIONS 1 /* exception option */
-#define XCHAL_HAVE_HALT 0 /* halt architecture option */
-#define XCHAL_HAVE_BOOTLOADER 0 /* boot loader (for TX) */
-#define XCHAL_HAVE_MEM_ECC_PARITY 0 /* local memory ECC/parity */
-#define XCHAL_HAVE_VECTOR_SELECT 1 /* relocatable vectors */
-#define XCHAL_HAVE_VECBASE 1 /* relocatable vectors */
-#define XCHAL_VECBASE_RESET_VADDR 0xff2c0400 /* VECBASE reset value */
-#define XCHAL_VECBASE_RESET_PADDR 0xff2c0400
-#define XCHAL_RESET_VECBASE_OVERLAP 0
-
-#define XCHAL_RESET_VECTOR0_VADDR 0xff2c0000
-#define XCHAL_RESET_VECTOR0_PADDR 0xff2c0000
-#define XCHAL_RESET_VECTOR1_VADDR 0xff2c0000
-#define XCHAL_RESET_VECTOR1_PADDR 0xff2c0000
-#define XCHAL_RESET_VECTOR_VADDR 0xff2c0000
-#define XCHAL_RESET_VECTOR_PADDR 0xff2c0000
-#define XCHAL_USER_VECOFS 0x0000025c
-#define XCHAL_USER_VECTOR_VADDR 0xff2c065c
-#define XCHAL_USER_VECTOR_PADDR 0xff2c065c
-#define XCHAL_KERNEL_VECOFS 0x0000023c
-#define XCHAL_KERNEL_VECTOR_VADDR 0xff2c063c
-#define XCHAL_KERNEL_VECTOR_PADDR 0xff2c063c
-#define XCHAL_DOUBLEEXC_VECOFS 0x0000027c
-#define XCHAL_DOUBLEEXC_VECTOR_VADDR 0xff2c067c
-#define XCHAL_DOUBLEEXC_VECTOR_PADDR 0xff2c067c
-#define XCHAL_WINDOW_OF4_VECOFS 0x00000000
-#define XCHAL_WINDOW_UF4_VECOFS 0x00000040
-#define XCHAL_WINDOW_OF8_VECOFS 0x00000080
-#define XCHAL_WINDOW_UF8_VECOFS 0x000000C0
-#define XCHAL_WINDOW_OF12_VECOFS 0x00000100
-#define XCHAL_WINDOW_UF12_VECOFS 0x00000140
-#define XCHAL_WINDOW_VECTORS_VADDR 0xff2c0400
-#define XCHAL_WINDOW_VECTORS_PADDR 0xff2c0400
-#define XCHAL_INTLEVEL2_VECOFS 0x0000017c
-#define XCHAL_INTLEVEL2_VECTOR_VADDR 0xff2c057c
-#define XCHAL_INTLEVEL2_VECTOR_PADDR 0xff2c057c
-#define XCHAL_INTLEVEL3_VECOFS 0x0000019c
-#define XCHAL_INTLEVEL3_VECTOR_VADDR 0xff2c059c
-#define XCHAL_INTLEVEL3_VECTOR_PADDR 0xff2c059c
-#define XCHAL_INTLEVEL4_VECOFS 0x000001bc
-#define XCHAL_INTLEVEL4_VECTOR_VADDR 0xff2c05bc
-#define XCHAL_INTLEVEL4_VECTOR_PADDR 0xff2c05bc
-#define XCHAL_INTLEVEL5_VECOFS 0x000001dc
-#define XCHAL_INTLEVEL5_VECTOR_VADDR 0xff2c05dc
-#define XCHAL_INTLEVEL5_VECTOR_PADDR 0xff2c05dc
-#define XCHAL_INTLEVEL6_VECOFS 0x000001fc
-#define XCHAL_INTLEVEL6_VECTOR_VADDR 0xff2c05fc
-#define XCHAL_INTLEVEL6_VECTOR_PADDR 0xff2c05fc
-#define XCHAL_DEBUG_VECOFS XCHAL_INTLEVEL6_VECOFS
-#define XCHAL_DEBUG_VECTOR_VADDR XCHAL_INTLEVEL6_VECTOR_VADDR
-#define XCHAL_DEBUG_VECTOR_PADDR XCHAL_INTLEVEL6_VECTOR_PADDR
-#define XCHAL_NMI_VECOFS 0x0000021c
-#define XCHAL_NMI_VECTOR_VADDR 0xff2c061c
-#define XCHAL_NMI_VECTOR_PADDR 0xff2c061c
-#define XCHAL_INTLEVEL7_VECOFS XCHAL_NMI_VECOFS
-#define XCHAL_INTLEVEL7_VECTOR_VADDR XCHAL_NMI_VECTOR_VADDR
-#define XCHAL_INTLEVEL7_VECTOR_PADDR XCHAL_NMI_VECTOR_PADDR
-
-
-/*----------------------------------------------------------------------
- DEBUG MODULE
- ----------------------------------------------------------------------*/
-
-/* Misc */
-#define XCHAL_HAVE_DEBUG_ERI 0 /* ERI to debug module */
-#define XCHAL_HAVE_DEBUG_APB 0 /* APB to debug module */
-#define XCHAL_HAVE_DEBUG_JTAG 1 /* JTAG to debug module */
-
-/* On-Chip Debug (OCD) */
-#define XCHAL_HAVE_OCD 1 /* OnChipDebug option */
-#define XCHAL_NUM_IBREAK 2 /* number of IBREAKn regs */
-#define XCHAL_NUM_DBREAK 2 /* number of DBREAKn regs */
-#define XCHAL_HAVE_OCD_DIR_ARRAY 1 /* faster OCD option (to LX4) */
-#define XCHAL_HAVE_OCD_LS32DDR 1 /* L32DDR/S32DDR (faster OCD) */
-
-/* TRAX (in core) */
-#define XCHAL_HAVE_TRAX 0 /* TRAX in debug module */
-#define XCHAL_TRAX_MEM_SIZE 0 /* TRAX memory size in bytes */
-#define XCHAL_TRAX_MEM_SHAREABLE 0 /* start/end regs; ready sig. */
-#define XCHAL_TRAX_ATB_WIDTH 0 /* ATB width (bits), 0=no ATB */
-#define XCHAL_TRAX_TIME_WIDTH 0 /* timestamp bitwidth, 0=none */
-
-/* Perf counters */
-#define XCHAL_NUM_PERF_COUNTERS 0 /* performance counters */
-
-
-/*----------------------------------------------------------------------
- MMU
- ----------------------------------------------------------------------*/
-
-/* See core-matmap.h header file for more details. */
-
-#define XCHAL_HAVE_TLBS 1 /* inverse of HAVE_CACHEATTR */
-#define XCHAL_HAVE_SPANNING_WAY 1 /* one way maps I+D 4GB vaddr */
-#define XCHAL_SPANNING_WAY 0 /* TLB spanning way number */
-#define XCHAL_HAVE_IDENTITY_MAP 0 /* vaddr == paddr always */
-#define XCHAL_HAVE_CACHEATTR 0 /* CACHEATTR register present */
-#define XCHAL_HAVE_MIMIC_CACHEATTR 0 /* region protection */
-#define XCHAL_HAVE_XLT_CACHEATTR 1 /* region prot. w/translation */
-#define XCHAL_HAVE_PTP_MMU 0 /* full MMU (with page table
- [autorefill] and protection)
- usable for an MMU-based OS */
-/* If none of the above last 4 are set, it's a custom TLB configuration. */
-
-#define XCHAL_MMU_ASID_BITS 0 /* number of bits in ASIDs */
-#define XCHAL_MMU_RINGS 1 /* number of rings (1..4) */
-#define XCHAL_MMU_RING_BITS 0 /* num of bits in RING field */
-
-#endif /* !XTENSA_HAL_NON_PRIVILEGED_ONLY */
-
-
-#endif /* _XTENSA_CORE_CONFIGURATION_H */
-
diff --git a/src/platform/baytrail/include/arch/xtensa/config/core-isa.h b/src/platform/baytrail/include/arch/xtensa/config/core-isa.h
deleted file mode 100644
index 70c35bf..0000000
--- a/src/platform/baytrail/include/arch/xtensa/config/core-isa.h
+++ /dev/null
@@ -1,9 +0,0 @@
-#include <config.h>
-
-#ifdef CONFIG_BAYTRAIL
-#include <xtensa/config/core-isa-byt.h>
-#elif CONFIG_CHERRYTRAIL
-#include <xtensa/config/core-isa-cht.h>
-#else
-#error "No ISA configuration selected"
-#endif
diff --git a/src/platform/baytrail/include/arch/xtensa/config/core-matmap.h b/src/platform/baytrail/include/arch/xtensa/config/core-matmap.h
deleted file mode 100644
index 5c6fffe..0000000
--- a/src/platform/baytrail/include/arch/xtensa/config/core-matmap.h
+++ /dev/null
@@ -1,314 +0,0 @@
-/*
- * xtensa/config/core-matmap.h -- Memory access and translation mapping
- * parameters (CHAL) of the Xtensa processor core configuration.
- *
- * If you are using Xtensa Tools, see <xtensa/config/core.h> (which includes
- * this file) for more details.
- *
- * In the Xtensa processor products released to date, all parameters
- * defined in this file are derivable (at least in theory) from
- * information contained in the core-isa.h header file.
- * In particular, the following core configuration parameters are relevant:
- * XCHAL_HAVE_CACHEATTR
- * XCHAL_HAVE_MIMIC_CACHEATTR
- * XCHAL_HAVE_XLT_CACHEATTR
- * XCHAL_HAVE_PTP_MMU
- * XCHAL_ITLB_ARF_ENTRIES_LOG2
- * XCHAL_DTLB_ARF_ENTRIES_LOG2
- * XCHAL_DCACHE_IS_WRITEBACK
- * XCHAL_ICACHE_SIZE (presence of I-cache)
- * XCHAL_DCACHE_SIZE (presence of D-cache)
- * XCHAL_HW_VERSION_MAJOR
- * XCHAL_HW_VERSION_MINOR
- */
-
-/* Customer ID=4313; Build=0x5483b; Copyright (c) 1999-2015 Tensilica Inc.
-
- Permission is hereby granted, free of charge, to any person obtaining
- a copy of this software and associated documentation files (the
- "Software"), to deal in the Software without restriction, including
- without limitation the rights to use, copy, modify, merge, publish,
- distribute, sublicense, and/or sell copies of the Software, and to
- permit persons to whom the Software is furnished to do so, subject to
- the following conditions:
-
- The above copyright notice and this permission notice shall be included
- in all copies or substantial portions of the Software.
-
- THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
- EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
- MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
- IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY
- CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
- TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
- SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. */
-
-
-#ifndef XTENSA_CONFIG_CORE_MATMAP_H
-#define XTENSA_CONFIG_CORE_MATMAP_H
-
-
-/*----------------------------------------------------------------------
- CACHE (MEMORY ACCESS) ATTRIBUTES
- ----------------------------------------------------------------------*/
-
-
-/* Cache Attribute encodings -- lists of access modes for each cache attribute: */
-#define XCHAL_FCA_LIST XTHAL_FAM_EXCEPTION XCHAL_SEP \
- XTHAL_FAM_CACHED XCHAL_SEP \
- XTHAL_FAM_BYPASS XCHAL_SEP \
- XTHAL_FAM_CACHED XCHAL_SEP \
- XTHAL_FAM_CACHED XCHAL_SEP \
- XTHAL_FAM_CACHED XCHAL_SEP \
- XTHAL_FAM_BYPASS XCHAL_SEP \
- XTHAL_FAM_EXCEPTION XCHAL_SEP \
- XTHAL_FAM_EXCEPTION XCHAL_SEP \
- XTHAL_FAM_EXCEPTION XCHAL_SEP \
- XTHAL_FAM_EXCEPTION XCHAL_SEP \
- XTHAL_FAM_EXCEPTION XCHAL_SEP \
- XTHAL_FAM_EXCEPTION XCHAL_SEP \
- XTHAL_FAM_EXCEPTION XCHAL_SEP \
- XTHAL_FAM_EXCEPTION XCHAL_SEP \
- XTHAL_FAM_EXCEPTION
-#define XCHAL_LCA_LIST XTHAL_LAM_CACHED_NOALLOC XCHAL_SEP \
- XTHAL_LAM_CACHED XCHAL_SEP \
- XTHAL_LAM_BYPASSG XCHAL_SEP \
- XTHAL_LAM_EXCEPTION XCHAL_SEP \
- XTHAL_LAM_CACHED XCHAL_SEP \
- XTHAL_LAM_CACHED XCHAL_SEP \
- XTHAL_LAM_BYPASSG XCHAL_SEP \
- XTHAL_LAM_EXCEPTION XCHAL_SEP \
- XTHAL_LAM_EXCEPTION XCHAL_SEP \
- XTHAL_LAM_EXCEPTION XCHAL_SEP \
- XTHAL_LAM_EXCEPTION XCHAL_SEP \
- XTHAL_LAM_EXCEPTION XCHAL_SEP \
- XTHAL_LAM_EXCEPTION XCHAL_SEP \
- XTHAL_LAM_EXCEPTION XCHAL_SEP \
- XTHAL_LAM_ISOLATE XCHAL_SEP \
- XTHAL_LAM_EXCEPTION
-#define XCHAL_SCA_LIST XTHAL_SAM_WRITETHRU XCHAL_SEP \
- XTHAL_SAM_WRITETHRU XCHAL_SEP \
- XTHAL_SAM_BYPASS XCHAL_SEP \
- XTHAL_SAM_EXCEPTION XCHAL_SEP \
- XTHAL_SAM_WRITEBACK XCHAL_SEP \
- XTHAL_SAM_WRITEBACK_NOALLOC XCHAL_SEP \
- XTHAL_SAM_BYPASS XCHAL_SEP \
- XTHAL_SAM_EXCEPTION XCHAL_SEP \
- XTHAL_SAM_EXCEPTION XCHAL_SEP \
- XTHAL_SAM_EXCEPTION XCHAL_SEP \
- XTHAL_SAM_EXCEPTION XCHAL_SEP \
- XTHAL_SAM_EXCEPTION XCHAL_SEP \
- XTHAL_SAM_EXCEPTION XCHAL_SEP \
- XTHAL_SAM_EXCEPTION XCHAL_SEP \
- XTHAL_SAM_ISOLATE XCHAL_SEP \
- XTHAL_SAM_EXCEPTION
-
-
-/*
- * Specific encoded cache attribute values of general interest.
- * If a specific cache mode is not available, the closest available
- * one is returned instead (eg. writethru instead of writeback,
- * bypass instead of writethru).
- */
-#define XCHAL_CA_BYPASS 2 /* cache disabled (bypassed) mode */
-#define XCHAL_CA_BYPASSBUF 6 /* cache disabled (bypassed) bufferable mode */
-#define XCHAL_CA_WRITETHRU 1 /* cache enabled (write-through) mode */
-#define XCHAL_CA_WRITEBACK 4 /* cache enabled (write-back) mode */
-#define XCHAL_HAVE_CA_WRITEBACK_NOALLOC 1 /* write-back no-allocate availability */
-#define XCHAL_CA_WRITEBACK_NOALLOC 5 /* cache enabled (write-back no-allocate) mode */
-#define XCHAL_CA_ILLEGAL 15 /* no access allowed (all cause exceptions) mode */
-#define XCHAL_CA_ISOLATE 14 /* cache isolate (accesses go to cache not memory) mode */
-
-
-/*----------------------------------------------------------------------
- MMU
- ----------------------------------------------------------------------*/
-
-/*
- * General notes on MMU parameters.
- *
- * Terminology:
- * ASID = address-space ID (acts as an "extension" of virtual addresses)
- * VPN = virtual page number
- * PPN = physical page number
- * CA = encoded cache attribute (access modes)
- * TLB = translation look-aside buffer (term is stretched somewhat here)
- * I = instruction (fetch accesses)
- * D = data (load and store accesses)
- * way = each TLB (ITLB and DTLB) consists of a number of "ways"
- * that simultaneously match the virtual address of an access;
- * a TLB successfully translates a virtual address if exactly
- * one way matches the vaddr; if none match, it is a miss;
- * if multiple match, one gets a "multihit" exception;
- * each way can be independently configured in terms of number of
- * entries, page sizes, which fields are writable or constant, etc.
- * set = group of contiguous ways with exactly identical parameters
- * ARF = auto-refill; hardware services a 1st-level miss by loading a PTE
- * from the page table and storing it in one of the auto-refill ways;
- * if this PTE load also misses, a miss exception is posted for s/w.
- * min-wired = a "min-wired" way can be used to map a single (minimum-sized)
- * page arbitrarily under program control; it has a single entry,
- * is non-auto-refill (some other way(s) must be auto-refill),
- * all its fields (VPN, PPN, ASID, CA) are all writable, and it
- * supports the XCHAL_MMU_MIN_PTE_PAGE_SIZE page size (a current
- * restriction is that this be the only page size it supports).
- *
- * TLB way entries are virtually indexed.
- * TLB ways that support multiple page sizes:
- * - must have all writable VPN and PPN fields;
- * - can only use one page size at any given time (eg. setup at startup),
- * selected by the respective ITLBCFG or DTLBCFG special register,
- * whose bits n*4+3 .. n*4 index the list of page sizes for way n
- * (XCHAL_xTLB_SETm_PAGESZ_LOG2_LIST for set m corresponding to way n);
- * this list may be sparse for auto-refill ways because auto-refill
- * ways have independent lists of supported page sizes sharing a
- * common encoding with PTE entries; the encoding is the index into
- * this list; unsupported sizes for a given way are zero in the list;
- * selecting unsupported sizes results in undefined hardware behaviour;
- * - is only possible for ways 0 thru 7 (due to ITLBCFG/DTLBCFG definition).
- */
-
-#define XCHAL_MMU_ASID_INVALID 0 /* ASID value indicating invalid address space */
-#define XCHAL_MMU_ASID_KERNEL 0 /* ASID value indicating kernel (ring 0) address space */
-#define XCHAL_MMU_SR_BITS 0 /* number of size-restriction bits supported */
-#define XCHAL_MMU_CA_BITS 4 /* number of bits needed to hold cache attribute encoding */
-#define XCHAL_MMU_MAX_PTE_PAGE_SIZE 29 /* max page size in a PTE structure (log2) */
-#define XCHAL_MMU_MIN_PTE_PAGE_SIZE 29 /* min page size in a PTE structure (log2) */
-
-
-/*** Instruction TLB: ***/
-
-#define XCHAL_ITLB_WAY_BITS 0 /* number of bits holding the ways */
-#define XCHAL_ITLB_WAYS 1 /* number of ways (n-way set-associative TLB) */
-#define XCHAL_ITLB_ARF_WAYS 0 /* number of auto-refill ways */
-#define XCHAL_ITLB_SETS 1 /* number of sets (groups of ways with identical settings) */
-
-/* Way set to which each way belongs: */
-#define XCHAL_ITLB_WAY0_SET 0
-
-/* Ways sets that are used by hardware auto-refill (ARF): */
-#define XCHAL_ITLB_ARF_SETS 0 /* number of auto-refill sets */
-
-/* Way sets that are "min-wired" (see terminology comment above): */
-#define XCHAL_ITLB_MINWIRED_SETS 0 /* number of "min-wired" sets */
-
-
-/* ITLB way set 0 (group of ways 0 thru 0): */
-#define XCHAL_ITLB_SET0_WAY 0 /* index of first way in this way set */
-#define XCHAL_ITLB_SET0_WAYS 1 /* number of (contiguous) ways in this way set */
-#define XCHAL_ITLB_SET0_ENTRIES_LOG2 3 /* log2(number of entries in this way) */
-#define XCHAL_ITLB_SET0_ENTRIES 8 /* number of entries in this way (always a power of 2) */
-#define XCHAL_ITLB_SET0_ARF 0 /* 1=autorefill by h/w, 0=non-autorefill (wired/constant/static) */
-#define XCHAL_ITLB_SET0_PAGESIZES 1 /* number of supported page sizes in this way */
-#define XCHAL_ITLB_SET0_PAGESZ_BITS 0 /* number of bits to encode the page size */
-#define XCHAL_ITLB_SET0_PAGESZ_LOG2_MIN 29 /* log2(minimum supported page size) */
-#define XCHAL_ITLB_SET0_PAGESZ_LOG2_MAX 29 /* log2(maximum supported page size) */
-#define XCHAL_ITLB_SET0_PAGESZ_LOG2_LIST 29 /* list of log2(page size)s, separated by XCHAL_SEP;
- 2^PAGESZ_BITS entries in list, unsupported entries are zero */
-#define XCHAL_ITLB_SET0_ASID_CONSTMASK 0 /* constant ASID bits; 0 if all writable */
-#define XCHAL_ITLB_SET0_VPN_CONSTMASK 0x00000000 /* constant VPN bits, not including entry index bits; 0 if all writable */
-#define XCHAL_ITLB_SET0_PPN_CONSTMASK 0xE0000000 /* constant PPN bits, including entry index bits; 0 if all writable */
-#define XCHAL_ITLB_SET0_CA_CONSTMASK 0 /* constant CA bits; 0 if all writable */
-#define XCHAL_ITLB_SET0_ASID_RESET 0 /* 1 if ASID reset values defined (and all writable); 0 otherwise */
-#define XCHAL_ITLB_SET0_VPN_RESET 0 /* 1 if VPN reset values defined (and all writable); 0 otherwise */
-#define XCHAL_ITLB_SET0_PPN_RESET 0 /* 1 if PPN reset values defined (and all writable); 0 otherwise */
-#define XCHAL_ITLB_SET0_CA_RESET 1 /* 1 if CA reset values defined (and all writable); 0 otherwise */
-/* Constant VPN values for each entry of ITLB way set 0 (because VPN_CONSTMASK is non-zero): */
-#define XCHAL_ITLB_SET0_E0_VPN_CONST 0x00000000
-#define XCHAL_ITLB_SET0_E1_VPN_CONST 0x20000000
-#define XCHAL_ITLB_SET0_E2_VPN_CONST 0x40000000
-#define XCHAL_ITLB_SET0_E3_VPN_CONST 0x60000000
-#define XCHAL_ITLB_SET0_E4_VPN_CONST 0x80000000
-#define XCHAL_ITLB_SET0_E5_VPN_CONST 0xA0000000
-#define XCHAL_ITLB_SET0_E6_VPN_CONST 0xC0000000
-#define XCHAL_ITLB_SET0_E7_VPN_CONST 0xE0000000
-/* Constant PPN values for each entry of ITLB way set 0 (because PPN_CONSTMASK is non-zero): */
-#define XCHAL_ITLB_SET0_E0_PPN_CONST 0x00000000
-#define XCHAL_ITLB_SET0_E1_PPN_CONST 0x20000000
-#define XCHAL_ITLB_SET0_E2_PPN_CONST 0x40000000
-#define XCHAL_ITLB_SET0_E3_PPN_CONST 0x60000000
-#define XCHAL_ITLB_SET0_E4_PPN_CONST 0x80000000
-#define XCHAL_ITLB_SET0_E5_PPN_CONST 0xA0000000
-#define XCHAL_ITLB_SET0_E6_PPN_CONST 0xC0000000
-#define XCHAL_ITLB_SET0_E7_PPN_CONST 0xE0000000
-/* Reset CA values for each entry of ITLB way set 0 (because SET0_CA_RESET is non-zero): */
-#define XCHAL_ITLB_SET0_E0_CA_RESET 0x02
-#define XCHAL_ITLB_SET0_E1_CA_RESET 0x02
-#define XCHAL_ITLB_SET0_E2_CA_RESET 0x02
-#define XCHAL_ITLB_SET0_E3_CA_RESET 0x02
-#define XCHAL_ITLB_SET0_E4_CA_RESET 0x02
-#define XCHAL_ITLB_SET0_E5_CA_RESET 0x02
-#define XCHAL_ITLB_SET0_E6_CA_RESET 0x02
-#define XCHAL_ITLB_SET0_E7_CA_RESET 0x02
-
-
-/*** Data TLB: ***/
-
-#define XCHAL_DTLB_WAY_BITS 0 /* number of bits holding the ways */
-#define XCHAL_DTLB_WAYS 1 /* number of ways (n-way set-associative TLB) */
-#define XCHAL_DTLB_ARF_WAYS 0 /* number of auto-refill ways */
-#define XCHAL_DTLB_SETS 1 /* number of sets (groups of ways with identical settings) */
-
-/* Way set to which each way belongs: */
-#define XCHAL_DTLB_WAY0_SET 0
-
-/* Ways sets that are used by hardware auto-refill (ARF): */
-#define XCHAL_DTLB_ARF_SETS 0 /* number of auto-refill sets */
-
-/* Way sets that are "min-wired" (see terminology comment above): */
-#define XCHAL_DTLB_MINWIRED_SETS 0 /* number of "min-wired" sets */
-
-
-/* DTLB way set 0 (group of ways 0 thru 0): */
-#define XCHAL_DTLB_SET0_WAY 0 /* index of first way in this way set */
-#define XCHAL_DTLB_SET0_WAYS 1 /* number of (contiguous) ways in this way set */
-#define XCHAL_DTLB_SET0_ENTRIES_LOG2 3 /* log2(number of entries in this way) */
-#define XCHAL_DTLB_SET0_ENTRIES 8 /* number of entries in this way (always a power of 2) */
-#define XCHAL_DTLB_SET0_ARF 0 /* 1=autorefill by h/w, 0=non-autorefill (wired/constant/static) */
-#define XCHAL_DTLB_SET0_PAGESIZES 1 /* number of supported page sizes in this way */
-#define XCHAL_DTLB_SET0_PAGESZ_BITS 0 /* number of bits to encode the page size */
-#define XCHAL_DTLB_SET0_PAGESZ_LOG2_MIN 29 /* log2(minimum supported page size) */
-#define XCHAL_DTLB_SET0_PAGESZ_LOG2_MAX 29 /* log2(maximum supported page size) */
-#define XCHAL_DTLB_SET0_PAGESZ_LOG2_LIST 29 /* list of log2(page size)s, separated by XCHAL_SEP;
- 2^PAGESZ_BITS entries in list, unsupported entries are zero */
-#define XCHAL_DTLB_SET0_ASID_CONSTMASK 0 /* constant ASID bits; 0 if all writable */
-#define XCHAL_DTLB_SET0_VPN_CONSTMASK 0x00000000 /* constant VPN bits, not including entry index bits; 0 if all writable */
-#define XCHAL_DTLB_SET0_PPN_CONSTMASK 0xE0000000 /* constant PPN bits, including entry index bits; 0 if all writable */
-#define XCHAL_DTLB_SET0_CA_CONSTMASK 0 /* constant CA bits; 0 if all writable */
-#define XCHAL_DTLB_SET0_ASID_RESET 0 /* 1 if ASID reset values defined (and all writable); 0 otherwise */
-#define XCHAL_DTLB_SET0_VPN_RESET 0 /* 1 if VPN reset values defined (and all writable); 0 otherwise */
-#define XCHAL_DTLB_SET0_PPN_RESET 0 /* 1 if PPN reset values defined (and all writable); 0 otherwise */
-#define XCHAL_DTLB_SET0_CA_RESET 1 /* 1 if CA reset values defined (and all writable); 0 otherwise */
-/* Constant VPN values for each entry of DTLB way set 0 (because VPN_CONSTMASK is non-zero): */
-#define XCHAL_DTLB_SET0_E0_VPN_CONST 0x00000000
-#define XCHAL_DTLB_SET0_E1_VPN_CONST 0x20000000
-#define XCHAL_DTLB_SET0_E2_VPN_CONST 0x40000000
-#define XCHAL_DTLB_SET0_E3_VPN_CONST 0x60000000
-#define XCHAL_DTLB_SET0_E4_VPN_CONST 0x80000000
-#define XCHAL_DTLB_SET0_E5_VPN_CONST 0xA0000000
-#define XCHAL_DTLB_SET0_E6_VPN_CONST 0xC0000000
-#define XCHAL_DTLB_SET0_E7_VPN_CONST 0xE0000000
-/* Constant PPN values for each entry of DTLB way set 0 (because PPN_CONSTMASK is non-zero): */
-#define XCHAL_DTLB_SET0_E0_PPN_CONST 0x00000000
-#define XCHAL_DTLB_SET0_E1_PPN_CONST 0x20000000
-#define XCHAL_DTLB_SET0_E2_PPN_CONST 0x40000000
-#define XCHAL_DTLB_SET0_E3_PPN_CONST 0x60000000
-#define XCHAL_DTLB_SET0_E4_PPN_CONST 0x80000000
-#define XCHAL_DTLB_SET0_E5_PPN_CONST 0xA0000000
-#define XCHAL_DTLB_SET0_E6_PPN_CONST 0xC0000000
-#define XCHAL_DTLB_SET0_E7_PPN_CONST 0xE0000000
-/* Reset CA values for each entry of DTLB way set 0 (because SET0_CA_RESET is non-zero): */
-#define XCHAL_DTLB_SET0_E0_CA_RESET 0x02
-#define XCHAL_DTLB_SET0_E1_CA_RESET 0x02
-#define XCHAL_DTLB_SET0_E2_CA_RESET 0x02
-#define XCHAL_DTLB_SET0_E3_CA_RESET 0x02
-#define XCHAL_DTLB_SET0_E4_CA_RESET 0x02
-#define XCHAL_DTLB_SET0_E5_CA_RESET 0x02
-#define XCHAL_DTLB_SET0_E6_CA_RESET 0x02
-#define XCHAL_DTLB_SET0_E7_CA_RESET 0x02
-
-
-
-
-#endif /*XTENSA_CONFIG_CORE_MATMAP_H*/
-
diff --git a/src/platform/baytrail/include/arch/xtensa/config/defs.h b/src/platform/baytrail/include/arch/xtensa/config/defs.h
deleted file mode 100644
index b695e59..0000000
--- a/src/platform/baytrail/include/arch/xtensa/config/defs.h
+++ /dev/null
@@ -1,38 +0,0 @@
-/* Definitions for Xtensa instructions, types, and protos. */
-
-/* Customer ID=4313; Build=0x5483b; Copyright (c) 2003-2004 Tensilica Inc.
-
- Permission is hereby granted, free of charge, to any person obtaining
- a copy of this software and associated documentation files (the
- "Software"), to deal in the Software without restriction, including
- without limitation the rights to use, copy, modify, merge, publish,
- distribute, sublicense, and/or sell copies of the Software, and to
- permit persons to whom the Software is furnished to do so, subject to
- the following conditions:
-
- The above copyright notice and this permission notice shall be included
- in all copies or substantial portions of the Software.
-
- THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
- EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
- MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
- IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY
- CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
- TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
- SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. */
-
-/* NOTE: This file exists only for backward compatibility with T1050
- and earlier Xtensa releases. It includes only a subset of the
- available header files. */
-
-#ifndef _XTENSA_BASE_HEADER
-#define _XTENSA_BASE_HEADER
-
-#ifdef __XTENSA__
-
-#include <xtensa/tie/xt_core.h>
-#include <xtensa/tie/xt_misc.h>
-#include <xtensa/tie/xt_booleans.h>
-
-#endif /* __XTENSA__ */
-#endif /* !_XTENSA_BASE_HEADER */
diff --git a/src/platform/baytrail/include/arch/xtensa/config/specreg.h b/src/platform/baytrail/include/arch/xtensa/config/specreg.h
deleted file mode 100644
index 89bfe16..0000000
--- a/src/platform/baytrail/include/arch/xtensa/config/specreg.h
+++ /dev/null
@@ -1,107 +0,0 @@
-/*
- * Xtensa Special Register symbolic names
- */
-
-/* $Id: //depot/rel/Eaglenest/Xtensa/SWConfig/hal/specreg.h.tpp#1 $ */
-
-/* Customer ID=4313; Build=0x5483b; Copyright (c) 1998-2002 Tensilica Inc.
-
- Permission is hereby granted, free of charge, to any person obtaining
- a copy of this software and associated documentation files (the
- "Software"), to deal in the Software without restriction, including
- without limitation the rights to use, copy, modify, merge, publish,
- distribute, sublicense, and/or sell copies of the Software, and to
- permit persons to whom the Software is furnished to do so, subject to
- the following conditions:
-
- The above copyright notice and this permission notice shall be included
- in all copies or substantial portions of the Software.
-
- THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
- EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
- MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
- IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY
- CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
- TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
- SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. */
-
-#ifndef XTENSA_SPECREG_H
-#define XTENSA_SPECREG_H
-
-/* Include these special register bitfield definitions, for historical reasons: */
-#include <xtensa/corebits.h>
-
-
-/* Special registers: */
-#define LBEG 0
-#define LEND 1
-#define LCOUNT 2
-#define SAR 3
-#define BR 4
-#define SCOMPARE1 12
-#define WINDOWBASE 72
-#define WINDOWSTART 73
-#define IBREAKENABLE 96
-#define ATOMCTL 99
-#define DDR 104
-#define IBREAKA_0 128
-#define IBREAKA_1 129
-#define DBREAKA_0 144
-#define DBREAKA_1 145
-#define DBREAKC_0 160
-#define DBREAKC_1 161
-#define EPC_1 177
-#define EPC_2 178
-#define EPC_3 179
-#define EPC_4 180
-#define EPC_5 181
-#define EPC_6 182
-#define EPC_7 183
-#define DEPC 192
-#define EPS_2 194
-#define EPS_3 195
-#define EPS_4 196
-#define EPS_5 197
-#define EPS_6 198
-#define EPS_7 199
-#define EXCSAVE_1 209
-#define EXCSAVE_2 210
-#define EXCSAVE_3 211
-#define EXCSAVE_4 212
-#define EXCSAVE_5 213
-#define EXCSAVE_6 214
-#define EXCSAVE_7 215
-#define CPENABLE 224
-#define INTERRUPT 226
-#define INTENABLE 228
-#define PS 230
-#define VECBASE 231
-#define EXCCAUSE 232
-#define DEBUGCAUSE 233
-#define CCOUNT 234
-#define PRID 235
-#define ICOUNT 236
-#define ICOUNTLEVEL 237
-#define EXCVADDR 238
-#define CCOMPARE_0 240
-#define CCOMPARE_1 241
-#define CCOMPARE_2 242
-#define MISC_REG_0 244
-#define MISC_REG_1 245
-
-/* Special cases (bases of special register series): */
-#define IBREAKA 128
-#define DBREAKA 144
-#define DBREAKC 160
-#define EPC 176
-#define EPS 192
-#define EXCSAVE 208
-#define CCOMPARE 240
-
-/* Special names for read-only and write-only interrupt registers: */
-#define INTREAD 226
-#define INTSET 226
-#define INTCLEAR 227
-
-#endif /* XTENSA_SPECREG_H */
-
diff --git a/src/platform/baytrail/include/arch/xtensa/config/system.h b/src/platform/baytrail/include/arch/xtensa/config/system.h
deleted file mode 100644
index 147346a..0000000
--- a/src/platform/baytrail/include/arch/xtensa/config/system.h
+++ /dev/null
@@ -1,272 +0,0 @@
-/*
- * xtensa/config/system.h -- HAL definitions that are dependent on SYSTEM configuration
- *
- * NOTE: The location and contents of this file are highly subject to change.
- *
- * Source for configuration-independent binaries (which link in a
- * configuration-specific HAL library) must NEVER include this file.
- * The HAL itself has historically included this file in some instances,
- * but this is not appropriate either, because the HAL is meant to be
- * core-specific but system independent.
- */
-
-/* Customer ID=4313; Build=0x5483b; Copyright (c) 2000-2010 Tensilica Inc.
-
- Permission is hereby granted, free of charge, to any person obtaining
- a copy of this software and associated documentation files (the
- "Software"), to deal in the Software without restriction, including
- without limitation the rights to use, copy, modify, merge, publish,
- distribute, sublicense, and/or sell copies of the Software, and to
- permit persons to whom the Software is furnished to do so, subject to
- the following conditions:
-
- The above copyright notice and this permission notice shall be included
- in all copies or substantial portions of the Software.
-
- THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
- EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
- MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
- IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY
- CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
- TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
- SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. */
-
-
-#ifndef XTENSA_CONFIG_SYSTEM_H
-#define XTENSA_CONFIG_SYSTEM_H
-
-/*#include <xtensa/hal.h>*/
-
-
-
-/*----------------------------------------------------------------------
- CONFIGURED SOFTWARE OPTIONS
- ----------------------------------------------------------------------*/
-
-#define XSHAL_USE_ABSOLUTE_LITERALS 0 /* (sw-only option, whether software uses absolute literals) */
-#define XSHAL_HAVE_TEXT_SECTION_LITERALS 1 /* Set if there is some memory that allows both code and literals. */
-
-#define XSHAL_ABI XTHAL_ABI_CALL0 /* (sw-only option, selected ABI) */
-/* The above maps to one of the following constants: */
-#define XTHAL_ABI_WINDOWED 0
-#define XTHAL_ABI_CALL0 1
-/* Alternatives: */
-/*#define XSHAL_WINDOWED_ABI 1*/ /* set if windowed ABI selected */
-/*#define XSHAL_CALL0_ABI 0*/ /* set if call0 ABI selected */
-
-#define XSHAL_CLIB XTHAL_CLIB_NEWLIB /* (sw-only option, selected C library) */
-/* The above maps to one of the following constants: */
-#define XTHAL_CLIB_NEWLIB 0
-#define XTHAL_CLIB_UCLIBC 1
-#define XTHAL_CLIB_XCLIB 2
-/* Alternatives: */
-/*#define XSHAL_NEWLIB 1*/ /* set if newlib C library selected */
-/*#define XSHAL_UCLIBC 0*/ /* set if uCLibC C library selected */
-/*#define XSHAL_XCLIB 0*/ /* set if Xtensa C library selected */
-
-#define XSHAL_USE_FLOATING_POINT 1
-
-#define XSHAL_FLOATING_POINT_ABI 0
-
-/*----------------------------------------------------------------------
- DEVICE ADDRESSES
- ----------------------------------------------------------------------*/
-
-/*
- * Strange place to find these, but the configuration GUI
- * allows moving these around to account for various core
- * configurations. Specific boards (and their BSP software)
- * will have specific meanings for these components.
- */
-
-/* I/O Block areas: */
-#define XSHAL_IOBLOCK_CACHED_VADDR 0x70000000
-#define XSHAL_IOBLOCK_CACHED_PADDR 0x70000000
-#define XSHAL_IOBLOCK_CACHED_SIZE 0x0E000000
-
-#define XSHAL_IOBLOCK_BYPASS_VADDR 0x90000000
-#define XSHAL_IOBLOCK_BYPASS_PADDR 0x90000000
-#define XSHAL_IOBLOCK_BYPASS_SIZE 0x0E000000
-
-/* System ROM: */
-#define XSHAL_ROM_VADDR 0x50000000
-#define XSHAL_ROM_PADDR 0x50000000
-#define XSHAL_ROM_SIZE 0x01000000
-/* Largest available area (free of vectors): */
-#define XSHAL_ROM_AVAIL_VADDR 0x50000300
-#define XSHAL_ROM_AVAIL_VSIZE 0x00FFFD00
-
-/* System RAM: */
-#define XSHAL_RAM_VADDR 0x60000000
-#define XSHAL_RAM_PADDR 0x60000000
-#define XSHAL_RAM_VSIZE 0x04000000
-#define XSHAL_RAM_PSIZE 0x04000000
-#define XSHAL_RAM_SIZE XSHAL_RAM_PSIZE
-/* Largest available area (free of vectors): */
-#define XSHAL_RAM_AVAIL_VADDR 0x60000400
-#define XSHAL_RAM_AVAIL_VSIZE 0x03FFFC00
-
-/*
- * Shadow system RAM (same device as system RAM, at different address).
- * (Emulation boards need this for the SONIC Ethernet driver
- * when data caches are configured for writeback mode.)
- * NOTE: on full MMU configs, this points to the BYPASS virtual address
- * of system RAM, ie. is the same as XSHAL_RAM_* except that virtual
- * addresses are viewed through the BYPASS static map rather than
- * the CACHED static map.
- */
-#define XSHAL_RAM_BYPASS_VADDR 0xA0000000
-#define XSHAL_RAM_BYPASS_PADDR 0xA0000000
-#define XSHAL_RAM_BYPASS_PSIZE 0x04000000
-
-/* Alternate system RAM (different device than system RAM): */
-/*#define XSHAL_ALTRAM_[VP]ADDR ...not configured...*/
-/*#define XSHAL_ALTRAM_SIZE ...not configured...*/
-
-/* Some available location in which to place devices in a simulation (eg. XTMP): */
-#define XSHAL_SIMIO_CACHED_VADDR 0xC0000000
-#define XSHAL_SIMIO_BYPASS_VADDR 0xC0000000
-#define XSHAL_SIMIO_PADDR 0xC0000000
-#define XSHAL_SIMIO_SIZE 0x20000000
-
-
-/*----------------------------------------------------------------------
- * For use by reference testbench exit and diagnostic routines.
- */
-#define XSHAL_MAGIC_EXIT 0x0
-
-/*----------------------------------------------------------------------
- * DEVICE-ADDRESS DEPENDENT...
- *
- * Values written to CACHEATTR special register (or its equivalent)
- * to enable and disable caches in various modes.
- *----------------------------------------------------------------------*/
-
-/*----------------------------------------------------------------------
- BACKWARD COMPATIBILITY ...
- ----------------------------------------------------------------------*/
-
-/*
- * NOTE: the following two macros are DEPRECATED. Use the latter
- * board-specific macros instead, which are specially tuned for the
- * particular target environments' memory maps.
- */
-#define XSHAL_CACHEATTR_BYPASS XSHAL_XT2000_CACHEATTR_BYPASS /* disable caches in bypass mode */
-#define XSHAL_CACHEATTR_DEFAULT XSHAL_XT2000_CACHEATTR_DEFAULT /* default setting to enable caches (no writeback!) */
-
-/*----------------------------------------------------------------------
- GENERIC
- ----------------------------------------------------------------------*/
-
-/* For the following, a 512MB region is used if it contains a system (PIF) RAM,
- * system (PIF) ROM, local memory, or XLMI. */
-
-/* These set any unused 512MB region to cache-BYPASS attribute: */
-#define XSHAL_ALLVALID_CACHEATTR_WRITEBACK 0x22224442 /* enable caches in write-back mode */
-#define XSHAL_ALLVALID_CACHEATTR_WRITEALLOC 0x22221112 /* enable caches in write-allocate mode */
-#define XSHAL_ALLVALID_CACHEATTR_WRITETHRU 0x22221112 /* enable caches in write-through mode */
-#define XSHAL_ALLVALID_CACHEATTR_BYPASS 0x22222222 /* disable caches in bypass mode */
-#define XSHAL_ALLVALID_CACHEATTR_DEFAULT XSHAL_ALLVALID_CACHEATTR_WRITEBACK /* default setting to enable caches */
-
-/* These set any unused 512MB region to ILLEGAL attribute: */
-#define XSHAL_STRICT_CACHEATTR_WRITEBACK 0xFFFF444F /* enable caches in write-back mode */
-#define XSHAL_STRICT_CACHEATTR_WRITEALLOC 0xFFFF111F /* enable caches in write-allocate mode */
-#define XSHAL_STRICT_CACHEATTR_WRITETHRU 0xFFFF111F /* enable caches in write-through mode */
-#define XSHAL_STRICT_CACHEATTR_BYPASS 0xFFFF222F /* disable caches in bypass mode */
-#define XSHAL_STRICT_CACHEATTR_DEFAULT XSHAL_STRICT_CACHEATTR_WRITEBACK /* default setting to enable caches */
-
-/* These set the first 512MB, if unused, to ILLEGAL attribute to help catch
- * NULL-pointer dereference bugs; all other unused 512MB regions are set
- * to cache-BYPASS attribute: */
-#define XSHAL_TRAPNULL_CACHEATTR_WRITEBACK 0x2222444F /* enable caches in write-back mode */
-#define XSHAL_TRAPNULL_CACHEATTR_WRITEALLOC 0x2222111F /* enable caches in write-allocate mode */
-#define XSHAL_TRAPNULL_CACHEATTR_WRITETHRU 0x2222111F /* enable caches in write-through mode */
-#define XSHAL_TRAPNULL_CACHEATTR_BYPASS 0x2222222F /* disable caches in bypass mode */
-#define XSHAL_TRAPNULL_CACHEATTR_DEFAULT XSHAL_TRAPNULL_CACHEATTR_WRITEBACK /* default setting to enable caches */
-
-/*----------------------------------------------------------------------
- ISS (Instruction Set Simulator) SPECIFIC ...
- ----------------------------------------------------------------------*/
-
-/* For now, ISS defaults to the TRAPNULL settings: */
-#define XSHAL_ISS_CACHEATTR_WRITEBACK XSHAL_TRAPNULL_CACHEATTR_WRITEBACK
-#define XSHAL_ISS_CACHEATTR_WRITEALLOC XSHAL_TRAPNULL_CACHEATTR_WRITEALLOC
-#define XSHAL_ISS_CACHEATTR_WRITETHRU XSHAL_TRAPNULL_CACHEATTR_WRITETHRU
-#define XSHAL_ISS_CACHEATTR_BYPASS XSHAL_TRAPNULL_CACHEATTR_BYPASS
-#define XSHAL_ISS_CACHEATTR_DEFAULT XSHAL_TRAPNULL_CACHEATTR_WRITEBACK
-
-#define XSHAL_ISS_PIPE_REGIONS 0
-#define XSHAL_ISS_SDRAM_REGIONS 0
-
-
-/*----------------------------------------------------------------------
- XT2000 BOARD SPECIFIC ...
- ----------------------------------------------------------------------*/
-
-/* For the following, a 512MB region is used if it contains any system RAM,
- * system ROM, local memory, XLMI, or other XT2000 board device or memory.
- * Regions containing devices are forced to cache-BYPASS mode regardless
- * of whether the macro is _WRITEBACK vs. _BYPASS etc. */
-
-/* These set any 512MB region unused on the XT2000 to ILLEGAL attribute: */
-#define XSHAL_XT2000_CACHEATTR_WRITEBACK 0xFF22444F /* enable caches in write-back mode */
-#define XSHAL_XT2000_CACHEATTR_WRITEALLOC 0xFF22111F /* enable caches in write-allocate mode */
-#define XSHAL_XT2000_CACHEATTR_WRITETHRU 0xFF22111F /* enable caches in write-through mode */
-#define XSHAL_XT2000_CACHEATTR_BYPASS 0xFF22222F /* disable caches in bypass mode */
-#define XSHAL_XT2000_CACHEATTR_DEFAULT XSHAL_XT2000_CACHEATTR_WRITEBACK /* default setting to enable caches */
-
-#define XSHAL_XT2000_PIPE_REGIONS 0x00000000 /* BusInt pipeline regions */
-#define XSHAL_XT2000_SDRAM_REGIONS 0x00000440 /* BusInt SDRAM regions */
-
-
-/*----------------------------------------------------------------------
- VECTOR INFO AND SIZES
- ----------------------------------------------------------------------*/
-
-#define XSHAL_VECTORS_PACKED 0
-#define XSHAL_STATIC_VECTOR_SELECT 0
-#define XSHAL_RESET_VECTOR_VADDR 0x50000000
-#define XSHAL_RESET_VECTOR_PADDR 0x50000000
-
-/*
- * Sizes allocated to vectors by the system (memory map) configuration.
- * These sizes are constrained by core configuration (eg. one vector's
- * code cannot overflow into another vector) but are dependent on the
- * system or board (or LSP) memory map configuration.
- *
- * Whether or not each vector happens to be in a system ROM is also
- * a system configuration matter, sometimes useful, included here also:
- */
-#define XSHAL_RESET_VECTOR_SIZE 0x00000300
-#define XSHAL_RESET_VECTOR_ISROM 1
-#define XSHAL_USER_VECTOR_SIZE 0x00000038
-#define XSHAL_USER_VECTOR_ISROM 0
-#define XSHAL_PROGRAMEXC_VECTOR_SIZE XSHAL_USER_VECTOR_SIZE /* for backward compatibility */
-#define XSHAL_USEREXC_VECTOR_SIZE XSHAL_USER_VECTOR_SIZE /* for backward compatibility */
-#define XSHAL_KERNEL_VECTOR_SIZE 0x00000038
-#define XSHAL_KERNEL_VECTOR_ISROM 0
-#define XSHAL_STACKEDEXC_VECTOR_SIZE XSHAL_KERNEL_VECTOR_SIZE /* for backward compatibility */
-#define XSHAL_KERNELEXC_VECTOR_SIZE XSHAL_KERNEL_VECTOR_SIZE /* for backward compatibility */
-#define XSHAL_DOUBLEEXC_VECTOR_SIZE 0x00000040
-#define XSHAL_DOUBLEEXC_VECTOR_ISROM 0
-#define XSHAL_WINDOW_VECTORS_SIZE 0x00000178
-#define XSHAL_WINDOW_VECTORS_ISROM 0
-#define XSHAL_INTLEVEL2_VECTOR_SIZE 0x00000038
-#define XSHAL_INTLEVEL2_VECTOR_ISROM 0
-#define XSHAL_INTLEVEL3_VECTOR_SIZE 0x00000038
-#define XSHAL_INTLEVEL3_VECTOR_ISROM 0
-#define XSHAL_INTLEVEL4_VECTOR_SIZE 0x00000038
-#define XSHAL_INTLEVEL4_VECTOR_ISROM 0
-#define XSHAL_INTLEVEL5_VECTOR_SIZE 0x00000038
-#define XSHAL_INTLEVEL5_VECTOR_ISROM 0
-#define XSHAL_INTLEVEL6_VECTOR_SIZE 0x00000038
-#define XSHAL_INTLEVEL6_VECTOR_ISROM 0
-#define XSHAL_DEBUG_VECTOR_SIZE XSHAL_INTLEVEL6_VECTOR_SIZE
-#define XSHAL_DEBUG_VECTOR_ISROM XSHAL_INTLEVEL6_VECTOR_ISROM
-#define XSHAL_NMI_VECTOR_SIZE 0x00000038
-#define XSHAL_NMI_VECTOR_ISROM 0
-#define XSHAL_INTLEVEL7_VECTOR_SIZE XSHAL_NMI_VECTOR_SIZE
-
-
-#endif /*XTENSA_CONFIG_SYSTEM_H*/
-
diff --git a/src/platform/baytrail/include/arch/xtensa/config/tie-asm.h b/src/platform/baytrail/include/arch/xtensa/config/tie-asm.h
deleted file mode 100644
index d7140f8..0000000
--- a/src/platform/baytrail/include/arch/xtensa/config/tie-asm.h
+++ /dev/null
@@ -1,240 +0,0 @@
-/*
- * tie-asm.h -- compile-time HAL assembler definitions dependent on CORE & TIE
- *
- * NOTE: This header file is not meant to be included directly.
- */
-
-/* This header file contains assembly-language definitions (assembly
- macros, etc.) for this specific Xtensa processor's TIE extensions
- and options. It is customized to this Xtensa processor configuration.
-
- Copyright (c) 1999-2015 Cadence Design Systems Inc.
-
- Permission is hereby granted, free of charge, to any person obtaining
- a copy of this software and associated documentation files (the
- "Software"), to deal in the Software without restriction, including
- without limitation the rights to use, copy, modify, merge, publish,
- distribute, sublicense, and/or sell copies of the Software, and to
- permit persons to whom the Software is furnished to do so, subject to
- the following conditions:
-
- The above copyright notice and this permission notice shall be included
- in all copies or substantial portions of the Software.
-
- THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
- EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
- MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
- IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY
- CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
- TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
- SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. */
-
-#ifndef _XTENSA_CORE_TIE_ASM_H
-#define _XTENSA_CORE_TIE_ASM_H
-
-/* Selection parameter values for save-area save/restore macros: */
-/* Option vs. TIE: */
-#define XTHAL_SAS_TIE 0x0001 /* custom extension or coprocessor */
-#define XTHAL_SAS_OPT 0x0002 /* optional (and not a coprocessor) */
-#define XTHAL_SAS_ANYOT 0x0003 /* both of the above */
-/* Whether used automatically by compiler: */
-#define XTHAL_SAS_NOCC 0x0004 /* not used by compiler w/o special opts/code */
-#define XTHAL_SAS_CC 0x0008 /* used by compiler without special opts/code */
-#define XTHAL_SAS_ANYCC 0x000C /* both of the above */
-/* ABI handling across function calls: */
-#define XTHAL_SAS_CALR 0x0010 /* caller-saved */
-#define XTHAL_SAS_CALE 0x0020 /* callee-saved */
-#define XTHAL_SAS_GLOB 0x0040 /* global across function calls (in thread) */
-#define XTHAL_SAS_ANYABI 0x0070 /* all of the above three */
-/* Misc */
-#define XTHAL_SAS_ALL 0xFFFF /* include all default NCP contents */
-#define XTHAL_SAS3(optie,ccuse,abi) ( ((optie) & XTHAL_SAS_ANYOT) \
- | ((ccuse) & XTHAL_SAS_ANYCC) \
- | ((abi) & XTHAL_SAS_ANYABI) )
-
-
- /*
- * Macro to store all non-coprocessor (extra) custom TIE and optional state
- * (not including zero-overhead loop registers).
- * Required parameters:
- * ptr Save area pointer address register (clobbered)
- * (register must contain a 4 byte aligned address).
- * at1..at4 Four temporary address registers (first XCHAL_NCP_NUM_ATMPS
- * registers are clobbered, the remaining are unused).
- * Optional parameters:
- * continue If macro invoked as part of a larger store sequence, set to 1
- * if this is not the first in the sequence. Defaults to 0.
- * ofs Offset from start of larger sequence (from value of first ptr
- * in sequence) at which to store. Defaults to next available space
- * (or 0 if <continue> is 0).
- * select Select what category(ies) of registers to store, as a bitmask
- * (see XTHAL_SAS_xxx constants). Defaults to all registers.
- * alloc Select what category(ies) of registers to allocate; if any
- * category is selected here that is not in <select>, space for
- * the corresponding registers is skipped without doing any store.
- */
- .macro xchal_ncp_store ptr at1 at2 at3 at4 continue=0 ofs=-1 select=XTHAL_SAS_ALL alloc=0
- xchal_sa_start \continue, \ofs
- // Optional caller-saved registers not used by default by the compiler:
- .ifeq (XTHAL_SAS_OPT | XTHAL_SAS_NOCC | XTHAL_SAS_CALR) & ~(\select)
- xchal_sa_align \ptr, 0, 1016, 4, 4
- rsr.BR \at1 // boolean option
- s32i \at1, \ptr, .Lxchal_ofs_+0
- rsr.SCOMPARE1 \at1 // conditional store option
- s32i \at1, \ptr, .Lxchal_ofs_+4
- .set .Lxchal_ofs_, .Lxchal_ofs_ + 8
- .elseif ((XTHAL_SAS_OPT | XTHAL_SAS_NOCC | XTHAL_SAS_CALR) & ~(\alloc)) == 0
- xchal_sa_align \ptr, 0, 1016, 4, 4
- .set .Lxchal_ofs_, .Lxchal_ofs_ + 8
- .endif
- .endm // xchal_ncp_store
-
- /*
- * Macro to load all non-coprocessor (extra) custom TIE and optional state
- * (not including zero-overhead loop registers).
- * Required parameters:
- * ptr Save area pointer address register (clobbered)
- * (register must contain a 4 byte aligned address).
- * at1..at4 Four temporary address registers (first XCHAL_NCP_NUM_ATMPS
- * registers are clobbered, the remaining are unused).
- * Optional parameters:
- * continue If macro invoked as part of a larger load sequence, set to 1
- * if this is not the first in the sequence. Defaults to 0.
- * ofs Offset from start of larger sequence (from value of first ptr
- * in sequence) at which to load. Defaults to next available space
- * (or 0 if <continue> is 0).
- * select Select what category(ies) of registers to load, as a bitmask
- * (see XTHAL_SAS_xxx constants). Defaults to all registers.
- * alloc Select what category(ies) of registers to allocate; if any
- * category is selected here that is not in <select>, space for
- * the corresponding registers is skipped without doing any load.
- */
- .macro xchal_ncp_load ptr at1 at2 at3 at4 continue=0 ofs=-1 select=XTHAL_SAS_ALL alloc=0
- xchal_sa_start \continue, \ofs
- // Optional caller-saved registers not used by default by the compiler:
- .ifeq (XTHAL_SAS_OPT | XTHAL_SAS_NOCC | XTHAL_SAS_CALR) & ~(\select)
- xchal_sa_align \ptr, 0, 1016, 4, 4
- l32i \at1, \ptr, .Lxchal_ofs_+0
- wsr.BR \at1 // boolean option
- l32i \at1, \ptr, .Lxchal_ofs_+4
- wsr.SCOMPARE1 \at1 // conditional store option
- .set .Lxchal_ofs_, .Lxchal_ofs_ + 8
- .elseif ((XTHAL_SAS_OPT | XTHAL_SAS_NOCC | XTHAL_SAS_CALR) & ~(\alloc)) == 0
- xchal_sa_align \ptr, 0, 1016, 4, 4
- .set .Lxchal_ofs_, .Lxchal_ofs_ + 8
- .endif
- .endm // xchal_ncp_load
-
-
-#define XCHAL_NCP_NUM_ATMPS 1
-
- /*
- * Macro to store the state of TIE coprocessor AudioEngineLX.
- * Required parameters:
- * ptr Save area pointer address register (clobbered)
- * (register must contain a 8 byte aligned address).
- * at1..at4 Four temporary address registers (first XCHAL_CP1_NUM_ATMPS
- * registers are clobbered, the remaining are unused).
- * Optional parameters are the same as for xchal_ncp_store.
- */
-#define xchal_cp_AudioEngineLX_store xchal_cp1_store
- .macro xchal_cp1_store ptr at1 at2 at3 at4 continue=0 ofs=-1 select=XTHAL_SAS_ALL alloc=0
- xchal_sa_start \continue, \ofs
- // Custom caller-saved registers not used by default by the compiler:
- .ifeq (XTHAL_SAS_TIE | XTHAL_SAS_NOCC | XTHAL_SAS_CALR) & ~(\select)
- xchal_sa_align \ptr, 0, 0, 8, 8
- rur.AE_OVF_SAR \at1 // ureg 240
- s32i \at1, \ptr, .Lxchal_ofs_+0
- rur.AE_BITHEAD \at1 // ureg 241
- s32i \at1, \ptr, .Lxchal_ofs_+4
- rur.AE_TS_FTS_BU_BP \at1 // ureg 242
- s32i \at1, \ptr, .Lxchal_ofs_+8
- rur.AE_SD_NO \at1 // ureg 243
- s32i \at1, \ptr, .Lxchal_ofs_+12
- ae_sp24x2s.i aep0, \ptr, .Lxchal_ofs_+16
- ae_sp24x2s.i aep1, \ptr, .Lxchal_ofs_+24
- ae_sp24x2s.i aep2, \ptr, .Lxchal_ofs_+32
- ae_sp24x2s.i aep3, \ptr, .Lxchal_ofs_+40
- ae_sp24x2s.i aep4, \ptr, .Lxchal_ofs_+48
- ae_sp24x2s.i aep5, \ptr, .Lxchal_ofs_+56
- addi \ptr, \ptr, 64
- ae_sp24x2s.i aep6, \ptr, .Lxchal_ofs_+0
- ae_sp24x2s.i aep7, \ptr, .Lxchal_ofs_+8
- ae_sq56s.i aeq0, \ptr, .Lxchal_ofs_+16
- ae_sq56s.i aeq1, \ptr, .Lxchal_ofs_+24
- ae_sq56s.i aeq2, \ptr, .Lxchal_ofs_+32
- ae_sq56s.i aeq3, \ptr, .Lxchal_ofs_+40
- .set .Lxchal_pofs_, .Lxchal_pofs_ + 64
- .set .Lxchal_ofs_, .Lxchal_ofs_ + 48
- .elseif ((XTHAL_SAS_TIE | XTHAL_SAS_NOCC | XTHAL_SAS_CALR) & ~(\alloc)) == 0
- xchal_sa_align \ptr, 0, 0, 8, 8
- .set .Lxchal_ofs_, .Lxchal_ofs_ + 112
- .endif
- .endm // xchal_cp1_store
-
- /*
- * Macro to load the state of TIE coprocessor AudioEngineLX.
- * Required parameters:
- * ptr Save area pointer address register (clobbered)
- * (register must contain a 8 byte aligned address).
- * at1..at4 Four temporary address registers (first XCHAL_CP1_NUM_ATMPS
- * registers are clobbered, the remaining are unused).
- * Optional parameters are the same as for xchal_ncp_load.
- */
-#define xchal_cp_AudioEngineLX_load xchal_cp1_load
- .macro xchal_cp1_load ptr at1 at2 at3 at4 continue=0 ofs=-1 select=XTHAL_SAS_ALL alloc=0
- xchal_sa_start \continue, \ofs
- // Custom caller-saved registers not used by default by the compiler:
- .ifeq (XTHAL_SAS_TIE | XTHAL_SAS_NOCC | XTHAL_SAS_CALR) & ~(\select)
- xchal_sa_align \ptr, 0, 0, 8, 8
- l32i \at1, \ptr, .Lxchal_ofs_+0
- wur.AE_OVF_SAR \at1 // ureg 240
- l32i \at1, \ptr, .Lxchal_ofs_+4
- wur.AE_BITHEAD \at1 // ureg 241
- l32i \at1, \ptr, .Lxchal_ofs_+8
- wur.AE_TS_FTS_BU_BP \at1 // ureg 242
- l32i \at1, \ptr, .Lxchal_ofs_+12
- wur.AE_SD_NO \at1 // ureg 243
- ae_lp24x2.i aep0, \ptr, .Lxchal_ofs_+16
- ae_lp24x2.i aep1, \ptr, .Lxchal_ofs_+24
- ae_lp24x2.i aep2, \ptr, .Lxchal_ofs_+32
- ae_lp24x2.i aep3, \ptr, .Lxchal_ofs_+40
- ae_lp24x2.i aep4, \ptr, .Lxchal_ofs_+48
- ae_lp24x2.i aep5, \ptr, .Lxchal_ofs_+56
- addi \ptr, \ptr, 64
- ae_lp24x2.i aep6, \ptr, .Lxchal_ofs_+0
- ae_lp24x2.i aep7, \ptr, .Lxchal_ofs_+8
- addi \ptr, \ptr, 16
- ae_lq56.i aeq0, \ptr, .Lxchal_ofs_+0
- ae_lq56.i aeq1, \ptr, .Lxchal_ofs_+8
- ae_lq56.i aeq2, \ptr, .Lxchal_ofs_+16
- ae_lq56.i aeq3, \ptr, .Lxchal_ofs_+24
- .set .Lxchal_pofs_, .Lxchal_pofs_ + 80
- .set .Lxchal_ofs_, .Lxchal_ofs_ + 32
- .elseif ((XTHAL_SAS_TIE | XTHAL_SAS_NOCC | XTHAL_SAS_CALR) & ~(\alloc)) == 0
- xchal_sa_align \ptr, 0, 0, 8, 8
- .set .Lxchal_ofs_, .Lxchal_ofs_ + 112
- .endif
- .endm // xchal_cp1_load
-
-#define XCHAL_CP1_NUM_ATMPS 1
-#define XCHAL_SA_NUM_ATMPS 1
-
- /* Empty macros for unconfigured coprocessors: */
- .macro xchal_cp0_store p a b c d continue=0 ofs=-1 select=-1 ; .endm
- .macro xchal_cp0_load p a b c d continue=0 ofs=-1 select=-1 ; .endm
- .macro xchal_cp2_store p a b c d continue=0 ofs=-1 select=-1 ; .endm
- .macro xchal_cp2_load p a b c d continue=0 ofs=-1 select=-1 ; .endm
- .macro xchal_cp3_store p a b c d continue=0 ofs=-1 select=-1 ; .endm
- .macro xchal_cp3_load p a b c d continue=0 ofs=-1 select=-1 ; .endm
- .macro xchal_cp4_store p a b c d continue=0 ofs=-1 select=-1 ; .endm
- .macro xchal_cp4_load p a b c d continue=0 ofs=-1 select=-1 ; .endm
- .macro xchal_cp5_store p a b c d continue=0 ofs=-1 select=-1 ; .endm
- .macro xchal_cp5_load p a b c d continue=0 ofs=-1 select=-1 ; .endm
- .macro xchal_cp6_store p a b c d continue=0 ofs=-1 select=-1 ; .endm
- .macro xchal_cp6_load p a b c d continue=0 ofs=-1 select=-1 ; .endm
- .macro xchal_cp7_store p a b c d continue=0 ofs=-1 select=-1 ; .endm
- .macro xchal_cp7_load p a b c d continue=0 ofs=-1 select=-1 ; .endm
-
-#endif /*_XTENSA_CORE_TIE_ASM_H*/
-
diff --git a/src/platform/baytrail/include/arch/xtensa/config/tie.h b/src/platform/baytrail/include/arch/xtensa/config/tie.h
deleted file mode 100644
index 3c63812..0000000
--- a/src/platform/baytrail/include/arch/xtensa/config/tie.h
+++ /dev/null
@@ -1,170 +0,0 @@
-/*
- * tie.h -- compile-time HAL definitions dependent on CORE & TIE configuration
- *
- * NOTE: This header file is not meant to be included directly.
- */
-
-/* This header file describes this specific Xtensa processor's TIE extensions
- that extend basic Xtensa core functionality. It is customized to this
- Xtensa processor configuration.
-
- Copyright (c) 1999-2015 Cadence Design Systems Inc.
-
- Permission is hereby granted, free of charge, to any person obtaining
- a copy of this software and associated documentation files (the
- "Software"), to deal in the Software without restriction, including
- without limitation the rights to use, copy, modify, merge, publish,
- distribute, sublicense, and/or sell copies of the Software, and to
- permit persons to whom the Software is furnished to do so, subject to
- the following conditions:
-
- The above copyright notice and this permission notice shall be included
- in all copies or substantial portions of the Software.
-
- THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
- EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
- MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
- IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY
- CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
- TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
- SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. */
-
-#ifndef _XTENSA_CORE_TIE_H
-#define _XTENSA_CORE_TIE_H
-
-#define XCHAL_CP_NUM 1 /* number of coprocessors */
-#define XCHAL_CP_MAX 2 /* max CP ID + 1 (0 if none) */
-#define XCHAL_CP_MASK 0x02 /* bitmask of all CPs by ID */
-#define XCHAL_CP_PORT_MASK 0x00 /* bitmask of only port CPs */
-
-/* Basic parameters of each coprocessor: */
-#define XCHAL_CP1_NAME "AudioEngineLX"
-#define XCHAL_CP1_IDENT AudioEngineLX
-#define XCHAL_CP1_SA_SIZE 112 /* size of state save area */
-#define XCHAL_CP1_SA_ALIGN 8 /* min alignment of save area */
-#define XCHAL_CP_ID_AUDIOENGINELX 1 /* coprocessor ID (0..7) */
-
-/* Filler info for unassigned coprocessors, to simplify arrays etc: */
-#define XCHAL_CP0_SA_SIZE 0
-#define XCHAL_CP0_SA_ALIGN 1
-#define XCHAL_CP2_SA_SIZE 0
-#define XCHAL_CP2_SA_ALIGN 1
-#define XCHAL_CP3_SA_SIZE 0
-#define XCHAL_CP3_SA_ALIGN 1
-#define XCHAL_CP4_SA_SIZE 0
-#define XCHAL_CP4_SA_ALIGN 1
-#define XCHAL_CP5_SA_SIZE 0
-#define XCHAL_CP5_SA_ALIGN 1
-#define XCHAL_CP6_SA_SIZE 0
-#define XCHAL_CP6_SA_ALIGN 1
-#define XCHAL_CP7_SA_SIZE 0
-#define XCHAL_CP7_SA_ALIGN 1
-
-/* Save area for non-coprocessor optional and custom (TIE) state: */
-#define XCHAL_NCP_SA_SIZE 8
-#define XCHAL_NCP_SA_ALIGN 4
-
-/* Total save area for optional and custom state (NCP + CPn): */
-#define XCHAL_TOTAL_SA_SIZE 128 /* with 16-byte align padding */
-#define XCHAL_TOTAL_SA_ALIGN 8 /* actual minimum alignment */
-
-/*
- * Detailed contents of save areas.
- * NOTE: caller must define the XCHAL_SA_REG macro (not defined here)
- * before expanding the XCHAL_xxx_SA_LIST() macros.
- *
- * XCHAL_SA_REG(s,ccused,abikind,kind,opt,name,galign,align,asize,
- * dbnum,base,regnum,bitsz,gapsz,reset,x...)
- *
- * s = passed from XCHAL_*_LIST(s), eg. to select how to expand
- * ccused = set if used by compiler without special options or code
- * abikind = 0 (caller-saved), 1 (callee-saved), or 2 (thread-global)
- * kind = 0 (special reg), 1 (TIE user reg), or 2 (TIE regfile reg)
- * opt = 0 (custom TIE extension or coprocessor), or 1 (optional reg)
- * name = lowercase reg name (no quotes)
- * galign = group byte alignment (power of 2) (galign >= align)
- * align = register byte alignment (power of 2)
- * asize = allocated size in bytes (asize*8 == bitsz + gapsz + padsz)
- * (not including any pad bytes required to galign this or next reg)
- * dbnum = unique target number f/debug (see <xtensa-libdb-macros.h>)
- * base = reg shortname w/o index (or sr=special, ur=TIE user reg)
- * regnum = reg index in regfile, or special/TIE-user reg number
- * bitsz = number of significant bits (regfile width, or ur/sr mask bits)
- * gapsz = intervening bits, if bitsz bits not stored contiguously
- * (padsz = pad bits at end [TIE regfile] or at msbits [ur,sr] of asize)
- * reset = register reset value (or 0 if undefined at reset)
- * x = reserved for future use (0 until then)
- *
- * To filter out certain registers, e.g. to expand only the non-global
- * registers used by the compiler, you can do something like this:
- *
- * #define XCHAL_SA_REG(s,ccused,p...) SELCC##ccused(p)
- * #define SELCC0(p...)
- * #define SELCC1(abikind,p...) SELAK##abikind(p)
- * #define SELAK0(p...) REG(p)
- * #define SELAK1(p...) REG(p)
- * #define SELAK2(p...)
- * #define REG(kind,tie,name,galn,aln,asz,csz,dbnum,base,rnum,bsz,rst,x...) \
- * ...what you want to expand...
- */
-
-#define XCHAL_NCP_SA_NUM 2
-#define XCHAL_NCP_SA_LIST(s) \
- XCHAL_SA_REG(s,0,0,0,1, br, 4, 4, 4,0x0204, sr,4 , 16,0,0,0) \
- XCHAL_SA_REG(s,0,0,0,1, scompare1, 4, 4, 4,0x020C, sr,12 , 32,0,0,0)
-
-#define XCHAL_CP0_SA_NUM 0
-#define XCHAL_CP0_SA_LIST(s) /* empty */
-
-#define XCHAL_CP1_SA_NUM 16
-#define XCHAL_CP1_SA_LIST(s) \
- XCHAL_SA_REG(s,0,0,1,0, ae_ovf_sar, 8, 4, 4,0x03F0, ur,240, 7,0,0,0) \
- XCHAL_SA_REG(s,0,0,1,0, ae_bithead, 4, 4, 4,0x03F1, ur,241, 32,0,0,0) \
- XCHAL_SA_REG(s,0,0,1,0,ae_ts_fts_bu_bp, 4, 4, 4,0x03F2, ur,242, 16,0,0,0) \
- XCHAL_SA_REG(s,0,0,1,0, ae_sd_no, 4, 4, 4,0x03F3, ur,243, 28,0,0,0) \
- XCHAL_SA_REG(s,0,0,2,0, aep0, 8, 8, 8,0x0060, aep,0 , 48,0,0,0) \
- XCHAL_SA_REG(s,0,0,2,0, aep1, 8, 8, 8,0x0061, aep,1 , 48,0,0,0) \
- XCHAL_SA_REG(s,0,0,2,0, aep2, 8, 8, 8,0x0062, aep,2 , 48,0,0,0) \
- XCHAL_SA_REG(s,0,0,2,0, aep3, 8, 8, 8,0x0063, aep,3 , 48,0,0,0) \
- XCHAL_SA_REG(s,0,0,2,0, aep4, 8, 8, 8,0x0064, aep,4 , 48,0,0,0) \
- XCHAL_SA_REG(s,0,0,2,0, aep5, 8, 8, 8,0x0065, aep,5 , 48,0,0,0) \
- XCHAL_SA_REG(s,0,0,2,0, aep6, 8, 8, 8,0x0066, aep,6 , 48,0,0,0) \
- XCHAL_SA_REG(s,0,0,2,0, aep7, 8, 8, 8,0x0067, aep,7 , 48,0,0,0) \
- XCHAL_SA_REG(s,0,0,2,0, aeq0, 8, 8, 8,0x0068, aeq,0 , 56,0,0,0) \
- XCHAL_SA_REG(s,0,0,2,0, aeq1, 8, 8, 8,0x0069, aeq,1 , 56,0,0,0) \
- XCHAL_SA_REG(s,0,0,2,0, aeq2, 8, 8, 8,0x006A, aeq,2 , 56,0,0,0) \
- XCHAL_SA_REG(s,0,0,2,0, aeq3, 8, 8, 8,0x006B, aeq,3 , 56,0,0,0)
-
-#define XCHAL_CP2_SA_NUM 0
-#define XCHAL_CP2_SA_LIST(s) /* empty */
-
-#define XCHAL_CP3_SA_NUM 0
-#define XCHAL_CP3_SA_LIST(s) /* empty */
-
-#define XCHAL_CP4_SA_NUM 0
-#define XCHAL_CP4_SA_LIST(s) /* empty */
-
-#define XCHAL_CP5_SA_NUM 0
-#define XCHAL_CP5_SA_LIST(s) /* empty */
-
-#define XCHAL_CP6_SA_NUM 0
-#define XCHAL_CP6_SA_LIST(s) /* empty */
-
-#define XCHAL_CP7_SA_NUM 0
-#define XCHAL_CP7_SA_LIST(s) /* empty */
-
-/* Byte length of instruction from its first nibble (op0 field), per FLIX. */
-#define XCHAL_OP0_FORMAT_LENGTHS 3,3,3,3,3,3,3,3,2,2,2,2,2,2,3,8
-/* Byte length of instruction from its first byte, per FLIX. */
-#define XCHAL_BYTE0_FORMAT_LENGTHS \
- 3,3,3,3,3,3,3,3,2,2,2,2,2,2,3,8, 3,3,3,3,3,3,3,3,2,2,2,2,2,2,3,8,\
- 3,3,3,3,3,3,3,3,2,2,2,2,2,2,3,8, 3,3,3,3,3,3,3,3,2,2,2,2,2,2,3,8,\
- 3,3,3,3,3,3,3,3,2,2,2,2,2,2,3,8, 3,3,3,3,3,3,3,3,2,2,2,2,2,2,3,8,\
- 3,3,3,3,3,3,3,3,2,2,2,2,2,2,3,8, 3,3,3,3,3,3,3,3,2,2,2,2,2,2,3,8,\
- 3,3,3,3,3,3,3,3,2,2,2,2,2,2,3,8, 3,3,3,3,3,3,3,3,2,2,2,2,2,2,3,8,\
- 3,3,3,3,3,3,3,3,2,2,2,2,2,2,3,8, 3,3,3,3,3,3,3,3,2,2,2,2,2,2,3,8,\
- 3,3,3,3,3,3,3,3,2,2,2,2,2,2,3,8, 3,3,3,3,3,3,3,3,2,2,2,2,2,2,3,8,\
- 3,3,3,3,3,3,3,3,2,2,2,2,2,2,3,8, 3,3,3,3,3,3,3,3,2,2,2,2,2,2,3,8
-
-#endif /*_XTENSA_CORE_TIE_H*/
-
diff --git a/src/platform/baytrail/include/platform/Makefile.am b/src/platform/baytrail/include/platform/Makefile.am
deleted file mode 100644
index f3caa55..0000000
--- a/src/platform/baytrail/include/platform/Makefile.am
+++ /dev/null
@@ -1,13 +0,0 @@
-noinst_HEADERS = \
- clk.h \
- dma.h \
- idc.h \
- interrupt.h \
- mailbox.h \
- memory.h \
- platcfg.h \
- platform.h \
- pm_runtime.h \
- pmc.h \
- shim.h \
- timer.h
diff --git a/src/platform/baytrail/include/platform/clk.h b/src/platform/baytrail/include/platform/clk.h
deleted file mode 100644
index 7292b00..0000000
--- a/src/platform/baytrail/include/platform/clk.h
+++ /dev/null
@@ -1,42 +0,0 @@
-/*
- * Copyright (c) 2016, Intel Corporation
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- * * Redistributions of source code must retain the above copyright
- * notice, this list of conditions and the following disclaimer.
- * * Redistributions in binary form must reproduce the above copyright
- * notice, this list of conditions and the following disclaimer in the
- * documentation and/or other materials provided with the distribution.
- * * Neither the name of the Intel Corporation nor the
- * names of its contributors may be used to endorse or promote products
- * derived from this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
- * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
- * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
- * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
- * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
- * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
- * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
- * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
- * POSSIBILITY OF SUCH DAMAGE.
- *
- * Author: Liam Girdwood <liam.r.girdwood@linux.intel.com>
- */
-
-#ifndef __PLATFORM_CLOCK__
-#define __PLATFORM_CLOCK__
-
-#define CLK_CPU 0
-#define CLK_SSP 1
-
-#define CLK_DEFAULT_CPU_HZ 50000000
-#define CLK_MAX_CPU_HZ 343000000
-
-void init_platform_clocks(void);
-
-#endif
diff --git a/src/platform/baytrail/include/platform/dma.h b/src/platform/baytrail/include/platform/dma.h
deleted file mode 100644
index 5084dad..0000000
--- a/src/platform/baytrail/include/platform/dma.h
+++ /dev/null
@@ -1,65 +0,0 @@
-/*
- * Copyright (c) 2016, Intel Corporation
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- * * Redistributions of source code must retain the above copyright
- * notice, this list of conditions and the following disclaimer.
- * * Redistributions in binary form must reproduce the above copyright
- * notice, this list of conditions and the following disclaimer in the
- * documentation and/or other materials provided with the distribution.
- * * Neither the name of the Intel Corporation nor the
- * names of its contributors may be used to endorse or promote products
- * derived from this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
- * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
- * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
- * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
- * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
- * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
- * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
- * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
- * POSSIBILITY OF SUCH DAMAGE.
- *
- * Author: Liam Girdwood <liam.r.girdwood@linux.intel.com>
- * Keyon Jie <yang.jie@linux.intel.com>
- */
-
-#ifndef __PLATFORM_DMA_H__
-#define __PLATFORM_DMA_H__
-
-#include <stdint.h>
-#include <sof/dma.h>
-
-#if defined CONFIG_CHERRYTRAIL
-#define PLATFORM_NUM_DMACS 3
-#else
-#define PLATFORM_NUM_DMACS 2
-#endif
-
-#define DMA_ID_DMAC0 0
-#define DMA_ID_DMAC1 1
-#define DMA_ID_DMAC2 2
-
-#define DMA_HANDSHAKE_SSP0_RX 0
-#define DMA_HANDSHAKE_SSP0_TX 1
-#define DMA_HANDSHAKE_SSP1_RX 2
-#define DMA_HANDSHAKE_SSP1_TX 3
-#define DMA_HANDSHAKE_SSP2_RX 4
-#define DMA_HANDSHAKE_SSP2_TX 5
-#define DMA_HANDSHAKE_SSP3_RX 6
-#define DMA_HANDSHAKE_SSP3_TX 7
-#define DMA_HANDSHAKE_SSP4_RX 8
-#define DMA_HANDSHAKE_SSP4_TX 9
-#define DMA_HANDSHAKE_SSP5_RX 10
-#define DMA_HANDSHAKE_SSP5_TX 11
-#define DMA_HANDSHAKE_SSP6_RX 12
-#define DMA_HANDSHAKE_SSP6_TX 13
-
-extern struct dma dma[PLATFORM_NUM_DMACS];
-
-#endif
diff --git a/src/platform/baytrail/include/platform/idc.h b/src/platform/baytrail/include/platform/idc.h
deleted file mode 100644
index ec727e3..0000000
--- a/src/platform/baytrail/include/platform/idc.h
+++ /dev/null
@@ -1,43 +0,0 @@
-/*
- * Copyright (c) 2018, Intel Corporation
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- * * Redistributions of source code must retain the above copyright
- * notice, this list of conditions and the following disclaimer.
- * * Redistributions in binary form must reproduce the above copyright
- * notice, this list of conditions and the following disclaimer in the
- * documentation and/or other materials provided with the distribution.
- * * Neither the name of the Intel Corporation nor the
- * names of its contributors may be used to endorse or promote products
- * derived from this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
- * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
- * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
- * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
- * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
- * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
- * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
- * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
- * POSSIBILITY OF SUCH DAMAGE.
- *
- * Author: Tomasz Lauda <tomasz.lauda@linux.intel.com>
- */
-
-#ifndef __INCLUDE_PLATFORM_IDC_H__
-#define __INCLUDE_PLATFORM_IDC_H__
-
-struct idc_msg;
-
-static inline int idc_send_msg(struct idc_msg *msg,
- uint32_t mode) { return 0; }
-
-static inline void idc_process_msg_queue(void) { }
-
-static inline void idc_init(void) { }
-
-#endif
diff --git a/src/platform/baytrail/include/platform/interrupt.h b/src/platform/baytrail/include/platform/interrupt.h
deleted file mode 100644
index d0cd17b..0000000
--- a/src/platform/baytrail/include/platform/interrupt.h
+++ /dev/null
@@ -1,104 +0,0 @@
-/*
- * Copyright (c) 2016, Intel Corporation
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- * * Redistributions of source code must retain the above copyright
- * notice, this list of conditions and the following disclaimer.
- * * Redistributions in binary form must reproduce the above copyright
- * notice, this list of conditions and the following disclaimer in the
- * documentation and/or other materials provided with the distribution.
- * * Neither the name of the Intel Corporation nor the
- * names of its contributors may be used to endorse or promote products
- * derived from this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
- * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
- * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
- * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
- * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
- * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
- * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
- * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
- * POSSIBILITY OF SUCH DAMAGE.
- *
- * Author: Liam Girdwood <liam.r.girdwood@linux.intel.com>
- */
-
-#ifndef __INCLUDE_PLATFORM_INTERRUPT__
-#define __INCLUDE_PLATFORM_INTERRUPT__
-
-#include <stdint.h>
-#include <string.h>
-#include <sof/interrupt-map.h>
-
-/* IRQ numbers */
-#define IRQ_NUM_SOFTWARE0 0 /* Level 1 */
-#define IRQ_NUM_TIMER1 1 /* Level 1 */
-#define IRQ_NUM_SOFTWARE1 2 /* Level 1 */
-#define IRQ_NUM_SOFTWARE2 3 /* Level 1 */
-#define IRQ_NUM_TIMER2 5 /* Level 2 */
-#define IRQ_NUM_SOFTWARE3 6 /* Level 2 */
-#define IRQ_NUM_TIMER3 7 /* Level 3 */
-#define IRQ_NUM_SOFTWARE4 8 /* Level 3 */
-#define IRQ_NUM_SOFTWARE5 9 /* Level 3 */
-#define IRQ_NUM_EXT_IA 10 /* Level 4 */
-#define IRQ_NUM_EXT_PMC 11 /* Level 4 */
-#define IRQ_NUM_SOFTWARE6 12 /* Level 5 */
-#define IRQ_NUM_EXT_DMAC0 13 /* Level 5 */
-#define IRQ_NUM_EXT_DMAC1 14 /* Level 5 */
-#define IRQ_NUM_EXT_TIMER 15 /* Level 5 */
-#define IRQ_NUM_EXT_SSP0 16 /* Level 5 */
-#define IRQ_NUM_EXT_SSP1 17 /* Level 5 */
-#define IRQ_NUM_EXT_SSP2 18 /* Level 5 */
-#define IRQ_NUM_EXT_DMAC2 19 /* Level 5 */
-#define IRQ_NUM_NMI 20 /* Level 7 */
-
-/* SSP 3,4,5 share PHY IRQs with SSP 0,1,2 respectively but we give them a
- virtual number in order to differentiate from SSP0, 1 and 2 IRQs */
-#define IRQ_CHT_SSP_OFFSET 16
-#define IRQ_NUM_EXT_SSP3 (IRQ_CHT_SSP_OFFSET + IRQ_NUM_EXT_SSP0) /* Level 5 */
-#define IRQ_NUM_EXT_SSP4 (IRQ_CHT_SSP_OFFSET + IRQ_NUM_EXT_SSP1) /* Level 5 */
-#define IRQ_NUM_EXT_SSP5 (IRQ_CHT_SSP_OFFSET + IRQ_NUM_EXT_SSP2) /* Level 5 */
-
-/* IRQ Masks */
-#define IRQ_MASK_SOFTWARE0 (1 << IRQ_NUM_SOFTWARE0)
-#define IRQ_MASK_TIMER1 (1 << IRQ_NUM_TIMER1)
-#define IRQ_MASK_SOFTWARE1 (1 << IRQ_NUM_SOFTWARE1)
-#define IRQ_MASK_SOFTWARE2 (1 << IRQ_NUM_SOFTWARE2)
-#define IRQ_MASK_TIMER2 (1 << IRQ_NUM_TIMER2)
-#define IRQ_MASK_SOFTWARE3 (1 << IRQ_NUM_SOFTWARE3)
-#define IRQ_MASK_TIMER3 (1 << IRQ_NUM_TIMER3)
-#define IRQ_MASK_SOFTWARE4 (1 << IRQ_NUM_SOFTWARE4)
-#define IRQ_MASK_SOFTWARE5 (1 << IRQ_NUM_SOFTWARE5)
-#define IRQ_MASK_EXT_IA (1 << IRQ_NUM_EXT_IA)
-#define IRQ_MASK_EXT_PMC (1 << IRQ_NUM_EXT_PMC)
-#define IRQ_MASK_SOFTWARE6 (1 << IRQ_NUM_SOFTWARE6)
-#define IRQ_MASK_EXT_DMAC0 (1 << IRQ_NUM_EXT_DMAC0)
-#define IRQ_MASK_EXT_DMAC1 (1 << IRQ_NUM_EXT_DMAC1)
-#define IRQ_MASK_EXT_TIMER (1 << IRQ_NUM_EXT_TIMER)
-#define IRQ_MASK_EXT_SSP0 (1 << IRQ_NUM_EXT_SSP0)
-#define IRQ_MASK_EXT_SSP1 (1 << IRQ_NUM_EXT_SSP1)
-#define IRQ_MASK_EXT_SSP2 (1 << IRQ_NUM_EXT_SSP2)
-#define IRQ_MASK_EXT_DMAC2 (1 << IRQ_NUM_EXT_DMAC2)
-
-/* no nested interrupts */
-#define PLATFORM_IRQ_CHILDREN 0
-
-static inline void platform_interrupt_init(void) {}
-
-static inline struct irq_desc *platform_irq_get_parent(uint32_t irq)
-{
- return NULL;
-}
-
-void platform_interrupt_set(int irq);
-void platform_interrupt_clear(uint32_t irq, uint32_t mask);
-uint32_t platform_interrupt_get_enabled(void);
-void platform_interrupt_mask(uint32_t irq, uint32_t mask);
-void platform_interrupt_unmask(uint32_t irq, uint32_t mask);
-
-#endif
diff --git a/src/platform/baytrail/include/platform/mailbox.h b/src/platform/baytrail/include/platform/mailbox.h
deleted file mode 100644
index b03887e..0000000
--- a/src/platform/baytrail/include/platform/mailbox.h
+++ /dev/null
@@ -1,72 +0,0 @@
-/*
- * Copyright (c) 2016, Intel Corporation
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- * * Redistributions of source code must retain the above copyright
- * notice, this list of conditions and the following disclaimer.
- * * Redistributions in binary form must reproduce the above copyright
- * notice, this list of conditions and the following disclaimer in the
- * documentation and/or other materials provided with the distribution.
- * * Neither the name of the Intel Corporation nor the
- * names of its contributors may be used to endorse or promote products
- * derived from this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
- * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
- * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
- * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
- * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
- * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
- * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
- * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
- * POSSIBILITY OF SUCH DAMAGE.
- *
- * Author: Liam Girdwood <liam.r.girdwood@linux.intel.com>
- */
-
-#ifndef __INCLUDE_PLATFORM_MAILBOX__
-#define __INCLUDE_PLATFORM_MAILBOX__
-
-#include <platform/memory.h>
-
-#define MAILBOX_HOST_OFFSET 0x144000
-
-#define MAILBOX_DSPBOX_OFFSET 0x0
-#define MAILBOX_DSPBOX_SIZE 0x400
-#define MAILBOX_DSPBOX_BASE \
- (MAILBOX_BASE + MAILBOX_DSPBOX_OFFSET)
-
-#define MAILBOX_HOSTBOX_OFFSET MAILBOX_DSPBOX_SIZE
-#define MAILBOX_HOSTBOX_SIZE 0x400
-#define MAILBOX_HOSTBOX_BASE \
- (MAILBOX_BASE + MAILBOX_HOSTBOX_OFFSET)
-
-#define MAILBOX_EXCEPTION_OFFSET \
- (MAILBOX_HOSTBOX_SIZE + MAILBOX_DSPBOX_SIZE)
-#define MAILBOX_EXCEPTION_SIZE 0x100
-#define MAILBOX_EXCEPTION_BASE \
- (MAILBOX_BASE + MAILBOX_EXCEPTION_OFFSET)
-
-#define MAILBOX_DEBUG_OFFSET \
- (MAILBOX_EXCEPTION_SIZE + MAILBOX_EXCEPTION_OFFSET)
-#define MAILBOX_DEBUG_SIZE 0x100
-#define MAILBOX_DEBUG_BASE \
- (MAILBOX_BASE + MAILBOX_DEBUG_OFFSET)
-
-#define MAILBOX_STREAM_OFFSET \
- (MAILBOX_DEBUG_SIZE + MAILBOX_DEBUG_OFFSET)
-#define MAILBOX_STREAM_SIZE 0x200
-#define MAILBOX_STREAM_BASE \
- (MAILBOX_BASE + MAILBOX_STREAM_OFFSET)
-
-#define MAILBOX_TRACE_OFFSET \
- (MAILBOX_STREAM_SIZE + MAILBOX_STREAM_OFFSET)
-#define MAILBOX_TRACE_SIZE 0x380
-#define MAILBOX_TRACE_BASE \
- (MAILBOX_BASE + MAILBOX_TRACE_OFFSET)
-
-#endif
diff --git a/src/platform/baytrail/include/platform/memory.h b/src/platform/baytrail/include/platform/memory.h
deleted file mode 100644
index 4a5fb93..0000000
--- a/src/platform/baytrail/include/platform/memory.h
+++ /dev/null
@@ -1,151 +0,0 @@
-/*
- * Copyright (c) 2016, Intel Corporation
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- * * Redistributions of source code must retain the above copyright
- * notice, this list of conditions and the following disclaimer.
- * * Redistributions in binary form must reproduce the above copyright
- * notice, this list of conditions and the following disclaimer in the
- * documentation and/or other materials provided with the distribution.
- * * Neither the name of the Intel Corporation nor the
- * names of its contributors may be used to endorse or promote products
- * derived from this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
- * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
- * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
- * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
- * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
- * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
- * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
- * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
- * POSSIBILITY OF SUCH DAMAGE.
- *
- * Author: Liam Girdwood <liam.r.girdwood@linux.intel.com>
- */
-
-#ifndef __PLATFORM_MEMORY_H__
-#define __PLATFORM_MEMORY_H__
-
-#include <config.h>
-
-/* physical DSP addresses */
-
-#define SHIM_BASE 0xFF340000
-#define SHIM_SIZE 0x00004000
-
-#define IRAM_BASE 0xFF2C0000
-#define IRAM_SIZE 0x00014000
-
-#define DRAM0_BASE 0xFF300000
-#define DRAM0_SIZE 0x00028000
-#define DRAM0_VBASE 0xC0000000
-
-#define MAILBOX_BASE 0xFF344000
-#define MAILBOX_SIZE 0x00001000
-
-#define DMA0_BASE 0xFF298000
-#define DMA0_SIZE 0x00004000
-
-#define DMA1_BASE 0xFF29C000
-#define DMA1_SIZE 0x00004000
-
-#define DMA2_BASE 0xFF294000
-#define DMA2_SIZE 0x00004000
-
-#define SSP0_BASE 0xFF2A0000
-#define SSP0_SIZE 0x00001000
-
-#define SSP1_BASE 0xFF2A1000
-#define SSP1_SIZE 0x00001000
-
-#define SSP2_BASE 0xFF2A2000
-#define SSP2_SIZE 0x00001000
-
-#define SSP3_BASE 0xFF2A4000
-#define SSP3_SIZE 0x00001000
-
-#define SSP4_BASE 0xFF2A5000
-#define SSP4_SIZE 0x00001000
-
-#define SSP5_BASE 0xFF2A6000
-#define SSP5_SIZE 0x00001000
-
-/*
- * The Heap and Stack on Baytrail are organised like this :-
- *
- * +--------------------------------------------------------------------------+
- * | Offset | Region | Size |
- * +---------------------+----------------+-----------------------------------+
- * | DRAM0_BASE | RO Data | SOF_DATA_SIZE |
- * | | Data | |
- * | | BSS | |
- * +---------------------+----------------+-----------------------------------+
- * | HEAP_SYSTEM_BASE | System Heap | HEAP_SYSTEM_SIZE |
- * +---------------------+----------------+-----------------------------------+
- * | HEAP_RUNTIME_BASE | Runtime Heap | HEAP_RUNTIME_SIZE |
- * +---------------------+----------------+-----------------------------------+
- * | HEAP_BUFFER_BASE | Module Buffers | HEAP_BUFFER_SIZE |
- * +---------------------+----------------+-----------------------------------+
- * | SOF_STACK_END | Stack | SOF_STACK_SIZE |
- * +---------------------+----------------+-----------------------------------+
- * | SOF_STACK_BASE | | |
- * +---------------------+----------------+-----------------------------------+
- */
-
-
-/* Heap section sizes for module pool */
-#define HEAP_RT_COUNT8 0
-#define HEAP_RT_COUNT16 64
-#define HEAP_RT_COUNT32 64
-#define HEAP_RT_COUNT64 64
-#define HEAP_RT_COUNT128 64
-#define HEAP_RT_COUNT256 64
-#define HEAP_RT_COUNT512 8
-#define HEAP_RT_COUNT1024 4
-
-/* Heap configuration */
-#define SOF_DATA_SIZE 0x6800
-
-#define HEAP_SYSTEM_BASE (DRAM0_BASE + SOF_DATA_SIZE)
-#define HEAP_SYSTEM_SIZE 0x2000
-
-#define HEAP_RUNTIME_BASE (HEAP_SYSTEM_BASE + HEAP_SYSTEM_SIZE)
-#define HEAP_RUNTIME_SIZE \
- (HEAP_RT_COUNT8 * 8 + HEAP_RT_COUNT16 * 16 + \
- HEAP_RT_COUNT32 * 32 + HEAP_RT_COUNT64 * 64 + \
- HEAP_RT_COUNT128 * 128 + HEAP_RT_COUNT256 * 256 + \
- HEAP_RT_COUNT512 * 512 + HEAP_RT_COUNT1024 * 1024)
-
-#define HEAP_BUFFER_BASE (HEAP_RUNTIME_BASE + HEAP_RUNTIME_SIZE)
-#define HEAP_BUFFER_SIZE \
- (DRAM0_SIZE - HEAP_RUNTIME_SIZE - SOF_STACK_SIZE -\
- HEAP_SYSTEM_SIZE - SOF_DATA_SIZE)
-
-#define HEAP_BUFFER_BLOCK_SIZE 0x180
-#define HEAP_BUFFER_COUNT (HEAP_BUFFER_SIZE / HEAP_BUFFER_BLOCK_SIZE)
-
-#define PLATFORM_HEAP_RUNTIME 1
-#define PLATFORM_HEAP_BUFFER 1
-
-/* Stack configuration */
-#define SOF_STACK_SIZE 0x1000
-#define SOF_STACK_BASE (DRAM0_BASE + DRAM0_SIZE)
-#define SOF_STACK_END (SOF_STACK_BASE - SOF_STACK_SIZE)
-
-/* Vector and literal sizes - not in core-isa.h */
-#define SOF_MEM_VECT_LIT_SIZE 0x4
-#define SOF_MEM_VECT_TEXT_SIZE 0x1c
-#define SOF_MEM_VECT_SIZE (SOF_MEM_VECT_TEXT_SIZE + SOF_MEM_VECT_LIT_SIZE)
-
-#define SOF_MEM_RESET_TEXT_SIZE 0x2e0
-#define SOF_MEM_RESET_LIT_SIZE 0x120
-#define SOF_MEM_VECBASE_LIT_SIZE 0x178
-
-#define SOF_MEM_RO_SIZE 0x8
-
-#endif
diff --git a/src/platform/baytrail/include/platform/platcfg.h b/src/platform/baytrail/include/platform/platcfg.h
deleted file mode 100644
index d41be5a..0000000
--- a/src/platform/baytrail/include/platform/platcfg.h
+++ /dev/null
@@ -1,38 +0,0 @@
-/*
- * Copyright (c) 2018, Intel Corporation
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- * * Redistributions of source code must retain the above copyright
- * notice, this list of conditions and the following disclaimer.
- * * Redistributions in binary form must reproduce the above copyright
- * notice, this list of conditions and the following disclaimer in the
- * documentation and/or other materials provided with the distribution.
- * * Neither the name of the Intel Corporation nor the
- * names of its contributors may be used to endorse or promote products
- * derived from this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
- * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
- * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
- * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
- * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
- * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
- * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
- * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
- * POSSIBILITY OF SUCH DAMAGE.
- *
- * Author: Marcin Maka <marcin.maka@linux.intel.com>
- */
-
-#ifndef __PLATFORM_PLATCFG_H__
-#define __PLATFORM_PLATCFG_H__
-
-#define PLATFORM_CORE_COUNT 1
-
-#define PLATFORM_MASTER_CORE_ID 0
-
-#endif
diff --git a/src/platform/baytrail/include/platform/platform.h b/src/platform/baytrail/include/platform/platform.h
deleted file mode 100644
index 4cd7c50..0000000
--- a/src/platform/baytrail/include/platform/platform.h
+++ /dev/null
@@ -1,115 +0,0 @@
-/*
- * Copyright (c) 2016, Intel Corporation
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- * * Redistributions of source code must retain the above copyright
- * notice, this list of conditions and the following disclaimer.
- * * Redistributions in binary form must reproduce the above copyright
- * notice, this list of conditions and the following disclaimer in the
- * documentation and/or other materials provided with the distribution.
- * * Neither the name of the Intel Corporation nor the
- * names of its contributors may be used to endorse or promote products
- * derived from this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
- * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
- * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
- * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
- * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
- * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
- * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
- * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
- * POSSIBILITY OF SUCH DAMAGE.
- *
- * Author: Liam Girdwood <liam.r.girdwood@linux.intel.com>
- * Keyon Jie <yang.jie@linux.intel.com>
- * Xiuli Pan <xiuli.pan@linux.intel.com>
- */
-
-#ifndef __PLATFORM_PLATFORM_H__
-#define __PLATFORM_PLATFORM_H__
-
-#include <sof/platform.h>
-#include <platform/shim.h>
-#include <platform/interrupt.h>
-#include <uapi/ipc.h>
-
-struct sof;
-
-/* IPC Interrupt */
-#define PLATFORM_IPC_INTERUPT IRQ_NUM_EXT_IA
-
-/* Host page size */
-#define HOST_PAGE_SIZE 4096
-#define PLATFORM_PAGE_TABLE_SIZE 256
-
-/* pipeline IRQ */
-#define PLATFORM_SCHEDULE_IRQ IRQ_NUM_SOFTWARE5
-
-#define PLATFORM_IRQ_TASK_HIGH IRQ_NUM_SOFTWARE4
-#define PLATFORM_IRQ_TASK_MED IRQ_NUM_SOFTWARE3
-#define PLATFORM_IRQ_TASK_LOW IRQ_NUM_SOFTWARE2
-
-#define PLATFORM_SCHEDULE_COST 200
-
-/* maximum preload pipeline depth */
-#define MAX_PRELOAD_SIZE 20
-
-/* DMA treats PHY addresses as host address unless within DSP region */
-#define PLATFORM_HOST_DMA_MASK 0xFF000000
-
-/* Platform stream capabilities */
-#define PLATFORM_MAX_CHANNELS 4
-#define PLATFORM_MAX_STREAMS 5
-
-/* clock source used by scheduler for deadline calculations */
-#define PLATFORM_SCHED_CLOCK CLK_SSP
-
-/* DMA channel drain timeout in microseconds - TODO: caclulate based on topology */
-#define PLATFORM_DMA_TIMEOUT 1333
-
-/* DMA host transfer timeouts in microseconds */
-#define PLATFORM_HOST_DMA_TIMEOUT 50
-
-/* WorkQ window size in microseconds */
-#define PLATFORM_WORKQ_WINDOW 2000
-
-/* platform WorkQ clock */
-#define PLATFORM_WORKQ_CLOCK CLK_SSP
-
-/* local buffer size of DMA tracing */
-#define DMA_TRACE_LOCAL_SIZE HOST_PAGE_SIZE
-
-/* trace bytes flushed during panic */
-#define DMA_FLUSH_TRACE_SIZE (MAILBOX_TRACE_SIZE >> 2)
-
-/* the interval of DMA trace copying */
-#define DMA_TRACE_PERIOD 500000
-
-/*
- * the interval of reschedule DMA trace copying in special case like half
- * fullness of local DMA trace buffer
- */
-#define DMA_TRACE_RESCHEDULE_TIME 5
-
-/* DSP should be idle in this time frame */
-#define PLATFORM_IDLE_TIME 750000
-
-/* DSP default delay in cycles */
-#define PLATFORM_DEFAULT_DELAY 12
-
-/* Platform defined panic code */
-static inline void platform_panic(uint32_t p)
-{
- shim_write(SHIM_IPCDL, p);
- shim_write(SHIM_IPCDH, (SHIM_IPCDH_BUSY | MAILBOX_EXCEPTION_OFFSET));
-}
-
-/* Platform defined trace code */
-#define platform_trace_point(__x) \
- shim_write(SHIM_IPCXL, (__x & 0x3fffffff))
-#endif
diff --git a/src/platform/baytrail/include/platform/pm_runtime.h b/src/platform/baytrail/include/platform/pm_runtime.h
deleted file mode 100644
index 6757e32..0000000
--- a/src/platform/baytrail/include/platform/pm_runtime.h
+++ /dev/null
@@ -1,60 +0,0 @@
-/*
- * Copyright (c) 2018, Intel Corporation
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- * * Redistributions of source code must retain the above copyright
- * notice, this list of conditions and the following disclaimer.
- * * Redistributions in binary form must reproduce the above copyright
- * notice, this list of conditions and the following disclaimer in the
- * documentation and/or other materials provided with the distribution.
- * * Neither the name of the Intel Corporation nor the
- * names of its contributors may be used to endorse or promote products
- * derived from this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
- * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
- * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
- * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
- * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
- * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
- * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
- * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
- * POSSIBILITY OF SUCH DAMAGE.
- *
- * Author: Tomasz Lauda <tomasz.lauda@linux.intel.com>
- */
-
-/**
- * \file platform/baytrail/include/platform/pm_runtime.h
- * \brief Runtime power management header file for Baytrail
- * \author Tomasz Lauda <tomasz.lauda@linux.intel.com>
- */
-
-#ifndef __INCLUDE_PLATFORM_PM_RUNTIME__
-#define __INCLUDE_PLATFORM_PM_RUNTIME__
-
-#include <sof/pm_runtime.h>
-
-/**
- * \brief Initializes platform specific runtime power management.
- * \param[in,out] prd Runtime power management data.
- */
-static inline void platform_pm_runtime_init(struct pm_runtime_data *prd) { }
-
-/**
- * \brief Retrieves platform specific power management resource.
- * \param[in] context Type of power management context.
- */
-static inline void platform_pm_runtime_get(enum pm_runtime_context context) { }
-
-/**
- * \brief Releases platform specific power management resource.
- * \param[in] context Type of power management context.
- */
-static inline void platform_pm_runtime_put(enum pm_runtime_context context) { }
-
-#endif /* __INCLUDE_PLATFORM_PM_RUNTIME__ */
diff --git a/src/platform/baytrail/include/platform/pmc.h b/src/platform/baytrail/include/platform/pmc.h
deleted file mode 100644
index c174f19..0000000
--- a/src/platform/baytrail/include/platform/pmc.h
+++ /dev/null
@@ -1,57 +0,0 @@
-/*
- * Copyright (c) 2016, Intel Corporation
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- * * Redistributions of source code must retain the above copyright
- * notice, this list of conditions and the following disclaimer.
- * * Redistributions in binary form must reproduce the above copyright
- * notice, this list of conditions and the following disclaimer in the
- * documentation and/or other materials provided with the distribution.
- * * Neither the name of the Intel Corporation nor the
- * names of its contributors may be used to endorse or promote products
- * derived from this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
- * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
- * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
- * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
- * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
- * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
- * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
- * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
- * POSSIBILITY OF SUCH DAMAGE.
- *
- * Author: Liam Girdwood <liam.r.girdwood@linux.intel.com>
- */
-
-#ifndef __PLATFORM_PMC_H__
-#define __PLATFORM_PMC_H__
-
-#include <stdint.h>
-#include <config.h>
-
-/* messages */
-#define PMC_DDR_LINK_UP 0xc0 /* LPE req path to DRAM is up */
-#define PMC_DDR_LINK_DOWN 0xc1 /* LPE req path to DRAM is down */
-#define PMC_SET_LPECLK 0xc2 /* LPE req clock change to FR_LAT_REQ */
-
-#ifdef CONFIG_BAYTRAIL
-
-#define PMC_SET_SSP_19M2 0xc5 /* LPE req SSP clock to 19.2MHz w/ PLL*/
-#define PMC_SET_SSP_25M 0xc6 /* LPE req SSP clock to 25MHz w/ XTAL */
-
-#elif CONFIG_CHERRYTRAIL
-
-#define PMC_SET_SSP_25M 0xc5 /* LPE req SSP clock to 25MHz w/ PLL */
-#define PMC_SET_SSP_19M2 0xc6 /* LPE req SSP clock to 19.2MHz w/ XTAL*/
-#endif
-
-int platform_ipc_pmc_init(void);
-int ipc_pmc_send_msg(uint32_t message);
-int pmc_process_msg_queue(void);
-
-#endif
diff --git a/src/platform/baytrail/include/platform/shim.h b/src/platform/baytrail/include/platform/shim.h
deleted file mode 100644
index 61bc6a8..0000000
--- a/src/platform/baytrail/include/platform/shim.h
+++ /dev/null
@@ -1,163 +0,0 @@
-/*
- * Copyright (c) 2016, Intel Corporation
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- * * Redistributions of source code must retain the above copyright
- * notice, this list of conditions and the following disclaimer.
- * * Redistributions in binary form must reproduce the above copyright
- * notice, this list of conditions and the following disclaimer in the
- * documentation and/or other materials provided with the distribution.
- * * Neither the name of the Intel Corporation nor the
- * names of its contributors may be used to endorse or promote products
- * derived from this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
- * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
- * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
- * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
- * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
- * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
- * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
- * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
- * POSSIBILITY OF SUCH DAMAGE.
- *
- * Author: Liam Girdwood <liam.r.girdwood@linux.intel.com>
- */
-
-#ifndef __PLATFORM_SHIM_H__
-#define __PLATFORM_SHIM_H__
-
-#include <platform/memory.h>
-#include <stdint.h>
-
-#define SHIM_CSR 0x00
-#define SHIM_PISR 0x08
-#define SHIM_PISRH 0x0c
-#define SHIM_PIMR 0x10
-#define SHIM_PIMRH 0x14
-#define SHIM_ISRX 0x18
-#define SHIM_ISRD 0x20
-#define SHIM_IMRX 0x28
-#define SHIM_IMRD 0x30
-#define SHIM_IPCXL 0x38 /* IPC IA -> SST */
-#define SHIM_IPCXH 0x3c /* IPC IA -> SST */
-#define SHIM_IPCDL 0x40 /* IPC SST -> IA */
-#define SHIM_IPCDH 0x44 /* IPC SST -> IA */
-#define SHIM_ISRSC 0x48
-#define SHIM_ISRLPESC 0x50
-#define SHIM_IMRSCL 0x58
-#define SHIM_IMRSCH 0x5c
-#define SHIM_IMRLPESC 0x60
-#define SHIM_IPCSCL 0x68
-#define SHIM_IPCSCH 0x6c
-#define SHIM_IPCLPESCL 0x70
-#define SHIM_IPCLPESCH 0x74
-#define SHIM_CLKCTL 0x78
-#define SHIM_FR_LAT_REQ 0x80
-#define SHIM_MISC 0x88
-#define SHIM_EXT_TIMER_CNTLL 0xC0
-#define SHIM_EXT_TIMER_CNTLH 0xC4
-#define SHIM_EXT_TIMER_STAT 0xC8
-#define SHIM_SSP0_DIVL 0xE8
-#define SHIM_SSP0_DIVH 0xEC
-#define SHIM_SSP1_DIVL 0xF0
-#define SHIM_SSP1_DIVH 0xF4
-#define SHIM_SSP2_DIVL 0xF8
-#define SHIM_SSP2_DIVH 0xFC
-#define SHIM_SSP3_DIVL 0x100
-#define SHIM_SSP3_DIVH 0x104
-#define SHIM_SSP4_DIVL 0x108
-#define SHIM_SSP4_DIVH 0x10c
-#define SHIM_SSP5_DIVL 0x110
-#define SHIM_SSP5_DIVH 0x114
-
-#define SHIM_SHIM_BEGIN SHIM_CSR
-#define SHIM_SHIM_END SHIM_HDMC
-
-/* CSR 0x0 */
-#define SHIM_CSR_RST (0x1 << 0)
-#define SHIM_CSR_VECTOR_SEL (0x1 << 1)
-#define SHIM_CSR_STALL (0x1 << 2)
-#define SHIM_CSR_PWAITMODE (0x1 << 3)
-
-/* PISR */
-#define SHIM_PISR_EXT_TIMER (1 << 10)
-
-/* ISRX 0x18 */
-#define SHIM_ISRX_BUSY (0x1 << 1)
-#define SHIM_ISRX_DONE (0x1 << 0)
-
-/* ISRD / ISD */
-#define SHIM_ISRD_BUSY (0x1 << 1)
-#define SHIM_ISRD_DONE (0x1 << 0)
-
-/* IMRX / IMC */
-#define SHIM_IMRX_BUSY (0x1 << 1)
-#define SHIM_IMRX_DONE (0x1 << 0)
-
-/* IMRD / IMD */
-#define SHIM_IMRD_DONE (0x1 << 0)
-#define SHIM_IMRD_BUSY (0x1 << 1)
-#define SHIM_IMRD_SSP0 (0x1 << 16)
-#define SHIM_IMRD_DMAC0 (0x1 << 21)
-#define SHIM_IMRD_DMAC1 (0x1 << 22)
-#define SHIM_IMRD_DMAC (SHIM_IMRD_DMAC0 | SHIM_IMRD_DMAC1)
-
-/* IPCX / IPCCH */
-#define SHIM_IPCXH_DONE (0x1 << 30)
-#define SHIM_IPCXH_BUSY (0x1 << 31)
-
-/* IPCDH */
-#define SHIM_IPCDH_DONE (0x1 << 30)
-#define SHIM_IPCDH_BUSY (0x1 << 31)
-
-/* ISRLPESC */
-#define SHIM_ISRLPESC_DONE (0x1 << 0)
-#define SHIM_ISRLPESC_BUSY (0x1 << 1)
-
-/* IMRLPESC */
-#define SHIM_IMRLPESC_BUSY (0x1 << 1)
-#define SHIM_IMRLPESC_DONE (0x1 << 0)
-
-/* IPCSCH */
-#define SHIM_IPCSCH_DONE (0x1 << 30)
-#define SHIM_IPCSCH_BUSY (0x1 << 31)
-
-/* IPCLPESCH */
-#define SHIM_IPCLPESCH_DONE (0x1 << 30)
-#define SHIM_IPCLPESCH_BUSY (0x1 << 31)
-
-/* CLKCTL */
-#define SHIM_CLKCTL_SSP2_EN (1 << 18)
-#define SHIM_CLKCTL_SSP1_EN (1 << 17)
-#define SHIM_CLKCTL_SSP0_EN (1 << 16)
-#define SHIM_CLKCTL_FRCHNGGO (1 << 5)
-#define SHIM_CLKCTL_FRCHNGACK (1 << 4)
-
-/* SHIM_FR_LAT_REQ */
-#define SHIM_FR_LAT_CLK_MASK 0x7
-
-/* ext timer */
-#define SHIM_EXT_TIMER_RUN (1 << 31)
-#define SHIM_EXT_TIMER_CLEAR (1 << 30)
-
-/* SSP M/N */
-#define SHIM_SSP_DIV_BYP (1 << 31)
-#define SHIM_SSP_DIV_ENA (1 << 30)
-#define SHIM_SSP_DIV_UPD (1 << 29)
-
-static inline uint32_t shim_read(uint32_t reg)
-{
- return *((volatile uint32_t*)(SHIM_BASE + reg));
-}
-
-static inline void shim_write(uint32_t reg, uint32_t val)
-{
- *((volatile uint32_t*)(SHIM_BASE + reg)) = val;
-}
-
-#endif
diff --git a/src/platform/baytrail/include/platform/timer.h b/src/platform/baytrail/include/platform/timer.h
deleted file mode 100644
index 2801bb5..0000000
--- a/src/platform/baytrail/include/platform/timer.h
+++ /dev/null
@@ -1,69 +0,0 @@
-/*
- * Copyright (c) 2016, Intel Corporation
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- * * Redistributions of source code must retain the above copyright
- * notice, this list of conditions and the following disclaimer.
- * * Redistributions in binary form must reproduce the above copyright
- * notice, this list of conditions and the following disclaimer in the
- * documentation and/or other materials provided with the distribution.
- * * Neither the name of the Intel Corporation nor the
- * names of its contributors may be used to endorse or promote products
- * derived from this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
- * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
- * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
- * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
- * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
- * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
- * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
- * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
- * POSSIBILITY OF SUCH DAMAGE.
- *
- * Author: Liam Girdwood <liam.r.girdwood@linux.intel.com>
- */
-
-
-#ifndef __PLATFORM_TIMER_H__
-#define __PLATFORM_TIMER_H__
-
-#include <stdint.h>
-#include <sof/timer.h>
-#include <platform/interrupt.h>
-
-#define TIMER_COUNT 4
-
-/* timer numbers must use associated IRQ number */
-#define TIMER0 IRQ_NUM_TIMER1
-#define TIMER1 IRQ_NUM_TIMER2
-#define TIMER2 IRQ_NUM_TIMER3
-#define TIMER3 IRQ_NUM_EXT_TIMER
-
-struct comp_dev;
-struct sof_ipc_stream_posn;
-
-extern struct timer *platform_timer;
-
-int platform_timer_set(struct timer *timer, uint64_t ticks);
-void platform_timer_clear(struct timer *timer);
-uint64_t platform_timer_get(struct timer *timer);
-void platform_timer_start(struct timer *timer);
-void platform_timer_stop(struct timer *timer);
-
-/* get timestamp for host stream DMA position */
-void platform_host_timestamp(struct comp_dev *host,
- struct sof_ipc_stream_posn *posn);
-
-/* get timestamp for DAI stream DMA position */
-void platform_dai_timestamp(struct comp_dev *dai,
- struct sof_ipc_stream_posn *posn);
-
-/* get current wallclock for componnent */
-void platform_dai_wallclock(struct comp_dev *dai, uint64_t *wallclock);
-
-#endif
diff --git a/src/platform/baytrail/ipc.c b/src/platform/baytrail/ipc.c
deleted file mode 100644
index 3a7ad9f..0000000
--- a/src/platform/baytrail/ipc.c
+++ /dev/null
@@ -1,39 +0,0 @@
-/*
- * Copyright (c) 2016, Intel Corporation
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- * * Redistributions of source code must retain the above copyright
- * notice, this list of conditions and the following disclaimer.
- * * Redistributions in binary form must reproduce the above copyright
- * notice, this list of conditions and the following disclaimer in the
- * documentation and/or other materials provided with the distribution.
- * * Neither the name of the Intel Corporation nor the
- * names of its contributors may be used to endorse or promote products
- * derived from this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
- * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
- * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
- * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
- * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
- * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
- * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
- * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
- * POSSIBILITY OF SUCH DAMAGE.
- *
- * Author: Liam Girdwood <liam.r.girdwood@linux.intel.com>
- */
-
-#include <platform/memory.h>
-#include <platform/shim.h>
-#include <platform/mailbox.h>
-
-int platform_boot_complete(uint32_t boot_message)
-{
- shim_write(SHIM_IPCD, SST_IPCD_BUSY | (boot_message &0x3fffffff));
- return 0;
-}
diff --git a/src/platform/baytrail/memory.c b/src/platform/baytrail/memory.c
deleted file mode 100644
index e1eb7cf..0000000
--- a/src/platform/baytrail/memory.c
+++ /dev/null
@@ -1,89 +0,0 @@
-/*
- * Copyright (c) 2018, Intel Corporation
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- * * Redistributions of source code must retain the above copyright
- * notice, this list of conditions and the following disclaimer.
- * * Redistributions in binary form must reproduce the above copyright
- * notice, this list of conditions and the following disclaimer in the
- * documentation and/or other materials provided with the distribution.
- * * Neither the name of the Intel Corporation nor the
- * names of its contributors may be used to endorse or promote products
- * derived from this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
- * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
- * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
- * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
- * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
- * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
- * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
- * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
- * POSSIBILITY OF SUCH DAMAGE.
- *
- * Author: Liam Girdwood <liam.r.girdwood@linux.intel.com>
- */
-
-#include <sof/alloc.h>
-
-/* Heap blocks for modules */
-static struct block_hdr mod_block16[HEAP_RT_COUNT16];
-static struct block_hdr mod_block32[HEAP_RT_COUNT32];
-static struct block_hdr mod_block64[HEAP_RT_COUNT64];
-static struct block_hdr mod_block128[HEAP_RT_COUNT128];
-static struct block_hdr mod_block256[HEAP_RT_COUNT256];
-static struct block_hdr mod_block512[HEAP_RT_COUNT512];
-static struct block_hdr mod_block1024[HEAP_RT_COUNT1024];
-
-/* Heap memory map for modules */
-static struct block_map rt_heap_map[] = {
- BLOCK_DEF(16, HEAP_RT_COUNT16, mod_block16),
- BLOCK_DEF(32, HEAP_RT_COUNT32, mod_block32),
- BLOCK_DEF(64, HEAP_RT_COUNT64, mod_block64),
- BLOCK_DEF(128, HEAP_RT_COUNT128, mod_block128),
- BLOCK_DEF(256, HEAP_RT_COUNT256, mod_block256),
- BLOCK_DEF(512, HEAP_RT_COUNT512, mod_block512),
- BLOCK_DEF(1024, HEAP_RT_COUNT1024, mod_block1024),
-};
-
-/* Heap blocks for buffers */
-static struct block_hdr buf_block[HEAP_BUFFER_COUNT];
-
-/* Heap memory map for buffers */
-static struct block_map buf_heap_map[] = {
- BLOCK_DEF(HEAP_BUFFER_BLOCK_SIZE, HEAP_BUFFER_COUNT, buf_block),
-};
-
-struct mm memmap = {
- .system = {
- .heap = HEAP_SYSTEM_BASE,
- .size = HEAP_SYSTEM_SIZE,
- .info = {.free = HEAP_SYSTEM_SIZE,},
- .caps = SOF_MEM_CAPS_RAM | SOF_MEM_CAPS_CACHE |
- SOF_MEM_CAPS_DMA,
- },
- .runtime[0] = {
- .blocks = ARRAY_SIZE(rt_heap_map),
- .map = rt_heap_map,
- .heap = HEAP_RUNTIME_BASE,
- .size = HEAP_RUNTIME_SIZE,
- .info = {.free = HEAP_RUNTIME_SIZE,},
- .caps = SOF_MEM_CAPS_RAM | SOF_MEM_CAPS_CACHE |
- SOF_MEM_CAPS_DMA,
- },
- .buffer[0] = {
- .blocks = ARRAY_SIZE(buf_heap_map),
- .map = buf_heap_map,
- .heap = HEAP_BUFFER_BASE,
- .size = HEAP_BUFFER_SIZE,
- .info = {.free = HEAP_BUFFER_SIZE,},
- .caps = SOF_MEM_CAPS_RAM | SOF_MEM_CAPS_CACHE |
- SOF_MEM_CAPS_DMA,
- },
- .total = {.free = HEAP_SYSTEM_SIZE + HEAP_RUNTIME_SIZE +
- HEAP_BUFFER_SIZE,},
-};
diff --git a/src/platform/baytrail/platform.c b/src/platform/baytrail/platform.c
deleted file mode 100644
index fb08cf6..0000000
--- a/src/platform/baytrail/platform.c
+++ /dev/null
@@ -1,405 +0,0 @@
-/*
- * Copyright (c) 2016, Intel Corporation
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- * * Redistributions of source code must retain the above copyright
- * notice, this list of conditions and the following disclaimer.
- * * Redistributions in binary form must reproduce the above copyright
- * notice, this list of conditions and the following disclaimer in the
- * documentation and/or other materials provided with the distribution.
- * * Neither the name of the Intel Corporation nor the
- * names of its contributors may be used to endorse or promote products
- * derived from this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
- * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
- * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
- * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
- * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
- * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
- * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
- * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
- * POSSIBILITY OF SUCH DAMAGE.
- *
- * Author: Liam Girdwood <liam.r.girdwood@linux.intel.com>
- * Keyon Jie <yang.jie@linux.intel.com>
- */
-
-#include <platform/memory.h>
-#include <platform/mailbox.h>
-#include <platform/shim.h>
-#include <platform/dma.h>
-#include <platform/clk.h>
-#include <platform/timer.h>
-#include <platform/pmc.h>
-#include <uapi/ipc.h>
-#include <sof/mailbox.h>
-#include <sof/dai.h>
-#include <sof/dma.h>
-#include <sof/interrupt.h>
-#include <sof/sof.h>
-#include <sof/work.h>
-#include <sof/clock.h>
-#include <sof/ipc.h>
-#include <sof/trace.h>
-#include <sof/agent.h>
-#include <sof/dma-trace.h>
-#include <sof/audio/component.h>
-#include <config.h>
-#include <string.h>
-#include <version.h>
-
-static const struct sof_ipc_fw_ready ready = {
- .hdr = {
- .cmd = SOF_IPC_FW_READY,
- .size = sizeof(struct sof_ipc_fw_ready),
- },
- /* dspbox is for DSP initiated IPC, hostbox is for host initiated IPC */
- .version = {
- .build = SOF_BUILD,
- .minor = SOF_MINOR,
- .major = SOF_MAJOR,
- .date = __DATE__,
- .time = __TIME__,
- .tag = SOF_TAG,
- },
- /* TODO: add capabilities */
-};
-
-#define NUM_BYT_WINDOWS 6
-static const struct sof_ipc_window sram_window = {
- .ext_hdr = {
- .hdr.cmd = SOF_IPC_FW_READY,
- .hdr.size = sizeof(struct sof_ipc_window) +
- sizeof(struct sof_ipc_window_elem) * NUM_BYT_WINDOWS,
- .type = SOF_IPC_EXT_WINDOW,
- },
- .num_windows = NUM_BYT_WINDOWS,
- .window = {
- {
- .type = SOF_IPC_REGION_UPBOX,
- .id = 0, /* map to host window 0 */
- .flags = 0, // TODO: set later
- .size = MAILBOX_DSPBOX_SIZE,
- .offset = MAILBOX_DSPBOX_OFFSET,
- },
- {
- .type = SOF_IPC_REGION_DOWNBOX,
- .id = 0, /* map to host window 0 */
- .flags = 0, // TODO: set later
- .size = MAILBOX_HOSTBOX_SIZE,
- .offset = MAILBOX_HOSTBOX_OFFSET,
- },
- {
- .type = SOF_IPC_REGION_DEBUG,
- .id = 0, /* map to host window 0 */
- .flags = 0, // TODO: set later
- .size = MAILBOX_DEBUG_SIZE,
- .offset = MAILBOX_DEBUG_OFFSET,
- },
- {
- .type = SOF_IPC_REGION_TRACE,
- .id = 0, /* map to host window 0 */
- .flags = 0, // TODO: set later
- .size = MAILBOX_TRACE_SIZE,
- .offset = MAILBOX_TRACE_OFFSET,
- },
- {
- .type = SOF_IPC_REGION_STREAM,
- .id = 0, /* map to host window 0 */
- .flags = 0, // TODO: set later
- .size = MAILBOX_STREAM_SIZE,
- .offset = MAILBOX_STREAM_OFFSET,
- },
- {
- .type = SOF_IPC_REGION_EXCEPTION,
- .id = 0, /* map to host window 0 */
- .flags = 0, // TODO: set later
- .size = MAILBOX_EXCEPTION_SIZE,
- .offset = MAILBOX_EXCEPTION_OFFSET,
- },
- },
-};
-
-static struct work_queue_timesource platform_generic_queue = {
- .timer = {
- .id = TIMER3, /* external timer */
- .irq = IRQ_NUM_EXT_TIMER,
- },
- .clk = PLATFORM_WORKQ_CLOCK,
- .notifier = NOTIFIER_ID_SSP_FREQ,
- .timer_set = platform_timer_set,
- .timer_clear = platform_timer_clear,
- .timer_get = platform_timer_get,
-};
-
-struct timer *platform_timer = &platform_generic_queue.timer;
-
-int platform_boot_complete(uint32_t boot_message)
-{
- uint64_t outbox = MAILBOX_HOST_OFFSET >> 3;
-
- mailbox_dspbox_write(0, &ready, sizeof(ready));
- mailbox_dspbox_write(sizeof(ready), &sram_window,
- sram_window.ext_hdr.hdr.size);
-
- /* now interrupt host to tell it we are done booting */
- shim_write(SHIM_IPCDL, SOF_IPC_FW_READY | outbox);
- shim_write(SHIM_IPCDH, SHIM_IPCDH_BUSY);
-
- /* boot now complete so we can relax the CPU */
- /* For now skip this to gain more processing performance
- * for SRC component.
- */
- /* clock_set_freq(CLK_CPU, CLK_DEFAULT_CPU_HZ); */
-
- return 0;
-}
-
-/* clear mask in PISR, bits are W1C in docs but some bits need preserved ?? */
-void platform_interrupt_clear(uint32_t irq, uint32_t mask)
-{
- switch (irq) {
- case IRQ_NUM_EXT_SSP0:
- shim_write(SHIM_PISR, mask << 3);
- interrupt_clear(irq);
- break;
- case IRQ_NUM_EXT_SSP1:
- shim_write(SHIM_PISR, mask << 4);
- interrupt_clear(irq);
- break;
- case IRQ_NUM_EXT_SSP2:
- shim_write(SHIM_PISR, mask << 5);
- interrupt_clear(irq);
- break;
- case IRQ_NUM_EXT_DMAC0:
- shim_write(SHIM_PISR, mask << 16);
- interrupt_clear(irq);
- break;
- case IRQ_NUM_EXT_DMAC1:
- shim_write(SHIM_PISR, mask << 24);
- interrupt_clear(irq);
- break;
-#if defined CONFIG_CHERRYTRAIL
- case IRQ_NUM_EXT_DMAC2:
- shim_write(SHIM_PISRH, mask << 0);
- interrupt_clear(irq);
- break;
- case IRQ_NUM_EXT_SSP3:
- shim_write(SHIM_PISRH, mask << 8);
- interrupt_clear(irq);
- break;
- case IRQ_NUM_EXT_SSP4:
- shim_write(SHIM_PISRH, mask << 9);
- interrupt_clear(irq);
- break;
- case IRQ_NUM_EXT_SSP5:
- shim_write(SHIM_PISRH, mask << 10);
- interrupt_clear(irq);
- break;
-#endif
- default:
- break;
- }
-}
-
-/* TODO: expand this to 64 bit - should we just return mask of IRQ numbers */
-uint32_t platform_interrupt_get_enabled(void)
-{
- return shim_read(SHIM_PIMR);
-}
-
-void platform_interrupt_mask(uint32_t irq, uint32_t mask)
-{
- switch (irq) {
- case IRQ_NUM_EXT_SSP0:
- shim_write(SHIM_PIMR, mask << 3);
- break;
- case IRQ_NUM_EXT_SSP1:
- shim_write(SHIM_PIMR, mask << 4);
- break;
- case IRQ_NUM_EXT_SSP2:
- shim_write(SHIM_PIMR, mask << 5);
- break;
- case IRQ_NUM_EXT_DMAC0:
- shim_write(SHIM_PIMR, mask << 16);
- break;
- case IRQ_NUM_EXT_DMAC1:
- shim_write(SHIM_PIMR, mask << 24);
- break;
-#if defined CONFIG_CHERRYTRAIL
- case IRQ_NUM_EXT_DMAC2:
- shim_write(SHIM_PIMRH, mask << 8);
- break;
- case IRQ_NUM_EXT_SSP3:
- shim_write(SHIM_PIMRH, mask << 0);
- break;
- case IRQ_NUM_EXT_SSP4:
- shim_write(SHIM_PIMRH, mask << 1);
- break;
- case IRQ_NUM_EXT_SSP5:
- shim_write(SHIM_PIMRH, mask << 2);
- break;
-#endif
- default:
- break;
- }
-}
-
-void platform_interrupt_unmask(uint32_t irq, uint32_t mask)
-{
- switch (irq) {
- case IRQ_NUM_EXT_SSP0:
- shim_write(SHIM_PIMR, shim_read(SHIM_PIMR) & ~(mask << 3));
- break;
- case IRQ_NUM_EXT_SSP1:
- shim_write(SHIM_PIMR, shim_read(SHIM_PIMR) & ~(mask << 4));
- break;
- case IRQ_NUM_EXT_SSP2:
- shim_write(SHIM_PIMR, shim_read(SHIM_PIMR) & ~(mask << 5));
- break;
- case IRQ_NUM_EXT_DMAC0:
- shim_write(SHIM_PIMR, shim_read(SHIM_PIMR) & ~(mask << 16));
- break;
- case IRQ_NUM_EXT_DMAC1:
- shim_write(SHIM_PIMR, shim_read(SHIM_PIMR) & ~(mask << 24));
- break;
-#if defined CONFIG_CHERRYTRAIL
- case IRQ_NUM_EXT_DMAC2:
- shim_write(SHIM_PIMRH, shim_read(SHIM_PIMRH) & ~(mask << 8));
- break;
- case IRQ_NUM_EXT_SSP3:
- shim_write(SHIM_PIMRH, shim_read(SHIM_PIMRH) & ~(mask << 0));
- break;
- case IRQ_NUM_EXT_SSP4:
- shim_write(SHIM_PIMRH, shim_read(SHIM_PIMRH) & ~(mask << 1));
- break;
- case IRQ_NUM_EXT_SSP5:
- shim_write(SHIM_PIMRH, shim_read(SHIM_PIMRH) & ~(mask << 2));
- break;
-#endif
- default:
- break;
- }
-}
-
-int platform_init(struct sof *sof)
-{
-#if defined CONFIG_BAYTRAIL
- struct dai *ssp0;
- struct dai *ssp1;
- struct dai *ssp2;
-#elif defined CONFIG_CHERRYTRAIL
- struct dai *ssp0;
- struct dai *ssp1;
- struct dai *ssp2;
- struct dai *ssp3;
- struct dai *ssp4;
- struct dai *ssp5;
-#else
-#error Undefined platform
-#endif
- int ret;
-
- trace_point(TRACE_BOOT_PLATFORM_MBOX);
-
- /* clear mailbox for early trace and debug */
- bzero((void *)MAILBOX_BASE, IPC_MAX_MAILBOX_BYTES);
-
- trace_point(TRACE_BOOT_PLATFORM_SHIM);
-
- /* configure the shim */
-#if defined CONFIG_BAYTRAIL
- shim_write(SHIM_MISC, shim_read(SHIM_MISC) | 0x0000000e);
-#elif defined CONFIG_CHERRYTRAIL
- shim_write(SHIM_MISC, shim_read(SHIM_MISC) | 0x00000e0e);
-#endif
-
- trace_point(TRACE_BOOT_PLATFORM_PMC);
-
- /* init PMC IPC */
- platform_ipc_pmc_init();
-
- trace_point(TRACE_BOOT_PLATFORM_CLOCK);
- init_platform_clocks();
-
- /* init work queues and clocks */
- trace_point(TRACE_BOOT_SYS_WORK);
- init_system_workq(&platform_generic_queue);
-
- trace_point(TRACE_BOOT_PLATFORM_TIMER);
- platform_timer_start(platform_timer);
-
- /* init the system agent */
- sa_init(sof);
-
- /* Set CPU to default frequency for booting */
- trace_point(TRACE_BOOT_SYS_CPU_FREQ);
- clock_set_freq(CLK_CPU, CLK_MAX_CPU_HZ);
-
- trace_point(TRACE_BOOT_PLATFORM_SSP_FREQ);
-
- /* set SSP clock to 19.2M */
- clock_set_freq(CLK_SSP, 19200000);
-
- /* initialise the host IPC mechanisms */
- trace_point(TRACE_BOOT_PLATFORM_IPC);
- ipc_init(sof);
-
- /* init DMACs */
- trace_point(TRACE_BOOT_PLATFORM_DMA);
- ret = dmac_init();
- if (ret < 0)
- return -ENODEV;
-
- /* mask SSP 0 - 2 interrupts */
- shim_write(SHIM_PIMR, shim_read(SHIM_PIMR) | 0x00000038);
-
-#if defined CONFIG_CHERRYTRAIL
- /* mask SSP 3 - 5 interrupts */
- shim_write(SHIM_PIMRH, shim_read(SHIM_PIMRH) | 0x00000700);
-#endif
-
- /* init SSP ports */
- trace_point(TRACE_BOOT_PLATFORM_SSP);
- ssp0 = dai_get(SOF_DAI_INTEL_SSP, 0);
- if (ssp0 == NULL)
- return -ENODEV;
- dai_probe(ssp0);
-
- ssp1 = dai_get(SOF_DAI_INTEL_SSP, 1);
- if (ssp1 == NULL)
- return -ENODEV;
- dai_probe(ssp1);
-
- ssp2 = dai_get(SOF_DAI_INTEL_SSP, 2);
- if (ssp2 == NULL)
- return -ENODEV;
- dai_probe(ssp2);
-
-#if defined CONFIG_CHERRYTRAIL
- ssp3 = dai_get(SOF_DAI_INTEL_SSP, 3);
- if (ssp3 == NULL)
- return -ENODEV;
- dai_probe(ssp3);
-
- ssp4 = dai_get(SOF_DAI_INTEL_SSP, 4);
- if (ssp4 == NULL)
- return -ENODEV;
- dai_probe(ssp4);
-
- ssp5 = dai_get(SOF_DAI_INTEL_SSP, 5);
- if (ssp5 == NULL)
- return -ENODEV;
- dai_probe(ssp5);
-#endif
-
- /* Initialize DMA for Trace*/
- dma_trace_init_complete(sof->dmat);
-
- return 0;
-}
diff --git a/src/platform/baytrail/timer.c b/src/platform/baytrail/timer.c
deleted file mode 100644
index 835b2ee..0000000
--- a/src/platform/baytrail/timer.c
+++ /dev/null
@@ -1,232 +0,0 @@
-/*
- * Copyright (c) 2016, Intel Corporation
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- * * Redistributions of source code must retain the above copyright
- * notice, this list of conditions and the following disclaimer.
- * * Redistributions in binary form must reproduce the above copyright
- * notice, this list of conditions and the following disclaimer in the
- * documentation and/or other materials provided with the distribution.
- * * Neither the name of the Intel Corporation nor the
- * names of its contributors may be used to endorse or promote products
- * derived from this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
- * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
- * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
- * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
- * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
- * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
- * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
- * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
- * POSSIBILITY OF SUCH DAMAGE.
- *
- * Author: Liam Girdwood <liam.r.girdwood@linux.intel.com>
- *
- * Baytrail external timer control.
- */
-
-#include <platform/timer.h>
-#include <platform/shim.h>
-#include <platform/interrupt.h>
-#include <sof/debug.h>
-#include <sof/audio/component.h>
-#include <stdint.h>
-
-struct timer_data {
- void (*handler2)(void *arg);
- void *arg2;
-};
-
-static struct timer_data xtimer[1] = {};
-
-static void platform_timer_64_handler(void *arg)
-{
- struct timer *timer = arg;
- struct timer_data *tdata = timer->timer_data;
- uint32_t timeout;
-
- /* get timeout value - will tell us timeout reason */
- timeout = shim_read(SHIM_EXT_TIMER_CNTLL);
-
- /* we don't use the timer clear bit as we only need to clear the ISR */
- shim_write(SHIM_PISR, SHIM_PISR_EXT_TIMER);
-
- /* is this a 32 bit rollover ? */
- if (timeout == 1) {
- /* roll over the timer */
- timer->hitime++;
- } else {
- /* no roll over, run the handler */
- tdata->handler2(tdata->arg2);
- }
-
- /* get next timeout value */
- if (timer->hitimeout == timer->hitime) {
- /* timeout is in this 32 bit period */
- timeout = timer->lowtimeout;
- } else {
- /* timeout is in another 32 bit period */
- timeout = 1;
- }
-
- /* set new value and run */
- shim_write(SHIM_EXT_TIMER_CNTLH, SHIM_EXT_TIMER_RUN);
- shim_write(SHIM_EXT_TIMER_CNTLL, timeout);
-}
-
-void platform_timer_start(struct timer *timer)
-{
- /* run timer */
- shim_write(SHIM_EXT_TIMER_CNTLH, SHIM_EXT_TIMER_RUN);
- shim_write(SHIM_EXT_TIMER_CNTLL, 1);
-}
-
-/* this seems to stop rebooting with RTD3 ???? */
-void platform_timer_stop(struct timer *timer)
-{
- /* run timer */
- shim_write(SHIM_EXT_TIMER_CNTLL, 0);
- shim_write(SHIM_EXT_TIMER_CNTLH, SHIM_EXT_TIMER_CLEAR);
-}
-
-int platform_timer_set(struct timer *timer, uint64_t ticks)
-{
- uint32_t time = 1;
- uint32_t hitimeout = ticks >> 32;
- uint32_t flags;
-
- /* a tick value of 0 will not generate an IRQ */
- /* value of 1 represents rollover */
- if ((ticks & 0xffffffff) < 0x2)
- ticks += 2;
-
- flags = arch_interrupt_global_disable();
-
- /* same hi 64 bit context as ticks ? */
- if (hitimeout < timer->hitime) {
- /* cant be in the past */
- arch_interrupt_global_enable(flags);
- return -EINVAL;
- } else {
- /* set for checking at next timeout */
- time = ticks;
- timer->hitimeout = hitimeout;
- timer->lowtimeout = ticks;
- }
-
- /* set new value and run */
- shim_write(SHIM_EXT_TIMER_CNTLH, SHIM_EXT_TIMER_RUN);
- shim_write(SHIM_EXT_TIMER_CNTLL, time);
-
- arch_interrupt_global_enable(flags);
-
- return 0;
-}
-
-void platform_timer_clear(struct timer *timer)
-{
- /* we don't use the timer clear bit as we only need to clear the ISR */
- shim_write(SHIM_PISR, SHIM_PISR_EXT_TIMER);
-}
-
-uint64_t platform_timer_get(struct timer *timer)
-{
- uint64_t time;
- uint32_t flags;
- uint32_t low;
- uint32_t high;
-
- flags = arch_interrupt_global_disable();
-
- /* read low 32 bits */
- low = shim_read(SHIM_EXT_TIMER_STAT);
-
- /* check and see whether 32bit IRQ is pending for timer */
- if (arch_interrupt_get_status() & IRQ_MASK_EXT_TIMER &&
- shim_read(SHIM_EXT_TIMER_CNTLL) == 1) {
- /* yes, overflow has occurred but handler has not run */
- high = timer->hitime + 1;
- } else {
- /* no overflow */
- high = timer->hitime;
- }
-
- time = ((uint64_t)high << 32) | low;
-
- arch_interrupt_global_enable(flags);
-
- return time;
-}
-
-/* get timestamp for host stream DMA position */
-void platform_host_timestamp(struct comp_dev *host,
- struct sof_ipc_stream_posn *posn)
-{
- int err;
-
- /* get host position */
- err = comp_position(host, posn);
- if (err == 0)
- posn->flags |= SOF_TIME_HOST_VALID | SOF_TIME_HOST_64;
-}
-
-/* get timestamp for DAI stream DMA position */
-void platform_dai_timestamp(struct comp_dev *dai,
- struct sof_ipc_stream_posn *posn)
-{
- int err;
-
- /* get DAI position */
- err = comp_position(dai, posn);
- if (err == 0)
- posn->flags |= SOF_TIME_DAI_VALID;
-
- /* get SSP wallclock - DAI sets this to stream start value */
- posn->wallclock = platform_timer_get(platform_timer) - posn->wallclock;
- posn->flags |= SOF_TIME_WALL_VALID | SOF_TIME_WALL_64;
-}
-
-/* get current wallclock for component */
-void platform_dai_wallclock(struct comp_dev *dai, uint64_t *wallclock)
-{
- /* only 1 wallclock on BYT */
- *wallclock = platform_timer_get(platform_timer);
-}
-
-static int platform_timer_register(struct timer *timer,
- void(*handler)(void *arg), void *arg)
-{
- struct timer_data *tdata = &xtimer[0];
- uint32_t flags;
- int ret;
-
- flags = arch_interrupt_global_disable();
- tdata->handler2 = handler;
- tdata->arg2 = arg;
- timer->timer_data = tdata;
- timer->hitime = 0;
- timer->hitimeout = 0;
- ret = arch_interrupt_register(timer->id, platform_timer_64_handler, timer);
- arch_interrupt_global_enable(flags);
-
- return ret;
-}
-
-int timer_register(struct timer *timer, void(*handler)(void *arg), void *arg)
-{
- switch (timer->id) {
- case TIMER0:
- case TIMER1:
- case TIMER2:
- return arch_timer_register(timer, handler, arg);
- case TIMER3:
- return platform_timer_register(timer, handler, arg);
- default:
- return -EINVAL;
- }
-}
diff --git a/src/platform/cannonlake/Makefile.am b/src/platform/cannonlake/Makefile.am
deleted file mode 100644
index d352a54..0000000
--- a/src/platform/cannonlake/Makefile.am
+++ /dev/null
@@ -1,38 +0,0 @@
-SUBDIRS = include
-
-EXTRA_DIST = \
- cannonlake.x.in \
- boot_ldr.x.in
-
-noinst_LTLIBRARIES = libplatform.la
-
-libplatform_la_LIBADD = ../intel/cavs/libcavsplatform.la
-
-libplatform_la_SOURCES =
-
-libplatform_la_CFLAGS = \
- $(AM_CFLAGS) \
- $(ARCH_CFLAGS) \
- $(ARCH_INCDIR) \
- $(PLATFORM_INCDIR) \
- $(SOF_INCDIR)
-
-noinst_PROGRAMS = module boot_module
-
-module_SOURCES = \
- base_module.c
-
-module_CFLAGS = \
- $(AM_CFLAGS) \
- $(ARCH_INCDIR) \
- $(PLATFORM_INCDIR) \
- $(SOF_INCDIR)
-
-boot_module_SOURCES = \
- boot_module.c
-
-boot_module_CFLAGS = \
- $(AM_CFLAGS) \
- $(ARCH_INCDIR) \
- $(PLATFORM_INCDIR) \
- $(SOF_INCDIR)
diff --git a/src/platform/cannonlake/base_module.c b/src/platform/cannonlake/base_module.c
deleted file mode 100644
index 9f3cb9c..0000000
--- a/src/platform/cannonlake/base_module.c
+++ /dev/null
@@ -1,54 +0,0 @@
-/*
- * Copyright (c) 2018, Intel Corporation
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- * * Redistributions of source code must retain the above copyright
- * notice, this list of conditions and the following disclaimer.
- * * Redistributions in binary form must reproduce the above copyright
- * notice, this list of conditions and the following disclaimer in the
- * documentation and/or other materials provided with the distribution.
- * * Neither the name of the Intel Corporation nor the
- * names of its contributors may be used to endorse or promote products
- * derived from this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
- * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
- * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
- * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
- * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
- * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
- * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
- * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
- * POSSIBILITY OF SUCH DAMAGE.
- *
- * Author: Liam Girdwood <liam.r.girdwood@linux.intel.com>
- */
-
-#include <uapi/manifest.h>
-#include <platform/memory.h>
-
-/*
- * Each module has an entry in the FW manifest header. This is NOT part of
- * the SOF executable image but is inserted by object copy as a ELF section
- * for parsing by rimage (to genrate the manifest).
- */
-struct sof_man_module_manifest cnl_manifest = {
- .module = {
- .name = "BASEFW",
- .uuid = {0x32, 0x8c, 0x39, 0x0e, 0xde, 0x5a, 0x4b, 0xba,
- 0x93, 0xb1, 0xc5, 0x04, 0x32, 0x28, 0x0e, 0xe4},
- .entry_point = SOF_TEXT_START,
- .type = {
- .load_type = SOF_MAN_MOD_TYPE_MODULE,
- .domain_ll = 1,
- },
- .affinity_mask = 3,
- },
-};
-
-/* not used, but stops linker complaining */
-int _start;
diff --git a/src/platform/cannonlake/boot_ldr.x.in b/src/platform/cannonlake/boot_ldr.x.in
deleted file mode 100644
index a023f2e..0000000
--- a/src/platform/cannonlake/boot_ldr.x.in
+++ /dev/null
@@ -1,236 +0,0 @@
-/*
- * Linker Script for Cannonlake Bootloader.
- *
- * This script is run through the GNU C preprocessor to align the memory
- * offsets with headers.
- *
- * Use spaces for formatting as cpp ignore tab sizes.
- */
-
-#include <platform/memory.h>
-#include <xtensa/config/core-isa.h>
-
-OUTPUT_ARCH(xtensa)
-
-MEMORY
-{
- boot_entry_text :
- org = IMR_BOOT_LDR_TEXT_ENTRY_BASE,
- len = IMR_BOOT_LDR_TEXT_ENTRY_SIZE
- boot_entry_lit :
- org = IMR_BOOT_LDR_LIT_BASE,
- len = IMR_BOOT_LDR_LIT_SIZE
- sof_text :
- org = IMR_BOOT_LDR_TEXT_BASE,
- len = IMR_BOOT_LDR_TEXT_SIZE,
- sof_data :
- org = IMR_BOOT_LDR_DATA_BASE,
- len = IMR_BOOT_LDR_DATA_SIZE
- sof_bss_data :
- org = IMR_BOOT_LDR_BSS_BASE,
- len = IMR_BOOT_LDR_BSS_SIZE
- sof_stack :
- org = SOF_STACK_END,
- len = SOF_STACK_BASE - SOF_STACK_END
- wnd0 :
- org = HP_SRAM_WIN0_BASE,
- len = HP_SRAM_WIN0_SIZE
-}
-
-PHDRS
-{
- boot_entry_text_phdr PT_LOAD;
- boot_entry_lit_phdr PT_LOAD;
- sof_text_phdr PT_LOAD;
- sof_data_phdr PT_LOAD;
- sof_bss_data_phdr PT_LOAD;
- sof_stack_phdr PT_LOAD;
- wnd0_phdr PT_LOAD;
-}
-
-/* Default entry point: */
-ENTRY(boot_entry)
-EXTERN(reset_vector)
-
-SECTIONS
-{
- .boot_entry.text : ALIGN(4)
- {
- _boot_entry_text_start = ABSOLUTE(.);
- KEEP (*(.boot_entry.text))
- _boot_entry_text_end = ABSOLUTE(.);
- } >boot_entry_text :boot_entry_text_phdr
-
- .boot_entry.literal : ALIGN(4)
- {
- _boot_entry_literal_start = ABSOLUTE(.);
- *(.boot_entry.literal)
- *(.literal .literal.* .stub .gnu.warning .gnu.linkonce.literal.* .gnu.linkonce.t.*.literal .gnu.linkonce.t.*)
- _boot_entry_literal_end = ABSOLUTE(.);
- } >boot_entry_lit :boot_entry_lit_phdr
-
- .text : ALIGN(4)
- {
- _stext = .;
- _text_start = ABSOLUTE(.);
- *(.entry.text)
- *(.init.literal)
- KEEP(*(.init))
- *( .text .text.*)
- *(.fini.literal)
- KEEP(*(.fini))
- *(.gnu.version)
- KEEP (*(.ResetVector.text))
- KEEP (*(.ResetHandler.text))
- _text_end = ABSOLUTE(.);
- _etext = .;
- } >sof_text :sof_text_phdr
-
- .rodata : ALIGN(4)
- {
- _rodata_start = ABSOLUTE(.);
- *(.rodata)
- *(.rodata.*)
- *(.gnu.linkonce.r.*)
- *(.rodata1)
- __XT_EXCEPTION_TABLE__ = ABSOLUTE(.);
- KEEP (*(.xt_except_table))
- KEEP (*(.gcc_except_table))
- *(.gnu.linkonce.e.*)
- *(.gnu.version_r)
- KEEP (*(.eh_frame))
- /* C++ constructor and destructor tables, properly ordered: */
- KEEP (*crtbegin.o(.ctors))
- KEEP (*(EXCLUDE_FILE (*crtend.o) .ctors))
- KEEP (*(SORT(.ctors.*)))
- KEEP (*(.ctors))
- KEEP (*crtbegin.o(.dtors))
- KEEP (*(EXCLUDE_FILE (*crtend.o) .dtors))
- KEEP (*(SORT(.dtors.*)))
- KEEP (*(.dtors))
- /* C++ exception handlers table: */
- __XT_EXCEPTION_DESCS__ = ABSOLUTE(.);
- *(.xt_except_desc)
- *(.gnu.linkonce.h.*)
- __XT_EXCEPTION_DESCS_END__ = ABSOLUTE(.);
- *(.xt_except_desc_end)
- *(.dynamic)
- *(.gnu.version_d)
- . = ALIGN(4); /* this table MUST be 4-byte aligned */
- _bss_table_start = ABSOLUTE(.);
- LONG(_bss_start)
- LONG(_bss_end)
- _bss_table_end = ABSOLUTE(.);
- _rodata_end = ABSOLUTE(.);
- } >sof_data :sof_data_phdr
-
- .data : ALIGN(4)
- {
- _data_start = ABSOLUTE(.);
- *(.data)
- *(.data.*)
- *(.gnu.linkonce.d.*)
- KEEP(*(.gnu.linkonce.d.*personality*))
- *(.data1)
- *(.sdata)
- *(.sdata.*)
- *(.gnu.linkonce.s.*)
- *(.sdata2)
- *(.sdata2.*)
- *(.gnu.linkonce.s2.*)
- KEEP(*(.jcr))
- _data_end = ABSOLUTE(.);
- } >sof_data :sof_data_phdr
-
- .lit4 : ALIGN(4)
- {
- _lit4_start = ABSOLUTE(.);
- *(*.lit4)
- *(.lit4.*)
- *(.gnu.linkonce.lit4.*)
- _lit4_end = ABSOLUTE(.);
- } >sof_data :sof_data_phdr
-
- .bss (NOLOAD) : ALIGN(8)
- {
- . = ALIGN (8);
- _bss_start = ABSOLUTE(.);
- *(.dynsbss)
- *(.sbss)
- *(.sbss.*)
- *(.gnu.linkonce.sb.*)
- *(.scommon)
- *(.sbss2)
- *(.sbss2.*)
- *(.gnu.linkonce.sb2.*)
- *(.dynbss)
- *(.bss)
- *(.bss.*)
- *(.gnu.linkonce.b.*)
- *(COMMON)
- . = ALIGN (8);
- _bss_end = ABSOLUTE(.);
- } >sof_bss_data :sof_bss_data_phdr
-
- _man = 0x1234567;
-
- PROVIDE(_memmap_vecbase_reset = HP_SRAM_VECBASE_RESET);
-
- _memmap_cacheattr_wbna_trapnull = 0xFF42FFF2;
- PROVIDE(_memmap_cacheattr_reset = _memmap_cacheattr_wbna_trapnull);
-
- __stack = SOF_STACK_BASE;
- __wnd0 = HP_SRAM_WIN0_BASE;
- __wnd0_size = HP_SRAM_WIN0_SIZE;
-
- .debug 0 : { *(.debug) }
- .line 0 : { *(.line) }
- .debug_srcinfo 0 : { *(.debug_srcinfo) }
- .debug_sfnames 0 : { *(.debug_sfnames) }
- .debug_aranges 0 : { *(.debug_aranges) }
- .debug_pubnames 0 : { *(.debug_pubnames) }
- .debug_info 0 : { *(.debug_info) }
- .debug_abbrev 0 : { *(.debug_abbrev) }
- .debug_line 0 : { *(.debug_line) }
- .debug_frame 0 : { *(.debug_frame) }
- .debug_str 0 : { *(.debug_str) }
- .debug_loc 0 : { *(.debug_loc) }
- .debug_macinfo 0 : { *(.debug_macinfo) }
- .debug_weaknames 0 : { *(.debug_weaknames) }
- .debug_funcnames 0 : { *(.debug_funcnames) }
- .debug_typenames 0 : { *(.debug_typenames) }
- .debug_varnames 0 : { *(.debug_varnames) }
-
- .xt.insn 0 :
- {
- KEEP (*(.xt.insn))
- KEEP (*(.gnu.linkonce.x.*))
- }
- .xt.prop 0 :
- {
- KEEP (*(.xt.prop))
- KEEP (*(.xt.prop.*))
- KEEP (*(.gnu.linkonce.prop.*))
- }
- .xt.lit 0 :
- {
- KEEP (*(.xt.lit))
- KEEP (*(.xt.lit.*))
- KEEP (*(.gnu.linkonce.p.*))
- }
- .xt.profile_range 0 :
- {
- KEEP (*(.xt.profile_range))
- KEEP (*(.gnu.linkonce.profile_range.*))
- }
- .xt.profile_ranges 0 :
- {
- KEEP (*(.xt.profile_ranges))
- KEEP (*(.gnu.linkonce.xt.profile_ranges.*))
- }
- .xt.profile_files 0 :
- {
- KEEP (*(.xt.profile_files))
- KEEP (*(.gnu.linkonce.xt.profile_files.*))
- }
-}
diff --git a/src/platform/cannonlake/boot_module.c b/src/platform/cannonlake/boot_module.c
deleted file mode 100644
index 4837493..0000000
--- a/src/platform/cannonlake/boot_module.c
+++ /dev/null
@@ -1,54 +0,0 @@
-/*
- * Copyright (c) 2018, Intel Corporation
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- * * Redistributions of source code must retain the above copyright
- * notice, this list of conditions and the following disclaimer.
- * * Redistributions in binary form must reproduce the above copyright
- * notice, this list of conditions and the following disclaimer in the
- * documentation and/or other materials provided with the distribution.
- * * Neither the name of the Intel Corporation nor the
- * names of its contributors may be used to endorse or promote products
- * derived from this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
- * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
- * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
- * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
- * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
- * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
- * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
- * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
- * POSSIBILITY OF SUCH DAMAGE.
- *
- * Author: Liam Girdwood <liam.r.girdwood@linux.intel.com>
- */
-
-#include <uapi/manifest.h>
-#include <platform/memory.h>
-
-/*
- * Each module has an entry in the FW manifest header. This is NOT part of
- * the SOF executable image but is inserted by object copy as a ELF section
- * for parsing by rimage (to genrate the manifest).
- */
-struct sof_man_module_manifest cnl_bootldr_manifest = {
- .module = {
- .name = "BRNGUP",
- .uuid = {0xf3, 0xe4, 0x79, 0x2b, 0x75, 0x46, 0x49, 0xf6,
- 0x89, 0xdf, 0x3b, 0xc1, 0x94, 0xa9, 0x1a, 0xeb},
- .entry_point = IMR_BOOT_LDR_TEXT_ENTRY_BASE,
- .type = {
- .load_type = SOF_MAN_MOD_TYPE_MODULE,
- .domain_ll = 1,
- },
- .affinity_mask = 3,
- },
-};
-
-/* not used, but stops linker complaining */
-int _start;
diff --git a/src/platform/cannonlake/cannonlake.x.in b/src/platform/cannonlake/cannonlake.x.in
deleted file mode 100644
index 06f745b..0000000
--- a/src/platform/cannonlake/cannonlake.x.in
+++ /dev/null
@@ -1,504 +0,0 @@
-/*
- * Linker Script for Cannonlake.
- *
- * This script is run through the GNU C preprocessor to align the memory
- * offsets with headers.
- *
- * Use spaces for formatting as cpp ignore tab sizes.
- */
-
-#include <platform/memory.h>
-#include <xtensa/config/core-isa.h>
-
-OUTPUT_ARCH(xtensa)
-
-MEMORY
-{
- vector_memory_lit :
- org = XCHAL_MEMERROR_VECTOR_PADDR + SOF_MEM_ERROR_LIT_SIZE,
- len = SOF_MEM_ERROR_LIT_SIZE
- vector_memory_text :
- org = XCHAL_MEMERROR_VECTOR_PADDR,
- len = SOF_MEM_ERROR_TEXT_SIZE
- vector_base_text :
- org = SOF_MEM_VECBASE,
- len = SOF_MEM_VECBASE_LIT_SIZE
- vector_int2_lit :
- org = SOF_MEM_VECBASE + XCHAL_INTLEVEL2_VECOFS - SOF_MEM_VECT_LIT_SIZE,
- len = SOF_MEM_VECT_LIT_SIZE
- vector_int2_text :
- org = SOF_MEM_VECBASE + XCHAL_INTLEVEL2_VECOFS,
- len = SOF_MEM_VECT_TEXT_SIZE
- vector_int3_lit :
- org = SOF_MEM_VECBASE + XCHAL_INTLEVEL3_VECOFS - SOF_MEM_VECT_LIT_SIZE,
- len = SOF_MEM_VECT_LIT_SIZE
- vector_int3_text :
- org = SOF_MEM_VECBASE + XCHAL_INTLEVEL3_VECOFS,
- len = SOF_MEM_VECT_TEXT_SIZE
- vector_int4_lit :
- org = SOF_MEM_VECBASE + XCHAL_INTLEVEL4_VECOFS - SOF_MEM_VECT_LIT_SIZE,
- len = SOF_MEM_VECT_LIT_SIZE
- vector_int4_text :
- org = SOF_MEM_VECBASE + XCHAL_INTLEVEL4_VECOFS,
- len = SOF_MEM_VECT_TEXT_SIZE
- vector_int5_lit :
- org = SOF_MEM_VECBASE + XCHAL_INTLEVEL5_VECOFS - SOF_MEM_VECT_LIT_SIZE,
- len = SOF_MEM_VECT_LIT_SIZE
- vector_int5_text :
- org = SOF_MEM_VECBASE + XCHAL_INTLEVEL5_VECOFS,
- len = SOF_MEM_VECT_TEXT_SIZE
- vector_int6_lit :
- org = SOF_MEM_VECBASE + XCHAL_INTLEVEL6_VECOFS - SOF_MEM_VECT_LIT_SIZE,
- len = SOF_MEM_VECT_LIT_SIZE
- vector_int6_text :
- org = SOF_MEM_VECBASE + XCHAL_INTLEVEL6_VECOFS,
- len = SOF_MEM_VECT_TEXT_SIZE
- vector_int7_lit :
- org = SOF_MEM_VECBASE + XCHAL_INTLEVEL7_VECOFS - SOF_MEM_VECT_LIT_SIZE,
- len = SOF_MEM_VECT_LIT_SIZE
- vector_int7_text :
- org = SOF_MEM_VECBASE + XCHAL_INTLEVEL7_VECOFS,
- len = SOF_MEM_VECT_TEXT_SIZE
- vector_kernel_lit :
- org = SOF_MEM_VECBASE + XCHAL_KERNEL_VECOFS - SOF_MEM_VECT_LIT_SIZE,
- len = SOF_MEM_VECT_LIT_SIZE
- vector_kernel_text :
- org = SOF_MEM_VECBASE + XCHAL_KERNEL_VECOFS,
- len = SOF_MEM_VECT_TEXT_SIZE
- vector_user_lit :
- org = SOF_MEM_VECBASE + XCHAL_USER_VECOFS - SOF_MEM_VECT_LIT_SIZE,
- len = SOF_MEM_VECT_LIT_SIZE
- vector_user_text :
- org = SOF_MEM_VECBASE + XCHAL_USER_VECOFS,
- len = SOF_MEM_VECT_TEXT_SIZE
- vector_double_lit :
- org = SOF_MEM_VECBASE + XCHAL_DOUBLEEXC_VECOFS - SOF_MEM_VECT_LIT_SIZE,
- len = SOF_MEM_VECT_LIT_SIZE
- vector_double_text :
- org = SOF_MEM_VECBASE + XCHAL_DOUBLEEXC_VECOFS,
- len = SOF_MEM_VECT_TEXT_SIZE
- sof_text :
- org = SOF_TEXT_BASE,
- len = SOF_TEXT_SIZE,
- sof_data :
- org = SOF_TEXT_BASE + SOF_TEXT_SIZE,
- len = SOF_DATA_SIZE
- sof_bss_data :
- org = SOF_TEXT_BASE + SOF_TEXT_SIZE + SOF_DATA_SIZE,
- len = SOF_BSS_DATA_SIZE
- system_heap :
- org = HEAP_SYSTEM_BASE,
- len = HEAP_SYSTEM_SIZE
- runtime_heap :
- org = HEAP_RUNTIME_BASE,
- len = HEAP_RUNTIME_SIZE
- buffer_heap :
- org = HEAP_BUFFER_BASE,
- len = HEAP_BUFFER_SIZE
- sof_stack :
- org = SOF_STACK_END,
- len = SOF_STACK_BASE - SOF_STACK_END
-}
-
-PHDRS
-{
- vector_memory_lit_phdr PT_LOAD;
- vector_memory_text_phdr PT_LOAD;
- vector_base_text_phdr PT_LOAD;
- vector_int2_lit_phdr PT_LOAD;
- vector_int2_text_phdr PT_LOAD;
- vector_int3_lit_phdr PT_LOAD;
- vector_int3_text_phdr PT_LOAD;
- vector_int4_lit_phdr PT_LOAD;
- vector_int4_text_phdr PT_LOAD;
- vector_int5_lit_phdr PT_LOAD;
- vector_int5_text_phdr PT_LOAD;
- vector_int6_lit_phdr PT_LOAD;
- vector_int6_text_phdr PT_LOAD;
- vector_int7_lit_phdr PT_LOAD;
- vector_int7_text_phdr PT_LOAD;
- vector_kernel_lit_phdr PT_LOAD;
- vector_kernel_text_phdr PT_LOAD;
- vector_user_lit_phdr PT_LOAD;
- vector_user_text_phdr PT_LOAD;
- vector_double_lit_phdr PT_LOAD;
- vector_double_text_phdr PT_LOAD;
- sof_text_phdr PT_LOAD;
- sof_data_phdr PT_LOAD;
- sof_bss_data_phdr PT_LOAD;
- system_heap_phdr PT_LOAD;
- runtime_heap_phdr PT_LOAD;
- buffer_heap_phdr PT_LOAD;
- sof_stack_phdr PT_LOAD;
-}
-
-/* Default entry point: */
-ENTRY(_MainEntry)
-_rom_store_table = 0;
-
-/* ABI0 does not use Window base */
-PROVIDE(_memmap_vecbase_reset = XCHAL_VECBASE_RESET_PADDR);
-
-/* Various memory-map dependent cache attribute settings: */
-_memmap_cacheattr_wb_base = 0x44024000;
-_memmap_cacheattr_wt_base = 0x11021000;
-_memmap_cacheattr_bp_base = 0x22022000;
-_memmap_cacheattr_unused_mask = 0x00F00FFF;
-_memmap_cacheattr_wb_trapnull = 0x4422422F;
-_memmap_cacheattr_wba_trapnull = 0x4422422F;
-_memmap_cacheattr_wbna_trapnull = 0xFF42FFF2;
-_memmap_cacheattr_wt_trapnull = 0x1122122F;
-_memmap_cacheattr_bp_trapnull = 0x2222222F;
-_memmap_cacheattr_wb_strict = 0x44F24FFF;
-_memmap_cacheattr_wt_strict = 0x11F21FFF;
-_memmap_cacheattr_bp_strict = 0x22F22FFF;
-_memmap_cacheattr_wb_allvalid = 0x44224222;
-_memmap_cacheattr_wt_allvalid = 0x11221222;
-_memmap_cacheattr_bp_allvalid = 0x22222222;
-PROVIDE(_memmap_cacheattr_reset = _memmap_cacheattr_wbna_trapnull);
-
-SECTIONS
-{
- .MemoryExceptionVector.text : ALIGN(4)
- {
- _MemoryExceptionVector_text_start = ABSOLUTE(.);
- KEEP (*(.MemoryExceptionVector.text))
- _MemoryExceptionVector_text_end = ABSOLUTE(.);
- } >vector_memory_text :vector_memory_text_phdr
-
- .WindowVectors.text : ALIGN(4)
- {
- _WindowVectors_text_start = ABSOLUTE(.);
- KEEP (*(.WindowVectors.text))
- _WindowVectors_text_end = ABSOLUTE(.);
- } >vector_base_text :vector_base_text_phdr
-
- .Level2InterruptVector.literal : ALIGN(4)
- {
- _Level2InterruptVector_literal_start = ABSOLUTE(.);
- *(.Level2InterruptVector.literal)
- _Level2InterruptVector_literal_end = ABSOLUTE(.);
- } >vector_int2_lit :vector_int2_lit_phdr
-
- .Level2InterruptVector.text : ALIGN(4)
- {
- _Level2InterruptVector_text_start = ABSOLUTE(.);
- KEEP (*(.Level2InterruptVector.text))
- _Level2InterruptVector_text_end = ABSOLUTE(.);
- } >vector_int2_text :vector_int2_text_phdr
-
- .Level3InterruptVector.literal : ALIGN(4)
- {
- _Level3InterruptVector_literal_start = ABSOLUTE(.);
- *(.Level3InterruptVector.literal)
- _Level3InterruptVector_literal_end = ABSOLUTE(.);
- } >vector_int3_lit :vector_int3_lit_phdr
-
- .Level3InterruptVector.text : ALIGN(4)
- {
- _Level3InterruptVector_text_start = ABSOLUTE(.);
- KEEP (*(.Level3InterruptVector.text))
- _Level3InterruptVector_text_end = ABSOLUTE(.);
- } >vector_int3_text :vector_int3_text_phdr
-
- .Level4InterruptVector.literal : ALIGN(4)
- {
- _Level4InterruptVector_literal_start = ABSOLUTE(.);
- *(.Level4InterruptVector.literal)
- _Level4InterruptVector_literal_end = ABSOLUTE(.);
- } >vector_int4_lit :vector_int4_lit_phdr
-
- .Level4InterruptVector.text : ALIGN(4)
- {
- _Level4InterruptVector_text_start = ABSOLUTE(.);
- KEEP (*(.Level4InterruptVector.text))
- _Level4InterruptVector_text_end = ABSOLUTE(.);
- } >vector_int4_text :vector_int4_text_phdr
-
- .Level5InterruptVector.literal : ALIGN(4)
- {
- _Level5InterruptVector_literal_start = ABSOLUTE(.);
- *(.Level5InterruptVector.literal)
- _Level5InterruptVector_literal_end = ABSOLUTE(.);
- } >vector_int5_lit :vector_int5_lit_phdr
-
- .Level5InterruptVector.text : ALIGN(4)
- {
- _Level5InterruptVector_text_start = ABSOLUTE(.);
- KEEP (*(.Level5InterruptVector.text))
- _Level5InterruptVector_text_end = ABSOLUTE(.);
- } >vector_int5_text :vector_int5_text_phdr
-
- .DebugExceptionVector.literal : ALIGN(4)
- {
- _DebugExceptionVector_literal_start = ABSOLUTE(.);
- *(.DebugExceptionVector.literal)
- _DebugExceptionVector_literal_end = ABSOLUTE(.);
- } >vector_int6_lit :vector_int6_lit_phdr
-
- .DebugExceptionVector.text : ALIGN(4)
- {
- _DebugExceptionVector_text_start = ABSOLUTE(.);
- KEEP (*(.DebugExceptionVector.text))
- _DebugExceptionVector_text_end = ABSOLUTE(.);
- } >vector_int6_text :vector_int6_text_phdr
-
- .NMIExceptionVector.literal : ALIGN(4)
- {
- _NMIExceptionVector_literal_start = ABSOLUTE(.);
- *(.NMIExceptionVector.literal)
- _NMIExceptionVector_literal_end = ABSOLUTE(.);
- } >vector_int7_lit :vector_int7_lit_phdr
-
- .NMIExceptionVector.text : ALIGN(4)
- {
- _NMIExceptionVector_text_start = ABSOLUTE(.);
- KEEP (*(.NMIExceptionVector.text))
- _NMIExceptionVector_text_end = ABSOLUTE(.);
- } >vector_int7_text :vector_int7_text_phdr
-
- .KernelExceptionVector.literal : ALIGN(4)
- {
- _KernelExceptionVector_literal_start = ABSOLUTE(.);
- *(.KernelExceptionVector.literal)
- _KernelExceptionVector_literal_end = ABSOLUTE(.);
- } >vector_kernel_lit :vector_kernel_lit_phdr
-
- .KernelExceptionVector.text : ALIGN(4)
- {
- _KernelExceptionVector_text_start = ABSOLUTE(.);
- KEEP (*(.KernelExceptionVector.text))
- _KernelExceptionVector_text_end = ABSOLUTE(.);
- } >vector_kernel_text :vector_kernel_text_phdr
-
- .UserExceptionVector.literal : ALIGN(4)
- {
- _UserExceptionVector_literal_start = ABSOLUTE(.);
- *(.UserExceptionVector.literal)
- _UserExceptionVector_literal_end = ABSOLUTE(.);
- } >vector_user_lit :vector_user_lit_phdr
-
- .UserExceptionVector.text : ALIGN(4)
- {
- _UserExceptionVector_text_start = ABSOLUTE(.);
- KEEP (*(.UserExceptionVector.text))
- _UserExceptionVector_text_end = ABSOLUTE(.);
- } >vector_user_text :vector_user_text_phdr
-
- .DoubleExceptionVector.literal : ALIGN(4)
- {
- _DoubleExceptionVector_literal_start = ABSOLUTE(.);
- *(.DoubleExceptionVector.literal)
- _DoubleExceptionVector_literal_end = ABSOLUTE(.);
- } >vector_double_lit :vector_double_lit_phdr
-
- .DoubleExceptionVector.text : ALIGN(4)
- {
- _DoubleExceptionVector_text_start = ABSOLUTE(.);
- KEEP (*(.DoubleExceptionVector.text))
- _DoubleExceptionVector_text_end = ABSOLUTE(.);
- } >vector_double_text :vector_double_text_phdr
-
- .text : ALIGN(4)
- {
- _stext = .;
- _text_start = ABSOLUTE(.);
- KEEP (*(.MainEntry.text))
- *(.entry.text)
- *(.init.literal)
- KEEP(*(.init))
- *(.literal .text .literal.* .text.* .stub .gnu.warning .gnu.linkonce.literal.* .gnu.linkonce.t.*.literal .gnu.linkonce.t.*)
- *(.fini.literal)
- KEEP(*(.fini))
- *(.gnu.version)
- KEEP (*(.ResetHandler.text))
- _text_end = ABSOLUTE(.);
- _etext = .;
- } >sof_text :sof_text_phdr
-
- .rodata : ALIGN(4)
- {
- _rodata_start = ABSOLUTE(.);
- *(.rodata)
- *(.rodata.*)
- *(.gnu.linkonce.r.*)
- *(.rodata1)
- __XT_EXCEPTION_TABLE__ = ABSOLUTE(.);
- KEEP (*(.xt_except_table))
- KEEP (*(.gcc_except_table))
- *(.gnu.linkonce.e.*)
- *(.gnu.version_r)
- KEEP (*(.eh_frame))
- /* C++ constructor and destructor tables, properly ordered: */
- KEEP (*crtbegin.o(.ctors))
- KEEP (*(EXCLUDE_FILE (*crtend.o) .ctors))
- KEEP (*(SORT(.ctors.*)))
- KEEP (*(.ctors))
- KEEP (*crtbegin.o(.dtors))
- KEEP (*(EXCLUDE_FILE (*crtend.o) .dtors))
- KEEP (*(SORT(.dtors.*)))
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- *(.xt_except_desc)
- *(.gnu.linkonce.h.*)
- __XT_EXCEPTION_DESCS_END__ = ABSOLUTE(.);
- *(.xt_except_desc_end)
- *(.dynamic)
- *(.gnu.version_d)
- . = ALIGN(4); /* this table MUST be 4-byte aligned */
- _bss_table_start = ABSOLUTE(.);
- LONG(_bss_start)
- LONG(_bss_end)
- _bss_table_end = ABSOLUTE(.);
- _rodata_end = ABSOLUTE(.);
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- *(.gnu.linkonce.d.*)
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- *(*.lit4)
- *(.lit4.*)
- *(.gnu.linkonce.lit4.*)
- _lit4_end = ABSOLUTE(.);
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- *(.dynsbss)
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- *(.sbss.*)
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-
- /* stack */
- _end = SOF_STACK_END;
- PROVIDE(end = SOF_STACK_END);
- _stack_sentry = SOF_STACK_END;
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-
- /* System Heap */
- _system_heap = HEAP_SYSTEM_BASE;
-
-
- /* module heap */
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-
- /* buffer heap */
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- _buffer_heap_end = _stack_sentry;
-
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- .system_heap (NOLOAD) : ALIGN(8)
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- _system_heap_start = ABSOLUTE(.);
- . = . + HEAP_SYSTEM_SIZE;
- _system_heap_end = ABSOLUTE(.);
- } >system_heap :system_heap_phdr
-
- .runtime_heap (NOLOAD) : ALIGN(8)
- {
- . = ALIGN (32);
- _runtime_heap_start = ABSOLUTE(.);
- . = . + HEAP_RUNTIME_SIZE;
- _runtime_heap_end = ABSOLUTE(.);
- } >runtime_heap :runtime_heap_phdr
-
- .buffer_heap (NOLOAD) : ALIGN(8)
- {
- . = ALIGN (32);
- _system_heap_start = ABSOLUTE(.);
- . = . + HEAP_BUFFER_SIZE;
- _system_heap_end = ABSOLUTE(.);
- } >buffer_heap :buffer_heap_phdr
-
- .sof_stack (NOLOAD) : ALIGN(8)
- {
- . = ALIGN (4096);
- _sof_stack_start = ABSOLUTE(.);
- . = . + SOF_STACK_SIZE;
- _sof_stack_end = ABSOLUTE(.);
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-}
diff --git a/src/platform/cannonlake/include/Makefile.am b/src/platform/cannonlake/include/Makefile.am
deleted file mode 100644
index c5113a4..0000000
--- a/src/platform/cannonlake/include/Makefile.am
+++ /dev/null
@@ -1 +0,0 @@
-SUBDIRS = arch platform
diff --git a/src/platform/cannonlake/include/arch/Makefile.am b/src/platform/cannonlake/include/arch/Makefile.am
deleted file mode 100644
index 63616bf..0000000
--- a/src/platform/cannonlake/include/arch/Makefile.am
+++ /dev/null
@@ -1 +0,0 @@
-SUBDIRS = xtensa
diff --git a/src/platform/cannonlake/include/arch/xtensa/Makefile.am b/src/platform/cannonlake/include/arch/xtensa/Makefile.am
deleted file mode 100644
index a85a5bb..0000000
--- a/src/platform/cannonlake/include/arch/xtensa/Makefile.am
+++ /dev/null
@@ -1 +0,0 @@
-SUBDIRS = config
diff --git a/src/platform/cannonlake/include/arch/xtensa/config/Makefile.am b/src/platform/cannonlake/include/arch/xtensa/config/Makefile.am
deleted file mode 100644
index 99c21a5..0000000
--- a/src/platform/cannonlake/include/arch/xtensa/config/Makefile.am
+++ /dev/null
@@ -1,8 +0,0 @@
-noinst_HEADERS = \
- core-isa.h \
- core-matmap.h \
- defs.h \
- specreg.h \
- system.h \
- tie.h \
- tie-asm.h
diff --git a/src/platform/cannonlake/include/arch/xtensa/config/core-isa.h b/src/platform/cannonlake/include/arch/xtensa/config/core-isa.h
deleted file mode 100644
index 8a02768..0000000
--- a/src/platform/cannonlake/include/arch/xtensa/config/core-isa.h
+++ /dev/null
@@ -1,565 +0,0 @@
-/*
- * xtensa/config/core-isa.h -- HAL definitions that are dependent on Xtensa
- * processor CORE configuration
- *
- * See <xtensa/config/core.h>, which includes this file, for more details.
- */
-
-/* Xtensa processor core configuration information.
-
- Customer ID=10631; Build=0x60f88; Copyright (c) 1999-2016 Tensilica Inc.
-
- Permission is hereby granted, free of charge, to any person obtaining
- a copy of this software and associated documentation files (the
- "Software"), to deal in the Software without restriction, including
- without limitation the rights to use, copy, modify, merge, publish,
- distribute, sublicense, and/or sell copies of the Software, and to
- permit persons to whom the Software is furnished to do so, subject to
- the following conditions:
-
- The above copyright notice and this permission notice shall be included
- in all copies or substantial portions of the Software.
-
- THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
- EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
- MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
- IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY
- CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
- TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
- SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. */
-
-#if !defined __XCC__
-
-#ifndef _XTENSA_CORE_CONFIGURATION_H
-#define _XTENSA_CORE_CONFIGURATION_H
-
-
-/****************************************************************************
- Parameters Useful for Any Code, USER or PRIVILEGED
- ****************************************************************************/
-
-/*
- * Note: Macros of the form XCHAL_HAVE_*** have a value of 1 if the option is
- * configured, and a value of 0 otherwise. These macros are always defined.
- */
-
-
-/*----------------------------------------------------------------------
- ISA
- ----------------------------------------------------------------------*/
-
-#define XCHAL_HAVE_BE 0 /* big-endian byte ordering */
-#define XCHAL_HAVE_WINDOWED 1 /* windowed registers option */
-#define XCHAL_NUM_AREGS 64 /* num of physical addr regs */
-#define XCHAL_NUM_AREGS_LOG2 6 /* log2(XCHAL_NUM_AREGS) */
-#define XCHAL_MAX_INSTRUCTION_SIZE 8 /* max instr bytes (3..8) */
-#define XCHAL_HAVE_DEBUG 1 /* debug option */
-#define XCHAL_HAVE_DENSITY 1 /* 16-bit instructions */
-#define XCHAL_HAVE_LOOPS 1 /* zero-overhead loops */
-#define XCHAL_LOOP_BUFFER_SIZE 64 /* zero-ov. loop instr buffer size */
-#define XCHAL_HAVE_NSA 1 /* NSA/NSAU instructions */
-#define XCHAL_HAVE_MINMAX 1 /* MIN/MAX instructions */
-#define XCHAL_HAVE_SEXT 1 /* SEXT instruction */
-#define XCHAL_HAVE_DEPBITS 0 /* DEPBITS instruction */
-#define XCHAL_HAVE_CLAMPS 1 /* CLAMPS instruction */
-#define XCHAL_HAVE_MUL16 1 /* MUL16S/MUL16U instructions */
-#define XCHAL_HAVE_MUL32 1 /* MULL instruction */
-#define XCHAL_HAVE_MUL32_HIGH 1 /* MULUH/MULSH instructions */
-#define XCHAL_HAVE_DIV32 1 /* QUOS/QUOU/REMS/REMU instructions */
-#define XCHAL_HAVE_L32R 1 /* L32R instruction */
-#define XCHAL_HAVE_ABSOLUTE_LITERALS 0 /* non-PC-rel (extended) L32R */
-#define XCHAL_HAVE_CONST16 0 /* CONST16 instruction */
-#define XCHAL_HAVE_ADDX 1 /* ADDX#/SUBX# instructions */
-#define XCHAL_HAVE_WIDE_BRANCHES 0 /* B*.W18 or B*.W15 instr's */
-#define XCHAL_HAVE_PREDICTED_BRANCHES 0 /* B[EQ/EQZ/NE/NEZ]T instr's */
-#define XCHAL_HAVE_CALL4AND12 1 /* (obsolete option) */
-#define XCHAL_HAVE_ABS 1 /* ABS instruction */
-/*#define XCHAL_HAVE_POPC 0*/ /* POPC instruction */
-/*#define XCHAL_HAVE_CRC 0*/ /* CRC instruction */
-#define XCHAL_HAVE_RELEASE_SYNC 1 /* L32AI/S32RI instructions */
-#define XCHAL_HAVE_S32C1I 1 /* S32C1I instruction */
-#define XCHAL_HAVE_SPECULATION 0 /* speculation */
-#define XCHAL_HAVE_FULL_RESET 1 /* all regs/state reset */
-#define XCHAL_NUM_CONTEXTS 1 /* */
-#define XCHAL_NUM_MISC_REGS 0 /* num of scratch regs (0..4) */
-#define XCHAL_HAVE_TAP_MASTER 0 /* JTAG TAP control instr's */
-#define XCHAL_HAVE_PRID 1 /* processor ID register */
-#define XCHAL_HAVE_EXTERN_REGS 1 /* WER/RER instructions */
-#define XCHAL_HAVE_MX 0 /* MX core (Tensilica internal) */
-#define XCHAL_HAVE_MP_INTERRUPTS 0 /* interrupt distributor port */
-#define XCHAL_HAVE_MP_RUNSTALL 0 /* core RunStall control port */
-#define XCHAL_HAVE_PSO 0 /* Power Shut-Off */
-#define XCHAL_HAVE_PSO_CDM 0 /* core/debug/mem pwr domains */
-#define XCHAL_HAVE_PSO_FULL_RETENTION 0 /* all regs preserved on PSO */
-#define XCHAL_HAVE_THREADPTR 1 /* THREADPTR register */
-#define XCHAL_HAVE_BOOLEANS 1 /* boolean registers */
-/* TODO: CP is 1 - need assembler support */
-#define XCHAL_HAVE_CP 0 /* CPENABLE reg (coprocessor) */
-#define XCHAL_CP_MAXCFG 2 /* max allowed cp id plus one */
-#define XCHAL_HAVE_MAC16 0 /* MAC16 package */
-
-#define XCHAL_HAVE_FUSION 0 /* Fusion*/
-#define XCHAL_HAVE_FUSION_FP 0 /* Fusion FP option */
-#define XCHAL_HAVE_FUSION_LOW_POWER 0 /* Fusion Low Power option */
-#define XCHAL_HAVE_FUSION_AES 0 /* Fusion BLE/Wifi AES-128 CCM option */
-#define XCHAL_HAVE_FUSION_CONVENC 0 /* Fusion Conv Encode option */
-#define XCHAL_HAVE_FUSION_LFSR_CRC 0 /* Fusion LFSR-CRC option */
-#define XCHAL_HAVE_FUSION_BITOPS 0 /* Fusion Bit Operations Support option */
-#define XCHAL_HAVE_FUSION_AVS 0 /* Fusion AVS option */
-#define XCHAL_HAVE_FUSION_16BIT_BASEBAND 0 /* Fusion 16-bit Baseband option */
-#define XCHAL_HAVE_FUSION_VITERBI 0 /* Fusion Viterbi option */
-#define XCHAL_HAVE_FUSION_SOFTDEMAP 0 /* Fusion Soft Bit Demap option */
-#define XCHAL_HAVE_HIFIPRO 0 /* HiFiPro Audio Engine pkg */
-#define XCHAL_HAVE_HIFI4 0 /* HiFi4 Audio Engine pkg */
-#define XCHAL_HAVE_HIFI4_VFPU 0 /* HiFi4 Audio Engine VFPU option */
-#define XCHAL_HAVE_HIFI3 1 /* HiFi3 Audio Engine pkg */
-#define XCHAL_HAVE_HIFI3_VFPU 0 /* HiFi3 Audio Engine VFPU option */
-#define XCHAL_HAVE_HIFI2 0 /* HiFi2 Audio Engine pkg */
-#define XCHAL_HAVE_HIFI2EP 0 /* HiFi2EP */
-#define XCHAL_HAVE_HIFI_MINI 0
-
-
-#define XCHAL_HAVE_VECTORFPU2005 0 /* vector or user floating-point pkg */
-#define XCHAL_HAVE_USER_DPFPU 0 /* user DP floating-point pkg */
-#define XCHAL_HAVE_USER_SPFPU 0 /* user DP floating-point pkg */
-#define XCHAL_HAVE_FP 1 /* single prec floating point */
-#define XCHAL_HAVE_FP_DIV 1 /* FP with DIV instructions */
-#define XCHAL_HAVE_FP_RECIP 1 /* FP with RECIP instructions */
-#define XCHAL_HAVE_FP_SQRT 1 /* FP with SQRT instructions */
-#define XCHAL_HAVE_FP_RSQRT 1 /* FP with RSQRT instructions */
-#define XCHAL_HAVE_DFP 0 /* double precision FP pkg */
-#define XCHAL_HAVE_DFP_DIV 0 /* DFP with DIV instructions */
-#define XCHAL_HAVE_DFP_RECIP 0 /* DFP with RECIP instructions*/
-#define XCHAL_HAVE_DFP_SQRT 0 /* DFP with SQRT instructions */
-#define XCHAL_HAVE_DFP_RSQRT 0 /* DFP with RSQRT instructions*/
-#define XCHAL_HAVE_DFP_ACCEL 0 /* double precision FP acceleration pkg */
-#define XCHAL_HAVE_DFP_accel XCHAL_HAVE_DFP_ACCEL /* for backward compatibility */
-
-#define XCHAL_HAVE_DFPU_SINGLE_ONLY 1 /* DFPU Coprocessor, single precision only */
-#define XCHAL_HAVE_DFPU_SINGLE_DOUBLE 0 /* DFPU Coprocessor, single and double precision */
-#define XCHAL_HAVE_VECTRA1 0 /* Vectra I pkg */
-#define XCHAL_HAVE_VECTRALX 0 /* Vectra LX pkg */
-#define XCHAL_HAVE_PDX4 0 /* PDX4 */
-#define XCHAL_HAVE_CONNXD2 0 /* ConnX D2 pkg */
-#define XCHAL_HAVE_CONNXD2_DUALLSFLIX 0 /* ConnX D2 & Dual LoadStore Flix */
-#define XCHAL_HAVE_BBE16 0 /* ConnX BBE16 pkg */
-#define XCHAL_HAVE_BBE16_RSQRT 0 /* BBE16 & vector recip sqrt */
-#define XCHAL_HAVE_BBE16_VECDIV 0 /* BBE16 & vector divide */
-#define XCHAL_HAVE_BBE16_DESPREAD 0 /* BBE16 & despread */
-#define XCHAL_HAVE_BBENEP 0 /* ConnX BBENEP pkgs */
-#define XCHAL_HAVE_BSP3 0 /* ConnX BSP3 pkg */
-#define XCHAL_HAVE_BSP3_TRANSPOSE 0 /* BSP3 & transpose32x32 */
-#define XCHAL_HAVE_SSP16 0 /* ConnX SSP16 pkg */
-#define XCHAL_HAVE_SSP16_VITERBI 0 /* SSP16 & viterbi */
-#define XCHAL_HAVE_TURBO16 0 /* ConnX Turbo16 pkg */
-#define XCHAL_HAVE_BBP16 0 /* ConnX BBP16 pkg */
-#define XCHAL_HAVE_FLIX3 0 /* basic 3-way FLIX option */
-#define XCHAL_HAVE_GRIVPEP 0 /* GRIVPEP is General Release of IVPEP */
-#define XCHAL_HAVE_GRIVPEP_HISTOGRAM 0 /* Histogram option on GRIVPEP */
-
-
-/*----------------------------------------------------------------------
- MISC
- ----------------------------------------------------------------------*/
-
-#define XCHAL_NUM_LOADSTORE_UNITS 1 /* load/store units */
-#define XCHAL_NUM_WRITEBUFFER_ENTRIES 16 /* size of write buffer */
-#define XCHAL_INST_FETCH_WIDTH 8 /* instr-fetch width in bytes */
-#define XCHAL_DATA_WIDTH 8 /* data width in bytes */
-#define XCHAL_DATA_PIPE_DELAY 2 /* d-side pipeline delay
- (1 = 5-stage, 2 = 7-stage) */
-#define XCHAL_CLOCK_GATING_GLOBAL 1 /* global clock gating */
-#define XCHAL_CLOCK_GATING_FUNCUNIT 1 /* funct. unit clock gating */
-/* In T1050, applies to selected core load and store instructions (see ISA): */
-#define XCHAL_UNALIGNED_LOAD_EXCEPTION 1 /* unaligned loads cause exc. */
-#define XCHAL_UNALIGNED_STORE_EXCEPTION 1 /* unaligned stores cause exc.*/
-#define XCHAL_UNALIGNED_LOAD_HW 0 /* unaligned loads work in hw */
-#define XCHAL_UNALIGNED_STORE_HW 0 /* unaligned stores work in hw*/
-
-#define XCHAL_SW_VERSION 1100003 /* sw version of this header */
-
-#define XCHAL_CORE_ID "cavs21_LX6HiFi3_RF3_WB16" /* alphanum core name
- (CoreID) set in the Xtensa
- Processor Generator */
-
-#define XCHAL_BUILD_UNIQUE_ID 0x00060F88 /* 22-bit sw build ID */
-
-/*
- * These definitions describe the hardware targeted by this software.
- */
-#define XCHAL_HW_CONFIGID0 0xC2F3FBFE /* ConfigID hi 32 bits*/
-#define XCHAL_HW_CONFIGID1 0x1CC60F88 /* ConfigID lo 32 bits*/
-#define XCHAL_HW_VERSION_NAME "LX6.0.3" /* full version name */
-#define XCHAL_HW_VERSION_MAJOR 2600 /* major ver# of targeted hw */
-#define XCHAL_HW_VERSION_MINOR 3 /* minor ver# of targeted hw */
-#define XCHAL_HW_VERSION 260003 /* major*100+minor */
-#define XCHAL_HW_REL_LX6 1
-#define XCHAL_HW_REL_LX6_0 1
-#define XCHAL_HW_REL_LX6_0_3 1
-#define XCHAL_HW_CONFIGID_RELIABLE 1
-/* If software targets a *range* of hardware versions, these are the bounds: */
-#define XCHAL_HW_MIN_VERSION_MAJOR 2600 /* major v of earliest tgt hw */
-#define XCHAL_HW_MIN_VERSION_MINOR 3 /* minor v of earliest tgt hw */
-#define XCHAL_HW_MIN_VERSION 260003 /* earliest targeted hw */
-#define XCHAL_HW_MAX_VERSION_MAJOR 2600 /* major v of latest tgt hw */
-#define XCHAL_HW_MAX_VERSION_MINOR 3 /* minor v of latest tgt hw */
-#define XCHAL_HW_MAX_VERSION 260003 /* latest targeted hw */
-
-
-/*----------------------------------------------------------------------
- CACHE
- ----------------------------------------------------------------------*/
-
-#define XCHAL_ICACHE_LINESIZE 64 /* I-cache line size in bytes */
-#define XCHAL_DCACHE_LINESIZE 64 /* D-cache line size in bytes */
-#define XCHAL_ICACHE_LINEWIDTH 6 /* log2(I line size in bytes) */
-#define XCHAL_DCACHE_LINEWIDTH 6 /* log2(D line size in bytes) */
-
-#define XCHAL_ICACHE_SIZE 16384 /* I-cache size in bytes or 0 */
-#define XCHAL_DCACHE_SIZE 49152 /* D-cache size in bytes or 0 */
-
-#define XCHAL_DCACHE_IS_WRITEBACK 1 /* writeback feature */
-#define XCHAL_DCACHE_IS_COHERENT 0 /* MP coherence feature */
-
-#define XCHAL_HAVE_PREFETCH 1 /* PREFCTL register */
-#define XCHAL_HAVE_PREFETCH_L1 1 /* prefetch to L1 dcache */
-#define XCHAL_PREFETCH_CASTOUT_LINES 2 /* dcache pref. castout bufsz */
-#define XCHAL_PREFETCH_ENTRIES 8 /* cache prefetch entries */
-#define XCHAL_PREFETCH_BLOCK_ENTRIES 0 /* prefetch block streams */
-#define XCHAL_HAVE_CACHE_BLOCKOPS 0 /* block prefetch for caches */
-#define XCHAL_HAVE_ICACHE_TEST 1 /* Icache test instructions */
-#define XCHAL_HAVE_DCACHE_TEST 1 /* Dcache test instructions */
-#define XCHAL_HAVE_ICACHE_DYN_WAYS 1 /* Icache dynamic way support */
-#define XCHAL_HAVE_DCACHE_DYN_WAYS 1 /* Dcache dynamic way support */
-
-
-
-
-/****************************************************************************
- Parameters Useful for PRIVILEGED (Supervisory or Non-Virtualized) Code
- ****************************************************************************/
-
-
-#ifndef XTENSA_HAL_NON_PRIVILEGED_ONLY
-
-/*----------------------------------------------------------------------
- CACHE
- ----------------------------------------------------------------------*/
-
-#define XCHAL_HAVE_PIF 1 /* any outbound PIF present */
-#define XCHAL_HAVE_AXI 0 /* AXI bus */
-
-#define XCHAL_HAVE_PIF_WR_RESP 0 /* pif write response */
-#define XCHAL_HAVE_PIF_REQ_ATTR 1 /* pif attribute */
-
-/* If present, cache size in bytes == (ways * 2^(linewidth + setwidth)). */
-
-/* Number of cache sets in log2(lines per way): */
-#define XCHAL_ICACHE_SETWIDTH 6
-#define XCHAL_DCACHE_SETWIDTH 8
-
-/* Cache set associativity (number of ways): */
-#define XCHAL_ICACHE_WAYS 4
-#define XCHAL_DCACHE_WAYS 3
-
-/* Cache features: */
-#define XCHAL_ICACHE_LINE_LOCKABLE 1
-#define XCHAL_DCACHE_LINE_LOCKABLE 1
-#define XCHAL_ICACHE_ECC_PARITY XTHAL_MEMEP_ECC
-#define XCHAL_DCACHE_ECC_PARITY XTHAL_MEMEP_ECC
-
-/* Cache access size in bytes (affects operation of SICW instruction): */
-#define XCHAL_ICACHE_ACCESS_SIZE 8
-#define XCHAL_DCACHE_ACCESS_SIZE 8
-
-#define XCHAL_DCACHE_BANKS 1 /* number of banks */
-
-/* Number of encoded cache attr bits (see <xtensa/hal.h> for decoded bits): */
-#define XCHAL_CA_BITS 4
-
-
-/*----------------------------------------------------------------------
- INTERNAL I/D RAM/ROMs and XLMI
- ----------------------------------------------------------------------*/
-
-#define XCHAL_NUM_INSTROM 0 /* number of core instr. ROMs */
-#define XCHAL_NUM_INSTRAM 0 /* number of core instr. RAMs */
-#define XCHAL_NUM_DATAROM 0 /* number of core data ROMs */
-#define XCHAL_NUM_DATARAM 0 /* number of core data RAMs */
-#define XCHAL_NUM_URAM 0 /* number of core unified RAMs*/
-#define XCHAL_NUM_XLMI 0 /* number of core XLMI ports */
-
-#define XCHAL_HAVE_IMEM_LOADSTORE 1 /* can load/store to IROM/IRAM*/
-
-
-/*----------------------------------------------------------------------
- INTERRUPTS and TIMERS
- ----------------------------------------------------------------------*/
-
-#define XCHAL_HAVE_INTERRUPTS 1 /* interrupt option */
-#define XCHAL_HAVE_HIGHPRI_INTERRUPTS 1 /* med/high-pri. interrupts */
-#define XCHAL_HAVE_NMI 1 /* non-maskable interrupt */
-#define XCHAL_HAVE_CCOUNT 1 /* CCOUNT reg. (timer option) */
-#define XCHAL_NUM_TIMERS 3 /* number of CCOMPAREn regs */
-#define XCHAL_NUM_INTERRUPTS 21 /* number of interrupts */
-#define XCHAL_NUM_INTERRUPTS_LOG2 5 /* ceil(log2(NUM_INTERRUPTS)) */
-#define XCHAL_NUM_EXTINTERRUPTS 8 /* num of external interrupts */
-#define XCHAL_NUM_INTLEVELS 6 /* number of interrupt levels
- (not including level zero) */
-#define XCHAL_EXCM_LEVEL 5 /* level masked by PS.EXCM */
- /* (always 1 in XEA1; levels 2 .. EXCM_LEVEL are "medium priority") */
-
-/* Masks of interrupts at each interrupt level: */
-#define XCHAL_INTLEVEL1_MASK 0x0000000F
-#define XCHAL_INTLEVEL2_MASK 0x000000F0
-#define XCHAL_INTLEVEL3_MASK 0x00000F00
-#define XCHAL_INTLEVEL4_MASK 0x00007000
-#define XCHAL_INTLEVEL5_MASK 0x000F8000
-#define XCHAL_INTLEVEL6_MASK 0x00000000
-#define XCHAL_INTLEVEL7_MASK 0x00100000
-
-/* Masks of interrupts at each range 1..n of interrupt levels: */
-#define XCHAL_INTLEVEL1_ANDBELOW_MASK 0x0000000F
-#define XCHAL_INTLEVEL2_ANDBELOW_MASK 0x000000FF
-#define XCHAL_INTLEVEL3_ANDBELOW_MASK 0x00000FFF
-#define XCHAL_INTLEVEL4_ANDBELOW_MASK 0x00007FFF
-#define XCHAL_INTLEVEL5_ANDBELOW_MASK 0x000FFFFF
-#define XCHAL_INTLEVEL6_ANDBELOW_MASK 0x000FFFFF
-#define XCHAL_INTLEVEL7_ANDBELOW_MASK 0x001FFFFF
-
-/* Level of each interrupt: */
-#define XCHAL_INT0_LEVEL 1
-#define XCHAL_INT1_LEVEL 1
-#define XCHAL_INT2_LEVEL 1
-#define XCHAL_INT3_LEVEL 1
-#define XCHAL_INT4_LEVEL 2
-#define XCHAL_INT5_LEVEL 2
-#define XCHAL_INT6_LEVEL 2
-#define XCHAL_INT7_LEVEL 2
-#define XCHAL_INT8_LEVEL 3
-#define XCHAL_INT9_LEVEL 3
-#define XCHAL_INT10_LEVEL 3
-#define XCHAL_INT11_LEVEL 3
-#define XCHAL_INT12_LEVEL 4
-#define XCHAL_INT13_LEVEL 4
-#define XCHAL_INT14_LEVEL 4
-#define XCHAL_INT15_LEVEL 5
-#define XCHAL_INT16_LEVEL 5
-#define XCHAL_INT17_LEVEL 5
-#define XCHAL_INT18_LEVEL 5
-#define XCHAL_INT19_LEVEL 5
-#define XCHAL_INT20_LEVEL 7
-#define XCHAL_DEBUGLEVEL 6 /* debug interrupt level */
-#define XCHAL_HAVE_DEBUG_EXTERN_INT 1 /* OCD external db interrupt */
-#define XCHAL_NMILEVEL 7 /* NMI "level" (for use with
- EXCSAVE/EPS/EPC_n, RFI n) */
-
-/* Type of each interrupt: */
-#define XCHAL_INT0_TYPE XTHAL_INTTYPE_SOFTWARE
-#define XCHAL_INT1_TYPE XTHAL_INTTYPE_TIMER
-#define XCHAL_INT2_TYPE XTHAL_INTTYPE_EXTERN_LEVEL
-#define XCHAL_INT3_TYPE XTHAL_INTTYPE_SOFTWARE
-#define XCHAL_INT4_TYPE XTHAL_INTTYPE_SOFTWARE
-#define XCHAL_INT5_TYPE XTHAL_INTTYPE_TIMER
-#define XCHAL_INT6_TYPE XTHAL_INTTYPE_EXTERN_LEVEL
-#define XCHAL_INT7_TYPE XTHAL_INTTYPE_SOFTWARE
-#define XCHAL_INT8_TYPE XTHAL_INTTYPE_SOFTWARE
-#define XCHAL_INT9_TYPE XTHAL_INTTYPE_TIMER
-#define XCHAL_INT10_TYPE XTHAL_INTTYPE_EXTERN_LEVEL
-#define XCHAL_INT11_TYPE XTHAL_INTTYPE_SOFTWARE
-#define XCHAL_INT12_TYPE XTHAL_INTTYPE_SOFTWARE
-#define XCHAL_INT13_TYPE XTHAL_INTTYPE_EXTERN_LEVEL
-#define XCHAL_INT14_TYPE XTHAL_INTTYPE_SOFTWARE
-#define XCHAL_INT15_TYPE XTHAL_INTTYPE_SOFTWARE
-#define XCHAL_INT16_TYPE XTHAL_INTTYPE_EXTERN_LEVEL
-#define XCHAL_INT17_TYPE XTHAL_INTTYPE_EXTERN_LEVEL
-#define XCHAL_INT18_TYPE XTHAL_INTTYPE_EXTERN_LEVEL
-#define XCHAL_INT19_TYPE XTHAL_INTTYPE_SOFTWARE
-#define XCHAL_INT20_TYPE XTHAL_INTTYPE_NMI
-
-/* Masks of interrupts for each type of interrupt: */
-#define XCHAL_INTTYPE_MASK_UNCONFIGURED 0xFFE00000
-#define XCHAL_INTTYPE_MASK_SOFTWARE 0x0008D999
-#define XCHAL_INTTYPE_MASK_EXTERN_EDGE 0x00000000
-#define XCHAL_INTTYPE_MASK_EXTERN_LEVEL 0x00072444
-#define XCHAL_INTTYPE_MASK_TIMER 0x00000222
-#define XCHAL_INTTYPE_MASK_NMI 0x00100000
-#define XCHAL_INTTYPE_MASK_WRITE_ERROR 0x00000000
-#define XCHAL_INTTYPE_MASK_PROFILING 0x00000000
-
-/* Interrupt numbers assigned to specific interrupt sources: */
-#define XCHAL_TIMER0_INTERRUPT 1 /* CCOMPARE0 */
-#define XCHAL_TIMER1_INTERRUPT 5 /* CCOMPARE1 */
-#define XCHAL_TIMER2_INTERRUPT 9 /* CCOMPARE2 */
-#define XCHAL_TIMER3_INTERRUPT XTHAL_TIMER_UNCONFIGURED
-#define XCHAL_NMI_INTERRUPT 20 /* non-maskable interrupt */
-
-/* Interrupt numbers for levels at which only one interrupt is configured: */
-#define XCHAL_INTLEVEL7_NUM 20
-/* (There are many interrupts each at level(s) 1, 2, 3, 4, 5.) */
-
-
-/*
- * External interrupt mapping.
- * These macros describe how Xtensa processor interrupt numbers
- * (as numbered internally, eg. in INTERRUPT and INTENABLE registers)
- * map to external BInterrupt<n> pins, for those interrupts
- * configured as external (level-triggered, edge-triggered, or NMI).
- * See the Xtensa processor databook for more details.
- */
-
-/* Core interrupt numbers mapped to each EXTERNAL BInterrupt pin number: */
-#define XCHAL_EXTINT0_NUM 2 /* (intlevel 1) */
-#define XCHAL_EXTINT1_NUM 6 /* (intlevel 2) */
-#define XCHAL_EXTINT2_NUM 10 /* (intlevel 3) */
-#define XCHAL_EXTINT3_NUM 13 /* (intlevel 4) */
-#define XCHAL_EXTINT4_NUM 16 /* (intlevel 5) */
-#define XCHAL_EXTINT5_NUM 17 /* (intlevel 5) */
-#define XCHAL_EXTINT6_NUM 18 /* (intlevel 5) */
-#define XCHAL_EXTINT7_NUM 20 /* (intlevel 7) */
-/* EXTERNAL BInterrupt pin numbers mapped to each core interrupt number: */
-#define XCHAL_INT2_EXTNUM 0 /* (intlevel 1) */
-#define XCHAL_INT6_EXTNUM 1 /* (intlevel 2) */
-#define XCHAL_INT10_EXTNUM 2 /* (intlevel 3) */
-#define XCHAL_INT13_EXTNUM 3 /* (intlevel 4) */
-#define XCHAL_INT16_EXTNUM 4 /* (intlevel 5) */
-#define XCHAL_INT17_EXTNUM 5 /* (intlevel 5) */
-#define XCHAL_INT18_EXTNUM 6 /* (intlevel 5) */
-#define XCHAL_INT20_EXTNUM 7 /* (intlevel 7) */
-
-
-/*----------------------------------------------------------------------
- EXCEPTIONS and VECTORS
- ----------------------------------------------------------------------*/
-
-#define XCHAL_XEA_VERSION 2 /* Xtensa Exception Architecture
- number: 1 == XEA1 (old)
- 2 == XEA2 (new)
- 0 == XEAX (extern) or TX */
-#define XCHAL_HAVE_XEA1 0 /* Exception Architecture 1 */
-#define XCHAL_HAVE_XEA2 1 /* Exception Architecture 2 */
-#define XCHAL_HAVE_XEAX 0 /* External Exception Arch. */
-#define XCHAL_HAVE_EXCEPTIONS 1 /* exception option */
-#define XCHAL_HAVE_HALT 0 /* halt architecture option */
-#define XCHAL_HAVE_BOOTLOADER 1 /* boot loader (for TX) */
-#define XCHAL_HAVE_MEM_ECC_PARITY 1 /* local memory ECC/parity */
-#define XCHAL_HAVE_VECTOR_SELECT 1 /* relocatable vectors */
-#define XCHAL_HAVE_VECBASE 1 /* relocatable vectors */
-#define XCHAL_VECBASE_RESET_VADDR 0xBEFE0800 /* VECBASE reset value */
-#define XCHAL_VECBASE_RESET_PADDR 0xBEFE0800
-#define XCHAL_RESET_VECBASE_OVERLAP 0
-
-#define XCHAL_RESET_VECTOR0_VADDR 0xBEFE0000
-#define XCHAL_RESET_VECTOR0_PADDR 0xBEFE0000
-#define XCHAL_RESET_VECTOR1_VADDR 0xBE800000
-#define XCHAL_RESET_VECTOR1_PADDR 0xBE800000
-#define XCHAL_RESET_VECTOR_VADDR 0xBEFE0000
-#define XCHAL_RESET_VECTOR_PADDR 0xBEFE0000
-#define XCHAL_MEMERROR_VECTOR0_VADDR 0xBEFE0400
-#define XCHAL_MEMERROR_VECTOR0_PADDR 0xBEFE0400
-#define XCHAL_MEMERROR_VECTOR1_VADDR 0xBE800400
-#define XCHAL_MEMERROR_VECTOR1_PADDR 0xBE800400
-#define XCHAL_MEMERROR_VECTOR_VADDR 0xBEFE0400
-#define XCHAL_MEMERROR_VECTOR_PADDR 0xBEFE0400
-#define XCHAL_USER_VECOFS 0x00000340
-#define XCHAL_USER_VECTOR_VADDR 0xBEFE0B40
-#define XCHAL_USER_VECTOR_PADDR 0xBEFE0B40
-#define XCHAL_KERNEL_VECOFS 0x00000300
-#define XCHAL_KERNEL_VECTOR_VADDR 0xBEFE0B00
-#define XCHAL_KERNEL_VECTOR_PADDR 0xBEFE0B00
-#define XCHAL_DOUBLEEXC_VECOFS 0x000003C0
-#define XCHAL_DOUBLEEXC_VECTOR_VADDR 0xBEFE0BC0
-#define XCHAL_DOUBLEEXC_VECTOR_PADDR 0xBEFE0BC0
-#define XCHAL_WINDOW_OF4_VECOFS 0x00000000
-#define XCHAL_WINDOW_UF4_VECOFS 0x00000040
-#define XCHAL_WINDOW_OF8_VECOFS 0x00000080
-#define XCHAL_WINDOW_UF8_VECOFS 0x000000C0
-#define XCHAL_WINDOW_OF12_VECOFS 0x00000100
-#define XCHAL_WINDOW_UF12_VECOFS 0x00000140
-#define XCHAL_WINDOW_VECTORS_VADDR 0xBEFE0800
-#define XCHAL_WINDOW_VECTORS_PADDR 0xBEFE0800
-#define XCHAL_INTLEVEL2_VECOFS 0x00000180
-#define XCHAL_INTLEVEL2_VECTOR_VADDR 0xBEFE0980
-#define XCHAL_INTLEVEL2_VECTOR_PADDR 0xBEFE0980
-#define XCHAL_INTLEVEL3_VECOFS 0x000001C0
-#define XCHAL_INTLEVEL3_VECTOR_VADDR 0xBEFE09C0
-#define XCHAL_INTLEVEL3_VECTOR_PADDR 0xBEFE09C0
-#define XCHAL_INTLEVEL4_VECOFS 0x00000200
-#define XCHAL_INTLEVEL4_VECTOR_VADDR 0xBEFE0A00
-#define XCHAL_INTLEVEL4_VECTOR_PADDR 0xBEFE0A00
-#define XCHAL_INTLEVEL5_VECOFS 0x00000240
-#define XCHAL_INTLEVEL5_VECTOR_VADDR 0xBEFE0A40
-#define XCHAL_INTLEVEL5_VECTOR_PADDR 0xBEFE0A40
-#define XCHAL_INTLEVEL6_VECOFS 0x00000280
-#define XCHAL_INTLEVEL6_VECTOR_VADDR 0xBEFE0A80
-#define XCHAL_INTLEVEL6_VECTOR_PADDR 0xBEFE0A80
-#define XCHAL_DEBUG_VECOFS XCHAL_INTLEVEL6_VECOFS
-#define XCHAL_DEBUG_VECTOR_VADDR XCHAL_INTLEVEL6_VECTOR_VADDR
-#define XCHAL_DEBUG_VECTOR_PADDR XCHAL_INTLEVEL6_VECTOR_PADDR
-#define XCHAL_NMI_VECOFS 0x000002C0
-#define XCHAL_NMI_VECTOR_VADDR 0xBEFE0AC0
-#define XCHAL_NMI_VECTOR_PADDR 0xBEFE0AC0
-#define XCHAL_INTLEVEL7_VECOFS XCHAL_NMI_VECOFS
-#define XCHAL_INTLEVEL7_VECTOR_VADDR XCHAL_NMI_VECTOR_VADDR
-#define XCHAL_INTLEVEL7_VECTOR_PADDR XCHAL_NMI_VECTOR_PADDR
-
-
-/*----------------------------------------------------------------------
- DEBUG MODULE
- ----------------------------------------------------------------------*/
-
-/* Misc */
-#define XCHAL_HAVE_DEBUG_ERI 0 /* ERI to debug module */
-#define XCHAL_HAVE_DEBUG_APB 0 /* APB to debug module */
-#define XCHAL_HAVE_DEBUG_JTAG 1 /* JTAG to debug module */
-
-/* On-Chip Debug (OCD) */
-#define XCHAL_HAVE_OCD 1 /* OnChipDebug option */
-#define XCHAL_NUM_IBREAK 2 /* number of IBREAKn regs */
-#define XCHAL_NUM_DBREAK 2 /* number of DBREAKn regs */
-#define XCHAL_HAVE_OCD_DIR_ARRAY 0 /* faster OCD option (to LX4) */
-#define XCHAL_HAVE_OCD_LS32DDR 1 /* L32DDR/S32DDR (faster OCD) */
-
-/* TRAX (in core) */
-#define XCHAL_HAVE_TRAX 0 /* TRAX in debug module */
-#define XCHAL_TRAX_MEM_SIZE 0 /* TRAX memory size in bytes */
-#define XCHAL_TRAX_MEM_SHAREABLE 0 /* start/end regs; ready sig. */
-#define XCHAL_TRAX_ATB_WIDTH 0 /* ATB width (bits), 0=no ATB */
-#define XCHAL_TRAX_TIME_WIDTH 0 /* timestamp bitwidth, 0=none */
-
-/* Perf counters */
-#define XCHAL_NUM_PERF_COUNTERS 0 /* performance counters */
-
-
-/*----------------------------------------------------------------------
- MMU
- ----------------------------------------------------------------------*/
-
-/* See core-matmap.h header file for more details. */
-
-#define XCHAL_HAVE_TLBS 1 /* inverse of HAVE_CACHEATTR */
-#define XCHAL_HAVE_SPANNING_WAY 1 /* one way maps I+D 4GB vaddr */
-#define XCHAL_SPANNING_WAY 0 /* TLB spanning way number */
-#define XCHAL_HAVE_IDENTITY_MAP 1 /* vaddr == paddr always */
-#define XCHAL_HAVE_CACHEATTR 0 /* CACHEATTR register present */
-#define XCHAL_HAVE_MIMIC_CACHEATTR 1 /* region protection */
-#define XCHAL_HAVE_XLT_CACHEATTR 0 /* region prot. w/translation */
-#define XCHAL_HAVE_PTP_MMU 0 /* full MMU (with page table
- [autorefill] and protection)
- usable for an MMU-based OS */
-/* If none of the above last 4 are set, it's a custom TLB configuration. */
-
-#define XCHAL_MMU_ASID_BITS 0 /* number of bits in ASIDs */
-#define XCHAL_MMU_RINGS 1 /* number of rings (1..4) */
-#define XCHAL_MMU_RING_BITS 0 /* num of bits in RING field */
-
-#endif /* !XTENSA_HAL_NON_PRIVILEGED_ONLY */
-
-
-#endif /* _XTENSA_CORE_CONFIGURATION_H */
-
-#else
-
-#error "xcc should not use this header"
-
-#endif /* __XCC__ */
diff --git a/src/platform/cannonlake/include/arch/xtensa/config/core-matmap.h b/src/platform/cannonlake/include/arch/xtensa/config/core-matmap.h
deleted file mode 100644
index ad0f0d7..0000000
--- a/src/platform/cannonlake/include/arch/xtensa/config/core-matmap.h
+++ /dev/null
@@ -1,320 +0,0 @@
-/*
- * xtensa/config/core-matmap.h -- Memory access and translation mapping
- * parameters (CHAL) of the Xtensa processor core configuration.
- *
- * If you are using Xtensa Tools, see <xtensa/config/core.h> (which includes
- * this file) for more details.
- *
- * In the Xtensa processor products released to date, all parameters
- * defined in this file are derivable (at least in theory) from
- * information contained in the core-isa.h header file.
- * In particular, the following core configuration parameters are relevant:
- * XCHAL_HAVE_CACHEATTR
- * XCHAL_HAVE_MIMIC_CACHEATTR
- * XCHAL_HAVE_XLT_CACHEATTR
- * XCHAL_HAVE_PTP_MMU
- * XCHAL_ITLB_ARF_ENTRIES_LOG2
- * XCHAL_DTLB_ARF_ENTRIES_LOG2
- * XCHAL_DCACHE_IS_WRITEBACK
- * XCHAL_ICACHE_SIZE (presence of I-cache)
- * XCHAL_DCACHE_SIZE (presence of D-cache)
- * XCHAL_HW_VERSION_MAJOR
- * XCHAL_HW_VERSION_MINOR
- */
-
-/* Customer ID=4313; Build=0x5483b; Copyright (c) 1999-2015 Tensilica Inc.
-
- Permission is hereby granted, free of charge, to any person obtaining
- a copy of this software and associated documentation files (the
- "Software"), to deal in the Software without restriction, including
- without limitation the rights to use, copy, modify, merge, publish,
- distribute, sublicense, and/or sell copies of the Software, and to
- permit persons to whom the Software is furnished to do so, subject to
- the following conditions:
-
- The above copyright notice and this permission notice shall be included
- in all copies or substantial portions of the Software.
-
- THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
- EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
- MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
- IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY
- CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
- TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
- SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. */
-
-#if !defined __XCC__
-
-#ifndef XTENSA_CONFIG_CORE_MATMAP_H
-#define XTENSA_CONFIG_CORE_MATMAP_H
-
-
-/*----------------------------------------------------------------------
- CACHE (MEMORY ACCESS) ATTRIBUTES
- ----------------------------------------------------------------------*/
-
-
-/* Cache Attribute encodings -- lists of access modes for each cache attribute: */
-#define XCHAL_FCA_LIST XTHAL_FAM_EXCEPTION XCHAL_SEP \
- XTHAL_FAM_CACHED XCHAL_SEP \
- XTHAL_FAM_BYPASS XCHAL_SEP \
- XTHAL_FAM_CACHED XCHAL_SEP \
- XTHAL_FAM_CACHED XCHAL_SEP \
- XTHAL_FAM_CACHED XCHAL_SEP \
- XTHAL_FAM_BYPASS XCHAL_SEP \
- XTHAL_FAM_EXCEPTION XCHAL_SEP \
- XTHAL_FAM_EXCEPTION XCHAL_SEP \
- XTHAL_FAM_EXCEPTION XCHAL_SEP \
- XTHAL_FAM_EXCEPTION XCHAL_SEP \
- XTHAL_FAM_EXCEPTION XCHAL_SEP \
- XTHAL_FAM_EXCEPTION XCHAL_SEP \
- XTHAL_FAM_EXCEPTION XCHAL_SEP \
- XTHAL_FAM_EXCEPTION XCHAL_SEP \
- XTHAL_FAM_EXCEPTION
-#define XCHAL_LCA_LIST XTHAL_LAM_CACHED_NOALLOC XCHAL_SEP \
- XTHAL_LAM_CACHED XCHAL_SEP \
- XTHAL_LAM_BYPASSG XCHAL_SEP \
- XTHAL_LAM_EXCEPTION XCHAL_SEP \
- XTHAL_LAM_CACHED XCHAL_SEP \
- XTHAL_LAM_CACHED XCHAL_SEP \
- XTHAL_LAM_BYPASSG XCHAL_SEP \
- XTHAL_LAM_EXCEPTION XCHAL_SEP \
- XTHAL_LAM_EXCEPTION XCHAL_SEP \
- XTHAL_LAM_EXCEPTION XCHAL_SEP \
- XTHAL_LAM_EXCEPTION XCHAL_SEP \
- XTHAL_LAM_EXCEPTION XCHAL_SEP \
- XTHAL_LAM_EXCEPTION XCHAL_SEP \
- XTHAL_LAM_EXCEPTION XCHAL_SEP \
- XTHAL_LAM_ISOLATE XCHAL_SEP \
- XTHAL_LAM_EXCEPTION
-#define XCHAL_SCA_LIST XTHAL_SAM_WRITETHRU XCHAL_SEP \
- XTHAL_SAM_WRITETHRU XCHAL_SEP \
- XTHAL_SAM_BYPASS XCHAL_SEP \
- XTHAL_SAM_EXCEPTION XCHAL_SEP \
- XTHAL_SAM_WRITEBACK XCHAL_SEP \
- XTHAL_SAM_WRITEBACK_NOALLOC XCHAL_SEP \
- XTHAL_SAM_BYPASS XCHAL_SEP \
- XTHAL_SAM_EXCEPTION XCHAL_SEP \
- XTHAL_SAM_EXCEPTION XCHAL_SEP \
- XTHAL_SAM_EXCEPTION XCHAL_SEP \
- XTHAL_SAM_EXCEPTION XCHAL_SEP \
- XTHAL_SAM_EXCEPTION XCHAL_SEP \
- XTHAL_SAM_EXCEPTION XCHAL_SEP \
- XTHAL_SAM_EXCEPTION XCHAL_SEP \
- XTHAL_SAM_ISOLATE XCHAL_SEP \
- XTHAL_SAM_EXCEPTION
-
-
-/*
- * Specific encoded cache attribute values of general interest.
- * If a specific cache mode is not available, the closest available
- * one is returned instead (eg. writethru instead of writeback,
- * bypass instead of writethru).
- */
-#define XCHAL_CA_BYPASS 2 /* cache disabled (bypassed) mode */
-#define XCHAL_CA_BYPASSBUF 6 /* cache disabled (bypassed) bufferable mode */
-#define XCHAL_CA_WRITETHRU 1 /* cache enabled (write-through) mode */
-#define XCHAL_CA_WRITEBACK 4 /* cache enabled (write-back) mode */
-#define XCHAL_HAVE_CA_WRITEBACK_NOALLOC 1 /* write-back no-allocate availability */
-#define XCHAL_CA_WRITEBACK_NOALLOC 5 /* cache enabled (write-back no-allocate) mode */
-#define XCHAL_CA_ILLEGAL 15 /* no access allowed (all cause exceptions) mode */
-#define XCHAL_CA_ISOLATE 14 /* cache isolate (accesses go to cache not memory) mode */
-
-
-/*----------------------------------------------------------------------
- MMU
- ----------------------------------------------------------------------*/
-
-/*
- * General notes on MMU parameters.
- *
- * Terminology:
- * ASID = address-space ID (acts as an "extension" of virtual addresses)
- * VPN = virtual page number
- * PPN = physical page number
- * CA = encoded cache attribute (access modes)
- * TLB = translation look-aside buffer (term is stretched somewhat here)
- * I = instruction (fetch accesses)
- * D = data (load and store accesses)
- * way = each TLB (ITLB and DTLB) consists of a number of "ways"
- * that simultaneously match the virtual address of an access;
- * a TLB successfully translates a virtual address if exactly
- * one way matches the vaddr; if none match, it is a miss;
- * if multiple match, one gets a "multihit" exception;
- * each way can be independently configured in terms of number of
- * entries, page sizes, which fields are writable or constant, etc.
- * set = group of contiguous ways with exactly identical parameters
- * ARF = auto-refill; hardware services a 1st-level miss by loading a PTE
- * from the page table and storing it in one of the auto-refill ways;
- * if this PTE load also misses, a miss exception is posted for s/w.
- * min-wired = a "min-wired" way can be used to map a single (minimum-sized)
- * page arbitrarily under program control; it has a single entry,
- * is non-auto-refill (some other way(s) must be auto-refill),
- * all its fields (VPN, PPN, ASID, CA) are all writable, and it
- * supports the XCHAL_MMU_MIN_PTE_PAGE_SIZE page size (a current
- * restriction is that this be the only page size it supports).
- *
- * TLB way entries are virtually indexed.
- * TLB ways that support multiple page sizes:
- * - must have all writable VPN and PPN fields;
- * - can only use one page size at any given time (eg. setup at startup),
- * selected by the respective ITLBCFG or DTLBCFG special register,
- * whose bits n*4+3 .. n*4 index the list of page sizes for way n
- * (XCHAL_xTLB_SETm_PAGESZ_LOG2_LIST for set m corresponding to way n);
- * this list may be sparse for auto-refill ways because auto-refill
- * ways have independent lists of supported page sizes sharing a
- * common encoding with PTE entries; the encoding is the index into
- * this list; unsupported sizes for a given way are zero in the list;
- * selecting unsupported sizes results in undefined hardware behaviour;
- * - is only possible for ways 0 thru 7 (due to ITLBCFG/DTLBCFG definition).
- */
-
-#define XCHAL_MMU_ASID_INVALID 0 /* ASID value indicating invalid address space */
-#define XCHAL_MMU_ASID_KERNEL 0 /* ASID value indicating kernel (ring 0) address space */
-#define XCHAL_MMU_SR_BITS 0 /* number of size-restriction bits supported */
-#define XCHAL_MMU_CA_BITS 4 /* number of bits needed to hold cache attribute encoding */
-#define XCHAL_MMU_MAX_PTE_PAGE_SIZE 29 /* max page size in a PTE structure (log2) */
-#define XCHAL_MMU_MIN_PTE_PAGE_SIZE 29 /* min page size in a PTE structure (log2) */
-
-
-/*** Instruction TLB: ***/
-
-#define XCHAL_ITLB_WAY_BITS 0 /* number of bits holding the ways */
-#define XCHAL_ITLB_WAYS 1 /* number of ways (n-way set-associative TLB) */
-#define XCHAL_ITLB_ARF_WAYS 0 /* number of auto-refill ways */
-#define XCHAL_ITLB_SETS 1 /* number of sets (groups of ways with identical settings) */
-
-/* Way set to which each way belongs: */
-#define XCHAL_ITLB_WAY0_SET 0
-
-/* Ways sets that are used by hardware auto-refill (ARF): */
-#define XCHAL_ITLB_ARF_SETS 0 /* number of auto-refill sets */
-
-/* Way sets that are "min-wired" (see terminology comment above): */
-#define XCHAL_ITLB_MINWIRED_SETS 0 /* number of "min-wired" sets */
-
-
-/* ITLB way set 0 (group of ways 0 thru 0): */
-#define XCHAL_ITLB_SET0_WAY 0 /* index of first way in this way set */
-#define XCHAL_ITLB_SET0_WAYS 1 /* number of (contiguous) ways in this way set */
-#define XCHAL_ITLB_SET0_ENTRIES_LOG2 3 /* log2(number of entries in this way) */
-#define XCHAL_ITLB_SET0_ENTRIES 8 /* number of entries in this way (always a power of 2) */
-#define XCHAL_ITLB_SET0_ARF 0 /* 1=autorefill by h/w, 0=non-autorefill (wired/constant/static) */
-#define XCHAL_ITLB_SET0_PAGESIZES 1 /* number of supported page sizes in this way */
-#define XCHAL_ITLB_SET0_PAGESZ_BITS 0 /* number of bits to encode the page size */
-#define XCHAL_ITLB_SET0_PAGESZ_LOG2_MIN 29 /* log2(minimum supported page size) */
-#define XCHAL_ITLB_SET0_PAGESZ_LOG2_MAX 29 /* log2(maximum supported page size) */
-#define XCHAL_ITLB_SET0_PAGESZ_LOG2_LIST 29 /* list of log2(page size)s, separated by XCHAL_SEP;
- 2^PAGESZ_BITS entries in list, unsupported entries are zero */
-#define XCHAL_ITLB_SET0_ASID_CONSTMASK 0 /* constant ASID bits; 0 if all writable */
-#define XCHAL_ITLB_SET0_VPN_CONSTMASK 0x00000000 /* constant VPN bits, not including entry index bits; 0 if all writable */
-#define XCHAL_ITLB_SET0_PPN_CONSTMASK 0xE0000000 /* constant PPN bits, including entry index bits; 0 if all writable */
-#define XCHAL_ITLB_SET0_CA_CONSTMASK 0 /* constant CA bits; 0 if all writable */
-#define XCHAL_ITLB_SET0_ASID_RESET 0 /* 1 if ASID reset values defined (and all writable); 0 otherwise */
-#define XCHAL_ITLB_SET0_VPN_RESET 0 /* 1 if VPN reset values defined (and all writable); 0 otherwise */
-#define XCHAL_ITLB_SET0_PPN_RESET 0 /* 1 if PPN reset values defined (and all writable); 0 otherwise */
-#define XCHAL_ITLB_SET0_CA_RESET 1 /* 1 if CA reset values defined (and all writable); 0 otherwise */
-/* Constant VPN values for each entry of ITLB way set 0 (because VPN_CONSTMASK is non-zero): */
-#define XCHAL_ITLB_SET0_E0_VPN_CONST 0x00000000
-#define XCHAL_ITLB_SET0_E1_VPN_CONST 0x20000000
-#define XCHAL_ITLB_SET0_E2_VPN_CONST 0x40000000
-#define XCHAL_ITLB_SET0_E3_VPN_CONST 0x60000000
-#define XCHAL_ITLB_SET0_E4_VPN_CONST 0x80000000
-#define XCHAL_ITLB_SET0_E5_VPN_CONST 0xA0000000
-#define XCHAL_ITLB_SET0_E6_VPN_CONST 0xC0000000
-#define XCHAL_ITLB_SET0_E7_VPN_CONST 0xE0000000
-/* Constant PPN values for each entry of ITLB way set 0 (because PPN_CONSTMASK is non-zero): */
-#define XCHAL_ITLB_SET0_E0_PPN_CONST 0x00000000
-#define XCHAL_ITLB_SET0_E1_PPN_CONST 0x20000000
-#define XCHAL_ITLB_SET0_E2_PPN_CONST 0x40000000
-#define XCHAL_ITLB_SET0_E3_PPN_CONST 0x60000000
-#define XCHAL_ITLB_SET0_E4_PPN_CONST 0x80000000
-#define XCHAL_ITLB_SET0_E5_PPN_CONST 0xA0000000
-#define XCHAL_ITLB_SET0_E6_PPN_CONST 0xC0000000
-#define XCHAL_ITLB_SET0_E7_PPN_CONST 0xE0000000
-/* Reset CA values for each entry of ITLB way set 0 (because SET0_CA_RESET is non-zero): */
-#define XCHAL_ITLB_SET0_E0_CA_RESET 0x02
-#define XCHAL_ITLB_SET0_E1_CA_RESET 0x02
-#define XCHAL_ITLB_SET0_E2_CA_RESET 0x02
-#define XCHAL_ITLB_SET0_E3_CA_RESET 0x02
-#define XCHAL_ITLB_SET0_E4_CA_RESET 0x02
-#define XCHAL_ITLB_SET0_E5_CA_RESET 0x02
-#define XCHAL_ITLB_SET0_E6_CA_RESET 0x02
-#define XCHAL_ITLB_SET0_E7_CA_RESET 0x02
-
-
-/*** Data TLB: ***/
-
-#define XCHAL_DTLB_WAY_BITS 0 /* number of bits holding the ways */
-#define XCHAL_DTLB_WAYS 1 /* number of ways (n-way set-associative TLB) */
-#define XCHAL_DTLB_ARF_WAYS 0 /* number of auto-refill ways */
-#define XCHAL_DTLB_SETS 1 /* number of sets (groups of ways with identical settings) */
-
-/* Way set to which each way belongs: */
-#define XCHAL_DTLB_WAY0_SET 0
-
-/* Ways sets that are used by hardware auto-refill (ARF): */
-#define XCHAL_DTLB_ARF_SETS 0 /* number of auto-refill sets */
-
-/* Way sets that are "min-wired" (see terminology comment above): */
-#define XCHAL_DTLB_MINWIRED_SETS 0 /* number of "min-wired" sets */
-
-
-/* DTLB way set 0 (group of ways 0 thru 0): */
-#define XCHAL_DTLB_SET0_WAY 0 /* index of first way in this way set */
-#define XCHAL_DTLB_SET0_WAYS 1 /* number of (contiguous) ways in this way set */
-#define XCHAL_DTLB_SET0_ENTRIES_LOG2 3 /* log2(number of entries in this way) */
-#define XCHAL_DTLB_SET0_ENTRIES 8 /* number of entries in this way (always a power of 2) */
-#define XCHAL_DTLB_SET0_ARF 0 /* 1=autorefill by h/w, 0=non-autorefill (wired/constant/static) */
-#define XCHAL_DTLB_SET0_PAGESIZES 1 /* number of supported page sizes in this way */
-#define XCHAL_DTLB_SET0_PAGESZ_BITS 0 /* number of bits to encode the page size */
-#define XCHAL_DTLB_SET0_PAGESZ_LOG2_MIN 29 /* log2(minimum supported page size) */
-#define XCHAL_DTLB_SET0_PAGESZ_LOG2_MAX 29 /* log2(maximum supported page size) */
-#define XCHAL_DTLB_SET0_PAGESZ_LOG2_LIST 29 /* list of log2(page size)s, separated by XCHAL_SEP;
- 2^PAGESZ_BITS entries in list, unsupported entries are zero */
-#define XCHAL_DTLB_SET0_ASID_CONSTMASK 0 /* constant ASID bits; 0 if all writable */
-#define XCHAL_DTLB_SET0_VPN_CONSTMASK 0x00000000 /* constant VPN bits, not including entry index bits; 0 if all writable */
-#define XCHAL_DTLB_SET0_PPN_CONSTMASK 0xE0000000 /* constant PPN bits, including entry index bits; 0 if all writable */
-#define XCHAL_DTLB_SET0_CA_CONSTMASK 0 /* constant CA bits; 0 if all writable */
-#define XCHAL_DTLB_SET0_ASID_RESET 0 /* 1 if ASID reset values defined (and all writable); 0 otherwise */
-#define XCHAL_DTLB_SET0_VPN_RESET 0 /* 1 if VPN reset values defined (and all writable); 0 otherwise */
-#define XCHAL_DTLB_SET0_PPN_RESET 0 /* 1 if PPN reset values defined (and all writable); 0 otherwise */
-#define XCHAL_DTLB_SET0_CA_RESET 1 /* 1 if CA reset values defined (and all writable); 0 otherwise */
-/* Constant VPN values for each entry of DTLB way set 0 (because VPN_CONSTMASK is non-zero): */
-#define XCHAL_DTLB_SET0_E0_VPN_CONST 0x00000000
-#define XCHAL_DTLB_SET0_E1_VPN_CONST 0x20000000
-#define XCHAL_DTLB_SET0_E2_VPN_CONST 0x40000000
-#define XCHAL_DTLB_SET0_E3_VPN_CONST 0x60000000
-#define XCHAL_DTLB_SET0_E4_VPN_CONST 0x80000000
-#define XCHAL_DTLB_SET0_E5_VPN_CONST 0xA0000000
-#define XCHAL_DTLB_SET0_E6_VPN_CONST 0xC0000000
-#define XCHAL_DTLB_SET0_E7_VPN_CONST 0xE0000000
-/* Constant PPN values for each entry of DTLB way set 0 (because PPN_CONSTMASK is non-zero): */
-#define XCHAL_DTLB_SET0_E0_PPN_CONST 0x00000000
-#define XCHAL_DTLB_SET0_E1_PPN_CONST 0x20000000
-#define XCHAL_DTLB_SET0_E2_PPN_CONST 0x40000000
-#define XCHAL_DTLB_SET0_E3_PPN_CONST 0x60000000
-#define XCHAL_DTLB_SET0_E4_PPN_CONST 0x80000000
-#define XCHAL_DTLB_SET0_E5_PPN_CONST 0xA0000000
-#define XCHAL_DTLB_SET0_E6_PPN_CONST 0xC0000000
-#define XCHAL_DTLB_SET0_E7_PPN_CONST 0xE0000000
-/* Reset CA values for each entry of DTLB way set 0 (because SET0_CA_RESET is non-zero): */
-#define XCHAL_DTLB_SET0_E0_CA_RESET 0x02
-#define XCHAL_DTLB_SET0_E1_CA_RESET 0x02
-#define XCHAL_DTLB_SET0_E2_CA_RESET 0x02
-#define XCHAL_DTLB_SET0_E3_CA_RESET 0x02
-#define XCHAL_DTLB_SET0_E4_CA_RESET 0x02
-#define XCHAL_DTLB_SET0_E5_CA_RESET 0x02
-#define XCHAL_DTLB_SET0_E6_CA_RESET 0x02
-#define XCHAL_DTLB_SET0_E7_CA_RESET 0x02
-
-
-
-
-#endif /*XTENSA_CONFIG_CORE_MATMAP_H*/
-
-#else
-
-#error "xcc should not use this header"
-
-#endif /* __XCC__ */
diff --git a/src/platform/cannonlake/include/arch/xtensa/config/defs.h b/src/platform/cannonlake/include/arch/xtensa/config/defs.h
deleted file mode 100644
index c2ef1d9..0000000
--- a/src/platform/cannonlake/include/arch/xtensa/config/defs.h
+++ /dev/null
@@ -1,46 +0,0 @@
-/* Definitions for Xtensa instructions, types, and protos. */
-
-/* Customer ID=4313; Build=0x5483b; Copyright (c) 2003-2004 Tensilica Inc.
-
- Permission is hereby granted, free of charge, to any person obtaining
- a copy of this software and associated documentation files (the
- "Software"), to deal in the Software without restriction, including
- without limitation the rights to use, copy, modify, merge, publish,
- distribute, sublicense, and/or sell copies of the Software, and to
- permit persons to whom the Software is furnished to do so, subject to
- the following conditions:
-
- The above copyright notice and this permission notice shall be included
- in all copies or substantial portions of the Software.
-
- THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
- EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
- MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
- IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY
- CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
- TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
- SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. */
-
-/* NOTE: This file exists only for backward compatibility with T1050
- and earlier Xtensa releases. It includes only a subset of the
- available header files. */
-
-#if !defined __XCC__
-
-#ifndef _XTENSA_BASE_HEADER
-#define _XTENSA_BASE_HEADER
-
-#ifdef __XTENSA__
-
-#include <xtensa/tie/xt_core.h>
-#include <xtensa/tie/xt_misc.h>
-#include <xtensa/tie/xt_booleans.h>
-
-#endif /* __XTENSA__ */
-#endif /* !_XTENSA_BASE_HEADER */
-
-#else
-
-#error "xcc should not use this header"
-
-#endif /* __XCC__ */
diff --git a/src/platform/cannonlake/include/arch/xtensa/config/specreg.h b/src/platform/cannonlake/include/arch/xtensa/config/specreg.h
deleted file mode 100644
index c99cda6..0000000
--- a/src/platform/cannonlake/include/arch/xtensa/config/specreg.h
+++ /dev/null
@@ -1,114 +0,0 @@
-/*
- * Xtensa Special Register symbolic names
- */
-
-/* $Id: //depot/rel/Eaglenest/Xtensa/SWConfig/hal/specreg.h.tpp#1 $ */
-
-/* Customer ID=4313; Build=0x5483b; Copyright (c) 1998-2002 Tensilica Inc.
-
- Permission is hereby granted, free of charge, to any person obtaining
- a copy of this software and associated documentation files (the
- "Software"), to deal in the Software without restriction, including
- without limitation the rights to use, copy, modify, merge, publish,
- distribute, sublicense, and/or sell copies of the Software, and to
- permit persons to whom the Software is furnished to do so, subject to
- the following conditions:
-
- The above copyright notice and this permission notice shall be included
- in all copies or substantial portions of the Software.
-
- THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
- EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
- MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
- IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY
- CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
- TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
- SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. */
-
-#if !defined __XCC__
-
-#ifndef XTENSA_SPECREG_H
-#define XTENSA_SPECREG_H
-
-/* Include these special register bitfield definitions, for historical reasons: */
-#include <xtensa/corebits.h>
-
-
-/* Special registers: */
-#define LBEG 0
-#define LEND 1
-#define LCOUNT 2
-#define SAR 3
-#define BR 4
-#define SCOMPARE1 12
-#define WINDOWBASE 72
-#define WINDOWSTART 73
-#define IBREAKENABLE 96
-#define ATOMCTL 99
-#define DDR 104
-#define IBREAKA_0 128
-#define IBREAKA_1 129
-#define DBREAKA_0 144
-#define DBREAKA_1 145
-#define DBREAKC_0 160
-#define DBREAKC_1 161
-#define EPC_1 177
-#define EPC_2 178
-#define EPC_3 179
-#define EPC_4 180
-#define EPC_5 181
-#define EPC_6 182
-#define EPC_7 183
-#define DEPC 192
-#define EPS_2 194
-#define EPS_3 195
-#define EPS_4 196
-#define EPS_5 197
-#define EPS_6 198
-#define EPS_7 199
-#define EXCSAVE_1 209
-#define EXCSAVE_2 210
-#define EXCSAVE_3 211
-#define EXCSAVE_4 212
-#define EXCSAVE_5 213
-#define EXCSAVE_6 214
-#define EXCSAVE_7 215
-#define CPENABLE 224
-#define INTERRUPT 226
-#define INTENABLE 228
-#define PS 230
-#define VECBASE 231
-#define EXCCAUSE 232
-#define DEBUGCAUSE 233
-#define CCOUNT 234
-#define PRID 235
-#define ICOUNT 236
-#define ICOUNTLEVEL 237
-#define EXCVADDR 238
-#define CCOMPARE_0 240
-#define CCOMPARE_1 241
-#define CCOMPARE_2 242
-#define MISC_REG_0 244
-#define MISC_REG_1 245
-
-/* Special cases (bases of special register series): */
-#define IBREAKA 128
-#define DBREAKA 144
-#define DBREAKC 160
-#define EPC 176
-#define EPS 192
-#define EXCSAVE 208
-#define CCOMPARE 240
-
-/* Special names for read-only and write-only interrupt registers: */
-#define INTREAD 226
-#define INTSET 226
-#define INTCLEAR 227
-
-#endif /* XTENSA_SPECREG_H */
-
-#else
-
-#error "xcc should not use this header"
-
-#endif /* __XCC__ */
diff --git a/src/platform/cannonlake/include/arch/xtensa/config/system.h b/src/platform/cannonlake/include/arch/xtensa/config/system.h
deleted file mode 100644
index f1fd8a0..0000000
--- a/src/platform/cannonlake/include/arch/xtensa/config/system.h
+++ /dev/null
@@ -1,278 +0,0 @@
-/*
- * xtensa/config/system.h -- HAL definitions that are dependent on SYSTEM configuration
- *
- * NOTE: The location and contents of this file are highly subject to change.
- *
- * Source for configuration-independent binaries (which link in a
- * configuration-specific HAL library) must NEVER include this file.
- * The HAL itself has historically included this file in some instances,
- * but this is not appropriate either, because the HAL is meant to be
- * core-specific but system independent.
- */
-
-/* Customer ID=4313; Build=0x5483b; Copyright (c) 2000-2010 Tensilica Inc.
-
- Permission is hereby granted, free of charge, to any person obtaining
- a copy of this software and associated documentation files (the
- "Software"), to deal in the Software without restriction, including
- without limitation the rights to use, copy, modify, merge, publish,
- distribute, sublicense, and/or sell copies of the Software, and to
- permit persons to whom the Software is furnished to do so, subject to
- the following conditions:
-
- The above copyright notice and this permission notice shall be included
- in all copies or substantial portions of the Software.
-
- THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
- EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
- MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
- IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY
- CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
- TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
- SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. */
-
-#if !defined __XCC__
-
-#ifndef XTENSA_CONFIG_SYSTEM_H
-#define XTENSA_CONFIG_SYSTEM_H
-
-/*#include <xtensa/hal.h>*/
-
-
-
-/*----------------------------------------------------------------------
- CONFIGURED SOFTWARE OPTIONS
- ----------------------------------------------------------------------*/
-
-#define XSHAL_USE_ABSOLUTE_LITERALS 0 /* (sw-only option, whether software uses absolute literals) */
-#define XSHAL_HAVE_TEXT_SECTION_LITERALS 1 /* Set if there is some memory that allows both code and literals. */
-
-#define XSHAL_ABI XTHAL_ABI_CALL0 /* (sw-only option, selected ABI) */
-/* The above maps to one of the following constants: */
-#define XTHAL_ABI_WINDOWED 0
-#define XTHAL_ABI_CALL0 1
-/* Alternatives: */
-/*#define XSHAL_WINDOWED_ABI 1*/ /* set if windowed ABI selected */
-/*#define XSHAL_CALL0_ABI 0*/ /* set if call0 ABI selected */
-
-#define XSHAL_CLIB XTHAL_CLIB_NEWLIB /* (sw-only option, selected C library) */
-/* The above maps to one of the following constants: */
-#define XTHAL_CLIB_NEWLIB 0
-#define XTHAL_CLIB_UCLIBC 1
-#define XTHAL_CLIB_XCLIB 2
-/* Alternatives: */
-/*#define XSHAL_NEWLIB 1*/ /* set if newlib C library selected */
-/*#define XSHAL_UCLIBC 0*/ /* set if uCLibC C library selected */
-/*#define XSHAL_XCLIB 0*/ /* set if Xtensa C library selected */
-
-#define XSHAL_USE_FLOATING_POINT 1
-
-#define XSHAL_FLOATING_POINT_ABI 0
-
-/*----------------------------------------------------------------------
- DEVICE ADDRESSES
- ----------------------------------------------------------------------*/
-
-/*
- * Strange place to find these, but the configuration GUI
- * allows moving these around to account for various core
- * configurations. Specific boards (and their BSP software)
- * will have specific meanings for these components.
- */
-
-/* I/O Block areas: */
-#define XSHAL_IOBLOCK_CACHED_VADDR 0x70000000
-#define XSHAL_IOBLOCK_CACHED_PADDR 0x70000000
-#define XSHAL_IOBLOCK_CACHED_SIZE 0x0E000000
-
-#define XSHAL_IOBLOCK_BYPASS_VADDR 0x90000000
-#define XSHAL_IOBLOCK_BYPASS_PADDR 0x90000000
-#define XSHAL_IOBLOCK_BYPASS_SIZE 0x0E000000
-
-/* System ROM: */
-#define XSHAL_ROM_VADDR 0x50000000
-#define XSHAL_ROM_PADDR 0x50000000
-#define XSHAL_ROM_SIZE 0x01000000
-/* Largest available area (free of vectors): */
-#define XSHAL_ROM_AVAIL_VADDR 0x50000300
-#define XSHAL_ROM_AVAIL_VSIZE 0x00FFFD00
-
-/* System RAM: */
-#define XSHAL_RAM_VADDR 0x60000000
-#define XSHAL_RAM_PADDR 0x60000000
-#define XSHAL_RAM_VSIZE 0x04000000
-#define XSHAL_RAM_PSIZE 0x04000000
-#define XSHAL_RAM_SIZE XSHAL_RAM_PSIZE
-/* Largest available area (free of vectors): */
-#define XSHAL_RAM_AVAIL_VADDR 0x60000400
-#define XSHAL_RAM_AVAIL_VSIZE 0x03FFFC00
-
-/*
- * Shadow system RAM (same device as system RAM, at different address).
- * (Emulation boards need this for the SONIC Ethernet driver
- * when data caches are configured for writeback mode.)
- * NOTE: on full MMU configs, this points to the BYPASS virtual address
- * of system RAM, ie. is the same as XSHAL_RAM_* except that virtual
- * addresses are viewed through the BYPASS static map rather than
- * the CACHED static map.
- */
-#define XSHAL_RAM_BYPASS_VADDR 0xA0000000
-#define XSHAL_RAM_BYPASS_PADDR 0xA0000000
-#define XSHAL_RAM_BYPASS_PSIZE 0x04000000
-
-/* Alternate system RAM (different device than system RAM): */
-/*#define XSHAL_ALTRAM_[VP]ADDR ...not configured...*/
-/*#define XSHAL_ALTRAM_SIZE ...not configured...*/
-
-/* Some available location in which to place devices in a simulation (eg. XTMP): */
-#define XSHAL_SIMIO_CACHED_VADDR 0xC0000000
-#define XSHAL_SIMIO_BYPASS_VADDR 0xC0000000
-#define XSHAL_SIMIO_PADDR 0xC0000000
-#define XSHAL_SIMIO_SIZE 0x20000000
-
-
-/*----------------------------------------------------------------------
- * For use by reference testbench exit and diagnostic routines.
- */
-#define XSHAL_MAGIC_EXIT 0x0
-
-/*----------------------------------------------------------------------
- * DEVICE-ADDRESS DEPENDENT...
- *
- * Values written to CACHEATTR special register (or its equivalent)
- * to enable and disable caches in various modes.
- *----------------------------------------------------------------------*/
-
-/*----------------------------------------------------------------------
- BACKWARD COMPATIBILITY ...
- ----------------------------------------------------------------------*/
-
-/*
- * NOTE: the following two macros are DEPRECATED. Use the latter
- * board-specific macros instead, which are specially tuned for the
- * particular target environments' memory maps.
- */
-#define XSHAL_CACHEATTR_BYPASS XSHAL_XT2000_CACHEATTR_BYPASS /* disable caches in bypass mode */
-#define XSHAL_CACHEATTR_DEFAULT XSHAL_XT2000_CACHEATTR_DEFAULT /* default setting to enable caches (no writeback!) */
-
-/*----------------------------------------------------------------------
- GENERIC
- ----------------------------------------------------------------------*/
-
-/* For the following, a 512MB region is used if it contains a system (PIF) RAM,
- * system (PIF) ROM, local memory, or XLMI. */
-
-/* These set any unused 512MB region to cache-BYPASS attribute: */
-#define XSHAL_ALLVALID_CACHEATTR_WRITEBACK 0x22224442 /* enable caches in write-back mode */
-#define XSHAL_ALLVALID_CACHEATTR_WRITEALLOC 0x22221112 /* enable caches in write-allocate mode */
-#define XSHAL_ALLVALID_CACHEATTR_WRITETHRU 0x22221112 /* enable caches in write-through mode */
-#define XSHAL_ALLVALID_CACHEATTR_BYPASS 0x22222222 /* disable caches in bypass mode */
-#define XSHAL_ALLVALID_CACHEATTR_DEFAULT XSHAL_ALLVALID_CACHEATTR_WRITEBACK /* default setting to enable caches */
-
-/* These set any unused 512MB region to ILLEGAL attribute: */
-#define XSHAL_STRICT_CACHEATTR_WRITEBACK 0xFFFF444F /* enable caches in write-back mode */
-#define XSHAL_STRICT_CACHEATTR_WRITEALLOC 0xFFFF111F /* enable caches in write-allocate mode */
-#define XSHAL_STRICT_CACHEATTR_WRITETHRU 0xFFFF111F /* enable caches in write-through mode */
-#define XSHAL_STRICT_CACHEATTR_BYPASS 0xFFFF222F /* disable caches in bypass mode */
-#define XSHAL_STRICT_CACHEATTR_DEFAULT XSHAL_STRICT_CACHEATTR_WRITEBACK /* default setting to enable caches */
-
-/* These set the first 512MB, if unused, to ILLEGAL attribute to help catch
- * NULL-pointer dereference bugs; all other unused 512MB regions are set
- * to cache-BYPASS attribute: */
-#define XSHAL_TRAPNULL_CACHEATTR_WRITEBACK 0x2222444F /* enable caches in write-back mode */
-#define XSHAL_TRAPNULL_CACHEATTR_WRITEALLOC 0x2222111F /* enable caches in write-allocate mode */
-#define XSHAL_TRAPNULL_CACHEATTR_WRITETHRU 0x2222111F /* enable caches in write-through mode */
-#define XSHAL_TRAPNULL_CACHEATTR_BYPASS 0x2222222F /* disable caches in bypass mode */
-#define XSHAL_TRAPNULL_CACHEATTR_DEFAULT XSHAL_TRAPNULL_CACHEATTR_WRITEBACK /* default setting to enable caches */
-
-/*----------------------------------------------------------------------
- ISS (Instruction Set Simulator) SPECIFIC ...
- ----------------------------------------------------------------------*/
-
-/* For now, ISS defaults to the TRAPNULL settings: */
-#define XSHAL_ISS_CACHEATTR_WRITEBACK XSHAL_TRAPNULL_CACHEATTR_WRITEBACK
-#define XSHAL_ISS_CACHEATTR_WRITEALLOC XSHAL_TRAPNULL_CACHEATTR_WRITEALLOC
-#define XSHAL_ISS_CACHEATTR_WRITETHRU XSHAL_TRAPNULL_CACHEATTR_WRITETHRU
-#define XSHAL_ISS_CACHEATTR_BYPASS XSHAL_TRAPNULL_CACHEATTR_BYPASS
-#define XSHAL_ISS_CACHEATTR_DEFAULT XSHAL_TRAPNULL_CACHEATTR_WRITEBACK
-
-#define XSHAL_ISS_PIPE_REGIONS 0
-#define XSHAL_ISS_SDRAM_REGIONS 0
-
-
-/*----------------------------------------------------------------------
- XT2000 BOARD SPECIFIC ...
- ----------------------------------------------------------------------*/
-
-/* For the following, a 512MB region is used if it contains any system RAM,
- * system ROM, local memory, XLMI, or other XT2000 board device or memory.
- * Regions containing devices are forced to cache-BYPASS mode regardless
- * of whether the macro is _WRITEBACK vs. _BYPASS etc. */
-
-/* These set any 512MB region unused on the XT2000 to ILLEGAL attribute: */
-#define XSHAL_XT2000_CACHEATTR_WRITEBACK 0xFF22444F /* enable caches in write-back mode */
-#define XSHAL_XT2000_CACHEATTR_WRITEALLOC 0xFF22111F /* enable caches in write-allocate mode */
-#define XSHAL_XT2000_CACHEATTR_WRITETHRU 0xFF22111F /* enable caches in write-through mode */
-#define XSHAL_XT2000_CACHEATTR_BYPASS 0xFF22222F /* disable caches in bypass mode */
-#define XSHAL_XT2000_CACHEATTR_DEFAULT XSHAL_XT2000_CACHEATTR_WRITEBACK /* default setting to enable caches */
-
-#define XSHAL_XT2000_PIPE_REGIONS 0x00000000 /* BusInt pipeline regions */
-#define XSHAL_XT2000_SDRAM_REGIONS 0x00000440 /* BusInt SDRAM regions */
-
-
-/*----------------------------------------------------------------------
- VECTOR INFO AND SIZES
- ----------------------------------------------------------------------*/
-
-#define XSHAL_VECTORS_PACKED 0
-#define XSHAL_STATIC_VECTOR_SELECT 0
-#define XSHAL_RESET_VECTOR_VADDR 0x50000000
-#define XSHAL_RESET_VECTOR_PADDR 0x50000000
-
-/*
- * Sizes allocated to vectors by the system (memory map) configuration.
- * These sizes are constrained by core configuration (eg. one vector's
- * code cannot overflow into another vector) but are dependent on the
- * system or board (or LSP) memory map configuration.
- *
- * Whether or not each vector happens to be in a system ROM is also
- * a system configuration matter, sometimes useful, included here also:
- */
-#define XSHAL_RESET_VECTOR_SIZE 0x00000300
-#define XSHAL_RESET_VECTOR_ISROM 1
-#define XSHAL_USER_VECTOR_SIZE 0x00000038
-#define XSHAL_USER_VECTOR_ISROM 0
-#define XSHAL_PROGRAMEXC_VECTOR_SIZE XSHAL_USER_VECTOR_SIZE /* for backward compatibility */
-#define XSHAL_USEREXC_VECTOR_SIZE XSHAL_USER_VECTOR_SIZE /* for backward compatibility */
-#define XSHAL_KERNEL_VECTOR_SIZE 0x00000038
-#define XSHAL_KERNEL_VECTOR_ISROM 0
-#define XSHAL_STACKEDEXC_VECTOR_SIZE XSHAL_KERNEL_VECTOR_SIZE /* for backward compatibility */
-#define XSHAL_KERNELEXC_VECTOR_SIZE XSHAL_KERNEL_VECTOR_SIZE /* for backward compatibility */
-#define XSHAL_DOUBLEEXC_VECTOR_SIZE 0x00000040
-#define XSHAL_DOUBLEEXC_VECTOR_ISROM 0
-#define XSHAL_WINDOW_VECTORS_SIZE 0x00000178
-#define XSHAL_WINDOW_VECTORS_ISROM 0
-#define XSHAL_INTLEVEL2_VECTOR_SIZE 0x00000038
-#define XSHAL_INTLEVEL2_VECTOR_ISROM 0
-#define XSHAL_INTLEVEL3_VECTOR_SIZE 0x00000038
-#define XSHAL_INTLEVEL3_VECTOR_ISROM 0
-#define XSHAL_INTLEVEL4_VECTOR_SIZE 0x00000038
-#define XSHAL_INTLEVEL4_VECTOR_ISROM 0
-#define XSHAL_INTLEVEL5_VECTOR_SIZE 0x00000038
-#define XSHAL_INTLEVEL5_VECTOR_ISROM 0
-#define XSHAL_INTLEVEL6_VECTOR_SIZE 0x00000038
-#define XSHAL_INTLEVEL6_VECTOR_ISROM 0
-#define XSHAL_DEBUG_VECTOR_SIZE XSHAL_INTLEVEL6_VECTOR_SIZE
-#define XSHAL_DEBUG_VECTOR_ISROM XSHAL_INTLEVEL6_VECTOR_ISROM
-#define XSHAL_NMI_VECTOR_SIZE 0x00000038
-#define XSHAL_NMI_VECTOR_ISROM 0
-#define XSHAL_INTLEVEL7_VECTOR_SIZE XSHAL_NMI_VECTOR_SIZE
-
-
-#endif /*XTENSA_CONFIG_SYSTEM_H*/
-
-#else
-
-#error "xcc should not use this header"
-
-#endif /* __XCC__ */
diff --git a/src/platform/cannonlake/include/arch/xtensa/config/tie-asm.h b/src/platform/cannonlake/include/arch/xtensa/config/tie-asm.h
deleted file mode 100644
index 706545a..0000000
--- a/src/platform/cannonlake/include/arch/xtensa/config/tie-asm.h
+++ /dev/null
@@ -1,247 +0,0 @@
-/*
- * tie-asm.h -- compile-time HAL assembler definitions dependent on CORE & TIE
- *
- * NOTE: This header file is not meant to be included directly.
- */
-
-/* This header file contains assembly-language definitions (assembly
- macros, etc.) for this specific Xtensa processor's TIE extensions
- and options. It is customized to this Xtensa processor configuration.
-
- Copyright (c) 1999-2015 Cadence Design Systems Inc.
-
- Permission is hereby granted, free of charge, to any person obtaining
- a copy of this software and associated documentation files (the
- "Software"), to deal in the Software without restriction, including
- without limitation the rights to use, copy, modify, merge, publish,
- distribute, sublicense, and/or sell copies of the Software, and to
- permit persons to whom the Software is furnished to do so, subject to
- the following conditions:
-
- The above copyright notice and this permission notice shall be included
- in all copies or substantial portions of the Software.
-
- THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
- EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
- MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
- IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY
- CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
- TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
- SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. */
-
-#if !defined __XCC__
-
-#ifndef _XTENSA_CORE_TIE_ASM_H
-#define _XTENSA_CORE_TIE_ASM_H
-
-/* Selection parameter values for save-area save/restore macros: */
-/* Option vs. TIE: */
-#define XTHAL_SAS_TIE 0x0001 /* custom extension or coprocessor */
-#define XTHAL_SAS_OPT 0x0002 /* optional (and not a coprocessor) */
-#define XTHAL_SAS_ANYOT 0x0003 /* both of the above */
-/* Whether used automatically by compiler: */
-#define XTHAL_SAS_NOCC 0x0004 /* not used by compiler w/o special opts/code */
-#define XTHAL_SAS_CC 0x0008 /* used by compiler without special opts/code */
-#define XTHAL_SAS_ANYCC 0x000C /* both of the above */
-/* ABI handling across function calls: */
-#define XTHAL_SAS_CALR 0x0010 /* caller-saved */
-#define XTHAL_SAS_CALE 0x0020 /* callee-saved */
-#define XTHAL_SAS_GLOB 0x0040 /* global across function calls (in thread) */
-#define XTHAL_SAS_ANYABI 0x0070 /* all of the above three */
-/* Misc */
-#define XTHAL_SAS_ALL 0xFFFF /* include all default NCP contents */
-#define XTHAL_SAS3(optie,ccuse,abi) ( ((optie) & XTHAL_SAS_ANYOT) \
- | ((ccuse) & XTHAL_SAS_ANYCC) \
- | ((abi) & XTHAL_SAS_ANYABI) )
-
-
- /*
- * Macro to store all non-coprocessor (extra) custom TIE and optional state
- * (not including zero-overhead loop registers).
- * Required parameters:
- * ptr Save area pointer address register (clobbered)
- * (register must contain a 4 byte aligned address).
- * at1..at4 Four temporary address registers (first XCHAL_NCP_NUM_ATMPS
- * registers are clobbered, the remaining are unused).
- * Optional parameters:
- * continue If macro invoked as part of a larger store sequence, set to 1
- * if this is not the first in the sequence. Defaults to 0.
- * ofs Offset from start of larger sequence (from value of first ptr
- * in sequence) at which to store. Defaults to next available space
- * (or 0 if <continue> is 0).
- * select Select what category(ies) of registers to store, as a bitmask
- * (see XTHAL_SAS_xxx constants). Defaults to all registers.
- * alloc Select what category(ies) of registers to allocate; if any
- * category is selected here that is not in <select>, space for
- * the corresponding registers is skipped without doing any store.
- */
- .macro xchal_ncp_store ptr at1 at2 at3 at4 continue=0 ofs=-1 select=XTHAL_SAS_ALL alloc=0
- xchal_sa_start \continue, \ofs
- // Optional caller-saved registers not used by default by the compiler:
- .ifeq (XTHAL_SAS_OPT | XTHAL_SAS_NOCC | XTHAL_SAS_CALR) & ~(\select)
- xchal_sa_align \ptr, 0, 1016, 4, 4
- rsr.BR \at1 // boolean option
- s32i \at1, \ptr, .Lxchal_ofs_+0
- rsr.SCOMPARE1 \at1 // conditional store option
- s32i \at1, \ptr, .Lxchal_ofs_+4
- .set .Lxchal_ofs_, .Lxchal_ofs_ + 8
- .elseif ((XTHAL_SAS_OPT | XTHAL_SAS_NOCC | XTHAL_SAS_CALR) & ~(\alloc)) == 0
- xchal_sa_align \ptr, 0, 1016, 4, 4
- .set .Lxchal_ofs_, .Lxchal_ofs_ + 8
- .endif
- .endm // xchal_ncp_store
-
- /*
- * Macro to load all non-coprocessor (extra) custom TIE and optional state
- * (not including zero-overhead loop registers).
- * Required parameters:
- * ptr Save area pointer address register (clobbered)
- * (register must contain a 4 byte aligned address).
- * at1..at4 Four temporary address registers (first XCHAL_NCP_NUM_ATMPS
- * registers are clobbered, the remaining are unused).
- * Optional parameters:
- * continue If macro invoked as part of a larger load sequence, set to 1
- * if this is not the first in the sequence. Defaults to 0.
- * ofs Offset from start of larger sequence (from value of first ptr
- * in sequence) at which to load. Defaults to next available space
- * (or 0 if <continue> is 0).
- * select Select what category(ies) of registers to load, as a bitmask
- * (see XTHAL_SAS_xxx constants). Defaults to all registers.
- * alloc Select what category(ies) of registers to allocate; if any
- * category is selected here that is not in <select>, space for
- * the corresponding registers is skipped without doing any load.
- */
- .macro xchal_ncp_load ptr at1 at2 at3 at4 continue=0 ofs=-1 select=XTHAL_SAS_ALL alloc=0
- xchal_sa_start \continue, \ofs
- // Optional caller-saved registers not used by default by the compiler:
- .ifeq (XTHAL_SAS_OPT | XTHAL_SAS_NOCC | XTHAL_SAS_CALR) & ~(\select)
- xchal_sa_align \ptr, 0, 1016, 4, 4
- l32i \at1, \ptr, .Lxchal_ofs_+0
- wsr.BR \at1 // boolean option
- l32i \at1, \ptr, .Lxchal_ofs_+4
- wsr.SCOMPARE1 \at1 // conditional store option
- .set .Lxchal_ofs_, .Lxchal_ofs_ + 8
- .elseif ((XTHAL_SAS_OPT | XTHAL_SAS_NOCC | XTHAL_SAS_CALR) & ~(\alloc)) == 0
- xchal_sa_align \ptr, 0, 1016, 4, 4
- .set .Lxchal_ofs_, .Lxchal_ofs_ + 8
- .endif
- .endm // xchal_ncp_load
-
-
-#define XCHAL_NCP_NUM_ATMPS 1
-
- /*
- * Macro to store the state of TIE coprocessor AudioEngineLX.
- * Required parameters:
- * ptr Save area pointer address register (clobbered)
- * (register must contain a 8 byte aligned address).
- * at1..at4 Four temporary address registers (first XCHAL_CP1_NUM_ATMPS
- * registers are clobbered, the remaining are unused).
- * Optional parameters are the same as for xchal_ncp_store.
- */
-#define xchal_cp_AudioEngineLX_store xchal_cp1_store
- .macro xchal_cp1_store ptr at1 at2 at3 at4 continue=0 ofs=-1 select=XTHAL_SAS_ALL alloc=0
- xchal_sa_start \continue, \ofs
- // Custom caller-saved registers not used by default by the compiler:
- .ifeq (XTHAL_SAS_TIE | XTHAL_SAS_NOCC | XTHAL_SAS_CALR) & ~(\select)
- xchal_sa_align \ptr, 0, 0, 8, 8
- rur.AE_OVF_SAR \at1 // ureg 240
- s32i \at1, \ptr, .Lxchal_ofs_+0
- rur.AE_BITHEAD \at1 // ureg 241
- s32i \at1, \ptr, .Lxchal_ofs_+4
- rur.AE_TS_FTS_BU_BP \at1 // ureg 242
- s32i \at1, \ptr, .Lxchal_ofs_+8
- rur.AE_SD_NO \at1 // ureg 243
- s32i \at1, \ptr, .Lxchal_ofs_+12
- ae_sp24x2s.i aep0, \ptr, .Lxchal_ofs_+16
- ae_sp24x2s.i aep1, \ptr, .Lxchal_ofs_+24
- ae_sp24x2s.i aep2, \ptr, .Lxchal_ofs_+32
- ae_sp24x2s.i aep3, \ptr, .Lxchal_ofs_+40
- ae_sp24x2s.i aep4, \ptr, .Lxchal_ofs_+48
- ae_sp24x2s.i aep5, \ptr, .Lxchal_ofs_+56
- addi \ptr, \ptr, 64
- ae_sp24x2s.i aep6, \ptr, .Lxchal_ofs_+0
- ae_sp24x2s.i aep7, \ptr, .Lxchal_ofs_+8
- ae_sq56s.i aeq0, \ptr, .Lxchal_ofs_+16
- ae_sq56s.i aeq1, \ptr, .Lxchal_ofs_+24
- ae_sq56s.i aeq2, \ptr, .Lxchal_ofs_+32
- ae_sq56s.i aeq3, \ptr, .Lxchal_ofs_+40
- .set .Lxchal_pofs_, .Lxchal_pofs_ + 64
- .set .Lxchal_ofs_, .Lxchal_ofs_ + 48
- .elseif ((XTHAL_SAS_TIE | XTHAL_SAS_NOCC | XTHAL_SAS_CALR) & ~(\alloc)) == 0
- xchal_sa_align \ptr, 0, 0, 8, 8
- .set .Lxchal_ofs_, .Lxchal_ofs_ + 112
- .endif
- .endm // xchal_cp1_store
-
- /*
- * Macro to load the state of TIE coprocessor AudioEngineLX.
- * Required parameters:
- * ptr Save area pointer address register (clobbered)
- * (register must contain a 8 byte aligned address).
- * at1..at4 Four temporary address registers (first XCHAL_CP1_NUM_ATMPS
- * registers are clobbered, the remaining are unused).
- * Optional parameters are the same as for xchal_ncp_load.
- */
-#define xchal_cp_AudioEngineLX_load xchal_cp1_load
- .macro xchal_cp1_load ptr at1 at2 at3 at4 continue=0 ofs=-1 select=XTHAL_SAS_ALL alloc=0
- xchal_sa_start \continue, \ofs
- // Custom caller-saved registers not used by default by the compiler:
- .ifeq (XTHAL_SAS_TIE | XTHAL_SAS_NOCC | XTHAL_SAS_CALR) & ~(\select)
- xchal_sa_align \ptr, 0, 0, 8, 8
- l32i \at1, \ptr, .Lxchal_ofs_+0
- wur.AE_OVF_SAR \at1 // ureg 240
- l32i \at1, \ptr, .Lxchal_ofs_+4
- wur.AE_BITHEAD \at1 // ureg 241
- l32i \at1, \ptr, .Lxchal_ofs_+8
- wur.AE_TS_FTS_BU_BP \at1 // ureg 242
- l32i \at1, \ptr, .Lxchal_ofs_+12
- wur.AE_SD_NO \at1 // ureg 243
- ae_lp24x2.i aep0, \ptr, .Lxchal_ofs_+16
- ae_lp24x2.i aep1, \ptr, .Lxchal_ofs_+24
- ae_lp24x2.i aep2, \ptr, .Lxchal_ofs_+32
- ae_lp24x2.i aep3, \ptr, .Lxchal_ofs_+40
- ae_lp24x2.i aep4, \ptr, .Lxchal_ofs_+48
- ae_lp24x2.i aep5, \ptr, .Lxchal_ofs_+56
- addi \ptr, \ptr, 64
- ae_lp24x2.i aep6, \ptr, .Lxchal_ofs_+0
- ae_lp24x2.i aep7, \ptr, .Lxchal_ofs_+8
- addi \ptr, \ptr, 16
- ae_lq56.i aeq0, \ptr, .Lxchal_ofs_+0
- ae_lq56.i aeq1, \ptr, .Lxchal_ofs_+8
- ae_lq56.i aeq2, \ptr, .Lxchal_ofs_+16
- ae_lq56.i aeq3, \ptr, .Lxchal_ofs_+24
- .set .Lxchal_pofs_, .Lxchal_pofs_ + 80
- .set .Lxchal_ofs_, .Lxchal_ofs_ + 32
- .elseif ((XTHAL_SAS_TIE | XTHAL_SAS_NOCC | XTHAL_SAS_CALR) & ~(\alloc)) == 0
- xchal_sa_align \ptr, 0, 0, 8, 8
- .set .Lxchal_ofs_, .Lxchal_ofs_ + 112
- .endif
- .endm // xchal_cp1_load
-
-#define XCHAL_CP1_NUM_ATMPS 1
-#define XCHAL_SA_NUM_ATMPS 1
-
- /* Empty macros for unconfigured coprocessors: */
- .macro xchal_cp0_store p a b c d continue=0 ofs=-1 select=-1 ; .endm
- .macro xchal_cp0_load p a b c d continue=0 ofs=-1 select=-1 ; .endm
- .macro xchal_cp2_store p a b c d continue=0 ofs=-1 select=-1 ; .endm
- .macro xchal_cp2_load p a b c d continue=0 ofs=-1 select=-1 ; .endm
- .macro xchal_cp3_store p a b c d continue=0 ofs=-1 select=-1 ; .endm
- .macro xchal_cp3_load p a b c d continue=0 ofs=-1 select=-1 ; .endm
- .macro xchal_cp4_store p a b c d continue=0 ofs=-1 select=-1 ; .endm
- .macro xchal_cp4_load p a b c d continue=0 ofs=-1 select=-1 ; .endm
- .macro xchal_cp5_store p a b c d continue=0 ofs=-1 select=-1 ; .endm
- .macro xchal_cp5_load p a b c d continue=0 ofs=-1 select=-1 ; .endm
- .macro xchal_cp6_store p a b c d continue=0 ofs=-1 select=-1 ; .endm
- .macro xchal_cp6_load p a b c d continue=0 ofs=-1 select=-1 ; .endm
- .macro xchal_cp7_store p a b c d continue=0 ofs=-1 select=-1 ; .endm
- .macro xchal_cp7_load p a b c d continue=0 ofs=-1 select=-1 ; .endm
-
-#endif /*_XTENSA_CORE_TIE_ASM_H*/
-
-#else
-
-#error "xcc should not use this header"
-
-#endif /* __XCC__ */
diff --git a/src/platform/cannonlake/include/arch/xtensa/config/tie.h b/src/platform/cannonlake/include/arch/xtensa/config/tie.h
deleted file mode 100644
index b5fd4c9..0000000
--- a/src/platform/cannonlake/include/arch/xtensa/config/tie.h
+++ /dev/null
@@ -1,177 +0,0 @@
-/*
- * tie.h -- compile-time HAL definitions dependent on CORE & TIE configuration
- *
- * NOTE: This header file is not meant to be included directly.
- */
-
-/* This header file describes this specific Xtensa processor's TIE extensions
- that extend basic Xtensa core functionality. It is customized to this
- Xtensa processor configuration.
-
- Copyright (c) 1999-2015 Cadence Design Systems Inc.
-
- Permission is hereby granted, free of charge, to any person obtaining
- a copy of this software and associated documentation files (the
- "Software"), to deal in the Software without restriction, including
- without limitation the rights to use, copy, modify, merge, publish,
- distribute, sublicense, and/or sell copies of the Software, and to
- permit persons to whom the Software is furnished to do so, subject to
- the following conditions:
-
- The above copyright notice and this permission notice shall be included
- in all copies or substantial portions of the Software.
-
- THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
- EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
- MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
- IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY
- CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
- TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
- SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. */
-
-#if !defined __XCC__
-
-#ifndef _XTENSA_CORE_TIE_H
-#define _XTENSA_CORE_TIE_H
-
-#define XCHAL_CP_NUM 1 /* number of coprocessors */
-#define XCHAL_CP_MAX 2 /* max CP ID + 1 (0 if none) */
-#define XCHAL_CP_MASK 0x02 /* bitmask of all CPs by ID */
-#define XCHAL_CP_PORT_MASK 0x00 /* bitmask of only port CPs */
-
-/* Basic parameters of each coprocessor: */
-#define XCHAL_CP1_NAME "AudioEngineLX"
-#define XCHAL_CP1_IDENT AudioEngineLX
-#define XCHAL_CP1_SA_SIZE 112 /* size of state save area */
-#define XCHAL_CP1_SA_ALIGN 8 /* min alignment of save area */
-#define XCHAL_CP_ID_AUDIOENGINELX 1 /* coprocessor ID (0..7) */
-
-/* Filler info for unassigned coprocessors, to simplify arrays etc: */
-#define XCHAL_CP0_SA_SIZE 0
-#define XCHAL_CP0_SA_ALIGN 1
-#define XCHAL_CP2_SA_SIZE 0
-#define XCHAL_CP2_SA_ALIGN 1
-#define XCHAL_CP3_SA_SIZE 0
-#define XCHAL_CP3_SA_ALIGN 1
-#define XCHAL_CP4_SA_SIZE 0
-#define XCHAL_CP4_SA_ALIGN 1
-#define XCHAL_CP5_SA_SIZE 0
-#define XCHAL_CP5_SA_ALIGN 1
-#define XCHAL_CP6_SA_SIZE 0
-#define XCHAL_CP6_SA_ALIGN 1
-#define XCHAL_CP7_SA_SIZE 0
-#define XCHAL_CP7_SA_ALIGN 1
-
-/* Save area for non-coprocessor optional and custom (TIE) state: */
-#define XCHAL_NCP_SA_SIZE 8
-#define XCHAL_NCP_SA_ALIGN 4
-
-/* Total save area for optional and custom state (NCP + CPn): */
-#define XCHAL_TOTAL_SA_SIZE 128 /* with 16-byte align padding */
-#define XCHAL_TOTAL_SA_ALIGN 8 /* actual minimum alignment */
-
-/*
- * Detailed contents of save areas.
- * NOTE: caller must define the XCHAL_SA_REG macro (not defined here)
- * before expanding the XCHAL_xxx_SA_LIST() macros.
- *
- * XCHAL_SA_REG(s,ccused,abikind,kind,opt,name,galign,align,asize,
- * dbnum,base,regnum,bitsz,gapsz,reset,x...)
- *
- * s = passed from XCHAL_*_LIST(s), eg. to select how to expand
- * ccused = set if used by compiler without special options or code
- * abikind = 0 (caller-saved), 1 (callee-saved), or 2 (thread-global)
- * kind = 0 (special reg), 1 (TIE user reg), or 2 (TIE regfile reg)
- * opt = 0 (custom TIE extension or coprocessor), or 1 (optional reg)
- * name = lowercase reg name (no quotes)
- * galign = group byte alignment (power of 2) (galign >= align)
- * align = register byte alignment (power of 2)
- * asize = allocated size in bytes (asize*8 == bitsz + gapsz + padsz)
- * (not including any pad bytes required to galign this or next reg)
- * dbnum = unique target number f/debug (see <xtensa-libdb-macros.h>)
- * base = reg shortname w/o index (or sr=special, ur=TIE user reg)
- * regnum = reg index in regfile, or special/TIE-user reg number
- * bitsz = number of significant bits (regfile width, or ur/sr mask bits)
- * gapsz = intervening bits, if bitsz bits not stored contiguously
- * (padsz = pad bits at end [TIE regfile] or at msbits [ur,sr] of asize)
- * reset = register reset value (or 0 if undefined at reset)
- * x = reserved for future use (0 until then)
- *
- * To filter out certain registers, e.g. to expand only the non-global
- * registers used by the compiler, you can do something like this:
- *
- * #define XCHAL_SA_REG(s,ccused,p...) SELCC##ccused(p)
- * #define SELCC0(p...)
- * #define SELCC1(abikind,p...) SELAK##abikind(p)
- * #define SELAK0(p...) REG(p)
- * #define SELAK1(p...) REG(p)
- * #define SELAK2(p...)
- * #define REG(kind,tie,name,galn,aln,asz,csz,dbnum,base,rnum,bsz,rst,x...) \
- * ...what you want to expand...
- */
-
-#define XCHAL_NCP_SA_NUM 2
-#define XCHAL_NCP_SA_LIST(s) \
- XCHAL_SA_REG(s,0,0,0,1, br, 4, 4, 4,0x0204, sr,4 , 16,0,0,0) \
- XCHAL_SA_REG(s,0,0,0,1, scompare1, 4, 4, 4,0x020C, sr,12 , 32,0,0,0)
-
-#define XCHAL_CP0_SA_NUM 0
-#define XCHAL_CP0_SA_LIST(s) /* empty */
-
-#define XCHAL_CP1_SA_NUM 16
-#define XCHAL_CP1_SA_LIST(s) \
- XCHAL_SA_REG(s,0,0,1,0, ae_ovf_sar, 8, 4, 4,0x03F0, ur,240, 7,0,0,0) \
- XCHAL_SA_REG(s,0,0,1,0, ae_bithead, 4, 4, 4,0x03F1, ur,241, 32,0,0,0) \
- XCHAL_SA_REG(s,0,0,1,0,ae_ts_fts_bu_bp, 4, 4, 4,0x03F2, ur,242, 16,0,0,0) \
- XCHAL_SA_REG(s,0,0,1,0, ae_sd_no, 4, 4, 4,0x03F3, ur,243, 28,0,0,0) \
- XCHAL_SA_REG(s,0,0,2,0, aep0, 8, 8, 8,0x0060, aep,0 , 48,0,0,0) \
- XCHAL_SA_REG(s,0,0,2,0, aep1, 8, 8, 8,0x0061, aep,1 , 48,0,0,0) \
- XCHAL_SA_REG(s,0,0,2,0, aep2, 8, 8, 8,0x0062, aep,2 , 48,0,0,0) \
- XCHAL_SA_REG(s,0,0,2,0, aep3, 8, 8, 8,0x0063, aep,3 , 48,0,0,0) \
- XCHAL_SA_REG(s,0,0,2,0, aep4, 8, 8, 8,0x0064, aep,4 , 48,0,0,0) \
- XCHAL_SA_REG(s,0,0,2,0, aep5, 8, 8, 8,0x0065, aep,5 , 48,0,0,0) \
- XCHAL_SA_REG(s,0,0,2,0, aep6, 8, 8, 8,0x0066, aep,6 , 48,0,0,0) \
- XCHAL_SA_REG(s,0,0,2,0, aep7, 8, 8, 8,0x0067, aep,7 , 48,0,0,0) \
- XCHAL_SA_REG(s,0,0,2,0, aeq0, 8, 8, 8,0x0068, aeq,0 , 56,0,0,0) \
- XCHAL_SA_REG(s,0,0,2,0, aeq1, 8, 8, 8,0x0069, aeq,1 , 56,0,0,0) \
- XCHAL_SA_REG(s,0,0,2,0, aeq2, 8, 8, 8,0x006A, aeq,2 , 56,0,0,0) \
- XCHAL_SA_REG(s,0,0,2,0, aeq3, 8, 8, 8,0x006B, aeq,3 , 56,0,0,0)
-
-#define XCHAL_CP2_SA_NUM 0
-#define XCHAL_CP2_SA_LIST(s) /* empty */
-
-#define XCHAL_CP3_SA_NUM 0
-#define XCHAL_CP3_SA_LIST(s) /* empty */
-
-#define XCHAL_CP4_SA_NUM 0
-#define XCHAL_CP4_SA_LIST(s) /* empty */
-
-#define XCHAL_CP5_SA_NUM 0
-#define XCHAL_CP5_SA_LIST(s) /* empty */
-
-#define XCHAL_CP6_SA_NUM 0
-#define XCHAL_CP6_SA_LIST(s) /* empty */
-
-#define XCHAL_CP7_SA_NUM 0
-#define XCHAL_CP7_SA_LIST(s) /* empty */
-
-/* Byte length of instruction from its first nibble (op0 field), per FLIX. */
-#define XCHAL_OP0_FORMAT_LENGTHS 3,3,3,3,3,3,3,3,2,2,2,2,2,2,3,8
-/* Byte length of instruction from its first byte, per FLIX. */
-#define XCHAL_BYTE0_FORMAT_LENGTHS \
- 3,3,3,3,3,3,3,3,2,2,2,2,2,2,3,8, 3,3,3,3,3,3,3,3,2,2,2,2,2,2,3,8,\
- 3,3,3,3,3,3,3,3,2,2,2,2,2,2,3,8, 3,3,3,3,3,3,3,3,2,2,2,2,2,2,3,8,\
- 3,3,3,3,3,3,3,3,2,2,2,2,2,2,3,8, 3,3,3,3,3,3,3,3,2,2,2,2,2,2,3,8,\
- 3,3,3,3,3,3,3,3,2,2,2,2,2,2,3,8, 3,3,3,3,3,3,3,3,2,2,2,2,2,2,3,8,\
- 3,3,3,3,3,3,3,3,2,2,2,2,2,2,3,8, 3,3,3,3,3,3,3,3,2,2,2,2,2,2,3,8,\
- 3,3,3,3,3,3,3,3,2,2,2,2,2,2,3,8, 3,3,3,3,3,3,3,3,2,2,2,2,2,2,3,8,\
- 3,3,3,3,3,3,3,3,2,2,2,2,2,2,3,8, 3,3,3,3,3,3,3,3,2,2,2,2,2,2,3,8,\
- 3,3,3,3,3,3,3,3,2,2,2,2,2,2,3,8, 3,3,3,3,3,3,3,3,2,2,2,2,2,2,3,8
-
-#endif /*_XTENSA_CORE_TIE_H*/
-
-#else
-
-#error "xcc should not use this header"
-
-#endif /* __XCC__ */
diff --git a/src/platform/cannonlake/include/platform/Makefile.am b/src/platform/cannonlake/include/platform/Makefile.am
deleted file mode 100644
index a12dd72..0000000
--- a/src/platform/cannonlake/include/platform/Makefile.am
+++ /dev/null
@@ -1,12 +0,0 @@
-noinst_HEADERS = \
- clk.h \
- dma.h \
- idc.h \
- interrupt.h \
- mailbox.h \
- memory.h \
- platcfg.h \
- platform.h \
- pm_runtime.h \
- shim.h \
- timer.h
diff --git a/src/platform/cannonlake/include/platform/clk.h b/src/platform/cannonlake/include/platform/clk.h
deleted file mode 100644
index d6ccd6c..0000000
--- a/src/platform/cannonlake/include/platform/clk.h
+++ /dev/null
@@ -1,44 +0,0 @@
-/*
- * Copyright (c) 2017, Intel Corporation
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- * * Redistributions of source code must retain the above copyright
- * notice, this list of conditions and the following disclaimer.
- * * Redistributions in binary form must reproduce the above copyright
- * notice, this list of conditions and the following disclaimer in the
- * documentation and/or other materials provided with the distribution.
- * * Neither the name of the Intel Corporation nor the
- * names of its contributors may be used to endorse or promote products
- * derived from this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
- * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
- * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
- * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
- * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
- * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
- * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
- * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
- * POSSIBILITY OF SUCH DAMAGE.
- *
- * Author: Liam Girdwood <liam.r.girdwood@linux.intel.com>
- * Keyon Jie <yang.jie@linux.intel.com>
- * Rander Wang <rander.wang@intel.com>
- */
-
-#ifndef __PLATFORM_CLOCK__
-#define __PLATFORM_CLOCK__
-
-#define CLK_CPU 0
-#define CLK_SSP 1
-
-#define CLK_DEFAULT_CPU_HZ 120000000
-#define CLK_MAX_CPU_HZ 400000000
-
-void init_platform_clocks(void);
-
-#endif
diff --git a/src/platform/cannonlake/include/platform/dma.h b/src/platform/cannonlake/include/platform/dma.h
deleted file mode 100644
index b6366a0..0000000
--- a/src/platform/cannonlake/include/platform/dma.h
+++ /dev/null
@@ -1,78 +0,0 @@
-/*
- * Copyright (c) 2017, Intel Corporation
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- * * Redistributions of source code must retain the above copyright
- * notice, this list of conditions and the following disclaimer.
- * * Redistributions in binary form must reproduce the above copyright
- * notice, this list of conditions and the following disclaimer in the
- * documentation and/or other materials provided with the distribution.
- * * Neither the name of the Intel Corporation nor the
- * names of its contributors may be used to endorse or promote products
- * derived from this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
- * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
- * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
- * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
- * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
- * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
- * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
- * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
- * POSSIBILITY OF SUCH DAMAGE.
- *
- * Author: Liam Girdwood <liam.r.girdwood@linux.intel.com>
- * Keyon Jie <yang.jie@linux.intel.com>
- * Rander Wang <rander.wang@intel.com>
- */
-
-#ifndef __PLATFORM_DMA_H__
-#define __PLATFORM_DMA_H__
-
-#include <sof/dma.h>
-
-#define PLATFORM_NUM_DMACS 6
-
-/* available DMACs */
-#define DMA_GP_LP_DMAC0 0
-#define DMA_GP_LP_DMAC1 1
-#define DMA_GP_HP_DMAC0 2
-#define DMA_GP_HP_DMAC1 3
-#define DMA_HOST_IN_DMAC 4
-#define DMA_HOST_OUT_DMAC 5
-#define DMA_LINK_IN_DMAC 6
-#define DMA_LINK_OUT_DMAC 7
-
-/* mappings - TODO improve API to get type */
-#define DMA_ID_DMAC0 DMA_HOST_IN_DMAC
-#define DMA_ID_DMAC1 DMA_GP_LP_DMAC0
-#define DMA_ID_DMAC2 DMA_HOST_OUT_DMAC
-#define DMA_ID_DMAC3 DMA_GP_HP_DMAC0
-#define DMA_ID_DMAC4 DMA_GP_LP_DMAC1
-#define DMA_ID_DMAC5 DMA_GP_HP_DMAC1
-#define DMA_ID_DMAC6 DMA_LINK_IN_DMAC
-#define DMA_ID_DMAC7 DMA_LINK_OUT_DMAC
-
-/* handshakes */
-#define DMA_HANDSHAKE_DMIC_CH0 0
-#define DMA_HANDSHAKE_DMIC_CH1 1
-#define DMA_HANDSHAKE_SSP0_TX 2
-#define DMA_HANDSHAKE_SSP0_RX 3
-#define DMA_HANDSHAKE_SSP1_TX 4
-#define DMA_HANDSHAKE_SSP1_RX 5
-#define DMA_HANDSHAKE_SSP2_TX 6
-#define DMA_HANDSHAKE_SSP2_RX 7
-#define DMA_HANDSHAKE_SSP3_TX 8
-#define DMA_HANDSHAKE_SSP3_RX 9
-#define DMA_HANDSHAKE_SSP4_TX 10
-#define DMA_HANDSHAKE_SSP4_RX 11
-#define DMA_HANDSHAKE_SSP5_TX 12
-#define DMA_HANDSHAKE_SSP5_RX 13
-
-extern struct dma dma[PLATFORM_NUM_DMACS];
-
-#endif
diff --git a/src/platform/cannonlake/include/platform/idc.h b/src/platform/cannonlake/include/platform/idc.h
deleted file mode 100644
index cc6d4d6..0000000
--- a/src/platform/cannonlake/include/platform/idc.h
+++ /dev/null
@@ -1,51 +0,0 @@
-/*
- * Copyright (c) 2018, Intel Corporation
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- * * Redistributions of source code must retain the above copyright
- * notice, this list of conditions and the following disclaimer.
- * * Redistributions in binary form must reproduce the above copyright
- * notice, this list of conditions and the following disclaimer in the
- * documentation and/or other materials provided with the distribution.
- * * Neither the name of the Intel Corporation nor the
- * names of its contributors may be used to endorse or promote products
- * derived from this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
- * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
- * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
- * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
- * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
- * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
- * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
- * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
- * POSSIBILITY OF SUCH DAMAGE.
- *
- * Author: Tomasz Lauda <tomasz.lauda@linux.intel.com>
- */
-
-#ifndef __INCLUDE_PLATFORM_IDC_H__
-#define __INCLUDE_PLATFORM_IDC_H__
-
-#include <arch/idc.h>
-
-static inline int idc_send_msg(struct idc_msg *msg, uint32_t mode)
-{
- return arch_idc_send_msg(msg, mode);
-}
-
-static inline void idc_process_msg_queue(void)
-{
- arch_idc_process_msg_queue();
-}
-
-static inline void idc_init(void)
-{
- arch_idc_init();
-}
-
-#endif
diff --git a/src/platform/cannonlake/include/platform/interrupt.h b/src/platform/cannonlake/include/platform/interrupt.h
deleted file mode 100644
index b14cfdf..0000000
--- a/src/platform/cannonlake/include/platform/interrupt.h
+++ /dev/null
@@ -1,171 +0,0 @@
-/*
- * Copyright (c) 2017, Intel Corporation
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- * * Redistributions of source code must retain the above copyright
- * notice, this list of conditions and the following disclaimer.
- * * Redistributions in binary form must reproduce the above copyright
- * notice, this list of conditions and the following disclaimer in the
- * documentation and/or other materials provided with the distribution.
- * * Neither the name of the Intel Corporation nor the
- * names of its contributors may be used to endorse or promote products
- * derived from this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
- * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
- * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
- * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
- * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
- * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
- * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
- * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
- * POSSIBILITY OF SUCH DAMAGE.
- *
- * Author: Liam Girdwood <liam.r.girdwood@linux.intel.com>
- * Keyon Jie <yang.jie@linux.intel.com>
- * Rander Wang <rander.wang@intel.com>
- */
-
-#ifndef __INCLUDE_PLATFORM_INTERRUPT__
-#define __INCLUDE_PLATFORM_INTERRUPT__
-
-#include <stdint.h>
-#include <sof/interrupt-map.h>
-
-#define PLATFORM_IRQ_CHILDREN 32
-
-/* IRQ numbers - wrt Tensilica DSP */
-#define IRQ_NUM_SOFTWARE0 0 /* level 1 */
-#define IRQ_NUM_TIMER1 1 /* level 1 */
-#define IRQ_NUM_EXT_LEVEL1 2 /* level 1 */
-#define IRQ_NUM_SOFTWARE1 3 /* level 1 */
-#define IRQ_NUM_SOFTWARE2 4 /* level 2 */
-#define IRQ_NUM_TIMER2 5 /* level 2 */
-#define IRQ_NUM_EXT_LEVEL2 6 /* level 2 */
-#define IRQ_NUM_SOFTWARE3 7 /* level 2 */
-#define IRQ_NUM_SOFTWARE4 8 /* level 3 */
-#define IRQ_NUM_TIMER3 9 /* level 3 */
-#define IRQ_NUM_EXT_LEVEL3 10 /* level 3 */
-#define IRQ_NUM_SOFTWARE5 11 /* level 3 */
-#define IRQ_NUM_SOFTWARE6 12 /* level 4 */
-#define IRQ_NUM_EXT_LEVEL4 13 /* level 4 */
-#define IRQ_NUM_SOFTWARE7 14 /* level 4 */
-#define IRQ_NUM_SOFTWARE8 15 /* level 5 */
-#define IRQ_NUM_EXT_LEVEL5 16 /* level 5 */
-#define IRQ_NUM_EXT_LEVEL6 17 /* level 5 */
-#define IRQ_NUM_EXT_LEVEL7 18 /* level 5 */
-#define IRQ_NUM_SOFTWARE9 19 /* level 5 */
-#define IRQ_NUM_NMI 20 /* level 7 */
-
-/* IRQ Level 2 bits */
-#define IRQ_BIT_LVL2_HP_GP_DMA0(x) (x + 24)
-#define IRQ_BIT_LVL2_WALL_CLK1 23
-#define IRQ_BIT_LVL2_WALL_CLK0 22
-#define IRQ_BIT_LVL2_L2_MEMERR 21
-#define IRQ_BIT_LVL2_SHA256 16
-#define IRQ_BIT_LVL2_L2_CACHE 15
-#define IRQ_BIT_LVL2_IDC 8
-#define IRQ_BIT_LVL2_HOST_IPC 7
-#define IRQ_BIT_LVL2_CSME_IPC 6
-#define IRQ_BIT_LVL2_PMC_IPC 5
-
-/* IRQ Level 3 bits */
-#define IRQ_BIT_LVL3_CODE_LOADER 31
-#define IRQ_BIT_LVL3_HOST_STREAM_OUT(x) (16 + x)
-#define IRQ_BIT_LVL3_HOST_STREAM_IN(x) (0 + x)
-
-/* IRQ Level 4 bits */
-#define IRQ_BIT_LVL4_LINK_STREAM_OUT(x) (16 + x)
-#define IRQ_BIT_LVL4_LINK_STREAM_IN(x) (0 + x)
-
-/* IRQ Level 5 bits */
-#define IRQ_BIT_LVL5_LP_GP_DMA1 15
-#define IRQ_BIT_LVL5_LP_GP_DMA0 16
-#define IRQ_BIT_LVL5_DMIC 6
-#define IRQ_BIT_LVL5_SSP(x) (0 + x)
-
-/* Priority 2 Peripheral IRQ mappings */
-#define IRQ_EXT_HP_GPDMA_LVL2(xcpu) \
- SOF_IRQ(IRQ_BIT_LVL2_HP_GP_DMA0(0), 2, xcpu, IRQ_NUM_EXT_LEVEL2)
-#define IRQ_EXT_IDC_LVL2(xcpu) \
- SOF_IRQ(IRQ_BIT_LVL2_IDC, 2, xcpu, IRQ_NUM_EXT_LEVEL2)
-#define IRQ_EXT_IPC_LVL2(xcpu) \
- SOF_IRQ(IRQ_BIT_LVL2_HOST_IPC, 2, xcpu, IRQ_NUM_EXT_LEVEL2)
-#define IRQ_EXT_TSTAMP1_LVL2(xcpu) \
- SOF_IRQ(IRQ_BIT_LVL2_WALL_CLK1, 2, xcpu, IRQ_NUM_EXT_LEVEL2)
-#define IRQ_EXT_TSTAMP0_LVL2(xcpu) \
- SOF_IRQ(IRQ_BIT_LVL2_WALL_CLK0, 2, xcpu, IRQ_NUM_EXT_LEVEL2)
-#define IRQ_EXT_MERR_LVL2(xcpu) \
- SOF_IRQ(IRQ_BIT_LVL2_L2_MEMERR, 2, xcpu, IRQ_NUM_EXT_LEVEL2)
-#define IRQ_EXT_L2CACHE_LVL2(xcpu) \
- SOF_IRQ(IRQ_BIT_LVL2_L2_CACHE, 2, xcpu, IRQ_NUM_EXT_LEVEL2)
-#define IRQ_EXT_SHA256_LVL2(xcpu) \
- SOF_IRQ(IRQ_BIT_LVL2_SHA256, 2, xcpu, IRQ_NUM_EXT_LEVEL2)
-
-/* Priority 3 Peripheral IRQ mappings */
-#define IRQ_EXT_CODE_DMA_LVL3(xcpu) \
- SOF_IRQ(IRQ_BIT_LVL3_CODE_LOADER, 3, xcpu, IRQ_NUM_EXT_LEVEL3)
-#define IRQ_EXT_HOST_DMA_IN_LVL3(xcpu, channel) \
- SOF_IRQ(IRQ_BIT_LVL3_HOST_STREAM_IN(channel), 3, xcpu, IRQ_NUM_EXT_LEVEL3)
-#define IRQ_EXT_HOST_DMA_OUT_LVL3(xcpu, channel) \
- SOF_IRQ(IRQ_BIT_LVL3_HOST_STREAM_OUT(channel), 3, xcpu, IRQ_NUM_EXT_LEVEL3)
-
-/* Priority 4 Peripheral IRQ mappings */
-#define IRQ_EXT_LINK_DMA_IN_LVL4(xcpu, channel) \
- SOF_IRQ(IRQ_BIT_LVL4_LINK_STREAM_IN(channel), 4, xcpu, IRQ_NUM_EXT_LEVEL4)
-#define IRQ_EXT_LINK_DMA_OUT_LVL4(xcpu, channel) \
- SOF_IRQ(IRQ_BIT_LVL4_LINK_STREAM_OUT(channel), 4, xcpu, IRQ_NUM_EXT_LEVEL4)
-
-/* Priority 5 Peripheral IRQ mappings */
-#define IRQ_EXT_LP_GPDMA0_LVL5(xcpu, channel) \
- SOF_ID_IRQ(0, IRQ_BIT_LVL5_LP_GP_DMA0, 5, xcpu, IRQ_NUM_EXT_LEVEL5)
-#define IRQ_EXT_LP_GPDMA1_LVL5(xcpu, channel) \
- SOF_ID_IRQ(1, IRQ_BIT_LVL5_LP_GP_DMA0, 5, xcpu, IRQ_NUM_EXT_LEVEL5)
-#define IRQ_EXT_SSP0_LVL5(xcpu) \
- SOF_IRQ(IRQ_BIT_LVL5_SSP(0), 5, xcpu, IRQ_NUM_EXT_LEVEL5)
-#define IRQ_EXT_SSP1_LVL5(xcpu) \
- SOF_IRQ(IRQ_BIT_LVL5_SSP(1), 5, xcpu, IRQ_NUM_EXT_LEVEL5)
-#define IRQ_EXT_SSP2_LVL5(xcpu) \
- SOF_IRQ(IRQ_BIT_LVL5_SSP(2), 5, xcpu, IRQ_NUM_EXT_LEVEL5)
-#define IRQ_EXT_SSP3_LVL5(xcpu) \
- SOF_IRQ(IRQ_BIT_LVL5_SSP(3), 5, xcpu, IRQ_NUM_EXT_LEVEL5)
-#define IRQ_EXT_DMIC_LVL5(xcpu) \
- SOF_IRQ(IRQ_BIT_LVL5_DMIC, 5, xcpu, IRQ_NUM_EXT_LEVEL5)
-
-
-/* IRQ Masks */
-#define IRQ_MASK_SOFTWARE0 (1 << IRQ_NUM_SOFTWARE0)
-#define IRQ_MASK_TIMER1 (1 << IRQ_NUM_TIMER1)
-#define IRQ_MASK_EXT_LEVEL1 (1 << IRQ_NUM_EXT_LEVEL1)
-#define IRQ_MASK_SOFTWARE1 (1 << IRQ_NUM_SOFTWARE1)
-#define IRQ_MASK_SOFTWARE2 (1 << IRQ_NUM_SOFTWARE2)
-#define IRQ_MASK_TIMER2 (1 << IRQ_NUM_TIMER2)
-#define IRQ_MASK_EXT_LEVEL2 (1 << IRQ_NUM_EXT_LEVEL2)
-#define IRQ_MASK_SOFTWARE3 (1 << IRQ_NUM_SOFTWARE3)
-#define IRQ_MASK_SOFTWARE4 (1 << IRQ_NUM_SOFTWARE4)
-#define IRQ_MASK_TIMER3 (1 << IRQ_NUM_TIMER3)
-#define IRQ_MASK_EXT_LEVEL3 (1 << IRQ_NUM_EXT_LEVEL3)
-#define IRQ_MASK_SOFTWARE5 (1 << IRQ_NUM_SOFTWARE5)
-#define IRQ_MASK_SOFTWARE6 (1 << IRQ_NUM_SOFTWARE6)
-#define IRQ_MASK_EXT_LEVEL4 (1 << IRQ_NUM_EXT_LEVEL4)
-#define IRQ_MASK_SOFTWARE7 (1 << IRQ_NUM_SOFTWARE7)
-#define IRQ_MASK_SOFTWARE8 (1 << IRQ_NUM_SOFTWARE8)
-#define IRQ_MASK_EXT_LEVEL5 (1 << IRQ_NUM_EXT_LEVEL5)
-#define IRQ_MASK_EXT_LEVEL6 (1 << IRQ_NUM_EXT_LEVEL6)
-#define IRQ_MASK_EXT_LEVEL7 (1 << IRQ_NUM_EXT_LEVEL7)
-#define IRQ_MASK_SOFTWARE9 (1 << IRQ_NUM_SOFTWARE9)
-
-void platform_interrupt_init(void);
-
-struct irq_desc *platform_irq_get_parent(uint32_t irq);
-void platform_interrupt_set(int irq);
-void platform_interrupt_clear(uint32_t irq, uint32_t mask);
-uint32_t platform_interrupt_get_enabled(void);
-void platform_interrupt_mask(uint32_t irq, uint32_t mask);
-void platform_interrupt_unmask(uint32_t irq, uint32_t mask);
-
-#endif
diff --git a/src/platform/cannonlake/include/platform/mailbox.h b/src/platform/cannonlake/include/platform/mailbox.h
deleted file mode 100644
index 2b68bcb..0000000
--- a/src/platform/cannonlake/include/platform/mailbox.h
+++ /dev/null
@@ -1,83 +0,0 @@
-/*
- * Copyright (c) 2017, Intel Corporation
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- * * Redistributions of source code must retain the above copyright
- * notice, this list of conditions and the following disclaimer.
- * * Redistributions in binary form must reproduce the above copyright
- * notice, this list of conditions and the following disclaimer in the
- * documentation and/or other materials provided with the distribution.
- * * Neither the name of the Intel Corporation nor the
- * names of its contributors may be used to endorse or promote products
- * derived from this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
- * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
- * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
- * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
- * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
- * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
- * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
- * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
- * POSSIBILITY OF SUCH DAMAGE.
- *
- * Author: Liam Girdwood <liam.r.girdwood@linux.intel.com>
- * Keyon Jie <yang.jie@linux.intel.com>
- * Rander Wang <rander.wang@intel.com>
- */
-
-#ifndef __INCLUDE_PLATFORM_MAILBOX__
-#define __INCLUDE_PLATFORM_MAILBOX__
-
-#include <platform/memory.h>
-
-
-/*
- * The Window Region on Broxton HPSRAM is organised like this :-
- * +--------------------------------------------------------------------------+
- * | Offset | Region | Size |
- * +---------------------+----------------+-----------------------------------+
- * | SRAM_TRACE_BASE | Trace Buffer W3| SRAM_TRACE_SIZE |
- * +---------------------+----------------+-----------------------------------+
- * | SRAM_DEBUG_BASE | Debug data W2 | SRAM_DEBUG_SIZE |
- * +---------------------+----------------+-----------------------------------+
- * | SRAM_INBOX_BASE | Inbox W1 | SRAM_INBOX_SIZE |
- * +---------------------+----------------+-----------------------------------+
- * | SRAM_OUTBOX_BASE | Outbox W0 | SRAM_MAILBOX_SIZE |
- * +---------------------+----------------+-----------------------------------+
- * | SRAM_SW_REG_BASE | SW Registers W0| SRAM_SW_REG_SIZE |
- * +---------------------+----------------+-----------------------------------+
- */
-
-/* window 3 - trace */
-#define MAILBOX_TRACE_SIZE SRAM_TRACE_SIZE
-#define MAILBOX_TRACE_BASE SRAM_TRACE_BASE
-
-/* window 2 debug, exception and stream */
-#define MAILBOX_DEBUG_SIZE SRAM_DEBUG_SIZE
-#define MAILBOX_DEBUG_BASE SRAM_DEBUG_BASE
-
-#define MAILBOX_EXCEPTION_SIZE SRAM_EXCEPT_SIZE
-#define MAILBOX_EXCEPTION_BASE SRAM_EXCEPT_BASE
-#define MAILBOX_EXCEPTION_OFFSET SRAM_DEBUG_SIZE
-
-#define MAILBOX_STREAM_SIZE SRAM_STREAM_SIZE
-#define MAILBOX_STREAM_BASE SRAM_STREAM_BASE
-#define MAILBOX_STREAM_OFFSET (SRAM_DEBUG_SIZE + SRAM_EXCEPT_SIZE)
-
-/* window 1 inbox/downlink and FW registers */
-#define MAILBOX_HOSTBOX_SIZE SRAM_INBOX_SIZE
-#define MAILBOX_HOSTBOX_BASE SRAM_INBOX_BASE
-
-/* window 0 */
-#define MAILBOX_DSPBOX_SIZE SRAM_OUTBOX_SIZE
-#define MAILBOX_DSPBOX_BASE SRAM_OUTBOX_BASE
-
-#define MAILBOX_SW_REG_SIZE SRAM_SW_REG_SIZE
-#define MAILBOX_SW_REG_BASE SRAM_SW_REG_BASE
-
-#endif
diff --git a/src/platform/cannonlake/include/platform/memory.h b/src/platform/cannonlake/include/platform/memory.h
deleted file mode 100644
index 721a7ff..0000000
--- a/src/platform/cannonlake/include/platform/memory.h
+++ /dev/null
@@ -1,360 +0,0 @@
-/*
- * Copyright (c) 2017, Intel Corporation
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- * * Redistributions of source code must retain the above copyright
- * notice, this list of conditions and the following disclaimer.
- * * Redistributions in binary form must reproduce the above copyright
- * notice, this list of conditions and the following disclaimer in the
- * documentation and/or other materials provided with the distribution.
- * * Neither the name of the Intel Corporation nor the
- * names of its contributors may be used to endorse or promote products
- * derived from this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
- * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
- * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
- * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
- * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
- * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
- * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
- * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
- * POSSIBILITY OF SUCH DAMAGE.
- *
- * Author: Liam Girdwood <liam.r.girdwood@linux.intel.com>
- * Keyon Jie <yang.jie@linux.intel.com>
- * Rander Wang <rander.wang@intel.com>
- */
-
-#ifndef __PLATFORM_MEMORY_H__
-#define __PLATFORM_MEMORY_H__
-
-#include <config.h>
-
-/* physical DSP addresses */
-
-/* shim */
-#define SHIM_BASE 0x00071F00
-#define SHIM_SIZE 0x00000100
-
-/* cmd IO to audio codecs */
-#define CMD_BASE 0x00001100
-#define CMD_SIZE 0x00000010
-
-/* resource allocation */
-#define RES_BASE 0x00001110
-#define RES_SIZE 0x00000010
-
-/* IPC to the host */
-#define IPC_HOST_BASE 0x00071E00
-#define IPC_HOST_SIZE 0x00000020
-
-/* intra DSP IPC */
-#define IPC_DSP_SIZE 0x00000080
-#define IPC_DSP_BASE(x) (0x00001200 + x * IPC_DSP_SIZE)
-
-/* SRAM window for HOST */
-#define HOST_WIN_SIZE 0x00000008
-#define HOST_WIN_BASE(x) (0x00071A00 + x * HOST_WIN_SIZE)
-
-/* IRQ controller */
-#define IRQ_BASE 0x00078800
-#define IRQ_SIZE 0x00000200
-
-/* time stamping */
-#define TIME_BASE 0x00071800
-#define TIME_SIZE 0x00000200
-
-/* M/N dividers */
-#define MN_BASE 0x00078C00
-#define MN_SIZE 0x00000200
-
-/* low power DMA position */
-#define LP_GP_DMA_LINK_SIZE 0x00000080
-#define LP_GP_DMA_LINK_BASE(x) (0x00001C00 + x * LP_GP_DMA_LINK_SIZE)
-
-/* high performance DMA position */
-#define HP_GP_DMA_LINK_SIZE 0x00000800
-#define HP_GP_DMA_LINK_BASE(x) (0x00001D00 + x * HP_GP_DMA_LINK_SIZE)
-
-/* link DMAC stream */
-#define GTW_LINK_OUT_STREAM_SIZE 0x00000020
-#define GTW_LINK_OUT_STREAM_BASE(x) \
- (0x00072400 + x * GTW_LINK_OUT_STREAM_SIZE)
-
-#define GTW_LINK_IN_STREAM_SIZE 0x00000020
-#define GTW_LINK_IN_STREAM_BASE(x) \
- (0x00072600 + x * GTW_LINK_IN_STREAM_SIZE)
-
-/* host DMAC stream */
-#define GTW_HOST_OUT_STREAM_SIZE 0x00000040
-#define GTW_HOST_OUT_STREAM_BASE(x) \
- (0x00072800 + x * GTW_HOST_OUT_STREAM_SIZE)
-
-#define GTW_HOST_IN_STREAM_SIZE 0x00000040
-#define GTW_HOST_IN_STREAM_BASE(x) \
- (0x00072C00 + x * GTW_HOST_IN_STREAM_SIZE)
-
-/* code loader */
-#define GTW_CODE_LDR_SIZE 0x00000040
-#define GTW_CODE_LDR_BASE 0x00002BC0
-
-/* L2 TLBs */
-#define L2_HP_SRAM_TLB_SIZE 0x00001000
-#define L2_HP_SRAM_TLB_BASE 0x00003000
-
-/* DMICs */
-#define DMIC_BASE 0x00010000
-#define DMIC_SIZE 0x00008000
-
-/* SSP */
-#define SSP_BASE(x) (0x00077000 + x * SSP_SIZE)
-#define SSP_SIZE 0x0000200
-
-/* low power DMACs */
-#define LP_GP_DMA_SIZE 0x00001000
-#define LP_GP_DMA_BASE(x) (0x0007C000 + x * LP_GP_DMA_SIZE)
-
-/* high performance DMACs */
-#define HP_GP_DMA_SIZE 0x00001000
-#define HP_GP_DMA_BASE(x) (0x0000E000 + x * HP_GP_DMA_SIZE)
-
-/* ROM */
-#define ROM_BASE 0xBEFE0000
-#define ROM_SIZE 0x00002000
-
-/*
- * The HP SRAM Region on Cannonlake is organised like this :-
- * +--------------------------------------------------------------------------+
- * | Offset | Region | Size |
- * +---------------------+----------------+-----------------------------------+
- * | SRAM_SW_REG_BASE | SW Registers W0| SRAM_SW_REG_SIZE |
- * +---------------------+----------------+-----------------------------------+
- * | SRAM_OUTBOX_BASE | Outbox W0 | SRAM_MAILBOX_SIZE |
- * +---------------------+----------------+-----------------------------------+
- * | SRAM_INBOX_BASE | Inbox W1 | SRAM_INBOX_SIZE |
- * +---------------------+----------------+-----------------------------------+
- * | SRAM_DEBUG_BASE | Debug data W2 | SRAM_DEBUG_SIZE |
- * +---------------------+----------------+-----------------------------------+
- * | SRAM_EXCEPT_BASE | Debug data W2 | SRAM_EXCEPT_SIZE |
- * +---------------------+----------------+-----------------------------------+
- * | SRAM_STREAM_BASE | Stream data W2 | SRAM_STREAM_SIZE |
- * +---------------------+----------------+-----------------------------------+
- * | SRAM_TRACE_BASE | Trace Buffer W3| SRAM_TRACE_SIZE |
- * +---------------------+----------------+-----------------------------------+
- * | HP_SRAM_BASE | DMA | HEAP_HP_BUFFER_SIZE |
- * +---------------------+----------------+-----------------------------------+
- * | HEAP_SYSTEM_BASE | System Heap | HEAP_SYSTEM_SIZE |
- * +---------------------+----------------+-----------------------------------+
- * | HEAP_RUNTIME_BASE | Runtime Heap | HEAP_RUNTIME_SIZE |
- * +---------------------+----------------+-----------------------------------+
- * | HEAP_BUFFER_BASE | Module Buffers | HEAP_BUFFER_SIZE |
- * +---------------------+----------------+-----------------------------------+
- * | SOF_STACK_END | Stack | SOF_STACK_SIZE |
- * +---------------------+----------------+-----------------------------------+
- * | SOF_STACK_BASE | | |
- * +---------------------+----------------+-----------------------------------+
- */
-
-/* HP SRAM */
-#define SRAM_ALIAS_OFFSET 0x20000000
-#define HP_SRAM_BASE 0xBE000000
-#define HP_SRAM_SIZE 0x002F0000
-
-/* HP SRAM Base */
-#define HP_SRAM_VECBASE_RESET (HP_SRAM_BASE + 0x40000)
-
-/* Heap section sizes for module pool */
-#define HEAP_RT_COUNT64 256
-#define HEAP_RT_COUNT128 32
-#define HEAP_RT_COUNT256 64
-#define HEAP_RT_COUNT512 32
-
-#define L2_VECTOR_SIZE 0x1000
-
-/* HP SRAM windows */
-/* window 0 */
-#define SRAM_SW_REG_BASE (HP_SRAM_BASE + 0x4000)
-#define SRAM_SW_REG_SIZE 0x1000
-
-/* SRAM window 0 FW "registers" */
-#define SRAM_REG_ROM_STATUS 0x0
-#define SRAM_REG_FW_STATUS 0x4
-#define SRAM_REG_FW_TRACEP 0x8
-#define SRAM_REG_FW_END 0xc
-
-#define SRAM_OUTBOX_BASE (SRAM_SW_REG_BASE + SRAM_SW_REG_SIZE)
-#define SRAM_OUTBOX_SIZE 0x1000
-
-/* window 1 */
-#define SRAM_INBOX_BASE (SRAM_OUTBOX_BASE + SRAM_OUTBOX_SIZE)
-#define SRAM_INBOX_SIZE 0x2000
-
-/* window 2 */
-#define SRAM_DEBUG_BASE (SRAM_INBOX_BASE + SRAM_INBOX_SIZE)
-#define SRAM_DEBUG_SIZE 0x800
-
-#define SRAM_EXCEPT_BASE (SRAM_DEBUG_BASE + SRAM_DEBUG_SIZE)
-#define SRAM_EXCEPT_SIZE 0x800
-
-#define SRAM_STREAM_BASE (SRAM_EXCEPT_BASE + SRAM_EXCEPT_SIZE)
-#define SRAM_STREAM_SIZE 0x1000
-
-/* window 3 */
-#define SRAM_TRACE_BASE (SRAM_STREAM_BASE + SRAM_STREAM_SIZE)
-#define SRAM_TRACE_SIZE 0x2000
-
-#define HP_SRAM_WIN0_BASE SRAM_SW_REG_BASE
-#define HP_SRAM_WIN0_SIZE (SRAM_SW_REG_SIZE + SRAM_OUTBOX_SIZE)
-#define HP_SRAM_WIN1_BASE SRAM_INBOX_BASE
-#define HP_SRAM_WIN1_SIZE SRAM_INBOX_SIZE
-#define HP_SRAM_WIN2_BASE SRAM_DEBUG_BASE
-#define HP_SRAM_WIN2_SIZE (SRAM_DEBUG_SIZE + SRAM_EXCEPT_SIZE + \
- SRAM_STREAM_SIZE)
-#define HP_SRAM_WIN3_BASE SRAM_TRACE_BASE
-#define HP_SRAM_WIN3_SIZE SRAM_TRACE_SIZE
-
-#define HEAP_HP_BUFFER_BASE (SRAM_TRACE_BASE + SRAM_TRACE_SIZE)
-#define HEAP_HP_BUFFER_SIZE 0x20000
-#define HEAP_HP_BUFFER_BLOCK_SIZE 0x180
-#define HEAP_HP_BUFFER_COUNT \
- (HEAP_HP_BUFFER_SIZE / HEAP_HP_BUFFER_BLOCK_SIZE)
-
-/* text and data share the same HP L2 SRAM on Cannonlake */
-#define SOF_TEXT_START 0xBE040400
-#define SOF_TEXT_BASE (SOF_TEXT_START)
-#define SOF_TEXT_SIZE (0x18000 - 0x400)
-
-/* initialized data */
-#if defined CONFIG_DMIC
-#define SOF_DATA_SIZE 0x1b000
-#else
-#define SOF_DATA_SIZE 0x19000
-#endif
-
-/* bss data */
-#define SOF_BSS_DATA_SIZE 0x10900
-
-/* Heap configuration */
-#define HEAP_SYSTEM_BASE (SOF_TEXT_BASE + SOF_TEXT_SIZE + \
- SOF_DATA_SIZE + SOF_BSS_DATA_SIZE)
-
-#define HEAP_SYSTEM_SIZE 0x11000
-
-#define HEAP_RUNTIME_BASE (HEAP_SYSTEM_BASE + HEAP_SYSTEM_SIZE)
-#define HEAP_RUNTIME_SIZE \
- (HEAP_RT_COUNT64 * 64 + HEAP_RT_COUNT128 * 128 + \
- HEAP_RT_COUNT256 * 256 + HEAP_RT_COUNT512 * 512)
-
-/* Stack configuration */
-#define SOF_STACK_SIZE 0x2000
-#define SOF_STACK_BASE (HP_SRAM_BASE + HP_SRAM_SIZE)
-#define SOF_STACK_END (SOF_STACK_BASE - SOF_STACK_SIZE)
-
-#define HEAP_BUFFER_BASE (HEAP_RUNTIME_BASE + HEAP_RUNTIME_SIZE)
-#define HEAP_BUFFER_SIZE \
- (SOF_STACK_END - HEAP_BUFFER_BASE)
-#define HEAP_BUFFER_BLOCK_SIZE 0x180
-#define HEAP_BUFFER_COUNT (HEAP_BUFFER_SIZE / HEAP_BUFFER_BLOCK_SIZE)
-
-/*
- * The LP SRAM Heap and Stack on Cannonlake are organised like this :-
- *
- * +--------------------------------------------------------------------------+
- * | Offset | Region | Size |
- * +---------------------+----------------+-----------------------------------+
- * | LP_SRAM_BASE | RO Data | SOF_LP_DATA_SIZE |
- * | | Data | |
- * | | BSS | |
- * +---------------------+----------------+-----------------------------------+
- * | HEAP_LP_SYSTEM_BASE | System Heap | HEAP_LP_SYSTEM_SIZE |
- * +---------------------+----------------+-----------------------------------+
- * | HEAP_LP_RUNTIME_BASE| Runtime Heap | HEAP_LP_RUNTIME_SIZE |
- * +---------------------+----------------+-----------------------------------+
- * | HEAP_LP_BUFFER_BASE | Module Buffers | HEAP_LP_BUFFER_SIZE |
- * +---------------------+----------------+-----------------------------------+
- * | SOF_LP_STACK_END | Stack | SOF_LP_STACK_SIZE |
- * +---------------------+----------------+-----------------------------------+
- * | SOF_STACK_BASE | | |
- * +---------------------+----------------+-----------------------------------+
- */
-
-/* LP SRAM */
-#define LP_SRAM_BASE 0xBE800000
-#define LP_SRAM_SIZE 0x00020000
-
-/* Heap section sizes for module pool */
-#define HEAP_RT_LP_COUNT8 0
-#define HEAP_RT_LP_COUNT16 256
-#define HEAP_RT_LP_COUNT32 128
-#define HEAP_RT_LP_COUNT64 64
-#define HEAP_RT_LP_COUNT128 32
-#define HEAP_RT_LP_COUNT256 16
-#define HEAP_RT_LP_COUNT512 8
-#define HEAP_RT_LP_COUNT1024 4
-
-/* Heap configuration */
-#define SOF_LP_DATA_SIZE 0x4000
-
-#define HEAP_LP_SYSTEM_BASE (LP_SRAM_BASE + SOF_LP_DATA_SIZE)
-#define HEAP_LP_SYSTEM_SIZE 0x1000
-
-#define HEAP_LP_RUNTIME_BASE (HEAP_LP_SYSTEM_BASE + HEAP_LP_SYSTEM_SIZE)
-#define HEAP_LP_RUNTIME_SIZE \
- (HEAP_RT_LP_COUNT8 * 8 + HEAP_RT_LP_COUNT16 * 16 + \
- HEAP_RT_LP_COUNT32 * 32 + HEAP_RT_LP_COUNT64 * 64 + \
- HEAP_RT_LP_COUNT128 * 128 + HEAP_RT_LP_COUNT256 * 256 + \
- HEAP_RT_LP_COUNT512 * 512 + HEAP_RT_LP_COUNT1024 * 1024)
-
-#define HEAP_LP_BUFFER_BASE (HEAP_LP_RUNTIME_BASE + HEAP_LP_RUNTIME_SIZE)
-#define HEAP_LP_BUFFER_SIZE \
- (LP_SRAM_SIZE - HEAP_LP_RUNTIME_SIZE - SOF_LP_STACK_SIZE - HEAP_LP_SYSTEM_SIZE)
-
-#define HEAP_LP_BUFFER_BLOCK_SIZE 0x180
-#define HEAP_LP_BUFFER_COUNT (HEAP_LP_BUFFER_SIZE / HEAP_LP_BUFFER_BLOCK_SIZE)
-
-
-#define PLATFORM_HEAP_RUNTIME 1
-#define PLATFORM_HEAP_BUFFER 3
-
-/* Stack configuration */
-#define SOF_LP_STACK_SIZE 0x1000
-#define SOF_LP_STACK_BASE (LP_SRAM_BASE + LP_SRAM_SIZE)
-#define SOF_LP_STACK_END (SOF_LP_STACK_BASE - SOF_LP_STACK_SIZE)
-
-
-/* Vector and literal sizes - do not use core-isa.h */
-#define SOF_MEM_VECBASE HP_SRAM_VECBASE_RESET
-#define SOF_MEM_VECT_LIT_SIZE 0x8
-#define SOF_MEM_VECT_TEXT_SIZE 0x38
-#define SOF_MEM_VECT_SIZE (SOF_MEM_VECT_TEXT_SIZE + SOF_MEM_VECT_LIT_SIZE)
-
-#define SOF_MEM_ERROR_TEXT_SIZE 0x180
-#define SOF_MEM_ERROR_LIT_SIZE 0x8
-
-#define SOF_MEM_RESET_TEXT_SIZE 0x268
-#define SOF_MEM_RESET_LIT_SIZE 0x8
-#define SOF_MEM_VECBASE_LIT_SIZE 0x178
-
-#define SOF_MEM_RO_SIZE 0x8
-
-/* boot loader in IMR */
-#define IMR_BOOT_LDR_MANIFEST_BASE 0xB0032000
-#define IMR_BOOT_LDR_MANIFEST_SIZE 0x6000
-
-#define IMR_BOOT_LDR_TEXT_ENTRY_BASE 0xB0038000
-#define IMR_BOOT_LDR_TEXT_ENTRY_SIZE 0x86
-#define IMR_BOOT_LDR_LIT_BASE (IMR_BOOT_LDR_TEXT_ENTRY_BASE + IMR_BOOT_LDR_TEXT_ENTRY_SIZE)
-#define IMR_BOOT_LDR_LIT_SIZE 0x22
-#define IMR_BOOT_LDR_TEXT_BASE (IMR_BOOT_LDR_LIT_BASE + IMR_BOOT_LDR_LIT_SIZE)
-#define IMR_BOOT_LDR_TEXT_SIZE 0x1C00
-#define IMR_BOOT_LDR_DATA_BASE 0xB0039000
-#define IMR_BOOT_LDR_DATA_SIZE 0x1000
-#define IMR_BOOT_LDR_BSS_BASE 0xB0100000
-#define IMR_BOOT_LDR_BSS_SIZE 0x10000
-
-#endif
diff --git a/src/platform/cannonlake/include/platform/platcfg.h b/src/platform/cannonlake/include/platform/platcfg.h
deleted file mode 100644
index f455ff2..0000000
--- a/src/platform/cannonlake/include/platform/platcfg.h
+++ /dev/null
@@ -1,40 +0,0 @@
-/*
- * Copyright (c) 2018, Intel Corporation
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- * * Redistributions of source code must retain the above copyright
- * notice, this list of conditions and the following disclaimer.
- * * Redistributions in binary form must reproduce the above copyright
- * notice, this list of conditions and the following disclaimer in the
- * documentation and/or other materials provided with the distribution.
- * * Neither the name of the Intel Corporation nor the
- * names of its contributors may be used to endorse or promote products
- * derived from this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
- * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
- * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
- * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
- * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
- * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
- * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
- * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
- * POSSIBILITY OF SUCH DAMAGE.
- *
- * Author: Liam Girdwood <liam.r.girdwood@linux.intel.com>
- */
-
-#ifndef __PLATFORM_PLATCFG_H__
-#define __PLATFORM_PLATCFG_H__
-
-#define PLATFORM_RESET_MHE_AT_BOOT 1
-
-#define PLATFORM_CORE_COUNT 4
-
-#define PLATFORM_MASTER_CORE_ID 0
-
-#endif
diff --git a/src/platform/cannonlake/include/platform/platform.h b/src/platform/cannonlake/include/platform/platform.h
deleted file mode 100644
index 571c1e5..0000000
--- a/src/platform/cannonlake/include/platform/platform.h
+++ /dev/null
@@ -1,156 +0,0 @@
-/*
- * Copyright (c) 2017, Intel Corporation
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- * * Redistributions of source code must retain the above copyright
- * notice, this list of conditions and the following disclaimer.
- * * Redistributions in binary form must reproduce the above copyright
- * notice, this list of conditions and the following disclaimer in the
- * documentation and/or other materials provided with the distribution.
- * * Neither the name of the Intel Corporation nor the
- * names of its contributors may be used to endorse or promote products
- * derived from this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
- * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
- * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
- * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
- * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
- * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
- * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
- * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
- * POSSIBILITY OF SUCH DAMAGE.
- *
- * Author: Liam Girdwood <liam.r.girdwood@linux.intel.com>
- * Keyon Jie <yang.jie@linux.intel.com>
- * Rander Wang <rander.wang@intel.com>
- * Xiuli Pan <xiuli.pan@linux.intel.com>
- */
-
-#ifndef __PLATFORM_PLATFORM_H__
-#define __PLATFORM_PLATFORM_H__
-
-#include <sof/platform.h>
-#include <platform/platcfg.h>
-#include <platform/shim.h>
-#include <platform/interrupt.h>
-#include <uapi/ipc.h>
-
-struct sof;
-
-#define PLATFORM_WAITI_DELAY 1
-
-#define PLATFORM_SSP_COUNT 3
-#define MAX_GPDMA_COUNT 2
-
-/* DGMBS align value */
-#define PLATFORM_HDA_BUFFER_ALIGNMENT 0x20
-
-/* Host page size */
-#define HOST_PAGE_SIZE 4096
-#define PLATFORM_PAGE_TABLE_SIZE 256
-
-/* IDC Interrupt */
-#define PLATFORM_IDC_INTERRUPT(x) IRQ_EXT_IDC_LVL2(x)
-
-/* IPC Interrupt */
-#define PLATFORM_IPC_INTERUPT IRQ_EXT_IPC_LVL2(0)
-
-/* pipeline IRQ */
-#define PLATFORM_SCHEDULE_IRQ IRQ_NUM_SOFTWARE4
-
-#define PLATFORM_IRQ_TASK_HIGH IRQ_NUM_SOFTWARE3
-#define PLATFORM_IRQ_TASK_MED IRQ_NUM_SOFTWARE2
-#define PLATFORM_IRQ_TASK_LOW IRQ_NUM_SOFTWARE1
-
-#define PLATFORM_SCHEDULE_COST 200
-
-/* maximum preload pipeline depth */
-#define MAX_PRELOAD_SIZE 20
-
-/* DMA treats PHY addresses as host address unless within DSP region */
-#define PLATFORM_HOST_DMA_MASK 0x00000000
-
-/* Platform stream capabilities */
-#define PLATFORM_MAX_CHANNELS 4
-#define PLATFORM_MAX_STREAMS 5
-
-/* clock source used by scheduler for deadline calculations */
-#define PLATFORM_SCHED_CLOCK CLK_SSP
-
-/* DMA channel drain timeout in microseconds - TODO: caclulate based on topology */
-#define PLATFORM_DMA_TIMEOUT 1333
-
-/* DMA host transfer timeouts in microseconds */
-#define PLATFORM_HOST_DMA_TIMEOUT 50
-
-/* WorkQ window size in microseconds */
-#define PLATFORM_WORKQ_WINDOW 2000
-
-/* platform WorkQ clock */
-#define PLATFORM_WORKQ_CLOCK CLK_SSP
-
-/* Host finish work schedule delay in microseconds */
-#define PLATFORM_HOST_FINISH_DELAY 100
-
-/* Host finish work(drain from host to dai) timeout in microseconds */
-#define PLATFORM_HOST_FINISH_TIMEOUT 50000
-
-/* local buffer size of DMA tracing */
-#define DMA_TRACE_LOCAL_SIZE HOST_PAGE_SIZE
-
-/* trace bytes flushed during panic */
-#define DMA_FLUSH_TRACE_SIZE (MAILBOX_TRACE_SIZE >> 2)
-
-/* the interval of DMA trace copying */
-#define DMA_TRACE_PERIOD 500000
-
-/*
- * the interval of reschedule DMA trace copying in special case like half
- * fullness of local DMA trace buffer
- */
-#define DMA_TRACE_RESCHEDULE_TIME 5
-
-/* DSP should be idle in this time frame */
-#define PLATFORM_IDLE_TIME 750000
-
-/* DSP default delay in cycles */
-#define PLATFORM_DEFAULT_DELAY 12
-
-/* minimal L1 exit time in cycles */
-#define PLATFORM_FORCE_L1_EXIT_TIME 985
-
-/* the SSP port fifo depth */
-#define SSP_FIFO_DEPTH 16
-
-/* the watermark for the SSP fifo depth setting */
-#define SSP_FIFO_WATERMARK 8
-
-/* Platform defined trace code */
-static inline void platform_panic(uint32_t p)
-{
- mailbox_sw_reg_write(SRAM_REG_FW_STATUS, p & 0x3fffffff);
- ipc_write(IPC_DIPCIDD, MAILBOX_EXCEPTION_OFFSET + 2 * 0x20000);
- ipc_write(IPC_DIPCIDR, 0x80000000 | (p & 0x3fffffff));
-}
-
-/* Platform defined trace code */
-#define platform_trace_point(__x) \
- mailbox_sw_reg_write(SRAM_REG_FW_TRACEP, (__x))
-
-extern struct timer *platform_timer;
-
-/*
- * APIs declared here are defined for every platform and IPC mechanism.
- */
-
-int platform_ssp_set_mn(uint32_t ssp_port, uint32_t source, uint32_t rate,
- uint32_t bclk_fs);
-
-void platform_ssp_disable_mn(uint32_t ssp_port);
-
-#endif
diff --git a/src/platform/cannonlake/include/platform/pm_runtime.h b/src/platform/cannonlake/include/platform/pm_runtime.h
deleted file mode 100644
index 3cf113d..0000000
--- a/src/platform/cannonlake/include/platform/pm_runtime.h
+++ /dev/null
@@ -1,65 +0,0 @@
-/*
- * Copyright (c) 2018, Intel Corporation
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- * * Redistributions of source code must retain the above copyright
- * notice, this list of conditions and the following disclaimer.
- * * Redistributions in binary form must reproduce the above copyright
- * notice, this list of conditions and the following disclaimer in the
- * documentation and/or other materials provided with the distribution.
- * * Neither the name of the Intel Corporation nor the
- * names of its contributors may be used to endorse or promote products
- * derived from this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
- * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
- * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
- * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
- * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
- * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
- * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
- * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
- * POSSIBILITY OF SUCH DAMAGE.
- *
- * Author: Tomasz Lauda <tomasz.lauda@linux.intel.com>
- */
-
-/**
- * \file platform/cannonlake/include/platform/pm_runtime.h
- * \brief Runtime power management header file for Cannonlake
- * \author Tomasz Lauda <tomasz.lauda@linux.intel.com>
- */
-
-#ifndef __INCLUDE_PLATFORM_PM_RUNTIME__
-#define __INCLUDE_PLATFORM_PM_RUNTIME__
-
-#include <sof/pm_runtime.h>
-
-/** \brief Platform specific runtime power management data. */
-struct platform_pm_runtime_data {
- /* TBD */
-};
-
-/**
- * \brief Initializes platform specific runtime power management.
- * \param[in,out] prd Runtime power management data.
- */
-void platform_pm_runtime_init(struct pm_runtime_data *prd);
-
-/**
- * \brief Retrieves platform specific power management resource.
- * \param[in] context Type of power management context.
- */
-void platform_pm_runtime_get(enum pm_runtime_context context);
-
-/**
- * \brief Releases platform specific power management resource.
- * \param[in] context Type of power management context.
- */
-void platform_pm_runtime_put(enum pm_runtime_context context);
-
-#endif /* __INCLUDE_PLATFORM_PM_RUNTIME__ */
diff --git a/src/platform/cannonlake/include/platform/shim.h b/src/platform/cannonlake/include/platform/shim.h
deleted file mode 100644
index 828700c..0000000
--- a/src/platform/cannonlake/include/platform/shim.h
+++ /dev/null
@@ -1,317 +0,0 @@
-/*
- * Copyright (c) 2017, Intel Corporation
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- * * Redistributions of source code must retain the above copyright
- * notice, this list of conditions and the following disclaimer.
- * * Redistributions in binary form must reproduce the above copyright
- * notice, this list of conditions and the following disclaimer in the
- * documentation and/or other materials provided with the distribution.
- * * Neither the name of the Intel Corporation nor the
- * names of its contributors may be used to endorse or promote products
- * derived from this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
- * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
- * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
- * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
- * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
- * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
- * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
- * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
- * POSSIBILITY OF SUCH DAMAGE.
- *
- * Author: Liam Girdwood <liam.r.girdwood@linux.intel.com>
- * Keyon Jie <yang.jie@linux.intel.com>
- * Rander Wang <rander.wang@intel.com>
- */
-
-#ifndef __PLATFORM_SHIM_H__
-#define __PLATFORM_SHIM_H__
-
-#include <platform/memory.h>
-
-#ifndef ASSEMBLY
-#include <stdint.h>
-#endif
-
-/* DSP IPC for Host Registers */
-#define IPC_DIPCTDR 0x00
-#define IPC_DIPCTDA 0x04
-#define IPC_DIPCTDD 0x08
-#define IPC_DIPCIDR 0x10
-#define IPC_DIPCIDA 0x14
-#define IPC_DIPCIDD 0x18
-#define IPC_DIPCCTL 0x28
-
-
-/* DIPCTDR */
-#define IPC_DIPCTDR_BUSY (1 << 31)
-#define IPC_DIPCTDR_MSG_MASK 0x7FFFFFFF
-
-/* DIPCTDA */
-#define IPC_DIPCTDA_BUSY (1 << 31)
-#define IPC_DIPCTDA_MSG_MASK 0x7FFFFFFF
-
-/* DIPCTE */
-#define IPC_DIPCTE_MSG_MASK 0x3FFFFFFF
-
-/* DIPCIDA*/
-#define IPC_DIPCIDA_DONE (1 << 31)
-
-/* DIPCIE */
-#define IPC_DIPCIE_DONE (1 << 31)
-#define IPC_DIPCIE_MSG_MASK 0x3FFFFFFF
-
-/* DIPCCTL */
-#define IPC_DIPCCTL_IPCIDIE (1 << 1)
-#define IPC_DIPCCTL_IPCTBIE (1 << 0)
-
-#define IPC_DSP_OFFSET 0x10
-
-/* DSP IPC for intra DSP communication */
-#define IPC_IDCTFC(x) (0x0 + x * IPC_DSP_OFFSET)
-#define IPC_IDCTEFC(x) (0x4 + x * IPC_DSP_OFFSET)
-#define IPC_IDCITC(x) (0x8 + x * IPC_DSP_OFFSET)
-#define IPC_IDCIETC(x) (0xc + x * IPC_DSP_OFFSET)
-#define IPC_IDCCTL 0x50
-
-/* IDCTFC */
-#define IPC_IDCTFC_BUSY (1 << 31)
-#define IPC_IDCTFC_MSG_MASK 0x7FFFFFFF
-
-/* IDCTEFC */
-#define IPC_IDCTEFC_MSG_MASK 0x3FFFFFFF
-
-/* IDCITC */
-#define IPC_IDCITC_BUSY (1 << 31)
-#define IPC_IDCITC_MSG_MASK 0x7FFFFFFF
-
-/* IDCIETC */
-#define IPC_IDCIETC_DONE (1 << 30)
-#define IPC_IDCIETC_MSG_MASK 0x3FFFFFFF
-
-/* IDCCTL */
-#define IPC_IDCCTL_IDCIDIE(x) (0x100 << (x))
-#define IPC_IDCCTL_IDCTBIE(x) (0x1 << (x))
-
-#define IRQ_CPU_OFFSET 0x40
-
-#define REG_IRQ_IL2MSD(xcpu) (0x0 + (xcpu * IRQ_CPU_OFFSET))
-#define REG_IRQ_IL2MCD(xcpu) (0x4 + (xcpu * IRQ_CPU_OFFSET))
-#define REG_IRQ_IL2MD(xcpu) (0x8 + (xcpu * IRQ_CPU_OFFSET))
-#define REG_IRQ_IL2SD(xcpu) (0xc + (xcpu * IRQ_CPU_OFFSET))
-
-/* all mask valid bits */
-#define REG_IRQ_IL2MD_ALL 0x03F181F0
-
-#define REG_IRQ_IL3MSD(xcpu) (0x10 + (xcpu * IRQ_CPU_OFFSET))
-#define REG_IRQ_IL3MCD(xcpu) (0x14 + (xcpu * IRQ_CPU_OFFSET))
-#define REG_IRQ_IL3MD(xcpu) (0x18 + (xcpu * IRQ_CPU_OFFSET))
-#define REG_IRQ_IL3SD(xcpu) (0x1c + (xcpu * IRQ_CPU_OFFSET))
-
-/* all mask valid bits */
-#define REG_IRQ_IL3MD_ALL 0x807F81FF
-
-#define REG_IRQ_IL4MSD(xcpu) (0x20 + (xcpu * IRQ_CPU_OFFSET))
-#define REG_IRQ_IL4MCD(xcpu) (0x24 + (xcpu * IRQ_CPU_OFFSET))
-#define REG_IRQ_IL4MD(xcpu) (0x28 + (xcpu * IRQ_CPU_OFFSET))
-#define REG_IRQ_IL4SD(xcpu) (0x2c + (xcpu * IRQ_CPU_OFFSET))
-
-/* all mask valid bits */
-#define REG_IRQ_IL4MD_ALL 0x807F81FF
-
-#define REG_IRQ_IL5MSD(xcpu) (0x30 + (xcpu * IRQ_CPU_OFFSET))
-#define REG_IRQ_IL5MCD(xcpu) (0x34 + (xcpu * IRQ_CPU_OFFSET))
-#define REG_IRQ_IL5MD(xcpu) (0x38 + (xcpu * IRQ_CPU_OFFSET))
-#define REG_IRQ_IL5SD(xcpu) (0x3c + (xcpu * IRQ_CPU_OFFSET))
-
-/* all mask valid bits */
-#define REG_IRQ_IL5MD_ALL 0xFFFFC0CF
-
-#define REG_IRQ_IL2RSD 0x100
-#define REG_IRQ_IL3RSD 0x104
-#define REG_IRQ_IL4RSD 0x108
-#define REG_IRQ_IL5RSD 0x10c
-
-#define REG_IRQ_LVL5_LP_GPDMA0_MASK (0xff << 16)
-#define REG_IRQ_LVL5_LP_GPDMA1_MASK (0xff << 24)
-
-/* DSP Shim Registers */
-#define SHIM_DSPWC 0x20 /* DSP Wall Clock */
-#define SHIM_DSPWCTCS 0x28 /* DSP Wall Clock Timer Control & Status */
-#define SHIM_DSPWCT0C 0x30 /* DSP Wall Clock Timer 0 Compare */
-#define SHIM_DSPWCT1C 0x38 /* DSP Wall Clock Timer 1 Compare */
-
-#define SHIM_DSPWCTCS_T1T (0x1 << 5) /* Timer 1 triggered */
-#define SHIM_DSPWCTCS_T0T (0x1 << 4) /* Timer 0 triggered */
-#define SHIM_DSPWCTCS_T1A (0x1 << 1) /* Timer 1 armed */
-#define SHIM_DSPWCTCS_T0A (0x1 << 0) /* Timer 0 armed */
-
-#define SHIM_CLKCTL 0x78
-#define SHIM_CLKSTS 0x7C
-
-#define SHIM_PWRCTL 0x90
-#define SHIM_PWRSTS 0x92
-#define SHIM_PWRCTL_TCPDSP0PG (0x1 << 0)
-
-/* LP GPDMA Force Dynamic Clock Gating bits, 0--enable */
-#define SHIM_CLKCTL_LPGPDMAFDCGB(x) (0x1 << (26 + x))
-#define SHIM_CLKCTL_TCPLCG(x) (0x1 << (16 + x))
-
-/* Core clock PLL divisor */
-#define SHIM_CLKCTL_DPCS_MASK(x) (0x1 << 2)
-
-/* Prevent Audio PLL Shutdown */
-#define SHIM_CLKCTL_TCPAPLLS (0x1 << 7)
-
-/* 0--from PLL, 1--from oscillator */
-#define SHIM_CLKCTL_HDCS (0x1 << 4)
-
-/* Oscillator select */
-#define SHIM_CLKCTL_HDOCS (0x1 << 2)
-
-/* HP memory clock PLL divisor */
-#define SHIM_CLKCTL_HPMPCS (0x1 << 0)
-
-#define GPDMA_CLKCTL(x) (0x78404 + x*0x100)
-#define GPDMA_FDCGB (0x1 << 0)
-
-#define L2LMCAP 0x71D00
-#define L2MPAT 0x71D04
-
-#define HSPGCTL0 0x71D10
-#define HSRMCTL0 0x71D14
-#define HSPGISTS0 0x71D18
-
-#define HSPGCTL1 0x71D20
-#define HSRMCTL1 0x71D24
-#define HSPGISTS1 0x71D28
-
-#define LSPGCTL 0x71D50
-#define LSRMCTL 0x71D54
-#define LSPGISTS 0x71D58
-
-#define SHIM_L2_MECS (SHIM_BASE + 0xd0)
-
-#define SHIM_LDOCTL 0xA4
-#define SHIM_HPMEM_POWER_ON (0x3 << 0)
-#define SHIM_LPMEM_POWER_BYPASS (0x1 << 0)
-
-#define DSP_INIT_LPGPDMA(x) (0x71A60 + (2*x))
-#define LPGPDMA_CTLOSEL_FLAG (1 << 15)
-#define LPGPDMA_CHOSEL_FLAG (0xFF)
-
-#define DSP_INIT_IOPO 0x71A68
-#define IOPO_DMIC_FLAG (1 << 0)
-#define IOPO_I2S_FLAG (7 << 8)
-
-#define DSP_INIT_GENO 0x71A6C
-#define GENO_MDIVOSEL (1 << 1)
-#define GENO_DIOPTOSEL (1 << 2)
-
-#define DSP_INIT_ALHO 0x71A70
-#define ALHO_ASO_FLAG (1 << 0)
-#define ALHO_CSO_FLAG (1 << 1)
-#define ALHO_CFO_FLAG (1 << 2)
-
-#define SHIM_SVCFG 0xF4
-#define SHIM_SVCFG_FORCE_L1_EXIT (0x1 << 1)
-
-/* host windows */
-#define DMWBA(x) (HOST_WIN_BASE(x) + 0x0)
-#define DMWLO(x) (HOST_WIN_BASE(x) + 0x4)
-
-#define DMWBA_ENABLE (1 << 0)
-#define DMWBA_READONLY (1 << 1)
-
-#ifndef ASSEMBLY
-
-static inline uint16_t shim_read16(uint16_t reg)
-{
- return *((volatile uint16_t*)(SHIM_BASE + reg));
-}
-
-static inline void shim_write16(uint16_t reg, uint16_t val)
-{
- *((volatile uint16_t*)(SHIM_BASE + reg)) = val;
-}
-
-static inline uint32_t shim_read(uint32_t reg)
-{
- return *((volatile uint32_t*)(SHIM_BASE + reg));
-}
-
-static inline void shim_write(uint32_t reg, uint32_t val)
-{
- *((volatile uint32_t*)(SHIM_BASE + reg)) = val;
-}
-
-static inline uint64_t shim_read64(uint32_t reg)
-{
- return *((volatile uint64_t*)(SHIM_BASE + reg));
-}
-
-static inline void shim_write64(uint32_t reg, uint64_t val)
-{
- *((volatile uint64_t*)(SHIM_BASE + reg)) = val;
-}
-
-static inline uint32_t sw_reg_read(uint32_t reg)
-{
- return *((volatile uint32_t*)((SRAM_SW_REG_BASE -
- SRAM_ALIAS_OFFSET) + reg));
-}
-
-static inline void sw_reg_write(uint32_t reg, uint32_t val)
-{
- *((volatile uint32_t*)((SRAM_SW_REG_BASE -
- SRAM_ALIAS_OFFSET) + reg)) = val;
-}
-
-static inline uint32_t mn_reg_read(uint32_t reg)
-{
- return *((volatile uint32_t*)(MN_BASE + reg));
-}
-
-static inline void mn_reg_write(uint32_t reg, uint32_t val)
-{
- *((volatile uint32_t*)(MN_BASE + reg)) = val;
-}
-
-static inline uint32_t irq_read(uint32_t reg)
-{
- return *((volatile uint32_t*)(IRQ_BASE + reg));
-}
-
-static inline void irq_write(uint32_t reg, uint32_t val)
-{
- *((volatile uint32_t*)(IRQ_BASE + reg)) = val;
-}
-
-static inline uint32_t ipc_read(uint32_t reg)
-{
- return *((volatile uint32_t*)(IPC_HOST_BASE + reg));
-}
-
-static inline void ipc_write(uint32_t reg, uint32_t val)
-{
- *((volatile uint32_t*)(IPC_HOST_BASE + reg)) = val;
-}
-
-static inline uint32_t idc_read(uint32_t reg, uint32_t core_id)
-{
- return *((volatile uint32_t*)(IPC_DSP_BASE(core_id) + reg));
-}
-
-static inline void idc_write(uint32_t reg, uint32_t core_id, uint32_t val)
-{
- *((volatile uint32_t*)(IPC_DSP_BASE(core_id) + reg)) = val;
-}
-#endif
-
-#endif
diff --git a/src/platform/cannonlake/include/platform/timer.h b/src/platform/cannonlake/include/platform/timer.h
deleted file mode 100644
index 02b7c6e..0000000
--- a/src/platform/cannonlake/include/platform/timer.h
+++ /dev/null
@@ -1,70 +0,0 @@
-/*
- * Copyright (c) 2017, Intel Corporation
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- * * Redistributions of source code must retain the above copyright
- * notice, this list of conditions and the following disclaimer.
- * * Redistributions in binary form must reproduce the above copyright
- * notice, this list of conditions and the following disclaimer in the
- * documentation and/or other materials provided with the distribution.
- * * Neither the name of the Intel Corporation nor the
- * names of its contributors may be used to endorse or promote products
- * derived from this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
- * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
- * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
- * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
- * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
- * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
- * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
- * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
- * POSSIBILITY OF SUCH DAMAGE.
- *
- * Author: Liam Girdwood <liam.r.girdwood@linux.intel.com>
- * Keyon Jie <yang.jie@linux.intel.com>
- * Rander Wang <rander.wang@intel.com>
- */
-
-#ifndef __PLATFORM_TIMER_H__
-#define __PLATFORM_TIMER_H__
-
-#include <stdint.h>
-#include <sof/timer.h>
-#include <platform/interrupt.h>
-
-#define TIMER_COUNT 5
-
-/* timer numbers must use associated IRQ number */
-#define TIMER0 IRQ_NUM_TIMER1
-#define TIMER1 IRQ_NUM_TIMER2
-#define TIMER2 IRQ_NUM_TIMER3
-#define TIMER3 IRQ_EXT_TSTAMP0_LVL2(0)
-#define TIMER4 IRQ_EXT_TSTAMP1_LVL2(0)
-
-struct comp_dev;
-struct sof_ipc_stream_posn;
-
-int platform_timer_set(struct timer *timer, uint64_t ticks);
-void platform_timer_clear(struct timer *timer);
-uint64_t platform_timer_get(struct timer *timer);
-void platform_timer_start(struct timer *timer);
-void platform_timer_stop(struct timer *timer);
-int platform_timer_register(struct timer *timer,
- void (*handler)(void *arg), void *arg);
-
-/* get timestamp for host stream DMA position */
-void platform_host_timestamp(struct comp_dev *host,
- struct sof_ipc_stream_posn *posn);
-
-/* get timestamp for DAI stream DMA position */
-void platform_dai_timestamp(struct comp_dev *dai,
- struct sof_ipc_stream_posn *posn);
-
-/* get current wallclock for componnent */
-void platform_dai_wallclock(struct comp_dev *dai, uint64_t *wallclock);
-#endif
diff --git a/src/platform/haswell/Makefile.am b/src/platform/haswell/Makefile.am
deleted file mode 100644
index 4f09c3a..0000000
--- a/src/platform/haswell/Makefile.am
+++ /dev/null
@@ -1,20 +0,0 @@
-SUBDIRS = include
-
-EXTRA_DIST = haswell.x.in
-
-noinst_LTLIBRARIES = libplatform.la
-
-libplatform_la_SOURCES = \
- platform.c \
- dai.c \
- dma.c \
- clk.c \
- timer.c \
- memory.c
-
-libplatform_la_CFLAGS = \
- $(AM_CFLAGS) \
- $(ARCH_CFLAGS) \
- $(ARCH_INCDIR) \
- $(PLATFORM_INCDIR) \
- $(SOF_INCDIR)
diff --git a/src/platform/haswell/broadwell.x.in b/src/platform/haswell/broadwell.x.in
deleted file mode 100755
index 9551eb6..0000000
--- a/src/platform/haswell/broadwell.x.in
+++ /dev/null
@@ -1,508 +0,0 @@
-/*
- * Linker Script for Broadwell.
- *
- * This script is run through the GNU C preprocessor to align the memory
- * offsets with headers.
- *
- * Use spaces for formatting as cpp ignore tab sizes.
- */
-
-#include <platform/memory.h>
-#include <xtensa/config/core-isa.h>
-
-OUTPUT_ARCH(xtensa)
-
-MEMORY
-{
- vector_reset_text :
- org = XCHAL_RESET_VECTOR0_PADDR,
- len = SOF_MEM_RESET_TEXT_SIZE
- vector_reset_lit :
- org = XCHAL_RESET_VECTOR0_PADDR + SOF_MEM_RESET_TEXT_SIZE,
- len = SOF_MEM_RESET_LIT_SIZE
- vector_base_text :
- org = XCHAL_VECBASE_RESET_PADDR,
- len = SOF_MEM_VECBASE_LIT_SIZE
- vector_int2_lit :
- org = XCHAL_INTLEVEL2_VECTOR_PADDR - SOF_MEM_VECT_LIT_SIZE,
- len = SOF_MEM_VECT_LIT_SIZE
- vector_int2_text :
- org = XCHAL_INTLEVEL2_VECTOR_PADDR,
- len = SOF_MEM_VECT_TEXT_SIZE
- vector_int3_lit :
- org = XCHAL_INTLEVEL3_VECTOR_PADDR - SOF_MEM_VECT_LIT_SIZE,
- len = SOF_MEM_VECT_LIT_SIZE
- vector_int3_text :
- org = XCHAL_INTLEVEL3_VECTOR_PADDR,
- len = SOF_MEM_VECT_TEXT_SIZE
- vector_int4_lit :
- org = XCHAL_INTLEVEL4_VECTOR_PADDR - SOF_MEM_VECT_LIT_SIZE,
- len = SOF_MEM_VECT_LIT_SIZE
- vector_int4_text :
- org = XCHAL_INTLEVEL4_VECTOR_PADDR,
- len = SOF_MEM_VECT_TEXT_SIZE
- vector_int5_lit :
- org = XCHAL_INTLEVEL5_VECTOR_PADDR - SOF_MEM_VECT_LIT_SIZE,
- len = SOF_MEM_VECT_LIT_SIZE
- vector_int5_text :
- org = XCHAL_INTLEVEL5_VECTOR_PADDR,
- len = SOF_MEM_VECT_TEXT_SIZE
- vector_int6_lit :
- org = XCHAL_INTLEVEL6_VECTOR_PADDR - SOF_MEM_VECT_LIT_SIZE,
- len = SOF_MEM_VECT_LIT_SIZE
- vector_int6_text :
- org = XCHAL_INTLEVEL6_VECTOR_PADDR,
- len = SOF_MEM_VECT_TEXT_SIZE
- vector_int7_lit :
- org = XCHAL_INTLEVEL7_VECTOR_PADDR - SOF_MEM_VECT_LIT_SIZE,
- len = SOF_MEM_VECT_LIT_SIZE
- vector_int7_text :
- org = XCHAL_INTLEVEL7_VECTOR_PADDR,
- len = SOF_MEM_VECT_TEXT_SIZE
- vector_kernel_lit :
- org = XCHAL_KERNEL_VECTOR_PADDR - SOF_MEM_VECT_LIT_SIZE,
- len = SOF_MEM_VECT_LIT_SIZE
- vector_kernel_text :
- org = XCHAL_KERNEL_VECTOR_PADDR,
- len = SOF_MEM_VECT_TEXT_SIZE
- vector_user_lit :
- org = XCHAL_USER_VECTOR_PADDR - SOF_MEM_VECT_LIT_SIZE,
- len = SOF_MEM_VECT_LIT_SIZE
- vector_user_text :
- org = XCHAL_USER_VECTOR_PADDR,
- len = SOF_MEM_VECT_TEXT_SIZE
- vector_double_lit :
- org = XCHAL_DOUBLEEXC_VECTOR_PADDR - SOF_MEM_VECT_LIT_SIZE,
- len = SOF_MEM_VECT_LIT_SIZE
- vector_double_text :
- org = XCHAL_DOUBLEEXC_VECTOR_PADDR,
- len = SOF_MEM_VECT_TEXT_SIZE
- sof_text_start :
- org = XCHAL_NMI_VECTOR_VADDR + SOF_MEM_VECT_SIZE,
- len = (IRAM_BASE + IRAM_SIZE) - (XCHAL_NMI_VECTOR_VADDR + SOF_MEM_VECT_SIZE)
- sof_data_ro :
- org = DRAM0_BASE,
- len = SOF_MEM_RO_SIZE
- sof_data :
- org = DRAM0_BASE + SOF_MEM_RO_SIZE,
- len = HEAP_SYSTEM_BASE - (DRAM0_BASE + SOF_MEM_RO_SIZE)
- system_heap :
- org = HEAP_SYSTEM_BASE,
- len = HEAP_SYSTEM_SIZE
- runtime_heap :
- org = HEAP_RUNTIME_BASE,
- len = HEAP_RUNTIME_SIZE
- buffer_heap :
- org = HEAP_BUFFER_BASE,
- len = HEAP_BUFFER_SIZE
- sof_stack :
- org = SOF_STACK_END,
- len = SOF_STACK_BASE - SOF_STACK_END
-}
-
-PHDRS
-{
- vector_reset_text_phdr PT_LOAD;
- vector_reset_lit_phdr PT_LOAD;
- vector_base_text_phdr PT_LOAD;
- vector_base_lit_phdr PT_LOAD;
- vector_int2_text_phdr PT_LOAD;
- vector_int2_lit_phdr PT_LOAD;
- vector_int3_text_phdr PT_LOAD;
- vector_int3_lit_phdr PT_LOAD;
- vector_int4_text_phdr PT_LOAD;
- vector_int4_lit_phdr PT_LOAD;
- vector_int5_text_phdr PT_LOAD;
- vector_int5_lit_phdr PT_LOAD;
- vector_int6_text_phdr PT_LOAD;
- vector_int6_lit_phdr PT_LOAD;
- vector_int7_text_phdr PT_LOAD;
- vector_int7_lit_phdr PT_LOAD;
- vector_kernel_text_phdr PT_LOAD;
- vector_kernel_lit_phdr PT_LOAD;
- vector_user_text_phdr PT_LOAD;
- vector_user_lit_phdr PT_LOAD;
- vector_double_text_phdr PT_LOAD;
- vector_double_lit_phdr PT_LOAD;
- sof_text_start_phdr PT_LOAD;
- sof_data_ro_phdr PT_LOAD;
- sof_data_phdr PT_LOAD;
- sof_data_bss_phdr PT_LOAD;
- system_heap_phdr PT_LOAD;
- runtime_heap_phdr PT_LOAD;
- buffer_heap_phdr PT_LOAD;
- sof_stack_phdr PT_LOAD;
-}
-
-/* Default entry point: */
-ENTRY(_ResetVector)
-_rom_store_table = 0;
-
-/* ABI0 does not use Window base */
-PROVIDE(_memmap_vecbase_reset = XCHAL_VECBASE_RESET_PADDR);
-
-/* Various memory-map dependent cache attribute settings: */
-_memmap_cacheattr_wb_base = 0x44024000;
-_memmap_cacheattr_wt_base = 0x11021000;
-_memmap_cacheattr_bp_base = 0x22022000;
-_memmap_cacheattr_unused_mask = 0x00F00FFF;
-_memmap_cacheattr_wb_trapnull = 0x4422422F;
-_memmap_cacheattr_wba_trapnull = 0x4422422F;
-_memmap_cacheattr_wbna_trapnull = 0x25222222;
-_memmap_cacheattr_wt_trapnull = 0x1122122F;
-_memmap_cacheattr_bp_trapnull = 0x2222222F;
-_memmap_cacheattr_wb_strict = 0x44F24FFF;
-_memmap_cacheattr_wt_strict = 0x11F21FFF;
-_memmap_cacheattr_bp_strict = 0x22F22FFF;
-_memmap_cacheattr_wb_allvalid = 0x44224222;
-_memmap_cacheattr_wt_allvalid = 0x11221222;
-_memmap_cacheattr_bp_allvalid = 0x22222222;
-PROVIDE(_memmap_cacheattr_reset = _memmap_cacheattr_wbna_trapnull);
-
-SECTIONS
-{
- .ResetVector.text : ALIGN(4)
- {
- _ResetVector_text_start = ABSOLUTE(.);
- KEEP (*(.ResetVector.text))
- _ResetVector_text_end = ABSOLUTE(.);
- } >vector_reset_text :vector_reset_text_phdr
-
- .ResetVector.literal : ALIGN(4)
- {
- _ResetVector_literal_start = ABSOLUTE(.);
- *(.ResetVector.literal)
- _ResetVector_literal_end = ABSOLUTE(.);
- } >vector_reset_lit :vector_reset_lit_phdr
-
- .WindowVectors.text : ALIGN(4)
- {
- _WindowVectors_text_start = ABSOLUTE(.);
- KEEP (*(.WindowVectors.text))
- _WindowVectors_text_end = ABSOLUTE(.);
- } >vector_base_text :vector_base_text_phdr
-
- .Level2InterruptVector.literal : ALIGN(4)
- {
- _Level2InterruptVector_literal_start = ABSOLUTE(.);
- *(.Level2InterruptVector.literal)
- _Level2InterruptVector_literal_end = ABSOLUTE(.);
- } >vector_int2_lit :vector_int2_lit_phdr
-
- .Level2InterruptVector.text : ALIGN(4)
- {
- _Level2InterruptVector_text_start = ABSOLUTE(.);
- KEEP (*(.Level2InterruptVector.text))
- _Level2InterruptVector_text_end = ABSOLUTE(.);
- } >vector_int2_text :vector_int2_text_phdr
-
- .Level3InterruptVector.literal : ALIGN(4)
- {
- _Level3InterruptVector_literal_start = ABSOLUTE(.);
- *(.Level3InterruptVector.literal)
- _Level3InterruptVector_literal_end = ABSOLUTE(.);
- } >vector_int3_lit :vector_int3_lit_phdr
-
- .Level3InterruptVector.text : ALIGN(4)
- {
- _Level3InterruptVector_text_start = ABSOLUTE(.);
- KEEP (*(.Level3InterruptVector.text))
- _Level3InterruptVector_text_end = ABSOLUTE(.);
- } >vector_int3_text :vector_int3_text_phdr
-
- .Level4InterruptVector.literal : ALIGN(4)
- {
- _Level4InterruptVector_literal_start = ABSOLUTE(.);
- *(.Level4InterruptVector.literal)
- _Level4InterruptVector_literal_end = ABSOLUTE(.);
- } >vector_int4_lit :vector_int4_lit_phdr
-
- .Level4InterruptVector.text : ALIGN(4)
- {
- _Level4InterruptVector_text_start = ABSOLUTE(.);
- KEEP (*(.Level4InterruptVector.text))
- _Level4InterruptVector_text_end = ABSOLUTE(.);
- } >vector_int4_text :vector_int4_text_phdr
-
- .Level5InterruptVector.literal : ALIGN(4)
- {
- _Level5InterruptVector_literal_start = ABSOLUTE(.);
- *(.Level5InterruptVector.literal)
- _Level5InterruptVector_literal_end = ABSOLUTE(.);
- } >vector_int5_lit :vector_int5_lit_phdr
-
- .Level5InterruptVector.text : ALIGN(4)
- {
- _Level5InterruptVector_text_start = ABSOLUTE(.);
- KEEP (*(.Level5InterruptVector.text))
- _Level5InterruptVector_text_end = ABSOLUTE(.);
- } >vector_int5_text :vector_int5_text_phdr
-
- .DebugExceptionVector.literal : ALIGN(4)
- {
- _DebugExceptionVector_literal_start = ABSOLUTE(.);
- *(.DebugExceptionVector.literal)
- _DebugExceptionVector_literal_end = ABSOLUTE(.);
- } >vector_int6_lit :vector_int6_lit_phdr
-
- .DebugExceptionVector.text : ALIGN(4)
- {
- _DebugExceptionVector_text_start = ABSOLUTE(.);
- KEEP (*(.DebugExceptionVector.text))
- _DebugExceptionVector_text_end = ABSOLUTE(.);
- } >vector_int6_text :vector_int6_text_phdr
-
- .NMIExceptionVector.literal : ALIGN(4)
- {
- _NMIExceptionVector_literal_start = ABSOLUTE(.);
- *(.NMIExceptionVector.literal)
- _NMIExceptionVector_literal_end = ABSOLUTE(.);
- } >vector_int7_lit :vector_int7_lit_phdr
-
- .NMIExceptionVector.text : ALIGN(4)
- {
- _NMIExceptionVector_text_start = ABSOLUTE(.);
- KEEP (*(.NMIExceptionVector.text))
- _NMIExceptionVector_text_end = ABSOLUTE(.);
- } >vector_int7_text :vector_int7_text_phdr
-
- .KernelExceptionVector.literal : ALIGN(4)
- {
- _KernelExceptionVector_literal_start = ABSOLUTE(.);
- *(.KernelExceptionVector.literal)
- _KernelExceptionVector_literal_end = ABSOLUTE(.);
- } >vector_kernel_lit :vector_kernel_lit_phdr
-
- .KernelExceptionVector.text : ALIGN(4)
- {
- _KernelExceptionVector_text_start = ABSOLUTE(.);
- KEEP (*(.KernelExceptionVector.text))
- _KernelExceptionVector_text_end = ABSOLUTE(.);
- } >vector_kernel_text :vector_kernel_text_phdr
-
- .UserExceptionVector.literal : ALIGN(4)
- {
- _UserExceptionVector_literal_start = ABSOLUTE(.);
- *(.UserExceptionVector.literal)
- _UserExceptionVector_literal_end = ABSOLUTE(.);
- } >vector_user_lit :vector_user_lit_phdr
-
- .UserExceptionVector.text : ALIGN(4)
- {
- _UserExceptionVector_text_start = ABSOLUTE(.);
- KEEP (*(.UserExceptionVector.text))
- _UserExceptionVector_text_end = ABSOLUTE(.);
- } >vector_user_text :vector_user_text_phdr
-
- .DoubleExceptionVector.literal : ALIGN(4)
- {
- _DoubleExceptionVector_literal_start = ABSOLUTE(.);
- *(.DoubleExceptionVector.literal)
- _DoubleExceptionVector_literal_end = ABSOLUTE(.);
- } >vector_double_lit :vector_double_lit_phdr
-
- .DoubleExceptionVector.text : ALIGN(4)
- {
- _DoubleExceptionVector_text_start = ABSOLUTE(.);
- KEEP (*(.DoubleExceptionVector.text))
- _DoubleExceptionVector_text_end = ABSOLUTE(.);
- } >vector_double_text :vector_double_text_phdr
-
- .text : ALIGN(4)
- {
- _stext = .;
- _text_start = ABSOLUTE(.);
- *(.entry.text)
- *(.init.literal)
- KEEP(*(.init))
- *(.literal .text .literal.* .text.* .stub .gnu.warning .gnu.linkonce.literal.* .gnu.linkonce.t.*.literal .gnu.linkonce.t.*)
- *(.fini.literal)
- KEEP(*(.fini))
- *(.gnu.version)
- _text_end = ABSOLUTE(.);
- _etext = .;
- } >sof_text_start :sof_text_start_phdr
-
- .reset.rodata : ALIGN(4)
- {
- _reset_rodata_start = ABSOLUTE(.);
- *(.reset.rodata)
- _reset_rodata_end = ABSOLUTE(.);
- } >sof_data_ro :sof_data_ro_phdr
-
- .rodata : ALIGN(4)
- {
- _rodata_start = ABSOLUTE(.);
- *(.rodata)
- *(.rodata.*)
- *(.gnu.linkonce.r.*)
- *(.rodata1)
- __XT_EXCEPTION_TABLE__ = ABSOLUTE(.);
- KEEP (*(.xt_except_table))
- KEEP (*(.gcc_except_table))
- *(.gnu.linkonce.e.*)
- *(.gnu.version_r)
- KEEP (*(.eh_frame))
- /* C++ constructor and destructor tables, properly ordered: */
- KEEP (*crtbegin.o(.ctors))
- KEEP (*(EXCLUDE_FILE (*crtend.o) .ctors))
- KEEP (*(SORT(.ctors.*)))
- KEEP (*(.ctors))
- KEEP (*crtbegin.o(.dtors))
- KEEP (*(EXCLUDE_FILE (*crtend.o) .dtors))
- KEEP (*(SORT(.dtors.*)))
- KEEP (*(.dtors))
- /* C++ exception handlers table: */
- __XT_EXCEPTION_DESCS__ = ABSOLUTE(.);
- *(.xt_except_desc)
- *(.gnu.linkonce.h.*)
- __XT_EXCEPTION_DESCS_END__ = ABSOLUTE(.);
- *(.xt_except_desc_end)
- *(.dynamic)
- *(.gnu.version_d)
- . = ALIGN(4); /* this table MUST be 4-byte aligned */
- _bss_table_start = ABSOLUTE(.);
- LONG(_bss_start)
- LONG(_bss_end)
- _bss_table_end = ABSOLUTE(.);
- _rodata_end = ABSOLUTE(.);
- } >sof_data :sof_data_phdr
-
- .data : ALIGN(4)
- {
- _data_start = ABSOLUTE(.);
- *(.data)
- *(.data.*)
- *(.gnu.linkonce.d.*)
- KEEP(*(.gnu.linkonce.d.*personality*))
- *(.data1)
- *(.sdata)
- *(.sdata.*)
- *(.gnu.linkonce.s.*)
- *(.sdata2)
- *(.sdata2.*)
- *(.gnu.linkonce.s2.*)
- KEEP(*(.jcr))
- _data_end = ABSOLUTE(.);
- } >sof_data :sof_data_phdr
-
- .lit4 : ALIGN(4)
- {
- _lit4_start = ABSOLUTE(.);
- *(*.lit4)
- *(.lit4.*)
- *(.gnu.linkonce.lit4.*)
- _lit4_end = ABSOLUTE(.);
- } >sof_data :sof_data_phdr
-
- .bss (NOLOAD) : ALIGN(8)
- {
- . = ALIGN (8);
- _bss_start = ABSOLUTE(.);
- *(.dynsbss)
- *(.sbss)
- *(.sbss.*)
- *(.gnu.linkonce.sb.*)
- *(.scommon)
- *(.sbss2)
- *(.sbss2.*)
- *(.gnu.linkonce.sb2.*)
- *(.dynbss)
- *(.bss)
- *(.bss.*)
- *(.gnu.linkonce.b.*)
- *(COMMON)
- . = ALIGN (8);
- _bss_end = ABSOLUTE(.);
- } >sof_data :sof_data_bss_phdr
-
- /* stack */
- _end = SOF_STACK_END;
- PROVIDE(end = SOF_STACK_END);
- _stack_sentry = SOF_STACK_END;
- __stack = SOF_STACK_BASE;
-
- .debug 0 : { *(.debug) }
- .line 0 : { *(.line) }
- .debug_srcinfo 0 : { *(.debug_srcinfo) }
- .debug_sfnames 0 : { *(.debug_sfnames) }
- .debug_aranges 0 : { *(.debug_aranges) }
- .debug_pubnames 0 : { *(.debug_pubnames) }
- .debug_info 0 : { *(.debug_info) }
- .debug_abbrev 0 : { *(.debug_abbrev) }
- .debug_line 0 : { *(.debug_line) }
- .debug_frame 0 : { *(.debug_frame) }
- .debug_str 0 : { *(.debug_str) }
- .debug_loc 0 : { *(.debug_loc) }
- .debug_macinfo 0 : { *(.debug_macinfo) }
- .debug_weaknames 0 : { *(.debug_weaknames) }
- .debug_funcnames 0 : { *(.debug_funcnames) }
- .debug_typenames 0 : { *(.debug_typenames) }
- .debug_varnames 0 : { *(.debug_varnames) }
-
- .xt.insn 0 :
- {
- KEEP (*(.xt.insn))
- KEEP (*(.gnu.linkonce.x.*))
- }
- .xt.prop 0 :
- {
- KEEP (*(.xt.prop))
- KEEP (*(.xt.prop.*))
- KEEP (*(.gnu.linkonce.prop.*))
- }
- .xt.lit 0 :
- {
- KEEP (*(.xt.lit))
- KEEP (*(.xt.lit.*))
- KEEP (*(.gnu.linkonce.p.*))
- }
- .xt.profile_range 0 :
- {
- KEEP (*(.xt.profile_range))
- KEEP (*(.gnu.linkonce.profile_range.*))
- }
- .xt.profile_ranges 0 :
- {
- KEEP (*(.xt.profile_ranges))
- KEEP (*(.gnu.linkonce.xt.profile_ranges.*))
- }
- .xt.profile_files 0 :
- {
- KEEP (*(.xt.profile_files))
- KEEP (*(.gnu.linkonce.xt.profile_files.*))
- }
-
- .system_heap (NOLOAD) : ALIGN(8)
- {
- . = ALIGN (32);
- _system_heap_start = ABSOLUTE(.);
- . = . + HEAP_SYSTEM_SIZE;
- _system_heap_end = ABSOLUTE(.);
- } >system_heap :system_heap_phdr
-
- .runtime_heap (NOLOAD) : ALIGN(8)
- {
- . = ALIGN (32);
- _runtime_heap_start = ABSOLUTE(.);
- . = . + HEAP_RUNTIME_SIZE;
- _runtime_heap_end = ABSOLUTE(.);
- } >runtime_heap :runtime_heap_phdr
-
- .buffer_heap (NOLOAD) : ALIGN(8)
- {
- . = ALIGN (32);
- _system_heap_start = ABSOLUTE(.);
- . = . + HEAP_BUFFER_SIZE;
- _system_heap_end = ABSOLUTE(.);
- } >buffer_heap :buffer_heap_phdr
-
- .sof_stack (NOLOAD) : ALIGN(8)
- {
- . = ALIGN (4096);
- _sof_stack_start = ABSOLUTE(.);
- . = . + SOF_STACK_SIZE;
- _sof_stack_end = ABSOLUTE(.);
- } >sof_stack :sof_stack_phdr
-}
-
diff --git a/src/platform/haswell/clk.c b/src/platform/haswell/clk.c
deleted file mode 100644
index 0482aab..0000000
--- a/src/platform/haswell/clk.c
+++ /dev/null
@@ -1,215 +0,0 @@
-/*
- * Copyright (c) 2016, Intel Corporation
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- * * Redistributions of source code must retain the above copyright
- * notice, this list of conditions and the following disclaimer.
- * * Redistributions in binary form must reproduce the above copyright
- * notice, this list of conditions and the following disclaimer in the
- * documentation and/or other materials provided with the distribution.
- * * Neither the name of the Intel Corporation nor the
- * names of its contributors may be used to endorse or promote products
- * derived from this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
- * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
- * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
- * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
- * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
- * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
- * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
- * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
- * POSSIBILITY OF SUCH DAMAGE.
- *
- * Author: Liam Girdwood <liam.r.girdwood@linux.intel.com>
- */
-
-#include <sof/clock.h>
-#include <sof/io.h>
-#include <sof/sof.h>
-#include <sof/list.h>
-#include <sof/alloc.h>
-#include <sof/notifier.h>
-#include <sof/lock.h>
-#include <platform/clk.h>
-#include <platform/shim.h>
-#include <platform/timer.h>
-#include <config.h>
-#include <stdint.h>
-#include <limits.h>
-
-#define NUM_CLOCKS 2
-
-struct clk_data {
- uint32_t freq;
- uint32_t ticks_per_usec;
- spinlock_t lock;
-};
-
-struct clk_pdata {
- struct clk_data clk[NUM_CLOCKS];
-};
-
-struct freq_table {
- uint32_t freq;
- uint32_t ticks_per_usec;
- uint32_t fabric;
- uint32_t enc;
-};
-
-static struct clk_pdata *clk_pdata;
-
-/* increasing frequency order */
-static const struct freq_table cpu_freq[] = {
- {32000000, 80, 32000000, 0x6},
- {80000000, 80, 80000000, 0x2},
- {160000000, 160, 80000000, 0x1},
- {320000000, 320, 160000000, 0x4},/* default */
- {320000000, 320, 80000000, 0x0},
- {160000000, 160, 160000000, 0x5},
-};
-
-static const struct freq_table ssp_freq[] = {
- {24000000, 24, 0, 0}, /* default */
-};
-
-#define CPU_DEFAULT_IDX 3
-#define SSP_DEFAULT_IDX 0
-
-static inline uint32_t get_freq(const struct freq_table *table, int size,
- unsigned int hz)
-{
- uint32_t i;
-
- /* find lowest available frequency that is >= requested Hz */
- for (i = 0; i < size; i++) {
- if (hz <= table[i].freq)
- return i;
- }
-
- /* not found, so return max frequency */
- return size - 1;
-}
-
-void clock_enable(int clock)
-{
- switch (clock) {
- case CLK_CPU:
- break;
- case CLK_SSP:
- default:
- break;
- }
-}
-
-void clock_disable(int clock)
-{
- switch (clock) {
- case CLK_CPU:
- break;
- case CLK_SSP:
- default:
- break;
- }
-}
-
-uint32_t clock_set_freq(int clock, uint32_t hz)
-{
- struct clock_notify_data notify_data;
- uint32_t idx;
- uint32_t flags;
-
- notify_data.old_freq = clk_pdata->clk[clock].freq;
- notify_data.old_ticks_per_usec = clk_pdata->clk[clock].ticks_per_usec;
-
- /* atomic context for chaining clocks */
- spin_lock_irq(&clk_pdata->clk[clock].lock, flags);
-
- switch (clock) {
- case CLK_CPU:
-
- /* get nearest frequency that is >= requested Hz */
- idx = get_freq(cpu_freq, ARRAY_SIZE(cpu_freq), hz);
- notify_data.freq = cpu_freq[idx].freq;
-
- /* tell anyone interested we are about to change CPU freq */
- notifier_event(NOTIFIER_ID_CPU_FREQ, CLOCK_NOTIFY_PRE,
- ¬ify_data);
-
- /* set CPU frequency request for CCU */
- io_reg_update_bits(SHIM_BASE + SHIM_CSR,
- SHIM_CSR_DCS_MASK,
- SHIM_CSR_DCS(cpu_freq[idx].enc));
-
- /* tell anyone interested we have now changed CPU freq */
- notifier_event(NOTIFIER_ID_CPU_FREQ, CLOCK_NOTIFY_POST,
- ¬ify_data);
- break;
- case CLK_SSP:
- default:
- break;
- }
-
- spin_unlock_irq(&clk_pdata->clk[clock].lock, flags);
- return clk_pdata->clk[clock].freq;
-}
-
-uint32_t clock_get_freq(int clock)
-{
- return clk_pdata->clk[clock].freq;
-}
-
-uint64_t clock_us_to_ticks(int clock, uint64_t us)
-{
- return clk_pdata->clk[clock].ticks_per_usec * us;
-}
-
-uint64_t clock_ms_to_ticks(int clock, uint64_t ms)
-{
- return clk_pdata->clk[clock].ticks_per_usec * ms * 1000;
-}
-
-uint64_t clock_time_elapsed(int clock, uint64_t previous, uint64_t *current)
-{
- uint64_t _current;
-
- // TODO: change timer APIs to clk APIs ??
- switch (clock) {
- case CLK_CPU:
- _current = arch_timer_get_system(NULL);
- break;
- case CLK_SSP:
- _current = platform_timer_get(platform_timer);
- break;
- default:
- return 0;
- }
-
- *current = _current;
- if (_current >= previous)
- return (_current - previous) /
- clk_pdata->clk[clock].ticks_per_usec;
- else
- return (_current + (ULONG_LONG_MAX - previous)) /
- clk_pdata->clk[clock].ticks_per_usec;
-}
-
-void init_platform_clocks(void)
-{
- clk_pdata = rzalloc(RZONE_SYS, SOF_MEM_CAPS_RAM, sizeof(*clk_pdata));
-
- spinlock_init(&clk_pdata->clk[0].lock);
- spinlock_init(&clk_pdata->clk[1].lock);
-
- /* set defaults */
- clk_pdata->clk[CLK_CPU].freq = cpu_freq[CPU_DEFAULT_IDX].freq;
- clk_pdata->clk[CLK_CPU].ticks_per_usec =
- cpu_freq[CPU_DEFAULT_IDX].ticks_per_usec;
- clk_pdata->clk[CLK_SSP].freq = ssp_freq[SSP_DEFAULT_IDX].freq;
- clk_pdata->clk[CLK_SSP].ticks_per_usec =
- ssp_freq[SSP_DEFAULT_IDX].ticks_per_usec;
-}
diff --git a/src/platform/haswell/dai.c b/src/platform/haswell/dai.c
deleted file mode 100644
index 91c05ff..0000000
--- a/src/platform/haswell/dai.c
+++ /dev/null
@@ -1,89 +0,0 @@
-/*
- * Copyright (c) 2016, Intel Corporation
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- * * Redistributions of source code must retain the above copyright
- * notice, this list of conditions and the following disclaimer.
- * * Redistributions in binary form must reproduce the above copyright
- * notice, this list of conditions and the following disclaimer in the
- * documentation and/or other materials provided with the distribution.
- * * Neither the name of the Intel Corporation nor the
- * names of its contributors may be used to endorse or promote products
- * derived from this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
- * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
- * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
- * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
- * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
- * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
- * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
- * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
- * POSSIBILITY OF SUCH DAMAGE.
- *
- * Author: Liam Girdwood <liam.r.girdwood@linux.intel.com>
- */
-
-#include <sof/sof.h>
-#include <sof/dai.h>
-#include <sof/ssp.h>
-#include <sof/stream.h>
-#include <sof/audio/component.h>
-#include <platform/memory.h>
-#include <platform/interrupt.h>
-#include <platform/dma.h>
-#include <stdint.h>
-#include <string.h>
-#include <config.h>
-
-static struct dai ssp[2] = {
-{
- .type = SOF_DAI_INTEL_SSP,
- .index = 0,
- .plat_data = {
- .base = SSP0_BASE,
- .irq = IRQ_NUM_EXT_SSP0,
- .fifo[SOF_IPC_STREAM_PLAYBACK] = {
- .offset = SSP0_BASE + SSDR,
- .handshake = DMA_HANDSHAKE_SSP0_TX,
- },
- .fifo[SOF_IPC_STREAM_CAPTURE] = {
- .offset = SSP0_BASE + SSDR,
- .handshake = DMA_HANDSHAKE_SSP0_RX,
- }
- },
- .ops = &ssp_ops,
-},
-{
- .type = SOF_DAI_INTEL_SSP,
- .index = 1,
- .plat_data = {
- .base = SSP1_BASE,
- .irq = IRQ_NUM_EXT_SSP1,
- .fifo[SOF_IPC_STREAM_PLAYBACK] = {
- .offset = SSP1_BASE + SSDR,
- .handshake = DMA_HANDSHAKE_SSP1_TX,
- },
- .fifo[SOF_IPC_STREAM_CAPTURE] = {
- .offset = SSP1_BASE + SSDR,
- .handshake = DMA_HANDSHAKE_SSP1_RX,
- }
- },
- .ops = &ssp_ops,
-}};
-
-struct dai *dai_get(uint32_t type, uint32_t index)
-{
- int i;
-
- for (i = 0; i < ARRAY_SIZE(ssp); i++) {
- if (ssp[i].type == type && ssp[i].index == index)
- return &ssp[i];
- }
-
- return NULL;
-}
diff --git a/src/platform/haswell/dma.c b/src/platform/haswell/dma.c
deleted file mode 100644
index 8b4d713..0000000
--- a/src/platform/haswell/dma.c
+++ /dev/null
@@ -1,159 +0,0 @@
-/*
- * Copyright (c) 2016, Intel Corporation
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- * * Redistributions of source code must retain the above copyright
- * notice, this list of conditions and the following disclaimer.
- * * Redistributions in binary form must reproduce the above copyright
- * notice, this list of conditions and the following disclaimer in the
- * documentation and/or other materials provided with the distribution.
- * * Neither the name of the Intel Corporation nor the
- * names of its contributors may be used to endorse or promote products
- * derived from this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
- * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
- * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
- * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
- * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
- * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
- * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
- * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
- * POSSIBILITY OF SUCH DAMAGE.
- *
- * Author: Liam Girdwood <liam.r.girdwood@linux.intel.com>
- */
-
-#include <sof/dma.h>
-#include <sof/dw-dma.h>
-#include <platform/memory.h>
-#include <platform/interrupt.h>
-#include <platform/dma.h>
-#include <stdint.h>
-#include <string.h>
-
-static struct dw_drv_plat_data dmac0 = {
- .chan[0] = {
- .class = 6,
- .weight = 0,
- },
- .chan[1] = {
- .class = 6,
- .weight = 0,
- },
- .chan[2] = {
- .class = 6,
- .weight = 0,
- },
- .chan[3] = {
- .class = 6,
- .weight = 0,
- },
- .chan[4] = {
- .class = 6,
- .weight = 0,
- },
- .chan[5] = {
- .class = 6,
- .weight = 0,
- },
- .chan[6] = {
- .class = 6,
- .weight = 0,
- },
- .chan[7] = {
- .class = 6,
- .weight = 0,
- },
-};
-
-static struct dw_drv_plat_data dmac1 = {
- .chan[0] = {
- .class = 7,
- .weight = 0,
- },
- .chan[1] = {
- .class = 7,
- .weight = 0,
- },
- .chan[2] = {
- .class = 7,
- .weight = 0,
- },
- .chan[3] = {
- .class = 7,
- .weight = 0,
- },
- .chan[4] = {
- .class = 7,
- .weight = 0,
- },
- .chan[5] = {
- .class = 7,
- .weight = 0,
- },
- .chan[6] = {
- .class = 7,
- .weight = 0,
- },
- .chan[7] = {
- .class = 7,
- .weight = 0,
- },
-};
-
-struct dma dma[PLATFORM_NUM_DMACS] = {
-{
- .plat_data = {
- .base = DMA0_BASE,
- .dir = DMA_DIR_MEM_TO_MEM,
- .caps = DMA_CAP_GP_HP | DMA_CAP_GP_LP,
- .devs = DMA_DEV_SSP | DMA_DEV_DMIC | DMA_DEV_HOST,
- .irq = IRQ_NUM_EXT_DMAC0,
- .drv_plat_data = &dmac0,
- },
- .ops = &dw_dma_ops,
-},
-{
- .plat_data = {
- .base = DMA1_BASE,
- .dir = DMA_DIR_MEM_TO_MEM | DMA_DIR_MEM_TO_DEV |
- DMA_DIR_DEV_TO_MEM | DMA_DIR_DEV_TO_DEV |
- DMA_DIR_HMEM_TO_LMEM | DMA_DIR_LMEM_TO_HMEM,
- .caps = DMA_CAP_GP_HP | DMA_CAP_GP_LP,
- .devs = DMA_DEV_SSP | DMA_DEV_DMIC | DMA_DEV_HOST,
- .irq = IRQ_NUM_EXT_DMAC1,
- .drv_plat_data = &dmac1,
- },
- .ops = &dw_dma_ops,
-},};
-
-/* Initialize all platform DMAC's */
-int dmac_init(void)
-{
- int i, ret;
-
- for (i = 0; i < ARRAY_SIZE(dma); i++) {
- ret = dma_probe(&dma[i]);
- if (ret < 0) {
-
- /* trace failed DMAC ID */
- trace_error(TRACE_CLASS_DMA, "edi");
- trace_error_value(dma[i].plat_data.id);
- return ret;
- }
- }
-
- /* clear the masks for dsp of the dmacs */
- io_reg_update_bits(SHIM_BASE + SHIM_IMRD,
- SHIM_IMRD_DMAC0, 0);
-
- io_reg_update_bits(SHIM_BASE + SHIM_IMRD,
- SHIM_IMRD_DMAC1, 0);
-
- return 0;
-}
diff --git a/src/platform/haswell/haswell.x.in b/src/platform/haswell/haswell.x.in
deleted file mode 100755
index 8733bfc..0000000
--- a/src/platform/haswell/haswell.x.in
+++ /dev/null
@@ -1,508 +0,0 @@
-/*
- * Linker Script for Baytrail.
- *
- * This script is run through the GNU C preprocessor to align the memory
- * offsets with headers.
- *
- * Use spaces for formatting as cpp ignore tab sizes.
- */
-
-#include <platform/memory.h>
-#include <xtensa/config/core-isa.h>
-
-OUTPUT_ARCH(xtensa)
-
-MEMORY
-{
- vector_reset_text :
- org = XCHAL_RESET_VECTOR0_PADDR,
- len = SOF_MEM_RESET_TEXT_SIZE
- vector_reset_lit :
- org = XCHAL_RESET_VECTOR0_PADDR + SOF_MEM_RESET_TEXT_SIZE,
- len = SOF_MEM_RESET_LIT_SIZE
- vector_base_text :
- org = XCHAL_VECBASE_RESET_PADDR,
- len = SOF_MEM_VECBASE_LIT_SIZE
- vector_int2_lit :
- org = XCHAL_INTLEVEL2_VECTOR_PADDR - SOF_MEM_VECT_LIT_SIZE,
- len = SOF_MEM_VECT_LIT_SIZE
- vector_int2_text :
- org = XCHAL_INTLEVEL2_VECTOR_PADDR,
- len = SOF_MEM_VECT_TEXT_SIZE
- vector_int3_lit :
- org = XCHAL_INTLEVEL3_VECTOR_PADDR - SOF_MEM_VECT_LIT_SIZE,
- len = SOF_MEM_VECT_LIT_SIZE
- vector_int3_text :
- org = XCHAL_INTLEVEL3_VECTOR_PADDR,
- len = SOF_MEM_VECT_TEXT_SIZE
- vector_int4_lit :
- org = XCHAL_INTLEVEL4_VECTOR_PADDR - SOF_MEM_VECT_LIT_SIZE,
- len = SOF_MEM_VECT_LIT_SIZE
- vector_int4_text :
- org = XCHAL_INTLEVEL4_VECTOR_PADDR,
- len = SOF_MEM_VECT_TEXT_SIZE
- vector_int5_lit :
- org = XCHAL_INTLEVEL5_VECTOR_PADDR - SOF_MEM_VECT_LIT_SIZE,
- len = SOF_MEM_VECT_LIT_SIZE
- vector_int5_text :
- org = XCHAL_INTLEVEL5_VECTOR_PADDR,
- len = SOF_MEM_VECT_TEXT_SIZE
- vector_int6_lit :
- org = XCHAL_INTLEVEL6_VECTOR_PADDR - SOF_MEM_VECT_LIT_SIZE,
- len = SOF_MEM_VECT_LIT_SIZE
- vector_int6_text :
- org = XCHAL_INTLEVEL6_VECTOR_PADDR,
- len = SOF_MEM_VECT_TEXT_SIZE
- vector_int7_lit :
- org = XCHAL_INTLEVEL7_VECTOR_PADDR - SOF_MEM_VECT_LIT_SIZE,
- len = SOF_MEM_VECT_LIT_SIZE
- vector_int7_text :
- org = XCHAL_INTLEVEL7_VECTOR_PADDR,
- len = SOF_MEM_VECT_TEXT_SIZE
- vector_kernel_lit :
- org = XCHAL_KERNEL_VECTOR_PADDR - SOF_MEM_VECT_LIT_SIZE,
- len = SOF_MEM_VECT_LIT_SIZE
- vector_kernel_text :
- org = XCHAL_KERNEL_VECTOR_PADDR,
- len = SOF_MEM_VECT_TEXT_SIZE
- vector_user_lit :
- org = XCHAL_USER_VECTOR_PADDR - SOF_MEM_VECT_LIT_SIZE,
- len = SOF_MEM_VECT_LIT_SIZE
- vector_user_text :
- org = XCHAL_USER_VECTOR_PADDR,
- len = SOF_MEM_VECT_TEXT_SIZE
- vector_double_lit :
- org = XCHAL_DOUBLEEXC_VECTOR_PADDR - SOF_MEM_VECT_LIT_SIZE,
- len = SOF_MEM_VECT_LIT_SIZE
- vector_double_text :
- org = XCHAL_DOUBLEEXC_VECTOR_PADDR,
- len = SOF_MEM_VECT_TEXT_SIZE
- sof_text_start :
- org = XCHAL_NMI_VECTOR_VADDR + SOF_MEM_VECT_SIZE,
- len = (IRAM_BASE + IRAM_SIZE) - (XCHAL_NMI_VECTOR_VADDR + SOF_MEM_VECT_SIZE)
- sof_data_ro :
- org = DRAM0_BASE,
- len = SOF_MEM_RO_SIZE
- sof_data :
- org = DRAM0_BASE + SOF_MEM_RO_SIZE,
- len = HEAP_SYSTEM_BASE - (DRAM0_BASE + SOF_MEM_RO_SIZE)
- system_heap :
- org = HEAP_SYSTEM_BASE,
- len = HEAP_SYSTEM_SIZE
- runtime_heap :
- org = HEAP_RUNTIME_BASE,
- len = HEAP_RUNTIME_SIZE
- buffer_heap :
- org = HEAP_BUFFER_BASE,
- len = HEAP_BUFFER_SIZE
- sof_stack :
- org = SOF_STACK_END,
- len = SOF_STACK_BASE - SOF_STACK_END
-}
-
-PHDRS
-{
- vector_reset_text_phdr PT_LOAD;
- vector_reset_lit_phdr PT_LOAD;
- vector_base_text_phdr PT_LOAD;
- vector_base_lit_phdr PT_LOAD;
- vector_int2_text_phdr PT_LOAD;
- vector_int2_lit_phdr PT_LOAD;
- vector_int3_text_phdr PT_LOAD;
- vector_int3_lit_phdr PT_LOAD;
- vector_int4_text_phdr PT_LOAD;
- vector_int4_lit_phdr PT_LOAD;
- vector_int5_text_phdr PT_LOAD;
- vector_int5_lit_phdr PT_LOAD;
- vector_int6_text_phdr PT_LOAD;
- vector_int6_lit_phdr PT_LOAD;
- vector_int7_text_phdr PT_LOAD;
- vector_int7_lit_phdr PT_LOAD;
- vector_kernel_text_phdr PT_LOAD;
- vector_kernel_lit_phdr PT_LOAD;
- vector_user_text_phdr PT_LOAD;
- vector_user_lit_phdr PT_LOAD;
- vector_double_text_phdr PT_LOAD;
- vector_double_lit_phdr PT_LOAD;
- sof_text_start_phdr PT_LOAD;
- sof_data_ro_phdr PT_LOAD;
- sof_data_phdr PT_LOAD;
- sof_data_bss_phdr PT_LOAD;
- system_heap_phdr PT_LOAD;
- runtime_heap_phdr PT_LOAD;
- buffer_heap_phdr PT_LOAD;
- sof_stack_phdr PT_LOAD;
-}
-
-/* Default entry point: */
-ENTRY(_ResetVector)
-_rom_store_table = 0;
-
-/* ABI0 does not use Window base */
-PROVIDE(_memmap_vecbase_reset = XCHAL_VECBASE_RESET_PADDR);
-
-/* Various memory-map dependent cache attribute settings: */
-_memmap_cacheattr_wb_base = 0x44024000;
-_memmap_cacheattr_wt_base = 0x11021000;
-_memmap_cacheattr_bp_base = 0x22022000;
-_memmap_cacheattr_unused_mask = 0x00F00FFF;
-_memmap_cacheattr_wb_trapnull = 0x4422422F;
-_memmap_cacheattr_wba_trapnull = 0x4422422F;
-_memmap_cacheattr_wbna_trapnull = 0x25222222;
-_memmap_cacheattr_wt_trapnull = 0x1122122F;
-_memmap_cacheattr_bp_trapnull = 0x2222222F;
-_memmap_cacheattr_wb_strict = 0x44F24FFF;
-_memmap_cacheattr_wt_strict = 0x11F21FFF;
-_memmap_cacheattr_bp_strict = 0x22F22FFF;
-_memmap_cacheattr_wb_allvalid = 0x44224222;
-_memmap_cacheattr_wt_allvalid = 0x11221222;
-_memmap_cacheattr_bp_allvalid = 0x22222222;
-PROVIDE(_memmap_cacheattr_reset = _memmap_cacheattr_wbna_trapnull);
-
-SECTIONS
-{
- .ResetVector.text : ALIGN(4)
- {
- _ResetVector_text_start = ABSOLUTE(.);
- KEEP (*(.ResetVector.text))
- _ResetVector_text_end = ABSOLUTE(.);
- } >vector_reset_text :vector_reset_text_phdr
-
- .ResetVector.literal : ALIGN(4)
- {
- _ResetVector_literal_start = ABSOLUTE(.);
- *(.ResetVector.literal)
- _ResetVector_literal_end = ABSOLUTE(.);
- } >vector_reset_lit :vector_reset_lit_phdr
-
- .WindowVectors.text : ALIGN(4)
- {
- _WindowVectors_text_start = ABSOLUTE(.);
- KEEP (*(.WindowVectors.text))
- _WindowVectors_text_end = ABSOLUTE(.);
- } >vector_base_text :vector_base_text_phdr
-
- .Level2InterruptVector.literal : ALIGN(4)
- {
- _Level2InterruptVector_literal_start = ABSOLUTE(.);
- *(.Level2InterruptVector.literal)
- _Level2InterruptVector_literal_end = ABSOLUTE(.);
- } >vector_int2_lit :vector_int2_lit_phdr
-
- .Level2InterruptVector.text : ALIGN(4)
- {
- _Level2InterruptVector_text_start = ABSOLUTE(.);
- KEEP (*(.Level2InterruptVector.text))
- _Level2InterruptVector_text_end = ABSOLUTE(.);
- } >vector_int2_text :vector_int2_text_phdr
-
- .Level3InterruptVector.literal : ALIGN(4)
- {
- _Level3InterruptVector_literal_start = ABSOLUTE(.);
- *(.Level3InterruptVector.literal)
- _Level3InterruptVector_literal_end = ABSOLUTE(.);
- } >vector_int3_lit :vector_int3_lit_phdr
-
- .Level3InterruptVector.text : ALIGN(4)
- {
- _Level3InterruptVector_text_start = ABSOLUTE(.);
- KEEP (*(.Level3InterruptVector.text))
- _Level3InterruptVector_text_end = ABSOLUTE(.);
- } >vector_int3_text :vector_int3_text_phdr
-
- .Level4InterruptVector.literal : ALIGN(4)
- {
- _Level4InterruptVector_literal_start = ABSOLUTE(.);
- *(.Level4InterruptVector.literal)
- _Level4InterruptVector_literal_end = ABSOLUTE(.);
- } >vector_int4_lit :vector_int4_lit_phdr
-
- .Level4InterruptVector.text : ALIGN(4)
- {
- _Level4InterruptVector_text_start = ABSOLUTE(.);
- KEEP (*(.Level4InterruptVector.text))
- _Level4InterruptVector_text_end = ABSOLUTE(.);
- } >vector_int4_text :vector_int4_text_phdr
-
- .Level5InterruptVector.literal : ALIGN(4)
- {
- _Level5InterruptVector_literal_start = ABSOLUTE(.);
- *(.Level5InterruptVector.literal)
- _Level5InterruptVector_literal_end = ABSOLUTE(.);
- } >vector_int5_lit :vector_int5_lit_phdr
-
- .Level5InterruptVector.text : ALIGN(4)
- {
- _Level5InterruptVector_text_start = ABSOLUTE(.);
- KEEP (*(.Level5InterruptVector.text))
- _Level5InterruptVector_text_end = ABSOLUTE(.);
- } >vector_int5_text :vector_int5_text_phdr
-
- .DebugExceptionVector.literal : ALIGN(4)
- {
- _DebugExceptionVector_literal_start = ABSOLUTE(.);
- *(.DebugExceptionVector.literal)
- _DebugExceptionVector_literal_end = ABSOLUTE(.);
- } >vector_int6_lit :vector_int6_lit_phdr
-
- .DebugExceptionVector.text : ALIGN(4)
- {
- _DebugExceptionVector_text_start = ABSOLUTE(.);
- KEEP (*(.DebugExceptionVector.text))
- _DebugExceptionVector_text_end = ABSOLUTE(.);
- } >vector_int6_text :vector_int6_text_phdr
-
- .NMIExceptionVector.literal : ALIGN(4)
- {
- _NMIExceptionVector_literal_start = ABSOLUTE(.);
- *(.NMIExceptionVector.literal)
- _NMIExceptionVector_literal_end = ABSOLUTE(.);
- } >vector_int7_lit :vector_int7_lit_phdr
-
- .NMIExceptionVector.text : ALIGN(4)
- {
- _NMIExceptionVector_text_start = ABSOLUTE(.);
- KEEP (*(.NMIExceptionVector.text))
- _NMIExceptionVector_text_end = ABSOLUTE(.);
- } >vector_int7_text :vector_int7_text_phdr
-
- .KernelExceptionVector.literal : ALIGN(4)
- {
- _KernelExceptionVector_literal_start = ABSOLUTE(.);
- *(.KernelExceptionVector.literal)
- _KernelExceptionVector_literal_end = ABSOLUTE(.);
- } >vector_kernel_lit :vector_kernel_lit_phdr
-
- .KernelExceptionVector.text : ALIGN(4)
- {
- _KernelExceptionVector_text_start = ABSOLUTE(.);
- KEEP (*(.KernelExceptionVector.text))
- _KernelExceptionVector_text_end = ABSOLUTE(.);
- } >vector_kernel_text :vector_kernel_text_phdr
-
- .UserExceptionVector.literal : ALIGN(4)
- {
- _UserExceptionVector_literal_start = ABSOLUTE(.);
- *(.UserExceptionVector.literal)
- _UserExceptionVector_literal_end = ABSOLUTE(.);
- } >vector_user_lit :vector_user_lit_phdr
-
- .UserExceptionVector.text : ALIGN(4)
- {
- _UserExceptionVector_text_start = ABSOLUTE(.);
- KEEP (*(.UserExceptionVector.text))
- _UserExceptionVector_text_end = ABSOLUTE(.);
- } >vector_user_text :vector_user_text_phdr
-
- .DoubleExceptionVector.literal : ALIGN(4)
- {
- _DoubleExceptionVector_literal_start = ABSOLUTE(.);
- *(.DoubleExceptionVector.literal)
- _DoubleExceptionVector_literal_end = ABSOLUTE(.);
- } >vector_double_lit :vector_double_lit_phdr
-
- .DoubleExceptionVector.text : ALIGN(4)
- {
- _DoubleExceptionVector_text_start = ABSOLUTE(.);
- KEEP (*(.DoubleExceptionVector.text))
- _DoubleExceptionVector_text_end = ABSOLUTE(.);
- } >vector_double_text :vector_double_text_phdr
-
- .text : ALIGN(4)
- {
- _stext = .;
- _text_start = ABSOLUTE(.);
- *(.entry.text)
- *(.init.literal)
- KEEP(*(.init))
- *(.literal .text .literal.* .text.* .stub .gnu.warning .gnu.linkonce.literal.* .gnu.linkonce.t.*.literal .gnu.linkonce.t.*)
- *(.fini.literal)
- KEEP(*(.fini))
- *(.gnu.version)
- _text_end = ABSOLUTE(.);
- _etext = .;
- } >sof_text_start :sof_text_start_phdr
-
- .reset.rodata : ALIGN(4)
- {
- _reset_rodata_start = ABSOLUTE(.);
- *(.reset.rodata)
- _reset_rodata_end = ABSOLUTE(.);
- } >sof_data_ro :sof_data_ro_phdr
-
- .rodata : ALIGN(4)
- {
- _rodata_start = ABSOLUTE(.);
- *(.rodata)
- *(.rodata.*)
- *(.gnu.linkonce.r.*)
- *(.rodata1)
- __XT_EXCEPTION_TABLE__ = ABSOLUTE(.);
- KEEP (*(.xt_except_table))
- KEEP (*(.gcc_except_table))
- *(.gnu.linkonce.e.*)
- *(.gnu.version_r)
- KEEP (*(.eh_frame))
- /* C++ constructor and destructor tables, properly ordered: */
- KEEP (*crtbegin.o(.ctors))
- KEEP (*(EXCLUDE_FILE (*crtend.o) .ctors))
- KEEP (*(SORT(.ctors.*)))
- KEEP (*(.ctors))
- KEEP (*crtbegin.o(.dtors))
- KEEP (*(EXCLUDE_FILE (*crtend.o) .dtors))
- KEEP (*(SORT(.dtors.*)))
- KEEP (*(.dtors))
- /* C++ exception handlers table: */
- __XT_EXCEPTION_DESCS__ = ABSOLUTE(.);
- *(.xt_except_desc)
- *(.gnu.linkonce.h.*)
- __XT_EXCEPTION_DESCS_END__ = ABSOLUTE(.);
- *(.xt_except_desc_end)
- *(.dynamic)
- *(.gnu.version_d)
- . = ALIGN(4); /* this table MUST be 4-byte aligned */
- _bss_table_start = ABSOLUTE(.);
- LONG(_bss_start)
- LONG(_bss_end)
- _bss_table_end = ABSOLUTE(.);
- _rodata_end = ABSOLUTE(.);
- } >sof_data :sof_data_phdr
-
- .data : ALIGN(4)
- {
- _data_start = ABSOLUTE(.);
- *(.data)
- *(.data.*)
- *(.gnu.linkonce.d.*)
- KEEP(*(.gnu.linkonce.d.*personality*))
- *(.data1)
- *(.sdata)
- *(.sdata.*)
- *(.gnu.linkonce.s.*)
- *(.sdata2)
- *(.sdata2.*)
- *(.gnu.linkonce.s2.*)
- KEEP(*(.jcr))
- _data_end = ABSOLUTE(.);
- } >sof_data :sof_data_phdr
-
- .lit4 : ALIGN(4)
- {
- _lit4_start = ABSOLUTE(.);
- *(*.lit4)
- *(.lit4.*)
- *(.gnu.linkonce.lit4.*)
- _lit4_end = ABSOLUTE(.);
- } >sof_data :sof_data_phdr
-
- .bss (NOLOAD) : ALIGN(8)
- {
- . = ALIGN (8);
- _bss_start = ABSOLUTE(.);
- *(.dynsbss)
- *(.sbss)
- *(.sbss.*)
- *(.gnu.linkonce.sb.*)
- *(.scommon)
- *(.sbss2)
- *(.sbss2.*)
- *(.gnu.linkonce.sb2.*)
- *(.dynbss)
- *(.bss)
- *(.bss.*)
- *(.gnu.linkonce.b.*)
- *(COMMON)
- . = ALIGN (8);
- _bss_end = ABSOLUTE(.);
- } >sof_data :sof_data_bss_phdr
-
- /* stack */
- _end = SOF_STACK_END;
- PROVIDE(end = SOF_STACK_END);
- _stack_sentry = SOF_STACK_END;
- __stack = SOF_STACK_BASE;
-
- .debug 0 : { *(.debug) }
- .line 0 : { *(.line) }
- .debug_srcinfo 0 : { *(.debug_srcinfo) }
- .debug_sfnames 0 : { *(.debug_sfnames) }
- .debug_aranges 0 : { *(.debug_aranges) }
- .debug_pubnames 0 : { *(.debug_pubnames) }
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- .debug_frame 0 : { *(.debug_frame) }
- .debug_str 0 : { *(.debug_str) }
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- .debug_weaknames 0 : { *(.debug_weaknames) }
- .debug_funcnames 0 : { *(.debug_funcnames) }
- .debug_typenames 0 : { *(.debug_typenames) }
- .debug_varnames 0 : { *(.debug_varnames) }
-
- .xt.insn 0 :
- {
- KEEP (*(.xt.insn))
- KEEP (*(.gnu.linkonce.x.*))
- }
- .xt.prop 0 :
- {
- KEEP (*(.xt.prop))
- KEEP (*(.xt.prop.*))
- KEEP (*(.gnu.linkonce.prop.*))
- }
- .xt.lit 0 :
- {
- KEEP (*(.xt.lit))
- KEEP (*(.xt.lit.*))
- KEEP (*(.gnu.linkonce.p.*))
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- .xt.profile_range 0 :
- {
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- KEEP (*(.gnu.linkonce.profile_range.*))
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- .xt.profile_ranges 0 :
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- KEEP (*(.xt.profile_ranges))
- KEEP (*(.gnu.linkonce.xt.profile_ranges.*))
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- .xt.profile_files 0 :
- {
- KEEP (*(.xt.profile_files))
- KEEP (*(.gnu.linkonce.xt.profile_files.*))
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-
- .system_heap (NOLOAD) : ALIGN(8)
- {
- . = ALIGN (32);
- _system_heap_start = ABSOLUTE(.);
- . = . + HEAP_SYSTEM_SIZE;
- _system_heap_end = ABSOLUTE(.);
- } >system_heap :system_heap_phdr
-
- .runtime_heap (NOLOAD) : ALIGN(8)
- {
- . = ALIGN (32);
- _runtime_heap_start = ABSOLUTE(.);
- . = . + HEAP_RUNTIME_SIZE;
- _runtime_heap_end = ABSOLUTE(.);
- } >runtime_heap :runtime_heap_phdr
-
- .buffer_heap (NOLOAD) : ALIGN(8)
- {
- . = ALIGN (32);
- _system_heap_start = ABSOLUTE(.);
- . = . + HEAP_BUFFER_SIZE;
- _system_heap_end = ABSOLUTE(.);
- } >buffer_heap :buffer_heap_phdr
-
- .sof_stack (NOLOAD) : ALIGN(8)
- {
- . = ALIGN (4096);
- _sof_stack_start = ABSOLUTE(.);
- . = . + SOF_STACK_SIZE;
- _sof_stack_end = ABSOLUTE(.);
- } >sof_stack :sof_stack_phdr
-}
-
diff --git a/src/platform/haswell/include/Makefile.am b/src/platform/haswell/include/Makefile.am
deleted file mode 100644
index c5113a4..0000000
--- a/src/platform/haswell/include/Makefile.am
+++ /dev/null
@@ -1 +0,0 @@
-SUBDIRS = arch platform
diff --git a/src/platform/haswell/include/arch/Makefile.am b/src/platform/haswell/include/arch/Makefile.am
deleted file mode 100644
index 63616bf..0000000
--- a/src/platform/haswell/include/arch/Makefile.am
+++ /dev/null
@@ -1 +0,0 @@
-SUBDIRS = xtensa
diff --git a/src/platform/haswell/include/arch/xtensa/Makefile.am b/src/platform/haswell/include/arch/xtensa/Makefile.am
deleted file mode 100644
index a85a5bb..0000000
--- a/src/platform/haswell/include/arch/xtensa/Makefile.am
+++ /dev/null
@@ -1 +0,0 @@
-SUBDIRS = config
diff --git a/src/platform/haswell/include/arch/xtensa/config/Makefile.am b/src/platform/haswell/include/arch/xtensa/config/Makefile.am
deleted file mode 100644
index 2404f99..0000000
--- a/src/platform/haswell/include/arch/xtensa/config/Makefile.am
+++ /dev/null
@@ -1,9 +0,0 @@
-noinst_HEADERS = \
- core-isa.h \
- core-matmap.h \
- defs.h \
- specreg.h \
- system.h \
- tie.h \
- core-isa-hsw.h \
- tie-asm.h
diff --git a/src/platform/haswell/include/arch/xtensa/config/core-isa-bdw.h b/src/platform/haswell/include/arch/xtensa/config/core-isa-bdw.h
deleted file mode 100644
index 8e562f9..0000000
--- a/src/platform/haswell/include/arch/xtensa/config/core-isa-bdw.h
+++ /dev/null
@@ -1,582 +0,0 @@
-/*
- * xtensa/config/core-isa.h -- HAL definitions that are dependent on Xtensa
- * processor CORE configuration
- *
- * See <xtensa/config/core.h>, which includes this file, for more details.
- */
-
-/* Xtensa processor core configuration information.
-
- Customer ID=4313; Build=0x5483b; Copyright (c) 1999-2015 Tensilica Inc.
-
- Permission is hereby granted, free of charge, to any person obtaining
- a copy of this software and associated documentation files (the
- "Software"), to deal in the Software without restriction, including
- without limitation the rights to use, copy, modify, merge, publish,
- distribute, sublicense, and/or sell copies of the Software, and to
- permit persons to whom the Software is furnished to do so, subject to
- the following conditions:
-
- The above copyright notice and this permission notice shall be included
- in all copies or substantial portions of the Software.
-
- THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
- EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
- MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
- IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY
- CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
- TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
- SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. */
-
-#ifndef _XTENSA_CORE_CONFIGURATION_H
-#define _XTENSA_CORE_CONFIGURATION_H
-
-
-/****************************************************************************
- Parameters Useful for Any Code, USER or PRIVILEGED
- ****************************************************************************/
-
-/*
- * Note: Macros of the form XCHAL_HAVE_*** have a value of 1 if the option is
- * configured, and a value of 0 otherwise. These macros are always defined.
- */
-
-
-/*----------------------------------------------------------------------
- ISA
- ----------------------------------------------------------------------*/
-
-#define XCHAL_HAVE_BE 0 /* big-endian byte ordering */
-#define XCHAL_HAVE_WINDOWED 1 /* windowed registers option */
-#define XCHAL_NUM_AREGS 32 /* num of physical addr regs */
-#define XCHAL_NUM_AREGS_LOG2 5 /* log2(XCHAL_NUM_AREGS) */
-#define XCHAL_MAX_INSTRUCTION_SIZE 8 /* max instr bytes (3..8) */
-#define XCHAL_HAVE_DEBUG 1 /* debug option */
-#define XCHAL_HAVE_DENSITY 1 /* 16-bit instructions */
-#define XCHAL_HAVE_LOOPS 1 /* zero-overhead loops */
-#define XCHAL_LOOP_BUFFER_SIZE 0 /* zero-ov. loop instr buffer size */
-#define XCHAL_HAVE_NSA 1 /* NSA/NSAU instructions */
-#define XCHAL_HAVE_MINMAX 1 /* MIN/MAX instructions */
-#define XCHAL_HAVE_SEXT 1 /* SEXT instruction */
-#define XCHAL_HAVE_DEPBITS 0 /* DEPBITS instruction */
-#define XCHAL_HAVE_CLAMPS 1 /* CLAMPS instruction */
-#define XCHAL_HAVE_MUL16 1 /* MUL16S/MUL16U instructions */
-#define XCHAL_HAVE_MUL32 0 /* MULL instruction */
-#define XCHAL_HAVE_MUL32_HIGH 0 /* MULUH/MULSH instructions */
-#define XCHAL_HAVE_DIV32 0 /* QUOS/QUOU/REMS/REMU instructions */
-#define XCHAL_HAVE_L32R 1 /* L32R instruction */
-#define XCHAL_HAVE_ABSOLUTE_LITERALS 0 /* non-PC-rel (extended) L32R */
-#define XCHAL_HAVE_CONST16 0 /* CONST16 instruction */
-#define XCHAL_HAVE_ADDX 1 /* ADDX#/SUBX# instructions */
-#define XCHAL_HAVE_WIDE_BRANCHES 0 /* B*.W18 or B*.W15 instr's */
-#define XCHAL_HAVE_PREDICTED_BRANCHES 0 /* B[EQ/EQZ/NE/NEZ]T instr's */
-#define XCHAL_HAVE_CALL4AND12 1 /* (obsolete option) */
-#define XCHAL_HAVE_ABS 1 /* ABS instruction */
-/*#define XCHAL_HAVE_POPC 0*/ /* POPC instruction */
-/*#define XCHAL_HAVE_CRC 0*/ /* CRC instruction */
-#define XCHAL_HAVE_RELEASE_SYNC 1 /* L32AI/S32RI instructions */
-#define XCHAL_HAVE_S32C1I 1 /* S32C1I instruction */
-#define XCHAL_HAVE_SPECULATION 0 /* speculation */
-#define XCHAL_HAVE_FULL_RESET 1 /* all regs/state reset */
-#define XCHAL_NUM_CONTEXTS 1 /* */
-#define XCHAL_NUM_MISC_REGS 0 /* num of scratch regs (0..4) */
-#define XCHAL_HAVE_TAP_MASTER 0 /* JTAG TAP control instr's */
-#define XCHAL_HAVE_PRID 1 /* processor ID register */
-#define XCHAL_HAVE_EXTERN_REGS 1 /* WER/RER instructions */
-#define XCHAL_HAVE_MX 0 /* MX core (Tensilica internal) */
-#define XCHAL_HAVE_MP_INTERRUPTS 0 /* interrupt distributor port */
-#define XCHAL_HAVE_MP_RUNSTALL 0 /* core RunStall control port */
-#define XCHAL_HAVE_PSO 0 /* Power Shut-Off */
-#define XCHAL_HAVE_PSO_CDM 0 /* core/debug/mem pwr domains */
-#define XCHAL_HAVE_PSO_FULL_RETENTION 0 /* all regs preserved on PSO */
-#define XCHAL_HAVE_THREADPTR 1 /* THREADPTR register */
-#define XCHAL_HAVE_BOOLEANS 1 /* boolean registers */
-#define XCHAL_HAVE_CP 1 /* CPENABLE reg (coprocessor) */
-#define XCHAL_CP_MAXCFG 2 /* max allowed cp id plus one */
-
-/* TODO: we have this option but currently our assembler does not support it */
-#define XCHAL_HAVE_MAC16 0 /* MAC16 package */
-
-#define XCHAL_HAVE_FUSION 0 /* Fusion*/
-#define XCHAL_HAVE_FUSION_FP 0 /* Fusion FP option */
-#define XCHAL_HAVE_FUSION_LOW_POWER 0 /* Fusion Low Power option */
-#define XCHAL_HAVE_FUSION_AES 0 /* Fusion BLE/Wifi AES-128 CCM option */
-#define XCHAL_HAVE_FUSION_CONVENC 0 /* Fusion Conv Encode option */
-#define XCHAL_HAVE_FUSION_LFSR_CRC 0 /* Fusion LFSR-CRC option */
-#define XCHAL_HAVE_FUSION_BITOPS 0 /* Fusion Bit Operations Support option */
-#define XCHAL_HAVE_FUSION_AVS 0 /* Fusion AVS option */
-#define XCHAL_HAVE_FUSION_16BIT_BASEBAND 0 /* Fusion 16-bit Baseband option */
-#define XCHAL_HAVE_HIFIPRO 0 /* HiFiPro Audio Engine pkg */
-#define XCHAL_HAVE_HIFI4 0 /* HiFi4 Audio Engine pkg */
-#define XCHAL_HAVE_HIFI4_VFPU 0 /* HiFi4 Audio Engine VFPU option */
-#define XCHAL_HAVE_HIFI3 0 /* HiFi3 Audio Engine pkg */
-#define XCHAL_HAVE_HIFI3_VFPU 0 /* HiFi3 Audio Engine VFPU option */
-#define XCHAL_HAVE_HIFI2 1 /* HiFi2 Audio Engine pkg */
-#define XCHAL_HAVE_HIFI2EP 1 /* HiFi2EP */
-#define XCHAL_HAVE_HIFI2_MUL32X24 1 /* HiFi2 and 32x24 MACs */
-#define XCHAL_HAVE_HIFI_MINI 0
-
-
-#define XCHAL_HAVE_VECTORFPU2005 0 /* vector or user floating-point pkg */
-#define XCHAL_HAVE_USER_DPFPU 0 /* user DP floating-point pkg */
-#define XCHAL_HAVE_USER_SPFPU 0 /* user DP floating-point pkg */
-#define XCHAL_HAVE_FP 0 /* single prec floating point */
-#define XCHAL_HAVE_FP_DIV 0 /* FP with DIV instructions */
-#define XCHAL_HAVE_FP_RECIP 0 /* FP with RECIP instructions */
-#define XCHAL_HAVE_FP_SQRT 0 /* FP with SQRT instructions */
-#define XCHAL_HAVE_FP_RSQRT 0 /* FP with RSQRT instructions */
-#define XCHAL_HAVE_DFP 0 /* double precision FP pkg */
-#define XCHAL_HAVE_DFP_DIV 0 /* DFP with DIV instructions */
-#define XCHAL_HAVE_DFP_RECIP 0 /* DFP with RECIP instructions*/
-#define XCHAL_HAVE_DFP_SQRT 0 /* DFP with SQRT instructions */
-#define XCHAL_HAVE_DFP_RSQRT 0 /* DFP with RSQRT instructions*/
-#define XCHAL_HAVE_DFP_ACCEL 0 /* double precision FP acceleration pkg */
-#define XCHAL_HAVE_DFP_accel XCHAL_HAVE_DFP_ACCEL /* for backward compatibility */
-
-#define XCHAL_HAVE_DFPU_SINGLE_ONLY 0 /* DFPU Coprocessor, single precision only */
-#define XCHAL_HAVE_DFPU_SINGLE_DOUBLE 0 /* DFPU Coprocessor, single and double precision */
-#define XCHAL_HAVE_VECTRA1 0 /* Vectra I pkg */
-#define XCHAL_HAVE_VECTRALX 0 /* Vectra LX pkg */
-#define XCHAL_HAVE_PDX4 0 /* PDX4 */
-#define XCHAL_HAVE_CONNXD2 0 /* ConnX D2 pkg */
-#define XCHAL_HAVE_CONNXD2_DUALLSFLIX 0 /* ConnX D2 & Dual LoadStore Flix */
-#define XCHAL_HAVE_BBE16 0 /* ConnX BBE16 pkg */
-#define XCHAL_HAVE_BBE16_RSQRT 0 /* BBE16 & vector recip sqrt */
-#define XCHAL_HAVE_BBE16_VECDIV 0 /* BBE16 & vector divide */
-#define XCHAL_HAVE_BBE16_DESPREAD 0 /* BBE16 & despread */
-#define XCHAL_HAVE_BBENEP 0 /* ConnX BBENEP pkgs */
-#define XCHAL_HAVE_BSP3 0 /* ConnX BSP3 pkg */
-#define XCHAL_HAVE_BSP3_TRANSPOSE 0 /* BSP3 & transpose32x32 */
-#define XCHAL_HAVE_SSP16 0 /* ConnX SSP16 pkg */
-#define XCHAL_HAVE_SSP16_VITERBI 0 /* SSP16 & viterbi */
-#define XCHAL_HAVE_TURBO16 0 /* ConnX Turbo16 pkg */
-#define XCHAL_HAVE_BBP16 0 /* ConnX BBP16 pkg */
-#define XCHAL_HAVE_FLIX3 0 /* basic 3-way FLIX option */
-#define XCHAL_HAVE_GRIVPEP 0 /* GRIVPEP is General Release of IVPEP */
-#define XCHAL_HAVE_GRIVPEP_HISTOGRAM 0 /* Histogram option on GRIVPEP */
-
-
-/*----------------------------------------------------------------------
- MISC
- ----------------------------------------------------------------------*/
-
-#define XCHAL_NUM_LOADSTORE_UNITS 1 /* load/store units */
-#define XCHAL_NUM_WRITEBUFFER_ENTRIES 16 /* size of write buffer */
-#define XCHAL_INST_FETCH_WIDTH 8 /* instr-fetch width in bytes */
-#define XCHAL_DATA_WIDTH 8 /* data width in bytes */
-#define XCHAL_DATA_PIPE_DELAY 1 /* d-side pipeline delay
- (1 = 5-stage, 2 = 7-stage) */
-#define XCHAL_CLOCK_GATING_GLOBAL 1 /* global clock gating */
-#define XCHAL_CLOCK_GATING_FUNCUNIT 1 /* funct. unit clock gating */
-/* In T1050, applies to selected core load and store instructions (see ISA): */
-#define XCHAL_UNALIGNED_LOAD_EXCEPTION 0 /* unaligned loads cause exc. */
-#define XCHAL_UNALIGNED_STORE_EXCEPTION 0 /* unaligned stores cause exc.*/
-#define XCHAL_UNALIGNED_LOAD_HW 1 /* unaligned loads work in hw */
-#define XCHAL_UNALIGNED_STORE_HW 1 /* unaligned stores work in hw*/
-
-#define XCHAL_SW_VERSION 1100002 /* sw version of this header */
-
-#define XCHAL_CORE_ID "hifi2ep" /* alphanum core name
- (CoreID) set in the Xtensa
- Processor Generator */
-
-#define XCHAL_BUILD_UNIQUE_ID 0x0005483B /* 22-bit sw build ID */
-
-/*
- * These definitions describe the hardware targeted by this software.
- */
-#define XCHAL_HW_CONFIGID0 0xC2B3DBFE /* ConfigID hi 32 bits*/
-#define XCHAL_HW_CONFIGID1 0x1C85483E /* ConfigID lo 32 bits*/
-#define XCHAL_HW_VERSION_NAME "LX6.0.2" /* full version name */
-#define XCHAL_HW_VERSION_MAJOR 2600 /* major ver# of targeted hw */
-#define XCHAL_HW_VERSION_MINOR 2 /* minor ver# of targeted hw */
-#define XCHAL_HW_VERSION 260002 /* major*100+minor */
-#define XCHAL_HW_REL_LX6 1
-#define XCHAL_HW_REL_LX6_0 1
-#define XCHAL_HW_REL_LX6_0_2 1
-#define XCHAL_HW_CONFIGID_RELIABLE 1
-/* If software targets a *range* of hardware versions, these are the bounds: */
-#define XCHAL_HW_MIN_VERSION_MAJOR 2600 /* major v of earliest tgt hw */
-#define XCHAL_HW_MIN_VERSION_MINOR 2 /* minor v of earliest tgt hw */
-#define XCHAL_HW_MIN_VERSION 260002 /* earliest targeted hw */
-#define XCHAL_HW_MAX_VERSION_MAJOR 2600 /* major v of latest tgt hw */
-#define XCHAL_HW_MAX_VERSION_MINOR 2 /* minor v of latest tgt hw */
-#define XCHAL_HW_MAX_VERSION 260002 /* latest targeted hw */
-
-
-/*----------------------------------------------------------------------
- CACHE
- ----------------------------------------------------------------------*/
-
-#define XCHAL_ICACHE_LINESIZE 128 /* I-cache line size in bytes */
-#define XCHAL_DCACHE_LINESIZE 128 /* D-cache line size in bytes */
-#define XCHAL_ICACHE_LINEWIDTH 7 /* log2(I line size in bytes) */
-#define XCHAL_DCACHE_LINEWIDTH 7 /* log2(D line size in bytes) */
-
-#define XCHAL_ICACHE_SIZE 0 /* I-cache size in bytes or 0 */
-#define XCHAL_DCACHE_SIZE 0 /* D-cache size in bytes or 0 */
-
-#define XCHAL_DCACHE_IS_WRITEBACK 0 /* writeback feature */
-#define XCHAL_DCACHE_IS_COHERENT 0 /* MP coherence feature */
-
-#define XCHAL_HAVE_PREFETCH 0 /* PREFCTL register */
-#define XCHAL_HAVE_PREFETCH_L1 0 /* prefetch to L1 dcache */
-#define XCHAL_PREFETCH_CASTOUT_LINES 0 /* dcache pref. castout bufsz */
-#define XCHAL_PREFETCH_ENTRIES 0 /* cache prefetch entries */
-#define XCHAL_PREFETCH_BLOCK_ENTRIES 0 /* prefetch block streams */
-#define XCHAL_HAVE_CACHE_BLOCKOPS 0 /* block prefetch for caches */
-#define XCHAL_HAVE_ICACHE_TEST 0 /* Icache test instructions */
-#define XCHAL_HAVE_DCACHE_TEST 0 /* Dcache test instructions */
-#define XCHAL_HAVE_ICACHE_DYN_WAYS 0 /* Icache dynamic way support */
-#define XCHAL_HAVE_DCACHE_DYN_WAYS 0 /* Dcache dynamic way support */
-
-
-
-
-/****************************************************************************
- Parameters Useful for PRIVILEGED (Supervisory or Non-Virtualized) Code
- ****************************************************************************/
-
-
-#ifndef XTENSA_HAL_NON_PRIVILEGED_ONLY
-
-/*----------------------------------------------------------------------
- CACHE
- ----------------------------------------------------------------------*/
-
-#define XCHAL_HAVE_PIF 1 /* any outbound PIF present */
-
-/* If present, cache size in bytes == (ways * 2^(linewidth + setwidth)). */
-
-/* Number of cache sets in log2(lines per way): */
-#define XCHAL_ICACHE_SETWIDTH 0
-#define XCHAL_DCACHE_SETWIDTH 0
-
-/* Cache set associativity (number of ways): */
-#define XCHAL_ICACHE_WAYS 0
-#define XCHAL_DCACHE_WAYS 0
-
-/* Cache features: */
-#define XCHAL_ICACHE_LINE_LOCKABLE 0
-#define XCHAL_DCACHE_LINE_LOCKABLE 0
-#define XCHAL_ICACHE_ECC_PARITY 0
-#define XCHAL_DCACHE_ECC_PARITY 0
-
-/* Cache access size in bytes (affects operation of SICW instruction): */
-#define XCHAL_ICACHE_ACCESS_SIZE 8
-#define XCHAL_DCACHE_ACCESS_SIZE 8
-
-#define XCHAL_DCACHE_BANKS 0 /* number of banks */
-
-/* Number of encoded cache attr bits (see <xtensa/hal.h> for decoded bits): */
-#define XCHAL_CA_BITS 4
-
-/* Whether MEMCTL register has anything useful */
-#define XCHAL_USE_MEMCTL (((XCHAL_LOOP_BUFFER_SIZE > 0) || \
- XCHAL_DCACHE_IS_COHERENT || \
- XCHAL_HAVE_ICACHE_DYN_WAYS || \
- XCHAL_HAVE_DCACHE_DYN_WAYS) && \
- (XCHAL_HW_MIN_VERSION >= XTENSA_HWVERSION_RE_2012_0))
-
-
-/*----------------------------------------------------------------------
- INTERNAL I/D RAM/ROMs and XLMI
- ----------------------------------------------------------------------*/
-
-#define XCHAL_NUM_INSTROM 0 /* number of core instr. ROMs */
-#define XCHAL_NUM_INSTRAM 1 /* number of core instr. RAMs */
-#define XCHAL_NUM_DATAROM 0 /* number of core data ROMs */
-#define XCHAL_NUM_DATARAM 1 /* number of core data RAMs */
-#define XCHAL_NUM_URAM 0 /* number of core unified RAMs*/
-#define XCHAL_NUM_XLMI 0 /* number of core XLMI ports */
-
-/* Instruction RAM 0: */
-#define XCHAL_INSTRAM0_VADDR 0x00000000 /* virtual address */
-#define XCHAL_INSTRAM0_PADDR 0x00000000 /* physical address */
-#define XCHAL_INSTRAM0_SIZE 0x50000 /* size in bytes */
-#define XCHAL_INSTRAM0_ECC_PARITY 0 /* ECC/parity type, 0=none */
-
-/* Data RAM 0: */
-#define XCHAL_DATARAM0_VADDR 0x00400000 /* virtual address */
-#define XCHAL_DATARAM0_PADDR 0x00400000 /* physical address */
-#define XCHAL_DATARAM0_SIZE 0xA0000 /* size in bytes */
-#define XCHAL_DATARAM0_ECC_PARITY 0 /* ECC/parity type, 0=none */
-#define XCHAL_DATARAM0_BANKS 1 /* number of banks */
-
-
-#define XCHAL_HAVE_IMEM_LOADSTORE 1 /* can load/store to IROM/IRAM*/
-
-
-/*----------------------------------------------------------------------
- INTERRUPTS and TIMERS
- ----------------------------------------------------------------------*/
-
-#define XCHAL_HAVE_INTERRUPTS 1 /* interrupt option */
-#define XCHAL_HAVE_HIGHPRI_INTERRUPTS 1 /* med/high-pri. interrupts */
-#define XCHAL_HAVE_NMI 1 /* non-maskable interrupt */
-#define XCHAL_HAVE_CCOUNT 1 /* CCOUNT reg. (timer option) */
-#define XCHAL_NUM_TIMERS 3 /* number of CCOMPAREn regs */
-#define XCHAL_NUM_INTERRUPTS 15 /* number of interrupts */
-#define XCHAL_NUM_INTERRUPTS_LOG2 4 /* ceil(log2(NUM_INTERRUPTS)) */
-#define XCHAL_NUM_EXTINTERRUPTS 10 /* num of external interrupts */
-#define XCHAL_NUM_INTLEVELS 6 /* number of interrupt levels
- (not including level zero) */
-#define XCHAL_EXCM_LEVEL 3 /* level masked by PS.EXCM */
- /* (always 1 in XEA1; levels 2 .. EXCM_LEVEL are "medium priority") */
-
-/* Masks of interrupts at each interrupt level: */
-#define XCHAL_INTLEVEL1_MASK 0x000000FF
-#define XCHAL_INTLEVEL2_MASK 0x00000100
-#define XCHAL_INTLEVEL3_MASK 0x00000e00
-#define XCHAL_INTLEVEL4_MASK 0x00001000
-#define XCHAL_INTLEVEL5_MASK 0x00002000
-#define XCHAL_INTLEVEL6_MASK 0x00000000
-#define XCHAL_INTLEVEL7_MASK 0x00004000
-
-/* Masks of interrupts at each range 1..n of interrupt levels: */
-#define XCHAL_INTLEVEL1_ANDBELOW_MASK 0x000000FF
-#define XCHAL_INTLEVEL2_ANDBELOW_MASK 0x000001FF
-#define XCHAL_INTLEVEL3_ANDBELOW_MASK 0x00000FFF
-#define XCHAL_INTLEVEL4_ANDBELOW_MASK 0x00001FFF
-#define XCHAL_INTLEVEL5_ANDBELOW_MASK 0x00003FFF
-#define XCHAL_INTLEVEL6_ANDBELOW_MASK 0x00003FFF
-#define XCHAL_INTLEVEL7_ANDBELOW_MASK 0x00007FFF
-
-/* Level of each interrupt: */
-#define XCHAL_INT0_LEVEL 1
-#define XCHAL_INT1_LEVEL 1
-#define XCHAL_INT2_LEVEL 1
-#define XCHAL_INT3_LEVEL 1
-
-#define XCHAL_INT4_LEVEL 1
-#define XCHAL_INT5_LEVEL 1
-#define XCHAL_INT6_LEVEL 1
-#define XCHAL_INT7_LEVEL 1
-
-#define XCHAL_INT8_LEVEL 2
-#define XCHAL_INT9_LEVEL 3
-#define XCHAL_INT10_LEVEL 3
-#define XCHAL_INT11_LEVEL 3
-
-#define XCHAL_INT12_LEVEL 4
-#define XCHAL_INT13_LEVEL 5
-#define XCHAL_INT14_LEVEL 7
-
-#define XCHAL_DEBUGLEVEL 6 /* debug interrupt level */
-#define XCHAL_HAVE_DEBUG_EXTERN_INT 1 /* OCD external db interrupt */
-#define XCHAL_NMILEVEL 7 /* NMI "level" (for use with
- EXCSAVE/EPS/EPC_n, RFI n) */
-
-/* Type of each interrupt: */
-#define XCHAL_INT0_TYPE XTHAL_INTTYPE_EXTERN_LEVEL
-#define XCHAL_INT1_TYPE XTHAL_INTTYPE_EXTERN_LEVEL
-#define XCHAL_INT2_TYPE XTHAL_INTTYPE_EXTERN_LEVEL
-#define XCHAL_INT3_TYPE XTHAL_INTTYPE_EXTERN_LEVEL
-#define XCHAL_INT4_TYPE XTHAL_INTTYPE_EXTERN_LEVEL
-#define XCHAL_INT5_TYPE XTHAL_INTTYPE_EXTERN_LEVEL
-#define XCHAL_INT6_TYPE XTHAL_INTTYPE_TIMER
-#define XCHAL_INT7_TYPE XTHAL_INTTYPE_SOFTWARE
-#define XCHAL_INT8_TYPE XTHAL_INTTYPE_EXTERN_LEVEL
-#define XCHAL_INT9_TYPE XTHAL_INTTYPE_EXTERN_LEVEL
-#define XCHAL_INT10_TYPE XTHAL_INTTYPE_TIMER
-#define XCHAL_INT11_TYPE XTHAL_INTTYPE_SOFTWARE
-#define XCHAL_INT12_TYPE XTHAL_INTTYPE_EXTERN_LEVEL
-#define XCHAL_INT13_TYPE XTHAL_INTTYPE_TIMER
-#define XCHAL_INT14_TYPE XTHAL_INTTYPE_NMI
-
-/* Masks of interrupts for each type of interrupt: */
-#define XCHAL_INTTYPE_MASK_UNCONFIGURED 0xFFFF8000
-#define XCHAL_INTTYPE_MASK_SOFTWARE 0x00000880
-#define XCHAL_INTTYPE_MASK_EXTERN_EDGE 0x00000000
-#define XCHAL_INTTYPE_MASK_EXTERN_LEVEL 0x0000133f
-#define XCHAL_INTTYPE_MASK_TIMER 0x00002440
-#define XCHAL_INTTYPE_MASK_NMI 0x00004000
-#define XCHAL_INTTYPE_MASK_WRITE_ERROR 0x00000000
-#define XCHAL_INTTYPE_MASK_PROFILING 0x00000000
-
-/* Interrupt numbers assigned to specific interrupt sources: */
-#define XCHAL_TIMER0_INTERRUPT 6 /* CCOMPARE0 */
-#define XCHAL_TIMER1_INTERRUPT 10 /* CCOMPARE1 */
-#define XCHAL_TIMER2_INTERRUPT 13 /* CCOMPARE2 */
-#define XCHAL_TIMER3_INTERRUPT XTHAL_TIMER_UNCONFIGURED
-#define XCHAL_NMI_INTERRUPT 14 /* non-maskable interrupt */
-
-/* Interrupt numbers for levels at which only one interrupt is configured: */
-//#define XCHAL_INTLEVEL2_NUM 8
-//#define XCHAL_INTLEVEL4_NUM 12
-//#define XCHAL_INTLEVEL5_NUM 13
-#define XCHAL_INTLEVEL7_NUM 14
-/* (There are many interrupts each at level(s) 1, 3.) */
-
-
-/*
- * External interrupt mapping.
- * These macros describe how Xtensa processor interrupt numbers
- * (as numbered internally, eg. in INTERRUPT and INTENABLE registers)
- * map to external BInterrupt<n> pins, for those interrupts
- * configured as external (level-triggered, edge-triggered, or NMI).
- * See the Xtensa processor databook for more details.
- */
-
-/* Core interrupt numbers mapped to each EXTERNAL BInterrupt pin number: */
-#define XCHAL_EXTINT0_NUM 0 /* (intlevel 1) */
-#define XCHAL_EXTINT1_NUM 1 /* (intlevel 1) */
-#define XCHAL_EXTINT2_NUM 2 /* (intlevel 1) */
-#define XCHAL_EXTINT3_NUM 3 /* (intlevel 1) */
-#define XCHAL_EXTINT4_NUM 4 /* (intlevel 1) */
-#define XCHAL_EXTINT5_NUM 5 /* (intlevel 1) */
-#define XCHAL_EXTINT6_NUM 8 /* (intlevel 2) */
-#define XCHAL_EXTINT7_NUM 9 /* (intlevel 3) */
-#define XCHAL_EXTINT8_NUM 12 /* (intlevel 4) */
-#define XCHAL_EXTINT9_NUM 14 /* (intlevel 7) */
-#define XCHAL_EXTINT10_NUM 15 /* (intlevel 1) */
-#define XCHAL_EXTINT11_NUM 16 /* (intlevel 1) */
-#define XCHAL_EXTINT12_NUM 17 /* (intlevel 1) */
-#define XCHAL_EXTINT13_NUM 18 /* (intlevel 1) */
-#define XCHAL_EXTINT14_NUM 19 /* (intlevel 1) */
-#define XCHAL_EXTINT15_NUM 20 /* (intlevel 1) */
-#define XCHAL_EXTINT16_NUM 21 /* (intlevel 3) */
-/* EXTERNAL BInterrupt pin numbers mapped to each core interrupt number: */
-#define XCHAL_INT0_EXTNUM 0 /* (intlevel 1) */
-#define XCHAL_INT1_EXTNUM 1 /* (intlevel 1) */
-#define XCHAL_INT2_EXTNUM 2 /* (intlevel 1) */
-#define XCHAL_INT3_EXTNUM 3 /* (intlevel 1) */
-#define XCHAL_INT4_EXTNUM 4 /* (intlevel 1) */
-#define XCHAL_INT5_EXTNUM 5 /* (intlevel 1) */
-#define XCHAL_INT8_EXTNUM 6 /* (intlevel 2) */
-#define XCHAL_INT9_EXTNUM 7 /* (intlevel 3) */
-#define XCHAL_INT12_EXTNUM 8 /* (intlevel 4) */
-#define XCHAL_INT14_EXTNUM 9 /* (intlevel 7) */
-#define XCHAL_INT15_EXTNUM 10 /* (intlevel 1) */
-#define XCHAL_INT16_EXTNUM 11 /* (intlevel 1) */
-#define XCHAL_INT17_EXTNUM 12 /* (intlevel 1) */
-#define XCHAL_INT18_EXTNUM 13 /* (intlevel 1) */
-#define XCHAL_INT19_EXTNUM 14 /* (intlevel 1) */
-#define XCHAL_INT20_EXTNUM 15 /* (intlevel 1) */
-#define XCHAL_INT21_EXTNUM 16 /* (intlevel 3) */
-
-
-/*----------------------------------------------------------------------
- EXCEPTIONS and VECTORS
- ----------------------------------------------------------------------*/
-
-#define XCHAL_XEA_VERSION 2 /* Xtensa Exception Architecture
- number: 1 == XEA1 (old)
- 2 == XEA2 (new)
- 0 == XEAX (extern) or TX */
-#define XCHAL_HAVE_XEA1 0 /* Exception Architecture 1 */
-#define XCHAL_HAVE_XEA2 1 /* Exception Architecture 2 */
-#define XCHAL_HAVE_XEAX 0 /* External Exception Arch. */
-#define XCHAL_HAVE_EXCEPTIONS 1 /* exception option */
-#define XCHAL_HAVE_HALT 0 /* halt architecture option */
-#define XCHAL_HAVE_BOOTLOADER 0 /* boot loader (for TX) */
-#define XCHAL_HAVE_MEM_ECC_PARITY 0 /* local memory ECC/parity */
-#define XCHAL_HAVE_VECTOR_SELECT 0 /* relocatable vectors */
-#define XCHAL_HAVE_VECBASE 0 /* relocatable vectors */
-#define XCHAL_VECBASE_RESET_VADDR 0x00000400 /* VECBASE reset value */
-#define XCHAL_VECBASE_RESET_PADDR 0x00000400
-#define XCHAL_RESET_VECBASE_OVERLAP 0
-
-#define XCHAL_RESET_VECTOR0_VADDR 0x00000000
-#define XCHAL_RESET_VECTOR0_PADDR 0x00000000
-#define XCHAL_RESET_VECTOR1_VADDR 0x00000000
-#define XCHAL_RESET_VECTOR1_PADDR 0x00000000
-#define XCHAL_RESET_VECTOR_VADDR 0x00000000
-#define XCHAL_RESET_VECTOR_PADDR 0x00000000
-#define XCHAL_USER_VECOFS 0x000005c0
-#define XCHAL_USER_VECTOR_VADDR 0x000005c0
-#define XCHAL_USER_VECTOR_PADDR 0x000005c0
-#define XCHAL_KERNEL_VECOFS 0x00000584
-#define XCHAL_KERNEL_VECTOR_VADDR 0x00000584
-#define XCHAL_KERNEL_VECTOR_PADDR 0x00000584
-#define XCHAL_DOUBLEEXC_VECOFS 0x000005fc
-#define XCHAL_DOUBLEEXC_VECTOR_VADDR 0x000005fc
-#define XCHAL_DOUBLEEXC_VECTOR_PADDR 0x000005fc
-#define XCHAL_WINDOW_OF4_VECOFS 0x00000000
-#define XCHAL_WINDOW_UF4_VECOFS 0x00000040
-#define XCHAL_WINDOW_OF8_VECOFS 0x00000080
-#define XCHAL_WINDOW_UF8_VECOFS 0x000000C0
-#define XCHAL_WINDOW_OF12_VECOFS 0x00000100
-#define XCHAL_WINDOW_UF12_VECOFS 0x00000140
-#define XCHAL_WINDOW_VECTORS_VADDR 0x00000400
-#define XCHAL_WINDOW_VECTORS_PADDR 0x00000400
-#define XCHAL_INTLEVEL2_VECOFS 0x00000640
-#define XCHAL_INTLEVEL2_VECTOR_VADDR 0x00000640
-#define XCHAL_INTLEVEL2_VECTOR_PADDR 0x00000640
-#define XCHAL_INTLEVEL3_VECOFS 0x0000067c
-#define XCHAL_INTLEVEL3_VECTOR_VADDR 0x0000067c
-#define XCHAL_INTLEVEL3_VECTOR_PADDR 0x0000067c
-#define XCHAL_INTLEVEL4_VECOFS 0x000006b8
-#define XCHAL_INTLEVEL4_VECTOR_VADDR 0x000006b8
-#define XCHAL_INTLEVEL4_VECTOR_PADDR 0x000006b8
-#define XCHAL_INTLEVEL5_VECOFS 0x000006f4
-#define XCHAL_INTLEVEL5_VECTOR_VADDR 0x000006f4
-#define XCHAL_INTLEVEL5_VECTOR_PADDR 0x000006f4
-#define XCHAL_INTLEVEL6_VECOFS 0x00000730
-#define XCHAL_INTLEVEL6_VECTOR_VADDR 0x00000730
-#define XCHAL_INTLEVEL6_VECTOR_PADDR 0x00000730
-#define XCHAL_DEBUG_VECOFS XCHAL_INTLEVEL6_VECOFS
-#define XCHAL_DEBUG_VECTOR_VADDR XCHAL_INTLEVEL6_VECTOR_VADDR
-#define XCHAL_DEBUG_VECTOR_PADDR XCHAL_INTLEVEL6_VECTOR_PADDR
-#define XCHAL_NMI_VECOFS 0x0000076c
-#define XCHAL_NMI_VECTOR_VADDR 0x0000076c
-#define XCHAL_NMI_VECTOR_PADDR 0x0000076c
-#define XCHAL_INTLEVEL7_VECOFS XCHAL_NMI_VECOFS
-#define XCHAL_INTLEVEL7_VECTOR_VADDR XCHAL_NMI_VECTOR_VADDR
-#define XCHAL_INTLEVEL7_VECTOR_PADDR XCHAL_NMI_VECTOR_PADDR
-
-
-/*----------------------------------------------------------------------
- DEBUG MODULE
- ----------------------------------------------------------------------*/
-
-/* Misc */
-#define XCHAL_HAVE_DEBUG_ERI 0 /* ERI to debug module */
-#define XCHAL_HAVE_DEBUG_APB 0 /* APB to debug module */
-#define XCHAL_HAVE_DEBUG_JTAG 1 /* JTAG to debug module */
-
-/* On-Chip Debug (OCD) */
-#define XCHAL_HAVE_OCD 1 /* OnChipDebug option */
-#define XCHAL_NUM_IBREAK 2 /* number of IBREAKn regs */
-#define XCHAL_NUM_DBREAK 2 /* number of DBREAKn regs */
-#define XCHAL_HAVE_OCD_DIR_ARRAY 1 /* faster OCD option (to LX4) */
-#define XCHAL_HAVE_OCD_LS32DDR 1 /* L32DDR/S32DDR (faster OCD) */
-
-/* TRAX (in core) */
-#define XCHAL_HAVE_TRAX 0 /* TRAX in debug module */
-#define XCHAL_TRAX_MEM_SIZE 0 /* TRAX memory size in bytes */
-#define XCHAL_TRAX_MEM_SHAREABLE 0 /* start/end regs; ready sig. */
-#define XCHAL_TRAX_ATB_WIDTH 0 /* ATB width (bits), 0=no ATB */
-#define XCHAL_TRAX_TIME_WIDTH 0 /* timestamp bitwidth, 0=none */
-
-/* Perf counters */
-#define XCHAL_NUM_PERF_COUNTERS 0 /* performance counters */
-
-
-/*----------------------------------------------------------------------
- MMU
- ----------------------------------------------------------------------*/
-
-/* See core-matmap.h header file for more details. */
-
-#define XCHAL_HAVE_TLBS 1 /* inverse of HAVE_CACHEATTR */
-#define XCHAL_HAVE_SPANNING_WAY 1 /* one way maps I+D 4GB vaddr */
-#define XCHAL_SPANNING_WAY 0 /* TLB spanning way number */
-#define XCHAL_HAVE_IDENTITY_MAP 0 /* vaddr == paddr always */
-#define XCHAL_HAVE_CACHEATTR 0 /* CACHEATTR register present */
-#define XCHAL_HAVE_MIMIC_CACHEATTR 1 /* region protection */
-#define XCHAL_HAVE_XLT_CACHEATTR 0 /* region prot. w/translation */
-#define XCHAL_HAVE_PTP_MMU 0 /* full MMU (with page table
- [autorefill] and protection)
- usable for an MMU-based OS */
-/* If none of the above last 4 are set, it's a custom TLB configuration. */
-
-#define XCHAL_MMU_ASID_BITS 0 /* number of bits in ASIDs */
-#define XCHAL_MMU_RINGS 1 /* number of rings (1..4) */
-#define XCHAL_MMU_RING_BITS 0 /* num of bits in RING field */
-
-#endif /* !XTENSA_HAL_NON_PRIVILEGED_ONLY */
-
-
-#endif /* _XTENSA_CORE_CONFIGURATION_H */
-
diff --git a/src/platform/haswell/include/arch/xtensa/config/core-isa-hsw.h b/src/platform/haswell/include/arch/xtensa/config/core-isa-hsw.h
deleted file mode 100644
index b25162d..0000000
--- a/src/platform/haswell/include/arch/xtensa/config/core-isa-hsw.h
+++ /dev/null
@@ -1,582 +0,0 @@
-/*
- * xtensa/config/core-isa.h -- HAL definitions that are dependent on Xtensa
- * processor CORE configuration
- *
- * See <xtensa/config/core.h>, which includes this file, for more details.
- */
-
-/* Xtensa processor core configuration information.
-
- Customer ID=4313; Build=0x5483b; Copyright (c) 1999-2015 Tensilica Inc.
-
- Permission is hereby granted, free of charge, to any person obtaining
- a copy of this software and associated documentation files (the
- "Software"), to deal in the Software without restriction, including
- without limitation the rights to use, copy, modify, merge, publish,
- distribute, sublicense, and/or sell copies of the Software, and to
- permit persons to whom the Software is furnished to do so, subject to
- the following conditions:
-
- The above copyright notice and this permission notice shall be included
- in all copies or substantial portions of the Software.
-
- THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
- EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
- MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
- IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY
- CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
- TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
- SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. */
-
-#ifndef _XTENSA_CORE_CONFIGURATION_H
-#define _XTENSA_CORE_CONFIGURATION_H
-
-
-/****************************************************************************
- Parameters Useful for Any Code, USER or PRIVILEGED
- ****************************************************************************/
-
-/*
- * Note: Macros of the form XCHAL_HAVE_*** have a value of 1 if the option is
- * configured, and a value of 0 otherwise. These macros are always defined.
- */
-
-
-/*----------------------------------------------------------------------
- ISA
- ----------------------------------------------------------------------*/
-
-#define XCHAL_HAVE_BE 0 /* big-endian byte ordering */
-#define XCHAL_HAVE_WINDOWED 1 /* windowed registers option */
-#define XCHAL_NUM_AREGS 32 /* num of physical addr regs */
-#define XCHAL_NUM_AREGS_LOG2 5 /* log2(XCHAL_NUM_AREGS) */
-#define XCHAL_MAX_INSTRUCTION_SIZE 8 /* max instr bytes (3..8) */
-#define XCHAL_HAVE_DEBUG 1 /* debug option */
-#define XCHAL_HAVE_DENSITY 1 /* 16-bit instructions */
-#define XCHAL_HAVE_LOOPS 1 /* zero-overhead loops */
-#define XCHAL_LOOP_BUFFER_SIZE 0 /* zero-ov. loop instr buffer size */
-#define XCHAL_HAVE_NSA 1 /* NSA/NSAU instructions */
-#define XCHAL_HAVE_MINMAX 1 /* MIN/MAX instructions */
-#define XCHAL_HAVE_SEXT 1 /* SEXT instruction */
-#define XCHAL_HAVE_DEPBITS 0 /* DEPBITS instruction */
-#define XCHAL_HAVE_CLAMPS 1 /* CLAMPS instruction */
-#define XCHAL_HAVE_MUL16 1 /* MUL16S/MUL16U instructions */
-#define XCHAL_HAVE_MUL32 0 /* MULL instruction */
-#define XCHAL_HAVE_MUL32_HIGH 0 /* MULUH/MULSH instructions */
-#define XCHAL_HAVE_DIV32 0 /* QUOS/QUOU/REMS/REMU instructions */
-#define XCHAL_HAVE_L32R 1 /* L32R instruction */
-#define XCHAL_HAVE_ABSOLUTE_LITERALS 0 /* non-PC-rel (extended) L32R */
-#define XCHAL_HAVE_CONST16 0 /* CONST16 instruction */
-#define XCHAL_HAVE_ADDX 1 /* ADDX#/SUBX# instructions */
-#define XCHAL_HAVE_WIDE_BRANCHES 0 /* B*.W18 or B*.W15 instr's */
-#define XCHAL_HAVE_PREDICTED_BRANCHES 0 /* B[EQ/EQZ/NE/NEZ]T instr's */
-#define XCHAL_HAVE_CALL4AND12 1 /* (obsolete option) */
-#define XCHAL_HAVE_ABS 1 /* ABS instruction */
-/*#define XCHAL_HAVE_POPC 0*/ /* POPC instruction */
-/*#define XCHAL_HAVE_CRC 0*/ /* CRC instruction */
-#define XCHAL_HAVE_RELEASE_SYNC 1 /* L32AI/S32RI instructions */
-#define XCHAL_HAVE_S32C1I 1 /* S32C1I instruction */
-#define XCHAL_HAVE_SPECULATION 0 /* speculation */
-#define XCHAL_HAVE_FULL_RESET 1 /* all regs/state reset */
-#define XCHAL_NUM_CONTEXTS 1 /* */
-#define XCHAL_NUM_MISC_REGS 0 /* num of scratch regs (0..4) */
-#define XCHAL_HAVE_TAP_MASTER 0 /* JTAG TAP control instr's */
-#define XCHAL_HAVE_PRID 1 /* processor ID register */
-#define XCHAL_HAVE_EXTERN_REGS 1 /* WER/RER instructions */
-#define XCHAL_HAVE_MX 0 /* MX core (Tensilica internal) */
-#define XCHAL_HAVE_MP_INTERRUPTS 0 /* interrupt distributor port */
-#define XCHAL_HAVE_MP_RUNSTALL 0 /* core RunStall control port */
-#define XCHAL_HAVE_PSO 0 /* Power Shut-Off */
-#define XCHAL_HAVE_PSO_CDM 0 /* core/debug/mem pwr domains */
-#define XCHAL_HAVE_PSO_FULL_RETENTION 0 /* all regs preserved on PSO */
-#define XCHAL_HAVE_THREADPTR 1 /* THREADPTR register */
-#define XCHAL_HAVE_BOOLEANS 1 /* boolean registers */
-#define XCHAL_HAVE_CP 1 /* CPENABLE reg (coprocessor) */
-#define XCHAL_CP_MAXCFG 2 /* max allowed cp id plus one */
-
-/* TODO: we have this option but currently our assembler does not support it */
-#define XCHAL_HAVE_MAC16 0 /* MAC16 package */
-
-#define XCHAL_HAVE_FUSION 0 /* Fusion*/
-#define XCHAL_HAVE_FUSION_FP 0 /* Fusion FP option */
-#define XCHAL_HAVE_FUSION_LOW_POWER 0 /* Fusion Low Power option */
-#define XCHAL_HAVE_FUSION_AES 0 /* Fusion BLE/Wifi AES-128 CCM option */
-#define XCHAL_HAVE_FUSION_CONVENC 0 /* Fusion Conv Encode option */
-#define XCHAL_HAVE_FUSION_LFSR_CRC 0 /* Fusion LFSR-CRC option */
-#define XCHAL_HAVE_FUSION_BITOPS 0 /* Fusion Bit Operations Support option */
-#define XCHAL_HAVE_FUSION_AVS 0 /* Fusion AVS option */
-#define XCHAL_HAVE_FUSION_16BIT_BASEBAND 0 /* Fusion 16-bit Baseband option */
-#define XCHAL_HAVE_HIFIPRO 0 /* HiFiPro Audio Engine pkg */
-#define XCHAL_HAVE_HIFI4 0 /* HiFi4 Audio Engine pkg */
-#define XCHAL_HAVE_HIFI4_VFPU 0 /* HiFi4 Audio Engine VFPU option */
-#define XCHAL_HAVE_HIFI3 0 /* HiFi3 Audio Engine pkg */
-#define XCHAL_HAVE_HIFI3_VFPU 0 /* HiFi3 Audio Engine VFPU option */
-#define XCHAL_HAVE_HIFI2 1 /* HiFi2 Audio Engine pkg */
-#define XCHAL_HAVE_HIFI2EP 1 /* HiFi2EP */
-#define XCHAL_HAVE_HIFI2_MUL32X24 1 /* HiFi2 and 32x24 MACs */
-#define XCHAL_HAVE_HIFI_MINI 0
-
-
-#define XCHAL_HAVE_VECTORFPU2005 0 /* vector or user floating-point pkg */
-#define XCHAL_HAVE_USER_DPFPU 0 /* user DP floating-point pkg */
-#define XCHAL_HAVE_USER_SPFPU 0 /* user DP floating-point pkg */
-#define XCHAL_HAVE_FP 0 /* single prec floating point */
-#define XCHAL_HAVE_FP_DIV 0 /* FP with DIV instructions */
-#define XCHAL_HAVE_FP_RECIP 0 /* FP with RECIP instructions */
-#define XCHAL_HAVE_FP_SQRT 0 /* FP with SQRT instructions */
-#define XCHAL_HAVE_FP_RSQRT 0 /* FP with RSQRT instructions */
-#define XCHAL_HAVE_DFP 0 /* double precision FP pkg */
-#define XCHAL_HAVE_DFP_DIV 0 /* DFP with DIV instructions */
-#define XCHAL_HAVE_DFP_RECIP 0 /* DFP with RECIP instructions*/
-#define XCHAL_HAVE_DFP_SQRT 0 /* DFP with SQRT instructions */
-#define XCHAL_HAVE_DFP_RSQRT 0 /* DFP with RSQRT instructions*/
-#define XCHAL_HAVE_DFP_ACCEL 0 /* double precision FP acceleration pkg */
-#define XCHAL_HAVE_DFP_accel XCHAL_HAVE_DFP_ACCEL /* for backward compatibility */
-
-#define XCHAL_HAVE_DFPU_SINGLE_ONLY 0 /* DFPU Coprocessor, single precision only */
-#define XCHAL_HAVE_DFPU_SINGLE_DOUBLE 0 /* DFPU Coprocessor, single and double precision */
-#define XCHAL_HAVE_VECTRA1 0 /* Vectra I pkg */
-#define XCHAL_HAVE_VECTRALX 0 /* Vectra LX pkg */
-#define XCHAL_HAVE_PDX4 0 /* PDX4 */
-#define XCHAL_HAVE_CONNXD2 0 /* ConnX D2 pkg */
-#define XCHAL_HAVE_CONNXD2_DUALLSFLIX 0 /* ConnX D2 & Dual LoadStore Flix */
-#define XCHAL_HAVE_BBE16 0 /* ConnX BBE16 pkg */
-#define XCHAL_HAVE_BBE16_RSQRT 0 /* BBE16 & vector recip sqrt */
-#define XCHAL_HAVE_BBE16_VECDIV 0 /* BBE16 & vector divide */
-#define XCHAL_HAVE_BBE16_DESPREAD 0 /* BBE16 & despread */
-#define XCHAL_HAVE_BBENEP 0 /* ConnX BBENEP pkgs */
-#define XCHAL_HAVE_BSP3 0 /* ConnX BSP3 pkg */
-#define XCHAL_HAVE_BSP3_TRANSPOSE 0 /* BSP3 & transpose32x32 */
-#define XCHAL_HAVE_SSP16 0 /* ConnX SSP16 pkg */
-#define XCHAL_HAVE_SSP16_VITERBI 0 /* SSP16 & viterbi */
-#define XCHAL_HAVE_TURBO16 0 /* ConnX Turbo16 pkg */
-#define XCHAL_HAVE_BBP16 0 /* ConnX BBP16 pkg */
-#define XCHAL_HAVE_FLIX3 0 /* basic 3-way FLIX option */
-#define XCHAL_HAVE_GRIVPEP 0 /* GRIVPEP is General Release of IVPEP */
-#define XCHAL_HAVE_GRIVPEP_HISTOGRAM 0 /* Histogram option on GRIVPEP */
-
-
-/*----------------------------------------------------------------------
- MISC
- ----------------------------------------------------------------------*/
-
-#define XCHAL_NUM_LOADSTORE_UNITS 1 /* load/store units */
-#define XCHAL_NUM_WRITEBUFFER_ENTRIES 16 /* size of write buffer */
-#define XCHAL_INST_FETCH_WIDTH 8 /* instr-fetch width in bytes */
-#define XCHAL_DATA_WIDTH 8 /* data width in bytes */
-#define XCHAL_DATA_PIPE_DELAY 1 /* d-side pipeline delay
- (1 = 5-stage, 2 = 7-stage) */
-#define XCHAL_CLOCK_GATING_GLOBAL 1 /* global clock gating */
-#define XCHAL_CLOCK_GATING_FUNCUNIT 1 /* funct. unit clock gating */
-/* In T1050, applies to selected core load and store instructions (see ISA): */
-#define XCHAL_UNALIGNED_LOAD_EXCEPTION 0 /* unaligned loads cause exc. */
-#define XCHAL_UNALIGNED_STORE_EXCEPTION 0 /* unaligned stores cause exc.*/
-#define XCHAL_UNALIGNED_LOAD_HW 1 /* unaligned loads work in hw */
-#define XCHAL_UNALIGNED_STORE_HW 1 /* unaligned stores work in hw*/
-
-#define XCHAL_SW_VERSION 1100002 /* sw version of this header */
-
-#define XCHAL_CORE_ID "hifi2ep" /* alphanum core name
- (CoreID) set in the Xtensa
- Processor Generator */
-
-#define XCHAL_BUILD_UNIQUE_ID 0x0005483B /* 22-bit sw build ID */
-
-/*
- * These definitions describe the hardware targeted by this software.
- */
-#define XCHAL_HW_CONFIGID0 0xC2B3DBFE /* ConfigID hi 32 bits*/
-#define XCHAL_HW_CONFIGID1 0x1C85483E /* ConfigID lo 32 bits*/
-#define XCHAL_HW_VERSION_NAME "LX6.0.2" /* full version name */
-#define XCHAL_HW_VERSION_MAJOR 2600 /* major ver# of targeted hw */
-#define XCHAL_HW_VERSION_MINOR 2 /* minor ver# of targeted hw */
-#define XCHAL_HW_VERSION 260002 /* major*100+minor */
-#define XCHAL_HW_REL_LX6 1
-#define XCHAL_HW_REL_LX6_0 1
-#define XCHAL_HW_REL_LX6_0_2 1
-#define XCHAL_HW_CONFIGID_RELIABLE 1
-/* If software targets a *range* of hardware versions, these are the bounds: */
-#define XCHAL_HW_MIN_VERSION_MAJOR 2600 /* major v of earliest tgt hw */
-#define XCHAL_HW_MIN_VERSION_MINOR 2 /* minor v of earliest tgt hw */
-#define XCHAL_HW_MIN_VERSION 260002 /* earliest targeted hw */
-#define XCHAL_HW_MAX_VERSION_MAJOR 2600 /* major v of latest tgt hw */
-#define XCHAL_HW_MAX_VERSION_MINOR 2 /* minor v of latest tgt hw */
-#define XCHAL_HW_MAX_VERSION 260002 /* latest targeted hw */
-
-
-/*----------------------------------------------------------------------
- CACHE
- ----------------------------------------------------------------------*/
-
-#define XCHAL_ICACHE_LINESIZE 128 /* I-cache line size in bytes */
-#define XCHAL_DCACHE_LINESIZE 128 /* D-cache line size in bytes */
-#define XCHAL_ICACHE_LINEWIDTH 7 /* log2(I line size in bytes) */
-#define XCHAL_DCACHE_LINEWIDTH 7 /* log2(D line size in bytes) */
-
-#define XCHAL_ICACHE_SIZE 0 /* I-cache size in bytes or 0 */
-#define XCHAL_DCACHE_SIZE 0 /* D-cache size in bytes or 0 */
-
-#define XCHAL_DCACHE_IS_WRITEBACK 0 /* writeback feature */
-#define XCHAL_DCACHE_IS_COHERENT 0 /* MP coherence feature */
-
-#define XCHAL_HAVE_PREFETCH 0 /* PREFCTL register */
-#define XCHAL_HAVE_PREFETCH_L1 0 /* prefetch to L1 dcache */
-#define XCHAL_PREFETCH_CASTOUT_LINES 0 /* dcache pref. castout bufsz */
-#define XCHAL_PREFETCH_ENTRIES 0 /* cache prefetch entries */
-#define XCHAL_PREFETCH_BLOCK_ENTRIES 0 /* prefetch block streams */
-#define XCHAL_HAVE_CACHE_BLOCKOPS 0 /* block prefetch for caches */
-#define XCHAL_HAVE_ICACHE_TEST 0 /* Icache test instructions */
-#define XCHAL_HAVE_DCACHE_TEST 0 /* Dcache test instructions */
-#define XCHAL_HAVE_ICACHE_DYN_WAYS 0 /* Icache dynamic way support */
-#define XCHAL_HAVE_DCACHE_DYN_WAYS 0 /* Dcache dynamic way support */
-
-
-
-
-/****************************************************************************
- Parameters Useful for PRIVILEGED (Supervisory or Non-Virtualized) Code
- ****************************************************************************/
-
-
-#ifndef XTENSA_HAL_NON_PRIVILEGED_ONLY
-
-/*----------------------------------------------------------------------
- CACHE
- ----------------------------------------------------------------------*/
-
-#define XCHAL_HAVE_PIF 1 /* any outbound PIF present */
-
-/* If present, cache size in bytes == (ways * 2^(linewidth + setwidth)). */
-
-/* Number of cache sets in log2(lines per way): */
-#define XCHAL_ICACHE_SETWIDTH 0
-#define XCHAL_DCACHE_SETWIDTH 0
-
-/* Cache set associativity (number of ways): */
-#define XCHAL_ICACHE_WAYS 0
-#define XCHAL_DCACHE_WAYS 0
-
-/* Cache features: */
-#define XCHAL_ICACHE_LINE_LOCKABLE 0
-#define XCHAL_DCACHE_LINE_LOCKABLE 0
-#define XCHAL_ICACHE_ECC_PARITY 0
-#define XCHAL_DCACHE_ECC_PARITY 0
-
-/* Cache access size in bytes (affects operation of SICW instruction): */
-#define XCHAL_ICACHE_ACCESS_SIZE 8
-#define XCHAL_DCACHE_ACCESS_SIZE 8
-
-#define XCHAL_DCACHE_BANKS 0 /* number of banks */
-
-/* Number of encoded cache attr bits (see <xtensa/hal.h> for decoded bits): */
-#define XCHAL_CA_BITS 4
-
-/* Whether MEMCTL register has anything useful */
-#define XCHAL_USE_MEMCTL (((XCHAL_LOOP_BUFFER_SIZE > 0) || \
- XCHAL_DCACHE_IS_COHERENT || \
- XCHAL_HAVE_ICACHE_DYN_WAYS || \
- XCHAL_HAVE_DCACHE_DYN_WAYS) && \
- (XCHAL_HW_MIN_VERSION >= XTENSA_HWVERSION_RE_2012_0))
-
-
-/*----------------------------------------------------------------------
- INTERNAL I/D RAM/ROMs and XLMI
- ----------------------------------------------------------------------*/
-
-#define XCHAL_NUM_INSTROM 0 /* number of core instr. ROMs */
-#define XCHAL_NUM_INSTRAM 1 /* number of core instr. RAMs */
-#define XCHAL_NUM_DATAROM 0 /* number of core data ROMs */
-#define XCHAL_NUM_DATARAM 1 /* number of core data RAMs */
-#define XCHAL_NUM_URAM 0 /* number of core unified RAMs*/
-#define XCHAL_NUM_XLMI 0 /* number of core XLMI ports */
-
-/* Instruction RAM 0: */
-#define XCHAL_INSTRAM0_VADDR 0x00000000 /* virtual address */
-#define XCHAL_INSTRAM0_PADDR 0x00000000 /* physical address */
-#define XCHAL_INSTRAM0_SIZE 0x50000 /* size in bytes */
-#define XCHAL_INSTRAM0_ECC_PARITY 0 /* ECC/parity type, 0=none */
-
-/* Data RAM 0: */
-#define XCHAL_DATARAM0_VADDR 0x00400000 /* virtual address */
-#define XCHAL_DATARAM0_PADDR 0x00400000 /* physical address */
-#define XCHAL_DATARAM0_SIZE 0x80000 /* size in bytes */
-#define XCHAL_DATARAM0_ECC_PARITY 0 /* ECC/parity type, 0=none */
-#define XCHAL_DATARAM0_BANKS 1 /* number of banks */
-
-
-#define XCHAL_HAVE_IMEM_LOADSTORE 1 /* can load/store to IROM/IRAM*/
-
-
-/*----------------------------------------------------------------------
- INTERRUPTS and TIMERS
- ----------------------------------------------------------------------*/
-
-#define XCHAL_HAVE_INTERRUPTS 1 /* interrupt option */
-#define XCHAL_HAVE_HIGHPRI_INTERRUPTS 1 /* med/high-pri. interrupts */
-#define XCHAL_HAVE_NMI 1 /* non-maskable interrupt */
-#define XCHAL_HAVE_CCOUNT 1 /* CCOUNT reg. (timer option) */
-#define XCHAL_NUM_TIMERS 3 /* number of CCOMPAREn regs */
-#define XCHAL_NUM_INTERRUPTS 15 /* number of interrupts */
-#define XCHAL_NUM_INTERRUPTS_LOG2 4 /* ceil(log2(NUM_INTERRUPTS)) */
-#define XCHAL_NUM_EXTINTERRUPTS 10 /* num of external interrupts */
-#define XCHAL_NUM_INTLEVELS 6 /* number of interrupt levels
- (not including level zero) */
-#define XCHAL_EXCM_LEVEL 3 /* level masked by PS.EXCM */
- /* (always 1 in XEA1; levels 2 .. EXCM_LEVEL are "medium priority") */
-
-/* Masks of interrupts at each interrupt level: */
-#define XCHAL_INTLEVEL1_MASK 0x000000FF
-#define XCHAL_INTLEVEL2_MASK 0x00000100
-#define XCHAL_INTLEVEL3_MASK 0x00000e00
-#define XCHAL_INTLEVEL4_MASK 0x00001000
-#define XCHAL_INTLEVEL5_MASK 0x00002000
-#define XCHAL_INTLEVEL6_MASK 0x00000000
-#define XCHAL_INTLEVEL7_MASK 0x00004000
-
-/* Masks of interrupts at each range 1..n of interrupt levels: */
-#define XCHAL_INTLEVEL1_ANDBELOW_MASK 0x000000FF
-#define XCHAL_INTLEVEL2_ANDBELOW_MASK 0x000001FF
-#define XCHAL_INTLEVEL3_ANDBELOW_MASK 0x00000FFF
-#define XCHAL_INTLEVEL4_ANDBELOW_MASK 0x00001FFF
-#define XCHAL_INTLEVEL5_ANDBELOW_MASK 0x00003FFF
-#define XCHAL_INTLEVEL6_ANDBELOW_MASK 0x00003FFF
-#define XCHAL_INTLEVEL7_ANDBELOW_MASK 0x00007FFF
-
-/* Level of each interrupt: */
-#define XCHAL_INT0_LEVEL 1
-#define XCHAL_INT1_LEVEL 1
-#define XCHAL_INT2_LEVEL 1
-#define XCHAL_INT3_LEVEL 1
-
-#define XCHAL_INT4_LEVEL 1
-#define XCHAL_INT5_LEVEL 1
-#define XCHAL_INT6_LEVEL 1
-#define XCHAL_INT7_LEVEL 1
-
-#define XCHAL_INT8_LEVEL 2
-#define XCHAL_INT9_LEVEL 3
-#define XCHAL_INT10_LEVEL 3
-#define XCHAL_INT11_LEVEL 3
-
-#define XCHAL_INT12_LEVEL 4
-#define XCHAL_INT13_LEVEL 5
-#define XCHAL_INT14_LEVEL 7
-
-#define XCHAL_DEBUGLEVEL 6 /* debug interrupt level */
-#define XCHAL_HAVE_DEBUG_EXTERN_INT 1 /* OCD external db interrupt */
-#define XCHAL_NMILEVEL 7 /* NMI "level" (for use with
- EXCSAVE/EPS/EPC_n, RFI n) */
-
-/* Type of each interrupt: */
-#define XCHAL_INT0_TYPE XTHAL_INTTYPE_EXTERN_LEVEL
-#define XCHAL_INT1_TYPE XTHAL_INTTYPE_EXTERN_LEVEL
-#define XCHAL_INT2_TYPE XTHAL_INTTYPE_EXTERN_LEVEL
-#define XCHAL_INT3_TYPE XTHAL_INTTYPE_EXTERN_LEVEL
-#define XCHAL_INT4_TYPE XTHAL_INTTYPE_EXTERN_LEVEL
-#define XCHAL_INT5_TYPE XTHAL_INTTYPE_EXTERN_LEVEL
-#define XCHAL_INT6_TYPE XTHAL_INTTYPE_TIMER
-#define XCHAL_INT7_TYPE XTHAL_INTTYPE_SOFTWARE
-#define XCHAL_INT8_TYPE XTHAL_INTTYPE_EXTERN_LEVEL
-#define XCHAL_INT9_TYPE XTHAL_INTTYPE_EXTERN_LEVEL
-#define XCHAL_INT10_TYPE XTHAL_INTTYPE_TIMER
-#define XCHAL_INT11_TYPE XTHAL_INTTYPE_SOFTWARE
-#define XCHAL_INT12_TYPE XTHAL_INTTYPE_EXTERN_LEVEL
-#define XCHAL_INT13_TYPE XTHAL_INTTYPE_TIMER
-#define XCHAL_INT14_TYPE XTHAL_INTTYPE_NMI
-
-/* Masks of interrupts for each type of interrupt: */
-#define XCHAL_INTTYPE_MASK_UNCONFIGURED 0xFFFF8000
-#define XCHAL_INTTYPE_MASK_SOFTWARE 0x00000880
-#define XCHAL_INTTYPE_MASK_EXTERN_EDGE 0x00000000
-#define XCHAL_INTTYPE_MASK_EXTERN_LEVEL 0x0000133f
-#define XCHAL_INTTYPE_MASK_TIMER 0x00002440
-#define XCHAL_INTTYPE_MASK_NMI 0x00004000
-#define XCHAL_INTTYPE_MASK_WRITE_ERROR 0x00000000
-#define XCHAL_INTTYPE_MASK_PROFILING 0x00000000
-
-/* Interrupt numbers assigned to specific interrupt sources: */
-#define XCHAL_TIMER0_INTERRUPT 6 /* CCOMPARE0 */
-#define XCHAL_TIMER1_INTERRUPT 10 /* CCOMPARE1 */
-#define XCHAL_TIMER2_INTERRUPT 13 /* CCOMPARE2 */
-#define XCHAL_TIMER3_INTERRUPT XTHAL_TIMER_UNCONFIGURED
-#define XCHAL_NMI_INTERRUPT 14 /* non-maskable interrupt */
-
-/* Interrupt numbers for levels at which only one interrupt is configured: */
-//#define XCHAL_INTLEVEL2_NUM 8
-//#define XCHAL_INTLEVEL4_NUM 12
-//#define XCHAL_INTLEVEL5_NUM 13
-#define XCHAL_INTLEVEL7_NUM 14
-/* (There are many interrupts each at level(s) 1, 3.) */
-
-
-/*
- * External interrupt mapping.
- * These macros describe how Xtensa processor interrupt numbers
- * (as numbered internally, eg. in INTERRUPT and INTENABLE registers)
- * map to external BInterrupt<n> pins, for those interrupts
- * configured as external (level-triggered, edge-triggered, or NMI).
- * See the Xtensa processor databook for more details.
- */
-
-/* Core interrupt numbers mapped to each EXTERNAL BInterrupt pin number: */
-#define XCHAL_EXTINT0_NUM 0 /* (intlevel 1) */
-#define XCHAL_EXTINT1_NUM 1 /* (intlevel 1) */
-#define XCHAL_EXTINT2_NUM 2 /* (intlevel 1) */
-#define XCHAL_EXTINT3_NUM 3 /* (intlevel 1) */
-#define XCHAL_EXTINT4_NUM 4 /* (intlevel 1) */
-#define XCHAL_EXTINT5_NUM 5 /* (intlevel 1) */
-#define XCHAL_EXTINT6_NUM 8 /* (intlevel 2) */
-#define XCHAL_EXTINT7_NUM 9 /* (intlevel 3) */
-#define XCHAL_EXTINT8_NUM 12 /* (intlevel 4) */
-#define XCHAL_EXTINT9_NUM 14 /* (intlevel 7) */
-#define XCHAL_EXTINT10_NUM 15 /* (intlevel 1) */
-#define XCHAL_EXTINT11_NUM 16 /* (intlevel 1) */
-#define XCHAL_EXTINT12_NUM 17 /* (intlevel 1) */
-#define XCHAL_EXTINT13_NUM 18 /* (intlevel 1) */
-#define XCHAL_EXTINT14_NUM 19 /* (intlevel 1) */
-#define XCHAL_EXTINT15_NUM 20 /* (intlevel 1) */
-#define XCHAL_EXTINT16_NUM 21 /* (intlevel 3) */
-/* EXTERNAL BInterrupt pin numbers mapped to each core interrupt number: */
-#define XCHAL_INT0_EXTNUM 0 /* (intlevel 1) */
-#define XCHAL_INT1_EXTNUM 1 /* (intlevel 1) */
-#define XCHAL_INT2_EXTNUM 2 /* (intlevel 1) */
-#define XCHAL_INT3_EXTNUM 3 /* (intlevel 1) */
-#define XCHAL_INT4_EXTNUM 4 /* (intlevel 1) */
-#define XCHAL_INT5_EXTNUM 5 /* (intlevel 1) */
-#define XCHAL_INT8_EXTNUM 6 /* (intlevel 2) */
-#define XCHAL_INT9_EXTNUM 7 /* (intlevel 3) */
-#define XCHAL_INT12_EXTNUM 8 /* (intlevel 4) */
-#define XCHAL_INT14_EXTNUM 9 /* (intlevel 7) */
-#define XCHAL_INT15_EXTNUM 10 /* (intlevel 1) */
-#define XCHAL_INT16_EXTNUM 11 /* (intlevel 1) */
-#define XCHAL_INT17_EXTNUM 12 /* (intlevel 1) */
-#define XCHAL_INT18_EXTNUM 13 /* (intlevel 1) */
-#define XCHAL_INT19_EXTNUM 14 /* (intlevel 1) */
-#define XCHAL_INT20_EXTNUM 15 /* (intlevel 1) */
-#define XCHAL_INT21_EXTNUM 16 /* (intlevel 3) */
-
-
-/*----------------------------------------------------------------------
- EXCEPTIONS and VECTORS
- ----------------------------------------------------------------------*/
-
-#define XCHAL_XEA_VERSION 2 /* Xtensa Exception Architecture
- number: 1 == XEA1 (old)
- 2 == XEA2 (new)
- 0 == XEAX (extern) or TX */
-#define XCHAL_HAVE_XEA1 0 /* Exception Architecture 1 */
-#define XCHAL_HAVE_XEA2 1 /* Exception Architecture 2 */
-#define XCHAL_HAVE_XEAX 0 /* External Exception Arch. */
-#define XCHAL_HAVE_EXCEPTIONS 1 /* exception option */
-#define XCHAL_HAVE_HALT 0 /* halt architecture option */
-#define XCHAL_HAVE_BOOTLOADER 0 /* boot loader (for TX) */
-#define XCHAL_HAVE_MEM_ECC_PARITY 0 /* local memory ECC/parity */
-#define XCHAL_HAVE_VECTOR_SELECT 0 /* relocatable vectors */
-#define XCHAL_HAVE_VECBASE 0 /* relocatable vectors */
-#define XCHAL_VECBASE_RESET_VADDR 0x00000400 /* VECBASE reset value */
-#define XCHAL_VECBASE_RESET_PADDR 0x00000400
-#define XCHAL_RESET_VECBASE_OVERLAP 0
-
-#define XCHAL_RESET_VECTOR0_VADDR 0x00000000
-#define XCHAL_RESET_VECTOR0_PADDR 0x00000000
-#define XCHAL_RESET_VECTOR1_VADDR 0x00000000
-#define XCHAL_RESET_VECTOR1_PADDR 0x00000000
-#define XCHAL_RESET_VECTOR_VADDR 0x00000000
-#define XCHAL_RESET_VECTOR_PADDR 0x00000000
-#define XCHAL_USER_VECOFS 0x000005c0
-#define XCHAL_USER_VECTOR_VADDR 0x000005c0
-#define XCHAL_USER_VECTOR_PADDR 0x000005c0
-#define XCHAL_KERNEL_VECOFS 0x00000584
-#define XCHAL_KERNEL_VECTOR_VADDR 0x00000584
-#define XCHAL_KERNEL_VECTOR_PADDR 0x00000584
-#define XCHAL_DOUBLEEXC_VECOFS 0x000005fc
-#define XCHAL_DOUBLEEXC_VECTOR_VADDR 0x000005fc
-#define XCHAL_DOUBLEEXC_VECTOR_PADDR 0x000005fc
-#define XCHAL_WINDOW_OF4_VECOFS 0x00000000
-#define XCHAL_WINDOW_UF4_VECOFS 0x00000040
-#define XCHAL_WINDOW_OF8_VECOFS 0x00000080
-#define XCHAL_WINDOW_UF8_VECOFS 0x000000C0
-#define XCHAL_WINDOW_OF12_VECOFS 0x00000100
-#define XCHAL_WINDOW_UF12_VECOFS 0x00000140
-#define XCHAL_WINDOW_VECTORS_VADDR 0x00000400
-#define XCHAL_WINDOW_VECTORS_PADDR 0x00000400
-#define XCHAL_INTLEVEL2_VECOFS 0x00000640
-#define XCHAL_INTLEVEL2_VECTOR_VADDR 0x00000640
-#define XCHAL_INTLEVEL2_VECTOR_PADDR 0x00000640
-#define XCHAL_INTLEVEL3_VECOFS 0x0000067c
-#define XCHAL_INTLEVEL3_VECTOR_VADDR 0x0000067c
-#define XCHAL_INTLEVEL3_VECTOR_PADDR 0x0000067c
-#define XCHAL_INTLEVEL4_VECOFS 0x000006b8
-#define XCHAL_INTLEVEL4_VECTOR_VADDR 0x000006b8
-#define XCHAL_INTLEVEL4_VECTOR_PADDR 0x000006b8
-#define XCHAL_INTLEVEL5_VECOFS 0x000006f4
-#define XCHAL_INTLEVEL5_VECTOR_VADDR 0x000006f4
-#define XCHAL_INTLEVEL5_VECTOR_PADDR 0x000006f4
-#define XCHAL_INTLEVEL6_VECOFS 0x00000730
-#define XCHAL_INTLEVEL6_VECTOR_VADDR 0x00000730
-#define XCHAL_INTLEVEL6_VECTOR_PADDR 0x00000730
-#define XCHAL_DEBUG_VECOFS XCHAL_INTLEVEL6_VECOFS
-#define XCHAL_DEBUG_VECTOR_VADDR XCHAL_INTLEVEL6_VECTOR_VADDR
-#define XCHAL_DEBUG_VECTOR_PADDR XCHAL_INTLEVEL6_VECTOR_PADDR
-#define XCHAL_NMI_VECOFS 0x0000076c
-#define XCHAL_NMI_VECTOR_VADDR 0x0000076c
-#define XCHAL_NMI_VECTOR_PADDR 0x0000076c
-#define XCHAL_INTLEVEL7_VECOFS XCHAL_NMI_VECOFS
-#define XCHAL_INTLEVEL7_VECTOR_VADDR XCHAL_NMI_VECTOR_VADDR
-#define XCHAL_INTLEVEL7_VECTOR_PADDR XCHAL_NMI_VECTOR_PADDR
-
-
-/*----------------------------------------------------------------------
- DEBUG MODULE
- ----------------------------------------------------------------------*/
-
-/* Misc */
-#define XCHAL_HAVE_DEBUG_ERI 0 /* ERI to debug module */
-#define XCHAL_HAVE_DEBUG_APB 0 /* APB to debug module */
-#define XCHAL_HAVE_DEBUG_JTAG 1 /* JTAG to debug module */
-
-/* On-Chip Debug (OCD) */
-#define XCHAL_HAVE_OCD 1 /* OnChipDebug option */
-#define XCHAL_NUM_IBREAK 2 /* number of IBREAKn regs */
-#define XCHAL_NUM_DBREAK 2 /* number of DBREAKn regs */
-#define XCHAL_HAVE_OCD_DIR_ARRAY 1 /* faster OCD option (to LX4) */
-#define XCHAL_HAVE_OCD_LS32DDR 1 /* L32DDR/S32DDR (faster OCD) */
-
-/* TRAX (in core) */
-#define XCHAL_HAVE_TRAX 0 /* TRAX in debug module */
-#define XCHAL_TRAX_MEM_SIZE 0 /* TRAX memory size in bytes */
-#define XCHAL_TRAX_MEM_SHAREABLE 0 /* start/end regs; ready sig. */
-#define XCHAL_TRAX_ATB_WIDTH 0 /* ATB width (bits), 0=no ATB */
-#define XCHAL_TRAX_TIME_WIDTH 0 /* timestamp bitwidth, 0=none */
-
-/* Perf counters */
-#define XCHAL_NUM_PERF_COUNTERS 0 /* performance counters */
-
-
-/*----------------------------------------------------------------------
- MMU
- ----------------------------------------------------------------------*/
-
-/* See core-matmap.h header file for more details. */
-
-#define XCHAL_HAVE_TLBS 1 /* inverse of HAVE_CACHEATTR */
-#define XCHAL_HAVE_SPANNING_WAY 1 /* one way maps I+D 4GB vaddr */
-#define XCHAL_SPANNING_WAY 0 /* TLB spanning way number */
-#define XCHAL_HAVE_IDENTITY_MAP 0 /* vaddr == paddr always */
-#define XCHAL_HAVE_CACHEATTR 0 /* CACHEATTR register present */
-#define XCHAL_HAVE_MIMIC_CACHEATTR 1 /* region protection */
-#define XCHAL_HAVE_XLT_CACHEATTR 0 /* region prot. w/translation */
-#define XCHAL_HAVE_PTP_MMU 0 /* full MMU (with page table
- [autorefill] and protection)
- usable for an MMU-based OS */
-/* If none of the above last 4 are set, it's a custom TLB configuration. */
-
-#define XCHAL_MMU_ASID_BITS 0 /* number of bits in ASIDs */
-#define XCHAL_MMU_RINGS 1 /* number of rings (1..4) */
-#define XCHAL_MMU_RING_BITS 0 /* num of bits in RING field */
-
-#endif /* !XTENSA_HAL_NON_PRIVILEGED_ONLY */
-
-
-#endif /* _XTENSA_CORE_CONFIGURATION_H */
-
diff --git a/src/platform/haswell/include/arch/xtensa/config/core-isa.h b/src/platform/haswell/include/arch/xtensa/config/core-isa.h
deleted file mode 100644
index 00a8b7d..0000000
--- a/src/platform/haswell/include/arch/xtensa/config/core-isa.h
+++ /dev/null
@@ -1,9 +0,0 @@
-#include <config.h>
-
-#ifdef CONFIG_HASWELL
-#include <xtensa/config/core-isa-hsw.h>
-#elif CONFIG_BROADWELL
-#include <xtensa/config/core-isa-bdw.h>
-#else
-#error "No ISA configuration selected"
-#endif
diff --git a/src/platform/haswell/include/arch/xtensa/config/core-matmap.h b/src/platform/haswell/include/arch/xtensa/config/core-matmap.h
deleted file mode 100644
index 5c6fffe..0000000
--- a/src/platform/haswell/include/arch/xtensa/config/core-matmap.h
+++ /dev/null
@@ -1,314 +0,0 @@
-/*
- * xtensa/config/core-matmap.h -- Memory access and translation mapping
- * parameters (CHAL) of the Xtensa processor core configuration.
- *
- * If you are using Xtensa Tools, see <xtensa/config/core.h> (which includes
- * this file) for more details.
- *
- * In the Xtensa processor products released to date, all parameters
- * defined in this file are derivable (at least in theory) from
- * information contained in the core-isa.h header file.
- * In particular, the following core configuration parameters are relevant:
- * XCHAL_HAVE_CACHEATTR
- * XCHAL_HAVE_MIMIC_CACHEATTR
- * XCHAL_HAVE_XLT_CACHEATTR
- * XCHAL_HAVE_PTP_MMU
- * XCHAL_ITLB_ARF_ENTRIES_LOG2
- * XCHAL_DTLB_ARF_ENTRIES_LOG2
- * XCHAL_DCACHE_IS_WRITEBACK
- * XCHAL_ICACHE_SIZE (presence of I-cache)
- * XCHAL_DCACHE_SIZE (presence of D-cache)
- * XCHAL_HW_VERSION_MAJOR
- * XCHAL_HW_VERSION_MINOR
- */
-
-/* Customer ID=4313; Build=0x5483b; Copyright (c) 1999-2015 Tensilica Inc.
-
- Permission is hereby granted, free of charge, to any person obtaining
- a copy of this software and associated documentation files (the
- "Software"), to deal in the Software without restriction, including
- without limitation the rights to use, copy, modify, merge, publish,
- distribute, sublicense, and/or sell copies of the Software, and to
- permit persons to whom the Software is furnished to do so, subject to
- the following conditions:
-
- The above copyright notice and this permission notice shall be included
- in all copies or substantial portions of the Software.
-
- THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
- EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
- MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
- IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY
- CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
- TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
- SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. */
-
-
-#ifndef XTENSA_CONFIG_CORE_MATMAP_H
-#define XTENSA_CONFIG_CORE_MATMAP_H
-
-
-/*----------------------------------------------------------------------
- CACHE (MEMORY ACCESS) ATTRIBUTES
- ----------------------------------------------------------------------*/
-
-
-/* Cache Attribute encodings -- lists of access modes for each cache attribute: */
-#define XCHAL_FCA_LIST XTHAL_FAM_EXCEPTION XCHAL_SEP \
- XTHAL_FAM_CACHED XCHAL_SEP \
- XTHAL_FAM_BYPASS XCHAL_SEP \
- XTHAL_FAM_CACHED XCHAL_SEP \
- XTHAL_FAM_CACHED XCHAL_SEP \
- XTHAL_FAM_CACHED XCHAL_SEP \
- XTHAL_FAM_BYPASS XCHAL_SEP \
- XTHAL_FAM_EXCEPTION XCHAL_SEP \
- XTHAL_FAM_EXCEPTION XCHAL_SEP \
- XTHAL_FAM_EXCEPTION XCHAL_SEP \
- XTHAL_FAM_EXCEPTION XCHAL_SEP \
- XTHAL_FAM_EXCEPTION XCHAL_SEP \
- XTHAL_FAM_EXCEPTION XCHAL_SEP \
- XTHAL_FAM_EXCEPTION XCHAL_SEP \
- XTHAL_FAM_EXCEPTION XCHAL_SEP \
- XTHAL_FAM_EXCEPTION
-#define XCHAL_LCA_LIST XTHAL_LAM_CACHED_NOALLOC XCHAL_SEP \
- XTHAL_LAM_CACHED XCHAL_SEP \
- XTHAL_LAM_BYPASSG XCHAL_SEP \
- XTHAL_LAM_EXCEPTION XCHAL_SEP \
- XTHAL_LAM_CACHED XCHAL_SEP \
- XTHAL_LAM_CACHED XCHAL_SEP \
- XTHAL_LAM_BYPASSG XCHAL_SEP \
- XTHAL_LAM_EXCEPTION XCHAL_SEP \
- XTHAL_LAM_EXCEPTION XCHAL_SEP \
- XTHAL_LAM_EXCEPTION XCHAL_SEP \
- XTHAL_LAM_EXCEPTION XCHAL_SEP \
- XTHAL_LAM_EXCEPTION XCHAL_SEP \
- XTHAL_LAM_EXCEPTION XCHAL_SEP \
- XTHAL_LAM_EXCEPTION XCHAL_SEP \
- XTHAL_LAM_ISOLATE XCHAL_SEP \
- XTHAL_LAM_EXCEPTION
-#define XCHAL_SCA_LIST XTHAL_SAM_WRITETHRU XCHAL_SEP \
- XTHAL_SAM_WRITETHRU XCHAL_SEP \
- XTHAL_SAM_BYPASS XCHAL_SEP \
- XTHAL_SAM_EXCEPTION XCHAL_SEP \
- XTHAL_SAM_WRITEBACK XCHAL_SEP \
- XTHAL_SAM_WRITEBACK_NOALLOC XCHAL_SEP \
- XTHAL_SAM_BYPASS XCHAL_SEP \
- XTHAL_SAM_EXCEPTION XCHAL_SEP \
- XTHAL_SAM_EXCEPTION XCHAL_SEP \
- XTHAL_SAM_EXCEPTION XCHAL_SEP \
- XTHAL_SAM_EXCEPTION XCHAL_SEP \
- XTHAL_SAM_EXCEPTION XCHAL_SEP \
- XTHAL_SAM_EXCEPTION XCHAL_SEP \
- XTHAL_SAM_EXCEPTION XCHAL_SEP \
- XTHAL_SAM_ISOLATE XCHAL_SEP \
- XTHAL_SAM_EXCEPTION
-
-
-/*
- * Specific encoded cache attribute values of general interest.
- * If a specific cache mode is not available, the closest available
- * one is returned instead (eg. writethru instead of writeback,
- * bypass instead of writethru).
- */
-#define XCHAL_CA_BYPASS 2 /* cache disabled (bypassed) mode */
-#define XCHAL_CA_BYPASSBUF 6 /* cache disabled (bypassed) bufferable mode */
-#define XCHAL_CA_WRITETHRU 1 /* cache enabled (write-through) mode */
-#define XCHAL_CA_WRITEBACK 4 /* cache enabled (write-back) mode */
-#define XCHAL_HAVE_CA_WRITEBACK_NOALLOC 1 /* write-back no-allocate availability */
-#define XCHAL_CA_WRITEBACK_NOALLOC 5 /* cache enabled (write-back no-allocate) mode */
-#define XCHAL_CA_ILLEGAL 15 /* no access allowed (all cause exceptions) mode */
-#define XCHAL_CA_ISOLATE 14 /* cache isolate (accesses go to cache not memory) mode */
-
-
-/*----------------------------------------------------------------------
- MMU
- ----------------------------------------------------------------------*/
-
-/*
- * General notes on MMU parameters.
- *
- * Terminology:
- * ASID = address-space ID (acts as an "extension" of virtual addresses)
- * VPN = virtual page number
- * PPN = physical page number
- * CA = encoded cache attribute (access modes)
- * TLB = translation look-aside buffer (term is stretched somewhat here)
- * I = instruction (fetch accesses)
- * D = data (load and store accesses)
- * way = each TLB (ITLB and DTLB) consists of a number of "ways"
- * that simultaneously match the virtual address of an access;
- * a TLB successfully translates a virtual address if exactly
- * one way matches the vaddr; if none match, it is a miss;
- * if multiple match, one gets a "multihit" exception;
- * each way can be independently configured in terms of number of
- * entries, page sizes, which fields are writable or constant, etc.
- * set = group of contiguous ways with exactly identical parameters
- * ARF = auto-refill; hardware services a 1st-level miss by loading a PTE
- * from the page table and storing it in one of the auto-refill ways;
- * if this PTE load also misses, a miss exception is posted for s/w.
- * min-wired = a "min-wired" way can be used to map a single (minimum-sized)
- * page arbitrarily under program control; it has a single entry,
- * is non-auto-refill (some other way(s) must be auto-refill),
- * all its fields (VPN, PPN, ASID, CA) are all writable, and it
- * supports the XCHAL_MMU_MIN_PTE_PAGE_SIZE page size (a current
- * restriction is that this be the only page size it supports).
- *
- * TLB way entries are virtually indexed.
- * TLB ways that support multiple page sizes:
- * - must have all writable VPN and PPN fields;
- * - can only use one page size at any given time (eg. setup at startup),
- * selected by the respective ITLBCFG or DTLBCFG special register,
- * whose bits n*4+3 .. n*4 index the list of page sizes for way n
- * (XCHAL_xTLB_SETm_PAGESZ_LOG2_LIST for set m corresponding to way n);
- * this list may be sparse for auto-refill ways because auto-refill
- * ways have independent lists of supported page sizes sharing a
- * common encoding with PTE entries; the encoding is the index into
- * this list; unsupported sizes for a given way are zero in the list;
- * selecting unsupported sizes results in undefined hardware behaviour;
- * - is only possible for ways 0 thru 7 (due to ITLBCFG/DTLBCFG definition).
- */
-
-#define XCHAL_MMU_ASID_INVALID 0 /* ASID value indicating invalid address space */
-#define XCHAL_MMU_ASID_KERNEL 0 /* ASID value indicating kernel (ring 0) address space */
-#define XCHAL_MMU_SR_BITS 0 /* number of size-restriction bits supported */
-#define XCHAL_MMU_CA_BITS 4 /* number of bits needed to hold cache attribute encoding */
-#define XCHAL_MMU_MAX_PTE_PAGE_SIZE 29 /* max page size in a PTE structure (log2) */
-#define XCHAL_MMU_MIN_PTE_PAGE_SIZE 29 /* min page size in a PTE structure (log2) */
-
-
-/*** Instruction TLB: ***/
-
-#define XCHAL_ITLB_WAY_BITS 0 /* number of bits holding the ways */
-#define XCHAL_ITLB_WAYS 1 /* number of ways (n-way set-associative TLB) */
-#define XCHAL_ITLB_ARF_WAYS 0 /* number of auto-refill ways */
-#define XCHAL_ITLB_SETS 1 /* number of sets (groups of ways with identical settings) */
-
-/* Way set to which each way belongs: */
-#define XCHAL_ITLB_WAY0_SET 0
-
-/* Ways sets that are used by hardware auto-refill (ARF): */
-#define XCHAL_ITLB_ARF_SETS 0 /* number of auto-refill sets */
-
-/* Way sets that are "min-wired" (see terminology comment above): */
-#define XCHAL_ITLB_MINWIRED_SETS 0 /* number of "min-wired" sets */
-
-
-/* ITLB way set 0 (group of ways 0 thru 0): */
-#define XCHAL_ITLB_SET0_WAY 0 /* index of first way in this way set */
-#define XCHAL_ITLB_SET0_WAYS 1 /* number of (contiguous) ways in this way set */
-#define XCHAL_ITLB_SET0_ENTRIES_LOG2 3 /* log2(number of entries in this way) */
-#define XCHAL_ITLB_SET0_ENTRIES 8 /* number of entries in this way (always a power of 2) */
-#define XCHAL_ITLB_SET0_ARF 0 /* 1=autorefill by h/w, 0=non-autorefill (wired/constant/static) */
-#define XCHAL_ITLB_SET0_PAGESIZES 1 /* number of supported page sizes in this way */
-#define XCHAL_ITLB_SET0_PAGESZ_BITS 0 /* number of bits to encode the page size */
-#define XCHAL_ITLB_SET0_PAGESZ_LOG2_MIN 29 /* log2(minimum supported page size) */
-#define XCHAL_ITLB_SET0_PAGESZ_LOG2_MAX 29 /* log2(maximum supported page size) */
-#define XCHAL_ITLB_SET0_PAGESZ_LOG2_LIST 29 /* list of log2(page size)s, separated by XCHAL_SEP;
- 2^PAGESZ_BITS entries in list, unsupported entries are zero */
-#define XCHAL_ITLB_SET0_ASID_CONSTMASK 0 /* constant ASID bits; 0 if all writable */
-#define XCHAL_ITLB_SET0_VPN_CONSTMASK 0x00000000 /* constant VPN bits, not including entry index bits; 0 if all writable */
-#define XCHAL_ITLB_SET0_PPN_CONSTMASK 0xE0000000 /* constant PPN bits, including entry index bits; 0 if all writable */
-#define XCHAL_ITLB_SET0_CA_CONSTMASK 0 /* constant CA bits; 0 if all writable */
-#define XCHAL_ITLB_SET0_ASID_RESET 0 /* 1 if ASID reset values defined (and all writable); 0 otherwise */
-#define XCHAL_ITLB_SET0_VPN_RESET 0 /* 1 if VPN reset values defined (and all writable); 0 otherwise */
-#define XCHAL_ITLB_SET0_PPN_RESET 0 /* 1 if PPN reset values defined (and all writable); 0 otherwise */
-#define XCHAL_ITLB_SET0_CA_RESET 1 /* 1 if CA reset values defined (and all writable); 0 otherwise */
-/* Constant VPN values for each entry of ITLB way set 0 (because VPN_CONSTMASK is non-zero): */
-#define XCHAL_ITLB_SET0_E0_VPN_CONST 0x00000000
-#define XCHAL_ITLB_SET0_E1_VPN_CONST 0x20000000
-#define XCHAL_ITLB_SET0_E2_VPN_CONST 0x40000000
-#define XCHAL_ITLB_SET0_E3_VPN_CONST 0x60000000
-#define XCHAL_ITLB_SET0_E4_VPN_CONST 0x80000000
-#define XCHAL_ITLB_SET0_E5_VPN_CONST 0xA0000000
-#define XCHAL_ITLB_SET0_E6_VPN_CONST 0xC0000000
-#define XCHAL_ITLB_SET0_E7_VPN_CONST 0xE0000000
-/* Constant PPN values for each entry of ITLB way set 0 (because PPN_CONSTMASK is non-zero): */
-#define XCHAL_ITLB_SET0_E0_PPN_CONST 0x00000000
-#define XCHAL_ITLB_SET0_E1_PPN_CONST 0x20000000
-#define XCHAL_ITLB_SET0_E2_PPN_CONST 0x40000000
-#define XCHAL_ITLB_SET0_E3_PPN_CONST 0x60000000
-#define XCHAL_ITLB_SET0_E4_PPN_CONST 0x80000000
-#define XCHAL_ITLB_SET0_E5_PPN_CONST 0xA0000000
-#define XCHAL_ITLB_SET0_E6_PPN_CONST 0xC0000000
-#define XCHAL_ITLB_SET0_E7_PPN_CONST 0xE0000000
-/* Reset CA values for each entry of ITLB way set 0 (because SET0_CA_RESET is non-zero): */
-#define XCHAL_ITLB_SET0_E0_CA_RESET 0x02
-#define XCHAL_ITLB_SET0_E1_CA_RESET 0x02
-#define XCHAL_ITLB_SET0_E2_CA_RESET 0x02
-#define XCHAL_ITLB_SET0_E3_CA_RESET 0x02
-#define XCHAL_ITLB_SET0_E4_CA_RESET 0x02
-#define XCHAL_ITLB_SET0_E5_CA_RESET 0x02
-#define XCHAL_ITLB_SET0_E6_CA_RESET 0x02
-#define XCHAL_ITLB_SET0_E7_CA_RESET 0x02
-
-
-/*** Data TLB: ***/
-
-#define XCHAL_DTLB_WAY_BITS 0 /* number of bits holding the ways */
-#define XCHAL_DTLB_WAYS 1 /* number of ways (n-way set-associative TLB) */
-#define XCHAL_DTLB_ARF_WAYS 0 /* number of auto-refill ways */
-#define XCHAL_DTLB_SETS 1 /* number of sets (groups of ways with identical settings) */
-
-/* Way set to which each way belongs: */
-#define XCHAL_DTLB_WAY0_SET 0
-
-/* Ways sets that are used by hardware auto-refill (ARF): */
-#define XCHAL_DTLB_ARF_SETS 0 /* number of auto-refill sets */
-
-/* Way sets that are "min-wired" (see terminology comment above): */
-#define XCHAL_DTLB_MINWIRED_SETS 0 /* number of "min-wired" sets */
-
-
-/* DTLB way set 0 (group of ways 0 thru 0): */
-#define XCHAL_DTLB_SET0_WAY 0 /* index of first way in this way set */
-#define XCHAL_DTLB_SET0_WAYS 1 /* number of (contiguous) ways in this way set */
-#define XCHAL_DTLB_SET0_ENTRIES_LOG2 3 /* log2(number of entries in this way) */
-#define XCHAL_DTLB_SET0_ENTRIES 8 /* number of entries in this way (always a power of 2) */
-#define XCHAL_DTLB_SET0_ARF 0 /* 1=autorefill by h/w, 0=non-autorefill (wired/constant/static) */
-#define XCHAL_DTLB_SET0_PAGESIZES 1 /* number of supported page sizes in this way */
-#define XCHAL_DTLB_SET0_PAGESZ_BITS 0 /* number of bits to encode the page size */
-#define XCHAL_DTLB_SET0_PAGESZ_LOG2_MIN 29 /* log2(minimum supported page size) */
-#define XCHAL_DTLB_SET0_PAGESZ_LOG2_MAX 29 /* log2(maximum supported page size) */
-#define XCHAL_DTLB_SET0_PAGESZ_LOG2_LIST 29 /* list of log2(page size)s, separated by XCHAL_SEP;
- 2^PAGESZ_BITS entries in list, unsupported entries are zero */
-#define XCHAL_DTLB_SET0_ASID_CONSTMASK 0 /* constant ASID bits; 0 if all writable */
-#define XCHAL_DTLB_SET0_VPN_CONSTMASK 0x00000000 /* constant VPN bits, not including entry index bits; 0 if all writable */
-#define XCHAL_DTLB_SET0_PPN_CONSTMASK 0xE0000000 /* constant PPN bits, including entry index bits; 0 if all writable */
-#define XCHAL_DTLB_SET0_CA_CONSTMASK 0 /* constant CA bits; 0 if all writable */
-#define XCHAL_DTLB_SET0_ASID_RESET 0 /* 1 if ASID reset values defined (and all writable); 0 otherwise */
-#define XCHAL_DTLB_SET0_VPN_RESET 0 /* 1 if VPN reset values defined (and all writable); 0 otherwise */
-#define XCHAL_DTLB_SET0_PPN_RESET 0 /* 1 if PPN reset values defined (and all writable); 0 otherwise */
-#define XCHAL_DTLB_SET0_CA_RESET 1 /* 1 if CA reset values defined (and all writable); 0 otherwise */
-/* Constant VPN values for each entry of DTLB way set 0 (because VPN_CONSTMASK is non-zero): */
-#define XCHAL_DTLB_SET0_E0_VPN_CONST 0x00000000
-#define XCHAL_DTLB_SET0_E1_VPN_CONST 0x20000000
-#define XCHAL_DTLB_SET0_E2_VPN_CONST 0x40000000
-#define XCHAL_DTLB_SET0_E3_VPN_CONST 0x60000000
-#define XCHAL_DTLB_SET0_E4_VPN_CONST 0x80000000
-#define XCHAL_DTLB_SET0_E5_VPN_CONST 0xA0000000
-#define XCHAL_DTLB_SET0_E6_VPN_CONST 0xC0000000
-#define XCHAL_DTLB_SET0_E7_VPN_CONST 0xE0000000
-/* Constant PPN values for each entry of DTLB way set 0 (because PPN_CONSTMASK is non-zero): */
-#define XCHAL_DTLB_SET0_E0_PPN_CONST 0x00000000
-#define XCHAL_DTLB_SET0_E1_PPN_CONST 0x20000000
-#define XCHAL_DTLB_SET0_E2_PPN_CONST 0x40000000
-#define XCHAL_DTLB_SET0_E3_PPN_CONST 0x60000000
-#define XCHAL_DTLB_SET0_E4_PPN_CONST 0x80000000
-#define XCHAL_DTLB_SET0_E5_PPN_CONST 0xA0000000
-#define XCHAL_DTLB_SET0_E6_PPN_CONST 0xC0000000
-#define XCHAL_DTLB_SET0_E7_PPN_CONST 0xE0000000
-/* Reset CA values for each entry of DTLB way set 0 (because SET0_CA_RESET is non-zero): */
-#define XCHAL_DTLB_SET0_E0_CA_RESET 0x02
-#define XCHAL_DTLB_SET0_E1_CA_RESET 0x02
-#define XCHAL_DTLB_SET0_E2_CA_RESET 0x02
-#define XCHAL_DTLB_SET0_E3_CA_RESET 0x02
-#define XCHAL_DTLB_SET0_E4_CA_RESET 0x02
-#define XCHAL_DTLB_SET0_E5_CA_RESET 0x02
-#define XCHAL_DTLB_SET0_E6_CA_RESET 0x02
-#define XCHAL_DTLB_SET0_E7_CA_RESET 0x02
-
-
-
-
-#endif /*XTENSA_CONFIG_CORE_MATMAP_H*/
-
diff --git a/src/platform/haswell/include/arch/xtensa/config/defs.h b/src/platform/haswell/include/arch/xtensa/config/defs.h
deleted file mode 100644
index b695e59..0000000
--- a/src/platform/haswell/include/arch/xtensa/config/defs.h
+++ /dev/null
@@ -1,38 +0,0 @@
-/* Definitions for Xtensa instructions, types, and protos. */
-
-/* Customer ID=4313; Build=0x5483b; Copyright (c) 2003-2004 Tensilica Inc.
-
- Permission is hereby granted, free of charge, to any person obtaining
- a copy of this software and associated documentation files (the
- "Software"), to deal in the Software without restriction, including
- without limitation the rights to use, copy, modify, merge, publish,
- distribute, sublicense, and/or sell copies of the Software, and to
- permit persons to whom the Software is furnished to do so, subject to
- the following conditions:
-
- The above copyright notice and this permission notice shall be included
- in all copies or substantial portions of the Software.
-
- THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
- EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
- MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
- IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY
- CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
- TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
- SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. */
-
-/* NOTE: This file exists only for backward compatibility with T1050
- and earlier Xtensa releases. It includes only a subset of the
- available header files. */
-
-#ifndef _XTENSA_BASE_HEADER
-#define _XTENSA_BASE_HEADER
-
-#ifdef __XTENSA__
-
-#include <xtensa/tie/xt_core.h>
-#include <xtensa/tie/xt_misc.h>
-#include <xtensa/tie/xt_booleans.h>
-
-#endif /* __XTENSA__ */
-#endif /* !_XTENSA_BASE_HEADER */
diff --git a/src/platform/haswell/include/arch/xtensa/config/specreg.h b/src/platform/haswell/include/arch/xtensa/config/specreg.h
deleted file mode 100644
index 89bfe16..0000000
--- a/src/platform/haswell/include/arch/xtensa/config/specreg.h
+++ /dev/null
@@ -1,107 +0,0 @@
-/*
- * Xtensa Special Register symbolic names
- */
-
-/* $Id: //depot/rel/Eaglenest/Xtensa/SWConfig/hal/specreg.h.tpp#1 $ */
-
-/* Customer ID=4313; Build=0x5483b; Copyright (c) 1998-2002 Tensilica Inc.
-
- Permission is hereby granted, free of charge, to any person obtaining
- a copy of this software and associated documentation files (the
- "Software"), to deal in the Software without restriction, including
- without limitation the rights to use, copy, modify, merge, publish,
- distribute, sublicense, and/or sell copies of the Software, and to
- permit persons to whom the Software is furnished to do so, subject to
- the following conditions:
-
- The above copyright notice and this permission notice shall be included
- in all copies or substantial portions of the Software.
-
- THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
- EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
- MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
- IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY
- CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
- TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
- SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. */
-
-#ifndef XTENSA_SPECREG_H
-#define XTENSA_SPECREG_H
-
-/* Include these special register bitfield definitions, for historical reasons: */
-#include <xtensa/corebits.h>
-
-
-/* Special registers: */
-#define LBEG 0
-#define LEND 1
-#define LCOUNT 2
-#define SAR 3
-#define BR 4
-#define SCOMPARE1 12
-#define WINDOWBASE 72
-#define WINDOWSTART 73
-#define IBREAKENABLE 96
-#define ATOMCTL 99
-#define DDR 104
-#define IBREAKA_0 128
-#define IBREAKA_1 129
-#define DBREAKA_0 144
-#define DBREAKA_1 145
-#define DBREAKC_0 160
-#define DBREAKC_1 161
-#define EPC_1 177
-#define EPC_2 178
-#define EPC_3 179
-#define EPC_4 180
-#define EPC_5 181
-#define EPC_6 182
-#define EPC_7 183
-#define DEPC 192
-#define EPS_2 194
-#define EPS_3 195
-#define EPS_4 196
-#define EPS_5 197
-#define EPS_6 198
-#define EPS_7 199
-#define EXCSAVE_1 209
-#define EXCSAVE_2 210
-#define EXCSAVE_3 211
-#define EXCSAVE_4 212
-#define EXCSAVE_5 213
-#define EXCSAVE_6 214
-#define EXCSAVE_7 215
-#define CPENABLE 224
-#define INTERRUPT 226
-#define INTENABLE 228
-#define PS 230
-#define VECBASE 231
-#define EXCCAUSE 232
-#define DEBUGCAUSE 233
-#define CCOUNT 234
-#define PRID 235
-#define ICOUNT 236
-#define ICOUNTLEVEL 237
-#define EXCVADDR 238
-#define CCOMPARE_0 240
-#define CCOMPARE_1 241
-#define CCOMPARE_2 242
-#define MISC_REG_0 244
-#define MISC_REG_1 245
-
-/* Special cases (bases of special register series): */
-#define IBREAKA 128
-#define DBREAKA 144
-#define DBREAKC 160
-#define EPC 176
-#define EPS 192
-#define EXCSAVE 208
-#define CCOMPARE 240
-
-/* Special names for read-only and write-only interrupt registers: */
-#define INTREAD 226
-#define INTSET 226
-#define INTCLEAR 227
-
-#endif /* XTENSA_SPECREG_H */
-
diff --git a/src/platform/haswell/include/arch/xtensa/config/system.h b/src/platform/haswell/include/arch/xtensa/config/system.h
deleted file mode 100644
index 147346a..0000000
--- a/src/platform/haswell/include/arch/xtensa/config/system.h
+++ /dev/null
@@ -1,272 +0,0 @@
-/*
- * xtensa/config/system.h -- HAL definitions that are dependent on SYSTEM configuration
- *
- * NOTE: The location and contents of this file are highly subject to change.
- *
- * Source for configuration-independent binaries (which link in a
- * configuration-specific HAL library) must NEVER include this file.
- * The HAL itself has historically included this file in some instances,
- * but this is not appropriate either, because the HAL is meant to be
- * core-specific but system independent.
- */
-
-/* Customer ID=4313; Build=0x5483b; Copyright (c) 2000-2010 Tensilica Inc.
-
- Permission is hereby granted, free of charge, to any person obtaining
- a copy of this software and associated documentation files (the
- "Software"), to deal in the Software without restriction, including
- without limitation the rights to use, copy, modify, merge, publish,
- distribute, sublicense, and/or sell copies of the Software, and to
- permit persons to whom the Software is furnished to do so, subject to
- the following conditions:
-
- The above copyright notice and this permission notice shall be included
- in all copies or substantial portions of the Software.
-
- THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
- EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
- MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
- IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY
- CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
- TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
- SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. */
-
-
-#ifndef XTENSA_CONFIG_SYSTEM_H
-#define XTENSA_CONFIG_SYSTEM_H
-
-/*#include <xtensa/hal.h>*/
-
-
-
-/*----------------------------------------------------------------------
- CONFIGURED SOFTWARE OPTIONS
- ----------------------------------------------------------------------*/
-
-#define XSHAL_USE_ABSOLUTE_LITERALS 0 /* (sw-only option, whether software uses absolute literals) */
-#define XSHAL_HAVE_TEXT_SECTION_LITERALS 1 /* Set if there is some memory that allows both code and literals. */
-
-#define XSHAL_ABI XTHAL_ABI_CALL0 /* (sw-only option, selected ABI) */
-/* The above maps to one of the following constants: */
-#define XTHAL_ABI_WINDOWED 0
-#define XTHAL_ABI_CALL0 1
-/* Alternatives: */
-/*#define XSHAL_WINDOWED_ABI 1*/ /* set if windowed ABI selected */
-/*#define XSHAL_CALL0_ABI 0*/ /* set if call0 ABI selected */
-
-#define XSHAL_CLIB XTHAL_CLIB_NEWLIB /* (sw-only option, selected C library) */
-/* The above maps to one of the following constants: */
-#define XTHAL_CLIB_NEWLIB 0
-#define XTHAL_CLIB_UCLIBC 1
-#define XTHAL_CLIB_XCLIB 2
-/* Alternatives: */
-/*#define XSHAL_NEWLIB 1*/ /* set if newlib C library selected */
-/*#define XSHAL_UCLIBC 0*/ /* set if uCLibC C library selected */
-/*#define XSHAL_XCLIB 0*/ /* set if Xtensa C library selected */
-
-#define XSHAL_USE_FLOATING_POINT 1
-
-#define XSHAL_FLOATING_POINT_ABI 0
-
-/*----------------------------------------------------------------------
- DEVICE ADDRESSES
- ----------------------------------------------------------------------*/
-
-/*
- * Strange place to find these, but the configuration GUI
- * allows moving these around to account for various core
- * configurations. Specific boards (and their BSP software)
- * will have specific meanings for these components.
- */
-
-/* I/O Block areas: */
-#define XSHAL_IOBLOCK_CACHED_VADDR 0x70000000
-#define XSHAL_IOBLOCK_CACHED_PADDR 0x70000000
-#define XSHAL_IOBLOCK_CACHED_SIZE 0x0E000000
-
-#define XSHAL_IOBLOCK_BYPASS_VADDR 0x90000000
-#define XSHAL_IOBLOCK_BYPASS_PADDR 0x90000000
-#define XSHAL_IOBLOCK_BYPASS_SIZE 0x0E000000
-
-/* System ROM: */
-#define XSHAL_ROM_VADDR 0x50000000
-#define XSHAL_ROM_PADDR 0x50000000
-#define XSHAL_ROM_SIZE 0x01000000
-/* Largest available area (free of vectors): */
-#define XSHAL_ROM_AVAIL_VADDR 0x50000300
-#define XSHAL_ROM_AVAIL_VSIZE 0x00FFFD00
-
-/* System RAM: */
-#define XSHAL_RAM_VADDR 0x60000000
-#define XSHAL_RAM_PADDR 0x60000000
-#define XSHAL_RAM_VSIZE 0x04000000
-#define XSHAL_RAM_PSIZE 0x04000000
-#define XSHAL_RAM_SIZE XSHAL_RAM_PSIZE
-/* Largest available area (free of vectors): */
-#define XSHAL_RAM_AVAIL_VADDR 0x60000400
-#define XSHAL_RAM_AVAIL_VSIZE 0x03FFFC00
-
-/*
- * Shadow system RAM (same device as system RAM, at different address).
- * (Emulation boards need this for the SONIC Ethernet driver
- * when data caches are configured for writeback mode.)
- * NOTE: on full MMU configs, this points to the BYPASS virtual address
- * of system RAM, ie. is the same as XSHAL_RAM_* except that virtual
- * addresses are viewed through the BYPASS static map rather than
- * the CACHED static map.
- */
-#define XSHAL_RAM_BYPASS_VADDR 0xA0000000
-#define XSHAL_RAM_BYPASS_PADDR 0xA0000000
-#define XSHAL_RAM_BYPASS_PSIZE 0x04000000
-
-/* Alternate system RAM (different device than system RAM): */
-/*#define XSHAL_ALTRAM_[VP]ADDR ...not configured...*/
-/*#define XSHAL_ALTRAM_SIZE ...not configured...*/
-
-/* Some available location in which to place devices in a simulation (eg. XTMP): */
-#define XSHAL_SIMIO_CACHED_VADDR 0xC0000000
-#define XSHAL_SIMIO_BYPASS_VADDR 0xC0000000
-#define XSHAL_SIMIO_PADDR 0xC0000000
-#define XSHAL_SIMIO_SIZE 0x20000000
-
-
-/*----------------------------------------------------------------------
- * For use by reference testbench exit and diagnostic routines.
- */
-#define XSHAL_MAGIC_EXIT 0x0
-
-/*----------------------------------------------------------------------
- * DEVICE-ADDRESS DEPENDENT...
- *
- * Values written to CACHEATTR special register (or its equivalent)
- * to enable and disable caches in various modes.
- *----------------------------------------------------------------------*/
-
-/*----------------------------------------------------------------------
- BACKWARD COMPATIBILITY ...
- ----------------------------------------------------------------------*/
-
-/*
- * NOTE: the following two macros are DEPRECATED. Use the latter
- * board-specific macros instead, which are specially tuned for the
- * particular target environments' memory maps.
- */
-#define XSHAL_CACHEATTR_BYPASS XSHAL_XT2000_CACHEATTR_BYPASS /* disable caches in bypass mode */
-#define XSHAL_CACHEATTR_DEFAULT XSHAL_XT2000_CACHEATTR_DEFAULT /* default setting to enable caches (no writeback!) */
-
-/*----------------------------------------------------------------------
- GENERIC
- ----------------------------------------------------------------------*/
-
-/* For the following, a 512MB region is used if it contains a system (PIF) RAM,
- * system (PIF) ROM, local memory, or XLMI. */
-
-/* These set any unused 512MB region to cache-BYPASS attribute: */
-#define XSHAL_ALLVALID_CACHEATTR_WRITEBACK 0x22224442 /* enable caches in write-back mode */
-#define XSHAL_ALLVALID_CACHEATTR_WRITEALLOC 0x22221112 /* enable caches in write-allocate mode */
-#define XSHAL_ALLVALID_CACHEATTR_WRITETHRU 0x22221112 /* enable caches in write-through mode */
-#define XSHAL_ALLVALID_CACHEATTR_BYPASS 0x22222222 /* disable caches in bypass mode */
-#define XSHAL_ALLVALID_CACHEATTR_DEFAULT XSHAL_ALLVALID_CACHEATTR_WRITEBACK /* default setting to enable caches */
-
-/* These set any unused 512MB region to ILLEGAL attribute: */
-#define XSHAL_STRICT_CACHEATTR_WRITEBACK 0xFFFF444F /* enable caches in write-back mode */
-#define XSHAL_STRICT_CACHEATTR_WRITEALLOC 0xFFFF111F /* enable caches in write-allocate mode */
-#define XSHAL_STRICT_CACHEATTR_WRITETHRU 0xFFFF111F /* enable caches in write-through mode */
-#define XSHAL_STRICT_CACHEATTR_BYPASS 0xFFFF222F /* disable caches in bypass mode */
-#define XSHAL_STRICT_CACHEATTR_DEFAULT XSHAL_STRICT_CACHEATTR_WRITEBACK /* default setting to enable caches */
-
-/* These set the first 512MB, if unused, to ILLEGAL attribute to help catch
- * NULL-pointer dereference bugs; all other unused 512MB regions are set
- * to cache-BYPASS attribute: */
-#define XSHAL_TRAPNULL_CACHEATTR_WRITEBACK 0x2222444F /* enable caches in write-back mode */
-#define XSHAL_TRAPNULL_CACHEATTR_WRITEALLOC 0x2222111F /* enable caches in write-allocate mode */
-#define XSHAL_TRAPNULL_CACHEATTR_WRITETHRU 0x2222111F /* enable caches in write-through mode */
-#define XSHAL_TRAPNULL_CACHEATTR_BYPASS 0x2222222F /* disable caches in bypass mode */
-#define XSHAL_TRAPNULL_CACHEATTR_DEFAULT XSHAL_TRAPNULL_CACHEATTR_WRITEBACK /* default setting to enable caches */
-
-/*----------------------------------------------------------------------
- ISS (Instruction Set Simulator) SPECIFIC ...
- ----------------------------------------------------------------------*/
-
-/* For now, ISS defaults to the TRAPNULL settings: */
-#define XSHAL_ISS_CACHEATTR_WRITEBACK XSHAL_TRAPNULL_CACHEATTR_WRITEBACK
-#define XSHAL_ISS_CACHEATTR_WRITEALLOC XSHAL_TRAPNULL_CACHEATTR_WRITEALLOC
-#define XSHAL_ISS_CACHEATTR_WRITETHRU XSHAL_TRAPNULL_CACHEATTR_WRITETHRU
-#define XSHAL_ISS_CACHEATTR_BYPASS XSHAL_TRAPNULL_CACHEATTR_BYPASS
-#define XSHAL_ISS_CACHEATTR_DEFAULT XSHAL_TRAPNULL_CACHEATTR_WRITEBACK
-
-#define XSHAL_ISS_PIPE_REGIONS 0
-#define XSHAL_ISS_SDRAM_REGIONS 0
-
-
-/*----------------------------------------------------------------------
- XT2000 BOARD SPECIFIC ...
- ----------------------------------------------------------------------*/
-
-/* For the following, a 512MB region is used if it contains any system RAM,
- * system ROM, local memory, XLMI, or other XT2000 board device or memory.
- * Regions containing devices are forced to cache-BYPASS mode regardless
- * of whether the macro is _WRITEBACK vs. _BYPASS etc. */
-
-/* These set any 512MB region unused on the XT2000 to ILLEGAL attribute: */
-#define XSHAL_XT2000_CACHEATTR_WRITEBACK 0xFF22444F /* enable caches in write-back mode */
-#define XSHAL_XT2000_CACHEATTR_WRITEALLOC 0xFF22111F /* enable caches in write-allocate mode */
-#define XSHAL_XT2000_CACHEATTR_WRITETHRU 0xFF22111F /* enable caches in write-through mode */
-#define XSHAL_XT2000_CACHEATTR_BYPASS 0xFF22222F /* disable caches in bypass mode */
-#define XSHAL_XT2000_CACHEATTR_DEFAULT XSHAL_XT2000_CACHEATTR_WRITEBACK /* default setting to enable caches */
-
-#define XSHAL_XT2000_PIPE_REGIONS 0x00000000 /* BusInt pipeline regions */
-#define XSHAL_XT2000_SDRAM_REGIONS 0x00000440 /* BusInt SDRAM regions */
-
-
-/*----------------------------------------------------------------------
- VECTOR INFO AND SIZES
- ----------------------------------------------------------------------*/
-
-#define XSHAL_VECTORS_PACKED 0
-#define XSHAL_STATIC_VECTOR_SELECT 0
-#define XSHAL_RESET_VECTOR_VADDR 0x50000000
-#define XSHAL_RESET_VECTOR_PADDR 0x50000000
-
-/*
- * Sizes allocated to vectors by the system (memory map) configuration.
- * These sizes are constrained by core configuration (eg. one vector's
- * code cannot overflow into another vector) but are dependent on the
- * system or board (or LSP) memory map configuration.
- *
- * Whether or not each vector happens to be in a system ROM is also
- * a system configuration matter, sometimes useful, included here also:
- */
-#define XSHAL_RESET_VECTOR_SIZE 0x00000300
-#define XSHAL_RESET_VECTOR_ISROM 1
-#define XSHAL_USER_VECTOR_SIZE 0x00000038
-#define XSHAL_USER_VECTOR_ISROM 0
-#define XSHAL_PROGRAMEXC_VECTOR_SIZE XSHAL_USER_VECTOR_SIZE /* for backward compatibility */
-#define XSHAL_USEREXC_VECTOR_SIZE XSHAL_USER_VECTOR_SIZE /* for backward compatibility */
-#define XSHAL_KERNEL_VECTOR_SIZE 0x00000038
-#define XSHAL_KERNEL_VECTOR_ISROM 0
-#define XSHAL_STACKEDEXC_VECTOR_SIZE XSHAL_KERNEL_VECTOR_SIZE /* for backward compatibility */
-#define XSHAL_KERNELEXC_VECTOR_SIZE XSHAL_KERNEL_VECTOR_SIZE /* for backward compatibility */
-#define XSHAL_DOUBLEEXC_VECTOR_SIZE 0x00000040
-#define XSHAL_DOUBLEEXC_VECTOR_ISROM 0
-#define XSHAL_WINDOW_VECTORS_SIZE 0x00000178
-#define XSHAL_WINDOW_VECTORS_ISROM 0
-#define XSHAL_INTLEVEL2_VECTOR_SIZE 0x00000038
-#define XSHAL_INTLEVEL2_VECTOR_ISROM 0
-#define XSHAL_INTLEVEL3_VECTOR_SIZE 0x00000038
-#define XSHAL_INTLEVEL3_VECTOR_ISROM 0
-#define XSHAL_INTLEVEL4_VECTOR_SIZE 0x00000038
-#define XSHAL_INTLEVEL4_VECTOR_ISROM 0
-#define XSHAL_INTLEVEL5_VECTOR_SIZE 0x00000038
-#define XSHAL_INTLEVEL5_VECTOR_ISROM 0
-#define XSHAL_INTLEVEL6_VECTOR_SIZE 0x00000038
-#define XSHAL_INTLEVEL6_VECTOR_ISROM 0
-#define XSHAL_DEBUG_VECTOR_SIZE XSHAL_INTLEVEL6_VECTOR_SIZE
-#define XSHAL_DEBUG_VECTOR_ISROM XSHAL_INTLEVEL6_VECTOR_ISROM
-#define XSHAL_NMI_VECTOR_SIZE 0x00000038
-#define XSHAL_NMI_VECTOR_ISROM 0
-#define XSHAL_INTLEVEL7_VECTOR_SIZE XSHAL_NMI_VECTOR_SIZE
-
-
-#endif /*XTENSA_CONFIG_SYSTEM_H*/
-
diff --git a/src/platform/haswell/include/arch/xtensa/config/tie-asm.h b/src/platform/haswell/include/arch/xtensa/config/tie-asm.h
deleted file mode 100644
index d7140f8..0000000
--- a/src/platform/haswell/include/arch/xtensa/config/tie-asm.h
+++ /dev/null
@@ -1,240 +0,0 @@
-/*
- * tie-asm.h -- compile-time HAL assembler definitions dependent on CORE & TIE
- *
- * NOTE: This header file is not meant to be included directly.
- */
-
-/* This header file contains assembly-language definitions (assembly
- macros, etc.) for this specific Xtensa processor's TIE extensions
- and options. It is customized to this Xtensa processor configuration.
-
- Copyright (c) 1999-2015 Cadence Design Systems Inc.
-
- Permission is hereby granted, free of charge, to any person obtaining
- a copy of this software and associated documentation files (the
- "Software"), to deal in the Software without restriction, including
- without limitation the rights to use, copy, modify, merge, publish,
- distribute, sublicense, and/or sell copies of the Software, and to
- permit persons to whom the Software is furnished to do so, subject to
- the following conditions:
-
- The above copyright notice and this permission notice shall be included
- in all copies or substantial portions of the Software.
-
- THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
- EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
- MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
- IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY
- CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
- TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
- SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. */
-
-#ifndef _XTENSA_CORE_TIE_ASM_H
-#define _XTENSA_CORE_TIE_ASM_H
-
-/* Selection parameter values for save-area save/restore macros: */
-/* Option vs. TIE: */
-#define XTHAL_SAS_TIE 0x0001 /* custom extension or coprocessor */
-#define XTHAL_SAS_OPT 0x0002 /* optional (and not a coprocessor) */
-#define XTHAL_SAS_ANYOT 0x0003 /* both of the above */
-/* Whether used automatically by compiler: */
-#define XTHAL_SAS_NOCC 0x0004 /* not used by compiler w/o special opts/code */
-#define XTHAL_SAS_CC 0x0008 /* used by compiler without special opts/code */
-#define XTHAL_SAS_ANYCC 0x000C /* both of the above */
-/* ABI handling across function calls: */
-#define XTHAL_SAS_CALR 0x0010 /* caller-saved */
-#define XTHAL_SAS_CALE 0x0020 /* callee-saved */
-#define XTHAL_SAS_GLOB 0x0040 /* global across function calls (in thread) */
-#define XTHAL_SAS_ANYABI 0x0070 /* all of the above three */
-/* Misc */
-#define XTHAL_SAS_ALL 0xFFFF /* include all default NCP contents */
-#define XTHAL_SAS3(optie,ccuse,abi) ( ((optie) & XTHAL_SAS_ANYOT) \
- | ((ccuse) & XTHAL_SAS_ANYCC) \
- | ((abi) & XTHAL_SAS_ANYABI) )
-
-
- /*
- * Macro to store all non-coprocessor (extra) custom TIE and optional state
- * (not including zero-overhead loop registers).
- * Required parameters:
- * ptr Save area pointer address register (clobbered)
- * (register must contain a 4 byte aligned address).
- * at1..at4 Four temporary address registers (first XCHAL_NCP_NUM_ATMPS
- * registers are clobbered, the remaining are unused).
- * Optional parameters:
- * continue If macro invoked as part of a larger store sequence, set to 1
- * if this is not the first in the sequence. Defaults to 0.
- * ofs Offset from start of larger sequence (from value of first ptr
- * in sequence) at which to store. Defaults to next available space
- * (or 0 if <continue> is 0).
- * select Select what category(ies) of registers to store, as a bitmask
- * (see XTHAL_SAS_xxx constants). Defaults to all registers.
- * alloc Select what category(ies) of registers to allocate; if any
- * category is selected here that is not in <select>, space for
- * the corresponding registers is skipped without doing any store.
- */
- .macro xchal_ncp_store ptr at1 at2 at3 at4 continue=0 ofs=-1 select=XTHAL_SAS_ALL alloc=0
- xchal_sa_start \continue, \ofs
- // Optional caller-saved registers not used by default by the compiler:
- .ifeq (XTHAL_SAS_OPT | XTHAL_SAS_NOCC | XTHAL_SAS_CALR) & ~(\select)
- xchal_sa_align \ptr, 0, 1016, 4, 4
- rsr.BR \at1 // boolean option
- s32i \at1, \ptr, .Lxchal_ofs_+0
- rsr.SCOMPARE1 \at1 // conditional store option
- s32i \at1, \ptr, .Lxchal_ofs_+4
- .set .Lxchal_ofs_, .Lxchal_ofs_ + 8
- .elseif ((XTHAL_SAS_OPT | XTHAL_SAS_NOCC | XTHAL_SAS_CALR) & ~(\alloc)) == 0
- xchal_sa_align \ptr, 0, 1016, 4, 4
- .set .Lxchal_ofs_, .Lxchal_ofs_ + 8
- .endif
- .endm // xchal_ncp_store
-
- /*
- * Macro to load all non-coprocessor (extra) custom TIE and optional state
- * (not including zero-overhead loop registers).
- * Required parameters:
- * ptr Save area pointer address register (clobbered)
- * (register must contain a 4 byte aligned address).
- * at1..at4 Four temporary address registers (first XCHAL_NCP_NUM_ATMPS
- * registers are clobbered, the remaining are unused).
- * Optional parameters:
- * continue If macro invoked as part of a larger load sequence, set to 1
- * if this is not the first in the sequence. Defaults to 0.
- * ofs Offset from start of larger sequence (from value of first ptr
- * in sequence) at which to load. Defaults to next available space
- * (or 0 if <continue> is 0).
- * select Select what category(ies) of registers to load, as a bitmask
- * (see XTHAL_SAS_xxx constants). Defaults to all registers.
- * alloc Select what category(ies) of registers to allocate; if any
- * category is selected here that is not in <select>, space for
- * the corresponding registers is skipped without doing any load.
- */
- .macro xchal_ncp_load ptr at1 at2 at3 at4 continue=0 ofs=-1 select=XTHAL_SAS_ALL alloc=0
- xchal_sa_start \continue, \ofs
- // Optional caller-saved registers not used by default by the compiler:
- .ifeq (XTHAL_SAS_OPT | XTHAL_SAS_NOCC | XTHAL_SAS_CALR) & ~(\select)
- xchal_sa_align \ptr, 0, 1016, 4, 4
- l32i \at1, \ptr, .Lxchal_ofs_+0
- wsr.BR \at1 // boolean option
- l32i \at1, \ptr, .Lxchal_ofs_+4
- wsr.SCOMPARE1 \at1 // conditional store option
- .set .Lxchal_ofs_, .Lxchal_ofs_ + 8
- .elseif ((XTHAL_SAS_OPT | XTHAL_SAS_NOCC | XTHAL_SAS_CALR) & ~(\alloc)) == 0
- xchal_sa_align \ptr, 0, 1016, 4, 4
- .set .Lxchal_ofs_, .Lxchal_ofs_ + 8
- .endif
- .endm // xchal_ncp_load
-
-
-#define XCHAL_NCP_NUM_ATMPS 1
-
- /*
- * Macro to store the state of TIE coprocessor AudioEngineLX.
- * Required parameters:
- * ptr Save area pointer address register (clobbered)
- * (register must contain a 8 byte aligned address).
- * at1..at4 Four temporary address registers (first XCHAL_CP1_NUM_ATMPS
- * registers are clobbered, the remaining are unused).
- * Optional parameters are the same as for xchal_ncp_store.
- */
-#define xchal_cp_AudioEngineLX_store xchal_cp1_store
- .macro xchal_cp1_store ptr at1 at2 at3 at4 continue=0 ofs=-1 select=XTHAL_SAS_ALL alloc=0
- xchal_sa_start \continue, \ofs
- // Custom caller-saved registers not used by default by the compiler:
- .ifeq (XTHAL_SAS_TIE | XTHAL_SAS_NOCC | XTHAL_SAS_CALR) & ~(\select)
- xchal_sa_align \ptr, 0, 0, 8, 8
- rur.AE_OVF_SAR \at1 // ureg 240
- s32i \at1, \ptr, .Lxchal_ofs_+0
- rur.AE_BITHEAD \at1 // ureg 241
- s32i \at1, \ptr, .Lxchal_ofs_+4
- rur.AE_TS_FTS_BU_BP \at1 // ureg 242
- s32i \at1, \ptr, .Lxchal_ofs_+8
- rur.AE_SD_NO \at1 // ureg 243
- s32i \at1, \ptr, .Lxchal_ofs_+12
- ae_sp24x2s.i aep0, \ptr, .Lxchal_ofs_+16
- ae_sp24x2s.i aep1, \ptr, .Lxchal_ofs_+24
- ae_sp24x2s.i aep2, \ptr, .Lxchal_ofs_+32
- ae_sp24x2s.i aep3, \ptr, .Lxchal_ofs_+40
- ae_sp24x2s.i aep4, \ptr, .Lxchal_ofs_+48
- ae_sp24x2s.i aep5, \ptr, .Lxchal_ofs_+56
- addi \ptr, \ptr, 64
- ae_sp24x2s.i aep6, \ptr, .Lxchal_ofs_+0
- ae_sp24x2s.i aep7, \ptr, .Lxchal_ofs_+8
- ae_sq56s.i aeq0, \ptr, .Lxchal_ofs_+16
- ae_sq56s.i aeq1, \ptr, .Lxchal_ofs_+24
- ae_sq56s.i aeq2, \ptr, .Lxchal_ofs_+32
- ae_sq56s.i aeq3, \ptr, .Lxchal_ofs_+40
- .set .Lxchal_pofs_, .Lxchal_pofs_ + 64
- .set .Lxchal_ofs_, .Lxchal_ofs_ + 48
- .elseif ((XTHAL_SAS_TIE | XTHAL_SAS_NOCC | XTHAL_SAS_CALR) & ~(\alloc)) == 0
- xchal_sa_align \ptr, 0, 0, 8, 8
- .set .Lxchal_ofs_, .Lxchal_ofs_ + 112
- .endif
- .endm // xchal_cp1_store
-
- /*
- * Macro to load the state of TIE coprocessor AudioEngineLX.
- * Required parameters:
- * ptr Save area pointer address register (clobbered)
- * (register must contain a 8 byte aligned address).
- * at1..at4 Four temporary address registers (first XCHAL_CP1_NUM_ATMPS
- * registers are clobbered, the remaining are unused).
- * Optional parameters are the same as for xchal_ncp_load.
- */
-#define xchal_cp_AudioEngineLX_load xchal_cp1_load
- .macro xchal_cp1_load ptr at1 at2 at3 at4 continue=0 ofs=-1 select=XTHAL_SAS_ALL alloc=0
- xchal_sa_start \continue, \ofs
- // Custom caller-saved registers not used by default by the compiler:
- .ifeq (XTHAL_SAS_TIE | XTHAL_SAS_NOCC | XTHAL_SAS_CALR) & ~(\select)
- xchal_sa_align \ptr, 0, 0, 8, 8
- l32i \at1, \ptr, .Lxchal_ofs_+0
- wur.AE_OVF_SAR \at1 // ureg 240
- l32i \at1, \ptr, .Lxchal_ofs_+4
- wur.AE_BITHEAD \at1 // ureg 241
- l32i \at1, \ptr, .Lxchal_ofs_+8
- wur.AE_TS_FTS_BU_BP \at1 // ureg 242
- l32i \at1, \ptr, .Lxchal_ofs_+12
- wur.AE_SD_NO \at1 // ureg 243
- ae_lp24x2.i aep0, \ptr, .Lxchal_ofs_+16
- ae_lp24x2.i aep1, \ptr, .Lxchal_ofs_+24
- ae_lp24x2.i aep2, \ptr, .Lxchal_ofs_+32
- ae_lp24x2.i aep3, \ptr, .Lxchal_ofs_+40
- ae_lp24x2.i aep4, \ptr, .Lxchal_ofs_+48
- ae_lp24x2.i aep5, \ptr, .Lxchal_ofs_+56
- addi \ptr, \ptr, 64
- ae_lp24x2.i aep6, \ptr, .Lxchal_ofs_+0
- ae_lp24x2.i aep7, \ptr, .Lxchal_ofs_+8
- addi \ptr, \ptr, 16
- ae_lq56.i aeq0, \ptr, .Lxchal_ofs_+0
- ae_lq56.i aeq1, \ptr, .Lxchal_ofs_+8
- ae_lq56.i aeq2, \ptr, .Lxchal_ofs_+16
- ae_lq56.i aeq3, \ptr, .Lxchal_ofs_+24
- .set .Lxchal_pofs_, .Lxchal_pofs_ + 80
- .set .Lxchal_ofs_, .Lxchal_ofs_ + 32
- .elseif ((XTHAL_SAS_TIE | XTHAL_SAS_NOCC | XTHAL_SAS_CALR) & ~(\alloc)) == 0
- xchal_sa_align \ptr, 0, 0, 8, 8
- .set .Lxchal_ofs_, .Lxchal_ofs_ + 112
- .endif
- .endm // xchal_cp1_load
-
-#define XCHAL_CP1_NUM_ATMPS 1
-#define XCHAL_SA_NUM_ATMPS 1
-
- /* Empty macros for unconfigured coprocessors: */
- .macro xchal_cp0_store p a b c d continue=0 ofs=-1 select=-1 ; .endm
- .macro xchal_cp0_load p a b c d continue=0 ofs=-1 select=-1 ; .endm
- .macro xchal_cp2_store p a b c d continue=0 ofs=-1 select=-1 ; .endm
- .macro xchal_cp2_load p a b c d continue=0 ofs=-1 select=-1 ; .endm
- .macro xchal_cp3_store p a b c d continue=0 ofs=-1 select=-1 ; .endm
- .macro xchal_cp3_load p a b c d continue=0 ofs=-1 select=-1 ; .endm
- .macro xchal_cp4_store p a b c d continue=0 ofs=-1 select=-1 ; .endm
- .macro xchal_cp4_load p a b c d continue=0 ofs=-1 select=-1 ; .endm
- .macro xchal_cp5_store p a b c d continue=0 ofs=-1 select=-1 ; .endm
- .macro xchal_cp5_load p a b c d continue=0 ofs=-1 select=-1 ; .endm
- .macro xchal_cp6_store p a b c d continue=0 ofs=-1 select=-1 ; .endm
- .macro xchal_cp6_load p a b c d continue=0 ofs=-1 select=-1 ; .endm
- .macro xchal_cp7_store p a b c d continue=0 ofs=-1 select=-1 ; .endm
- .macro xchal_cp7_load p a b c d continue=0 ofs=-1 select=-1 ; .endm
-
-#endif /*_XTENSA_CORE_TIE_ASM_H*/
-
diff --git a/src/platform/haswell/include/arch/xtensa/config/tie.h b/src/platform/haswell/include/arch/xtensa/config/tie.h
deleted file mode 100644
index 3c63812..0000000
--- a/src/platform/haswell/include/arch/xtensa/config/tie.h
+++ /dev/null
@@ -1,170 +0,0 @@
-/*
- * tie.h -- compile-time HAL definitions dependent on CORE & TIE configuration
- *
- * NOTE: This header file is not meant to be included directly.
- */
-
-/* This header file describes this specific Xtensa processor's TIE extensions
- that extend basic Xtensa core functionality. It is customized to this
- Xtensa processor configuration.
-
- Copyright (c) 1999-2015 Cadence Design Systems Inc.
-
- Permission is hereby granted, free of charge, to any person obtaining
- a copy of this software and associated documentation files (the
- "Software"), to deal in the Software without restriction, including
- without limitation the rights to use, copy, modify, merge, publish,
- distribute, sublicense, and/or sell copies of the Software, and to
- permit persons to whom the Software is furnished to do so, subject to
- the following conditions:
-
- The above copyright notice and this permission notice shall be included
- in all copies or substantial portions of the Software.
-
- THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
- EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
- MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
- IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY
- CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
- TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
- SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. */
-
-#ifndef _XTENSA_CORE_TIE_H
-#define _XTENSA_CORE_TIE_H
-
-#define XCHAL_CP_NUM 1 /* number of coprocessors */
-#define XCHAL_CP_MAX 2 /* max CP ID + 1 (0 if none) */
-#define XCHAL_CP_MASK 0x02 /* bitmask of all CPs by ID */
-#define XCHAL_CP_PORT_MASK 0x00 /* bitmask of only port CPs */
-
-/* Basic parameters of each coprocessor: */
-#define XCHAL_CP1_NAME "AudioEngineLX"
-#define XCHAL_CP1_IDENT AudioEngineLX
-#define XCHAL_CP1_SA_SIZE 112 /* size of state save area */
-#define XCHAL_CP1_SA_ALIGN 8 /* min alignment of save area */
-#define XCHAL_CP_ID_AUDIOENGINELX 1 /* coprocessor ID (0..7) */
-
-/* Filler info for unassigned coprocessors, to simplify arrays etc: */
-#define XCHAL_CP0_SA_SIZE 0
-#define XCHAL_CP0_SA_ALIGN 1
-#define XCHAL_CP2_SA_SIZE 0
-#define XCHAL_CP2_SA_ALIGN 1
-#define XCHAL_CP3_SA_SIZE 0
-#define XCHAL_CP3_SA_ALIGN 1
-#define XCHAL_CP4_SA_SIZE 0
-#define XCHAL_CP4_SA_ALIGN 1
-#define XCHAL_CP5_SA_SIZE 0
-#define XCHAL_CP5_SA_ALIGN 1
-#define XCHAL_CP6_SA_SIZE 0
-#define XCHAL_CP6_SA_ALIGN 1
-#define XCHAL_CP7_SA_SIZE 0
-#define XCHAL_CP7_SA_ALIGN 1
-
-/* Save area for non-coprocessor optional and custom (TIE) state: */
-#define XCHAL_NCP_SA_SIZE 8
-#define XCHAL_NCP_SA_ALIGN 4
-
-/* Total save area for optional and custom state (NCP + CPn): */
-#define XCHAL_TOTAL_SA_SIZE 128 /* with 16-byte align padding */
-#define XCHAL_TOTAL_SA_ALIGN 8 /* actual minimum alignment */
-
-/*
- * Detailed contents of save areas.
- * NOTE: caller must define the XCHAL_SA_REG macro (not defined here)
- * before expanding the XCHAL_xxx_SA_LIST() macros.
- *
- * XCHAL_SA_REG(s,ccused,abikind,kind,opt,name,galign,align,asize,
- * dbnum,base,regnum,bitsz,gapsz,reset,x...)
- *
- * s = passed from XCHAL_*_LIST(s), eg. to select how to expand
- * ccused = set if used by compiler without special options or code
- * abikind = 0 (caller-saved), 1 (callee-saved), or 2 (thread-global)
- * kind = 0 (special reg), 1 (TIE user reg), or 2 (TIE regfile reg)
- * opt = 0 (custom TIE extension or coprocessor), or 1 (optional reg)
- * name = lowercase reg name (no quotes)
- * galign = group byte alignment (power of 2) (galign >= align)
- * align = register byte alignment (power of 2)
- * asize = allocated size in bytes (asize*8 == bitsz + gapsz + padsz)
- * (not including any pad bytes required to galign this or next reg)
- * dbnum = unique target number f/debug (see <xtensa-libdb-macros.h>)
- * base = reg shortname w/o index (or sr=special, ur=TIE user reg)
- * regnum = reg index in regfile, or special/TIE-user reg number
- * bitsz = number of significant bits (regfile width, or ur/sr mask bits)
- * gapsz = intervening bits, if bitsz bits not stored contiguously
- * (padsz = pad bits at end [TIE regfile] or at msbits [ur,sr] of asize)
- * reset = register reset value (or 0 if undefined at reset)
- * x = reserved for future use (0 until then)
- *
- * To filter out certain registers, e.g. to expand only the non-global
- * registers used by the compiler, you can do something like this:
- *
- * #define XCHAL_SA_REG(s,ccused,p...) SELCC##ccused(p)
- * #define SELCC0(p...)
- * #define SELCC1(abikind,p...) SELAK##abikind(p)
- * #define SELAK0(p...) REG(p)
- * #define SELAK1(p...) REG(p)
- * #define SELAK2(p...)
- * #define REG(kind,tie,name,galn,aln,asz,csz,dbnum,base,rnum,bsz,rst,x...) \
- * ...what you want to expand...
- */
-
-#define XCHAL_NCP_SA_NUM 2
-#define XCHAL_NCP_SA_LIST(s) \
- XCHAL_SA_REG(s,0,0,0,1, br, 4, 4, 4,0x0204, sr,4 , 16,0,0,0) \
- XCHAL_SA_REG(s,0,0,0,1, scompare1, 4, 4, 4,0x020C, sr,12 , 32,0,0,0)
-
-#define XCHAL_CP0_SA_NUM 0
-#define XCHAL_CP0_SA_LIST(s) /* empty */
-
-#define XCHAL_CP1_SA_NUM 16
-#define XCHAL_CP1_SA_LIST(s) \
- XCHAL_SA_REG(s,0,0,1,0, ae_ovf_sar, 8, 4, 4,0x03F0, ur,240, 7,0,0,0) \
- XCHAL_SA_REG(s,0,0,1,0, ae_bithead, 4, 4, 4,0x03F1, ur,241, 32,0,0,0) \
- XCHAL_SA_REG(s,0,0,1,0,ae_ts_fts_bu_bp, 4, 4, 4,0x03F2, ur,242, 16,0,0,0) \
- XCHAL_SA_REG(s,0,0,1,0, ae_sd_no, 4, 4, 4,0x03F3, ur,243, 28,0,0,0) \
- XCHAL_SA_REG(s,0,0,2,0, aep0, 8, 8, 8,0x0060, aep,0 , 48,0,0,0) \
- XCHAL_SA_REG(s,0,0,2,0, aep1, 8, 8, 8,0x0061, aep,1 , 48,0,0,0) \
- XCHAL_SA_REG(s,0,0,2,0, aep2, 8, 8, 8,0x0062, aep,2 , 48,0,0,0) \
- XCHAL_SA_REG(s,0,0,2,0, aep3, 8, 8, 8,0x0063, aep,3 , 48,0,0,0) \
- XCHAL_SA_REG(s,0,0,2,0, aep4, 8, 8, 8,0x0064, aep,4 , 48,0,0,0) \
- XCHAL_SA_REG(s,0,0,2,0, aep5, 8, 8, 8,0x0065, aep,5 , 48,0,0,0) \
- XCHAL_SA_REG(s,0,0,2,0, aep6, 8, 8, 8,0x0066, aep,6 , 48,0,0,0) \
- XCHAL_SA_REG(s,0,0,2,0, aep7, 8, 8, 8,0x0067, aep,7 , 48,0,0,0) \
- XCHAL_SA_REG(s,0,0,2,0, aeq0, 8, 8, 8,0x0068, aeq,0 , 56,0,0,0) \
- XCHAL_SA_REG(s,0,0,2,0, aeq1, 8, 8, 8,0x0069, aeq,1 , 56,0,0,0) \
- XCHAL_SA_REG(s,0,0,2,0, aeq2, 8, 8, 8,0x006A, aeq,2 , 56,0,0,0) \
- XCHAL_SA_REG(s,0,0,2,0, aeq3, 8, 8, 8,0x006B, aeq,3 , 56,0,0,0)
-
-#define XCHAL_CP2_SA_NUM 0
-#define XCHAL_CP2_SA_LIST(s) /* empty */
-
-#define XCHAL_CP3_SA_NUM 0
-#define XCHAL_CP3_SA_LIST(s) /* empty */
-
-#define XCHAL_CP4_SA_NUM 0
-#define XCHAL_CP4_SA_LIST(s) /* empty */
-
-#define XCHAL_CP5_SA_NUM 0
-#define XCHAL_CP5_SA_LIST(s) /* empty */
-
-#define XCHAL_CP6_SA_NUM 0
-#define XCHAL_CP6_SA_LIST(s) /* empty */
-
-#define XCHAL_CP7_SA_NUM 0
-#define XCHAL_CP7_SA_LIST(s) /* empty */
-
-/* Byte length of instruction from its first nibble (op0 field), per FLIX. */
-#define XCHAL_OP0_FORMAT_LENGTHS 3,3,3,3,3,3,3,3,2,2,2,2,2,2,3,8
-/* Byte length of instruction from its first byte, per FLIX. */
-#define XCHAL_BYTE0_FORMAT_LENGTHS \
- 3,3,3,3,3,3,3,3,2,2,2,2,2,2,3,8, 3,3,3,3,3,3,3,3,2,2,2,2,2,2,3,8,\
- 3,3,3,3,3,3,3,3,2,2,2,2,2,2,3,8, 3,3,3,3,3,3,3,3,2,2,2,2,2,2,3,8,\
- 3,3,3,3,3,3,3,3,2,2,2,2,2,2,3,8, 3,3,3,3,3,3,3,3,2,2,2,2,2,2,3,8,\
- 3,3,3,3,3,3,3,3,2,2,2,2,2,2,3,8, 3,3,3,3,3,3,3,3,2,2,2,2,2,2,3,8,\
- 3,3,3,3,3,3,3,3,2,2,2,2,2,2,3,8, 3,3,3,3,3,3,3,3,2,2,2,2,2,2,3,8,\
- 3,3,3,3,3,3,3,3,2,2,2,2,2,2,3,8, 3,3,3,3,3,3,3,3,2,2,2,2,2,2,3,8,\
- 3,3,3,3,3,3,3,3,2,2,2,2,2,2,3,8, 3,3,3,3,3,3,3,3,2,2,2,2,2,2,3,8,\
- 3,3,3,3,3,3,3,3,2,2,2,2,2,2,3,8, 3,3,3,3,3,3,3,3,2,2,2,2,2,2,3,8
-
-#endif /*_XTENSA_CORE_TIE_H*/
-
diff --git a/src/platform/haswell/include/platform/Makefile.am b/src/platform/haswell/include/platform/Makefile.am
deleted file mode 100644
index a12dd72..0000000
--- a/src/platform/haswell/include/platform/Makefile.am
+++ /dev/null
@@ -1,12 +0,0 @@
-noinst_HEADERS = \
- clk.h \
- dma.h \
- idc.h \
- interrupt.h \
- mailbox.h \
- memory.h \
- platcfg.h \
- platform.h \
- pm_runtime.h \
- shim.h \
- timer.h
diff --git a/src/platform/haswell/include/platform/clk.h b/src/platform/haswell/include/platform/clk.h
deleted file mode 100644
index 010396d..0000000
--- a/src/platform/haswell/include/platform/clk.h
+++ /dev/null
@@ -1,42 +0,0 @@
-/*
- * Copyright (c) 2016, Intel Corporation
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- * * Redistributions of source code must retain the above copyright
- * notice, this list of conditions and the following disclaimer.
- * * Redistributions in binary form must reproduce the above copyright
- * notice, this list of conditions and the following disclaimer in the
- * documentation and/or other materials provided with the distribution.
- * * Neither the name of the Intel Corporation nor the
- * names of its contributors may be used to endorse or promote products
- * derived from this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
- * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
- * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
- * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
- * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
- * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
- * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
- * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
- * POSSIBILITY OF SUCH DAMAGE.
- *
- * Author: Liam Girdwood <liam.r.girdwood@linux.intel.com>
- */
-
-#ifndef __PLATFORM_CLOCK__
-#define __PLATFORM_CLOCK__
-
-#define CLK_CPU 0
-#define CLK_SSP 1
-
-#define CLK_DEFAULT_CPU_HZ 320000000
-#define CLK_MAX_CPU_HZ 320000000
-
-void init_platform_clocks(void);
-
-#endif
diff --git a/src/platform/haswell/include/platform/dma.h b/src/platform/haswell/include/platform/dma.h
deleted file mode 100644
index c926672..0000000
--- a/src/platform/haswell/include/platform/dma.h
+++ /dev/null
@@ -1,61 +0,0 @@
-/*
- * Copyright (c) 2016, Intel Corporation
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- * * Redistributions of source code must retain the above copyright
- * notice, this list of conditions and the following disclaimer.
- * * Redistributions in binary form must reproduce the above copyright
- * notice, this list of conditions and the following disclaimer in the
- * documentation and/or other materials provided with the distribution.
- * * Neither the name of the Intel Corporation nor the
- * names of its contributors may be used to endorse or promote products
- * derived from this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
- * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
- * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
- * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
- * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
- * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
- * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
- * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
- * POSSIBILITY OF SUCH DAMAGE.
- *
- * Author: Liam Girdwood <liam.r.girdwood@linux.intel.com>
- */
-
-#ifndef __PLATFORM_DMA_H__
-#define __PLATFORM_DMA_H__
-
-#include <stdint.h>
-#include <sof/dma.h>
-
-#define PLATFORM_NUM_DMACS 2
-
-#define DMA_ID_DMAC0 0
-#define DMA_ID_DMAC1 1
-
-#define DMA_HANDSHAKE_SSP1_RX 0
-#define DMA_HANDSHAKE_SSP1_TX 1
-#define DMA_HANDSHAKE_SSP0_RX 2
-#define DMA_HANDSHAKE_SSP0_TX 3
-#define DMA_HANDSHAKE_OBFF_0 4
-#define DMA_HANDSHAKE_OBFF_1 5
-#define DMA_HANDSHAKE_OBFF_2 6
-#define DMA_HANDSHAKE_OBFF_3 7
-#define DMA_HANDSHAKE_OBFF_4 8
-#define DMA_HANDSHAKE_OBFF_5 9
-#define DMA_HANDSHAKE_OBFF_6 10
-#define DMA_HANDSHAKE_OBFF_7 11
-#define DMA_HANDSHAKE_OBFF_8 12
-#define DMA_HANDSHAKE_OBFF_9 13
-#define DMA_HANDSHAKE_OBFF_10 14
-#define DMA_HANDSHAKE_OBFF_11 15
-
-extern struct dma dma[PLATFORM_NUM_DMACS];
-
-#endif
diff --git a/src/platform/haswell/include/platform/idc.h b/src/platform/haswell/include/platform/idc.h
deleted file mode 100644
index ec727e3..0000000
--- a/src/platform/haswell/include/platform/idc.h
+++ /dev/null
@@ -1,43 +0,0 @@
-/*
- * Copyright (c) 2018, Intel Corporation
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- * * Redistributions of source code must retain the above copyright
- * notice, this list of conditions and the following disclaimer.
- * * Redistributions in binary form must reproduce the above copyright
- * notice, this list of conditions and the following disclaimer in the
- * documentation and/or other materials provided with the distribution.
- * * Neither the name of the Intel Corporation nor the
- * names of its contributors may be used to endorse or promote products
- * derived from this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
- * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
- * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
- * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
- * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
- * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
- * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
- * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
- * POSSIBILITY OF SUCH DAMAGE.
- *
- * Author: Tomasz Lauda <tomasz.lauda@linux.intel.com>
- */
-
-#ifndef __INCLUDE_PLATFORM_IDC_H__
-#define __INCLUDE_PLATFORM_IDC_H__
-
-struct idc_msg;
-
-static inline int idc_send_msg(struct idc_msg *msg,
- uint32_t mode) { return 0; }
-
-static inline void idc_process_msg_queue(void) { }
-
-static inline void idc_init(void) { }
-
-#endif
diff --git a/src/platform/haswell/include/platform/interrupt.h b/src/platform/haswell/include/platform/interrupt.h
deleted file mode 100644
index 14d0e30..0000000
--- a/src/platform/haswell/include/platform/interrupt.h
+++ /dev/null
@@ -1,83 +0,0 @@
-/*
- * Copyright (c) 2016, Intel Corporation
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- * * Redistributions of source code must retain the above copyright
- * notice, this list of conditions and the following disclaimer.
- * * Redistributions in binary form must reproduce the above copyright
- * notice, this list of conditions and the following disclaimer in the
- * documentation and/or other materials provided with the distribution.
- * * Neither the name of the Intel Corporation nor the
- * names of its contributors may be used to endorse or promote products
- * derived from this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
- * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
- * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
- * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
- * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
- * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
- * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
- * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
- * POSSIBILITY OF SUCH DAMAGE.
- *
- * Author: Liam Girdwood <liam.r.girdwood@linux.intel.com>
- */
-
-#ifndef __INCLUDE_PLATFORM_INTERRUPT__
-#define __INCLUDE_PLATFORM_INTERRUPT__
-
-#include <stdint.h>
-#include <stddef.h>
-#include <sof/interrupt-map.h>
-
-#define PLATFORM_IRQ_CHILDREN 0
-
-/* IRQ numbers */
-#define IRQ_NUM_EXT_SSP0 0 /* Level 1 */
-#define IRQ_NUM_EXT_SSP1 1 /* Level 1 */
-#define IRQ_NUM_EXT_OBFF 2 /* Level 1 */
-#define IRQ_NUM_EXT_IA 4 /* Level 1 */
-#define IRQ_NUM_TIMER1 6 /* Level 1 */
-#define IRQ_NUM_SOFTWARE1 7 /* Level 1 */
-#define IRQ_NUM_EXT_DMAC0 8 /* Level 2 */
-#define IRQ_NUM_EXT_DMAC1 9 /* Level 3 */
-#define IRQ_NUM_TIMER2 10 /* Level 3 */
-#define IRQ_NUM_SOFTWARE2 11 /* Level 3 */
-#define IRQ_NUM_EXT_PARITY 12 /* Level 4 */
-#define IRQ_NUM_TIMER3 13 /* Level 5 */
-#define IRQ_NUM_NMI 14 /* Level 7 */
-
-/* IRQ Masks */
-#define IRQ_MASK_EXT_SSP0 (1 << IRQ_NUM_EXT_SSP0)
-#define IRQ_MASK_EXT_SSP1 (1 << IRQ_NUM_EXT_SSP1)
-#define IRQ_MASK_EXT_OBFF (1 << IRQ_NUM_EXT_OBFF)
-#define IRQ_MASK_EXT_IA (1 << IRQ_NUM_EXT_IA)
-#define IRQ_MASK_TIMER1 (1 << IRQ_NUM_TIMER1)
-#define IRQ_MASK_SOFTWARE1 (1 << IRQ_NUM_SOFTWARE1)
-#define IRQ_MASK_EXT_DMAC0 (1 << IRQ_NUM_EXT_DMAC0)
-#define IRQ_MASK_EXT_DMAC1 (1 << IRQ_NUM_EXT_DMAC1)
-#define IRQ_MASK_TIMER2 (1 << IRQ_NUM_TIMER2)
-#define IRQ_MASK_SOFTWARE2 (1 << IRQ_NUM_SOFTWARE2)
-#define IRQ_MASK_EXT_PARITY (1 << IRQ_NUM_EXT_PARITY)
-#define IRQ_MASK_TIMER3 (1 << IRQ_NUM_TIMER3)
-
-static inline void platform_interrupt_init(void) {}
-
-/* haswell does not support child IRQs */
-static inline struct irq_desc *platform_irq_get_parent(uint32_t irq)
-{
- return NULL;
-}
-
-void platform_interrupt_set(int irq);
-void platform_interrupt_clear(uint32_t irq, uint32_t mask);
-uint32_t platform_interrupt_get_enabled(void);
-void platform_interrupt_mask(uint32_t irq, uint32_t mask);
-void platform_interrupt_unmask(uint32_t irq, uint32_t mask);
-
-#endif
diff --git a/src/platform/haswell/include/platform/mailbox.h b/src/platform/haswell/include/platform/mailbox.h
deleted file mode 100644
index 858eb87..0000000
--- a/src/platform/haswell/include/platform/mailbox.h
+++ /dev/null
@@ -1,76 +0,0 @@
-/*
- * Copyright (c) 2016, Intel Corporation
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- * * Redistributions of source code must retain the above copyright
- * notice, this list of conditions and the following disclaimer.
- * * Redistributions in binary form must reproduce the above copyright
- * notice, this list of conditions and the following disclaimer in the
- * documentation and/or other materials provided with the distribution.
- * * Neither the name of the Intel Corporation nor the
- * names of its contributors may be used to endorse or promote products
- * derived from this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
- * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
- * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
- * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
- * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
- * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
- * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
- * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
- * POSSIBILITY OF SUCH DAMAGE.
- *
- * Author: Liam Girdwood <liam.r.girdwood@linux.intel.com>
- */
-
-#ifndef __INCLUDE_PLATFORM_MAILBOX__
-#define __INCLUDE_PLATFORM_MAILBOX__
-
-#include <platform/memory.h>
-
-#if CONFIG_BROADWELL
-#define MAILBOX_HOST_OFFSET 0x0009E000
-#else
-#define MAILBOX_HOST_OFFSET 0x0007E000
-#endif
-
-#define MAILBOX_DSPBOX_OFFSET 0x0
-#define MAILBOX_DSPBOX_SIZE 0x400
-#define MAILBOX_DSPBOX_BASE \
- (MAILBOX_BASE + MAILBOX_DSPBOX_OFFSET)
-
-#define MAILBOX_HOSTBOX_OFFSET MAILBOX_DSPBOX_SIZE
-#define MAILBOX_HOSTBOX_SIZE 0x400
-#define MAILBOX_HOSTBOX_BASE \
- (MAILBOX_BASE + MAILBOX_HOSTBOX_OFFSET)
-
-#define MAILBOX_EXCEPTION_OFFSET \
- (MAILBOX_HOSTBOX_SIZE + MAILBOX_DSPBOX_SIZE)
-#define MAILBOX_EXCEPTION_SIZE 0x100
-#define MAILBOX_EXCEPTION_BASE \
- (MAILBOX_BASE + MAILBOX_EXCEPTION_OFFSET)
-
-#define MAILBOX_DEBUG_OFFSET \
- (MAILBOX_EXCEPTION_SIZE + MAILBOX_EXCEPTION_OFFSET)
-#define MAILBOX_DEBUG_SIZE 0x100
-#define MAILBOX_DEBUG_BASE \
- (MAILBOX_BASE + MAILBOX_DEBUG_OFFSET)
-
-#define MAILBOX_STREAM_OFFSET \
- (MAILBOX_DEBUG_SIZE + MAILBOX_DEBUG_OFFSET)
-#define MAILBOX_STREAM_SIZE 0x200
-#define MAILBOX_STREAM_BASE \
- (MAILBOX_BASE + MAILBOX_STREAM_OFFSET)
-
-#define MAILBOX_TRACE_OFFSET \
- (MAILBOX_STREAM_SIZE + MAILBOX_STREAM_OFFSET)
-#define MAILBOX_TRACE_SIZE 0x380
-#define MAILBOX_TRACE_BASE \
- (MAILBOX_BASE + MAILBOX_TRACE_OFFSET)
-
-#endif
diff --git a/src/platform/haswell/include/platform/memory.h b/src/platform/haswell/include/platform/memory.h
deleted file mode 100644
index a79d0f6..0000000
--- a/src/platform/haswell/include/platform/memory.h
+++ /dev/null
@@ -1,148 +0,0 @@
-/*
- * Copyright (c) 2016, Intel Corporation
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- * * Redistributions of source code must retain the above copyright
- * notice, this list of conditions and the following disclaimer.
- * * Redistributions in binary form must reproduce the above copyright
- * notice, this list of conditions and the following disclaimer in the
- * documentation and/or other materials provided with the distribution.
- * * Neither the name of the Intel Corporation nor the
- * names of its contributors may be used to endorse or promote products
- * derived from this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
- * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
- * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
- * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
- * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
- * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
- * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
- * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
- * POSSIBILITY OF SUCH DAMAGE.
- *
- * Author: Liam Girdwood <liam.r.girdwood@linux.intel.com>
- */
-
-#ifndef __PLATFORM_MEMORY_H__
-#define __PLATFORM_MEMORY_H__
-
-#include <config.h>
-
-/* physical DSP addresses */
-
-
-#define SHIM_SIZE 0x00001000
-
-#define IRAM_BASE 0x00000000
-#define IRAM_SIZE 0x00050000
-
-#define DRAM0_BASE 0x00400000
-#define DRAM0_VBASE 0x00400000
-
-#define MAILBOX_SIZE 0x00001000
-#define DMA0_SIZE 0x00001000
-#define DMA1_SIZE 0x00001000
-#define SSP0_SIZE 0x00001000
-#define SSP1_SIZE 0x00001000
-
-#if CONFIG_BROADWELL
-#define DRAM0_SIZE 0x000A0000
-#define SHIM_BASE 0xFFFFB000
-#define DMA0_BASE 0xFFFFE000
-#define DMA1_BASE 0xFFFFF000
-#define SSP0_BASE 0xFFFFC000
-#define SSP1_BASE 0xFFFFD000
-
-#else /* HASWELL */
-#define DRAM0_SIZE 0x00080000
-#define SHIM_BASE 0xFFFE7000
-#define DMA0_BASE 0xFFFF0000
-#define DMA1_BASE 0xFFFF8000
-#define SSP0_BASE 0xFFFE8000
-#define SSP1_BASE 0xFFFE9000
-
-#endif
-
-/*
- * The Heap and Stack on Haswell/Broadwell are organised like this :-
- *
- * +--------------------------------------------------------------------------+
- * | Offset | Region | Size |
- * +---------------------+----------------+-----------------------------------+
- * | DRAM0_BASE | RO Data | SOF_DATA_SIZE |
- * | | Data | |
- * | | BSS | |
- * +---------------------+----------------+-----------------------------------+
- * | HEAP_SYSTEM_BASE | System Heap | HEAP_SYSTEM_SIZE |
- * +---------------------+----------------+-----------------------------------+
- * | HEAP_RUNTIME_BASE | Runtime Heap | HEAP_RUNTIME_SIZE |
- * +---------------------+----------------+-----------------------------------+
- * | HEAP_BUFFER_BASE | Module Buffers | HEAP_BUFFER_SIZE |
- * +---------------------+----------------+-----------------------------------+
- * | MAILBOX_BASE | Mailbox | MAILBOX_SIZE |
- * +---------------------+----------------+-----------------------------------+
- * | SOF_STACK_END | Stack | SOF_STACK_SIZE |
- * +---------------------+----------------+-----------------------------------+
- * | SOF_STACK_BASE | | |
- * +---------------------+----------------+-----------------------------------+
- */
-
-
-/* Heap section sizes for module pool */
-#define HEAP_RT_COUNT8 0
-#define HEAP_RT_COUNT16 256
-#define HEAP_RT_COUNT32 128
-#define HEAP_RT_COUNT64 64
-#define HEAP_RT_COUNT128 32
-#define HEAP_RT_COUNT256 16
-#define HEAP_RT_COUNT512 8
-#define HEAP_RT_COUNT1024 4
-
-/* Heap configuration */
-#define SOF_DATA_SIZE 0xa000
-
-#define HEAP_SYSTEM_BASE (DRAM0_BASE + SOF_DATA_SIZE)
-#define HEAP_SYSTEM_SIZE 0x2000
-
-#define HEAP_RUNTIME_BASE (HEAP_SYSTEM_BASE + HEAP_SYSTEM_SIZE)
-#define HEAP_RUNTIME_SIZE \
- (HEAP_RT_COUNT8 * 8 + HEAP_RT_COUNT16 * 16 + \
- HEAP_RT_COUNT32 * 32 + HEAP_RT_COUNT64 * 64 + \
- HEAP_RT_COUNT128 * 128 + HEAP_RT_COUNT256 * 256 + \
- HEAP_RT_COUNT512 * 512 + HEAP_RT_COUNT1024 * 1024)
-
-#define HEAP_BUFFER_BASE (HEAP_RUNTIME_BASE + HEAP_RUNTIME_SIZE)
-#define HEAP_BUFFER_SIZE \
- (DRAM0_SIZE - HEAP_RUNTIME_SIZE - SOF_STACK_SIZE -\
- HEAP_SYSTEM_SIZE - SOF_DATA_SIZE - MAILBOX_SIZE)
-
-#define HEAP_BUFFER_BLOCK_SIZE 0x180
-#define HEAP_BUFFER_COUNT (HEAP_BUFFER_SIZE / HEAP_BUFFER_BLOCK_SIZE)
-
-#define PLATFORM_HEAP_RUNTIME 1
-#define PLATFORM_HEAP_BUFFER 1
-
-/* Stack configuration */
-#define SOF_STACK_SIZE 0x1000
-#define SOF_STACK_BASE (DRAM0_BASE + DRAM0_SIZE)
-#define SOF_STACK_END (SOF_STACK_BASE - SOF_STACK_SIZE)
-
-#define MAILBOX_BASE (SOF_STACK_END - MAILBOX_SIZE)
-
-/* Vector and literal sizes - not in core-isa.h */
-#define SOF_MEM_VECT_LIT_SIZE 0x4
-#define SOF_MEM_VECT_TEXT_SIZE 0x1c
-#define SOF_MEM_VECT_SIZE (SOF_MEM_VECT_TEXT_SIZE + SOF_MEM_VECT_LIT_SIZE)
-
-#define SOF_MEM_RESET_TEXT_SIZE 0x2e0
-#define SOF_MEM_RESET_LIT_SIZE 0x120
-#define SOF_MEM_VECBASE_LIT_SIZE 0x178
-
-#define SOF_MEM_RO_SIZE 0x8
-
-#endif
diff --git a/src/platform/haswell/include/platform/platcfg.h b/src/platform/haswell/include/platform/platcfg.h
deleted file mode 100644
index d41be5a..0000000
--- a/src/platform/haswell/include/platform/platcfg.h
+++ /dev/null
@@ -1,38 +0,0 @@
-/*
- * Copyright (c) 2018, Intel Corporation
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- * * Redistributions of source code must retain the above copyright
- * notice, this list of conditions and the following disclaimer.
- * * Redistributions in binary form must reproduce the above copyright
- * notice, this list of conditions and the following disclaimer in the
- * documentation and/or other materials provided with the distribution.
- * * Neither the name of the Intel Corporation nor the
- * names of its contributors may be used to endorse or promote products
- * derived from this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
- * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
- * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
- * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
- * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
- * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
- * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
- * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
- * POSSIBILITY OF SUCH DAMAGE.
- *
- * Author: Marcin Maka <marcin.maka@linux.intel.com>
- */
-
-#ifndef __PLATFORM_PLATCFG_H__
-#define __PLATFORM_PLATCFG_H__
-
-#define PLATFORM_CORE_COUNT 1
-
-#define PLATFORM_MASTER_CORE_ID 0
-
-#endif
diff --git a/src/platform/haswell/include/platform/platform.h b/src/platform/haswell/include/platform/platform.h
deleted file mode 100644
index 4a7f9b3..0000000
--- a/src/platform/haswell/include/platform/platform.h
+++ /dev/null
@@ -1,114 +0,0 @@
-/*
- * Copyright (c) 2016, Intel Corporation
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- * * Redistributions of source code must retain the above copyright
- * notice, this list of conditions and the following disclaimer.
- * * Redistributions in binary form must reproduce the above copyright
- * notice, this list of conditions and the following disclaimer in the
- * documentation and/or other materials provided with the distribution.
- * * Neither the name of the Intel Corporation nor the
- * names of its contributors may be used to endorse or promote products
- * derived from this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
- * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
- * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
- * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
- * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
- * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
- * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
- * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
- * POSSIBILITY OF SUCH DAMAGE.
- *
- * Authors: Liam Girdwood <liam.r.girdwood@linux.intel.com>
- * Xiuli Pan <xiuli.pan@linux.intel.com>
- */
-
-#ifndef __PLATFORM_PLATFORM_H__
-#define __PLATFORM_PLATFORM_H__
-
-#include <sof/platform.h>
-#include <platform/shim.h>
-#include <platform/interrupt.h>
-#include <uapi/ipc.h>
-
-struct sof;
-
-/* IPC Interrupt */
-#define PLATFORM_IPC_INTERUPT IRQ_NUM_EXT_IA
-
-/* Host page size */
-#define HOST_PAGE_SIZE 4096
-#define PLATFORM_PAGE_TABLE_SIZE 256
-
-/* pipeline IRQ */
-#define PLATFORM_SCHEDULE_IRQ IRQ_NUM_SOFTWARE2
-
-#define PLATFORM_IRQ_TASK_HIGH IRQ_NUM_SOFTWARE2
-#define PLATFORM_IRQ_TASK_MED IRQ_NUM_SOFTWARE1
-#define PLATFORM_IRQ_TASK_LOW IRQ_NUM_SOFTWARE1
-
-#define PLATFORM_SCHEDULE_COST 200
-
-/* maximum preload pipeline depth */
-#define MAX_PRELOAD_SIZE 20
-
-/* DMA treats PHY addresses as host address unless within DSP region */
-#define PLATFORM_HOST_DMA_MASK 0xFFF00000
-
-/* Platform stream capabilities */
-#define PLATFORM_MAX_CHANNELS 4
-#define PLATFORM_MAX_STREAMS 5
-
-/* clock source used by scheduler for deadline calculations */
-#define PLATFORM_SCHED_CLOCK CLK_CPU
-
-/* DMA channel drain timeout in microseconds - TODO: caclulate based on topology */
-#define PLATFORM_DMA_TIMEOUT 1333
-
-/* DMA host transfer timeouts in microseconds */
-#define PLATFORM_HOST_DMA_TIMEOUT 50
-
-/* WorkQ window size in microseconds */
-#define PLATFORM_WORKQ_WINDOW 2000
-
-/* platform WorkQ clock */
-#define PLATFORM_WORKQ_CLOCK CLK_CPU
-
-/* local buffer size of DMA tracing */
-#define DMA_TRACE_LOCAL_SIZE HOST_PAGE_SIZE
-
-/* trace bytes flushed during panic */
-#define DMA_FLUSH_TRACE_SIZE (MAILBOX_TRACE_SIZE >> 2)
-
-/* the interval of DMA trace copying */
-#define DMA_TRACE_PERIOD 500000
-
-/*
- * the interval of reschedule DMA trace copying in special case like half
- * fullness of local DMA trace buffer
- */
-#define DMA_TRACE_RESCHEDULE_TIME 5
-
-/* DSP should be idle in this time frame */
-#define PLATFORM_IDLE_TIME 750000
-
-/* DSP default delay in cycles */
-#define PLATFORM_DEFAULT_DELAY 12
-
-/* Platform defined panic code */
-static inline void platform_panic(uint32_t p)
-{
- shim_write(SHIM_IPCX, MAILBOX_EXCEPTION_OFFSET & 0x3fffffff);
- shim_write(SHIM_IPCD, (SHIM_IPCD_BUSY | p));
-}
-
-/* Platform defined trace code */
-#define platform_trace_point(__x) \
- shim_write(SHIM_IPCX, ((__x) & 0x3fffffff))
-#endif
diff --git a/src/platform/haswell/include/platform/pm_runtime.h b/src/platform/haswell/include/platform/pm_runtime.h
deleted file mode 100644
index 1475838..0000000
--- a/src/platform/haswell/include/platform/pm_runtime.h
+++ /dev/null
@@ -1,60 +0,0 @@
-/*
- * Copyright (c) 2018, Intel Corporation
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- * * Redistributions of source code must retain the above copyright
- * notice, this list of conditions and the following disclaimer.
- * * Redistributions in binary form must reproduce the above copyright
- * notice, this list of conditions and the following disclaimer in the
- * documentation and/or other materials provided with the distribution.
- * * Neither the name of the Intel Corporation nor the
- * names of its contributors may be used to endorse or promote products
- * derived from this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
- * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
- * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
- * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
- * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
- * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
- * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
- * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
- * POSSIBILITY OF SUCH DAMAGE.
- *
- * Author: Tomasz Lauda <tomasz.lauda@linux.intel.com>
- */
-
-/**
- * \file platform/haswell/include/platform/pm_runtime.h
- * \brief Runtime power management header file for Haswell
- * \author Tomasz Lauda <tomasz.lauda@linux.intel.com>
- */
-
-#ifndef __INCLUDE_PLATFORM_PM_RUNTIME__
-#define __INCLUDE_PLATFORM_PM_RUNTIME__
-
-#include <sof/pm_runtime.h>
-
-/**
- * \brief Initializes platform specific runtime power management.
- * \param[in,out] prd Runtime power management data.
- */
-static inline void platform_pm_runtime_init(struct pm_runtime_data *prd) { }
-
-/**
- * \brief Retrieves platform specific power management resource.
- * \param[in] context Type of power management context.
- */
-static inline void platform_pm_runtime_get(enum pm_runtime_context context) { }
-
-/**
- * \brief Releases platform specific power management resource.
- * \param[in] context Type of power management context.
- */
-static inline void platform_pm_runtime_put(enum pm_runtime_context context) { }
-
-#endif /* __INCLUDE_PLATFORM_PM_RUNTIME__ */
diff --git a/src/platform/haswell/include/platform/shim.h b/src/platform/haswell/include/platform/shim.h
deleted file mode 100644
index fefaec9..0000000
--- a/src/platform/haswell/include/platform/shim.h
+++ /dev/null
@@ -1,137 +0,0 @@
-/*
- * Copyright (c) 2016, Intel Corporation
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- * * Redistributions of source code must retain the above copyright
- * notice, this list of conditions and the following disclaimer.
- * * Redistributions in binary form must reproduce the above copyright
- * notice, this list of conditions and the following disclaimer in the
- * documentation and/or other materials provided with the distribution.
- * * Neither the name of the Intel Corporation nor the
- * names of its contributors may be used to endorse or promote products
- * derived from this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
- * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
- * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
- * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
- * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
- * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
- * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
- * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
- * POSSIBILITY OF SUCH DAMAGE.
- *
- * Author: Liam Girdwood <liam.r.girdwood@linux.intel.com>
- */
-
-#ifndef __PLATFORM_SHIM_H__
-#define __PLATFORM_SHIM_H__
-
-#include <platform/memory.h>
-#include <sof/io.h>
-#include <stdint.h>
-
-#define SHIM_CSR 0x00
-#define SHIM_ISRX 0x18
-#define SHIM_ISRD 0x20
-#define SHIM_IMRX 0x28
-#define SHIM_IMRD 0x30
-#define SHIM_IPCX 0x38 /* IPC IA -> SST */
-#define SHIM_IPCD 0x40 /* IPC SST -> IA */
-
-#define SHIM_CLKCTL 0x78
-
-#define SHIM_CSR2 0x80
-#define SHIM_LTRC 0xE0
-#define SHIM_HMDC 0xE8
-
-#define SHIM_SHIM_BEGIN SHIM_CSR
-#define SHIM_SHIM_END SHIM_HMDC
-
-/* CSR 0x0 */
-#define SHIM_CSR_RST (0x1 << 1)
-#define SHIM_CSR_STALL (0x1 << 10)
-#define SHIM_CSR_SDPM0 (0x1 << 11)
-#define SHIM_CSR_SDPM1 (0x1 << 12)
-#define SHIM_CSR_PCE (0x1 << 15)
-#define SHIM_CSR_SFCR0 (0x1 << 27)
-#define SHIM_CSR_SFCR1 (0x1 << 28)
-#define SHIM_CSR_DCS(x) (x << 4)
-#define SHIM_CSR_DCS_MASK (0x7 << 4)
-#define SHIM_CSR_SFCR_SSP(x) (1 << (27 + x))
-
-/* ISRX 0x18 */
-#define SHIM_ISRX_BUSY (0x1 << 1)
-#define SHIM_ISRX_DONE (0x1 << 0)
-
-/* ISRD / ISD */
-#define SHIM_ISRD_BUSY (0x1 << 1)
-#define SHIM_ISRD_DONE (0x1 << 0)
-
-/* IMRX / IMC */
-#define SHIM_IMRX_BUSY (0x1 << 1)
-#define SHIM_IMRX_DONE (0x1 << 0)
-
-/* IMRD / IMD */
-#define SHIM_IMRD_DONE (0x1 << 0)
-#define SHIM_IMRD_BUSY (0x1 << 1)
-#define SHIM_IMRD_SSP0 (0x1 << 16)
-#define SHIM_IMRD_SSP1 (0x1 << 17)
-#define SHIM_IMRD_DMAC0 (0x1 << 21)
-#define SHIM_IMRD_DMAC1 (0x1 << 22)
-#define SHIM_IMRD_DMAC (SHIM_IMRD_DMAC0 | SHIM_IMRD_DMAC1)
-
-/* IPCX / IPCCH */
-#define SHIM_IPCX_DONE (0x1 << 30)
-#define SHIM_IPCX_BUSY (0x1 << 31)
-
-/* IPCDH */
-#define SHIM_IPCD_DONE (0x1 << 30)
-#define SHIM_IPCD_BUSY (0x1 << 31)
-
-/* CLKCTL */
-#define SHIM_CLKCTL_SMOS(x) (x << 24)
-#define SHIM_CLKCTL_MASK (3 << 24)
-#define SHIM_CLKCTL_DCPLCG (1 << 18)
-#define SHIM_CLKCTL_EN_SSP(x) (1 << (16 + x))
-
-/* CSR2 / CS2 */
-#define SHIM_CSR2_SDFD_SSP0 (1 << 1)
-#define SHIM_CSR2_SDFD_SSP1 (1 << 2)
-
-/* LTRC */
-#define SHIM_LTRC_VAL(x) (x << 0)
-
-/* HMDC */
-#define SHIM_HMDC_HDDA0(x) (x << 0)
-#define SHIM_HMDC_HDDA1(x) (x << 8)
-#define SHIM_HMDC_HDDA_CH_MASK 0xFF
-#define SHIM_HMDC_HDDA_E0_ALLCH SHIM_HMDC_HDDA0(SHIM_HMDC_HDDA_CH_MASK)
-#define SHIM_HMDC_HDDA_E1_ALLCH SHIM_HMDC_HDDA1(SHIM_HMDC_HDDA_CH_MASK)
-#define SHIM_HMDC_HDDA_ALLCH (SHIM_HMDC_HDDA_E0_ALLCH | SHIM_HMDC_HDDA_E1_ALLCH)
-
-/* PMCS */
-#define PCI_PMCS 0x84
-#define PCI_PMCS_PS_MASK 0x3
-
-static inline uint32_t shim_read(uint32_t reg)
-{
- return *((volatile uint32_t*)(SHIM_BASE + reg));
-}
-
-static inline void shim_write(uint32_t reg, uint32_t val)
-{
- *((volatile uint32_t*)(SHIM_BASE + reg)) = val;
-}
-
-static inline void shim_update_bits(uint32_t reg, uint32_t mask,
- uint32_t value)
-{
- io_reg_update_bits(SHIM_BASE + reg, mask, value);
-}
-
-#endif
diff --git a/src/platform/haswell/include/platform/timer.h b/src/platform/haswell/include/platform/timer.h
deleted file mode 100644
index c51e0e6..0000000
--- a/src/platform/haswell/include/platform/timer.h
+++ /dev/null
@@ -1,68 +0,0 @@
-/*
- * Copyright (c) 2016, Intel Corporation
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- * * Redistributions of source code must retain the above copyright
- * notice, this list of conditions and the following disclaimer.
- * * Redistributions in binary form must reproduce the above copyright
- * notice, this list of conditions and the following disclaimer in the
- * documentation and/or other materials provided with the distribution.
- * * Neither the name of the Intel Corporation nor the
- * names of its contributors may be used to endorse or promote products
- * derived from this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
- * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
- * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
- * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
- * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
- * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
- * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
- * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
- * POSSIBILITY OF SUCH DAMAGE.
- *
- * Author: Liam Girdwood <liam.r.girdwood@linux.intel.com>
- */
-
-
-#ifndef __PLATFORM_TIMER_H__
-#define __PLATFORM_TIMER_H__
-
-#include <stdint.h>
-#include <sof/timer.h>
-#include <platform/interrupt.h>
-
-#define TIMER_COUNT 3
-
-/* timer numbers must use associated IRQ number */
-#define TIMER0 IRQ_NUM_TIMER1
-#define TIMER1 IRQ_NUM_TIMER2
-#define TIMER2 IRQ_NUM_TIMER3
-
-struct comp_dev;
-struct sof_ipc_stream_posn;
-
-extern struct timer *platform_timer;
-
-int platform_timer_set(struct timer *timer, uint64_t ticks);
-void platform_timer_clear(struct timer *timer);
-uint64_t platform_timer_get(struct timer *timer);
-void platform_timer_start(struct timer *timer);
-void platform_timer_stop(struct timer *timer);
-
-/* get timestamp for host stream DMA position */
-void platform_host_timestamp(struct comp_dev *host,
- struct sof_ipc_stream_posn *posn);
-
-/* get timestamp for DAI stream DMA position */
-void platform_dai_timestamp(struct comp_dev *dai,
- struct sof_ipc_stream_posn *posn);
-
-/* get current wallclock for componnent */
-void platform_dai_wallclock(struct comp_dev *dai, uint64_t *wallclock);
-
-#endif
diff --git a/src/platform/haswell/memory.c b/src/platform/haswell/memory.c
deleted file mode 100644
index e1eb7cf..0000000
--- a/src/platform/haswell/memory.c
+++ /dev/null
@@ -1,89 +0,0 @@
-/*
- * Copyright (c) 2018, Intel Corporation
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- * * Redistributions of source code must retain the above copyright
- * notice, this list of conditions and the following disclaimer.
- * * Redistributions in binary form must reproduce the above copyright
- * notice, this list of conditions and the following disclaimer in the
- * documentation and/or other materials provided with the distribution.
- * * Neither the name of the Intel Corporation nor the
- * names of its contributors may be used to endorse or promote products
- * derived from this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
- * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
- * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
- * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
- * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
- * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
- * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
- * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
- * POSSIBILITY OF SUCH DAMAGE.
- *
- * Author: Liam Girdwood <liam.r.girdwood@linux.intel.com>
- */
-
-#include <sof/alloc.h>
-
-/* Heap blocks for modules */
-static struct block_hdr mod_block16[HEAP_RT_COUNT16];
-static struct block_hdr mod_block32[HEAP_RT_COUNT32];
-static struct block_hdr mod_block64[HEAP_RT_COUNT64];
-static struct block_hdr mod_block128[HEAP_RT_COUNT128];
-static struct block_hdr mod_block256[HEAP_RT_COUNT256];
-static struct block_hdr mod_block512[HEAP_RT_COUNT512];
-static struct block_hdr mod_block1024[HEAP_RT_COUNT1024];
-
-/* Heap memory map for modules */
-static struct block_map rt_heap_map[] = {
- BLOCK_DEF(16, HEAP_RT_COUNT16, mod_block16),
- BLOCK_DEF(32, HEAP_RT_COUNT32, mod_block32),
- BLOCK_DEF(64, HEAP_RT_COUNT64, mod_block64),
- BLOCK_DEF(128, HEAP_RT_COUNT128, mod_block128),
- BLOCK_DEF(256, HEAP_RT_COUNT256, mod_block256),
- BLOCK_DEF(512, HEAP_RT_COUNT512, mod_block512),
- BLOCK_DEF(1024, HEAP_RT_COUNT1024, mod_block1024),
-};
-
-/* Heap blocks for buffers */
-static struct block_hdr buf_block[HEAP_BUFFER_COUNT];
-
-/* Heap memory map for buffers */
-static struct block_map buf_heap_map[] = {
- BLOCK_DEF(HEAP_BUFFER_BLOCK_SIZE, HEAP_BUFFER_COUNT, buf_block),
-};
-
-struct mm memmap = {
- .system = {
- .heap = HEAP_SYSTEM_BASE,
- .size = HEAP_SYSTEM_SIZE,
- .info = {.free = HEAP_SYSTEM_SIZE,},
- .caps = SOF_MEM_CAPS_RAM | SOF_MEM_CAPS_CACHE |
- SOF_MEM_CAPS_DMA,
- },
- .runtime[0] = {
- .blocks = ARRAY_SIZE(rt_heap_map),
- .map = rt_heap_map,
- .heap = HEAP_RUNTIME_BASE,
- .size = HEAP_RUNTIME_SIZE,
- .info = {.free = HEAP_RUNTIME_SIZE,},
- .caps = SOF_MEM_CAPS_RAM | SOF_MEM_CAPS_CACHE |
- SOF_MEM_CAPS_DMA,
- },
- .buffer[0] = {
- .blocks = ARRAY_SIZE(buf_heap_map),
- .map = buf_heap_map,
- .heap = HEAP_BUFFER_BASE,
- .size = HEAP_BUFFER_SIZE,
- .info = {.free = HEAP_BUFFER_SIZE,},
- .caps = SOF_MEM_CAPS_RAM | SOF_MEM_CAPS_CACHE |
- SOF_MEM_CAPS_DMA,
- },
- .total = {.free = HEAP_SYSTEM_SIZE + HEAP_RUNTIME_SIZE +
- HEAP_BUFFER_SIZE,},
-};
diff --git a/src/platform/haswell/platform.c b/src/platform/haswell/platform.c
deleted file mode 100644
index 2281504..0000000
--- a/src/platform/haswell/platform.c
+++ /dev/null
@@ -1,302 +0,0 @@
-/*
- * Copyright (c) 2016, Intel Corporation
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- * * Redistributions of source code must retain the above copyright
- * notice, this list of conditions and the following disclaimer.
- * * Redistributions in binary form must reproduce the above copyright
- * notice, this list of conditions and the following disclaimer in the
- * documentation and/or other materials provided with the distribution.
- * * Neither the name of the Intel Corporation nor the
- * names of its contributors may be used to endorse or promote products
- * derived from this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
- * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
- * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
- * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
- * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
- * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
- * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
- * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
- * POSSIBILITY OF SUCH DAMAGE.
- *
- * Author: Liam Girdwood <liam.r.girdwood@linux.intel.com>
- */
-
-#include <platform/memory.h>
-#include <platform/mailbox.h>
-#include <platform/shim.h>
-#include <platform/dma.h>
-#include <platform/clk.h>
-#include <platform/timer.h>
-#include <uapi/ipc.h>
-#include <sof/mailbox.h>
-#include <sof/dai.h>
-#include <sof/dma.h>
-#include <sof/interrupt.h>
-#include <sof/sof.h>
-#include <sof/work.h>
-#include <sof/clock.h>
-#include <sof/ipc.h>
-#include <sof/trace.h>
-#include <sof/agent.h>
-#include <sof/io.h>
-#include <sof/dma-trace.h>
-#include <sof/audio/component.h>
-#include <config.h>
-#include <string.h>
-#include <version.h>
-
-static const struct sof_ipc_fw_ready ready = {
- .hdr = {
- .cmd = SOF_IPC_FW_READY,
- .size = sizeof(struct sof_ipc_fw_ready),
- },
- /* dspbox is for DSP initiated IPC, hostbox is for host initiated IPC */
- .version = {
- .build = SOF_BUILD,
- .minor = SOF_MINOR,
- .major = SOF_MAJOR,
- .date = __DATE__,
- .time = __TIME__,
- .tag = SOF_TAG,
- },
- /* TODO: add capabilities */
-};
-
-#define NUM_HSW_WINDOWS 6
-static const struct sof_ipc_window sram_window = {
- .ext_hdr = {
- .hdr.cmd = SOF_IPC_FW_READY,
- .hdr.size = sizeof(struct sof_ipc_window) +
- sizeof(struct sof_ipc_window_elem) * NUM_HSW_WINDOWS,
- .type = SOF_IPC_EXT_WINDOW,
- },
- .num_windows = NUM_HSW_WINDOWS,
- .window = {
- {
- .type = SOF_IPC_REGION_UPBOX,
- .id = 0, /* map to host window 0 */
- .flags = 0, // TODO: set later
- .size = MAILBOX_DSPBOX_SIZE,
- .offset = MAILBOX_DSPBOX_OFFSET,
- },
- {
- .type = SOF_IPC_REGION_DOWNBOX,
- .id = 0, /* map to host window 0 */
- .flags = 0, // TODO: set later
- .size = MAILBOX_HOSTBOX_SIZE,
- .offset = MAILBOX_HOSTBOX_OFFSET,
- },
- {
- .type = SOF_IPC_REGION_DEBUG,
- .id = 0, /* map to host window 0 */
- .flags = 0, // TODO: set later
- .size = MAILBOX_DEBUG_SIZE,
- .offset = MAILBOX_DEBUG_OFFSET,
- },
- {
- .type = SOF_IPC_REGION_TRACE,
- .id = 0, /* map to host window 0 */
- .flags = 0, // TODO: set later
- .size = MAILBOX_TRACE_SIZE,
- .offset = MAILBOX_TRACE_OFFSET,
- },
- {
- .type = SOF_IPC_REGION_STREAM,
- .id = 0, /* map to host window 0 */
- .flags = 0, // TODO: set later
- .size = MAILBOX_STREAM_SIZE,
- .offset = MAILBOX_STREAM_OFFSET,
- },
- {
- .type = SOF_IPC_REGION_EXCEPTION,
- .id = 0, /* map to host window 0 */
- .flags = 0, // TODO: set later
- .size = MAILBOX_EXCEPTION_SIZE,
- .offset = MAILBOX_EXCEPTION_OFFSET,
- },
- },
-};
-
-static struct work_queue_timesource platform_generic_queue = {
- .timer = {
- .id = TIMER1, /* internal timer */
- .irq = IRQ_NUM_TIMER2,
- },
- .clk = CLK_CPU,
- .notifier = NOTIFIER_ID_CPU_FREQ,
- .timer_set = arch_timer_set,
- .timer_clear = arch_timer_clear,
- .timer_get = arch_timer_get_system,
-};
-
-struct timer *platform_timer = &platform_generic_queue.timer;
-
-int platform_boot_complete(uint32_t boot_message)
-{
- uint32_t outbox = MAILBOX_HOST_OFFSET >> 3;
-
- mailbox_dspbox_write(0, &ready, sizeof(ready));
- mailbox_dspbox_write(sizeof(ready), &sram_window,
- sram_window.ext_hdr.hdr.size);
-
- /* now interrupt host to tell it we are done booting */
- shim_write(SHIM_IPCD, outbox | SHIM_IPCD_BUSY);
-
- /* boot now complete so we can relax the CPU */
- clock_set_freq(CLK_CPU, CLK_DEFAULT_CPU_HZ);
-
- return 0;
-}
-
-void platform_interrupt_set(int irq)
-{
- arch_interrupt_set(irq);
-}
-
-/* clear mask in PISR, bits are W1C in docs but some bits need preserved ?? */
-void platform_interrupt_clear(uint32_t irq, uint32_t mask)
-{
- switch (irq) {
- case IRQ_NUM_EXT_DMAC0:
- case IRQ_NUM_EXT_DMAC1:
- case IRQ_NUM_EXT_SSP0:
- case IRQ_NUM_EXT_SSP1:
- interrupt_clear(irq);
- break;
- default:
- break;
- }
-}
-
-/* TODO: expand this to 64 bit - should we just return mask of IRQ numbers */
-uint32_t platform_interrupt_get_enabled(void)
-{
- return shim_read(SHIM_IMRD);
-}
-
-void platform_interrupt_mask(uint32_t irq, uint32_t mask)
-{
- switch (irq) {
- case IRQ_NUM_EXT_SSP0:
- shim_write(SHIM_IMRD, SHIM_IMRD_SSP0);
- break;
- case IRQ_NUM_EXT_SSP1:
- shim_write(SHIM_IMRD, SHIM_IMRD_SSP1);
- break;
- case IRQ_NUM_EXT_DMAC0:
- shim_write(SHIM_IMRD, SHIM_IMRD_DMAC0);
- break;
- case IRQ_NUM_EXT_DMAC1:
- shim_write(SHIM_IMRD, SHIM_IMRD_DMAC1);
- break;
- default:
- break;
- }
-}
-
-void platform_interrupt_unmask(uint32_t irq, uint32_t mask)
-{
- switch (irq) {
- case IRQ_NUM_EXT_SSP0:
- shim_write(SHIM_IMRD, shim_read(SHIM_IMRD) & ~SHIM_IMRD_SSP0);
- break;
- case IRQ_NUM_EXT_SSP1:
- shim_write(SHIM_IMRD, shim_read(SHIM_IMRD) & ~SHIM_IMRD_SSP1);
- break;
- case IRQ_NUM_EXT_DMAC0:
- shim_write(SHIM_IMRD, shim_read(SHIM_IMRD) & ~SHIM_IMRD_DMAC0);
- break;
- case IRQ_NUM_EXT_DMAC1:
- shim_write(SHIM_IMRD, shim_read(SHIM_IMRD) & ~SHIM_IMRD_DMAC1);
- break;
- default:
- break;
- }
-}
-
-/* init shim registers */
-static void platform_init_shim(void)
-{
- /* disable power gate */
- io_reg_update_bits(SHIM_BASE + SHIM_CLKCTL,
- SHIM_CLKCTL_DCPLCG,
- SHIM_CLKCTL_DCPLCG);
-
- /* disable parity check */
- io_reg_update_bits(SHIM_BASE + SHIM_CSR, SHIM_CSR_PCE, 0);
-
- /* enable DMA finsh on ssp ports */
- io_reg_update_bits(SHIM_BASE + SHIM_CSR2,
- SHIM_CSR2_SDFD_SSP0 | SHIM_CSR2_SDFD_SSP1,
- SHIM_CSR2_SDFD_SSP0 | SHIM_CSR2_SDFD_SSP1);
-}
-
-int platform_init(struct sof *sof)
-{
- struct dai *ssp0;
- struct dai *ssp1;
- int ret;
-
- trace_point(TRACE_BOOT_PLATFORM_MBOX);
-
- /* clear mailbox for early trace and debug */
- bzero((void *)MAILBOX_BASE, IPC_MAX_MAILBOX_BYTES);
-
- trace_point(TRACE_BOOT_PLATFORM_SHIM);
- platform_init_shim();
-
- trace_point(TRACE_BOOT_PLATFORM_CLOCK);
- init_platform_clocks();
-
- /* init work queues and clocks */
- trace_point(TRACE_BOOT_SYS_WORK);
- init_system_workq(&platform_generic_queue);
-
- trace_point(TRACE_BOOT_PLATFORM_TIMER);
- platform_timer_start(platform_timer);
-
- /* init the system agent */
- sa_init(sof);
-
- /* Set CPU to default frequency for booting */
- trace_point(TRACE_BOOT_SYS_CPU_FREQ);
- clock_set_freq(CLK_CPU, CLK_MAX_CPU_HZ);
-
- /* set SSP clock to 25M */
- trace_point(TRACE_BOOT_PLATFORM_SSP_FREQ);
- clock_set_freq(CLK_SSP, 25000000);
-
- /* initialise the host IPC mechanisms */
- trace_point(TRACE_BOOT_PLATFORM_IPC);
- ipc_init(sof);
-
- /* init DMACs */
- trace_point(TRACE_BOOT_PLATFORM_DMA);
- ret = dmac_init();
- if (ret < 0)
- return -ENODEV;
-
- /* init SSP ports */
- trace_point(TRACE_BOOT_PLATFORM_SSP);
- ssp0 = dai_get(SOF_DAI_INTEL_SSP, 0);
- if (ssp0 == NULL)
- return -ENODEV;
- dai_probe(ssp0);
-
- ssp1 = dai_get(SOF_DAI_INTEL_SSP, 1);
- if (ssp1 == NULL)
- return -ENODEV;
- dai_probe(ssp1);
-
- /* Initialize DMA for Trace*/
- dma_trace_init_complete(sof->dmat);
-
- return 0;
-}
diff --git a/src/platform/haswell/timer.c b/src/platform/haswell/timer.c
deleted file mode 100644
index ebdbd07..0000000
--- a/src/platform/haswell/timer.c
+++ /dev/null
@@ -1,108 +0,0 @@
-/*
- * Copyright (c) 2016, Intel Corporation
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- * * Redistributions of source code must retain the above copyright
- * notice, this list of conditions and the following disclaimer.
- * * Redistributions in binary form must reproduce the above copyright
- * notice, this list of conditions and the following disclaimer in the
- * documentation and/or other materials provided with the distribution.
- * * Neither the name of the Intel Corporation nor the
- * names of its contributors may be used to endorse or promote products
- * derived from this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
- * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
- * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
- * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
- * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
- * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
- * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
- * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
- * POSSIBILITY OF SUCH DAMAGE.
- *
- * Author: Liam Girdwood <liam.r.girdwood@linux.intel.com>
- */
-
-#include <platform/timer.h>
-#include <platform/shim.h>
-#include <platform/interrupt.h>
-#include <sof/debug.h>
-#include <sof/audio/component.h>
-#include <stdint.h>
-
-void platform_timer_start(struct timer *timer)
-{
- arch_timer_enable(timer);
-}
-
-void platform_timer_stop(struct timer *timer)
-{
- arch_timer_disable(timer);
-}
-
-int platform_timer_set(struct timer *timer, uint64_t ticks)
-{
- return arch_timer_set(timer, ticks);
-}
-
-void platform_timer_clear(struct timer *timer)
-{
- arch_timer_clear(timer);
-}
-
-uint64_t platform_timer_get(struct timer *timer)
-{
- return arch_timer_get_system(timer);
-}
-
-/* get timestamp for host stream DMA position */
-void platform_host_timestamp(struct comp_dev *host,
- struct sof_ipc_stream_posn *posn)
-{
- int err;
-
- /* get host postion */
- err = comp_position(host, posn);
- if (err == 0)
- posn->flags |= SOF_TIME_HOST_VALID | SOF_TIME_HOST_64;
-}
-
-/* get timestamp for DAI stream DMA position */
-void platform_dai_timestamp(struct comp_dev *dai,
- struct sof_ipc_stream_posn *posn)
-{
- int err;
-
- /* get DAI postion */
- err = comp_position(dai, posn);
- if (err == 0)
- posn->flags |= SOF_TIME_DAI_VALID;
-
- /* get SSP wallclock - DAI sets this to stream start value */
- posn->wallclock = timer_get_system(platform_timer) - posn->wallclock;
- posn->flags |= SOF_TIME_WALL_VALID | SOF_TIME_WALL_64;
-}
-
-/* get current wallclock for componnent */
-void platform_dai_wallclock(struct comp_dev *dai, uint64_t *wallclock)
-{
- /* only 1 wallclock on HSW */
- *wallclock = timer_get_system(platform_timer);
-}
-
-int timer_register(struct timer *timer, void(*handler)(void *arg), void *arg)
-{
- switch (timer->id) {
- case TIMER0:
- case TIMER1:
- case TIMER2:
- return arch_timer_register(timer, handler, arg);
- default:
- return -EINVAL;
- }
-}
diff --git a/src/platform/intel/Makefile.am b/src/platform/intel/Makefile.am
deleted file mode 100644
index 6a966ba..0000000
--- a/src/platform/intel/Makefile.am
+++ /dev/null
@@ -1,5 +0,0 @@
-SUBDIRS = include
-
-if BUILD_CAVS
-SUBDIRS += cavs
-endif
\ No newline at end of file
diff --git a/src/platform/intel/cavs/Makefile.am b/src/platform/intel/cavs/Makefile.am
deleted file mode 100644
index 503d604..0000000
--- a/src/platform/intel/cavs/Makefile.am
+++ /dev/null
@@ -1,18 +0,0 @@
-noinst_LTLIBRARIES = libcavsplatform.la
-
-libcavsplatform_la_SOURCES = \
- platform.c \
- dai.c \
- dma.c \
- clk.c \
- timer.c \
- interrupt.c \
- memory.c \
- pm_runtime.c
-
-libcavsplatform_la_CFLAGS = \
- $(AM_CFLAGS) \
- $(ARCH_CFLAGS) \
- $(ARCH_INCDIR) \
- $(PLATFORM_INCDIR) \
- $(SOF_INCDIR)
diff --git a/src/platform/intel/cavs/clk.c b/src/platform/intel/cavs/clk.c
deleted file mode 100644
index c49fc00..0000000
--- a/src/platform/intel/cavs/clk.c
+++ /dev/null
@@ -1,247 +0,0 @@
-/*
- * Copyright (c) 2018, Intel Corporation
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- * * Redistributions of source code must retain the above copyright
- * notice, this list of conditions and the following disclaimer.
- * * Redistributions in binary form must reproduce the above copyright
- * notice, this list of conditions and the following disclaimer in the
- * documentation and/or other materials provided with the distribution.
- * * Neither the name of the Intel Corporation nor the
- * names of its contributors may be used to endorse or promote products
- * derived from this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
- * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
- * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
- * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
- * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
- * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
- * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
- * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
- * POSSIBILITY OF SUCH DAMAGE.
- *
- * Author: Liam Girdwood <liam.r.girdwood@linux.intel.com>
- * Keyon Jie <yang.jie@linux.intel.com>
- * Rander Wang <rander.wang@intel.com>
- * Janusz Jankowski <janusz.jankowski@linux.intel.com>
- */
-
-#include <sof/clock.h>
-#include <sof/io.h>
-#include <sof/sof.h>
-#include <sof/list.h>
-#include <sof/alloc.h>
-#include <sof/notifier.h>
-#include <sof/lock.h>
-#include <platform/clk.h>
-#include <platform/shim.h>
-#include <platform/timer.h>
-#include <config.h>
-#include <stdint.h>
-#include <limits.h>
-
-#define NUM_CLOCKS 2
-
-struct clk_data {
- uint32_t freq;
- uint32_t ticks_per_usec;
- uint32_t ticks_per_msec;
- spinlock_t lock;
-};
-
-struct clk_pdata {
- struct clk_data clk[NUM_CLOCKS];
-};
-
-struct freq_table {
- uint32_t freq;
- uint32_t ticks_per_usec;
- uint32_t ticks_per_msec;
- uint32_t enc;
-};
-
-static struct clk_pdata *clk_pdata;
-
-/* increasing frequency order */
-
-#if defined(CONFIG_APOLLOLAKE)
-static const struct freq_table cpu_freq[] = {
- {100000000, 100, 100000, 0x3},
- {200000000, 200, 200000, 0x1},
- {400000000, 400, 400000, 0x0}, /* default */
-};
-#elif defined(CONFIG_CANNONLAKE)
-static const struct freq_table cpu_freq[] = {
- {120000000, 120, 120000, 0x0},
- {400000000, 400, 400000, 0x4},
-};
-#endif
-
-/*
- * XTAL clock, used as Wall Clock(external timer),
- */
-
-#if defined(CONFIG_APOLLOLAKE)
-static const struct freq_table ssp_freq[] = {
- {19200000, 19, 19200, }, /* default */
- {24576000, 24, 24576, },
-};
-#elif defined(CONFIG_CANNONLAKE)
-static const struct freq_table ssp_freq[] = {
- {19200000, 19, 19200, },
- {24000000, 24, 24000, }, /* default */
-};
-#endif
-
-#if defined(CONFIG_APOLLOLAKE)
-#define CPU_DEFAULT_IDX 2
-#define SSP_DEFAULT_IDX 0
-#elif defined(CONFIG_CANNONLAKE)
-#define CPU_DEFAULT_IDX 1
-#define SSP_DEFAULT_IDX 1
-#endif
-
-static inline uint32_t get_freq(const struct freq_table *table, int size,
- unsigned int hz)
-{
- uint32_t i;
-
- /* find lowest available frequency that is >= requested hz */
- for (i = 0; i < size; i++) {
- if (hz <= table[i].freq)
- return i;
- }
-
- /* not found, so return max frequency */
- return size - 1;
-}
-
-void clock_enable(int clock)
-{
- switch (clock) {
- case CLK_CPU:
- break;
- case CLK_SSP:
- default:
- break;
- }
-}
-
-void clock_disable(int clock)
-{
- switch (clock) {
- case CLK_CPU:
- break;
- case CLK_SSP:
- default:
- break;
- }
-}
-
-uint32_t clock_set_freq(int clock, uint32_t hz)
-{
- struct clock_notify_data notify_data;
- uint32_t idx;
- uint32_t flags;
-
- notify_data.old_freq = clk_pdata->clk[clock].freq;
- notify_data.old_ticks_per_usec = clk_pdata->clk[clock].ticks_per_usec;
-
- /* atomic context for chaning clocks */
- spin_lock_irq(&clk_pdata->clk[clock].lock, flags);
-
- switch (clock) {
- case CLK_CPU:
- /* get nearest frequency that is >= requested Hz */
- idx = get_freq(cpu_freq, ARRAY_SIZE(cpu_freq), hz);
- notify_data.freq = cpu_freq[idx].freq;
-
- /* tell anyone interested we are about to change CPU freq */
- notifier_event(NOTIFIER_ID_CPU_FREQ, CLOCK_NOTIFY_PRE,
- ¬ify_data);
-
- /* set CPU frequency request for CCU */
- #if defined(CONFIG_APOLLOLAKE)
- io_reg_update_bits(SHIM_BASE + SHIM_CLKCTL,
- SHIM_CLKCTL_HDCS, 0);
- #endif
- io_reg_update_bits(SHIM_BASE + SHIM_CLKCTL,
- SHIM_CLKCTL_DPCS_MASK(0), cpu_freq[idx].enc);
-
- /* tell anyone interested we have now changed CPU freq */
- notifier_event(NOTIFIER_ID_CPU_FREQ, CLOCK_NOTIFY_POST,
- ¬ify_data);
- break;
- case CLK_SSP:
- default:
- break;
- }
-
- spin_unlock_irq(&clk_pdata->clk[clock].lock, flags);
- return clk_pdata->clk[clock].freq;
-}
-
-uint32_t clock_get_freq(int clock)
-{
- return clk_pdata->clk[clock].freq;
-}
-
-uint64_t clock_us_to_ticks(int clock, uint64_t us)
-{
- return clk_pdata->clk[clock].ticks_per_usec * us;
-}
-
-uint64_t clock_ms_to_ticks(int clock, uint64_t ms)
-{
- return clk_pdata->clk[clock].ticks_per_msec * ms;
-}
-
-uint64_t clock_time_elapsed(int clock, uint64_t previous, uint64_t *current)
-{
- uint64_t _current;
-
- // TODO: change timer APIs to clk APIs ??
- switch (clock) {
- case CLK_CPU:
- _current = arch_timer_get_system(NULL);
- break;
- case CLK_SSP:
- _current = platform_timer_get(platform_timer);
- break;
- default:
- return 0;
- }
-
- *current = _current;
- if (_current >= previous)
- return (_current - previous) /
- clk_pdata->clk[clock].ticks_per_usec;
- else
- return (_current + (ULONG_LONG_MAX - previous)) /
- clk_pdata->clk[clock].ticks_per_usec;
-}
-
-void init_platform_clocks(void)
-{
- clk_pdata = rmalloc(RZONE_SYS, SOF_MEM_CAPS_RAM, sizeof(*clk_pdata));
-
- spinlock_init(&clk_pdata->clk[0].lock);
- spinlock_init(&clk_pdata->clk[1].lock);
-
- /* set defaults */
- clk_pdata->clk[CLK_CPU].freq = cpu_freq[CPU_DEFAULT_IDX].freq;
- clk_pdata->clk[CLK_CPU].ticks_per_usec =
- cpu_freq[CPU_DEFAULT_IDX].ticks_per_usec;
- clk_pdata->clk[CLK_CPU].ticks_per_msec =
- cpu_freq[CPU_DEFAULT_IDX].ticks_per_msec;
- clk_pdata->clk[CLK_SSP].freq = ssp_freq[SSP_DEFAULT_IDX].freq;
- clk_pdata->clk[CLK_SSP].ticks_per_usec =
- ssp_freq[SSP_DEFAULT_IDX].ticks_per_usec;
- clk_pdata->clk[CLK_SSP].ticks_per_msec =
- ssp_freq[SSP_DEFAULT_IDX].ticks_per_msec;
-}
diff --git a/src/platform/intel/cavs/dai.c b/src/platform/intel/cavs/dai.c
deleted file mode 100644
index f8ec87c..0000000
--- a/src/platform/intel/cavs/dai.c
+++ /dev/null
@@ -1,302 +0,0 @@
-/*
- * Copyright (c) 2018, Intel Corporation
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- * * Redistributions of source code must retain the above copyright
- * notice, this list of conditions and the following disclaimer.
- * * Redistributions in binary form must reproduce the above copyright
- * notice, this list of conditions and the following disclaimer in the
- * documentation and/or other materials provided with the distribution.
- * * Neither the name of the Intel Corporation nor the
- * names of its contributors may be used to endorse or promote products
- * derived from this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
- * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
- * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
- * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
- * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
- * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
- * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
- * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
- * POSSIBILITY OF SUCH DAMAGE.
- *
- * Author: Liam Girdwood <liam.r.girdwood@linux.intel.com>
- * Keyon Jie <yang.jie@linux.intel.com>
- * Rander Wang <rander.wang@intel.com>
- * Janusz Jankowski <janusz.jankowski@linux.intel.com>
- */
-
-#include <sof/sof.h>
-#include <sof/dai.h>
-#include <sof/ssp.h>
-#include <sof/dmic.h>
-#include <sof/stream.h>
-#include <sof/audio/component.h>
-#include <platform/platform.h>
-#include <platform/memory.h>
-#include <platform/interrupt.h>
-#include <platform/dma.h>
-#include <stdint.h>
-#include <string.h>
-#include <config.h>
-
-/* TODO: ops should be declared by their respective dai headers */
-extern const struct dai_ops hda_ops;
-
-static struct dai ssp[] = {
-{
- .type = SOF_DAI_INTEL_SSP,
- .index = 0,
- .plat_data = {
- .base = SSP_BASE(0),
- .irq = IRQ_EXT_SSP0_LVL5(0),
- .fifo[SOF_IPC_STREAM_PLAYBACK] = {
- .offset = SSP_BASE(0) + SSDR,
- .handshake = DMA_HANDSHAKE_SSP0_TX,
- },
- .fifo[SOF_IPC_STREAM_CAPTURE] = {
- .offset = SSP_BASE(0) + SSDR,
- .handshake = DMA_HANDSHAKE_SSP0_RX,
- }
- },
- .ops = &ssp_ops,
-},
-{
- .type = SOF_DAI_INTEL_SSP,
- .index = 1,
- .plat_data = {
- .base = SSP_BASE(1),
- .irq = IRQ_EXT_SSP1_LVL5(0),
- .fifo[SOF_IPC_STREAM_PLAYBACK] = {
- .offset = SSP_BASE(1) + SSDR,
- .handshake = DMA_HANDSHAKE_SSP1_TX,
- },
- .fifo[SOF_IPC_STREAM_CAPTURE] = {
- .offset = SSP_BASE(1) + SSDR,
- .handshake = DMA_HANDSHAKE_SSP1_RX,
- }
- },
- .ops = &ssp_ops,
-},
-{
- .type = SOF_DAI_INTEL_SSP,
- .index = 2,
- .plat_data = {
- .base = SSP_BASE(2),
- .irq = IRQ_EXT_SSP2_LVL5(0),
- .fifo[SOF_IPC_STREAM_PLAYBACK] = {
- .offset = SSP_BASE(2) + SSDR,
- .handshake = DMA_HANDSHAKE_SSP2_TX,
- },
- .fifo[SOF_IPC_STREAM_CAPTURE] = {
- .offset = SSP_BASE(2) + SSDR,
- .handshake = DMA_HANDSHAKE_SSP2_RX,
- }
- },
- .ops = &ssp_ops,
-},
-#if defined(CONFIG_APOLLOLAKE)
-{
- .type = SOF_DAI_INTEL_SSP,
- .index = 3,
- .plat_data = {
- .base = SSP_BASE(3),
- .irq = IRQ_EXT_SSP3_LVL5(0),
- .fifo[SOF_IPC_STREAM_PLAYBACK] = {
- .offset = SSP_BASE(3) + SSDR,
- .handshake = DMA_HANDSHAKE_SSP3_TX,
- },
- .fifo[SOF_IPC_STREAM_CAPTURE] = {
- .offset = SSP_BASE(3) + SSDR,
- .handshake = DMA_HANDSHAKE_SSP3_RX,
- }
- },
- .ops = &ssp_ops,
-},
-{
- .type = SOF_DAI_INTEL_SSP,
- .index = 4,
- .plat_data = {
- .base = SSP_BASE(4),
- .irq = IRQ_EXT_SSP4_LVL5(0),
- .fifo[SOF_IPC_STREAM_PLAYBACK] = {
- .offset = SSP_BASE(4) + SSDR,
- .handshake = DMA_HANDSHAKE_SSP4_TX,
- },
- .fifo[SOF_IPC_STREAM_CAPTURE] = {
- .offset = SSP_BASE(4) + SSDR,
- .handshake = DMA_HANDSHAKE_SSP4_RX,
- }
- },
- .ops = &ssp_ops,
-},
-{
- .type = SOF_DAI_INTEL_SSP,
- .index = 5,
- .plat_data = {
- .base = SSP_BASE(5),
- .irq = IRQ_EXT_SSP5_LVL5(0),
- .fifo[SOF_IPC_STREAM_PLAYBACK] = {
- .offset = SSP_BASE(5) + SSDR,
- .handshake = DMA_HANDSHAKE_SSP5_TX,
- },
- .fifo[SOF_IPC_STREAM_CAPTURE] = {
- .offset = SSP_BASE(5) + SSDR,
- .handshake = DMA_HANDSHAKE_SSP5_RX,
- }
- },
- .ops = &ssp_ops,
-},
-#endif
-};
-
-#if defined CONFIG_DMIC
-
-static struct dai dmic[2] = {
- /* Testing idea if DMIC FIFOs A and B to access the same microphones
- * with two different sample rate and PCM format could be presented
- * similarly as SSP0..N. The difference however is that the DMIC
- * programming is global and not per FIFO.
- */
-
- /* Primary FIFO A */
- {
- .type = SOF_DAI_INTEL_DMIC,
- .index = 0,
- .plat_data = {
- .base = DMIC_BASE,
- .irq = IRQ_EXT_DMIC_LVL5(0),
- .fifo[SOF_IPC_STREAM_PLAYBACK] = {
- .offset = 0, /* No playback */
- .handshake = 0,
- },
- .fifo[SOF_IPC_STREAM_CAPTURE] = {
- .offset = DMIC_BASE + OUTDATA0,
- .handshake = DMA_HANDSHAKE_DMIC_CH0,
- }
- },
- .ops = &dmic_ops,
- },
- /* Secondary FIFO B */
- {
- .type = SOF_DAI_INTEL_DMIC,
- .index = 1,
- .plat_data = {
- .base = DMIC_BASE,
- .irq = IRQ_EXT_DMIC_LVL5(0),
- .fifo[SOF_IPC_STREAM_PLAYBACK] = {
- .offset = 0, /* No playback */
- .handshake = 0,
- },
- .fifo[SOF_IPC_STREAM_CAPTURE] = {
- .offset = DMIC_BASE + OUTDATA1,
- .handshake = DMA_HANDSHAKE_DMIC_CH1,
- }
- },
- .ops = &dmic_ops,
- }
-};
-
-#endif
-
-/* TODO: numbers to be defined and shared with HD/A dmas */
-static struct dai hda[(6 + 7)] = {
- {
- .type = SOF_DAI_INTEL_HDA,
- .index = 0,
- .ops = &hda_ops
- },
- {
- .type = SOF_DAI_INTEL_HDA,
- .index = 1,
- .ops = &hda_ops
- },
- {
- .type = SOF_DAI_INTEL_HDA,
- .index = 2,
- .ops = &hda_ops
- },
- {
- .type = SOF_DAI_INTEL_HDA,
- .index = 3,
- .ops = &hda_ops
- },
- {
- .type = SOF_DAI_INTEL_HDA,
- .index = 4,
- .ops = &hda_ops
- },
- {
- .type = SOF_DAI_INTEL_HDA,
- .index = 5,
- .ops = &hda_ops
- },
- {
- .type = SOF_DAI_INTEL_HDA,
- .index = 6,
- .ops = &hda_ops
- },
- {
- .type = SOF_DAI_INTEL_HDA,
- .index = 7,
- .ops = &hda_ops
- },
- {
- .type = SOF_DAI_INTEL_HDA,
- .index = 8,
- .ops = &hda_ops
- },
- {
- .type = SOF_DAI_INTEL_HDA,
- .index = 9,
- .ops = &hda_ops
- },
- {
- .type = SOF_DAI_INTEL_HDA,
- .index = 10,
- .ops = &hda_ops
- },
- {
- .type = SOF_DAI_INTEL_HDA,
- .index = 11,
- .ops = &hda_ops
- },
- {
- .type = SOF_DAI_INTEL_HDA,
- .index = 12,
- .ops = &hda_ops
- }
-};
-
-struct dai *dai_get(uint32_t type, uint32_t index)
-{
- int i;
-
- if (type == SOF_DAI_INTEL_SSP) {
- for (i = 0; i < ARRAY_SIZE(ssp); i++) {
- if (ssp[i].type == type && ssp[i].index == index)
- return &ssp[i];
- }
- }
-
-#if defined CONFIG_DMIC
- if (type == SOF_DAI_INTEL_DMIC) {
- for (i = 0; i < ARRAY_SIZE(dmic); i++) {
- if (dmic[i].type == type && dmic[i].index == index)
- return &dmic[i];
- }
- }
-#endif
- if (type == SOF_DAI_INTEL_HDA) {
- for (i = 0; i < ARRAY_SIZE(hda); i++) {
- if (hda[i].type == type && hda[i].index == index)
- return &hda[i];
- }
- }
- return NULL;
-}
diff --git a/src/platform/intel/cavs/dma.c b/src/platform/intel/cavs/dma.c
deleted file mode 100644
index 225205b..0000000
--- a/src/platform/intel/cavs/dma.c
+++ /dev/null
@@ -1,226 +0,0 @@
-/*
- * Copyright (c) 2018, Intel Corporation
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- * * Redistributions of source code must retain the above copyright
- * notice, this list of conditions and the following disclaimer.
- * * Redistributions in binary form must reproduce the above copyright
- * notice, this list of conditions and the following disclaimer in the
- * documentation and/or other materials provided with the distribution.
- * * Neither the name of the Intel Corporation nor the
- * names of its contributors may be used to endorse or promote products
- * derived from this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
- * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
- * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
- * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
- * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
- * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
- * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
- * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
- * POSSIBILITY OF SUCH DAMAGE.
- *
- * Author: Liam Girdwood <liam.r.girdwood@linux.intel.com>
- * Keyon Jie <yang.jie@linux.intel.com>
- * Rander Wang <rander.wang@intel.com>
- * Janusz Jankowski <janusz.jankowski@linux.intel.com>
- */
-
-#include <sof/dma.h>
-#include <sof/dw-dma.h>
-#include <sof/hda-dma.h>
-#include <platform/memory.h>
-#include <platform/interrupt.h>
-#include <platform/dma.h>
-#include <stdint.h>
-#include <string.h>
-
-#if defined(CONFIG_APOLLOLAKE)
-#define DMAC0_CLASS 1
-#define DMAC1_CLASS 2
-#define DMAC_HOST_OUT_CHANNELS_COUNT 6
-#define DMAC_LINK_IN_CHANNELS_COUNT 8
-#define DMAC_LINK_OUT_CHANNELS_COUNT 8
-#elif defined(CONFIG_CANNONLAKE)
-#define DMAC0_CLASS 6
-#define DMAC1_CLASS 7
-#define DMAC_HOST_OUT_CHANNELS_COUNT 9
-#define DMAC_LINK_IN_CHANNELS_COUNT 9
-#define DMAC_LINK_OUT_CHANNELS_COUNT 7
-#endif
-
-static struct dw_drv_plat_data dmac0 = {
- .chan[0] = {
- .class = DMAC0_CLASS,
- .weight = 0,
- },
- .chan[1] = {
- .class = DMAC0_CLASS,
- .weight = 0,
- },
- .chan[2] = {
- .class = DMAC0_CLASS,
- .weight = 0,
- },
- .chan[3] = {
- .class = DMAC0_CLASS,
- .weight = 0,
- },
- .chan[4] = {
- .class = DMAC0_CLASS,
- .weight = 0,
- },
- .chan[5] = {
- .class = DMAC0_CLASS,
- .weight = 0,
- },
- .chan[6] = {
- .class = DMAC0_CLASS,
- .weight = 0,
- },
- .chan[7] = {
- .class = DMAC0_CLASS,
- .weight = 0,
- },
-};
-
-static struct dw_drv_plat_data dmac1 = {
- .chan[0] = {
- .class = DMAC1_CLASS,
- .weight = 0,
- },
- .chan[1] = {
- .class = DMAC1_CLASS,
- .weight = 0,
- },
- .chan[2] = {
- .class = DMAC1_CLASS,
- .weight = 0,
- },
- .chan[3] = {
- .class = DMAC1_CLASS,
- .weight = 0,
- },
- .chan[4] = {
- .class = DMAC1_CLASS,
- .weight = 0,
- },
- .chan[5] = {
- .class = DMAC1_CLASS,
- .weight = 0,
- },
- .chan[6] = {
- .class = DMAC1_CLASS,
- .weight = 0,
- },
- .chan[7] = {
- .class = DMAC1_CLASS,
- .weight = 0,
- },
-};
-
-struct dma dma[PLATFORM_NUM_DMACS] = {
-{ /* Low Power GP DMAC 0 */
- .plat_data = {
- .id = DMA_GP_LP_DMAC0,
- .dir = DMA_DIR_MEM_TO_MEM | DMA_DIR_MEM_TO_DEV |
- DMA_DIR_DEV_TO_MEM | DMA_DIR_DEV_TO_DEV,
- .caps = DMA_CAP_GP_LP,
- .devs = DMA_DEV_SSP | DMA_DEV_DMIC,
- .base = LP_GP_DMA_BASE(0),
- .channels = 8,
- .irq = IRQ_EXT_LP_GPDMA0_LVL5(0, 0),
- .drv_plat_data = &dmac0,
- },
- .ops = &dw_dma_ops,
-},
-{ /* Low Power GP DMAC 1 */
- .plat_data = {
- .id = DMA_GP_LP_DMAC1,
- .dir = DMA_DIR_MEM_TO_MEM | DMA_DIR_MEM_TO_DEV |
- DMA_DIR_DEV_TO_MEM | DMA_DIR_DEV_TO_DEV,
- .caps = DMA_CAP_GP_LP,
- .devs = DMA_DEV_SSP | DMA_DEV_DMIC,
- .base = LP_GP_DMA_BASE(1),
- .channels = 8,
- .irq = IRQ_EXT_LP_GPDMA1_LVL5(0, 0),
- .drv_plat_data = &dmac1,
- },
- .ops = &dw_dma_ops,
-},
-{ /* Host In DMAC */
- .plat_data = {
- .id = DMA_HOST_IN_DMAC,
- .dir = DMA_DIR_LMEM_TO_HMEM,
- .caps = DMA_CAP_HDA,
- .devs = DMA_DEV_HOST,
- .base = GTW_HOST_IN_STREAM_BASE(0),
- .channels = 7,
- .irq = IRQ_EXT_HOST_DMA_IN_LVL3(0, 0),
- .chan_size = GTW_HOST_IN_STREAM_SIZE,
- },
- .ops = &hda_host_dma_ops,
-},
-{ /* Host out DMAC */
- .plat_data = {
- .id = DMA_HOST_OUT_DMAC,
- .dir = DMA_DIR_HMEM_TO_LMEM,
- .caps = DMA_CAP_HDA,
- .devs = DMA_DEV_HOST,
- .base = GTW_HOST_OUT_STREAM_BASE(0),
- .channels = DMAC_HOST_OUT_CHANNELS_COUNT,
- .irq = IRQ_EXT_HOST_DMA_OUT_LVL3(0, 0),
- .chan_size = GTW_HOST_OUT_STREAM_SIZE,
- },
- .ops = &hda_host_dma_ops,
-},
-{ /* Link In DMAC */
- .plat_data = {
- .id = DMA_LINK_IN_DMAC,
- .dir = DMA_DIR_MEM_TO_DEV,
- .caps = DMA_CAP_HDA,
- .devs = DMA_DEV_HDA,
- .base = GTW_LINK_IN_STREAM_BASE(0),
- .channels = DMAC_LINK_IN_CHANNELS_COUNT,
- .irq = IRQ_EXT_LINK_DMA_IN_LVL4(0, 0),
- .chan_size = GTW_LINK_IN_STREAM_SIZE,
- },
- .ops = &hda_link_dma_ops,
-},
-{ /* Link out DMAC */
- .plat_data = {
- .id = DMA_LINK_OUT_DMAC,
- .dir = DMA_DIR_DEV_TO_MEM,
- .caps = DMA_CAP_HDA,
- .devs = DMA_DEV_HDA,
- .base = GTW_LINK_OUT_STREAM_BASE(0),
- .channels = DMAC_LINK_OUT_CHANNELS_COUNT,
- .irq = IRQ_EXT_LINK_DMA_OUT_LVL4(0, 0),
- .chan_size = GTW_LINK_OUT_STREAM_SIZE,
- },
- .ops = &hda_link_dma_ops,
-},};
-
-/* Initialize all platform DMAC's */
-int dmac_init(void)
-{
- int i, ret;
-
- for (i = 0; i < ARRAY_SIZE(dma); i++) {
- ret = dma_probe(&dma[i]);
- if (ret < 0) {
-
- /* trace failed DMAC ID */
- trace_error(TRACE_CLASS_DMA, "edi");
- trace_error_value(dma[i].plat_data.id);
- return ret;
- }
- }
-
- return 0;
-}
diff --git a/src/platform/intel/cavs/interrupt.c b/src/platform/intel/cavs/interrupt.c
deleted file mode 100644
index c01eb3b..0000000
--- a/src/platform/intel/cavs/interrupt.c
+++ /dev/null
@@ -1,243 +0,0 @@
-/*
- * Copyright (c) 2018, Intel Corporation
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- * * Redistributions of source code must retain the above copyright
- * notice, this list of conditions and the following disclaimer.
- * * Redistributions in binary form must reproduce the above copyright
- * notice, this list of conditions and the following disclaimer in the
- * documentation and/or other materials provided with the distribution.
- * * Neither the name of the Intel Corporation nor the
- * names of its contributors may be used to endorse or promote products
- * derived from this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
- * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
- * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
- * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
- * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
- * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
- * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
- * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
- * POSSIBILITY OF SUCH DAMAGE.
- *
- * Author: Keyon Jie <yang.jie@linux.intel.com>
- * Liam Girdwood <liam.r.girdwood@linux.intel.com>
- * Rander Wang <rander.wang@intel.com>
- * Janusz Jankowski <janusz.jankowski@linux.intel.com>
- *
- */
-
-#include <sof/sof.h>
-#include <sof/interrupt.h>
-#include <sof/interrupt-map.h>
-#include <sof/cpu.h>
-#include <arch/interrupt.h>
-#include <platform/interrupt.h>
-#include <platform/platcfg.h>
-#include <platform/shim.h>
-#include <stdint.h>
-#include <stdlib.h>
-
-static inline void irq_lvl2_handler(void *data,
- int level,
- uint32_t ilxsd,
- uint32_t ilxmsd,
- uint32_t ilxmcd)
-{
- struct irq_desc *parent = (struct irq_desc *)data;
- struct irq_desc *child = NULL;
- struct list_item *clist;
- uint32_t status;
- uint32_t i = 0;
- uint32_t unmask = 0;
-
- /* mask the parent IRQ */
- arch_interrupt_disable_mask(1 << level);
-
- /* mask all child interrupts */
- status = irq_read(ilxsd);
- irq_write(ilxmsd, status);
-
- /* handle each child */
- while (status) {
-
- /* any IRQ for this child bit ? */
- if ((status & 0x1) == 0)
- goto next;
-
- /* get child if any and run handler */
- list_for_item(clist, &parent->child[i]) {
- child = container_of(clist, struct irq_desc, irq_list);
-
- if (child && child->handler) {
- child->handler(child->handler_arg);
- unmask = 1;
- } else {
- /* nobody cared ? */
- trace_irq_error("nbc");
- }
- }
-
- /* unmask this bit i interrupt */
- if (unmask)
- irq_write(ilxmcd, 0x1 << i);
-
-next:
- status >>= 1;
- i++;
- }
-
- /* clear parent and unmask */
- arch_interrupt_clear(level);
- arch_interrupt_enable_mask(1 << level);
-}
-
-#define IRQ_LVL2_HANDLER(n) int core = cpu_get_id(); \
- irq_lvl2_handler(data, \
- IRQ_NUM_EXT_LEVEL##n, \
- REG_IRQ_IL##n##SD(core), \
- REG_IRQ_IL##n##MSD(core), \
- REG_IRQ_IL##n##MCD(core))
-
-static void irq_lvl2_level2_handler(void *data)
-{
- IRQ_LVL2_HANDLER(2);
-}
-
-static void irq_lvl2_level3_handler(void *data)
-{
- IRQ_LVL2_HANDLER(3);
-}
-
-static void irq_lvl2_level4_handler(void *data)
-{
- IRQ_LVL2_HANDLER(4);
-}
-
-static void irq_lvl2_level5_handler(void *data)
-{
- IRQ_LVL2_HANDLER(5);
-}
-
-/* DSP internal interrupts */
-static struct irq_desc dsp_irq[PLATFORM_CORE_COUNT][4] = {
- #if defined(CONFIG_CANNONLAKE)
- {{IRQ_NUM_EXT_LEVEL2, irq_lvl2_level2_handler, },
- {IRQ_NUM_EXT_LEVEL3, irq_lvl2_level3_handler, },
- {IRQ_NUM_EXT_LEVEL4, irq_lvl2_level4_handler, },
- {IRQ_NUM_EXT_LEVEL5, irq_lvl2_level5_handler, } },
-
- {{IRQ_NUM_EXT_LEVEL2, irq_lvl2_level2_handler, },
- {IRQ_NUM_EXT_LEVEL3, irq_lvl2_level3_handler, },
- {IRQ_NUM_EXT_LEVEL4, irq_lvl2_level4_handler, },
- {IRQ_NUM_EXT_LEVEL5, irq_lvl2_level5_handler, } },
- #endif
-
- {{IRQ_NUM_EXT_LEVEL2, irq_lvl2_level2_handler, },
- {IRQ_NUM_EXT_LEVEL3, irq_lvl2_level3_handler, },
- {IRQ_NUM_EXT_LEVEL4, irq_lvl2_level4_handler, },
- {IRQ_NUM_EXT_LEVEL5, irq_lvl2_level5_handler, } },
-
- {{IRQ_NUM_EXT_LEVEL2, irq_lvl2_level2_handler, },
- {IRQ_NUM_EXT_LEVEL3, irq_lvl2_level3_handler, },
- {IRQ_NUM_EXT_LEVEL4, irq_lvl2_level4_handler, },
- {IRQ_NUM_EXT_LEVEL5, irq_lvl2_level5_handler, } },
-};
-
-struct irq_desc *platform_irq_get_parent(uint32_t irq)
-{
- int core = SOF_IRQ_CPU(irq);
-
- switch (SOF_IRQ_NUMBER(irq)) {
- case IRQ_NUM_EXT_LEVEL2:
- return &dsp_irq[core][0];
- case IRQ_NUM_EXT_LEVEL3:
- return &dsp_irq[core][1];
- case IRQ_NUM_EXT_LEVEL4:
- return &dsp_irq[core][2];
- case IRQ_NUM_EXT_LEVEL5:
- return &dsp_irq[core][3];
- default:
- return NULL;
- }
-}
-
-uint32_t platform_interrupt_get_enabled(void)
-{
- return 0;
-}
-
-void platform_interrupt_mask(uint32_t irq, uint32_t mask)
-{
- int core = SOF_IRQ_CPU(irq);
-
- /* mask external interrupt bit */
- switch (SOF_IRQ_NUMBER(irq)) {
- case IRQ_NUM_EXT_LEVEL5:
- irq_write(REG_IRQ_IL5MSD(core), 1 << SOF_IRQ_BIT(irq));
- break;
- case IRQ_NUM_EXT_LEVEL4:
- irq_write(REG_IRQ_IL4MSD(core), 1 << SOF_IRQ_BIT(irq));
- break;
- case IRQ_NUM_EXT_LEVEL3:
- irq_write(REG_IRQ_IL3MSD(core), 1 << SOF_IRQ_BIT(irq));
- break;
- case IRQ_NUM_EXT_LEVEL2:
- irq_write(REG_IRQ_IL2MSD(core), 1 << SOF_IRQ_BIT(irq));
- break;
- default:
- break;
- }
-
-}
-
-void platform_interrupt_unmask(uint32_t irq, uint32_t mask)
-{
- int core = SOF_IRQ_CPU(irq);
-
- /* unmask external interrupt bit */
- switch (SOF_IRQ_NUMBER(irq)) {
- case IRQ_NUM_EXT_LEVEL5:
- irq_write(REG_IRQ_IL5MCD(core), 1 << SOF_IRQ_BIT(irq));
- break;
- case IRQ_NUM_EXT_LEVEL4:
- irq_write(REG_IRQ_IL4MCD(core), 1 << SOF_IRQ_BIT(irq));
- break;
- case IRQ_NUM_EXT_LEVEL3:
- irq_write(REG_IRQ_IL3MCD(core), 1 << SOF_IRQ_BIT(irq));
- break;
- case IRQ_NUM_EXT_LEVEL2:
- irq_write(REG_IRQ_IL2MCD(core), 1 << SOF_IRQ_BIT(irq));
- break;
- default:
- break;
- }
-
-}
-
-void platform_interrupt_clear(uint32_t irq, uint32_t mask)
-{
-}
-
-void platform_interrupt_init(void)
-{
- int i, j;
- int core = cpu_get_id();
-
- /* mask all external IRQs by default */
- irq_write(REG_IRQ_IL2MSD(core), REG_IRQ_IL2MD_ALL);
- irq_write(REG_IRQ_IL3MSD(core), REG_IRQ_IL3MD_ALL);
- irq_write(REG_IRQ_IL4MSD(core), REG_IRQ_IL4MD_ALL);
- irq_write(REG_IRQ_IL5MSD(core), REG_IRQ_IL5MD_ALL);
-
- for (i = 0; i < ARRAY_SIZE(dsp_irq[core]); i++) {
- spinlock_init(&dsp_irq[core][i].lock);
- for (j = 0; j < PLATFORM_IRQ_CHILDREN; j++)
- list_init(&dsp_irq[core][i].child[j]);
- }
-}
diff --git a/src/platform/intel/cavs/memory.c b/src/platform/intel/cavs/memory.c
deleted file mode 100644
index 21792f0..0000000
--- a/src/platform/intel/cavs/memory.c
+++ /dev/null
@@ -1,115 +0,0 @@
-/*
- * Copyright (c) 2018, Intel Corporation
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- * * Redistributions of source code must retain the above copyright
- * notice, this list of conditions and the following disclaimer.
- * * Redistributions in binary form must reproduce the above copyright
- * notice, this list of conditions and the following disclaimer in the
- * documentation and/or other materials provided with the distribution.
- * * Neither the name of the Intel Corporation nor the
- * names of its contributors may be used to endorse or promote products
- * derived from this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
- * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
- * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
- * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
- * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
- * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
- * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
- * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
- * POSSIBILITY OF SUCH DAMAGE.
- *
- * Author: Liam Girdwood <liam.r.girdwood@linux.intel.com>
- * Janusz Jankowski <janusz.jankowski@linux.intel.com>
- */
-
-#include <sof/alloc.h>
-
-/* Heap blocks for modules */
-static struct block_hdr mod_block64[HEAP_RT_COUNT64];
-static struct block_hdr mod_block128[HEAP_RT_COUNT128];
-static struct block_hdr mod_block256[HEAP_RT_COUNT256];
-static struct block_hdr mod_block512[HEAP_RT_COUNT512];
-
-/* Heap memory map for modules */
-static struct block_map rt_heap_map[] = {
- BLOCK_DEF(64, HEAP_RT_COUNT64, mod_block64),
- BLOCK_DEF(128, HEAP_RT_COUNT128, mod_block128),
- BLOCK_DEF(256, HEAP_RT_COUNT256, mod_block256),
- BLOCK_DEF(512, HEAP_RT_COUNT512, mod_block512),
-};
-
-/* Heap blocks for buffers */
-static struct block_hdr buf_block[HEAP_BUFFER_COUNT];
-static struct block_hdr hp_buf_block[HEAP_HP_BUFFER_COUNT];
-static struct block_hdr lp_buf_block[HEAP_LP_BUFFER_COUNT];
-
-/* Heap memory map for buffers */
-static struct block_map buf_heap_map[] = {
- BLOCK_DEF(HEAP_BUFFER_BLOCK_SIZE, HEAP_BUFFER_COUNT, buf_block),
-};
-
-static struct block_map hp_buf_heap_map[] = {
- BLOCK_DEF(HEAP_HP_BUFFER_BLOCK_SIZE, HEAP_HP_BUFFER_COUNT,
- hp_buf_block),
-};
-
-static struct block_map lp_buf_heap_map[] = {
- BLOCK_DEF(HEAP_LP_BUFFER_BLOCK_SIZE, HEAP_LP_BUFFER_COUNT,
- lp_buf_block),
-};
-
-struct mm memmap = {
- .system = {
- .heap = HEAP_SYSTEM_BASE,
- .size = HEAP_SYSTEM_SIZE,
- .info = {.free = HEAP_SYSTEM_SIZE,},
- .caps = SOF_MEM_CAPS_RAM | SOF_MEM_CAPS_EXT |
- SOF_MEM_CAPS_CACHE,
- },
- .runtime[0] = {
- .blocks = ARRAY_SIZE(rt_heap_map),
- .map = rt_heap_map,
- .heap = HEAP_RUNTIME_BASE,
- .size = HEAP_RUNTIME_SIZE,
- .info = {.free = HEAP_RUNTIME_SIZE,},
- .caps = SOF_MEM_CAPS_RAM | SOF_MEM_CAPS_EXT |
- SOF_MEM_CAPS_CACHE,
- },
- .buffer[0] = {
- .blocks = ARRAY_SIZE(buf_heap_map),
- .map = buf_heap_map,
- .heap = HEAP_BUFFER_BASE,
- .size = HEAP_BUFFER_SIZE,
- .info = {.free = HEAP_BUFFER_SIZE,},
- .caps = SOF_MEM_CAPS_RAM | SOF_MEM_CAPS_EXT |
- SOF_MEM_CAPS_CACHE,
- },
- .buffer[1] = {
- .blocks = ARRAY_SIZE(hp_buf_heap_map),
- .map = hp_buf_heap_map,
- .heap = HEAP_HP_BUFFER_BASE,
- .size = HEAP_HP_BUFFER_SIZE,
- .info = {.free = HEAP_HP_BUFFER_SIZE,},
- .caps = SOF_MEM_CAPS_RAM | SOF_MEM_CAPS_HP |
- SOF_MEM_CAPS_CACHE | SOF_MEM_CAPS_DMA,
- },
- .buffer[2] = {
- .blocks = ARRAY_SIZE(lp_buf_heap_map),
- .map = lp_buf_heap_map,
- .heap = HEAP_LP_BUFFER_BASE,
- .size = HEAP_LP_BUFFER_SIZE,
- .info = {.free = HEAP_LP_BUFFER_SIZE,},
- .caps = SOF_MEM_CAPS_RAM | SOF_MEM_CAPS_LP |
- SOF_MEM_CAPS_CACHE | SOF_MEM_CAPS_DMA,
- },
- .total = {.free = HEAP_SYSTEM_SIZE + HEAP_RUNTIME_SIZE +
- HEAP_BUFFER_SIZE + HEAP_HP_BUFFER_SIZE +
- HEAP_LP_BUFFER_SIZE,},
-};
diff --git a/src/platform/intel/cavs/platform.c b/src/platform/intel/cavs/platform.c
deleted file mode 100644
index f9da89d..0000000
--- a/src/platform/intel/cavs/platform.c
+++ /dev/null
@@ -1,353 +0,0 @@
-/*
- * Copyright (c) 2018, Intel Corporation
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- * * Redistributions of source code must retain the above copyright
- * notice, this list of conditions and the following disclaimer.
- * * Redistributions in binary form must reproduce the above copyright
- * notice, this list of conditions and the following disclaimer in the
- * documentation and/or other materials provided with the distribution.
- * * Neither the name of the Intel Corporation nor the
- * names of its contributors may be used to endorse or promote products
- * derived from this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
- * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
- * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
- * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
- * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
- * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
- * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
- * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
- * POSSIBILITY OF SUCH DAMAGE.
- *
- * Author: Liam Girdwood <liam.r.girdwood@linux.intel.com>
- * Keyon Jie <yang.jie@linux.intel.com>
- * Rander Wang <rander.wang@intel.com>
- * Janusz Jankowski <janusz.jankowski@linux.intel.com>
- */
-
-#include <platform/memory.h>
-#include <platform/mailbox.h>
-#include <platform/shim.h>
-#include <platform/dma.h>
-#include <platform/clk.h>
-#include <platform/timer.h>
-#include <platform/interrupt.h>
-#include <platform/idc.h>
-#include <uapi/ipc.h>
-#include <sof/mailbox.h>
-#include <sof/dai.h>
-#include <sof/dma.h>
-#include <sof/sof.h>
-#include <sof/agent.h>
-#include <sof/work.h>
-#include <sof/clock.h>
-#include <sof/ipc.h>
-#include <sof/io.h>
-#include <sof/trace.h>
-#include <sof/audio/component.h>
-#include <config.h>
-#include <string.h>
-#include <version.h>
-
-#if defined(CONFIG_APOLLOLAKE)
-#define SSP_COUNT PLATFORM_NUM_SSP
-#define SSP_CLOCK_FREQUENCY 19200000
-#elif defined(CONFIG_CANNONLAKE)
-#define SSP_COUNT PLATFORM_SSP_COUNT
-#define SSP_CLOCK_FREQUENCY 24000000
-#endif
-
-static const struct sof_ipc_fw_ready ready = {
- .hdr = {
- .cmd = SOF_IPC_FW_READY,
- .size = sizeof(struct sof_ipc_fw_ready),
- },
- .version = {
- .build = SOF_BUILD,
- .minor = SOF_MINOR,
- .major = SOF_MAJOR,
- .date = __DATE__,
- .time = __TIME__,
- .tag = SOF_TAG,
- },
-};
-
-#define SRAM_WINDOW_HOST_OFFSET(x) (0x80000 + x * 0x20000)
-
-#define NUM_WINDOWS 7
-
-static const struct sof_ipc_window sram_window = {
- .ext_hdr = {
- .hdr.cmd = SOF_IPC_FW_READY,
- .hdr.size = sizeof(struct sof_ipc_window) +
- sizeof(struct sof_ipc_window_elem) * NUM_WINDOWS,
- .type = SOF_IPC_EXT_WINDOW,
- },
- .num_windows = NUM_WINDOWS,
- .window = {
- {
- .type = SOF_IPC_REGION_REGS,
- .id = 0, /* map to host window 0 */
- .flags = 0, // TODO: set later
- .size = MAILBOX_SW_REG_SIZE,
- .offset = 0,
- },
- {
- .type = SOF_IPC_REGION_UPBOX,
- .id = 0, /* map to host window 0 */
- .flags = 0, // TODO: set later
- .size = MAILBOX_DSPBOX_SIZE,
- .offset = MAILBOX_SW_REG_SIZE,
- },
- {
- .type = SOF_IPC_REGION_DOWNBOX,
- .id = 1, /* map to host window 1 */
- .flags = 0, // TODO: set later
- .size = MAILBOX_HOSTBOX_SIZE,
- .offset = 0,
- },
- {
- .type = SOF_IPC_REGION_DEBUG,
- .id = 2, /* map to host window 2 */
- .flags = 0, // TODO: set later
- .size = MAILBOX_EXCEPTION_SIZE + MAILBOX_DEBUG_SIZE,
- .offset = 0,
- },
- {
- .type = SOF_IPC_REGION_EXCEPTION,
- .id = 2, /* map to host window 2 */
- .flags = 0, // TODO: set later
- .size = MAILBOX_EXCEPTION_SIZE,
- .offset = MAILBOX_EXCEPTION_OFFSET,
- },
- {
- .type = SOF_IPC_REGION_STREAM,
- .id = 2, /* map to host window 2 */
- .flags = 0, // TODO: set later
- .size = MAILBOX_STREAM_SIZE,
- .offset = MAILBOX_STREAM_OFFSET,
- },
- {
- .type = SOF_IPC_REGION_TRACE,
- .id = 3, /* map to host window 3 */
- .flags = 0, // TODO: set later
- .size = MAILBOX_TRACE_SIZE,
- .offset = 0,
- },
- },
-};
-
-static struct work_queue_timesource platform_generic_queue = {
- .timer = {
- .id = TIMER3, /* external timer */
- .irq = IRQ_EXT_TSTAMP0_LVL2(0),
- },
- .clk = CLK_SSP,
- .notifier = NOTIFIER_ID_SSP_FREQ,
- .timer_set = platform_timer_set,
- .timer_clear = platform_timer_clear,
- .timer_get = platform_timer_get,
-};
-
-struct timer *platform_timer = &platform_generic_queue.timer;
-
-int platform_boot_complete(uint32_t boot_message)
-{
- mailbox_dspbox_write(0, &ready, sizeof(ready));
- mailbox_dspbox_write(sizeof(ready), &sram_window,
- sram_window.ext_hdr.hdr.size);
-
- #if defined(CONFIG_APOLLOLAKE)
- /* boot now complete so we can relax the CPU */
- clock_set_freq(CLK_CPU, CLK_DEFAULT_CPU_HZ);
-
- /* tell host we are ready */
- ipc_write(IPC_DIPCIE, SRAM_WINDOW_HOST_OFFSET(0) >> 12);
- ipc_write(IPC_DIPCI, 0x80000000 | SOF_IPC_FW_READY);
- #elif defined(CONFIG_CANNONLAKE)
- /* tell host we are ready */
- ipc_write(IPC_DIPCIDD, SRAM_WINDOW_HOST_OFFSET(0) >> 12);
- ipc_write(IPC_DIPCIDR, 0x80000000 | SOF_IPC_FW_READY);
- #endif
-
- return 0;
-}
-
-static void platform_memory_windows_init(void)
-{
- /* window0, for fw status & outbox/uplink mbox */
- io_reg_write(DMWLO(0), HP_SRAM_WIN0_SIZE | 0x7);
- io_reg_write(DMWBA(0), HP_SRAM_WIN0_BASE
- | DMWBA_READONLY | DMWBA_ENABLE);
- bzero((void *)(HP_SRAM_WIN0_BASE + SRAM_REG_FW_END),
- HP_SRAM_WIN0_SIZE - SRAM_REG_FW_END);
- dcache_writeback_region((void *)(HP_SRAM_WIN0_BASE + SRAM_REG_FW_END),
- HP_SRAM_WIN0_SIZE - SRAM_REG_FW_END);
-
- /* window1, for inbox/downlink mbox */
- io_reg_write(DMWLO(1), HP_SRAM_WIN1_SIZE | 0x7);
- io_reg_write(DMWBA(1), HP_SRAM_WIN1_BASE
- | DMWBA_ENABLE);
- bzero((void *)HP_SRAM_WIN1_BASE, HP_SRAM_WIN1_SIZE);
- dcache_writeback_region((void *)HP_SRAM_WIN1_BASE, HP_SRAM_WIN1_SIZE);
-
- /* window2, for debug */
- io_reg_write(DMWLO(2), HP_SRAM_WIN2_SIZE | 0x7);
- io_reg_write(DMWBA(2), HP_SRAM_WIN2_BASE
- | DMWBA_READONLY | DMWBA_ENABLE);
- bzero((void *)HP_SRAM_WIN2_BASE, HP_SRAM_WIN2_SIZE);
- dcache_writeback_region((void *)HP_SRAM_WIN2_BASE, HP_SRAM_WIN2_SIZE);
-
- /* window3, for trace */
- io_reg_write(DMWLO(3), HP_SRAM_WIN3_SIZE | 0x7);
- io_reg_write(DMWBA(3), HP_SRAM_WIN3_BASE
- | DMWBA_READONLY | DMWBA_ENABLE);
- bzero((void *)HP_SRAM_WIN3_BASE, HP_SRAM_WIN3_SIZE);
- dcache_writeback_region((void *)HP_SRAM_WIN3_BASE, HP_SRAM_WIN3_SIZE);
-}
-
-#if defined(CONFIG_CANNONLAKE)
-/* init HW */
-static void platform_init_hw(void)
-{
- io_reg_write(DSP_INIT_GENO,
- GENO_MDIVOSEL | GENO_DIOPTOSEL);
-
- io_reg_write(DSP_INIT_IOPO,
- IOPO_DMIC_FLAG | IOPO_I2S_FLAG);
-
- io_reg_write(DSP_INIT_ALHO,
- ALHO_ASO_FLAG | ALHO_CSO_FLAG | ALHO_CFO_FLAG);
-
- io_reg_write(DSP_INIT_LPGPDMA(0),
- LPGPDMA_CHOSEL_FLAG | LPGPDMA_CTLOSEL_FLAG);
- io_reg_write(DSP_INIT_LPGPDMA(1),
- LPGPDMA_CHOSEL_FLAG | LPGPDMA_CTLOSEL_FLAG);
-}
-
-static struct timer platform_ext_timer = {
- .id = TIMER3,
- .irq = IRQ_EXT_TSTAMP0_LVL2(0),
-};
-#endif
-
-int platform_init(struct sof *sof)
-{
- struct dai *ssp;
- struct dai *dmic0;
- int i, ret;
-
- #if defined(CONFIG_CANNONLAKE)
- trace_point(TRACE_BOOT_PLATFORM_ENTRY);
- platform_init_hw();
- #endif
-
- platform_interrupt_init();
-
- trace_point(TRACE_BOOT_PLATFORM_MBOX);
- platform_memory_windows_init();
-
- trace_point(TRACE_BOOT_PLATFORM_SHIM);
-
- /* init work queues and clocks */
- trace_point(TRACE_BOOT_PLATFORM_TIMER);
- #if defined(CONFIG_APOLLOLAKE)
- platform_timer_start(&platform_generic_queue.timer);
- #elif defined(CONFIG_CANNONLAKE)
- platform_timer_start(&platform_ext_timer);
- #endif
-
- trace_point(TRACE_BOOT_PLATFORM_CLOCK);
- init_platform_clocks();
-
- trace_point(TRACE_BOOT_SYS_WORK);
- init_system_workq(&platform_generic_queue);
-
- /* init the system agent */
- sa_init(sof);
-
- /* Set CPU to default frequency for booting */
- trace_point(TRACE_BOOT_SYS_CPU_FREQ);
- clock_set_freq(CLK_CPU, CLK_MAX_CPU_HZ);
-
- /* set SSP clock */
- trace_point(TRACE_BOOT_PLATFORM_SSP_FREQ);
- clock_set_freq(CLK_SSP, SSP_CLOCK_FREQUENCY);
-
- /* initialise the host IPC mechanisms */
- trace_point(TRACE_BOOT_PLATFORM_IPC);
- ipc_init(sof);
-
- #if defined(CONFIG_APOLLOLAKE)
- /* disable PM for boot */
- shim_write(SHIM_CLKCTL, shim_read(SHIM_CLKCTL) |
- SHIM_CLKCTL_LPGPDMAFDCGB(0) |
- SHIM_CLKCTL_LPGPDMAFDCGB(1) |
- SHIM_CLKCTL_I2SFDCGB(3) |
- SHIM_CLKCTL_I2SFDCGB(2) |
- SHIM_CLKCTL_I2SFDCGB(1) |
- SHIM_CLKCTL_I2SFDCGB(0) |
- SHIM_CLKCTL_DMICFDCGB |
- SHIM_CLKCTL_I2SEFDCGB(1) |
- SHIM_CLKCTL_I2SEFDCGB(0) |
- SHIM_CLKCTL_TCPAPLLS |
- SHIM_CLKCTL_RAPLLC |
- SHIM_CLKCTL_RXOSCC |
- SHIM_CLKCTL_RFROSCC |
- SHIM_CLKCTL_TCPLCG(0) | SHIM_CLKCTL_TCPLCG(1));
-
- shim_write(SHIM_LPSCTL, shim_read(SHIM_LPSCTL));
- #elif defined(CONFIG_CANNONLAKE)
- /* prevent Core0 clock gating. */
- shim_write(SHIM_CLKCTL, shim_read(SHIM_CLKCTL) |
- SHIM_CLKCTL_TCPLCG(0));
-
- /* prevent LP GPDMA 0&1 clock gating */
- io_reg_write(GPDMA_CLKCTL(0), GPDMA_FDCGB);
- io_reg_write(GPDMA_CLKCTL(1), GPDMA_FDCGB);
-
- /* prevent DSP Common power gating */
- shim_write16(SHIM_PWRCTL, SHIM_PWRCTL_TCPDSP0PG);
- #endif
-
- /* init DMACs */
- trace_point(TRACE_BOOT_PLATFORM_DMA);
- ret = dmac_init();
- if (ret < 0)
- return -ENODEV;
-
-
- /* init SSP ports */
- trace_point(TRACE_BOOT_PLATFORM_SSP);
- for (i = 0; i < SSP_COUNT; i++) {
- ssp = dai_get(SOF_DAI_INTEL_SSP, i);
- if (ssp == NULL)
- return -ENODEV;
- dai_probe(ssp);
- }
-
- /* Init DMIC. Note that the two PDM controllers and four microphones
- * supported max. those are available in platform are handled by dmic0.
- */
- trace_point(TRACE_BOOT_PLATFORM_DMIC);
- dmic0 = dai_get(SOF_DAI_INTEL_DMIC, 0);
- if (!dmic0)
- return -ENODEV;
-
- dai_probe(dmic0);
-
- /* initialize IDC mechanism */
- trace_point(TRACE_BOOT_PLATFORM_IDC);
- idc_init();
-
- /* Initialize DMA for Trace*/
- dma_trace_init_complete(sof->dmat);
-
- return 0;
-}
diff --git a/src/platform/intel/cavs/pm_runtime.c b/src/platform/intel/cavs/pm_runtime.c
deleted file mode 100644
index fd3bd88..0000000
--- a/src/platform/intel/cavs/pm_runtime.c
+++ /dev/null
@@ -1,86 +0,0 @@
-/*
- * Copyright (c) 2018, Intel Corporation
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- * * Redistributions of source code must retain the above copyright
- * notice, this list of conditions and the following disclaimer.
- * * Redistributions in binary form must reproduce the above copyright
- * notice, this list of conditions and the following disclaimer in the
- * documentation and/or other materials provided with the distribution.
- * * Neither the name of the Intel Corporation nor the
- * names of its contributors may be used to endorse or promote products
- * derived from this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
- * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
- * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
- * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
- * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
- * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
- * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
- * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
- * POSSIBILITY OF SUCH DAMAGE.
- *
- * Author: Tomasz Lauda <tomasz.lauda@linux.intel.com>
- */
-
-/**
- * \file platform/intel/cavs/pm_runtime.c
- * \brief Runtime power management implementation for Apollolake & Cannonlake
- * \author Tomasz Lauda <tomasz.lauda@linux.intel.com>
- */
-
-#include <sof/alloc.h>
-#include <platform/platform.h>
-#include <platform/pm_runtime.h>
-#include <platform/cavs/pm_runtime.h>
-
-#if defined(CONFIG_APOLLOLAKE)
-//TODO: add support or at least stub api for Cannonlake
-#include <platform/power_down.h>
-#endif
-
-/** \brief Runtime power management data pointer. */
-struct pm_runtime_data *_prd;
-
-void platform_pm_runtime_init(struct pm_runtime_data *prd)
-{
- struct platform_pm_runtime_data *pprd;
-
- _prd = prd;
-
- pprd = rzalloc(RZONE_SYS, SOF_MEM_CAPS_RAM, sizeof(*pprd));
- _prd->platform_data = pprd;
-}
-
-void platform_pm_runtime_get(enum pm_runtime_context context)
-{
- /* Action based on context */
-}
-
-void platform_pm_runtime_put(enum pm_runtime_context context)
-{
- switch (context) {
- case PM_RUNTIME_HOST_DMA_L1:
- cavs_pm_runtime_force_host_dma_l1_exit();
- break;
- }
-}
-
-#if defined(CONFIG_APOLLOLAKE)
-void platform_pm_runtime_power_off(void)
-{
- uint32_t hpsram_mask[PLATFORM_HPSRAM_SEGMENTS];
- //TODO: add LDO control for LP SRAM - set LDO BYPASS & LDO ON
- //TODO: mask to be used in the future for run-time power management of
- //SRAM banks
- /* power down entire HPSRAM */
- hpsram_mask[0] = 0x1;
-
- power_down(true, hpsram_mask);
-}
-#endif
diff --git a/src/platform/intel/cavs/timer.c b/src/platform/intel/cavs/timer.c
deleted file mode 100644
index de745c4..0000000
--- a/src/platform/intel/cavs/timer.c
+++ /dev/null
@@ -1,135 +0,0 @@
-/*
- * Copyright (c) 2018, Intel Corporation
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- * * Redistributions of source code must retain the above copyright
- * notice, this list of conditions and the following disclaimer.
- * * Redistributions in binary form must reproduce the above copyright
- * notice, this list of conditions and the following disclaimer in the
- * documentation and/or other materials provided with the distribution.
- * * Neither the name of the Intel Corporation nor the
- * names of its contributors may be used to endorse or promote products
- * derived from this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
- * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
- * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
- * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
- * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
- * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
- * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
- * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
- * POSSIBILITY OF SUCH DAMAGE.
- *
- * Author: Liam Girdwood <liam.r.girdwood@linux.intel.com>
- * Keyon Jie <yang.jie@linux.intel.com>
- * Rander Wang <rander.wang@intel.com>
- * Janusz Jankowski <janusz.jankowski@linux.intel.com>
- */
-
-#include <platform/timer.h>
-#include <platform/shim.h>
-#include <sof/debug.h>
-#include <sof/audio/component.h>
-#include <stdint.h>
-
-void platform_timer_start(struct timer *timer)
-{
- /* run timer */
- shim_write64(SHIM_DSPWCT0C, 0);
- shim_write(SHIM_DSPWCTCS,
- shim_read(SHIM_DSPWCTCS) | SHIM_DSPWCTCS_T0A);
-}
-
-void platform_timer_stop(struct timer *timer)
-{
- /* stop timer */
- shim_write64(SHIM_DSPWCT0C, 0);
- shim_write(SHIM_DSPWCTCS,
- shim_read(SHIM_DSPWCTCS) & ~SHIM_DSPWCTCS_T0A);
-}
-
-int platform_timer_set(struct timer *timer, uint64_t ticks)
-{
- /* a tick value of 0 will not generate an IRQ */
- if (ticks == 0)
- ticks = 1;
-
- /* set new value and run */
- shim_write64(SHIM_DSPWCT0C, ticks);
- shim_write(SHIM_DSPWCTCS,
- shim_read(SHIM_DSPWCTCS) | SHIM_DSPWCTCS_T0A);
-
- return 0;
-}
-
-void platform_timer_clear(struct timer *timer)
-{
- /* write 1 to clear the timer interrupt */
- shim_write(SHIM_DSPWCTCS,
- shim_read(SHIM_DSPWCTCS) | SHIM_DSPWCTCS_T0T);
-}
-
-uint64_t platform_timer_get(struct timer *timer)
-{
-// return arch_timer_get_system(timer);
- return (uint64_t)shim_read64(SHIM_DSPWC);
-}
-
-/* get timestamp for host stream DMA position */
-void platform_host_timestamp(struct comp_dev *host,
- struct sof_ipc_stream_posn *posn)
-{
- int err;
-
- /* get host postion */
- err = comp_position(host, posn);
- if (err == 0)
- posn->flags |= SOF_TIME_HOST_VALID;
-}
-
-/* get timestamp for DAI stream DMA position */
-void platform_dai_timestamp(struct comp_dev *dai,
- struct sof_ipc_stream_posn *posn)
-{
- int err;
-
- /* get DAI postion */
- err = comp_position(dai, posn);
- if (err == 0)
- posn->flags |= SOF_TIME_DAI_VALID;
-
- /* get SSP wallclock - DAI sets this to stream start value */
- posn->wallclock = shim_read64(SHIM_DSPWC) - posn->wallclock;
- posn->flags |= SOF_TIME_WALL_VALID;
-}
-
-/* get current wallclock for componnent */
-void platform_dai_wallclock(struct comp_dev *dai, uint64_t *wallclock)
-{
- *wallclock = shim_read64(SHIM_DSPWC);
-}
-
-int platform_timer_register(struct timer *timer,
- void (*handler)(void *arg), void *arg)
-{
- return interrupt_register(timer->irq, handler, arg);
-}
-
-int timer_register(struct timer *timer, void(*handler)(void *arg), void *arg)
-{
- switch (timer->id) {
- case TIMER0:
- case TIMER1:
- case TIMER2:
- return arch_timer_register(timer, handler, arg);
- case TIMER3:
- return platform_timer_register(timer, handler, arg);
- default:
- return -EINVAL;
- }
-}
diff --git a/src/platform/intel/include/Makefile.am b/src/platform/intel/include/Makefile.am
deleted file mode 100644
index 912728c..0000000
--- a/src/platform/intel/include/Makefile.am
+++ /dev/null
@@ -1 +0,0 @@
-SUBDIRS = platform
diff --git a/src/platform/intel/include/platform/Makefile.am b/src/platform/intel/include/platform/Makefile.am
deleted file mode 100644
index 13161e0..0000000
--- a/src/platform/intel/include/platform/Makefile.am
+++ /dev/null
@@ -1,3 +0,0 @@
-if BUILD_CAVS
-SUBDIRS = cavs
-endif
diff --git a/src/platform/intel/include/platform/cavs/Makefile.am b/src/platform/intel/include/platform/cavs/Makefile.am
deleted file mode 100644
index 712c197..0000000
--- a/src/platform/intel/include/platform/cavs/Makefile.am
+++ /dev/null
@@ -1,2 +0,0 @@
-noinst_HEADERS = \
- pm_runtime.h
diff --git a/src/platform/intel/include/platform/cavs/pm_runtime.h b/src/platform/intel/include/platform/cavs/pm_runtime.h
deleted file mode 100644
index e6b483d..0000000
--- a/src/platform/intel/include/platform/cavs/pm_runtime.h
+++ /dev/null
@@ -1,65 +0,0 @@
-/*
- * Copyright (c) 2018, Intel Corporation
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- * * Redistributions of source code must retain the above copyright
- * notice, this list of conditions and the following disclaimer.
- * * Redistributions in binary form must reproduce the above copyright
- * notice, this list of conditions and the following disclaimer in the
- * documentation and/or other materials provided with the distribution.
- * * Neither the name of the Intel Corporation nor the
- * names of its contributors may be used to endorse or promote products
- * derived from this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
- * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
- * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
- * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
- * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
- * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
- * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
- * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
- * POSSIBILITY OF SUCH DAMAGE.
- *
- * Author: Tomasz Lauda <tomasz.lauda@linux.intel.com>
- */
-
-/**
- * \file platform/intel/platform/cavs/include/pm_runtime.h
- * \brief Runtime power management header file for cAVS
- * \author Tomasz Lauda <tomasz.lauda@linux.intel.com>
- */
-
-#ifndef __INCLUDE_CAVS_PM_RUNTIME__
-#define __INCLUDE_CAVS_PM_RUNTIME__
-
-#include <platform/pm_runtime.h>
-
-extern struct pm_runtime_data *_prd;
-
-/**
- * \brief Forces Host DMAs to exit L1.
- */
-static inline void cavs_pm_runtime_force_host_dma_l1_exit(void)
-{
- uint32_t flags;
-
- spin_lock_irq(&_prd->lock, flags);
-
- if (!(shim_read(SHIM_SVCFG) & SHIM_SVCFG_FORCE_L1_EXIT)) {
- shim_write(SHIM_SVCFG,
- shim_read(SHIM_SVCFG) | SHIM_SVCFG_FORCE_L1_EXIT);
-
- wait_delay(PLATFORM_FORCE_L1_EXIT_TIME);
-
- shim_write(SHIM_SVCFG,
- shim_read(SHIM_SVCFG) & ~(SHIM_SVCFG_FORCE_L1_EXIT));
- }
-
- spin_unlock_irq(&_prd->lock, flags);
-}
-#endif /* __INCLUDE_CAVS_PM_RUNTIME__ */
diff --git a/src/tasks/Makefile.am b/src/tasks/Makefile.am
deleted file mode 100644
index 0bb53b9..0000000
--- a/src/tasks/Makefile.am
+++ /dev/null
@@ -1,11 +0,0 @@
-noinst_LIBRARIES = libtasks.a
-
-libtasks_a_SOURCES = \
- audio.c
-
-libtasks_a_CFLAGS = \
- $(AM_CFLAGS) \
- $(ARCH_CFLAGS) \
- $(ARCH_INCDIR) \
- $(PLATFORM_INCDIR) \
- $(SOF_INCDIR)
diff --git a/src/tasks/audio.c b/src/tasks/audio.c
deleted file mode 100644
index b872793..0000000
--- a/src/tasks/audio.c
+++ /dev/null
@@ -1,115 +0,0 @@
-/*
- * Copyright (c) 2016, Intel Corporation
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- * * Redistributions of source code must retain the above copyright
- * notice, this list of conditions and the following disclaimer.
- * * Redistributions in binary form must reproduce the above copyright
- * notice, this list of conditions and the following disclaimer in the
- * documentation and/or other materials provided with the distribution.
- * * Neither the name of the Intel Corporation nor the
- * names of its contributors may be used to endorse or promote products
- * derived from this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
- * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
- * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
- * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
- * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
- * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
- * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
- * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
- * POSSIBILITY OF SUCH DAMAGE.
- *
- * Author: Liam Girdwood <liam.r.girdwood@linux.intel.com>
- *
- * Generic audio task.
- */
-
-#include <sof/task.h>
-#include <sof/wait.h>
-#include <sof/debug.h>
-#include <sof/timer.h>
-#include <sof/interrupt.h>
-#include <sof/ipc.h>
-#include <sof/agent.h>
-#include <platform/idc.h>
-#include <platform/interrupt.h>
-#include <platform/shim.h>
-#include <sof/audio/pipeline.h>
-#include <sof/work.h>
-#include <sof/debug.h>
-#include <sof/trace.h>
-#include <stdint.h>
-#include <stdlib.h>
-#include <errno.h>
-
-struct audio_data {
- struct pipeline *p;
-};
-
-int do_task_master_core(struct sof *sof)
-{
-#ifdef STATIC_PIPE
- struct audio_data pdata;
-#endif
- /* init default audio components */
- sys_comp_init();
- sys_comp_dai_init();
- sys_comp_host_init();
- sys_comp_mixer_init();
- sys_comp_mux_init();
- sys_comp_switch_init();
- sys_comp_volume_init();
- sys_comp_src_init();
- sys_comp_tone_init();
- sys_comp_eq_iir_init();
- sys_comp_eq_fir_init();
-
-#if STATIC_PIPE
- /* init static pipeline */
- pdata.p = init_static_pipeline();
- if (pdata.p == NULL)
- panic(SOF_IPC_PANIC_TASK);
-#endif
- /* let host know DSP boot is complete */
- platform_boot_complete(0);
-
- /* main audio IPC processing loop */
- while (1) {
- /* sleep until next IPC or DMA */
- sa_enter_idle(sof);
- wait_for_interrupt(0);
-
- /* now process any IPC messages from host */
- ipc_process_msg_queue();
-
- /* schedule any idle tasks */
- schedule();
- }
-
- /* something bad happened */
- return -EIO;
-}
-
-int do_task_slave_core(struct sof *sof)
-{
- /* main audio IDC processing loop */
- while (1) {
- /* sleep until next IDC */
- wait_for_interrupt(0);
-
- /* now process any IDC messages from master core */
- idc_process_msg_queue();
-
- /* schedule any idle tasks */
- schedule();
- }
-
- /* something bad happened */
- return -EIO;
-}
diff --git a/test/Makefile.am b/test/Makefile.am
deleted file mode 100644
index 9c9bda0..0000000
--- a/test/Makefile.am
+++ /dev/null
@@ -1 +0,0 @@
-SUBDIRS = cmocka
diff --git a/test/cmocka/Makefile.am b/test/cmocka/Makefile.am
deleted file mode 100644
index 7ec924f..0000000
--- a/test/cmocka/Makefile.am
+++ /dev/null
@@ -1,166 +0,0 @@
-check_PROGRAMS =
-
-LOG_DRIVER = env AM_TAP_AWK='$(AWK)' $(SHELL) $(top_srcdir)/tap-driver.sh
-
-if BUILD_XTENSA
-LOG_COMPILER = xt-run
-endif
-
-# cmocka needs stdlib
-override LDFLAGS := $(filter-out -nostdlib,$(LDFLAGS))
-
-override AM_CFLAGS := \
- $(filter-out -nostdlib,$(AM_CFLAGS)) \
- $(SOF_INCDIR)
-
-override AM_LDFLAGS := \
- $(filter-out -nostdlib,$(AM_LDFLAGS))
-
-if HAVE_CMOCKA_PREFIX
-AM_CFLAGS += -I$(CMOCKA_PREFIX)/include
-AM_LDFLAGS += -L$(CMOCKA_PREFIX)/lib
-endif
-
-if BUILD_XTENSA
-AM_CFLAGS += -I../../src/arch/xtensa/include
-AM_CFLAGS += $(ARCH_INCDIR)
-AM_CFLAGS += $(PLATFORM_INCDIR)
-AM_CFLAGS += -I../../src/audio
-endif
-
-if BUILD_HOST
-AM_CFLAGS += -I../../src/arch/host/include
-endif
-
-LDADD = -lcmocka
-
-# mixer tests
-check_PROGRAMS += mixer
-mixer_SOURCES = src/audio/mixer/mixer_test.c \
- src/audio/mixer/mock.c \
- src/audio/mixer/comp_mock.c \
- ../../src/audio/buffer.c \
- ../../src/audio/mixer.c
-mixer_LDADD = -lm $(LDADD)
-
-# memory allocator test
-
-# TODO: fix
-#if BUILD_XTENSA
-#check_PROGRAMS += alloc
-#alloc_SOURCES = src/lib/alloc/alloc.c src/lib/alloc/mock.c ../../src/lib/alloc.c ../../src/platform/intel/cavs/memory.c
-#endif
-
-# pipeline tests
-
-if BUILD_XTENSA
-
-if BUILD_XTENSA_SMP
-pipeline_cpu_c = ../../src/arch/xtensa/smp/cpu.c
-else
-pipeline_cpu_c = ../../src/arch/xtensa/up/cpu.c
-endif
-
-check_PROGRAMS += pipeline_new
-pipeline_new_SOURCES = $(pipeline_cpu_c) ../../src/audio/pipeline.c src/audio/pipeline/pipeline_new.c src/audio/pipeline/pipeline_mocks.c src/audio/pipeline/pipeline_mocks_rzalloc.c
-
-check_PROGRAMS += pipeline_new_allocation
-pipeline_new_allocation_SOURCES = $(pipeline_cpu_c) ../../src/audio/pipeline.c src/audio/pipeline/pipeline_new_allocation.c src/audio/pipeline/pipeline_mocks.c src/audio/pipeline/pipeline_new_allocation_mocks.c
-
-endif
-
-# lib/lib tests
-
-check_PROGRAMS += rstrcmp
-rstrcmp_SOURCES = src/lib/lib/rstrcmp.c
-rstrcmp_LDADD = ../../src/lib/libcore.a $(LDADD)
-
-check_PROGRAMS += bzero
-bzero_SOURCES = src/lib/lib/bzero.c
-bzero_LDADD = ../../src/lib/libcore.a $(LDADD)
-
-# volume tests
-
-check_PROGRAMS += volume_process
-volume_process_SOURCES = src/audio/volume/volume_process.c
-volume_process_LDADD = ../../src/audio/libaudio.a $(LDADD)
-
-# buffer tests
-
-check_PROGRAMS += buffer_new
-buffer_new_SOURCES = src/audio/buffer/buffer_new.c src/audio/buffer/mock.c
-buffer_new_LDADD = ../../src/audio/libaudio.a $(LDADD)
-
-check_PROGRAMS += buffer_write
-buffer_write_SOURCES = src/audio/buffer/buffer_write.c src/audio/buffer/mock.c
-buffer_write_LDADD = ../../src/audio/libaudio.a $(LDADD)
-
-check_PROGRAMS += buffer_wrap
-buffer_wrap_SOURCES = src/audio/buffer/buffer_wrap.c src/audio/buffer/mock.c
-buffer_wrap_LDADD = ../../src/audio/libaudio.a $(LDADD)
-
-check_PROGRAMS += buffer_copy
-buffer_copy_SOURCES = src/audio/buffer/buffer_copy.c src/audio/buffer/mock.c
-buffer_copy_LDADD = ../../src/audio/libaudio.a $(LDADD)
-
-# component tests
-
-check_PROGRAMS += comp_set_state
-comp_set_state_SOURCES = src/audio/component/comp_set_state.c src/audio/component/mock.c
-comp_set_state_LDADD = ../../src/audio/libaudio.a $(LDADD)
-
-# list tests
-
-check_PROGRAMS += list_init
-list_init_SOURCES = src/list/list_init.c
-
-check_PROGRAMS += list_is_empty
-list_is_empty_SOURCES = src/list/list_is_empty.c
-
-check_PROGRAMS += list_item_append
-list_item_append_SOURCES = src/list/list_item_append.c
-
-check_PROGRAMS += list_item_del
-list_item_del_SOURCES = src/list/list_item_del.c
-
-check_PROGRAMS += list_item_is_last
-list_item_is_last_SOURCES = src/list/list_item_is_last.c
-
-check_PROGRAMS += list_item_prepend
-list_item_prepend_SOURCES = src/list/list_item_prepend.c
-
-check_PROGRAMS += list_item
-list_item_SOURCES = src/list/list_item.c
-
-# math/numbers tests
-
-check_PROGRAMS += gcd
-gcd_SOURCES = src/math/numbers/gcd.c
-gcd_LDADD = ../../src/math/libsof_math.a $(LDADD)
-
-check_PROGRAMS += ceil_divide
-ceil_divide_SOURCES = src/math/numbers/ceil_divide.c
-ceil_divide_LDADD = ../../src/math/libsof_math.a -lm $(LDADD)
-
-check_PROGRAMS += find_equal_int16
-find_equal_int16_SOURCES = src/math/numbers/find_equal_int16.c
-find_equal_int16_LDADD = ../../src/math/libsof_math.a $(LDADD)
-
-check_PROGRAMS += find_min_int16
-find_min_int16_SOURCES = src/math/numbers/find_min_int16.c
-find_min_int16_LDADD = ../../src/math/libsof_math.a $(LDADD)
-
-check_PROGRAMS += find_max_abs_int32
-find_max_abs_int32_SOURCES = src/math/numbers/find_max_abs_int32.c
-find_max_abs_int32_LDADD = ../../src/math/libsof_math.a $(LDADD)
-
-check_PROGRAMS += norm_int32
-norm_int32_SOURCES = src/math/numbers/norm_int32.c
-norm_int32_LDADD = ../../src/math/libsof_math.a $(LDADD)
-
-check_PROGRAMS += sin_fixed
-sin_fixed_SOURCES = src/math/trig/sin_fixed.c
-sin_fixed_LDADD = ../../src/math/libsof_math.a $(LDADD)
-
-# all our binaries are test cases
-TESTS = $(check_PROGRAMS)
diff --git a/test/cmocka/src/audio/buffer/buffer_copy.c b/test/cmocka/src/audio/buffer/buffer_copy.c
deleted file mode 100644
index 6a9dea3..0000000
--- a/test/cmocka/src/audio/buffer/buffer_copy.c
+++ /dev/null
@@ -1,174 +0,0 @@
-/*
- * Copyright (c) 2018, Intel Corporation
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- * * Redistributions of source code must retain the above copyright
- * notice, this list of conditions and the following disclaimer.
- * * Redistributions in binary form must reproduce the above copyright
- * notice, this list of conditions and the following disclaimer in the
- * documentation and/or other materials provided with the distribution.
- * * Neither the name of the Intel Corporation nor the
- * names of its contributors may be used to endorse or promote products
- * derived from this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
- * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
- * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
- * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
- * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
- * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
- * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
- * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
- * POSSIBILITY OF SUCH DAMAGE.
- *
- * Author: Slawomir Blauciak <slawomir.blauciak@linux.intel.com>
- */
-
-#include <sof/audio/component.h>
-#include <sof/audio/buffer.h>
-#include <sof/ipc.h>
-
-#include <stdio.h>
-#include <stdarg.h>
-#include <stddef.h>
-#include <setjmp.h>
-#include <math.h>
-#include <cmocka.h>
-
-static void test_audio_buffer_copy_underrun(void **state)
-{
- (void)state;
-
- struct sof_ipc_buffer test_buf_desc = {
- .size = 256
- };
-
- struct comp_buffer *src = buffer_new(&test_buf_desc);
- struct comp_buffer *snk = buffer_new(&test_buf_desc);
-
- assert_non_null(src);
- assert_non_null(snk);
-
- comp_update_buffer_produce(src, 10);
-
- assert_int_equal(src->avail, 10);
- assert_int_equal(comp_buffer_can_copy_bytes(src, snk, 16), -1);
-
- buffer_free(src);
- buffer_free(snk);
-}
-
-static void test_audio_buffer_copy_overrun(void **state)
-{
- (void)state;
-
- struct sof_ipc_buffer test_buf_desc = {
- .size = 256
- };
-
- struct comp_buffer *src = buffer_new(&test_buf_desc);
- struct comp_buffer *snk = buffer_new(&test_buf_desc);
-
- assert_non_null(src);
- assert_non_null(snk);
-
- comp_update_buffer_produce(src, 16);
- comp_update_buffer_produce(snk, 246);
-
- assert_int_equal(src->avail, 16);
- assert_int_equal(snk->free, 10);
- assert_int_equal(comp_buffer_can_copy_bytes(src, snk, 16), 1);
-
- buffer_free(src);
- buffer_free(snk);
-}
-
-static void test_audio_buffer_copy_success(void **state)
-{
- (void)state;
-
- struct sof_ipc_buffer test_buf_desc = {
- .size = 256
- };
-
- struct comp_buffer *src = buffer_new(&test_buf_desc);
- struct comp_buffer *snk = buffer_new(&test_buf_desc);
-
- assert_non_null(src);
- assert_non_null(snk);
-
- comp_update_buffer_produce(src, 10);
-
- assert_int_equal(src->avail, 10);
- assert_int_equal(comp_buffer_can_copy_bytes(src, snk, 0), 0);
-
- buffer_free(src);
- buffer_free(snk);
-}
-
-static void test_audio_buffer_copy_fit_space_constraint(void **state)
-{
- (void)state;
-
- struct sof_ipc_buffer test_buf_desc = {
- .size = 256
- };
-
- struct comp_buffer *src = buffer_new(&test_buf_desc);
- struct comp_buffer *snk = buffer_new(&test_buf_desc);
-
- assert_non_null(src);
- assert_non_null(snk);
-
- comp_update_buffer_produce(src, 16);
- comp_update_buffer_produce(snk, 246);
-
- assert_int_equal(src->avail, 16);
- assert_int_equal(snk->free, 10);
- assert_int_equal(comp_buffer_get_copy_bytes(src, snk), 10);
-
- buffer_free(src);
- buffer_free(snk);
-}
-
-static void test_audio_buffer_copy_fit_no_space_constraint(void **state)
-{
- (void)state;
-
- struct sof_ipc_buffer test_buf_desc = {
- .size = 256
- };
-
- struct comp_buffer *src = buffer_new(&test_buf_desc);
- struct comp_buffer *snk = buffer_new(&test_buf_desc);
-
- assert_non_null(src);
- assert_non_null(snk);
-
- comp_update_buffer_produce(src, 16);
-
- assert_int_equal(src->avail, 16);
- assert_int_equal(comp_buffer_get_copy_bytes(src, snk), 16);
-
- buffer_free(src);
- buffer_free(snk);
-}
-
-int main(void)
-{
- const struct CMUnitTest tests[] = {
- cmocka_unit_test(test_audio_buffer_copy_underrun),
- cmocka_unit_test(test_audio_buffer_copy_overrun),
- cmocka_unit_test(test_audio_buffer_copy_success),
- cmocka_unit_test(test_audio_buffer_copy_fit_space_constraint),
- cmocka_unit_test(test_audio_buffer_copy_fit_no_space_constraint)
- };
-
- cmocka_set_message_output(CM_OUTPUT_TAP);
-
- return cmocka_run_group_tests(tests, NULL, NULL);
-}
diff --git a/test/cmocka/src/audio/buffer/buffer_new.c b/test/cmocka/src/audio/buffer/buffer_new.c
deleted file mode 100644
index 4c5cb5b..0000000
--- a/test/cmocka/src/audio/buffer/buffer_new.c
+++ /dev/null
@@ -1,69 +0,0 @@
-/*
- * Copyright (c) 2018, Intel Corporation
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- * * Redistributions of source code must retain the above copyright
- * notice, this list of conditions and the following disclaimer.
- * * Redistributions in binary form must reproduce the above copyright
- * notice, this list of conditions and the following disclaimer in the
- * documentation and/or other materials provided with the distribution.
- * * Neither the name of the Intel Corporation nor the
- * names of its contributors may be used to endorse or promote products
- * derived from this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
- * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
- * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
- * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
- * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
- * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
- * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
- * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
- * POSSIBILITY OF SUCH DAMAGE.
- *
- * Author: Slawomir Blauciak <slawomir.blauciak@linux.intel.com>
- */
-
-#include <sof/audio/component.h>
-#include <sof/audio/buffer.h>
-#include <sof/ipc.h>
-
-#include <stdio.h>
-#include <stdarg.h>
-#include <stddef.h>
-#include <setjmp.h>
-#include <math.h>
-#include <cmocka.h>
-
-static void test_audio_buffer_new(void **state)
-{
- (void)state;
-
- struct sof_ipc_buffer test_buf_desc = {
- .size = 256
- };
-
- struct comp_buffer *buf = buffer_new(&test_buf_desc);
-
- assert_non_null(buf);
- assert_int_equal(buf->avail, 0);
- assert_int_equal(buf->free, 256);
- assert_ptr_equal(buf->w_ptr, buf->r_ptr);
-
- buffer_free(buf);
-}
-
-int main(void)
-{
- const struct CMUnitTest tests[] = {
- cmocka_unit_test(test_audio_buffer_new)
- };
-
- cmocka_set_message_output(CM_OUTPUT_TAP);
-
- return cmocka_run_group_tests(tests, NULL, NULL);
-}
diff --git a/test/cmocka/src/audio/buffer/buffer_wrap.c b/test/cmocka/src/audio/buffer/buffer_wrap.c
deleted file mode 100644
index aae5b03..0000000
--- a/test/cmocka/src/audio/buffer/buffer_wrap.c
+++ /dev/null
@@ -1,91 +0,0 @@
-/*
- * Copyright (c) 2018, Intel Corporation
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- * * Redistributions of source code must retain the above copyright
- * notice, this list of conditions and the following disclaimer.
- * * Redistributions in binary form must reproduce the above copyright
- * notice, this list of conditions and the following disclaimer in the
- * documentation and/or other materials provided with the distribution.
- * * Neither the name of the Intel Corporation nor the
- * names of its contributors may be used to endorse or promote products
- * derived from this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
- * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
- * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
- * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
- * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
- * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
- * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
- * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
- * POSSIBILITY OF SUCH DAMAGE.
- *
- * Author: Slawomir Blauciak <slawomir.blauciak@linux.intel.com>
- */
-
-#include <sof/audio/component.h>
-#include <sof/audio/buffer.h>
-#include <sof/ipc.h>
-
-#include <stdio.h>
-#include <stdarg.h>
-#include <stddef.h>
-#include <setjmp.h>
-#include <math.h>
-#include <cmocka.h>
-
-static void test_audio_buffer_write_fill_10_bytes_and_write_5(void **state)
-{
- (void)state;
-
- struct sof_ipc_buffer test_buf_desc = {
- .size = 10
- };
-
- struct comp_buffer *buf = buffer_new(&test_buf_desc);
-
- assert_non_null(buf);
- assert_int_equal(buf->avail, 0);
- assert_int_equal(buf->free, 10);
- assert_ptr_equal(buf->w_ptr, buf->r_ptr);
-
- uint8_t bytes[10] = {0, 1, 2, 3, 4, 5, 6, 7, 8, 9};
-
- memcpy(buf->w_ptr, &bytes, 10);
- comp_update_buffer_produce(buf, 10);
-
- assert_int_equal(buf->avail, 10);
- assert_int_equal(buf->free, 0);
- assert_ptr_equal(buf->w_ptr, buf->r_ptr);
-
- uint8_t more_bytes[5] = {10, 11, 12, 13, 14};
-
- memcpy(buf->w_ptr, &more_bytes, 5);
- comp_update_buffer_produce(buf, 5);
-
- uint8_t ref[10] = {10, 11, 12, 13, 14, 5, 6, 7, 8, 9};
-
- assert_int_equal(buf->avail, 5);
- assert_int_equal(buf->free, 5);
- assert_ptr_equal(buf->w_ptr, buf->r_ptr + 5);
- assert_int_equal(memcmp(buf->r_ptr, &ref, 10), 0);
-
- buffer_free(buf);
-}
-
-int main(void)
-{
- const struct CMUnitTest tests[] = {
- cmocka_unit_test
- (test_audio_buffer_write_fill_10_bytes_and_write_5)
- };
-
- cmocka_set_message_output(CM_OUTPUT_TAP);
-
- return cmocka_run_group_tests(tests, NULL, NULL);
-}
diff --git a/test/cmocka/src/audio/buffer/buffer_write.c b/test/cmocka/src/audio/buffer/buffer_write.c
deleted file mode 100644
index 47e45c7..0000000
--- a/test/cmocka/src/audio/buffer/buffer_write.c
+++ /dev/null
@@ -1,116 +0,0 @@
-/*
- * Copyright (c) 2018, Intel Corporation
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- * * Redistributions of source code must retain the above copyright
- * notice, this list of conditions and the following disclaimer.
- * * Redistributions in binary form must reproduce the above copyright
- * notice, this list of conditions and the following disclaimer in the
- * documentation and/or other materials provided with the distribution.
- * * Neither the name of the Intel Corporation nor the
- * names of its contributors may be used to endorse or promote products
- * derived from this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
- * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
- * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
- * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
- * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
- * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
- * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
- * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
- * POSSIBILITY OF SUCH DAMAGE.
- *
- * Author: Slawomir Blauciak <slawomir.blauciak@linux.intel.com>
- */
-
-#include <sof/audio/component.h>
-#include <sof/audio/buffer.h>
-#include <sof/ipc.h>
-
-#include <stdio.h>
-#include <stdarg.h>
-#include <stddef.h>
-#include <setjmp.h>
-#include <math.h>
-#include <cmocka.h>
-
-static void test_audio_buffer_write_10_bytes_out_of_256_and_read_back
- (void **state)
-{
- (void)state;
-
- struct sof_ipc_buffer test_buf_desc = {
- .size = 256
- };
-
- struct comp_buffer *buf = buffer_new(&test_buf_desc);
-
- assert_non_null(buf);
- assert_int_equal(buf->avail, 0);
- assert_int_equal(buf->free, 256);
- assert_ptr_equal(buf->w_ptr, buf->r_ptr);
-
- uint8_t bytes[10] = {0, 1, 2, 3, 4, 5, 6, 7, 8, 9};
-
- memcpy(buf->w_ptr, &bytes, 10);
- comp_update_buffer_produce(buf, 10);
-
- assert_int_equal(buf->avail, 10);
- assert_int_equal(buf->free, 246);
- assert_ptr_equal(buf->w_ptr, buf->r_ptr + 10);
-
- assert_int_equal(memcmp(buf->r_ptr, &bytes, 10), 0);
-
- comp_update_buffer_consume(buf, 10);
-
- assert_int_equal(buf->avail, 0);
- assert_int_equal(buf->free, 256);
- assert_ptr_equal(buf->w_ptr, buf->r_ptr);
-
- buffer_free(buf);
-}
-
-static void test_audio_buffer_fill_10_bytes(void **state)
-{
- (void)state;
-
- struct sof_ipc_buffer test_buf_desc = {
- .size = 10
- };
-
- struct comp_buffer *buf = buffer_new(&test_buf_desc);
-
- assert_non_null(buf);
- assert_int_equal(buf->avail, 0);
- assert_int_equal(buf->free, 10);
- assert_ptr_equal(buf->w_ptr, buf->r_ptr);
-
- uint8_t bytes[10] = {0, 1, 2, 3, 4, 5, 6, 7, 8, 9};
-
- memcpy(buf->w_ptr, &bytes, 10);
- comp_update_buffer_produce(buf, 10);
-
- assert_int_equal(buf->avail, 10);
- assert_int_equal(buf->free, 0);
- assert_ptr_equal(buf->w_ptr, buf->r_ptr);
-
- buffer_free(buf);
-}
-
-int main(void)
-{
- const struct CMUnitTest tests[] = {
- cmocka_unit_test
- (test_audio_buffer_write_10_bytes_out_of_256_and_read_back),
- cmocka_unit_test(test_audio_buffer_fill_10_bytes)
- };
-
- cmocka_set_message_output(CM_OUTPUT_TAP);
-
- return cmocka_run_group_tests(tests, NULL, NULL);
-}
diff --git a/test/cmocka/src/audio/buffer/mock.c b/test/cmocka/src/audio/buffer/mock.c
deleted file mode 100644
index cfe2b2e..0000000
--- a/test/cmocka/src/audio/buffer/mock.c
+++ /dev/null
@@ -1,65 +0,0 @@
-/*
- * Copyright (c) 2018, Intel Corporation
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- * * Redistributions of source code must retain the above copyright
- * notice, this list of conditions and the following disclaimer.
- * * Redistributions in binary form must reproduce the above copyright
- * notice, this list of conditions and the following disclaimer in the
- * documentation and/or other materials provided with the distribution.
- * * Neither the name of the Intel Corporation nor the
- * names of its contributors may be used to endorse or promote products
- * derived from this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
- * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
- * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
- * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
- * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
- * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
- * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
- * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
- * POSSIBILITY OF SUCH DAMAGE.
- *
- * Author: Slawomir Blauciak <slawomir.blauciak@linux.intel.com>
- */
-
-#include <stdint.h>
-#include <stdlib.h>
-
-#include <sof/alloc.h>
-
-void _trace_event(uint32_t e)
-{
- (void)e;
-}
-
-void _trace_event_mbox_atomic(uint32_t e)
-{
- (void)e;
-}
-
-void *rzalloc(int zone, uint32_t caps, size_t bytes)
-{
- (void)zone;
- (void)caps;
-
- return malloc(bytes);
-}
-
-void *rballoc(int zone, uint32_t caps, size_t bytes)
-{
- (void)zone;
- (void)caps;
-
- return malloc(bytes);
-}
-
-void rfree(void *ptr)
-{
- free(ptr);
-}
diff --git a/test/cmocka/src/audio/component/comp_set_state.c b/test/cmocka/src/audio/component/comp_set_state.c
deleted file mode 100644
index a838677..0000000
--- a/test/cmocka/src/audio/component/comp_set_state.c
+++ /dev/null
@@ -1,253 +0,0 @@
-/*
- * Copyright (c) 2018, Intel Corporation
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- * * Redistributions of source code must retain the above copyright
- * notice, this list of conditions and the following disclaimer.
- * * Redistributions in binary form must reproduce the above copyright
- * notice, this list of conditions and the following disclaimer in the
- * documentation and/or other materials provided with the distribution.
- * * Neither the name of the Intel Corporation nor the
- * names of its contributors may be used to endorse or promote products
- * derived from this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
- * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
- * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
- * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
- * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
- * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
- * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
- * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
- * POSSIBILITY OF SUCH DAMAGE.
- *
- * Author: Bartosz Kokoszko <bartoszx.kokoszko@linux.intel.com>
- */
-
-#include <sof/audio/component.h>
-#include <errno.h>
-
-#include <stdarg.h>
-#include <stddef.h>
-#include <setjmp.h>
-#include <cmocka.h>
-#include <sof/sof.h>
-
-enum test_type {
- SUCCEED = 0,
- FAIL,
- CORRECT_OUTPUT_STATE,
-
-};
-
-struct test_case {
- enum test_type type;
- uint16_t in_state;
- int cmd;
- uint16_t out_state;
- const char *name;
-};
-
-#define TEST_CASE(type, in_state, cmd, out_state) \
- {(type), (in_state), (cmd), (out_state), \
- ("test_audio_component_comp_set_state__" \
- #type "__" #in_state "__" #cmd "__" #out_state)}
-
-
-/*
- * NULL_STATE enum is used in every case, when new state of component is
- * insignificant due to action of testing function
- */
-enum {
- NULL_STATE = -1
-};
-
-struct test_case test_cases[] = {
-
- /*succeed set state*/
- TEST_CASE(SUCCEED, COMP_STATE_PREPARE,
- COMP_TRIGGER_START, NULL_STATE),
- TEST_CASE(SUCCEED, COMP_STATE_PAUSED,
- COMP_TRIGGER_RELEASE, NULL_STATE),
- TEST_CASE(SUCCEED, COMP_STATE_ACTIVE,
- COMP_TRIGGER_STOP, NULL_STATE),
- TEST_CASE(SUCCEED, COMP_STATE_PAUSED,
- COMP_TRIGGER_STOP, NULL_STATE),
- TEST_CASE(SUCCEED, COMP_STATE_ACTIVE,
- COMP_TRIGGER_XRUN, NULL_STATE),
- TEST_CASE(SUCCEED, COMP_STATE_PAUSED,
- COMP_TRIGGER_XRUN, NULL_STATE),
- TEST_CASE(SUCCEED, COMP_STATE_ACTIVE,
- COMP_TRIGGER_PAUSE, NULL_STATE),
- TEST_CASE(SUCCEED, COMP_STATE_INIT,
- COMP_TRIGGER_RESET, NULL_STATE),
- TEST_CASE(SUCCEED, COMP_STATE_READY,
- COMP_TRIGGER_RESET, NULL_STATE),
- TEST_CASE(SUCCEED, COMP_STATE_SUSPEND,
- COMP_TRIGGER_RESET, NULL_STATE),
- TEST_CASE(SUCCEED, COMP_STATE_PREPARE,
- COMP_TRIGGER_RESET, NULL_STATE),
- TEST_CASE(SUCCEED, COMP_STATE_PAUSED,
- COMP_TRIGGER_RESET, NULL_STATE),
- TEST_CASE(SUCCEED, COMP_STATE_ACTIVE,
- COMP_TRIGGER_RESET, NULL_STATE),
- TEST_CASE(SUCCEED, COMP_STATE_PREPARE,
- COMP_TRIGGER_PREPARE, NULL_STATE),
- TEST_CASE(SUCCEED, COMP_STATE_READY,
- COMP_TRIGGER_PREPARE, NULL_STATE),
-
- /*fail set state*/
- TEST_CASE(FAIL, COMP_STATE_INIT, COMP_TRIGGER_START,
- NULL_STATE),
- TEST_CASE(FAIL, COMP_STATE_READY, COMP_TRIGGER_START,
- NULL_STATE),
- TEST_CASE(FAIL, COMP_STATE_SUSPEND, COMP_TRIGGER_START,
- NULL_STATE),
- TEST_CASE(FAIL, COMP_STATE_PAUSED, COMP_TRIGGER_START,
- NULL_STATE),
- TEST_CASE(FAIL, COMP_STATE_ACTIVE, COMP_TRIGGER_START,
- NULL_STATE),
- TEST_CASE(FAIL, COMP_STATE_INIT, COMP_TRIGGER_RELEASE,
- NULL_STATE),
- TEST_CASE(FAIL, COMP_STATE_READY, COMP_TRIGGER_RELEASE,
- NULL_STATE),
- TEST_CASE(FAIL, COMP_STATE_SUSPEND, COMP_TRIGGER_RELEASE,
- NULL_STATE),
- TEST_CASE(FAIL, COMP_STATE_PREPARE, COMP_TRIGGER_RELEASE,
- NULL_STATE),
- TEST_CASE(FAIL, COMP_STATE_INIT, COMP_TRIGGER_STOP,
- NULL_STATE),
- TEST_CASE(FAIL, COMP_STATE_READY, COMP_TRIGGER_STOP,
- NULL_STATE),
- TEST_CASE(FAIL, COMP_STATE_SUSPEND, COMP_TRIGGER_STOP,
- NULL_STATE),
- TEST_CASE(FAIL, COMP_STATE_PREPARE, COMP_TRIGGER_STOP,
- NULL_STATE),
- TEST_CASE(FAIL, COMP_STATE_INIT, COMP_TRIGGER_XRUN,
- NULL_STATE),
- TEST_CASE(FAIL, COMP_STATE_READY, COMP_TRIGGER_XRUN,
- NULL_STATE),
- TEST_CASE(FAIL, COMP_STATE_SUSPEND, COMP_TRIGGER_XRUN,
- NULL_STATE),
- TEST_CASE(FAIL, COMP_STATE_PREPARE, COMP_TRIGGER_XRUN,
- NULL_STATE),
- TEST_CASE(FAIL, COMP_STATE_INIT, COMP_TRIGGER_PAUSE,
- NULL_STATE),
- TEST_CASE(FAIL, COMP_STATE_READY, COMP_TRIGGER_PAUSE,
- NULL_STATE),
- TEST_CASE(FAIL, COMP_STATE_SUSPEND, COMP_TRIGGER_PAUSE,
- NULL_STATE),
- TEST_CASE(FAIL, COMP_STATE_PREPARE, COMP_TRIGGER_PAUSE,
- NULL_STATE),
- TEST_CASE(FAIL, COMP_STATE_PAUSED, COMP_TRIGGER_PAUSE,
- NULL_STATE),
- TEST_CASE(FAIL, COMP_STATE_INIT, COMP_TRIGGER_PREPARE,
- NULL_STATE),
- TEST_CASE(FAIL, COMP_STATE_SUSPEND, COMP_TRIGGER_PREPARE,
- NULL_STATE),
- TEST_CASE(FAIL, COMP_STATE_PAUSED, COMP_TRIGGER_PREPARE,
- NULL_STATE),
- TEST_CASE(FAIL, COMP_STATE_ACTIVE, COMP_TRIGGER_PREPARE,
- NULL_STATE),
-
- /*correct output state*/
- TEST_CASE(CORRECT_OUTPUT_STATE, COMP_STATE_PREPARE,
- COMP_TRIGGER_START, COMP_STATE_ACTIVE),
- TEST_CASE(CORRECT_OUTPUT_STATE, COMP_STATE_PAUSED,
- COMP_TRIGGER_RELEASE, COMP_STATE_ACTIVE),
- TEST_CASE(CORRECT_OUTPUT_STATE, COMP_STATE_ACTIVE,
- COMP_TRIGGER_STOP, COMP_STATE_PREPARE),
- TEST_CASE(CORRECT_OUTPUT_STATE, COMP_STATE_PAUSED,
- COMP_TRIGGER_STOP, COMP_STATE_PREPARE),
- TEST_CASE(CORRECT_OUTPUT_STATE, COMP_STATE_ACTIVE,
- COMP_TRIGGER_XRUN, COMP_STATE_PREPARE),
- TEST_CASE(CORRECT_OUTPUT_STATE, COMP_STATE_PAUSED,
- COMP_TRIGGER_XRUN, COMP_STATE_PREPARE),
- TEST_CASE(CORRECT_OUTPUT_STATE, COMP_STATE_ACTIVE,
- COMP_TRIGGER_PAUSE, COMP_STATE_PAUSED),
- TEST_CASE(CORRECT_OUTPUT_STATE, COMP_STATE_INIT,
- COMP_TRIGGER_RESET, COMP_STATE_READY),
- TEST_CASE(CORRECT_OUTPUT_STATE, COMP_STATE_READY,
- COMP_TRIGGER_RESET, COMP_STATE_READY),
- TEST_CASE(CORRECT_OUTPUT_STATE, COMP_STATE_SUSPEND,
- COMP_TRIGGER_RESET, COMP_STATE_READY),
- TEST_CASE(CORRECT_OUTPUT_STATE, COMP_STATE_PREPARE,
- COMP_TRIGGER_RESET, COMP_STATE_READY),
- TEST_CASE(CORRECT_OUTPUT_STATE, COMP_STATE_PAUSED,
- COMP_TRIGGER_RESET, COMP_STATE_READY),
- TEST_CASE(CORRECT_OUTPUT_STATE, COMP_STATE_ACTIVE,
- COMP_TRIGGER_RESET, COMP_STATE_READY),
- TEST_CASE(CORRECT_OUTPUT_STATE, COMP_STATE_PREPARE,
- COMP_TRIGGER_PREPARE, COMP_STATE_PREPARE),
- TEST_CASE(CORRECT_OUTPUT_STATE, COMP_STATE_READY,
- COMP_TRIGGER_PREPARE, COMP_STATE_PREPARE),
-};
-
-static void test_audio_component_comp_set_state_succeed(struct test_case *tc)
-{
- struct comp_dev test_dev;
-
- test_dev.state = tc->in_state;
-
- assert_int_equal(comp_set_state(&test_dev, tc->cmd), 0);
-}
-
-static void test_audio_component_comp_set_state_correct_output_state(struct test_case *tc)
-{
- struct comp_dev test_dev;
-
- test_dev.state = tc->in_state;
- comp_set_state(&test_dev, tc->cmd);
-
- assert_int_equal(test_dev.state, tc->out_state);
-}
-
-static void test_audio_component_comp_set_state_fail(struct test_case *tc)
-{
- struct comp_dev test_drv;
-
- test_drv.state = tc->in_state;
- assert_int_equal(comp_set_state(&test_drv, tc->cmd), -EINVAL);
-}
-
-static void test_audio_component_comp_set_state(void **state)
-{
- struct test_case *tc = *((struct test_case **) state);
-
- switch (tc->type) {
- case SUCCEED:
- test_audio_component_comp_set_state_succeed(tc);
- break;
- case FAIL:
- test_audio_component_comp_set_state_fail(tc);
- break;
- case CORRECT_OUTPUT_STATE:
- test_audio_component_comp_set_state_correct_output_state(tc);
- break;
- }
-}
-
-int main(void)
-{
- struct CMUnitTest tests[ARRAY_SIZE(test_cases)];
-
- int i;
-
- for (i = 0; i < ARRAY_SIZE(test_cases); i++) {
- struct CMUnitTest *t = &tests[i];
-
- t->name = test_cases[i].name;
- t->test_func = test_audio_component_comp_set_state;
- t->initial_state = &test_cases[i];
- t->setup_func = NULL;
- t->teardown_func = NULL;
-
- }
- cmocka_set_message_output(CM_OUTPUT_TAP);
-
- return cmocka_run_group_tests(tests, NULL, NULL);
-}
diff --git a/test/cmocka/src/audio/component/mock.c b/test/cmocka/src/audio/component/mock.c
deleted file mode 100644
index 175c03f..0000000
--- a/test/cmocka/src/audio/component/mock.c
+++ /dev/null
@@ -1,48 +0,0 @@
-/*
- * Copyright (c) 2018, Intel Corporation
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- * * Redistributions of source code must retain the above copyright
- * notice, this list of conditions and the following disclaimer.
- * * Redistributions in binary form must reproduce the above copyright
- * notice, this list of conditions and the following disclaimer in the
- * documentation and/or other materials provided with the distribution.
- * * Neither the name of the Intel Corporation nor the
- * names of its contributors may be used to endorse or promote products
- * derived from this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
- * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
- * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
- * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
- * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
- * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
- * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
- * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
- * POSSIBILITY OF SUCH DAMAGE.
- *
- * Author: Bartosz Kokoszko <bartoszx.kokoszko@linux.intel.com>
- */
-
-#include <stdint.h>
-#include <stdlib.h>
-
-#include <sof/alloc.h>
-#include <sof/trace.h>
-
-void _trace_event_mbox_atomic(uint32_t e)
-{
- (void)e;
-}
-
-void *rzalloc(int zone, uint32_t caps, size_t bytes)
-{
- (void)zone;
- (void)caps;
-
- return calloc(bytes, 1);
-}
diff --git a/test/cmocka/src/audio/mixer/comp_mock.c b/test/cmocka/src/audio/mixer/comp_mock.c
deleted file mode 100644
index a73bf5c..0000000
--- a/test/cmocka/src/audio/mixer/comp_mock.c
+++ /dev/null
@@ -1,91 +0,0 @@
-/*
- * Copyright (c) 2018, Intel Corporation
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- * * Redistributions of source code must retain the above copyright
- * notice, this list of conditions and the following disclaimer.
- * * Redistributions in binary form must reproduce the above copyright
- * notice, this list of conditions and the following disclaimer in the
- * documentation and/or other materials provided with the distribution.
- * * Neither the name of the Intel Corporation nor the
- * names of its contributors may be used to endorse or promote products
- * derived from this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
- * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
- * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
- * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
- * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
- * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
- * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
- * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
- * POSSIBILITY OF SUCH DAMAGE.
- *
- * Author: Slawomir Blauciak <slawomir.blauciak@linux.intel.com>
- */
-
-#include <stdint.h>
-#include <stddef.h>
-#include <sof/lock.h>
-#include <sof/list.h>
-#include <sof/stream.h>
-#include <sof/audio/component.h>
-
-#include "comp_mock.h"
-
-static struct comp_dev *mock_comp_new(struct sof_ipc_comp *comp)
-{
- return calloc(1, sizeof(struct comp_dev));
-}
-
-static void mock_comp_free(struct comp_dev *dev)
-{
- free(dev);
-}
-
-static int mock_comp_params(struct comp_dev *dev)
-{
- return 0;
-}
-
-static int mock_comp_cmd(struct comp_dev *dev, int cmd, void *data)
-{
- return 0;
-}
-
-static int mock_comp_copy(struct comp_dev *dev)
-{
- return 0;
-}
-
-static int mock_comp_reset(struct comp_dev *dev)
-{
- return 0;
-}
-
-static int mock_comp_prepare(struct comp_dev *dev)
-{
- return 0;
-}
-
-struct comp_driver comp_mock = {
- .type = SOF_COMP_MOCK,
- .ops = {
- .new = mock_comp_new,
- .free = mock_comp_free,
- .params = mock_comp_params,
- .cmd = mock_comp_cmd,
- .copy = mock_comp_copy,
- .prepare = mock_comp_prepare,
- .reset = mock_comp_reset,
- },
-};
-
-void sys_comp_mock_init(void)
-{
- comp_register(&comp_mock);
-}
diff --git a/test/cmocka/src/audio/mixer/comp_mock.h b/test/cmocka/src/audio/mixer/comp_mock.h
deleted file mode 100644
index 035fa69..0000000
--- a/test/cmocka/src/audio/mixer/comp_mock.h
+++ /dev/null
@@ -1,36 +0,0 @@
-/*
- * Copyright (c) 2018, Intel Corporation
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- * * Redistributions of source code must retain the above copyright
- * notice, this list of conditions and the following disclaimer.
- * * Redistributions in binary form must reproduce the above copyright
- * notice, this list of conditions and the following disclaimer in the
- * documentation and/or other materials provided with the distribution.
- * * Neither the name of the Intel Corporation nor the
- * names of its contributors may be used to endorse or promote products
- * derived from this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
- * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
- * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
- * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
- * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
- * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
- * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
- * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
- * POSSIBILITY OF SUCH DAMAGE.
- *
- * Author: Slawomir Blauciak <slawomir.blauciak@linux.intel.com>
- */
-
-#include <stdint.h>
-#include <sof/audio/component.h>
-
-#define SOF_COMP_MOCK ((uint32_t)-1)
-
-void sys_comp_mock_init(void);
diff --git a/test/cmocka/src/audio/mixer/mixer_test.c b/test/cmocka/src/audio/mixer/mixer_test.c
deleted file mode 100644
index d5ece9a..0000000
--- a/test/cmocka/src/audio/mixer/mixer_test.c
+++ /dev/null
@@ -1,328 +0,0 @@
-/*
- * Copyright (c) 2018, Intel Corporation
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- * * Redistributions of source code must retain the above copyright
- * notice, this list of conditions and the following disclaimer.
- * * Redistributions in binary form must reproduce the above copyright
- * notice, this list of conditions and the following disclaimer in the
- * documentation and/or other materials provided with the distribution.
- * * Neither the name of the Intel Corporation nor the
- * names of its contributors may be used to endorse or promote products
- * derived from this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
- * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
- * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
- * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
- * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
- * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
- * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
- * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
- * POSSIBILITY OF SUCH DAMAGE.
- *
- * Author: Slawomir Blauciak <slawomir.blauciak@linux.intel.com>
- */
-
-#include <stdarg.h>
-#include <stddef.h>
-#include <math.h>
-#include <setjmp.h>
-#include <cmocka.h>
-
-#include <sof/list.h>
-#include <sof/ipc.h>
-#include <sof/audio/buffer.h>
-#include <sof/audio/component.h>
-#include <sof/audio/format.h>
-
-#include "comp_mock.h"
-
-#define MIX_TEST_SAMPLES 32
-
-struct comp_driver drv_mock;
-
-struct comp_driver mixer_drv_mock;
-struct comp_dev *mixer_dev_mock;
-
-struct comp_dev *post_mixer_comp;
-struct comp_buffer *post_mixer_buf;
-
-/* Mocking comp_register here so we can register our components properly */
-int comp_register(struct comp_driver *drv)
-{
- void *dst;
-
- switch (drv->type) {
- case SOF_COMP_MIXER:
- dst = &mixer_drv_mock;
- break;
-
- case SOF_COMP_MOCK:
- dst = &drv_mock;
- break;
- }
-
- memcpy(dst, drv, sizeof(struct comp_driver));
-
- return 0;
-}
-
-struct source {
- struct comp_dev *comp;
- struct comp_buffer *buf;
-};
-
-struct mix_test_case {
- int num_sources;
- int num_chans;
- const char *name;
- struct source *sources;
-};
-
-#define TEST_CASE(_num_sources, _num_chans) \
- { \
- .num_sources = (_num_sources), \
- .num_chans = (_num_chans), \
- .name = ("test_audio_mixer_copy_" \
- #_num_sources "_srcs_" \
- #_num_chans "ch"), \
- .sources = NULL \
- }
-
-static struct mix_test_case mix_test_cases[] = {
- TEST_CASE(1, 2),
- TEST_CASE(1, 4),
- TEST_CASE(1, 8),
- TEST_CASE(2, 2),
- TEST_CASE(2, 4),
- TEST_CASE(2, 8),
- TEST_CASE(3, 2),
- TEST_CASE(4, 2),
- TEST_CASE(6, 2),
- TEST_CASE(8, 2)
-};
-
-static struct sof_ipc_comp mixer = {
- .type = SOF_COMP_MIXER
-};
-
-static struct sof_ipc_comp mock_comp = {
- .type = SOF_COMP_MOCK
-};
-
-static struct comp_dev *create_comp(struct sof_ipc_comp *comp,
- struct comp_driver *drv)
-{
- struct comp_dev *cd = drv->ops.new(comp);
-
- assert_non_null(cd);
-
- memcpy(&cd->comp, comp, sizeof(*comp));
- cd->drv = drv;
- spinlock_init(&cd->lock);
- list_init(&cd->bsource_list);
- list_init(&cd->bsink_list);
-
- return cd;
-}
-
-static void destroy_comp(struct comp_driver *drv, struct comp_dev *dev)
-{
- drv->ops.free(dev);
-}
-
-static void create_sources(struct mix_test_case *tc)
-{
- int src_idx;
-
- tc->sources = malloc(tc->num_sources * sizeof(struct source));
-
- for (src_idx = 0; src_idx < tc->num_sources; ++src_idx) {
- struct source *src = &tc->sources[src_idx];
-
- struct sof_ipc_buffer buf = {
- .size = (MIX_TEST_SAMPLES * sizeof(uint32_t)) *
- tc->num_chans
- };
-
- src->comp = create_comp(&mock_comp, &drv_mock);
- src->buf = buffer_new(&buf);
-
- src->buf->source = src->comp;
- src->buf->sink = mixer_dev_mock;
-
- list_item_prepend(&src->buf->source_list,
- &src->comp->bsink_list);
- list_item_prepend(&src->buf->sink_list,
- &mixer_dev_mock->bsource_list);
- }
-}
-
-static void destroy_sources(struct mix_test_case *tc)
-{
- int src_idx;
-
- for (src_idx = 0; src_idx < tc->num_sources; ++src_idx)
- destroy_comp(&drv_mock, tc->sources[src_idx].comp);
-
- free(tc->sources);
-}
-
-static void activate_periph_comps(struct mix_test_case *tc)
-{
- int src_idx;
-
- for (src_idx = 0; src_idx < tc->num_sources; ++src_idx)
- tc->sources[src_idx].comp->state = COMP_STATE_ACTIVE;
-
- post_mixer_comp->state = COMP_STATE_ACTIVE;
-}
-
-static int test_group_setup(void **state)
-{
- sys_comp_mixer_init();
- sys_comp_mock_init();
-
- return 0;
-}
-
-static int test_setup(void **state)
-{
- mixer_dev_mock = create_comp(&mixer, &mixer_drv_mock);
-
- struct mix_test_case *tc = *((struct mix_test_case **)state);
-
- if (tc) {
- struct sof_ipc_buffer buf = {
- .size = (MIX_TEST_SAMPLES * sizeof(uint32_t)) *
- tc->num_chans
- };
-
- post_mixer_buf = buffer_new(&buf);
-
- create_sources(tc);
- post_mixer_comp = create_comp(&mock_comp, &drv_mock);
-
- activate_periph_comps(tc);
- mixer_drv_mock.ops.prepare(mixer_dev_mock);
-
- mixer_dev_mock->state = COMP_STATE_ACTIVE;
-
- post_mixer_buf->source = mixer_dev_mock;
- post_mixer_buf->sink = post_mixer_comp;
- list_item_prepend(&post_mixer_buf->source_list,
- &mixer_dev_mock->bsink_list);
- list_item_prepend(&post_mixer_buf->sink_list,
- &post_mixer_comp->bsource_list);
-
- mixer_dev_mock->frames = MIX_TEST_SAMPLES;
- }
-
- return 0;
-}
-
-static int test_teardown(void **state)
-{
- destroy_comp(&mixer_drv_mock, mixer_dev_mock);
-
- struct mix_test_case *tc = *((struct mix_test_case **)state);
-
- if (tc) {
- buffer_free(post_mixer_buf);
- destroy_sources(tc);
- }
-
- return 0;
-}
-
-/*
- * Tests
- */
-
-static void test_audio_mixer_new(void **state)
-{
- assert_non_null(mixer_dev_mock->private);
-}
-
-static void test_audio_mixer_prepare_no_sources(void **state)
-{
- int downstream = mixer_drv_mock.ops.prepare(mixer_dev_mock);
-
- assert_int_equal(downstream, 0);
-}
-
-static void test_audio_mixer_copy(void **state)
-{
- int src_idx;
- int smp;
- struct mix_test_case *tc = *((struct mix_test_case **)state);
-
- mixer_dev_mock->params.channels = tc->num_chans;
-
- for (src_idx = 0; src_idx < tc->num_sources; ++src_idx) {
- uint32_t *samples = tc->sources[src_idx].buf->addr;
-
- for (smp = 0; smp < MIX_TEST_SAMPLES; ++smp) {
- double rad = M_PI / (180.0 / (smp * (src_idx + 1)));
-
- samples[smp] = ((sin(rad) + 1) / 2) * (0xFFFFFFFF / 2);
- }
- }
-
- mixer_drv_mock.ops.copy(mixer_dev_mock);
-
- for (smp = 0; smp < MIX_TEST_SAMPLES; ++smp) {
- uint64_t sum = 0;
-
- for (src_idx = 0; src_idx < tc->num_sources; ++src_idx) {
- assert_non_null(tc->sources[src_idx].buf);
-
- uint32_t *samples = tc->sources[src_idx].buf->addr;
-
- sum += samples[smp];
- }
-
- sum = sat_int32(sum);
-
- uint32_t *out_samples = post_mixer_buf->addr;
-
- assert_int_equal(out_samples[smp], sum);
- }
-}
-
-int main(void)
-{
- struct CMUnitTest tests[ARRAY_SIZE(mix_test_cases) + 2];
-
- int i;
- int cur_test_case = 0;
-
- tests[0].test_func = test_audio_mixer_new;
- tests[0].initial_state = NULL;
- tests[0].setup_func = test_setup;
- tests[0].teardown_func = test_teardown;
- tests[0].name = "test_audio_mixer_new";
-
- tests[1].test_func = test_audio_mixer_prepare_no_sources;
- tests[1].initial_state = NULL;
- tests[1].setup_func = test_setup;
- tests[1].teardown_func = test_teardown;
- tests[1].name = "test_audio_mixer_prepare_no_sources";
-
- for (i = 2; i < ARRAY_SIZE(tests); (++i, ++cur_test_case)) {
- tests[i].test_func = test_audio_mixer_copy;
- tests[i].initial_state = &mix_test_cases[cur_test_case];
- tests[i].setup_func = test_setup;
- tests[i].teardown_func = test_teardown;
- tests[i].name = mix_test_cases[cur_test_case].name;
- }
-
- cmocka_set_message_output(CM_OUTPUT_TAP);
-
- return cmocka_run_group_tests(tests, test_group_setup, NULL);
-}
diff --git a/test/cmocka/src/audio/mixer/mock.c b/test/cmocka/src/audio/mixer/mock.c
deleted file mode 100644
index 4f506f6..0000000
--- a/test/cmocka/src/audio/mixer/mock.c
+++ /dev/null
@@ -1,83 +0,0 @@
-/*
- * Copyright (c) 2018, Intel Corporation
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- * * Redistributions of source code must retain the above copyright
- * notice, this list of conditions and the following disclaimer.
- * * Redistributions in binary form must reproduce the above copyright
- * notice, this list of conditions and the following disclaimer in the
- * documentation and/or other materials provided with the distribution.
- * * Neither the name of the Intel Corporation nor the
- * names of its contributors may be used to endorse or promote products
- * derived from this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
- * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
- * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
- * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
- * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
- * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
- * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
- * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
- * POSSIBILITY OF SUCH DAMAGE.
- *
- * Author: Slawomir Blauciak <slawomir.blauciak@linux.intel.com>
- */
-
-#include <stdarg.h>
-#include <stddef.h>
-#include <setjmp.h>
-#include <cmocka.h>
-
-#include <sof/alloc.h>
-#include <sof/audio/component.h>
-
-#include "comp_mock.h"
-
-void _trace_event(uint32_t e)
-{
- (void)e;
-}
-
-void _trace_event_mbox_atomic(uint32_t e)
-{
- (void)e;
-}
-
-void *rballoc(int zone, uint32_t caps, size_t bytes)
-{
- (void)zone;
- (void)caps;
-
- return malloc(bytes);
-}
-
-void *rzalloc(int zone, uint32_t caps, size_t bytes)
-{
- (void)zone;
- (void)caps;
-
- return calloc(bytes, 1);
-}
-
-void rfree(void *ptr)
-{
- free(ptr);
-}
-
-void pipeline_xrun(struct pipeline *p, struct comp_dev *dev, int32_t bytes)
-{
-}
-
-int comp_set_state(struct comp_dev *dev, int cmd)
-{
- return 0;
-}
-
-void work_schedule_default(struct work *w, uint64_t timeout)
-{
-}
diff --git a/test/cmocka/src/audio/pipeline/pipeline_mocks.c b/test/cmocka/src/audio/pipeline/pipeline_mocks.c
deleted file mode 100644
index c7538c9..0000000
--- a/test/cmocka/src/audio/pipeline/pipeline_mocks.c
+++ /dev/null
@@ -1,84 +0,0 @@
-/*
- * Copyright (c) 2018, Intel Corporation
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- * * Redistributions of source code must retain the above copyright
- * notice, this list of conditions and the following disclaimer.
- * * Redistributions in binary form must reproduce the above copyright
- * notice, this list of conditions and the following disclaimer in the
- * documentation and/or other materials provided with the distribution.
- * * Neither the name of the Intel Corporation nor the
- * names of its contributors may be used to endorse or promote products
- * derived from this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
- * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
- * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
- * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
- * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
- * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
- * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
- * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
- * POSSIBILITY OF SUCH DAMAGE.
- *
- * Author: Jakub Dabek <jakub.dabek@linux.intel.com>
- */
-
-#include "pipeline_mocks.h"
-
-void platform_dai_timestamp(struct comp_dev *dai,
- struct sof_ipc_stream_posn *posn)
-{
- (void)dai;
- (void)posn;
-}
-
-void schedule_task(struct task *task, uint64_t start, uint64_t deadline)
-{
- (void)deadline;
- (void)start;
- (void)task;
-}
-
-void schedule_task_complete(struct task *task)
-{
- (void)task;
-}
-
-void schedule_task_idle(struct task *task, uint64_t deadline)
-{
- (void)deadline;
- (void)task;
-}
-
-void rfree(void *ptr)
-{
- (void)ptr;
-}
-
-void platform_host_timestamp(struct comp_dev *host,
- struct sof_ipc_stream_posn *posn)
-{
- (void)host;
- (void)posn;
-}
-
-int ipc_stream_send_xrun(struct comp_dev *cdev,
- struct sof_ipc_stream_posn *posn)
-{
- return 0;
-}
-
-void _trace_event(uint32_t event)
-{
- (void)event;
-}
-
-void _trace_event_mbox_atomic(uint32_t event)
-{
- (void)event;
-}
diff --git a/test/cmocka/src/audio/pipeline/pipeline_mocks.h b/test/cmocka/src/audio/pipeline/pipeline_mocks.h
deleted file mode 100644
index 52aee79..0000000
--- a/test/cmocka/src/audio/pipeline/pipeline_mocks.h
+++ /dev/null
@@ -1,46 +0,0 @@
-/*
- * Copyright (c) 2018, Intel Corporation
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- * * Redistributions of source code must retain the above copyright
- * notice, this list of conditions and the following disclaimer.
- * * Redistributions in binary form must reproduce the above copyright
- * notice, this list of conditions and the following disclaimer in the
- * documentation and/or other materials provided with the distribution.
- * * Neither the name of the Intel Corporation nor the
- * names of its contributors may be used to endorse or promote products
- * derived from this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
- * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
- * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
- * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
- * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
- * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
- * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
- * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
- * POSSIBILITY OF SUCH DAMAGE.
- *
- * Author: Jakub Dabek <jakub.dabek@linux.intel.com>
- */
-
-#include <sof/audio/component.h>
-#include <sof/audio/pipeline.h>
-#include <sof/schedule.h>
-#include <stdarg.h>
-#include <stddef.h>
-#include <setjmp.h>
-#include <stdint.h>
-#include <cmocka.h>
-
-int ipc_stream_send_xrun(struct comp_dev *cdev,
- struct sof_ipc_stream_posn *posn);
-
-struct pipeline_new_setup_data {
- struct sof_ipc_pipe_new ipc_data;
- struct comp_dev *comp_data;
-};
diff --git a/test/cmocka/src/audio/pipeline/pipeline_mocks_rzalloc.c b/test/cmocka/src/audio/pipeline/pipeline_mocks_rzalloc.c
deleted file mode 100644
index fc6372d..0000000
--- a/test/cmocka/src/audio/pipeline/pipeline_mocks_rzalloc.c
+++ /dev/null
@@ -1,46 +0,0 @@
-/*
- * Copyright (c) 2018, Intel Corporation
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- * * Redistributions of source code must retain the above copyright
- * notice, this list of conditions and the following disclaimer.
- * * Redistributions in binary form must reproduce the above copyright
- * notice, this list of conditions and the following disclaimer in the
- * documentation and/or other materials provided with the distribution.
- * * Neither the name of the Intel Corporation nor the
- * names of its contributors may be used to endorse or promote products
- * derived from this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
- * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
- * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
- * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
- * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
- * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
- * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
- * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
- * POSSIBILITY OF SUCH DAMAGE.
- *
- * Author: Jakub Dabek <jakub.dabek@linux.intel.com>
- */
-
-#include <sof/audio/component.h>
-#include <sof/audio/pipeline.h>
-#include <sof/schedule.h>
-#include <stdarg.h>
-#include <stddef.h>
-#include <setjmp.h>
-#include <stdint.h>
-#include <cmocka.h>
-#include <sof/alloc.h>
-
-void *rzalloc(int zone, uint32_t caps, size_t bytes)
-{
- (void)zone;
- (void)caps;
- return calloc(bytes, 1);
-}
diff --git a/test/cmocka/src/audio/pipeline/pipeline_new.c b/test/cmocka/src/audio/pipeline/pipeline_new.c
deleted file mode 100644
index 6c25567..0000000
--- a/test/cmocka/src/audio/pipeline/pipeline_new.c
+++ /dev/null
@@ -1,143 +0,0 @@
-/*
- * Copyright (c) 2018, Intel Corporation
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- * * Redistributions of source code must retain the above copyright
- * notice, this list of conditions and the following disclaimer.
- * * Redistributions in binary form must reproduce the above copyright
- * notice, this list of conditions and the following disclaimer in the
- * documentation and/or other materials provided with the distribution.
- * * Neither the name of the Intel Corporation nor the
- * names of its contributors may be used to endorse or promote products
- * derived from this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
- * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
- * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
- * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
- * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
- * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
- * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
- * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
- * POSSIBILITY OF SUCH DAMAGE.
- *
- * Author: Jakub Dabek <jakub.dabek@linux.intel.com>
- */
-
-#include <stdint.h>
-#include <sof/audio/component.h>
-#include <sof/audio/pipeline.h>
-#include <sof/schedule.h>
-#include "pipeline_mocks.h"
-#include <stdarg.h>
-#include <stddef.h>
-#include <setjmp.h>
-#include <cmocka.h>
-
-static int setup(void **state)
-{
- struct pipeline_new_setup_data *pipeline_data = malloc(
- sizeof(struct pipeline_new_setup_data));
-
- if (pipeline_data == NULL)
- return -1;
-
- struct sof_ipc_pipe_new pipe_desc = { .core = 1, .priority = 2 };
-
- pipeline_data->ipc_data = pipe_desc;
-
- *state = pipeline_data;
- return 0;
-}
-
-static int teardown(void **state)
-{
- free(*state);
- return 0;
-}
-
-static void test_audio_pipeline_pipeline_new_creation(void **state)
-{
- struct pipeline_new_setup_data *test_data = *state;
-
- /*Testing component*/
- struct pipeline *result = pipeline_new(&test_data->ipc_data,
- test_data->comp_data);
-
- /*Pipeline should have been created so pointer can't be null*/
- assert_non_null(result);
-}
-
-static void test_audio_pipeline_new_list_initialization(void **state)
-{
- struct pipeline_new_setup_data *test_data = *state;
-
- /*Testing component*/
- struct pipeline *result = pipeline_new(&test_data->ipc_data,
- test_data->comp_data);
-
- /*Check list initialization*/
- assert_ptr_equal(&result->comp_list, result->comp_list.next);
- assert_ptr_equal(&result->buffer_list, result->buffer_list.next);
-}
-
-static void test_audio_pipeline_new_sheduler_init(void **state)
-{
- struct pipeline_new_setup_data *test_data = *state;
-
- /*Testing component*/
- struct pipeline *result = pipeline_new(&test_data->ipc_data,
- test_data->comp_data);
-
- /*Check if all parameters are passed to sheduler
- *(initialization)
- */
- assert_int_equal(result->pipe_task.state, TASK_STATE_INIT);
- assert_int_equal(result->pipe_task.core, test_data->ipc_data.core);
-}
-
-static void test_audio_pipeline_new_sheduler_config(void **state)
-{
- struct pipeline_new_setup_data *test_data = *state;
-
- /*Testing component*/
- struct pipeline *result = pipeline_new(&test_data->ipc_data,
- test_data->comp_data);
-
- /*Pipeline should end in pre init state untli sheduler runs
- *task that initializes it
- */
- assert_int_equal(COMP_STATE_INIT, result->status);
-}
-
-static void test_audio_pipeline_new_ipc_data_coppy(void **state)
-{
- struct pipeline_new_setup_data *test_data = *state;
-
- /*Testing component*/
- struct pipeline *result = pipeline_new(&test_data->ipc_data,
- test_data->comp_data);
-
- assert_memory_equal(&test_data->ipc_data, &result->ipc_pipe,
- sizeof(struct sof_ipc_pipe_new));
-}
-
-int main(void)
-{
-
- const struct CMUnitTest tests[] = {
- cmocka_unit_test(test_audio_pipeline_pipeline_new_creation),
- cmocka_unit_test(test_audio_pipeline_new_list_initialization),
- cmocka_unit_test(test_audio_pipeline_new_sheduler_init),
- cmocka_unit_test(test_audio_pipeline_new_sheduler_config),
- cmocka_unit_test(test_audio_pipeline_new_ipc_data_coppy),
- };
-
- cmocka_set_message_output(CM_OUTPUT_TAP);
-
- return cmocka_run_group_tests(tests, setup, teardown);
-}
diff --git a/test/cmocka/src/audio/pipeline/pipeline_new_allocation.c b/test/cmocka/src/audio/pipeline/pipeline_new_allocation.c
deleted file mode 100644
index 3dc0d2e..0000000
--- a/test/cmocka/src/audio/pipeline/pipeline_new_allocation.c
+++ /dev/null
@@ -1,73 +0,0 @@
-/*
- * Copyright (c) 2018, Intel Corporation
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- * * Redistributions of source code must retain the above copyright
- * notice, this list of conditions and the following disclaimer.
- * * Redistributions in binary form must reproduce the above copyright
- * notice, this list of conditions and the following disclaimer in the
- * documentation and/or other materials provided with the distribution.
- * * Neither the name of the Intel Corporation nor the
- * names of its contributors may be used to endorse or promote products
- * derived from this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
- * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
- * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
- * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
- * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
- * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
- * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
- * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
- * POSSIBILITY OF SUCH DAMAGE.
- *
- * Author: Jakub Dabek <jakub.dabek@linux.intel.com>
- */
-
-#include <stdint.h>
-#include <sof/audio/component.h>
-#include <sof/audio/pipeline.h>
-#include <sof/schedule.h>
-#include "pipeline_mocks.h"
-#include <stdarg.h>
-#include <stddef.h>
-#include <setjmp.h>
-#include <cmocka.h>
-
-static void test_audio_pipeline_pipeline_new_memory_allocation(
- void **state)
-{
- (void)state;
-
- /*Initialize structs for arguments*/
- struct sof_ipc_pipe_new pipe_desc = {.core = 1, .priority = 2};
- struct comp_dev *cd = malloc(sizeof(cd));
- struct pipeline *result;
-
- /*Memmory allocation values check. Pipeline can have those changed
- *in future so expect errors here if any change to pipeline memory
- *capabilities or memmory space was made
- */
- expect_value(rzalloc, zone, RZONE_RUNTIME);
- expect_value(rzalloc, caps, SOF_MEM_CAPS_RAM);
- expect_value(rzalloc, bytes, sizeof(struct pipeline));
-
- /*Testing component*/
- result = pipeline_new(&pipe_desc, cd);
-}
-
-int main(void)
-{
- const struct CMUnitTest tests[] = {
- cmocka_unit_test(
- test_audio_pipeline_pipeline_new_memory_allocation),
- };
-
- cmocka_set_message_output(CM_OUTPUT_TAP);
-
- return cmocka_run_group_tests(tests, NULL, NULL);
-}
diff --git a/test/cmocka/src/audio/pipeline/pipeline_new_allocation_mocks.c b/test/cmocka/src/audio/pipeline/pipeline_new_allocation_mocks.c
deleted file mode 100644
index 6a21c66..0000000
--- a/test/cmocka/src/audio/pipeline/pipeline_new_allocation_mocks.c
+++ /dev/null
@@ -1,48 +0,0 @@
-/*
- * Copyright (c) 2018, Intel Corporation
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- * * Redistributions of source code must retain the above copyright
- * notice, this list of conditions and the following disclaimer.
- * * Redistributions in binary form must reproduce the above copyright
- * notice, this list of conditions and the following disclaimer in the
- * documentation and/or other materials provided with the distribution.
- * * Neither the name of the Intel Corporation nor the
- * names of its contributors may be used to endorse or promote products
- * derived from this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
- * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
- * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
- * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
- * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
- * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
- * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
- * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
- * POSSIBILITY OF SUCH DAMAGE.
- *
- * Author: Jakub Dabek <jakub.dabek@linux.intel.com>
- */
-
-#include <sof/audio/component.h>
-#include <sof/audio/pipeline.h>
-#include <sof/schedule.h>
-#include <stdarg.h>
-#include <stddef.h>
-#include <setjmp.h>
-#include <stdint.h>
-#include <cmocka.h>
-
-void *rzalloc(int zone, uint32_t caps, size_t bytes)
-{
- check_expected(zone);
- check_expected(caps);
- check_expected(bytes);
- (void)zone;
- (void)caps;
- return calloc(bytes, 1);
-}
diff --git a/test/cmocka/src/audio/volume/volume_process.c b/test/cmocka/src/audio/volume/volume_process.c
deleted file mode 100644
index e5b7ac3..0000000
--- a/test/cmocka/src/audio/volume/volume_process.c
+++ /dev/null
@@ -1,353 +0,0 @@
-/*
- * Copyright (c) 2018, Intel Corporation
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- * * Redistributions of source code must retain the above copyright
- * notice, this list of conditions and the following disclaimer.
- * * Redistributions in binary form must reproduce the above copyright
- * notice, this list of conditions and the following disclaimer in the
- * documentation and/or other materials provided with the distribution.
- * * Neither the name of the Intel Corporation nor the
- * names of its contributors may be used to endorse or promote products
- * derived from this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
- * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
- * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
- * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
- * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
- * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
- * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
- * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
- * POSSIBILITY OF SUCH DAMAGE.
- *
- * Author: Tomasz Lauda <tomasz.lauda@linux.intel.com>
- */
-
-#include <stdarg.h>
-#include <stddef.h>
-#include <setjmp.h>
-#include <cmocka.h>
-#include <sof/audio/component.h>
-#include "volume.h"
-
-#define VOL_SCALE (uint32_t)((double)INT32_MAX / VOL_MAX)
-
-struct vol_test_state {
- struct comp_dev *dev;
- struct comp_buffer *sink;
- struct comp_buffer *source;
- void (*verify)(struct comp_dev *dev, struct comp_buffer *sink,
- struct comp_buffer *source);
-};
-
-struct vol_test_parameters {
- uint32_t volume;
- uint32_t channels;
- uint32_t frames;
- uint32_t buffer_size_ms;
- uint32_t source_format;
- uint32_t sink_format;
- void (*verify)(struct comp_dev *dev, struct comp_buffer *sink,
- struct comp_buffer *source);
-};
-
-static void set_volume(uint32_t *vol, uint32_t value, uint32_t channels)
-{
- int i;
-
- for (i = 0; i < channels; i++)
- vol[i] = value;
-}
-
-static int setup(void **state)
-{
- struct vol_test_parameters *parameters = *state;
- struct vol_test_state *vol_state;
- struct comp_data *cd;
- uint32_t size = 0;
-
- /* allocate new state */
- vol_state = test_malloc(sizeof(*vol_state));
-
- /* allocate and set new device */
- vol_state->dev = test_malloc(COMP_SIZE(struct sof_ipc_comp_volume));
- vol_state->dev->params.channels = parameters->channels;
- vol_state->dev->frames = parameters->frames;
-
- /* allocate and set new data */
- cd = test_malloc(sizeof(*cd));
- comp_set_drvdata(vol_state->dev, cd);
- cd->source_format = parameters->source_format;
- cd->sink_format = parameters->sink_format;
- cd->scale_vol = vol_get_processing_function(vol_state->dev);
- set_volume(cd->volume, parameters->volume, parameters->channels);
-
- /* allocate new sink buffer */
- vol_state->sink = test_malloc(sizeof(*vol_state->sink));
- vol_state->dev->params.frame_fmt = parameters->sink_format;
- size = parameters->frames * comp_frame_bytes(vol_state->dev);
- vol_state->sink->w_ptr = test_calloc(parameters->buffer_size_ms,
- size);
- vol_state->sink->size = parameters->buffer_size_ms * size;
-
- /* allocate new source buffer */
- vol_state->source = test_malloc(sizeof(*vol_state->source));
- vol_state->dev->params.frame_fmt = parameters->source_format;
- size = parameters->frames * comp_frame_bytes(vol_state->dev);
- vol_state->source->r_ptr = test_calloc(parameters->buffer_size_ms,
- size);
- vol_state->source->size = parameters->buffer_size_ms * size;
-
- /* assigns verification function */
- vol_state->verify = parameters->verify;
-
- /* assign test state */
- *state = vol_state;
-
- return 0;
-}
-
-static int teardown(void **state)
-{
- struct vol_test_state *vol_state = *state;
- struct comp_data *cd = comp_get_drvdata(vol_state->dev);
-
- /* free everything */
- test_free(cd);
- test_free(vol_state->dev);
- test_free(vol_state->sink->w_ptr);
- test_free(vol_state->sink);
- test_free(vol_state->source->r_ptr);
- test_free(vol_state->source);
- test_free(vol_state);
-
- return 0;
-}
-
-static void fill_source_s16(struct vol_test_state *vol_state)
-{
- int16_t *src = (int16_t *)vol_state->source->r_ptr;
- int i;
-
- for (i = 0; i < vol_state->source->size / sizeof(int16_t); i++)
- src[i] = i;
-}
-
-static void fill_source_s32(struct vol_test_state *vol_state)
-{
- int32_t *src = (int32_t *)vol_state->source->r_ptr;
- int i;
-
- for (i = 0; i < vol_state->source->size / sizeof(int32_t); i++)
- src[i] = i << 16;
-}
-
-static void verify_s16_to_s16(struct comp_dev *dev, struct comp_buffer *sink,
- struct comp_buffer *source)
-{
- struct comp_data *cd = comp_get_drvdata(dev);
- const uint16_t *src = (uint16_t *)source->r_ptr;
- const uint16_t *dst = (uint16_t *)sink->w_ptr;
- int channels = dev->params.channels;
- int channel;
- int i;
- double processed;
-
- for (i = 0; i < sink->size / sizeof(uint16_t); i += channels) {
- for (channel = 0; channel < channels; channel++) {
- processed = src[i + channel] *
- ((double)cd->volume[channel] *
- (double)VOL_SCALE / INT32_MAX);
- assert_int_equal(dst[i + channel], processed + 0.5);
- }
- }
-}
-
-static void verify_s16_to_sX(struct comp_dev *dev, struct comp_buffer *sink,
- struct comp_buffer *source)
-{
- struct comp_data *cd = comp_get_drvdata(dev);
- const uint16_t *src = (uint16_t *)source->r_ptr;
- const uint32_t *dst = (uint32_t *)sink->w_ptr;
- int channels = dev->params.channels;
- int channel;
- int i;
- double processed;
- int shift = 0;
-
- /* get shift value */
- if (cd->sink_format == SOF_IPC_FRAME_S24_4LE)
- shift = 8;
- else if (cd->sink_format == SOF_IPC_FRAME_S32_LE)
- shift = 16;
-
- for (i = 0; i < sink->size / sizeof(uint32_t); i += channels) {
- for (channel = 0; channel < channels; channel++) {
- processed = src[i + channel] *
- ((double)cd->volume[channel] *
- (double)VOL_SCALE / INT32_MAX);
- assert_int_equal(dst[i + channel],
- (uint32_t)(processed + 0.5) << shift);
- }
- }
-}
-
-static void verify_sX_to_s16(struct comp_dev *dev, struct comp_buffer *sink,
- struct comp_buffer *source)
-{
- struct comp_data *cd = comp_get_drvdata(dev);
- const uint32_t *src = (uint32_t *)source->r_ptr;
- const uint16_t *dst = (uint16_t *)sink->w_ptr;
- int channels = dev->params.channels;
- int channel;
- int i;
- double processed;
- int shift = 0;
-
- /* get shift value */
- if (cd->source_format == SOF_IPC_FRAME_S24_4LE)
- shift = 8;
-
- for (i = 0; i < sink->size / sizeof(uint16_t); i += channels) {
- for (channel = 0; channel < channels; channel++) {
- processed = (src[i + channel] << shift) *
- ((double)cd->volume[channel] *
- (double)VOL_SCALE / INT32_MAX);
- assert_int_equal(dst[i + channel],
- (uint32_t)(processed + 0.5) >> 16);
- }
- }
-}
-
-static void verify_s24_to_s24_s32(struct comp_dev *dev,
- struct comp_buffer *sink,
- struct comp_buffer *source)
-{
- struct comp_data *cd = comp_get_drvdata(dev);
- const uint32_t *src = (uint32_t *)source->r_ptr;
- const uint32_t *dst = (uint32_t *)sink->w_ptr;
- int channels = dev->params.channels;
- int channel;
- int i;
- double processed;
- int shift = 0;
-
- /* get shift value */
- if (cd->sink_format == SOF_IPC_FRAME_S32_LE)
- shift = 8;
-
- for (i = 0; i < sink->size / sizeof(uint32_t); i += channels) {
- for (channel = 0; channel < channels; channel++) {
- processed = (src[i + channel] << 8) *
- ((double)cd->volume[channel] *
- (double)VOL_SCALE / INT32_MAX);
- assert_int_equal(dst[i + channel],
- ((uint32_t)(processed + 0.5) >> 8) << shift);
- }
- }
-}
-
-static void verify_s32_to_s24_s32(struct comp_dev *dev,
- struct comp_buffer *sink,
- struct comp_buffer *source)
-{
- struct comp_data *cd = comp_get_drvdata(dev);
- const uint32_t *src = (uint32_t *)source->r_ptr;
- const uint32_t *dst = (uint32_t *)sink->w_ptr;
- int channels = dev->params.channels;
- int channel;
- int i;
- double processed;
- int shift = 0;
-
- /* get shift value */
- if (cd->sink_format == SOF_IPC_FRAME_S24_4LE)
- shift = 8;
-
- for (i = 0; i < sink->size / sizeof(uint32_t); i += channels) {
- for (channel = 0; channel < channels; channel++) {
- processed = src[i + channel] *
- ((double)cd->volume[channel] *
- (double)VOL_SCALE / INT32_MAX);
- assert_int_equal(dst[i + channel],
- (uint32_t)(processed + 0.5) >> shift);
- }
- }
-}
-
-static void test_audio_vol(void **state)
-{
- struct vol_test_state *vol_state = *state;
- struct comp_data *cd = comp_get_drvdata(vol_state->dev);
-
- switch (cd->source_format) {
- case SOF_IPC_FRAME_S16_LE:
- fill_source_s16(vol_state);
- break;
- case SOF_IPC_FRAME_S24_4LE:
- case SOF_IPC_FRAME_S32_LE:
- case SOF_IPC_FRAME_FLOAT:
- fill_source_s32(vol_state);
- break;
- }
-
- cd->scale_vol(vol_state->dev, vol_state->sink, vol_state->source);
-
- vol_state->verify(vol_state->dev, vol_state->sink, vol_state->source);
-}
-
-static struct vol_test_parameters parameters[] = {
- { VOL_MAX, 2, 48, 1, SOF_IPC_FRAME_S16_LE, SOF_IPC_FRAME_S16_LE, verify_s16_to_s16 },
- { VOL_MAX / 2, 2, 48, 1, SOF_IPC_FRAME_S16_LE, SOF_IPC_FRAME_S16_LE, verify_s16_to_s16 },
- { VOL_MAX / 3, 2, 48, 1, SOF_IPC_FRAME_S16_LE, SOF_IPC_FRAME_S16_LE, verify_s16_to_s16 },
- { VOL_MAX, 2, 48, 1, SOF_IPC_FRAME_S16_LE, SOF_IPC_FRAME_S24_4LE, verify_s16_to_sX },
- { VOL_MAX / 2, 2, 48, 1, SOF_IPC_FRAME_S16_LE, SOF_IPC_FRAME_S24_4LE, verify_s16_to_sX },
- { VOL_MAX / 3, 2, 48, 1, SOF_IPC_FRAME_S16_LE, SOF_IPC_FRAME_S24_4LE, verify_s16_to_sX },
- { VOL_MAX, 2, 48, 1, SOF_IPC_FRAME_S16_LE, SOF_IPC_FRAME_S32_LE, verify_s16_to_sX },
- { VOL_MAX / 2, 2, 48, 1, SOF_IPC_FRAME_S16_LE, SOF_IPC_FRAME_S32_LE, verify_s16_to_sX },
- { VOL_MAX / 3, 2, 48, 1, SOF_IPC_FRAME_S16_LE, SOF_IPC_FRAME_S32_LE, verify_s16_to_sX },
-
- { VOL_MAX, 2, 48, 1, SOF_IPC_FRAME_S24_4LE, SOF_IPC_FRAME_S16_LE, verify_sX_to_s16 },
- { VOL_MAX / 2, 2, 48, 1, SOF_IPC_FRAME_S24_4LE, SOF_IPC_FRAME_S16_LE, verify_sX_to_s16 },
- { VOL_MAX / 3, 2, 48, 1, SOF_IPC_FRAME_S24_4LE, SOF_IPC_FRAME_S16_LE, verify_sX_to_s16 },
- { VOL_MAX, 2, 48, 1, SOF_IPC_FRAME_S24_4LE, SOF_IPC_FRAME_S24_4LE, verify_s24_to_s24_s32 },
- { VOL_MAX / 2, 2, 48, 1, SOF_IPC_FRAME_S24_4LE, SOF_IPC_FRAME_S24_4LE, verify_s24_to_s24_s32 },
- { VOL_MAX / 3, 2, 48, 1, SOF_IPC_FRAME_S24_4LE, SOF_IPC_FRAME_S24_4LE, verify_s24_to_s24_s32 },
- { VOL_MAX, 2, 48, 1, SOF_IPC_FRAME_S24_4LE, SOF_IPC_FRAME_S32_LE, verify_s24_to_s24_s32 },
- { VOL_MAX / 2, 2, 48, 1, SOF_IPC_FRAME_S24_4LE, SOF_IPC_FRAME_S32_LE, verify_s24_to_s24_s32 },
- { VOL_MAX / 3, 2, 48, 1, SOF_IPC_FRAME_S24_4LE, SOF_IPC_FRAME_S32_LE, verify_s24_to_s24_s32 },
-
- { VOL_MAX, 2, 48, 1, SOF_IPC_FRAME_S32_LE, SOF_IPC_FRAME_S16_LE, verify_sX_to_s16 },
- { VOL_MAX / 2, 2, 48, 1, SOF_IPC_FRAME_S32_LE, SOF_IPC_FRAME_S16_LE, verify_sX_to_s16 },
- { VOL_MAX / 3, 2, 48, 1, SOF_IPC_FRAME_S32_LE, SOF_IPC_FRAME_S16_LE, verify_sX_to_s16 },
- { VOL_MAX, 2, 48, 1, SOF_IPC_FRAME_S32_LE, SOF_IPC_FRAME_S24_4LE, verify_s32_to_s24_s32 },
- { VOL_MAX / 2, 2, 48, 1, SOF_IPC_FRAME_S32_LE, SOF_IPC_FRAME_S24_4LE, verify_s32_to_s24_s32 },
- { VOL_MAX / 3, 2, 48, 1, SOF_IPC_FRAME_S32_LE, SOF_IPC_FRAME_S24_4LE, verify_s32_to_s24_s32 },
- { VOL_MAX, 2, 48, 1, SOF_IPC_FRAME_S32_LE, SOF_IPC_FRAME_S32_LE, verify_s32_to_s24_s32 },
- { VOL_MAX / 2, 2, 48, 1, SOF_IPC_FRAME_S32_LE, SOF_IPC_FRAME_S32_LE, verify_s32_to_s24_s32 },
- { VOL_MAX / 3, 2, 48, 1, SOF_IPC_FRAME_S32_LE, SOF_IPC_FRAME_S32_LE, verify_s32_to_s24_s32 },
-};
-
-int main(void)
-{
- int i;
-
- struct CMUnitTest tests[ARRAY_SIZE(parameters)];
-
- for (i = 0; i < ARRAY_SIZE(parameters); i++) {
- tests[i].name = "test_audio_vol";
- tests[i].test_func = test_audio_vol;
- tests[i].setup_func = setup;
- tests[i].teardown_func = teardown;
- tests[i].initial_state = ¶meters[i];
- }
-
- cmocka_set_message_output(CM_OUTPUT_TAP);
-
- return cmocka_run_group_tests(tests, NULL, NULL);
-}
diff --git a/test/cmocka/src/lib/alloc/alloc.c b/test/cmocka/src/lib/alloc/alloc.c
deleted file mode 100644
index 4f004d8..0000000
--- a/test/cmocka/src/lib/alloc/alloc.c
+++ /dev/null
@@ -1,330 +0,0 @@
-/*
- * Copyright (c) 2018, Intel Corporation
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- * * Redistributions of source code must retain the above copyright
- * notice, this list of conditions and the following disclaimer.
- * * Redistributions in binary form must reproduce the above copyright
- * notice, this list of conditions and the following disclaimer in the
- * documentation and/or other materials provided with the distribution.
- * * Neither the name of the Intel Corporation nor the
- * names of its contributors may be used to endorse or promote products
- * derived from this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
- * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
- * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
- * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
- * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
- * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
- * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
- * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
- * POSSIBILITY OF SUCH DAMAGE.
- *
- * Author: Slawomir Blauciak <slawomir.blauciak@linux.intel.com>
- */
-
-#include <stdint.h>
-#include <stdarg.h>
-#include <stddef.h>
-#include <setjmp.h>
-#include <cmocka.h>
-
-#include <sof/sof.h>
-#include <sof/alloc.h>
-
-static struct sof *sof;
-
-enum test_type {
- TEST_BULK = 0,
- TEST_ZERO,
- TEST_IMMEDIATE_FREE
-};
-
-struct test_case {
- size_t alloc_size;
- int alloc_zone;
- uint32_t alloc_caps;
- uint16_t alloc_num;
- enum test_type type;
- const char *name;
-};
-
-#define TEST_CASE(bytes, zone, caps, num, type, name_base) \
- {(bytes), (zone), (caps), (num), (type), \
- ("test_lib_alloc_" name_base "__" #zone "__" #bytes "x" #num)}
-
-static struct test_case test_cases[] = {
- /*
- * rmalloc tests
- */
-
- TEST_CASE(4, RZONE_SYS, SOF_MEM_CAPS_RAM, 1024, TEST_IMMEDIATE_FREE,
- "rmalloc"),
-
- TEST_CASE(1, RZONE_SYS, SOF_MEM_CAPS_RAM, 2, TEST_BULK, "rmalloc"),
- TEST_CASE(4, RZONE_SYS, SOF_MEM_CAPS_RAM, 2, TEST_BULK, "rmalloc"),
- TEST_CASE(256, RZONE_SYS, SOF_MEM_CAPS_RAM, 2, TEST_BULK, "rmalloc"),
-
- TEST_CASE(1, RZONE_SYS, SOF_MEM_CAPS_RAM, 4, TEST_BULK, "rmalloc"),
- TEST_CASE(4, RZONE_SYS, SOF_MEM_CAPS_RAM, 4, TEST_BULK, "rmalloc"),
- TEST_CASE(256, RZONE_SYS, SOF_MEM_CAPS_RAM, 4, TEST_BULK, "rmalloc"),
-
- TEST_CASE(1, RZONE_SYS, SOF_MEM_CAPS_RAM, 8, TEST_BULK, "rmalloc"),
- TEST_CASE(4, RZONE_SYS, SOF_MEM_CAPS_RAM, 8, TEST_BULK, "rmalloc"),
- TEST_CASE(256, RZONE_SYS, SOF_MEM_CAPS_RAM, 8, TEST_BULK, "rmalloc"),
-
- TEST_CASE(16, RZONE_SYS, SOF_MEM_CAPS_RAM, 128, TEST_BULK,
- "rmalloc"),
- TEST_CASE(4, RZONE_SYS, SOF_MEM_CAPS_RAM, 256, TEST_BULK,
- "rmalloc"),
-
- TEST_CASE(1, RZONE_RUNTIME, SOF_MEM_CAPS_RAM, 2, TEST_BULK,
- "rmalloc"),
- TEST_CASE(4, RZONE_RUNTIME, SOF_MEM_CAPS_RAM, 2, TEST_BULK,
- "rmalloc"),
- TEST_CASE(256, RZONE_RUNTIME, SOF_MEM_CAPS_RAM, 2, TEST_BULK,
- "rmalloc"),
-
- TEST_CASE(1, RZONE_RUNTIME, SOF_MEM_CAPS_RAM, 4, TEST_BULK,
- "rmalloc"),
- TEST_CASE(4, RZONE_RUNTIME, SOF_MEM_CAPS_RAM, 4, TEST_BULK,
- "rmalloc"),
- TEST_CASE(256, RZONE_RUNTIME, SOF_MEM_CAPS_RAM, 4, TEST_BULK,
- "rmalloc"),
-
- TEST_CASE(1, RZONE_RUNTIME, SOF_MEM_CAPS_RAM, 8, TEST_BULK,
- "rmalloc"),
- TEST_CASE(4, RZONE_RUNTIME, SOF_MEM_CAPS_RAM, 8, TEST_BULK,
- "rmalloc"),
- TEST_CASE(256, RZONE_RUNTIME, SOF_MEM_CAPS_RAM, 8, TEST_BULK,
- "rmalloc"),
-
- TEST_CASE(16, RZONE_RUNTIME, SOF_MEM_CAPS_RAM, 128, TEST_BULK,
- "rmalloc"),
- TEST_CASE(4, RZONE_RUNTIME, SOF_MEM_CAPS_RAM, 256, TEST_BULK,
- "rmalloc"),
-
- TEST_CASE(1, RZONE_RUNTIME, SOF_MEM_CAPS_RAM | SOF_MEM_CAPS_DMA, 2,
- TEST_BULK, "rmalloc_dma"),
- TEST_CASE(4, RZONE_RUNTIME, SOF_MEM_CAPS_RAM | SOF_MEM_CAPS_DMA, 2,
- TEST_BULK, "rmalloc_dma"),
- TEST_CASE(256, RZONE_RUNTIME, SOF_MEM_CAPS_RAM | SOF_MEM_CAPS_DMA, 2,
- TEST_BULK, "rmalloc_dma"),
-
- /*
- * rzalloc tests
- */
-
- TEST_CASE(1, RZONE_SYS, SOF_MEM_CAPS_RAM, 2, TEST_ZERO, "rzalloc"),
- TEST_CASE(4, RZONE_SYS, SOF_MEM_CAPS_RAM, 2, TEST_ZERO, "rzalloc"),
- TEST_CASE(256, RZONE_SYS, SOF_MEM_CAPS_RAM, 2, TEST_ZERO, "rzalloc"),
-
- TEST_CASE(1, RZONE_SYS, SOF_MEM_CAPS_RAM, 4, TEST_ZERO, "rzalloc"),
- TEST_CASE(4, RZONE_SYS, SOF_MEM_CAPS_RAM, 4, TEST_ZERO, "rzalloc"),
- TEST_CASE(256, RZONE_SYS, SOF_MEM_CAPS_RAM, 4, TEST_ZERO, "rzalloc"),
-
- TEST_CASE(1, RZONE_SYS, SOF_MEM_CAPS_RAM, 8, TEST_ZERO, "rzalloc"),
- TEST_CASE(4, RZONE_SYS, SOF_MEM_CAPS_RAM, 8, TEST_ZERO, "rzalloc"),
- TEST_CASE(256, RZONE_SYS, SOF_MEM_CAPS_RAM, 8, TEST_ZERO, "rzalloc"),
-
- TEST_CASE(16, RZONE_SYS, SOF_MEM_CAPS_RAM, 128, TEST_ZERO, "rzalloc"),
- TEST_CASE(4, RZONE_SYS, SOF_MEM_CAPS_RAM, 256, TEST_ZERO, "rzalloc"),
-
- TEST_CASE(1, RZONE_RUNTIME, SOF_MEM_CAPS_RAM, 2, TEST_ZERO,
- "rzalloc"),
- TEST_CASE(4, RZONE_RUNTIME, SOF_MEM_CAPS_RAM, 2, TEST_ZERO,
- "rzalloc"),
- TEST_CASE(256, RZONE_RUNTIME, SOF_MEM_CAPS_RAM, 2, TEST_ZERO,
- "rzalloc"),
-
- TEST_CASE(1, RZONE_RUNTIME, SOF_MEM_CAPS_RAM, 4, TEST_ZERO,
- "rzalloc"),
- TEST_CASE(4, RZONE_RUNTIME, SOF_MEM_CAPS_RAM, 4, TEST_ZERO,
- "rzalloc"),
- TEST_CASE(256, RZONE_RUNTIME, SOF_MEM_CAPS_RAM, 4, TEST_ZERO,
- "rzalloc"),
-
- TEST_CASE(1, RZONE_RUNTIME, SOF_MEM_CAPS_RAM, 8, TEST_ZERO,
- "rzalloc"),
- TEST_CASE(4, RZONE_RUNTIME, SOF_MEM_CAPS_RAM, 8, TEST_ZERO,
- "rzalloc"),
- TEST_CASE(256, RZONE_RUNTIME, SOF_MEM_CAPS_RAM, 8, TEST_ZERO,
- "rzalloc"),
-
- TEST_CASE(16, RZONE_RUNTIME, SOF_MEM_CAPS_RAM, 128, TEST_ZERO,
- "rzalloc"),
- TEST_CASE(4, RZONE_RUNTIME, SOF_MEM_CAPS_RAM, 512, TEST_ZERO,
- "rzalloc"),
-
- TEST_CASE(1, RZONE_RUNTIME, SOF_MEM_CAPS_RAM | SOF_MEM_CAPS_DMA, 2,
- TEST_ZERO, "rzalloc_dma"),
- TEST_CASE(4, RZONE_RUNTIME, SOF_MEM_CAPS_RAM | SOF_MEM_CAPS_DMA, 2,
- TEST_ZERO, "rzalloc_dma"),
- TEST_CASE(256, RZONE_RUNTIME, SOF_MEM_CAPS_RAM | SOF_MEM_CAPS_DMA, 2,
- TEST_ZERO, "rzalloc_dma"),
-
- /*
- * rballoc tests
- */
-
- TEST_CASE(4, RZONE_BUFFER, SOF_MEM_CAPS_RAM, 1024,
- TEST_IMMEDIATE_FREE, "rballoc"),
-
- TEST_CASE(1, RZONE_BUFFER, SOF_MEM_CAPS_RAM, 2, TEST_BULK,
- "rballoc"),
- TEST_CASE(4, RZONE_BUFFER, SOF_MEM_CAPS_RAM, 2, TEST_BULK,
- "rballoc"),
- TEST_CASE(256, RZONE_BUFFER, SOF_MEM_CAPS_RAM, 2, TEST_BULK,
- "rballoc"),
-
- TEST_CASE(1, RZONE_BUFFER, SOF_MEM_CAPS_RAM, 4, TEST_BULK,
- "rballoc"),
- TEST_CASE(4, RZONE_BUFFER, SOF_MEM_CAPS_RAM, 4, TEST_BULK,
- "rballoc"),
- TEST_CASE(256, RZONE_BUFFER, SOF_MEM_CAPS_RAM, 4, TEST_BULK,
- "rballoc"),
-
- TEST_CASE(1, RZONE_BUFFER, SOF_MEM_CAPS_RAM, 8, TEST_BULK,
- "rballoc"),
- TEST_CASE(4, RZONE_BUFFER, SOF_MEM_CAPS_RAM, 8, TEST_BULK,
- "rballoc"),
- TEST_CASE(256, RZONE_BUFFER, SOF_MEM_CAPS_RAM, 8, TEST_BULK,
- "rballoc"),
-
- TEST_CASE(16, RZONE_BUFFER, SOF_MEM_CAPS_RAM, 64, TEST_BULK,
- "rballoc"),
- TEST_CASE(4, RZONE_BUFFER, SOF_MEM_CAPS_RAM, 64, TEST_BULK,
- "rballoc"),
-
- TEST_CASE(1, RZONE_BUFFER, SOF_MEM_CAPS_RAM | SOF_MEM_CAPS_DMA, 2,
- TEST_BULK, "rballoc_dma"),
- TEST_CASE(4, RZONE_BUFFER, SOF_MEM_CAPS_RAM | SOF_MEM_CAPS_DMA, 2,
- TEST_BULK, "rballoc_dma"),
- TEST_CASE(256, RZONE_BUFFER, SOF_MEM_CAPS_RAM | SOF_MEM_CAPS_DMA, 2,
- TEST_BULK, "rballoc_dma")
-};
-
-static int setup(void **state)
-{
- sof = malloc(sizeof(struct sof));
- init_heap(sof);
-
- return 0;
-}
-
-static int teardown(void **state)
-{
- free(sof);
-
- return 0;
-}
-
-static void *alloc(struct test_case *tc)
-{
- void *mem;
-
- if (tc->alloc_zone == RZONE_BUFFER)
- mem = rballoc(tc->alloc_zone, tc->alloc_caps, tc->alloc_size);
- else
- mem = rmalloc(tc->alloc_zone, tc->alloc_caps, tc->alloc_size);
-
- return mem;
-}
-
-static void test_lib_alloc_bulk_free(struct test_case *tc)
-{
- void **all_mem = malloc(sizeof(void *) * tc->alloc_num);
- int i;
-
- for (i = 0; i < tc->alloc_num; ++i) {
- void *mem = alloc(tc);
-
- assert_non_null(mem);
- all_mem[i] = mem;
- }
-
- for (i = 0; i < tc->alloc_num; ++i)
- rfree(all_mem[i]);
-
- rfree(all_mem);
-}
-
-static void test_lib_alloc_immediate_free(struct test_case *tc)
-{
- int i;
-
- for (i = 0; i < tc->alloc_num; ++i) {
- void *mem = alloc(tc);
-
- assert_non_null(mem);
- rfree(mem);
- }
-}
-
-static void test_lib_alloc_zero(struct test_case *tc)
-{
- void **all_mem = malloc(sizeof(void *) * tc->alloc_num);
- int i;
-
- for (i = 0; i < tc->alloc_num; ++i) {
- char *mem = rzalloc(tc->alloc_zone, tc->alloc_caps,
- tc->alloc_size);
- int j;
-
- assert_non_null(mem);
- all_mem[i] = mem;
-
- for (j = 0; j < tc->alloc_size; ++j)
- assert_int_equal(mem[j], 0);
- }
-
- for (i = 0; i < tc->alloc_num; ++i)
- rfree(all_mem[i]);
-
- rfree(all_mem);
-}
-
-static void test_lib_alloc(void **state)
-{
- struct test_case *tc = *((struct test_case **)state);
-
- switch (tc->type) {
- case TEST_BULK:
- test_lib_alloc_bulk_free(tc);
- break;
-
- case TEST_ZERO:
- test_lib_alloc_zero(tc);
- break;
-
- case TEST_IMMEDIATE_FREE:
- test_lib_alloc_immediate_free(tc);
- break;
- }
-}
-
-int main(void)
-{
- struct CMUnitTest tests[ARRAY_SIZE(test_cases)];
-
- int i;
-
- for (i = 0; i < ARRAY_SIZE(test_cases); ++i) {
- struct CMUnitTest *t = &tests[i];
-
- t->name = test_cases[i].name;
- t->test_func = test_lib_alloc;
- t->initial_state = &test_cases[i];
- t->setup_func = NULL;
- t->teardown_func = NULL;
- }
-
- cmocka_set_message_output(CM_OUTPUT_TAP);
-
- return cmocka_run_group_tests(tests, setup, teardown);
-}
diff --git a/test/cmocka/src/lib/alloc/mock.c b/test/cmocka/src/lib/alloc/mock.c
deleted file mode 100644
index 1fd882b..0000000
--- a/test/cmocka/src/lib/alloc/mock.c
+++ /dev/null
@@ -1,57 +0,0 @@
-/*
- * Copyright (c) 2018, Intel Corporation
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- * * Redistributions of source code must retain the above copyright
- * notice, this list of conditions and the following disclaimer.
- * * Redistributions in binary form must reproduce the above copyright
- * notice, this list of conditions and the following disclaimer in the
- * documentation and/or other materials provided with the distribution.
- * * Neither the name of the Intel Corporation nor the
- * names of its contributors may be used to endorse or promote products
- * derived from this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
- * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
- * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
- * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
- * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
- * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
- * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
- * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
- * POSSIBILITY OF SUCH DAMAGE.
- *
- * Author: Slawomir Blauciak <slawomir.blauciak@linux.intel.com>
- * Janusz Jankowski <janusz.jankowski@linux.intel.com>
- */
-
-#include <stdint.h>
-
-#include <sof/alloc.h>
-
-struct dma_copy;
-struct dma_sg_config;
-
-int dma_copy_from_host(struct dma_copy *dc, struct dma_sg_config *host_sg,
- int32_t host_offset, void *local_ptr, int32_t size)
-{
- return 0;
-}
-
-int dma_copy_to_host(struct dma_copy *dc, struct dma_sg_config *host_sg,
- int32_t host_offset, void *local_ptr, int32_t size)
-{
- return 0;
-}
-
-void _trace_event_mbox_atomic(uint32_t e)
-{
-}
-
-void trace_flush(void)
-{
-}
diff --git a/test/cmocka/src/lib/lib/bzero.c b/test/cmocka/src/lib/lib/bzero.c
deleted file mode 100644
index e1ab000..0000000
--- a/test/cmocka/src/lib/lib/bzero.c
+++ /dev/null
@@ -1,200 +0,0 @@
-/*
- * Copyright (c) 2018, Intel Corporation
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- * * Redistributions of source code must retain the above copyright
- * notice, this list of conditions and the following disclaimer.
- * * Redistributions in binary form must reproduce the above copyright
- * notice, this list of conditions and the following disclaimer in the
- * documentation and/or other materials provided with the distribution.
- * * Neither the name of the Intel Corporation nor the
- * names of its contributors may be used to endorse or promote products
- * derived from this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
- * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
- * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
- * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
- * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
- * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
- * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
- * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
- * POSSIBILITY OF SUCH DAMAGE.
- *
- * Author: Michal Jerzy Wierzbicki <michalx.wierzbicki@linux.intel.com>
- */
-
-#include <sof/alloc.h>
-
-#include <stdarg.h>
-#include <setjmp.h>
-#include <cmocka.h>
-
-struct test_data_t {
- size_t len;
- char str[0];
-};
-
-struct test_data_zero_middle_t {
- int beg;
- int end;
- int len;
-};
-
-static struct test_data_t *test_data;
-static struct test_data_zero_middle_t *test_data_zero_middle;
-static const char default_char = 'a';
-
-static void reset_test_arr(void)
-{
- int i;
-
- for (i = 0; i < test_data->len-1; ++i)
- test_data->str[i] = default_char;
- test_data->str[test_data->len] = 0;
-}
-
-static int setup(void **state)
-{
- const int len = 6;
-
- test_data = malloc(sizeof(struct test_data_t)
- + len * sizeof(test_data[0]));
- test_data->len = len;
-
- const int zero_beg = 2;
- const int zero_end = 4;
- // aa000aa... - pattern of zeroing
-
- test_data_zero_middle = malloc(sizeof(struct test_data_zero_middle_t));
- test_data_zero_middle->beg = zero_beg;
- test_data_zero_middle->end = zero_end;
- test_data_zero_middle->len = zero_end - zero_beg;
-
- return 0;
-}
-
-static int teardown(void **state)
-{
- free(test_data);
-
- return 0;
-}
-
-static int check_arr(char *arr, size_t n, char should_be)
-{
- size_t i;
-
- for (i = 0; i < n; ++i)
- if (arr[i] != should_be)
- return i;
- return -1;
-}
-
-static int check_test_arr(char should_be)
-{
- return check_arr(test_data->str, test_data->len-1, should_be);
-}
-
-static int check_test_arr_with_offset(
- int offset_beg, int offset_end, char should_be)
-{
- return check_arr(
- test_data->str+offset_beg,
- test_data->len+offset_end-1,
- should_be
- );
-}
-
-/* Tests*/
-static void test_lib_lib_bzero_check_test_arr(void **state)
-{
- reset_test_arr();
-
- (void) state;
-
- assert_int_equal(check_test_arr(default_char), -1);
-}
-
-static void test_lib_lib_bzero_check_test_arr_with_offset(void **state)
-{
- const int it = 3;
-
- reset_test_arr();
- test_data->str[it] = default_char+1;
-
- (void) state;
-
- assert_int_equal(check_test_arr(default_char), it);
-}
-
-static void test_lib_lib_bzero_char_zero_none(void **state)
-{
- reset_test_arr();
-
- (void) state;
-
- bzero(test_data->str, 0);
- assert_int_equal(check_test_arr(default_char), -1);
-}
-
-static void test_lib_lib_bzero_char_zero_all(void **state)
-{
- reset_test_arr();
-
- (void) state;
-
- bzero(test_data->str, test_data->len);
- assert_int_equal(check_test_arr(0), -1);
-}
-
-static void test_lib_lib_bzero_char_zero_middle_beg(void **state)
-{
- reset_test_arr();
-
- (void) state;
-
- bzero(test_data->str + test_data_zero_middle->beg,
- test_data_zero_middle->len);
- assert_int_equal(check_test_arr(default_char),
- test_data_zero_middle->beg);
-}
-
-static void test_lib_lib_bzero_char_zero_middle_mid(void **state)
-{
- (void) state;
-
- assert_int_equal(check_test_arr_with_offset(
- test_data_zero_middle->beg, -test_data_zero_middle->beg,
- 0), test_data_zero_middle->len);
-}
-
-static void test_lib_lib_bzero_char_zero_middle_end(void **state)
-{
- (void) state;
-
- assert_int_equal(check_test_arr_with_offset(
- test_data_zero_middle->end, -test_data_zero_middle->end,
- default_char), -1);
-}
-
-int main(void)
-{
- const struct CMUnitTest tests[] = {
- cmocka_unit_test(test_lib_lib_bzero_check_test_arr),
- cmocka_unit_test(test_lib_lib_bzero_check_test_arr_with_offset),
- cmocka_unit_test(test_lib_lib_bzero_char_zero_none),
- cmocka_unit_test(test_lib_lib_bzero_char_zero_all),
- cmocka_unit_test(test_lib_lib_bzero_char_zero_middle_beg),
- cmocka_unit_test(test_lib_lib_bzero_char_zero_middle_mid),
- cmocka_unit_test(test_lib_lib_bzero_char_zero_middle_end),
- };
-
- cmocka_set_message_output(CM_OUTPUT_TAP);
-
- return cmocka_run_group_tests(tests, setup, teardown);
-}
diff --git a/test/cmocka/src/lib/lib/rstrcmp.c b/test/cmocka/src/lib/lib/rstrcmp.c
deleted file mode 100644
index 267c5bb..0000000
--- a/test/cmocka/src/lib/lib/rstrcmp.c
+++ /dev/null
@@ -1,245 +0,0 @@
-/*
- * Copyright (c) 2018, Intel Corporation
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- * * Redistributions of source code must retain the above copyright
- * notice, this list of conditions and the following disclaimer.
- * * Redistributions in binary form must reproduce the above copyright
- * notice, this list of conditions and the following disclaimer in the
- * documentation and/or other materials provided with the distribution.
- * * Neither the name of the Intel Corporation nor the
- * names of its contributors may be used to endorse or promote products
- * derived from this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
- * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
- * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
- * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
- * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
- * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
- * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
- * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
- * POSSIBILITY OF SUCH DAMAGE.
- *
- * Author: Michal Jerzy Wierzbicki <michalx.wierzbicki@linux.intel.com>
- */
-
-#include <sof/alloc.h>
-
-#include <stdarg.h>
-#include <setjmp.h>
-#include <cmocka.h>
-
-static void test_lib_lib_rstrcmp_for_a_and_a_equals_0(void **state)
-{
- int r;
- const char *str1 = "a";
- const char *str2 = "a";
-
- (void) state;
-
- r = rstrcmp(str1, str2);
- assert_int_equal(r, 0);
-}
-
-static void test_lib_lib_rstrcmp_for_a_and_b_is_negative(void **state)
-{
- int r;
- const char *str1 = "a";
- const char *str2 = "b";
-
- (void) state;
-
- r = rstrcmp(str1, str2);
- assert_true(r < 0);
-}
-
-static void test_lib_lib_rstrcmp_for_b_and_a_is_positive(void **state)
-{
- int r;
- const char *str1 = "b";
- const char *str2 = "a";
-
- (void) state;
-
- r = rstrcmp(str1, str2);
- assert_true(r > 0);
-}
-
-static void test_lib_lib_rstrcmp_for_empty_and_null_str_equals_0(void **state)
-{
- int r;
- const char *str1 = "";
- const char *str2 = "\0";
-
- (void) state;
-
- r = rstrcmp(str1, str2);
- assert_int_equal(r, 0);
-}
-
-static void test_lib_lib_rstrcmp_for_abc_and_abcd_is_negative(void **state)
-{
- int r;
- const char *str1 = "abc";
- const char *str2 = "abcd";
-
- (void) state;
-
- r = rstrcmp(str1, str2);
- assert_true(r < 0);
-}
-
-static void test_lib_lib_rstrcmp_for_abcd_and_abc_is_positive(void **state)
-{
- int r;
- const char *str1 = "abcd";
- const char *str2 = "abc";
-
- (void) state;
-
- r = rstrcmp(str1, str2);
-
- assert_true(r > 0);
-}
-
-static void test_lib_lib_rstrcmp_for_abc_and_aBc_is_positive(void **state)
-{
- int r;
- const char *str1 = "abc";
- const char *str2 = "aBc";
-
- (void) state;
-
- r = rstrcmp(str1, str2);
- assert_true(r > 0);
-}
-
-static void test_lib_lib_rstrcmp_for_same_multinull_equals_0(void **state)
-{
- int r;
- const char *str1 = "Lorem\0Ipsum\0";
- const char *str2 = "Lorem\0Ipsum\0";
-
- (void) state;
-
- r = rstrcmp(str1, str2);
- assert_int_equal(r, 0);
-}
-
-static void test_lib_lib_rstrcmp_for_diff_after_null_equals_0(void **state)
-{
- int r;
- const char *str1 = "Lorem\0Ipsum\0";
- const char *str2 = "Lorem\0IPzum\0";
-
- (void) state;
-
- r = rstrcmp(str1, str2);
- assert_int_equal(r, 0);
-}
-
-static void test_lib_lib_rstrcmp_for_verylongstrings_equals_0(void **state)
-{
- int r;
- int i;
- const int size = 2048;
- char str1[size+1];
- char str2[size+1];
-
- for (i = 0; i < size; ++i) {
- str1[i] = 'a';
- str2[i] = 'a';
- }
- str1[size] = 0;
- str2[size] = 0;
-
- (void) state;
-
- r = rstrcmp(str1, str2);
- assert_int_equal(r, 0);
-}
-
-static void test_lib_lib_rstrcmp_for_verylongstrings_is_positive(void **state)
-{
- int r;
- int i;
- const int size = 2048;
- char str1[size+1];
- char str2[size+1];
-
- for (i = 0; i < size-1; ++i) {
- str1[i] = 'a';
- str2[i] = 'a';
- }
- str1[size-1] = 'a';
- str2[size-1] = 'A';
- str1[size] = 0;
- str2[size] = 0;
-
- (void) state;
-
- r = rstrcmp(str1, str2);
- assert_true(r > 0);
-}
-
-static void test_lib_lib_rstrcmp_for_verylongstrings_is_negative(void **state)
-{
- int r;
- int i;
- const int size = 2048;
- char str1[size+1];
- char str2[size+1];
-
- for (i = 0; i < size-1; ++i) {
- str1[i] = 'a';
- str2[i] = 'a';
- }
- str1[size-1] = 'A';
- str2[size-1] = 'a';
- str1[size] = 0;
- str2[size] = 0;
-
- (void) state;
-
- r = rstrcmp(str1, str2);
- assert_true(r < 0);
-}
-
-int main(void)
-{
- const struct CMUnitTest tests[] = {
- cmocka_unit_test(
- test_lib_lib_rstrcmp_for_a_and_a_equals_0),
- cmocka_unit_test(
- test_lib_lib_rstrcmp_for_a_and_b_is_negative),
- cmocka_unit_test(
- test_lib_lib_rstrcmp_for_b_and_a_is_positive),
- cmocka_unit_test(
- test_lib_lib_rstrcmp_for_empty_and_null_str_equals_0),
- cmocka_unit_test(
- test_lib_lib_rstrcmp_for_abc_and_abcd_is_negative),
- cmocka_unit_test(
- test_lib_lib_rstrcmp_for_abcd_and_abc_is_positive),
- cmocka_unit_test(
- test_lib_lib_rstrcmp_for_abc_and_aBc_is_positive),
- cmocka_unit_test(
- test_lib_lib_rstrcmp_for_same_multinull_equals_0),
- cmocka_unit_test(
- test_lib_lib_rstrcmp_for_diff_after_null_equals_0),
- cmocka_unit_test(
- test_lib_lib_rstrcmp_for_verylongstrings_equals_0),
- cmocka_unit_test(
- test_lib_lib_rstrcmp_for_verylongstrings_is_positive),
- cmocka_unit_test(
- test_lib_lib_rstrcmp_for_verylongstrings_is_negative),
- };
-
- cmocka_set_message_output(CM_OUTPUT_TAP);
-
- return cmocka_run_group_tests(tests, NULL, NULL);
-}
diff --git a/test/cmocka/src/list/list_init.c b/test/cmocka/src/list/list_init.c
deleted file mode 100644
index 5bd6f3e..0000000
--- a/test/cmocka/src/list/list_init.c
+++ /dev/null
@@ -1,70 +0,0 @@
-/*
- * Copyright (c) 2018, Intel Corporation
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- * * Redistributions of source code must retain the above copyright
- * notice, this list of conditions and the following disclaimer.
- * * Redistributions in binary form must reproduce the above copyright
- * notice, this list of conditions and the following disclaimer in the
- * documentation and/or other materials provided with the distribution.
- * * Neither the name of the Intel Corporation nor the
- * names of its contributors may be used to endorse or promote products
- * derived from this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
- * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
- * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
- * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
- * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
- * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
- * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
- * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
- * POSSIBILITY OF SUCH DAMAGE.
- *
- * Author: Janusz Jankowski <janusz.jankowski@linux.intel.com>
- */
-
-#include <sof/list.h>
-
-#include <stdarg.h>
-#include <stddef.h>
-#include <setjmp.h>
-#include <cmocka.h>
-
-static void test_list_list_init_prev_equal_to_root(void **state)
-{
- (void) state; /* unused */
-
- struct list_item list = {.prev = NULL, .next = NULL};
-
- list_init(&list);
-
- assert_ptr_equal(&list, list.prev);
-}
-
-static void test_list_list_init_next_equal_to_root(void **state)
-{
- (void) state; /* unused */
-
- struct list_item list = {.prev = NULL, .next = NULL};
-
- list_init(&list);
-
- assert_ptr_equal(&list, list.next);
-}
-
-int main(void)
-{
- const struct CMUnitTest tests[] = {
- cmocka_unit_test(test_list_list_init_prev_equal_to_root),
- cmocka_unit_test(test_list_list_init_next_equal_to_root),
- };
-
- cmocka_set_message_output(CM_OUTPUT_TAP);
-
- return cmocka_run_group_tests(tests, NULL, NULL);
-}
diff --git a/test/cmocka/src/list/list_is_empty.c b/test/cmocka/src/list/list_is_empty.c
deleted file mode 100644
index 95aff3e..0000000
--- a/test/cmocka/src/list/list_is_empty.c
+++ /dev/null
@@ -1,74 +0,0 @@
-/*
- * Copyright (c) 2018, Intel Corporation
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- * * Redistributions of source code must retain the above copyright
- * notice, this list of conditions and the following disclaimer.
- * * Redistributions in binary form must reproduce the above copyright
- * notice, this list of conditions and the following disclaimer in the
- * documentation and/or other materials provided with the distribution.
- * * Neither the name of the Intel Corporation nor the
- * names of its contributors may be used to endorse or promote products
- * derived from this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
- * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
- * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
- * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
- * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
- * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
- * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
- * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
- * POSSIBILITY OF SUCH DAMAGE.
- *
- * Author: Janusz Jankowski <janusz.jankowski@linux.intel.com>
- */
-
-#include <sof/list.h>
-
-#include <stdlib.h>
-#include <stdarg.h>
-#include <stddef.h>
-#include <setjmp.h>
-#include <cmocka.h>
-
-static void test_list_list_is_empty_when_empty_then_true(void **state)
-{
- (void) state; /* unused */
-
- struct list_item list;
-
- list_init(&list);
-
- assert_true(list_is_empty(&list));
-}
-
-static void test_list_list_is_empty_when_not_empty_then_false(void **state)
-{
- (void) state; /* unused */
-
- struct list_item list, item;
-
- list_init(&list);
- list_init(&item);
-
- list_item_append(&item, &list);
-
- assert_false(list_is_empty(&list));
-}
-
-int main(void)
-{
- const struct CMUnitTest tests[] = {
- cmocka_unit_test(test_list_list_is_empty_when_empty_then_true),
- cmocka_unit_test(test_list_list_is_empty_when_not_empty_then_false),
- };
-
- cmocka_set_message_output(CM_OUTPUT_TAP);
-
- return cmocka_run_group_tests(tests, NULL, NULL);
-}
diff --git a/test/cmocka/src/list/list_item.c b/test/cmocka/src/list/list_item.c
deleted file mode 100644
index 5a62f24..0000000
--- a/test/cmocka/src/list/list_item.c
+++ /dev/null
@@ -1,68 +0,0 @@
-/*
- * Copyright (c) 2018, Intel Corporation
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- * * Redistributions of source code must retain the above copyright
- * notice, this list of conditions and the following disclaimer.
- * * Redistributions in binary form must reproduce the above copyright
- * notice, this list of conditions and the following disclaimer in the
- * documentation and/or other materials provided with the distribution.
- * * Neither the name of the Intel Corporation nor the
- * names of its contributors may be used to endorse or promote products
- * derived from this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
- * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
- * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
- * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
- * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
- * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
- * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
- * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
- * POSSIBILITY OF SUCH DAMAGE.
- *
- * Author: Janusz Jankowski <janusz.jankowski@linux.intel.com>
- */
-
-#include <sof/list.h>
-
-#include <stdlib.h>
-#include <stdarg.h>
-#include <stddef.h>
-#include <setjmp.h>
-#include <cmocka.h>
-
-struct test_list_container {
- void *field1;
- struct list_item list;
- void *field2;
-};
-
-static void test_list_list_item_when_valid_offset_then_ptr_equal(void **state)
-{
- (void) state; /* unused */
-
- struct test_list_container container;
-
- list_init(&(container.list));
-
- struct test_list_container *result_container = list_item(
- &(container.list), struct test_list_container, list);
-
- assert_ptr_equal(result_container, &container);
-}
-
-int main(void)
-{
- const struct CMUnitTest tests[] = {
- cmocka_unit_test(test_list_list_item_when_valid_offset_then_ptr_equal),
- };
-
- cmocka_set_message_output(CM_OUTPUT_TAP);
-
- return cmocka_run_group_tests(tests, NULL, NULL);
-}
diff --git a/test/cmocka/src/list/list_item_append.c b/test/cmocka/src/list/list_item_append.c
deleted file mode 100644
index 4fd4c66..0000000
--- a/test/cmocka/src/list/list_item_append.c
+++ /dev/null
@@ -1,148 +0,0 @@
-/*
- * Copyright (c) 2018, Intel Corporation
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- * * Redistributions of source code must retain the above copyright
- * notice, this list of conditions and the following disclaimer.
- * * Redistributions in binary form must reproduce the above copyright
- * notice, this list of conditions and the following disclaimer in the
- * documentation and/or other materials provided with the distribution.
- * * Neither the name of the Intel Corporation nor the
- * names of its contributors may be used to endorse or promote products
- * derived from this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
- * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
- * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
- * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
- * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
- * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
- * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
- * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
- * POSSIBILITY OF SUCH DAMAGE.
- *
- * Author: Janusz Jankowski <janusz.jankowski@linux.intel.com>
- */
-
-#include <sof/list.h>
-
-#include <stdlib.h>
-#include <stdarg.h>
-#include <stddef.h>
-#include <setjmp.h>
-#include <cmocka.h>
-
-struct test_data {
- struct list_item *head;
- struct list_item *tail_minus_1;
- struct list_item *tail;
-};
-
-static int setup(void **state)
-{
- struct test_data *data = malloc(sizeof(struct test_data));
-
- if (data == NULL)
- return -1;
-
- data->head = malloc(sizeof(struct list_item));
- data->tail_minus_1 = malloc(sizeof(struct list_item));
- data->tail = malloc(sizeof(struct list_item));
-
- if (data->head == NULL
- || data->tail_minus_1 == NULL
- || data->tail == NULL) {
- free(data->head);
- free(data->tail_minus_1);
- free(data->tail);
-
- free(data);
-
- return -1;
- }
-
- list_init(data->head);
- list_init(data->tail_minus_1);
- list_init(data->tail);
-
- list_item_append(data->tail_minus_1, data->head);
- list_item_append(data->tail, data->head);
-
- *state = data;
- return 0;
-}
-
-static int teardown(void **state)
-{
- struct test_data *data = *state;
-
- free(data->head);
- free(data->tail_minus_1);
- free(data->tail);
-
- free(data);
- return 0;
-}
-
-static void test_list_list_item_append_head_prev_is_tail(void **state)
-{
- struct test_data *data = *state;
-
- assert_ptr_equal(data->head->prev, data->tail);
-}
-
-static void test_list_list_item_append_head_next_is_tail_minus_1(void **state)
-{
- struct test_data *data = *state;
-
- assert_ptr_equal(data->head->next, data->tail_minus_1);
-}
-
-static void test_list_list_item_append_tail_minus_1_prev_is_head(void **state)
-{
- struct test_data *data = *state;
-
- assert_ptr_equal(data->tail_minus_1->prev, data->head);
-}
-
-static void test_list_list_item_append_tail_minus_1_next_is_tail(void **state)
-{
- struct test_data *data = *state;
-
- assert_ptr_equal(data->tail_minus_1->next, data->tail);
-}
-
-static void test_list_list_item_append_tail_prev_is_tail_minus_1(void **state)
-{
- struct test_data *data = *state;
-
- assert_ptr_equal(data->tail->prev, data->tail_minus_1);
-}
-
-static void test_list_list_item_append_tail_next_is_head(void **state)
-{
- struct test_data *data = *state;
-
- assert_ptr_equal(data->tail->next, data->head);
-}
-
-int main(void)
-{
- const struct CMUnitTest tests[] = {
- cmocka_unit_test(test_list_list_item_append_head_prev_is_tail),
- cmocka_unit_test(test_list_list_item_append_head_next_is_tail_minus_1),
- cmocka_unit_test(test_list_list_item_append_tail_minus_1_prev_is_head),
- cmocka_unit_test(test_list_list_item_append_tail_minus_1_next_is_tail),
- cmocka_unit_test(test_list_list_item_append_tail_prev_is_tail_minus_1),
- cmocka_unit_test(test_list_list_item_append_tail_next_is_head),
- };
-
- cmocka_set_message_output(CM_OUTPUT_TAP);
-
- return cmocka_run_group_tests(tests, setup, teardown);
-}
-
diff --git a/test/cmocka/src/list/list_item_del.c b/test/cmocka/src/list/list_item_del.c
deleted file mode 100644
index dfe6e6d..0000000
--- a/test/cmocka/src/list/list_item_del.c
+++ /dev/null
@@ -1,221 +0,0 @@
-/*
- * Copyright (c) 2018, Intel Corporation
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- * * Redistributions of source code must retain the above copyright
- * notice, this list of conditions and the following disclaimer.
- * * Redistributions in binary form must reproduce the above copyright
- * notice, this list of conditions and the following disclaimer in the
- * documentation and/or other materials provided with the distribution.
- * * Neither the name of the Intel Corporation nor the
- * names of its contributors may be used to endorse or promote products
- * derived from this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
- * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
- * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
- * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
- * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
- * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
- * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
- * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
- * POSSIBILITY OF SUCH DAMAGE.
- *
- * Author: Janusz Jankowski <janusz.jankowski@linux.intel.com>
- */
-
-#include <sof/list.h>
-
-#include <stdlib.h>
-#include <stdarg.h>
-#include <stddef.h>
-#include <setjmp.h>
-#include <cmocka.h>
-
-struct test_data {
- struct list_item *head;
- struct list_item *tail_minus_1;
- struct list_item *tail;
-};
-
-static int setup(void **state)
-{
- struct test_data *data = malloc(sizeof(struct test_data));
-
- if (data == NULL)
- return -1;
-
- data->head = malloc(sizeof(struct list_item));
- data->tail_minus_1 = malloc(sizeof(struct list_item));
- data->tail = malloc(sizeof(struct list_item));
-
- if (data->head == NULL
- || data->tail_minus_1 == NULL
- || data->tail == NULL) {
- free(data->head);
- free(data->tail_minus_1);
- free(data->tail);
-
- free(data);
-
- return -1;
- }
-
- list_init(data->head);
- list_init(data->tail_minus_1);
- list_init(data->tail);
-
- list_item_append(data->tail_minus_1, data->head);
- list_item_append(data->tail, data->head);
-
- *state = data;
- return 0;
-}
-
-static int teardown(void **state)
-{
- struct test_data *data = *state;
-
- free(data->head);
- free(data->tail_minus_1);
- free(data->tail);
-
- free(data);
- return 0;
-}
-
-static void test_list_list_item_del_when_delete_head_then_tail_minus_1_prev_is_tail(void **state)
-{
- struct test_data *data = *state;
-
- list_item_del(data->head);
-
- assert_ptr_equal(data->tail_minus_1->prev, data->tail);
-}
-
-static void test_list_list_item_del_when_delete_head_then_tail_minus_1_next_is_tail(void **state)
-{
- struct test_data *data = *state;
-
- list_item_del(data->head);
-
- assert_ptr_equal(data->tail_minus_1->next, data->tail);
-}
-
-static void test_list_list_item_del_when_delete_head_then_tail_prev_is_tail_minus_1(void **state)
-{
- struct test_data *data = *state;
-
- list_item_del(data->head);
-
- assert_ptr_equal(data->tail->prev, data->tail_minus_1);
-}
-
-static void test_list_list_item_del_when_delete_head_then_tail_next_is_tail_minus_1(void **state)
-{
- struct test_data *data = *state;
-
- list_item_del(data->head);
-
- assert_ptr_equal(data->tail->next, data->tail_minus_1);
-}
-
-static void test_list_list_item_del_when_delete_tail_minus_1_then_head_prev_is_tail(void **state)
-{
- struct test_data *data = *state;
-
- list_item_del(data->tail_minus_1);
-
- assert_ptr_equal(data->head->prev, data->tail);
-}
-
-static void test_list_list_item_del_when_delete_tail_minus_1_then_head_next_is_tail(void **state)
-{
- struct test_data *data = *state;
-
- list_item_del(data->tail_minus_1);
-
- assert_ptr_equal(data->head->next, data->tail);
-}
-
-static void test_list_list_item_del_when_delete_tail_minus_1_then_tail_prev_is_head(void **state)
-{
- struct test_data *data = *state;
-
- list_item_del(data->tail_minus_1);
-
- assert_ptr_equal(data->tail->prev, data->head);
-}
-
-static void test_list_list_item_del_when_delete_tail_minus_1_then_tail_next_is_head(void **state)
-{
- struct test_data *data = *state;
-
- list_item_del(data->tail_minus_1);
-
- assert_ptr_equal(data->tail->next, data->head);
-}
-
-static void test_list_list_item_del_when_delete_tail_then_head_prev_is_tail_minus_1(void **state)
-{
- struct test_data *data = *state;
-
- list_item_del(data->tail);
-
- assert_ptr_equal(data->head->prev, data->tail_minus_1);
-}
-
-static void test_list_list_item_del_when_delete_tail_then_head_next_is_tail_minus_1(void **state)
-{
- struct test_data *data = *state;
-
- list_item_del(data->tail);
-
- assert_ptr_equal(data->head->next, data->tail_minus_1);
-}
-
-static void test_list_list_item_del_when_delete_tail_then_tail_minus_1_prev_is_head(void **state)
-{
- struct test_data *data = *state;
-
- list_item_del(data->tail);
-
- assert_ptr_equal(data->tail_minus_1->prev, data->head);
-}
-
-static void test_list_list_item_del_when_delete_tail_then_tail_minus_1_next_is_head(void **state)
-{
- struct test_data *data = *state;
-
- list_item_del(data->tail);
-
- assert_ptr_equal(data->tail_minus_1->next, data->head);
-}
-
-int main(void)
-{
- const struct CMUnitTest tests[] = {
- cmocka_unit_test_setup_teardown(test_list_list_item_del_when_delete_head_then_tail_minus_1_prev_is_tail, setup, teardown),
- cmocka_unit_test_setup_teardown(test_list_list_item_del_when_delete_head_then_tail_minus_1_next_is_tail, setup, teardown),
- cmocka_unit_test_setup_teardown(test_list_list_item_del_when_delete_head_then_tail_prev_is_tail_minus_1, setup, teardown),
- cmocka_unit_test_setup_teardown(test_list_list_item_del_when_delete_head_then_tail_next_is_tail_minus_1, setup, teardown),
-
- cmocka_unit_test_setup_teardown(test_list_list_item_del_when_delete_tail_minus_1_then_head_prev_is_tail, setup, teardown),
- cmocka_unit_test_setup_teardown(test_list_list_item_del_when_delete_tail_minus_1_then_head_next_is_tail, setup, teardown),
- cmocka_unit_test_setup_teardown(test_list_list_item_del_when_delete_tail_minus_1_then_tail_prev_is_head, setup, teardown),
- cmocka_unit_test_setup_teardown(test_list_list_item_del_when_delete_tail_minus_1_then_tail_next_is_head, setup, teardown),
-
- cmocka_unit_test_setup_teardown(test_list_list_item_del_when_delete_tail_then_head_prev_is_tail_minus_1, setup, teardown),
- cmocka_unit_test_setup_teardown(test_list_list_item_del_when_delete_tail_then_head_next_is_tail_minus_1, setup, teardown),
- cmocka_unit_test_setup_teardown(test_list_list_item_del_when_delete_tail_then_tail_minus_1_prev_is_head, setup, teardown),
- cmocka_unit_test_setup_teardown(test_list_list_item_del_when_delete_tail_then_tail_minus_1_next_is_head, setup, teardown),
- };
-
- cmocka_set_message_output(CM_OUTPUT_TAP);
-
- return cmocka_run_group_tests(tests, NULL, NULL);
-}
diff --git a/test/cmocka/src/list/list_item_is_last.c b/test/cmocka/src/list/list_item_is_last.c
deleted file mode 100644
index 2e6bd0f..0000000
--- a/test/cmocka/src/list/list_item_is_last.c
+++ /dev/null
@@ -1,134 +0,0 @@
-/*
- * Copyright (c) 2018, Intel Corporation
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- * * Redistributions of source code must retain the above copyright
- * notice, this list of conditions and the following disclaimer.
- * * Redistributions in binary form must reproduce the above copyright
- * notice, this list of conditions and the following disclaimer in the
- * documentation and/or other materials provided with the distribution.
- * * Neither the name of the Intel Corporation nor the
- * names of its contributors may be used to endorse or promote products
- * derived from this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
- * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
- * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
- * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
- * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
- * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
- * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
- * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
- * POSSIBILITY OF SUCH DAMAGE.
- *
- * Author: Janusz Jankowski <janusz.jankowski@linux.intel.com>
- */
-
-#include <sof/list.h>
-
-#include <stdlib.h>
-#include <stdarg.h>
-#include <stddef.h>
-#include <setjmp.h>
-#include <cmocka.h>
-
-struct test_data {
- struct list_item *head;
- struct list_item *tail_minus_1;
- struct list_item *tail;
-};
-
-static int setup(void **state)
-{
- struct test_data *data = malloc(sizeof(struct test_data));
-
- if (data == NULL)
- return -1;
-
- data->head = malloc(sizeof(struct list_item));
- data->tail_minus_1 = malloc(sizeof(struct list_item));
- data->tail = malloc(sizeof(struct list_item));
-
- if (data->head == NULL
- || data->tail_minus_1 == NULL
- || data->tail == NULL) {
- free(data->head);
- free(data->tail_minus_1);
- free(data->tail);
-
- free(data);
-
- return -1;
- }
-
- list_init(data->head);
- list_init(data->tail_minus_1);
- list_init(data->tail);
-
- list_item_append(data->tail_minus_1, data->head);
- list_item_append(data->tail, data->head);
-
- *state = data;
- return 0;
-}
-
-static int teardown(void **state)
-{
- struct test_data *data = *state;
-
- free(data->head);
- free(data->tail_minus_1);
- free(data->tail);
-
- free(data);
- return 0;
-}
-
-static void test_list_list_item_is_last_when_head_then_false(void **state)
-{
- struct test_data *data = *state;
-
- assert_false(list_item_is_last(data->head, data->head));
-}
-
-static void test_list_list_item_is_last_when_tail_minus_1_then_false(void **state)
-{
- struct test_data *data = *state;
-
- assert_false(list_item_is_last(data->tail_minus_1, data->head));
-}
-
-static void test_list_list_item_is_last_when_tail_then_true(void **state)
-{
- struct test_data *data = *state;
-
- assert_true(list_item_is_last(data->tail, data->head));
-}
-
-static void test_list_list_item_is_last_when_not_in_list_then_false(void **state)
-{
- struct list_item other_list;
- struct test_data *data = *state;
-
- list_init(&other_list);
-
- assert_false(list_item_is_last(&other_list, data->head));
-}
-
-int main(void)
-{
- const struct CMUnitTest tests[] = {
- cmocka_unit_test(test_list_list_item_is_last_when_head_then_false),
- cmocka_unit_test(test_list_list_item_is_last_when_tail_minus_1_then_false),
- cmocka_unit_test(test_list_list_item_is_last_when_tail_then_true),
- cmocka_unit_test(test_list_list_item_is_last_when_not_in_list_then_false),
- };
-
- cmocka_set_message_output(CM_OUTPUT_TAP);
-
- return cmocka_run_group_tests(tests, setup, teardown);
-}
diff --git a/test/cmocka/src/list/list_item_prepend.c b/test/cmocka/src/list/list_item_prepend.c
deleted file mode 100644
index 75c1e76..0000000
--- a/test/cmocka/src/list/list_item_prepend.c
+++ /dev/null
@@ -1,147 +0,0 @@
-/*
- * Copyright (c) 2018, Intel Corporation
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- * * Redistributions of source code must retain the above copyright
- * notice, this list of conditions and the following disclaimer.
- * * Redistributions in binary form must reproduce the above copyright
- * notice, this list of conditions and the following disclaimer in the
- * documentation and/or other materials provided with the distribution.
- * * Neither the name of the Intel Corporation nor the
- * names of its contributors may be used to endorse or promote products
- * derived from this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
- * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
- * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
- * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
- * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
- * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
- * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
- * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
- * POSSIBILITY OF SUCH DAMAGE.
- *
- * Author: Janusz Jankowski <janusz.jankowski@linux.intel.com>
- */
-
-#include <sof/list.h>
-
-#include <stdlib.h>
-#include <stdarg.h>
-#include <stddef.h>
-#include <setjmp.h>
-#include <cmocka.h>
-
-struct test_data {
- struct list_item *head;
- struct list_item *tail_minus_1;
- struct list_item *tail;
-};
-
-static int setup(void **state)
-{
- struct test_data *data = malloc(sizeof(struct test_data));
-
- if (data == NULL)
- return -1;
-
- data->head = malloc(sizeof(struct list_item));
- data->tail_minus_1 = malloc(sizeof(struct list_item));
- data->tail = malloc(sizeof(struct list_item));
-
- if (data->head == NULL
- || data->tail_minus_1 == NULL
- || data->tail == NULL) {
- free(data->head);
- free(data->tail_minus_1);
- free(data->tail);
-
- free(data);
-
- return -1;
- }
-
- list_init(data->head);
- list_init(data->tail_minus_1);
- list_init(data->tail);
-
- list_item_prepend(data->tail, data->head);
- list_item_prepend(data->tail_minus_1, data->head);
-
- *state = data;
- return 0;
-}
-
-static int teardown(void **state)
-{
- struct test_data *data = *state;
-
- free(data->head);
- free(data->tail_minus_1);
- free(data->tail);
-
- free(data);
- return 0;
-}
-
-static void test_list_list_item_prepend_head_prev_is_tail(void **state)
-{
- struct test_data *data = *state;
-
- assert_ptr_equal(data->head->prev, data->tail);
-}
-
-static void test_list_list_item_prepend_head_next_is_tail_minus_1(void **state)
-{
- struct test_data *data = *state;
-
- assert_ptr_equal(data->head->next, data->tail_minus_1);
-}
-
-static void test_list_list_item_prepend_tail_minus_1_prev_is_head(void **state)
-{
- struct test_data *data = *state;
-
- assert_ptr_equal(data->tail_minus_1->prev, data->head);
-}
-
-static void test_list_list_item_prepend_tail_minus_1_next_is_tail(void **state)
-{
- struct test_data *data = *state;
-
- assert_ptr_equal(data->tail_minus_1->next, data->tail);
-}
-
-static void test_list_list_item_prepend_tail_prev_is_tail_minus_1(void **state)
-{
- struct test_data *data = *state;
-
- assert_ptr_equal(data->tail->prev, data->tail_minus_1);
-}
-
-static void test_list_list_item_prepend_tail_next_is_head(void **state)
-{
- struct test_data *data = *state;
-
- assert_ptr_equal(data->tail->next, data->head);
-}
-
-int main(void)
-{
- const struct CMUnitTest tests[] = {
- cmocka_unit_test(test_list_list_item_prepend_head_prev_is_tail),
- cmocka_unit_test(test_list_list_item_prepend_head_next_is_tail_minus_1),
- cmocka_unit_test(test_list_list_item_prepend_tail_minus_1_prev_is_head),
- cmocka_unit_test(test_list_list_item_prepend_tail_minus_1_next_is_tail),
- cmocka_unit_test(test_list_list_item_prepend_tail_prev_is_tail_minus_1),
- cmocka_unit_test(test_list_list_item_prepend_tail_next_is_head),
- };
-
- cmocka_set_message_output(CM_OUTPUT_TAP);
-
- return cmocka_run_group_tests(tests, setup, teardown);
-}
diff --git a/test/cmocka/src/math/numbers/ceil_divide.c b/test/cmocka/src/math/numbers/ceil_divide.c
deleted file mode 100644
index f20514e..0000000
--- a/test/cmocka/src/math/numbers/ceil_divide.c
+++ /dev/null
@@ -1,82 +0,0 @@
-/*
- * Copyright (c) 2018, Intel Corporation
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- * * Redistributions of source code must retain the above copyright
- * notice, this list of conditions and the following disclaimer.
- * * Redistributions in binary form must reproduce the above copyright
- * notice, this list of conditions and the following disclaimer in the
- * documentation and/or other materials provided with the distribution.
- * * Neither the name of the Intel Corporation nor the
- * names of its contributors may be used to endorse or promote products
- * derived from this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
- * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
- * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
- * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
- * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
- * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
- * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
- * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
- * POSSIBILITY OF SUCH DAMAGE.
- *
- * Author: Slawomir Blauciak <slawomir.blauciak@linux.intel.com>
- */
-
-#include <sof/math/numbers.h>
-
-#include <stdio.h>
-#include <stdarg.h>
-#include <stddef.h>
-#include <setjmp.h>
-#include <math.h>
-#include <cmocka.h>
-
-static void test_math_numbers_ceil_divide(void **state)
-{
- (void)state;
-
- int params[8] = {
- -1000,
- 300,
- 123,
- -10,
- 1337,
- -6,
- 999,
- -2
- };
-
- int i, j;
-
- for (i = 0; i < 8; ++i) {
- for (j = 0; j < 8; ++j) {
- int ref = ceilf((float)params[i] / (float)params[j]);
- int r = ceil_divide(params[i], params[j]);
-
- if (r != ref) {
- printf("%s: %d / %d = %d (ref: %d)\n", __func__,
- params[i], params[j], r, ref);
- }
-
- assert_int_equal(r, ref);
- }
- }
-
-}
-
-int main(void)
-{
- const struct CMUnitTest tests[] = {
- cmocka_unit_test(test_math_numbers_ceil_divide)
- };
-
- cmocka_set_message_output(CM_OUTPUT_TAP);
-
- return cmocka_run_group_tests(tests, NULL, NULL);
-}
diff --git a/test/cmocka/src/math/numbers/find_equal_int16.c b/test/cmocka/src/math/numbers/find_equal_int16.c
deleted file mode 100644
index 84e06de..0000000
--- a/test/cmocka/src/math/numbers/find_equal_int16.c
+++ /dev/null
@@ -1,78 +0,0 @@
-/*
- * Copyright (c) 2018, Intel Corporation
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- * * Redistributions of source code must retain the above copyright
- * notice, this list of conditions and the following disclaimer.
- * * Redistributions in binary form must reproduce the above copyright
- * notice, this list of conditions and the following disclaimer in the
- * documentation and/or other materials provided with the distribution.
- * * Neither the name of the Intel Corporation nor the
- * names of its contributors may be used to endorse or promote products
- * derived from this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
- * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
- * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
- * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
- * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
- * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
- * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
- * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
- * POSSIBILITY OF SUCH DAMAGE.
- *
- * Author: Slawomir Blauciak <slawomir.blauciak@linux.intel.com>
- */
-
-#include <sof/math/numbers.h>
-
-#include <stdarg.h>
-#include <stddef.h>
-#include <setjmp.h>
-#include <cmocka.h>
-
-static void test_math_numbers_find_equal_int16_for_5_123_5_10_123_500_123_n_123_equals_1_4_and_6
- (void **state)
-{
- (void)state;
-
- int16_t r[4];
- int16_t vec[] = {5, 123, 5, 10, 123, 500, 123};
- int16_t template[] = {1, 4, 6};
-
- int r_num = find_equal_int16(r, vec, 123, 7, 4);
-
- assert_int_equal(r_num, 3);
- assert_memory_equal(r, template, sizeof(int16_t) * 3);
-}
-
-static void test_math_numbers_find_equal_int16_for_1_2_3_4_5_n_0_equals_nothing
- (void **state)
-{
- (void)state;
-
- int16_t r[4];
- int16_t vec[] = {1, 2, 3, 4, 5};
-
- int r_num = find_equal_int16(r, vec, 0, 5, 4);
-
- assert_int_equal(r_num, 0);
-}
-
-int main(void)
-{
- const struct CMUnitTest tests[] = {
- cmocka_unit_test
- (test_math_numbers_find_equal_int16_for_5_123_5_10_123_500_123_n_123_equals_1_4_and_6),
- cmocka_unit_test
- (test_math_numbers_find_equal_int16_for_1_2_3_4_5_n_0_equals_nothing)
- };
-
- cmocka_set_message_output(CM_OUTPUT_TAP);
-
- return cmocka_run_group_tests(tests, NULL, NULL);
-}
diff --git a/test/cmocka/src/math/numbers/find_max_abs_int32.c b/test/cmocka/src/math/numbers/find_max_abs_int32.c
deleted file mode 100644
index 1a88263..0000000
--- a/test/cmocka/src/math/numbers/find_max_abs_int32.c
+++ /dev/null
@@ -1,72 +0,0 @@
-/*
- * Copyright (c) 2018, Intel Corporation
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- * * Redistributions of source code must retain the above copyright
- * notice, this list of conditions and the following disclaimer.
- * * Redistributions in binary form must reproduce the above copyright
- * notice, this list of conditions and the following disclaimer in the
- * documentation and/or other materials provided with the distribution.
- * * Neither the name of the Intel Corporation nor the
- * names of its contributors may be used to endorse or promote products
- * derived from this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
- * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
- * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
- * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
- * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
- * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
- * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
- * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
- * POSSIBILITY OF SUCH DAMAGE.
- *
- * Author: Slawomir Blauciak <slawomir.blauciak@linux.intel.com>
- */
-
-#include <sof/math/numbers.h>
-
-#include <stdarg.h>
-#include <stddef.h>
-#include <setjmp.h>
-#include <cmocka.h>
-
-static void test_math_numbers_find_max_abs_int32_for_neg100_99_98_50_equals_100
- (void **state)
-{
- (void)state;
-
- int32_t vec[] = {-100, 99, 98, 50};
- int r = find_max_abs_int32(vec, sizeof(vec) / sizeof(int32_t));
-
- assert_int_equal(r, 100);
-}
-
-static void test_math_numbers_find_max_abs_int32_for_neg100_99_98_50_101_equals_101
- (void **state)
-{
- (void)state;
-
- int32_t vec[] = {-100, 99, 98, 50, 101};
- int r = find_max_abs_int32(vec, sizeof(vec) / sizeof(int32_t));
-
- assert_int_equal(r, 101);
-}
-
-int main(void)
-{
- const struct CMUnitTest tests[] = {
- cmocka_unit_test
- (test_math_numbers_find_max_abs_int32_for_neg100_99_98_50_equals_100),
- cmocka_unit_test
- (test_math_numbers_find_max_abs_int32_for_neg100_99_98_50_101_equals_101)
- };
-
- cmocka_set_message_output(CM_OUTPUT_TAP);
-
- return cmocka_run_group_tests(tests, NULL, NULL);
-}
diff --git a/test/cmocka/src/math/numbers/find_min_int16.c b/test/cmocka/src/math/numbers/find_min_int16.c
deleted file mode 100644
index 744ed12..0000000
--- a/test/cmocka/src/math/numbers/find_min_int16.c
+++ /dev/null
@@ -1,71 +0,0 @@
-/*
- * Copyright (c) 2018, Intel Corporation
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- * * Redistributions of source code must retain the above copyright
- * notice, this list of conditions and the following disclaimer.
- * * Redistributions in binary form must reproduce the above copyright
- * notice, this list of conditions and the following disclaimer in the
- * documentation and/or other materials provided with the distribution.
- * * Neither the name of the Intel Corporation nor the
- * names of its contributors may be used to endorse or promote products
- * derived from this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
- * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
- * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
- * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
- * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
- * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
- * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
- * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
- * POSSIBILITY OF SUCH DAMAGE.
- *
- * Author: Slawomir Blauciak <slawomir.blauciak@linux.intel.com>
- */
-
-#include <sof/math/numbers.h>
-
-#include <stdarg.h>
-#include <stddef.h>
-#include <setjmp.h>
-#include <cmocka.h>
-
-static void test_math_numbers_find_min_int16_for_2_equals_2(void **state)
-{
- (void)state;
-
- int16_t vec[] = {2};
- int r = find_min_int16(vec, sizeof(vec) / sizeof(int16_t));
-
- assert_int_equal(r, 2);
-}
-
-static void test_math_numbers_find_min_int16_for_5_2_3_4_1_equals_1
- (void **state)
-{
- (void)state;
-
- int16_t vec[] = {5, 2, 3, 4, 1};
- int r = find_min_int16(vec, sizeof(vec) / sizeof(int16_t));
-
- assert_int_equal(r, 1);
-}
-
-int main(void)
-{
- const struct CMUnitTest tests[] = {
- cmocka_unit_test
- (test_math_numbers_find_min_int16_for_2_equals_2),
- cmocka_unit_test
- (test_math_numbers_find_min_int16_for_5_2_3_4_1_equals_1)
- };
-
- cmocka_set_message_output(CM_OUTPUT_TAP);
-
- return cmocka_run_group_tests(tests, NULL, NULL);
-}
diff --git a/test/cmocka/src/math/numbers/gcd.c b/test/cmocka/src/math/numbers/gcd.c
deleted file mode 100644
index dab9fa3..0000000
--- a/test/cmocka/src/math/numbers/gcd.c
+++ /dev/null
@@ -1,70 +0,0 @@
-/*
- * Copyright (c) 2018, Intel Corporation
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- * * Redistributions of source code must retain the above copyright
- * notice, this list of conditions and the following disclaimer.
- * * Redistributions in binary form must reproduce the above copyright
- * notice, this list of conditions and the following disclaimer in the
- * documentation and/or other materials provided with the distribution.
- * * Neither the name of the Intel Corporation nor the
- * names of its contributors may be used to endorse or promote products
- * derived from this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
- * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
- * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
- * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
- * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
- * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
- * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
- * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
- * POSSIBILITY OF SUCH DAMAGE.
- *
- * Author: Marcin Maka <marcin.maka@linux.intel.com>
- * Author: Janusz Jankowski <janusz.jankowski@linux.intel.com>
- */
-
-#include <sof/math/numbers.h>
-
-#include <stdarg.h>
-#include <stddef.h>
-#include <setjmp.h>
-#include <cmocka.h>
-
-static void test_math_numbers_gcd_for_5083_and_391_equals_391(void **state)
-{
- int r;
-
- (void) state;
-
- r = gcd(5083, 391);
- assert_int_equal(r, 391);
-}
-
-static void test_math_numbers_gcd_for_12_and_9_equals_3(void **state)
-{
- int r;
-
- (void) state;
-
- r = gcd(12, 9);
- assert_int_equal(r, 3);
-}
-
-int main(void)
-{
- const struct CMUnitTest tests[] = {
- cmocka_unit_test
- (test_math_numbers_gcd_for_5083_and_391_equals_391),
- cmocka_unit_test(test_math_numbers_gcd_for_12_and_9_equals_3),
- };
-
- cmocka_set_message_output(CM_OUTPUT_TAP);
-
- return cmocka_run_group_tests(tests, NULL, NULL);
-}
diff --git a/test/cmocka/src/math/numbers/norm_int32.c b/test/cmocka/src/math/numbers/norm_int32.c
deleted file mode 100644
index 5ffe33e..0000000
--- a/test/cmocka/src/math/numbers/norm_int32.c
+++ /dev/null
@@ -1,78 +0,0 @@
-/*
- * Copyright (c) 2018, Intel Corporation
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- * * Redistributions of source code must retain the above copyright
- * notice, this list of conditions and the following disclaimer.
- * * Redistributions in binary form must reproduce the above copyright
- * notice, this list of conditions and the following disclaimer in the
- * documentation and/or other materials provided with the distribution.
- * * Neither the name of the Intel Corporation nor the
- * names of its contributors may be used to endorse or promote products
- * derived from this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
- * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
- * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
- * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
- * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
- * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
- * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
- * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
- * POSSIBILITY OF SUCH DAMAGE.
- *
- * Author: Slawomir Blauciak <slawomir.blauciak@linux.intel.com>
- */
-
-#include <sof/math/numbers.h>
-
-#include <stdarg.h>
-#include <stddef.h>
-#include <setjmp.h>
-#include <cmocka.h>
-
-static void test_math_numbers_norm_int32_for_0_equals_31(void **state)
-{
- (void)state;
-
- int r = norm_int32(0);
-
- assert_int_equal(r, 31);
-}
-
-static void test_math_numbers_norm_int32_for_35_equals_10(void **state)
-{
- (void)state;
-
- int r = norm_int32(35);
-
- assert_int_equal(r, 25);
-}
-
-static void test_math_numbers_norm_int32_for_2147483647_equals_0(void **state)
-{
- (void)state;
-
- int r = norm_int32(2147483647);
-
- assert_int_equal(r, 0);
-}
-
-int main(void)
-{
- const struct CMUnitTest tests[] = {
- cmocka_unit_test(test_math_numbers_norm_int32_for_0_equals_31),
- cmocka_unit_test
- (test_math_numbers_norm_int32_for_35_equals_10),
- cmocka_unit_test
- (test_math_numbers_norm_int32_for_2147483647_equals_0)
- };
-
- cmocka_set_message_output(CM_OUTPUT_TAP);
-
- return cmocka_run_group_tests(tests, NULL, NULL);
-}
diff --git a/test/cmocka/src/math/trig/sin_fixed.c b/test/cmocka/src/math/trig/sin_fixed.c
deleted file mode 100644
index de0bd41..0000000
--- a/test/cmocka/src/math/trig/sin_fixed.c
+++ /dev/null
@@ -1,169 +0,0 @@
-/*
- * Copyright (c) 2018, Intel Corporation
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- * * Redistributions of source code must retain the above copyright
- * notice, this list of conditions and the following disclaimer.
- * * Redistributions in binary form must reproduce the above copyright
- * notice, this list of conditions and the following disclaimer in the
- * documentation and/or other materials provided with the distribution.
- * * Neither the name of the Intel Corporation nor the
- * names of its contributors may be used to endorse or promote products
- * derived from this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
- * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
- * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
- * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
- * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
- * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
- * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
- * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
- * POSSIBILITY OF SUCH DAMAGE.
- *
- * Author: Slawomir Blauciak <slawomir.blauciak@linux.intel.com>
- */
-
-#include <stdio.h>
-#include <stdint.h>
-#include <stdarg.h>
-#include <stddef.h>
-#include <setjmp.h>
-#include <math.h>
-#include <cmocka.h>
-
-#include <sof/audio/format.h>
-#include <sof/math/trig.h>
-
-#define CMP_TOLERANCE 0.000005
-
-/* Reference table generated by sin(), gcc-4.3.2 */
-static const float sin_ref_table[] = {
- 0.0000000000, 0.0174524064, 0.0348994967, 0.0523359562,
- 0.0697564737, 0.0871557427, 0.1045284633, 0.1218693434,
- 0.1391731010, 0.1564344650, 0.1736481777, 0.1908089954,
- 0.2079116908, 0.2249510543, 0.2419218956, 0.2588190451,
- 0.2756373558, 0.2923717047, 0.3090169944, 0.3255681545,
- 0.3420201433, 0.3583679495, 0.3746065934, 0.3907311285,
- 0.4067366431, 0.4226182617, 0.4383711468, 0.4539904997,
- 0.4694715628, 0.4848096202, 0.5000000000, 0.5150380749,
- 0.5299192642, 0.5446390350, 0.5591929035, 0.5735764364,
- 0.5877852523, 0.6018150232, 0.6156614753, 0.6293203910,
- 0.6427876097, 0.6560590290, 0.6691306064, 0.6819983601,
- 0.6946583705, 0.7071067812, 0.7193398003, 0.7313537016,
- 0.7431448255, 0.7547095802, 0.7660444431, 0.7771459615,
- 0.7880107536, 0.7986355100, 0.8090169944, 0.8191520443,
- 0.8290375726, 0.8386705679, 0.8480480962, 0.8571673007,
- 0.8660254038, 0.8746197071, 0.8829475929, 0.8910065242,
- 0.8987940463, 0.9063077870, 0.9135454576, 0.9205048535,
- 0.9271838546, 0.9335804265, 0.9396926208, 0.9455185756,
- 0.9510565163, 0.9563047560, 0.9612616959, 0.9659258263,
- 0.9702957263, 0.9743700648, 0.9781476007, 0.9816271834,
- 0.9848077530, 0.9876883406, 0.9902680687, 0.9925461516,
- 0.9945218954, 0.9961946981, 0.9975640503, 0.9986295348,
- 0.9993908270, 0.9998476952, 1.0000000000, 0.9998476952,
- 0.9993908270, 0.9986295348, 0.9975640503, 0.9961946981,
- 0.9945218954, 0.9925461516, 0.9902680687, 0.9876883406,
- 0.9848077530, 0.9816271834, 0.9781476007, 0.9743700648,
- 0.9702957263, 0.9659258263, 0.9612616959, 0.9563047560,
- 0.9510565163, 0.9455185756, 0.9396926208, 0.9335804265,
- 0.9271838546, 0.9205048535, 0.9135454576, 0.9063077870,
- 0.8987940463, 0.8910065242, 0.8829475929, 0.8746197071,
- 0.8660254038, 0.8571673007, 0.8480480962, 0.8386705679,
- 0.8290375726, 0.8191520443, 0.8090169944, 0.7986355100,
- 0.7880107536, 0.7771459615, 0.7660444431, 0.7547095802,
- 0.7431448255, 0.7313537016, 0.7193398003, 0.7071067812,
- 0.6946583705, 0.6819983601, 0.6691306064, 0.6560590290,
- 0.6427876097, 0.6293203910, 0.6156614753, 0.6018150232,
- 0.5877852523, 0.5735764364, 0.5591929035, 0.5446390350,
- 0.5299192642, 0.5150380749, 0.5000000000, 0.4848096202,
- 0.4694715628, 0.4539904997, 0.4383711468, 0.4226182617,
- 0.4067366431, 0.3907311285, 0.3746065934, 0.3583679495,
- 0.3420201433, 0.3255681545, 0.3090169944, 0.2923717047,
- 0.2756373558, 0.2588190451, 0.2419218956, 0.2249510543,
- 0.2079116908, 0.1908089954, 0.1736481777, 0.1564344650,
- 0.1391731010, 0.1218693434, 0.1045284633, 0.0871557427,
- 0.0697564737, 0.0523359562, 0.0348994967, 0.0174524064,
- 0.0000000000, -0.0174524064, -0.0348994967, -0.0523359562,
- -0.0697564737, -0.0871557427, -0.1045284633, -0.1218693434,
- -0.1391731010, -0.1564344650, -0.1736481777, -0.1908089954,
- -0.2079116908, -0.2249510543, -0.2419218956, -0.2588190451,
- -0.2756373558, -0.2923717047, -0.3090169944, -0.3255681545,
- -0.3420201433, -0.3583679495, -0.3746065934, -0.3907311285,
- -0.4067366431, -0.4226182617, -0.4383711468, -0.4539904997,
- -0.4694715628, -0.4848096202, -0.5000000000, -0.5150380749,
- -0.5299192642, -0.5446390350, -0.5591929035, -0.5735764364,
- -0.5877852523, -0.6018150232, -0.6156614753, -0.6293203910,
- -0.6427876097, -0.6560590290, -0.6691306064, -0.6819983601,
- -0.6946583705, -0.7071067812, -0.7193398003, -0.7313537016,
- -0.7431448255, -0.7547095802, -0.7660444431, -0.7771459615,
- -0.7880107536, -0.7986355100, -0.8090169944, -0.8191520443,
- -0.8290375726, -0.8386705679, -0.8480480962, -0.8571673007,
- -0.8660254038, -0.8746197071, -0.8829475929, -0.8910065242,
- -0.8987940463, -0.9063077870, -0.9135454576, -0.9205048535,
- -0.9271838546, -0.9335804265, -0.9396926208, -0.9455185756,
- -0.9510565163, -0.9563047560, -0.9612616959, -0.9659258263,
- -0.9702957263, -0.9743700648, -0.9781476007, -0.9816271834,
- -0.9848077530, -0.9876883406, -0.9902680687, -0.9925461516,
- -0.9945218954, -0.9961946981, -0.9975640503, -0.9986295348,
- -0.9993908270, -0.9998476952, -1.0000000000, -0.9998476952,
- -0.9993908270, -0.9986295348, -0.9975640503, -0.9961946981,
- -0.9945218954, -0.9925461516, -0.9902680687, -0.9876883406,
- -0.9848077530, -0.9816271834, -0.9781476007, -0.9743700648,
- -0.9702957263, -0.9659258263, -0.9612616959, -0.9563047560,
- -0.9510565163, -0.9455185756, -0.9396926208, -0.9335804265,
- -0.9271838546, -0.9205048535, -0.9135454576, -0.9063077870,
- -0.8987940463, -0.8910065242, -0.8829475929, -0.8746197071,
- -0.8660254038, -0.8571673007, -0.8480480962, -0.8386705679,
- -0.8290375726, -0.8191520443, -0.8090169944, -0.7986355100,
- -0.7880107536, -0.7771459615, -0.7660444431, -0.7547095802,
- -0.7431448255, -0.7313537016, -0.7193398003, -0.7071067812,
- -0.6946583705, -0.6819983601, -0.6691306064, -0.6560590290,
- -0.6427876097, -0.6293203910, -0.6156614753, -0.6018150232,
- -0.5877852523, -0.5735764364, -0.5591929035, -0.5446390350,
- -0.5299192642, -0.5150380749, -0.5000000000, -0.4848096202,
- -0.4694715628, -0.4539904997, -0.4383711468, -0.4226182617,
- -0.4067366431, -0.3907311285, -0.3746065934, -0.3583679495,
- -0.3420201433, -0.3255681545, -0.3090169944, -0.2923717047,
- -0.2756373558, -0.2588190451, -0.2419218956, -0.2249510543,
- -0.2079116908, -0.1908089954, -0.1736481777, -0.1564344650,
- -0.1391731010, -0.1218693434, -0.1045284633, -0.0871557427,
- -0.0697564737, -0.0523359562, -0.0348994967, -0.0174524064
-};
-
-static void test_math_trig_sin_fixed(void **state)
-{
- (void)state;
-
- int theta;
-
- for (theta = 0; theta < 360; ++theta) {
- double rad = M_PI / (180.0 / theta);
- int32_t rad_q28 = Q_CONVERT_FLOAT(rad, 28);
-
- float r = Q_CONVERT_QTOF(sin_fixed(rad_q28), 31);
- float diff = fabsf(sin_ref_table[theta] - r);
-
- if (diff > CMP_TOLERANCE) {
- printf("%s: diff for %d deg = %.10f\n", __func__,
- theta, diff);
- }
-
- assert_true(diff <= CMP_TOLERANCE);
- }
-}
-
-int main(void)
-{
- const struct CMUnitTest tests[] = {
- cmocka_unit_test(test_math_trig_sin_fixed)
- };
-
- cmocka_set_message_output(CM_OUTPUT_TAP);
-
- return cmocka_run_group_tests(tests, NULL, NULL);
-}
diff --git a/version.sh b/version.sh
deleted file mode 100755
index 76a522e..0000000
--- a/version.sh
+++ /dev/null
@@ -1,57 +0,0 @@
-#!/bin/bash
-
-# version for configure, make dist and FW etc
-# usage "version.sh dir"
-# Where dir is the top level directory path.
-
-# use pwd is no path argument is given
-if [ $# -eq 0 ]; then
- DIR=`pwd`
-else
- DIR=$1
-fi
-
-# get version from git tag
-GIT_TAG=`git describe --abbrev=4 2>/dev/null`
-
-# may fail to get git describe in some case, add this fallback to handle error
-if [[ "x$GIT_TAG" == "x" ]]
-then
- GIT_TAG="v0.0-0-g0000"
-fi
-
-# Some releases have a SOF_FW_XXX_ prefix on the tag and this prefix
-# must be stripped for usage in version.h. i.e. we just need the number.
-if [ $(expr match $GIT_TAG 'SOF_FW_[A-Z]+_' ) -lt 15 ]; then
- VER=`echo $GIT_TAG | cut -d_ -f4`
-else
- VER=$GIT_TAG
-fi
-
-# create git version if we are a git repo or git worktree
-if [ -e $DIR/.git -o -d $DIR/.git ]; then
-# version for make dist
- echo $VER > $DIR/.version
- echo $VER > $DIR/.tarball-version
-
- # git commit for IPC
- echo "#define SOF_TAG \"`git log --pretty=format:\"%h\" -1 | cut -c1-5`\"" > $DIR/src/include/version.h
-else
- echo "#define SOF_TAG \"0\"" > $DIR/src/include/version.h
-fi
-
-# build counter
-if [ -e $DIR/.build ]; then
- num=$((`cat $DIR/.build` + 1))
-else
- num=0
-fi
-
-# save and insert build counter
-echo $num > $DIR/.build
-echo "#define SOF_BUILD $num" >> $DIR/src/include/version.h
-
-#echo version for AC_INIT
-if [ -e $DIR/.version ]; then
- echo -n `cat $DIR/.version | cut -dv -f2 | cut -d. -f1`.`cat $DIR/.version | cut -d. -f2 | cut -d- -f1`.`cat $DIR/.version | cut -d. -f3 | cut -d- -f1`
-fi
