DSP: Integrate CMSIS-DSP 1.8.0 (CMSIS 5.7.0)
This commit integrates the newly added CMSIS-DSP 1.8.0 (part of CMSIS
5.7.0 release) component to the Zephyr build system.
Note that the CMake files added in this commit were re-implemented
specifically for Zephyr, and they are therefore different from the
upstream version.
Signed-off-by: Stephanos Ioannidis <root@stephanos.io>
diff --git a/CMSIS/CMakeLists.txt b/CMSIS/CMakeLists.txt
index 8bf141a..4b1191f 100644
--- a/CMSIS/CMakeLists.txt
+++ b/CMSIS/CMakeLists.txt
@@ -3,3 +3,5 @@
add_subdirectory_ifdef(CONFIG_HAS_CMSIS_CORE_M Core)
add_subdirectory_ifdef(CONFIG_HAS_CMSIS_CORE_A Core_A)
add_subdirectory_ifdef(CONFIG_HAS_CMSIS_CORE_R Core_R)
+
+add_subdirectory_ifdef(CONFIG_CMSIS_DSP DSP)
diff --git a/CMSIS/DSP/CMakeLists.txt b/CMSIS/DSP/CMakeLists.txt
new file mode 100644
index 0000000..40bbda2
--- /dev/null
+++ b/CMSIS/DSP/CMakeLists.txt
@@ -0,0 +1,10 @@
+# Copyright (c) 2020 Stephanos Ioannidis <root@stephanos.io>
+# SPDX-License-Identifier: Apache-2.0
+
+zephyr_include_directories(Include)
+
+if(CONFIG_CMSIS_DSP_HELIUM OR CONFIG_CMSIS_DSP_MVEF OR CONFIG_CMSIS_DSP_SUPPORT)
+ include_directories(PrivateInclude)
+endif()
+
+add_subdirectory(Source)
diff --git a/CMSIS/DSP/Source/BasicMathFunctions/CMakeLists.txt b/CMSIS/DSP/Source/BasicMathFunctions/CMakeLists.txt
new file mode 100644
index 0000000..e9fee3e
--- /dev/null
+++ b/CMSIS/DSP/Source/BasicMathFunctions/CMakeLists.txt
@@ -0,0 +1,54 @@
+# Copyright (c) 2020 Stephanos Ioannidis <root@stephanos.io>
+# SPDX-License-Identifier: Apache-2.0
+
+zephyr_library()
+
+zephyr_library_sources(
+ arm_abs_f32.c
+ arm_abs_q7.c
+ arm_abs_q15.c
+ arm_abs_q31.c
+ arm_add_f32.c
+ arm_add_q7.c
+ arm_add_q15.c
+ arm_add_q31.c
+ arm_and_u8.c
+ arm_and_u16.c
+ arm_and_u32.c
+ arm_dot_prod_f32.c
+ arm_dot_prod_q7.c
+ arm_dot_prod_q15.c
+ arm_dot_prod_q31.c
+ arm_mult_f32.c
+ arm_mult_q7.c
+ arm_mult_q15.c
+ arm_mult_q31.c
+ arm_negate_f32.c
+ arm_negate_q7.c
+ arm_negate_q15.c
+ arm_negate_q31.c
+ arm_not_u8.c
+ arm_not_u16.c
+ arm_not_u32.c
+ arm_offset_f32.c
+ arm_offset_q7.c
+ arm_offset_q15.c
+ arm_offset_q31.c
+ arm_or_u8.c
+ arm_or_u16.c
+ arm_or_u32.c
+ arm_scale_f32.c
+ arm_scale_q7.c
+ arm_scale_q15.c
+ arm_scale_q31.c
+ arm_shift_q7.c
+ arm_shift_q15.c
+ arm_shift_q31.c
+ arm_sub_f32.c
+ arm_sub_q7.c
+ arm_sub_q15.c
+ arm_sub_q31.c
+ arm_xor_u8.c
+ arm_xor_u16.c
+ arm_xor_u32.c
+ )
diff --git a/CMSIS/DSP/Source/BayesFunctions/CMakeLists.txt b/CMSIS/DSP/Source/BayesFunctions/CMakeLists.txt
new file mode 100644
index 0000000..c497589
--- /dev/null
+++ b/CMSIS/DSP/Source/BayesFunctions/CMakeLists.txt
@@ -0,0 +1,8 @@
+# Copyright (c) 2020 Stephanos Ioannidis <root@stephanos.io>
+# SPDX-License-Identifier: Apache-2.0
+
+zephyr_library()
+
+zephyr_library_sources(
+ arm_gaussian_naive_bayes_predict_f32.c
+ )
diff --git a/CMSIS/DSP/Source/CMakeLists.txt b/CMSIS/DSP/Source/CMakeLists.txt
new file mode 100644
index 0000000..93553d9
--- /dev/null
+++ b/CMSIS/DSP/Source/CMakeLists.txt
@@ -0,0 +1,310 @@
+# Copyright (c) 2020 Stephanos Ioannidis <root@stephanos.io>
+# SPDX-License-Identifier: Apache-2.0
+
+# Global Feature Definitions
+zephyr_compile_definitions_ifdef(CONFIG_CMSIS_DSP_NEON ARM_MATH_NEON)
+zephyr_compile_definitions_ifdef(CONFIG_CMSIS_DSP_HELIUM ARM_MATH_HELIUM)
+zephyr_compile_definitions_ifdef(CONFIG_CMSIS_DSP_MVEF ARM_MATH_MVEF)
+zephyr_compile_definitions_ifdef(CONFIG_CMSIS_DSP_MVEI ARM_MATH_MVEI)
+zephyr_compile_definitions_ifdef(CONFIG_CMSIS_DSP_LOOPUNROLL ARM_MATH_LOOPUNROLL)
+zephyr_compile_definitions_ifdef(CONFIG_CMSIS_DSP_ROUNDING ARM_MATH_ROUNDING)
+zephyr_compile_definitions_ifdef(CONFIG_CMSIS_DSP_MATRIXCHECK ARM_MATH_MATRIX_CHECK)
+zephyr_compile_definitions_ifdef(CONFIG_CMSIS_DSP_AUTOVECTORIZE ARM_MATH_AUTOVECTORIZE)
+
+# Table Definitions
+zephyr_compile_definitions_ifdef(CONFIG_CMSIS_DSP_TABLES ARM_DSP_CONFIG_TABLES)
+zephyr_compile_definitions_ifdef(CONFIG_CMSIS_DSP_TABLES ARM_FAST_ALLOW_TABLES)
+zephyr_compile_definitions_ifdef(CONFIG_CMSIS_DSP_TABLES ARM_FFT_ALLOW_TABLES)
+
+zephyr_compile_definitions_ifdef(CONFIG_CMSIS_DSP_TABLES_ALL_FAST ARM_ALL_FAST_TABLES)
+zephyr_compile_definitions_ifdef(CONFIG_CMSIS_DSP_TABLES_ALL_FFT ARM_ALL_FFT_TABLES)
+
+zephyr_compile_definitions_ifdef(CONFIG_CMSIS_DSP_TABLES_ARM_COS_F32 ARM_TABLE_SIN_F32)
+zephyr_compile_definitions_ifdef(CONFIG_CMSIS_DSP_TABLES_ARM_COS_Q31 ARM_TABLE_SIN_Q31)
+zephyr_compile_definitions_ifdef(CONFIG_CMSIS_DSP_TABLES_ARM_COS_Q15 ARM_TABLE_SIN_Q15)
+zephyr_compile_definitions_ifdef(CONFIG_CMSIS_DSP_TABLES_ARM_SIN_F32 ARM_TABLE_SIN_F32)
+zephyr_compile_definitions_ifdef(CONFIG_CMSIS_DSP_TABLES_ARM_SIN_Q31 ARM_TABLE_SIN_Q31)
+zephyr_compile_definitions_ifdef(CONFIG_CMSIS_DSP_TABLES_ARM_SIN_Q15 ARM_TABLE_SIN_Q15)
+zephyr_compile_definitions_ifdef(CONFIG_CMSIS_DSP_TABLES_ARM_SIN_COS_F32 ARM_TABLE_SIN_F32)
+zephyr_compile_definitions_ifdef(CONFIG_CMSIS_DSP_TABLES_ARM_SIN_COS_Q31 ARM_TABLE_SIN_Q31)
+zephyr_compile_definitions_ifdef(CONFIG_CMSIS_DSP_TABLES_ARM_LMS_NORM_Q31 ARM_TABLE_RECIP_Q31)
+zephyr_compile_definitions_ifdef(CONFIG_CMSIS_DSP_TABLES_ARM_LMS_NORM_Q15 ARM_TABLE_RECIP_Q15)
+
+if(CONFIG_CMSIS_DSP_MVEI)
+ zephyr_compile_definitions_ifdef(CONFIG_CMSIS_DSP_TABLES_ARM_CMPLX_MAG_Q31 ARM_TABLE_FAST_SQRT_Q31_MVE)
+ zephyr_compile_definitions_ifdef(CONFIG_CMSIS_DSP_TABLES_ARM_CMPLX_MAG_Q15 ARM_TABLE_FAST_SQRT_Q15_MVE)
+endif()
+
+zephyr_compile_definitions_ifdef(CONFIG_CMSIS_DSP_TABLES_CFFT_F32_16 ARM_TABLE_TWIDDLECOEF_F32_16)
+zephyr_compile_definitions_ifdef(CONFIG_CMSIS_DSP_TABLES_CFFT_F32_32 ARM_TABLE_TWIDDLECOEF_F32_32)
+zephyr_compile_definitions_ifdef(CONFIG_CMSIS_DSP_TABLES_CFFT_F32_64 ARM_TABLE_TWIDDLECOEF_F32_64)
+zephyr_compile_definitions_ifdef(CONFIG_CMSIS_DSP_TABLES_CFFT_F32_128 ARM_TABLE_TWIDDLECOEF_F32_128)
+zephyr_compile_definitions_ifdef(CONFIG_CMSIS_DSP_TABLES_CFFT_F32_256 ARM_TABLE_TWIDDLECOEF_F32_256)
+zephyr_compile_definitions_ifdef(CONFIG_CMSIS_DSP_TABLES_CFFT_F32_512 ARM_TABLE_TWIDDLECOEF_F32_512)
+zephyr_compile_definitions_ifdef(CONFIG_CMSIS_DSP_TABLES_CFFT_F32_1024 ARM_TABLE_TWIDDLECOEF_F32_1024)
+zephyr_compile_definitions_ifdef(CONFIG_CMSIS_DSP_TABLES_CFFT_F32_2048 ARM_TABLE_TWIDDLECOEF_F32_2048)
+zephyr_compile_definitions_ifdef(CONFIG_CMSIS_DSP_TABLES_CFFT_F32_4096 ARM_TABLE_TWIDDLECOEF_F32_4096)
+
+if(CONFIG_CMSIS_DSP_HELIUM OR CONFIG_CMSIS_DSP_MVEF)
+ zephyr_compile_definitions_ifdef(CONFIG_CMSIS_DSP_TABLES_CFFT_F32_16 ARM_TABLE_BITREVIDX_FXT_16)
+ zephyr_compile_definitions_ifdef(CONFIG_CMSIS_DSP_TABLES_CFFT_F32_32 ARM_TABLE_BITREVIDX_FXT_32)
+ zephyr_compile_definitions_ifdef(CONFIG_CMSIS_DSP_TABLES_CFFT_F32_64 ARM_TABLE_BITREVIDX_FXT_64)
+ zephyr_compile_definitions_ifdef(CONFIG_CMSIS_DSP_TABLES_CFFT_F32_128 ARM_TABLE_BITREVIDX_FXT_128)
+ zephyr_compile_definitions_ifdef(CONFIG_CMSIS_DSP_TABLES_CFFT_F32_256 ARM_TABLE_BITREVIDX_FXT_256)
+ zephyr_compile_definitions_ifdef(CONFIG_CMSIS_DSP_TABLES_CFFT_F32_512 ARM_TABLE_BITREVIDX_FXT_512)
+ zephyr_compile_definitions_ifdef(CONFIG_CMSIS_DSP_TABLES_CFFT_F32_1024 ARM_TABLE_BITREVIDX_FXT_1024)
+ zephyr_compile_definitions_ifdef(CONFIG_CMSIS_DSP_TABLES_CFFT_F32_2048 ARM_TABLE_BITREVIDX_FXT_2048)
+ zephyr_compile_definitions_ifdef(CONFIG_CMSIS_DSP_TABLES_CFFT_F32_4096 ARM_TABLE_BITREVIDX_FXT_4096)
+else()
+ zephyr_compile_definitions_ifdef(CONFIG_CMSIS_DSP_TABLES_CFFT_F32_16 ARM_TABLE_BITREVIDX_FLT_16)
+ zephyr_compile_definitions_ifdef(CONFIG_CMSIS_DSP_TABLES_CFFT_F32_32 ARM_TABLE_BITREVIDX_FLT_32)
+ zephyr_compile_definitions_ifdef(CONFIG_CMSIS_DSP_TABLES_CFFT_F32_64 ARM_TABLE_BITREVIDX_FLT_64)
+ zephyr_compile_definitions_ifdef(CONFIG_CMSIS_DSP_TABLES_CFFT_F32_128 ARM_TABLE_BITREVIDX_FLT_128)
+ zephyr_compile_definitions_ifdef(CONFIG_CMSIS_DSP_TABLES_CFFT_F32_256 ARM_TABLE_BITREVIDX_FLT_256)
+ zephyr_compile_definitions_ifdef(CONFIG_CMSIS_DSP_TABLES_CFFT_F32_512 ARM_TABLE_BITREVIDX_FLT_512)
+ zephyr_compile_definitions_ifdef(CONFIG_CMSIS_DSP_TABLES_CFFT_F32_1024 ARM_TABLE_BITREVIDX_FLT_1024)
+ zephyr_compile_definitions_ifdef(CONFIG_CMSIS_DSP_TABLES_CFFT_F32_2048 ARM_TABLE_BITREVIDX_FLT_2048)
+ zephyr_compile_definitions_ifdef(CONFIG_CMSIS_DSP_TABLES_CFFT_F32_4096 ARM_TABLE_BITREVIDX_FLT_4096)
+endif()
+
+zephyr_compile_definitions_ifdef(CONFIG_CMSIS_DSP_TABLES_CFFT_F64_16 ARM_TABLE_TWIDDLECOEF_F64_16)
+zephyr_compile_definitions_ifdef(CONFIG_CMSIS_DSP_TABLES_CFFT_F64_16 ARM_TABLE_BITREVIDX_FLT64_16)
+zephyr_compile_definitions_ifdef(CONFIG_CMSIS_DSP_TABLES_CFFT_F64_32 ARM_TABLE_TWIDDLECOEF_F64_32)
+zephyr_compile_definitions_ifdef(CONFIG_CMSIS_DSP_TABLES_CFFT_F64_32 ARM_TABLE_BITREVIDX_FLT64_32)
+zephyr_compile_definitions_ifdef(CONFIG_CMSIS_DSP_TABLES_CFFT_F64_64 ARM_TABLE_TWIDDLECOEF_F64_64)
+zephyr_compile_definitions_ifdef(CONFIG_CMSIS_DSP_TABLES_CFFT_F64_64 ARM_TABLE_BITREVIDX_FLT64_64)
+zephyr_compile_definitions_ifdef(CONFIG_CMSIS_DSP_TABLES_CFFT_F64_128 ARM_TABLE_TWIDDLECOEF_F64_128)
+zephyr_compile_definitions_ifdef(CONFIG_CMSIS_DSP_TABLES_CFFT_F64_128 ARM_TABLE_BITREVIDX_FLT64_128)
+zephyr_compile_definitions_ifdef(CONFIG_CMSIS_DSP_TABLES_CFFT_F64_256 ARM_TABLE_TWIDDLECOEF_F64_256)
+zephyr_compile_definitions_ifdef(CONFIG_CMSIS_DSP_TABLES_CFFT_F64_256 ARM_TABLE_BITREVIDX_FLT64_256)
+zephyr_compile_definitions_ifdef(CONFIG_CMSIS_DSP_TABLES_CFFT_F64_512 ARM_TABLE_TWIDDLECOEF_F64_512)
+zephyr_compile_definitions_ifdef(CONFIG_CMSIS_DSP_TABLES_CFFT_F64_512 ARM_TABLE_BITREVIDX_FLT64_512)
+zephyr_compile_definitions_ifdef(CONFIG_CMSIS_DSP_TABLES_CFFT_F64_1024 ARM_TABLE_TWIDDLECOEF_F64_1024)
+zephyr_compile_definitions_ifdef(CONFIG_CMSIS_DSP_TABLES_CFFT_F64_1024 ARM_TABLE_BITREVIDX_FLT64_1024)
+zephyr_compile_definitions_ifdef(CONFIG_CMSIS_DSP_TABLES_CFFT_F64_2048 ARM_TABLE_TWIDDLECOEF_F64_2048)
+zephyr_compile_definitions_ifdef(CONFIG_CMSIS_DSP_TABLES_CFFT_F64_2048 ARM_TABLE_BITREVIDX_FLT64_2048)
+zephyr_compile_definitions_ifdef(CONFIG_CMSIS_DSP_TABLES_CFFT_F64_4096 ARM_TABLE_TWIDDLECOEF_F64_4096)
+zephyr_compile_definitions_ifdef(CONFIG_CMSIS_DSP_TABLES_CFFT_F64_4096 ARM_TABLE_BITREVIDX_FLT64_4096)
+
+zephyr_compile_definitions_ifdef(CONFIG_CMSIS_DSP_TABLES_CFFT_Q31_16 ARM_TABLE_TWIDDLECOEF_Q31_16)
+zephyr_compile_definitions_ifdef(CONFIG_CMSIS_DSP_TABLES_CFFT_Q31_16 ARM_TABLE_BITREVIDX_FXT_16)
+zephyr_compile_definitions_ifdef(CONFIG_CMSIS_DSP_TABLES_CFFT_Q31_32 ARM_TABLE_TWIDDLECOEF_Q31_32)
+zephyr_compile_definitions_ifdef(CONFIG_CMSIS_DSP_TABLES_CFFT_Q31_32 ARM_TABLE_BITREVIDX_FXT_32)
+zephyr_compile_definitions_ifdef(CONFIG_CMSIS_DSP_TABLES_CFFT_Q31_64 ARM_TABLE_TWIDDLECOEF_Q31_64)
+zephyr_compile_definitions_ifdef(CONFIG_CMSIS_DSP_TABLES_CFFT_Q31_64 ARM_TABLE_BITREVIDX_FXT_64)
+zephyr_compile_definitions_ifdef(CONFIG_CMSIS_DSP_TABLES_CFFT_Q31_128 ARM_TABLE_TWIDDLECOEF_Q31_128)
+zephyr_compile_definitions_ifdef(CONFIG_CMSIS_DSP_TABLES_CFFT_Q31_128 ARM_TABLE_BITREVIDX_FXT_128)
+zephyr_compile_definitions_ifdef(CONFIG_CMSIS_DSP_TABLES_CFFT_Q31_256 ARM_TABLE_TWIDDLECOEF_Q31_256)
+zephyr_compile_definitions_ifdef(CONFIG_CMSIS_DSP_TABLES_CFFT_Q31_256 ARM_TABLE_BITREVIDX_FXT_256)
+zephyr_compile_definitions_ifdef(CONFIG_CMSIS_DSP_TABLES_CFFT_Q31_512 ARM_TABLE_TWIDDLECOEF_Q31_512)
+zephyr_compile_definitions_ifdef(CONFIG_CMSIS_DSP_TABLES_CFFT_Q31_512 ARM_TABLE_BITREVIDX_FXT_512)
+zephyr_compile_definitions_ifdef(CONFIG_CMSIS_DSP_TABLES_CFFT_Q31_1024 ARM_TABLE_TWIDDLECOEF_Q31_1024)
+zephyr_compile_definitions_ifdef(CONFIG_CMSIS_DSP_TABLES_CFFT_Q31_1024 ARM_TABLE_BITREVIDX_FXT_1024)
+zephyr_compile_definitions_ifdef(CONFIG_CMSIS_DSP_TABLES_CFFT_Q31_2048 ARM_TABLE_TWIDDLECOEF_Q31_2048)
+zephyr_compile_definitions_ifdef(CONFIG_CMSIS_DSP_TABLES_CFFT_Q31_2048 ARM_TABLE_BITREVIDX_FXT_2048)
+zephyr_compile_definitions_ifdef(CONFIG_CMSIS_DSP_TABLES_CFFT_Q31_4096 ARM_TABLE_TWIDDLECOEF_Q31_4096)
+zephyr_compile_definitions_ifdef(CONFIG_CMSIS_DSP_TABLES_CFFT_Q31_4096 ARM_TABLE_BITREVIDX_FXT_4096)
+
+zephyr_compile_definitions_ifdef(CONFIG_CMSIS_DSP_TABLES_CFFT_Q15_16 ARM_TABLE_TWIDDLECOEF_Q15_16)
+zephyr_compile_definitions_ifdef(CONFIG_CMSIS_DSP_TABLES_CFFT_Q15_16 ARM_TABLE_BITREVIDX_FXT_16)
+zephyr_compile_definitions_ifdef(CONFIG_CMSIS_DSP_TABLES_CFFT_Q15_32 ARM_TABLE_TWIDDLECOEF_Q15_32)
+zephyr_compile_definitions_ifdef(CONFIG_CMSIS_DSP_TABLES_CFFT_Q15_32 ARM_TABLE_BITREVIDX_FXT_32)
+zephyr_compile_definitions_ifdef(CONFIG_CMSIS_DSP_TABLES_CFFT_Q15_64 ARM_TABLE_TWIDDLECOEF_Q15_64)
+zephyr_compile_definitions_ifdef(CONFIG_CMSIS_DSP_TABLES_CFFT_Q15_64 ARM_TABLE_BITREVIDX_FXT_64)
+zephyr_compile_definitions_ifdef(CONFIG_CMSIS_DSP_TABLES_CFFT_Q15_128 ARM_TABLE_TWIDDLECOEF_Q15_128)
+zephyr_compile_definitions_ifdef(CONFIG_CMSIS_DSP_TABLES_CFFT_Q15_128 ARM_TABLE_BITREVIDX_FXT_128)
+zephyr_compile_definitions_ifdef(CONFIG_CMSIS_DSP_TABLES_CFFT_Q15_256 ARM_TABLE_TWIDDLECOEF_Q15_256)
+zephyr_compile_definitions_ifdef(CONFIG_CMSIS_DSP_TABLES_CFFT_Q15_256 ARM_TABLE_BITREVIDX_FXT_256)
+zephyr_compile_definitions_ifdef(CONFIG_CMSIS_DSP_TABLES_CFFT_Q15_512 ARM_TABLE_TWIDDLECOEF_Q15_512)
+zephyr_compile_definitions_ifdef(CONFIG_CMSIS_DSP_TABLES_CFFT_Q15_512 ARM_TABLE_BITREVIDX_FXT_512)
+zephyr_compile_definitions_ifdef(CONFIG_CMSIS_DSP_TABLES_CFFT_Q15_1024 ARM_TABLE_TWIDDLECOEF_Q15_1024)
+zephyr_compile_definitions_ifdef(CONFIG_CMSIS_DSP_TABLES_CFFT_Q15_1024 ARM_TABLE_BITREVIDX_FXT_1024)
+zephyr_compile_definitions_ifdef(CONFIG_CMSIS_DSP_TABLES_CFFT_Q15_2048 ARM_TABLE_TWIDDLECOEF_Q15_2048)
+zephyr_compile_definitions_ifdef(CONFIG_CMSIS_DSP_TABLES_CFFT_Q15_2048 ARM_TABLE_BITREVIDX_FXT_2048)
+zephyr_compile_definitions_ifdef(CONFIG_CMSIS_DSP_TABLES_CFFT_Q15_4096 ARM_TABLE_TWIDDLECOEF_Q15_4096)
+zephyr_compile_definitions_ifdef(CONFIG_CMSIS_DSP_TABLES_CFFT_Q15_4096 ARM_TABLE_BITREVIDX_FXT_4096)
+
+zephyr_compile_definitions_ifdef(CONFIG_CMSIS_DSP_TABLES_RFFT_FAST_F64_32 ARM_TABLE_TWIDDLECOEF_F64_16)
+zephyr_compile_definitions_ifdef(CONFIG_CMSIS_DSP_TABLES_RFFT_FAST_F64_32 ARM_TABLE_BITREVIDX_FLT64_16)
+zephyr_compile_definitions_ifdef(CONFIG_CMSIS_DSP_TABLES_RFFT_FAST_F64_32 ARM_TABLE_TWIDDLECOEF_RFFT_F64_32)
+zephyr_compile_definitions_ifdef(CONFIG_CMSIS_DSP_TABLES_RFFT_FAST_F64_64 ARM_TABLE_TWIDDLECOEF_F64_32)
+zephyr_compile_definitions_ifdef(CONFIG_CMSIS_DSP_TABLES_RFFT_FAST_F64_64 ARM_TABLE_BITREVIDX_FLT64_32)
+zephyr_compile_definitions_ifdef(CONFIG_CMSIS_DSP_TABLES_RFFT_FAST_F64_64 ARM_TABLE_TWIDDLECOEF_RFFT_F64_64)
+zephyr_compile_definitions_ifdef(CONFIG_CMSIS_DSP_TABLES_RFFT_FAST_F64_128 ARM_TABLE_TWIDDLECOEF_F64_64)
+zephyr_compile_definitions_ifdef(CONFIG_CMSIS_DSP_TABLES_RFFT_FAST_F64_128 ARM_TABLE_BITREVIDX_FLT64_64)
+zephyr_compile_definitions_ifdef(CONFIG_CMSIS_DSP_TABLES_RFFT_FAST_F64_128 ARM_TABLE_TWIDDLECOEF_RFFT_F64_128)
+zephyr_compile_definitions_ifdef(CONFIG_CMSIS_DSP_TABLES_RFFT_FAST_F64_256 ARM_TABLE_TWIDDLECOEF_F64_128)
+zephyr_compile_definitions_ifdef(CONFIG_CMSIS_DSP_TABLES_RFFT_FAST_F64_256 ARM_TABLE_BITREVIDX_FLT64_128)
+zephyr_compile_definitions_ifdef(CONFIG_CMSIS_DSP_TABLES_RFFT_FAST_F64_256 ARM_TABLE_TWIDDLECOEF_RFFT_F64_256)
+zephyr_compile_definitions_ifdef(CONFIG_CMSIS_DSP_TABLES_RFFT_FAST_F64_512 ARM_TABLE_TWIDDLECOEF_F64_256)
+zephyr_compile_definitions_ifdef(CONFIG_CMSIS_DSP_TABLES_RFFT_FAST_F64_512 ARM_TABLE_BITREVIDX_FLT64_256)
+zephyr_compile_definitions_ifdef(CONFIG_CMSIS_DSP_TABLES_RFFT_FAST_F64_512 ARM_TABLE_TWIDDLECOEF_RFFT_F64_512)
+zephyr_compile_definitions_ifdef(CONFIG_CMSIS_DSP_TABLES_RFFT_FAST_F64_1024 ARM_TABLE_TWIDDLECOEF_F64_512)
+zephyr_compile_definitions_ifdef(CONFIG_CMSIS_DSP_TABLES_RFFT_FAST_F64_1024 ARM_TABLE_BITREVIDX_FLT64_512)
+zephyr_compile_definitions_ifdef(CONFIG_CMSIS_DSP_TABLES_RFFT_FAST_F64_1024 ARM_TABLE_TWIDDLECOEF_RFFT_F64_1024)
+zephyr_compile_definitions_ifdef(CONFIG_CMSIS_DSP_TABLES_RFFT_FAST_F64_2048 ARM_TABLE_TWIDDLECOEF_F64_1024)
+zephyr_compile_definitions_ifdef(CONFIG_CMSIS_DSP_TABLES_RFFT_FAST_F64_2048 ARM_TABLE_BITREVIDX_FLT64_1024)
+zephyr_compile_definitions_ifdef(CONFIG_CMSIS_DSP_TABLES_RFFT_FAST_F64_2048 ARM_TABLE_TWIDDLECOEF_RFFT_F64_2048)
+zephyr_compile_definitions_ifdef(CONFIG_CMSIS_DSP_TABLES_RFFT_FAST_F64_4096 ARM_TABLE_TWIDDLECOEF_F64_2048)
+zephyr_compile_definitions_ifdef(CONFIG_CMSIS_DSP_TABLES_RFFT_FAST_F64_4096 ARM_TABLE_BITREVIDX_FLT64_2048)
+zephyr_compile_definitions_ifdef(CONFIG_CMSIS_DSP_TABLES_RFFT_FAST_F64_4096 ARM_TABLE_TWIDDLECOEF_RFFT_F64_4096)
+
+zephyr_compile_definitions_ifdef(CONFIG_CMSIS_DSP_TABLES_RFFT_FAST_F32_32 ARM_TABLE_TWIDDLECOEF_F32_16)
+zephyr_compile_definitions_ifdef(CONFIG_CMSIS_DSP_TABLES_RFFT_FAST_F32_32 ARM_TABLE_BITREVIDX_FLT_16)
+zephyr_compile_definitions_ifdef(CONFIG_CMSIS_DSP_TABLES_RFFT_FAST_F32_32 ARM_TABLE_TWIDDLECOEF_RFFT_F32_32)
+zephyr_compile_definitions_ifdef(CONFIG_CMSIS_DSP_TABLES_RFFT_FAST_F32_64 ARM_TABLE_TWIDDLECOEF_F32_32)
+zephyr_compile_definitions_ifdef(CONFIG_CMSIS_DSP_TABLES_RFFT_FAST_F32_64 ARM_TABLE_BITREVIDX_FLT_32)
+zephyr_compile_definitions_ifdef(CONFIG_CMSIS_DSP_TABLES_RFFT_FAST_F32_64 ARM_TABLE_TWIDDLECOEF_RFFT_F32_64)
+zephyr_compile_definitions_ifdef(CONFIG_CMSIS_DSP_TABLES_RFFT_FAST_F32_128 ARM_TABLE_TWIDDLECOEF_F32_64)
+zephyr_compile_definitions_ifdef(CONFIG_CMSIS_DSP_TABLES_RFFT_FAST_F32_128 ARM_TABLE_BITREVIDX_FLT_64)
+zephyr_compile_definitions_ifdef(CONFIG_CMSIS_DSP_TABLES_RFFT_FAST_F32_128 ARM_TABLE_TWIDDLECOEF_RFFT_F32_128)
+zephyr_compile_definitions_ifdef(CONFIG_CMSIS_DSP_TABLES_RFFT_FAST_F32_256 ARM_TABLE_TWIDDLECOEF_F32_128)
+zephyr_compile_definitions_ifdef(CONFIG_CMSIS_DSP_TABLES_RFFT_FAST_F32_256 ARM_TABLE_BITREVIDX_FLT_128)
+zephyr_compile_definitions_ifdef(CONFIG_CMSIS_DSP_TABLES_RFFT_FAST_F32_256 ARM_TABLE_TWIDDLECOEF_RFFT_F32_256)
+zephyr_compile_definitions_ifdef(CONFIG_CMSIS_DSP_TABLES_RFFT_FAST_F32_512 ARM_TABLE_TWIDDLECOEF_F32_256)
+zephyr_compile_definitions_ifdef(CONFIG_CMSIS_DSP_TABLES_RFFT_FAST_F32_512 ARM_TABLE_BITREVIDX_FLT_256)
+zephyr_compile_definitions_ifdef(CONFIG_CMSIS_DSP_TABLES_RFFT_FAST_F32_512 ARM_TABLE_TWIDDLECOEF_RFFT_F32_512)
+zephyr_compile_definitions_ifdef(CONFIG_CMSIS_DSP_TABLES_RFFT_FAST_F32_1024 ARM_TABLE_TWIDDLECOEF_F32_512)
+zephyr_compile_definitions_ifdef(CONFIG_CMSIS_DSP_TABLES_RFFT_FAST_F32_1024 ARM_TABLE_BITREVIDX_FLT_512)
+zephyr_compile_definitions_ifdef(CONFIG_CMSIS_DSP_TABLES_RFFT_FAST_F32_1024 ARM_TABLE_TWIDDLECOEF_RFFT_F32_1024)
+zephyr_compile_definitions_ifdef(CONFIG_CMSIS_DSP_TABLES_RFFT_FAST_F32_2048 ARM_TABLE_TWIDDLECOEF_F32_1024)
+zephyr_compile_definitions_ifdef(CONFIG_CMSIS_DSP_TABLES_RFFT_FAST_F32_2048 ARM_TABLE_BITREVIDX_FLT_1024)
+zephyr_compile_definitions_ifdef(CONFIG_CMSIS_DSP_TABLES_RFFT_FAST_F32_2048 ARM_TABLE_TWIDDLECOEF_RFFT_F32_2048)
+zephyr_compile_definitions_ifdef(CONFIG_CMSIS_DSP_TABLES_RFFT_FAST_F32_4096 ARM_TABLE_TWIDDLECOEF_F32_2048)
+zephyr_compile_definitions_ifdef(CONFIG_CMSIS_DSP_TABLES_RFFT_FAST_F32_4096 ARM_TABLE_BITREVIDX_FLT_2048)
+zephyr_compile_definitions_ifdef(CONFIG_CMSIS_DSP_TABLES_RFFT_FAST_F32_4096 ARM_TABLE_TWIDDLECOEF_RFFT_F32_4096)
+
+zephyr_compile_definitions_ifdef(CONFIG_CMSIS_DSP_TABLES_RFFT_F32_128 ARM_TABLE_REALCOEF_F32)
+zephyr_compile_definitions_ifdef(CONFIG_CMSIS_DSP_TABLES_RFFT_F32_128 ARM_TABLE_BITREV_1024)
+zephyr_compile_definitions_ifdef(CONFIG_CMSIS_DSP_TABLES_RFFT_F32_128 ARM_TABLE_TWIDDLECOEF_F32_4096)
+zephyr_compile_definitions_ifdef(CONFIG_CMSIS_DSP_TABLES_RFFT_F32_512 ARM_TABLE_REALCOEF_F32)
+zephyr_compile_definitions_ifdef(CONFIG_CMSIS_DSP_TABLES_RFFT_F32_512 ARM_TABLE_BITREV_1024)
+zephyr_compile_definitions_ifdef(CONFIG_CMSIS_DSP_TABLES_RFFT_F32_512 ARM_TABLE_TWIDDLECOEF_F32_4096)
+zephyr_compile_definitions_ifdef(CONFIG_CMSIS_DSP_TABLES_RFFT_F32_2048 ARM_TABLE_REALCOEF_F32)
+zephyr_compile_definitions_ifdef(CONFIG_CMSIS_DSP_TABLES_RFFT_F32_2048 ARM_TABLE_BITREV_1024)
+zephyr_compile_definitions_ifdef(CONFIG_CMSIS_DSP_TABLES_RFFT_F32_2048 ARM_TABLE_TWIDDLECOEF_F32_4096)
+zephyr_compile_definitions_ifdef(CONFIG_CMSIS_DSP_TABLES_RFFT_F32_8192 ARM_TABLE_REALCOEF_F32)
+zephyr_compile_definitions_ifdef(CONFIG_CMSIS_DSP_TABLES_RFFT_F32_8192 ARM_TABLE_BITREV_1024)
+zephyr_compile_definitions_ifdef(CONFIG_CMSIS_DSP_TABLES_RFFT_F32_8192 ARM_TABLE_TWIDDLECOEF_F32_4096)
+
+zephyr_compile_definitions_ifdef(CONFIG_CMSIS_DSP_TABLES_RFFT_Q31_32 ARM_TABLE_REALCOEF_Q31)
+zephyr_compile_definitions_ifdef(CONFIG_CMSIS_DSP_TABLES_RFFT_Q31_32 ARM_TABLE_TWIDDLECOEF_Q31_16)
+zephyr_compile_definitions_ifdef(CONFIG_CMSIS_DSP_TABLES_RFFT_Q31_32 ARM_TABLE_BITREVIDX_FXT_16)
+zephyr_compile_definitions_ifdef(CONFIG_CMSIS_DSP_TABLES_RFFT_Q31_64 ARM_TABLE_REALCOEF_Q31)
+zephyr_compile_definitions_ifdef(CONFIG_CMSIS_DSP_TABLES_RFFT_Q31_64 ARM_TABLE_TWIDDLECOEF_Q31_32)
+zephyr_compile_definitions_ifdef(CONFIG_CMSIS_DSP_TABLES_RFFT_Q31_64 ARM_TABLE_BITREVIDX_FXT_32)
+zephyr_compile_definitions_ifdef(CONFIG_CMSIS_DSP_TABLES_RFFT_Q31_128 ARM_TABLE_REALCOEF_Q31)
+zephyr_compile_definitions_ifdef(CONFIG_CMSIS_DSP_TABLES_RFFT_Q31_128 ARM_TABLE_TWIDDLECOEF_Q31_64)
+zephyr_compile_definitions_ifdef(CONFIG_CMSIS_DSP_TABLES_RFFT_Q31_128 ARM_TABLE_BITREVIDX_FXT_64)
+zephyr_compile_definitions_ifdef(CONFIG_CMSIS_DSP_TABLES_RFFT_Q31_256 ARM_TABLE_REALCOEF_Q31)
+zephyr_compile_definitions_ifdef(CONFIG_CMSIS_DSP_TABLES_RFFT_Q31_256 ARM_TABLE_TWIDDLECOEF_Q31_128)
+zephyr_compile_definitions_ifdef(CONFIG_CMSIS_DSP_TABLES_RFFT_Q31_256 ARM_TABLE_BITREVIDX_FXT_128)
+zephyr_compile_definitions_ifdef(CONFIG_CMSIS_DSP_TABLES_RFFT_Q31_512 ARM_TABLE_REALCOEF_Q31)
+zephyr_compile_definitions_ifdef(CONFIG_CMSIS_DSP_TABLES_RFFT_Q31_512 ARM_TABLE_TWIDDLECOEF_Q31_256)
+zephyr_compile_definitions_ifdef(CONFIG_CMSIS_DSP_TABLES_RFFT_Q31_512 ARM_TABLE_BITREVIDX_FXT_256)
+zephyr_compile_definitions_ifdef(CONFIG_CMSIS_DSP_TABLES_RFFT_Q31_1024 ARM_TABLE_REALCOEF_Q31)
+zephyr_compile_definitions_ifdef(CONFIG_CMSIS_DSP_TABLES_RFFT_Q31_1024 ARM_TABLE_TWIDDLECOEF_Q31_512)
+zephyr_compile_definitions_ifdef(CONFIG_CMSIS_DSP_TABLES_RFFT_Q31_1024 ARM_TABLE_BITREVIDX_FXT_512)
+zephyr_compile_definitions_ifdef(CONFIG_CMSIS_DSP_TABLES_RFFT_Q31_2048 ARM_TABLE_REALCOEF_Q31)
+zephyr_compile_definitions_ifdef(CONFIG_CMSIS_DSP_TABLES_RFFT_Q31_2048 ARM_TABLE_TWIDDLECOEF_Q31_1024)
+zephyr_compile_definitions_ifdef(CONFIG_CMSIS_DSP_TABLES_RFFT_Q31_2048 ARM_TABLE_BITREVIDX_FXT_1024)
+zephyr_compile_definitions_ifdef(CONFIG_CMSIS_DSP_TABLES_RFFT_Q31_4096 ARM_TABLE_REALCOEF_Q31)
+zephyr_compile_definitions_ifdef(CONFIG_CMSIS_DSP_TABLES_RFFT_Q31_4096 ARM_TABLE_TWIDDLECOEF_Q31_2048)
+zephyr_compile_definitions_ifdef(CONFIG_CMSIS_DSP_TABLES_RFFT_Q31_4096 ARM_TABLE_BITREVIDX_FXT_2048)
+zephyr_compile_definitions_ifdef(CONFIG_CMSIS_DSP_TABLES_RFFT_Q31_8192 ARM_TABLE_REALCOEF_Q31)
+zephyr_compile_definitions_ifdef(CONFIG_CMSIS_DSP_TABLES_RFFT_Q31_8192 ARM_TABLE_TWIDDLECOEF_Q31_4096)
+zephyr_compile_definitions_ifdef(CONFIG_CMSIS_DSP_TABLES_RFFT_Q31_8192 ARM_TABLE_BITREVIDX_FXT_4096)
+
+zephyr_compile_definitions_ifdef(CONFIG_CMSIS_DSP_TABLES_RFFT_Q15_32 ARM_TABLE_REALCOEF_Q15)
+zephyr_compile_definitions_ifdef(CONFIG_CMSIS_DSP_TABLES_RFFT_Q15_32 ARM_TABLE_TWIDDLECOEF_Q15_16)
+zephyr_compile_definitions_ifdef(CONFIG_CMSIS_DSP_TABLES_RFFT_Q15_32 ARM_TABLE_BITREVIDX_FXT_16)
+zephyr_compile_definitions_ifdef(CONFIG_CMSIS_DSP_TABLES_RFFT_Q15_64 ARM_TABLE_REALCOEF_Q15)
+zephyr_compile_definitions_ifdef(CONFIG_CMSIS_DSP_TABLES_RFFT_Q15_64 ARM_TABLE_TWIDDLECOEF_Q15_32)
+zephyr_compile_definitions_ifdef(CONFIG_CMSIS_DSP_TABLES_RFFT_Q15_64 ARM_TABLE_BITREVIDX_FXT_32)
+zephyr_compile_definitions_ifdef(CONFIG_CMSIS_DSP_TABLES_RFFT_Q15_128 ARM_TABLE_REALCOEF_Q15)
+zephyr_compile_definitions_ifdef(CONFIG_CMSIS_DSP_TABLES_RFFT_Q15_128 ARM_TABLE_TWIDDLECOEF_Q15_64)
+zephyr_compile_definitions_ifdef(CONFIG_CMSIS_DSP_TABLES_RFFT_Q15_128 ARM_TABLE_BITREVIDX_FXT_64)
+zephyr_compile_definitions_ifdef(CONFIG_CMSIS_DSP_TABLES_RFFT_Q15_256 ARM_TABLE_REALCOEF_Q15)
+zephyr_compile_definitions_ifdef(CONFIG_CMSIS_DSP_TABLES_RFFT_Q15_256 ARM_TABLE_TWIDDLECOEF_Q15_128)
+zephyr_compile_definitions_ifdef(CONFIG_CMSIS_DSP_TABLES_RFFT_Q15_256 ARM_TABLE_BITREVIDX_FXT_128)
+zephyr_compile_definitions_ifdef(CONFIG_CMSIS_DSP_TABLES_RFFT_Q15_512 ARM_TABLE_REALCOEF_Q15)
+zephyr_compile_definitions_ifdef(CONFIG_CMSIS_DSP_TABLES_RFFT_Q15_512 ARM_TABLE_TWIDDLECOEF_Q15_256)
+zephyr_compile_definitions_ifdef(CONFIG_CMSIS_DSP_TABLES_RFFT_Q15_512 ARM_TABLE_BITREVIDX_FXT_256)
+zephyr_compile_definitions_ifdef(CONFIG_CMSIS_DSP_TABLES_RFFT_Q15_1024 ARM_TABLE_REALCOEF_Q15)
+zephyr_compile_definitions_ifdef(CONFIG_CMSIS_DSP_TABLES_RFFT_Q15_1024 ARM_TABLE_TWIDDLECOEF_Q15_512)
+zephyr_compile_definitions_ifdef(CONFIG_CMSIS_DSP_TABLES_RFFT_Q15_1024 ARM_TABLE_BITREVIDX_FXT_512)
+zephyr_compile_definitions_ifdef(CONFIG_CMSIS_DSP_TABLES_RFFT_Q15_2048 ARM_TABLE_REALCOEF_Q15)
+zephyr_compile_definitions_ifdef(CONFIG_CMSIS_DSP_TABLES_RFFT_Q15_2048 ARM_TABLE_TWIDDLECOEF_Q15_1024)
+zephyr_compile_definitions_ifdef(CONFIG_CMSIS_DSP_TABLES_RFFT_Q15_2048 ARM_TABLE_BITREVIDX_FXT_1024)
+zephyr_compile_definitions_ifdef(CONFIG_CMSIS_DSP_TABLES_RFFT_Q15_4096 ARM_TABLE_REALCOEF_Q15)
+zephyr_compile_definitions_ifdef(CONFIG_CMSIS_DSP_TABLES_RFFT_Q15_4096 ARM_TABLE_TWIDDLECOEF_Q15_2048)
+zephyr_compile_definitions_ifdef(CONFIG_CMSIS_DSP_TABLES_RFFT_Q15_4096 ARM_TABLE_BITREVIDX_FXT_2048)
+zephyr_compile_definitions_ifdef(CONFIG_CMSIS_DSP_TABLES_RFFT_Q15_8192 ARM_TABLE_REALCOEF_Q15)
+zephyr_compile_definitions_ifdef(CONFIG_CMSIS_DSP_TABLES_RFFT_Q15_8192 ARM_TABLE_TWIDDLECOEF_Q15_4096)
+zephyr_compile_definitions_ifdef(CONFIG_CMSIS_DSP_TABLES_RFFT_Q15_8192 ARM_TABLE_BITREVIDX_FXT_4096)
+
+zephyr_compile_definitions_ifdef(CONFIG_CMSIS_DSP_TABLES_DCT4_F32_128 ARM_TABLE_DCT4_F32_128)
+zephyr_compile_definitions_ifdef(CONFIG_CMSIS_DSP_TABLES_DCT4_F32_128 ARM_TABLE_REALCOEF_F32)
+zephyr_compile_definitions_ifdef(CONFIG_CMSIS_DSP_TABLES_DCT4_F32_128 ARM_TABLE_BITREV_1024)
+zephyr_compile_definitions_ifdef(CONFIG_CMSIS_DSP_TABLES_DCT4_F32_128 ARM_TABLE_TWIDDLECOEF_F32_4096)
+zephyr_compile_definitions_ifdef(CONFIG_CMSIS_DSP_TABLES_DCT4_F32_512 ARM_TABLE_DCT4_F32_512)
+zephyr_compile_definitions_ifdef(CONFIG_CMSIS_DSP_TABLES_DCT4_F32_512 ARM_TABLE_REALCOEF_F32)
+zephyr_compile_definitions_ifdef(CONFIG_CMSIS_DSP_TABLES_DCT4_F32_512 ARM_TABLE_BITREV_1024)
+zephyr_compile_definitions_ifdef(CONFIG_CMSIS_DSP_TABLES_DCT4_F32_512 ARM_TABLE_TWIDDLECOEF_F32_4096)
+zephyr_compile_definitions_ifdef(CONFIG_CMSIS_DSP_TABLES_DCT4_F32_2048 ARM_TABLE_DCT4_F32_2048)
+zephyr_compile_definitions_ifdef(CONFIG_CMSIS_DSP_TABLES_DCT4_F32_2048 ARM_TABLE_REALCOEF_F32)
+zephyr_compile_definitions_ifdef(CONFIG_CMSIS_DSP_TABLES_DCT4_F32_2048 ARM_TABLE_BITREV_1024)
+zephyr_compile_definitions_ifdef(CONFIG_CMSIS_DSP_TABLES_DCT4_F32_2048 ARM_TABLE_TWIDDLECOEF_F32_4096)
+zephyr_compile_definitions_ifdef(CONFIG_CMSIS_DSP_TABLES_DCT4_F32_8192 ARM_TABLE_DCT4_F32_8192)
+zephyr_compile_definitions_ifdef(CONFIG_CMSIS_DSP_TABLES_DCT4_F32_8192 ARM_TABLE_REALCOEF_F32)
+zephyr_compile_definitions_ifdef(CONFIG_CMSIS_DSP_TABLES_DCT4_F32_8192 ARM_TABLE_BITREV_1024)
+zephyr_compile_definitions_ifdef(CONFIG_CMSIS_DSP_TABLES_DCT4_F32_8192 ARM_TABLE_TWIDDLECOEF_F32_4096)
+
+zephyr_compile_definitions_ifdef(CONFIG_CMSIS_DSP_TABLES_DCT4_Q31_128 ARM_TABLE_DCT4_Q31_128)
+zephyr_compile_definitions_ifdef(CONFIG_CMSIS_DSP_TABLES_DCT4_Q31_128 ARM_TABLE_REALCOEF_Q31)
+zephyr_compile_definitions_ifdef(CONFIG_CMSIS_DSP_TABLES_DCT4_Q31_128 ARM_TABLE_BITREV_1024)
+zephyr_compile_definitions_ifdef(CONFIG_CMSIS_DSP_TABLES_DCT4_Q31_128 ARM_TABLE_TWIDDLECOEF_Q31_4096)
+zephyr_compile_definitions_ifdef(CONFIG_CMSIS_DSP_TABLES_DCT4_Q31_512 ARM_TABLE_DCT4_Q31_512)
+zephyr_compile_definitions_ifdef(CONFIG_CMSIS_DSP_TABLES_DCT4_Q31_512 ARM_TABLE_REALCOEF_Q31)
+zephyr_compile_definitions_ifdef(CONFIG_CMSIS_DSP_TABLES_DCT4_Q31_512 ARM_TABLE_BITREV_1024)
+zephyr_compile_definitions_ifdef(CONFIG_CMSIS_DSP_TABLES_DCT4_Q31_512 ARM_TABLE_TWIDDLECOEF_Q31_4096)
+zephyr_compile_definitions_ifdef(CONFIG_CMSIS_DSP_TABLES_DCT4_Q31_2048 ARM_TABLE_DCT4_Q31_2048)
+zephyr_compile_definitions_ifdef(CONFIG_CMSIS_DSP_TABLES_DCT4_Q31_2048 ARM_TABLE_REALCOEF_Q31)
+zephyr_compile_definitions_ifdef(CONFIG_CMSIS_DSP_TABLES_DCT4_Q31_2048 ARM_TABLE_BITREV_1024)
+zephyr_compile_definitions_ifdef(CONFIG_CMSIS_DSP_TABLES_DCT4_Q31_2048 ARM_TABLE_TWIDDLECOEF_Q31_4096)
+zephyr_compile_definitions_ifdef(CONFIG_CMSIS_DSP_TABLES_DCT4_Q31_8192 ARM_TABLE_DCT4_Q31_8192)
+zephyr_compile_definitions_ifdef(CONFIG_CMSIS_DSP_TABLES_DCT4_Q31_8192 ARM_TABLE_REALCOEF_Q31)
+zephyr_compile_definitions_ifdef(CONFIG_CMSIS_DSP_TABLES_DCT4_Q31_8192 ARM_TABLE_BITREV_1024)
+zephyr_compile_definitions_ifdef(CONFIG_CMSIS_DSP_TABLES_DCT4_Q31_8192 ARM_TABLE_TWIDDLECOEF_Q31_4096)
+
+zephyr_compile_definitions_ifdef(CONFIG_CMSIS_DSP_TABLES_DCT4_Q15_128 ARM_TABLE_DCT4_Q15_128)
+zephyr_compile_definitions_ifdef(CONFIG_CMSIS_DSP_TABLES_DCT4_Q15_128 ARM_TABLE_REALCOEF_Q15)
+zephyr_compile_definitions_ifdef(CONFIG_CMSIS_DSP_TABLES_DCT4_Q15_128 ARM_TABLE_BITREV_1024)
+zephyr_compile_definitions_ifdef(CONFIG_CMSIS_DSP_TABLES_DCT4_Q15_128 ARM_TABLE_TWIDDLECOEF_Q15_4096)
+zephyr_compile_definitions_ifdef(CONFIG_CMSIS_DSP_TABLES_DCT4_Q15_512 ARM_TABLE_DCT4_Q15_512)
+zephyr_compile_definitions_ifdef(CONFIG_CMSIS_DSP_TABLES_DCT4_Q15_512 ARM_TABLE_REALCOEF_Q15)
+zephyr_compile_definitions_ifdef(CONFIG_CMSIS_DSP_TABLES_DCT4_Q15_512 ARM_TABLE_BITREV_1024)
+zephyr_compile_definitions_ifdef(CONFIG_CMSIS_DSP_TABLES_DCT4_Q15_512 ARM_TABLE_TWIDDLECOEF_Q15_4096)
+zephyr_compile_definitions_ifdef(CONFIG_CMSIS_DSP_TABLES_DCT4_Q15_2048 ARM_TABLE_DCT4_Q15_2048)
+zephyr_compile_definitions_ifdef(CONFIG_CMSIS_DSP_TABLES_DCT4_Q15_2048 ARM_TABLE_REALCOEF_Q15)
+zephyr_compile_definitions_ifdef(CONFIG_CMSIS_DSP_TABLES_DCT4_Q15_2048 ARM_TABLE_BITREV_1024)
+zephyr_compile_definitions_ifdef(CONFIG_CMSIS_DSP_TABLES_DCT4_Q15_2048 ARM_TABLE_TWIDDLECOEF_Q15_4096)
+zephyr_compile_definitions_ifdef(CONFIG_CMSIS_DSP_TABLES_DCT4_Q15_8192 ARM_TABLE_DCT4_Q15_8192)
+zephyr_compile_definitions_ifdef(CONFIG_CMSIS_DSP_TABLES_DCT4_Q15_8192 ARM_TABLE_REALCOEF_Q15)
+zephyr_compile_definitions_ifdef(CONFIG_CMSIS_DSP_TABLES_DCT4_Q15_8192 ARM_TABLE_BITREV_1024)
+zephyr_compile_definitions_ifdef(CONFIG_CMSIS_DSP_TABLES_DCT4_Q15_8192 ARM_TABLE_TWIDDLECOEF_Q15_4096)
+
+# CMSIS-DSP Components
+add_subdirectory_ifdef(CONFIG_CMSIS_DSP_BASICMATH BasicMathFunctions)
+add_subdirectory_ifdef(CONFIG_CMSIS_DSP_COMPLEXMATH ComplexMathFunctions)
+add_subdirectory_ifdef(CONFIG_CMSIS_DSP_CONTROLLER ControllerFunctions)
+add_subdirectory_ifdef(CONFIG_CMSIS_DSP_FASTMATH FastMathFunctions)
+add_subdirectory_ifdef(CONFIG_CMSIS_DSP_FILTERING FilteringFunctions)
+add_subdirectory_ifdef(CONFIG_CMSIS_DSP_MATRIX MatrixFunctions)
+add_subdirectory_ifdef(CONFIG_CMSIS_DSP_STATISTICS StatisticsFunctions)
+add_subdirectory_ifdef(CONFIG_CMSIS_DSP_SUPPORT SupportFunctions)
+add_subdirectory_ifdef(CONFIG_CMSIS_DSP_TRANSFORM TransformFunctions)
+add_subdirectory_ifdef(CONFIG_CMSIS_DSP_SVM SVMFunctions)
+add_subdirectory_ifdef(CONFIG_CMSIS_DSP_BAYES BayesFunctions)
+add_subdirectory_ifdef(CONFIG_CMSIS_DSP_DISTANCE DistanceFunctions)
+add_subdirectory_ifdef(CONFIG_CMSIS_DSP_TABLES CommonTables)
diff --git a/CMSIS/DSP/Source/CommonTables/CMakeLists.txt b/CMSIS/DSP/Source/CommonTables/CMakeLists.txt
new file mode 100644
index 0000000..17c0aed
--- /dev/null
+++ b/CMSIS/DSP/Source/CommonTables/CMakeLists.txt
@@ -0,0 +1,10 @@
+# Copyright (c) 2019 Stephanos Ioannidis <root@stephanos.io>
+# SPDX-License-Identifier: Apache-2.0
+
+zephyr_library()
+
+zephyr_library_sources(
+ arm_common_tables.c
+ arm_const_structs.c
+ arm_mve_tables.c
+ )
diff --git a/CMSIS/DSP/Source/ComplexMathFunctions/CMakeLists.txt b/CMSIS/DSP/Source/ComplexMathFunctions/CMakeLists.txt
new file mode 100644
index 0000000..2e0d03a
--- /dev/null
+++ b/CMSIS/DSP/Source/ComplexMathFunctions/CMakeLists.txt
@@ -0,0 +1,26 @@
+# Copyright (c) 2020 Stephanos Ioannidis <root@stephanos.io>
+# SPDX-License-Identifier: Apache-2.0
+
+zephyr_library()
+
+zephyr_library_sources(
+ arm_cmplx_conj_f32.c
+ arm_cmplx_conj_q15.c
+ arm_cmplx_conj_q31.c
+ arm_cmplx_dot_prod_f32.c
+ arm_cmplx_dot_prod_q15.c
+ arm_cmplx_dot_prod_q31.c
+ arm_cmplx_mag_f32.c
+ arm_cmplx_mag_squared_f32.c
+ arm_cmplx_mag_squared_q15.c
+ arm_cmplx_mag_squared_q31.c
+ arm_cmplx_mult_cmplx_f32.c
+ arm_cmplx_mult_cmplx_q15.c
+ arm_cmplx_mult_cmplx_q31.c
+ arm_cmplx_mult_real_f32.c
+ arm_cmplx_mult_real_q15.c
+ arm_cmplx_mult_real_q31.c
+ )
+
+zephyr_library_sources_ifdef(CONFIG_CMSIS_DSP_TABLES_ARM_CMPLX_MAG_Q31 arm_cmplx_mag_q31.c)
+zephyr_library_sources_ifdef(CONFIG_CMSIS_DSP_TABLES_ARM_CMPLX_MAG_Q15 arm_cmplx_mag_q15.c)
diff --git a/CMSIS/DSP/Source/ControllerFunctions/CMakeLists.txt b/CMSIS/DSP/Source/ControllerFunctions/CMakeLists.txt
new file mode 100644
index 0000000..634061e
--- /dev/null
+++ b/CMSIS/DSP/Source/ControllerFunctions/CMakeLists.txt
@@ -0,0 +1,16 @@
+# Copyright (c) 2020 Stephanos Ioannidis <root@stephanos.io>
+# SPDX-License-Identifier: Apache-2.0
+
+zephyr_library()
+
+zephyr_library_sources(
+ arm_pid_init_f32.c
+ arm_pid_init_q15.c
+ arm_pid_init_q31.c
+ arm_pid_reset_f32.c
+ arm_pid_reset_q15.c
+ arm_pid_reset_q31.c
+ )
+
+zephyr_library_sources_ifdef(CMSIS_DSP_TABLES_ARM_SIN_COS_F32 arm_sin_cos_f32.c)
+zephyr_library_sources_ifdef(CMSIS_DSP_TABLES_ARM_SIN_COS_Q31 arm_sin_cos_q31.c)
diff --git a/CMSIS/DSP/Source/DistanceFunctions/CMakeLists.txt b/CMSIS/DSP/Source/DistanceFunctions/CMakeLists.txt
new file mode 100644
index 0000000..887b943
--- /dev/null
+++ b/CMSIS/DSP/Source/DistanceFunctions/CMakeLists.txt
@@ -0,0 +1,27 @@
+# Copyright (c) 2020 Stephanos Ioannidis <root@stephanos.io>
+# SPDX-License-Identifier: Apache-2.0
+
+zephyr_library()
+
+zephyr_library_sources(
+ arm_boolean_distance.c
+ arm_boolean_distance_template.h
+ arm_braycurtis_distance_f32.c
+ arm_canberra_distance_f32.c
+ arm_chebyshev_distance_f32.c
+ arm_cityblock_distance_f32.c
+ arm_correlation_distance_f32.c
+ arm_cosine_distance_f32.c
+ arm_dice_distance.c
+ arm_euclidean_distance_f32.c
+ arm_hamming_distance.c
+ arm_jaccard_distance.c
+ arm_jensenshannon_distance_f32.c
+ arm_kulsinski_distance.c
+ arm_minkowski_distance_f32.c
+ arm_rogerstanimoto_distance.c
+ arm_russellrao_distance.c
+ arm_sokalmichener_distance.c
+ arm_sokalsneath_distance.c
+ arm_yule_distance.c
+ )
diff --git a/CMSIS/DSP/Source/FastMathFunctions/CMakeLists.txt b/CMSIS/DSP/Source/FastMathFunctions/CMakeLists.txt
new file mode 100644
index 0000000..3ce2ef6
--- /dev/null
+++ b/CMSIS/DSP/Source/FastMathFunctions/CMakeLists.txt
@@ -0,0 +1,18 @@
+# Copyright (c) 2020 Stephanos Ioannidis <root@stephanos.io>
+# SPDX-License-Identifier: Apache-2.0
+
+zephyr_library()
+
+zephyr_library_sources(
+ arm_sqrt_q15.c
+ arm_sqrt_q31.c
+ arm_vexp_f32.c
+ arm_vlog_f32.c
+ )
+
+zephyr_library_sources_ifdef(CONFIG_CMSIS_DSP_TABLES_ARM_COS_F32 arm_cos_f32.c)
+zephyr_library_sources_ifdef(CONFIG_CMSIS_DSP_TABLES_ARM_COS_Q31 arm_cos_q31.c)
+zephyr_library_sources_ifdef(CONFIG_CMSIS_DSP_TABLES_ARM_COS_Q15 arm_cos_q15.c)
+zephyr_library_sources_ifdef(CONFIG_CMSIS_DSP_TABLES_ARM_SIN_F32 arm_sin_f32.c)
+zephyr_library_sources_ifdef(CONFIG_CMSIS_DSP_TABLES_ARM_SIN_Q31 arm_sin_q31.c)
+zephyr_library_sources_ifdef(CONFIG_CMSIS_DSP_TABLES_ARM_SIN_Q15 arm_sin_q15.c)
diff --git a/CMSIS/DSP/Source/FilteringFunctions/CMakeLists.txt b/CMSIS/DSP/Source/FilteringFunctions/CMakeLists.txt
new file mode 100644
index 0000000..3fb5a45
--- /dev/null
+++ b/CMSIS/DSP/Source/FilteringFunctions/CMakeLists.txt
@@ -0,0 +1,107 @@
+# Copyright (c) 2020 Stephanos Ioannidis <root@stephanos.io>
+# SPDX-License-Identifier: Apache-2.0
+
+zephyr_library()
+
+zephyr_library_sources(
+ arm_biquad_cascade_df1_32x64_init_q31.c
+ arm_biquad_cascade_df1_32x64_q31.c
+ arm_biquad_cascade_df1_f32.c
+ arm_biquad_cascade_df1_fast_q15.c
+ arm_biquad_cascade_df1_fast_q31.c
+ arm_biquad_cascade_df1_init_f32.c
+ arm_biquad_cascade_df1_init_q15.c
+ arm_biquad_cascade_df1_init_q31.c
+ arm_biquad_cascade_df1_q15.c
+ arm_biquad_cascade_df1_q31.c
+ arm_biquad_cascade_df2T_f32.c
+ arm_biquad_cascade_df2T_f64.c
+ arm_biquad_cascade_df2T_init_f32.c
+ arm_biquad_cascade_df2T_init_f64.c
+ arm_biquad_cascade_stereo_df2T_f32.c
+ arm_biquad_cascade_stereo_df2T_init_f32.c
+ arm_conv_f32.c
+ arm_conv_fast_opt_q15.c
+ arm_conv_fast_q15.c
+ arm_conv_fast_q31.c
+ arm_conv_opt_q15.c
+ arm_conv_opt_q7.c
+ arm_conv_partial_f32.c
+ arm_conv_partial_fast_opt_q15.c
+ arm_conv_partial_fast_q15.c
+ arm_conv_partial_fast_q31.c
+ arm_conv_partial_opt_q15.c
+ arm_conv_partial_opt_q7.c
+ arm_conv_partial_q15.c
+ arm_conv_partial_q31.c
+ arm_conv_partial_q7.c
+ arm_conv_q15.c
+ arm_conv_q31.c
+ arm_conv_q7.c
+ arm_correlate_f32.c
+ arm_correlate_fast_opt_q15.c
+ arm_correlate_fast_q15.c
+ arm_correlate_fast_q31.c
+ arm_correlate_opt_q15.c
+ arm_correlate_opt_q7.c
+ arm_correlate_q15.c
+ arm_correlate_q31.c
+ arm_correlate_q7.c
+ arm_fir_decimate_f32.c
+ arm_fir_decimate_fast_q15.c
+ arm_fir_decimate_fast_q31.c
+ arm_fir_decimate_init_f32.c
+ arm_fir_decimate_init_q15.c
+ arm_fir_decimate_init_q31.c
+ arm_fir_decimate_q15.c
+ arm_fir_decimate_q31.c
+ arm_fir_f32.c
+ arm_fir_fast_q15.c
+ arm_fir_fast_q31.c
+ arm_fir_init_f32.c
+ arm_fir_init_q15.c
+ arm_fir_init_q31.c
+ arm_fir_init_q7.c
+ arm_fir_interpolate_f32.c
+ arm_fir_interpolate_init_f32.c
+ arm_fir_interpolate_init_q15.c
+ arm_fir_interpolate_init_q31.c
+ arm_fir_interpolate_q15.c
+ arm_fir_interpolate_q31.c
+ arm_fir_lattice_f32.c
+ arm_fir_lattice_init_f32.c
+ arm_fir_lattice_init_q15.c
+ arm_fir_lattice_init_q31.c
+ arm_fir_lattice_q15.c
+ arm_fir_lattice_q31.c
+ arm_fir_q15.c
+ arm_fir_q31.c
+ arm_fir_q7.c
+ arm_fir_sparse_f32.c
+ arm_fir_sparse_init_f32.c
+ arm_fir_sparse_init_q15.c
+ arm_fir_sparse_init_q31.c
+ arm_fir_sparse_init_q7.c
+ arm_fir_sparse_q15.c
+ arm_fir_sparse_q31.c
+ arm_fir_sparse_q7.c
+ arm_iir_lattice_f32.c
+ arm_iir_lattice_init_f32.c
+ arm_iir_lattice_init_q15.c
+ arm_iir_lattice_init_q31.c
+ arm_iir_lattice_q15.c
+ arm_iir_lattice_q31.c
+ arm_lms_f32.c
+ arm_lms_init_f32.c
+ arm_lms_init_q15.c
+ arm_lms_init_q31.c
+ arm_lms_norm_f32.c
+ arm_lms_norm_init_f32.c
+ arm_lms_norm_q15.c
+ arm_lms_norm_q31.c
+ arm_lms_q15.c
+ arm_lms_q31.c
+ )
+
+zephyr_library_sources_ifdef(CONFIG_CMSIS_DSP_TABLES_ARM_LMS_NORM_Q31 arm_lms_norm_init_q31.c)
+zephyr_library_sources_ifdef(CONFIG_CMSIS_DSP_TABLES_ARM_LMS_NORM_Q15 arm_lms_norm_init_q15.c)
diff --git a/CMSIS/DSP/Source/MatrixFunctions/CMakeLists.txt b/CMSIS/DSP/Source/MatrixFunctions/CMakeLists.txt
new file mode 100644
index 0000000..f84a9d2
--- /dev/null
+++ b/CMSIS/DSP/Source/MatrixFunctions/CMakeLists.txt
@@ -0,0 +1,32 @@
+# Copyright (c) 2020 Stephanos Ioannidis <root@stephanos.io>
+# SPDX-License-Identifier: Apache-2.0
+
+zephyr_library()
+
+zephyr_library_sources(
+ arm_mat_add_f32.c
+ arm_mat_add_q15.c
+ arm_mat_add_q31.c
+ arm_mat_cmplx_mult_f32.c
+ arm_mat_cmplx_mult_q15.c
+ arm_mat_cmplx_mult_q31.c
+ arm_mat_init_f32.c
+ arm_mat_init_q15.c
+ arm_mat_init_q31.c
+ arm_mat_inverse_f32.c
+ arm_mat_inverse_f64.c
+ arm_mat_mult_f32.c
+ arm_mat_mult_fast_q15.c
+ arm_mat_mult_fast_q31.c
+ arm_mat_mult_q15.c
+ arm_mat_mult_q31.c
+ arm_mat_scale_f32.c
+ arm_mat_scale_q15.c
+ arm_mat_scale_q31.c
+ arm_mat_sub_f32.c
+ arm_mat_sub_q15.c
+ arm_mat_sub_q31.c
+ arm_mat_trans_f32.c
+ arm_mat_trans_q15.c
+ arm_mat_trans_q31.c
+ )
diff --git a/CMSIS/DSP/Source/SVMFunctions/CMakeLists.txt b/CMSIS/DSP/Source/SVMFunctions/CMakeLists.txt
new file mode 100644
index 0000000..fdf42bb
--- /dev/null
+++ b/CMSIS/DSP/Source/SVMFunctions/CMakeLists.txt
@@ -0,0 +1,15 @@
+# Copyright (c) 2020 Stephanos Ioannidis <root@stephanos.io>
+# SPDX-License-Identifier: Apache-2.0
+
+zephyr_library()
+
+zephyr_library_sources(
+ arm_svm_linear_init_f32.c
+ arm_svm_linear_predict_f32.c
+ arm_svm_polynomial_init_f32.c
+ arm_svm_polynomial_predict_f32.c
+ arm_svm_rbf_init_f32.c
+ arm_svm_rbf_predict_f32.c
+ arm_svm_sigmoid_init_f32.c
+ arm_svm_sigmoid_predict_f32.c
+ )
diff --git a/CMSIS/DSP/Source/StatisticsFunctions/CMakeLists.txt b/CMSIS/DSP/Source/StatisticsFunctions/CMakeLists.txt
new file mode 100644
index 0000000..5ce9c23
--- /dev/null
+++ b/CMSIS/DSP/Source/StatisticsFunctions/CMakeLists.txt
@@ -0,0 +1,39 @@
+# Copyright (c) 2020 Stephanos Ioannidis <root@stephanos.io>
+# SPDX-License-Identifier: Apache-2.0
+
+zephyr_library()
+
+zephyr_library_sources(
+ arm_entropy_f32.c
+ arm_entropy_f64.c
+ arm_kullback_leibler_f32.c
+ arm_kullback_leibler_f64.c
+ arm_logsumexp_dot_prod_f32.c
+ arm_logsumexp_f32.c
+ arm_max_f32.c
+ arm_max_no_idx_f32.c
+ arm_max_q15.c
+ arm_max_q31.c
+ arm_max_q7.c
+ arm_mean_f32.c
+ arm_mean_q15.c
+ arm_mean_q31.c
+ arm_mean_q7.c
+ arm_min_f32.c
+ arm_min_q15.c
+ arm_min_q31.c
+ arm_min_q7.c
+ arm_power_f32.c
+ arm_power_q15.c
+ arm_power_q31.c
+ arm_power_q7.c
+ arm_rms_f32.c
+ arm_rms_q15.c
+ arm_rms_q31.c
+ arm_std_f32.c
+ arm_std_q15.c
+ arm_std_q31.c
+ arm_var_f32.c
+ arm_var_q15.c
+ arm_var_q31.c
+ )
diff --git a/CMSIS/DSP/Source/SupportFunctions/CMakeLists.txt b/CMSIS/DSP/Source/SupportFunctions/CMakeLists.txt
new file mode 100644
index 0000000..098fe58
--- /dev/null
+++ b/CMSIS/DSP/Source/SupportFunctions/CMakeLists.txt
@@ -0,0 +1,41 @@
+# Copyright (c) 2020 Stephanos Ioannidis <root@stephanos.io>
+# SPDX-License-Identifier: Apache-2.0
+
+zephyr_library()
+
+zephyr_library_sources(
+ arm_barycenter_f32.c
+ arm_bitonic_sort_f32.c
+ arm_bubble_sort_f32.c
+ arm_copy_f32.c
+ arm_copy_q15.c
+ arm_copy_q31.c
+ arm_copy_q7.c
+ arm_fill_f32.c
+ arm_fill_q15.c
+ arm_fill_q31.c
+ arm_fill_q7.c
+ arm_float_to_q15.c
+ arm_float_to_q31.c
+ arm_float_to_q7.c
+ arm_heap_sort_f32.c
+ arm_insertion_sort_f32.c
+ arm_merge_sort_f32.c
+ arm_merge_sort_init_f32.c
+ arm_q15_to_float.c
+ arm_q15_to_q31.c
+ arm_q15_to_q7.c
+ arm_q31_to_float.c
+ arm_q31_to_q15.c
+ arm_q31_to_q7.c
+ arm_q7_to_float.c
+ arm_q7_to_q15.c
+ arm_q7_to_q31.c
+ arm_quick_sort_f32.c
+ arm_selection_sort_f32.c
+ arm_sort_f32.c
+ arm_sort_init_f32.c
+ arm_spline_interp_f32.c
+ arm_spline_interp_init_f32.c
+ arm_weighted_sum_f32.c
+ )
diff --git a/CMSIS/DSP/Source/TransformFunctions/CMakeLists.txt b/CMSIS/DSP/Source/TransformFunctions/CMakeLists.txt
new file mode 100644
index 0000000..ac57ca8
--- /dev/null
+++ b/CMSIS/DSP/Source/TransformFunctions/CMakeLists.txt
@@ -0,0 +1,274 @@
+# Copyright (c) 2020 Stephanos Ioannidis <root@stephanos.io>
+# SPDX-License-Identifier: Apache-2.0
+
+zephyr_library()
+
+zephyr_library_sources(
+ arm_bitreversal.c
+ arm_bitreversal2.c
+ # NOTE: The ASM implementation of `arm_bitreversal2` is disabled for now in
+ # order to allow the compiler to perform ISA and microarchitecture-
+ # specific optimisations. This may be re-enabled in the future when we
+ # have a more advanced implementation that supports ARMv8.1-M MVE.
+ # arm_bitreversal2.S
+)
+
+if(
+ CONFIG_CMSIS_DSP_TABLES_CFFT_F64_16 OR
+ CONFIG_CMSIS_DSP_TABLES_CFFT_F64_32 OR
+ CONFIG_CMSIS_DSP_TABLES_CFFT_F64_64 OR
+ CONFIG_CMSIS_DSP_TABLES_CFFT_F64_128 OR
+ CONFIG_CMSIS_DSP_TABLES_CFFT_F64_256 OR
+ CONFIG_CMSIS_DSP_TABLES_CFFT_F64_512 OR
+ CONFIG_CMSIS_DSP_TABLES_CFFT_F64_1024 OR
+ CONFIG_CMSIS_DSP_TABLES_CFFT_F64_2048 OR
+ CONFIG_CMSIS_DSP_TABLES_CFFT_F64_4096
+ )
+
+ zephyr_library_sources(
+ arm_cfft_f64.c
+ arm_cfft_init_f64.c
+ )
+
+endif()
+
+if(
+ CONFIG_CMSIS_DSP_TABLES_CFFT_F32_16 OR
+ CONFIG_CMSIS_DSP_TABLES_CFFT_F32_32 OR
+ CONFIG_CMSIS_DSP_TABLES_CFFT_F32_64 OR
+ CONFIG_CMSIS_DSP_TABLES_CFFT_F32_128 OR
+ CONFIG_CMSIS_DSP_TABLES_CFFT_F32_256 OR
+ CONFIG_CMSIS_DSP_TABLES_CFFT_F32_512 OR
+ CONFIG_CMSIS_DSP_TABLES_CFFT_F32_1024 OR
+ CONFIG_CMSIS_DSP_TABLES_CFFT_F32_2048 OR
+ CONFIG_CMSIS_DSP_TABLES_CFFT_F32_4096
+ )
+
+ zephyr_library_sources(
+ arm_cfft_radix2_f32.c
+ arm_cfft_radix4_f32.c
+ arm_cfft_radix8_f32.c
+ arm_cfft_f32.c
+ arm_cfft_init_f32.c
+ )
+
+endif()
+
+if(
+ CONFIG_CMSIS_DSP_TABLES_CFFT_Q31_16 OR
+ CONFIG_CMSIS_DSP_TABLES_CFFT_Q31_32 OR
+ CONFIG_CMSIS_DSP_TABLES_CFFT_Q31_64 OR
+ CONFIG_CMSIS_DSP_TABLES_CFFT_Q31_128 OR
+ CONFIG_CMSIS_DSP_TABLES_CFFT_Q31_256 OR
+ CONFIG_CMSIS_DSP_TABLES_CFFT_Q31_512 OR
+ CONFIG_CMSIS_DSP_TABLES_CFFT_Q31_1024 OR
+ CONFIG_CMSIS_DSP_TABLES_CFFT_Q31_2048 OR
+ CONFIG_CMSIS_DSP_TABLES_CFFT_Q31_4096
+ )
+
+ zephyr_library_sources(
+ arm_cfft_radix2_q31.c
+ arm_cfft_radix4_q31.c
+ arm_cfft_q31.c
+ arm_cfft_init_q31.c
+ )
+
+endif()
+
+if(
+ CONFIG_CMSIS_DSP_TABLES_CFFT_Q15_16 OR
+ CONFIG_CMSIS_DSP_TABLES_CFFT_Q15_32 OR
+ CONFIG_CMSIS_DSP_TABLES_CFFT_Q15_64 OR
+ CONFIG_CMSIS_DSP_TABLES_CFFT_Q15_128 OR
+ CONFIG_CMSIS_DSP_TABLES_CFFT_Q15_256 OR
+ CONFIG_CMSIS_DSP_TABLES_CFFT_Q15_512 OR
+ CONFIG_CMSIS_DSP_TABLES_CFFT_Q15_1024 OR
+ CONFIG_CMSIS_DSP_TABLES_CFFT_Q15_2048 OR
+ CONFIG_CMSIS_DSP_TABLES_CFFT_Q15_4096
+ )
+
+ zephyr_library_sources(
+ arm_cfft_radix2_q15.c
+ arm_cfft_radix4_q15.c
+ arm_cfft_q15.c
+ arm_cfft_init_q15.c
+ )
+
+endif()
+
+if(CONFIG_CMSIS_DSP_TABLES_ALL_FFT)
+
+ zephyr_library_sources(
+ arm_cfft_radix2_init_q15.c
+ arm_cfft_radix2_init_q31.c
+ )
+
+endif()
+
+if(
+ CONFIG_CMSIS_DSP_TABLES_RFFT_FAST_F64_32 OR
+ CONFIG_CMSIS_DSP_TABLES_RFFT_FAST_F64_64 OR
+ CONFIG_CMSIS_DSP_TABLES_RFFT_FAST_F64_128 OR
+ CONFIG_CMSIS_DSP_TABLES_RFFT_FAST_F64_256 OR
+ CONFIG_CMSIS_DSP_TABLES_RFFT_FAST_F64_512 OR
+ CONFIG_CMSIS_DSP_TABLES_RFFT_FAST_F64_1024 OR
+ CONFIG_CMSIS_DSP_TABLES_RFFT_FAST_F64_2048 OR
+ CONFIG_CMSIS_DSP_TABLES_RFFT_FAST_F64_4096
+ )
+
+ zephyr_library_sources(
+ arm_rfft_fast_f64.c
+ arm_rfft_fast_init_f64.c
+ )
+
+endif()
+
+if(
+ CONFIG_CMSIS_DSP_TABLES_RFFT_FAST_F32_32 OR
+ CONFIG_CMSIS_DSP_TABLES_RFFT_FAST_F32_64 OR
+ CONFIG_CMSIS_DSP_TABLES_RFFT_FAST_F32_128 OR
+ CONFIG_CMSIS_DSP_TABLES_RFFT_FAST_F32_256 OR
+ CONFIG_CMSIS_DSP_TABLES_RFFT_FAST_F32_512 OR
+ CONFIG_CMSIS_DSP_TABLES_RFFT_FAST_F32_1024 OR
+ CONFIG_CMSIS_DSP_TABLES_RFFT_FAST_F32_2048 OR
+ CONFIG_CMSIS_DSP_TABLES_RFFT_FAST_F32_4096
+ )
+
+ zephyr_library_sources(
+ arm_rfft_fast_f32.c
+ arm_rfft_fast_init_f32.c
+ arm_cfft_f32.c
+ arm_cfft_init_f32.c
+ arm_cfft_radix8_f32.c
+ )
+
+endif()
+
+if(
+ CONFIG_CMSIS_DSP_TABLES_RFFT_F32_128 OR
+ CONFIG_CMSIS_DSP_TABLES_RFFT_F32_512 OR
+ CONFIG_CMSIS_DSP_TABLES_RFFT_F32_2048 OR
+ CONFIG_CMSIS_DSP_TABLES_RFFT_F32_8192
+ )
+
+ zephyr_library_sources(
+ arm_rfft_init_f32.c
+ arm_rfft_f32.c
+ arm_cfft_radix4_init_f32.c
+ arm_cfft_radix4_f32.c
+ )
+
+endif()
+
+if(
+ CONFIG_CMSIS_DSP_TABLES_RFFT_Q31_32 OR
+ CONFIG_CMSIS_DSP_TABLES_RFFT_Q31_64 OR
+ CONFIG_CMSIS_DSP_TABLES_RFFT_Q31_128 OR
+ CONFIG_CMSIS_DSP_TABLES_RFFT_Q31_256 OR
+ CONFIG_CMSIS_DSP_TABLES_RFFT_Q31_512 OR
+ CONFIG_CMSIS_DSP_TABLES_RFFT_Q31_1024 OR
+ CONFIG_CMSIS_DSP_TABLES_RFFT_Q31_2048 OR
+ CONFIG_CMSIS_DSP_TABLES_RFFT_Q31_4096 OR
+ CONFIG_CMSIS_DSP_TABLES_RFFT_Q31_8192
+ )
+
+ zephyr_library_sources(
+ arm_rfft_init_q31.c
+ arm_rfft_q31.c
+ arm_cfft_q31.c
+ arm_cfft_init_q31.c
+ arm_cfft_radix4_q31.c
+ )
+
+endif()
+
+if(
+ CONFIG_CMSIS_DSP_TABLES_RFFT_Q15_32 OR
+ CONFIG_CMSIS_DSP_TABLES_RFFT_Q15_64 OR
+ CONFIG_CMSIS_DSP_TABLES_RFFT_Q15_128 OR
+ CONFIG_CMSIS_DSP_TABLES_RFFT_Q15_256 OR
+ CONFIG_CMSIS_DSP_TABLES_RFFT_Q15_512 OR
+ CONFIG_CMSIS_DSP_TABLES_RFFT_Q15_1024 OR
+ CONFIG_CMSIS_DSP_TABLES_RFFT_Q15_2048 OR
+ CONFIG_CMSIS_DSP_TABLES_RFFT_Q15_4096 OR
+ CONFIG_CMSIS_DSP_TABLES_RFFT_Q15_8192
+ )
+
+ zephyr_library_sources(
+ arm_rfft_init_q15.c
+ arm_rfft_q15.c
+ arm_cfft_q15.c
+ arm_cfft_init_q15.c
+ arm_cfft_radix4_q15.c
+ )
+
+endif()
+
+if(
+ CONFIG_CMSIS_DSP_TABLES_DCT4_F32_128 OR
+ CONFIG_CMSIS_DSP_TABLES_DCT4_F32_512 OR
+ CONFIG_CMSIS_DSP_TABLES_DCT4_F32_2048 OR
+ CONFIG_CMSIS_DSP_TABLES_DCT4_F32_8192
+ )
+
+ zephyr_library_sources(
+ arm_dct4_f32.c
+ arm_dct4_init_f32.c
+
+ arm_rfft_init_f32.c
+ arm_rfft_f32.c
+ arm_cfft_radix4_init_f32.c
+ arm_cfft_radix4_f32.c
+ )
+
+endif()
+
+if(
+ CONFIG_CMSIS_DSP_TABLES_DCT4_Q31_128 OR
+ CONFIG_CMSIS_DSP_TABLES_DCT4_Q31_512 OR
+ CONFIG_CMSIS_DSP_TABLES_DCT4_Q31_2048 OR
+ CONFIG_CMSIS_DSP_TABLES_DCT4_Q31_8192
+ )
+
+ zephyr_library_sources(
+ arm_dct4_q31.c
+ arm_dct4_init_q31.c
+
+ arm_rfft_init_q31.c
+ arm_rfft_q31.c
+ arm_cfft_q31.c
+ arm_cfft_init_q31.c
+ arm_cfft_radix4_init_q31.c
+ arm_cfft_radix4_q31.c
+ )
+
+endif()
+
+if(
+ CONFIG_CMSIS_DSP_TABLES_DCT4_Q15_128 OR
+ CONFIG_CMSIS_DSP_TABLES_DCT4_Q15_512 OR
+ CONFIG_CMSIS_DSP_TABLES_DCT4_Q15_2048 OR
+ CONFIG_CMSIS_DSP_TABLES_DCT4_Q15_8192
+ )
+
+ zephyr_library_sources(
+ arm_dct4_q15.c
+ arm_dct4_init_q15.c
+
+ arm_rfft_init_q15.c
+ arm_rfft_q15.c
+ arm_cfft_q15.c
+ arm_cfft_init_q15.c
+ arm_cfft_radix4_init_q15.c
+ arm_cfft_radix4_q15.c
+ )
+
+endif()
+
+if(CONFIG_CMSIS_DSP_WRAPPER)
+
+ zephyr_library_sources(
+ arm_cfft_radix2_init_f32.c
+ )
+
+endif()
