| // Copyright 2015, VIXL authors |
| // All rights reserved. |
| // |
| // Redistribution and use in source and binary forms, with or without |
| // modification, are permitted provided that the following conditions are met: |
| // |
| // * Redistributions of source code must retain the above copyright notice, |
| // this list of conditions and the following disclaimer. |
| // * Redistributions in binary form must reproduce the above copyright notice, |
| // this list of conditions and the following disclaimer in the documentation |
| // and/or other materials provided with the distribution. |
| // * Neither the name of ARM Limited nor the names of its contributors may be |
| // used to endorse or promote products derived from this software without |
| // specific prior written permission. |
| // |
| // THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS CONTRIBUTORS "AS IS" AND |
| // ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED |
| // WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE |
| // DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE |
| // FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL |
| // DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR |
| // SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER |
| // CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, |
| // OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE |
| // OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. |
| |
| |
| // --------------------------------------------------------------------- |
| // This file is auto generated using tools/generate_simulator_traces.py. |
| // |
| // PLEASE DO NOT EDIT. |
| // --------------------------------------------------------------------- |
| |
| #ifndef VIXL_SIM_FCVTNS_WS_TRACE_AARCH64_H_ |
| #define VIXL_SIM_FCVTNS_WS_TRACE_AARCH64_H_ |
| |
| const int32_t kExpected_fcvtns_ws[] = { |
| INT32_C(0), |
| INT32_C(0), |
| INT32_C(0), |
| INT32_C(0), |
| INT32_C(1), |
| INT32_C(1), |
| INT32_C(1), |
| INT32_C(1), |
| INT32_C(2), |
| INT32_C(10), |
| INT32_C(0), |
| INT32_C(2147483647), |
| INT32_C(0), |
| INT32_C(0), |
| INT32_C(0), |
| INT32_C(0), |
| INT32_C(0), |
| INT32_C(0), |
| INT32_C(0), |
| INT32_C(0), |
| INT32_C(0), |
| INT32_C(0), |
| INT32_C(0), |
| -INT32_C(1), |
| -INT32_C(1), |
| -INT32_C(1), |
| -INT32_C(1), |
| -INT32_C(2), |
| -INT32_C(10), |
| INT32_C(0), |
| -INT32_C(2147483647) - 1, |
| INT32_C(0), |
| INT32_C(0), |
| INT32_C(0), |
| INT32_C(0), |
| INT32_C(0), |
| INT32_C(0), |
| INT32_C(0), |
| INT32_C(8388608), |
| INT32_C(8388609), |
| INT32_C(8388610), |
| INT32_C(8388611), |
| INT32_C(16143410), |
| INT32_C(16777212), |
| INT32_C(16777213), |
| INT32_C(16777214), |
| INT32_C(16777215), |
| INT32_C(4194304), |
| INT32_C(4194304), |
| INT32_C(4194305), |
| INT32_C(4194306), |
| INT32_C(8071705), |
| INT32_C(8388606), |
| INT32_C(8388606), |
| INT32_C(8388607), |
| INT32_C(8388608), |
| INT32_C(2097152), |
| INT32_C(2097152), |
| INT32_C(2097152), |
| INT32_C(2097153), |
| INT32_C(4035852), |
| INT32_C(4194303), |
| INT32_C(4194303), |
| INT32_C(4194304), |
| INT32_C(4194304), |
| -INT32_C(8388608), |
| -INT32_C(8388609), |
| -INT32_C(8388610), |
| -INT32_C(8388611), |
| -INT32_C(16143410), |
| -INT32_C(16777212), |
| -INT32_C(16777213), |
| -INT32_C(16777214), |
| -INT32_C(16777215), |
| -INT32_C(4194304), |
| -INT32_C(4194304), |
| -INT32_C(4194305), |
| -INT32_C(4194306), |
| -INT32_C(8071705), |
| -INT32_C(8388606), |
| -INT32_C(8388606), |
| -INT32_C(8388607), |
| -INT32_C(8388608), |
| -INT32_C(2097152), |
| -INT32_C(2097152), |
| -INT32_C(2097152), |
| -INT32_C(2097153), |
| -INT32_C(4035852), |
| -INT32_C(4194303), |
| -INT32_C(4194303), |
| -INT32_C(4194304), |
| -INT32_C(4194304), |
| -INT32_C(2147483647) - 1, |
| -INT32_C(2147483647) - 1, |
| -INT32_C(2147483647) - 1, |
| INT32_C(2147483647), |
| INT32_C(2147483647), |
| INT32_C(2147483647), |
| INT32_C(2147483647), |
| -INT32_C(2147483647) - 1, |
| -INT32_C(2147483647) - 1, |
| -INT32_C(2147483520), |
| INT32_C(2147483520), |
| INT32_C(2147483647), |
| }; |
| const unsigned kExpectedCount_fcvtns_ws = 104; |
| |
| #endif // VIXL_SIM_FCVTNS_WS_TRACE_AARCH64_H_ |