sim-urecpe-4s-trace-arm64.h

// Copyright 2015, VIXL authors
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// ---------------------------------------------------------------------
// This file is auto generated using tools/generate_simulator_traces.py.
//
// PLEASE DO NOT EDIT.
// ---------------------------------------------------------------------

#ifndef VIXL_SIM_URECPE_4S_TRACE_AARCH64_H_
#define VIXL_SIM_URECPE_4S_TRACE_AARCH64_H_

const uint32_t kExpected_NEON_urecpe_4S[] = {
  0x80000000, 0x80000000, 0x80000000, 0xffffffff,
  0x80000000, 0x80000000, 0xffffffff, 0xffffffff,
  0x80000000, 0xffffffff, 0xffffffff, 0xffffffff,
  0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff,
  0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff,
  0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff,
  0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff,
  0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff,
  0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff,
  0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff,
  0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff,
  0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff,
  0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff,
  0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff,
  0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff,
  0xffffffff, 0xffffffff, 0xffffffff, 0xff800000,
  0xffffffff, 0xffffffff, 0xff800000, 0xff800000,
  0xffffffff, 0xff800000, 0xff800000, 0xc0000000,
  0xff800000, 0xff800000, 0xc0000000, 0xa0000000,
  0xff800000, 0xc0000000, 0xa0000000, 0x80000000,
  0xc0000000, 0xa0000000, 0x80000000, 0x80000000,
  0xa0000000, 0x80000000, 0x80000000, 0x80000000,
  0x80000000, 0x80000000, 0x80000000, 0x80000000,
  0x80000000, 0x80000000, 0x80000000, 0x80000000,
  0x80000000, 0x80000000, 0x80000000, 0x80000000,
  0x80000000, 0x80000000, 0x80000000, 0x80000000,
  0x80000000, 0x80000000, 0x80000000, 0x80000000,
  0x80000000, 0x80000000, 0x80000000, 0x80000000,
  0x80000000, 0x80000000, 0x80000000, 0x80000000,
  0x80000000, 0x80000000, 0x80000000, 0x80000000,
  0x80000000, 0x80000000, 0x80000000, 0x80000000,
};
const unsigned kExpectedCount_NEON_urecpe_4S = 31;

#endif  // VIXL_SIM_URECPE_4S_TRACE_AARCH64_H_