Add barriers to handle Secure Timer interrupts correctly
This patch adds instruction synchronization barriers around the code which
handles the timer interrupt in the TSP. This ensures that the interrupt is not
acknowledged after or EOIed before it is deactivated at the peripheral.
Change-Id: Ic691ab909bc671d8f0f43ffc443f46237c75536d
diff --git a/bl32/tsp/tsp_timer.c b/bl32/tsp/tsp_timer.c
index 366640f..fd4a9c5 100644
--- a/bl32/tsp/tsp_timer.c
+++ b/bl32/tsp/tsp_timer.c
@@ -68,9 +68,14 @@
/* Ensure that the timer did assert the interrupt */
assert(get_cntp_ctl_istatus(read_cntps_ctl_el1()));
- /* Disable the timer and reprogram it */
+ /*
+ * Disable the timer and reprogram it. The barriers ensure that there is
+ * no reordering of instructions around the reprogramming code.
+ */
+ isb();
write_cntps_ctl_el1(0);
tsp_generic_timer_start();
+ isb();
}
/*******************************************************************************
