| """ |
| Microkernel filenames lists. |
| |
| Auto-generated file. Do not edit! |
| Generator: tools/update-microkernels.py |
| """ |
| |
| ALL_ARMSIMD32_MICROKERNEL_SRCS = [ |
| "src/qs8-gemm/gen/qs8-gemm-1x1c4-minmax-fp32-armsimd32.c", |
| "src/qs8-gemm/gen/qs8-gemm-1x2c4-minmax-fp32-armsimd32.c", |
| "src/qs8-gemm/gen/qs8-gemm-2x1c4-minmax-fp32-armsimd32.c", |
| "src/qs8-gemm/gen/qs8-gemm-2x2c4-minmax-fp32-armsimd32.c", |
| "src/qs8-igemm/gen/qs8-igemm-1x1c4-minmax-fp32-armsimd32.c", |
| "src/qs8-igemm/gen/qs8-igemm-1x2c4-minmax-fp32-armsimd32.c", |
| "src/qs8-igemm/gen/qs8-igemm-2x1c4-minmax-fp32-armsimd32.c", |
| "src/qs8-igemm/gen/qs8-igemm-2x2c4-minmax-fp32-armsimd32.c", |
| "src/qs8-qc8w-gemm/gen/qs8-qc8w-gemm-1x1c4-minmax-fp32-armsimd32.c", |
| "src/qs8-qc8w-gemm/gen/qs8-qc8w-gemm-1x2c4-minmax-fp32-armsimd32.c", |
| "src/qs8-qc8w-gemm/gen/qs8-qc8w-gemm-2x1c4-minmax-fp32-armsimd32.c", |
| "src/qs8-qc8w-gemm/gen/qs8-qc8w-gemm-2x2c4-minmax-fp32-armsimd32.c", |
| "src/qs8-qc8w-igemm/gen/qs8-qc8w-igemm-1x1c4-minmax-fp32-armsimd32.c", |
| "src/qs8-qc8w-igemm/gen/qs8-qc8w-igemm-1x2c4-minmax-fp32-armsimd32.c", |
| "src/qs8-qc8w-igemm/gen/qs8-qc8w-igemm-2x1c4-minmax-fp32-armsimd32.c", |
| "src/qs8-qc8w-igemm/gen/qs8-qc8w-igemm-2x2c4-minmax-fp32-armsimd32.c", |
| "src/qs8-vcvt/gen/qs8-vcvt-armsimd32-u4.c", |
| "src/qs8-vcvt/gen/qs8-vcvt-armsimd32-u8.c", |
| "src/qs8-vlrelu/gen/qs8-vlrelu-armsimd32-u4.c", |
| "src/qs8-vlrelu/gen/qs8-vlrelu-armsimd32-u8.c", |
| "src/qu8-gemm/gen/qu8-gemm-1x1c4-minmax-fp32-armsimd32.c", |
| "src/qu8-gemm/gen/qu8-gemm-1x2c4-minmax-fp32-armsimd32.c", |
| "src/qu8-gemm/gen/qu8-gemm-2x1c4-minmax-fp32-armsimd32.c", |
| "src/qu8-gemm/gen/qu8-gemm-2x2c4-minmax-fp32-armsimd32.c", |
| "src/qu8-igemm/gen/qu8-igemm-1x1c4-minmax-fp32-armsimd32.c", |
| "src/qu8-igemm/gen/qu8-igemm-1x2c4-minmax-fp32-armsimd32.c", |
| "src/qu8-igemm/gen/qu8-igemm-2x1c4-minmax-fp32-armsimd32.c", |
| "src/qu8-igemm/gen/qu8-igemm-2x2c4-minmax-fp32-armsimd32.c", |
| "src/qu8-vcvt/gen/qu8-vcvt-armsimd32-u4.c", |
| "src/qu8-vcvt/gen/qu8-vcvt-armsimd32-u8.c", |
| "src/qu8-vlrelu/gen/qu8-vlrelu-armsimd32-u4.c", |
| "src/qu8-vlrelu/gen/qu8-vlrelu-armsimd32-u8.c", |
| ] |
| |
| ALL_AVX_MICROKERNEL_SRCS = [ |
| "src/f16-f32-vcvt/gen/f16-f32-vcvt-avx-int16-u8.c", |
| "src/f16-f32-vcvt/gen/f16-f32-vcvt-avx-int16-u16.c", |
| "src/f16-f32-vcvt/gen/f16-f32-vcvt-avx-int16-u24.c", |
| "src/f16-f32-vcvt/gen/f16-f32-vcvt-avx-int16-u32.c", |
| "src/f16-f32-vcvt/gen/f16-f32-vcvt-avx-int32-u8.c", |
| "src/f16-f32-vcvt/gen/f16-f32-vcvt-avx-int32-u16.c", |
| "src/f16-f32-vcvt/gen/f16-f32-vcvt-avx-int32-u24.c", |
| "src/f16-f32-vcvt/gen/f16-f32-vcvt-avx-int32-u32.c", |
| "src/f32-dwconv/gen/f32-dwconv-3p8c-minmax-avx-acc2.c", |
| "src/f32-dwconv/gen/f32-dwconv-3p8c-minmax-avx.c", |
| "src/f32-dwconv/gen/f32-dwconv-3p16c-minmax-avx-acc2.c", |
| "src/f32-dwconv/gen/f32-dwconv-3p16c-minmax-avx.c", |
| "src/f32-dwconv/gen/f32-dwconv-4p8c-minmax-avx-acc2.c", |
| "src/f32-dwconv/gen/f32-dwconv-4p8c-minmax-avx.c", |
| "src/f32-dwconv/gen/f32-dwconv-4p16c-minmax-avx-acc2.c", |
| "src/f32-dwconv/gen/f32-dwconv-4p16c-minmax-avx.c", |
| "src/f32-dwconv/gen/f32-dwconv-5f5m5l8c8s4r-minmax-avx-acc2.c", |
| "src/f32-dwconv/gen/f32-dwconv-5f5m5l8c8s4r-minmax-avx.c", |
| "src/f32-dwconv/gen/f32-dwconv-5f5m5l16c8s4r-minmax-avx-acc2.c", |
| "src/f32-dwconv/gen/f32-dwconv-5f5m5l16c8s4r-minmax-avx.c", |
| "src/f32-dwconv/gen/f32-dwconv-6f6m7l8c8s4r-minmax-avx-acc2.c", |
| "src/f32-dwconv/gen/f32-dwconv-6f6m7l8c8s4r-minmax-avx.c", |
| "src/f32-dwconv/gen/f32-dwconv-6f6m7l16c8s4r-minmax-avx-acc2.c", |
| "src/f32-dwconv/gen/f32-dwconv-6f6m7l16c8s4r-minmax-avx.c", |
| "src/f32-dwconv/gen/f32-dwconv-8f8m9l8c8s4r-minmax-avx-acc2.c", |
| "src/f32-dwconv/gen/f32-dwconv-8f8m9l8c8s4r-minmax-avx.c", |
| "src/f32-dwconv/gen/f32-dwconv-8f8m9l16c8s4r-minmax-avx-acc2.c", |
| "src/f32-dwconv/gen/f32-dwconv-8f8m9l16c8s4r-minmax-avx.c", |
| "src/f32-dwconv/gen/f32-dwconv-9p8c-minmax-avx-acc2.c", |
| "src/f32-dwconv/gen/f32-dwconv-9p8c-minmax-avx.c", |
| "src/f32-dwconv/gen/f32-dwconv-9p16c-minmax-avx-acc2.c", |
| "src/f32-dwconv/gen/f32-dwconv-9p16c-minmax-avx.c", |
| "src/f32-dwconv/gen/f32-dwconv-25p8c-minmax-avx-acc2.c", |
| "src/f32-dwconv/gen/f32-dwconv-25p8c-minmax-avx.c", |
| "src/f32-dwconv/gen/f32-dwconv-25p16c-minmax-avx-acc2.c", |
| "src/f32-dwconv/gen/f32-dwconv-25p16c-minmax-avx.c", |
| "src/f32-f16-vcvt/gen/f32-f16-vcvt-avx-u8.c", |
| "src/f32-f16-vcvt/gen/f32-f16-vcvt-avx-u16.c", |
| "src/f32-f16-vcvt/gen/f32-f16-vcvt-avx-u24.c", |
| "src/f32-f16-vcvt/gen/f32-f16-vcvt-avx-u32.c", |
| "src/f32-gemm/gen/f32-gemm-1x8-minmax-avx-broadcast.c", |
| "src/f32-gemm/gen/f32-gemm-1x16-minmax-avx-broadcast.c", |
| "src/f32-gemm/gen/f32-gemm-3x16-minmax-avx-broadcast.c", |
| "src/f32-gemm/gen/f32-gemm-4x8-minmax-avx-broadcast.c", |
| "src/f32-gemm/gen/f32-gemm-4x16-minmax-avx-broadcast.c", |
| "src/f32-gemm/gen/f32-gemm-5x8-minmax-avx-broadcast.c", |
| "src/f32-gemm/gen/f32-gemm-5x16-minmax-avx-broadcast.c", |
| "src/f32-gemm/gen/f32-gemm-6x8-minmax-avx-broadcast.c", |
| "src/f32-gemm/gen/f32-gemm-6x16-minmax-avx-broadcast.c", |
| "src/f32-gemm/gen/f32-gemm-7x8-minmax-avx-broadcast.c", |
| "src/f32-gemminc/gen/f32-gemminc-1x8-minmax-avx-broadcast.c", |
| "src/f32-gemminc/gen/f32-gemminc-1x16-minmax-avx-broadcast.c", |
| "src/f32-gemminc/gen/f32-gemminc-3x16-minmax-avx-broadcast.c", |
| "src/f32-gemminc/gen/f32-gemminc-4x8-minmax-avx-broadcast.c", |
| "src/f32-gemminc/gen/f32-gemminc-4x16-minmax-avx-broadcast.c", |
| "src/f32-gemminc/gen/f32-gemminc-5x8-minmax-avx-broadcast.c", |
| "src/f32-gemminc/gen/f32-gemminc-5x16-minmax-avx-broadcast.c", |
| "src/f32-gemminc/gen/f32-gemminc-6x8-minmax-avx-broadcast.c", |
| "src/f32-gemminc/gen/f32-gemminc-6x16-minmax-avx-broadcast.c", |
| "src/f32-gemminc/gen/f32-gemminc-7x8-minmax-avx-broadcast.c", |
| "src/f32-igemm/gen/f32-igemm-1x8-minmax-avx-broadcast.c", |
| "src/f32-igemm/gen/f32-igemm-1x16-minmax-avx-broadcast.c", |
| "src/f32-igemm/gen/f32-igemm-3x16-minmax-avx-broadcast.c", |
| "src/f32-igemm/gen/f32-igemm-4x8-minmax-avx-broadcast.c", |
| "src/f32-igemm/gen/f32-igemm-4x16-minmax-avx-broadcast.c", |
| "src/f32-igemm/gen/f32-igemm-5x8-minmax-avx-broadcast.c", |
| "src/f32-igemm/gen/f32-igemm-5x16-minmax-avx-broadcast.c", |
| "src/f32-igemm/gen/f32-igemm-6x8-minmax-avx-broadcast.c", |
| "src/f32-igemm/gen/f32-igemm-6x16-minmax-avx-broadcast.c", |
| "src/f32-igemm/gen/f32-igemm-7x8-minmax-avx-broadcast.c", |
| "src/f32-prelu/gen/f32-prelu-avx-2x8.c", |
| "src/f32-prelu/gen/f32-prelu-avx-2x16.c", |
| "src/f32-qc4w-gemm/gen/f32-qc4w-gemm-1x16-minmax-avx-broadcast.c", |
| "src/f32-qc4w-gemm/gen/f32-qc4w-gemm-2x16-minmax-avx-broadcast.c", |
| "src/f32-qc4w-gemm/gen/f32-qc4w-gemm-3x16-minmax-avx-broadcast.c", |
| "src/f32-qc4w-gemm/gen/f32-qc4w-gemm-4x16-minmax-avx-broadcast.c", |
| "src/f32-qc4w-gemm/gen/f32-qc4w-gemm-5x16-minmax-avx-broadcast.c", |
| "src/f32-qc4w-gemm/gen/f32-qc4w-gemm-6x16-minmax-avx-broadcast.c", |
| "src/f32-qc4w-gemm/gen/f32-qc4w-gemm-7x16-minmax-avx-broadcast.c", |
| "src/f32-qc4w-gemm/gen/f32-qc4w-gemm-8x16-minmax-avx-broadcast.c", |
| "src/f32-qc8w-gemm/gen/f32-qc8w-gemm-1x16-minmax-avx-broadcast.c", |
| "src/f32-qc8w-gemm/gen/f32-qc8w-gemm-2x16-minmax-avx-broadcast.c", |
| "src/f32-qc8w-gemm/gen/f32-qc8w-gemm-3x16-minmax-avx-broadcast.c", |
| "src/f32-qc8w-gemm/gen/f32-qc8w-gemm-4x16-minmax-avx-broadcast.c", |
| "src/f32-qc8w-gemm/gen/f32-qc8w-gemm-5x16-minmax-avx-broadcast.c", |
| "src/f32-qc8w-gemm/gen/f32-qc8w-gemm-6x16-minmax-avx-broadcast.c", |
| "src/f32-qc8w-gemm/gen/f32-qc8w-gemm-7x16-minmax-avx-broadcast.c", |
| "src/f32-qc8w-gemm/gen/f32-qc8w-gemm-8x16-minmax-avx-broadcast.c", |
| "src/f32-qs8-vcvt/gen/f32-qs8-vcvt-avx-u8.c", |
| "src/f32-qs8-vcvt/gen/f32-qs8-vcvt-avx-u16.c", |
| "src/f32-qs8-vcvt/gen/f32-qs8-vcvt-avx-u24.c", |
| "src/f32-qs8-vcvt/gen/f32-qs8-vcvt-avx-u32.c", |
| "src/f32-qu8-vcvt/gen/f32-qu8-vcvt-avx-u8.c", |
| "src/f32-qu8-vcvt/gen/f32-qu8-vcvt-avx-u16.c", |
| "src/f32-qu8-vcvt/gen/f32-qu8-vcvt-avx-u24.c", |
| "src/f32-qu8-vcvt/gen/f32-qu8-vcvt-avx-u32.c", |
| "src/f32-rmax/f32-rmax-avx.c", |
| "src/f32-rminmax/gen/f32-rmax-avx-u8.c", |
| "src/f32-rminmax/gen/f32-rmax-avx-u16-acc2.c", |
| "src/f32-rminmax/gen/f32-rmax-avx-u24-acc3.c", |
| "src/f32-rminmax/gen/f32-rmax-avx-u32-acc2.c", |
| "src/f32-rminmax/gen/f32-rmax-avx-u32-acc4.c", |
| "src/f32-rminmax/gen/f32-rmin-avx-u8.c", |
| "src/f32-rminmax/gen/f32-rmin-avx-u16-acc2.c", |
| "src/f32-rminmax/gen/f32-rmin-avx-u24-acc3.c", |
| "src/f32-rminmax/gen/f32-rmin-avx-u32-acc2.c", |
| "src/f32-rminmax/gen/f32-rmin-avx-u32-acc4.c", |
| "src/f32-rminmax/gen/f32-rminmax-avx-u8.c", |
| "src/f32-rminmax/gen/f32-rminmax-avx-u16-acc2.c", |
| "src/f32-rminmax/gen/f32-rminmax-avx-u24-acc3.c", |
| "src/f32-rminmax/gen/f32-rminmax-avx-u32-acc2.c", |
| "src/f32-rminmax/gen/f32-rminmax-avx-u32-acc4.c", |
| "src/f32-rsum/gen/f32-rsum-avx-u8.c", |
| "src/f32-rsum/gen/f32-rsum-avx-u16-acc2.c", |
| "src/f32-rsum/gen/f32-rsum-avx-u24-acc3.c", |
| "src/f32-rsum/gen/f32-rsum-avx-u32-acc2.c", |
| "src/f32-rsum/gen/f32-rsum-avx-u32-acc4.c", |
| "src/f32-vbinary/gen/f32-vadd-minmax-avx-u8.c", |
| "src/f32-vbinary/gen/f32-vadd-minmax-avx-u16.c", |
| "src/f32-vbinary/gen/f32-vaddc-minmax-avx-u8.c", |
| "src/f32-vbinary/gen/f32-vaddc-minmax-avx-u16.c", |
| "src/f32-vbinary/gen/f32-vdiv-minmax-avx-u8.c", |
| "src/f32-vbinary/gen/f32-vdiv-minmax-avx-u16.c", |
| "src/f32-vbinary/gen/f32-vdivc-minmax-avx-u8.c", |
| "src/f32-vbinary/gen/f32-vdivc-minmax-avx-u16.c", |
| "src/f32-vbinary/gen/f32-vmax-avx-u8.c", |
| "src/f32-vbinary/gen/f32-vmax-avx-u16.c", |
| "src/f32-vbinary/gen/f32-vmaxc-avx-u8.c", |
| "src/f32-vbinary/gen/f32-vmaxc-avx-u16.c", |
| "src/f32-vbinary/gen/f32-vmin-avx-u8.c", |
| "src/f32-vbinary/gen/f32-vmin-avx-u16.c", |
| "src/f32-vbinary/gen/f32-vminc-avx-u8.c", |
| "src/f32-vbinary/gen/f32-vminc-avx-u16.c", |
| "src/f32-vbinary/gen/f32-vmul-minmax-avx-u8.c", |
| "src/f32-vbinary/gen/f32-vmul-minmax-avx-u16.c", |
| "src/f32-vbinary/gen/f32-vmulc-minmax-avx-u8.c", |
| "src/f32-vbinary/gen/f32-vmulc-minmax-avx-u16.c", |
| "src/f32-vbinary/gen/f32-vrdivc-minmax-avx-u8.c", |
| "src/f32-vbinary/gen/f32-vrdivc-minmax-avx-u16.c", |
| "src/f32-vbinary/gen/f32-vrsubc-minmax-avx-u8.c", |
| "src/f32-vbinary/gen/f32-vrsubc-minmax-avx-u16.c", |
| "src/f32-vbinary/gen/f32-vsqrdiff-avx-u8.c", |
| "src/f32-vbinary/gen/f32-vsqrdiff-avx-u16.c", |
| "src/f32-vbinary/gen/f32-vsqrdiffc-avx-u8.c", |
| "src/f32-vbinary/gen/f32-vsqrdiffc-avx-u16.c", |
| "src/f32-vbinary/gen/f32-vsub-minmax-avx-u8.c", |
| "src/f32-vbinary/gen/f32-vsub-minmax-avx-u16.c", |
| "src/f32-vbinary/gen/f32-vsubc-minmax-avx-u8.c", |
| "src/f32-vbinary/gen/f32-vsubc-minmax-avx-u16.c", |
| "src/f32-vclamp/gen/f32-vclamp-avx-u8.c", |
| "src/f32-vclamp/gen/f32-vclamp-avx-u16.c", |
| "src/f32-velu/gen/f32-velu-avx-rr2-lut4-p4-perm-u8.c", |
| "src/f32-velu/gen/f32-velu-avx-rr2-lut4-p4-perm-u16.c", |
| "src/f32-velu/gen/f32-velu-avx-rr2-lut4-p4-perm-u24.c", |
| "src/f32-velu/gen/f32-velu-avx-rr2-lut4-p4-perm-u32.c", |
| "src/f32-velu/gen/f32-velu-avx-rr2-lut4-p4-perm-u40.c", |
| "src/f32-velu/gen/f32-velu-avx-rr2-lut4-p4-perm-u48.c", |
| "src/f32-velu/gen/f32-velu-avx-rr2-lut16-p3-u8.c", |
| "src/f32-velu/gen/f32-velu-avx-rr2-lut16-p3-u16.c", |
| "src/f32-velu/gen/f32-velu-avx-rr2-lut16-p3-u24.c", |
| "src/f32-velu/gen/f32-velu-avx-rr2-lut16-p3-u32.c", |
| "src/f32-velu/gen/f32-velu-avx-rr2-lut16-p3-u40.c", |
| "src/f32-velu/gen/f32-velu-avx-rr2-lut16-p3-u48.c", |
| "src/f32-velu/gen/f32-velu-avx-rr2-p6-u8.c", |
| "src/f32-velu/gen/f32-velu-avx-rr2-p6-u16.c", |
| "src/f32-velu/gen/f32-velu-avx-rr2-p6-u24.c", |
| "src/f32-velu/gen/f32-velu-avx-rr2-p6-u32.c", |
| "src/f32-velu/gen/f32-velu-avx-rr2-p6-u40.c", |
| "src/f32-velu/gen/f32-velu-avx-rr2-p6-u48.c", |
| "src/f32-vhswish/gen/f32-vhswish-avx-u8.c", |
| "src/f32-vhswish/gen/f32-vhswish-avx-u16.c", |
| "src/f32-vlrelu/gen/f32-vlrelu-avx-u8.c", |
| "src/f32-vlrelu/gen/f32-vlrelu-avx-u16.c", |
| "src/f32-vrelu/gen/f32-vrelu-avx-u8.c", |
| "src/f32-vrelu/gen/f32-vrelu-avx-u16.c", |
| "src/f32-vrnd/gen/f32-vrndd-avx-u8.c", |
| "src/f32-vrnd/gen/f32-vrndd-avx-u16.c", |
| "src/f32-vrnd/gen/f32-vrndne-avx-u8.c", |
| "src/f32-vrnd/gen/f32-vrndne-avx-u16.c", |
| "src/f32-vrnd/gen/f32-vrndu-avx-u8.c", |
| "src/f32-vrnd/gen/f32-vrndu-avx-u16.c", |
| "src/f32-vrnd/gen/f32-vrndz-avx-u8.c", |
| "src/f32-vrnd/gen/f32-vrndz-avx-u16.c", |
| "src/f32-vsigmoid/gen/f32-vsigmoid-avx-rr2-p5-div-u8.c", |
| "src/f32-vsigmoid/gen/f32-vsigmoid-avx-rr2-p5-div-u16.c", |
| "src/f32-vsigmoid/gen/f32-vsigmoid-avx-rr2-p5-div-u24.c", |
| "src/f32-vsigmoid/gen/f32-vsigmoid-avx-rr2-p5-div-u32.c", |
| "src/f32-vsigmoid/gen/f32-vsigmoid-avx-rr2-p5-div-u40.c", |
| "src/f32-vsigmoid/gen/f32-vsigmoid-avx-rr2-p5-div-u48.c", |
| "src/f32-vsigmoid/gen/f32-vsigmoid-avx-rr2-p5-div-u56.c", |
| "src/f32-vsigmoid/gen/f32-vsigmoid-avx-rr2-p5-div-u64.c", |
| "src/f32-vsigmoid/gen/f32-vsigmoid-avx-rr2-p5-div-u72.c", |
| "src/f32-vsigmoid/gen/f32-vsigmoid-avx-rr2-p5-div-u80.c", |
| "src/f32-vsigmoid/gen/f32-vsigmoid-avx-rr2-p5-nr2-u8.c", |
| "src/f32-vsigmoid/gen/f32-vsigmoid-avx-rr2-p5-nr2-u16.c", |
| "src/f32-vsigmoid/gen/f32-vsigmoid-avx-rr2-p5-nr2-u24.c", |
| "src/f32-vsigmoid/gen/f32-vsigmoid-avx-rr2-p5-nr2-u32.c", |
| "src/f32-vsigmoid/gen/f32-vsigmoid-avx-rr2-p5-nr2-u40.c", |
| "src/f32-vsigmoid/gen/f32-vsigmoid-avx-rr2-p5-nr2-u48.c", |
| "src/f32-vsigmoid/gen/f32-vsigmoid-avx-rr2-p5-nr2-u56.c", |
| "src/f32-vsigmoid/gen/f32-vsigmoid-avx-rr2-p5-nr2-u64.c", |
| "src/f32-vsigmoid/gen/f32-vsigmoid-avx-rr2-p5-nr2-u72.c", |
| "src/f32-vsigmoid/gen/f32-vsigmoid-avx-rr2-p5-nr2-u80.c", |
| "src/f32-vsqrt/gen/f32-vsqrt-avx-sqrt-u8.c", |
| "src/f32-vsqrt/gen/f32-vsqrt-avx-sqrt-u16.c", |
| "src/f32-vtanh/gen/f32-vtanh-avx-expm1minus-rr1-lut4-p4h2ts-perm-div-u8.c", |
| "src/f32-vtanh/gen/f32-vtanh-avx-expm1minus-rr1-lut4-p4h2ts-perm-div-u16.c", |
| "src/f32-vtanh/gen/f32-vtanh-avx-expm1minus-rr1-lut4-p4h2ts-perm-div-u24.c", |
| "src/f32-vtanh/gen/f32-vtanh-avx-expm1minus-rr1-lut4-p4h2ts-perm-div-u32.c", |
| "src/f32-vtanh/gen/f32-vtanh-avx-expm1minus-rr1-lut4-p4h2ts-perm-div-u40.c", |
| "src/f32-vtanh/gen/f32-vtanh-avx-expm1minus-rr1-lut4-p4h2ts-perm-div-u48.c", |
| "src/f32-vtanh/gen/f32-vtanh-avx-expm1minus-rr1-lut4-p4h2ts-perm-div-u56.c", |
| "src/f32-vtanh/gen/f32-vtanh-avx-expm1minus-rr1-lut4-p4h2ts-perm-div-u64.c", |
| "src/f32-vtanh/gen/f32-vtanh-avx-expm1minus-rr1-lut4-p4h2ts-perm-div-u72.c", |
| "src/f32-vtanh/gen/f32-vtanh-avx-expm1minus-rr1-lut4-p4h2ts-perm-div-u80.c", |
| "src/f32-vtanh/gen/f32-vtanh-avx-expm1minus-rr1-lut8-p4h3ts-div-u8.c", |
| "src/f32-vtanh/gen/f32-vtanh-avx-expm1minus-rr1-lut8-p4h3ts-div-u16.c", |
| "src/f32-vtanh/gen/f32-vtanh-avx-expm1minus-rr1-lut8-p4h3ts-div-u24.c", |
| "src/f32-vtanh/gen/f32-vtanh-avx-expm1minus-rr1-lut8-p4h3ts-div-u32.c", |
| "src/f32-vtanh/gen/f32-vtanh-avx-expm1minus-rr1-p6h5ts-div-u8.c", |
| "src/f32-vtanh/gen/f32-vtanh-avx-expm1minus-rr1-p6h5ts-div-u16.c", |
| "src/f32-vtanh/gen/f32-vtanh-avx-expm1minus-rr1-p6h5ts-div-u24.c", |
| "src/f32-vtanh/gen/f32-vtanh-avx-expm1minus-rr1-p6h5ts-div-u32.c", |
| "src/f32-vtanh/gen/f32-vtanh-avx-expm1minus-rr1-p6h5ts-div-u40.c", |
| "src/f32-vtanh/gen/f32-vtanh-avx-expm1minus-rr1-p6h5ts-div-u48.c", |
| "src/f32-vtanh/gen/f32-vtanh-avx-expm1minus-rr1-p6h5ts-div-u56.c", |
| "src/f32-vtanh/gen/f32-vtanh-avx-expm1minus-rr1-p6h5ts-div-u64.c", |
| "src/f32-vtanh/gen/f32-vtanh-avx-expm1minus-rr1-p6h5ts-div-u72.c", |
| "src/f32-vtanh/gen/f32-vtanh-avx-expm1minus-rr1-p6h5ts-div-u80.c", |
| "src/f32-vtanh/gen/f32-vtanh-avx-expm1minus-rr1-p6h5ts-nr1-u8.c", |
| "src/f32-vtanh/gen/f32-vtanh-avx-expm1minus-rr1-p6h5ts-nr1-u16.c", |
| "src/f32-vtanh/gen/f32-vtanh-avx-expm1minus-rr1-p6h5ts-nr1-u24.c", |
| "src/f32-vtanh/gen/f32-vtanh-avx-expm1minus-rr1-p6h5ts-nr1-u32.c", |
| "src/f32-vtanh/gen/f32-vtanh-avx-expm1minus-rr1-p6h5ts-nr1-u40.c", |
| "src/f32-vtanh/gen/f32-vtanh-avx-expm1minus-rr1-p6h5ts-nr1-u48.c", |
| "src/f32-vtanh/gen/f32-vtanh-avx-expm1minus-rr1-p6h5ts-nr1-u56.c", |
| "src/f32-vtanh/gen/f32-vtanh-avx-expm1minus-rr1-p6h5ts-nr1-u64.c", |
| "src/f32-vtanh/gen/f32-vtanh-avx-expm1minus-rr1-p6h5ts-nr1-u72.c", |
| "src/f32-vtanh/gen/f32-vtanh-avx-expm1minus-rr1-p6h5ts-nr1-u80.c", |
| "src/f32-vtanh/gen/f32-vtanh-avx-expm1minus-rr1-p6h5ts-nr2-u8.c", |
| "src/f32-vtanh/gen/f32-vtanh-avx-expm1minus-rr1-p6h5ts-nr2-u16.c", |
| "src/f32-vtanh/gen/f32-vtanh-avx-expm1minus-rr1-p6h5ts-nr2-u24.c", |
| "src/f32-vtanh/gen/f32-vtanh-avx-expm1minus-rr1-p6h5ts-nr2-u32.c", |
| "src/f32-vtanh/gen/f32-vtanh-avx-expm1minus-rr1-p6h5ts-nr2-u40.c", |
| "src/f32-vtanh/gen/f32-vtanh-avx-expm1minus-rr1-p6h5ts-nr2-u48.c", |
| "src/f32-vtanh/gen/f32-vtanh-avx-expm1minus-rr1-p6h5ts-nr2-u56.c", |
| "src/f32-vtanh/gen/f32-vtanh-avx-expm1minus-rr1-p6h5ts-nr2-u64.c", |
| "src/f32-vtanh/gen/f32-vtanh-avx-expm1minus-rr1-p6h5ts-nr2-u72.c", |
| "src/f32-vtanh/gen/f32-vtanh-avx-expm1minus-rr1-p6h5ts-nr2-u80.c", |
| "src/f32-vunary/gen/f32-vabs-avx-u8.c", |
| "src/f32-vunary/gen/f32-vabs-avx-u16.c", |
| "src/f32-vunary/gen/f32-vneg-avx-u8.c", |
| "src/f32-vunary/gen/f32-vneg-avx-u16.c", |
| "src/f32-vunary/gen/f32-vsqr-avx-u8.c", |
| "src/f32-vunary/gen/f32-vsqr-avx-u16.c", |
| "src/math/f32-exp-avx-rr2-p5.c", |
| "src/math/f32-expm1minus-avx-rr2-lut4-p4-perm.c", |
| "src/math/f32-expm1minus-avx-rr2-lut16-p3.c", |
| "src/math/f32-expm1minus-avx-rr2-p6.c", |
| "src/math/f32-sigmoid-avx-rr2-lut64-p2-div.c", |
| "src/math/f32-sigmoid-avx-rr2-p5-div.c", |
| "src/math/f32-sigmoid-avx-rr2-p5-nr1.c", |
| "src/math/f32-sigmoid-avx-rr2-p5-nr2.c", |
| "src/math/gen/f32-tanh-avx-expm1minus-rr1-lut4-p4h2ts-perm-div.c", |
| "src/math/gen/f32-tanh-avx-expm1minus-rr1-lut8-p4h3ps-div.c", |
| "src/math/gen/f32-tanh-avx-expm1minus-rr1-p6h5ts-div.c", |
| "src/math/gen/f32-tanh-avx-expm1minus-rr1-p6h5ts-nr1.c", |
| "src/math/gen/f32-tanh-avx-expm1minus-rr1-p6h5ts-nr2.c", |
| "src/math/gen/f32-tanh-avx-expm1minus-rr2-lut8-p4h2ts-nr1.c", |
| "src/math/gen/f32-tanh-avx-expm1minus-rr2-lut8-p4h2ts-nr2.c", |
| "src/math/gen/f32-tanh-avx-expm1minus-rr2-lut8-p4h3ps-nr1.c", |
| "src/math/gen/f32-tanh-avx-expm1minus-rr2-lut8-p4h3ps-nr2.c", |
| "src/math/gen/f32-tanh-avx-expm1minus-rr2-lut8-p4h3ts-nr1.c", |
| "src/math/gen/f32-tanh-avx-expm1minus-rr2-lut8-p4h3ts-nr2.c", |
| "src/qd8-f32-qc8w-gemm/gen/qd8-f32-qc8w-gemm-1x4c8-minmax-avx-ld64.c", |
| "src/qd8-f32-qc8w-gemm/gen/qd8-f32-qc8w-gemm-1x4c8-minmax-avx-ld128.c", |
| "src/qd8-f32-qc8w-gemm/gen/qd8-f32-qc8w-gemm-2x4c8-minmax-avx-ld64.c", |
| "src/qd8-f32-qc8w-gemm/gen/qd8-f32-qc8w-gemm-2x4c8-minmax-avx-ld128.c", |
| "src/qd8-f32-qc8w-gemm/gen/qd8-f32-qc8w-gemm-3x4c8-minmax-avx-ld64.c", |
| "src/qd8-f32-qc8w-gemm/gen/qd8-f32-qc8w-gemm-3x4c8-minmax-avx-ld128.c", |
| "src/qd8-f32-qc8w-gemm/gen/qd8-f32-qc8w-gemm-4x4c8-minmax-avx-ld64.c", |
| "src/qd8-f32-qc8w-gemm/gen/qd8-f32-qc8w-gemm-4x4c8-minmax-avx-ld128.c", |
| "src/qs8-dwconv/gen/qs8-dwconv-5f5m5l8c4s4r-minmax-fp32-avx-mul32.c", |
| "src/qs8-dwconv/gen/qs8-dwconv-5f5m5l16c4s4r-minmax-fp32-avx-mul32.c", |
| "src/qs8-dwconv/gen/qs8-dwconv-6f6m7l8c4s4r-minmax-fp32-avx-mul32.c", |
| "src/qs8-dwconv/gen/qs8-dwconv-6f6m7l16c4s4r-minmax-fp32-avx-mul32.c", |
| "src/qs8-dwconv/gen/qs8-dwconv-8f8m9l8c4s4r-minmax-fp32-avx-mul32.c", |
| "src/qs8-dwconv/gen/qs8-dwconv-8f8m9l16c4s4r-minmax-fp32-avx-mul32.c", |
| "src/qs8-dwconv/gen/qs8-dwconv-9p8c-minmax-fp32-avx-mul16-add16.c", |
| "src/qs8-dwconv/gen/qs8-dwconv-9p8c-minmax-fp32-avx-mul16.c", |
| "src/qs8-dwconv/gen/qs8-dwconv-9p8c-minmax-fp32-avx-mul32.c", |
| "src/qs8-dwconv/gen/qs8-dwconv-9p16c-minmax-fp32-avx-mul16-add16.c", |
| "src/qs8-dwconv/gen/qs8-dwconv-9p16c-minmax-fp32-avx-mul16.c", |
| "src/qs8-dwconv/gen/qs8-dwconv-9p16c-minmax-fp32-avx-mul32.c", |
| "src/qs8-dwconv/gen/qs8-dwconv-25p8c-minmax-fp32-avx-mul16-add16.c", |
| "src/qs8-dwconv/gen/qs8-dwconv-25p8c-minmax-fp32-avx-mul16.c", |
| "src/qs8-dwconv/gen/qs8-dwconv-25p8c-minmax-fp32-avx-mul32.c", |
| "src/qs8-dwconv/gen/qs8-dwconv-25p16c-minmax-fp32-avx-mul16-add16.c", |
| "src/qs8-dwconv/gen/qs8-dwconv-25p16c-minmax-fp32-avx-mul16.c", |
| "src/qs8-dwconv/gen/qs8-dwconv-25p16c-minmax-fp32-avx-mul32.c", |
| "src/qs8-f32-vcvt/gen/qs8-f32-vcvt-avx-u8.c", |
| "src/qs8-f32-vcvt/gen/qs8-f32-vcvt-avx-u16.c", |
| "src/qs8-f32-vcvt/gen/qs8-f32-vcvt-avx-u24.c", |
| "src/qs8-f32-vcvt/gen/qs8-f32-vcvt-avx-u32.c", |
| "src/qs8-gemm/gen/qs8-gemm-1x4c2-minmax-fp32-avx-ld64.c", |
| "src/qs8-gemm/gen/qs8-gemm-1x4c2-minmax-fp32-avx-ld128.c", |
| "src/qs8-gemm/gen/qs8-gemm-1x4c2-xw-minmax-fp32-avx.c", |
| "src/qs8-gemm/gen/qs8-gemm-1x4c2s4-minmax-fp32-avx-ld64.c", |
| "src/qs8-gemm/gen/qs8-gemm-1x4c2s4-minmax-fp32-avx-ld128.c", |
| "src/qs8-gemm/gen/qs8-gemm-1x4c2s4-xw-minmax-fp32-avx.c", |
| "src/qs8-gemm/gen/qs8-gemm-1x4c8-minmax-fp32-avx-ld64.c", |
| "src/qs8-gemm/gen/qs8-gemm-1x4c8-minmax-fp32-avx-ld128.c", |
| "src/qs8-gemm/gen/qs8-gemm-1x4c8-xw-minmax-fp32-avx.c", |
| "src/qs8-gemm/gen/qs8-gemm-2x4c2-minmax-fp32-avx-ld64.c", |
| "src/qs8-gemm/gen/qs8-gemm-2x4c2-minmax-fp32-avx-ld128.c", |
| "src/qs8-gemm/gen/qs8-gemm-2x4c2-xw-minmax-fp32-avx.c", |
| "src/qs8-gemm/gen/qs8-gemm-2x4c2s4-minmax-fp32-avx-ld64.c", |
| "src/qs8-gemm/gen/qs8-gemm-2x4c2s4-minmax-fp32-avx-ld128.c", |
| "src/qs8-gemm/gen/qs8-gemm-2x4c2s4-xw-minmax-fp32-avx.c", |
| "src/qs8-gemm/gen/qs8-gemm-2x4c8-minmax-fp32-avx-ld64.c", |
| "src/qs8-gemm/gen/qs8-gemm-2x4c8-minmax-fp32-avx-ld128.c", |
| "src/qs8-gemm/gen/qs8-gemm-2x4c8-xw-minmax-fp32-avx.c", |
| "src/qs8-gemm/gen/qs8-gemm-3x4c2-minmax-fp32-avx-ld64.c", |
| "src/qs8-gemm/gen/qs8-gemm-3x4c2-minmax-fp32-avx-ld128.c", |
| "src/qs8-gemm/gen/qs8-gemm-3x4c2-xw-minmax-fp32-avx.c", |
| "src/qs8-gemm/gen/qs8-gemm-3x4c2s4-minmax-fp32-avx-ld64.c", |
| "src/qs8-gemm/gen/qs8-gemm-3x4c2s4-minmax-fp32-avx-ld128.c", |
| "src/qs8-gemm/gen/qs8-gemm-3x4c2s4-xw-minmax-fp32-avx.c", |
| "src/qs8-gemm/gen/qs8-gemm-3x4c8-minmax-fp32-avx-ld64.c", |
| "src/qs8-gemm/gen/qs8-gemm-3x4c8-minmax-fp32-avx-ld128.c", |
| "src/qs8-gemm/gen/qs8-gemm-3x4c8-xw-minmax-fp32-avx.c", |
| "src/qs8-gemm/gen/qs8-gemm-4x4c2-minmax-fp32-avx-ld64.c", |
| "src/qs8-gemm/gen/qs8-gemm-4x4c2-minmax-fp32-avx-ld128.c", |
| "src/qs8-gemm/gen/qs8-gemm-4x4c2-xw-minmax-fp32-avx.c", |
| "src/qs8-gemm/gen/qs8-gemm-4x4c2s4-minmax-fp32-avx-ld64.c", |
| "src/qs8-gemm/gen/qs8-gemm-4x4c2s4-minmax-fp32-avx-ld128.c", |
| "src/qs8-gemm/gen/qs8-gemm-4x4c2s4-xw-minmax-fp32-avx.c", |
| "src/qs8-igemm/gen/qs8-igemm-1x4c2-minmax-fp32-avx-ld64.c", |
| "src/qs8-igemm/gen/qs8-igemm-1x4c2-minmax-fp32-avx-ld128.c", |
| "src/qs8-igemm/gen/qs8-igemm-1x4c2s4-minmax-fp32-avx-ld64.c", |
| "src/qs8-igemm/gen/qs8-igemm-1x4c2s4-minmax-fp32-avx-ld128.c", |
| "src/qs8-igemm/gen/qs8-igemm-1x4c8-minmax-fp32-avx-ld64.c", |
| "src/qs8-igemm/gen/qs8-igemm-1x4c8-minmax-fp32-avx-ld128.c", |
| "src/qs8-igemm/gen/qs8-igemm-2x4c2-minmax-fp32-avx-ld64.c", |
| "src/qs8-igemm/gen/qs8-igemm-2x4c2-minmax-fp32-avx-ld128.c", |
| "src/qs8-igemm/gen/qs8-igemm-2x4c2s4-minmax-fp32-avx-ld64.c", |
| "src/qs8-igemm/gen/qs8-igemm-2x4c2s4-minmax-fp32-avx-ld128.c", |
| "src/qs8-igemm/gen/qs8-igemm-2x4c8-minmax-fp32-avx-ld64.c", |
| "src/qs8-igemm/gen/qs8-igemm-2x4c8-minmax-fp32-avx-ld128.c", |
| "src/qs8-igemm/gen/qs8-igemm-3x4c2-minmax-fp32-avx-ld64.c", |
| "src/qs8-igemm/gen/qs8-igemm-3x4c2-minmax-fp32-avx-ld128.c", |
| "src/qs8-igemm/gen/qs8-igemm-3x4c2s4-minmax-fp32-avx-ld64.c", |
| "src/qs8-igemm/gen/qs8-igemm-3x4c2s4-minmax-fp32-avx-ld128.c", |
| "src/qs8-igemm/gen/qs8-igemm-3x4c8-minmax-fp32-avx-ld64.c", |
| "src/qs8-igemm/gen/qs8-igemm-3x4c8-minmax-fp32-avx-ld128.c", |
| "src/qs8-igemm/gen/qs8-igemm-4x4c2-minmax-fp32-avx-ld64.c", |
| "src/qs8-igemm/gen/qs8-igemm-4x4c2-minmax-fp32-avx-ld128.c", |
| "src/qs8-igemm/gen/qs8-igemm-4x4c2s4-minmax-fp32-avx-ld64.c", |
| "src/qs8-igemm/gen/qs8-igemm-4x4c2s4-minmax-fp32-avx-ld128.c", |
| "src/qs8-qc8w-dwconv/gen/qs8-qc8w-dwconv-3p16c-minmax-fp32-avx-mul16-add16.c", |
| "src/qs8-qc8w-dwconv/gen/qs8-qc8w-dwconv-5f5m5l8c4s4r-minmax-fp32-avx-mul32.c", |
| "src/qs8-qc8w-dwconv/gen/qs8-qc8w-dwconv-5f5m5l16c4s4r-minmax-fp32-avx-mul32.c", |
| "src/qs8-qc8w-dwconv/gen/qs8-qc8w-dwconv-6f6m7l8c4s4r-minmax-fp32-avx-mul32.c", |
| "src/qs8-qc8w-dwconv/gen/qs8-qc8w-dwconv-6f6m7l16c4s4r-minmax-fp32-avx-mul32.c", |
| "src/qs8-qc8w-dwconv/gen/qs8-qc8w-dwconv-8f8m9l8c4s4r-minmax-fp32-avx-mul32.c", |
| "src/qs8-qc8w-dwconv/gen/qs8-qc8w-dwconv-8f8m9l16c4s4r-minmax-fp32-avx-mul32.c", |
| "src/qs8-qc8w-dwconv/gen/qs8-qc8w-dwconv-9p8c-minmax-fp32-avx-mul16-add16.c", |
| "src/qs8-qc8w-dwconv/gen/qs8-qc8w-dwconv-9p8c-minmax-fp32-avx-mul16.c", |
| "src/qs8-qc8w-dwconv/gen/qs8-qc8w-dwconv-9p8c-minmax-fp32-avx-mul32.c", |
| "src/qs8-qc8w-dwconv/gen/qs8-qc8w-dwconv-9p16c-minmax-fp32-avx-mul16-add16.c", |
| "src/qs8-qc8w-dwconv/gen/qs8-qc8w-dwconv-9p16c-minmax-fp32-avx-mul16.c", |
| "src/qs8-qc8w-dwconv/gen/qs8-qc8w-dwconv-9p16c-minmax-fp32-avx-mul32.c", |
| "src/qs8-qc8w-dwconv/gen/qs8-qc8w-dwconv-25p8c-minmax-fp32-avx-mul16-add16.c", |
| "src/qs8-qc8w-dwconv/gen/qs8-qc8w-dwconv-25p8c-minmax-fp32-avx-mul16.c", |
| "src/qs8-qc8w-dwconv/gen/qs8-qc8w-dwconv-25p8c-minmax-fp32-avx-mul32.c", |
| "src/qs8-qc8w-dwconv/gen/qs8-qc8w-dwconv-25p16c-minmax-fp32-avx-mul16-add16.c", |
| "src/qs8-qc8w-dwconv/gen/qs8-qc8w-dwconv-25p16c-minmax-fp32-avx-mul16.c", |
| "src/qs8-qc8w-dwconv/gen/qs8-qc8w-dwconv-25p16c-minmax-fp32-avx-mul32.c", |
| "src/qs8-qc8w-gemm/gen/qs8-qc8w-gemm-1x4c2-minmax-fp32-avx-ld64.c", |
| "src/qs8-qc8w-gemm/gen/qs8-qc8w-gemm-1x4c2-minmax-fp32-avx-ld128.c", |
| "src/qs8-qc8w-gemm/gen/qs8-qc8w-gemm-1x4c2s4-minmax-fp32-avx-ld64.c", |
| "src/qs8-qc8w-gemm/gen/qs8-qc8w-gemm-1x4c2s4-minmax-fp32-avx-ld128.c", |
| "src/qs8-qc8w-gemm/gen/qs8-qc8w-gemm-1x4c8-minmax-fp32-avx-ld64.c", |
| "src/qs8-qc8w-gemm/gen/qs8-qc8w-gemm-1x4c8-minmax-fp32-avx-ld128.c", |
| "src/qs8-qc8w-gemm/gen/qs8-qc8w-gemm-2x4c2-minmax-fp32-avx-ld64.c", |
| "src/qs8-qc8w-gemm/gen/qs8-qc8w-gemm-2x4c2-minmax-fp32-avx-ld128.c", |
| "src/qs8-qc8w-gemm/gen/qs8-qc8w-gemm-2x4c2s4-minmax-fp32-avx-ld64.c", |
| "src/qs8-qc8w-gemm/gen/qs8-qc8w-gemm-2x4c2s4-minmax-fp32-avx-ld128.c", |
| "src/qs8-qc8w-gemm/gen/qs8-qc8w-gemm-2x4c8-minmax-fp32-avx-ld64.c", |
| "src/qs8-qc8w-gemm/gen/qs8-qc8w-gemm-2x4c8-minmax-fp32-avx-ld128.c", |
| "src/qs8-qc8w-gemm/gen/qs8-qc8w-gemm-3x4c2-minmax-fp32-avx-ld64.c", |
| "src/qs8-qc8w-gemm/gen/qs8-qc8w-gemm-3x4c2-minmax-fp32-avx-ld128.c", |
| "src/qs8-qc8w-gemm/gen/qs8-qc8w-gemm-3x4c2s4-minmax-fp32-avx-ld64.c", |
| "src/qs8-qc8w-gemm/gen/qs8-qc8w-gemm-3x4c2s4-minmax-fp32-avx-ld128.c", |
| "src/qs8-qc8w-gemm/gen/qs8-qc8w-gemm-3x4c8-minmax-fp32-avx-ld64.c", |
| "src/qs8-qc8w-gemm/gen/qs8-qc8w-gemm-3x4c8-minmax-fp32-avx-ld128.c", |
| "src/qs8-qc8w-gemm/gen/qs8-qc8w-gemm-4x4c2-minmax-fp32-avx-ld64.c", |
| "src/qs8-qc8w-gemm/gen/qs8-qc8w-gemm-4x4c2-minmax-fp32-avx-ld128.c", |
| "src/qs8-qc8w-gemm/gen/qs8-qc8w-gemm-4x4c2s4-minmax-fp32-avx-ld64.c", |
| "src/qs8-qc8w-gemm/gen/qs8-qc8w-gemm-4x4c2s4-minmax-fp32-avx-ld128.c", |
| "src/qs8-qc8w-igemm/gen/qs8-qc8w-igemm-1x4c2-minmax-fp32-avx-ld64.c", |
| "src/qs8-qc8w-igemm/gen/qs8-qc8w-igemm-1x4c2-minmax-fp32-avx-ld128.c", |
| "src/qs8-qc8w-igemm/gen/qs8-qc8w-igemm-1x4c2s4-minmax-fp32-avx-ld64.c", |
| "src/qs8-qc8w-igemm/gen/qs8-qc8w-igemm-1x4c2s4-minmax-fp32-avx-ld128.c", |
| "src/qs8-qc8w-igemm/gen/qs8-qc8w-igemm-1x4c8-minmax-fp32-avx-ld64.c", |
| "src/qs8-qc8w-igemm/gen/qs8-qc8w-igemm-1x4c8-minmax-fp32-avx-ld128.c", |
| "src/qs8-qc8w-igemm/gen/qs8-qc8w-igemm-2x4c2-minmax-fp32-avx-ld64.c", |
| "src/qs8-qc8w-igemm/gen/qs8-qc8w-igemm-2x4c2-minmax-fp32-avx-ld128.c", |
| "src/qs8-qc8w-igemm/gen/qs8-qc8w-igemm-2x4c2s4-minmax-fp32-avx-ld64.c", |
| "src/qs8-qc8w-igemm/gen/qs8-qc8w-igemm-2x4c2s4-minmax-fp32-avx-ld128.c", |
| "src/qs8-qc8w-igemm/gen/qs8-qc8w-igemm-2x4c8-minmax-fp32-avx-ld64.c", |
| "src/qs8-qc8w-igemm/gen/qs8-qc8w-igemm-2x4c8-minmax-fp32-avx-ld128.c", |
| "src/qs8-qc8w-igemm/gen/qs8-qc8w-igemm-3x4c2-minmax-fp32-avx-ld64.c", |
| "src/qs8-qc8w-igemm/gen/qs8-qc8w-igemm-3x4c2-minmax-fp32-avx-ld128.c", |
| "src/qs8-qc8w-igemm/gen/qs8-qc8w-igemm-3x4c2s4-minmax-fp32-avx-ld64.c", |
| "src/qs8-qc8w-igemm/gen/qs8-qc8w-igemm-3x4c2s4-minmax-fp32-avx-ld128.c", |
| "src/qs8-qc8w-igemm/gen/qs8-qc8w-igemm-3x4c8-minmax-fp32-avx-ld64.c", |
| "src/qs8-qc8w-igemm/gen/qs8-qc8w-igemm-3x4c8-minmax-fp32-avx-ld128.c", |
| "src/qs8-qc8w-igemm/gen/qs8-qc8w-igemm-4x4c2-minmax-fp32-avx-ld64.c", |
| "src/qs8-qc8w-igemm/gen/qs8-qc8w-igemm-4x4c2-minmax-fp32-avx-ld128.c", |
| "src/qs8-qc8w-igemm/gen/qs8-qc8w-igemm-4x4c2s4-minmax-fp32-avx-ld64.c", |
| "src/qs8-qc8w-igemm/gen/qs8-qc8w-igemm-4x4c2s4-minmax-fp32-avx-ld128.c", |
| "src/qs8-vadd/gen/qs8-vadd-minmax-avx-mul16-ld64-u8.c", |
| "src/qs8-vadd/gen/qs8-vadd-minmax-avx-mul16-ld64-u16.c", |
| "src/qs8-vadd/gen/qs8-vadd-minmax-avx-mul16-ld64-u24.c", |
| "src/qs8-vadd/gen/qs8-vadd-minmax-avx-mul16-ld64-u32.c", |
| "src/qs8-vadd/gen/qs8-vadd-minmax-avx-mul32-ld32-u8.c", |
| "src/qs8-vadd/gen/qs8-vadd-minmax-avx-mul32-ld32-u16.c", |
| "src/qs8-vadd/gen/qs8-vadd-minmax-avx-mul32-ld32-u24.c", |
| "src/qs8-vadd/gen/qs8-vadd-minmax-avx-mul32-ld32-u32.c", |
| "src/qs8-vaddc/gen/qs8-vaddc-minmax-avx-mul16-ld64-u8.c", |
| "src/qs8-vaddc/gen/qs8-vaddc-minmax-avx-mul16-ld64-u16.c", |
| "src/qs8-vaddc/gen/qs8-vaddc-minmax-avx-mul16-ld64-u24.c", |
| "src/qs8-vaddc/gen/qs8-vaddc-minmax-avx-mul16-ld64-u32.c", |
| "src/qs8-vaddc/gen/qs8-vaddc-minmax-avx-mul32-ld32-u8.c", |
| "src/qs8-vaddc/gen/qs8-vaddc-minmax-avx-mul32-ld32-u16.c", |
| "src/qs8-vaddc/gen/qs8-vaddc-minmax-avx-mul32-ld32-u24.c", |
| "src/qs8-vaddc/gen/qs8-vaddc-minmax-avx-mul32-ld32-u32.c", |
| "src/qs8-vcvt/gen/qs8-vcvt-avx-u8.c", |
| "src/qs8-vcvt/gen/qs8-vcvt-avx-u16.c", |
| "src/qs8-vcvt/gen/qs8-vcvt-avx-u32.c", |
| "src/qs8-vlrelu/gen/qs8-vlrelu-avx-u8.c", |
| "src/qs8-vlrelu/gen/qs8-vlrelu-avx-u16.c", |
| "src/qs8-vlrelu/gen/qs8-vlrelu-avx-u32.c", |
| "src/qs8-vmul/gen/qs8-vmul-minmax-fp32-avx-mul16-ld64-u8.c", |
| "src/qs8-vmul/gen/qs8-vmul-minmax-fp32-avx-mul16-ld64-u16.c", |
| "src/qs8-vmulc/gen/qs8-vmulc-minmax-fp32-avx-mul16-ld64-u8.c", |
| "src/qs8-vmulc/gen/qs8-vmulc-minmax-fp32-avx-mul16-ld64-u16.c", |
| "src/qs16-qs8-vcvt/gen/qs16-qs8-vcvt-avx-u4.c", |
| "src/qs16-qs8-vcvt/gen/qs16-qs8-vcvt-avx-u8.c", |
| "src/qs16-qs8-vcvt/gen/qs16-qs8-vcvt-avx-u16.c", |
| "src/qu8-dwconv/gen/qu8-dwconv-5f5m5l8c4s4r-minmax-fp32-avx-mul32.c", |
| "src/qu8-dwconv/gen/qu8-dwconv-5f5m5l16c4s4r-minmax-fp32-avx-mul32.c", |
| "src/qu8-dwconv/gen/qu8-dwconv-6f6m7l8c4s4r-minmax-fp32-avx-mul32.c", |
| "src/qu8-dwconv/gen/qu8-dwconv-6f6m7l16c4s4r-minmax-fp32-avx-mul32.c", |
| "src/qu8-dwconv/gen/qu8-dwconv-8f8m9l8c4s4r-minmax-fp32-avx-mul32.c", |
| "src/qu8-dwconv/gen/qu8-dwconv-8f8m9l16c4s4r-minmax-fp32-avx-mul32.c", |
| "src/qu8-dwconv/gen/qu8-dwconv-9p8c-minmax-fp32-avx-mul16.c", |
| "src/qu8-dwconv/gen/qu8-dwconv-9p8c-minmax-fp32-avx-mul32.c", |
| "src/qu8-dwconv/gen/qu8-dwconv-9p16c-minmax-fp32-avx-mul16.c", |
| "src/qu8-dwconv/gen/qu8-dwconv-9p16c-minmax-fp32-avx-mul32.c", |
| "src/qu8-dwconv/gen/qu8-dwconv-25p8c-minmax-fp32-avx-mul16.c", |
| "src/qu8-dwconv/gen/qu8-dwconv-25p8c-minmax-fp32-avx-mul32.c", |
| "src/qu8-dwconv/gen/qu8-dwconv-25p16c-minmax-fp32-avx-mul16.c", |
| "src/qu8-dwconv/gen/qu8-dwconv-25p16c-minmax-fp32-avx-mul32.c", |
| "src/qu8-f32-vcvt/gen/qu8-f32-vcvt-avx-u8.c", |
| "src/qu8-f32-vcvt/gen/qu8-f32-vcvt-avx-u16.c", |
| "src/qu8-f32-vcvt/gen/qu8-f32-vcvt-avx-u24.c", |
| "src/qu8-f32-vcvt/gen/qu8-f32-vcvt-avx-u32.c", |
| "src/qu8-gemm/gen/qu8-gemm-1x4c2-minmax-fp32-avx-ld64.c", |
| "src/qu8-gemm/gen/qu8-gemm-1x4c2-minmax-fp32-avx-ld128.c", |
| "src/qu8-gemm/gen/qu8-gemm-1x4c2s4-minmax-fp32-avx-ld64.c", |
| "src/qu8-gemm/gen/qu8-gemm-1x4c2s4-minmax-fp32-avx-ld128.c", |
| "src/qu8-gemm/gen/qu8-gemm-1x4c8-minmax-fp32-avx-ld64.c", |
| "src/qu8-gemm/gen/qu8-gemm-1x4c8-minmax-fp32-avx-ld128.c", |
| "src/qu8-gemm/gen/qu8-gemm-2x4c2-minmax-fp32-avx-ld64.c", |
| "src/qu8-gemm/gen/qu8-gemm-2x4c2-minmax-fp32-avx-ld128.c", |
| "src/qu8-gemm/gen/qu8-gemm-2x4c2s4-minmax-fp32-avx-ld64.c", |
| "src/qu8-gemm/gen/qu8-gemm-2x4c2s4-minmax-fp32-avx-ld128.c", |
| "src/qu8-gemm/gen/qu8-gemm-2x4c8-minmax-fp32-avx-ld64.c", |
| "src/qu8-gemm/gen/qu8-gemm-2x4c8-minmax-fp32-avx-ld128.c", |
| "src/qu8-gemm/gen/qu8-gemm-3x4c2-minmax-fp32-avx-ld64.c", |
| "src/qu8-gemm/gen/qu8-gemm-3x4c2-minmax-fp32-avx-ld128.c", |
| "src/qu8-gemm/gen/qu8-gemm-3x4c2s4-minmax-fp32-avx-ld64.c", |
| "src/qu8-gemm/gen/qu8-gemm-3x4c2s4-minmax-fp32-avx-ld128.c", |
| "src/qu8-gemm/gen/qu8-gemm-3x4c8-minmax-fp32-avx-ld64.c", |
| "src/qu8-gemm/gen/qu8-gemm-3x4c8-minmax-fp32-avx-ld128.c", |
| "src/qu8-gemm/gen/qu8-gemm-4x4c2-minmax-fp32-avx-ld64.c", |
| "src/qu8-gemm/gen/qu8-gemm-4x4c2-minmax-fp32-avx-ld128.c", |
| "src/qu8-gemm/gen/qu8-gemm-4x4c2s4-minmax-fp32-avx-ld64.c", |
| "src/qu8-gemm/gen/qu8-gemm-4x4c2s4-minmax-fp32-avx-ld128.c", |
| "src/qu8-igemm/gen/qu8-igemm-1x4c2-minmax-fp32-avx-ld64.c", |
| "src/qu8-igemm/gen/qu8-igemm-1x4c2-minmax-fp32-avx-ld128.c", |
| "src/qu8-igemm/gen/qu8-igemm-1x4c2s4-minmax-fp32-avx-ld64.c", |
| "src/qu8-igemm/gen/qu8-igemm-1x4c2s4-minmax-fp32-avx-ld128.c", |
| "src/qu8-igemm/gen/qu8-igemm-1x4c8-minmax-fp32-avx-ld64.c", |
| "src/qu8-igemm/gen/qu8-igemm-1x4c8-minmax-fp32-avx-ld128.c", |
| "src/qu8-igemm/gen/qu8-igemm-2x4c2-minmax-fp32-avx-ld64.c", |
| "src/qu8-igemm/gen/qu8-igemm-2x4c2-minmax-fp32-avx-ld128.c", |
| "src/qu8-igemm/gen/qu8-igemm-2x4c2s4-minmax-fp32-avx-ld64.c", |
| "src/qu8-igemm/gen/qu8-igemm-2x4c2s4-minmax-fp32-avx-ld128.c", |
| "src/qu8-igemm/gen/qu8-igemm-2x4c8-minmax-fp32-avx-ld64.c", |
| "src/qu8-igemm/gen/qu8-igemm-2x4c8-minmax-fp32-avx-ld128.c", |
| "src/qu8-igemm/gen/qu8-igemm-3x4c2-minmax-fp32-avx-ld64.c", |
| "src/qu8-igemm/gen/qu8-igemm-3x4c2-minmax-fp32-avx-ld128.c", |
| "src/qu8-igemm/gen/qu8-igemm-3x4c2s4-minmax-fp32-avx-ld64.c", |
| "src/qu8-igemm/gen/qu8-igemm-3x4c2s4-minmax-fp32-avx-ld128.c", |
| "src/qu8-igemm/gen/qu8-igemm-3x4c8-minmax-fp32-avx-ld64.c", |
| "src/qu8-igemm/gen/qu8-igemm-3x4c8-minmax-fp32-avx-ld128.c", |
| "src/qu8-igemm/gen/qu8-igemm-4x4c2-minmax-fp32-avx-ld64.c", |
| "src/qu8-igemm/gen/qu8-igemm-4x4c2-minmax-fp32-avx-ld128.c", |
| "src/qu8-igemm/gen/qu8-igemm-4x4c2s4-minmax-fp32-avx-ld64.c", |
| "src/qu8-igemm/gen/qu8-igemm-4x4c2s4-minmax-fp32-avx-ld128.c", |
| "src/qu8-vadd/gen/qu8-vadd-minmax-avx-mul16-ld64-u8.c", |
| "src/qu8-vadd/gen/qu8-vadd-minmax-avx-mul16-ld64-u16.c", |
| "src/qu8-vadd/gen/qu8-vadd-minmax-avx-mul32-ld32-u8.c", |
| "src/qu8-vadd/gen/qu8-vadd-minmax-avx-mul32-ld32-u16.c", |
| "src/qu8-vaddc/gen/qu8-vaddc-minmax-avx-mul16-ld64-u8.c", |
| "src/qu8-vaddc/gen/qu8-vaddc-minmax-avx-mul16-ld64-u16.c", |
| "src/qu8-vaddc/gen/qu8-vaddc-minmax-avx-mul32-ld32-u8.c", |
| "src/qu8-vaddc/gen/qu8-vaddc-minmax-avx-mul32-ld32-u16.c", |
| "src/qu8-vcvt/gen/qu8-vcvt-avx-u8.c", |
| "src/qu8-vcvt/gen/qu8-vcvt-avx-u16.c", |
| "src/qu8-vcvt/gen/qu8-vcvt-avx-u32.c", |
| "src/qu8-vlrelu/gen/qu8-vlrelu-avx-u8.c", |
| "src/qu8-vlrelu/gen/qu8-vlrelu-avx-u16.c", |
| "src/qu8-vlrelu/gen/qu8-vlrelu-avx-u32.c", |
| "src/qu8-vmul/gen/qu8-vmul-minmax-fp32-avx-mul16-ld64-u8.c", |
| "src/qu8-vmul/gen/qu8-vmul-minmax-fp32-avx-mul16-ld64-u16.c", |
| "src/qu8-vmulc/gen/qu8-vmulc-minmax-fp32-avx-mul16-ld64-u8.c", |
| "src/qu8-vmulc/gen/qu8-vmulc-minmax-fp32-avx-mul16-ld64-u16.c", |
| "src/x8-lut/gen/x8-lut-avx-u16.c", |
| "src/x8-lut/gen/x8-lut-avx-u32.c", |
| "src/x8-lut/gen/x8-lut-avx-u48.c", |
| "src/x8-lut/gen/x8-lut-avx-u64.c", |
| "src/x32-packw/gen/x32-packw-x8-gemm-goi-avx-u4-prfm.c", |
| "src/x32-packw/gen/x32-packw-x8-gemm-goi-avx-u4.c", |
| "src/x32-packw/gen/x32-packw-x8s4-gemm-goi-avx-u4-prfm.c", |
| "src/x32-packw/gen/x32-packw-x8s4-gemm-goi-avx-u4.c", |
| "src/x32-packw/gen/x32-packw-x16-gemm-goi-avx-u4-prfm.c", |
| "src/x32-packw/gen/x32-packw-x16-gemm-goi-avx-u4.c", |
| "src/x32-packw/gen/x32-packw-x16s4-gemm-goi-avx-u4-prfm.c", |
| "src/x32-packw/gen/x32-packw-x16s4-gemm-goi-avx-u4.c", |
| "src/x32-transposec/gen/x32-transposec-8x8-multi-mov-avx.c", |
| "src/x32-transposec/gen/x32-transposec-8x8-multi-switch-avx.c", |
| "src/x32-transposec/gen/x32-transposec-8x8-reuse-mov-avx.c", |
| "src/x32-transposec/gen/x32-transposec-8x8-reuse-multi-avx.c", |
| "src/x32-transposec/gen/x32-transposec-8x8-reuse-switch-avx.c", |
| "src/x64-transposec/gen/x64-transposec-4x4-multi-mov-avx.c", |
| "src/x64-transposec/gen/x64-transposec-4x4-multi-multi-avx.c", |
| "src/x64-transposec/gen/x64-transposec-4x4-multi-switch-avx.c", |
| "src/x64-transposec/gen/x64-transposec-4x4-reuse-mov-avx.c", |
| "src/x64-transposec/gen/x64-transposec-4x4-reuse-multi-avx.c", |
| "src/x64-transposec/gen/x64-transposec-4x4-reuse-switch-avx.c", |
| ] |
| |
| ALL_AVX2_MICROKERNEL_SRCS = [ |
| "src/f16-f32acc-gemm/gen/f16-f32acc-gemm-1x8-minmax-avx2-broadcast.c", |
| "src/f16-f32acc-gemm/gen/f16-f32acc-gemm-1x16-minmax-avx2-broadcast.c", |
| "src/f16-f32acc-gemm/gen/f16-f32acc-gemm-3x16-minmax-avx2-broadcast.c", |
| "src/f16-f32acc-gemm/gen/f16-f32acc-gemm-4x8-minmax-avx2-broadcast.c", |
| "src/f16-f32acc-gemm/gen/f16-f32acc-gemm-4x16-minmax-avx2-broadcast.c", |
| "src/f16-f32acc-gemm/gen/f16-f32acc-gemm-5x8-minmax-avx2-broadcast.c", |
| "src/f16-f32acc-gemm/gen/f16-f32acc-gemm-5x16-minmax-avx2-broadcast.c", |
| "src/f16-f32acc-gemm/gen/f16-f32acc-gemm-6x8-minmax-avx2-broadcast.c", |
| "src/f16-f32acc-gemm/gen/f16-f32acc-gemm-7x8-minmax-avx2-broadcast.c", |
| "src/f16-f32acc-igemm/gen/f16-f32acc-igemm-1x8-minmax-avx2-broadcast.c", |
| "src/f16-f32acc-igemm/gen/f16-f32acc-igemm-1x16-minmax-avx2-broadcast.c", |
| "src/f16-f32acc-igemm/gen/f16-f32acc-igemm-3x16-minmax-avx2-broadcast.c", |
| "src/f16-f32acc-igemm/gen/f16-f32acc-igemm-4x8-minmax-avx2-broadcast.c", |
| "src/f16-f32acc-igemm/gen/f16-f32acc-igemm-4x16-minmax-avx2-broadcast.c", |
| "src/f16-f32acc-igemm/gen/f16-f32acc-igemm-5x8-minmax-avx2-broadcast.c", |
| "src/f16-f32acc-igemm/gen/f16-f32acc-igemm-5x16-minmax-avx2-broadcast.c", |
| "src/f16-f32acc-igemm/gen/f16-f32acc-igemm-6x8-minmax-avx2-broadcast.c", |
| "src/f16-f32acc-igemm/gen/f16-f32acc-igemm-7x8-minmax-avx2-broadcast.c", |
| "src/f16-gemm/gen/f16-gemm-1x8-minmax-avx2-broadcast.c", |
| "src/f16-gemm/gen/f16-gemm-1x16-minmax-avx2-broadcast.c", |
| "src/f16-gemm/gen/f16-gemm-3x16-minmax-avx2-broadcast.c", |
| "src/f16-gemm/gen/f16-gemm-4x8-minmax-avx2-broadcast.c", |
| "src/f16-gemm/gen/f16-gemm-4x16-minmax-avx2-broadcast.c", |
| "src/f16-gemm/gen/f16-gemm-5x8-minmax-avx2-broadcast.c", |
| "src/f16-gemm/gen/f16-gemm-5x16-minmax-avx2-broadcast.c", |
| "src/f16-gemm/gen/f16-gemm-6x8-minmax-avx2-broadcast.c", |
| "src/f16-gemm/gen/f16-gemm-7x8-minmax-avx2-broadcast.c", |
| "src/f16-igemm/gen/f16-igemm-1x8-minmax-avx2-broadcast.c", |
| "src/f16-igemm/gen/f16-igemm-1x16-minmax-avx2-broadcast.c", |
| "src/f16-igemm/gen/f16-igemm-3x16-minmax-avx2-broadcast.c", |
| "src/f16-igemm/gen/f16-igemm-4x8-minmax-avx2-broadcast.c", |
| "src/f16-igemm/gen/f16-igemm-4x16-minmax-avx2-broadcast.c", |
| "src/f16-igemm/gen/f16-igemm-5x8-minmax-avx2-broadcast.c", |
| "src/f16-igemm/gen/f16-igemm-5x16-minmax-avx2-broadcast.c", |
| "src/f16-igemm/gen/f16-igemm-6x8-minmax-avx2-broadcast.c", |
| "src/f16-igemm/gen/f16-igemm-7x8-minmax-avx2-broadcast.c", |
| "src/f16-pavgpool/f16-pavgpool-9p8x-minmax-avx2-c8.c", |
| "src/f16-pavgpool/f16-pavgpool-9x-minmax-avx2-c8.c", |
| "src/f16-raddstoreexpminusmax/gen/f16-raddstoreexpminusmax-avx2-rr1-p2-u32-acc2.c", |
| "src/f16-raddstoreexpminusmax/gen/f16-raddstoreexpminusmax-avx2-rr1-p2-u32-acc4.c", |
| "src/f16-raddstoreexpminusmax/gen/f16-raddstoreexpminusmax-avx2-rr1-p2-u32.c", |
| "src/f16-raddstoreexpminusmax/gen/f16-raddstoreexpminusmax-avx2-rr1-p2-u40-acc2.c", |
| "src/f16-raddstoreexpminusmax/gen/f16-raddstoreexpminusmax-avx2-rr1-p2-u40-acc5.c", |
| "src/f16-raddstoreexpminusmax/gen/f16-raddstoreexpminusmax-avx2-rr1-p2-u40.c", |
| "src/f16-raddstoreexpminusmax/gen/f16-raddstoreexpminusmax-avx2-rr1-p2-u48-acc2.c", |
| "src/f16-raddstoreexpminusmax/gen/f16-raddstoreexpminusmax-avx2-rr1-p2-u48-acc3.c", |
| "src/f16-raddstoreexpminusmax/gen/f16-raddstoreexpminusmax-avx2-rr1-p2-u48.c", |
| "src/f16-raddstoreexpminusmax/gen/f16-raddstoreexpminusmax-avx2-rr1-p2-u64-acc2.c", |
| "src/f16-raddstoreexpminusmax/gen/f16-raddstoreexpminusmax-avx2-rr1-p2-u64-acc4.c", |
| "src/f16-raddstoreexpminusmax/gen/f16-raddstoreexpminusmax-avx2-rr1-p2-u64.c", |
| "src/f16-raddstoreexpminusmax/gen/f16-raddstoreexpminusmax-avx2-rr1-p2-u72-acc3.c", |
| "src/f16-raddstoreexpminusmax/gen/f16-raddstoreexpminusmax-avx2-rr1-p2-u72.c", |
| "src/f16-raddstoreexpminusmax/gen/f16-raddstoreexpminusmax-avx2-rr1-p2-u80-acc2.c", |
| "src/f16-raddstoreexpminusmax/gen/f16-raddstoreexpminusmax-avx2-rr1-p2-u80-acc5.c", |
| "src/f16-raddstoreexpminusmax/gen/f16-raddstoreexpminusmax-avx2-rr1-p2-u80.c", |
| "src/f16-raddstoreexpminusmax/gen/f16-raddstoreexpminusmax-avx2-rr1-p2-u96-acc2.c", |
| "src/f16-raddstoreexpminusmax/gen/f16-raddstoreexpminusmax-avx2-rr1-p2-u96-acc3.c", |
| "src/f16-raddstoreexpminusmax/gen/f16-raddstoreexpminusmax-avx2-rr1-p2-u96-acc6.c", |
| "src/f16-raddstoreexpminusmax/gen/f16-raddstoreexpminusmax-avx2-rr1-p2-u96.c", |
| "src/f16-velu/gen/f16-velu-avx2-rr1-p3-u8.c", |
| "src/f16-velu/gen/f16-velu-avx2-rr1-p3-u16.c", |
| "src/f16-vsigmoid/gen/f16-vsigmoid-avx2-rr1-p2-div-u8.c", |
| "src/f16-vsigmoid/gen/f16-vsigmoid-avx2-rr1-p2-div-u16.c", |
| "src/f16-vsigmoid/gen/f16-vsigmoid-avx2-rr1-p2-div-u24.c", |
| "src/f16-vsigmoid/gen/f16-vsigmoid-avx2-rr1-p2-div-u32.c", |
| "src/f16-vsigmoid/gen/f16-vsigmoid-avx2-rr1-p2-div-u40.c", |
| "src/f16-vsigmoid/gen/f16-vsigmoid-avx2-rr1-p2-div-u48.c", |
| "src/f16-vsigmoid/gen/f16-vsigmoid-avx2-rr1-p2-div-u56.c", |
| "src/f16-vsigmoid/gen/f16-vsigmoid-avx2-rr1-p2-div-u64.c", |
| "src/f16-vsigmoid/gen/f16-vsigmoid-avx2-rr1-p2-rcp-u8.c", |
| "src/f16-vsigmoid/gen/f16-vsigmoid-avx2-rr1-p2-rcp-u16.c", |
| "src/f16-vsigmoid/gen/f16-vsigmoid-avx2-rr1-p2-rcp-u24.c", |
| "src/f16-vsigmoid/gen/f16-vsigmoid-avx2-rr1-p2-rcp-u32.c", |
| "src/f16-vsigmoid/gen/f16-vsigmoid-avx2-rr1-p2-rcp-u40.c", |
| "src/f16-vsigmoid/gen/f16-vsigmoid-avx2-rr1-p2-rcp-u48.c", |
| "src/f16-vsigmoid/gen/f16-vsigmoid-avx2-rr1-p2-rcp-u56.c", |
| "src/f16-vsigmoid/gen/f16-vsigmoid-avx2-rr1-p2-rcp-u64.c", |
| "src/f16-vtanh/gen/f16-vtanh-avx2-expm1minus-rr1-p3h2ts-div-u8.c", |
| "src/f16-vtanh/gen/f16-vtanh-avx2-expm1minus-rr1-p3h2ts-div-u16.c", |
| "src/f16-vtanh/gen/f16-vtanh-avx2-expm1minus-rr1-p3h2ts-div-u24.c", |
| "src/f16-vtanh/gen/f16-vtanh-avx2-expm1minus-rr1-p3h2ts-div-u32.c", |
| "src/f16-vtanh/gen/f16-vtanh-avx2-expm1minus-rr1-p3h2ts-div-u40.c", |
| "src/f16-vtanh/gen/f16-vtanh-avx2-expm1minus-rr1-p3h2ts-div-u48.c", |
| "src/f16-vtanh/gen/f16-vtanh-avx2-expm1minus-rr1-p3h2ts-div-u56.c", |
| "src/f16-vtanh/gen/f16-vtanh-avx2-expm1minus-rr1-p3h2ts-div-u64.c", |
| "src/f16-vtanh/gen/f16-vtanh-avx2-expm1minus-rr1-p3h2ts-div-u72.c", |
| "src/f16-vtanh/gen/f16-vtanh-avx2-expm1minus-rr1-p3h2ts-div-u80.c", |
| "src/f16-vtanh/gen/f16-vtanh-avx2-expm1minus-rr1-p3h2ts-rcp-u8.c", |
| "src/f16-vtanh/gen/f16-vtanh-avx2-expm1minus-rr1-p3h2ts-rcp-u16.c", |
| "src/f16-vtanh/gen/f16-vtanh-avx2-expm1minus-rr1-p3h2ts-rcp-u24.c", |
| "src/f16-vtanh/gen/f16-vtanh-avx2-expm1minus-rr1-p3h2ts-rcp-u32.c", |
| "src/f16-vtanh/gen/f16-vtanh-avx2-expm1minus-rr1-p3h2ts-rcp-u40.c", |
| "src/f16-vtanh/gen/f16-vtanh-avx2-expm1minus-rr1-p3h2ts-rcp-u48.c", |
| "src/f16-vtanh/gen/f16-vtanh-avx2-expm1minus-rr1-p3h2ts-rcp-u56.c", |
| "src/f16-vtanh/gen/f16-vtanh-avx2-expm1minus-rr1-p3h2ts-rcp-u64.c", |
| "src/f16-vtanh/gen/f16-vtanh-avx2-expm1minus-rr1-p3h2ts-rcp-u72.c", |
| "src/f16-vtanh/gen/f16-vtanh-avx2-expm1minus-rr1-p3h2ts-rcp-u80.c", |
| "src/f32-qc4w-gemm/gen/f32-qc4w-gemm-1x16-minmax-avx2-broadcast.c", |
| "src/f32-qc4w-gemm/gen/f32-qc4w-gemm-2x16-minmax-avx2-broadcast.c", |
| "src/f32-qc4w-gemm/gen/f32-qc4w-gemm-3x16-minmax-avx2-broadcast.c", |
| "src/f32-qc4w-gemm/gen/f32-qc4w-gemm-4x16-minmax-avx2-broadcast.c", |
| "src/f32-qc4w-gemm/gen/f32-qc4w-gemm-5x16-minmax-avx2-broadcast.c", |
| "src/f32-qc4w-gemm/gen/f32-qc4w-gemm-6x16-minmax-avx2-broadcast.c", |
| "src/f32-qc4w-gemm/gen/f32-qc4w-gemm-7x16-minmax-avx2-broadcast.c", |
| "src/f32-qc4w-gemm/gen/f32-qc4w-gemm-8x16-minmax-avx2-broadcast.c", |
| "src/f32-qc8w-gemm/gen/f32-qc8w-gemm-1x8-minmax-avx2-broadcast.c", |
| "src/f32-qc8w-gemm/gen/f32-qc8w-gemm-1x16-minmax-avx2-broadcast.c", |
| "src/f32-qc8w-gemm/gen/f32-qc8w-gemm-1x16s4-minmax-avx2-broadcast.c", |
| "src/f32-qc8w-gemm/gen/f32-qc8w-gemm-2x16-minmax-avx2-broadcast.c", |
| "src/f32-qc8w-gemm/gen/f32-qc8w-gemm-2x16s4-minmax-avx2-broadcast.c", |
| "src/f32-qc8w-gemm/gen/f32-qc8w-gemm-3x16-minmax-avx2-broadcast.c", |
| "src/f32-qc8w-gemm/gen/f32-qc8w-gemm-3x16s4-minmax-avx2-broadcast.c", |
| "src/f32-qc8w-gemm/gen/f32-qc8w-gemm-4x8-minmax-avx2-broadcast.c", |
| "src/f32-qc8w-gemm/gen/f32-qc8w-gemm-4x16-minmax-avx2-broadcast.c", |
| "src/f32-qc8w-gemm/gen/f32-qc8w-gemm-4x16s4-minmax-avx2-broadcast.c", |
| "src/f32-qc8w-gemm/gen/f32-qc8w-gemm-5x8-minmax-avx2-broadcast.c", |
| "src/f32-qc8w-gemm/gen/f32-qc8w-gemm-5x16-minmax-avx2-broadcast.c", |
| "src/f32-qc8w-gemm/gen/f32-qc8w-gemm-5x16s4-minmax-avx2-broadcast.c", |
| "src/f32-qc8w-gemm/gen/f32-qc8w-gemm-6x8-minmax-avx2-broadcast.c", |
| "src/f32-qc8w-gemm/gen/f32-qc8w-gemm-6x16-minmax-avx2-broadcast.c", |
| "src/f32-qc8w-gemm/gen/f32-qc8w-gemm-6x16s4-minmax-avx2-broadcast.c", |
| "src/f32-qc8w-gemm/gen/f32-qc8w-gemm-7x8-minmax-avx2-broadcast.c", |
| "src/f32-qc8w-gemm/gen/f32-qc8w-gemm-7x16-minmax-avx2-broadcast.c", |
| "src/f32-qc8w-gemm/gen/f32-qc8w-gemm-8x8-minmax-avx2-broadcast.c", |
| "src/f32-qc8w-gemm/gen/f32-qc8w-gemm-8x16-minmax-avx2-broadcast.c", |
| "src/f32-qs8-vcvt/gen/f32-qs8-vcvt-avx2-u16.c", |
| "src/f32-qs8-vcvt/gen/f32-qs8-vcvt-avx2-u32.c", |
| "src/f32-qs8-vcvt/gen/f32-qs8-vcvt-avx2-u48.c", |
| "src/f32-qs8-vcvt/gen/f32-qs8-vcvt-avx2-u64.c", |
| "src/f32-qu8-vcvt/gen/f32-qu8-vcvt-avx2-u16.c", |
| "src/f32-qu8-vcvt/gen/f32-qu8-vcvt-avx2-u32.c", |
| "src/f32-qu8-vcvt/gen/f32-qu8-vcvt-avx2-u48.c", |
| "src/f32-qu8-vcvt/gen/f32-qu8-vcvt-avx2-u64.c", |
| "src/f32-raddexpminusmax/gen/f32-raddexpminusmax-avx2-p5-u64-acc2.c", |
| "src/f32-raddexpminusmax/gen/f32-raddexpminusmax-avx2-p5-u64-acc4.c", |
| "src/f32-raddexpminusmax/gen/f32-raddexpminusmax-avx2-p5-u64.c", |
| "src/f32-raddexpminusmax/gen/f32-raddexpminusmax-avx2-p5-u72-acc3.c", |
| "src/f32-raddexpminusmax/gen/f32-raddexpminusmax-avx2-p5-u72.c", |
| "src/f32-raddexpminusmax/gen/f32-raddexpminusmax-avx2-p5-u80-acc2.c", |
| "src/f32-raddexpminusmax/gen/f32-raddexpminusmax-avx2-p5-u80-acc5.c", |
| "src/f32-raddexpminusmax/gen/f32-raddexpminusmax-avx2-p5-u80.c", |
| "src/f32-raddexpminusmax/gen/f32-raddexpminusmax-avx2-p5-u96-acc2.c", |
| "src/f32-raddexpminusmax/gen/f32-raddexpminusmax-avx2-p5-u96-acc3.c", |
| "src/f32-raddexpminusmax/gen/f32-raddexpminusmax-avx2-p5-u96-acc6.c", |
| "src/f32-raddexpminusmax/gen/f32-raddexpminusmax-avx2-p5-u96.c", |
| "src/f32-raddextexp/gen/f32-raddextexp-avx2-p5-u64-acc2.c", |
| "src/f32-raddextexp/gen/f32-raddextexp-avx2-p5-u64-acc4.c", |
| "src/f32-raddextexp/gen/f32-raddextexp-avx2-p5-u64.c", |
| "src/f32-raddextexp/gen/f32-raddextexp-avx2-p5-u72-acc3.c", |
| "src/f32-raddextexp/gen/f32-raddextexp-avx2-p5-u72.c", |
| "src/f32-raddextexp/gen/f32-raddextexp-avx2-p5-u80-acc2.c", |
| "src/f32-raddextexp/gen/f32-raddextexp-avx2-p5-u80-acc5.c", |
| "src/f32-raddextexp/gen/f32-raddextexp-avx2-p5-u80.c", |
| "src/f32-raddextexp/gen/f32-raddextexp-avx2-p5-u96-acc2.c", |
| "src/f32-raddextexp/gen/f32-raddextexp-avx2-p5-u96-acc3.c", |
| "src/f32-raddextexp/gen/f32-raddextexp-avx2-p5-u96-acc6.c", |
| "src/f32-raddextexp/gen/f32-raddextexp-avx2-p5-u96.c", |
| "src/f32-raddstoreexpminusmax/gen/f32-raddstoreexpminusmax-avx2-rr1-p5-u64-acc2.c", |
| "src/f32-raddstoreexpminusmax/gen/f32-raddstoreexpminusmax-avx2-rr1-p5-u64-acc4.c", |
| "src/f32-raddstoreexpminusmax/gen/f32-raddstoreexpminusmax-avx2-rr1-p5-u64.c", |
| "src/f32-raddstoreexpminusmax/gen/f32-raddstoreexpminusmax-avx2-rr1-p5-u72-acc3.c", |
| "src/f32-raddstoreexpminusmax/gen/f32-raddstoreexpminusmax-avx2-rr1-p5-u72.c", |
| "src/f32-raddstoreexpminusmax/gen/f32-raddstoreexpminusmax-avx2-rr1-p5-u80-acc2.c", |
| "src/f32-raddstoreexpminusmax/gen/f32-raddstoreexpminusmax-avx2-rr1-p5-u80-acc5.c", |
| "src/f32-raddstoreexpminusmax/gen/f32-raddstoreexpminusmax-avx2-rr1-p5-u80.c", |
| "src/f32-raddstoreexpminusmax/gen/f32-raddstoreexpminusmax-avx2-rr1-p5-u96-acc2.c", |
| "src/f32-raddstoreexpminusmax/gen/f32-raddstoreexpminusmax-avx2-rr1-p5-u96-acc3.c", |
| "src/f32-raddstoreexpminusmax/gen/f32-raddstoreexpminusmax-avx2-rr1-p5-u96-acc6.c", |
| "src/f32-raddstoreexpminusmax/gen/f32-raddstoreexpminusmax-avx2-rr1-p5-u96.c", |
| "src/f32-velu/gen/f32-velu-avx2-rr1-lut4-p4-perm-u8.c", |
| "src/f32-velu/gen/f32-velu-avx2-rr1-lut4-p4-perm-u16.c", |
| "src/f32-velu/gen/f32-velu-avx2-rr1-lut4-p4-perm-u24.c", |
| "src/f32-velu/gen/f32-velu-avx2-rr1-lut4-p4-perm-u32.c", |
| "src/f32-velu/gen/f32-velu-avx2-rr1-lut4-p4-perm-u40.c", |
| "src/f32-velu/gen/f32-velu-avx2-rr1-lut4-p4-perm-u48.c", |
| "src/f32-velu/gen/f32-velu-avx2-rr1-lut4-p4-perm-u56.c", |
| "src/f32-velu/gen/f32-velu-avx2-rr1-lut4-p4-perm-u64.c", |
| "src/f32-velu/gen/f32-velu-avx2-rr1-lut4-p4-perm-u72.c", |
| "src/f32-velu/gen/f32-velu-avx2-rr1-lut4-p4-perm-u80.c", |
| "src/f32-velu/gen/f32-velu-avx2-rr1-lut8-p4-perm-u8.c", |
| "src/f32-velu/gen/f32-velu-avx2-rr1-lut8-p4-perm-u16.c", |
| "src/f32-velu/gen/f32-velu-avx2-rr1-lut8-p4-perm-u24.c", |
| "src/f32-velu/gen/f32-velu-avx2-rr1-lut8-p4-perm-u32.c", |
| "src/f32-velu/gen/f32-velu-avx2-rr1-lut8-p4-perm-u40.c", |
| "src/f32-velu/gen/f32-velu-avx2-rr1-lut8-p4-perm-u48.c", |
| "src/f32-velu/gen/f32-velu-avx2-rr1-lut8-p4-perm-u56.c", |
| "src/f32-velu/gen/f32-velu-avx2-rr1-lut8-p4-perm-u64.c", |
| "src/f32-velu/gen/f32-velu-avx2-rr1-lut8-p4-perm-u72.c", |
| "src/f32-velu/gen/f32-velu-avx2-rr1-lut8-p4-perm-u80.c", |
| "src/f32-velu/gen/f32-velu-avx2-rr1-lut16-p3-gather-u8.c", |
| "src/f32-velu/gen/f32-velu-avx2-rr1-lut16-p3-gather-u16.c", |
| "src/f32-velu/gen/f32-velu-avx2-rr1-lut16-p3-gather-u24.c", |
| "src/f32-velu/gen/f32-velu-avx2-rr1-lut16-p3-gather-u32.c", |
| "src/f32-velu/gen/f32-velu-avx2-rr1-lut16-p3-gather-u40.c", |
| "src/f32-velu/gen/f32-velu-avx2-rr1-lut16-p3-gather-u48.c", |
| "src/f32-velu/gen/f32-velu-avx2-rr1-lut16-p3-gather-u56.c", |
| "src/f32-velu/gen/f32-velu-avx2-rr1-lut16-p3-gather-u64.c", |
| "src/f32-velu/gen/f32-velu-avx2-rr1-lut16-p3-gather-u72.c", |
| "src/f32-velu/gen/f32-velu-avx2-rr1-lut16-p3-gather-u80.c", |
| "src/f32-velu/gen/f32-velu-avx2-rr1-p6-u8.c", |
| "src/f32-velu/gen/f32-velu-avx2-rr1-p6-u16.c", |
| "src/f32-velu/gen/f32-velu-avx2-rr1-p6-u24.c", |
| "src/f32-velu/gen/f32-velu-avx2-rr1-p6-u32.c", |
| "src/f32-velu/gen/f32-velu-avx2-rr1-p6-u40.c", |
| "src/f32-velu/gen/f32-velu-avx2-rr1-p6-u48.c", |
| "src/f32-velu/gen/f32-velu-avx2-rr1-p6-u56.c", |
| "src/f32-velu/gen/f32-velu-avx2-rr1-p6-u64.c", |
| "src/f32-velu/gen/f32-velu-avx2-rr1-p6-u72.c", |
| "src/f32-velu/gen/f32-velu-avx2-rr1-p6-u80.c", |
| "src/f32-vscaleexpminusmax/gen/f32-vscaleexpminusmax-avx2-p5-u8.c", |
| "src/f32-vscaleexpminusmax/gen/f32-vscaleexpminusmax-avx2-p5-u16.c", |
| "src/f32-vscaleexpminusmax/gen/f32-vscaleexpminusmax-avx2-p5-u24.c", |
| "src/f32-vscaleexpminusmax/gen/f32-vscaleexpminusmax-avx2-p5-u32.c", |
| "src/f32-vscaleexpminusmax/gen/f32-vscaleexpminusmax-avx2-p5-u40.c", |
| "src/f32-vscaleexpminusmax/gen/f32-vscaleexpminusmax-avx2-p5-u48.c", |
| "src/f32-vscaleexpminusmax/gen/f32-vscaleexpminusmax-avx2-p5-u56.c", |
| "src/f32-vscaleexpminusmax/gen/f32-vscaleexpminusmax-avx2-p5-u64.c", |
| "src/f32-vscaleexpminusmax/gen/f32-vscaleexpminusmax-avx2-p5-u72.c", |
| "src/f32-vscaleexpminusmax/gen/f32-vscaleexpminusmax-avx2-p5-u80.c", |
| "src/f32-vscaleexpminusmax/gen/f32-vscaleexpminusmax-avx2-p5-u88.c", |
| "src/f32-vscaleexpminusmax/gen/f32-vscaleexpminusmax-avx2-p5-u96.c", |
| "src/f32-vscaleextexp/gen/f32-vscaleextexp-avx2-p5-u8.c", |
| "src/f32-vscaleextexp/gen/f32-vscaleextexp-avx2-p5-u16.c", |
| "src/f32-vscaleextexp/gen/f32-vscaleextexp-avx2-p5-u24.c", |
| "src/f32-vscaleextexp/gen/f32-vscaleextexp-avx2-p5-u32.c", |
| "src/f32-vscaleextexp/gen/f32-vscaleextexp-avx2-p5-u40.c", |
| "src/f32-vscaleextexp/gen/f32-vscaleextexp-avx2-p5-u48.c", |
| "src/f32-vscaleextexp/gen/f32-vscaleextexp-avx2-p5-u56.c", |
| "src/f32-vscaleextexp/gen/f32-vscaleextexp-avx2-p5-u64.c", |
| "src/f32-vscaleextexp/gen/f32-vscaleextexp-avx2-p5-u72.c", |
| "src/f32-vscaleextexp/gen/f32-vscaleextexp-avx2-p5-u80.c", |
| "src/f32-vscaleextexp/gen/f32-vscaleextexp-avx2-p5-u88.c", |
| "src/f32-vscaleextexp/gen/f32-vscaleextexp-avx2-p5-u96.c", |
| "src/f32-vsigmoid/gen/f32-vsigmoid-avx2-rr1-p5-div-u8.c", |
| "src/f32-vsigmoid/gen/f32-vsigmoid-avx2-rr1-p5-div-u16.c", |
| "src/f32-vsigmoid/gen/f32-vsigmoid-avx2-rr1-p5-div-u24.c", |
| "src/f32-vsigmoid/gen/f32-vsigmoid-avx2-rr1-p5-div-u32.c", |
| "src/f32-vsigmoid/gen/f32-vsigmoid-avx2-rr1-p5-div-u40.c", |
| "src/f32-vsigmoid/gen/f32-vsigmoid-avx2-rr1-p5-div-u48.c", |
| "src/f32-vsigmoid/gen/f32-vsigmoid-avx2-rr1-p5-div-u56.c", |
| "src/f32-vsigmoid/gen/f32-vsigmoid-avx2-rr1-p5-div-u64.c", |
| "src/f32-vsigmoid/gen/f32-vsigmoid-avx2-rr1-p5-div-u72.c", |
| "src/f32-vsigmoid/gen/f32-vsigmoid-avx2-rr1-p5-div-u80.c", |
| "src/f32-vsigmoid/gen/f32-vsigmoid-avx2-rr1-p5-nr1fma-u8.c", |
| "src/f32-vsigmoid/gen/f32-vsigmoid-avx2-rr1-p5-nr1fma-u16.c", |
| "src/f32-vsigmoid/gen/f32-vsigmoid-avx2-rr1-p5-nr1fma-u24.c", |
| "src/f32-vsigmoid/gen/f32-vsigmoid-avx2-rr1-p5-nr1fma-u32.c", |
| "src/f32-vsigmoid/gen/f32-vsigmoid-avx2-rr1-p5-nr1fma-u40.c", |
| "src/f32-vsigmoid/gen/f32-vsigmoid-avx2-rr1-p5-nr1fma-u48.c", |
| "src/f32-vsigmoid/gen/f32-vsigmoid-avx2-rr1-p5-nr1fma-u56.c", |
| "src/f32-vsigmoid/gen/f32-vsigmoid-avx2-rr1-p5-nr1fma-u64.c", |
| "src/f32-vsigmoid/gen/f32-vsigmoid-avx2-rr1-p5-nr1fma-u72.c", |
| "src/f32-vsigmoid/gen/f32-vsigmoid-avx2-rr1-p5-nr1fma-u80.c", |
| "src/f32-vsigmoid/gen/f32-vsigmoid-avx2-rr1-p5-nr2fma-u8.c", |
| "src/f32-vsigmoid/gen/f32-vsigmoid-avx2-rr1-p5-nr2fma-u16.c", |
| "src/f32-vsigmoid/gen/f32-vsigmoid-avx2-rr1-p5-nr2fma-u24.c", |
| "src/f32-vsigmoid/gen/f32-vsigmoid-avx2-rr1-p5-nr2fma-u32.c", |
| "src/f32-vsigmoid/gen/f32-vsigmoid-avx2-rr1-p5-nr2fma-u40.c", |
| "src/f32-vsigmoid/gen/f32-vsigmoid-avx2-rr1-p5-nr2fma-u48.c", |
| "src/f32-vsigmoid/gen/f32-vsigmoid-avx2-rr1-p5-nr2fma-u56.c", |
| "src/f32-vsigmoid/gen/f32-vsigmoid-avx2-rr1-p5-nr2fma-u64.c", |
| "src/f32-vsigmoid/gen/f32-vsigmoid-avx2-rr1-p5-nr2fma-u72.c", |
| "src/f32-vsigmoid/gen/f32-vsigmoid-avx2-rr1-p5-nr2fma-u80.c", |
| "src/f32-vtanh/gen/f32-vtanh-avx2-expm1minus-rr1-lut4-p4h3ts-perm-div-u8.c", |
| "src/f32-vtanh/gen/f32-vtanh-avx2-expm1minus-rr1-lut4-p4h3ts-perm-div-u16.c", |
| "src/f32-vtanh/gen/f32-vtanh-avx2-expm1minus-rr1-lut4-p4h3ts-perm-div-u24.c", |
| "src/f32-vtanh/gen/f32-vtanh-avx2-expm1minus-rr1-lut4-p4h3ts-perm-div-u32.c", |
| "src/f32-vtanh/gen/f32-vtanh-avx2-expm1minus-rr1-lut4-p4h3ts-perm-div-u40.c", |
| "src/f32-vtanh/gen/f32-vtanh-avx2-expm1minus-rr1-lut4-p4h3ts-perm-div-u48.c", |
| "src/f32-vtanh/gen/f32-vtanh-avx2-expm1minus-rr1-lut4-p4h3ts-perm-div-u56.c", |
| "src/f32-vtanh/gen/f32-vtanh-avx2-expm1minus-rr1-lut4-p4h3ts-perm-div-u64.c", |
| "src/f32-vtanh/gen/f32-vtanh-avx2-expm1minus-rr1-lut4-p4h3ts-perm-div-u72.c", |
| "src/f32-vtanh/gen/f32-vtanh-avx2-expm1minus-rr1-lut4-p4h3ts-perm-div-u80.c", |
| "src/f32-vtanh/gen/f32-vtanh-avx2-expm1minus-rr1-lut4-p4h3ts-perm-nr1adj-u8.c", |
| "src/f32-vtanh/gen/f32-vtanh-avx2-expm1minus-rr1-lut4-p4h3ts-perm-nr1adj-u16.c", |
| "src/f32-vtanh/gen/f32-vtanh-avx2-expm1minus-rr1-lut4-p4h3ts-perm-nr1adj-u24.c", |
| "src/f32-vtanh/gen/f32-vtanh-avx2-expm1minus-rr1-lut4-p4h3ts-perm-nr1adj-u32.c", |
| "src/f32-vtanh/gen/f32-vtanh-avx2-expm1minus-rr1-lut4-p4h3ts-perm-nr1adj-u40.c", |
| "src/f32-vtanh/gen/f32-vtanh-avx2-expm1minus-rr1-lut4-p4h3ts-perm-nr1adj-u48.c", |
| "src/f32-vtanh/gen/f32-vtanh-avx2-expm1minus-rr1-lut4-p4h3ts-perm-nr1adj-u56.c", |
| "src/f32-vtanh/gen/f32-vtanh-avx2-expm1minus-rr1-lut4-p4h3ts-perm-nr1adj-u64.c", |
| "src/f32-vtanh/gen/f32-vtanh-avx2-expm1minus-rr1-lut4-p4h3ts-perm-nr1adj-u72.c", |
| "src/f32-vtanh/gen/f32-vtanh-avx2-expm1minus-rr1-lut4-p4h3ts-perm-nr1adj-u80.c", |
| "src/f32-vtanh/gen/f32-vtanh-avx2-expm1minus-rr1-lut8-p4h3ts-gather-div-u8.c", |
| "src/f32-vtanh/gen/f32-vtanh-avx2-expm1minus-rr1-lut8-p4h3ts-gather-div-u16.c", |
| "src/f32-vtanh/gen/f32-vtanh-avx2-expm1minus-rr1-lut8-p4h3ts-gather-div-u24.c", |
| "src/f32-vtanh/gen/f32-vtanh-avx2-expm1minus-rr1-lut8-p4h3ts-gather-div-u32.c", |
| "src/f32-vtanh/gen/f32-vtanh-avx2-expm1minus-rr1-lut8-p4h3ts-gather-div-u40.c", |
| "src/f32-vtanh/gen/f32-vtanh-avx2-expm1minus-rr1-lut8-p4h3ts-gather-div-u48.c", |
| "src/f32-vtanh/gen/f32-vtanh-avx2-expm1minus-rr1-lut8-p4h3ts-gather-div-u56.c", |
| "src/f32-vtanh/gen/f32-vtanh-avx2-expm1minus-rr1-lut8-p4h3ts-gather-div-u64.c", |
| "src/f32-vtanh/gen/f32-vtanh-avx2-expm1minus-rr1-lut8-p4h3ts-gather-div-u72.c", |
| "src/f32-vtanh/gen/f32-vtanh-avx2-expm1minus-rr1-lut8-p4h3ts-gather-div-u80.c", |
| "src/f32-vtanh/gen/f32-vtanh-avx2-expm1minus-rr1-lut8-p4h3ts-gather-nr1adj-u8.c", |
| "src/f32-vtanh/gen/f32-vtanh-avx2-expm1minus-rr1-lut8-p4h3ts-gather-nr1adj-u16.c", |
| "src/f32-vtanh/gen/f32-vtanh-avx2-expm1minus-rr1-lut8-p4h3ts-gather-nr1adj-u24.c", |
| "src/f32-vtanh/gen/f32-vtanh-avx2-expm1minus-rr1-lut8-p4h3ts-gather-nr1adj-u32.c", |
| "src/f32-vtanh/gen/f32-vtanh-avx2-expm1minus-rr1-lut8-p4h3ts-gather-nr1adj-u40.c", |
| "src/f32-vtanh/gen/f32-vtanh-avx2-expm1minus-rr1-lut8-p4h3ts-gather-nr1adj-u48.c", |
| "src/f32-vtanh/gen/f32-vtanh-avx2-expm1minus-rr1-lut8-p4h3ts-gather-nr1adj-u56.c", |
| "src/f32-vtanh/gen/f32-vtanh-avx2-expm1minus-rr1-lut8-p4h3ts-gather-nr1adj-u64.c", |
| "src/f32-vtanh/gen/f32-vtanh-avx2-expm1minus-rr1-lut8-p4h3ts-gather-nr1adj-u72.c", |
| "src/f32-vtanh/gen/f32-vtanh-avx2-expm1minus-rr1-lut8-p4h3ts-gather-nr1adj-u80.c", |
| "src/f32-vtanh/gen/f32-vtanh-avx2-expm1minus-rr1-lut8-p4h3ts-perm-div-u8.c", |
| "src/f32-vtanh/gen/f32-vtanh-avx2-expm1minus-rr1-lut8-p4h3ts-perm-div-u16.c", |
| "src/f32-vtanh/gen/f32-vtanh-avx2-expm1minus-rr1-lut8-p4h3ts-perm-div-u24.c", |
| "src/f32-vtanh/gen/f32-vtanh-avx2-expm1minus-rr1-lut8-p4h3ts-perm-div-u32.c", |
| "src/f32-vtanh/gen/f32-vtanh-avx2-expm1minus-rr1-lut8-p4h3ts-perm-div-u40.c", |
| "src/f32-vtanh/gen/f32-vtanh-avx2-expm1minus-rr1-lut8-p4h3ts-perm-div-u48.c", |
| "src/f32-vtanh/gen/f32-vtanh-avx2-expm1minus-rr1-lut8-p4h3ts-perm-div-u56.c", |
| "src/f32-vtanh/gen/f32-vtanh-avx2-expm1minus-rr1-lut8-p4h3ts-perm-div-u64.c", |
| "src/f32-vtanh/gen/f32-vtanh-avx2-expm1minus-rr1-lut8-p4h3ts-perm-div-u72.c", |
| "src/f32-vtanh/gen/f32-vtanh-avx2-expm1minus-rr1-lut8-p4h3ts-perm-div-u80.c", |
| "src/f32-vtanh/gen/f32-vtanh-avx2-expm1minus-rr1-lut8-p4h3ts-perm-nr1adj-u8.c", |
| "src/f32-vtanh/gen/f32-vtanh-avx2-expm1minus-rr1-lut8-p4h3ts-perm-nr1adj-u16.c", |
| "src/f32-vtanh/gen/f32-vtanh-avx2-expm1minus-rr1-lut8-p4h3ts-perm-nr1adj-u24.c", |
| "src/f32-vtanh/gen/f32-vtanh-avx2-expm1minus-rr1-lut8-p4h3ts-perm-nr1adj-u32.c", |
| "src/f32-vtanh/gen/f32-vtanh-avx2-expm1minus-rr1-lut8-p4h3ts-perm-nr1adj-u40.c", |
| "src/f32-vtanh/gen/f32-vtanh-avx2-expm1minus-rr1-lut8-p4h3ts-perm-nr1adj-u48.c", |
| "src/f32-vtanh/gen/f32-vtanh-avx2-expm1minus-rr1-lut8-p4h3ts-perm-nr1adj-u56.c", |
| "src/f32-vtanh/gen/f32-vtanh-avx2-expm1minus-rr1-lut8-p4h3ts-perm-nr1adj-u64.c", |
| "src/f32-vtanh/gen/f32-vtanh-avx2-expm1minus-rr1-lut8-p4h3ts-perm-nr1adj-u72.c", |
| "src/f32-vtanh/gen/f32-vtanh-avx2-expm1minus-rr1-lut8-p4h3ts-perm-nr1adj-u80.c", |
| "src/f32-vtanh/gen/f32-vtanh-avx2-expm1minus-rr1-p6h5ts-div-u8.c", |
| "src/f32-vtanh/gen/f32-vtanh-avx2-expm1minus-rr1-p6h5ts-div-u16.c", |
| "src/f32-vtanh/gen/f32-vtanh-avx2-expm1minus-rr1-p6h5ts-div-u24.c", |
| "src/f32-vtanh/gen/f32-vtanh-avx2-expm1minus-rr1-p6h5ts-div-u32.c", |
| "src/f32-vtanh/gen/f32-vtanh-avx2-expm1minus-rr1-p6h5ts-div-u40.c", |
| "src/f32-vtanh/gen/f32-vtanh-avx2-expm1minus-rr1-p6h5ts-div-u48.c", |
| "src/f32-vtanh/gen/f32-vtanh-avx2-expm1minus-rr1-p6h5ts-div-u56.c", |
| "src/f32-vtanh/gen/f32-vtanh-avx2-expm1minus-rr1-p6h5ts-div-u64.c", |
| "src/f32-vtanh/gen/f32-vtanh-avx2-expm1minus-rr1-p6h5ts-div-u72.c", |
| "src/f32-vtanh/gen/f32-vtanh-avx2-expm1minus-rr1-p6h5ts-div-u80.c", |
| "src/f32-vtanh/gen/f32-vtanh-avx2-expm1minus-rr1-p6h5ts-nr1-u8.c", |
| "src/f32-vtanh/gen/f32-vtanh-avx2-expm1minus-rr1-p6h5ts-nr1-u16.c", |
| "src/f32-vtanh/gen/f32-vtanh-avx2-expm1minus-rr1-p6h5ts-nr1-u24.c", |
| "src/f32-vtanh/gen/f32-vtanh-avx2-expm1minus-rr1-p6h5ts-nr1-u32.c", |
| "src/f32-vtanh/gen/f32-vtanh-avx2-expm1minus-rr1-p6h5ts-nr1-u40.c", |
| "src/f32-vtanh/gen/f32-vtanh-avx2-expm1minus-rr1-p6h5ts-nr1-u48.c", |
| "src/f32-vtanh/gen/f32-vtanh-avx2-expm1minus-rr1-p6h5ts-nr1-u56.c", |
| "src/f32-vtanh/gen/f32-vtanh-avx2-expm1minus-rr1-p6h5ts-nr1-u64.c", |
| "src/f32-vtanh/gen/f32-vtanh-avx2-expm1minus-rr1-p6h5ts-nr1-u72.c", |
| "src/f32-vtanh/gen/f32-vtanh-avx2-expm1minus-rr1-p6h5ts-nr1-u80.c", |
| "src/f32-vtanh/gen/f32-vtanh-avx2-expm1minus-rr1-p6h5ts-nr1adj-u8.c", |
| "src/f32-vtanh/gen/f32-vtanh-avx2-expm1minus-rr1-p6h5ts-nr1adj-u16.c", |
| "src/f32-vtanh/gen/f32-vtanh-avx2-expm1minus-rr1-p6h5ts-nr1adj-u24.c", |
| "src/f32-vtanh/gen/f32-vtanh-avx2-expm1minus-rr1-p6h5ts-nr1adj-u32.c", |
| "src/f32-vtanh/gen/f32-vtanh-avx2-expm1minus-rr1-p6h5ts-nr1adj-u40.c", |
| "src/f32-vtanh/gen/f32-vtanh-avx2-expm1minus-rr1-p6h5ts-nr1adj-u48.c", |
| "src/f32-vtanh/gen/f32-vtanh-avx2-expm1minus-rr1-p6h5ts-nr1adj-u56.c", |
| "src/f32-vtanh/gen/f32-vtanh-avx2-expm1minus-rr1-p6h5ts-nr1adj-u64.c", |
| "src/f32-vtanh/gen/f32-vtanh-avx2-expm1minus-rr1-p6h5ts-nr1adj-u72.c", |
| "src/f32-vtanh/gen/f32-vtanh-avx2-expm1minus-rr1-p6h5ts-nr1adj-u80.c", |
| "src/math/f16-expm1minus-avx2-rr1-p2.c", |
| "src/math/f16-expm1minus-avx2-rr1-p3.c", |
| "src/math/f16-expminus-avx2-rr1-p2.c", |
| "src/math/f16-expminus-avx2-rr1-p3.c", |
| "src/math/f16-sigmoid-avx2-rr1-p2-div.c", |
| "src/math/f16-sigmoid-avx2-rr1-p2-rcp.c", |
| "src/math/f16-sigmoid-avx2-rr1-p3-div.c", |
| "src/math/f16-sigmoid-avx2-rr1-p3-rcp.c", |
| "src/math/f32-exp-avx2-rr2-lut8-p3-perm.c", |
| "src/math/f32-exp-avx2-rr2-lut8-p4-perm.c", |
| "src/math/f32-exp-avx2-rr2-p5.c", |
| "src/math/f32-expm1minus-avx2-rr1-lut4-p4-perm.c", |
| "src/math/f32-expm1minus-avx2-rr1-lut8-p4-perm.c", |
| "src/math/f32-expm1minus-avx2-rr1-lut16-p3-gather.c", |
| "src/math/f32-expm1minus-avx2-rr1-p6.c", |
| "src/math/f32-expminus-avx2-rr1-p5.c", |
| "src/math/f32-expminus-avx2-rr2-p5.c", |
| "src/math/f32-extexp-avx2-p5.c", |
| "src/math/f32-sigmoid-avx2-rr1-lut64-p2-gather-div.c", |
| "src/math/f32-sigmoid-avx2-rr1-lut64-p2-gather-nr1fma.c", |
| "src/math/f32-sigmoid-avx2-rr1-lut64-p2-gather-nr2fma1adj.c", |
| "src/math/f32-sigmoid-avx2-rr1-lut64-p2-gather-nr2fma.c", |
| "src/math/f32-sigmoid-avx2-rr1-p5-div.c", |
| "src/math/f32-sigmoid-avx2-rr1-p5-nr1fma.c", |
| "src/math/f32-sigmoid-avx2-rr1-p5-nr2fma.c", |
| "src/math/f32-sigmoid-avx2-rr2-lut64-p2-gather-div.c", |
| "src/math/f32-sigmoid-avx2-rr2-lut64-p2-gather-nr1fma.c", |
| "src/math/f32-sigmoid-avx2-rr2-lut64-p2-gather-nr2fma1adj.c", |
| "src/math/f32-sigmoid-avx2-rr2-lut64-p2-gather-nr2fma.c", |
| "src/math/f32-sigmoid-avx2-rr2-p5-div.c", |
| "src/math/f32-sigmoid-avx2-rr2-p5-nr1fma.c", |
| "src/math/f32-sigmoid-avx2-rr2-p5-nr2fma.c", |
| "src/math/gen/f16-tanh-avx2-expm1minus-rr1-p3h2ts-div.c", |
| "src/math/gen/f16-tanh-avx2-expm1minus-rr1-p3h2ts-rcp.c", |
| "src/math/gen/f32-tanh-avx2-expm1minus-rr1-lut4-p4h3ts-perm-div.c", |
| "src/math/gen/f32-tanh-avx2-expm1minus-rr1-lut4-p4h3ts-perm-nr1adj.c", |
| "src/math/gen/f32-tanh-avx2-expm1minus-rr1-lut8-p4h3ps-gather-div.c", |
| "src/math/gen/f32-tanh-avx2-expm1minus-rr1-lut8-p4h3ps-gather-nr1.c", |
| "src/math/gen/f32-tanh-avx2-expm1minus-rr1-lut8-p4h3ps-gather-nr1adj.c", |
| "src/math/gen/f32-tanh-avx2-expm1minus-rr1-lut8-p4h3ps-perm-div.c", |
| "src/math/gen/f32-tanh-avx2-expm1minus-rr1-lut8-p4h3ps-perm-nr1.c", |
| "src/math/gen/f32-tanh-avx2-expm1minus-rr1-lut8-p4h3ps-perm-nr1adj.c", |
| "src/math/gen/f32-tanh-avx2-expm1minus-rr1-p6h5ts-div.c", |
| "src/math/gen/f32-tanh-avx2-expm1minus-rr1-p6h5ts-nr1.c", |
| "src/math/gen/f32-tanh-avx2-expm1minus-rr1-p6h5ts-nr1adj.c", |
| "src/qd8-f32-qc8w-gemm/gen/qd8-f32-qc8w-gemm-1x8c8-minmax-avx2.c", |
| "src/qd8-f32-qc8w-gemm/gen/qd8-f32-qc8w-gemm-2x8c8-minmax-avx2.c", |
| "src/qd8-f32-qc8w-gemm/gen/qd8-f32-qc8w-gemm-3x8c8-minmax-avx2.c", |
| "src/qs8-dwconv/gen/qs8-dwconv-5f5m5l8c8s8r-minmax-fp32-avx2-mul32.c", |
| "src/qs8-dwconv/gen/qs8-dwconv-5f5m5l16c8s8r-minmax-fp32-avx2-mul32.c", |
| "src/qs8-dwconv/gen/qs8-dwconv-5f5m5l16c16s16r-minmax-fp32-avx2-mul16-add16-vpunpck.c", |
| "src/qs8-dwconv/gen/qs8-dwconv-5f5m5l16c16s16r-minmax-fp32-avx2-mul16-vpmovsx.c", |
| "src/qs8-dwconv/gen/qs8-dwconv-5f5m5l16c16s16r-minmax-fp32-avx2-mul16-vpunpck.c", |
| "src/qs8-dwconv/gen/qs8-dwconv-5f5m5l32c8s8r-minmax-fp32-avx2-mul32.c", |
| "src/qs8-dwconv/gen/qs8-dwconv-5f5m5l32c16s16r-minmax-fp32-avx2-mul16-add16-vpunpck.c", |
| "src/qs8-dwconv/gen/qs8-dwconv-5f5m5l32c16s16r-minmax-fp32-avx2-mul16-vpmovsx.c", |
| "src/qs8-dwconv/gen/qs8-dwconv-5f5m5l32c16s16r-minmax-fp32-avx2-mul16-vpunpck.c", |
| "src/qs8-dwconv/gen/qs8-dwconv-6f6m7l8c8s8r-minmax-fp32-avx2-mul32.c", |
| "src/qs8-dwconv/gen/qs8-dwconv-6f6m7l16c8s8r-minmax-fp32-avx2-mul32.c", |
| "src/qs8-dwconv/gen/qs8-dwconv-6f6m7l16c16s16r-minmax-fp32-avx2-mul16-add16-vpunpck.c", |
| "src/qs8-dwconv/gen/qs8-dwconv-6f6m7l16c16s16r-minmax-fp32-avx2-mul16-vpmovsx.c", |
| "src/qs8-dwconv/gen/qs8-dwconv-6f6m7l16c16s16r-minmax-fp32-avx2-mul16-vpunpck.c", |
| "src/qs8-dwconv/gen/qs8-dwconv-6f6m7l32c8s8r-minmax-fp32-avx2-mul32.c", |
| "src/qs8-dwconv/gen/qs8-dwconv-6f6m7l32c16s16r-minmax-fp32-avx2-mul16-add16-vpunpck.c", |
| "src/qs8-dwconv/gen/qs8-dwconv-6f6m7l32c16s16r-minmax-fp32-avx2-mul16-vpmovsx.c", |
| "src/qs8-dwconv/gen/qs8-dwconv-6f6m7l32c16s16r-minmax-fp32-avx2-mul16-vpunpck.c", |
| "src/qs8-dwconv/gen/qs8-dwconv-8f8m9l8c8s8r-minmax-fp32-avx2-mul32.c", |
| "src/qs8-dwconv/gen/qs8-dwconv-8f8m9l16c8s8r-minmax-fp32-avx2-mul32.c", |
| "src/qs8-dwconv/gen/qs8-dwconv-8f8m9l16c16s16r-minmax-fp32-avx2-mul16-add16-vpunpck.c", |
| "src/qs8-dwconv/gen/qs8-dwconv-8f8m9l16c16s16r-minmax-fp32-avx2-mul16-vpmovsx.c", |
| "src/qs8-dwconv/gen/qs8-dwconv-8f8m9l16c16s16r-minmax-fp32-avx2-mul16-vpunpck.c", |
| "src/qs8-dwconv/gen/qs8-dwconv-8f8m9l32c8s8r-minmax-fp32-avx2-mul32.c", |
| "src/qs8-dwconv/gen/qs8-dwconv-8f8m9l32c16s16r-minmax-fp32-avx2-mul16-add16-vpunpck.c", |
| "src/qs8-dwconv/gen/qs8-dwconv-8f8m9l32c16s16r-minmax-fp32-avx2-mul16-vpmovsx.c", |
| "src/qs8-dwconv/gen/qs8-dwconv-8f8m9l32c16s16r-minmax-fp32-avx2-mul16-vpunpck.c", |
| "src/qs8-dwconv/gen/qs8-dwconv-9p8c-minmax-fp32-avx2-mul32.c", |
| "src/qs8-dwconv/gen/qs8-dwconv-9p16c-minmax-fp32-avx2-mul16-add16-vpunpck.c", |
| "src/qs8-dwconv/gen/qs8-dwconv-9p16c-minmax-fp32-avx2-mul16-vpmovsx.c", |
| "src/qs8-dwconv/gen/qs8-dwconv-9p16c-minmax-fp32-avx2-mul16-vpunpck.c", |
| "src/qs8-dwconv/gen/qs8-dwconv-9p16c-minmax-fp32-avx2-mul32.c", |
| "src/qs8-dwconv/gen/qs8-dwconv-9p32c-minmax-fp32-avx2-mul16-add16-vpunpck.c", |
| "src/qs8-dwconv/gen/qs8-dwconv-9p32c-minmax-fp32-avx2-mul16-vpmovsx.c", |
| "src/qs8-dwconv/gen/qs8-dwconv-9p32c-minmax-fp32-avx2-mul16-vpunpck.c", |
| "src/qs8-dwconv/gen/qs8-dwconv-9p32c-minmax-fp32-avx2-mul32.c", |
| "src/qs8-dwconv/gen/qs8-dwconv-25p8c-minmax-fp32-avx2-mul32.c", |
| "src/qs8-dwconv/gen/qs8-dwconv-25p16c-minmax-fp32-avx2-mul16-add16-vpunpck.c", |
| "src/qs8-dwconv/gen/qs8-dwconv-25p16c-minmax-fp32-avx2-mul16-vpmovsx.c", |
| "src/qs8-dwconv/gen/qs8-dwconv-25p16c-minmax-fp32-avx2-mul16-vpunpck.c", |
| "src/qs8-dwconv/gen/qs8-dwconv-25p16c-minmax-fp32-avx2-mul32.c", |
| "src/qs8-dwconv/gen/qs8-dwconv-25p32c-minmax-fp32-avx2-mul16-add16-vpunpck.c", |
| "src/qs8-dwconv/gen/qs8-dwconv-25p32c-minmax-fp32-avx2-mul16-vpmovsx.c", |
| "src/qs8-dwconv/gen/qs8-dwconv-25p32c-minmax-fp32-avx2-mul16-vpunpck.c", |
| "src/qs8-dwconv/gen/qs8-dwconv-25p32c-minmax-fp32-avx2-mul32.c", |
| "src/qs8-f32-vcvt/gen/qs8-f32-vcvt-avx2-u8.c", |
| "src/qs8-f32-vcvt/gen/qs8-f32-vcvt-avx2-u16.c", |
| "src/qs8-f32-vcvt/gen/qs8-f32-vcvt-avx2-u24.c", |
| "src/qs8-f32-vcvt/gen/qs8-f32-vcvt-avx2-u32.c", |
| "src/qs8-gemm/gen/qs8-gemm-1x8c8-minmax-fp32-avx2.c", |
| "src/qs8-gemm/gen/qs8-gemm-1x8c8-xw-minmax-fp32-avx2.c", |
| "src/qs8-gemm/gen/qs8-gemm-2x8c8-minmax-fp32-avx2.c", |
| "src/qs8-gemm/gen/qs8-gemm-2x8c8-xw-minmax-fp32-avx2.c", |
| "src/qs8-gemm/gen/qs8-gemm-3x8c8-minmax-fp32-avx2.c", |
| "src/qs8-gemm/gen/qs8-gemm-3x8c8-xw-minmax-fp32-avx2.c", |
| "src/qs8-igemm/gen/qs8-igemm-1x8c8-minmax-fp32-avx2.c", |
| "src/qs8-igemm/gen/qs8-igemm-2x8c8-minmax-fp32-avx2.c", |
| "src/qs8-igemm/gen/qs8-igemm-3x8c8-minmax-fp32-avx2.c", |
| "src/qs8-qc8w-dwconv/gen/qs8-qc8w-dwconv-3p16c-minmax-fp32-avx2-mul32.c", |
| "src/qs8-qc8w-dwconv/gen/qs8-qc8w-dwconv-5f5m5l8c8s8r-minmax-fp32-avx2-mul32.c", |
| "src/qs8-qc8w-dwconv/gen/qs8-qc8w-dwconv-5f5m5l16c8s8r-minmax-fp32-avx2-mul32.c", |
| "src/qs8-qc8w-dwconv/gen/qs8-qc8w-dwconv-5f5m5l16c16s16r-minmax-fp32-avx2-mul16-add16-vpunpck.c", |
| "src/qs8-qc8w-dwconv/gen/qs8-qc8w-dwconv-5f5m5l16c16s16r-minmax-fp32-avx2-mul16-vpmovsx.c", |
| "src/qs8-qc8w-dwconv/gen/qs8-qc8w-dwconv-5f5m5l16c16s16r-minmax-fp32-avx2-mul16-vpunpck.c", |
| "src/qs8-qc8w-dwconv/gen/qs8-qc8w-dwconv-5f5m5l32c8s8r-minmax-fp32-avx2-mul32.c", |
| "src/qs8-qc8w-dwconv/gen/qs8-qc8w-dwconv-5f5m5l32c16s16r-minmax-fp32-avx2-mul16-add16-vpunpck.c", |
| "src/qs8-qc8w-dwconv/gen/qs8-qc8w-dwconv-5f5m5l32c16s16r-minmax-fp32-avx2-mul16-vpmovsx.c", |
| "src/qs8-qc8w-dwconv/gen/qs8-qc8w-dwconv-5f5m5l32c16s16r-minmax-fp32-avx2-mul16-vpunpck.c", |
| "src/qs8-qc8w-dwconv/gen/qs8-qc8w-dwconv-6f6m7l8c8s8r-minmax-fp32-avx2-mul32.c", |
| "src/qs8-qc8w-dwconv/gen/qs8-qc8w-dwconv-6f6m7l16c8s8r-minmax-fp32-avx2-mul32.c", |
| "src/qs8-qc8w-dwconv/gen/qs8-qc8w-dwconv-6f6m7l16c16s16r-minmax-fp32-avx2-mul16-add16-vpunpck.c", |
| "src/qs8-qc8w-dwconv/gen/qs8-qc8w-dwconv-6f6m7l16c16s16r-minmax-fp32-avx2-mul16-vpmovsx.c", |
| "src/qs8-qc8w-dwconv/gen/qs8-qc8w-dwconv-6f6m7l16c16s16r-minmax-fp32-avx2-mul16-vpunpck.c", |
| "src/qs8-qc8w-dwconv/gen/qs8-qc8w-dwconv-6f6m7l32c8s8r-minmax-fp32-avx2-mul32.c", |
| "src/qs8-qc8w-dwconv/gen/qs8-qc8w-dwconv-6f6m7l32c16s16r-minmax-fp32-avx2-mul16-add16-vpunpck.c", |
| "src/qs8-qc8w-dwconv/gen/qs8-qc8w-dwconv-6f6m7l32c16s16r-minmax-fp32-avx2-mul16-vpmovsx.c", |
| "src/qs8-qc8w-dwconv/gen/qs8-qc8w-dwconv-6f6m7l32c16s16r-minmax-fp32-avx2-mul16-vpunpck.c", |
| "src/qs8-qc8w-dwconv/gen/qs8-qc8w-dwconv-8f8m9l8c8s8r-minmax-fp32-avx2-mul32.c", |
| "src/qs8-qc8w-dwconv/gen/qs8-qc8w-dwconv-8f8m9l16c8s8r-minmax-fp32-avx2-mul32.c", |
| "src/qs8-qc8w-dwconv/gen/qs8-qc8w-dwconv-8f8m9l16c16s16r-minmax-fp32-avx2-mul16-add16-vpunpck.c", |
| "src/qs8-qc8w-dwconv/gen/qs8-qc8w-dwconv-8f8m9l16c16s16r-minmax-fp32-avx2-mul16-vpmovsx.c", |
| "src/qs8-qc8w-dwconv/gen/qs8-qc8w-dwconv-8f8m9l16c16s16r-minmax-fp32-avx2-mul16-vpunpck.c", |
| "src/qs8-qc8w-dwconv/gen/qs8-qc8w-dwconv-8f8m9l32c8s8r-minmax-fp32-avx2-mul32.c", |
| "src/qs8-qc8w-dwconv/gen/qs8-qc8w-dwconv-8f8m9l32c16s16r-minmax-fp32-avx2-mul16-add16-vpunpck.c", |
| "src/qs8-qc8w-dwconv/gen/qs8-qc8w-dwconv-8f8m9l32c16s16r-minmax-fp32-avx2-mul16-vpmovsx.c", |
| "src/qs8-qc8w-dwconv/gen/qs8-qc8w-dwconv-8f8m9l32c16s16r-minmax-fp32-avx2-mul16-vpunpck.c", |
| "src/qs8-qc8w-dwconv/gen/qs8-qc8w-dwconv-9p8c-minmax-fp32-avx2-mul32.c", |
| "src/qs8-qc8w-dwconv/gen/qs8-qc8w-dwconv-9p16c-minmax-fp32-avx2-mul16-add16-vpunpck.c", |
| "src/qs8-qc8w-dwconv/gen/qs8-qc8w-dwconv-9p16c-minmax-fp32-avx2-mul16-vpmovsx.c", |
| "src/qs8-qc8w-dwconv/gen/qs8-qc8w-dwconv-9p16c-minmax-fp32-avx2-mul16-vpunpck.c", |
| "src/qs8-qc8w-dwconv/gen/qs8-qc8w-dwconv-9p16c-minmax-fp32-avx2-mul32.c", |
| "src/qs8-qc8w-dwconv/gen/qs8-qc8w-dwconv-9p32c-minmax-fp32-avx2-mul16-add16-vpunpck.c", |
| "src/qs8-qc8w-dwconv/gen/qs8-qc8w-dwconv-9p32c-minmax-fp32-avx2-mul16-vpmovsx.c", |
| "src/qs8-qc8w-dwconv/gen/qs8-qc8w-dwconv-9p32c-minmax-fp32-avx2-mul16-vpunpck.c", |
| "src/qs8-qc8w-dwconv/gen/qs8-qc8w-dwconv-9p32c-minmax-fp32-avx2-mul32.c", |
| "src/qs8-qc8w-dwconv/gen/qs8-qc8w-dwconv-25p8c-minmax-fp32-avx2-mul32.c", |
| "src/qs8-qc8w-dwconv/gen/qs8-qc8w-dwconv-25p16c-minmax-fp32-avx2-mul16-add16-vpunpck.c", |
| "src/qs8-qc8w-dwconv/gen/qs8-qc8w-dwconv-25p16c-minmax-fp32-avx2-mul16-vpmovsx.c", |
| "src/qs8-qc8w-dwconv/gen/qs8-qc8w-dwconv-25p16c-minmax-fp32-avx2-mul16-vpunpck.c", |
| "src/qs8-qc8w-dwconv/gen/qs8-qc8w-dwconv-25p16c-minmax-fp32-avx2-mul32.c", |
| "src/qs8-qc8w-dwconv/gen/qs8-qc8w-dwconv-25p32c-minmax-fp32-avx2-mul16-add16-vpunpck.c", |
| "src/qs8-qc8w-dwconv/gen/qs8-qc8w-dwconv-25p32c-minmax-fp32-avx2-mul16-vpmovsx.c", |
| "src/qs8-qc8w-dwconv/gen/qs8-qc8w-dwconv-25p32c-minmax-fp32-avx2-mul16-vpunpck.c", |
| "src/qs8-qc8w-dwconv/gen/qs8-qc8w-dwconv-25p32c-minmax-fp32-avx2-mul32.c", |
| "src/qs8-qc8w-gemm/gen/qs8-qc8w-gemm-1x8c8-minmax-fp32-avx2.c", |
| "src/qs8-qc8w-gemm/gen/qs8-qc8w-gemm-1x8c8-xw-minmax-fp32-avx2.c", |
| "src/qs8-qc8w-gemm/gen/qs8-qc8w-gemm-2x8c8-minmax-fp32-avx2.c", |
| "src/qs8-qc8w-gemm/gen/qs8-qc8w-gemm-2x8c8-xw-minmax-fp32-avx2.c", |
| "src/qs8-qc8w-gemm/gen/qs8-qc8w-gemm-3x8c8-minmax-fp32-avx2.c", |
| "src/qs8-qc8w-gemm/gen/qs8-qc8w-gemm-3x8c8-xw-minmax-fp32-avx2.c", |
| "src/qs8-qc8w-igemm/gen/qs8-qc8w-igemm-1x8c8-minmax-fp32-avx2.c", |
| "src/qs8-qc8w-igemm/gen/qs8-qc8w-igemm-2x8c8-minmax-fp32-avx2.c", |
| "src/qs8-qc8w-igemm/gen/qs8-qc8w-igemm-3x8c8-minmax-fp32-avx2.c", |
| "src/qs8-vadd/gen/qs8-vadd-minmax-avx2-mul32-ld64-u8.c", |
| "src/qs8-vadd/gen/qs8-vadd-minmax-avx2-mul32-ld64-u16.c", |
| "src/qs8-vadd/gen/qs8-vadd-minmax-avx2-mul32-ld64-u24.c", |
| "src/qs8-vadd/gen/qs8-vadd-minmax-avx2-mul32-ld64-u32.c", |
| "src/qs8-vaddc/gen/qs8-vaddc-minmax-avx2-mul32-ld64-u8.c", |
| "src/qs8-vaddc/gen/qs8-vaddc-minmax-avx2-mul32-ld64-u16.c", |
| "src/qs8-vaddc/gen/qs8-vaddc-minmax-avx2-mul32-ld64-u24.c", |
| "src/qs8-vaddc/gen/qs8-vaddc-minmax-avx2-mul32-ld64-u32.c", |
| "src/qs8-vcvt/gen/qs8-vcvt-avx2-u16.c", |
| "src/qs8-vcvt/gen/qs8-vcvt-avx2-u32.c", |
| "src/qs8-vcvt/gen/qs8-vcvt-avx2-u64.c", |
| "src/qs8-vlrelu/gen/qs8-vlrelu-avx2-u16.c", |
| "src/qs8-vlrelu/gen/qs8-vlrelu-avx2-u32.c", |
| "src/qs8-vlrelu/gen/qs8-vlrelu-avx2-u64.c", |
| "src/qu8-dwconv/gen/qu8-dwconv-5f5m5l8c8s8r-minmax-fp32-avx2-mul32.c", |
| "src/qu8-dwconv/gen/qu8-dwconv-5f5m5l16c8s8r-minmax-fp32-avx2-mul32.c", |
| "src/qu8-dwconv/gen/qu8-dwconv-5f5m5l32c8s8r-minmax-fp32-avx2-mul32.c", |
| "src/qu8-dwconv/gen/qu8-dwconv-6f6m7l8c8s8r-minmax-fp32-avx2-mul32.c", |
| "src/qu8-dwconv/gen/qu8-dwconv-6f6m7l16c8s8r-minmax-fp32-avx2-mul32.c", |
| "src/qu8-dwconv/gen/qu8-dwconv-6f6m7l32c8s8r-minmax-fp32-avx2-mul32.c", |
| "src/qu8-dwconv/gen/qu8-dwconv-8f8m9l8c8s8r-minmax-fp32-avx2-mul32.c", |
| "src/qu8-dwconv/gen/qu8-dwconv-8f8m9l16c8s8r-minmax-fp32-avx2-mul32.c", |
| "src/qu8-dwconv/gen/qu8-dwconv-8f8m9l32c8s8r-minmax-fp32-avx2-mul32.c", |
| "src/qu8-dwconv/gen/qu8-dwconv-9p8c-minmax-fp32-avx2-mul32.c", |
| "src/qu8-dwconv/gen/qu8-dwconv-9p16c-minmax-fp32-avx2-mul32.c", |
| "src/qu8-dwconv/gen/qu8-dwconv-9p32c-minmax-fp32-avx2-mul32.c", |
| "src/qu8-dwconv/gen/qu8-dwconv-25p8c-minmax-fp32-avx2-mul32.c", |
| "src/qu8-dwconv/gen/qu8-dwconv-25p16c-minmax-fp32-avx2-mul32.c", |
| "src/qu8-dwconv/gen/qu8-dwconv-25p32c-minmax-fp32-avx2-mul32.c", |
| "src/qu8-f32-vcvt/gen/qu8-f32-vcvt-avx2-u8.c", |
| "src/qu8-f32-vcvt/gen/qu8-f32-vcvt-avx2-u16.c", |
| "src/qu8-f32-vcvt/gen/qu8-f32-vcvt-avx2-u24.c", |
| "src/qu8-f32-vcvt/gen/qu8-f32-vcvt-avx2-u32.c", |
| "src/qu8-gemm/gen/qu8-gemm-1x8c8-minmax-fp32-avx2.c", |
| "src/qu8-gemm/gen/qu8-gemm-2x8c8-minmax-fp32-avx2.c", |
| "src/qu8-gemm/gen/qu8-gemm-3x8c8-minmax-fp32-avx2.c", |
| "src/qu8-igemm/gen/qu8-igemm-1x8c8-minmax-fp32-avx2.c", |
| "src/qu8-igemm/gen/qu8-igemm-2x8c8-minmax-fp32-avx2.c", |
| "src/qu8-igemm/gen/qu8-igemm-3x8c8-minmax-fp32-avx2.c", |
| "src/qu8-vadd/gen/qu8-vadd-minmax-avx2-mul32-ld64-u8.c", |
| "src/qu8-vadd/gen/qu8-vadd-minmax-avx2-mul32-ld64-u16.c", |
| "src/qu8-vaddc/gen/qu8-vaddc-minmax-avx2-mul32-ld64-u8.c", |
| "src/qu8-vaddc/gen/qu8-vaddc-minmax-avx2-mul32-ld64-u16.c", |
| "src/qu8-vcvt/gen/qu8-vcvt-avx2-u16.c", |
| "src/qu8-vcvt/gen/qu8-vcvt-avx2-u32.c", |
| "src/qu8-vcvt/gen/qu8-vcvt-avx2-u64.c", |
| "src/qu8-vlrelu/gen/qu8-vlrelu-avx2-u16.c", |
| "src/qu8-vlrelu/gen/qu8-vlrelu-avx2-u32.c", |
| "src/qu8-vlrelu/gen/qu8-vlrelu-avx2-u64.c", |
| "src/x8-lut/gen/x8-lut-avx2-u32.c", |
| "src/x8-lut/gen/x8-lut-avx2-u64.c", |
| "src/x8-lut/gen/x8-lut-avx2-u96.c", |
| "src/x8-lut/gen/x8-lut-avx2-u128.c", |
| "src/x8-transposec/gen/x8-transposec-32x32-reuse-mov-avx2.c", |
| "src/x8-transposec/gen/x8-transposec-32x32-reuse-switch-avx2.c", |
| "src/x16-packw/gen/x16-packw-x8-gemm-goi-avx2-u16-prfm.c", |
| "src/x16-packw/gen/x16-packw-x8-gemm-goi-avx2-u16.c", |
| "src/x16-packw/gen/x16-packw-x16-gemm-goi-avx2-u16-prfm.c", |
| "src/x16-packw/gen/x16-packw-x16-gemm-goi-avx2-u16.c", |
| "src/x16-transposec/gen/x16-transposec-16x16-reuse-mov-avx2.c", |
| "src/x16-transposec/gen/x16-transposec-16x16-reuse-switch-avx2.c", |
| ] |
| |
| ALL_AVX512F_MICROKERNEL_SRCS = [ |
| "src/f32-dwconv/gen/f32-dwconv-3p16c-minmax-avx512f-acc2.c", |
| "src/f32-dwconv/gen/f32-dwconv-3p16c-minmax-avx512f.c", |
| "src/f32-dwconv/gen/f32-dwconv-3p32c-minmax-avx512f-acc2.c", |
| "src/f32-dwconv/gen/f32-dwconv-3p32c-minmax-avx512f.c", |
| "src/f32-dwconv/gen/f32-dwconv-4p16c-minmax-avx512f-acc2.c", |
| "src/f32-dwconv/gen/f32-dwconv-4p16c-minmax-avx512f.c", |
| "src/f32-dwconv/gen/f32-dwconv-4p32c-minmax-avx512f-acc2.c", |
| "src/f32-dwconv/gen/f32-dwconv-4p32c-minmax-avx512f.c", |
| "src/f32-dwconv/gen/f32-dwconv-5f5m5l16c16s1r-minmax-avx512f-acc2.c", |
| "src/f32-dwconv/gen/f32-dwconv-5f5m5l16c16s1r-minmax-avx512f.c", |
| "src/f32-dwconv/gen/f32-dwconv-5f5m5l32c16s1r-minmax-avx512f-acc2.c", |
| "src/f32-dwconv/gen/f32-dwconv-5f5m5l32c16s1r-minmax-avx512f.c", |
| "src/f32-dwconv/gen/f32-dwconv-9p16c-minmax-avx512f-acc2.c", |
| "src/f32-dwconv/gen/f32-dwconv-9p16c-minmax-avx512f.c", |
| "src/f32-dwconv/gen/f32-dwconv-9p32c-minmax-avx512f-acc2.c", |
| "src/f32-dwconv/gen/f32-dwconv-9p32c-minmax-avx512f.c", |
| "src/f32-dwconv/gen/f32-dwconv-25p16c-minmax-avx512f-acc2.c", |
| "src/f32-dwconv/gen/f32-dwconv-25p16c-minmax-avx512f.c", |
| "src/f32-dwconv/gen/f32-dwconv-25p32c-minmax-avx512f-acc2.c", |
| "src/f32-dwconv/gen/f32-dwconv-25p32c-minmax-avx512f.c", |
| "src/f32-gemm/gen/f32-gemm-1x16-minmax-avx512f-broadcast.c", |
| "src/f32-gemm/gen/f32-gemm-4x16-minmax-avx512f-broadcast.c", |
| "src/f32-gemm/gen/f32-gemm-5x16-minmax-avx512f-broadcast.c", |
| "src/f32-gemm/gen/f32-gemm-6x16-minmax-avx512f-broadcast.c", |
| "src/f32-gemm/gen/f32-gemm-7x16-minmax-avx512f-broadcast.c", |
| "src/f32-gemm/gen/f32-gemm-8x16-minmax-avx512f-broadcast.c", |
| "src/f32-gemminc/gen/f32-gemminc-1x16-minmax-avx512f-broadcast.c", |
| "src/f32-gemminc/gen/f32-gemminc-4x16-minmax-avx512f-broadcast.c", |
| "src/f32-gemminc/gen/f32-gemminc-5x16-minmax-avx512f-broadcast.c", |
| "src/f32-gemminc/gen/f32-gemminc-6x16-minmax-avx512f-broadcast.c", |
| "src/f32-gemminc/gen/f32-gemminc-7x16-minmax-avx512f-broadcast.c", |
| "src/f32-gemminc/gen/f32-gemminc-8x16-minmax-avx512f-broadcast.c", |
| "src/f32-igemm/gen/f32-igemm-1x16-minmax-avx512f-broadcast.c", |
| "src/f32-igemm/gen/f32-igemm-4x16-minmax-avx512f-broadcast.c", |
| "src/f32-igemm/gen/f32-igemm-5x16-minmax-avx512f-broadcast.c", |
| "src/f32-igemm/gen/f32-igemm-6x16-minmax-avx512f-broadcast.c", |
| "src/f32-igemm/gen/f32-igemm-7x16-minmax-avx512f-broadcast.c", |
| "src/f32-igemm/gen/f32-igemm-8x16-minmax-avx512f-broadcast.c", |
| "src/f32-prelu/gen/f32-prelu-avx512f-2x16.c", |
| "src/f32-prelu/gen/f32-prelu-avx512f-2x32.c", |
| "src/f32-raddexpminusmax/gen/f32-raddexpminusmax-avx512f-p5-scalef-u128-acc2.c", |
| "src/f32-raddexpminusmax/gen/f32-raddexpminusmax-avx512f-p5-scalef-u128-acc4.c", |
| "src/f32-raddexpminusmax/gen/f32-raddexpminusmax-avx512f-p5-scalef-u128.c", |
| "src/f32-raddexpminusmax/gen/f32-raddexpminusmax-avx512f-p5-scalef-u144-acc3.c", |
| "src/f32-raddexpminusmax/gen/f32-raddexpminusmax-avx512f-p5-scalef-u144.c", |
| "src/f32-raddexpminusmax/gen/f32-raddexpminusmax-avx512f-p5-scalef-u160-acc2.c", |
| "src/f32-raddexpminusmax/gen/f32-raddexpminusmax-avx512f-p5-scalef-u160-acc5.c", |
| "src/f32-raddexpminusmax/gen/f32-raddexpminusmax-avx512f-p5-scalef-u160.c", |
| "src/f32-raddexpminusmax/gen/f32-raddexpminusmax-avx512f-p5-scalef-u192-acc2.c", |
| "src/f32-raddexpminusmax/gen/f32-raddexpminusmax-avx512f-p5-scalef-u192-acc3.c", |
| "src/f32-raddexpminusmax/gen/f32-raddexpminusmax-avx512f-p5-scalef-u192-acc6.c", |
| "src/f32-raddexpminusmax/gen/f32-raddexpminusmax-avx512f-p5-scalef-u192.c", |
| "src/f32-raddextexp/gen/f32-raddextexp-avx512f-p5-scalef-u128-acc2.c", |
| "src/f32-raddextexp/gen/f32-raddextexp-avx512f-p5-scalef-u128-acc4.c", |
| "src/f32-raddextexp/gen/f32-raddextexp-avx512f-p5-scalef-u128.c", |
| "src/f32-raddextexp/gen/f32-raddextexp-avx512f-p5-scalef-u144-acc3.c", |
| "src/f32-raddextexp/gen/f32-raddextexp-avx512f-p5-scalef-u144.c", |
| "src/f32-raddextexp/gen/f32-raddextexp-avx512f-p5-scalef-u160-acc2.c", |
| "src/f32-raddextexp/gen/f32-raddextexp-avx512f-p5-scalef-u160-acc5.c", |
| "src/f32-raddextexp/gen/f32-raddextexp-avx512f-p5-scalef-u160.c", |
| "src/f32-raddextexp/gen/f32-raddextexp-avx512f-p5-scalef-u192-acc2.c", |
| "src/f32-raddextexp/gen/f32-raddextexp-avx512f-p5-scalef-u192-acc3.c", |
| "src/f32-raddextexp/gen/f32-raddextexp-avx512f-p5-scalef-u192-acc6.c", |
| "src/f32-raddextexp/gen/f32-raddextexp-avx512f-p5-scalef-u192.c", |
| "src/f32-raddstoreexpminusmax/gen/f32-raddstoreexpminusmax-avx512f-rr1-p5-scalef-u128-acc2.c", |
| "src/f32-raddstoreexpminusmax/gen/f32-raddstoreexpminusmax-avx512f-rr1-p5-scalef-u128-acc4.c", |
| "src/f32-raddstoreexpminusmax/gen/f32-raddstoreexpminusmax-avx512f-rr1-p5-scalef-u128.c", |
| "src/f32-raddstoreexpminusmax/gen/f32-raddstoreexpminusmax-avx512f-rr1-p5-scalef-u144-acc3.c", |
| "src/f32-raddstoreexpminusmax/gen/f32-raddstoreexpminusmax-avx512f-rr1-p5-scalef-u144.c", |
| "src/f32-raddstoreexpminusmax/gen/f32-raddstoreexpminusmax-avx512f-rr1-p5-scalef-u160-acc2.c", |
| "src/f32-raddstoreexpminusmax/gen/f32-raddstoreexpminusmax-avx512f-rr1-p5-scalef-u160-acc5.c", |
| "src/f32-raddstoreexpminusmax/gen/f32-raddstoreexpminusmax-avx512f-rr1-p5-scalef-u160.c", |
| "src/f32-raddstoreexpminusmax/gen/f32-raddstoreexpminusmax-avx512f-rr1-p5-scalef-u192-acc2.c", |
| "src/f32-raddstoreexpminusmax/gen/f32-raddstoreexpminusmax-avx512f-rr1-p5-scalef-u192-acc3.c", |
| "src/f32-raddstoreexpminusmax/gen/f32-raddstoreexpminusmax-avx512f-rr1-p5-scalef-u192-acc6.c", |
| "src/f32-raddstoreexpminusmax/gen/f32-raddstoreexpminusmax-avx512f-rr1-p5-scalef-u192.c", |
| "src/f32-rmax/f32-rmax-avx512f.c", |
| "src/f32-rminmax/gen/f32-rmax-avx512f-u16.c", |
| "src/f32-rminmax/gen/f32-rmax-avx512f-u32-acc2.c", |
| "src/f32-rminmax/gen/f32-rmax-avx512f-u48-acc3.c", |
| "src/f32-rminmax/gen/f32-rmax-avx512f-u64-acc2.c", |
| "src/f32-rminmax/gen/f32-rmax-avx512f-u64-acc4.c", |
| "src/f32-rminmax/gen/f32-rmin-avx512f-u16.c", |
| "src/f32-rminmax/gen/f32-rmin-avx512f-u32-acc2.c", |
| "src/f32-rminmax/gen/f32-rmin-avx512f-u48-acc3.c", |
| "src/f32-rminmax/gen/f32-rmin-avx512f-u64-acc2.c", |
| "src/f32-rminmax/gen/f32-rmin-avx512f-u64-acc4.c", |
| "src/f32-rminmax/gen/f32-rminmax-avx512f-u16.c", |
| "src/f32-rminmax/gen/f32-rminmax-avx512f-u32-acc2.c", |
| "src/f32-rminmax/gen/f32-rminmax-avx512f-u48-acc3.c", |
| "src/f32-rminmax/gen/f32-rminmax-avx512f-u64-acc2.c", |
| "src/f32-rminmax/gen/f32-rminmax-avx512f-u64-acc4.c", |
| "src/f32-vbinary/gen/f32-vadd-minmax-avx512f-u16.c", |
| "src/f32-vbinary/gen/f32-vadd-minmax-avx512f-u32.c", |
| "src/f32-vbinary/gen/f32-vaddc-minmax-avx512f-u16.c", |
| "src/f32-vbinary/gen/f32-vaddc-minmax-avx512f-u32.c", |
| "src/f32-vbinary/gen/f32-vdiv-minmax-avx512f-u16.c", |
| "src/f32-vbinary/gen/f32-vdiv-minmax-avx512f-u32.c", |
| "src/f32-vbinary/gen/f32-vdivc-minmax-avx512f-u16.c", |
| "src/f32-vbinary/gen/f32-vdivc-minmax-avx512f-u32.c", |
| "src/f32-vbinary/gen/f32-vmax-avx512f-u16.c", |
| "src/f32-vbinary/gen/f32-vmax-avx512f-u32.c", |
| "src/f32-vbinary/gen/f32-vmaxc-avx512f-u16.c", |
| "src/f32-vbinary/gen/f32-vmaxc-avx512f-u32.c", |
| "src/f32-vbinary/gen/f32-vmin-avx512f-u16.c", |
| "src/f32-vbinary/gen/f32-vmin-avx512f-u32.c", |
| "src/f32-vbinary/gen/f32-vminc-avx512f-u16.c", |
| "src/f32-vbinary/gen/f32-vminc-avx512f-u32.c", |
| "src/f32-vbinary/gen/f32-vmul-minmax-avx512f-u16.c", |
| "src/f32-vbinary/gen/f32-vmul-minmax-avx512f-u32.c", |
| "src/f32-vbinary/gen/f32-vmulc-minmax-avx512f-u16.c", |
| "src/f32-vbinary/gen/f32-vmulc-minmax-avx512f-u32.c", |
| "src/f32-vbinary/gen/f32-vrdivc-minmax-avx512f-u16.c", |
| "src/f32-vbinary/gen/f32-vrdivc-minmax-avx512f-u32.c", |
| "src/f32-vbinary/gen/f32-vrsubc-minmax-avx512f-u16.c", |
| "src/f32-vbinary/gen/f32-vrsubc-minmax-avx512f-u32.c", |
| "src/f32-vbinary/gen/f32-vsqrdiff-avx512f-u16.c", |
| "src/f32-vbinary/gen/f32-vsqrdiff-avx512f-u32.c", |
| "src/f32-vbinary/gen/f32-vsqrdiffc-avx512f-u16.c", |
| "src/f32-vbinary/gen/f32-vsqrdiffc-avx512f-u32.c", |
| "src/f32-vbinary/gen/f32-vsub-minmax-avx512f-u16.c", |
| "src/f32-vbinary/gen/f32-vsub-minmax-avx512f-u32.c", |
| "src/f32-vbinary/gen/f32-vsubc-minmax-avx512f-u16.c", |
| "src/f32-vbinary/gen/f32-vsubc-minmax-avx512f-u32.c", |
| "src/f32-vclamp/gen/f32-vclamp-avx512f-u16.c", |
| "src/f32-vclamp/gen/f32-vclamp-avx512f-u32.c", |
| "src/f32-velu/gen/f32-velu-avx512f-rr1-lut16-p3-perm-u16.c", |
| "src/f32-velu/gen/f32-velu-avx512f-rr1-lut16-p3-perm-u32.c", |
| "src/f32-velu/gen/f32-velu-avx512f-rr1-lut16-p3-perm-u48.c", |
| "src/f32-velu/gen/f32-velu-avx512f-rr1-lut16-p3-perm-u64.c", |
| "src/f32-velu/gen/f32-velu-avx512f-rr1-lut16-p3-perm-u80.c", |
| "src/f32-velu/gen/f32-velu-avx512f-rr1-lut16-p3-perm-u96.c", |
| "src/f32-velu/gen/f32-velu-avx512f-rr1-lut16-p3-perm-u112.c", |
| "src/f32-velu/gen/f32-velu-avx512f-rr1-lut16-p3-perm-u128.c", |
| "src/f32-velu/gen/f32-velu-avx512f-rr1-p6-u16.c", |
| "src/f32-velu/gen/f32-velu-avx512f-rr1-p6-u32.c", |
| "src/f32-velu/gen/f32-velu-avx512f-rr1-p6-u48.c", |
| "src/f32-velu/gen/f32-velu-avx512f-rr1-p6-u64.c", |
| "src/f32-velu/gen/f32-velu-avx512f-rr1-p6-u80.c", |
| "src/f32-velu/gen/f32-velu-avx512f-rr1-p6-u96.c", |
| "src/f32-velu/gen/f32-velu-avx512f-rr1-p6-u112.c", |
| "src/f32-velu/gen/f32-velu-avx512f-rr1-p6-u128.c", |
| "src/f32-vhswish/gen/f32-vhswish-avx512f-u16.c", |
| "src/f32-vhswish/gen/f32-vhswish-avx512f-u32.c", |
| "src/f32-vlrelu/gen/f32-vlrelu-avx512f-u16.c", |
| "src/f32-vlrelu/gen/f32-vlrelu-avx512f-u32.c", |
| "src/f32-vrelu/gen/f32-vrelu-avx512f-u16.c", |
| "src/f32-vrelu/gen/f32-vrelu-avx512f-u32.c", |
| "src/f32-vrnd/gen/f32-vrndd-avx512f-u16.c", |
| "src/f32-vrnd/gen/f32-vrndd-avx512f-u32.c", |
| "src/f32-vrnd/gen/f32-vrndne-avx512f-u16.c", |
| "src/f32-vrnd/gen/f32-vrndne-avx512f-u32.c", |
| "src/f32-vrnd/gen/f32-vrndu-avx512f-u16.c", |
| "src/f32-vrnd/gen/f32-vrndu-avx512f-u32.c", |
| "src/f32-vrnd/gen/f32-vrndz-avx512f-u16.c", |
| "src/f32-vrnd/gen/f32-vrndz-avx512f-u32.c", |
| "src/f32-vscaleexpminusmax/gen/f32-vscaleexpminusmax-avx512f-p5-scalef-u16.c", |
| "src/f32-vscaleexpminusmax/gen/f32-vscaleexpminusmax-avx512f-p5-scalef-u32.c", |
| "src/f32-vscaleexpminusmax/gen/f32-vscaleexpminusmax-avx512f-p5-scalef-u48.c", |
| "src/f32-vscaleexpminusmax/gen/f32-vscaleexpminusmax-avx512f-p5-scalef-u64.c", |
| "src/f32-vscaleexpminusmax/gen/f32-vscaleexpminusmax-avx512f-p5-scalef-u80.c", |
| "src/f32-vscaleexpminusmax/gen/f32-vscaleexpminusmax-avx512f-p5-scalef-u96.c", |
| "src/f32-vscaleexpminusmax/gen/f32-vscaleexpminusmax-avx512f-p5-scalef-u112.c", |
| "src/f32-vscaleexpminusmax/gen/f32-vscaleexpminusmax-avx512f-p5-scalef-u128.c", |
| "src/f32-vscaleexpminusmax/gen/f32-vscaleexpminusmax-avx512f-p5-scalef-u144.c", |
| "src/f32-vscaleexpminusmax/gen/f32-vscaleexpminusmax-avx512f-p5-scalef-u160.c", |
| "src/f32-vscaleexpminusmax/gen/f32-vscaleexpminusmax-avx512f-p5-scalef-u176.c", |
| "src/f32-vscaleexpminusmax/gen/f32-vscaleexpminusmax-avx512f-p5-scalef-u192.c", |
| "src/f32-vscaleextexp/gen/f32-vscaleextexp-avx512f-p5-scalef-u16.c", |
| "src/f32-vscaleextexp/gen/f32-vscaleextexp-avx512f-p5-scalef-u32.c", |
| "src/f32-vscaleextexp/gen/f32-vscaleextexp-avx512f-p5-scalef-u48.c", |
| "src/f32-vscaleextexp/gen/f32-vscaleextexp-avx512f-p5-scalef-u64.c", |
| "src/f32-vscaleextexp/gen/f32-vscaleextexp-avx512f-p5-scalef-u80.c", |
| "src/f32-vscaleextexp/gen/f32-vscaleextexp-avx512f-p5-scalef-u96.c", |
| "src/f32-vscaleextexp/gen/f32-vscaleextexp-avx512f-p5-scalef-u112.c", |
| "src/f32-vscaleextexp/gen/f32-vscaleextexp-avx512f-p5-scalef-u128.c", |
| "src/f32-vscaleextexp/gen/f32-vscaleextexp-avx512f-p5-scalef-u144.c", |
| "src/f32-vscaleextexp/gen/f32-vscaleextexp-avx512f-p5-scalef-u160.c", |
| "src/f32-vscaleextexp/gen/f32-vscaleextexp-avx512f-p5-scalef-u176.c", |
| "src/f32-vscaleextexp/gen/f32-vscaleextexp-avx512f-p5-scalef-u192.c", |
| "src/f32-vsigmoid/gen/f32-vsigmoid-avx512f-rr1-lut16-p3-perm-scalef-div-u16.c", |
| "src/f32-vsigmoid/gen/f32-vsigmoid-avx512f-rr1-lut16-p3-perm-scalef-div-u32.c", |
| "src/f32-vsigmoid/gen/f32-vsigmoid-avx512f-rr1-lut16-p3-perm-scalef-div-u48.c", |
| "src/f32-vsigmoid/gen/f32-vsigmoid-avx512f-rr1-lut16-p3-perm-scalef-div-u64.c", |
| "src/f32-vsigmoid/gen/f32-vsigmoid-avx512f-rr1-lut16-p3-perm-scalef-div-u80.c", |
| "src/f32-vsigmoid/gen/f32-vsigmoid-avx512f-rr1-lut16-p3-perm-scalef-div-u96.c", |
| "src/f32-vsigmoid/gen/f32-vsigmoid-avx512f-rr1-lut16-p3-perm-scalef-div-u112.c", |
| "src/f32-vsigmoid/gen/f32-vsigmoid-avx512f-rr1-lut16-p3-perm-scalef-div-u128.c", |
| "src/f32-vsigmoid/gen/f32-vsigmoid-avx512f-rr1-lut16-p3-perm-scalef-nr1fma-u16.c", |
| "src/f32-vsigmoid/gen/f32-vsigmoid-avx512f-rr1-lut16-p3-perm-scalef-nr1fma-u32.c", |
| "src/f32-vsigmoid/gen/f32-vsigmoid-avx512f-rr1-lut16-p3-perm-scalef-nr1fma-u48.c", |
| "src/f32-vsigmoid/gen/f32-vsigmoid-avx512f-rr1-lut16-p3-perm-scalef-nr1fma-u64.c", |
| "src/f32-vsigmoid/gen/f32-vsigmoid-avx512f-rr1-lut16-p3-perm-scalef-nr1fma-u80.c", |
| "src/f32-vsigmoid/gen/f32-vsigmoid-avx512f-rr1-lut16-p3-perm-scalef-nr1fma-u96.c", |
| "src/f32-vsigmoid/gen/f32-vsigmoid-avx512f-rr1-lut16-p3-perm-scalef-nr1fma-u112.c", |
| "src/f32-vsigmoid/gen/f32-vsigmoid-avx512f-rr1-lut16-p3-perm-scalef-nr1fma-u128.c", |
| "src/f32-vsigmoid/gen/f32-vsigmoid-avx512f-rr1-p5-scalef-div-u16.c", |
| "src/f32-vsigmoid/gen/f32-vsigmoid-avx512f-rr1-p5-scalef-div-u32.c", |
| "src/f32-vsigmoid/gen/f32-vsigmoid-avx512f-rr1-p5-scalef-div-u48.c", |
| "src/f32-vsigmoid/gen/f32-vsigmoid-avx512f-rr1-p5-scalef-div-u64.c", |
| "src/f32-vsigmoid/gen/f32-vsigmoid-avx512f-rr1-p5-scalef-div-u80.c", |
| "src/f32-vsigmoid/gen/f32-vsigmoid-avx512f-rr1-p5-scalef-div-u96.c", |
| "src/f32-vsigmoid/gen/f32-vsigmoid-avx512f-rr1-p5-scalef-div-u112.c", |
| "src/f32-vsigmoid/gen/f32-vsigmoid-avx512f-rr1-p5-scalef-div-u128.c", |
| "src/f32-vsigmoid/gen/f32-vsigmoid-avx512f-rr1-p5-scalef-nr1fma-u16.c", |
| "src/f32-vsigmoid/gen/f32-vsigmoid-avx512f-rr1-p5-scalef-nr1fma-u32.c", |
| "src/f32-vsigmoid/gen/f32-vsigmoid-avx512f-rr1-p5-scalef-nr1fma-u48.c", |
| "src/f32-vsigmoid/gen/f32-vsigmoid-avx512f-rr1-p5-scalef-nr1fma-u64.c", |
| "src/f32-vsigmoid/gen/f32-vsigmoid-avx512f-rr1-p5-scalef-nr1fma-u80.c", |
| "src/f32-vsigmoid/gen/f32-vsigmoid-avx512f-rr1-p5-scalef-nr1fma-u96.c", |
| "src/f32-vsigmoid/gen/f32-vsigmoid-avx512f-rr1-p5-scalef-nr1fma-u112.c", |
| "src/f32-vsigmoid/gen/f32-vsigmoid-avx512f-rr1-p5-scalef-nr1fma-u128.c", |
| "src/f32-vsigmoid/gen/f32-vsigmoid-avx512f-rr2-lut32-p2-perm2-scalef-div-u16.c", |
| "src/f32-vsigmoid/gen/f32-vsigmoid-avx512f-rr2-lut32-p2-perm2-scalef-div-u32.c", |
| "src/f32-vsigmoid/gen/f32-vsigmoid-avx512f-rr2-lut32-p2-perm2-scalef-div-u48.c", |
| "src/f32-vsigmoid/gen/f32-vsigmoid-avx512f-rr2-lut32-p2-perm2-scalef-div-u64.c", |
| "src/f32-vsigmoid/gen/f32-vsigmoid-avx512f-rr2-lut32-p2-perm2-scalef-div-u80.c", |
| "src/f32-vsigmoid/gen/f32-vsigmoid-avx512f-rr2-lut32-p2-perm2-scalef-div-u96.c", |
| "src/f32-vsigmoid/gen/f32-vsigmoid-avx512f-rr2-lut32-p2-perm2-scalef-div-u112.c", |
| "src/f32-vsigmoid/gen/f32-vsigmoid-avx512f-rr2-lut32-p2-perm2-scalef-div-u128.c", |
| "src/f32-vsigmoid/gen/f32-vsigmoid-avx512f-rr2-lut32-p2-perm2-scalef-nr1fma-u16.c", |
| "src/f32-vsigmoid/gen/f32-vsigmoid-avx512f-rr2-lut32-p2-perm2-scalef-nr1fma-u32.c", |
| "src/f32-vsigmoid/gen/f32-vsigmoid-avx512f-rr2-lut32-p2-perm2-scalef-nr1fma-u48.c", |
| "src/f32-vsigmoid/gen/f32-vsigmoid-avx512f-rr2-lut32-p2-perm2-scalef-nr1fma-u64.c", |
| "src/f32-vsigmoid/gen/f32-vsigmoid-avx512f-rr2-lut32-p2-perm2-scalef-nr1fma-u80.c", |
| "src/f32-vsigmoid/gen/f32-vsigmoid-avx512f-rr2-lut32-p2-perm2-scalef-nr1fma-u96.c", |
| "src/f32-vsigmoid/gen/f32-vsigmoid-avx512f-rr2-lut32-p2-perm2-scalef-nr1fma-u112.c", |
| "src/f32-vsigmoid/gen/f32-vsigmoid-avx512f-rr2-lut32-p2-perm2-scalef-nr1fma-u128.c", |
| "src/f32-vsqrt/gen/f32-vsqrt-avx512f-nr1fma1adj-u16.c", |
| "src/f32-vsqrt/gen/f32-vsqrt-avx512f-nr1fma1adj-u32.c", |
| "src/f32-vsqrt/gen/f32-vsqrt-avx512f-nr1fma1adj-u48.c", |
| "src/f32-vsqrt/gen/f32-vsqrt-avx512f-nr1fma1adj-u64.c", |
| "src/f32-vsqrt/gen/f32-vsqrt-avx512f-nr1fma1adj-u80.c", |
| "src/f32-vsqrt/gen/f32-vsqrt-avx512f-nr1fma1adj-u96.c", |
| "src/f32-vsqrt/gen/f32-vsqrt-avx512f-nr1fma1adj-u112.c", |
| "src/f32-vsqrt/gen/f32-vsqrt-avx512f-nr1fma1adj-u128.c", |
| "src/f32-vunary/gen/f32-vabs-avx512f-u16.c", |
| "src/f32-vunary/gen/f32-vabs-avx512f-u32.c", |
| "src/f32-vunary/gen/f32-vneg-avx512f-u16.c", |
| "src/f32-vunary/gen/f32-vneg-avx512f-u32.c", |
| "src/f32-vunary/gen/f32-vsqr-avx512f-u16.c", |
| "src/f32-vunary/gen/f32-vsqr-avx512f-u32.c", |
| "src/math/f32-exp-avx512f-rr2-lut16-p3-perm-scalef.c", |
| "src/math/f32-exp-avx512f-rr2-lut16-p3-perm.c", |
| "src/math/f32-exp-avx512f-rr2-lut32-p2-perm2-scalef.c", |
| "src/math/f32-exp-avx512f-rr2-lut32-p2-perm2.c", |
| "src/math/f32-exp-avx512f-rr2-p5-scalef.c", |
| "src/math/f32-exp-avx512f-rr2-p5.c", |
| "src/math/f32-expm1minus-avx512f-rr1-lut16-p3-perm.c", |
| "src/math/f32-expm1minus-avx512f-rr1-p6.c", |
| "src/math/f32-extexp-avx512f-p5.c", |
| "src/math/f32-sigmoid-avx512f-rr1-lut16-p3-perm-scalef-div.c", |
| "src/math/f32-sigmoid-avx512f-rr1-lut16-p3-perm-scalef-nr1fma1adj.c", |
| "src/math/f32-sigmoid-avx512f-rr1-lut16-p3-perm-scalef-nr1fma.c", |
| "src/math/f32-sigmoid-avx512f-rr1-lut32-p2-perm2-scalef-div.c", |
| "src/math/f32-sigmoid-avx512f-rr1-lut32-p2-perm2-scalef-nr1fma1adj.c", |
| "src/math/f32-sigmoid-avx512f-rr1-lut32-p2-perm2-scalef-nr1fma.c", |
| "src/math/f32-sigmoid-avx512f-rr1-lut64-p2-gather-scalef-div.c", |
| "src/math/f32-sigmoid-avx512f-rr1-lut64-p2-gather-scalef-nr1fma1adj.c", |
| "src/math/f32-sigmoid-avx512f-rr1-lut64-p2-gather-scalef-nr1fma.c", |
| "src/math/f32-sigmoid-avx512f-rr1-p5-scalef-div.c", |
| "src/math/f32-sigmoid-avx512f-rr1-p5-scalef-nr1fma1adj.c", |
| "src/math/f32-sigmoid-avx512f-rr1-p5-scalef-nr1fma.c", |
| "src/math/f32-sigmoid-avx512f-rr2-lut16-p3-perm-scalef-div.c", |
| "src/math/f32-sigmoid-avx512f-rr2-lut16-p3-perm-scalef-nr1fma1adj.c", |
| "src/math/f32-sigmoid-avx512f-rr2-lut16-p3-perm-scalef-nr1fma.c", |
| "src/math/f32-sigmoid-avx512f-rr2-lut32-p2-perm2-scalef-div.c", |
| "src/math/f32-sigmoid-avx512f-rr2-lut32-p2-perm2-scalef-nr1fma1adj.c", |
| "src/math/f32-sigmoid-avx512f-rr2-lut32-p2-perm2-scalef-nr1fma.c", |
| "src/math/f32-sigmoid-avx512f-rr2-lut64-p2-gather-scalef-div.c", |
| "src/math/f32-sigmoid-avx512f-rr2-lut64-p2-gather-scalef-nr1fma1adj.c", |
| "src/math/f32-sigmoid-avx512f-rr2-lut64-p2-gather-scalef-nr1fma.c", |
| "src/math/f32-sigmoid-avx512f-rr2-p5-scalef-div.c", |
| "src/math/f32-sigmoid-avx512f-rr2-p5-scalef-nr1fma1adj.c", |
| "src/math/f32-sigmoid-avx512f-rr2-p5-scalef-nr1fma.c", |
| "src/math/f32-sqrt-avx512f-nr1fma1adj.c", |
| "src/math/f32-sqrt-avx512f-nr1fma.c", |
| "src/math/f32-sqrt-avx512f-nr2fma.c", |
| "src/x32-packw/gen/x32-packw-x16-gemm-goi-avx512f-u4-prfm.c", |
| "src/x32-packw/gen/x32-packw-x16-gemm-goi-avx512f-u4.c", |
| ] |
| |
| ALL_AVX512SKX_MICROKERNEL_SRCS = [ |
| "src/f16-f32-vcvt/gen/f16-f32-vcvt-avx512skx-u16.c", |
| "src/f16-f32-vcvt/gen/f16-f32-vcvt-avx512skx-u32.c", |
| "src/f32-f16-vcvt/gen/f32-f16-vcvt-avx512skx-u16.c", |
| "src/f32-f16-vcvt/gen/f32-f16-vcvt-avx512skx-u32.c", |
| "src/f32-qc8w-gemm/gen/f32-qc4w-gemm-1x32-minmax-avx512skx-broadcast.c", |
| "src/f32-qc8w-gemm/gen/f32-qc4w-gemm-2x32-minmax-avx512skx-broadcast.c", |
| "src/f32-qc8w-gemm/gen/f32-qc4w-gemm-3x32-minmax-avx512skx-broadcast.c", |
| "src/f32-qc8w-gemm/gen/f32-qc4w-gemm-4x32-minmax-avx512skx-broadcast.c", |
| "src/f32-qc8w-gemm/gen/f32-qc4w-gemm-5x32-minmax-avx512skx-broadcast.c", |
| "src/f32-qc8w-gemm/gen/f32-qc4w-gemm-6x32-minmax-avx512skx-broadcast.c", |
| "src/f32-qc8w-gemm/gen/f32-qc4w-gemm-7x32-minmax-avx512skx-broadcast.c", |
| "src/f32-qc8w-gemm/gen/f32-qc4w-gemm-8x32-minmax-avx512skx-broadcast.c", |
| "src/f32-qc8w-gemm/gen/f32-qc8w-gemm-1x16-minmax-avx512skx-broadcast.c", |
| "src/f32-qc8w-gemm/gen/f32-qc8w-gemm-1x32-minmax-avx512skx-broadcast.c", |
| "src/f32-qc8w-gemm/gen/f32-qc8w-gemm-2x16-minmax-avx512skx-broadcast.c", |
| "src/f32-qc8w-gemm/gen/f32-qc8w-gemm-2x32-minmax-avx512skx-broadcast.c", |
| "src/f32-qc8w-gemm/gen/f32-qc8w-gemm-3x16-minmax-avx512skx-broadcast.c", |
| "src/f32-qc8w-gemm/gen/f32-qc8w-gemm-3x32-minmax-avx512skx-broadcast.c", |
| "src/f32-qc8w-gemm/gen/f32-qc8w-gemm-4x16-minmax-avx512skx-broadcast.c", |
| "src/f32-qc8w-gemm/gen/f32-qc8w-gemm-4x32-minmax-avx512skx-broadcast.c", |
| "src/f32-qc8w-gemm/gen/f32-qc8w-gemm-5x16-minmax-avx512skx-broadcast.c", |
| "src/f32-qc8w-gemm/gen/f32-qc8w-gemm-5x32-minmax-avx512skx-broadcast.c", |
| "src/f32-qc8w-gemm/gen/f32-qc8w-gemm-6x16-minmax-avx512skx-broadcast.c", |
| "src/f32-qc8w-gemm/gen/f32-qc8w-gemm-6x32-minmax-avx512skx-broadcast.c", |
| "src/f32-qc8w-gemm/gen/f32-qc8w-gemm-7x16-minmax-avx512skx-broadcast.c", |
| "src/f32-qc8w-gemm/gen/f32-qc8w-gemm-7x32-minmax-avx512skx-broadcast.c", |
| "src/f32-qc8w-gemm/gen/f32-qc8w-gemm-8x16-minmax-avx512skx-broadcast.c", |
| "src/f32-qc8w-gemm/gen/f32-qc8w-gemm-8x32-minmax-avx512skx-broadcast.c", |
| "src/f32-qs8-vcvt/gen/f32-qs8-vcvt-avx512skx-u32.c", |
| "src/f32-qs8-vcvt/gen/f32-qs8-vcvt-avx512skx-u64.c", |
| "src/f32-qs8-vcvt/gen/f32-qs8-vcvt-avx512skx-u96.c", |
| "src/f32-qs8-vcvt/gen/f32-qs8-vcvt-avx512skx-u128.c", |
| "src/f32-qu8-vcvt/gen/f32-qu8-vcvt-avx512skx-u32.c", |
| "src/f32-qu8-vcvt/gen/f32-qu8-vcvt-avx512skx-u64.c", |
| "src/f32-qu8-vcvt/gen/f32-qu8-vcvt-avx512skx-u96.c", |
| "src/f32-qu8-vcvt/gen/f32-qu8-vcvt-avx512skx-u128.c", |
| "src/f32-vtanh/gen/f32-vtanh-avx512skx-expm1minus-rr1-lut4-p4h3ts-perm-div-u16.c", |
| "src/f32-vtanh/gen/f32-vtanh-avx512skx-expm1minus-rr1-lut4-p4h3ts-perm-div-u32.c", |
| "src/f32-vtanh/gen/f32-vtanh-avx512skx-expm1minus-rr1-lut4-p4h3ts-perm-div-u48.c", |
| "src/f32-vtanh/gen/f32-vtanh-avx512skx-expm1minus-rr1-lut4-p4h3ts-perm-div-u64.c", |
| "src/f32-vtanh/gen/f32-vtanh-avx512skx-expm1minus-rr1-lut4-p4h3ts-perm-div-u80.c", |
| "src/f32-vtanh/gen/f32-vtanh-avx512skx-expm1minus-rr1-lut4-p4h3ts-perm-div-u96.c", |
| "src/f32-vtanh/gen/f32-vtanh-avx512skx-expm1minus-rr1-lut4-p4h3ts-perm-div-u112.c", |
| "src/f32-vtanh/gen/f32-vtanh-avx512skx-expm1minus-rr1-lut4-p4h3ts-perm-div-u128.c", |
| "src/f32-vtanh/gen/f32-vtanh-avx512skx-expm1minus-rr1-lut4-p4h3ts-perm-div-u144.c", |
| "src/f32-vtanh/gen/f32-vtanh-avx512skx-expm1minus-rr1-lut4-p4h3ts-perm-div-u160.c", |
| "src/f32-vtanh/gen/f32-vtanh-avx512skx-expm1minus-rr1-lut4-p4h3ts-perm-nr1adj-u16.c", |
| "src/f32-vtanh/gen/f32-vtanh-avx512skx-expm1minus-rr1-lut4-p4h3ts-perm-nr1adj-u32.c", |
| "src/f32-vtanh/gen/f32-vtanh-avx512skx-expm1minus-rr1-lut4-p4h3ts-perm-nr1adj-u48.c", |
| "src/f32-vtanh/gen/f32-vtanh-avx512skx-expm1minus-rr1-lut4-p4h3ts-perm-nr1adj-u64.c", |
| "src/f32-vtanh/gen/f32-vtanh-avx512skx-expm1minus-rr1-lut4-p4h3ts-perm-nr1adj-u80.c", |
| "src/f32-vtanh/gen/f32-vtanh-avx512skx-expm1minus-rr1-lut4-p4h3ts-perm-nr1adj-u96.c", |
| "src/f32-vtanh/gen/f32-vtanh-avx512skx-expm1minus-rr1-lut4-p4h3ts-perm-nr1adj-u112.c", |
| "src/f32-vtanh/gen/f32-vtanh-avx512skx-expm1minus-rr1-lut4-p4h3ts-perm-nr1adj-u128.c", |
| "src/f32-vtanh/gen/f32-vtanh-avx512skx-expm1minus-rr1-lut4-p4h3ts-perm-nr1adj-u144.c", |
| "src/f32-vtanh/gen/f32-vtanh-avx512skx-expm1minus-rr1-lut4-p4h3ts-perm-nr1adj-u160.c", |
| "src/f32-vtanh/gen/f32-vtanh-avx512skx-expm1minus-rr1-lut8-p4h3ts-gather-div-u16.c", |
| "src/f32-vtanh/gen/f32-vtanh-avx512skx-expm1minus-rr1-lut8-p4h3ts-gather-div-u32.c", |
| "src/f32-vtanh/gen/f32-vtanh-avx512skx-expm1minus-rr1-lut8-p4h3ts-gather-div-u48.c", |
| "src/f32-vtanh/gen/f32-vtanh-avx512skx-expm1minus-rr1-lut8-p4h3ts-gather-div-u64.c", |
| "src/f32-vtanh/gen/f32-vtanh-avx512skx-expm1minus-rr1-lut8-p4h3ts-gather-div-u80.c", |
| "src/f32-vtanh/gen/f32-vtanh-avx512skx-expm1minus-rr1-lut8-p4h3ts-gather-div-u96.c", |
| "src/f32-vtanh/gen/f32-vtanh-avx512skx-expm1minus-rr1-lut8-p4h3ts-gather-div-u112.c", |
| "src/f32-vtanh/gen/f32-vtanh-avx512skx-expm1minus-rr1-lut8-p4h3ts-gather-div-u128.c", |
| "src/f32-vtanh/gen/f32-vtanh-avx512skx-expm1minus-rr1-lut8-p4h3ts-gather-div-u144.c", |
| "src/f32-vtanh/gen/f32-vtanh-avx512skx-expm1minus-rr1-lut8-p4h3ts-gather-div-u160.c", |
| "src/f32-vtanh/gen/f32-vtanh-avx512skx-expm1minus-rr1-lut8-p4h3ts-gather-nr1adj-u16.c", |
| "src/f32-vtanh/gen/f32-vtanh-avx512skx-expm1minus-rr1-lut8-p4h3ts-gather-nr1adj-u32.c", |
| "src/f32-vtanh/gen/f32-vtanh-avx512skx-expm1minus-rr1-lut8-p4h3ts-gather-nr1adj-u48.c", |
| "src/f32-vtanh/gen/f32-vtanh-avx512skx-expm1minus-rr1-lut8-p4h3ts-gather-nr1adj-u64.c", |
| "src/f32-vtanh/gen/f32-vtanh-avx512skx-expm1minus-rr1-lut8-p4h3ts-gather-nr1adj-u80.c", |
| "src/f32-vtanh/gen/f32-vtanh-avx512skx-expm1minus-rr1-lut8-p4h3ts-gather-nr1adj-u96.c", |
| "src/f32-vtanh/gen/f32-vtanh-avx512skx-expm1minus-rr1-lut8-p4h3ts-gather-nr1adj-u112.c", |
| "src/f32-vtanh/gen/f32-vtanh-avx512skx-expm1minus-rr1-lut8-p4h3ts-gather-nr1adj-u128.c", |
| "src/f32-vtanh/gen/f32-vtanh-avx512skx-expm1minus-rr1-lut8-p4h3ts-gather-nr1adj-u144.c", |
| "src/f32-vtanh/gen/f32-vtanh-avx512skx-expm1minus-rr1-lut8-p4h3ts-gather-nr1adj-u160.c", |
| "src/f32-vtanh/gen/f32-vtanh-avx512skx-expm1minus-rr1-lut8-p4h3ts-perm-div-u16.c", |
| "src/f32-vtanh/gen/f32-vtanh-avx512skx-expm1minus-rr1-lut8-p4h3ts-perm-div-u32.c", |
| "src/f32-vtanh/gen/f32-vtanh-avx512skx-expm1minus-rr1-lut8-p4h3ts-perm-div-u48.c", |
| "src/f32-vtanh/gen/f32-vtanh-avx512skx-expm1minus-rr1-lut8-p4h3ts-perm-div-u64.c", |
| "src/f32-vtanh/gen/f32-vtanh-avx512skx-expm1minus-rr1-lut8-p4h3ts-perm-div-u80.c", |
| "src/f32-vtanh/gen/f32-vtanh-avx512skx-expm1minus-rr1-lut8-p4h3ts-perm-div-u96.c", |
| "src/f32-vtanh/gen/f32-vtanh-avx512skx-expm1minus-rr1-lut8-p4h3ts-perm-div-u112.c", |
| "src/f32-vtanh/gen/f32-vtanh-avx512skx-expm1minus-rr1-lut8-p4h3ts-perm-div-u128.c", |
| "src/f32-vtanh/gen/f32-vtanh-avx512skx-expm1minus-rr1-lut8-p4h3ts-perm-div-u144.c", |
| "src/f32-vtanh/gen/f32-vtanh-avx512skx-expm1minus-rr1-lut8-p4h3ts-perm-div-u160.c", |
| "src/f32-vtanh/gen/f32-vtanh-avx512skx-expm1minus-rr1-lut8-p4h3ts-perm-nr1adj-u16.c", |
| "src/f32-vtanh/gen/f32-vtanh-avx512skx-expm1minus-rr1-lut8-p4h3ts-perm-nr1adj-u32.c", |
| "src/f32-vtanh/gen/f32-vtanh-avx512skx-expm1minus-rr1-lut8-p4h3ts-perm-nr1adj-u48.c", |
| "src/f32-vtanh/gen/f32-vtanh-avx512skx-expm1minus-rr1-lut8-p4h3ts-perm-nr1adj-u64.c", |
| "src/f32-vtanh/gen/f32-vtanh-avx512skx-expm1minus-rr1-lut8-p4h3ts-perm-nr1adj-u80.c", |
| "src/f32-vtanh/gen/f32-vtanh-avx512skx-expm1minus-rr1-lut8-p4h3ts-perm-nr1adj-u96.c", |
| "src/f32-vtanh/gen/f32-vtanh-avx512skx-expm1minus-rr1-lut8-p4h3ts-perm-nr1adj-u112.c", |
| "src/f32-vtanh/gen/f32-vtanh-avx512skx-expm1minus-rr1-lut8-p4h3ts-perm-nr1adj-u128.c", |
| "src/f32-vtanh/gen/f32-vtanh-avx512skx-expm1minus-rr1-lut8-p4h3ts-perm-nr1adj-u144.c", |
| "src/f32-vtanh/gen/f32-vtanh-avx512skx-expm1minus-rr1-lut8-p4h3ts-perm-nr1adj-u160.c", |
| "src/f32-vtanh/gen/f32-vtanh-avx512skx-expm1minus-rr1-p6h5ts-div-u16.c", |
| "src/f32-vtanh/gen/f32-vtanh-avx512skx-expm1minus-rr1-p6h5ts-div-u32.c", |
| "src/f32-vtanh/gen/f32-vtanh-avx512skx-expm1minus-rr1-p6h5ts-div-u48.c", |
| "src/f32-vtanh/gen/f32-vtanh-avx512skx-expm1minus-rr1-p6h5ts-div-u64.c", |
| "src/f32-vtanh/gen/f32-vtanh-avx512skx-expm1minus-rr1-p6h5ts-div-u80.c", |
| "src/f32-vtanh/gen/f32-vtanh-avx512skx-expm1minus-rr1-p6h5ts-div-u96.c", |
| "src/f32-vtanh/gen/f32-vtanh-avx512skx-expm1minus-rr1-p6h5ts-div-u112.c", |
| "src/f32-vtanh/gen/f32-vtanh-avx512skx-expm1minus-rr1-p6h5ts-div-u128.c", |
| "src/f32-vtanh/gen/f32-vtanh-avx512skx-expm1minus-rr1-p6h5ts-div-u144.c", |
| "src/f32-vtanh/gen/f32-vtanh-avx512skx-expm1minus-rr1-p6h5ts-div-u160.c", |
| "src/f32-vtanh/gen/f32-vtanh-avx512skx-expm1minus-rr1-p6h5ts-nr1-u16.c", |
| "src/f32-vtanh/gen/f32-vtanh-avx512skx-expm1minus-rr1-p6h5ts-nr1-u32.c", |
| "src/f32-vtanh/gen/f32-vtanh-avx512skx-expm1minus-rr1-p6h5ts-nr1-u48.c", |
| "src/f32-vtanh/gen/f32-vtanh-avx512skx-expm1minus-rr1-p6h5ts-nr1-u64.c", |
| "src/f32-vtanh/gen/f32-vtanh-avx512skx-expm1minus-rr1-p6h5ts-nr1-u80.c", |
| "src/f32-vtanh/gen/f32-vtanh-avx512skx-expm1minus-rr1-p6h5ts-nr1-u96.c", |
| "src/f32-vtanh/gen/f32-vtanh-avx512skx-expm1minus-rr1-p6h5ts-nr1-u112.c", |
| "src/f32-vtanh/gen/f32-vtanh-avx512skx-expm1minus-rr1-p6h5ts-nr1-u128.c", |
| "src/f32-vtanh/gen/f32-vtanh-avx512skx-expm1minus-rr1-p6h5ts-nr1-u144.c", |
| "src/f32-vtanh/gen/f32-vtanh-avx512skx-expm1minus-rr1-p6h5ts-nr1-u160.c", |
| "src/math/gen/f32-tanh-avx512skx-expm1minus-rr1-lut4-p4h3ts-perm-div.c", |
| "src/math/gen/f32-tanh-avx512skx-expm1minus-rr1-lut4-p4h3ts-perm-nr1adj.c", |
| "src/math/gen/f32-tanh-avx512skx-expm1minus-rr1-lut8-p4h3ps-gather-div.c", |
| "src/math/gen/f32-tanh-avx512skx-expm1minus-rr1-lut8-p4h3ps-gather-nr1.c", |
| "src/math/gen/f32-tanh-avx512skx-expm1minus-rr1-lut8-p4h3ps-gather-nr1adj.c", |
| "src/math/gen/f32-tanh-avx512skx-expm1minus-rr1-lut8-p4h3ps-perm-div.c", |
| "src/math/gen/f32-tanh-avx512skx-expm1minus-rr1-lut8-p4h3ps-perm-nr1.c", |
| "src/math/gen/f32-tanh-avx512skx-expm1minus-rr1-lut8-p4h3ps-perm-nr1adj.c", |
| "src/math/gen/f32-tanh-avx512skx-expm1minus-rr1-p6h5ts-div.c", |
| "src/math/gen/f32-tanh-avx512skx-expm1minus-rr1-p6h5ts-nr1.c", |
| "src/math/gen/f32-tanh-avx512skx-expm1minus-rr1-p6h5ts-nr1adj.c", |
| "src/qd8-f32-qc8w-gemm/gen/qd8-f32-qc8w-gemm-1x16c8-minmax-avx512skx.c", |
| "src/qd8-f32-qc8w-gemm/gen/qd8-f32-qc8w-gemm-2x16c8-minmax-avx512skx.c", |
| "src/qd8-f32-qc8w-gemm/gen/qd8-f32-qc8w-gemm-3x16c8-minmax-avx512skx.c", |
| "src/qd8-f32-qc8w-gemm/gen/qd8-f32-qc8w-gemm-4x16c8-minmax-avx512skx.c", |
| "src/qs8-dwconv/gen/qs8-dwconv-5f5m5l16c16s1r-minmax-fp32-avx512skx-mul32.c", |
| "src/qs8-dwconv/gen/qs8-dwconv-5f5m5l32c16s1r-minmax-fp32-avx512skx-mul32.c", |
| "src/qs8-dwconv/gen/qs8-dwconv-6f6m7l16c16s1r-minmax-fp32-avx512skx-mul32.c", |
| "src/qs8-dwconv/gen/qs8-dwconv-6f6m7l32c16s1r-minmax-fp32-avx512skx-mul32.c", |
| "src/qs8-dwconv/gen/qs8-dwconv-8f8m9l16c16s1r-minmax-fp32-avx512skx-mul32.c", |
| "src/qs8-dwconv/gen/qs8-dwconv-8f8m9l32c16s1r-minmax-fp32-avx512skx-mul32.c", |
| "src/qs8-dwconv/gen/qs8-dwconv-9p16c-minmax-fp32-avx512skx-mul32.c", |
| "src/qs8-dwconv/gen/qs8-dwconv-9p32c-minmax-fp32-avx512skx-mul32.c", |
| "src/qs8-dwconv/gen/qs8-dwconv-25p16c-minmax-fp32-avx512skx-mul32.c", |
| "src/qs8-dwconv/gen/qs8-dwconv-25p32c-minmax-fp32-avx512skx-mul32.c", |
| "src/qs8-f32-vcvt/gen/qs8-f32-vcvt-avx512skx-u16.c", |
| "src/qs8-f32-vcvt/gen/qs8-f32-vcvt-avx512skx-u32.c", |
| "src/qs8-f32-vcvt/gen/qs8-f32-vcvt-avx512skx-u48.c", |
| "src/qs8-f32-vcvt/gen/qs8-f32-vcvt-avx512skx-u64.c", |
| "src/qs8-gemm/gen/qs8-gemm-1x16c8-minmax-fp32-avx512skx.c", |
| "src/qs8-gemm/gen/qs8-gemm-2x16c8-minmax-fp32-avx512skx.c", |
| "src/qs8-gemm/gen/qs8-gemm-3x16c8-minmax-fp32-avx512skx.c", |
| "src/qs8-gemm/gen/qs8-gemm-4x16c8-minmax-fp32-avx512skx.c", |
| "src/qs8-igemm/gen/qs8-igemm-1x16c8-minmax-fp32-avx512skx.c", |
| "src/qs8-igemm/gen/qs8-igemm-2x16c8-minmax-fp32-avx512skx.c", |
| "src/qs8-igemm/gen/qs8-igemm-3x16c8-minmax-fp32-avx512skx.c", |
| "src/qs8-igemm/gen/qs8-igemm-4x16c8-minmax-fp32-avx512skx.c", |
| "src/qs8-qc8w-dwconv/gen/qs8-qc8w-dwconv-3p32c-minmax-fp32-avx512skx-mul32.c", |
| "src/qs8-qc8w-dwconv/gen/qs8-qc8w-dwconv-5f5m5l16c16s1r-minmax-fp32-avx512skx-mul32.c", |
| "src/qs8-qc8w-dwconv/gen/qs8-qc8w-dwconv-5f5m5l32c16s1r-minmax-fp32-avx512skx-mul32.c", |
| "src/qs8-qc8w-dwconv/gen/qs8-qc8w-dwconv-6f6m7l16c16s1r-minmax-fp32-avx512skx-mul32.c", |
| "src/qs8-qc8w-dwconv/gen/qs8-qc8w-dwconv-6f6m7l32c16s1r-minmax-fp32-avx512skx-mul32.c", |
| "src/qs8-qc8w-dwconv/gen/qs8-qc8w-dwconv-8f8m9l16c16s1r-minmax-fp32-avx512skx-mul32.c", |
| "src/qs8-qc8w-dwconv/gen/qs8-qc8w-dwconv-8f8m9l32c16s1r-minmax-fp32-avx512skx-mul32.c", |
| "src/qs8-qc8w-dwconv/gen/qs8-qc8w-dwconv-9p16c-minmax-fp32-avx512skx-mul32.c", |
| "src/qs8-qc8w-dwconv/gen/qs8-qc8w-dwconv-9p32c-minmax-fp32-avx512skx-mul32.c", |
| "src/qs8-qc8w-dwconv/gen/qs8-qc8w-dwconv-25p16c-minmax-fp32-avx512skx-mul32.c", |
| "src/qs8-qc8w-dwconv/gen/qs8-qc8w-dwconv-25p32c-minmax-fp32-avx512skx-mul32.c", |
| "src/qs8-qc8w-gemm/gen/qs8-qc8w-gemm-1x16c8-minmax-fp32-avx512skx.c", |
| "src/qs8-qc8w-gemm/gen/qs8-qc8w-gemm-2x16c8-minmax-fp32-avx512skx.c", |
| "src/qs8-qc8w-gemm/gen/qs8-qc8w-gemm-3x16c8-minmax-fp32-avx512skx.c", |
| "src/qs8-qc8w-gemm/gen/qs8-qc8w-gemm-4x16c8-minmax-fp32-avx512skx.c", |
| "src/qs8-qc8w-igemm/gen/qs8-qc8w-igemm-1x16c8-minmax-fp32-avx512skx.c", |
| "src/qs8-qc8w-igemm/gen/qs8-qc8w-igemm-2x16c8-minmax-fp32-avx512skx.c", |
| "src/qs8-qc8w-igemm/gen/qs8-qc8w-igemm-3x16c8-minmax-fp32-avx512skx.c", |
| "src/qs8-qc8w-igemm/gen/qs8-qc8w-igemm-4x16c8-minmax-fp32-avx512skx.c", |
| "src/qs8-vadd/gen/qs8-vadd-minmax-avx512skx-mul32-ld128-u16.c", |
| "src/qs8-vadd/gen/qs8-vadd-minmax-avx512skx-mul32-ld128-u32.c", |
| "src/qs8-vaddc/gen/qs8-vaddc-minmax-avx512skx-mul32-ld128-u16.c", |
| "src/qs8-vaddc/gen/qs8-vaddc-minmax-avx512skx-mul32-ld128-u32.c", |
| "src/qu8-dwconv/gen/qu8-dwconv-5f5m5l16c16s1r-minmax-fp32-avx512skx-mul32.c", |
| "src/qu8-dwconv/gen/qu8-dwconv-5f5m5l32c16s1r-minmax-fp32-avx512skx-mul32.c", |
| "src/qu8-dwconv/gen/qu8-dwconv-6f6m7l16c16s1r-minmax-fp32-avx512skx-mul32.c", |
| "src/qu8-dwconv/gen/qu8-dwconv-6f6m7l32c16s1r-minmax-fp32-avx512skx-mul32.c", |
| "src/qu8-dwconv/gen/qu8-dwconv-8f8m9l16c16s1r-minmax-fp32-avx512skx-mul32.c", |
| "src/qu8-dwconv/gen/qu8-dwconv-8f8m9l32c16s1r-minmax-fp32-avx512skx-mul32.c", |
| "src/qu8-dwconv/gen/qu8-dwconv-9p16c-minmax-fp32-avx512skx-mul32.c", |
| "src/qu8-dwconv/gen/qu8-dwconv-9p32c-minmax-fp32-avx512skx-mul32.c", |
| "src/qu8-dwconv/gen/qu8-dwconv-25p16c-minmax-fp32-avx512skx-mul32.c", |
| "src/qu8-dwconv/gen/qu8-dwconv-25p32c-minmax-fp32-avx512skx-mul32.c", |
| "src/qu8-f32-vcvt/gen/qu8-f32-vcvt-avx512skx-u16.c", |
| "src/qu8-f32-vcvt/gen/qu8-f32-vcvt-avx512skx-u32.c", |
| "src/qu8-f32-vcvt/gen/qu8-f32-vcvt-avx512skx-u48.c", |
| "src/qu8-f32-vcvt/gen/qu8-f32-vcvt-avx512skx-u64.c", |
| "src/qu8-gemm/gen/qu8-gemm-1x16c8-minmax-fp32-avx512skx.c", |
| "src/qu8-gemm/gen/qu8-gemm-2x16c8-minmax-fp32-avx512skx.c", |
| "src/qu8-gemm/gen/qu8-gemm-3x16c8-minmax-fp32-avx512skx.c", |
| "src/qu8-gemm/gen/qu8-gemm-4x16c8-minmax-fp32-avx512skx.c", |
| "src/qu8-igemm/gen/qu8-igemm-1x16c8-minmax-fp32-avx512skx.c", |
| "src/qu8-igemm/gen/qu8-igemm-2x16c8-minmax-fp32-avx512skx.c", |
| "src/qu8-igemm/gen/qu8-igemm-3x16c8-minmax-fp32-avx512skx.c", |
| "src/qu8-igemm/gen/qu8-igemm-4x16c8-minmax-fp32-avx512skx.c", |
| "src/qu8-vadd/gen/qu8-vadd-minmax-avx512skx-mul32-ld128-u16.c", |
| "src/qu8-vadd/gen/qu8-vadd-minmax-avx512skx-mul32-ld128-u32.c", |
| "src/qu8-vaddc/gen/qu8-vaddc-minmax-avx512skx-mul32-ld128-u16.c", |
| "src/qu8-vaddc/gen/qu8-vaddc-minmax-avx512skx-mul32-ld128-u32.c", |
| "src/x8-lut/gen/x8-lut-avx512skx-vpshufb-u64.c", |
| "src/x8-lut/gen/x8-lut-avx512skx-vpshufb-u128.c", |
| "src/x8-lut/gen/x8-lut-avx512skx-vpshufb-u192.c", |
| "src/x8-lut/gen/x8-lut-avx512skx-vpshufb-u256.c", |
| ] |
| |
| ALL_AVX512VBMI_MICROKERNEL_SRCS = [ |
| "src/x8-lut/gen/x8-lut-avx512vbmi-vpermx2b-u64.c", |
| "src/x8-lut/gen/x8-lut-avx512vbmi-vpermx2b-u128.c", |
| "src/x8-lut/gen/x8-lut-avx512vbmi-vpermx2b-u192.c", |
| "src/x8-lut/gen/x8-lut-avx512vbmi-vpermx2b-u256.c", |
| ] |
| |
| ALL_F16C_MICROKERNEL_SRCS = [ |
| "src/f16-avgpool/f16-avgpool-9p8x-minmax-f16c-c8.c", |
| "src/f16-avgpool/f16-avgpool-9x-minmax-f16c-c8.c", |
| "src/f16-f32-vcvt/gen/f16-f32-vcvt-f16c-u8.c", |
| "src/f16-f32-vcvt/gen/f16-f32-vcvt-f16c-u16.c", |
| "src/f16-f32acc-rsum/gen/f16-f32acc-rsum-f16c-u8.c", |
| "src/f16-f32acc-rsum/gen/f16-f32acc-rsum-f16c-u16-acc2.c", |
| "src/f16-f32acc-rsum/gen/f16-f32acc-rsum-f16c-u24-acc3.c", |
| "src/f16-f32acc-rsum/gen/f16-f32acc-rsum-f16c-u32-acc2.c", |
| "src/f16-f32acc-rsum/gen/f16-f32acc-rsum-f16c-u32-acc4.c", |
| "src/f16-gavgpool/gen/f16-gavgpool-7p7x-minmax-f16c-c8.c", |
| "src/f16-gavgpool/gen/f16-gavgpool-7p7x-minmax-f16c-c16.c", |
| "src/f16-gavgpool/gen/f16-gavgpool-7p7x-minmax-f16c-c24.c", |
| "src/f16-gavgpool/gen/f16-gavgpool-7p7x-minmax-f16c-c32.c", |
| "src/f16-gavgpool/gen/f16-gavgpool-7x-minmax-f16c-c8.c", |
| "src/f16-gavgpool/gen/f16-gavgpool-7x-minmax-f16c-c16.c", |
| "src/f16-gavgpool/gen/f16-gavgpool-7x-minmax-f16c-c24.c", |
| "src/f16-gavgpool/gen/f16-gavgpool-7x-minmax-f16c-c32.c", |
| "src/f16-maxpool/f16-maxpool-9p8x-minmax-f16c-c8.c", |
| "src/f16-prelu/gen/f16-prelu-f16c-2x8.c", |
| "src/f16-prelu/gen/f16-prelu-f16c-2x16.c", |
| "src/f16-rmax/f16-rmax-f16c.c", |
| "src/f16-vbinary/gen/f16-vadd-minmax-f16c-u8.c", |
| "src/f16-vbinary/gen/f16-vadd-minmax-f16c-u16.c", |
| "src/f16-vbinary/gen/f16-vaddc-minmax-f16c-u8.c", |
| "src/f16-vbinary/gen/f16-vaddc-minmax-f16c-u16.c", |
| "src/f16-vbinary/gen/f16-vdiv-minmax-f16c-u8.c", |
| "src/f16-vbinary/gen/f16-vdiv-minmax-f16c-u16.c", |
| "src/f16-vbinary/gen/f16-vdivc-minmax-f16c-u8.c", |
| "src/f16-vbinary/gen/f16-vdivc-minmax-f16c-u16.c", |
| "src/f16-vbinary/gen/f16-vmax-f16c-u8.c", |
| "src/f16-vbinary/gen/f16-vmax-f16c-u16.c", |
| "src/f16-vbinary/gen/f16-vmaxc-f16c-u8.c", |
| "src/f16-vbinary/gen/f16-vmaxc-f16c-u16.c", |
| "src/f16-vbinary/gen/f16-vmin-f16c-u8.c", |
| "src/f16-vbinary/gen/f16-vmin-f16c-u16.c", |
| "src/f16-vbinary/gen/f16-vminc-f16c-u8.c", |
| "src/f16-vbinary/gen/f16-vminc-f16c-u16.c", |
| "src/f16-vbinary/gen/f16-vmul-minmax-f16c-u8.c", |
| "src/f16-vbinary/gen/f16-vmul-minmax-f16c-u16.c", |
| "src/f16-vbinary/gen/f16-vmulc-minmax-f16c-u8.c", |
| "src/f16-vbinary/gen/f16-vmulc-minmax-f16c-u16.c", |
| "src/f16-vbinary/gen/f16-vrdivc-minmax-f16c-u8.c", |
| "src/f16-vbinary/gen/f16-vrdivc-minmax-f16c-u16.c", |
| "src/f16-vbinary/gen/f16-vrsubc-minmax-f16c-u8.c", |
| "src/f16-vbinary/gen/f16-vrsubc-minmax-f16c-u16.c", |
| "src/f16-vbinary/gen/f16-vsqrdiff-f16c-u8.c", |
| "src/f16-vbinary/gen/f16-vsqrdiff-f16c-u16.c", |
| "src/f16-vbinary/gen/f16-vsqrdiffc-f16c-u8.c", |
| "src/f16-vbinary/gen/f16-vsqrdiffc-f16c-u16.c", |
| "src/f16-vbinary/gen/f16-vsub-minmax-f16c-u8.c", |
| "src/f16-vbinary/gen/f16-vsub-minmax-f16c-u16.c", |
| "src/f16-vbinary/gen/f16-vsubc-minmax-f16c-u8.c", |
| "src/f16-vbinary/gen/f16-vsubc-minmax-f16c-u16.c", |
| "src/f16-vclamp/gen/f16-vclamp-f16c-u8.c", |
| "src/f16-vclamp/gen/f16-vclamp-f16c-u16.c", |
| "src/f16-vhswish/gen/f16-vhswish-f16c-u8.c", |
| "src/f16-vhswish/gen/f16-vhswish-f16c-u16.c", |
| "src/f16-vlrelu/gen/f16-vlrelu-f16c-u8.c", |
| "src/f16-vlrelu/gen/f16-vlrelu-f16c-u16.c", |
| "src/f16-vrnd/gen/f16-vrndd-f16c-u8.c", |
| "src/f16-vrnd/gen/f16-vrndd-f16c-u16.c", |
| "src/f16-vrnd/gen/f16-vrndne-f16c-u8.c", |
| "src/f16-vrnd/gen/f16-vrndne-f16c-u16.c", |
| "src/f16-vrnd/gen/f16-vrndu-f16c-u8.c", |
| "src/f16-vrnd/gen/f16-vrndu-f16c-u16.c", |
| "src/f16-vrnd/gen/f16-vrndz-f16c-u8.c", |
| "src/f16-vrnd/gen/f16-vrndz-f16c-u16.c", |
| "src/f16-vsqrt/gen/f16-vsqrt-f16c-sqrt-u8.c", |
| "src/f16-vsqrt/gen/f16-vsqrt-f16c-sqrt-u16.c", |
| "src/f16-vtanh/gen/f16-vtanh-f16c-expm1minus-rr1-p3h2ts-div-u8.c", |
| "src/f16-vtanh/gen/f16-vtanh-f16c-expm1minus-rr1-p3h2ts-div-u16.c", |
| "src/f16-vtanh/gen/f16-vtanh-f16c-expm1minus-rr1-p3h2ts-div-u24.c", |
| "src/f16-vtanh/gen/f16-vtanh-f16c-expm1minus-rr1-p3h2ts-div-u32.c", |
| "src/f16-vtanh/gen/f16-vtanh-f16c-expm1minus-rr1-p3h2ts-div-u40.c", |
| "src/f16-vtanh/gen/f16-vtanh-f16c-expm1minus-rr1-p3h2ts-div-u48.c", |
| "src/f16-vtanh/gen/f16-vtanh-f16c-expm1minus-rr1-p3h2ts-div-u56.c", |
| "src/f16-vtanh/gen/f16-vtanh-f16c-expm1minus-rr1-p3h2ts-div-u64.c", |
| "src/f16-vtanh/gen/f16-vtanh-f16c-expm1minus-rr1-p3h2ts-div-u72.c", |
| "src/f16-vtanh/gen/f16-vtanh-f16c-expm1minus-rr1-p3h2ts-div-u80.c", |
| "src/f16-vtanh/gen/f16-vtanh-f16c-expm1minus-rr1-p3h2ts-rcp-u8.c", |
| "src/f16-vtanh/gen/f16-vtanh-f16c-expm1minus-rr1-p3h2ts-rcp-u16.c", |
| "src/f16-vtanh/gen/f16-vtanh-f16c-expm1minus-rr1-p3h2ts-rcp-u24.c", |
| "src/f16-vtanh/gen/f16-vtanh-f16c-expm1minus-rr1-p3h2ts-rcp-u32.c", |
| "src/f16-vtanh/gen/f16-vtanh-f16c-expm1minus-rr1-p3h2ts-rcp-u40.c", |
| "src/f16-vtanh/gen/f16-vtanh-f16c-expm1minus-rr1-p3h2ts-rcp-u48.c", |
| "src/f16-vtanh/gen/f16-vtanh-f16c-expm1minus-rr1-p3h2ts-rcp-u56.c", |
| "src/f16-vtanh/gen/f16-vtanh-f16c-expm1minus-rr1-p3h2ts-rcp-u64.c", |
| "src/f16-vtanh/gen/f16-vtanh-f16c-expm1minus-rr1-p3h2ts-rcp-u72.c", |
| "src/f16-vtanh/gen/f16-vtanh-f16c-expm1minus-rr1-p3h2ts-rcp-u80.c", |
| "src/f16-vtanh/gen/f16-vtanh-f16c-polynomial-p19h9t2-u8.c", |
| "src/f16-vtanh/gen/f16-vtanh-f16c-polynomial-p19h9t2-u16.c", |
| "src/f16-vtanh/gen/f16-vtanh-f16c-polynomial-p19h9t2-u24.c", |
| "src/f16-vtanh/gen/f16-vtanh-f16c-polynomial-p19h9t2-u32.c", |
| "src/f16-vtanh/gen/f16-vtanh-f16c-polynomial-p19h9t2-u40.c", |
| "src/f16-vtanh/gen/f16-vtanh-f16c-polynomial-p19h9t2-u48.c", |
| "src/f16-vtanh/gen/f16-vtanh-f16c-polynomial-p19h9t2-u56.c", |
| "src/f16-vtanh/gen/f16-vtanh-f16c-polynomial-p19h9t2-u64.c", |
| "src/f16-vtanh/gen/f16-vtanh-f16c-polynomial-p19h9t2-u72.c", |
| "src/f16-vtanh/gen/f16-vtanh-f16c-polynomial-p19h9t2-u80.c", |
| "src/f16-vunary/gen/f16-vsqr-f16c-u8.c", |
| "src/f16-vunary/gen/f16-vsqr-f16c-u16.c", |
| "src/f32-f16-vcvt/gen/f32-f16-vcvt-f16c-u8.c", |
| "src/f32-f16-vcvt/gen/f32-f16-vcvt-f16c-u16.c", |
| "src/math/f16-f32-cvt-f16c.c", |
| "src/math/f32-f16-cvt-f16c.c", |
| "src/math/gen/f16-tanh-f16c-expm1minus-rr1-p3h2ts-div.c", |
| "src/math/gen/f16-tanh-f16c-expm1minus-rr1-p3h2ts-rcp.c", |
| "src/math/gen/f16-tanh-f16c-polynomial-p17h8t2.c", |
| "src/math/gen/f16-tanh-f16c-polynomial-p19h9t2.c", |
| ] |
| |
| ALL_FMA_MICROKERNEL_SRCS = [ |
| "src/f32-vtanh/gen/f32-vtanh-fma-expm1minus-rr1-lut8-p4h3ts-div-u1.c", |
| "src/f32-vtanh/gen/f32-vtanh-fma-expm1minus-rr1-lut8-p4h3ts-div-u2.c", |
| "src/f32-vtanh/gen/f32-vtanh-fma-expm1minus-rr1-lut8-p4h3ts-div-u4.c", |
| "src/f32-vtanh/gen/f32-vtanh-fma-expm1minus-rr1-p6h5ts-div-u1.c", |
| "src/f32-vtanh/gen/f32-vtanh-fma-expm1minus-rr1-p6h5ts-div-u2.c", |
| "src/f32-vtanh/gen/f32-vtanh-fma-expm1minus-rr1-p6h5ts-div-u4.c", |
| "src/math/gen/f32-tanh-fma-expm1minus-rr1-lut4-p4h2ts-div.c", |
| "src/math/gen/f32-tanh-fma-expm1minus-rr1-lut4-p4h2ts-rcp.c", |
| "src/math/gen/f32-tanh-fma-expm1minus-rr1-lut4-p4h3ps-div.c", |
| "src/math/gen/f32-tanh-fma-expm1minus-rr1-lut4-p4h3ps-rcp.c", |
| "src/math/gen/f32-tanh-fma-expm1minus-rr1-lut4-p4h3ts-div.c", |
| "src/math/gen/f32-tanh-fma-expm1minus-rr1-lut4-p4h3ts-rcp.c", |
| "src/math/gen/f32-tanh-fma-expm1minus-rr1-lut8-p3h1ts-div.c", |
| "src/math/gen/f32-tanh-fma-expm1minus-rr1-lut8-p4h2ts-div.c", |
| "src/math/gen/f32-tanh-fma-expm1minus-rr1-lut8-p4h2ts-rcp.c", |
| "src/math/gen/f32-tanh-fma-expm1minus-rr1-lut8-p4h3ps-div.c", |
| "src/math/gen/f32-tanh-fma-expm1minus-rr1-lut8-p4h3ps-rcp.c", |
| "src/math/gen/f32-tanh-fma-expm1minus-rr1-lut8-p4h3ts-div.c", |
| "src/math/gen/f32-tanh-fma-expm1minus-rr1-lut8-p4h3ts-rcp.c", |
| "src/math/gen/f32-tanh-fma-expm1minus-rr1-lut16-p3h1ts-div.c", |
| "src/math/gen/f32-tanh-fma-expm1minus-rr1-lut16-p4h2ts-div.c", |
| "src/math/gen/f32-tanh-fma-expm1minus-rr1-lut16-p4h2ts-rcp.c", |
| "src/math/gen/f32-tanh-fma-expm1minus-rr1-lut16-p4h3ps-div.c", |
| "src/math/gen/f32-tanh-fma-expm1minus-rr1-lut16-p4h3ts-div.c", |
| "src/math/gen/f32-tanh-fma-expm1minus-rr1-lut32-p3h1ts-div.c", |
| "src/math/gen/f32-tanh-fma-expm1minus-rr1-lut64-p3h1ts-div.c", |
| "src/math/gen/f32-tanh-fma-expm1minus-rr1-p6h4ts-div.c", |
| "src/math/gen/f32-tanh-fma-expm1minus-rr1-p6h5ps-div.c", |
| "src/math/gen/f32-tanh-fma-expm1minus-rr1-p6h5ps-rcp.c", |
| "src/math/gen/f32-tanh-fma-expm1minus-rr1-p6h5ts-div.c", |
| "src/math/gen/f32-tanh-fma-expm1minus-rr1-p6h5ts-rcp.c", |
| "src/math/gen/f32-tanh-fma-expm1minus-rr2-lut4-p4h2ts-div.c", |
| "src/math/gen/f32-tanh-fma-expm1minus-rr2-lut4-p4h3ps-div.c", |
| "src/math/gen/f32-tanh-fma-expm1minus-rr2-lut4-p4h3ts-div.c", |
| "src/math/gen/f32-tanh-fma-expm1minus-rr2-lut8-p3h1ts-div.c", |
| "src/math/gen/f32-tanh-fma-expm1minus-rr2-lut8-p4h2ts-div.c", |
| "src/math/gen/f32-tanh-fma-expm1minus-rr2-lut8-p4h2ts-rcp.c", |
| "src/math/gen/f32-tanh-fma-expm1minus-rr2-lut8-p4h3ps-div.c", |
| "src/math/gen/f32-tanh-fma-expm1minus-rr2-lut8-p4h3ts-div.c", |
| "src/math/gen/f32-tanh-fma-expm1minus-rr2-lut16-p3h1ts-div.c", |
| "src/math/gen/f32-tanh-fma-expm1minus-rr2-lut16-p4h2ts-div.c", |
| "src/math/gen/f32-tanh-fma-expm1minus-rr2-lut16-p4h3ps-div.c", |
| "src/math/gen/f32-tanh-fma-expm1minus-rr2-lut16-p4h3ts-div.c", |
| "src/math/gen/f32-tanh-fma-expm1minus-rr2-lut32-p3h1ts-div.c", |
| "src/math/gen/f32-tanh-fma-expm1minus-rr2-lut64-p3h1ts-div.c", |
| "src/math/gen/f32-tanh-fma-expm1minus-rr2-p6h4ts-div.c", |
| "src/math/gen/f32-tanh-fma-expm1minus-rr2-p6h5ps-div.c", |
| "src/math/gen/f32-tanh-fma-expm1minus-rr2-p6h5ts-div.c", |
| "src/math/gen/f32-tanh-fma-expm1plus-rr1-lut4-p4h2ts-div.c", |
| "src/math/gen/f32-tanh-fma-expm1plus-rr1-lut4-p4h3ps-div.c", |
| "src/math/gen/f32-tanh-fma-expm1plus-rr1-lut4-p4h3ts-div.c", |
| "src/math/gen/f32-tanh-fma-expm1plus-rr1-lut8-p3h1ts-div.c", |
| "src/math/gen/f32-tanh-fma-expm1plus-rr1-lut8-p4h2ts-div.c", |
| "src/math/gen/f32-tanh-fma-expm1plus-rr1-lut8-p4h3ps-div.c", |
| "src/math/gen/f32-tanh-fma-expm1plus-rr1-lut8-p4h3ts-div.c", |
| "src/math/gen/f32-tanh-fma-expm1plus-rr1-lut16-p3h1ts-div.c", |
| "src/math/gen/f32-tanh-fma-expm1plus-rr1-lut16-p4h2ts-div.c", |
| "src/math/gen/f32-tanh-fma-expm1plus-rr1-lut16-p4h3ps-div.c", |
| "src/math/gen/f32-tanh-fma-expm1plus-rr1-lut16-p4h3ts-div.c", |
| "src/math/gen/f32-tanh-fma-expm1plus-rr1-lut32-p3h1ts-div.c", |
| "src/math/gen/f32-tanh-fma-expm1plus-rr1-lut64-p3h1ts-div.c", |
| "src/math/gen/f32-tanh-fma-expm1plus-rr1-p6h4ts-div.c", |
| "src/math/gen/f32-tanh-fma-expm1plus-rr1-p6h5ps-div.c", |
| "src/math/gen/f32-tanh-fma-expm1plus-rr1-p6h5ts-div.c", |
| "src/math/gen/f32-tanh-fma-expm1plus-rr2-lut4-p4h2ts-div.c", |
| "src/math/gen/f32-tanh-fma-expm1plus-rr2-lut4-p4h3ps-div.c", |
| "src/math/gen/f32-tanh-fma-expm1plus-rr2-lut4-p4h3ts-div.c", |
| "src/math/gen/f32-tanh-fma-expm1plus-rr2-lut8-p3h1ts-div.c", |
| "src/math/gen/f32-tanh-fma-expm1plus-rr2-lut8-p4h2ts-div.c", |
| "src/math/gen/f32-tanh-fma-expm1plus-rr2-lut8-p4h3ps-div.c", |
| "src/math/gen/f32-tanh-fma-expm1plus-rr2-lut8-p4h3ts-div.c", |
| "src/math/gen/f32-tanh-fma-expm1plus-rr2-lut16-p3h1ts-div.c", |
| "src/math/gen/f32-tanh-fma-expm1plus-rr2-lut16-p4h2ts-div.c", |
| "src/math/gen/f32-tanh-fma-expm1plus-rr2-lut16-p4h3ps-div.c", |
| "src/math/gen/f32-tanh-fma-expm1plus-rr2-lut16-p4h3ts-div.c", |
| "src/math/gen/f32-tanh-fma-expm1plus-rr2-lut32-p3h1ts-div.c", |
| "src/math/gen/f32-tanh-fma-expm1plus-rr2-lut64-p3h1ts-div.c", |
| "src/math/gen/f32-tanh-fma-expm1plus-rr2-p6h4ts-div.c", |
| "src/math/gen/f32-tanh-fma-expm1plus-rr2-p6h5ps-div.c", |
| "src/math/gen/f32-tanh-fma-expm1plus-rr2-p6h5ts-div.c", |
| ] |
| |
| ALL_FMA3_MICROKERNEL_SRCS = [ |
| "src/f16-dwconv/gen/f16-dwconv-3p8c-minmax-fma3-acc2.c", |
| "src/f16-dwconv/gen/f16-dwconv-3p8c-minmax-fma3.c", |
| "src/f16-dwconv/gen/f16-dwconv-3p16c-minmax-fma3-acc2.c", |
| "src/f16-dwconv/gen/f16-dwconv-3p16c-minmax-fma3.c", |
| "src/f16-dwconv/gen/f16-dwconv-3p32c-minmax-fma3-acc2.c", |
| "src/f16-dwconv/gen/f16-dwconv-3p32c-minmax-fma3.c", |
| "src/f16-dwconv/gen/f16-dwconv-4p8c-minmax-fma3-acc2.c", |
| "src/f16-dwconv/gen/f16-dwconv-4p8c-minmax-fma3.c", |
| "src/f16-dwconv/gen/f16-dwconv-4p16c-minmax-fma3-acc2.c", |
| "src/f16-dwconv/gen/f16-dwconv-4p16c-minmax-fma3.c", |
| "src/f16-dwconv/gen/f16-dwconv-4p32c-minmax-fma3-acc2.c", |
| "src/f16-dwconv/gen/f16-dwconv-4p32c-minmax-fma3.c", |
| "src/f16-dwconv/gen/f16-dwconv-5f5m5l8c8s4r-minmax-fma3-acc2.c", |
| "src/f16-dwconv/gen/f16-dwconv-5f5m5l8c8s4r-minmax-fma3.c", |
| "src/f16-dwconv/gen/f16-dwconv-5f5m5l16c8s4r-minmax-fma3-acc2.c", |
| "src/f16-dwconv/gen/f16-dwconv-5f5m5l16c8s4r-minmax-fma3.c", |
| "src/f16-dwconv/gen/f16-dwconv-5f5m5l32c8s4r-minmax-fma3-acc2.c", |
| "src/f16-dwconv/gen/f16-dwconv-5f5m5l32c8s4r-minmax-fma3.c", |
| "src/f16-dwconv/gen/f16-dwconv-6f6m7l8c8s4r-minmax-fma3-acc2.c", |
| "src/f16-dwconv/gen/f16-dwconv-6f6m7l8c8s4r-minmax-fma3.c", |
| "src/f16-dwconv/gen/f16-dwconv-6f6m7l16c8s4r-minmax-fma3-acc2.c", |
| "src/f16-dwconv/gen/f16-dwconv-6f6m7l16c8s4r-minmax-fma3.c", |
| "src/f16-dwconv/gen/f16-dwconv-6f6m7l32c8s4r-minmax-fma3-acc2.c", |
| "src/f16-dwconv/gen/f16-dwconv-6f6m7l32c8s4r-minmax-fma3.c", |
| "src/f16-dwconv/gen/f16-dwconv-8f8m9l8c8s4r-minmax-fma3-acc2.c", |
| "src/f16-dwconv/gen/f16-dwconv-8f8m9l8c8s4r-minmax-fma3.c", |
| "src/f16-dwconv/gen/f16-dwconv-8f8m9l16c8s4r-minmax-fma3-acc2.c", |
| "src/f16-dwconv/gen/f16-dwconv-8f8m9l16c8s4r-minmax-fma3.c", |
| "src/f16-dwconv/gen/f16-dwconv-8f8m9l32c8s4r-minmax-fma3-acc2.c", |
| "src/f16-dwconv/gen/f16-dwconv-8f8m9l32c8s4r-minmax-fma3.c", |
| "src/f16-dwconv/gen/f16-dwconv-9p8c-minmax-fma3-acc2.c", |
| "src/f16-dwconv/gen/f16-dwconv-9p8c-minmax-fma3.c", |
| "src/f16-dwconv/gen/f16-dwconv-9p16c-minmax-fma3-acc2.c", |
| "src/f16-dwconv/gen/f16-dwconv-9p16c-minmax-fma3.c", |
| "src/f16-dwconv/gen/f16-dwconv-9p32c-minmax-fma3-acc2.c", |
| "src/f16-dwconv/gen/f16-dwconv-9p32c-minmax-fma3.c", |
| "src/f16-dwconv/gen/f16-dwconv-25p8c-minmax-fma3-acc2.c", |
| "src/f16-dwconv/gen/f16-dwconv-25p8c-minmax-fma3.c", |
| "src/f16-dwconv/gen/f16-dwconv-25p16c-minmax-fma3-acc2.c", |
| "src/f16-dwconv/gen/f16-dwconv-25p16c-minmax-fma3.c", |
| "src/f16-dwconv/gen/f16-dwconv-25p32c-minmax-fma3-acc2.c", |
| "src/f16-dwconv/gen/f16-dwconv-25p32c-minmax-fma3.c", |
| "src/f16-ibilinear/gen/f16-ibilinear-fma3-c8.c", |
| "src/f16-ibilinear/gen/f16-ibilinear-fma3-c16.c", |
| "src/f16-vmulcaddc/gen/f16-vmulcaddc-c8-minmax-fma3-2x.c", |
| "src/f16-vmulcaddc/gen/f16-vmulcaddc-c16-minmax-fma3-2x.c", |
| "src/f16-vtanh/gen/f16-vtanh-fma3-expm1minus-rr1-p3h2ts-div-u8.c", |
| "src/f16-vtanh/gen/f16-vtanh-fma3-expm1minus-rr1-p3h2ts-div-u16.c", |
| "src/f16-vtanh/gen/f16-vtanh-fma3-expm1minus-rr1-p3h2ts-div-u24.c", |
| "src/f16-vtanh/gen/f16-vtanh-fma3-expm1minus-rr1-p3h2ts-div-u32.c", |
| "src/f16-vtanh/gen/f16-vtanh-fma3-expm1minus-rr1-p3h2ts-div-u40.c", |
| "src/f16-vtanh/gen/f16-vtanh-fma3-expm1minus-rr1-p3h2ts-div-u48.c", |
| "src/f16-vtanh/gen/f16-vtanh-fma3-expm1minus-rr1-p3h2ts-div-u56.c", |
| "src/f16-vtanh/gen/f16-vtanh-fma3-expm1minus-rr1-p3h2ts-div-u64.c", |
| "src/f16-vtanh/gen/f16-vtanh-fma3-expm1minus-rr1-p3h2ts-div-u72.c", |
| "src/f16-vtanh/gen/f16-vtanh-fma3-expm1minus-rr1-p3h2ts-div-u80.c", |
| "src/f16-vtanh/gen/f16-vtanh-fma3-expm1minus-rr1-p3h2ts-rcp-u8.c", |
| "src/f16-vtanh/gen/f16-vtanh-fma3-expm1minus-rr1-p3h2ts-rcp-u16.c", |
| "src/f16-vtanh/gen/f16-vtanh-fma3-expm1minus-rr1-p3h2ts-rcp-u24.c", |
| "src/f16-vtanh/gen/f16-vtanh-fma3-expm1minus-rr1-p3h2ts-rcp-u32.c", |
| "src/f16-vtanh/gen/f16-vtanh-fma3-expm1minus-rr1-p3h2ts-rcp-u40.c", |
| "src/f16-vtanh/gen/f16-vtanh-fma3-expm1minus-rr1-p3h2ts-rcp-u48.c", |
| "src/f16-vtanh/gen/f16-vtanh-fma3-expm1minus-rr1-p3h2ts-rcp-u56.c", |
| "src/f16-vtanh/gen/f16-vtanh-fma3-expm1minus-rr1-p3h2ts-rcp-u64.c", |
| "src/f16-vtanh/gen/f16-vtanh-fma3-expm1minus-rr1-p3h2ts-rcp-u72.c", |
| "src/f16-vtanh/gen/f16-vtanh-fma3-expm1minus-rr1-p3h2ts-rcp-u80.c", |
| "src/f16-vtanh/gen/f16-vtanh-fma3-polynomial-p19h9t2-u8.c", |
| "src/f16-vtanh/gen/f16-vtanh-fma3-polynomial-p19h9t2-u16.c", |
| "src/f16-vtanh/gen/f16-vtanh-fma3-polynomial-p19h9t2-u24.c", |
| "src/f16-vtanh/gen/f16-vtanh-fma3-polynomial-p19h9t2-u32.c", |
| "src/f16-vtanh/gen/f16-vtanh-fma3-polynomial-p19h9t2-u40.c", |
| "src/f16-vtanh/gen/f16-vtanh-fma3-polynomial-p19h9t2-u48.c", |
| "src/f16-vtanh/gen/f16-vtanh-fma3-polynomial-p19h9t2-u56.c", |
| "src/f16-vtanh/gen/f16-vtanh-fma3-polynomial-p19h9t2-u64.c", |
| "src/f16-vtanh/gen/f16-vtanh-fma3-polynomial-p19h9t2-u72.c", |
| "src/f16-vtanh/gen/f16-vtanh-fma3-polynomial-p19h9t2-u80.c", |
| "src/f32-dwconv/gen/f32-dwconv-3p8c-minmax-fma3-acc2.c", |
| "src/f32-dwconv/gen/f32-dwconv-3p8c-minmax-fma3.c", |
| "src/f32-dwconv/gen/f32-dwconv-3p16c-minmax-fma3-acc2.c", |
| "src/f32-dwconv/gen/f32-dwconv-3p16c-minmax-fma3.c", |
| "src/f32-dwconv/gen/f32-dwconv-4p8c-minmax-fma3-acc2.c", |
| "src/f32-dwconv/gen/f32-dwconv-4p8c-minmax-fma3.c", |
| "src/f32-dwconv/gen/f32-dwconv-4p16c-minmax-fma3-acc2.c", |
| "src/f32-dwconv/gen/f32-dwconv-4p16c-minmax-fma3.c", |
| "src/f32-dwconv/gen/f32-dwconv-5f5m5l8c8s4r-minmax-fma3-acc2.c", |
| "src/f32-dwconv/gen/f32-dwconv-5f5m5l8c8s4r-minmax-fma3.c", |
| "src/f32-dwconv/gen/f32-dwconv-5f5m5l16c8s4r-minmax-fma3-acc2.c", |
| "src/f32-dwconv/gen/f32-dwconv-5f5m5l16c8s4r-minmax-fma3.c", |
| "src/f32-dwconv/gen/f32-dwconv-5f5m5l32c8s4r-minmax-fma3-acc2.c", |
| "src/f32-dwconv/gen/f32-dwconv-5f5m5l32c8s4r-minmax-fma3.c", |
| "src/f32-dwconv/gen/f32-dwconv-7f6m6l8c8s4r-minmax-fma3-acc2.c", |
| "src/f32-dwconv/gen/f32-dwconv-7f6m6l8c8s4r-minmax-fma3.c", |
| "src/f32-dwconv/gen/f32-dwconv-7f6m6l16c8s4r-minmax-fma3-acc2.c", |
| "src/f32-dwconv/gen/f32-dwconv-7f6m6l16c8s4r-minmax-fma3.c", |
| "src/f32-dwconv/gen/f32-dwconv-7f6m6l32c8s4r-minmax-fma3-acc2.c", |
| "src/f32-dwconv/gen/f32-dwconv-7f6m6l32c8s4r-minmax-fma3.c", |
| "src/f32-dwconv/gen/f32-dwconv-9p8c-minmax-fma3-acc2.c", |
| "src/f32-dwconv/gen/f32-dwconv-9p8c-minmax-fma3.c", |
| "src/f32-dwconv/gen/f32-dwconv-9p16c-minmax-fma3-acc2.c", |
| "src/f32-dwconv/gen/f32-dwconv-9p16c-minmax-fma3.c", |
| "src/f32-dwconv/gen/f32-dwconv-25p8c-minmax-fma3-acc2.c", |
| "src/f32-dwconv/gen/f32-dwconv-25p8c-minmax-fma3.c", |
| "src/f32-dwconv/gen/f32-dwconv-25p16c-minmax-fma3-acc2.c", |
| "src/f32-dwconv/gen/f32-dwconv-25p16c-minmax-fma3.c", |
| "src/f32-gemm/gen/f32-gemm-1x8-minmax-fma3-broadcast.c", |
| "src/f32-gemm/gen/f32-gemm-1x16-minmax-fma3-broadcast.c", |
| "src/f32-gemm/gen/f32-gemm-1x16s4-minmax-fma3-broadcast.c", |
| "src/f32-gemm/gen/f32-gemm-3x16-minmax-fma3-broadcast.c", |
| "src/f32-gemm/gen/f32-gemm-3x16s4-minmax-fma3-broadcast.c", |
| "src/f32-gemm/gen/f32-gemm-4x8-minmax-fma3-broadcast.c", |
| "src/f32-gemm/gen/f32-gemm-4x16-minmax-fma3-broadcast.c", |
| "src/f32-gemm/gen/f32-gemm-4x16s4-minmax-fma3-broadcast.c", |
| "src/f32-gemm/gen/f32-gemm-5x8-minmax-fma3-broadcast.c", |
| "src/f32-gemm/gen/f32-gemm-5x16-minmax-fma3-broadcast.c", |
| "src/f32-gemm/gen/f32-gemm-5x16s4-minmax-fma3-broadcast.c", |
| "src/f32-gemm/gen/f32-gemm-6x8-minmax-fma3-broadcast.c", |
| "src/f32-gemm/gen/f32-gemm-6x16-minmax-fma3-broadcast.c", |
| "src/f32-gemm/gen/f32-gemm-6x16s4-minmax-fma3-broadcast.c", |
| "src/f32-gemm/gen/f32-gemm-7x8-minmax-fma3-broadcast.c", |
| "src/f32-gemm/gen/f32-gemm-8x8-minmax-fma3-broadcast.c", |
| "src/f32-gemminc/gen/f32-gemminc-1x8-minmax-fma3-broadcast.c", |
| "src/f32-gemminc/gen/f32-gemminc-1x16-minmax-fma3-broadcast.c", |
| "src/f32-gemminc/gen/f32-gemminc-1x16s4-minmax-fma3-broadcast.c", |
| "src/f32-gemminc/gen/f32-gemminc-3x16-minmax-fma3-broadcast.c", |
| "src/f32-gemminc/gen/f32-gemminc-3x16s4-minmax-fma3-broadcast.c", |
| "src/f32-gemminc/gen/f32-gemminc-4x8-minmax-fma3-broadcast.c", |
| "src/f32-gemminc/gen/f32-gemminc-4x16-minmax-fma3-broadcast.c", |
| "src/f32-gemminc/gen/f32-gemminc-4x16s4-minmax-fma3-broadcast.c", |
| "src/f32-gemminc/gen/f32-gemminc-5x8-minmax-fma3-broadcast.c", |
| "src/f32-gemminc/gen/f32-gemminc-5x16-minmax-fma3-broadcast.c", |
| "src/f32-gemminc/gen/f32-gemminc-5x16s4-minmax-fma3-broadcast.c", |
| "src/f32-gemminc/gen/f32-gemminc-6x8-minmax-fma3-broadcast.c", |
| "src/f32-gemminc/gen/f32-gemminc-6x16-minmax-fma3-broadcast.c", |
| "src/f32-gemminc/gen/f32-gemminc-6x16s4-minmax-fma3-broadcast.c", |
| "src/f32-gemminc/gen/f32-gemminc-7x8-minmax-fma3-broadcast.c", |
| "src/f32-gemminc/gen/f32-gemminc-8x8-minmax-fma3-broadcast.c", |
| "src/f32-igemm/gen/f32-igemm-1x8-minmax-fma3-broadcast.c", |
| "src/f32-igemm/gen/f32-igemm-1x16-minmax-fma3-broadcast.c", |
| "src/f32-igemm/gen/f32-igemm-1x16s4-minmax-fma3-broadcast.c", |
| "src/f32-igemm/gen/f32-igemm-3x16-minmax-fma3-broadcast.c", |
| "src/f32-igemm/gen/f32-igemm-3x16s4-minmax-fma3-broadcast.c", |
| "src/f32-igemm/gen/f32-igemm-4x8-minmax-fma3-broadcast.c", |
| "src/f32-igemm/gen/f32-igemm-4x16-minmax-fma3-broadcast.c", |
| "src/f32-igemm/gen/f32-igemm-4x16s4-minmax-fma3-broadcast.c", |
| "src/f32-igemm/gen/f32-igemm-5x8-minmax-fma3-broadcast.c", |
| "src/f32-igemm/gen/f32-igemm-5x16-minmax-fma3-broadcast-prfm.c", |
| "src/f32-igemm/gen/f32-igemm-5x16-minmax-fma3-broadcast.c", |
| "src/f32-igemm/gen/f32-igemm-5x16s4-minmax-fma3-broadcast.c", |
| "src/f32-igemm/gen/f32-igemm-6x8-minmax-fma3-broadcast.c", |
| "src/f32-igemm/gen/f32-igemm-6x16-minmax-fma3-broadcast-prfm.c", |
| "src/f32-igemm/gen/f32-igemm-6x16-minmax-fma3-broadcast.c", |
| "src/f32-igemm/gen/f32-igemm-6x16s4-minmax-fma3-broadcast.c", |
| "src/f32-igemm/gen/f32-igemm-7x8-minmax-fma3-broadcast.c", |
| "src/f32-igemm/gen/f32-igemm-8x8-minmax-fma3-broadcast.c", |
| "src/f32-qc4w-gemm/gen/f32-qc4w-gemm-1x16-minmax-fma3-broadcast.c", |
| "src/f32-qc4w-gemm/gen/f32-qc4w-gemm-2x16-minmax-fma3-broadcast.c", |
| "src/f32-qc4w-gemm/gen/f32-qc4w-gemm-3x16-minmax-fma3-broadcast.c", |
| "src/f32-qc4w-gemm/gen/f32-qc4w-gemm-4x16-minmax-fma3-broadcast.c", |
| "src/f32-qc4w-gemm/gen/f32-qc4w-gemm-5x16-minmax-fma3-broadcast.c", |
| "src/f32-qc4w-gemm/gen/f32-qc4w-gemm-6x16-minmax-fma3-broadcast.c", |
| "src/f32-qc4w-gemm/gen/f32-qc4w-gemm-7x16-minmax-fma3-broadcast.c", |
| "src/f32-qc4w-gemm/gen/f32-qc4w-gemm-8x16-minmax-fma3-broadcast.c", |
| "src/f32-qc8w-gemm/gen/f32-qc8w-gemm-1x16-minmax-fma3-broadcast.c", |
| "src/f32-qc8w-gemm/gen/f32-qc8w-gemm-2x16-minmax-fma3-broadcast.c", |
| "src/f32-qc8w-gemm/gen/f32-qc8w-gemm-3x16-minmax-fma3-broadcast.c", |
| "src/f32-qc8w-gemm/gen/f32-qc8w-gemm-4x16-minmax-fma3-broadcast.c", |
| "src/f32-qc8w-gemm/gen/f32-qc8w-gemm-5x16-minmax-fma3-broadcast.c", |
| "src/f32-qc8w-gemm/gen/f32-qc8w-gemm-6x16-minmax-fma3-broadcast.c", |
| "src/f32-qc8w-gemm/gen/f32-qc8w-gemm-7x16-minmax-fma3-broadcast.c", |
| "src/f32-qc8w-gemm/gen/f32-qc8w-gemm-8x16-minmax-fma3-broadcast.c", |
| "src/f32-vhswish/gen/f32-vhswish-fma3-u8.c", |
| "src/f32-vhswish/gen/f32-vhswish-fma3-u16.c", |
| "src/f32-vsqrt/gen/f32-vsqrt-fma3-nr1fma1adj-u8.c", |
| "src/f32-vsqrt/gen/f32-vsqrt-fma3-nr1fma1adj-u16.c", |
| "src/f32-vsqrt/gen/f32-vsqrt-fma3-nr1fma1adj-u24.c", |
| "src/f32-vsqrt/gen/f32-vsqrt-fma3-nr1fma1adj-u32.c", |
| "src/f32-vsqrt/gen/f32-vsqrt-fma3-nr1fma1adj-u40.c", |
| "src/f32-vsqrt/gen/f32-vsqrt-fma3-nr1fma1adj-u48.c", |
| "src/f32-vsqrt/gen/f32-vsqrt-fma3-nr1fma1adj-u56.c", |
| "src/f32-vsqrt/gen/f32-vsqrt-fma3-nr1fma1adj-u64.c", |
| "src/f32-vtanh/gen/f32-vtanh-fma3-expm1minus-rr1-lut4-p4h3ts-perm-div-u8.c", |
| "src/f32-vtanh/gen/f32-vtanh-fma3-expm1minus-rr1-lut4-p4h3ts-perm-div-u16.c", |
| "src/f32-vtanh/gen/f32-vtanh-fma3-expm1minus-rr1-lut4-p4h3ts-perm-div-u24.c", |
| "src/f32-vtanh/gen/f32-vtanh-fma3-expm1minus-rr1-lut4-p4h3ts-perm-div-u32.c", |
| "src/f32-vtanh/gen/f32-vtanh-fma3-expm1minus-rr1-lut4-p4h3ts-perm-div-u40.c", |
| "src/f32-vtanh/gen/f32-vtanh-fma3-expm1minus-rr1-lut4-p4h3ts-perm-div-u48.c", |
| "src/f32-vtanh/gen/f32-vtanh-fma3-expm1minus-rr1-lut4-p4h3ts-perm-div-u56.c", |
| "src/f32-vtanh/gen/f32-vtanh-fma3-expm1minus-rr1-lut4-p4h3ts-perm-div-u64.c", |
| "src/f32-vtanh/gen/f32-vtanh-fma3-expm1minus-rr1-lut4-p4h3ts-perm-div-u72.c", |
| "src/f32-vtanh/gen/f32-vtanh-fma3-expm1minus-rr1-lut4-p4h3ts-perm-div-u80.c", |
| "src/f32-vtanh/gen/f32-vtanh-fma3-expm1minus-rr1-lut4-p4h3ts-perm-nr1adj-u8.c", |
| "src/f32-vtanh/gen/f32-vtanh-fma3-expm1minus-rr1-lut4-p4h3ts-perm-nr1adj-u16.c", |
| "src/f32-vtanh/gen/f32-vtanh-fma3-expm1minus-rr1-lut4-p4h3ts-perm-nr1adj-u24.c", |
| "src/f32-vtanh/gen/f32-vtanh-fma3-expm1minus-rr1-lut4-p4h3ts-perm-nr1adj-u32.c", |
| "src/f32-vtanh/gen/f32-vtanh-fma3-expm1minus-rr1-lut4-p4h3ts-perm-nr1adj-u40.c", |
| "src/f32-vtanh/gen/f32-vtanh-fma3-expm1minus-rr1-lut4-p4h3ts-perm-nr1adj-u48.c", |
| "src/f32-vtanh/gen/f32-vtanh-fma3-expm1minus-rr1-lut4-p4h3ts-perm-nr1adj-u56.c", |
| "src/f32-vtanh/gen/f32-vtanh-fma3-expm1minus-rr1-lut4-p4h3ts-perm-nr1adj-u64.c", |
| "src/f32-vtanh/gen/f32-vtanh-fma3-expm1minus-rr1-lut4-p4h3ts-perm-nr1adj-u72.c", |
| "src/f32-vtanh/gen/f32-vtanh-fma3-expm1minus-rr1-lut4-p4h3ts-perm-nr1adj-u80.c", |
| "src/f32-vtanh/gen/f32-vtanh-fma3-expm1minus-rr1-lut8-p4h3ts-div-u8.c", |
| "src/f32-vtanh/gen/f32-vtanh-fma3-expm1minus-rr1-lut8-p4h3ts-div-u16.c", |
| "src/f32-vtanh/gen/f32-vtanh-fma3-expm1minus-rr1-lut8-p4h3ts-div-u24.c", |
| "src/f32-vtanh/gen/f32-vtanh-fma3-expm1minus-rr1-lut8-p4h3ts-div-u32.c", |
| "src/f32-vtanh/gen/f32-vtanh-fma3-expm1minus-rr1-lut8-p4h3ts-nr1adj-u8.c", |
| "src/f32-vtanh/gen/f32-vtanh-fma3-expm1minus-rr1-lut8-p4h3ts-nr1adj-u16.c", |
| "src/f32-vtanh/gen/f32-vtanh-fma3-expm1minus-rr1-lut8-p4h3ts-nr1adj-u24.c", |
| "src/f32-vtanh/gen/f32-vtanh-fma3-expm1minus-rr1-lut8-p4h3ts-nr1adj-u32.c", |
| "src/f32-vtanh/gen/f32-vtanh-fma3-expm1minus-rr1-p6h5ts-div-u8.c", |
| "src/f32-vtanh/gen/f32-vtanh-fma3-expm1minus-rr1-p6h5ts-div-u16.c", |
| "src/f32-vtanh/gen/f32-vtanh-fma3-expm1minus-rr1-p6h5ts-div-u24.c", |
| "src/f32-vtanh/gen/f32-vtanh-fma3-expm1minus-rr1-p6h5ts-div-u32.c", |
| "src/f32-vtanh/gen/f32-vtanh-fma3-expm1minus-rr1-p6h5ts-div-u40.c", |
| "src/f32-vtanh/gen/f32-vtanh-fma3-expm1minus-rr1-p6h5ts-div-u48.c", |
| "src/f32-vtanh/gen/f32-vtanh-fma3-expm1minus-rr1-p6h5ts-div-u56.c", |
| "src/f32-vtanh/gen/f32-vtanh-fma3-expm1minus-rr1-p6h5ts-div-u64.c", |
| "src/f32-vtanh/gen/f32-vtanh-fma3-expm1minus-rr1-p6h5ts-div-u72.c", |
| "src/f32-vtanh/gen/f32-vtanh-fma3-expm1minus-rr1-p6h5ts-div-u80.c", |
| "src/f32-vtanh/gen/f32-vtanh-fma3-expm1minus-rr1-p6h5ts-nr1-u8.c", |
| "src/f32-vtanh/gen/f32-vtanh-fma3-expm1minus-rr1-p6h5ts-nr1-u16.c", |
| "src/f32-vtanh/gen/f32-vtanh-fma3-expm1minus-rr1-p6h5ts-nr1-u24.c", |
| "src/f32-vtanh/gen/f32-vtanh-fma3-expm1minus-rr1-p6h5ts-nr1-u32.c", |
| "src/f32-vtanh/gen/f32-vtanh-fma3-expm1minus-rr1-p6h5ts-nr1-u40.c", |
| "src/f32-vtanh/gen/f32-vtanh-fma3-expm1minus-rr1-p6h5ts-nr1-u48.c", |
| "src/f32-vtanh/gen/f32-vtanh-fma3-expm1minus-rr1-p6h5ts-nr1-u56.c", |
| "src/f32-vtanh/gen/f32-vtanh-fma3-expm1minus-rr1-p6h5ts-nr1-u64.c", |
| "src/f32-vtanh/gen/f32-vtanh-fma3-expm1minus-rr1-p6h5ts-nr1-u72.c", |
| "src/f32-vtanh/gen/f32-vtanh-fma3-expm1minus-rr1-p6h5ts-nr1-u80.c", |
| "src/f32-vtanh/gen/f32-vtanh-fma3-expm1minus-rr1-p6h5ts-nr1adj-u8.c", |
| "src/f32-vtanh/gen/f32-vtanh-fma3-expm1minus-rr1-p6h5ts-nr1adj-u16.c", |
| "src/f32-vtanh/gen/f32-vtanh-fma3-expm1minus-rr1-p6h5ts-nr1adj-u24.c", |
| "src/f32-vtanh/gen/f32-vtanh-fma3-expm1minus-rr1-p6h5ts-nr1adj-u32.c", |
| "src/f32-vtanh/gen/f32-vtanh-fma3-expm1minus-rr1-p6h5ts-nr1adj-u40.c", |
| "src/f32-vtanh/gen/f32-vtanh-fma3-expm1minus-rr1-p6h5ts-nr1adj-u48.c", |
| "src/f32-vtanh/gen/f32-vtanh-fma3-expm1minus-rr1-p6h5ts-nr1adj-u56.c", |
| "src/f32-vtanh/gen/f32-vtanh-fma3-expm1minus-rr1-p6h5ts-nr1adj-u64.c", |
| "src/f32-vtanh/gen/f32-vtanh-fma3-expm1minus-rr1-p6h5ts-nr1adj-u72.c", |
| "src/f32-vtanh/gen/f32-vtanh-fma3-expm1minus-rr1-p6h5ts-nr1adj-u80.c", |
| "src/math/f32-sqrt-fma3-nr1fma1adj.c", |
| "src/math/f32-sqrt-fma3-nr1fma.c", |
| "src/math/f32-sqrt-fma3-nr2fma.c", |
| "src/math/gen/f16-tanh-fma3-expm1minus-rr1-p3h2ts-div.c", |
| "src/math/gen/f16-tanh-fma3-expm1minus-rr1-p3h2ts-rcp.c", |
| "src/math/gen/f16-tanh-fma3-polynomial-p17h8t2.c", |
| "src/math/gen/f16-tanh-fma3-polynomial-p19h9t2.c", |
| "src/math/gen/f32-tanh-fma3-expm1minus-rr1-lut4-p4h3ts-perm-div.c", |
| "src/math/gen/f32-tanh-fma3-expm1minus-rr1-lut4-p4h3ts-perm-nr1adj.c", |
| "src/math/gen/f32-tanh-fma3-expm1minus-rr1-lut8-p4h3ps-div.c", |
| "src/math/gen/f32-tanh-fma3-expm1minus-rr1-lut8-p4h3ps-nr1.c", |
| "src/math/gen/f32-tanh-fma3-expm1minus-rr1-lut8-p4h3ps-nr1adj.c", |
| "src/math/gen/f32-tanh-fma3-expm1minus-rr1-p6h5ts-div.c", |
| "src/math/gen/f32-tanh-fma3-expm1minus-rr1-p6h5ts-nr1.c", |
| "src/math/gen/f32-tanh-fma3-expm1minus-rr1-p6h5ts-nr1adj.c", |
| ] |
| |
| ALL_FP16ARITH_MICROKERNEL_SRCS = [ |
| "src/f16-vbinary/gen/f16-vadd-minmax-fp16arith-u1.c", |
| "src/f16-vbinary/gen/f16-vadd-minmax-fp16arith-u2.c", |
| "src/f16-vbinary/gen/f16-vadd-minmax-fp16arith-u4.c", |
| "src/f16-vbinary/gen/f16-vaddc-minmax-fp16arith-u1.c", |
| "src/f16-vbinary/gen/f16-vaddc-minmax-fp16arith-u2.c", |
| "src/f16-vbinary/gen/f16-vaddc-minmax-fp16arith-u4.c", |
| "src/f16-vbinary/gen/f16-vdiv-minmax-fp16arith-u1.c", |
| "src/f16-vbinary/gen/f16-vdiv-minmax-fp16arith-u2.c", |
| "src/f16-vbinary/gen/f16-vdiv-minmax-fp16arith-u4.c", |
| "src/f16-vbinary/gen/f16-vdivc-minmax-fp16arith-u1.c", |
| "src/f16-vbinary/gen/f16-vdivc-minmax-fp16arith-u2.c", |
| "src/f16-vbinary/gen/f16-vdivc-minmax-fp16arith-u4.c", |
| "src/f16-vbinary/gen/f16-vmax-fp16arith-u1.c", |
| "src/f16-vbinary/gen/f16-vmax-fp16arith-u2.c", |
| "src/f16-vbinary/gen/f16-vmax-fp16arith-u4.c", |
| "src/f16-vbinary/gen/f16-vmaxc-fp16arith-u1.c", |
| "src/f16-vbinary/gen/f16-vmaxc-fp16arith-u2.c", |
| "src/f16-vbinary/gen/f16-vmaxc-fp16arith-u4.c", |
| "src/f16-vbinary/gen/f16-vmin-fp16arith-u1.c", |
| "src/f16-vbinary/gen/f16-vmin-fp16arith-u2.c", |
| "src/f16-vbinary/gen/f16-vmin-fp16arith-u4.c", |
| "src/f16-vbinary/gen/f16-vminc-fp16arith-u1.c", |
| "src/f16-vbinary/gen/f16-vminc-fp16arith-u2.c", |
| "src/f16-vbinary/gen/f16-vminc-fp16arith-u4.c", |
| "src/f16-vbinary/gen/f16-vmul-minmax-fp16arith-u1.c", |
| "src/f16-vbinary/gen/f16-vmul-minmax-fp16arith-u2.c", |
| "src/f16-vbinary/gen/f16-vmul-minmax-fp16arith-u4.c", |
| "src/f16-vbinary/gen/f16-vmulc-minmax-fp16arith-u1.c", |
| "src/f16-vbinary/gen/f16-vmulc-minmax-fp16arith-u2.c", |
| "src/f16-vbinary/gen/f16-vmulc-minmax-fp16arith-u4.c", |
| "src/f16-vbinary/gen/f16-vrdivc-minmax-fp16arith-u1.c", |
| "src/f16-vbinary/gen/f16-vrdivc-minmax-fp16arith-u2.c", |
| "src/f16-vbinary/gen/f16-vrdivc-minmax-fp16arith-u4.c", |
| "src/f16-vbinary/gen/f16-vrsubc-minmax-fp16arith-u1.c", |
| "src/f16-vbinary/gen/f16-vrsubc-minmax-fp16arith-u2.c", |
| "src/f16-vbinary/gen/f16-vrsubc-minmax-fp16arith-u4.c", |
| "src/f16-vbinary/gen/f16-vsqrdiff-fp16arith-u1.c", |
| "src/f16-vbinary/gen/f16-vsqrdiff-fp16arith-u2.c", |
| "src/f16-vbinary/gen/f16-vsqrdiff-fp16arith-u4.c", |
| "src/f16-vbinary/gen/f16-vsqrdiffc-fp16arith-u1.c", |
| "src/f16-vbinary/gen/f16-vsqrdiffc-fp16arith-u2.c", |
| "src/f16-vbinary/gen/f16-vsqrdiffc-fp16arith-u4.c", |
| "src/f16-vbinary/gen/f16-vsub-minmax-fp16arith-u1.c", |
| "src/f16-vbinary/gen/f16-vsub-minmax-fp16arith-u2.c", |
| "src/f16-vbinary/gen/f16-vsub-minmax-fp16arith-u4.c", |
| "src/f16-vbinary/gen/f16-vsubc-minmax-fp16arith-u1.c", |
| "src/f16-vbinary/gen/f16-vsubc-minmax-fp16arith-u2.c", |
| "src/f16-vbinary/gen/f16-vsubc-minmax-fp16arith-u4.c", |
| "src/f16-vsqrt/gen/f16-vsqrt-fp16arith-sqrt-u1.c", |
| "src/f16-vsqrt/gen/f16-vsqrt-fp16arith-sqrt-u2.c", |
| "src/f16-vsqrt/gen/f16-vsqrt-fp16arith-sqrt-u4.c", |
| ] |
| |
| ALL_HEXAGON_MICROKERNEL_SRCS = [ |
| "src/cs16-vsquareabs/gen/cs16-vsquareabs-hexagon-x2.c", |
| "src/cs16-vsquareabs/gen/cs16-vsquareabs-hexagon-x4.c", |
| "src/cs16-vsquareabs/gen/cs16-vsquareabs-hexagon-x6.c", |
| "src/cs16-vsquareabs/gen/cs16-vsquareabs-hexagon-x8.c", |
| "src/cs16-vsquareabs/gen/cs16-vsquareabs-hexagon-x10.c", |
| "src/cs16-vsquareabs/gen/cs16-vsquareabs-hexagon-x12.c", |
| ] |
| |
| ALL_NEON_MICROKERNEL_SRCS = [ |
| "src/cs16-bfly4/cs16-bfly4-neon-x1.c", |
| "src/cs16-bfly4/cs16-bfly4-neon-x4.c", |
| "src/cs16-bfly4/cs16-bfly4-samples1-neon.c", |
| "src/cs16-bfly4/cs16-bfly4-samples4-neon.c", |
| "src/cs16-fftr/cs16-fftr-neon-x4.c", |
| "src/cs16-vsquareabs/gen/cs16-vsquareabs-neon-mlal-ld128-x4.c", |
| "src/cs16-vsquareabs/gen/cs16-vsquareabs-neon-mlal-ld128-x8.c", |
| "src/cs16-vsquareabs/gen/cs16-vsquareabs-neon-mlal-ld128-x12.c", |
| "src/cs16-vsquareabs/gen/cs16-vsquareabs-neon-mlal-ld128-x16.c", |
| "src/f16-f32-vcvt/gen/f16-f32-vcvt-neon-int16-u8.c", |
| "src/f16-f32-vcvt/gen/f16-f32-vcvt-neon-int16-u16.c", |
| "src/f16-f32-vcvt/gen/f16-f32-vcvt-neon-int16-u24.c", |
| "src/f16-f32-vcvt/gen/f16-f32-vcvt-neon-int16-u32.c", |
| "src/f16-f32-vcvt/gen/f16-f32-vcvt-neon-int32-u8.c", |
| "src/f16-f32-vcvt/gen/f16-f32-vcvt-neon-int32-u16.c", |
| "src/f16-f32-vcvt/gen/f16-f32-vcvt-neon-int32-u24.c", |
| "src/f16-f32-vcvt/gen/f16-f32-vcvt-neon-int32-u32.c", |
| "src/f32-argmaxpool/f32-argmaxpool-4x-neon-c4.c", |
| "src/f32-argmaxpool/f32-argmaxpool-9p8x-neon-c4.c", |
| "src/f32-argmaxpool/f32-argmaxpool-9x-neon-c4.c", |
| "src/f32-avgpool/f32-avgpool-9p8x-minmax-neon-c4.c", |
| "src/f32-avgpool/f32-avgpool-9x-minmax-neon-c4.c", |
| "src/f32-conv-hwc2chw/f32-conv-hwc2chw-3x3s2p1c3x4-neon-2x2.c", |
| "src/f32-conv-hwc/gen/f32-conv-hwc-3x3s2p0p1c3x4-neon-2x1.c", |
| "src/f32-conv-hwc/gen/f32-conv-hwc-3x3s2p0p1c3x4-neon-2x2.c", |
| "src/f32-conv-hwc/gen/f32-conv-hwc-3x3s2p0p1c3x8-neon-2x1.c", |
| "src/f32-conv-hwc/gen/f32-conv-hwc-3x3s2p0p1c3x8-neon-2x2.c", |
| "src/f32-conv-hwc/gen/f32-conv-hwc-3x3s2p1c3x4-neon-2x1.c", |
| "src/f32-conv-hwc/gen/f32-conv-hwc-3x3s2p1c3x4-neon-2x2.c", |
| "src/f32-conv-hwc/gen/f32-conv-hwc-3x3s2p1c3x8-neon-2x1.c", |
| "src/f32-conv-hwc/gen/f32-conv-hwc-3x3s2p1c3x8-neon-2x2.c", |
| "src/f32-dwconv2d-chw/gen/f32-dwconv2d-chw-3x3p1-minmax-neon-1x4-acc2.c", |
| "src/f32-dwconv2d-chw/gen/f32-dwconv2d-chw-3x3p1-minmax-neon-1x4-acc3.c", |
| "src/f32-dwconv2d-chw/gen/f32-dwconv2d-chw-3x3p1-minmax-neon-1x4-acc4.c", |
| "src/f32-dwconv2d-chw/gen/f32-dwconv2d-chw-3x3p1-minmax-neon-1x4.c", |
| "src/f32-dwconv2d-chw/gen/f32-dwconv2d-chw-3x3p1-minmax-neon-2x4-acc2.c", |
| "src/f32-dwconv2d-chw/gen/f32-dwconv2d-chw-3x3p1-minmax-neon-2x4.c", |
| "src/f32-dwconv2d-chw/gen/f32-dwconv2d-chw-3x3p1-minmax-neon-3x4.c", |
| "src/f32-dwconv2d-chw/gen/f32-dwconv2d-chw-3x3p1-minmax-neon-4x4.c", |
| "src/f32-dwconv2d-chw/gen/f32-dwconv2d-chw-3x3p1-minmax-neon-5x4.c", |
| "src/f32-dwconv2d-chw/gen/f32-dwconv2d-chw-3x3p1-minmax-neon-6x4.c", |
| "src/f32-dwconv2d-chw/gen/f32-dwconv2d-chw-3x3s2p1-minmax-neon-1x4-acc2.c", |
| "src/f32-dwconv2d-chw/gen/f32-dwconv2d-chw-3x3s2p1-minmax-neon-1x4-acc3.c", |
| "src/f32-dwconv2d-chw/gen/f32-dwconv2d-chw-3x3s2p1-minmax-neon-1x4-acc4.c", |
| "src/f32-dwconv2d-chw/gen/f32-dwconv2d-chw-3x3s2p1-minmax-neon-1x4.c", |
| "src/f32-dwconv2d-chw/gen/f32-dwconv2d-chw-3x3s2p1-minmax-neon-2x4-acc2.c", |
| "src/f32-dwconv2d-chw/gen/f32-dwconv2d-chw-3x3s2p1-minmax-neon-2x4.c", |
| "src/f32-dwconv2d-chw/gen/f32-dwconv2d-chw-3x3s2p1-minmax-neon-3x4.c", |
| "src/f32-dwconv2d-chw/gen/f32-dwconv2d-chw-3x3s2p1-minmax-neon-4x4.c", |
| "src/f32-dwconv2d-chw/gen/f32-dwconv2d-chw-5x5p2-minmax-neon-1x4-acc2.c", |
| "src/f32-dwconv2d-chw/gen/f32-dwconv2d-chw-5x5p2-minmax-neon-1x4-acc3.c", |
| "src/f32-dwconv2d-chw/gen/f32-dwconv2d-chw-5x5p2-minmax-neon-1x4-acc4.c", |
| "src/f32-dwconv2d-chw/gen/f32-dwconv2d-chw-5x5p2-minmax-neon-1x4-acc5.c", |
| "src/f32-dwconv2d-chw/gen/f32-dwconv2d-chw-5x5p2-minmax-neon-1x4.c", |
| "src/f32-dwconv2d-chw/gen/f32-dwconv2d-chw-5x5p2-minmax-neon-2x4-acc2.c", |
| "src/f32-dwconv2d-chw/gen/f32-dwconv2d-chw-5x5p2-minmax-neon-2x4-acc3.c", |
| "src/f32-dwconv2d-chw/gen/f32-dwconv2d-chw-5x5p2-minmax-neon-2x4.c", |
| "src/f32-dwconv2d-chw/gen/f32-dwconv2d-chw-5x5p2-minmax-neon-3x4-acc2.c", |
| "src/f32-dwconv2d-chw/gen/f32-dwconv2d-chw-5x5p2-minmax-neon-3x4.c", |
| "src/f32-dwconv2d-chw/gen/f32-dwconv2d-chw-5x5p2-minmax-neon-4x4-acc2.c", |
| "src/f32-dwconv2d-chw/gen/f32-dwconv2d-chw-5x5p2-minmax-neon-4x4.c", |
| "src/f32-dwconv2d-chw/gen/f32-dwconv2d-chw-5x5p2-minmax-neon-5x4.c", |
| "src/f32-dwconv2d-chw/gen/f32-dwconv2d-chw-5x5s2p2-minmax-neon-1x4-acc2.c", |
| "src/f32-dwconv2d-chw/gen/f32-dwconv2d-chw-5x5s2p2-minmax-neon-1x4-acc3.c", |
| "src/f32-dwconv2d-chw/gen/f32-dwconv2d-chw-5x5s2p2-minmax-neon-1x4-acc4.c", |
| "src/f32-dwconv2d-chw/gen/f32-dwconv2d-chw-5x5s2p2-minmax-neon-1x4-acc5.c", |
| "src/f32-dwconv2d-chw/gen/f32-dwconv2d-chw-5x5s2p2-minmax-neon-1x4.c", |
| "src/f32-dwconv2d-chw/gen/f32-dwconv2d-chw-5x5s2p2-minmax-neon-2x4-acc2.c", |
| "src/f32-dwconv2d-chw/gen/f32-dwconv2d-chw-5x5s2p2-minmax-neon-2x4-acc3.c", |
| "src/f32-dwconv2d-chw/gen/f32-dwconv2d-chw-5x5s2p2-minmax-neon-2x4.c", |
| "src/f32-dwconv2d-chw/gen/f32-dwconv2d-chw-5x5s2p2-minmax-neon-3x4-acc2.c", |
| "src/f32-dwconv2d-chw/gen/f32-dwconv2d-chw-5x5s2p2-minmax-neon-3x4.c", |
| "src/f32-dwconv/gen/f32-dwconv-2f2m2l4c4s4r-minmax-neon-acc2.c", |
| "src/f32-dwconv/gen/f32-dwconv-2f2m2l4c4s4r-minmax-neon.c", |
| "src/f32-dwconv/gen/f32-dwconv-2f2m2l8c4s4r-minmax-neon-acc2.c", |
| "src/f32-dwconv/gen/f32-dwconv-2f2m2l8c4s4r-minmax-neon.c", |
| "src/f32-dwconv/gen/f32-dwconv-2f2m2l16c4s4r-minmax-neon-acc2.c", |
| "src/f32-dwconv/gen/f32-dwconv-2f2m2l16c4s4r-minmax-neon.c", |
| "src/f32-dwconv/gen/f32-dwconv-3p4c-minmax-neon-acc2.c", |
| "src/f32-dwconv/gen/f32-dwconv-3p4c-minmax-neon.c", |
| "src/f32-dwconv/gen/f32-dwconv-3p8c-minmax-neon-acc2.c", |
| "src/f32-dwconv/gen/f32-dwconv-3p8c-minmax-neon.c", |
| "src/f32-dwconv/gen/f32-dwconv-3p16c-minmax-neon-acc2.c", |
| "src/f32-dwconv/gen/f32-dwconv-3p16c-minmax-neon.c", |
| "src/f32-dwconv/gen/f32-dwconv-4p4c-minmax-neon-acc2.c", |
| "src/f32-dwconv/gen/f32-dwconv-4p4c-minmax-neon.c", |
| "src/f32-dwconv/gen/f32-dwconv-4p8c-minmax-neon-acc2.c", |
| "src/f32-dwconv/gen/f32-dwconv-4p8c-minmax-neon.c", |
| "src/f32-dwconv/gen/f32-dwconv-4p16c-minmax-neon-acc2.c", |
| "src/f32-dwconv/gen/f32-dwconv-4p16c-minmax-neon.c", |
| "src/f32-dwconv/gen/f32-dwconv-5f5m5l4c4s4r-minmax-neon-acc2.c", |
| "src/f32-dwconv/gen/f32-dwconv-5f5m5l4c4s4r-minmax-neon.c", |
| "src/f32-dwconv/gen/f32-dwconv-5f5m5l8c4s4r-minmax-neon-acc2.c", |
| "src/f32-dwconv/gen/f32-dwconv-5f5m5l8c4s4r-minmax-neon.c", |
| "src/f32-dwconv/gen/f32-dwconv-6f6m7l4c4s4r-minmax-neon-acc2.c", |
| "src/f32-dwconv/gen/f32-dwconv-6f6m7l4c4s4r-minmax-neon.c", |
| "src/f32-dwconv/gen/f32-dwconv-6f6m7l8c4s4r-minmax-neon-acc2.c", |
| "src/f32-dwconv/gen/f32-dwconv-6f6m7l8c4s4r-minmax-neon.c", |
| "src/f32-dwconv/gen/f32-dwconv-8f8m9l4c4s4r-minmax-neon-acc2.c", |
| "src/f32-dwconv/gen/f32-dwconv-8f8m9l4c4s4r-minmax-neon.c", |
| "src/f32-dwconv/gen/f32-dwconv-8f8m9l8c4s4r-minmax-neon-acc2.c", |
| "src/f32-dwconv/gen/f32-dwconv-8f8m9l8c4s4r-minmax-neon.c", |
| "src/f32-dwconv/gen/f32-dwconv-9p4c-minmax-neon-acc2.c", |
| "src/f32-dwconv/gen/f32-dwconv-9p4c-minmax-neon.c", |
| "src/f32-dwconv/gen/f32-dwconv-9p8c-minmax-neon-acc2.c", |
| "src/f32-dwconv/gen/f32-dwconv-9p8c-minmax-neon.c", |
| "src/f32-dwconv/gen/f32-dwconv-9p16c-minmax-neon-acc2.c", |
| "src/f32-dwconv/gen/f32-dwconv-9p16c-minmax-neon.c", |
| "src/f32-dwconv/gen/f32-dwconv-25p4c-minmax-neon-acc2.c", |
| "src/f32-dwconv/gen/f32-dwconv-25p4c-minmax-neon.c", |
| "src/f32-dwconv/gen/f32-dwconv-25p8c-minmax-neon-acc2.c", |
| "src/f32-dwconv/gen/f32-dwconv-25p8c-minmax-neon.c", |
| "src/f32-dwconv/gen/f32-dwconv-25p16c-minmax-neon-acc2.c", |
| "src/f32-dwconv/gen/f32-dwconv-25p16c-minmax-neon.c", |
| "src/f32-f16-vcvt/gen/f32-f16-vcvt-neon-u8.c", |
| "src/f32-f16-vcvt/gen/f32-f16-vcvt-neon-u16.c", |
| "src/f32-f16-vcvt/gen/f32-f16-vcvt-neon-u24.c", |
| "src/f32-f16-vcvt/gen/f32-f16-vcvt-neon-u32.c", |
| "src/f32-gavgpool-cw/f32-gavgpool-cw-neon-x4.c", |
| "src/f32-gavgpool/f32-gavgpool-7p7x-minmax-neon-c4.c", |
| "src/f32-gavgpool/f32-gavgpool-7x-minmax-neon-c4.c", |
| "src/f32-gemm/gen/f32-gemm-1x8-minmax-neon-dup-ld64.c", |
| "src/f32-gemm/gen/f32-gemm-1x8-minmax-neon-lane-ld64.c", |
| "src/f32-gemm/gen/f32-gemm-1x8s4-minmax-neon.c", |
| "src/f32-gemm/gen/f32-gemm-4x2-minmax-neon-lane-ld64.c", |
| "src/f32-gemm/gen/f32-gemm-4x8-minmax-neon-dup-ld64.c", |
| "src/f32-gemm/gen/f32-gemm-4x8-minmax-neon-dup-ld128.c", |
| "src/f32-gemm/gen/f32-gemm-4x8-minmax-neon-lane-ld64.c", |
| "src/f32-gemm/gen/f32-gemm-4x8-minmax-neon-lane-ld128.c", |
| "src/f32-gemm/gen/f32-gemm-4x8s4-minmax-neon.c", |
| "src/f32-gemm/gen/f32-gemm-5x8-minmax-neon-lane-ld64.c", |
| "src/f32-gemm/gen/f32-gemm-6x2-minmax-neon-lane-ld64.c", |
| "src/f32-gemm/gen/f32-gemm-6x8-minmax-neon-dup-ld64.c", |
| "src/f32-gemm/gen/f32-gemm-6x8-minmax-neon-dup-ld128.c", |
| "src/f32-gemm/gen/f32-gemm-6x8-minmax-neon-lane-ld64.c", |
| "src/f32-gemm/gen/f32-gemm-6x8-minmax-neon-lane-ld128.c", |
| "src/f32-gemm/gen/f32-gemm-6x8s4-minmax-neon.c", |
| "src/f32-gemm/gen/f32-gemm-8x8s4-minmax-neon.c", |
| "src/f32-gemminc/gen/f32-gemminc-1x8-minmax-neon-dup-ld64.c", |
| "src/f32-gemminc/gen/f32-gemminc-1x8-minmax-neon-lane-ld64.c", |
| "src/f32-gemminc/gen/f32-gemminc-1x8s4-minmax-neon.c", |
| "src/f32-gemminc/gen/f32-gemminc-4x8-minmax-neon-dup-ld64.c", |
| "src/f32-gemminc/gen/f32-gemminc-4x8-minmax-neon-dup-ld128.c", |
| "src/f32-gemminc/gen/f32-gemminc-4x8-minmax-neon-lane-ld64.c", |
| "src/f32-gemminc/gen/f32-gemminc-4x8-minmax-neon-lane-ld128.c", |
| "src/f32-gemminc/gen/f32-gemminc-4x8s4-minmax-neon.c", |
| "src/f32-gemminc/gen/f32-gemminc-5x8-minmax-neon-lane-ld64.c", |
| "src/f32-gemminc/gen/f32-gemminc-6x8-minmax-neon-dup-ld64.c", |
| "src/f32-gemminc/gen/f32-gemminc-6x8-minmax-neon-dup-ld128.c", |
| "src/f32-gemminc/gen/f32-gemminc-6x8-minmax-neon-lane-ld64.c", |
| "src/f32-gemminc/gen/f32-gemminc-6x8-minmax-neon-lane-ld128.c", |
| "src/f32-gemminc/gen/f32-gemminc-6x8s4-minmax-neon.c", |
| "src/f32-gemminc/gen/f32-gemminc-8x8s4-minmax-neon.c", |
| "src/f32-ibilinear-chw/gen/f32-ibilinear-chw-neon-p4.c", |
| "src/f32-ibilinear-chw/gen/f32-ibilinear-chw-neon-p8.c", |
| "src/f32-ibilinear-chw/gen/f32-ibilinear-chw-neon-p16.c", |
| "src/f32-ibilinear/gen/f32-ibilinear-neon-c4.c", |
| "src/f32-ibilinear/gen/f32-ibilinear-neon-c8.c", |
| "src/f32-igemm/gen/f32-igemm-1x8-minmax-neon-dup-ld64.c", |
| "src/f32-igemm/gen/f32-igemm-1x8-minmax-neon-lane-ld64.c", |
| "src/f32-igemm/gen/f32-igemm-1x8s4-minmax-neon.c", |
| "src/f32-igemm/gen/f32-igemm-4x2-minmax-neon-lane-ld64.c", |
| "src/f32-igemm/gen/f32-igemm-4x4-minmax-neon-lane-ld64.c", |
| "src/f32-igemm/gen/f32-igemm-4x8-minmax-neon-dup-ld64.c", |
| "src/f32-igemm/gen/f32-igemm-4x8-minmax-neon-dup-ld128.c", |
| "src/f32-igemm/gen/f32-igemm-4x8-minmax-neon-lane-ld64.c", |
| "src/f32-igemm/gen/f32-igemm-4x8-minmax-neon-lane-ld128.c", |
| "src/f32-igemm/gen/f32-igemm-4x8s4-minmax-neon.c", |
| "src/f32-igemm/gen/f32-igemm-6x2-minmax-neon-lane-ld64.c", |
| "src/f32-igemm/gen/f32-igemm-6x8-minmax-neon-dup-ld64.c", |
| "src/f32-igemm/gen/f32-igemm-6x8-minmax-neon-dup-ld128.c", |
| "src/f32-igemm/gen/f32-igemm-6x8-minmax-neon-lane-ld64.c", |
| "src/f32-igemm/gen/f32-igemm-6x8-minmax-neon-lane-ld128.c", |
| "src/f32-igemm/gen/f32-igemm-6x8s4-minmax-neon.c", |
| "src/f32-igemm/gen/f32-igemm-8x8s4-minmax-neon.c", |
| "src/f32-maxpool/f32-maxpool-9p8x-minmax-neon-c4.c", |
| "src/f32-pavgpool/f32-pavgpool-9p8x-minmax-neon-c4.c", |
| "src/f32-pavgpool/f32-pavgpool-9x-minmax-neon-c4.c", |
| "src/f32-ppmm/gen/f32-ppmm-4x8-minmax-neon-prfm.c", |
| "src/f32-ppmm/gen/f32-ppmm-4x8-minmax-neon.c", |
| "src/f32-ppmm/gen/f32-ppmm-4x16-minmax-neon-prfm.c", |
| "src/f32-ppmm/gen/f32-ppmm-4x16-minmax-neon.c", |
| "src/f32-ppmm/gen/f32-ppmm-8x8-minmax-neon-prfm.c", |
| "src/f32-ppmm/gen/f32-ppmm-8x8-minmax-neon.c", |
| "src/f32-prelu/gen/f32-prelu-neon-1x4.c", |
| "src/f32-prelu/gen/f32-prelu-neon-1x8.c", |
| "src/f32-prelu/gen/f32-prelu-neon-1x16.c", |
| "src/f32-prelu/gen/f32-prelu-neon-2x4.c", |
| "src/f32-prelu/gen/f32-prelu-neon-2x8.c", |
| "src/f32-prelu/gen/f32-prelu-neon-2x16.c", |
| "src/f32-prelu/gen/f32-prelu-neon-4x4.c", |
| "src/f32-prelu/gen/f32-prelu-neon-4x8.c", |
| "src/f32-prelu/gen/f32-prelu-neon-4x16.c", |
| "src/f32-qc4w-gemm/gen/f32-qc4w-gemm-1x8-minmax-neon-dup-ld64.c", |
| "src/f32-qc4w-gemm/gen/f32-qc4w-gemm-1x8-minmax-neon-lane-ld64.c", |
| "src/f32-qc4w-gemm/gen/f32-qc4w-gemm-4x8-minmax-neon-dup-ld64.c", |
| "src/f32-qc4w-gemm/gen/f32-qc4w-gemm-4x8-minmax-neon-lane-ld64.c", |
| "src/f32-qc4w-gemm/gen/f32-qc4w-gemm-5x8-minmax-neon-lane-ld64.c", |
| "src/f32-qc4w-gemm/gen/f32-qc4w-gemm-6x8-minmax-neon-dup-ld64.c", |
| "src/f32-qc4w-gemm/gen/f32-qc4w-gemm-6x8-minmax-neon-lane-ld64.c", |
| "src/f32-qc8w-gemm/gen/f32-qc8w-gemm-1x8-minmax-neon-dup-ld64.c", |
| "src/f32-qc8w-gemm/gen/f32-qc8w-gemm-1x8-minmax-neon-lane-ld64.c", |
| "src/f32-qc8w-gemm/gen/f32-qc8w-gemm-4x2-minmax-neon-lane-ld64.c", |
| "src/f32-qc8w-gemm/gen/f32-qc8w-gemm-4x8-minmax-neon-dup-ld64.c", |
| "src/f32-qc8w-gemm/gen/f32-qc8w-gemm-4x8-minmax-neon-lane-ld64.c", |
| "src/f32-qc8w-gemm/gen/f32-qc8w-gemm-5x8-minmax-neon-lane-ld64.c", |
| "src/f32-qc8w-gemm/gen/f32-qc8w-gemm-6x2-minmax-neon-lane-ld64.c", |
| "src/f32-qc8w-gemm/gen/f32-qc8w-gemm-6x8-minmax-neon-dup-ld64.c", |
| "src/f32-qc8w-gemm/gen/f32-qc8w-gemm-6x8-minmax-neon-lane-ld64.c", |
| "src/f32-qs8-vcvt/gen/f32-qs8-vcvt-neon-u8.c", |
| "src/f32-qs8-vcvt/gen/f32-qs8-vcvt-neon-u16.c", |
| "src/f32-qs8-vcvt/gen/f32-qs8-vcvt-neon-u24.c", |
| "src/f32-qs8-vcvt/gen/f32-qs8-vcvt-neon-u32.c", |
| "src/f32-qu8-vcvt/gen/f32-qu8-vcvt-neon-u8.c", |
| "src/f32-qu8-vcvt/gen/f32-qu8-vcvt-neon-u16.c", |
| "src/f32-qu8-vcvt/gen/f32-qu8-vcvt-neon-u24.c", |
| "src/f32-qu8-vcvt/gen/f32-qu8-vcvt-neon-u32.c", |
| "src/f32-raddstoreexpminusmax/gen/f32-raddstoreexpminusmax-neon-rr2-lut64-p2-u4.c", |
| "src/f32-raddstoreexpminusmax/gen/f32-raddstoreexpminusmax-neon-rr2-lut64-p2-u8-acc2.c", |
| "src/f32-raddstoreexpminusmax/gen/f32-raddstoreexpminusmax-neon-rr2-lut64-p2-u8.c", |
| "src/f32-raddstoreexpminusmax/gen/f32-raddstoreexpminusmax-neon-rr2-lut64-p2-u12-acc2.c", |
| "src/f32-raddstoreexpminusmax/gen/f32-raddstoreexpminusmax-neon-rr2-lut64-p2-u12-acc3.c", |
| "src/f32-raddstoreexpminusmax/gen/f32-raddstoreexpminusmax-neon-rr2-lut64-p2-u12.c", |
| "src/f32-raddstoreexpminusmax/gen/f32-raddstoreexpminusmax-neon-rr2-lut64-p2-u16-acc2.c", |
| "src/f32-raddstoreexpminusmax/gen/f32-raddstoreexpminusmax-neon-rr2-lut64-p2-u16-acc4.c", |
| "src/f32-raddstoreexpminusmax/gen/f32-raddstoreexpminusmax-neon-rr2-lut64-p2-u16.c", |
| "src/f32-raddstoreexpminusmax/gen/f32-raddstoreexpminusmax-neon-rr2-lut64-p2-u20-acc2.c", |
| "src/f32-raddstoreexpminusmax/gen/f32-raddstoreexpminusmax-neon-rr2-lut64-p2-u20-acc5.c", |
| "src/f32-raddstoreexpminusmax/gen/f32-raddstoreexpminusmax-neon-rr2-lut64-p2-u20.c", |
| "src/f32-raddstoreexpminusmax/gen/f32-raddstoreexpminusmax-neon-rr2-p5-u4.c", |
| "src/f32-raddstoreexpminusmax/gen/f32-raddstoreexpminusmax-neon-rr2-p5-u8-acc2.c", |
| "src/f32-raddstoreexpminusmax/gen/f32-raddstoreexpminusmax-neon-rr2-p5-u8.c", |
| "src/f32-raddstoreexpminusmax/gen/f32-raddstoreexpminusmax-neon-rr2-p5-u12-acc2.c", |
| "src/f32-raddstoreexpminusmax/gen/f32-raddstoreexpminusmax-neon-rr2-p5-u12-acc3.c", |
| "src/f32-raddstoreexpminusmax/gen/f32-raddstoreexpminusmax-neon-rr2-p5-u12.c", |
| "src/f32-raddstoreexpminusmax/gen/f32-raddstoreexpminusmax-neon-rr2-p5-u16-acc2.c", |
| "src/f32-raddstoreexpminusmax/gen/f32-raddstoreexpminusmax-neon-rr2-p5-u16-acc4.c", |
| "src/f32-raddstoreexpminusmax/gen/f32-raddstoreexpminusmax-neon-rr2-p5-u16.c", |
| "src/f32-raddstoreexpminusmax/gen/f32-raddstoreexpminusmax-neon-rr2-p5-u20-acc2.c", |
| "src/f32-raddstoreexpminusmax/gen/f32-raddstoreexpminusmax-neon-rr2-p5-u20-acc5.c", |
| "src/f32-raddstoreexpminusmax/gen/f32-raddstoreexpminusmax-neon-rr2-p5-u20.c", |
| "src/f32-rmax/f32-rmax-neon.c", |
| "src/f32-rminmax/gen/f32-rmax-neon-u4.c", |
| "src/f32-rminmax/gen/f32-rmax-neon-u8-acc2.c", |
| "src/f32-rminmax/gen/f32-rmax-neon-u12-acc3.c", |
| "src/f32-rminmax/gen/f32-rmax-neon-u16-acc2.c", |
| "src/f32-rminmax/gen/f32-rmax-neon-u16-acc4.c", |
| "src/f32-rminmax/gen/f32-rmin-neon-u4.c", |
| "src/f32-rminmax/gen/f32-rmin-neon-u8-acc2.c", |
| "src/f32-rminmax/gen/f32-rmin-neon-u12-acc3.c", |
| "src/f32-rminmax/gen/f32-rmin-neon-u16-acc2.c", |
| "src/f32-rminmax/gen/f32-rmin-neon-u16-acc4.c", |
| "src/f32-rminmax/gen/f32-rminmax-neon-u4.c", |
| "src/f32-rminmax/gen/f32-rminmax-neon-u8-acc2.c", |
| "src/f32-rminmax/gen/f32-rminmax-neon-u12-acc3.c", |
| "src/f32-rminmax/gen/f32-rminmax-neon-u16-acc2.c", |
| "src/f32-rminmax/gen/f32-rminmax-neon-u16-acc4.c", |
| "src/f32-rsum/gen/f32-rsum-neon-u4.c", |
| "src/f32-rsum/gen/f32-rsum-neon-u8-acc2.c", |
| "src/f32-rsum/gen/f32-rsum-neon-u12-acc3.c", |
| "src/f32-rsum/gen/f32-rsum-neon-u16-acc2.c", |
| "src/f32-rsum/gen/f32-rsum-neon-u16-acc4.c", |
| "src/f32-spmm/gen/f32-spmm-4x1-minmax-neon-pipelined.c", |
| "src/f32-spmm/gen/f32-spmm-4x1-minmax-neon-x2.c", |
| "src/f32-spmm/gen/f32-spmm-4x1-minmax-neon.c", |
| "src/f32-spmm/gen/f32-spmm-8x1-minmax-neon-pipelined.c", |
| "src/f32-spmm/gen/f32-spmm-8x1-minmax-neon-x2.c", |
| "src/f32-spmm/gen/f32-spmm-8x1-minmax-neon.c", |
| "src/f32-spmm/gen/f32-spmm-12x1-minmax-neon.c", |
| "src/f32-spmm/gen/f32-spmm-16x1-minmax-neon-pipelined.c", |
| "src/f32-spmm/gen/f32-spmm-16x1-minmax-neon-x2.c", |
| "src/f32-spmm/gen/f32-spmm-16x1-minmax-neon.c", |
| "src/f32-spmm/gen/f32-spmm-32x1-minmax-neon-pipelined.c", |
| "src/f32-spmm/gen/f32-spmm-32x1-minmax-neon-x2.c", |
| "src/f32-spmm/gen/f32-spmm-32x1-minmax-neon.c", |
| "src/f32-vbinary/gen/f32-vadd-minmax-neon-u4.c", |
| "src/f32-vbinary/gen/f32-vadd-minmax-neon-u8.c", |
| "src/f32-vbinary/gen/f32-vaddc-minmax-neon-u4.c", |
| "src/f32-vbinary/gen/f32-vaddc-minmax-neon-u8.c", |
| "src/f32-vbinary/gen/f32-vmax-neon-u4.c", |
| "src/f32-vbinary/gen/f32-vmax-neon-u8.c", |
| "src/f32-vbinary/gen/f32-vmaxc-neon-u4.c", |
| "src/f32-vbinary/gen/f32-vmaxc-neon-u8.c", |
| "src/f32-vbinary/gen/f32-vmin-neon-u4.c", |
| "src/f32-vbinary/gen/f32-vmin-neon-u8.c", |
| "src/f32-vbinary/gen/f32-vminc-neon-u4.c", |
| "src/f32-vbinary/gen/f32-vminc-neon-u8.c", |
| "src/f32-vbinary/gen/f32-vmul-minmax-neon-u4.c", |
| "src/f32-vbinary/gen/f32-vmul-minmax-neon-u8.c", |
| "src/f32-vbinary/gen/f32-vmulc-minmax-neon-u4.c", |
| "src/f32-vbinary/gen/f32-vmulc-minmax-neon-u8.c", |
| "src/f32-vbinary/gen/f32-vrsubc-minmax-neon-u4.c", |
| "src/f32-vbinary/gen/f32-vrsubc-minmax-neon-u8.c", |
| "src/f32-vbinary/gen/f32-vsqrdiff-neon-u4.c", |
| "src/f32-vbinary/gen/f32-vsqrdiff-neon-u8.c", |
| "src/f32-vbinary/gen/f32-vsqrdiffc-neon-u4.c", |
| "src/f32-vbinary/gen/f32-vsqrdiffc-neon-u8.c", |
| "src/f32-vbinary/gen/f32-vsub-minmax-neon-u4.c", |
| "src/f32-vbinary/gen/f32-vsub-minmax-neon-u8.c", |
| "src/f32-vbinary/gen/f32-vsubc-minmax-neon-u4.c", |
| "src/f32-vbinary/gen/f32-vsubc-minmax-neon-u8.c", |
| "src/f32-vclamp/gen/f32-vclamp-neon-u4.c", |
| "src/f32-vclamp/gen/f32-vclamp-neon-u8.c", |
| "src/f32-vcmul/gen/f32-vcmul-neon-u4.c", |
| "src/f32-vcmul/gen/f32-vcmul-neon-u8.c", |
| "src/f32-vcmul/gen/f32-vcmul-neon-u12.c", |
| "src/f32-vcmul/gen/f32-vcmul-neon-u16.c", |
| "src/f32-velu/gen/f32-velu-neon-rr2-lut16-p3-u4.c", |
| "src/f32-velu/gen/f32-velu-neon-rr2-lut16-p3-u8.c", |
| "src/f32-velu/gen/f32-velu-neon-rr2-lut16-p3-u12.c", |
| "src/f32-velu/gen/f32-velu-neon-rr2-lut16-p3-u16.c", |
| "src/f32-velu/gen/f32-velu-neon-rr2-lut16-p3-u20.c", |
| "src/f32-velu/gen/f32-velu-neon-rr2-lut16-p3-u24.c", |
| "src/f32-velu/gen/f32-velu-neon-rr2-p6-u4.c", |
| "src/f32-velu/gen/f32-velu-neon-rr2-p6-u8.c", |
| "src/f32-velu/gen/f32-velu-neon-rr2-p6-u12.c", |
| "src/f32-velu/gen/f32-velu-neon-rr2-p6-u16.c", |
| "src/f32-velu/gen/f32-velu-neon-rr2-p6-u20.c", |
| "src/f32-velu/gen/f32-velu-neon-rr2-p6-u24.c", |
| "src/f32-vhswish/gen/f32-vhswish-neon-u4.c", |
| "src/f32-vhswish/gen/f32-vhswish-neon-u8.c", |
| "src/f32-vhswish/gen/f32-vhswish-neon-u16.c", |
| "src/f32-vlrelu/gen/f32-vlrelu-neon-u4.c", |
| "src/f32-vlrelu/gen/f32-vlrelu-neon-u8.c", |
| "src/f32-vmulcaddc/gen/f32-vmulcaddc-c4-minmax-neon-2x.c", |
| "src/f32-vmulcaddc/gen/f32-vmulcaddc-c8-minmax-neon-2x.c", |
| "src/f32-vrelu/gen/f32-vrelu-neon-u4.c", |
| "src/f32-vrelu/gen/f32-vrelu-neon-u8.c", |
| "src/f32-vrnd/gen/f32-vrndd-neon-u4.c", |
| "src/f32-vrnd/gen/f32-vrndd-neon-u8.c", |
| "src/f32-vrnd/gen/f32-vrndne-neon-u4.c", |
| "src/f32-vrnd/gen/f32-vrndne-neon-u8.c", |
| "src/f32-vrnd/gen/f32-vrndu-neon-u4.c", |
| "src/f32-vrnd/gen/f32-vrndu-neon-u8.c", |
| "src/f32-vrnd/gen/f32-vrndz-neon-u4.c", |
| "src/f32-vrnd/gen/f32-vrndz-neon-u8.c", |
| "src/f32-vsigmoid/gen/f32-vsigmoid-neon-rr2-lut64-p2-nr2recps-u4.c", |
| "src/f32-vsigmoid/gen/f32-vsigmoid-neon-rr2-lut64-p2-nr2recps-u8.c", |
| "src/f32-vsigmoid/gen/f32-vsigmoid-neon-rr2-lut64-p2-nr2recps-u12.c", |
| "src/f32-vsigmoid/gen/f32-vsigmoid-neon-rr2-lut64-p2-nr2recps-u16.c", |
| "src/f32-vsigmoid/gen/f32-vsigmoid-neon-rr2-lut64-p2-nr2recps-u20.c", |
| "src/f32-vsigmoid/gen/f32-vsigmoid-neon-rr2-lut64-p2-nr2recps-u24.c", |
| "src/f32-vsigmoid/gen/f32-vsigmoid-neon-rr2-lut2048-p1-nr2recps-u4.c", |
| "src/f32-vsigmoid/gen/f32-vsigmoid-neon-rr2-lut2048-p1-nr2recps-u8.c", |
| "src/f32-vsigmoid/gen/f32-vsigmoid-neon-rr2-lut2048-p1-nr2recps-u12.c", |
| "src/f32-vsigmoid/gen/f32-vsigmoid-neon-rr2-lut2048-p1-nr2recps-u16.c", |
| "src/f32-vsigmoid/gen/f32-vsigmoid-neon-rr2-lut2048-p1-nr2recps-u20.c", |
| "src/f32-vsigmoid/gen/f32-vsigmoid-neon-rr2-lut2048-p1-nr2recps-u24.c", |
| "src/f32-vsigmoid/gen/f32-vsigmoid-neon-rr2-p5-nr2recps-u4.c", |
| "src/f32-vsigmoid/gen/f32-vsigmoid-neon-rr2-p5-nr2recps-u8.c", |
| "src/f32-vsigmoid/gen/f32-vsigmoid-neon-rr2-p5-nr2recps-u12.c", |
| "src/f32-vsigmoid/gen/f32-vsigmoid-neon-rr2-p5-nr2recps-u16.c", |
| "src/f32-vsigmoid/gen/f32-vsigmoid-neon-rr2-p5-nr2recps-u20.c", |
| "src/f32-vsigmoid/gen/f32-vsigmoid-neon-rr2-p5-nr2recps-u24.c", |
| "src/f32-vtanh/gen/f32-vtanh-neon-expm1minus-rr1-p6h5ts-nr2recps-u4.c", |
| "src/f32-vtanh/gen/f32-vtanh-neon-expm1minus-rr1-p6h5ts-nr2recps-u8.c", |
| "src/f32-vtanh/gen/f32-vtanh-neon-expm1minus-rr1-p6h5ts-nr2recps-u12.c", |
| "src/f32-vtanh/gen/f32-vtanh-neon-expm1minus-rr1-p6h5ts-nr2recps-u16.c", |
| "src/f32-vunary/gen/f32-vabs-neon-u4.c", |
| "src/f32-vunary/gen/f32-vabs-neon-u8.c", |
| "src/f32-vunary/gen/f32-vneg-neon-u4.c", |
| "src/f32-vunary/gen/f32-vneg-neon-u8.c", |
| "src/f32-vunary/gen/f32-vsqr-neon-u4.c", |
| "src/f32-vunary/gen/f32-vsqr-neon-u8.c", |
| "src/i16-vlshift/gen/i16-vlshift-neon-u8.c", |
| "src/i16-vlshift/gen/i16-vlshift-neon-u16.c", |
| "src/i16-vlshift/gen/i16-vlshift-neon-u24.c", |
| "src/i16-vlshift/gen/i16-vlshift-neon-u32.c", |
| "src/math/f16-f32-cvt-neon-int16.c", |
| "src/math/f16-f32-cvt-neon-int32.c", |
| "src/math/f32-expm1minus-neon-rr2-lut16-p3.c", |
| "src/math/f32-expm1minus-neon-rr2-p6.c", |
| "src/math/f32-f16-cvt-neon.c", |
| "src/math/f32-qs8-cvt-neon.c", |
| "src/math/f32-qu8-cvt-neon.c", |
| "src/math/f32-roundd-neon-addsub.c", |
| "src/math/f32-roundd-neon-cvt.c", |
| "src/math/f32-roundne-neon-addsub.c", |
| "src/math/f32-roundu-neon-addsub.c", |
| "src/math/f32-roundu-neon-cvt.c", |
| "src/math/f32-roundz-neon-addsub.c", |
| "src/math/f32-roundz-neon-cvt.c", |
| "src/math/f32-sigmoid-neon-rr2-lut64-p2-nr2recps.c", |
| "src/math/f32-sigmoid-neon-rr2-lut2048-p1-nr2recps.c", |
| "src/math/f32-sigmoid-neon-rr2-p5-nr2recps.c", |
| "src/math/f32-sqrt-neon-nr1rsqrts.c", |
| "src/math/f32-sqrt-neon-nr2rsqrts.c", |
| "src/math/f32-sqrt-neon-nr3rsqrts.c", |
| "src/math/gen/f32-tanh-neon-expm1minus-rr1-p6h5ts-nr2recps.c", |
| "src/math/gen/f32-tanh-neon-expm1minus-rr2-lut8-p4h2ts-nr2recps.c", |
| "src/math/gen/f32-tanh-neon-expm1minus-rr2-lut8-p4h3ps-nr2recps.c", |
| "src/qd8-f32-qc4w-gemm/gen/qd8-f32-qc4w-gemm-1x16-minmax-neon-mlal-lane-prfm.c", |
| "src/qd8-f32-qc4w-gemm/gen/qd8-f32-qc4w-gemm-1x16-minmax-neon-mlal-lane.c", |
| "src/qd8-f32-qc4w-gemm/gen/qd8-f32-qc4w-gemm-2x16-minmax-neon-mlal-lane-prfm.c", |
| "src/qd8-f32-qc4w-gemm/gen/qd8-f32-qc4w-gemm-2x16-minmax-neon-mlal-lane.c", |
| "src/qd8-f32-qc4w-gemm/gen/qd8-f32-qc4w-gemm-3x16-minmax-neon-mlal-lane-prfm.c", |
| "src/qd8-f32-qc4w-gemm/gen/qd8-f32-qc4w-gemm-3x16-minmax-neon-mlal-lane.c", |
| "src/qd8-f32-qc4w-gemm/gen/qd8-f32-qc4w-gemm-4x16-minmax-neon-mlal-lane-prfm.c", |
| "src/qd8-f32-qc4w-gemm/gen/qd8-f32-qc4w-gemm-4x16-minmax-neon-mlal-lane.c", |
| "src/qd8-f32-qc4w-gemm/gen/qd8-f32-qc4w-gemm-6x16-minmax-neon-mlal-lane-prfm.c", |
| "src/qd8-f32-qc4w-gemm/gen/qd8-f32-qc4w-gemm-6x16-minmax-neon-mlal-lane.c", |
| "src/qd8-f32-qc8w-gemm/gen/qd8-f32-qc8w-gemm-1x8-minmax-neon-mlal-lane-prfm.c", |
| "src/qd8-f32-qc8w-gemm/gen/qd8-f32-qc8w-gemm-1x8-minmax-neon-mlal-lane.c", |
| "src/qd8-f32-qc8w-gemm/gen/qd8-f32-qc8w-gemm-1x8c2s4-minmax-neon-mlal.c", |
| "src/qd8-f32-qc8w-gemm/gen/qd8-f32-qc8w-gemm-1x16-minmax-neon-mlal-lane-prfm.c", |
| "src/qd8-f32-qc8w-gemm/gen/qd8-f32-qc8w-gemm-1x16-minmax-neon-mlal-lane.c", |
| "src/qd8-f32-qc8w-gemm/gen/qd8-f32-qc8w-gemm-2x8-minmax-neon-mlal-lane-prfm.c", |
| "src/qd8-f32-qc8w-gemm/gen/qd8-f32-qc8w-gemm-2x8-minmax-neon-mlal-lane.c", |
| "src/qd8-f32-qc8w-gemm/gen/qd8-f32-qc8w-gemm-2x8c2s4-minmax-neon-mlal.c", |
| "src/qd8-f32-qc8w-gemm/gen/qd8-f32-qc8w-gemm-2x16-minmax-neon-mlal-lane-prfm.c", |
| "src/qd8-f32-qc8w-gemm/gen/qd8-f32-qc8w-gemm-2x16-minmax-neon-mlal-lane.c", |
| "src/qd8-f32-qc8w-gemm/gen/qd8-f32-qc8w-gemm-3x8-minmax-neon-mlal-lane-prfm.c", |
| "src/qd8-f32-qc8w-gemm/gen/qd8-f32-qc8w-gemm-3x8-minmax-neon-mlal-lane.c", |
| "src/qd8-f32-qc8w-gemm/gen/qd8-f32-qc8w-gemm-3x16-minmax-neon-mlal-lane-prfm.c", |
| "src/qd8-f32-qc8w-gemm/gen/qd8-f32-qc8w-gemm-3x16-minmax-neon-mlal-lane.c", |
| "src/qd8-f32-qc8w-gemm/gen/qd8-f32-qc8w-gemm-4x8-minmax-neon-mlal-lane-prfm.c", |
| "src/qd8-f32-qc8w-gemm/gen/qd8-f32-qc8w-gemm-4x8-minmax-neon-mlal-lane.c", |
| "src/qd8-f32-qc8w-gemm/gen/qd8-f32-qc8w-gemm-4x16-minmax-neon-mlal-lane-prfm.c", |
| "src/qd8-f32-qc8w-gemm/gen/qd8-f32-qc8w-gemm-4x16-minmax-neon-mlal-lane.c", |
| "src/qd8-f32-qc8w-gemm/gen/qd8-f32-qc8w-gemm-6x8-minmax-neon-mlal-lane-prfm.c", |
| "src/qd8-f32-qc8w-gemm/gen/qd8-f32-qc8w-gemm-6x8-minmax-neon-mlal-lane.c", |
| "src/qd8-f32-qc8w-gemm/gen/qd8-f32-qc8w-gemm-6x16-minmax-neon-mlal-lane-prfm.c", |
| "src/qd8-f32-qc8w-gemm/gen/qd8-f32-qc8w-gemm-6x16-minmax-neon-mlal-lane.c", |
| "src/qs8-dwconv/gen/qs8-dwconv-5f5m5l8c8s8r-minmax-fp32-neon-mul16.c", |
| "src/qs8-dwconv/gen/qs8-dwconv-5f5m5l8c8s8r-minmax-rndnu-neon-mla8-ld64.c", |
| "src/qs8-dwconv/gen/qs8-dwconv-5f5m5l8c8s8r-minmax-rndnu-neon-mul8-ld64.c", |
| "src/qs8-dwconv/gen/qs8-dwconv-5f5m5l8c8s8r-minmax-rndnu-neon-mul16.c", |
| "src/qs8-dwconv/gen/qs8-dwconv-5f5m5l16c8s8r-minmax-fp32-neon-mul16.c", |
| "src/qs8-dwconv/gen/qs8-dwconv-5f5m5l16c8s8r-minmax-rndnu-neon-mla8-ld64.c", |
| "src/qs8-dwconv/gen/qs8-dwconv-5f5m5l16c8s8r-minmax-rndnu-neon-mla8-ld128.c", |
| "src/qs8-dwconv/gen/qs8-dwconv-5f5m5l16c8s8r-minmax-rndnu-neon-mul8-ld64.c", |
| "src/qs8-dwconv/gen/qs8-dwconv-5f5m5l16c8s8r-minmax-rndnu-neon-mul8-ld128.c", |
| "src/qs8-dwconv/gen/qs8-dwconv-5f5m5l16c8s8r-minmax-rndnu-neon-mul16.c", |
| "src/qs8-dwconv/gen/qs8-dwconv-5f5m5l32c8s8r-minmax-fp32-neon-mul16.c", |
| "src/qs8-dwconv/gen/qs8-dwconv-5f5m5l32c8s8r-minmax-rndnu-neon-mul16.c", |
| "src/qs8-dwconv/gen/qs8-dwconv-6f6m7l8c8s8r-minmax-fp32-neon-mul16.c", |
| "src/qs8-dwconv/gen/qs8-dwconv-6f6m7l8c8s8r-minmax-rndnu-neon-mla8-ld64.c", |
| "src/qs8-dwconv/gen/qs8-dwconv-6f6m7l8c8s8r-minmax-rndnu-neon-mul8-ld64.c", |
| "src/qs8-dwconv/gen/qs8-dwconv-6f6m7l8c8s8r-minmax-rndnu-neon-mul16.c", |
| "src/qs8-dwconv/gen/qs8-dwconv-6f6m7l16c8s8r-minmax-fp32-neon-mul16.c", |
| "src/qs8-dwconv/gen/qs8-dwconv-6f6m7l16c8s8r-minmax-rndnu-neon-mla8-ld64.c", |
| "src/qs8-dwconv/gen/qs8-dwconv-6f6m7l16c8s8r-minmax-rndnu-neon-mla8-ld128.c", |
| "src/qs8-dwconv/gen/qs8-dwconv-6f6m7l16c8s8r-minmax-rndnu-neon-mul8-ld64.c", |
| "src/qs8-dwconv/gen/qs8-dwconv-6f6m7l16c8s8r-minmax-rndnu-neon-mul8-ld128.c", |
| "src/qs8-dwconv/gen/qs8-dwconv-6f6m7l16c8s8r-minmax-rndnu-neon-mul16.c", |
| "src/qs8-dwconv/gen/qs8-dwconv-6f6m7l32c8s8r-minmax-fp32-neon-mul16.c", |
| "src/qs8-dwconv/gen/qs8-dwconv-6f6m7l32c8s8r-minmax-rndnu-neon-mul16.c", |
| "src/qs8-dwconv/gen/qs8-dwconv-8f8m9l8c8s8r-minmax-fp32-neon-mul16.c", |
| "src/qs8-dwconv/gen/qs8-dwconv-8f8m9l8c8s8r-minmax-rndnu-neon-mla8-ld64.c", |
| "src/qs8-dwconv/gen/qs8-dwconv-8f8m9l8c8s8r-minmax-rndnu-neon-mul8-ld64.c", |
| "src/qs8-dwconv/gen/qs8-dwconv-8f8m9l8c8s8r-minmax-rndnu-neon-mul16.c", |
| "src/qs8-dwconv/gen/qs8-dwconv-8f8m9l16c8s8r-minmax-fp32-neon-mul16.c", |
| "src/qs8-dwconv/gen/qs8-dwconv-8f8m9l16c8s8r-minmax-rndnu-neon-mla8-ld64.c", |
| "src/qs8-dwconv/gen/qs8-dwconv-8f8m9l16c8s8r-minmax-rndnu-neon-mla8-ld128.c", |
| "src/qs8-dwconv/gen/qs8-dwconv-8f8m9l16c8s8r-minmax-rndnu-neon-mul8-ld64.c", |
| "src/qs8-dwconv/gen/qs8-dwconv-8f8m9l16c8s8r-minmax-rndnu-neon-mul8-ld128.c", |
| "src/qs8-dwconv/gen/qs8-dwconv-8f8m9l16c8s8r-minmax-rndnu-neon-mul16.c", |
| "src/qs8-dwconv/gen/qs8-dwconv-8f8m9l32c8s8r-minmax-fp32-neon-mul16.c", |
| "src/qs8-dwconv/gen/qs8-dwconv-8f8m9l32c8s8r-minmax-rndnu-neon-mul16.c", |
| "src/qs8-dwconv/gen/qs8-dwconv-9p8c-minmax-fp32-neon-mul16.c", |
| "src/qs8-dwconv/gen/qs8-dwconv-9p8c-minmax-rndnu-neon-mla8-ld64.c", |
| "src/qs8-dwconv/gen/qs8-dwconv-9p8c-minmax-rndnu-neon-mul8-ld64.c", |
| "src/qs8-dwconv/gen/qs8-dwconv-9p8c-minmax-rndnu-neon-mul16.c", |
| "src/qs8-dwconv/gen/qs8-dwconv-9p16c-minmax-fp32-neon-mul16.c", |
| "src/qs8-dwconv/gen/qs8-dwconv-9p16c-minmax-rndnu-neon-mla8-ld64.c", |
| "src/qs8-dwconv/gen/qs8-dwconv-9p16c-minmax-rndnu-neon-mla8-ld128.c", |
| "src/qs8-dwconv/gen/qs8-dwconv-9p16c-minmax-rndnu-neon-mul8-ld64.c", |
| "src/qs8-dwconv/gen/qs8-dwconv-9p16c-minmax-rndnu-neon-mul8-ld128.c", |
| "src/qs8-dwconv/gen/qs8-dwconv-9p16c-minmax-rndnu-neon-mul16.c", |
| "src/qs8-dwconv/gen/qs8-dwconv-9p32c-minmax-fp32-neon-mul16.c", |
| "src/qs8-dwconv/gen/qs8-dwconv-9p32c-minmax-rndnu-neon-mul16.c", |
| "src/qs8-dwconv/gen/qs8-dwconv-25p8c-minmax-fp32-neon-mul16.c", |
| "src/qs8-dwconv/gen/qs8-dwconv-25p8c-minmax-rndnu-neon-mla8-ld64.c", |
| "src/qs8-dwconv/gen/qs8-dwconv-25p8c-minmax-rndnu-neon-mul8-ld64.c", |
| "src/qs8-dwconv/gen/qs8-dwconv-25p8c-minmax-rndnu-neon-mul16.c", |
| "src/qs8-dwconv/gen/qs8-dwconv-25p16c-minmax-fp32-neon-mul16.c", |
| "src/qs8-dwconv/gen/qs8-dwconv-25p16c-minmax-rndnu-neon-mla8-ld64.c", |
| "src/qs8-dwconv/gen/qs8-dwconv-25p16c-minmax-rndnu-neon-mla8-ld128.c", |
| "src/qs8-dwconv/gen/qs8-dwconv-25p16c-minmax-rndnu-neon-mul8-ld64.c", |
| "src/qs8-dwconv/gen/qs8-dwconv-25p16c-minmax-rndnu-neon-mul8-ld128.c", |
| "src/qs8-dwconv/gen/qs8-dwconv-25p16c-minmax-rndnu-neon-mul16.c", |
| "src/qs8-dwconv/gen/qs8-dwconv-25p32c-minmax-fp32-neon-mul16.c", |
| "src/qs8-dwconv/gen/qs8-dwconv-25p32c-minmax-rndnu-neon-mul16.c", |
| "src/qs8-f32-vcvt/gen/qs8-f32-vcvt-neon-u8.c", |
| "src/qs8-f32-vcvt/gen/qs8-f32-vcvt-neon-u16.c", |
| "src/qs8-f32-vcvt/gen/qs8-f32-vcvt-neon-u24.c", |
| "src/qs8-f32-vcvt/gen/qs8-f32-vcvt-neon-u32.c", |
| "src/qs8-gavgpool/gen/qs8-gavgpool-7p7x-minmax-fp32-neon-c8.c", |
| "src/qs8-gavgpool/gen/qs8-gavgpool-7p7x-minmax-fp32-neon-c16.c", |
| "src/qs8-gavgpool/gen/qs8-gavgpool-7p7x-minmax-fp32-neon-c24.c", |
| "src/qs8-gavgpool/gen/qs8-gavgpool-7p7x-minmax-fp32-neon-c32.c", |
| "src/qs8-gavgpool/gen/qs8-gavgpool-7p7x-minmax-rndnu-neon-c8.c", |
| "src/qs8-gavgpool/gen/qs8-gavgpool-7p7x-minmax-rndnu-neon-c16.c", |
| "src/qs8-gavgpool/gen/qs8-gavgpool-7p7x-minmax-rndnu-neon-c24.c", |
| "src/qs8-gavgpool/gen/qs8-gavgpool-7p7x-minmax-rndnu-neon-c32.c", |
| "src/qs8-gavgpool/gen/qs8-gavgpool-7x-minmax-fp32-neon-c8.c", |
| "src/qs8-gavgpool/gen/qs8-gavgpool-7x-minmax-fp32-neon-c16.c", |
| "src/qs8-gavgpool/gen/qs8-gavgpool-7x-minmax-fp32-neon-c24.c", |
| "src/qs8-gavgpool/gen/qs8-gavgpool-7x-minmax-fp32-neon-c32.c", |
| "src/qs8-gavgpool/gen/qs8-gavgpool-7x-minmax-rndnu-neon-c8.c", |
| "src/qs8-gavgpool/gen/qs8-gavgpool-7x-minmax-rndnu-neon-c16.c", |
| "src/qs8-gavgpool/gen/qs8-gavgpool-7x-minmax-rndnu-neon-c24.c", |
| "src/qs8-gavgpool/gen/qs8-gavgpool-7x-minmax-rndnu-neon-c32.c", |
| "src/qs8-gemm/gen/qs8-gemm-1x8-minmax-rndnu-neon-mlal-lane-prfm.c", |
| "src/qs8-gemm/gen/qs8-gemm-1x8-minmax-rndnu-neon-mlal-lane.c", |
| "src/qs8-gemm/gen/qs8-gemm-1x8-minmax-rndnu-neon-mull-addw-dup.c", |
| "src/qs8-gemm/gen/qs8-gemm-1x8c2-minmax-fp32-neon-mlal-dup.c", |
| "src/qs8-gemm/gen/qs8-gemm-1x8c2-minmax-fp32-neon-mlal-ld1r.c", |
| "src/qs8-gemm/gen/qs8-gemm-1x8c2-minmax-fp32-neon-mlal-ld2r.c", |
| "src/qs8-gemm/gen/qs8-gemm-1x8c2-minmax-fp32-neon-mlal-ld4r.c", |
| "src/qs8-gemm/gen/qs8-gemm-1x8c2-minmax-rndnu-neon-mlal-dup.c", |
| "src/qs8-gemm/gen/qs8-gemm-1x8c2-minmax-rndnu-neon-mlal-ld1r.c", |
| "src/qs8-gemm/gen/qs8-gemm-1x8c2-minmax-rndnu-neon-mlal-ld2r.c", |
| "src/qs8-gemm/gen/qs8-gemm-1x8c2-minmax-rndnu-neon-mlal-ld4r.c", |
| "src/qs8-gemm/gen/qs8-gemm-1x8c2-minmax-rndnu-neon-mull-dup.c", |
| "src/qs8-gemm/gen/qs8-gemm-1x8c2-minmax-rndnu-neon-mull-ld1r.c", |
| "src/qs8-gemm/gen/qs8-gemm-1x8c2-minmax-rndnu-neon-mull-ld2r.c", |
| "src/qs8-gemm/gen/qs8-gemm-1x8c2-minmax-rndnu-neon-mull-ld4r.c", |
| "src/qs8-gemm/gen/qs8-gemm-1x8c2s4-minmax-fp32-neon-mlal.c", |
| "src/qs8-gemm/gen/qs8-gemm-1x8c2s4-minmax-rndnu-neon-mlal.c", |
| "src/qs8-gemm/gen/qs8-gemm-1x8c2s4-minmax-rndnu-neon-mull.c", |
| "src/qs8-gemm/gen/qs8-gemm-1x8c4-minmax-fp32-neon-mlal-dup.c", |
| "src/qs8-gemm/gen/qs8-gemm-1x8c4-minmax-fp32-neon-mlal-ld1r.c", |
| "src/qs8-gemm/gen/qs8-gemm-1x8c4-minmax-fp32-neon-mlal-ld2r.c", |
| "src/qs8-gemm/gen/qs8-gemm-1x8c4-minmax-rndnu-neon-mlal-dup.c", |
| "src/qs8-gemm/gen/qs8-gemm-1x8c4-minmax-rndnu-neon-mlal-ld1r.c", |
| "src/qs8-gemm/gen/qs8-gemm-1x8c4-minmax-rndnu-neon-mlal-ld2r.c", |
| "src/qs8-gemm/gen/qs8-gemm-1x8c4-minmax-rndnu-neon-mull-dup.c", |
| "src/qs8-gemm/gen/qs8-gemm-1x8c4-minmax-rndnu-neon-mull-ld1r.c", |
| "src/qs8-gemm/gen/qs8-gemm-1x8c4-minmax-rndnu-neon-mull-ld2r.c", |
| "src/qs8-gemm/gen/qs8-gemm-1x8c4s2-minmax-fp32-neon-mlal.c", |
| "src/qs8-gemm/gen/qs8-gemm-1x8c4s2-minmax-rndnu-neon-mlal.c", |
| "src/qs8-gemm/gen/qs8-gemm-1x8c4s2-minmax-rndnu-neon-mull.c", |
| "src/qs8-gemm/gen/qs8-gemm-1x8c8-minmax-fp32-neon-mlal.c", |
| "src/qs8-gemm/gen/qs8-gemm-1x8c8-minmax-rndnu-neon-mlal.c", |
| "src/qs8-gemm/gen/qs8-gemm-1x8c8-minmax-rndnu-neon-mull.c", |
| "src/qs8-gemm/gen/qs8-gemm-1x8c16-minmax-rndnu-neon-mlal.c", |
| "src/qs8-gemm/gen/qs8-gemm-1x16-minmax-fp32-neon-mlal-lane.c", |
| "src/qs8-gemm/gen/qs8-gemm-1x16-minmax-rndnu-neon-mlal-lane-prfm.c", |
| "src/qs8-gemm/gen/qs8-gemm-1x16-minmax-rndnu-neon-mlal-lane.c", |
| "src/qs8-gemm/gen/qs8-gemm-1x16-minmax-rndnu-neon-mull-addw-dup.c", |
| "src/qs8-gemm/gen/qs8-gemm-1x16c2-minmax-rndnu-neon-mlal-dup.c", |
| "src/qs8-gemm/gen/qs8-gemm-1x16c2-minmax-rndnu-neon-mlal-ld1r.c", |
| "src/qs8-gemm/gen/qs8-gemm-1x16c2-minmax-rndnu-neon-mlal-ld2r.c", |
| "src/qs8-gemm/gen/qs8-gemm-1x16c2-minmax-rndnu-neon-mlal-ld4r.c", |
| "src/qs8-gemm/gen/qs8-gemm-1x16c2-minmax-rndnu-neon-mull-dup.c", |
| "src/qs8-gemm/gen/qs8-gemm-1x16c2-minmax-rndnu-neon-mull-ld1r.c", |
| "src/qs8-gemm/gen/qs8-gemm-1x16c2-minmax-rndnu-neon-mull-ld2r.c", |
| "src/qs8-gemm/gen/qs8-gemm-1x16c2-minmax-rndnu-neon-mull-ld4r.c", |
| "src/qs8-gemm/gen/qs8-gemm-1x16c2s4-minmax-rndnu-neon-mlal.c", |
| "src/qs8-gemm/gen/qs8-gemm-1x16c2s4-minmax-rndnu-neon-mull.c", |
| "src/qs8-gemm/gen/qs8-gemm-1x16c4-minmax-rndnu-neon-mlal-dup.c", |
| "src/qs8-gemm/gen/qs8-gemm-1x16c4-minmax-rndnu-neon-mlal-ld1r.c", |
| "src/qs8-gemm/gen/qs8-gemm-1x16c4-minmax-rndnu-neon-mlal-ld2r.c", |
| "src/qs8-gemm/gen/qs8-gemm-1x16c4-minmax-rndnu-neon-mull-dup.c", |
| "src/qs8-gemm/gen/qs8-gemm-1x16c4-minmax-rndnu-neon-mull-ld1r.c", |
| "src/qs8-gemm/gen/qs8-gemm-1x16c4-minmax-rndnu-neon-mull-ld2r.c", |
| "src/qs8-gemm/gen/qs8-gemm-1x16c4s2-minmax-rndnu-neon-mlal.c", |
| "src/qs8-gemm/gen/qs8-gemm-1x16c4s2-minmax-rndnu-neon-mull.c", |
| "src/qs8-gemm/gen/qs8-gemm-1x16c8-minmax-rndnu-neon-mlal.c", |
| "src/qs8-gemm/gen/qs8-gemm-1x16c8-minmax-rndnu-neon-mull.c", |
| "src/qs8-gemm/gen/qs8-gemm-1x16c16-minmax-rndnu-neon-mlal.c", |
| "src/qs8-gemm/gen/qs8-gemm-2x8-minmax-rndnu-neon-mlal-lane-prfm.c", |
| "src/qs8-gemm/gen/qs8-gemm-2x8-minmax-rndnu-neon-mlal-lane.c", |
| "src/qs8-gemm/gen/qs8-gemm-2x8-minmax-rndnu-neon-mull-addw-dup.c", |
| "src/qs8-gemm/gen/qs8-gemm-2x8c2-minmax-fp32-neon-mlal-dup.c", |
| "src/qs8-gemm/gen/qs8-gemm-2x8c2-minmax-fp32-neon-mlal-ld1r.c", |
| "src/qs8-gemm/gen/qs8-gemm-2x8c2-minmax-fp32-neon-mlal-ld2r.c", |
| "src/qs8-gemm/gen/qs8-gemm-2x8c2-minmax-fp32-neon-mlal-ld4r.c", |
| "src/qs8-gemm/gen/qs8-gemm-2x8c2-minmax-rndnu-neon-mlal-dup.c", |
| "src/qs8-gemm/gen/qs8-gemm-2x8c2-minmax-rndnu-neon-mlal-ld1r.c", |
| "src/qs8-gemm/gen/qs8-gemm-2x8c2-minmax-rndnu-neon-mlal-ld2r.c", |
| "src/qs8-gemm/gen/qs8-gemm-2x8c2-minmax-rndnu-neon-mlal-ld4r.c", |
| "src/qs8-gemm/gen/qs8-gemm-2x8c2-minmax-rndnu-neon-mull-dup.c", |
| "src/qs8-gemm/gen/qs8-gemm-2x8c2-minmax-rndnu-neon-mull-ld1r.c", |
| "src/qs8-gemm/gen/qs8-gemm-2x8c2-minmax-rndnu-neon-mull-ld2r.c", |
| "src/qs8-gemm/gen/qs8-gemm-2x8c2-minmax-rndnu-neon-mull-ld4r.c", |
| "src/qs8-gemm/gen/qs8-gemm-2x8c2s4-minmax-fp32-neon-mlal.c", |
| "src/qs8-gemm/gen/qs8-gemm-2x8c2s4-minmax-rndnu-neon-mlal.c", |
| "src/qs8-gemm/gen/qs8-gemm-2x8c2s4-minmax-rndnu-neon-mull.c", |
| "src/qs8-gemm/gen/qs8-gemm-2x8c4-minmax-fp32-neon-mlal-dup.c", |
| "src/qs8-gemm/gen/qs8-gemm-2x8c4-minmax-fp32-neon-mlal-ld1r.c", |
| "src/qs8-gemm/gen/qs8-gemm-2x8c4-minmax-fp32-neon-mlal-ld2r.c", |
| "src/qs8-gemm/gen/qs8-gemm-2x8c4-minmax-rndnu-neon-mlal-dup.c", |
| "src/qs8-gemm/gen/qs8-gemm-2x8c4-minmax-rndnu-neon-mlal-ld1r.c", |
| "src/qs8-gemm/gen/qs8-gemm-2x8c4-minmax-rndnu-neon-mlal-ld2r.c", |
| "src/qs8-gemm/gen/qs8-gemm-2x8c4-minmax-rndnu-neon-mull-dup.c", |
| "src/qs8-gemm/gen/qs8-gemm-2x8c4-minmax-rndnu-neon-mull-ld1r.c", |
| "src/qs8-gemm/gen/qs8-gemm-2x8c4-minmax-rndnu-neon-mull-ld2r.c", |
| "src/qs8-gemm/gen/qs8-gemm-2x8c4s2-minmax-fp32-neon-mlal.c", |
| "src/qs8-gemm/gen/qs8-gemm-2x8c4s2-minmax-rndnu-neon-mlal.c", |
| "src/qs8-gemm/gen/qs8-gemm-2x8c4s2-minmax-rndnu-neon-mull.c", |
| "src/qs8-gemm/gen/qs8-gemm-2x8c8-minmax-fp32-neon-mlal.c", |
| "src/qs8-gemm/gen/qs8-gemm-2x8c8-minmax-rndnu-neon-mlal.c", |
| "src/qs8-gemm/gen/qs8-gemm-2x8c8-minmax-rndnu-neon-mull.c", |
| "src/qs8-gemm/gen/qs8-gemm-2x8c16-minmax-rndnu-neon-mlal.c", |
| "src/qs8-gemm/gen/qs8-gemm-2x16-minmax-rndnu-neon-mlal-lane-prfm.c", |
| "src/qs8-gemm/gen/qs8-gemm-2x16-minmax-rndnu-neon-mlal-lane.c", |
| "src/qs8-gemm/gen/qs8-gemm-2x16-minmax-rndnu-neon-mull-addw-dup.c", |
| "src/qs8-gemm/gen/qs8-gemm-2x16c2-minmax-rndnu-neon-mlal-dup.c", |
| "src/qs8-gemm/gen/qs8-gemm-2x16c2-minmax-rndnu-neon-mlal-ld1r.c", |
| "src/qs8-gemm/gen/qs8-gemm-2x16c2-minmax-rndnu-neon-mlal-ld2r.c", |
| "src/qs8-gemm/gen/qs8-gemm-2x16c2-minmax-rndnu-neon-mlal-ld4r.c", |
| "src/qs8-gemm/gen/qs8-gemm-2x16c2-minmax-rndnu-neon-mull-dup.c", |
| "src/qs8-gemm/gen/qs8-gemm-2x16c2-minmax-rndnu-neon-mull-ld1r.c", |
| "src/qs8-gemm/gen/qs8-gemm-2x16c2-minmax-rndnu-neon-mull-ld2r.c", |
| "src/qs8-gemm/gen/qs8-gemm-2x16c2-minmax-rndnu-neon-mull-ld4r.c", |
| "src/qs8-gemm/gen/qs8-gemm-2x16c2s4-minmax-rndnu-neon-mlal.c", |
| "src/qs8-gemm/gen/qs8-gemm-2x16c2s4-minmax-rndnu-neon-mull.c", |
| "src/qs8-gemm/gen/qs8-gemm-2x16c4-minmax-rndnu-neon-mlal-dup.c", |
| "src/qs8-gemm/gen/qs8-gemm-2x16c4-minmax-rndnu-neon-mlal-ld1r.c", |
| "src/qs8-gemm/gen/qs8-gemm-2x16c4-minmax-rndnu-neon-mlal-ld2r.c", |
| "src/qs8-gemm/gen/qs8-gemm-2x16c4-minmax-rndnu-neon-mull-dup.c", |
| "src/qs8-gemm/gen/qs8-gemm-2x16c4-minmax-rndnu-neon-mull-ld1r.c", |
| "src/qs8-gemm/gen/qs8-gemm-2x16c4-minmax-rndnu-neon-mull-ld2r.c", |
| "src/qs8-gemm/gen/qs8-gemm-2x16c4s2-minmax-rndnu-neon-mlal.c", |
| "src/qs8-gemm/gen/qs8-gemm-2x16c4s2-minmax-rndnu-neon-mull.c", |
| "src/qs8-gemm/gen/qs8-gemm-2x16c8-minmax-rndnu-neon-mlal.c", |
| "src/qs8-gemm/gen/qs8-gemm-2x16c8-minmax-rndnu-neon-mull.c", |
| "src/qs8-gemm/gen/qs8-gemm-2x16c16-minmax-rndnu-neon-mlal.c", |
| "src/qs8-gemm/gen/qs8-gemm-3x8-minmax-rndnu-neon-mlal-lane-prfm.c", |
| "src/qs8-gemm/gen/qs8-gemm-3x8-minmax-rndnu-neon-mlal-lane.c", |
| "src/qs8-gemm/gen/qs8-gemm-3x8-minmax-rndnu-neon-mull-addw-dup.c", |
| "src/qs8-gemm/gen/qs8-gemm-3x8c2-minmax-rndnu-neon-mlal-dup.c", |
| "src/qs8-gemm/gen/qs8-gemm-3x8c2-minmax-rndnu-neon-mlal-ld1r.c", |
| "src/qs8-gemm/gen/qs8-gemm-3x8c2-minmax-rndnu-neon-mlal-ld2r.c", |
| "src/qs8-gemm/gen/qs8-gemm-3x8c2-minmax-rndnu-neon-mlal-ld4r.c", |
| "src/qs8-gemm/gen/qs8-gemm-3x8c2-minmax-rndnu-neon-mull-dup.c", |
| "src/qs8-gemm/gen/qs8-gemm-3x8c2-minmax-rndnu-neon-mull-ld1r.c", |
| "src/qs8-gemm/gen/qs8-gemm-3x8c2-minmax-rndnu-neon-mull-ld2r.c", |
| "src/qs8-gemm/gen/qs8-gemm-3x8c2-minmax-rndnu-neon-mull-ld4r.c", |
| "src/qs8-gemm/gen/qs8-gemm-3x8c2s4-minmax-rndnu-neon-mlal.c", |
| "src/qs8-gemm/gen/qs8-gemm-3x8c2s4-minmax-rndnu-neon-mull.c", |
| "src/qs8-gemm/gen/qs8-gemm-3x8c4-minmax-rndnu-neon-mlal-dup.c", |
| "src/qs8-gemm/gen/qs8-gemm-3x8c4-minmax-rndnu-neon-mlal-ld1r.c", |
| "src/qs8-gemm/gen/qs8-gemm-3x8c4-minmax-rndnu-neon-mlal-ld2r.c", |
| "src/qs8-gemm/gen/qs8-gemm-3x8c4-minmax-rndnu-neon-mull-dup.c", |
| "src/qs8-gemm/gen/qs8-gemm-3x8c4-minmax-rndnu-neon-mull-ld1r.c", |
| "src/qs8-gemm/gen/qs8-gemm-3x8c4-minmax-rndnu-neon-mull-ld2r.c", |
| "src/qs8-gemm/gen/qs8-gemm-3x8c4s2-minmax-rndnu-neon-mlal.c", |
| "src/qs8-gemm/gen/qs8-gemm-3x8c4s2-minmax-rndnu-neon-mull.c", |
| "src/qs8-gemm/gen/qs8-gemm-3x8c8-minmax-rndnu-neon-mlal.c", |
| "src/qs8-gemm/gen/qs8-gemm-3x8c8-minmax-rndnu-neon-mull.c", |
| "src/qs8-gemm/gen/qs8-gemm-3x8c16-minmax-rndnu-neon-mlal.c", |
| "src/qs8-gemm/gen/qs8-gemm-3x16-minmax-rndnu-neon-mlal-lane-prfm.c", |
| "src/qs8-gemm/gen/qs8-gemm-3x16-minmax-rndnu-neon-mlal-lane.c", |
| "src/qs8-gemm/gen/qs8-gemm-3x16-minmax-rndnu-neon-mull-addw-dup.c", |
| "src/qs8-gemm/gen/qs8-gemm-3x16c2-minmax-rndnu-neon-mlal-dup.c", |
| "src/qs8-gemm/gen/qs8-gemm-3x16c2-minmax-rndnu-neon-mlal-ld1r.c", |
| "src/qs8-gemm/gen/qs8-gemm-3x16c2-minmax-rndnu-neon-mlal-ld2r.c", |
| "src/qs8-gemm/gen/qs8-gemm-3x16c2-minmax-rndnu-neon-mlal-ld4r.c", |
| "src/qs8-gemm/gen/qs8-gemm-3x16c2-minmax-rndnu-neon-mull-dup.c", |
| "src/qs8-gemm/gen/qs8-gemm-3x16c2-minmax-rndnu-neon-mull-ld1r.c", |
| "src/qs8-gemm/gen/qs8-gemm-3x16c2-minmax-rndnu-neon-mull-ld2r.c", |
| "src/qs8-gemm/gen/qs8-gemm-3x16c2-minmax-rndnu-neon-mull-ld4r.c", |
| "src/qs8-gemm/gen/qs8-gemm-3x16c2s4-minmax-rndnu-neon-mlal.c", |
| "src/qs8-gemm/gen/qs8-gemm-3x16c2s4-minmax-rndnu-neon-mull.c", |
| "src/qs8-gemm/gen/qs8-gemm-3x16c4-minmax-rndnu-neon-mlal-dup.c", |
| "src/qs8-gemm/gen/qs8-gemm-3x16c4-minmax-rndnu-neon-mlal-ld1r.c", |
| "src/qs8-gemm/gen/qs8-gemm-3x16c4-minmax-rndnu-neon-mlal-ld2r.c", |
| "src/qs8-gemm/gen/qs8-gemm-3x16c4-minmax-rndnu-neon-mull-dup.c", |
| "src/qs8-gemm/gen/qs8-gemm-3x16c4-minmax-rndnu-neon-mull-ld1r.c", |
| "src/qs8-gemm/gen/qs8-gemm-3x16c4-minmax-rndnu-neon-mull-ld2r.c", |
| "src/qs8-gemm/gen/qs8-gemm-3x16c4s2-minmax-rndnu-neon-mlal.c", |
| "src/qs8-gemm/gen/qs8-gemm-3x16c4s2-minmax-rndnu-neon-mull.c", |
| "src/qs8-gemm/gen/qs8-gemm-3x16c8-minmax-rndnu-neon-mlal.c", |
| "src/qs8-gemm/gen/qs8-gemm-3x16c8-minmax-rndnu-neon-mull.c", |
| "src/qs8-gemm/gen/qs8-gemm-3x16c16-minmax-rndnu-neon-mlal.c", |
| "src/qs8-gemm/gen/qs8-gemm-4x8-minmax-rndnu-neon-mlal-lane-prfm.c", |
| "src/qs8-gemm/gen/qs8-gemm-4x8-minmax-rndnu-neon-mlal-lane.c", |
| "src/qs8-gemm/gen/qs8-gemm-4x8-minmax-rndnu-neon-mull-addw-dup.c", |
| "src/qs8-gemm/gen/qs8-gemm-4x8c2-minmax-rndnu-neon-mlal-dup.c", |
| "src/qs8-gemm/gen/qs8-gemm-4x8c2-minmax-rndnu-neon-mlal-ld1r.c", |
| "src/qs8-gemm/gen/qs8-gemm-4x8c2-minmax-rndnu-neon-mlal-ld2r.c", |
| "src/qs8-gemm/gen/qs8-gemm-4x8c2-minmax-rndnu-neon-mlal-ld4r.c", |
| "src/qs8-gemm/gen/qs8-gemm-4x8c2-minmax-rndnu-neon-mull-dup.c", |
| "src/qs8-gemm/gen/qs8-gemm-4x8c2-minmax-rndnu-neon-mull-ld1r.c", |
| "src/qs8-gemm/gen/qs8-gemm-4x8c2-minmax-rndnu-neon-mull-ld2r.c", |
| "src/qs8-gemm/gen/qs8-gemm-4x8c2-minmax-rndnu-neon-mull-ld4r.c", |
| "src/qs8-gemm/gen/qs8-gemm-4x8c2s4-minmax-rndnu-neon-mlal.c", |
| "src/qs8-gemm/gen/qs8-gemm-4x8c2s4-minmax-rndnu-neon-mull.c", |
| "src/qs8-gemm/gen/qs8-gemm-4x8c4-minmax-rndnu-neon-mlal-dup.c", |
| "src/qs8-gemm/gen/qs8-gemm-4x8c4-minmax-rndnu-neon-mlal-ld1r.c", |
| "src/qs8-gemm/gen/qs8-gemm-4x8c4-minmax-rndnu-neon-mlal-ld2r.c", |
| "src/qs8-gemm/gen/qs8-gemm-4x8c4-minmax-rndnu-neon-mull-dup.c", |
| "src/qs8-gemm/gen/qs8-gemm-4x8c4-minmax-rndnu-neon-mull-ld1r.c", |
| "src/qs8-gemm/gen/qs8-gemm-4x8c4-minmax-rndnu-neon-mull-ld2r.c", |
| "src/qs8-gemm/gen/qs8-gemm-4x8c4s2-minmax-rndnu-neon-mlal.c", |
| "src/qs8-gemm/gen/qs8-gemm-4x8c4s2-minmax-rndnu-neon-mull.c", |
| "src/qs8-gemm/gen/qs8-gemm-4x8c8-minmax-rndnu-neon-mlal.c", |
| "src/qs8-gemm/gen/qs8-gemm-4x8c8-minmax-rndnu-neon-mull.c", |
| "src/qs8-gemm/gen/qs8-gemm-4x8c16-minmax-rndnu-neon-mlal.c", |
| "src/qs8-gemm/gen/qs8-gemm-4x16-minmax-fp32-neon-mlal-lane.c", |
| "src/qs8-gemm/gen/qs8-gemm-4x16-minmax-rndnu-neon-mlal-lane-prfm.c", |
| "src/qs8-gemm/gen/qs8-gemm-4x16-minmax-rndnu-neon-mlal-lane.c", |
| "src/qs8-gemm/gen/qs8-gemm-4x16-minmax-rndnu-neon-mull-addw-dup.c", |
| "src/qs8-gemm/gen/qs8-gemm-4x16c2-minmax-rndnu-neon-mlal-dup.c", |
| "src/qs8-gemm/gen/qs8-gemm-4x16c2-minmax-rndnu-neon-mlal-ld1r.c", |
| "src/qs8-gemm/gen/qs8-gemm-4x16c2-minmax-rndnu-neon-mlal-ld2r.c", |
| "src/qs8-gemm/gen/qs8-gemm-4x16c2-minmax-rndnu-neon-mlal-ld4r.c", |
| "src/qs8-gemm/gen/qs8-gemm-4x16c2-minmax-rndnu-neon-mull-dup.c", |
| "src/qs8-gemm/gen/qs8-gemm-4x16c2-minmax-rndnu-neon-mull-ld1r.c", |
| "src/qs8-gemm/gen/qs8-gemm-4x16c2-minmax-rndnu-neon-mull-ld2r.c", |
| "src/qs8-gemm/gen/qs8-gemm-4x16c2-minmax-rndnu-neon-mull-ld4r.c", |
| "src/qs8-gemm/gen/qs8-gemm-4x16c2s4-minmax-rndnu-neon-mlal.c", |
| "src/qs8-gemm/gen/qs8-gemm-4x16c2s4-minmax-rndnu-neon-mull.c", |
| "src/qs8-gemm/gen/qs8-gemm-4x16c4-minmax-rndnu-neon-mlal-dup.c", |
| "src/qs8-gemm/gen/qs8-gemm-4x16c4-minmax-rndnu-neon-mlal-ld1r.c", |
| "src/qs8-gemm/gen/qs8-gemm-4x16c4-minmax-rndnu-neon-mlal-ld2r.c", |
| "src/qs8-gemm/gen/qs8-gemm-4x16c4-minmax-rndnu-neon-mull-dup.c", |
| "src/qs8-gemm/gen/qs8-gemm-4x16c4-minmax-rndnu-neon-mull-ld1r.c", |
| "src/qs8-gemm/gen/qs8-gemm-4x16c4-minmax-rndnu-neon-mull-ld2r.c", |
| "src/qs8-gemm/gen/qs8-gemm-4x16c4s2-minmax-rndnu-neon-mlal.c", |
| "src/qs8-gemm/gen/qs8-gemm-4x16c4s2-minmax-rndnu-neon-mull.c", |
| "src/qs8-gemm/gen/qs8-gemm-4x16c8-minmax-rndnu-neon-mlal.c", |
| "src/qs8-gemm/gen/qs8-gemm-4x16c8-minmax-rndnu-neon-mull.c", |
| "src/qs8-gemm/gen/qs8-gemm-4x16c16-minmax-rndnu-neon-mlal.c", |
| "src/qs8-gemm/gen/qs8-gemm-6x8-minmax-rndnu-neon-mlal-lane-prfm.c", |
| "src/qs8-gemm/gen/qs8-gemm-6x8-minmax-rndnu-neon-mlal-lane.c", |
| "src/qs8-gemm/gen/qs8-gemm-6x16-minmax-rndnu-neon-mlal-lane-prfm.c", |
| "src/qs8-gemm/gen/qs8-gemm-6x16-minmax-rndnu-neon-mlal-lane.c", |
| "src/qs8-igemm/gen/qs8-igemm-1x8-minmax-rndnu-neon-mlal-lane-prfm.c", |
| "src/qs8-igemm/gen/qs8-igemm-1x8-minmax-rndnu-neon-mlal-lane.c", |
| "src/qs8-igemm/gen/qs8-igemm-1x8-minmax-rndnu-neon-mull-addw-dup.c", |
| "src/qs8-igemm/gen/qs8-igemm-1x8c2-minmax-fp32-neon-mlal-dup.c", |
| "src/qs8-igemm/gen/qs8-igemm-1x8c2-minmax-fp32-neon-mlal-ld1r.c", |
| "src/qs8-igemm/gen/qs8-igemm-1x8c2-minmax-fp32-neon-mlal-ld2r.c", |
| "src/qs8-igemm/gen/qs8-igemm-1x8c2-minmax-fp32-neon-mlal-ld4r.c", |
| "src/qs8-igemm/gen/qs8-igemm-1x8c2-minmax-rndnu-neon-mlal-dup.c", |
| "src/qs8-igemm/gen/qs8-igemm-1x8c2-minmax-rndnu-neon-mlal-ld1r.c", |
| "src/qs8-igemm/gen/qs8-igemm-1x8c2-minmax-rndnu-neon-mlal-ld2r.c", |
| "src/qs8-igemm/gen/qs8-igemm-1x8c2-minmax-rndnu-neon-mlal-ld4r.c", |
| "src/qs8-igemm/gen/qs8-igemm-1x8c2-minmax-rndnu-neon-mull-dup.c", |
| "src/qs8-igemm/gen/qs8-igemm-1x8c2-minmax-rndnu-neon-mull-ld1r.c", |
| "src/qs8-igemm/gen/qs8-igemm-1x8c2-minmax-rndnu-neon-mull-ld2r.c", |
| "src/qs8-igemm/gen/qs8-igemm-1x8c2-minmax-rndnu-neon-mull-ld4r.c", |
| "src/qs8-igemm/gen/qs8-igemm-1x8c2s4-minmax-fp32-neon-mlal.c", |
| "src/qs8-igemm/gen/qs8-igemm-1x8c2s4-minmax-rndnu-neon-mlal.c", |
| "src/qs8-igemm/gen/qs8-igemm-1x8c2s4-minmax-rndnu-neon-mull.c", |
| "src/qs8-igemm/gen/qs8-igemm-1x8c4-minmax-fp32-neon-mlal-dup.c", |
| "src/qs8-igemm/gen/qs8-igemm-1x8c4-minmax-fp32-neon-mlal-ld1r.c", |
| "src/qs8-igemm/gen/qs8-igemm-1x8c4-minmax-fp32-neon-mlal-ld2r.c", |
| "src/qs8-igemm/gen/qs8-igemm-1x8c4-minmax-rndnu-neon-mlal-dup.c", |
| "src/qs8-igemm/gen/qs8-igemm-1x8c4-minmax-rndnu-neon-mlal-ld1r.c", |
| "src/qs8-igemm/gen/qs8-igemm-1x8c4-minmax-rndnu-neon-mlal-ld2r.c", |
| "src/qs8-igemm/gen/qs8-igemm-1x8c4-minmax-rndnu-neon-mull-dup.c", |
| "src/qs8-igemm/gen/qs8-igemm-1x8c4-minmax-rndnu-neon-mull-ld1r.c", |
| "src/qs8-igemm/gen/qs8-igemm-1x8c4-minmax-rndnu-neon-mull-ld2r.c", |
| "src/qs8-igemm/gen/qs8-igemm-1x8c4s2-minmax-fp32-neon-mlal.c", |
| "src/qs8-igemm/gen/qs8-igemm-1x8c4s2-minmax-rndnu-neon-mlal.c", |
| "src/qs8-igemm/gen/qs8-igemm-1x8c4s2-minmax-rndnu-neon-mull.c", |
| "src/qs8-igemm/gen/qs8-igemm-1x8c8-minmax-fp32-neon-mlal.c", |
| "src/qs8-igemm/gen/qs8-igemm-1x8c8-minmax-rndnu-neon-mlal.c", |
| "src/qs8-igemm/gen/qs8-igemm-1x8c8-minmax-rndnu-neon-mull.c", |
| "src/qs8-igemm/gen/qs8-igemm-1x8c16-minmax-rndnu-neon-mlal.c", |
| "src/qs8-igemm/gen/qs8-igemm-1x16-minmax-fp32-neon-mlal-lane.c", |
| "src/qs8-igemm/gen/qs8-igemm-1x16-minmax-rndnu-neon-mlal-lane-prfm.c", |
| "src/qs8-igemm/gen/qs8-igemm-1x16-minmax-rndnu-neon-mlal-lane.c", |
| "src/qs8-igemm/gen/qs8-igemm-1x16-minmax-rndnu-neon-mull-addw-dup.c", |
| "src/qs8-igemm/gen/qs8-igemm-1x16c2-minmax-rndnu-neon-mlal-dup.c", |
| "src/qs8-igemm/gen/qs8-igemm-1x16c2-minmax-rndnu-neon-mlal-ld1r.c", |
| "src/qs8-igemm/gen/qs8-igemm-1x16c2-minmax-rndnu-neon-mlal-ld2r.c", |
| "src/qs8-igemm/gen/qs8-igemm-1x16c2-minmax-rndnu-neon-mlal-ld4r.c", |
| "src/qs8-igemm/gen/qs8-igemm-1x16c2-minmax-rndnu-neon-mull-dup.c", |
| "src/qs8-igemm/gen/qs8-igemm-1x16c2-minmax-rndnu-neon-mull-ld1r.c", |
| "src/qs8-igemm/gen/qs8-igemm-1x16c2-minmax-rndnu-neon-mull-ld2r.c", |
| "src/qs8-igemm/gen/qs8-igemm-1x16c2-minmax-rndnu-neon-mull-ld4r.c", |
| "src/qs8-igemm/gen/qs8-igemm-1x16c2s4-minmax-rndnu-neon-mlal.c", |
| "src/qs8-igemm/gen/qs8-igemm-1x16c2s4-minmax-rndnu-neon-mull.c", |
| "src/qs8-igemm/gen/qs8-igemm-1x16c4-minmax-rndnu-neon-mlal-dup.c", |
| "src/qs8-igemm/gen/qs8-igemm-1x16c4-minmax-rndnu-neon-mlal-ld1r.c", |
| "src/qs8-igemm/gen/qs8-igemm-1x16c4-minmax-rndnu-neon-mlal-ld2r.c", |
| "src/qs8-igemm/gen/qs8-igemm-1x16c4-minmax-rndnu-neon-mull-dup.c", |
| "src/qs8-igemm/gen/qs8-igemm-1x16c4-minmax-rndnu-neon-mull-ld1r.c", |
| "src/qs8-igemm/gen/qs8-igemm-1x16c4-minmax-rndnu-neon-mull-ld2r.c", |
| "src/qs8-igemm/gen/qs8-igemm-1x16c4s2-minmax-rndnu-neon-mlal.c", |
| "src/qs8-igemm/gen/qs8-igemm-1x16c4s2-minmax-rndnu-neon-mull.c", |
| "src/qs8-igemm/gen/qs8-igemm-1x16c8-minmax-rndnu-neon-mlal.c", |
| "src/qs8-igemm/gen/qs8-igemm-1x16c8-minmax-rndnu-neon-mull.c", |
| "src/qs8-igemm/gen/qs8-igemm-1x16c16-minmax-rndnu-neon-mlal.c", |
| "src/qs8-igemm/gen/qs8-igemm-2x8-minmax-rndnu-neon-mlal-lane-prfm.c", |
| "src/qs8-igemm/gen/qs8-igemm-2x8-minmax-rndnu-neon-mlal-lane.c", |
| "src/qs8-igemm/gen/qs8-igemm-2x8-minmax-rndnu-neon-mull-addw-dup.c", |
| "src/qs8-igemm/gen/qs8-igemm-2x8c2-minmax-fp32-neon-mlal-dup.c", |
| "src/qs8-igemm/gen/qs8-igemm-2x8c2-minmax-fp32-neon-mlal-ld1r.c", |
| "src/qs8-igemm/gen/qs8-igemm-2x8c2-minmax-fp32-neon-mlal-ld2r.c", |
| "src/qs8-igemm/gen/qs8-igemm-2x8c2-minmax-fp32-neon-mlal-ld4r.c", |
| "src/qs8-igemm/gen/qs8-igemm-2x8c2-minmax-rndnu-neon-mlal-dup.c", |
| "src/qs8-igemm/gen/qs8-igemm-2x8c2-minmax-rndnu-neon-mlal-ld1r.c", |
| "src/qs8-igemm/gen/qs8-igemm-2x8c2-minmax-rndnu-neon-mlal-ld2r.c", |
| "src/qs8-igemm/gen/qs8-igemm-2x8c2-minmax-rndnu-neon-mlal-ld4r.c", |
| "src/qs8-igemm/gen/qs8-igemm-2x8c2-minmax-rndnu-neon-mull-dup.c", |
| "src/qs8-igemm/gen/qs8-igemm-2x8c2-minmax-rndnu-neon-mull-ld1r.c", |
| "src/qs8-igemm/gen/qs8-igemm-2x8c2-minmax-rndnu-neon-mull-ld2r.c", |
| "src/qs8-igemm/gen/qs8-igemm-2x8c2-minmax-rndnu-neon-mull-ld4r.c", |
| "src/qs8-igemm/gen/qs8-igemm-2x8c2s4-minmax-fp32-neon-mlal.c", |
| "src/qs8-igemm/gen/qs8-igemm-2x8c2s4-minmax-rndnu-neon-mlal.c", |
| "src/qs8-igemm/gen/qs8-igemm-2x8c2s4-minmax-rndnu-neon-mull.c", |
| "src/qs8-igemm/gen/qs8-igemm-2x8c4-minmax-fp32-neon-mlal-dup.c", |
| "src/qs8-igemm/gen/qs8-igemm-2x8c4-minmax-fp32-neon-mlal-ld1r.c", |
| "src/qs8-igemm/gen/qs8-igemm-2x8c4-minmax-fp32-neon-mlal-ld2r.c", |
| "src/qs8-igemm/gen/qs8-igemm-2x8c4-minmax-rndnu-neon-mlal-dup.c", |
| "src/qs8-igemm/gen/qs8-igemm-2x8c4-minmax-rndnu-neon-mlal-ld1r.c", |
| "src/qs8-igemm/gen/qs8-igemm-2x8c4-minmax-rndnu-neon-mlal-ld2r.c", |
| "src/qs8-igemm/gen/qs8-igemm-2x8c4-minmax-rndnu-neon-mull-dup.c", |
| "src/qs8-igemm/gen/qs8-igemm-2x8c4-minmax-rndnu-neon-mull-ld1r.c", |
| "src/qs8-igemm/gen/qs8-igemm-2x8c4-minmax-rndnu-neon-mull-ld2r.c", |
| "src/qs8-igemm/gen/qs8-igemm-2x8c4s2-minmax-fp32-neon-mlal.c", |
| "src/qs8-igemm/gen/qs8-igemm-2x8c4s2-minmax-rndnu-neon-mlal.c", |
| "src/qs8-igemm/gen/qs8-igemm-2x8c4s2-minmax-rndnu-neon-mull.c", |
| "src/qs8-igemm/gen/qs8-igemm-2x8c8-minmax-fp32-neon-mlal.c", |
| "src/qs8-igemm/gen/qs8-igemm-2x8c8-minmax-rndnu-neon-mlal.c", |
| "src/qs8-igemm/gen/qs8-igemm-2x8c8-minmax-rndnu-neon-mull.c", |
| "src/qs8-igemm/gen/qs8-igemm-2x8c16-minmax-rndnu-neon-mlal.c", |
| "src/qs8-igemm/gen/qs8-igemm-2x16-minmax-rndnu-neon-mlal-lane-prfm.c", |
| "src/qs8-igemm/gen/qs8-igemm-2x16-minmax-rndnu-neon-mlal-lane.c", |
| "src/qs8-igemm/gen/qs8-igemm-2x16-minmax-rndnu-neon-mull-addw-dup.c", |
| "src/qs8-igemm/gen/qs8-igemm-2x16c2-minmax-rndnu-neon-mlal-dup.c", |
| "src/qs8-igemm/gen/qs8-igemm-2x16c2-minmax-rndnu-neon-mlal-ld1r.c", |
| "src/qs8-igemm/gen/qs8-igemm-2x16c2-minmax-rndnu-neon-mlal-ld2r.c", |
| "src/qs8-igemm/gen/qs8-igemm-2x16c2-minmax-rndnu-neon-mlal-ld4r.c", |
| "src/qs8-igemm/gen/qs8-igemm-2x16c2-minmax-rndnu-neon-mull-dup.c", |
| "src/qs8-igemm/gen/qs8-igemm-2x16c2-minmax-rndnu-neon-mull-ld1r.c", |
| "src/qs8-igemm/gen/qs8-igemm-2x16c2-minmax-rndnu-neon-mull-ld2r.c", |
| "src/qs8-igemm/gen/qs8-igemm-2x16c2-minmax-rndnu-neon-mull-ld4r.c", |
| "src/qs8-igemm/gen/qs8-igemm-2x16c2s4-minmax-rndnu-neon-mlal.c", |
| "src/qs8-igemm/gen/qs8-igemm-2x16c2s4-minmax-rndnu-neon-mull.c", |
| "src/qs8-igemm/gen/qs8-igemm-2x16c4-minmax-rndnu-neon-mlal-dup.c", |
| "src/qs8-igemm/gen/qs8-igemm-2x16c4-minmax-rndnu-neon-mlal-ld1r.c", |
| "src/qs8-igemm/gen/qs8-igemm-2x16c4-minmax-rndnu-neon-mlal-ld2r.c", |
| "src/qs8-igemm/gen/qs8-igemm-2x16c4-minmax-rndnu-neon-mull-dup.c", |
| "src/qs8-igemm/gen/qs8-igemm-2x16c4-minmax-rndnu-neon-mull-ld1r.c", |
| "src/qs8-igemm/gen/qs8-igemm-2x16c4-minmax-rndnu-neon-mull-ld2r.c", |
| "src/qs8-igemm/gen/qs8-igemm-2x16c4s2-minmax-rndnu-neon-mlal.c", |
| "src/qs8-igemm/gen/qs8-igemm-2x16c4s2-minmax-rndnu-neon-mull.c", |
| "src/qs8-igemm/gen/qs8-igemm-2x16c8-minmax-rndnu-neon-mlal.c", |
| "src/qs8-igemm/gen/qs8-igemm-2x16c8-minmax-rndnu-neon-mull.c", |
| "src/qs8-igemm/gen/qs8-igemm-2x16c16-minmax-rndnu-neon-mlal.c", |
| "src/qs8-igemm/gen/qs8-igemm-3x8-minmax-rndnu-neon-mlal-lane-prfm.c", |
| "src/qs8-igemm/gen/qs8-igemm-3x8-minmax-rndnu-neon-mlal-lane.c", |
| "src/qs8-igemm/gen/qs8-igemm-3x8-minmax-rndnu-neon-mull-addw-dup.c", |
| "src/qs8-igemm/gen/qs8-igemm-3x8c2-minmax-rndnu-neon-mlal-dup.c", |
| "src/qs8-igemm/gen/qs8-igemm-3x8c2-minmax-rndnu-neon-mlal-ld1r.c", |
| "src/qs8-igemm/gen/qs8-igemm-3x8c2-minmax-rndnu-neon-mlal-ld2r.c", |
| "src/qs8-igemm/gen/qs8-igemm-3x8c2-minmax-rndnu-neon-mlal-ld4r.c", |
| "src/qs8-igemm/gen/qs8-igemm-3x8c2-minmax-rndnu-neon-mull-dup.c", |
| "src/qs8-igemm/gen/qs8-igemm-3x8c2-minmax-rndnu-neon-mull-ld1r.c", |
| "src/qs8-igemm/gen/qs8-igemm-3x8c2-minmax-rndnu-neon-mull-ld2r.c", |
| "src/qs8-igemm/gen/qs8-igemm-3x8c2-minmax-rndnu-neon-mull-ld4r.c", |
| "src/qs8-igemm/gen/qs8-igemm-3x8c2s4-minmax-rndnu-neon-mlal.c", |
| "src/qs8-igemm/gen/qs8-igemm-3x8c2s4-minmax-rndnu-neon-mull.c", |
| "src/qs8-igemm/gen/qs8-igemm-3x8c4-minmax-rndnu-neon-mlal-dup.c", |
| "src/qs8-igemm/gen/qs8-igemm-3x8c4-minmax-rndnu-neon-mlal-ld1r.c", |
| "src/qs8-igemm/gen/qs8-igemm-3x8c4-minmax-rndnu-neon-mlal-ld2r.c", |
| "src/qs8-igemm/gen/qs8-igemm-3x8c4-minmax-rndnu-neon-mull-dup.c", |
| "src/qs8-igemm/gen/qs8-igemm-3x8c4-minmax-rndnu-neon-mull-ld1r.c", |
| "src/qs8-igemm/gen/qs8-igemm-3x8c4-minmax-rndnu-neon-mull-ld2r.c", |
| "src/qs8-igemm/gen/qs8-igemm-3x8c4s2-minmax-rndnu-neon-mlal.c", |
| "src/qs8-igemm/gen/qs8-igemm-3x8c4s2-minmax-rndnu-neon-mull.c", |
| "src/qs8-igemm/gen/qs8-igemm-3x8c8-minmax-rndnu-neon-mlal.c", |
| "src/qs8-igemm/gen/qs8-igemm-3x8c8-minmax-rndnu-neon-mull.c", |
| "src/qs8-igemm/gen/qs8-igemm-3x8c16-minmax-rndnu-neon-mlal.c", |
| "src/qs8-igemm/gen/qs8-igemm-3x16-minmax-rndnu-neon-mlal-lane-prfm.c", |
| "src/qs8-igemm/gen/qs8-igemm-3x16-minmax-rndnu-neon-mlal-lane.c", |
| "src/qs8-igemm/gen/qs8-igemm-3x16-minmax-rndnu-neon-mull-addw-dup.c", |
| "src/qs8-igemm/gen/qs8-igemm-3x16c2-minmax-rndnu-neon-mlal-dup.c", |
| "src/qs8-igemm/gen/qs8-igemm-3x16c2-minmax-rndnu-neon-mlal-ld1r.c", |
| "src/qs8-igemm/gen/qs8-igemm-3x16c2-minmax-rndnu-neon-mlal-ld2r.c", |
| "src/qs8-igemm/gen/qs8-igemm-3x16c2-minmax-rndnu-neon-mlal-ld4r.c", |
| "src/qs8-igemm/gen/qs8-igemm-3x16c2-minmax-rndnu-neon-mull-dup.c", |
| "src/qs8-igemm/gen/qs8-igemm-3x16c2-minmax-rndnu-neon-mull-ld1r.c", |
| "src/qs8-igemm/gen/qs8-igemm-3x16c2-minmax-rndnu-neon-mull-ld2r.c", |
| "src/qs8-igemm/gen/qs8-igemm-3x16c2-minmax-rndnu-neon-mull-ld4r.c", |
| "src/qs8-igemm/gen/qs8-igemm-3x16c2s4-minmax-rndnu-neon-mlal.c", |
| "src/qs8-igemm/gen/qs8-igemm-3x16c2s4-minmax-rndnu-neon-mull.c", |
| "src/qs8-igemm/gen/qs8-igemm-3x16c4-minmax-rndnu-neon-mlal-dup.c", |
| "src/qs8-igemm/gen/qs8-igemm-3x16c4-minmax-rndnu-neon-mlal-ld1r.c", |
| "src/qs8-igemm/gen/qs8-igemm-3x16c4-minmax-rndnu-neon-mlal-ld2r.c", |
| "src/qs8-igemm/gen/qs8-igemm-3x16c4-minmax-rndnu-neon-mull-dup.c", |
| "src/qs8-igemm/gen/qs8-igemm-3x16c4-minmax-rndnu-neon-mull-ld1r.c", |
| "src/qs8-igemm/gen/qs8-igemm-3x16c4-minmax-rndnu-neon-mull-ld2r.c", |
| "src/qs8-igemm/gen/qs8-igemm-3x16c4s2-minmax-rndnu-neon-mlal.c", |
| "src/qs8-igemm/gen/qs8-igemm-3x16c4s2-minmax-rndnu-neon-mull.c", |
| "src/qs8-igemm/gen/qs8-igemm-3x16c8-minmax-rndnu-neon-mlal.c", |
| "src/qs8-igemm/gen/qs8-igemm-3x16c8-minmax-rndnu-neon-mull.c", |
| "src/qs8-igemm/gen/qs8-igemm-3x16c16-minmax-rndnu-neon-mlal.c", |
| "src/qs8-igemm/gen/qs8-igemm-4x8-minmax-rndnu-neon-mlal-lane-prfm.c", |
| "src/qs8-igemm/gen/qs8-igemm-4x8-minmax-rndnu-neon-mlal-lane.c", |
| "src/qs8-igemm/gen/qs8-igemm-4x8-minmax-rndnu-neon-mull-addw-dup.c", |
| "src/qs8-igemm/gen/qs8-igemm-4x8c2-minmax-rndnu-neon-mlal-dup.c", |
| "src/qs8-igemm/gen/qs8-igemm-4x8c2-minmax-rndnu-neon-mlal-ld1r.c", |
| "src/qs8-igemm/gen/qs8-igemm-4x8c2-minmax-rndnu-neon-mlal-ld2r.c", |
| "src/qs8-igemm/gen/qs8-igemm-4x8c2-minmax-rndnu-neon-mlal-ld4r.c", |
| "src/qs8-igemm/gen/qs8-igemm-4x8c2-minmax-rndnu-neon-mull-dup.c", |
| "src/qs8-igemm/gen/qs8-igemm-4x8c2-minmax-rndnu-neon-mull-ld1r.c", |
| "src/qs8-igemm/gen/qs8-igemm-4x8c2-minmax-rndnu-neon-mull-ld2r.c", |
| "src/qs8-igemm/gen/qs8-igemm-4x8c2-minmax-rndnu-neon-mull-ld4r.c", |
| "src/qs8-igemm/gen/qs8-igemm-4x8c2s4-minmax-rndnu-neon-mlal.c", |
| "src/qs8-igemm/gen/qs8-igemm-4x8c2s4-minmax-rndnu-neon-mull.c", |
| "src/qs8-igemm/gen/qs8-igemm-4x8c4-minmax-rndnu-neon-mlal-dup.c", |
| "src/qs8-igemm/gen/qs8-igemm-4x8c4-minmax-rndnu-neon-mlal-ld1r.c", |
| "src/qs8-igemm/gen/qs8-igemm-4x8c4-minmax-rndnu-neon-mlal-ld2r.c", |
| "src/qs8-igemm/gen/qs8-igemm-4x8c4-minmax-rndnu-neon-mull-dup.c", |
| "src/qs8-igemm/gen/qs8-igemm-4x8c4-minmax-rndnu-neon-mull-ld1r.c", |
| "src/qs8-igemm/gen/qs8-igemm-4x8c4-minmax-rndnu-neon-mull-ld2r.c", |
| "src/qs8-igemm/gen/qs8-igemm-4x8c4s2-minmax-rndnu-neon-mlal.c", |
| "src/qs8-igemm/gen/qs8-igemm-4x8c4s2-minmax-rndnu-neon-mull.c", |
| "src/qs8-igemm/gen/qs8-igemm-4x8c8-minmax-rndnu-neon-mlal.c", |
| "src/qs8-igemm/gen/qs8-igemm-4x8c8-minmax-rndnu-neon-mull.c", |
| "src/qs8-igemm/gen/qs8-igemm-4x8c16-minmax-rndnu-neon-mlal.c", |
| "src/qs8-igemm/gen/qs8-igemm-4x16-minmax-fp32-neon-mlal-lane.c", |
| "src/qs8-igemm/gen/qs8-igemm-4x16-minmax-rndnu-neon-mlal-lane-prfm.c", |
| "src/qs8-igemm/gen/qs8-igemm-4x16-minmax-rndnu-neon-mlal-lane.c", |
| "src/qs8-igemm/gen/qs8-igemm-4x16-minmax-rndnu-neon-mull-addw-dup.c", |
| "src/qs8-igemm/gen/qs8-igemm-4x16c2-minmax-rndnu-neon-mlal-dup.c", |
| "src/qs8-igemm/gen/qs8-igemm-4x16c2-minmax-rndnu-neon-mlal-ld1r.c", |
| "src/qs8-igemm/gen/qs8-igemm-4x16c2-minmax-rndnu-neon-mlal-ld2r.c", |
| "src/qs8-igemm/gen/qs8-igemm-4x16c2-minmax-rndnu-neon-mlal-ld4r.c", |
| "src/qs8-igemm/gen/qs8-igemm-4x16c2-minmax-rndnu-neon-mull-dup.c", |
| "src/qs8-igemm/gen/qs8-igemm-4x16c2-minmax-rndnu-neon-mull-ld1r.c", |
| "src/qs8-igemm/gen/qs8-igemm-4x16c2-minmax-rndnu-neon-mull-ld2r.c", |
| "src/qs8-igemm/gen/qs8-igemm-4x16c2-minmax-rndnu-neon-mull-ld4r.c", |
| "src/qs8-igemm/gen/qs8-igemm-4x16c2s4-minmax-rndnu-neon-mlal.c", |
| "src/qs8-igemm/gen/qs8-igemm-4x16c2s4-minmax-rndnu-neon-mull.c", |
| "src/qs8-igemm/gen/qs8-igemm-4x16c4-minmax-rndnu-neon-mlal-dup.c", |
| "src/qs8-igemm/gen/qs8-igemm-4x16c4-minmax-rndnu-neon-mlal-ld1r.c", |
| "src/qs8-igemm/gen/qs8-igemm-4x16c4-minmax-rndnu-neon-mlal-ld2r.c", |
| "src/qs8-igemm/gen/qs8-igemm-4x16c4-minmax-rndnu-neon-mull-dup.c", |
| "src/qs8-igemm/gen/qs8-igemm-4x16c4-minmax-rndnu-neon-mull-ld1r.c", |
| "src/qs8-igemm/gen/qs8-igemm-4x16c4-minmax-rndnu-neon-mull-ld2r.c", |
| "src/qs8-igemm/gen/qs8-igemm-4x16c4s2-minmax-rndnu-neon-mlal.c", |
| "src/qs8-igemm/gen/qs8-igemm-4x16c4s2-minmax-rndnu-neon-mull.c", |
| "src/qs8-igemm/gen/qs8-igemm-4x16c8-minmax-rndnu-neon-mlal.c", |
| "src/qs8-igemm/gen/qs8-igemm-4x16c8-minmax-rndnu-neon-mull.c", |
| "src/qs8-igemm/gen/qs8-igemm-4x16c16-minmax-rndnu-neon-mlal.c", |
| "src/qs8-igemm/gen/qs8-igemm-6x8-minmax-rndnu-neon-mlal-lane-prfm.c", |
| "src/qs8-igemm/gen/qs8-igemm-6x8-minmax-rndnu-neon-mlal-lane.c", |
| "src/qs8-igemm/gen/qs8-igemm-6x16-minmax-rndnu-neon-mlal-lane-prfm.c", |
| "src/qs8-igemm/gen/qs8-igemm-6x16-minmax-rndnu-neon-mlal-lane.c", |
| "src/qs8-qc8w-dwconv/gen/qs8-qc8w-dwconv-3p8c-minmax-fp32-neon-mla8-ld64.c", |
| "src/qs8-qc8w-dwconv/gen/qs8-qc8w-dwconv-3p16c-minmax-fp32-neon-mla8-ld64.c", |
| "src/qs8-qc8w-dwconv/gen/qs8-qc8w-dwconv-3p16c-minmax-fp32-neon-mla8-ld128.c", |
| "src/qs8-qc8w-dwconv/gen/qs8-qc8w-dwconv-4p8c-minmax-fp32-neon-mla8-ld64.c", |
| "src/qs8-qc8w-dwconv/gen/qs8-qc8w-dwconv-5f5m5l8c8s8r-minmax-fp32-neon-mla8-ld64.c", |
| "src/qs8-qc8w-dwconv/gen/qs8-qc8w-dwconv-5f5m5l8c8s8r-minmax-fp32-neon-mul8-ld64.c", |
| "src/qs8-qc8w-dwconv/gen/qs8-qc8w-dwconv-5f5m5l8c8s8r-minmax-fp32-neon-mul16.c", |
| "src/qs8-qc8w-dwconv/gen/qs8-qc8w-dwconv-5f5m5l16c8s8r-minmax-fp32-neon-mla8-ld64.c", |
| "src/qs8-qc8w-dwconv/gen/qs8-qc8w-dwconv-5f5m5l16c8s8r-minmax-fp32-neon-mla8-ld128.c", |
| "src/qs8-qc8w-dwconv/gen/qs8-qc8w-dwconv-5f5m5l16c8s8r-minmax-fp32-neon-mul8-ld64.c", |
| "src/qs8-qc8w-dwconv/gen/qs8-qc8w-dwconv-5f5m5l16c8s8r-minmax-fp32-neon-mul8-ld128.c", |
| "src/qs8-qc8w-dwconv/gen/qs8-qc8w-dwconv-5f5m5l16c8s8r-minmax-fp32-neon-mul16.c", |
| "src/qs8-qc8w-dwconv/gen/qs8-qc8w-dwconv-5f5m5l32c8s8r-minmax-fp32-neon-mul16.c", |
| "src/qs8-qc8w-dwconv/gen/qs8-qc8w-dwconv-6f6m7l8c8s8r-minmax-fp32-neon-mla8-ld64.c", |
| "src/qs8-qc8w-dwconv/gen/qs8-qc8w-dwconv-6f6m7l8c8s8r-minmax-fp32-neon-mul8-ld64.c", |
| "src/qs8-qc8w-dwconv/gen/qs8-qc8w-dwconv-6f6m7l8c8s8r-minmax-fp32-neon-mul16.c", |
| "src/qs8-qc8w-dwconv/gen/qs8-qc8w-dwconv-6f6m7l16c8s8r-minmax-fp32-neon-mla8-ld64.c", |
| "src/qs8-qc8w-dwconv/gen/qs8-qc8w-dwconv-6f6m7l16c8s8r-minmax-fp32-neon-mla8-ld128.c", |
| "src/qs8-qc8w-dwconv/gen/qs8-qc8w-dwconv-6f6m7l16c8s8r-minmax-fp32-neon-mul8-ld64.c", |
| "src/qs8-qc8w-dwconv/gen/qs8-qc8w-dwconv-6f6m7l16c8s8r-minmax-fp32-neon-mul8-ld128.c", |
| "src/qs8-qc8w-dwconv/gen/qs8-qc8w-dwconv-6f6m7l16c8s8r-minmax-fp32-neon-mul16.c", |
| "src/qs8-qc8w-dwconv/gen/qs8-qc8w-dwconv-6f6m7l32c8s8r-minmax-fp32-neon-mul16.c", |
| "src/qs8-qc8w-dwconv/gen/qs8-qc8w-dwconv-8f8m9l8c8s8r-minmax-fp32-neon-mla8-ld64.c", |
| "src/qs8-qc8w-dwconv/gen/qs8-qc8w-dwconv-8f8m9l8c8s8r-minmax-fp32-neon-mul8-ld64.c", |
| "src/qs8-qc8w-dwconv/gen/qs8-qc8w-dwconv-8f8m9l8c8s8r-minmax-fp32-neon-mul16.c", |
| "src/qs8-qc8w-dwconv/gen/qs8-qc8w-dwconv-8f8m9l16c8s8r-minmax-fp32-neon-mla8-ld64.c", |
| "src/qs8-qc8w-dwconv/gen/qs8-qc8w-dwconv-8f8m9l16c8s8r-minmax-fp32-neon-mla8-ld128.c", |
| "src/qs8-qc8w-dwconv/gen/qs8-qc8w-dwconv-8f8m9l16c8s8r-minmax-fp32-neon-mul8-ld64.c", |
| "src/qs8-qc8w-dwconv/gen/qs8-qc8w-dwconv-8f8m9l16c8s8r-minmax-fp32-neon-mul8-ld128.c", |
| "src/qs8-qc8w-dwconv/gen/qs8-qc8w-dwconv-8f8m9l16c8s8r-minmax-fp32-neon-mul16.c", |
| "src/qs8-qc8w-dwconv/gen/qs8-qc8w-dwconv-8f8m9l32c8s8r-minmax-fp32-neon-mul16.c", |
| "src/qs8-qc8w-dwconv/gen/qs8-qc8w-dwconv-9p8c-minmax-fp32-neon-mla8-ld64.c", |
| "src/qs8-qc8w-dwconv/gen/qs8-qc8w-dwconv-9p8c-minmax-fp32-neon-mul8-ld64.c", |
| "src/qs8-qc8w-dwconv/gen/qs8-qc8w-dwconv-9p8c-minmax-fp32-neon-mul16.c", |
| "src/qs8-qc8w-dwconv/gen/qs8-qc8w-dwconv-9p16c-minmax-fp32-neon-mla8-ld64.c", |
| "src/qs8-qc8w-dwconv/gen/qs8-qc8w-dwconv-9p16c-minmax-fp32-neon-mla8-ld128.c", |
| "src/qs8-qc8w-dwconv/gen/qs8-qc8w-dwconv-9p16c-minmax-fp32-neon-mul8-ld64.c", |
| "src/qs8-qc8w-dwconv/gen/qs8-qc8w-dwconv-9p16c-minmax-fp32-neon-mul8-ld128.c", |
| "src/qs8-qc8w-dwconv/gen/qs8-qc8w-dwconv-9p16c-minmax-fp32-neon-mul16.c", |
| "src/qs8-qc8w-dwconv/gen/qs8-qc8w-dwconv-9p32c-minmax-fp32-neon-mul16.c", |
| "src/qs8-qc8w-dwconv/gen/qs8-qc8w-dwconv-25p8c-minmax-fp32-neon-mla8-ld64.c", |
| "src/qs8-qc8w-dwconv/gen/qs8-qc8w-dwconv-25p8c-minmax-fp32-neon-mul8-ld64.c", |
| "src/qs8-qc8w-dwconv/gen/qs8-qc8w-dwconv-25p8c-minmax-fp32-neon-mul16.c", |
| "src/qs8-qc8w-dwconv/gen/qs8-qc8w-dwconv-25p16c-minmax-fp32-neon-mla8-ld64.c", |
| "src/qs8-qc8w-dwconv/gen/qs8-qc8w-dwconv-25p16c-minmax-fp32-neon-mla8-ld128.c", |
| "src/qs8-qc8w-dwconv/gen/qs8-qc8w-dwconv-25p16c-minmax-fp32-neon-mul8-ld64.c", |
| "src/qs8-qc8w-dwconv/gen/qs8-qc8w-dwconv-25p16c-minmax-fp32-neon-mul8-ld128.c", |
| "src/qs8-qc8w-dwconv/gen/qs8-qc8w-dwconv-25p16c-minmax-fp32-neon-mul16.c", |
| "src/qs8-qc8w-dwconv/gen/qs8-qc8w-dwconv-25p32c-minmax-fp32-neon-mul16.c", |
| "src/qs8-qc8w-gemm/gen/qs8-qc8w-gemm-1x8-minmax-fp32-neon-mlal-lane-prfm.c", |
| "src/qs8-qc8w-gemm/gen/qs8-qc8w-gemm-1x8-minmax-fp32-neon-mlal-lane.c", |
| "src/qs8-qc8w-gemm/gen/qs8-qc8w-gemm-1x8c2-minmax-fp32-neon-mlal-dup.c", |
| "src/qs8-qc8w-gemm/gen/qs8-qc8w-gemm-1x8c2-minmax-fp32-neon-mlal-ld1r.c", |
| "src/qs8-qc8w-gemm/gen/qs8-qc8w-gemm-1x8c2-minmax-fp32-neon-mlal-ld2r.c", |
| "src/qs8-qc8w-gemm/gen/qs8-qc8w-gemm-1x8c2-minmax-fp32-neon-mlal-ld4r.c", |
| "src/qs8-qc8w-gemm/gen/qs8-qc8w-gemm-1x8c2s4-minmax-fp32-neon-mlal.c", |
| "src/qs8-qc8w-gemm/gen/qs8-qc8w-gemm-1x8c4-minmax-fp32-neon-mlal-dup.c", |
| "src/qs8-qc8w-gemm/gen/qs8-qc8w-gemm-1x8c4-minmax-fp32-neon-mlal-ld1r.c", |
| "src/qs8-qc8w-gemm/gen/qs8-qc8w-gemm-1x8c4-minmax-fp32-neon-mlal-ld2r.c", |
| "src/qs8-qc8w-gemm/gen/qs8-qc8w-gemm-1x8c4s2-minmax-fp32-neon-mlal.c", |
| "src/qs8-qc8w-gemm/gen/qs8-qc8w-gemm-1x8c8-minmax-fp32-neon-mlal.c", |
| "src/qs8-qc8w-gemm/gen/qs8-qc8w-gemm-1x16-minmax-fp32-neon-mlal-lane-prfm.c", |
| "src/qs8-qc8w-gemm/gen/qs8-qc8w-gemm-1x16-minmax-fp32-neon-mlal-lane.c", |
| "src/qs8-qc8w-gemm/gen/qs8-qc8w-gemm-2x8-minmax-fp32-neon-mlal-lane-prfm.c", |
| "src/qs8-qc8w-gemm/gen/qs8-qc8w-gemm-2x8-minmax-fp32-neon-mlal-lane.c", |
| "src/qs8-qc8w-gemm/gen/qs8-qc8w-gemm-2x8c2-minmax-fp32-neon-mlal-dup.c", |
| "src/qs8-qc8w-gemm/gen/qs8-qc8w-gemm-2x8c2-minmax-fp32-neon-mlal-ld1r.c", |
| "src/qs8-qc8w-gemm/gen/qs8-qc8w-gemm-2x8c2-minmax-fp32-neon-mlal-ld2r.c", |
| "src/qs8-qc8w-gemm/gen/qs8-qc8w-gemm-2x8c2-minmax-fp32-neon-mlal-ld4r.c", |
| "src/qs8-qc8w-gemm/gen/qs8-qc8w-gemm-2x8c2s4-minmax-fp32-neon-mlal.c", |
| "src/qs8-qc8w-gemm/gen/qs8-qc8w-gemm-2x8c4-minmax-fp32-neon-mlal-dup.c", |
| "src/qs8-qc8w-gemm/gen/qs8-qc8w-gemm-2x8c4-minmax-fp32-neon-mlal-ld1r.c", |
| "src/qs8-qc8w-gemm/gen/qs8-qc8w-gemm-2x8c4-minmax-fp32-neon-mlal-ld2r.c", |
| "src/qs8-qc8w-gemm/gen/qs8-qc8w-gemm-2x8c4s2-minmax-fp32-neon-mlal.c", |
| "src/qs8-qc8w-gemm/gen/qs8-qc8w-gemm-2x8c8-minmax-fp32-neon-mlal.c", |
| "src/qs8-qc8w-gemm/gen/qs8-qc8w-gemm-2x16-minmax-fp32-neon-mlal-lane-prfm.c", |
| "src/qs8-qc8w-gemm/gen/qs8-qc8w-gemm-2x16-minmax-fp32-neon-mlal-lane.c", |
| "src/qs8-qc8w-gemm/gen/qs8-qc8w-gemm-3x8-minmax-fp32-neon-mlal-lane-prfm.c", |
| "src/qs8-qc8w-gemm/gen/qs8-qc8w-gemm-3x8-minmax-fp32-neon-mlal-lane.c", |
| "src/qs8-qc8w-gemm/gen/qs8-qc8w-gemm-3x16-minmax-fp32-neon-mlal-lane-prfm.c", |
| "src/qs8-qc8w-gemm/gen/qs8-qc8w-gemm-3x16-minmax-fp32-neon-mlal-lane.c", |
| "src/qs8-qc8w-gemm/gen/qs8-qc8w-gemm-4x8-minmax-fp32-neon-mlal-lane-prfm.c", |
| "src/qs8-qc8w-gemm/gen/qs8-qc8w-gemm-4x8-minmax-fp32-neon-mlal-lane.c", |
| "src/qs8-qc8w-gemm/gen/qs8-qc8w-gemm-4x16-minmax-fp32-neon-mlal-lane-prfm.c", |
| "src/qs8-qc8w-gemm/gen/qs8-qc8w-gemm-4x16-minmax-fp32-neon-mlal-lane.c", |
| "src/qs8-qc8w-gemm/gen/qs8-qc8w-gemm-6x8-minmax-fp32-neon-mlal-lane-prfm.c", |
| "src/qs8-qc8w-gemm/gen/qs8-qc8w-gemm-6x8-minmax-fp32-neon-mlal-lane.c", |
| "src/qs8-qc8w-gemm/gen/qs8-qc8w-gemm-6x16-minmax-fp32-neon-mlal-lane-prfm.c", |
| "src/qs8-qc8w-gemm/gen/qs8-qc8w-gemm-6x16-minmax-fp32-neon-mlal-lane.c", |
| "src/qs8-qc8w-igemm/gen/qs8-qc8w-igemm-1x8-minmax-fp32-neon-mlal-lane-prfm.c", |
| "src/qs8-qc8w-igemm/gen/qs8-qc8w-igemm-1x8-minmax-fp32-neon-mlal-lane.c", |
| "src/qs8-qc8w-igemm/gen/qs8-qc8w-igemm-1x8c2-minmax-fp32-neon-mlal-dup.c", |
| "src/qs8-qc8w-igemm/gen/qs8-qc8w-igemm-1x8c2-minmax-fp32-neon-mlal-ld1r.c", |
| "src/qs8-qc8w-igemm/gen/qs8-qc8w-igemm-1x8c2-minmax-fp32-neon-mlal-ld2r.c", |
| "src/qs8-qc8w-igemm/gen/qs8-qc8w-igemm-1x8c2-minmax-fp32-neon-mlal-ld4r.c", |
| "src/qs8-qc8w-igemm/gen/qs8-qc8w-igemm-1x8c2s4-minmax-fp32-neon-mlal.c", |
| "src/qs8-qc8w-igemm/gen/qs8-qc8w-igemm-1x8c4-minmax-fp32-neon-mlal-dup.c", |
| "src/qs8-qc8w-igemm/gen/qs8-qc8w-igemm-1x8c4-minmax-fp32-neon-mlal-ld1r.c", |
| "src/qs8-qc8w-igemm/gen/qs8-qc8w-igemm-1x8c4-minmax-fp32-neon-mlal-ld2r.c", |
| "src/qs8-qc8w-igemm/gen/qs8-qc8w-igemm-1x8c4s2-minmax-fp32-neon-mlal.c", |
| "src/qs8-qc8w-igemm/gen/qs8-qc8w-igemm-1x8c8-minmax-fp32-neon-mlal.c", |
| "src/qs8-qc8w-igemm/gen/qs8-qc8w-igemm-1x16-minmax-fp32-neon-mlal-lane-prfm.c", |
| "src/qs8-qc8w-igemm/gen/qs8-qc8w-igemm-1x16-minmax-fp32-neon-mlal-lane.c", |
| "src/qs8-qc8w-igemm/gen/qs8-qc8w-igemm-2x8-minmax-fp32-neon-mlal-lane-prfm.c", |
| "src/qs8-qc8w-igemm/gen/qs8-qc8w-igemm-2x8-minmax-fp32-neon-mlal-lane.c", |
| "src/qs8-qc8w-igemm/gen/qs8-qc8w-igemm-2x8c2-minmax-fp32-neon-mlal-dup.c", |
| "src/qs8-qc8w-igemm/gen/qs8-qc8w-igemm-2x8c2-minmax-fp32-neon-mlal-ld1r.c", |
| "src/qs8-qc8w-igemm/gen/qs8-qc8w-igemm-2x8c2-minmax-fp32-neon-mlal-ld2r.c", |
| "src/qs8-qc8w-igemm/gen/qs8-qc8w-igemm-2x8c2-minmax-fp32-neon-mlal-ld4r.c", |
| "src/qs8-qc8w-igemm/gen/qs8-qc8w-igemm-2x8c2s4-minmax-fp32-neon-mlal.c", |
| "src/qs8-qc8w-igemm/gen/qs8-qc8w-igemm-2x8c4-minmax-fp32-neon-mlal-dup.c", |
| "src/qs8-qc8w-igemm/gen/qs8-qc8w-igemm-2x8c4-minmax-fp32-neon-mlal-ld1r.c", |
| "src/qs8-qc8w-igemm/gen/qs8-qc8w-igemm-2x8c4-minmax-fp32-neon-mlal-ld2r.c", |
| "src/qs8-qc8w-igemm/gen/qs8-qc8w-igemm-2x8c4s2-minmax-fp32-neon-mlal.c", |
| "src/qs8-qc8w-igemm/gen/qs8-qc8w-igemm-2x8c8-minmax-fp32-neon-mlal.c", |
| "src/qs8-qc8w-igemm/gen/qs8-qc8w-igemm-2x16-minmax-fp32-neon-mlal-lane-prfm.c", |
| "src/qs8-qc8w-igemm/gen/qs8-qc8w-igemm-2x16-minmax-fp32-neon-mlal-lane.c", |
| "src/qs8-qc8w-igemm/gen/qs8-qc8w-igemm-3x8-minmax-fp32-neon-mlal-lane-prfm.c", |
| "src/qs8-qc8w-igemm/gen/qs8-qc8w-igemm-3x8-minmax-fp32-neon-mlal-lane.c", |
| "src/qs8-qc8w-igemm/gen/qs8-qc8w-igemm-3x16-minmax-fp32-neon-mlal-lane-prfm.c", |
| "src/qs8-qc8w-igemm/gen/qs8-qc8w-igemm-3x16-minmax-fp32-neon-mlal-lane.c", |
| "src/qs8-qc8w-igemm/gen/qs8-qc8w-igemm-4x8-minmax-fp32-neon-mlal-lane-prfm.c", |
| "src/qs8-qc8w-igemm/gen/qs8-qc8w-igemm-4x8-minmax-fp32-neon-mlal-lane.c", |
| "src/qs8-qc8w-igemm/gen/qs8-qc8w-igemm-4x16-minmax-fp32-neon-mlal-lane-prfm.c", |
| "src/qs8-qc8w-igemm/gen/qs8-qc8w-igemm-4x16-minmax-fp32-neon-mlal-lane.c", |
| "src/qs8-qc8w-igemm/gen/qs8-qc8w-igemm-6x8-minmax-fp32-neon-mlal-lane-prfm.c", |
| "src/qs8-qc8w-igemm/gen/qs8-qc8w-igemm-6x8-minmax-fp32-neon-mlal-lane.c", |
| "src/qs8-qc8w-igemm/gen/qs8-qc8w-igemm-6x16-minmax-fp32-neon-mlal-lane-prfm.c", |
| "src/qs8-qc8w-igemm/gen/qs8-qc8w-igemm-6x16-minmax-fp32-neon-mlal-lane.c", |
| "src/qs8-requantization/qs8-requantization-fp32-neon.c", |
| "src/qs8-requantization/qs8-requantization-gemmlowp-neon.c", |
| "src/qs8-requantization/qs8-requantization-rndna-neon.c", |
| "src/qs8-requantization/qs8-requantization-rndnu-neon-mull.c", |
| "src/qs8-requantization/qs8-requantization-rndnu-neon-qdmulh.c", |
| "src/qs8-vadd/gen/qs8-vadd-minmax-neon-ld64-u8.c", |
| "src/qs8-vadd/gen/qs8-vadd-minmax-neon-ld64-u16.c", |
| "src/qs8-vadd/gen/qs8-vadd-minmax-neon-ld64-u24.c", |
| "src/qs8-vadd/gen/qs8-vadd-minmax-neon-ld64-u32.c", |
| "src/qs8-vadd/gen/qs8-vadd-minmax-neon-ld128-u16.c", |
| "src/qs8-vadd/gen/qs8-vadd-minmax-neon-ld128-u32.c", |
| "src/qs8-vaddc/gen/qs8-vaddc-minmax-neon-ld64-u8.c", |
| "src/qs8-vaddc/gen/qs8-vaddc-minmax-neon-ld64-u16.c", |
| "src/qs8-vaddc/gen/qs8-vaddc-minmax-neon-ld64-u24.c", |
| "src/qs8-vaddc/gen/qs8-vaddc-minmax-neon-ld64-u32.c", |
| "src/qs8-vaddc/gen/qs8-vaddc-minmax-neon-ld128-u16.c", |
| "src/qs8-vaddc/gen/qs8-vaddc-minmax-neon-ld128-u32.c", |
| "src/qs8-vcvt/gen/qs8-vcvt-neon-u8.c", |
| "src/qs8-vcvt/gen/qs8-vcvt-neon-u16.c", |
| "src/qs8-vcvt/gen/qs8-vcvt-neon-u32.c", |
| "src/qs8-vhswish/gen/qs8-vhswish-neon-u8.c", |
| "src/qs8-vhswish/gen/qs8-vhswish-neon-u16.c", |
| "src/qs8-vhswish/gen/qs8-vhswish-neon-u32.c", |
| "src/qs8-vhswish/gen/qs8-vhswish-neon-x8.c", |
| "src/qs8-vhswish/gen/qs8-vhswish-neon-x16.c", |
| "src/qs8-vhswish/gen/qs8-vhswish-neon-x32.c", |
| "src/qs8-vlrelu/gen/qs8-vlrelu-neon-u8.c", |
| "src/qs8-vlrelu/gen/qs8-vlrelu-neon-u16.c", |
| "src/qs8-vlrelu/gen/qs8-vlrelu-neon-u32.c", |
| "src/qs8-vmul/gen/qs8-vmul-minmax-fp32-neon-ld64-u8.c", |
| "src/qs8-vmul/gen/qs8-vmul-minmax-fp32-neon-ld64-u16.c", |
| "src/qs8-vmul/gen/qs8-vmul-minmax-fp32-neon-ld128-u16.c", |
| "src/qs8-vmul/gen/qs8-vmul-minmax-rndnu-neon-ld64-u8.c", |
| "src/qs8-vmul/gen/qs8-vmul-minmax-rndnu-neon-ld64-u16.c", |
| "src/qs8-vmul/gen/qs8-vmul-minmax-rndnu-neon-ld128-u16.c", |
| "src/qs8-vmulc/gen/qs8-vmulc-minmax-fp32-neon-ld64-u8.c", |
| "src/qs8-vmulc/gen/qs8-vmulc-minmax-fp32-neon-ld64-u16.c", |
| "src/qs8-vmulc/gen/qs8-vmulc-minmax-fp32-neon-ld128-u16.c", |
| "src/qs8-vmulc/gen/qs8-vmulc-minmax-rndnu-neon-ld64-u8.c", |
| "src/qs8-vmulc/gen/qs8-vmulc-minmax-rndnu-neon-ld64-u16.c", |
| "src/qs8-vmulc/gen/qs8-vmulc-minmax-rndnu-neon-ld128-u16.c", |
| "src/qs16-qs8-vcvt/gen/qs16-qs8-vcvt-neon-u8.c", |
| "src/qs16-qs8-vcvt/gen/qs16-qs8-vcvt-neon-u16.c", |
| "src/qs16-qs8-vcvt/gen/qs16-qs8-vcvt-neon-u32.c", |
| "src/qu8-avgpool/qu8-avgpool-9p8x-minmax-fp32-neon-c8.c", |
| "src/qu8-avgpool/qu8-avgpool-9x-minmax-fp32-neon-c8.c", |
| "src/qu8-dwconv/gen/qu8-dwconv-5f5m5l8c8s8r-minmax-fp32-neon-mul16.c", |
| "src/qu8-dwconv/gen/qu8-dwconv-5f5m5l8c8s8r-minmax-rndnu-neon-mul8.c", |
| "src/qu8-dwconv/gen/qu8-dwconv-5f5m5l8c8s8r-minmax-rndnu-neon-mul16.c", |
| "src/qu8-dwconv/gen/qu8-dwconv-5f5m5l16c8s8r-minmax-fp32-neon-mul16.c", |
| "src/qu8-dwconv/gen/qu8-dwconv-5f5m5l16c8s8r-minmax-rndnu-neon-mul8.c", |
| "src/qu8-dwconv/gen/qu8-dwconv-5f5m5l16c8s8r-minmax-rndnu-neon-mul16.c", |
| "src/qu8-dwconv/gen/qu8-dwconv-5f5m5l32c8s8r-minmax-fp32-neon-mul16.c", |
| "src/qu8-dwconv/gen/qu8-dwconv-5f5m5l32c8s8r-minmax-rndnu-neon-mul8.c", |
| "src/qu8-dwconv/gen/qu8-dwconv-5f5m5l32c8s8r-minmax-rndnu-neon-mul16.c", |
| "src/qu8-dwconv/gen/qu8-dwconv-6f6m7l8c8s8r-minmax-fp32-neon-mul16.c", |
| "src/qu8-dwconv/gen/qu8-dwconv-6f6m7l8c8s8r-minmax-rndnu-neon-mul8.c", |
| "src/qu8-dwconv/gen/qu8-dwconv-6f6m7l8c8s8r-minmax-rndnu-neon-mul16.c", |
| "src/qu8-dwconv/gen/qu8-dwconv-6f6m7l16c8s8r-minmax-fp32-neon-mul16.c", |
| "src/qu8-dwconv/gen/qu8-dwconv-6f6m7l16c8s8r-minmax-rndnu-neon-mul8.c", |
| "src/qu8-dwconv/gen/qu8-dwconv-6f6m7l16c8s8r-minmax-rndnu-neon-mul16.c", |
| "src/qu8-dwconv/gen/qu8-dwconv-6f6m7l32c8s8r-minmax-fp32-neon-mul16.c", |
| "src/qu8-dwconv/gen/qu8-dwconv-6f6m7l32c8s8r-minmax-rndnu-neon-mul8.c", |
| "src/qu8-dwconv/gen/qu8-dwconv-6f6m7l32c8s8r-minmax-rndnu-neon-mul16.c", |
| "src/qu8-dwconv/gen/qu8-dwconv-8f8m9l8c8s8r-minmax-fp32-neon-mul16.c", |
| "src/qu8-dwconv/gen/qu8-dwconv-8f8m9l8c8s8r-minmax-rndnu-neon-mul8.c", |
| "src/qu8-dwconv/gen/qu8-dwconv-8f8m9l8c8s8r-minmax-rndnu-neon-mul16.c", |
| "src/qu8-dwconv/gen/qu8-dwconv-8f8m9l16c8s8r-minmax-fp32-neon-mul16.c", |
| "src/qu8-dwconv/gen/qu8-dwconv-8f8m9l16c8s8r-minmax-rndnu-neon-mul8.c", |
| "src/qu8-dwconv/gen/qu8-dwconv-8f8m9l16c8s8r-minmax-rndnu-neon-mul16.c", |
| "src/qu8-dwconv/gen/qu8-dwconv-8f8m9l32c8s8r-minmax-fp32-neon-mul16.c", |
| "src/qu8-dwconv/gen/qu8-dwconv-8f8m9l32c8s8r-minmax-rndnu-neon-mul8.c", |
| "src/qu8-dwconv/gen/qu8-dwconv-8f8m9l32c8s8r-minmax-rndnu-neon-mul16.c", |
| "src/qu8-dwconv/gen/qu8-dwconv-9p8c-minmax-fp32-neon-mul16.c", |
| "src/qu8-dwconv/gen/qu8-dwconv-9p8c-minmax-rndnu-neon-mul8.c", |
| "src/qu8-dwconv/gen/qu8-dwconv-9p8c-minmax-rndnu-neon-mul16.c", |
| "src/qu8-dwconv/gen/qu8-dwconv-9p16c-minmax-fp32-neon-mul16.c", |
| "src/qu8-dwconv/gen/qu8-dwconv-9p16c-minmax-rndnu-neon-mul8.c", |
| "src/qu8-dwconv/gen/qu8-dwconv-9p16c-minmax-rndnu-neon-mul16.c", |
| "src/qu8-dwconv/gen/qu8-dwconv-9p32c-minmax-fp32-neon-mul16.c", |
| "src/qu8-dwconv/gen/qu8-dwconv-9p32c-minmax-rndnu-neon-mul8.c", |
| "src/qu8-dwconv/gen/qu8-dwconv-9p32c-minmax-rndnu-neon-mul16.c", |
| "src/qu8-dwconv/gen/qu8-dwconv-25p8c-minmax-fp32-neon-mul16.c", |
| "src/qu8-dwconv/gen/qu8-dwconv-25p8c-minmax-rndnu-neon-mul8.c", |
| "src/qu8-dwconv/gen/qu8-dwconv-25p8c-minmax-rndnu-neon-mul16.c", |
| "src/qu8-dwconv/gen/qu8-dwconv-25p16c-minmax-fp32-neon-mul16.c", |
| "src/qu8-dwconv/gen/qu8-dwconv-25p16c-minmax-rndnu-neon-mul8.c", |
| "src/qu8-dwconv/gen/qu8-dwconv-25p16c-minmax-rndnu-neon-mul16.c", |
| "src/qu8-dwconv/gen/qu8-dwconv-25p32c-minmax-fp32-neon-mul16.c", |
| "src/qu8-dwconv/gen/qu8-dwconv-25p32c-minmax-rndnu-neon-mul8.c", |
| "src/qu8-dwconv/gen/qu8-dwconv-25p32c-minmax-rndnu-neon-mul16.c", |
| "src/qu8-f32-vcvt/gen/qu8-f32-vcvt-neon-u8.c", |
| "src/qu8-f32-vcvt/gen/qu8-f32-vcvt-neon-u16.c", |
| "src/qu8-f32-vcvt/gen/qu8-f32-vcvt-neon-u24.c", |
| "src/qu8-f32-vcvt/gen/qu8-f32-vcvt-neon-u32.c", |
| "src/qu8-gavgpool/gen/qu8-gavgpool-7p7x-minmax-fp32-neon-c8.c", |
| "src/qu8-gavgpool/gen/qu8-gavgpool-7p7x-minmax-fp32-neon-c16.c", |
| "src/qu8-gavgpool/gen/qu8-gavgpool-7p7x-minmax-fp32-neon-c24.c", |
| "src/qu8-gavgpool/gen/qu8-gavgpool-7p7x-minmax-fp32-neon-c32.c", |
| "src/qu8-gavgpool/gen/qu8-gavgpool-7p7x-minmax-rndnu-neon-c8.c", |
| "src/qu8-gavgpool/gen/qu8-gavgpool-7p7x-minmax-rndnu-neon-c16.c", |
| "src/qu8-gavgpool/gen/qu8-gavgpool-7p7x-minmax-rndnu-neon-c24.c", |
| "src/qu8-gavgpool/gen/qu8-gavgpool-7p7x-minmax-rndnu-neon-c32.c", |
| "src/qu8-gavgpool/gen/qu8-gavgpool-7x-minmax-fp32-neon-c8.c", |
| "src/qu8-gavgpool/gen/qu8-gavgpool-7x-minmax-fp32-neon-c16.c", |
| "src/qu8-gavgpool/gen/qu8-gavgpool-7x-minmax-fp32-neon-c24.c", |
| "src/qu8-gavgpool/gen/qu8-gavgpool-7x-minmax-fp32-neon-c32.c", |
| "src/qu8-gavgpool/gen/qu8-gavgpool-7x-minmax-rndnu-neon-c8.c", |
| "src/qu8-gavgpool/gen/qu8-gavgpool-7x-minmax-rndnu-neon-c16.c", |
| "src/qu8-gavgpool/gen/qu8-gavgpool-7x-minmax-rndnu-neon-c24.c", |
| "src/qu8-gavgpool/gen/qu8-gavgpool-7x-minmax-rndnu-neon-c32.c", |
| "src/qu8-gemm/gen/qu8-gemm-1x8-minmax-fp32-neon-mlal-lane.c", |
| "src/qu8-gemm/gen/qu8-gemm-1x8-minmax-rndnu-neon-mlal-lane.c", |
| "src/qu8-gemm/gen/qu8-gemm-1x16-minmax-fp32-neon-mlal-lane.c", |
| "src/qu8-gemm/gen/qu8-gemm-1x16-minmax-rndnu-neon-mlal-lane.c", |
| "src/qu8-gemm/gen/qu8-gemm-2x8-minmax-rndnu-neon-mlal-lane.c", |
| "src/qu8-gemm/gen/qu8-gemm-2x16-minmax-rndnu-neon-mlal-lane.c", |
| "src/qu8-gemm/gen/qu8-gemm-3x8-minmax-rndnu-neon-mlal-lane.c", |
| "src/qu8-gemm/gen/qu8-gemm-3x16-minmax-rndnu-neon-mlal-lane.c", |
| "src/qu8-gemm/gen/qu8-gemm-4x8-minmax-fp32-neon-mlal-lane.c", |
| "src/qu8-gemm/gen/qu8-gemm-4x8-minmax-rndnu-neon-mlal-lane.c", |
| "src/qu8-gemm/gen/qu8-gemm-4x16-minmax-fp32-neon-mlal-lane.c", |
| "src/qu8-gemm/gen/qu8-gemm-4x16-minmax-rndnu-neon-mlal-lane.c", |
| "src/qu8-gemm/gen/qu8-gemm-6x8-minmax-rndnu-neon-mlal-lane.c", |
| "src/qu8-gemm/gen/qu8-gemm-6x16-minmax-rndnu-neon-mlal-lane.c", |
| "src/qu8-igemm/gen/qu8-igemm-1x8-minmax-fp32-neon-mlal-lane.c", |
| "src/qu8-igemm/gen/qu8-igemm-1x8-minmax-rndnu-neon-mlal-lane.c", |
| "src/qu8-igemm/gen/qu8-igemm-1x16-minmax-fp32-neon-mlal-lane.c", |
| "src/qu8-igemm/gen/qu8-igemm-1x16-minmax-rndnu-neon-mlal-lane.c", |
| "src/qu8-igemm/gen/qu8-igemm-2x8-minmax-rndnu-neon-mlal-lane.c", |
| "src/qu8-igemm/gen/qu8-igemm-2x16-minmax-rndnu-neon-mlal-lane.c", |
| "src/qu8-igemm/gen/qu8-igemm-3x8-minmax-rndnu-neon-mlal-lane.c", |
| "src/qu8-igemm/gen/qu8-igemm-3x16-minmax-rndnu-neon-mlal-lane.c", |
| "src/qu8-igemm/gen/qu8-igemm-4x8-minmax-fp32-neon-mlal-lane.c", |
| "src/qu8-igemm/gen/qu8-igemm-4x8-minmax-rndnu-neon-mlal-lane.c", |
| "src/qu8-igemm/gen/qu8-igemm-4x16-minmax-fp32-neon-mlal-lane.c", |
| "src/qu8-igemm/gen/qu8-igemm-4x16-minmax-rndnu-neon-mlal-lane.c", |
| "src/qu8-igemm/gen/qu8-igemm-6x8-minmax-rndnu-neon-mlal-lane.c", |
| "src/qu8-igemm/gen/qu8-igemm-6x16-minmax-rndnu-neon-mlal-lane.c", |
| "src/qu8-requantization/qu8-requantization-fp32-neon.c", |
| "src/qu8-requantization/qu8-requantization-gemmlowp-neon.c", |
| "src/qu8-requantization/qu8-requantization-rndna-neon.c", |
| "src/qu8-vadd/gen/qu8-vadd-minmax-neon-ld64-u8.c", |
| "src/qu8-vadd/gen/qu8-vadd-minmax-neon-ld64-u16.c", |
| "src/qu8-vadd/gen/qu8-vadd-minmax-neon-ld64-u32.c", |
| "src/qu8-vadd/gen/qu8-vadd-minmax-neon-ld128-u16.c", |
| "src/qu8-vaddc/gen/qu8-vaddc-minmax-neon-ld64-u8.c", |
| "src/qu8-vaddc/gen/qu8-vaddc-minmax-neon-ld64-u16.c", |
| "src/qu8-vaddc/gen/qu8-vaddc-minmax-neon-ld64-u32.c", |
| "src/qu8-vaddc/gen/qu8-vaddc-minmax-neon-ld128-u16.c", |
| "src/qu8-vcvt/gen/qu8-vcvt-neon-u8.c", |
| "src/qu8-vcvt/gen/qu8-vcvt-neon-u16.c", |
| "src/qu8-vcvt/gen/qu8-vcvt-neon-u32.c", |
| "src/qu8-vhswish/gen/qu8-vhswish-neon-x8.c", |
| "src/qu8-vhswish/gen/qu8-vhswish-neon-x16.c", |
| "src/qu8-vhswish/gen/qu8-vhswish-neon-x32.c", |
| "src/qu8-vlrelu/gen/qu8-vlrelu-neon-u8.c", |
| "src/qu8-vlrelu/gen/qu8-vlrelu-neon-u16.c", |
| "src/qu8-vlrelu/gen/qu8-vlrelu-neon-u32.c", |
| "src/qu8-vmul/gen/qu8-vmul-minmax-fp32-neon-ld64-u8.c", |
| "src/qu8-vmul/gen/qu8-vmul-minmax-fp32-neon-ld64-u16.c", |
| "src/qu8-vmul/gen/qu8-vmul-minmax-fp32-neon-ld128-u16.c", |
| "src/qu8-vmul/gen/qu8-vmul-minmax-rndnu-neon-ld64-u8.c", |
| "src/qu8-vmul/gen/qu8-vmul-minmax-rndnu-neon-ld64-u16.c", |
| "src/qu8-vmul/gen/qu8-vmul-minmax-rndnu-neon-ld128-u16.c", |
| "src/qu8-vmulc/gen/qu8-vmulc-minmax-fp32-neon-ld64-u8.c", |
| "src/qu8-vmulc/gen/qu8-vmulc-minmax-fp32-neon-ld64-u16.c", |
| "src/qu8-vmulc/gen/qu8-vmulc-minmax-fp32-neon-ld128-u16.c", |
| "src/qu8-vmulc/gen/qu8-vmulc-minmax-rndnu-neon-ld64-u8.c", |
| "src/qu8-vmulc/gen/qu8-vmulc-minmax-rndnu-neon-ld64-u16.c", |
| "src/qu8-vmulc/gen/qu8-vmulc-minmax-rndnu-neon-ld128-u16.c", |
| "src/s8-ibilinear/gen/s8-ibilinear-neon-c8.c", |
| "src/s8-ibilinear/gen/s8-ibilinear-neon-c16.c", |
| "src/s8-maxpool/s8-maxpool-2p2x-minmax-neon-c16.c", |
| "src/s8-maxpool/s8-maxpool-4p3x-minmax-neon-c16.c", |
| "src/s8-maxpool/s8-maxpool-9p8x-minmax-neon-c16.c", |
| "src/s8-vclamp/s8-vclamp-neon-u64.c", |
| "src/s16-rmaxabs/gen/s16-rmaxabs-neon-x8.c", |
| "src/s16-rmaxabs/gen/s16-rmaxabs-neon-x16.c", |
| "src/s16-rmaxabs/gen/s16-rmaxabs-neon-x24.c", |
| "src/s16-rmaxabs/gen/s16-rmaxabs-neon-x32.c", |
| "src/s16-window/gen/s16-window-neon-u8.c", |
| "src/s16-window/gen/s16-window-neon-u16.c", |
| "src/s16-window/gen/s16-window-neon-u24.c", |
| "src/s16-window/gen/s16-window-neon-u32.c", |
| "src/s16-window/gen/s16-window-shift12-neon-u8.c", |
| "src/s16-window/gen/s16-window-shift12-neon-u16.c", |
| "src/s16-window/gen/s16-window-shift12-neon-u24.c", |
| "src/s16-window/gen/s16-window-shift12-neon-u32.c", |
| "src/s16-window/gen/s16-window-shift15-neon-u8.c", |
| "src/s16-window/gen/s16-window-shift15-neon-u16.c", |
| "src/s16-window/gen/s16-window-shift15-neon-u24.c", |
| "src/s16-window/gen/s16-window-shift15-neon-u32.c", |
| "src/u8-ibilinear/gen/u8-ibilinear-neon-c8.c", |
| "src/u8-ibilinear/gen/u8-ibilinear-neon-c16.c", |
| "src/u8-maxpool/u8-maxpool-9p8x-minmax-neon-c16.c", |
| "src/u8-rmax/u8-rmax-neon.c", |
| "src/u8-vclamp/u8-vclamp-neon-u64.c", |
| "src/u32-filterbank-accumulate/gen/u32-filterbank-accumulate-neon-x1.c", |
| "src/u32-filterbank-accumulate/gen/u32-filterbank-accumulate-neon-x2.c", |
| "src/x8-transposec/gen/x8-transposec-8x8-multi-dec-zip-neon.c", |
| "src/x8-transposec/gen/x8-transposec-8x8-multi-mov-zip-neon.c", |
| "src/x8-transposec/gen/x8-transposec-8x8-multi-switch-zip-neon.c", |
| "src/x8-transposec/gen/x8-transposec-8x8-reuse-dec-zip-neon.c", |
| "src/x8-transposec/gen/x8-transposec-8x8-reuse-mov-zip-neon.c", |
| "src/x8-transposec/gen/x8-transposec-8x8-reuse-multi-zip-neon.c", |
| "src/x8-transposec/gen/x8-transposec-8x8-reuse-switch-zip-neon.c", |
| "src/x8-transposec/gen/x8-transposec-16x16-reuse-dec-zip-neon.c", |
| "src/x8-transposec/gen/x8-transposec-16x16-reuse-mov-zip-neon.c", |
| "src/x8-transposec/gen/x8-transposec-16x16-reuse-switch-zip-neon.c", |
| "src/x8-zip/x8-zip-x2-neon.c", |
| "src/x8-zip/x8-zip-x3-neon.c", |
| "src/x8-zip/x8-zip-x4-neon.c", |
| "src/x8-zip/x8-zip-xm-neon.c", |
| "src/x16-packw/gen/x16-packw-x8-gemm-goi-neon-ld4lane-u4-prfm.c", |
| "src/x16-packw/gen/x16-packw-x8-gemm-goi-neon-ld4lane-u4.c", |
| "src/x16-packw/gen/x16-packw-x8-gemm-goi-neon-ld4lane-u8-prfm.c", |
| "src/x16-packw/gen/x16-packw-x8-gemm-goi-neon-ld4lane-u8.c", |
| "src/x16-packw/gen/x16-packw-x8-gemm-goi-neon-ld4lane-u12-prfm.c", |
| "src/x16-packw/gen/x16-packw-x8-gemm-goi-neon-ld4lane-u12.c", |
| "src/x16-packw/gen/x16-packw-x8-gemm-goi-neon-ld4lane-u16-prfm.c", |
| "src/x16-packw/gen/x16-packw-x8-gemm-goi-neon-ld4lane-u16.c", |
| "src/x16-packw/gen/x16-packw-x16-gemm-goi-neon-ld4lane-u4-prfm.c", |
| "src/x16-packw/gen/x16-packw-x16-gemm-goi-neon-ld4lane-u4.c", |
| "src/x16-packw/gen/x16-packw-x16-gemm-goi-neon-ld4lane-u8-prfm.c", |
| "src/x16-packw/gen/x16-packw-x16-gemm-goi-neon-ld4lane-u8.c", |
| "src/x16-packw/gen/x16-packw-x16-gemm-goi-neon-ld4lane-u12-prfm.c", |
| "src/x16-packw/gen/x16-packw-x16-gemm-goi-neon-ld4lane-u12.c", |
| "src/x16-packw/gen/x16-packw-x16-gemm-goi-neon-ld4lane-u16-prfm.c", |
| "src/x16-packw/gen/x16-packw-x16-gemm-goi-neon-ld4lane-u16.c", |
| "src/x16-transposec/gen/x16-transposec-4x4-multi-dec-zip-neon.c", |
| "src/x16-transposec/gen/x16-transposec-4x4-multi-mov-zip-neon.c", |
| "src/x16-transposec/gen/x16-transposec-4x4-multi-multi-zip-neon.c", |
| "src/x16-transposec/gen/x16-transposec-4x4-multi-switch-zip-neon.c", |
| "src/x16-transposec/gen/x16-transposec-4x4-reuse-dec-zip-neon.c", |
| "src/x16-transposec/gen/x16-transposec-4x4-reuse-mov-zip-neon.c", |
| "src/x16-transposec/gen/x16-transposec-4x4-reuse-multi-zip-neon.c", |
| "src/x16-transposec/gen/x16-transposec-4x4-reuse-switch-zip-neon.c", |
| "src/x16-transposec/gen/x16-transposec-8x8-multi-dec-zip-neon.c", |
| "src/x16-transposec/gen/x16-transposec-8x8-multi-mov-zip-neon.c", |
| "src/x16-transposec/gen/x16-transposec-8x8-multi-switch-zip-neon.c", |
| "src/x16-transposec/gen/x16-transposec-8x8-reuse-dec-zip-neon.c", |
| "src/x16-transposec/gen/x16-transposec-8x8-reuse-mov-zip-neon.c", |
| "src/x16-transposec/gen/x16-transposec-8x8-reuse-multi-zip-neon.c", |
| "src/x16-transposec/gen/x16-transposec-8x8-reuse-switch-zip-neon.c", |
| "src/x24-transposec/x24-transposec-2x2-neon-tbl64.c", |
| "src/x32-packw/gen/x32-packw-x2-gemm-goi-neon-ld2lane-u2-prfm.c", |
| "src/x32-packw/gen/x32-packw-x2-gemm-goi-neon-ld2lane-u2.c", |
| "src/x32-packw/gen/x32-packw-x8-gemm-goi-neon-ld4lane-u4-prfm.c", |
| "src/x32-packw/gen/x32-packw-x8-gemm-goi-neon-ld4lane-u4.c", |
| "src/x32-packw/gen/x32-packw-x8-gemm-goi-neon-ld4lane-u8-prfm.c", |
| "src/x32-packw/gen/x32-packw-x8-gemm-goi-neon-ld4lane-u8.c", |
| "src/x32-packw/gen/x32-packw-x8s4-gemm-goi-neon-ld4lane-u4-prfm.c", |
| "src/x32-packw/gen/x32-packw-x8s4-gemm-goi-neon-ld4lane-u4.c", |
| "src/x32-packw/gen/x32-packw-x8s4-gemm-goi-neon-ld4lane-u8-prfm.c", |
| "src/x32-packw/gen/x32-packw-x8s4-gemm-goi-neon-ld4lane-u8.c", |
| "src/x32-packw/gen/x32-packw-x12-gemm-goi-neon-ld4lane-u4-prfm.c", |
| "src/x32-packw/gen/x32-packw-x12-gemm-goi-neon-ld4lane-u4.c", |
| "src/x32-packw/gen/x32-packw-x12-gemm-goi-neon-ld4lane-u8-prfm.c", |
| "src/x32-packw/gen/x32-packw-x12-gemm-goi-neon-ld4lane-u8.c", |
| "src/x32-packw/gen/x32-packw-x16-gemm-goi-neon-ld4lane-u4-prfm.c", |
| "src/x32-packw/gen/x32-packw-x16-gemm-goi-neon-ld4lane-u4.c", |
| "src/x32-packw/gen/x32-packw-x16-gemm-goi-neon-ld4lane-u8-prfm.c", |
| "src/x32-packw/gen/x32-packw-x16-gemm-goi-neon-ld4lane-u8.c", |
| "src/x32-packx/gen/x32-packx-4x-neon-st4-x4-prfm.c", |
| "src/x32-packx/gen/x32-packx-4x-neon-st4-x4.c", |
| "src/x32-packx/gen/x32-packx-4x-neon-st4-x8-prfm.c", |
| "src/x32-packx/gen/x32-packx-4x-neon-st4-x8.c", |
| "src/x32-packx/gen/x32-packx-8x-neon-st4-x4-prfm.c", |
| "src/x32-packx/gen/x32-packx-8x-neon-st4-x4.c", |
| "src/x32-packx/gen/x32-packx-8x-neon-st4-x8-prfm.c", |
| "src/x32-packx/gen/x32-packx-8x-neon-st4-x8.c", |
| "src/x32-transposec/gen/x32-transposec-2x2-multi-dec-zip-neon.c", |
| "src/x32-transposec/gen/x32-transposec-2x2-multi-mov-zip-neon.c", |
| "src/x32-transposec/gen/x32-transposec-2x2-multi-multi-zip-neon.c", |
| "src/x32-transposec/gen/x32-transposec-2x2-multi-switch-zip-neon.c", |
| "src/x32-transposec/gen/x32-transposec-2x2-reuse-dec-zip-neon.c", |
| "src/x32-transposec/gen/x32-transposec-2x2-reuse-mov-zip-neon.c", |
| "src/x32-transposec/gen/x32-transposec-2x2-reuse-multi-zip-neon.c", |
| "src/x32-transposec/gen/x32-transposec-2x2-reuse-switch-zip-neon.c", |
| "src/x32-transposec/gen/x32-transposec-4x4-multi-dec-zip-neon.c", |
| "src/x32-transposec/gen/x32-transposec-4x4-multi-mov-zip-neon.c", |
| "src/x32-transposec/gen/x32-transposec-4x4-multi-multi-zip-neon.c", |
| "src/x32-transposec/gen/x32-transposec-4x4-multi-switch-zip-neon.c", |
| "src/x32-transposec/gen/x32-transposec-4x4-reuse-dec-zip-neon.c", |
| "src/x32-transposec/gen/x32-transposec-4x4-reuse-mov-zip-neon.c", |
| "src/x32-transposec/gen/x32-transposec-4x4-reuse-multi-zip-neon.c", |
| "src/x32-transposec/gen/x32-transposec-4x4-reuse-switch-zip-neon.c", |
| "src/x32-unpool/x32-unpool-neon.c", |
| "src/x32-zip/x32-zip-x2-neon.c", |
| "src/x32-zip/x32-zip-x3-neon.c", |
| "src/x32-zip/x32-zip-x4-neon.c", |
| "src/x32-zip/x32-zip-xm-neon.c", |
| "src/x64-transposec/gen/x64-transposec-2x2-multi-dec-zip-neon.c", |
| "src/x64-transposec/gen/x64-transposec-2x2-multi-mov-zip-neon.c", |
| "src/x64-transposec/gen/x64-transposec-2x2-multi-multi-zip-neon.c", |
| "src/x64-transposec/gen/x64-transposec-2x2-multi-switch-zip-neon.c", |
| "src/x64-transposec/gen/x64-transposec-2x2-reuse-dec-zip-neon.c", |
| "src/x64-transposec/gen/x64-transposec-2x2-reuse-mov-zip-neon.c", |
| "src/x64-transposec/gen/x64-transposec-2x2-reuse-multi-zip-neon.c", |
| "src/x64-transposec/gen/x64-transposec-2x2-reuse-switch-zip-neon.c", |
| "src/xx-fill/xx-fill-neon-x64.c", |
| "src/xx-pad/xx-pad-neon.c", |
| ] |
| |
| ALL_NEON_AARCH64_MICROKERNEL_SRCS = [ |
| "src/f32-vbinary/gen/f32-vdiv-minmax-aarch64-neon-u4.c", |
| "src/f32-vbinary/gen/f32-vdiv-minmax-aarch64-neon-u8.c", |
| "src/f32-vbinary/gen/f32-vdivc-minmax-aarch64-neon-u4.c", |
| "src/f32-vbinary/gen/f32-vdivc-minmax-aarch64-neon-u8.c", |
| "src/f32-vbinary/gen/f32-vrdivc-minmax-aarch64-neon-u4.c", |
| "src/f32-vbinary/gen/f32-vrdivc-minmax-aarch64-neon-u8.c", |
| "src/f32-vsqrt/gen/f32-vsqrt-aarch64-neon-sqrt-u4.c", |
| "src/f32-vsqrt/gen/f32-vsqrt-aarch64-neon-sqrt-u8.c", |
| "src/x8-lut/gen/x8-lut-aarch64-neon-tbx128x4-u16.c", |
| "src/x8-lut/gen/x8-lut-aarch64-neon-tbx128x4-u32.c", |
| "src/x8-lut/gen/x8-lut-aarch64-neon-tbx128x4-u48.c", |
| "src/x8-lut/gen/x8-lut-aarch64-neon-tbx128x4-u64.c", |
| "src/x24-transposec/x24-transposec-4x4-aarch64-neon-tbl128.c", |
| "src/x32-transposec/x32-transposec-4x4-aarch64-neon-tbl128.c", |
| ] |
| |
| ALL_NEONBF16_MICROKERNEL_SRCS = [ |
| "src/bf16-gemm/gen/bf16-gemm-1x4c8-minmax-neonbf16-bfdot.c", |
| "src/bf16-gemm/gen/bf16-gemm-1x4c8-minmax-neonbf16-bfmlal.c", |
| "src/bf16-gemm/gen/bf16-gemm-1x8c2-minmax-neonbf16-bfdot-lane-ld128.c", |
| "src/bf16-gemm/gen/bf16-gemm-2x4c8-minmax-neonbf16-bfdot.c", |
| "src/bf16-gemm/gen/bf16-gemm-2x4c8-minmax-neonbf16-bfmlal.c", |
| "src/bf16-gemm/gen/bf16-gemm-3x4c8-minmax-neonbf16-bfdot.c", |
| "src/bf16-gemm/gen/bf16-gemm-3x4c8-minmax-neonbf16-bfmlal.c", |
| "src/bf16-gemm/gen/bf16-gemm-4x4c8-minmax-neonbf16-bfdot.c", |
| "src/bf16-gemm/gen/bf16-gemm-4x4c8-minmax-neonbf16-bfmlal.c", |
| "src/bf16-gemm/gen/bf16-gemm-4x8c2-minmax-neonbf16-bfdot-lane-ld128.c", |
| "src/bf16-gemm/gen/bf16-gemm-5x4c8-minmax-neonbf16-bfdot.c", |
| "src/bf16-gemm/gen/bf16-gemm-5x4c8-minmax-neonbf16-bfmlal.c", |
| "src/bf16-gemm/gen/bf16-gemm-5x8c2-minmax-neonbf16-bfdot-lane-ld128.c", |
| "src/bf16-gemm/gen/bf16-gemm-6x8c2-minmax-neonbf16-bfdot-lane-ld128.c", |
| ] |
| |
| ALL_NEONBF16_AARCH64_MICROKERNEL_SRCS = [ |
| ] |
| |
| ALL_NEONDOT_MICROKERNEL_SRCS = [ |
| "src/qd8-f32-qc4w-gemm/gen/qd8-f32-qc4w-gemm-1x8c4-minmax-neondot.c", |
| "src/qd8-f32-qc4w-gemm/gen/qd8-f32-qc4w-gemm-1x8c8-minmax-neondot-ld64.c", |
| "src/qd8-f32-qc4w-gemm/gen/qd8-f32-qc4w-gemm-1x16c4-minmax-neondot.c", |
| "src/qd8-f32-qc4w-gemm/gen/qd8-f32-qc4w-gemm-1x16c8-minmax-neondot-ld64.c", |
| "src/qd8-f32-qc4w-gemm/gen/qd8-f32-qc4w-gemm-2x8c4-minmax-neondot.c", |
| "src/qd8-f32-qc4w-gemm/gen/qd8-f32-qc4w-gemm-2x16c4-minmax-neondot.c", |
| "src/qd8-f32-qc4w-gemm/gen/qd8-f32-qc4w-gemm-3x16c4-minmax-neondot.c", |
| "src/qd8-f32-qc4w-gemm/gen/qd8-f32-qc4w-gemm-4x8c4-minmax-neondot.c", |
| "src/qd8-f32-qc4w-gemm/gen/qd8-f32-qc4w-gemm-4x16c4-minmax-neondot.c", |
| "src/qd8-f32-qc4w-gemm/gen/qd8-f32-qc4w-gemm-6x8c4-minmax-neondot.c", |
| "src/qd8-f32-qc4w-gemm/gen/qd8-f32-qc4w-gemm-6x16c4-minmax-neondot.c", |
| "src/qd8-f32-qc8w-gemm/gen/qd8-f32-qc8w-gemm-1x8c4-minmax-neondot.c", |
| "src/qd8-f32-qc8w-gemm/gen/qd8-f32-qc8w-gemm-1x8c8-minmax-neondot-ld64.c", |
| "src/qd8-f32-qc8w-gemm/gen/qd8-f32-qc8w-gemm-1x16c4-minmax-neondot.c", |
| "src/qd8-f32-qc8w-gemm/gen/qd8-f32-qc8w-gemm-1x16c8-minmax-neondot-ld64.c", |
| "src/qd8-f32-qc8w-gemm/gen/qd8-f32-qc8w-gemm-2x8c4-minmax-neondot.c", |
| "src/qd8-f32-qc8w-gemm/gen/qd8-f32-qc8w-gemm-2x16c4-minmax-neondot.c", |
| "src/qd8-f32-qc8w-gemm/gen/qd8-f32-qc8w-gemm-3x16c4-minmax-neondot.c", |
| "src/qd8-f32-qc8w-gemm/gen/qd8-f32-qc8w-gemm-4x8c4-minmax-neondot.c", |
| "src/qd8-f32-qc8w-gemm/gen/qd8-f32-qc8w-gemm-4x16c4-minmax-neondot.c", |
| "src/qd8-f32-qc8w-gemm/gen/qd8-f32-qc8w-gemm-6x8c4-minmax-neondot.c", |
| "src/qd8-f32-qc8w-gemm/gen/qd8-f32-qc8w-gemm-6x16c4-minmax-neondot.c", |
| "src/qs8-gemm/gen/qs8-gemm-1x8c4-minmax-fp32-neondot.c", |
| "src/qs8-gemm/gen/qs8-gemm-1x8c4-minmax-rndnu-neondot.c", |
| "src/qs8-gemm/gen/qs8-gemm-1x8c8-minmax-fp32-neondot-ld64.c", |
| "src/qs8-gemm/gen/qs8-gemm-1x8c8-minmax-rndnu-neondot-ld64.c", |
| "src/qs8-gemm/gen/qs8-gemm-1x16c4-minmax-rndnu-neondot.c", |
| "src/qs8-gemm/gen/qs8-gemm-1x16c8-minmax-fp32-neondot-ld64.c", |
| "src/qs8-gemm/gen/qs8-gemm-1x16c8-minmax-rndnu-neondot-ld64.c", |
| "src/qs8-gemm/gen/qs8-gemm-4x8c4-minmax-rndnu-neondot.c", |
| "src/qs8-gemm/gen/qs8-gemm-4x16c4-minmax-rndnu-neondot.c", |
| "src/qs8-gemm/gen/qs8-gemm-6x8c4-minmax-rndnu-neondot.c", |
| "src/qs8-gemm/gen/qs8-gemm-6x16c4-minmax-rndnu-neondot.c", |
| "src/qs8-gemm/gen/qs8-gemm-8x8c4-minmax-rndnu-neondot.c", |
| "src/qs8-gemm/gen/qs8-gemm-8x16c4-minmax-rndnu-neondot.c", |
| "src/qs8-igemm/gen/qs8-igemm-1x8c4-minmax-fp32-neondot.c", |
| "src/qs8-igemm/gen/qs8-igemm-1x8c4-minmax-rndnu-neondot.c", |
| "src/qs8-igemm/gen/qs8-igemm-1x8c8-minmax-fp32-neondot-ld64.c", |
| "src/qs8-igemm/gen/qs8-igemm-1x8c8-minmax-rndnu-neondot-ld64.c", |
| "src/qs8-igemm/gen/qs8-igemm-1x16c4-minmax-rndnu-neondot.c", |
| "src/qs8-igemm/gen/qs8-igemm-1x16c8-minmax-fp32-neondot-ld64.c", |
| "src/qs8-igemm/gen/qs8-igemm-1x16c8-minmax-rndnu-neondot-ld64.c", |
| "src/qs8-igemm/gen/qs8-igemm-4x8c4-minmax-rndnu-neondot.c", |
| "src/qs8-igemm/gen/qs8-igemm-4x16c4-minmax-rndnu-neondot.c", |
| "src/qs8-igemm/gen/qs8-igemm-6x8c4-minmax-rndnu-neondot.c", |
| "src/qs8-igemm/gen/qs8-igemm-6x16c4-minmax-rndnu-neondot.c", |
| "src/qs8-igemm/gen/qs8-igemm-8x8c4-minmax-rndnu-neondot.c", |
| "src/qs8-igemm/gen/qs8-igemm-8x16c4-minmax-rndnu-neondot.c", |
| "src/qs8-qc8w-gemm/gen/qs8-qc8w-gemm-1x8c4-minmax-fp32-neondot.c", |
| "src/qs8-qc8w-gemm/gen/qs8-qc8w-gemm-1x8c8-minmax-fp32-neondot-ld64.c", |
| "src/qs8-qc8w-gemm/gen/qs8-qc8w-gemm-1x16c4-minmax-fp32-neondot.c", |
| "src/qs8-qc8w-gemm/gen/qs8-qc8w-gemm-1x16c8-minmax-fp32-neondot-ld64.c", |
| "src/qs8-qc8w-gemm/gen/qs8-qc8w-gemm-4x8c4-minmax-fp32-neondot.c", |
| "src/qs8-qc8w-gemm/gen/qs8-qc8w-gemm-4x16c4-minmax-fp32-neondot.c", |
| "src/qs8-qc8w-gemm/gen/qs8-qc8w-gemm-6x8c4-minmax-fp32-neondot.c", |
| "src/qs8-qc8w-gemm/gen/qs8-qc8w-gemm-6x16c4-minmax-fp32-neondot.c", |
| "src/qs8-qc8w-gemm/gen/qs8-qc8w-gemm-8x8c4-minmax-fp32-neondot.c", |
| "src/qs8-qc8w-gemm/gen/qs8-qc8w-gemm-8x16c4-minmax-fp32-neondot.c", |
| "src/qs8-qc8w-igemm/gen/qs8-qc8w-igemm-1x8c4-minmax-fp32-neondot.c", |
| "src/qs8-qc8w-igemm/gen/qs8-qc8w-igemm-1x8c8-minmax-fp32-neondot-ld64.c", |
| "src/qs8-qc8w-igemm/gen/qs8-qc8w-igemm-1x16c4-minmax-fp32-neondot.c", |
| "src/qs8-qc8w-igemm/gen/qs8-qc8w-igemm-1x16c8-minmax-fp32-neondot-ld64.c", |
| "src/qs8-qc8w-igemm/gen/qs8-qc8w-igemm-4x8c4-minmax-fp32-neondot.c", |
| "src/qs8-qc8w-igemm/gen/qs8-qc8w-igemm-4x16c4-minmax-fp32-neondot.c", |
| "src/qs8-qc8w-igemm/gen/qs8-qc8w-igemm-6x8c4-minmax-fp32-neondot.c", |
| "src/qs8-qc8w-igemm/gen/qs8-qc8w-igemm-6x16c4-minmax-fp32-neondot.c", |
| "src/qs8-qc8w-igemm/gen/qs8-qc8w-igemm-8x8c4-minmax-fp32-neondot.c", |
| "src/qs8-qc8w-igemm/gen/qs8-qc8w-igemm-8x16c4-minmax-fp32-neondot.c", |
| "src/qu8-gemm/gen/qu8-gemm-1x8c4-minmax-rndnu-neondot.c", |
| "src/qu8-gemm/gen/qu8-gemm-1x16c4-minmax-fp32-neondot.c", |
| "src/qu8-gemm/gen/qu8-gemm-1x16c4-minmax-rndnu-neondot.c", |
| "src/qu8-gemm/gen/qu8-gemm-1x32c4-minmax-rndnu-neondot.c", |
| "src/qu8-gemm/gen/qu8-gemm-2x8c4-minmax-rndnu-neondot.c", |
| "src/qu8-gemm/gen/qu8-gemm-2x16c4-minmax-fp32-neondot.c", |
| "src/qu8-gemm/gen/qu8-gemm-2x16c4-minmax-rndnu-neondot.c", |
| "src/qu8-gemm/gen/qu8-gemm-2x32c4-minmax-rndnu-neondot.c", |
| "src/qu8-gemm/gen/qu8-gemm-3x8c4-minmax-rndnu-neondot.c", |
| "src/qu8-gemm/gen/qu8-gemm-3x16c4-minmax-rndnu-neondot.c", |
| "src/qu8-gemm/gen/qu8-gemm-3x32c4-minmax-rndnu-neondot.c", |
| "src/qu8-gemm/gen/qu8-gemm-4x8c4-minmax-rndnu-neondot.c", |
| "src/qu8-gemm/gen/qu8-gemm-4x16c4-minmax-fp32-neondot.c", |
| "src/qu8-gemm/gen/qu8-gemm-4x16c4-minmax-rndnu-neondot.c", |
| "src/qu8-gemm/gen/qu8-gemm-5x8c4-minmax-rndnu-neondot.c", |
| "src/qu8-gemm/gen/qu8-gemm-5x16c4-minmax-rndnu-neondot.c", |
| "src/qu8-gemm/gen/qu8-gemm-6x8c4-minmax-rndnu-neondot.c", |
| "src/qu8-gemm/gen/qu8-gemm-6x16c4-minmax-rndnu-neondot.c", |
| "src/qu8-gemm/gen/qu8-gemm-8x8c4-minmax-rndnu-neondot.c", |
| "src/qu8-gemm/gen/qu8-gemm-8x16c4-minmax-rndnu-neondot.c", |
| "src/qu8-igemm/gen/qu8-igemm-1x8c4-minmax-rndnu-neondot.c", |
| "src/qu8-igemm/gen/qu8-igemm-1x16c4-minmax-fp32-neondot.c", |
| "src/qu8-igemm/gen/qu8-igemm-1x16c4-minmax-rndnu-neondot.c", |
| "src/qu8-igemm/gen/qu8-igemm-1x32c4-minmax-rndnu-neondot.c", |
| "src/qu8-igemm/gen/qu8-igemm-2x8c4-minmax-rndnu-neondot.c", |
| "src/qu8-igemm/gen/qu8-igemm-2x16c4-minmax-fp32-neondot.c", |
| "src/qu8-igemm/gen/qu8-igemm-2x16c4-minmax-rndnu-neondot.c", |
| "src/qu8-igemm/gen/qu8-igemm-2x32c4-minmax-rndnu-neondot.c", |
| "src/qu8-igemm/gen/qu8-igemm-3x8c4-minmax-rndnu-neondot.c", |
| "src/qu8-igemm/gen/qu8-igemm-3x16c4-minmax-rndnu-neondot.c", |
| "src/qu8-igemm/gen/qu8-igemm-3x32c4-minmax-rndnu-neondot.c", |
| "src/qu8-igemm/gen/qu8-igemm-4x8c4-minmax-rndnu-neondot.c", |
| "src/qu8-igemm/gen/qu8-igemm-4x16c4-minmax-fp32-neondot.c", |
| "src/qu8-igemm/gen/qu8-igemm-4x16c4-minmax-rndnu-neondot.c", |
| "src/qu8-igemm/gen/qu8-igemm-5x8c4-minmax-rndnu-neondot.c", |
| "src/qu8-igemm/gen/qu8-igemm-5x16c4-minmax-rndnu-neondot.c", |
| "src/qu8-igemm/gen/qu8-igemm-6x8c4-minmax-rndnu-neondot.c", |
| "src/qu8-igemm/gen/qu8-igemm-6x16c4-minmax-rndnu-neondot.c", |
| "src/qu8-igemm/gen/qu8-igemm-8x8c4-minmax-rndnu-neondot.c", |
| "src/qu8-igemm/gen/qu8-igemm-8x16c4-minmax-rndnu-neondot.c", |
| ] |
| |
| ALL_NEONDOT_AARCH64_MICROKERNEL_SRCS = [ |
| "src/qd8-f32-qc4w-gemm/gen/qd8-f32-qc4w-gemm-1x8c8-minmax-aarch64-neondot-ld128.c", |
| "src/qd8-f32-qc4w-gemm/gen/qd8-f32-qc4w-gemm-1x16c8-minmax-aarch64-neondot-ld128.c", |
| "src/qd8-f32-qc8w-gemm/gen/qd8-f32-qc8w-gemm-1x8c8-minmax-aarch64-neondot-ld128.c", |
| "src/qd8-f32-qc8w-gemm/gen/qd8-f32-qc8w-gemm-1x16c8-minmax-aarch64-neondot-ld128.c", |
| "src/qs8-gemm/gen/qs8-gemm-1x8c8-minmax-fp32-aarch64-neondot-ld128.c", |
| "src/qs8-gemm/gen/qs8-gemm-1x8c8-minmax-rndnu-aarch64-neondot-ld128.c", |
| "src/qs8-gemm/gen/qs8-gemm-1x16c8-minmax-fp32-aarch64-neondot-ld128.c", |
| "src/qs8-gemm/gen/qs8-gemm-1x16c8-minmax-rndnu-aarch64-neondot-ld128.c", |
| "src/qs8-igemm/gen/qs8-igemm-1x8c8-minmax-fp32-aarch64-neondot-ld128.c", |
| "src/qs8-igemm/gen/qs8-igemm-1x8c8-minmax-rndnu-aarch64-neondot-ld128.c", |
| "src/qs8-igemm/gen/qs8-igemm-1x16c8-minmax-fp32-aarch64-neondot-ld128.c", |
| "src/qs8-igemm/gen/qs8-igemm-1x16c8-minmax-rndnu-aarch64-neondot-ld128.c", |
| "src/qs8-qc8w-gemm/gen/qs8-qc8w-gemm-1x8c8-minmax-fp32-aarch64-neondot-ld128.c", |
| "src/qs8-qc8w-gemm/gen/qs8-qc8w-gemm-1x16c8-minmax-fp32-aarch64-neondot-ld128.c", |
| "src/qs8-qc8w-igemm/gen/qs8-qc8w-igemm-1x8c8-minmax-fp32-aarch64-neondot-ld128.c", |
| "src/qs8-qc8w-igemm/gen/qs8-qc8w-igemm-1x16c8-minmax-fp32-aarch64-neondot-ld128.c", |
| ] |
| |
| ALL_NEONFMA_MICROKERNEL_SRCS = [ |
| "src/bf16-gemm/gen/bf16-gemm-1x4c8-minmax-neonfma-shland.c", |
| "src/bf16-gemm/gen/bf16-gemm-1x4c8-minmax-neonfma-zip.c", |
| "src/bf16-gemm/gen/bf16-gemm-2x4c8-minmax-neonfma-shland.c", |
| "src/bf16-gemm/gen/bf16-gemm-2x4c8-minmax-neonfma-zip.c", |
| "src/bf16-gemm/gen/bf16-gemm-3x4c8-minmax-neonfma-shland.c", |
| "src/bf16-gemm/gen/bf16-gemm-3x4c8-minmax-neonfma-zip.c", |
| "src/bf16-gemm/gen/bf16-gemm-4x4c8-minmax-neonfma-shland.c", |
| "src/bf16-gemm/gen/bf16-gemm-4x4c8-minmax-neonfma-zip.c", |
| "src/bf16-gemm/gen/bf16-gemm-5x4c8-minmax-neonfma-shland.c", |
| "src/bf16-gemm/gen/bf16-gemm-5x4c8-minmax-neonfma-zip.c", |
| "src/f32-dwconv/gen/f32-dwconv-2f2m2l4c4s4r-minmax-neonfma-acc2.c", |
| "src/f32-dwconv/gen/f32-dwconv-2f2m2l4c4s4r-minmax-neonfma.c", |
| "src/f32-dwconv/gen/f32-dwconv-2f2m2l8c4s4r-minmax-neonfma-acc2.c", |
| "src/f32-dwconv/gen/f32-dwconv-2f2m2l8c4s4r-minmax-neonfma.c", |
| "src/f32-dwconv/gen/f32-dwconv-2f2m2l16c4s4r-minmax-neonfma-acc2.c", |
| "src/f32-dwconv/gen/f32-dwconv-2f2m2l16c4s4r-minmax-neonfma.c", |
| "src/f32-dwconv/gen/f32-dwconv-3p4c-minmax-neonfma-acc2.c", |
| "src/f32-dwconv/gen/f32-dwconv-3p4c-minmax-neonfma.c", |
| "src/f32-dwconv/gen/f32-dwconv-3p8c-minmax-neonfma-acc2.c", |
| "src/f32-dwconv/gen/f32-dwconv-3p8c-minmax-neonfma.c", |
| "src/f32-dwconv/gen/f32-dwconv-3p16c-minmax-neonfma-acc2.c", |
| "src/f32-dwconv/gen/f32-dwconv-3p16c-minmax-neonfma.c", |
| "src/f32-dwconv/gen/f32-dwconv-4p4c-minmax-neonfma-acc2.c", |
| "src/f32-dwconv/gen/f32-dwconv-4p4c-minmax-neonfma.c", |
| "src/f32-dwconv/gen/f32-dwconv-4p8c-minmax-neonfma-acc2.c", |
| "src/f32-dwconv/gen/f32-dwconv-4p8c-minmax-neonfma.c", |
| "src/f32-dwconv/gen/f32-dwconv-4p16c-minmax-neonfma-acc2.c", |
| "src/f32-dwconv/gen/f32-dwconv-4p16c-minmax-neonfma.c", |
| "src/f32-dwconv/gen/f32-dwconv-5f5m5l4c4s4r-minmax-neonfma-acc2.c", |
| "src/f32-dwconv/gen/f32-dwconv-5f5m5l4c4s4r-minmax-neonfma.c", |
| "src/f32-dwconv/gen/f32-dwconv-5f5m5l8c4s4r-minmax-neonfma-acc2.c", |
| "src/f32-dwconv/gen/f32-dwconv-5f5m5l8c4s4r-minmax-neonfma.c", |
| "src/f32-dwconv/gen/f32-dwconv-6f6m7l4c4s4r-minmax-neonfma-acc2.c", |
| "src/f32-dwconv/gen/f32-dwconv-6f6m7l4c4s4r-minmax-neonfma.c", |
| "src/f32-dwconv/gen/f32-dwconv-6f6m7l8c4s4r-minmax-neonfma-acc2.c", |
| "src/f32-dwconv/gen/f32-dwconv-6f6m7l8c4s4r-minmax-neonfma.c", |
| "src/f32-dwconv/gen/f32-dwconv-8f8m9l4c4s4r-minmax-neonfma-acc2.c", |
| "src/f32-dwconv/gen/f32-dwconv-8f8m9l4c4s4r-minmax-neonfma.c", |
| "src/f32-dwconv/gen/f32-dwconv-8f8m9l8c4s4r-minmax-neonfma-acc2.c", |
| "src/f32-dwconv/gen/f32-dwconv-8f8m9l8c4s4r-minmax-neonfma.c", |
| "src/f32-dwconv/gen/f32-dwconv-9p4c-minmax-neonfma-acc2.c", |
| "src/f32-dwconv/gen/f32-dwconv-9p4c-minmax-neonfma.c", |
| "src/f32-dwconv/gen/f32-dwconv-9p8c-minmax-neonfma-acc2.c", |
| "src/f32-dwconv/gen/f32-dwconv-9p8c-minmax-neonfma.c", |
| "src/f32-dwconv/gen/f32-dwconv-9p16c-minmax-neonfma-acc2.c", |
| "src/f32-dwconv/gen/f32-dwconv-9p16c-minmax-neonfma.c", |
| "src/f32-dwconv/gen/f32-dwconv-25p4c-minmax-neonfma-acc2.c", |
| "src/f32-dwconv/gen/f32-dwconv-25p4c-minmax-neonfma.c", |
| "src/f32-dwconv/gen/f32-dwconv-25p8c-minmax-neonfma-acc2.c", |
| "src/f32-dwconv/gen/f32-dwconv-25p8c-minmax-neonfma.c", |
| "src/f32-dwconv/gen/f32-dwconv-25p16c-minmax-neonfma-acc2.c", |
| "src/f32-dwconv/gen/f32-dwconv-25p16c-minmax-neonfma.c", |
| "src/f32-gemm/gen/f32-gemm-1x8-minmax-neonfma-dup-ld64.c", |
| "src/f32-gemm/gen/f32-gemm-1x8s4-minmax-neonfma.c", |
| "src/f32-gemm/gen/f32-gemm-4x8-minmax-neonfma-dup-ld64.c", |
| "src/f32-gemm/gen/f32-gemm-4x8-minmax-neonfma-dup-ld128.c", |
| "src/f32-gemm/gen/f32-gemm-4x8s4-minmax-neonfma.c", |
| "src/f32-gemm/gen/f32-gemm-6x8-minmax-neonfma-dup-ld64.c", |
| "src/f32-gemm/gen/f32-gemm-6x8-minmax-neonfma-dup-ld128.c", |
| "src/f32-gemm/gen/f32-gemm-6x8s4-minmax-neonfma.c", |
| "src/f32-gemm/gen/f32-gemm-8x8s4-minmax-neonfma.c", |
| "src/f32-gemminc/gen/f32-gemminc-1x8-minmax-neonfma-dup-ld64.c", |
| "src/f32-gemminc/gen/f32-gemminc-1x8s4-minmax-neonfma.c", |
| "src/f32-gemminc/gen/f32-gemminc-4x8-minmax-neonfma-dup-ld64.c", |
| "src/f32-gemminc/gen/f32-gemminc-4x8-minmax-neonfma-dup-ld128.c", |
| "src/f32-gemminc/gen/f32-gemminc-4x8s4-minmax-neonfma.c", |
| "src/f32-gemminc/gen/f32-gemminc-6x8-minmax-neonfma-dup-ld64.c", |
| "src/f32-gemminc/gen/f32-gemminc-6x8-minmax-neonfma-dup-ld128.c", |
| "src/f32-gemminc/gen/f32-gemminc-6x8s4-minmax-neonfma.c", |
| "src/f32-gemminc/gen/f32-gemminc-8x8s4-minmax-neonfma.c", |
| "src/f32-ibilinear-chw/gen/f32-ibilinear-chw-neonfma-p4.c", |
| "src/f32-ibilinear-chw/gen/f32-ibilinear-chw-neonfma-p8.c", |
| "src/f32-ibilinear-chw/gen/f32-ibilinear-chw-neonfma-p16.c", |
| "src/f32-ibilinear/gen/f32-ibilinear-neonfma-c4.c", |
| "src/f32-ibilinear/gen/f32-ibilinear-neonfma-c8.c", |
| "src/f32-igemm/gen/f32-igemm-1x8-minmax-neonfma-dup-ld64.c", |
| "src/f32-igemm/gen/f32-igemm-1x8s4-minmax-neonfma.c", |
| "src/f32-igemm/gen/f32-igemm-4x8-minmax-neonfma-dup-ld64.c", |
| "src/f32-igemm/gen/f32-igemm-4x8-minmax-neonfma-dup-ld128.c", |
| "src/f32-igemm/gen/f32-igemm-4x8s4-minmax-neonfma.c", |
| "src/f32-igemm/gen/f32-igemm-6x8-minmax-neonfma-dup-ld64.c", |
| "src/f32-igemm/gen/f32-igemm-6x8-minmax-neonfma-dup-ld128.c", |
| "src/f32-igemm/gen/f32-igemm-6x8s4-minmax-neonfma.c", |
| "src/f32-igemm/gen/f32-igemm-8x8s4-minmax-neonfma.c", |
| "src/f32-qc4w-gemm/gen/f32-qc4w-gemm-1x8-minmax-neonfma-dup-ld64.c", |
| "src/f32-qc4w-gemm/gen/f32-qc4w-gemm-4x8-minmax-neonfma-dup-ld64.c", |
| "src/f32-qc4w-gemm/gen/f32-qc4w-gemm-6x8-minmax-neonfma-dup-ld64.c", |
| "src/f32-qc8w-gemm/gen/f32-qc8w-gemm-1x8-minmax-neonfma-dup-ld64.c", |
| "src/f32-qc8w-gemm/gen/f32-qc8w-gemm-1x8s4-minmax-neonfma.c", |
| "src/f32-qc8w-gemm/gen/f32-qc8w-gemm-4x8-minmax-neonfma-dup-ld64.c", |
| "src/f32-qc8w-gemm/gen/f32-qc8w-gemm-4x8s4-minmax-neonfma.c", |
| "src/f32-qc8w-gemm/gen/f32-qc8w-gemm-6x8-minmax-neonfma-dup-ld64.c", |
| "src/f32-qc8w-gemm/gen/f32-qc8w-gemm-6x8s4-minmax-neonfma.c", |
| "src/f32-raddstoreexpminusmax/gen/f32-raddstoreexpminusmax-neonfma-rr1-lut64-p2-u4.c", |
| "src/f32-raddstoreexpminusmax/gen/f32-raddstoreexpminusmax-neonfma-rr1-lut64-p2-u8-acc2.c", |
| "src/f32-raddstoreexpminusmax/gen/f32-raddstoreexpminusmax-neonfma-rr1-lut64-p2-u8.c", |
| "src/f32-raddstoreexpminusmax/gen/f32-raddstoreexpminusmax-neonfma-rr1-lut64-p2-u12-acc2.c", |
| "src/f32-raddstoreexpminusmax/gen/f32-raddstoreexpminusmax-neonfma-rr1-lut64-p2-u12-acc3.c", |
| "src/f32-raddstoreexpminusmax/gen/f32-raddstoreexpminusmax-neonfma-rr1-lut64-p2-u12.c", |
| "src/f32-raddstoreexpminusmax/gen/f32-raddstoreexpminusmax-neonfma-rr1-lut64-p2-u16-acc2.c", |
| "src/f32-raddstoreexpminusmax/gen/f32-raddstoreexpminusmax-neonfma-rr1-lut64-p2-u16-acc4.c", |
| "src/f32-raddstoreexpminusmax/gen/f32-raddstoreexpminusmax-neonfma-rr1-lut64-p2-u16.c", |
| "src/f32-raddstoreexpminusmax/gen/f32-raddstoreexpminusmax-neonfma-rr1-lut64-p2-u20-acc2.c", |
| "src/f32-raddstoreexpminusmax/gen/f32-raddstoreexpminusmax-neonfma-rr1-lut64-p2-u20-acc5.c", |
| "src/f32-raddstoreexpminusmax/gen/f32-raddstoreexpminusmax-neonfma-rr1-lut64-p2-u20.c", |
| "src/f32-raddstoreexpminusmax/gen/f32-raddstoreexpminusmax-neonfma-rr1-p5-u4.c", |
| "src/f32-raddstoreexpminusmax/gen/f32-raddstoreexpminusmax-neonfma-rr1-p5-u8-acc2.c", |
| "src/f32-raddstoreexpminusmax/gen/f32-raddstoreexpminusmax-neonfma-rr1-p5-u8.c", |
| "src/f32-raddstoreexpminusmax/gen/f32-raddstoreexpminusmax-neonfma-rr1-p5-u12-acc2.c", |
| "src/f32-raddstoreexpminusmax/gen/f32-raddstoreexpminusmax-neonfma-rr1-p5-u12-acc3.c", |
| "src/f32-raddstoreexpminusmax/gen/f32-raddstoreexpminusmax-neonfma-rr1-p5-u12.c", |
| "src/f32-raddstoreexpminusmax/gen/f32-raddstoreexpminusmax-neonfma-rr1-p5-u16-acc2.c", |
| "src/f32-raddstoreexpminusmax/gen/f32-raddstoreexpminusmax-neonfma-rr1-p5-u16-acc4.c", |
| "src/f32-raddstoreexpminusmax/gen/f32-raddstoreexpminusmax-neonfma-rr1-p5-u16.c", |
| "src/f32-raddstoreexpminusmax/gen/f32-raddstoreexpminusmax-neonfma-rr1-p5-u20-acc2.c", |
| "src/f32-raddstoreexpminusmax/gen/f32-raddstoreexpminusmax-neonfma-rr1-p5-u20-acc5.c", |
| "src/f32-raddstoreexpminusmax/gen/f32-raddstoreexpminusmax-neonfma-rr1-p5-u20.c", |
| "src/f32-spmm/gen/f32-spmm-4x1-minmax-neonfma-pipelined.c", |
| "src/f32-spmm/gen/f32-spmm-4x1-minmax-neonfma-x2.c", |
| "src/f32-spmm/gen/f32-spmm-4x1-minmax-neonfma.c", |
| "src/f32-spmm/gen/f32-spmm-8x1-minmax-neonfma-pipelined.c", |
| "src/f32-spmm/gen/f32-spmm-8x1-minmax-neonfma-x2.c", |
| "src/f32-spmm/gen/f32-spmm-8x1-minmax-neonfma.c", |
| "src/f32-spmm/gen/f32-spmm-12x1-minmax-neonfma.c", |
| "src/f32-spmm/gen/f32-spmm-16x1-minmax-neonfma-pipelined.c", |
| "src/f32-spmm/gen/f32-spmm-16x1-minmax-neonfma-x2.c", |
| "src/f32-spmm/gen/f32-spmm-16x1-minmax-neonfma.c", |
| "src/f32-spmm/gen/f32-spmm-32x1-minmax-neonfma-pipelined.c", |
| "src/f32-spmm/gen/f32-spmm-32x1-minmax-neonfma-x2.c", |
| "src/f32-spmm/gen/f32-spmm-32x1-minmax-neonfma.c", |
| "src/f32-velu/gen/f32-velu-neonfma-rr1-lut16-p3-u4.c", |
| "src/f32-velu/gen/f32-velu-neonfma-rr1-lut16-p3-u8.c", |
| "src/f32-velu/gen/f32-velu-neonfma-rr1-lut16-p3-u12.c", |
| "src/f32-velu/gen/f32-velu-neonfma-rr1-lut16-p3-u16.c", |
| "src/f32-velu/gen/f32-velu-neonfma-rr1-lut16-p3-u20.c", |
| "src/f32-velu/gen/f32-velu-neonfma-rr1-lut16-p3-u24.c", |
| "src/f32-velu/gen/f32-velu-neonfma-rr1-p6-u4.c", |
| "src/f32-velu/gen/f32-velu-neonfma-rr1-p6-u8.c", |
| "src/f32-velu/gen/f32-velu-neonfma-rr1-p6-u12.c", |
| "src/f32-velu/gen/f32-velu-neonfma-rr1-p6-u16.c", |
| "src/f32-velu/gen/f32-velu-neonfma-rr1-p6-u20.c", |
| "src/f32-velu/gen/f32-velu-neonfma-rr1-p6-u24.c", |
| "src/f32-vmulcaddc/gen/f32-vmulcaddc-c4-minmax-neonfma-2x.c", |
| "src/f32-vmulcaddc/gen/f32-vmulcaddc-c8-minmax-neonfma-2x.c", |
| "src/f32-vsigmoid/gen/f32-vsigmoid-neonfma-rr1-lut64-p2-nr1recps1fma-u4.c", |
| "src/f32-vsigmoid/gen/f32-vsigmoid-neonfma-rr1-lut64-p2-nr1recps1fma-u8.c", |
| "src/f32-vsigmoid/gen/f32-vsigmoid-neonfma-rr1-lut64-p2-nr1recps1fma-u12.c", |
| "src/f32-vsigmoid/gen/f32-vsigmoid-neonfma-rr1-lut64-p2-nr1recps1fma-u16.c", |
| "src/f32-vsigmoid/gen/f32-vsigmoid-neonfma-rr1-lut64-p2-nr1recps1fma-u20.c", |
| "src/f32-vsigmoid/gen/f32-vsigmoid-neonfma-rr1-lut64-p2-nr1recps1fma-u24.c", |
| "src/f32-vsigmoid/gen/f32-vsigmoid-neonfma-rr1-lut64-p2-nr2fma-u4.c", |
| "src/f32-vsigmoid/gen/f32-vsigmoid-neonfma-rr1-lut64-p2-nr2fma-u8.c", |
| "src/f32-vsigmoid/gen/f32-vsigmoid-neonfma-rr1-lut64-p2-nr2fma-u12.c", |
| "src/f32-vsigmoid/gen/f32-vsigmoid-neonfma-rr1-lut64-p2-nr2fma-u16.c", |
| "src/f32-vsigmoid/gen/f32-vsigmoid-neonfma-rr1-lut64-p2-nr2fma-u20.c", |
| "src/f32-vsigmoid/gen/f32-vsigmoid-neonfma-rr1-lut64-p2-nr2fma-u24.c", |
| "src/f32-vsigmoid/gen/f32-vsigmoid-neonfma-rr1-lut64-p2-nr2recps-u4.c", |
| "src/f32-vsigmoid/gen/f32-vsigmoid-neonfma-rr1-lut64-p2-nr2recps-u8.c", |
| "src/f32-vsigmoid/gen/f32-vsigmoid-neonfma-rr1-lut64-p2-nr2recps-u12.c", |
| "src/f32-vsigmoid/gen/f32-vsigmoid-neonfma-rr1-lut64-p2-nr2recps-u16.c", |
| "src/f32-vsigmoid/gen/f32-vsigmoid-neonfma-rr1-lut64-p2-nr2recps-u20.c", |
| "src/f32-vsigmoid/gen/f32-vsigmoid-neonfma-rr1-lut64-p2-nr2recps-u24.c", |
| "src/f32-vsigmoid/gen/f32-vsigmoid-neonfma-rr1-lut2048-p1-nr1recps1fma-u4.c", |
| "src/f32-vsigmoid/gen/f32-vsigmoid-neonfma-rr1-lut2048-p1-nr1recps1fma-u8.c", |
| "src/f32-vsigmoid/gen/f32-vsigmoid-neonfma-rr1-lut2048-p1-nr1recps1fma-u12.c", |
| "src/f32-vsigmoid/gen/f32-vsigmoid-neonfma-rr1-lut2048-p1-nr1recps1fma-u16.c", |
| "src/f32-vsigmoid/gen/f32-vsigmoid-neonfma-rr1-lut2048-p1-nr1recps1fma-u20.c", |
| "src/f32-vsigmoid/gen/f32-vsigmoid-neonfma-rr1-lut2048-p1-nr1recps1fma-u24.c", |
| "src/f32-vsigmoid/gen/f32-vsigmoid-neonfma-rr1-lut2048-p1-nr2fma-u4.c", |
| "src/f32-vsigmoid/gen/f32-vsigmoid-neonfma-rr1-lut2048-p1-nr2fma-u8.c", |
| "src/f32-vsigmoid/gen/f32-vsigmoid-neonfma-rr1-lut2048-p1-nr2fma-u12.c", |
| "src/f32-vsigmoid/gen/f32-vsigmoid-neonfma-rr1-lut2048-p1-nr2fma-u16.c", |
| "src/f32-vsigmoid/gen/f32-vsigmoid-neonfma-rr1-lut2048-p1-nr2fma-u20.c", |
| "src/f32-vsigmoid/gen/f32-vsigmoid-neonfma-rr1-lut2048-p1-nr2fma-u24.c", |
| "src/f32-vsigmoid/gen/f32-vsigmoid-neonfma-rr1-lut2048-p1-nr2recps-u4.c", |
| "src/f32-vsigmoid/gen/f32-vsigmoid-neonfma-rr1-lut2048-p1-nr2recps-u8.c", |
| "src/f32-vsigmoid/gen/f32-vsigmoid-neonfma-rr1-lut2048-p1-nr2recps-u12.c", |
| "src/f32-vsigmoid/gen/f32-vsigmoid-neonfma-rr1-lut2048-p1-nr2recps-u16.c", |
| "src/f32-vsigmoid/gen/f32-vsigmoid-neonfma-rr1-lut2048-p1-nr2recps-u20.c", |
| "src/f32-vsigmoid/gen/f32-vsigmoid-neonfma-rr1-lut2048-p1-nr2recps-u24.c", |
| "src/f32-vsigmoid/gen/f32-vsigmoid-neonfma-rr1-p5-nr1recps1fma-u4.c", |
| "src/f32-vsigmoid/gen/f32-vsigmoid-neonfma-rr1-p5-nr1recps1fma-u8.c", |
| "src/f32-vsigmoid/gen/f32-vsigmoid-neonfma-rr1-p5-nr1recps1fma-u12.c", |
| "src/f32-vsigmoid/gen/f32-vsigmoid-neonfma-rr1-p5-nr1recps1fma-u16.c", |
| "src/f32-vsigmoid/gen/f32-vsigmoid-neonfma-rr1-p5-nr1recps1fma-u20.c", |
| "src/f32-vsigmoid/gen/f32-vsigmoid-neonfma-rr1-p5-nr1recps1fma-u24.c", |
| "src/f32-vsigmoid/gen/f32-vsigmoid-neonfma-rr1-p5-nr2fma-u4.c", |
| "src/f32-vsigmoid/gen/f32-vsigmoid-neonfma-rr1-p5-nr2fma-u8.c", |
| "src/f32-vsigmoid/gen/f32-vsigmoid-neonfma-rr1-p5-nr2fma-u12.c", |
| "src/f32-vsigmoid/gen/f32-vsigmoid-neonfma-rr1-p5-nr2fma-u16.c", |
| "src/f32-vsigmoid/gen/f32-vsigmoid-neonfma-rr1-p5-nr2fma-u20.c", |
| "src/f32-vsigmoid/gen/f32-vsigmoid-neonfma-rr1-p5-nr2fma-u24.c", |
| "src/f32-vsigmoid/gen/f32-vsigmoid-neonfma-rr1-p5-nr2recps-u4.c", |
| "src/f32-vsigmoid/gen/f32-vsigmoid-neonfma-rr1-p5-nr2recps-u8.c", |
| "src/f32-vsigmoid/gen/f32-vsigmoid-neonfma-rr1-p5-nr2recps-u12.c", |
| "src/f32-vsigmoid/gen/f32-vsigmoid-neonfma-rr1-p5-nr2recps-u16.c", |
| "src/f32-vsigmoid/gen/f32-vsigmoid-neonfma-rr1-p5-nr2recps-u20.c", |
| "src/f32-vsigmoid/gen/f32-vsigmoid-neonfma-rr1-p5-nr2recps-u24.c", |
| "src/f32-vsqrt/gen/f32-vsqrt-neonfma-nr1rsqrts1fma1adj-u4.c", |
| "src/f32-vsqrt/gen/f32-vsqrt-neonfma-nr1rsqrts1fma1adj-u8.c", |
| "src/f32-vsqrt/gen/f32-vsqrt-neonfma-nr1rsqrts1fma1adj-u12.c", |
| "src/f32-vsqrt/gen/f32-vsqrt-neonfma-nr1rsqrts1fma1adj-u16.c", |
| "src/f32-vsqrt/gen/f32-vsqrt-neonfma-nr1rsqrts1fma1adj-u20.c", |
| "src/f32-vsqrt/gen/f32-vsqrt-neonfma-nr1rsqrts1fma1adj-u24.c", |
| "src/f32-vsqrt/gen/f32-vsqrt-neonfma-nr1rsqrts1fma1adj-u28.c", |
| "src/f32-vsqrt/gen/f32-vsqrt-neonfma-nr1rsqrts1fma1adj-u32.c", |
| "src/f32-vsqrt/gen/f32-vsqrt-neonfma-nr1rsqrts1fma1adj-u36.c", |
| "src/f32-vsqrt/gen/f32-vsqrt-neonfma-nr1rsqrts1fma1adj-u40.c", |
| "src/f32-vsqrt/gen/f32-vsqrt-neonfma-nr2fma1adj-u4.c", |
| "src/f32-vsqrt/gen/f32-vsqrt-neonfma-nr2fma1adj-u8.c", |
| "src/f32-vsqrt/gen/f32-vsqrt-neonfma-nr2fma1adj-u12.c", |
| "src/f32-vsqrt/gen/f32-vsqrt-neonfma-nr2fma1adj-u16.c", |
| "src/f32-vsqrt/gen/f32-vsqrt-neonfma-nr2fma1adj-u20.c", |
| "src/f32-vsqrt/gen/f32-vsqrt-neonfma-nr2fma1adj-u24.c", |
| "src/f32-vsqrt/gen/f32-vsqrt-neonfma-nr2fma1adj-u28.c", |
| "src/f32-vsqrt/gen/f32-vsqrt-neonfma-nr2fma1adj-u32.c", |
| "src/f32-vsqrt/gen/f32-vsqrt-neonfma-nr2fma1adj-u36.c", |
| "src/f32-vsqrt/gen/f32-vsqrt-neonfma-nr2fma1adj-u40.c", |
| "src/f32-vtanh/gen/f32-vtanh-neonfma-expm1minus-rr1-lut8-p4h3ts-nr1recps1fma-u4.c", |
| "src/f32-vtanh/gen/f32-vtanh-neonfma-expm1minus-rr1-lut8-p4h3ts-nr1recps1fma-u8.c", |
| "src/f32-vtanh/gen/f32-vtanh-neonfma-expm1minus-rr1-lut8-p4h3ts-nr1recps1fma-u12.c", |
| "src/f32-vtanh/gen/f32-vtanh-neonfma-expm1minus-rr1-lut8-p4h3ts-nr1recps1fma-u16.c", |
| "src/f32-vtanh/gen/f32-vtanh-neonfma-expm1minus-rr1-lut8-p4h3ts-nr2fma-u4.c", |
| "src/f32-vtanh/gen/f32-vtanh-neonfma-expm1minus-rr1-lut8-p4h3ts-nr2fma-u8.c", |
| "src/f32-vtanh/gen/f32-vtanh-neonfma-expm1minus-rr1-lut8-p4h3ts-nr2fma-u12.c", |
| "src/f32-vtanh/gen/f32-vtanh-neonfma-expm1minus-rr1-lut8-p4h3ts-nr2fma-u16.c", |
| "src/f32-vtanh/gen/f32-vtanh-neonfma-expm1minus-rr1-p6h5ts-nr1recps1fma-u4.c", |
| "src/f32-vtanh/gen/f32-vtanh-neonfma-expm1minus-rr1-p6h5ts-nr1recps1fma-u8.c", |
| "src/f32-vtanh/gen/f32-vtanh-neonfma-expm1minus-rr1-p6h5ts-nr1recps1fma-u12.c", |
| "src/f32-vtanh/gen/f32-vtanh-neonfma-expm1minus-rr1-p6h5ts-nr1recps1fma-u16.c", |
| "src/f32-vtanh/gen/f32-vtanh-neonfma-expm1minus-rr1-p6h5ts-nr2fma-u4.c", |
| "src/f32-vtanh/gen/f32-vtanh-neonfma-expm1minus-rr1-p6h5ts-nr2fma-u8.c", |
| "src/f32-vtanh/gen/f32-vtanh-neonfma-expm1minus-rr1-p6h5ts-nr2fma-u12.c", |
| "src/f32-vtanh/gen/f32-vtanh-neonfma-expm1minus-rr1-p6h5ts-nr2fma-u16.c", |
| "src/f32-vtanh/gen/f32-vtanh-neonfma-expm1minus-rr1-p6h5ts-nr2recps-u4.c", |
| "src/f32-vtanh/gen/f32-vtanh-neonfma-expm1minus-rr1-p6h5ts-nr2recps-u8.c", |
| "src/f32-vtanh/gen/f32-vtanh-neonfma-expm1minus-rr1-p6h5ts-nr2recps-u12.c", |
| "src/f32-vtanh/gen/f32-vtanh-neonfma-expm1minus-rr1-p6h5ts-nr2recps-u16.c", |
| "src/math/f32-exp-neonfma-rr2-lut64-p2.c", |
| "src/math/f32-exp-neonfma-rr2-p5.c", |
| "src/math/f32-expm1minus-neonfma-rr1-lut16-p3.c", |
| "src/math/f32-expm1minus-neonfma-rr1-p6.c", |
| "src/math/f32-expminus-neonfma-rr2-lut64-p2.c", |
| "src/math/f32-expminus-neonfma-rr2-lut2048-p1.c", |
| "src/math/f32-expminus-neonfma-rr2-p5.c", |
| "src/math/f32-sigmoid-neonfma-rr1-lut64-p2-nr1recps1fma.c", |
| "src/math/f32-sigmoid-neonfma-rr1-lut64-p2-nr2fma.c", |
| "src/math/f32-sigmoid-neonfma-rr1-lut64-p2-nr2recps.c", |
| "src/math/f32-sigmoid-neonfma-rr1-lut2048-p1-nr1recps1fma.c", |
| "src/math/f32-sigmoid-neonfma-rr1-lut2048-p1-nr2fma.c", |
| "src/math/f32-sigmoid-neonfma-rr1-lut2048-p1-nr2recps.c", |
| "src/math/f32-sigmoid-neonfma-rr1-p5-nr1recps1fma.c", |
| "src/math/f32-sigmoid-neonfma-rr1-p5-nr2fma.c", |
| "src/math/f32-sigmoid-neonfma-rr1-p5-nr2recps.c", |
| "src/math/f32-sigmoid-neonfma-rr2-lut64-p2-nr1recps1fma.c", |
| "src/math/f32-sigmoid-neonfma-rr2-lut64-p2-nr2fma.c", |
| "src/math/f32-sigmoid-neonfma-rr2-lut64-p2-nr2recps.c", |
| "src/math/f32-sigmoid-neonfma-rr2-lut2048-p1-nr1recps1fma.c", |
| "src/math/f32-sigmoid-neonfma-rr2-lut2048-p1-nr2fma.c", |
| "src/math/f32-sigmoid-neonfma-rr2-lut2048-p1-nr2recps.c", |
| "src/math/f32-sigmoid-neonfma-rr2-p5-nr1recps1fma.c", |
| "src/math/f32-sigmoid-neonfma-rr2-p5-nr2fma.c", |
| "src/math/f32-sigmoid-neonfma-rr2-p5-nr2recps.c", |
| "src/math/f32-sqrt-neonfma-nr1fma.c", |
| "src/math/f32-sqrt-neonfma-nr1rsqrts1fma1adj.c", |
| "src/math/f32-sqrt-neonfma-nr2fma1adj.c", |
| "src/math/f32-sqrt-neonfma-nr2fma.c", |
| "src/math/f32-sqrt-neonfma-nr3fma.c", |
| "src/math/gen/f32-tanh-neonfma-expm1minus-rr1-lut8-p4h2ts-nr1recps1fma.c", |
| "src/math/gen/f32-tanh-neonfma-expm1minus-rr1-lut8-p4h2ts-nr2fma.c", |
| "src/math/gen/f32-tanh-neonfma-expm1minus-rr1-lut8-p4h2ts-nr2recps.c", |
| "src/math/gen/f32-tanh-neonfma-expm1minus-rr1-lut8-p4h3ps-nr1recps1fma.c", |
| "src/math/gen/f32-tanh-neonfma-expm1minus-rr1-lut8-p4h3ps-nr1recps1fmaadj.c", |
| "src/math/gen/f32-tanh-neonfma-expm1minus-rr1-lut8-p4h3ps-nr2fma.c", |
| "src/math/gen/f32-tanh-neonfma-expm1minus-rr1-lut8-p4h3ps-nr2fmaadj.c", |
| "src/math/gen/f32-tanh-neonfma-expm1minus-rr1-lut8-p4h3ps-nr2recps.c", |
| "src/math/gen/f32-tanh-neonfma-expm1minus-rr1-lut8-p4h3ps-nr2recpsadj.c", |
| "src/math/gen/f32-tanh-neonfma-expm1minus-rr1-p6h5ts-nr1recps1fma.c", |
| "src/math/gen/f32-tanh-neonfma-expm1minus-rr1-p6h5ts-nr1recps1fmaadj.c", |
| "src/math/gen/f32-tanh-neonfma-expm1minus-rr1-p6h5ts-nr2fma.c", |
| "src/math/gen/f32-tanh-neonfma-expm1minus-rr1-p6h5ts-nr2fmaadj.c", |
| "src/math/gen/f32-tanh-neonfma-expm1minus-rr1-p6h5ts-nr2recps.c", |
| "src/math/gen/f32-tanh-neonfma-expm1minus-rr1-p6h5ts-nr2recpsadj.c", |
| ] |
| |
| ALL_NEONFMA_AARCH64_MICROKERNEL_SRCS = [ |
| "src/f32-conv-hwc2chw/f32-conv-hwc2chw-3x3s2p1c3x4-aarch64-neonfma-2x2.c", |
| "src/f32-conv-hwc/gen/f32-conv-hwc-3x3s2p0p1c3x4-aarch64-neonfma-2x1.c", |
| "src/f32-conv-hwc/gen/f32-conv-hwc-3x3s2p0p1c3x4-aarch64-neonfma-2x2.c", |
| "src/f32-conv-hwc/gen/f32-conv-hwc-3x3s2p0p1c3x8-aarch64-neonfma-2x1.c", |
| "src/f32-conv-hwc/gen/f32-conv-hwc-3x3s2p0p1c3x8-aarch64-neonfma-2x2.c", |
| "src/f32-conv-hwc/gen/f32-conv-hwc-3x3s2p1c3x4-aarch64-neonfma-2x1.c", |
| "src/f32-conv-hwc/gen/f32-conv-hwc-3x3s2p1c3x4-aarch64-neonfma-2x2.c", |
| "src/f32-conv-hwc/gen/f32-conv-hwc-3x3s2p1c3x8-aarch64-neonfma-2x1.c", |
| "src/f32-conv-hwc/gen/f32-conv-hwc-3x3s2p1c3x8-aarch64-neonfma-2x2.c", |
| "src/f32-dwconv2d-chw/gen/f32-dwconv2d-chw-3x3p1-minmax-aarch64-neonfma-1x4-acc2.c", |
| "src/f32-dwconv2d-chw/gen/f32-dwconv2d-chw-3x3p1-minmax-aarch64-neonfma-1x4-acc3.c", |
| "src/f32-dwconv2d-chw/gen/f32-dwconv2d-chw-3x3p1-minmax-aarch64-neonfma-1x4-acc4.c", |
| "src/f32-dwconv2d-chw/gen/f32-dwconv2d-chw-3x3p1-minmax-aarch64-neonfma-1x4.c", |
| "src/f32-dwconv2d-chw/gen/f32-dwconv2d-chw-3x3p1-minmax-aarch64-neonfma-2x4-acc2.c", |
| "src/f32-dwconv2d-chw/gen/f32-dwconv2d-chw-3x3p1-minmax-aarch64-neonfma-2x4.c", |
| "src/f32-dwconv2d-chw/gen/f32-dwconv2d-chw-3x3p1-minmax-aarch64-neonfma-3x4.c", |
| "src/f32-dwconv2d-chw/gen/f32-dwconv2d-chw-3x3p1-minmax-aarch64-neonfma-4x4.c", |
| "src/f32-dwconv2d-chw/gen/f32-dwconv2d-chw-3x3p1-minmax-aarch64-neonfma-5x4.c", |
| "src/f32-dwconv2d-chw/gen/f32-dwconv2d-chw-3x3p1-minmax-aarch64-neonfma-6x4.c", |
| "src/f32-dwconv2d-chw/gen/f32-dwconv2d-chw-3x3s2p1-minmax-aarch64-neonfma-1x4-acc2.c", |
| "src/f32-dwconv2d-chw/gen/f32-dwconv2d-chw-3x3s2p1-minmax-aarch64-neonfma-1x4-acc3.c", |
| "src/f32-dwconv2d-chw/gen/f32-dwconv2d-chw-3x3s2p1-minmax-aarch64-neonfma-1x4-acc4.c", |
| "src/f32-dwconv2d-chw/gen/f32-dwconv2d-chw-3x3s2p1-minmax-aarch64-neonfma-1x4.c", |
| "src/f32-dwconv2d-chw/gen/f32-dwconv2d-chw-3x3s2p1-minmax-aarch64-neonfma-2x4-acc2.c", |
| "src/f32-dwconv2d-chw/gen/f32-dwconv2d-chw-3x3s2p1-minmax-aarch64-neonfma-2x4.c", |
| "src/f32-dwconv2d-chw/gen/f32-dwconv2d-chw-3x3s2p1-minmax-aarch64-neonfma-3x4.c", |
| "src/f32-dwconv2d-chw/gen/f32-dwconv2d-chw-3x3s2p1-minmax-aarch64-neonfma-4x4.c", |
| "src/f32-dwconv2d-chw/gen/f32-dwconv2d-chw-5x5p2-minmax-aarch64-neonfma-1x4-acc2.c", |
| "src/f32-dwconv2d-chw/gen/f32-dwconv2d-chw-5x5p2-minmax-aarch64-neonfma-1x4-acc3.c", |
| "src/f32-dwconv2d-chw/gen/f32-dwconv2d-chw-5x5p2-minmax-aarch64-neonfma-1x4-acc4.c", |
| "src/f32-dwconv2d-chw/gen/f32-dwconv2d-chw-5x5p2-minmax-aarch64-neonfma-1x4-acc5.c", |
| "src/f32-dwconv2d-chw/gen/f32-dwconv2d-chw-5x5p2-minmax-aarch64-neonfma-1x4.c", |
| "src/f32-dwconv2d-chw/gen/f32-dwconv2d-chw-5x5p2-minmax-aarch64-neonfma-2x4-acc2.c", |
| "src/f32-dwconv2d-chw/gen/f32-dwconv2d-chw-5x5p2-minmax-aarch64-neonfma-2x4-acc3.c", |
| "src/f32-dwconv2d-chw/gen/f32-dwconv2d-chw-5x5p2-minmax-aarch64-neonfma-2x4.c", |
| "src/f32-dwconv2d-chw/gen/f32-dwconv2d-chw-5x5p2-minmax-aarch64-neonfma-3x4-acc2.c", |
| "src/f32-dwconv2d-chw/gen/f32-dwconv2d-chw-5x5p2-minmax-aarch64-neonfma-3x4.c", |
| "src/f32-dwconv2d-chw/gen/f32-dwconv2d-chw-5x5p2-minmax-aarch64-neonfma-4x4-acc2.c", |
| "src/f32-dwconv2d-chw/gen/f32-dwconv2d-chw-5x5p2-minmax-aarch64-neonfma-4x4.c", |
| "src/f32-dwconv2d-chw/gen/f32-dwconv2d-chw-5x5p2-minmax-aarch64-neonfma-5x4.c", |
| "src/f32-dwconv2d-chw/gen/f32-dwconv2d-chw-5x5s2p2-minmax-aarch64-neonfma-1x4-acc2.c", |
| "src/f32-dwconv2d-chw/gen/f32-dwconv2d-chw-5x5s2p2-minmax-aarch64-neonfma-1x4-acc3.c", |
| "src/f32-dwconv2d-chw/gen/f32-dwconv2d-chw-5x5s2p2-minmax-aarch64-neonfma-1x4-acc4.c", |
| "src/f32-dwconv2d-chw/gen/f32-dwconv2d-chw-5x5s2p2-minmax-aarch64-neonfma-1x4-acc5.c", |
| "src/f32-dwconv2d-chw/gen/f32-dwconv2d-chw-5x5s2p2-minmax-aarch64-neonfma-1x4.c", |
| "src/f32-dwconv2d-chw/gen/f32-dwconv2d-chw-5x5s2p2-minmax-aarch64-neonfma-2x4-acc2.c", |
| "src/f32-dwconv2d-chw/gen/f32-dwconv2d-chw-5x5s2p2-minmax-aarch64-neonfma-2x4-acc3.c", |
| "src/f32-dwconv2d-chw/gen/f32-dwconv2d-chw-5x5s2p2-minmax-aarch64-neonfma-2x4.c", |
| "src/f32-dwconv2d-chw/gen/f32-dwconv2d-chw-5x5s2p2-minmax-aarch64-neonfma-3x4-acc2.c", |
| "src/f32-dwconv2d-chw/gen/f32-dwconv2d-chw-5x5s2p2-minmax-aarch64-neonfma-3x4.c", |
| "src/f32-gemm/gen/f32-gemm-1x8-minmax-aarch64-neonfma-lane-ld64.c", |
| "src/f32-gemm/gen/f32-gemm-1x16-minmax-aarch64-neonfma-lane-ld128.c", |
| "src/f32-gemm/gen/f32-gemm-4x2-minmax-aarch64-neonfma-lane-ld64.c", |
| "src/f32-gemm/gen/f32-gemm-4x8-minmax-aarch64-neonfma-lane-ld64.c", |
| "src/f32-gemm/gen/f32-gemm-4x8-minmax-aarch64-neonfma-lane-ld128.c", |
| "src/f32-gemm/gen/f32-gemm-4x16-minmax-aarch64-neonfma-lane-ld128.c", |
| "src/f32-gemm/gen/f32-gemm-5x8-minmax-aarch64-neonfma-lane-ld64.c", |
| "src/f32-gemm/gen/f32-gemm-6x2-minmax-aarch64-neonfma-lane-ld64.c", |
| "src/f32-gemm/gen/f32-gemm-6x8-minmax-aarch64-neonfma-lane-ld64.c", |
| "src/f32-gemm/gen/f32-gemm-6x8-minmax-aarch64-neonfma-lane-ld128.c", |
| "src/f32-gemminc/gen/f32-gemminc-1x8-minmax-aarch64-neonfma-lane-ld64.c", |
| "src/f32-gemminc/gen/f32-gemminc-4x8-minmax-aarch64-neonfma-lane-ld64.c", |
| "src/f32-gemminc/gen/f32-gemminc-4x8-minmax-aarch64-neonfma-lane-ld128.c", |
| "src/f32-gemminc/gen/f32-gemminc-5x8-minmax-aarch64-neonfma-lane-ld64.c", |
| "src/f32-gemminc/gen/f32-gemminc-6x8-minmax-aarch64-neonfma-lane-ld64.c", |
| "src/f32-gemminc/gen/f32-gemminc-6x8-minmax-aarch64-neonfma-lane-ld128.c", |
| "src/f32-igemm/gen/f32-igemm-1x8-minmax-aarch64-neonfma-lane-ld64.c", |
| "src/f32-igemm/gen/f32-igemm-4x2-minmax-aarch64-neonfma-lane-ld64.c", |
| "src/f32-igemm/gen/f32-igemm-4x4-minmax-aarch64-neonfma-lane-ld64.c", |
| "src/f32-igemm/gen/f32-igemm-4x8-minmax-aarch64-neonfma-lane-ld64.c", |
| "src/f32-igemm/gen/f32-igemm-4x8-minmax-aarch64-neonfma-lane-ld128.c", |
| "src/f32-igemm/gen/f32-igemm-6x2-minmax-aarch64-neonfma-lane-ld64.c", |
| "src/f32-igemm/gen/f32-igemm-6x8-minmax-aarch64-neonfma-lane-ld64.c", |
| "src/f32-igemm/gen/f32-igemm-6x8-minmax-aarch64-neonfma-lane-ld128.c", |
| "src/f32-ppmm/gen/f32-ppmm-4x8-minmax-aarch64-neonfma-prfm.c", |
| "src/f32-ppmm/gen/f32-ppmm-4x8-minmax-aarch64-neonfma.c", |
| "src/f32-ppmm/gen/f32-ppmm-4x16-minmax-aarch64-neonfma-prfm.c", |
| "src/f32-ppmm/gen/f32-ppmm-4x16-minmax-aarch64-neonfma.c", |
| "src/f32-ppmm/gen/f32-ppmm-8x8-minmax-aarch64-neonfma-prfm.c", |
| "src/f32-ppmm/gen/f32-ppmm-8x8-minmax-aarch64-neonfma.c", |
| "src/f32-qc4w-gemm/gen/f32-qc4w-gemm-1x8-minmax-aarch64-neonfma-lane-ld64.c", |
| "src/f32-qc4w-gemm/gen/f32-qc4w-gemm-1x8-minmax-aarch64-neonfma-lane-ld128.c", |
| "src/f32-qc4w-gemm/gen/f32-qc4w-gemm-4x8-minmax-aarch64-neonfma-lane-ld64.c", |
| "src/f32-qc4w-gemm/gen/f32-qc4w-gemm-4x8-minmax-aarch64-neonfma-lane-ld128.c", |
| "src/f32-qc4w-gemm/gen/f32-qc4w-gemm-5x8-minmax-aarch64-neonfma-lane-ld64.c", |
| "src/f32-qc4w-gemm/gen/f32-qc4w-gemm-6x8-minmax-aarch64-neonfma-lane-ld64.c", |
| "src/f32-qc4w-gemm/gen/f32-qc4w-gemm-6x8-minmax-aarch64-neonfma-lane-ld128.c", |
| "src/f32-qc8w-gemm/gen/f32-qc8w-gemm-1x8-minmax-aarch64-neonfma-lane-ld64.c", |
| "src/f32-qc8w-gemm/gen/f32-qc8w-gemm-1x8-minmax-aarch64-neonfma-lane-ld128.c", |
| "src/f32-qc8w-gemm/gen/f32-qc8w-gemm-1x16-minmax-aarch64-neonfma-lane-ld128.c", |
| "src/f32-qc8w-gemm/gen/f32-qc8w-gemm-4x2-minmax-aarch64-neonfma-lane-ld64.c", |
| "src/f32-qc8w-gemm/gen/f32-qc8w-gemm-4x8-minmax-aarch64-neonfma-lane-ld64.c", |
| "src/f32-qc8w-gemm/gen/f32-qc8w-gemm-4x8-minmax-aarch64-neonfma-lane-ld128.c", |
| "src/f32-qc8w-gemm/gen/f32-qc8w-gemm-4x16-minmax-aarch64-neonfma-lane-ld128.c", |
| "src/f32-qc8w-gemm/gen/f32-qc8w-gemm-5x8-minmax-aarch64-neonfma-lane-ld64.c", |
| "src/f32-qc8w-gemm/gen/f32-qc8w-gemm-6x2-minmax-aarch64-neonfma-lane-ld64.c", |
| "src/f32-qc8w-gemm/gen/f32-qc8w-gemm-6x8-minmax-aarch64-neonfma-lane-ld64.c", |
| "src/f32-qc8w-gemm/gen/f32-qc8w-gemm-6x8-minmax-aarch64-neonfma-lane-ld128.c", |
| "src/f32-spmm/gen/f32-spmm-4x2-minmax-aarch64-neonfma.c", |
| "src/f32-spmm/gen/f32-spmm-4x4-minmax-aarch64-neonfma.c", |
| "src/f32-spmm/gen/f32-spmm-8x2-minmax-aarch64-neonfma.c", |
| "src/f32-spmm/gen/f32-spmm-8x4-minmax-aarch64-neonfma.c", |
| "src/f32-spmm/gen/f32-spmm-12x2-minmax-aarch64-neonfma.c", |
| "src/f32-spmm/gen/f32-spmm-12x4-minmax-aarch64-neonfma.c", |
| "src/f32-spmm/gen/f32-spmm-16x2-minmax-aarch64-neonfma.c", |
| "src/f32-spmm/gen/f32-spmm-16x4-minmax-aarch64-neonfma.c", |
| "src/f32-spmm/gen/f32-spmm-32x2-minmax-aarch64-neonfma.c", |
| "src/f32-spmm/gen/f32-spmm-32x4-minmax-aarch64-neonfma.c", |
| "src/f32-vsigmoid/gen/f32-vsigmoid-aarch64-neonfma-rr1-lut64-p2-div-u4.c", |
| "src/f32-vsigmoid/gen/f32-vsigmoid-aarch64-neonfma-rr1-lut64-p2-div-u8.c", |
| "src/f32-vsigmoid/gen/f32-vsigmoid-aarch64-neonfma-rr1-lut64-p2-div-u12.c", |
| "src/f32-vsigmoid/gen/f32-vsigmoid-aarch64-neonfma-rr1-lut64-p2-div-u16.c", |
| "src/f32-vsigmoid/gen/f32-vsigmoid-aarch64-neonfma-rr1-lut64-p2-div-u20.c", |
| "src/f32-vsigmoid/gen/f32-vsigmoid-aarch64-neonfma-rr1-lut64-p2-div-u24.c", |
| "src/f32-vsigmoid/gen/f32-vsigmoid-aarch64-neonfma-rr1-lut2048-p1-div-u4.c", |
| "src/f32-vsigmoid/gen/f32-vsigmoid-aarch64-neonfma-rr1-lut2048-p1-div-u8.c", |
| "src/f32-vsigmoid/gen/f32-vsigmoid-aarch64-neonfma-rr1-lut2048-p1-div-u12.c", |
| "src/f32-vsigmoid/gen/f32-vsigmoid-aarch64-neonfma-rr1-lut2048-p1-div-u16.c", |
| "src/f32-vsigmoid/gen/f32-vsigmoid-aarch64-neonfma-rr1-lut2048-p1-div-u20.c", |
| "src/f32-vsigmoid/gen/f32-vsigmoid-aarch64-neonfma-rr1-lut2048-p1-div-u24.c", |
| "src/f32-vsigmoid/gen/f32-vsigmoid-aarch64-neonfma-rr1-p5-div-u4.c", |
| "src/f32-vsigmoid/gen/f32-vsigmoid-aarch64-neonfma-rr1-p5-div-u8.c", |
| "src/f32-vsigmoid/gen/f32-vsigmoid-aarch64-neonfma-rr1-p5-div-u12.c", |
| "src/f32-vsigmoid/gen/f32-vsigmoid-aarch64-neonfma-rr1-p5-div-u16.c", |
| "src/f32-vsigmoid/gen/f32-vsigmoid-aarch64-neonfma-rr1-p5-div-u20.c", |
| "src/f32-vsigmoid/gen/f32-vsigmoid-aarch64-neonfma-rr1-p5-div-u24.c", |
| "src/f32-vtanh/gen/f32-vtanh-aarch64-neonfma-expm1minus-rr1-lut8-p4h3ts-div-u4.c", |
| "src/f32-vtanh/gen/f32-vtanh-aarch64-neonfma-expm1minus-rr1-lut8-p4h3ts-div-u8.c", |
| "src/f32-vtanh/gen/f32-vtanh-aarch64-neonfma-expm1minus-rr1-lut8-p4h3ts-div-u12.c", |
| "src/f32-vtanh/gen/f32-vtanh-aarch64-neonfma-expm1minus-rr1-lut8-p4h3ts-div-u16.c", |
| "src/f32-vtanh/gen/f32-vtanh-aarch64-neonfma-expm1minus-rr1-p6h5ts-div-u4.c", |
| "src/f32-vtanh/gen/f32-vtanh-aarch64-neonfma-expm1minus-rr1-p6h5ts-div-u8.c", |
| "src/f32-vtanh/gen/f32-vtanh-aarch64-neonfma-expm1minus-rr1-p6h5ts-div-u12.c", |
| "src/f32-vtanh/gen/f32-vtanh-aarch64-neonfma-expm1minus-rr1-p6h5ts-div-u16.c", |
| "src/math/f32-sigmoid-aarch64-neonfma-rr1-lut64-p2-div.c", |
| "src/math/f32-sigmoid-aarch64-neonfma-rr1-lut2048-p1-div.c", |
| "src/math/f32-sigmoid-aarch64-neonfma-rr1-p5-div.c", |
| "src/math/f32-sigmoid-aarch64-neonfma-rr2-lut64-p2-div.c", |
| "src/math/f32-sigmoid-aarch64-neonfma-rr2-lut2048-p1-div.c", |
| "src/math/f32-sigmoid-aarch64-neonfma-rr2-p5-div.c", |
| "src/math/gen/f32-tanh-aarch64-neonfma-expm1minus-rr1-lut8-p4h3ps-div.c", |
| "src/math/gen/f32-tanh-aarch64-neonfma-expm1minus-rr1-p6h5ts-div.c", |
| ] |
| |
| ALL_NEONFP16_MICROKERNEL_SRCS = [ |
| "src/f16-f32-vcvt/gen/f16-f32-vcvt-neonfp16-u8.c", |
| "src/f16-f32-vcvt/gen/f16-f32-vcvt-neonfp16-u16.c", |
| "src/f16-f32acc-rsum/gen/f16-f32acc-rsum-neonfp16-u4.c", |
| "src/f16-f32acc-rsum/gen/f16-f32acc-rsum-neonfp16-u8.c", |
| "src/f16-f32acc-rsum/gen/f16-f32acc-rsum-neonfp16-u16-acc2.c", |
| "src/f16-f32acc-rsum/gen/f16-f32acc-rsum-neonfp16-u24-acc3.c", |
| "src/f16-f32acc-rsum/gen/f16-f32acc-rsum-neonfp16-u32-acc2.c", |
| "src/f16-f32acc-rsum/gen/f16-f32acc-rsum-neonfp16-u32-acc4.c", |
| "src/f32-f16-vcvt/gen/f32-f16-vcvt-neonfp16-u8.c", |
| "src/f32-f16-vcvt/gen/f32-f16-vcvt-neonfp16-u16.c", |
| "src/math/f16-f32-cvt-neonfp16.c", |
| "src/math/f32-f16-cvt-neonfp16.c", |
| ] |
| |
| ALL_NEONFP16ARITH_MICROKERNEL_SRCS = [ |
| "src/f16-avgpool/f16-avgpool-9p8x-minmax-neonfp16arith-c8.c", |
| "src/f16-avgpool/f16-avgpool-9x-minmax-neonfp16arith-c8.c", |
| "src/f16-conv-hwc2chw/f16-conv-hwc2chw-3x3s2p1c3x4-neonfp16arith-2x2.c", |
| "src/f16-dwconv2d-chw/gen/f16-dwconv2d-chw-3x3p1-minmax-neonfp16arith-1x8-acc2.c", |
| "src/f16-dwconv2d-chw/gen/f16-dwconv2d-chw-3x3p1-minmax-neonfp16arith-1x8-acc3.c", |
| "src/f16-dwconv2d-chw/gen/f16-dwconv2d-chw-3x3p1-minmax-neonfp16arith-1x8-acc4.c", |
| "src/f16-dwconv2d-chw/gen/f16-dwconv2d-chw-3x3p1-minmax-neonfp16arith-1x8.c", |
| "src/f16-dwconv2d-chw/gen/f16-dwconv2d-chw-3x3p1-minmax-neonfp16arith-2x8-acc2.c", |
| "src/f16-dwconv2d-chw/gen/f16-dwconv2d-chw-3x3p1-minmax-neonfp16arith-2x8.c", |
| "src/f16-dwconv2d-chw/gen/f16-dwconv2d-chw-3x3p1-minmax-neonfp16arith-3x8.c", |
| "src/f16-dwconv2d-chw/gen/f16-dwconv2d-chw-3x3p1-minmax-neonfp16arith-4x8.c", |
| "src/f16-dwconv2d-chw/gen/f16-dwconv2d-chw-3x3p1-minmax-neonfp16arith-5x8.c", |
| "src/f16-dwconv2d-chw/gen/f16-dwconv2d-chw-3x3p1-minmax-neonfp16arith-6x8.c", |
| "src/f16-dwconv2d-chw/gen/f16-dwconv2d-chw-3x3s2p1-minmax-neonfp16arith-1x8-acc2.c", |
| "src/f16-dwconv2d-chw/gen/f16-dwconv2d-chw-3x3s2p1-minmax-neonfp16arith-1x8-acc3.c", |
| "src/f16-dwconv2d-chw/gen/f16-dwconv2d-chw-3x3s2p1-minmax-neonfp16arith-1x8-acc4.c", |
| "src/f16-dwconv2d-chw/gen/f16-dwconv2d-chw-3x3s2p1-minmax-neonfp16arith-1x8.c", |
| "src/f16-dwconv2d-chw/gen/f16-dwconv2d-chw-3x3s2p1-minmax-neonfp16arith-2x8-acc2.c", |
| "src/f16-dwconv2d-chw/gen/f16-dwconv2d-chw-3x3s2p1-minmax-neonfp16arith-2x8.c", |
| "src/f16-dwconv2d-chw/gen/f16-dwconv2d-chw-3x3s2p1-minmax-neonfp16arith-3x8.c", |
| "src/f16-dwconv2d-chw/gen/f16-dwconv2d-chw-3x3s2p1-minmax-neonfp16arith-4x8.c", |
| "src/f16-dwconv2d-chw/gen/f16-dwconv2d-chw-5x5p2-minmax-neonfp16arith-1x8-acc2.c", |
| "src/f16-dwconv2d-chw/gen/f16-dwconv2d-chw-5x5p2-minmax-neonfp16arith-1x8-acc3.c", |
| "src/f16-dwconv2d-chw/gen/f16-dwconv2d-chw-5x5p2-minmax-neonfp16arith-1x8-acc4.c", |
| "src/f16-dwconv2d-chw/gen/f16-dwconv2d-chw-5x5p2-minmax-neonfp16arith-1x8-acc5.c", |
| "src/f16-dwconv2d-chw/gen/f16-dwconv2d-chw-5x5p2-minmax-neonfp16arith-1x8.c", |
| "src/f16-dwconv2d-chw/gen/f16-dwconv2d-chw-5x5p2-minmax-neonfp16arith-2x8-acc2.c", |
| "src/f16-dwconv2d-chw/gen/f16-dwconv2d-chw-5x5p2-minmax-neonfp16arith-2x8-acc3.c", |
| "src/f16-dwconv2d-chw/gen/f16-dwconv2d-chw-5x5p2-minmax-neonfp16arith-2x8.c", |
| "src/f16-dwconv2d-chw/gen/f16-dwconv2d-chw-5x5p2-minmax-neonfp16arith-3x8-acc2.c", |
| "src/f16-dwconv2d-chw/gen/f16-dwconv2d-chw-5x5p2-minmax-neonfp16arith-3x8.c", |
| "src/f16-dwconv2d-chw/gen/f16-dwconv2d-chw-5x5p2-minmax-neonfp16arith-4x8-acc2.c", |
| "src/f16-dwconv2d-chw/gen/f16-dwconv2d-chw-5x5p2-minmax-neonfp16arith-4x8.c", |
| "src/f16-dwconv2d-chw/gen/f16-dwconv2d-chw-5x5p2-minmax-neonfp16arith-5x8.c", |
| "src/f16-dwconv2d-chw/gen/f16-dwconv2d-chw-5x5s2p2-minmax-neonfp16arith-1x8-acc2.c", |
| "src/f16-dwconv2d-chw/gen/f16-dwconv2d-chw-5x5s2p2-minmax-neonfp16arith-1x8-acc3.c", |
| "src/f16-dwconv2d-chw/gen/f16-dwconv2d-chw-5x5s2p2-minmax-neonfp16arith-1x8-acc4.c", |
| "src/f16-dwconv2d-chw/gen/f16-dwconv2d-chw-5x5s2p2-minmax-neonfp16arith-1x8-acc5.c", |
| "src/f16-dwconv2d-chw/gen/f16-dwconv2d-chw-5x5s2p2-minmax-neonfp16arith-1x8.c", |
| "src/f16-dwconv2d-chw/gen/f16-dwconv2d-chw-5x5s2p2-minmax-neonfp16arith-2x8-acc2.c", |
| "src/f16-dwconv2d-chw/gen/f16-dwconv2d-chw-5x5s2p2-minmax-neonfp16arith-2x8-acc3.c", |
| "src/f16-dwconv2d-chw/gen/f16-dwconv2d-chw-5x5s2p2-minmax-neonfp16arith-2x8.c", |
| "src/f16-dwconv2d-chw/gen/f16-dwconv2d-chw-5x5s2p2-minmax-neonfp16arith-3x8-acc2.c", |
| "src/f16-dwconv2d-chw/gen/f16-dwconv2d-chw-5x5s2p2-minmax-neonfp16arith-3x8.c", |
| "src/f16-dwconv/gen/f16-dwconv-3p8c-minmax-neonfp16arith-acc2.c", |
| "src/f16-dwconv/gen/f16-dwconv-3p8c-minmax-neonfp16arith.c", |
| "src/f16-dwconv/gen/f16-dwconv-3p16c-minmax-neonfp16arith-acc2.c", |
| "src/f16-dwconv/gen/f16-dwconv-3p16c-minmax-neonfp16arith.c", |
| "src/f16-dwconv/gen/f16-dwconv-3p32c-minmax-neonfp16arith-acc2.c", |
| "src/f16-dwconv/gen/f16-dwconv-3p32c-minmax-neonfp16arith.c", |
| "src/f16-dwconv/gen/f16-dwconv-4p8c-minmax-neonfp16arith-acc2.c", |
| "src/f16-dwconv/gen/f16-dwconv-4p8c-minmax-neonfp16arith.c", |
| "src/f16-dwconv/gen/f16-dwconv-4p16c-minmax-neonfp16arith-acc2.c", |
| "src/f16-dwconv/gen/f16-dwconv-4p16c-minmax-neonfp16arith.c", |
| "src/f16-dwconv/gen/f16-dwconv-4p32c-minmax-neonfp16arith-acc2.c", |
| "src/f16-dwconv/gen/f16-dwconv-4p32c-minmax-neonfp16arith.c", |
| "src/f16-dwconv/gen/f16-dwconv-5f5m5l8c8s4r-minmax-neonfp16arith-acc2.c", |
| "src/f16-dwconv/gen/f16-dwconv-5f5m5l8c8s4r-minmax-neonfp16arith.c", |
| "src/f16-dwconv/gen/f16-dwconv-5f5m5l16c8s4r-minmax-neonfp16arith-acc2.c", |
| "src/f16-dwconv/gen/f16-dwconv-5f5m5l16c8s4r-minmax-neonfp16arith.c", |
| "src/f16-dwconv/gen/f16-dwconv-5f5m5l32c8s4r-minmax-neonfp16arith-acc2.c", |
| "src/f16-dwconv/gen/f16-dwconv-5f5m5l32c8s4r-minmax-neonfp16arith.c", |
| "src/f16-dwconv/gen/f16-dwconv-6f6m7l8c8s4r-minmax-neonfp16arith-acc2.c", |
| "src/f16-dwconv/gen/f16-dwconv-6f6m7l8c8s4r-minmax-neonfp16arith.c", |
| "src/f16-dwconv/gen/f16-dwconv-6f6m7l16c8s4r-minmax-neonfp16arith-acc2.c", |
| "src/f16-dwconv/gen/f16-dwconv-6f6m7l16c8s4r-minmax-neonfp16arith.c", |
| "src/f16-dwconv/gen/f16-dwconv-6f6m7l32c8s4r-minmax-neonfp16arith-acc2.c", |
| "src/f16-dwconv/gen/f16-dwconv-6f6m7l32c8s4r-minmax-neonfp16arith.c", |
| "src/f16-dwconv/gen/f16-dwconv-8f8m9l8c8s4r-minmax-neonfp16arith-acc2.c", |
| "src/f16-dwconv/gen/f16-dwconv-8f8m9l8c8s4r-minmax-neonfp16arith.c", |
| "src/f16-dwconv/gen/f16-dwconv-8f8m9l16c8s4r-minmax-neonfp16arith-acc2.c", |
| "src/f16-dwconv/gen/f16-dwconv-8f8m9l16c8s4r-minmax-neonfp16arith.c", |
| "src/f16-dwconv/gen/f16-dwconv-8f8m9l32c8s4r-minmax-neonfp16arith-acc2.c", |
| "src/f16-dwconv/gen/f16-dwconv-8f8m9l32c8s4r-minmax-neonfp16arith.c", |
| "src/f16-dwconv/gen/f16-dwconv-9p8c-minmax-neonfp16arith-acc2.c", |
| "src/f16-dwconv/gen/f16-dwconv-9p8c-minmax-neonfp16arith.c", |
| "src/f16-dwconv/gen/f16-dwconv-9p16c-minmax-neonfp16arith-acc2.c", |
| "src/f16-dwconv/gen/f16-dwconv-9p16c-minmax-neonfp16arith.c", |
| "src/f16-dwconv/gen/f16-dwconv-9p32c-minmax-neonfp16arith-acc2.c", |
| "src/f16-dwconv/gen/f16-dwconv-9p32c-minmax-neonfp16arith.c", |
| "src/f16-dwconv/gen/f16-dwconv-25p8c-minmax-neonfp16arith-acc2.c", |
| "src/f16-dwconv/gen/f16-dwconv-25p8c-minmax-neonfp16arith.c", |
| "src/f16-dwconv/gen/f16-dwconv-25p16c-minmax-neonfp16arith-acc2.c", |
| "src/f16-dwconv/gen/f16-dwconv-25p16c-minmax-neonfp16arith.c", |
| "src/f16-dwconv/gen/f16-dwconv-25p32c-minmax-neonfp16arith-acc2.c", |
| "src/f16-dwconv/gen/f16-dwconv-25p32c-minmax-neonfp16arith.c", |
| "src/f16-gavgpool-cw/f16-gavgpool-cw-neonfp16arith-x8.c", |
| "src/f16-gavgpool/gen/f16-gavgpool-7p7x-minmax-neonfp16arith-c8.c", |
| "src/f16-gavgpool/gen/f16-gavgpool-7p7x-minmax-neonfp16arith-c16.c", |
| "src/f16-gavgpool/gen/f16-gavgpool-7p7x-minmax-neonfp16arith-c24.c", |
| "src/f16-gavgpool/gen/f16-gavgpool-7p7x-minmax-neonfp16arith-c32.c", |
| "src/f16-gavgpool/gen/f16-gavgpool-7x-minmax-neonfp16arith-c8.c", |
| "src/f16-gavgpool/gen/f16-gavgpool-7x-minmax-neonfp16arith-c16.c", |
| "src/f16-gavgpool/gen/f16-gavgpool-7x-minmax-neonfp16arith-c24.c", |
| "src/f16-gavgpool/gen/f16-gavgpool-7x-minmax-neonfp16arith-c32.c", |
| "src/f16-gemm/gen/f16-gemm-1x8-minmax-neonfp16arith-ld64.c", |
| "src/f16-gemm/gen/f16-gemm-1x16-minmax-neonfp16arith-ld64.c", |
| "src/f16-gemm/gen/f16-gemm-4x8-minmax-neonfp16arith-ld64.c", |
| "src/f16-gemm/gen/f16-gemm-4x16-minmax-neonfp16arith-ld64.c", |
| "src/f16-gemm/gen/f16-gemm-6x8-minmax-neonfp16arith-ld64.c", |
| "src/f16-gemm/gen/f16-gemm-6x16-minmax-neonfp16arith-ld64.c", |
| "src/f16-gemm/gen/f16-gemm-8x8-minmax-neonfp16arith-ld64.c", |
| "src/f16-gemm/gen/f16-gemm-8x16-minmax-neonfp16arith-ld64.c", |
| "src/f16-gemm/gen/f16-gemminc-1x8-minmax-neonfp16arith-ld64.c", |
| "src/f16-gemm/gen/f16-gemminc-1x16-minmax-neonfp16arith-ld64.c", |
| "src/f16-gemm/gen/f16-gemminc-4x8-minmax-neonfp16arith-ld64.c", |
| "src/f16-gemm/gen/f16-gemminc-4x16-minmax-neonfp16arith-ld64.c", |
| "src/f16-gemm/gen/f16-gemminc-6x8-minmax-neonfp16arith-ld64.c", |
| "src/f16-gemm/gen/f16-gemminc-6x16-minmax-neonfp16arith-ld64.c", |
| "src/f16-gemm/gen/f16-gemminc-8x8-minmax-neonfp16arith-ld64.c", |
| "src/f16-gemm/gen/f16-gemminc-8x16-minmax-neonfp16arith-ld64.c", |
| "src/f16-ibilinear-chw/gen/f16-ibilinear-chw-neonfp16arith-p4.c", |
| "src/f16-ibilinear-chw/gen/f16-ibilinear-chw-neonfp16arith-p8.c", |
| "src/f16-ibilinear-chw/gen/f16-ibilinear-chw-neonfp16arith-p16.c", |
| "src/f16-ibilinear/gen/f16-ibilinear-neonfp16arith-c8.c", |
| "src/f16-ibilinear/gen/f16-ibilinear-neonfp16arith-c16.c", |
| "src/f16-igemm/gen/f16-igemm-1x8-minmax-neonfp16arith-ld64.c", |
| "src/f16-igemm/gen/f16-igemm-1x16-minmax-neonfp16arith-ld64.c", |
| "src/f16-igemm/gen/f16-igemm-4x8-minmax-neonfp16arith-ld64.c", |
| "src/f16-igemm/gen/f16-igemm-4x16-minmax-neonfp16arith-ld64.c", |
| "src/f16-igemm/gen/f16-igemm-6x8-minmax-neonfp16arith-ld64.c", |
| "src/f16-igemm/gen/f16-igemm-6x16-minmax-neonfp16arith-ld64.c", |
| "src/f16-igemm/gen/f16-igemm-8x8-minmax-neonfp16arith-ld64.c", |
| "src/f16-igemm/gen/f16-igemm-8x16-minmax-neonfp16arith-ld64.c", |
| "src/f16-maxpool/f16-maxpool-9p8x-minmax-neonfp16arith-c8.c", |
| "src/f16-pavgpool/f16-pavgpool-9p8x-minmax-neonfp16arith-c8.c", |
| "src/f16-pavgpool/f16-pavgpool-9x-minmax-neonfp16arith-c8.c", |
| "src/f16-prelu/gen/f16-prelu-neonfp16arith-2x8.c", |
| "src/f16-prelu/gen/f16-prelu-neonfp16arith-2x16.c", |
| "src/f16-raddstoreexpminusmax/gen/f16-raddstoreexpminusmax-neonfp16arith-rr2-p2-u32-acc2.c", |
| "src/f16-raddstoreexpminusmax/gen/f16-raddstoreexpminusmax-neonfp16arith-rr2-p2-u32-acc4.c", |
| "src/f16-raddstoreexpminusmax/gen/f16-raddstoreexpminusmax-neonfp16arith-rr2-p2-u32.c", |
| "src/f16-raddstoreexpminusmax/gen/f16-raddstoreexpminusmax-neonfp16arith-rr2-p2-u40-acc2.c", |
| "src/f16-raddstoreexpminusmax/gen/f16-raddstoreexpminusmax-neonfp16arith-rr2-p2-u40-acc5.c", |
| "src/f16-raddstoreexpminusmax/gen/f16-raddstoreexpminusmax-neonfp16arith-rr2-p2-u40.c", |
| "src/f16-raddstoreexpminusmax/gen/f16-raddstoreexpminusmax-neonfp16arith-rr2-p2-u48-acc2.c", |
| "src/f16-raddstoreexpminusmax/gen/f16-raddstoreexpminusmax-neonfp16arith-rr2-p2-u48-acc3.c", |
| "src/f16-raddstoreexpminusmax/gen/f16-raddstoreexpminusmax-neonfp16arith-rr2-p2-u48.c", |
| "src/f16-raddstoreexpminusmax/gen/f16-raddstoreexpminusmax-neonfp16arith-rr2-p2-u64-acc2.c", |
| "src/f16-raddstoreexpminusmax/gen/f16-raddstoreexpminusmax-neonfp16arith-rr2-p2-u64-acc4.c", |
| "src/f16-raddstoreexpminusmax/gen/f16-raddstoreexpminusmax-neonfp16arith-rr2-p2-u64.c", |
| "src/f16-raddstoreexpminusmax/gen/f16-raddstoreexpminusmax-neonfp16arith-rr2-p2-u72-acc3.c", |
| "src/f16-raddstoreexpminusmax/gen/f16-raddstoreexpminusmax-neonfp16arith-rr2-p2-u72.c", |
| "src/f16-raddstoreexpminusmax/gen/f16-raddstoreexpminusmax-neonfp16arith-rr2-p2-u80-acc2.c", |
| "src/f16-raddstoreexpminusmax/gen/f16-raddstoreexpminusmax-neonfp16arith-rr2-p2-u80-acc5.c", |
| "src/f16-raddstoreexpminusmax/gen/f16-raddstoreexpminusmax-neonfp16arith-rr2-p2-u80.c", |
| "src/f16-raddstoreexpminusmax/gen/f16-raddstoreexpminusmax-neonfp16arith-rr2-p2-u96-acc2.c", |
| "src/f16-raddstoreexpminusmax/gen/f16-raddstoreexpminusmax-neonfp16arith-rr2-p2-u96-acc3.c", |
| "src/f16-raddstoreexpminusmax/gen/f16-raddstoreexpminusmax-neonfp16arith-rr2-p2-u96-acc6.c", |
| "src/f16-raddstoreexpminusmax/gen/f16-raddstoreexpminusmax-neonfp16arith-rr2-p2-u96.c", |
| "src/f16-rmax/f16-rmax-neonfp16arith.c", |
| "src/f16-rsum/gen/f16-rsum-neonfp16arith-u8.c", |
| "src/f16-rsum/gen/f16-rsum-neonfp16arith-u16-acc2.c", |
| "src/f16-rsum/gen/f16-rsum-neonfp16arith-u24-acc3.c", |
| "src/f16-rsum/gen/f16-rsum-neonfp16arith-u32-acc2.c", |
| "src/f16-rsum/gen/f16-rsum-neonfp16arith-u32-acc4.c", |
| "src/f16-spmm/gen/f16-spmm-8x1-minmax-neonfp16arith-pipelined.c", |
| "src/f16-spmm/gen/f16-spmm-8x1-minmax-neonfp16arith-x2.c", |
| "src/f16-spmm/gen/f16-spmm-8x1-minmax-neonfp16arith.c", |
| "src/f16-spmm/gen/f16-spmm-16x1-minmax-neonfp16arith-pipelined.c", |
| "src/f16-spmm/gen/f16-spmm-16x1-minmax-neonfp16arith-x2.c", |
| "src/f16-spmm/gen/f16-spmm-16x1-minmax-neonfp16arith.c", |
| "src/f16-spmm/gen/f16-spmm-24x1-minmax-neonfp16arith-pipelined.c", |
| "src/f16-spmm/gen/f16-spmm-24x1-minmax-neonfp16arith-x2.c", |
| "src/f16-spmm/gen/f16-spmm-24x1-minmax-neonfp16arith.c", |
| "src/f16-spmm/gen/f16-spmm-32x1-minmax-neonfp16arith-pipelined.c", |
| "src/f16-spmm/gen/f16-spmm-32x1-minmax-neonfp16arith-x2.c", |
| "src/f16-spmm/gen/f16-spmm-32x1-minmax-neonfp16arith.c", |
| "src/f16-vbinary/gen/f16-vadd-minmax-neonfp16arith-u8.c", |
| "src/f16-vbinary/gen/f16-vadd-minmax-neonfp16arith-u16.c", |
| "src/f16-vbinary/gen/f16-vaddc-minmax-neonfp16arith-u8.c", |
| "src/f16-vbinary/gen/f16-vaddc-minmax-neonfp16arith-u16.c", |
| "src/f16-vbinary/gen/f16-vmax-neonfp16arith-u8.c", |
| "src/f16-vbinary/gen/f16-vmax-neonfp16arith-u16.c", |
| "src/f16-vbinary/gen/f16-vmaxc-neonfp16arith-u8.c", |
| "src/f16-vbinary/gen/f16-vmaxc-neonfp16arith-u16.c", |
| "src/f16-vbinary/gen/f16-vmin-neonfp16arith-u8.c", |
| "src/f16-vbinary/gen/f16-vmin-neonfp16arith-u16.c", |
| "src/f16-vbinary/gen/f16-vminc-neonfp16arith-u8.c", |
| "src/f16-vbinary/gen/f16-vminc-neonfp16arith-u16.c", |
| "src/f16-vbinary/gen/f16-vmul-minmax-neonfp16arith-u8.c", |
| "src/f16-vbinary/gen/f16-vmul-minmax-neonfp16arith-u16.c", |
| "src/f16-vbinary/gen/f16-vmulc-minmax-neonfp16arith-u8.c", |
| "src/f16-vbinary/gen/f16-vmulc-minmax-neonfp16arith-u16.c", |
| "src/f16-vbinary/gen/f16-vrsubc-minmax-neonfp16arith-u8.c", |
| "src/f16-vbinary/gen/f16-vrsubc-minmax-neonfp16arith-u16.c", |
| "src/f16-vbinary/gen/f16-vsqrdiff-neonfp16arith-u8.c", |
| "src/f16-vbinary/gen/f16-vsqrdiff-neonfp16arith-u16.c", |
| "src/f16-vbinary/gen/f16-vsqrdiffc-neonfp16arith-u8.c", |
| "src/f16-vbinary/gen/f16-vsqrdiffc-neonfp16arith-u16.c", |
| "src/f16-vbinary/gen/f16-vsub-minmax-neonfp16arith-u8.c", |
| "src/f16-vbinary/gen/f16-vsub-minmax-neonfp16arith-u16.c", |
| "src/f16-vbinary/gen/f16-vsubc-minmax-neonfp16arith-u8.c", |
| "src/f16-vbinary/gen/f16-vsubc-minmax-neonfp16arith-u16.c", |
| "src/f16-vclamp/gen/f16-vclamp-neonfp16arith-u8.c", |
| "src/f16-vclamp/gen/f16-vclamp-neonfp16arith-u16.c", |
| "src/f16-velu/gen/f16-velu-neonfp16arith-rr1-p3-u8.c", |
| "src/f16-velu/gen/f16-velu-neonfp16arith-rr1-p3-u16.c", |
| "src/f16-vhswish/gen/f16-vhswish-neonfp16arith-u8.c", |
| "src/f16-vhswish/gen/f16-vhswish-neonfp16arith-u16.c", |
| "src/f16-vlrelu/gen/f16-vlrelu-neonfp16arith-u8.c", |
| "src/f16-vlrelu/gen/f16-vlrelu-neonfp16arith-u16.c", |
| "src/f16-vmulcaddc/gen/f16-vmulcaddc-c8-minmax-neonfp16arith-2x.c", |
| "src/f16-vmulcaddc/gen/f16-vmulcaddc-c16-minmax-neonfp16arith-2x.c", |
| "src/f16-vrnd/gen/f16-vrndd-neonfp16arith-u8.c", |
| "src/f16-vrnd/gen/f16-vrndd-neonfp16arith-u16.c", |
| "src/f16-vrnd/gen/f16-vrndne-neonfp16arith-u8.c", |
| "src/f16-vrnd/gen/f16-vrndne-neonfp16arith-u16.c", |
| "src/f16-vrnd/gen/f16-vrndu-neonfp16arith-u8.c", |
| "src/f16-vrnd/gen/f16-vrndu-neonfp16arith-u16.c", |
| "src/f16-vrnd/gen/f16-vrndz-neonfp16arith-u8.c", |
| "src/f16-vrnd/gen/f16-vrndz-neonfp16arith-u16.c", |
| "src/f16-vsigmoid/gen/f16-vsigmoid-neonfp16arith-rr2-p2-nr1fma-u8.c", |
| "src/f16-vsigmoid/gen/f16-vsigmoid-neonfp16arith-rr2-p2-nr1fma-u16.c", |
| "src/f16-vsigmoid/gen/f16-vsigmoid-neonfp16arith-rr2-p2-nr1fma-u24.c", |
| "src/f16-vsigmoid/gen/f16-vsigmoid-neonfp16arith-rr2-p2-nr1fma-u32.c", |
| "src/f16-vsigmoid/gen/f16-vsigmoid-neonfp16arith-rr2-p2-nr1fma-u40.c", |
| "src/f16-vsigmoid/gen/f16-vsigmoid-neonfp16arith-rr2-p2-nr1fma-u48.c", |
| "src/f16-vsigmoid/gen/f16-vsigmoid-neonfp16arith-rr2-p2-nr1fma-u56.c", |
| "src/f16-vsigmoid/gen/f16-vsigmoid-neonfp16arith-rr2-p2-nr1fma-u64.c", |
| "src/f16-vsigmoid/gen/f16-vsigmoid-neonfp16arith-rr2-p2-nr1recps-u8.c", |
| "src/f16-vsigmoid/gen/f16-vsigmoid-neonfp16arith-rr2-p2-nr1recps-u16.c", |
| "src/f16-vsigmoid/gen/f16-vsigmoid-neonfp16arith-rr2-p2-nr1recps-u24.c", |
| "src/f16-vsigmoid/gen/f16-vsigmoid-neonfp16arith-rr2-p2-nr1recps-u32.c", |
| "src/f16-vsigmoid/gen/f16-vsigmoid-neonfp16arith-rr2-p2-nr1recps-u40.c", |
| "src/f16-vsigmoid/gen/f16-vsigmoid-neonfp16arith-rr2-p2-nr1recps-u48.c", |
| "src/f16-vsigmoid/gen/f16-vsigmoid-neonfp16arith-rr2-p2-nr1recps-u56.c", |
| "src/f16-vsigmoid/gen/f16-vsigmoid-neonfp16arith-rr2-p2-nr1recps-u64.c", |
| "src/f16-vsqrt/gen/f16-vsqrt-neonfp16arith-nr1fma1adj-u8.c", |
| "src/f16-vsqrt/gen/f16-vsqrt-neonfp16arith-nr1fma1adj-u16.c", |
| "src/f16-vsqrt/gen/f16-vsqrt-neonfp16arith-nr1fma1adj-u24.c", |
| "src/f16-vsqrt/gen/f16-vsqrt-neonfp16arith-nr1fma1adj-u32.c", |
| "src/f16-vtanh/gen/f16-vtanh-neonfp16arith-expm1minus-rr1-p3h2ts-nr1fma-u8.c", |
| "src/f16-vtanh/gen/f16-vtanh-neonfp16arith-expm1minus-rr1-p3h2ts-nr1fma-u16.c", |
| "src/f16-vtanh/gen/f16-vtanh-neonfp16arith-expm1minus-rr1-p3h2ts-nr1fma-u24.c", |
| "src/f16-vtanh/gen/f16-vtanh-neonfp16arith-expm1minus-rr1-p3h2ts-nr1fma-u32.c", |
| "src/f16-vtanh/gen/f16-vtanh-neonfp16arith-expm1minus-rr1-p3h2ts-nr1fma-u40.c", |
| "src/f16-vtanh/gen/f16-vtanh-neonfp16arith-expm1minus-rr1-p3h2ts-nr1fma-u48.c", |
| "src/f16-vtanh/gen/f16-vtanh-neonfp16arith-expm1minus-rr1-p3h2ts-nr1fma-u56.c", |
| "src/f16-vtanh/gen/f16-vtanh-neonfp16arith-expm1minus-rr1-p3h2ts-nr1fma-u64.c", |
| "src/f16-vtanh/gen/f16-vtanh-neonfp16arith-expm1minus-rr1-p3h2ts-nr1fma-u72.c", |
| "src/f16-vtanh/gen/f16-vtanh-neonfp16arith-expm1minus-rr1-p3h2ts-nr1fma-u80.c", |
| "src/f16-vtanh/gen/f16-vtanh-neonfp16arith-expm1minus-rr1-p3h2ts-nr1recps-u8.c", |
| "src/f16-vtanh/gen/f16-vtanh-neonfp16arith-expm1minus-rr1-p3h2ts-nr1recps-u16.c", |
| "src/f16-vtanh/gen/f16-vtanh-neonfp16arith-expm1minus-rr1-p3h2ts-nr1recps-u24.c", |
| "src/f16-vtanh/gen/f16-vtanh-neonfp16arith-expm1minus-rr1-p3h2ts-nr1recps-u32.c", |
| "src/f16-vtanh/gen/f16-vtanh-neonfp16arith-expm1minus-rr1-p3h2ts-nr1recps-u40.c", |
| "src/f16-vtanh/gen/f16-vtanh-neonfp16arith-expm1minus-rr1-p3h2ts-nr1recps-u48.c", |
| "src/f16-vtanh/gen/f16-vtanh-neonfp16arith-expm1minus-rr1-p3h2ts-nr1recps-u56.c", |
| "src/f16-vtanh/gen/f16-vtanh-neonfp16arith-expm1minus-rr1-p3h2ts-nr1recps-u64.c", |
| "src/f16-vtanh/gen/f16-vtanh-neonfp16arith-expm1minus-rr1-p3h2ts-nr1recps-u72.c", |
| "src/f16-vtanh/gen/f16-vtanh-neonfp16arith-expm1minus-rr1-p3h2ts-nr1recps-u80.c", |
| "src/f16-vtanh/gen/f16-vtanh-neonfp16arith-expm1minus-rr1-p3h2ts-recpeadj-u8.c", |
| "src/f16-vtanh/gen/f16-vtanh-neonfp16arith-expm1minus-rr1-p3h2ts-recpeadj-u16.c", |
| "src/f16-vtanh/gen/f16-vtanh-neonfp16arith-expm1minus-rr1-p3h2ts-recpeadj-u24.c", |
| "src/f16-vtanh/gen/f16-vtanh-neonfp16arith-expm1minus-rr1-p3h2ts-recpeadj-u32.c", |
| "src/f16-vtanh/gen/f16-vtanh-neonfp16arith-expm1minus-rr1-p3h2ts-recpeadj-u40.c", |
| "src/f16-vtanh/gen/f16-vtanh-neonfp16arith-expm1minus-rr1-p3h2ts-recpeadj-u48.c", |
| "src/f16-vtanh/gen/f16-vtanh-neonfp16arith-expm1minus-rr1-p3h2ts-recpeadj-u56.c", |
| "src/f16-vtanh/gen/f16-vtanh-neonfp16arith-expm1minus-rr1-p3h2ts-recpeadj-u64.c", |
| "src/f16-vtanh/gen/f16-vtanh-neonfp16arith-expm1minus-rr1-p3h2ts-recpeadj-u72.c", |
| "src/f16-vtanh/gen/f16-vtanh-neonfp16arith-expm1minus-rr1-p3h2ts-recpeadj-u80.c", |
| "src/f16-vunary/gen/f16-vabs-neonfp16arith-u8.c", |
| "src/f16-vunary/gen/f16-vabs-neonfp16arith-u16.c", |
| "src/f16-vunary/gen/f16-vneg-neonfp16arith-u8.c", |
| "src/f16-vunary/gen/f16-vneg-neonfp16arith-u16.c", |
| "src/f16-vunary/gen/f16-vsqr-neonfp16arith-u8.c", |
| "src/f16-vunary/gen/f16-vsqr-neonfp16arith-u16.c", |
| "src/math/f16-exp-neonfp16arith-rr2-p3.c", |
| "src/math/f16-expm1minus-neonfp16arith-rr1-p3.c", |
| "src/math/f16-expm1minus-neonfp16arith-rr2-p3.c", |
| "src/math/f16-expminus-neonfp16arith-rr1-p2.c", |
| "src/math/f16-expminus-neonfp16arith-rr1-p3.c", |
| "src/math/f16-expminus-neonfp16arith-rr2-p2.c", |
| "src/math/f16-expminus-neonfp16arith-rr2-p3.c", |
| "src/math/f16-sigmoid-neonfp16arith-rr2-p2-nr1fma.c", |
| "src/math/f16-sigmoid-neonfp16arith-rr2-p2-nr1recps.c", |
| "src/math/f16-sigmoid-neonfp16arith-rr2-p2-recpe.c", |
| "src/math/f16-sigmoid-neonfp16arith-rr2-p3-nr1fma.c", |
| "src/math/f16-sigmoid-neonfp16arith-rr2-p3-nr1recps.c", |
| "src/math/f16-sigmoid-neonfp16arith-rr2-p3-recpe.c", |
| "src/math/f16-sqrt-neonfp16arith-nr1fma1adj.c", |
| "src/math/f16-sqrt-neonfp16arith-nr1fma.c", |
| "src/math/f16-sqrt-neonfp16arith-nr1rsqrts.c", |
| "src/math/gen/f16-tanh-neonfp16arith-expm1minus-rr1-p3h1ts-nr1fma.c", |
| "src/math/gen/f16-tanh-neonfp16arith-expm1minus-rr1-p3h1ts-nr1fmaadj.c", |
| "src/math/gen/f16-tanh-neonfp16arith-expm1minus-rr1-p3h1ts-nr1recps.c", |
| "src/math/gen/f16-tanh-neonfp16arith-expm1minus-rr1-p3h1ts-nr1recpsadj.c", |
| "src/math/gen/f16-tanh-neonfp16arith-expm1minus-rr1-p3h1ts-recpe.c", |
| "src/math/gen/f16-tanh-neonfp16arith-expm1minus-rr1-p3h1ts-recpeadj.c", |
| "src/math/gen/f16-tanh-neonfp16arith-expm1minus-rr1-p3h2ts-nr1fma.c", |
| "src/math/gen/f16-tanh-neonfp16arith-expm1minus-rr1-p3h2ts-nr1fmaadj.c", |
| "src/math/gen/f16-tanh-neonfp16arith-expm1minus-rr1-p3h2ts-nr1recps.c", |
| "src/math/gen/f16-tanh-neonfp16arith-expm1minus-rr1-p3h2ts-nr1recpsadj.c", |
| "src/math/gen/f16-tanh-neonfp16arith-expm1minus-rr1-p3h2ts-recpe.c", |
| "src/math/gen/f16-tanh-neonfp16arith-expm1minus-rr1-p3h2ts-recpeadj.c", |
| ] |
| |
| ALL_NEONFP16ARITH_AARCH64_MICROKERNEL_SRCS = [ |
| "src/f16-vbinary/gen/f16-vdiv-minmax-aarch64-neonfp16arith-u8.c", |
| "src/f16-vbinary/gen/f16-vdiv-minmax-aarch64-neonfp16arith-u16.c", |
| "src/f16-vbinary/gen/f16-vdivc-minmax-aarch64-neonfp16arith-u8.c", |
| "src/f16-vbinary/gen/f16-vdivc-minmax-aarch64-neonfp16arith-u16.c", |
| "src/f16-vbinary/gen/f16-vrdivc-minmax-aarch64-neonfp16arith-u8.c", |
| "src/f16-vbinary/gen/f16-vrdivc-minmax-aarch64-neonfp16arith-u16.c", |
| "src/f16-vsigmoid/gen/f16-vsigmoid-aarch64-neonfp16arith-rr2-p2-div-u8.c", |
| "src/f16-vsigmoid/gen/f16-vsigmoid-aarch64-neonfp16arith-rr2-p2-div-u16.c", |
| "src/f16-vsigmoid/gen/f16-vsigmoid-aarch64-neonfp16arith-rr2-p2-div-u24.c", |
| "src/f16-vsigmoid/gen/f16-vsigmoid-aarch64-neonfp16arith-rr2-p2-div-u32.c", |
| "src/f16-vsigmoid/gen/f16-vsigmoid-aarch64-neonfp16arith-rr2-p2-div-u40.c", |
| "src/f16-vsigmoid/gen/f16-vsigmoid-aarch64-neonfp16arith-rr2-p2-div-u48.c", |
| "src/f16-vsigmoid/gen/f16-vsigmoid-aarch64-neonfp16arith-rr2-p2-div-u56.c", |
| "src/f16-vsigmoid/gen/f16-vsigmoid-aarch64-neonfp16arith-rr2-p2-div-u64.c", |
| "src/f16-vsqrt/gen/f16-vsqrt-aarch64-neonfp16arith-sqrt-u8.c", |
| "src/f16-vsqrt/gen/f16-vsqrt-aarch64-neonfp16arith-sqrt-u16.c", |
| "src/f16-vtanh/gen/f16-vtanh-aarch64-neonfp16arith-expm1minus-rr1-p3h2ts-div-u8.c", |
| "src/f16-vtanh/gen/f16-vtanh-aarch64-neonfp16arith-expm1minus-rr1-p3h2ts-div-u16.c", |
| "src/f16-vtanh/gen/f16-vtanh-aarch64-neonfp16arith-expm1minus-rr1-p3h2ts-div-u24.c", |
| "src/f16-vtanh/gen/f16-vtanh-aarch64-neonfp16arith-expm1minus-rr1-p3h2ts-div-u32.c", |
| "src/f16-vtanh/gen/f16-vtanh-aarch64-neonfp16arith-expm1minus-rr1-p3h2ts-div-u40.c", |
| "src/f16-vtanh/gen/f16-vtanh-aarch64-neonfp16arith-expm1minus-rr1-p3h2ts-div-u48.c", |
| "src/f16-vtanh/gen/f16-vtanh-aarch64-neonfp16arith-expm1minus-rr1-p3h2ts-div-u56.c", |
| "src/f16-vtanh/gen/f16-vtanh-aarch64-neonfp16arith-expm1minus-rr1-p3h2ts-div-u64.c", |
| "src/f16-vtanh/gen/f16-vtanh-aarch64-neonfp16arith-expm1minus-rr1-p3h2ts-div-u72.c", |
| "src/f16-vtanh/gen/f16-vtanh-aarch64-neonfp16arith-expm1minus-rr1-p3h2ts-div-u80.c", |
| "src/math/f16-sigmoid-aarch64-neonfp16arith-rr1-p2-div.c", |
| "src/math/f16-sigmoid-aarch64-neonfp16arith-rr1-p3-div.c", |
| "src/math/f16-sigmoid-aarch64-neonfp16arith-rr2-p2-div.c", |
| "src/math/f16-sigmoid-aarch64-neonfp16arith-rr2-p3-div.c", |
| "src/math/f16-sqrt-aarch64-neonfp16arith-sqrt.c", |
| "src/math/gen/f16-tanh-aarch64-neonfp16arith-expm1minus-rr1-p3h1ts-div.c", |
| "src/math/gen/f16-tanh-aarch64-neonfp16arith-expm1minus-rr1-p3h2ts-div.c", |
| ] |
| |
| ALL_NEONI8MM_MICROKERNEL_SRCS = [ |
| "src/qd8-f32-qc8w-gemm/gen/qd8-f32-qc8w-gemm-1x8c8-minmax-neoni8mm.c", |
| "src/qd8-f32-qc8w-gemm/gen/qd8-f32-qc8w-gemm-1x16c8-minmax-neoni8mm.c", |
| "src/qd8-f32-qc8w-gemm/gen/qd8-f32-qc8w-gemm-2x8c8-minmax-neoni8mm.c", |
| "src/qd8-f32-qc8w-gemm/gen/qd8-f32-qc8w-gemm-2x16c8-minmax-neoni8mm.c", |
| "src/qd8-f32-qc8w-gemm/gen/qd8-f32-qc8w-gemm-4x8c8-minmax-neoni8mm.c", |
| "src/qd8-f32-qc8w-gemm/gen/qd8-f32-qc8w-gemm-4x16c8-minmax-neoni8mm.c", |
| "src/qd8-f32-qc8w-gemm/gen/qd8-f32-qc8w-gemm-6x8c8-minmax-neoni8mm.c", |
| "src/qd8-f32-qc8w-gemm/gen/qd8-f32-qc8w-gemm-6x16c8-minmax-neoni8mm.c", |
| "src/qd8-f32-qc8w-gemm/gen/qd8-f32-qc8w-gemm-8x8c8-minmax-neoni8mm.c", |
| "src/qd8-f32-qc8w-gemm/gen/qd8-f32-qc8w-gemm-8x16c8-minmax-neoni8mm.c", |
| "src/qs8-gemm/gen/qs8-gemm-1x8c8-minmax-fp32-neoni8mm.c", |
| "src/qs8-gemm/gen/qs8-gemm-1x8c8-minmax-rndnu-neoni8mm.c", |
| "src/qs8-gemm/gen/qs8-gemm-1x16c8-minmax-fp32-neoni8mm.c", |
| "src/qs8-gemm/gen/qs8-gemm-1x16c8-minmax-rndnu-neoni8mm.c", |
| "src/qs8-gemm/gen/qs8-gemm-2x8c8-minmax-fp32-neoni8mm.c", |
| "src/qs8-gemm/gen/qs8-gemm-2x8c8-minmax-rndnu-neoni8mm.c", |
| "src/qs8-gemm/gen/qs8-gemm-2x16c8-minmax-fp32-neoni8mm.c", |
| "src/qs8-gemm/gen/qs8-gemm-2x16c8-minmax-rndnu-neoni8mm.c", |
| "src/qs8-gemm/gen/qs8-gemm-4x8c8-minmax-fp32-neoni8mm.c", |
| "src/qs8-gemm/gen/qs8-gemm-4x8c8-minmax-rndnu-neoni8mm.c", |
| "src/qs8-gemm/gen/qs8-gemm-4x16c8-minmax-fp32-neoni8mm.c", |
| "src/qs8-gemm/gen/qs8-gemm-4x16c8-minmax-rndnu-neoni8mm.c", |
| "src/qs8-gemm/gen/qs8-gemm-6x8c8-minmax-fp32-neoni8mm.c", |
| "src/qs8-gemm/gen/qs8-gemm-6x8c8-minmax-rndnu-neoni8mm.c", |
| "src/qs8-gemm/gen/qs8-gemm-6x16c8-minmax-fp32-neoni8mm.c", |
| "src/qs8-gemm/gen/qs8-gemm-6x16c8-minmax-rndnu-neoni8mm.c", |
| "src/qs8-gemm/gen/qs8-gemm-8x8c8-minmax-fp32-neoni8mm.c", |
| "src/qs8-gemm/gen/qs8-gemm-8x8c8-minmax-rndnu-neoni8mm.c", |
| "src/qs8-gemm/gen/qs8-gemm-8x16c8-minmax-fp32-neoni8mm.c", |
| "src/qs8-gemm/gen/qs8-gemm-8x16c8-minmax-rndnu-neoni8mm.c", |
| "src/qs8-igemm/gen/qs8-igemm-1x8c8-minmax-fp32-neoni8mm.c", |
| "src/qs8-igemm/gen/qs8-igemm-1x8c8-minmax-rndnu-neoni8mm.c", |
| "src/qs8-igemm/gen/qs8-igemm-1x16c8-minmax-fp32-neoni8mm.c", |
| "src/qs8-igemm/gen/qs8-igemm-1x16c8-minmax-rndnu-neoni8mm.c", |
| "src/qs8-igemm/gen/qs8-igemm-2x8c8-minmax-fp32-neoni8mm.c", |
| "src/qs8-igemm/gen/qs8-igemm-2x8c8-minmax-rndnu-neoni8mm.c", |
| "src/qs8-igemm/gen/qs8-igemm-2x16c8-minmax-fp32-neoni8mm.c", |
| "src/qs8-igemm/gen/qs8-igemm-2x16c8-minmax-rndnu-neoni8mm.c", |
| "src/qs8-igemm/gen/qs8-igemm-4x8c8-minmax-fp32-neoni8mm.c", |
| "src/qs8-igemm/gen/qs8-igemm-4x8c8-minmax-rndnu-neoni8mm.c", |
| "src/qs8-igemm/gen/qs8-igemm-4x16c8-minmax-fp32-neoni8mm.c", |
| "src/qs8-igemm/gen/qs8-igemm-4x16c8-minmax-rndnu-neoni8mm.c", |
| "src/qs8-igemm/gen/qs8-igemm-6x8c8-minmax-fp32-neoni8mm.c", |
| "src/qs8-igemm/gen/qs8-igemm-6x8c8-minmax-rndnu-neoni8mm.c", |
| "src/qs8-igemm/gen/qs8-igemm-6x16c8-minmax-fp32-neoni8mm.c", |
| "src/qs8-igemm/gen/qs8-igemm-6x16c8-minmax-rndnu-neoni8mm.c", |
| "src/qs8-igemm/gen/qs8-igemm-8x8c8-minmax-fp32-neoni8mm.c", |
| "src/qs8-igemm/gen/qs8-igemm-8x8c8-minmax-rndnu-neoni8mm.c", |
| "src/qs8-igemm/gen/qs8-igemm-8x16c8-minmax-fp32-neoni8mm.c", |
| "src/qs8-igemm/gen/qs8-igemm-8x16c8-minmax-rndnu-neoni8mm.c", |
| "src/qs8-qc8w-gemm/gen/qs8-qc8w-gemm-1x8c8-minmax-fp32-neoni8mm.c", |
| "src/qs8-qc8w-gemm/gen/qs8-qc8w-gemm-1x16c8-minmax-fp32-neoni8mm.c", |
| "src/qs8-qc8w-gemm/gen/qs8-qc8w-gemm-2x8c8-minmax-fp32-neoni8mm.c", |
| "src/qs8-qc8w-gemm/gen/qs8-qc8w-gemm-2x16c8-minmax-fp32-neoni8mm.c", |
| "src/qs8-qc8w-gemm/gen/qs8-qc8w-gemm-4x8c8-minmax-fp32-neoni8mm.c", |
| "src/qs8-qc8w-gemm/gen/qs8-qc8w-gemm-4x16c8-minmax-fp32-neoni8mm.c", |
| "src/qs8-qc8w-gemm/gen/qs8-qc8w-gemm-6x8c8-minmax-fp32-neoni8mm.c", |
| "src/qs8-qc8w-gemm/gen/qs8-qc8w-gemm-6x16c8-minmax-fp32-neoni8mm.c", |
| "src/qs8-qc8w-gemm/gen/qs8-qc8w-gemm-8x8c8-minmax-fp32-neoni8mm.c", |
| "src/qs8-qc8w-gemm/gen/qs8-qc8w-gemm-8x16c8-minmax-fp32-neoni8mm.c", |
| "src/qs8-qc8w-igemm/gen/qs8-qc8w-igemm-1x8-minmax-fp32-neoni8mm.c", |
| "src/qs8-qc8w-igemm/gen/qs8-qc8w-igemm-1x16c8-minmax-fp32-neoni8mm.c", |
| "src/qs8-qc8w-igemm/gen/qs8-qc8w-igemm-2x8-minmax-fp32-neoni8mm.c", |
| "src/qs8-qc8w-igemm/gen/qs8-qc8w-igemm-2x16c8-minmax-fp32-neoni8mm.c", |
| "src/qs8-qc8w-igemm/gen/qs8-qc8w-igemm-4x8c8-minmax-fp32-neoni8mm.c", |
| "src/qs8-qc8w-igemm/gen/qs8-qc8w-igemm-4x16c8-minmax-fp32-neoni8mm.c", |
| "src/qs8-qc8w-igemm/gen/qs8-qc8w-igemm-6x8c8-minmax-fp32-neoni8mm.c", |
| "src/qs8-qc8w-igemm/gen/qs8-qc8w-igemm-6x16c8-minmax-fp32-neoni8mm.c", |
| "src/qs8-qc8w-igemm/gen/qs8-qc8w-igemm-8x8c8-minmax-fp32-neoni8mm.c", |
| "src/qs8-qc8w-igemm/gen/qs8-qc8w-igemm-8x16c8-minmax-fp32-neoni8mm.c", |
| "src/qu8-gemm/gen/qu8-gemm-1x8c8-minmax-fp32-neoni8mm.c", |
| "src/qu8-gemm/gen/qu8-gemm-1x8c8-minmax-rndnu-neoni8mm.c", |
| "src/qu8-gemm/gen/qu8-gemm-1x16c8-minmax-fp32-neoni8mm.c", |
| "src/qu8-gemm/gen/qu8-gemm-1x16c8-minmax-rndnu-neoni8mm.c", |
| "src/qu8-gemm/gen/qu8-gemm-2x8c8-minmax-fp32-neoni8mm.c", |
| "src/qu8-gemm/gen/qu8-gemm-2x8c8-minmax-rndnu-neoni8mm.c", |
| "src/qu8-gemm/gen/qu8-gemm-2x16c8-minmax-fp32-neoni8mm.c", |
| "src/qu8-gemm/gen/qu8-gemm-2x16c8-minmax-rndnu-neoni8mm.c", |
| "src/qu8-gemm/gen/qu8-gemm-4x8c8-minmax-fp32-neoni8mm.c", |
| "src/qu8-gemm/gen/qu8-gemm-4x8c8-minmax-rndnu-neoni8mm.c", |
| "src/qu8-gemm/gen/qu8-gemm-4x16c8-minmax-fp32-neoni8mm.c", |
| "src/qu8-gemm/gen/qu8-gemm-4x16c8-minmax-rndnu-neoni8mm.c", |
| "src/qu8-gemm/gen/qu8-gemm-6x8c8-minmax-fp32-neoni8mm.c", |
| "src/qu8-gemm/gen/qu8-gemm-6x8c8-minmax-rndnu-neoni8mm.c", |
| "src/qu8-gemm/gen/qu8-gemm-6x16c8-minmax-fp32-neoni8mm.c", |
| "src/qu8-gemm/gen/qu8-gemm-6x16c8-minmax-rndnu-neoni8mm.c", |
| "src/qu8-gemm/gen/qu8-gemm-8x8c8-minmax-fp32-neoni8mm.c", |
| "src/qu8-gemm/gen/qu8-gemm-8x8c8-minmax-rndnu-neoni8mm.c", |
| "src/qu8-gemm/gen/qu8-gemm-8x16c8-minmax-fp32-neoni8mm.c", |
| "src/qu8-gemm/gen/qu8-gemm-8x16c8-minmax-rndnu-neoni8mm.c", |
| "src/qu8-igemm/gen/qu8-igemm-1x8c8-minmax-fp32-neoni8mm.c", |
| "src/qu8-igemm/gen/qu8-igemm-1x8c8-minmax-rndnu-neoni8mm.c", |
| "src/qu8-igemm/gen/qu8-igemm-1x16c8-minmax-fp32-neoni8mm.c", |
| "src/qu8-igemm/gen/qu8-igemm-1x16c8-minmax-rndnu-neoni8mm.c", |
| "src/qu8-igemm/gen/qu8-igemm-2x8c8-minmax-fp32-neoni8mm.c", |
| "src/qu8-igemm/gen/qu8-igemm-2x8c8-minmax-rndnu-neoni8mm.c", |
| "src/qu8-igemm/gen/qu8-igemm-2x16c8-minmax-fp32-neoni8mm.c", |
| "src/qu8-igemm/gen/qu8-igemm-2x16c8-minmax-rndnu-neoni8mm.c", |
| "src/qu8-igemm/gen/qu8-igemm-4x8c8-minmax-fp32-neoni8mm.c", |
| "src/qu8-igemm/gen/qu8-igemm-4x8c8-minmax-rndnu-neoni8mm.c", |
| "src/qu8-igemm/gen/qu8-igemm-4x16c8-minmax-fp32-neoni8mm.c", |
| "src/qu8-igemm/gen/qu8-igemm-4x16c8-minmax-rndnu-neoni8mm.c", |
| "src/qu8-igemm/gen/qu8-igemm-6x8c8-minmax-fp32-neoni8mm.c", |
| "src/qu8-igemm/gen/qu8-igemm-6x8c8-minmax-rndnu-neoni8mm.c", |
| "src/qu8-igemm/gen/qu8-igemm-6x16c8-minmax-fp32-neoni8mm.c", |
| "src/qu8-igemm/gen/qu8-igemm-6x16c8-minmax-rndnu-neoni8mm.c", |
| "src/qu8-igemm/gen/qu8-igemm-8x8c8-minmax-fp32-neoni8mm.c", |
| "src/qu8-igemm/gen/qu8-igemm-8x8c8-minmax-rndnu-neoni8mm.c", |
| "src/qu8-igemm/gen/qu8-igemm-8x16c8-minmax-fp32-neoni8mm.c", |
| "src/qu8-igemm/gen/qu8-igemm-8x16c8-minmax-rndnu-neoni8mm.c", |
| ] |
| |
| ALL_NEONV8_MICROKERNEL_SRCS = [ |
| "src/f32-qs8-vcvt/gen/f32-qs8-vcvt-neonv8-u8.c", |
| "src/f32-qs8-vcvt/gen/f32-qs8-vcvt-neonv8-u16.c", |
| "src/f32-qs8-vcvt/gen/f32-qs8-vcvt-neonv8-u24.c", |
| "src/f32-qs8-vcvt/gen/f32-qs8-vcvt-neonv8-u32.c", |
| "src/f32-qu8-vcvt/gen/f32-qu8-vcvt-neonv8-u8.c", |
| "src/f32-qu8-vcvt/gen/f32-qu8-vcvt-neonv8-u16.c", |
| "src/f32-qu8-vcvt/gen/f32-qu8-vcvt-neonv8-u24.c", |
| "src/f32-qu8-vcvt/gen/f32-qu8-vcvt-neonv8-u32.c", |
| "src/f32-vrnd/gen/f32-vrndd-neonv8-u4.c", |
| "src/f32-vrnd/gen/f32-vrndd-neonv8-u8.c", |
| "src/f32-vrnd/gen/f32-vrndne-neonv8-u4.c", |
| "src/f32-vrnd/gen/f32-vrndne-neonv8-u8.c", |
| "src/f32-vrnd/gen/f32-vrndu-neonv8-u4.c", |
| "src/f32-vrnd/gen/f32-vrndu-neonv8-u8.c", |
| "src/f32-vrnd/gen/f32-vrndz-neonv8-u4.c", |
| "src/f32-vrnd/gen/f32-vrndz-neonv8-u8.c", |
| "src/math/f32-qs8-cvt-neonv8.c", |
| "src/math/f32-qu8-cvt-neonv8.c", |
| "src/math/f32-roundd-neonv8.c", |
| "src/math/f32-roundne-neonv8.c", |
| "src/math/f32-roundu-neonv8.c", |
| "src/math/f32-roundz-neonv8.c", |
| "src/qs8-dwconv/gen/qs8-dwconv-5f5m5l8c8s8r-minmax-fp32-neonv8-mul16.c", |
| "src/qs8-dwconv/gen/qs8-dwconv-5f5m5l16c8s8r-minmax-fp32-neonv8-mul16.c", |
| "src/qs8-dwconv/gen/qs8-dwconv-5f5m5l32c8s8r-minmax-fp32-neonv8-mul16.c", |
| "src/qs8-dwconv/gen/qs8-dwconv-6f6m7l8c8s8r-minmax-fp32-neonv8-mul16.c", |
| "src/qs8-dwconv/gen/qs8-dwconv-6f6m7l16c8s8r-minmax-fp32-neonv8-mul16.c", |
| "src/qs8-dwconv/gen/qs8-dwconv-6f6m7l32c8s8r-minmax-fp32-neonv8-mul16.c", |
| "src/qs8-dwconv/gen/qs8-dwconv-8f8m9l8c8s8r-minmax-fp32-neonv8-mul16.c", |
| "src/qs8-dwconv/gen/qs8-dwconv-8f8m9l16c8s8r-minmax-fp32-neonv8-mul16.c", |
| "src/qs8-dwconv/gen/qs8-dwconv-8f8m9l32c8s8r-minmax-fp32-neonv8-mul16.c", |
| "src/qs8-dwconv/gen/qs8-dwconv-9p8c-minmax-fp32-neonv8-mul16.c", |
| "src/qs8-dwconv/gen/qs8-dwconv-9p16c-minmax-fp32-neonv8-mul16.c", |
| "src/qs8-dwconv/gen/qs8-dwconv-9p32c-minmax-fp32-neonv8-mul16.c", |
| "src/qs8-dwconv/gen/qs8-dwconv-25p8c-minmax-fp32-neonv8-mul16.c", |
| "src/qs8-dwconv/gen/qs8-dwconv-25p16c-minmax-fp32-neonv8-mul16.c", |
| "src/qs8-dwconv/gen/qs8-dwconv-25p32c-minmax-fp32-neonv8-mul16.c", |
| "src/qs8-gavgpool/gen/qs8-gavgpool-7p7x-minmax-fp32-neonv8-c8.c", |
| "src/qs8-gavgpool/gen/qs8-gavgpool-7p7x-minmax-fp32-neonv8-c16.c", |
| "src/qs8-gavgpool/gen/qs8-gavgpool-7p7x-minmax-fp32-neonv8-c24.c", |
| "src/qs8-gavgpool/gen/qs8-gavgpool-7p7x-minmax-fp32-neonv8-c32.c", |
| "src/qs8-gavgpool/gen/qs8-gavgpool-7x-minmax-fp32-neonv8-c8.c", |
| "src/qs8-gavgpool/gen/qs8-gavgpool-7x-minmax-fp32-neonv8-c16.c", |
| "src/qs8-gavgpool/gen/qs8-gavgpool-7x-minmax-fp32-neonv8-c24.c", |
| "src/qs8-gavgpool/gen/qs8-gavgpool-7x-minmax-fp32-neonv8-c32.c", |
| "src/qs8-gemm/gen/qs8-gemm-1x8c2-minmax-fp32-neonv8-mlal-dup.c", |
| "src/qs8-gemm/gen/qs8-gemm-1x8c2-minmax-fp32-neonv8-mlal-ld1r.c", |
| "src/qs8-gemm/gen/qs8-gemm-1x8c2-minmax-fp32-neonv8-mlal-ld2r.c", |
| "src/qs8-gemm/gen/qs8-gemm-1x8c2-minmax-fp32-neonv8-mlal-ld4r.c", |
| "src/qs8-gemm/gen/qs8-gemm-1x8c2s4-minmax-fp32-neonv8-mlal.c", |
| "src/qs8-gemm/gen/qs8-gemm-1x8c4-minmax-fp32-neonv8-mlal-dup.c", |
| "src/qs8-gemm/gen/qs8-gemm-1x8c4-minmax-fp32-neonv8-mlal-ld1r.c", |
| "src/qs8-gemm/gen/qs8-gemm-1x8c4-minmax-fp32-neonv8-mlal-ld2r.c", |
| "src/qs8-gemm/gen/qs8-gemm-1x8c4s2-minmax-fp32-neonv8-mlal.c", |
| "src/qs8-gemm/gen/qs8-gemm-1x8c8-minmax-fp32-neonv8-mlal.c", |
| "src/qs8-gemm/gen/qs8-gemm-1x16-minmax-fp32-neonv8-mlal-lane.c", |
| "src/qs8-gemm/gen/qs8-gemm-2x8c2-minmax-fp32-neonv8-mlal-dup.c", |
| "src/qs8-gemm/gen/qs8-gemm-2x8c2-minmax-fp32-neonv8-mlal-ld1r.c", |
| "src/qs8-gemm/gen/qs8-gemm-2x8c2-minmax-fp32-neonv8-mlal-ld2r.c", |
| "src/qs8-gemm/gen/qs8-gemm-2x8c2-minmax-fp32-neonv8-mlal-ld4r.c", |
| "src/qs8-gemm/gen/qs8-gemm-2x8c2s4-minmax-fp32-neonv8-mlal.c", |
| "src/qs8-gemm/gen/qs8-gemm-2x8c4-minmax-fp32-neonv8-mlal-dup.c", |
| "src/qs8-gemm/gen/qs8-gemm-2x8c4-minmax-fp32-neonv8-mlal-ld1r.c", |
| "src/qs8-gemm/gen/qs8-gemm-2x8c4-minmax-fp32-neonv8-mlal-ld2r.c", |
| "src/qs8-gemm/gen/qs8-gemm-2x8c4s2-minmax-fp32-neonv8-mlal.c", |
| "src/qs8-gemm/gen/qs8-gemm-2x8c8-minmax-fp32-neonv8-mlal.c", |
| "src/qs8-gemm/gen/qs8-gemm-4x16-minmax-fp32-neonv8-mlal-lane.c", |
| "src/qs8-igemm/gen/qs8-igemm-1x8c2-minmax-fp32-neonv8-mlal-dup.c", |
| "src/qs8-igemm/gen/qs8-igemm-1x8c2-minmax-fp32-neonv8-mlal-ld1r.c", |
| "src/qs8-igemm/gen/qs8-igemm-1x8c2-minmax-fp32-neonv8-mlal-ld2r.c", |
| "src/qs8-igemm/gen/qs8-igemm-1x8c2-minmax-fp32-neonv8-mlal-ld4r.c", |
| "src/qs8-igemm/gen/qs8-igemm-1x8c2s4-minmax-fp32-neonv8-mlal.c", |
| "src/qs8-igemm/gen/qs8-igemm-1x8c4-minmax-fp32-neonv8-mlal-dup.c", |
| "src/qs8-igemm/gen/qs8-igemm-1x8c4-minmax-fp32-neonv8-mlal-ld1r.c", |
| "src/qs8-igemm/gen/qs8-igemm-1x8c4-minmax-fp32-neonv8-mlal-ld2r.c", |
| "src/qs8-igemm/gen/qs8-igemm-1x8c4s2-minmax-fp32-neonv8-mlal.c", |
| "src/qs8-igemm/gen/qs8-igemm-1x8c8-minmax-fp32-neonv8-mlal.c", |
| "src/qs8-igemm/gen/qs8-igemm-1x16-minmax-fp32-neonv8-mlal-lane.c", |
| "src/qs8-igemm/gen/qs8-igemm-2x8c2-minmax-fp32-neonv8-mlal-dup.c", |
| "src/qs8-igemm/gen/qs8-igemm-2x8c2-minmax-fp32-neonv8-mlal-ld1r.c", |
| "src/qs8-igemm/gen/qs8-igemm-2x8c2-minmax-fp32-neonv8-mlal-ld2r.c", |
| "src/qs8-igemm/gen/qs8-igemm-2x8c2-minmax-fp32-neonv8-mlal-ld4r.c", |
| "src/qs8-igemm/gen/qs8-igemm-2x8c2s4-minmax-fp32-neonv8-mlal.c", |
| "src/qs8-igemm/gen/qs8-igemm-2x8c4-minmax-fp32-neonv8-mlal-dup.c", |
| "src/qs8-igemm/gen/qs8-igemm-2x8c4-minmax-fp32-neonv8-mlal-ld1r.c", |
| "src/qs8-igemm/gen/qs8-igemm-2x8c4-minmax-fp32-neonv8-mlal-ld2r.c", |
| "src/qs8-igemm/gen/qs8-igemm-2x8c4s2-minmax-fp32-neonv8-mlal.c", |
| "src/qs8-igemm/gen/qs8-igemm-2x8c8-minmax-fp32-neonv8-mlal.c", |
| "src/qs8-igemm/gen/qs8-igemm-4x16-minmax-fp32-neonv8-mlal-lane.c", |
| "src/qs8-qc8w-dwconv/gen/qs8-qc8w-dwconv-3p8c-minmax-fp32-neonv8-mla8-ld64.c", |
| "src/qs8-qc8w-dwconv/gen/qs8-qc8w-dwconv-3p16c-minmax-fp32-neonv8-mla8-ld64.c", |
| "src/qs8-qc8w-dwconv/gen/qs8-qc8w-dwconv-3p16c-minmax-fp32-neonv8-mla8-ld128.c", |
| "src/qs8-qc8w-dwconv/gen/qs8-qc8w-dwconv-5f5m5l8c8s8r-minmax-fp32-neonv8-mla8-ld64.c", |
| "src/qs8-qc8w-dwconv/gen/qs8-qc8w-dwconv-5f5m5l8c8s8r-minmax-fp32-neonv8-mul8-ld64.c", |
| "src/qs8-qc8w-dwconv/gen/qs8-qc8w-dwconv-5f5m5l8c8s8r-minmax-fp32-neonv8-mul16.c", |
| "src/qs8-qc8w-dwconv/gen/qs8-qc8w-dwconv-5f5m5l16c8s8r-minmax-fp32-neonv8-mla8-ld64.c", |
| "src/qs8-qc8w-dwconv/gen/qs8-qc8w-dwconv-5f5m5l16c8s8r-minmax-fp32-neonv8-mla8-ld128.c", |
| "src/qs8-qc8w-dwconv/gen/qs8-qc8w-dwconv-5f5m5l16c8s8r-minmax-fp32-neonv8-mul8-ld64.c", |
| "src/qs8-qc8w-dwconv/gen/qs8-qc8w-dwconv-5f5m5l16c8s8r-minmax-fp32-neonv8-mul8-ld128.c", |
| "src/qs8-qc8w-dwconv/gen/qs8-qc8w-dwconv-5f5m5l16c8s8r-minmax-fp32-neonv8-mul16.c", |
| "src/qs8-qc8w-dwconv/gen/qs8-qc8w-dwconv-5f5m5l32c8s8r-minmax-fp32-neonv8-mul16.c", |
| "src/qs8-qc8w-dwconv/gen/qs8-qc8w-dwconv-6f6m7l8c8s8r-minmax-fp32-neonv8-mla8-ld64.c", |
| "src/qs8-qc8w-dwconv/gen/qs8-qc8w-dwconv-6f6m7l8c8s8r-minmax-fp32-neonv8-mul8-ld64.c", |
| "src/qs8-qc8w-dwconv/gen/qs8-qc8w-dwconv-6f6m7l8c8s8r-minmax-fp32-neonv8-mul16.c", |
| "src/qs8-qc8w-dwconv/gen/qs8-qc8w-dwconv-6f6m7l16c8s8r-minmax-fp32-neonv8-mla8-ld64.c", |
| "src/qs8-qc8w-dwconv/gen/qs8-qc8w-dwconv-6f6m7l16c8s8r-minmax-fp32-neonv8-mla8-ld128.c", |
| "src/qs8-qc8w-dwconv/gen/qs8-qc8w-dwconv-6f6m7l16c8s8r-minmax-fp32-neonv8-mul8-ld64.c", |
| "src/qs8-qc8w-dwconv/gen/qs8-qc8w-dwconv-6f6m7l16c8s8r-minmax-fp32-neonv8-mul8-ld128.c", |
| "src/qs8-qc8w-dwconv/gen/qs8-qc8w-dwconv-6f6m7l16c8s8r-minmax-fp32-neonv8-mul16.c", |
| "src/qs8-qc8w-dwconv/gen/qs8-qc8w-dwconv-6f6m7l32c8s8r-minmax-fp32-neonv8-mul16.c", |
| "src/qs8-qc8w-dwconv/gen/qs8-qc8w-dwconv-8f8m9l8c8s8r-minmax-fp32-neonv8-mla8-ld64.c", |
| "src/qs8-qc8w-dwconv/gen/qs8-qc8w-dwconv-8f8m9l8c8s8r-minmax-fp32-neonv8-mul8-ld64.c", |
| "src/qs8-qc8w-dwconv/gen/qs8-qc8w-dwconv-8f8m9l8c8s8r-minmax-fp32-neonv8-mul16.c", |
| "src/qs8-qc8w-dwconv/gen/qs8-qc8w-dwconv-8f8m9l16c8s8r-minmax-fp32-neonv8-mla8-ld64.c", |
| "src/qs8-qc8w-dwconv/gen/qs8-qc8w-dwconv-8f8m9l16c8s8r-minmax-fp32-neonv8-mla8-ld128.c", |
| "src/qs8-qc8w-dwconv/gen/qs8-qc8w-dwconv-8f8m9l16c8s8r-minmax-fp32-neonv8-mul8-ld64.c", |
| "src/qs8-qc8w-dwconv/gen/qs8-qc8w-dwconv-8f8m9l16c8s8r-minmax-fp32-neonv8-mul8-ld128.c", |
| "src/qs8-qc8w-dwconv/gen/qs8-qc8w-dwconv-8f8m9l16c8s8r-minmax-fp32-neonv8-mul16.c", |
| "src/qs8-qc8w-dwconv/gen/qs8-qc8w-dwconv-8f8m9l32c8s8r-minmax-fp32-neonv8-mul16.c", |
| "src/qs8-qc8w-dwconv/gen/qs8-qc8w-dwconv-9p8c-minmax-fp32-neonv8-mla8-ld64.c", |
| "src/qs8-qc8w-dwconv/gen/qs8-qc8w-dwconv-9p8c-minmax-fp32-neonv8-mul8-ld64.c", |
| "src/qs8-qc8w-dwconv/gen/qs8-qc8w-dwconv-9p8c-minmax-fp32-neonv8-mul16.c", |
| "src/qs8-qc8w-dwconv/gen/qs8-qc8w-dwconv-9p16c-minmax-fp32-neonv8-mla8-ld64.c", |
| "src/qs8-qc8w-dwconv/gen/qs8-qc8w-dwconv-9p16c-minmax-fp32-neonv8-mla8-ld128.c", |
| "src/qs8-qc8w-dwconv/gen/qs8-qc8w-dwconv-9p16c-minmax-fp32-neonv8-mul8-ld64.c", |
| "src/qs8-qc8w-dwconv/gen/qs8-qc8w-dwconv-9p16c-minmax-fp32-neonv8-mul8-ld128.c", |
| "src/qs8-qc8w-dwconv/gen/qs8-qc8w-dwconv-9p16c-minmax-fp32-neonv8-mul16.c", |
| "src/qs8-qc8w-dwconv/gen/qs8-qc8w-dwconv-9p32c-minmax-fp32-neonv8-mul16.c", |
| "src/qs8-qc8w-dwconv/gen/qs8-qc8w-dwconv-25p8c-minmax-fp32-neonv8-mla8-ld64.c", |
| "src/qs8-qc8w-dwconv/gen/qs8-qc8w-dwconv-25p8c-minmax-fp32-neonv8-mul8-ld64.c", |
| "src/qs8-qc8w-dwconv/gen/qs8-qc8w-dwconv-25p8c-minmax-fp32-neonv8-mul16.c", |
| "src/qs8-qc8w-dwconv/gen/qs8-qc8w-dwconv-25p16c-minmax-fp32-neonv8-mla8-ld64.c", |
| "src/qs8-qc8w-dwconv/gen/qs8-qc8w-dwconv-25p16c-minmax-fp32-neonv8-mla8-ld128.c", |
| "src/qs8-qc8w-dwconv/gen/qs8-qc8w-dwconv-25p16c-minmax-fp32-neonv8-mul8-ld64.c", |
| "src/qs8-qc8w-dwconv/gen/qs8-qc8w-dwconv-25p16c-minmax-fp32-neonv8-mul8-ld128.c", |
| "src/qs8-qc8w-dwconv/gen/qs8-qc8w-dwconv-25p16c-minmax-fp32-neonv8-mul16.c", |
| "src/qs8-qc8w-dwconv/gen/qs8-qc8w-dwconv-25p32c-minmax-fp32-neonv8-mul16.c", |
| "src/qs8-qc8w-gemm/gen/qs8-qc8w-gemm-1x8-minmax-fp32-neonv8-mlal-lane-prfm.c", |
| "src/qs8-qc8w-gemm/gen/qs8-qc8w-gemm-1x8-minmax-fp32-neonv8-mlal-lane.c", |
| "src/qs8-qc8w-gemm/gen/qs8-qc8w-gemm-1x8c2-minmax-fp32-neonv8-mlal-dup.c", |
| "src/qs8-qc8w-gemm/gen/qs8-qc8w-gemm-1x8c2-minmax-fp32-neonv8-mlal-ld1r.c", |
| "src/qs8-qc8w-gemm/gen/qs8-qc8w-gemm-1x8c2-minmax-fp32-neonv8-mlal-ld2r.c", |
| "src/qs8-qc8w-gemm/gen/qs8-qc8w-gemm-1x8c2-minmax-fp32-neonv8-mlal-ld4r.c", |
| "src/qs8-qc8w-gemm/gen/qs8-qc8w-gemm-1x8c2s4-minmax-fp32-neonv8-mlal.c", |
| "src/qs8-qc8w-gemm/gen/qs8-qc8w-gemm-1x8c4-minmax-fp32-neonv8-mlal-dup.c", |
| "src/qs8-qc8w-gemm/gen/qs8-qc8w-gemm-1x8c4-minmax-fp32-neonv8-mlal-ld1r.c", |
| "src/qs8-qc8w-gemm/gen/qs8-qc8w-gemm-1x8c4-minmax-fp32-neonv8-mlal-ld2r.c", |
| "src/qs8-qc8w-gemm/gen/qs8-qc8w-gemm-1x8c4s2-minmax-fp32-neonv8-mlal.c", |
| "src/qs8-qc8w-gemm/gen/qs8-qc8w-gemm-1x8c8-minmax-fp32-neonv8-mlal.c", |
| "src/qs8-qc8w-gemm/gen/qs8-qc8w-gemm-1x16-minmax-fp32-neonv8-mlal-lane-prfm.c", |
| "src/qs8-qc8w-gemm/gen/qs8-qc8w-gemm-1x16-minmax-fp32-neonv8-mlal-lane.c", |
| "src/qs8-qc8w-gemm/gen/qs8-qc8w-gemm-2x8-minmax-fp32-neonv8-mlal-lane-prfm.c", |
| "src/qs8-qc8w-gemm/gen/qs8-qc8w-gemm-2x8-minmax-fp32-neonv8-mlal-lane.c", |
| "src/qs8-qc8w-gemm/gen/qs8-qc8w-gemm-2x8c2-minmax-fp32-neonv8-mlal-dup.c", |
| "src/qs8-qc8w-gemm/gen/qs8-qc8w-gemm-2x8c2-minmax-fp32-neonv8-mlal-ld1r.c", |
| "src/qs8-qc8w-gemm/gen/qs8-qc8w-gemm-2x8c2-minmax-fp32-neonv8-mlal-ld2r.c", |
| "src/qs8-qc8w-gemm/gen/qs8-qc8w-gemm-2x8c2-minmax-fp32-neonv8-mlal-ld4r.c", |
| "src/qs8-qc8w-gemm/gen/qs8-qc8w-gemm-2x8c2s4-minmax-fp32-neonv8-mlal.c", |
| "src/qs8-qc8w-gemm/gen/qs8-qc8w-gemm-2x8c4-minmax-fp32-neonv8-mlal-dup.c", |
| "src/qs8-qc8w-gemm/gen/qs8-qc8w-gemm-2x8c4-minmax-fp32-neonv8-mlal-ld1r.c", |
| "src/qs8-qc8w-gemm/gen/qs8-qc8w-gemm-2x8c4-minmax-fp32-neonv8-mlal-ld2r.c", |
| "src/qs8-qc8w-gemm/gen/qs8-qc8w-gemm-2x8c4s2-minmax-fp32-neonv8-mlal.c", |
| "src/qs8-qc8w-gemm/gen/qs8-qc8w-gemm-2x8c8-minmax-fp32-neonv8-mlal.c", |
| "src/qs8-qc8w-gemm/gen/qs8-qc8w-gemm-2x16-minmax-fp32-neonv8-mlal-lane-prfm.c", |
| "src/qs8-qc8w-gemm/gen/qs8-qc8w-gemm-2x16-minmax-fp32-neonv8-mlal-lane.c", |
| "src/qs8-qc8w-gemm/gen/qs8-qc8w-gemm-3x8-minmax-fp32-neonv8-mlal-lane-prfm.c", |
| "src/qs8-qc8w-gemm/gen/qs8-qc8w-gemm-3x8-minmax-fp32-neonv8-mlal-lane.c", |
| "src/qs8-qc8w-gemm/gen/qs8-qc8w-gemm-3x16-minmax-fp32-neonv8-mlal-lane-prfm.c", |
| "src/qs8-qc8w-gemm/gen/qs8-qc8w-gemm-3x16-minmax-fp32-neonv8-mlal-lane.c", |
| "src/qs8-qc8w-gemm/gen/qs8-qc8w-gemm-4x8-minmax-fp32-neonv8-mlal-lane-prfm.c", |
| "src/qs8-qc8w-gemm/gen/qs8-qc8w-gemm-4x8-minmax-fp32-neonv8-mlal-lane.c", |
| "src/qs8-qc8w-gemm/gen/qs8-qc8w-gemm-4x16-minmax-fp32-neonv8-mlal-lane-prfm.c", |
| "src/qs8-qc8w-gemm/gen/qs8-qc8w-gemm-4x16-minmax-fp32-neonv8-mlal-lane.c", |
| "src/qs8-qc8w-gemm/gen/qs8-qc8w-gemm-6x8-minmax-fp32-neonv8-mlal-lane-prfm.c", |
| "src/qs8-qc8w-gemm/gen/qs8-qc8w-gemm-6x8-minmax-fp32-neonv8-mlal-lane.c", |
| "src/qs8-qc8w-gemm/gen/qs8-qc8w-gemm-6x16-minmax-fp32-neonv8-mlal-lane-prfm.c", |
| "src/qs8-qc8w-gemm/gen/qs8-qc8w-gemm-6x16-minmax-fp32-neonv8-mlal-lane.c", |
| "src/qs8-qc8w-igemm/gen/qs8-qc8w-igemm-1x8-minmax-fp32-neonv8-mlal-lane-prfm.c", |
| "src/qs8-qc8w-igemm/gen/qs8-qc8w-igemm-1x8-minmax-fp32-neonv8-mlal-lane.c", |
| "src/qs8-qc8w-igemm/gen/qs8-qc8w-igemm-1x8c2-minmax-fp32-neonv8-mlal-dup.c", |
| "src/qs8-qc8w-igemm/gen/qs8-qc8w-igemm-1x8c2-minmax-fp32-neonv8-mlal-ld1r.c", |
| "src/qs8-qc8w-igemm/gen/qs8-qc8w-igemm-1x8c2-minmax-fp32-neonv8-mlal-ld2r.c", |
| "src/qs8-qc8w-igemm/gen/qs8-qc8w-igemm-1x8c2-minmax-fp32-neonv8-mlal-ld4r.c", |
| "src/qs8-qc8w-igemm/gen/qs8-qc8w-igemm-1x8c2s4-minmax-fp32-neonv8-mlal.c", |
| "src/qs8-qc8w-igemm/gen/qs8-qc8w-igemm-1x8c4-minmax-fp32-neonv8-mlal-dup.c", |
| "src/qs8-qc8w-igemm/gen/qs8-qc8w-igemm-1x8c4-minmax-fp32-neonv8-mlal-ld1r.c", |
| "src/qs8-qc8w-igemm/gen/qs8-qc8w-igemm-1x8c4-minmax-fp32-neonv8-mlal-ld2r.c", |
| "src/qs8-qc8w-igemm/gen/qs8-qc8w-igemm-1x8c4s2-minmax-fp32-neonv8-mlal.c", |
| "src/qs8-qc8w-igemm/gen/qs8-qc8w-igemm-1x8c8-minmax-fp32-neonv8-mlal.c", |
| "src/qs8-qc8w-igemm/gen/qs8-qc8w-igemm-1x16-minmax-fp32-neonv8-mlal-lane-prfm.c", |
| "src/qs8-qc8w-igemm/gen/qs8-qc8w-igemm-1x16-minmax-fp32-neonv8-mlal-lane.c", |
| "src/qs8-qc8w-igemm/gen/qs8-qc8w-igemm-2x8-minmax-fp32-neonv8-mlal-lane-prfm.c", |
| "src/qs8-qc8w-igemm/gen/qs8-qc8w-igemm-2x8-minmax-fp32-neonv8-mlal-lane.c", |
| "src/qs8-qc8w-igemm/gen/qs8-qc8w-igemm-2x8c2-minmax-fp32-neonv8-mlal-dup.c", |
| "src/qs8-qc8w-igemm/gen/qs8-qc8w-igemm-2x8c2-minmax-fp32-neonv8-mlal-ld1r.c", |
| "src/qs8-qc8w-igemm/gen/qs8-qc8w-igemm-2x8c2-minmax-fp32-neonv8-mlal-ld2r.c", |
| "src/qs8-qc8w-igemm/gen/qs8-qc8w-igemm-2x8c2-minmax-fp32-neonv8-mlal-ld4r.c", |
| "src/qs8-qc8w-igemm/gen/qs8-qc8w-igemm-2x8c2s4-minmax-fp32-neonv8-mlal.c", |
| "src/qs8-qc8w-igemm/gen/qs8-qc8w-igemm-2x8c4-minmax-fp32-neonv8-mlal-dup.c", |
| "src/qs8-qc8w-igemm/gen/qs8-qc8w-igemm-2x8c4-minmax-fp32-neonv8-mlal-ld1r.c", |
| "src/qs8-qc8w-igemm/gen/qs8-qc8w-igemm-2x8c4-minmax-fp32-neonv8-mlal-ld2r.c", |
| "src/qs8-qc8w-igemm/gen/qs8-qc8w-igemm-2x8c4s2-minmax-fp32-neonv8-mlal.c", |
| "src/qs8-qc8w-igemm/gen/qs8-qc8w-igemm-2x8c8-minmax-fp32-neonv8-mlal.c", |
| "src/qs8-qc8w-igemm/gen/qs8-qc8w-igemm-2x16-minmax-fp32-neonv8-mlal-lane-prfm.c", |
| "src/qs8-qc8w-igemm/gen/qs8-qc8w-igemm-2x16-minmax-fp32-neonv8-mlal-lane.c", |
| "src/qs8-qc8w-igemm/gen/qs8-qc8w-igemm-3x8-minmax-fp32-neonv8-mlal-lane-prfm.c", |
| "src/qs8-qc8w-igemm/gen/qs8-qc8w-igemm-3x8-minmax-fp32-neonv8-mlal-lane.c", |
| "src/qs8-qc8w-igemm/gen/qs8-qc8w-igemm-3x16-minmax-fp32-neonv8-mlal-lane-prfm.c", |
| "src/qs8-qc8w-igemm/gen/qs8-qc8w-igemm-3x16-minmax-fp32-neonv8-mlal-lane.c", |
| "src/qs8-qc8w-igemm/gen/qs8-qc8w-igemm-4x8-minmax-fp32-neonv8-mlal-lane-prfm.c", |
| "src/qs8-qc8w-igemm/gen/qs8-qc8w-igemm-4x8-minmax-fp32-neonv8-mlal-lane.c", |
| "src/qs8-qc8w-igemm/gen/qs8-qc8w-igemm-4x16-minmax-fp32-neonv8-mlal-lane-prfm.c", |
| "src/qs8-qc8w-igemm/gen/qs8-qc8w-igemm-4x16-minmax-fp32-neonv8-mlal-lane.c", |
| "src/qs8-qc8w-igemm/gen/qs8-qc8w-igemm-6x8-minmax-fp32-neonv8-mlal-lane-prfm.c", |
| "src/qs8-qc8w-igemm/gen/qs8-qc8w-igemm-6x8-minmax-fp32-neonv8-mlal-lane.c", |
| "src/qs8-qc8w-igemm/gen/qs8-qc8w-igemm-6x16-minmax-fp32-neonv8-mlal-lane-prfm.c", |
| "src/qs8-qc8w-igemm/gen/qs8-qc8w-igemm-6x16-minmax-fp32-neonv8-mlal-lane.c", |
| "src/qs8-vmul/gen/qs8-vmul-minmax-fp32-neonv8-ld64-u8.c", |
| "src/qs8-vmul/gen/qs8-vmul-minmax-fp32-neonv8-ld64-u16.c", |
| "src/qs8-vmul/gen/qs8-vmul-minmax-fp32-neonv8-ld128-u16.c", |
| "src/qs8-vmulc/gen/qs8-vmulc-minmax-fp32-neonv8-ld64-u8.c", |
| "src/qs8-vmulc/gen/qs8-vmulc-minmax-fp32-neonv8-ld64-u16.c", |
| "src/qs8-vmulc/gen/qs8-vmulc-minmax-fp32-neonv8-ld128-u16.c", |
| "src/qu8-dwconv/gen/qu8-dwconv-5f5m5l8c8s8r-minmax-fp32-neonv8-mul16.c", |
| "src/qu8-dwconv/gen/qu8-dwconv-5f5m5l16c8s8r-minmax-fp32-neonv8-mul16.c", |
| "src/qu8-dwconv/gen/qu8-dwconv-5f5m5l32c8s8r-minmax-fp32-neonv8-mul16.c", |
| "src/qu8-dwconv/gen/qu8-dwconv-6f6m7l8c8s8r-minmax-fp32-neonv8-mul16.c", |
| "src/qu8-dwconv/gen/qu8-dwconv-6f6m7l16c8s8r-minmax-fp32-neonv8-mul16.c", |
| "src/qu8-dwconv/gen/qu8-dwconv-6f6m7l32c8s8r-minmax-fp32-neonv8-mul16.c", |
| "src/qu8-dwconv/gen/qu8-dwconv-8f8m9l8c8s8r-minmax-fp32-neonv8-mul16.c", |
| "src/qu8-dwconv/gen/qu8-dwconv-8f8m9l16c8s8r-minmax-fp32-neonv8-mul16.c", |
| "src/qu8-dwconv/gen/qu8-dwconv-8f8m9l32c8s8r-minmax-fp32-neonv8-mul16.c", |
| "src/qu8-dwconv/gen/qu8-dwconv-9p8c-minmax-fp32-neonv8-mul16.c", |
| "src/qu8-dwconv/gen/qu8-dwconv-9p16c-minmax-fp32-neonv8-mul16.c", |
| "src/qu8-dwconv/gen/qu8-dwconv-9p32c-minmax-fp32-neonv8-mul16.c", |
| "src/qu8-dwconv/gen/qu8-dwconv-25p8c-minmax-fp32-neonv8-mul16.c", |
| "src/qu8-dwconv/gen/qu8-dwconv-25p16c-minmax-fp32-neonv8-mul16.c", |
| "src/qu8-dwconv/gen/qu8-dwconv-25p32c-minmax-fp32-neonv8-mul16.c", |
| "src/qu8-gavgpool/gen/qu8-gavgpool-7p7x-minmax-fp32-neonv8-c8.c", |
| "src/qu8-gavgpool/gen/qu8-gavgpool-7p7x-minmax-fp32-neonv8-c16.c", |
| "src/qu8-gavgpool/gen/qu8-gavgpool-7p7x-minmax-fp32-neonv8-c24.c", |
| "src/qu8-gavgpool/gen/qu8-gavgpool-7p7x-minmax-fp32-neonv8-c32.c", |
| "src/qu8-gavgpool/gen/qu8-gavgpool-7x-minmax-fp32-neonv8-c8.c", |
| "src/qu8-gavgpool/gen/qu8-gavgpool-7x-minmax-fp32-neonv8-c16.c", |
| "src/qu8-gavgpool/gen/qu8-gavgpool-7x-minmax-fp32-neonv8-c24.c", |
| "src/qu8-gavgpool/gen/qu8-gavgpool-7x-minmax-fp32-neonv8-c32.c", |
| "src/qu8-gemm/gen/qu8-gemm-1x16-minmax-fp32-neonv8-mlal-lane.c", |
| "src/qu8-gemm/gen/qu8-gemm-4x16-minmax-fp32-neonv8-mlal-lane.c", |
| "src/qu8-igemm/gen/qu8-igemm-1x16-minmax-fp32-neonv8-mlal-lane.c", |
| "src/qu8-igemm/gen/qu8-igemm-4x16-minmax-fp32-neonv8-mlal-lane.c", |
| "src/qu8-vmul/gen/qu8-vmul-minmax-fp32-neonv8-ld64-u8.c", |
| "src/qu8-vmul/gen/qu8-vmul-minmax-fp32-neonv8-ld64-u16.c", |
| "src/qu8-vmul/gen/qu8-vmul-minmax-fp32-neonv8-ld128-u16.c", |
| "src/qu8-vmulc/gen/qu8-vmulc-minmax-fp32-neonv8-ld64-u8.c", |
| "src/qu8-vmulc/gen/qu8-vmulc-minmax-fp32-neonv8-ld64-u16.c", |
| "src/qu8-vmulc/gen/qu8-vmulc-minmax-fp32-neonv8-ld128-u16.c", |
| ] |
| |
| ALL_RVV_MICROKERNEL_SRCS = [ |
| "src/f32-vclamp/gen/f32-vclamp-rvv-u1v.c", |
| "src/f32-vclamp/gen/f32-vclamp-rvv-u2v.c", |
| "src/f32-vclamp/gen/f32-vclamp-rvv-u4v.c", |
| "src/f32-vclamp/gen/f32-vclamp-rvv-u8v.c", |
| "src/f32-vhswish/gen/f32-vhswish-rvv-u1v.c", |
| "src/f32-vhswish/gen/f32-vhswish-rvv-u2v.c", |
| "src/f32-vhswish/gen/f32-vhswish-rvv-u4v.c", |
| "src/f32-vhswish/gen/f32-vhswish-rvv-u8v.c", |
| "src/f32-vsqrt/gen/f32-vsqrt-rvv-sqrt-u1v.c", |
| "src/f32-vsqrt/gen/f32-vsqrt-rvv-sqrt-u2v.c", |
| "src/f32-vsqrt/gen/f32-vsqrt-rvv-sqrt-u4v.c", |
| "src/f32-vsqrt/gen/f32-vsqrt-rvv-sqrt-u8v.c", |
| "src/f32-vunary/gen/f32-vabs-rvv-u1v.c", |
| "src/f32-vunary/gen/f32-vabs-rvv-u2v.c", |
| "src/f32-vunary/gen/f32-vabs-rvv-u4v.c", |
| "src/f32-vunary/gen/f32-vabs-rvv-u8v.c", |
| "src/f32-vunary/gen/f32-vneg-rvv-u1v.c", |
| "src/f32-vunary/gen/f32-vneg-rvv-u2v.c", |
| "src/f32-vunary/gen/f32-vneg-rvv-u4v.c", |
| "src/f32-vunary/gen/f32-vneg-rvv-u8v.c", |
| "src/f32-vunary/gen/f32-vsqr-rvv-u1v.c", |
| "src/f32-vunary/gen/f32-vsqr-rvv-u2v.c", |
| "src/f32-vunary/gen/f32-vsqr-rvv-u4v.c", |
| "src/f32-vunary/gen/f32-vsqr-rvv-u8v.c", |
| ] |
| |
| ALL_SCALAR_MICROKERNEL_SRCS = [ |
| "src/cs16-bfly4/cs16-bfly4-samples1-scalar.c", |
| "src/cs16-bfly4/cs16-bfly4-samples4-scalar.c", |
| "src/cs16-bfly4/gen/cs16-bfly4-scalar-x1.c", |
| "src/cs16-bfly4/gen/cs16-bfly4-scalar-x2.c", |
| "src/cs16-bfly4/gen/cs16-bfly4-scalar-x4.c", |
| "src/cs16-fftr/gen/cs16-fftr-scalar-x1.c", |
| "src/cs16-fftr/gen/cs16-fftr-scalar-x2.c", |
| "src/cs16-fftr/gen/cs16-fftr-scalar-x4.c", |
| "src/cs16-vsquareabs/gen/cs16-vsquareabs-scalar-x1.c", |
| "src/cs16-vsquareabs/gen/cs16-vsquareabs-scalar-x2.c", |
| "src/cs16-vsquareabs/gen/cs16-vsquareabs-scalar-x3.c", |
| "src/cs16-vsquareabs/gen/cs16-vsquareabs-scalar-x4.c", |
| "src/f16-f32-vcvt/gen/f16-f32-vcvt-scalar-u1.c", |
| "src/f16-f32-vcvt/gen/f16-f32-vcvt-scalar-u2.c", |
| "src/f16-f32-vcvt/gen/f16-f32-vcvt-scalar-u3.c", |
| "src/f16-f32-vcvt/gen/f16-f32-vcvt-scalar-u4.c", |
| "src/f32-argmaxpool/f32-argmaxpool-4x-scalar-c1.c", |
| "src/f32-argmaxpool/f32-argmaxpool-9p8x-scalar-c1.c", |
| "src/f32-argmaxpool/f32-argmaxpool-9x-scalar-c1.c", |
| "src/f32-avgpool/f32-avgpool-9p8x-minmax-scalar-c1.c", |
| "src/f32-avgpool/f32-avgpool-9x-minmax-scalar-c1.c", |
| "src/f32-conv-hwc2chw/f32-conv-hwc2chw-3x3s2p1c3x4-scalar-1x1.c", |
| "src/f32-conv-hwc/f32-conv-hwc-3x3s2p0p1c3x4-scalar-1x1.c", |
| "src/f32-conv-hwc/f32-conv-hwc-3x3s2p1c3x4-scalar-1x1.c", |
| "src/f32-dwconv2d-chw/gen/f32-dwconv2d-chw-3x3p1-minmax-scalar-1x1-acc2.c", |
| "src/f32-dwconv2d-chw/gen/f32-dwconv2d-chw-3x3p1-minmax-scalar-1x1-acc3.c", |
| "src/f32-dwconv2d-chw/gen/f32-dwconv2d-chw-3x3p1-minmax-scalar-1x1-acc4.c", |
| "src/f32-dwconv2d-chw/gen/f32-dwconv2d-chw-3x3p1-minmax-scalar-1x1.c", |
| "src/f32-dwconv2d-chw/gen/f32-dwconv2d-chw-3x3p1-minmax-scalar-2x1-acc2.c", |
| "src/f32-dwconv2d-chw/gen/f32-dwconv2d-chw-3x3p1-minmax-scalar-2x1.c", |
| "src/f32-dwconv2d-chw/gen/f32-dwconv2d-chw-3x3p1-minmax-scalar-3x1.c", |
| "src/f32-dwconv2d-chw/gen/f32-dwconv2d-chw-3x3p1-minmax-scalar-4x1.c", |
| "src/f32-dwconv2d-chw/gen/f32-dwconv2d-chw-3x3p1-minmax-scalar-5x1.c", |
| "src/f32-dwconv2d-chw/gen/f32-dwconv2d-chw-3x3p1-minmax-scalar-6x1.c", |
| "src/f32-dwconv2d-chw/gen/f32-dwconv2d-chw-3x3s2p1-minmax-scalar-1x1-acc2.c", |
| "src/f32-dwconv2d-chw/gen/f32-dwconv2d-chw-3x3s2p1-minmax-scalar-1x1-acc3.c", |
| "src/f32-dwconv2d-chw/gen/f32-dwconv2d-chw-3x3s2p1-minmax-scalar-1x1-acc4.c", |
| "src/f32-dwconv2d-chw/gen/f32-dwconv2d-chw-3x3s2p1-minmax-scalar-1x1.c", |
| "src/f32-dwconv2d-chw/gen/f32-dwconv2d-chw-3x3s2p1-minmax-scalar-2x1-acc2.c", |
| "src/f32-dwconv2d-chw/gen/f32-dwconv2d-chw-3x3s2p1-minmax-scalar-2x1.c", |
| "src/f32-dwconv2d-chw/gen/f32-dwconv2d-chw-3x3s2p1-minmax-scalar-3x1.c", |
| "src/f32-dwconv2d-chw/gen/f32-dwconv2d-chw-3x3s2p1-minmax-scalar-4x1.c", |
| "src/f32-dwconv2d-chw/gen/f32-dwconv2d-chw-5x5p2-minmax-scalar-1x1-acc2.c", |
| "src/f32-dwconv2d-chw/gen/f32-dwconv2d-chw-5x5p2-minmax-scalar-1x1-acc3.c", |
| "src/f32-dwconv2d-chw/gen/f32-dwconv2d-chw-5x5p2-minmax-scalar-1x1-acc4.c", |
| "src/f32-dwconv2d-chw/gen/f32-dwconv2d-chw-5x5p2-minmax-scalar-1x1-acc5.c", |
| "src/f32-dwconv2d-chw/gen/f32-dwconv2d-chw-5x5p2-minmax-scalar-1x1.c", |
| "src/f32-dwconv2d-chw/gen/f32-dwconv2d-chw-5x5p2-minmax-scalar-2x1-acc2.c", |
| "src/f32-dwconv2d-chw/gen/f32-dwconv2d-chw-5x5p2-minmax-scalar-2x1-acc3.c", |
| "src/f32-dwconv2d-chw/gen/f32-dwconv2d-chw-5x5p2-minmax-scalar-2x1.c", |
| "src/f32-dwconv2d-chw/gen/f32-dwconv2d-chw-5x5p2-minmax-scalar-3x1-acc2.c", |
| "src/f32-dwconv2d-chw/gen/f32-dwconv2d-chw-5x5p2-minmax-scalar-3x1.c", |
| "src/f32-dwconv2d-chw/gen/f32-dwconv2d-chw-5x5s2p2-minmax-scalar-1x1-acc2.c", |
| "src/f32-dwconv2d-chw/gen/f32-dwconv2d-chw-5x5s2p2-minmax-scalar-1x1-acc3.c", |
| "src/f32-dwconv2d-chw/gen/f32-dwconv2d-chw-5x5s2p2-minmax-scalar-1x1-acc4.c", |
| "src/f32-dwconv2d-chw/gen/f32-dwconv2d-chw-5x5s2p2-minmax-scalar-1x1-acc5.c", |
| "src/f32-dwconv2d-chw/gen/f32-dwconv2d-chw-5x5s2p2-minmax-scalar-1x1.c", |
| "src/f32-dwconv2d-chw/gen/f32-dwconv2d-chw-5x5s2p2-minmax-scalar-2x1-acc2.c", |
| "src/f32-dwconv2d-chw/gen/f32-dwconv2d-chw-5x5s2p2-minmax-scalar-2x1-acc3.c", |
| "src/f32-dwconv2d-chw/gen/f32-dwconv2d-chw-5x5s2p2-minmax-scalar-2x1.c", |
| "src/f32-dwconv2d-chw/gen/f32-dwconv2d-chw-5x5s2p2-minmax-scalar-3x1-acc2.c", |
| "src/f32-dwconv2d-chw/gen/f32-dwconv2d-chw-5x5s2p2-minmax-scalar-3x1.c", |
| "src/f32-dwconv/gen/f32-dwconv-2f2m2l1c1s1r-minmax-scalar-acc2.c", |
| "src/f32-dwconv/gen/f32-dwconv-2f2m2l1c1s1r-minmax-scalar.c", |
| "src/f32-dwconv/gen/f32-dwconv-2f2m2l1c1s1r-scalar-acc2.c", |
| "src/f32-dwconv/gen/f32-dwconv-2f2m2l1c1s1r-scalar.c", |
| "src/f32-dwconv/gen/f32-dwconv-2f2m2l4c1s1r-minmax-scalar-acc2.c", |
| "src/f32-dwconv/gen/f32-dwconv-2f2m2l4c1s1r-minmax-scalar.c", |
| "src/f32-dwconv/gen/f32-dwconv-2f2m2l4c1s1r-scalar-acc2.c", |
| "src/f32-dwconv/gen/f32-dwconv-2f2m2l4c1s1r-scalar.c", |
| "src/f32-dwconv/gen/f32-dwconv-3f3m3l1c1s1r-scalar-acc2.c", |
| "src/f32-dwconv/gen/f32-dwconv-3f3m3l1c1s1r-scalar.c", |
| "src/f32-dwconv/gen/f32-dwconv-3p1c-minmax-scalar-acc2.c", |
| "src/f32-dwconv/gen/f32-dwconv-3p1c-minmax-scalar.c", |
| "src/f32-dwconv/gen/f32-dwconv-3p1c-scalar-acc2.c", |
| "src/f32-dwconv/gen/f32-dwconv-3p1c-scalar.c", |
| "src/f32-dwconv/gen/f32-dwconv-3p2c-minmax-scalar-acc2.c", |
| "src/f32-dwconv/gen/f32-dwconv-3p2c-minmax-scalar.c", |
| "src/f32-dwconv/gen/f32-dwconv-3p2c-scalar-acc2.c", |
| "src/f32-dwconv/gen/f32-dwconv-3p2c-scalar.c", |
| "src/f32-dwconv/gen/f32-dwconv-4p1c-minmax-scalar-acc2.c", |
| "src/f32-dwconv/gen/f32-dwconv-4p1c-minmax-scalar.c", |
| "src/f32-dwconv/gen/f32-dwconv-4p1c-scalar-acc2.c", |
| "src/f32-dwconv/gen/f32-dwconv-4p1c-scalar.c", |
| "src/f32-dwconv/gen/f32-dwconv-4p2c-minmax-scalar-acc2.c", |
| "src/f32-dwconv/gen/f32-dwconv-4p2c-minmax-scalar.c", |
| "src/f32-dwconv/gen/f32-dwconv-4p2c-scalar-acc2.c", |
| "src/f32-dwconv/gen/f32-dwconv-4p2c-scalar.c", |
| "src/f32-dwconv/gen/f32-dwconv-5f5m5l1c1s1r-minmax-scalar-acc2.c", |
| "src/f32-dwconv/gen/f32-dwconv-5f5m5l1c1s1r-minmax-scalar.c", |
| "src/f32-dwconv/gen/f32-dwconv-5f5m5l1c1s1r-scalar-acc2.c", |
| "src/f32-dwconv/gen/f32-dwconv-5f5m5l1c1s1r-scalar.c", |
| "src/f32-dwconv/gen/f32-dwconv-6f6m7l1c1s1r-minmax-scalar-acc2.c", |
| "src/f32-dwconv/gen/f32-dwconv-6f6m7l1c1s1r-minmax-scalar.c", |
| "src/f32-dwconv/gen/f32-dwconv-6f6m7l1c1s1r-scalar-acc2.c", |
| "src/f32-dwconv/gen/f32-dwconv-6f6m7l1c1s1r-scalar.c", |
| "src/f32-dwconv/gen/f32-dwconv-8f8m9l1c1s1r-minmax-scalar-acc2.c", |
| "src/f32-dwconv/gen/f32-dwconv-8f8m9l1c1s1r-minmax-scalar.c", |
| "src/f32-dwconv/gen/f32-dwconv-8f8m9l1c1s1r-scalar-acc2.c", |
| "src/f32-dwconv/gen/f32-dwconv-8f8m9l1c1s1r-scalar.c", |
| "src/f32-dwconv/gen/f32-dwconv-9p1c-minmax-scalar-acc2.c", |
| "src/f32-dwconv/gen/f32-dwconv-9p1c-minmax-scalar.c", |
| "src/f32-dwconv/gen/f32-dwconv-9p1c-scalar-acc2.c", |
| "src/f32-dwconv/gen/f32-dwconv-9p1c-scalar.c", |
| "src/f32-dwconv/gen/f32-dwconv-9p2c-minmax-scalar-acc2.c", |
| "src/f32-dwconv/gen/f32-dwconv-9p2c-minmax-scalar.c", |
| "src/f32-dwconv/gen/f32-dwconv-9p2c-scalar-acc2.c", |
| "src/f32-dwconv/gen/f32-dwconv-9p2c-scalar.c", |
| "src/f32-dwconv/gen/f32-dwconv-25p1c-minmax-scalar-acc2.c", |
| "src/f32-dwconv/gen/f32-dwconv-25p1c-minmax-scalar.c", |
| "src/f32-dwconv/gen/f32-dwconv-25p1c-scalar-acc2.c", |
| "src/f32-dwconv/gen/f32-dwconv-25p1c-scalar.c", |
| "src/f32-dwconv/gen/f32-dwconv-25p2c-minmax-scalar-acc2.c", |
| "src/f32-dwconv/gen/f32-dwconv-25p2c-minmax-scalar.c", |
| "src/f32-dwconv/gen/f32-dwconv-25p2c-scalar-acc2.c", |
| "src/f32-dwconv/gen/f32-dwconv-25p2c-scalar.c", |
| "src/f32-f16-vcvt/gen/f32-f16-vcvt-scalar-bitcast-u1.c", |
| "src/f32-f16-vcvt/gen/f32-f16-vcvt-scalar-bitcast-u2.c", |
| "src/f32-f16-vcvt/gen/f32-f16-vcvt-scalar-bitcast-u3.c", |
| "src/f32-f16-vcvt/gen/f32-f16-vcvt-scalar-bitcast-u4.c", |
| "src/f32-f16-vcvt/gen/f32-f16-vcvt-scalar-fabsf-u1.c", |
| "src/f32-f16-vcvt/gen/f32-f16-vcvt-scalar-fabsf-u2.c", |
| "src/f32-f16-vcvt/gen/f32-f16-vcvt-scalar-fabsf-u3.c", |
| "src/f32-f16-vcvt/gen/f32-f16-vcvt-scalar-fabsf-u4.c", |
| "src/f32-gavgpool-cw/f32-gavgpool-cw-scalar-x1.c", |
| "src/f32-gavgpool/f32-gavgpool-7p7x-minmax-scalar-c1.c", |
| "src/f32-gavgpool/f32-gavgpool-7x-minmax-scalar-c1.c", |
| "src/f32-gemm/gen/f32-gemm-1x4-minmax-scalar.c", |
| "src/f32-gemm/gen/f32-gemm-1x4-relu-scalar.c", |
| "src/f32-gemm/gen/f32-gemm-1x4-scalar.c", |
| "src/f32-gemm/gen/f32-gemm-2x4-minmax-scalar.c", |
| "src/f32-gemm/gen/f32-gemm-2x4-relu-scalar.c", |
| "src/f32-gemm/gen/f32-gemm-2x4-scalar.c", |
| "src/f32-gemm/gen/f32-gemm-4x2-minmax-scalar.c", |
| "src/f32-gemm/gen/f32-gemm-4x2-relu-scalar.c", |
| "src/f32-gemm/gen/f32-gemm-4x2-scalar.c", |
| "src/f32-gemm/gen/f32-gemm-4x4-minmax-scalar.c", |
| "src/f32-gemm/gen/f32-gemm-4x4-relu-scalar.c", |
| "src/f32-gemm/gen/f32-gemm-4x4-scalar.c", |
| "src/f32-gemminc/gen/f32-gemminc-1x4-minmax-scalar.c", |
| "src/f32-gemminc/gen/f32-gemminc-2x4-minmax-scalar.c", |
| "src/f32-gemminc/gen/f32-gemminc-4x4-minmax-scalar.c", |
| "src/f32-ibilinear-chw/gen/f32-ibilinear-chw-scalar-p1.c", |
| "src/f32-ibilinear-chw/gen/f32-ibilinear-chw-scalar-p2.c", |
| "src/f32-ibilinear-chw/gen/f32-ibilinear-chw-scalar-p4.c", |
| "src/f32-ibilinear/gen/f32-ibilinear-scalar-c1.c", |
| "src/f32-ibilinear/gen/f32-ibilinear-scalar-c2.c", |
| "src/f32-ibilinear/gen/f32-ibilinear-scalar-c4.c", |
| "src/f32-igemm/gen/f32-igemm-1x4-minmax-scalar.c", |
| "src/f32-igemm/gen/f32-igemm-1x4-relu-scalar.c", |
| "src/f32-igemm/gen/f32-igemm-1x4-scalar.c", |
| "src/f32-igemm/gen/f32-igemm-2x4-minmax-scalar.c", |
| "src/f32-igemm/gen/f32-igemm-2x4-relu-scalar.c", |
| "src/f32-igemm/gen/f32-igemm-2x4-scalar.c", |
| "src/f32-igemm/gen/f32-igemm-4x2-minmax-scalar.c", |
| "src/f32-igemm/gen/f32-igemm-4x2-relu-scalar.c", |
| "src/f32-igemm/gen/f32-igemm-4x2-scalar.c", |
| "src/f32-igemm/gen/f32-igemm-4x4-minmax-scalar.c", |
| "src/f32-igemm/gen/f32-igemm-4x4-relu-scalar.c", |
| "src/f32-igemm/gen/f32-igemm-4x4-scalar.c", |
| "src/f32-maxpool/f32-maxpool-9p8x-minmax-scalar-c1.c", |
| "src/f32-pavgpool/f32-pavgpool-9p8x-minmax-scalar-c1.c", |
| "src/f32-pavgpool/f32-pavgpool-9x-minmax-scalar-c1.c", |
| "src/f32-ppmm/gen/f32-ppmm-2x4-minmax-scalar.c", |
| "src/f32-ppmm/gen/f32-ppmm-3x3-minmax-scalar.c", |
| "src/f32-ppmm/gen/f32-ppmm-4x2-minmax-scalar.c", |
| "src/f32-ppmm/gen/f32-ppmm-4x4-minmax-scalar.c", |
| "src/f32-prelu/gen/f32-prelu-scalar-2x1.c", |
| "src/f32-prelu/gen/f32-prelu-scalar-2x4.c", |
| "src/f32-qc4w-gemm/gen/f32-qc4w-gemm-1x4-minmax-scalar.c", |
| "src/f32-qc4w-gemm/gen/f32-qc4w-gemm-2x4-minmax-scalar.c", |
| "src/f32-qc4w-gemm/gen/f32-qc4w-gemm-4x2-minmax-scalar.c", |
| "src/f32-qc4w-gemm/gen/f32-qc4w-gemm-4x4-minmax-scalar.c", |
| "src/f32-qc8w-gemm/gen/f32-qc8w-gemm-1x4-minmax-scalar.c", |
| "src/f32-qc8w-gemm/gen/f32-qc8w-gemm-1x4-relu-scalar.c", |
| "src/f32-qc8w-gemm/gen/f32-qc8w-gemm-1x4-scalar.c", |
| "src/f32-qc8w-gemm/gen/f32-qc8w-gemm-2x4-minmax-scalar.c", |
| "src/f32-qc8w-gemm/gen/f32-qc8w-gemm-2x4-relu-scalar.c", |
| "src/f32-qc8w-gemm/gen/f32-qc8w-gemm-2x4-scalar.c", |
| "src/f32-qc8w-gemm/gen/f32-qc8w-gemm-4x2-minmax-scalar.c", |
| "src/f32-qc8w-gemm/gen/f32-qc8w-gemm-4x2-relu-scalar.c", |
| "src/f32-qc8w-gemm/gen/f32-qc8w-gemm-4x2-scalar.c", |
| "src/f32-qc8w-gemm/gen/f32-qc8w-gemm-4x4-minmax-scalar.c", |
| "src/f32-qc8w-gemm/gen/f32-qc8w-gemm-4x4-relu-scalar.c", |
| "src/f32-qc8w-gemm/gen/f32-qc8w-gemm-4x4-scalar.c", |
| "src/f32-qc8w-spmm/gen/f32-qc8w-spmm-1x1-minmax-scalar.c", |
| "src/f32-qc8w-spmm/gen/f32-qc8w-spmm-2x1-minmax-scalar.c", |
| "src/f32-qc8w-spmm/gen/f32-qc8w-spmm-4x1-minmax-scalar.c", |
| "src/f32-qc8w-spmm/gen/f32-qc8w-spmm-8x1-minmax-scalar.c", |
| "src/f32-qc8w-spmm/gen/f32-qc8w-spmm-8x2-minmax-scalar.c", |
| "src/f32-qc8w-spmm/gen/f32-qc8w-spmm-8x4-minmax-scalar.c", |
| "src/f32-qs8-vcvt/gen/f32-qs8-vcvt-scalar-fmagic-u1.c", |
| "src/f32-qs8-vcvt/gen/f32-qs8-vcvt-scalar-fmagic-u2.c", |
| "src/f32-qs8-vcvt/gen/f32-qs8-vcvt-scalar-fmagic-u3.c", |
| "src/f32-qs8-vcvt/gen/f32-qs8-vcvt-scalar-fmagic-u4.c", |
| "src/f32-qs8-vcvt/gen/f32-qs8-vcvt-scalar-imagic-u1.c", |
| "src/f32-qs8-vcvt/gen/f32-qs8-vcvt-scalar-imagic-u2.c", |
| "src/f32-qs8-vcvt/gen/f32-qs8-vcvt-scalar-imagic-u3.c", |
| "src/f32-qs8-vcvt/gen/f32-qs8-vcvt-scalar-imagic-u4.c", |
| "src/f32-qs8-vcvt/gen/f32-qs8-vcvt-scalar-lrintf-u1.c", |
| "src/f32-qs8-vcvt/gen/f32-qs8-vcvt-scalar-lrintf-u2.c", |
| "src/f32-qs8-vcvt/gen/f32-qs8-vcvt-scalar-lrintf-u3.c", |
| "src/f32-qs8-vcvt/gen/f32-qs8-vcvt-scalar-lrintf-u4.c", |
| "src/f32-qu8-vcvt/gen/f32-qu8-vcvt-scalar-fmagic-u1.c", |
| "src/f32-qu8-vcvt/gen/f32-qu8-vcvt-scalar-fmagic-u2.c", |
| "src/f32-qu8-vcvt/gen/f32-qu8-vcvt-scalar-fmagic-u3.c", |
| "src/f32-qu8-vcvt/gen/f32-qu8-vcvt-scalar-fmagic-u4.c", |
| "src/f32-qu8-vcvt/gen/f32-qu8-vcvt-scalar-imagic-u1.c", |
| "src/f32-qu8-vcvt/gen/f32-qu8-vcvt-scalar-imagic-u2.c", |
| "src/f32-qu8-vcvt/gen/f32-qu8-vcvt-scalar-imagic-u3.c", |
| "src/f32-qu8-vcvt/gen/f32-qu8-vcvt-scalar-imagic-u4.c", |
| "src/f32-qu8-vcvt/gen/f32-qu8-vcvt-scalar-lrintf-u1.c", |
| "src/f32-qu8-vcvt/gen/f32-qu8-vcvt-scalar-lrintf-u2.c", |
| "src/f32-qu8-vcvt/gen/f32-qu8-vcvt-scalar-lrintf-u3.c", |
| "src/f32-qu8-vcvt/gen/f32-qu8-vcvt-scalar-lrintf-u4.c", |
| "src/f32-raddstoreexpminusmax/gen/f32-raddstoreexpminusmax-scalar-rr2-lut64-p2-u1.c", |
| "src/f32-raddstoreexpminusmax/gen/f32-raddstoreexpminusmax-scalar-rr2-lut64-p2-u2-acc2.c", |
| "src/f32-raddstoreexpminusmax/gen/f32-raddstoreexpminusmax-scalar-rr2-lut64-p2-u2.c", |
| "src/f32-raddstoreexpminusmax/gen/f32-raddstoreexpminusmax-scalar-rr2-lut64-p2-u4-acc2.c", |
| "src/f32-raddstoreexpminusmax/gen/f32-raddstoreexpminusmax-scalar-rr2-lut64-p2-u4-acc4.c", |
| "src/f32-raddstoreexpminusmax/gen/f32-raddstoreexpminusmax-scalar-rr2-lut64-p2-u4.c", |
| "src/f32-raddstoreexpminusmax/gen/f32-raddstoreexpminusmax-scalar-rr2-p5-u1.c", |
| "src/f32-raddstoreexpminusmax/gen/f32-raddstoreexpminusmax-scalar-rr2-p5-u2-acc2.c", |
| "src/f32-raddstoreexpminusmax/gen/f32-raddstoreexpminusmax-scalar-rr2-p5-u2.c", |
| "src/f32-raddstoreexpminusmax/gen/f32-raddstoreexpminusmax-scalar-rr2-p5-u4-acc2.c", |
| "src/f32-raddstoreexpminusmax/gen/f32-raddstoreexpminusmax-scalar-rr2-p5-u4-acc4.c", |
| "src/f32-raddstoreexpminusmax/gen/f32-raddstoreexpminusmax-scalar-rr2-p5-u4.c", |
| "src/f32-rmax/f32-rmax-scalar.c", |
| "src/f32-rminmax/gen/f32-rmax-scalar-u1.c", |
| "src/f32-rminmax/gen/f32-rmax-scalar-u2-acc2.c", |
| "src/f32-rminmax/gen/f32-rmax-scalar-u3-acc3.c", |
| "src/f32-rminmax/gen/f32-rmax-scalar-u4-acc2.c", |
| "src/f32-rminmax/gen/f32-rmax-scalar-u4-acc4.c", |
| "src/f32-rminmax/gen/f32-rmin-scalar-u1.c", |
| "src/f32-rminmax/gen/f32-rmin-scalar-u2-acc2.c", |
| "src/f32-rminmax/gen/f32-rmin-scalar-u3-acc3.c", |
| "src/f32-rminmax/gen/f32-rmin-scalar-u4-acc2.c", |
| "src/f32-rminmax/gen/f32-rmin-scalar-u4-acc4.c", |
| "src/f32-rminmax/gen/f32-rminmax-scalar-u1.c", |
| "src/f32-rminmax/gen/f32-rminmax-scalar-u2-acc2.c", |
| "src/f32-rminmax/gen/f32-rminmax-scalar-u3-acc3.c", |
| "src/f32-rminmax/gen/f32-rminmax-scalar-u4-acc2.c", |
| "src/f32-rminmax/gen/f32-rminmax-scalar-u4-acc4.c", |
| "src/f32-rsum/gen/f32-rsum-scalar-u1.c", |
| "src/f32-rsum/gen/f32-rsum-scalar-u2-acc2.c", |
| "src/f32-rsum/gen/f32-rsum-scalar-u3-acc3.c", |
| "src/f32-rsum/gen/f32-rsum-scalar-u4-acc2.c", |
| "src/f32-rsum/gen/f32-rsum-scalar-u4-acc4.c", |
| "src/f32-spmm/gen/f32-spmm-1x1-minmax-scalar-pipelined.c", |
| "src/f32-spmm/gen/f32-spmm-1x1-minmax-scalar.c", |
| "src/f32-spmm/gen/f32-spmm-2x1-minmax-scalar-pipelined.c", |
| "src/f32-spmm/gen/f32-spmm-2x1-minmax-scalar.c", |
| "src/f32-spmm/gen/f32-spmm-4x1-minmax-scalar-pipelined.c", |
| "src/f32-spmm/gen/f32-spmm-4x1-minmax-scalar.c", |
| "src/f32-spmm/gen/f32-spmm-8x1-minmax-scalar-pipelined.c", |
| "src/f32-spmm/gen/f32-spmm-8x1-minmax-scalar.c", |
| "src/f32-spmm/gen/f32-spmm-8x2-minmax-scalar.c", |
| "src/f32-spmm/gen/f32-spmm-8x4-minmax-scalar.c", |
| "src/f32-vbinary/gen/f32-vadd-minmax-scalar-u1.c", |
| "src/f32-vbinary/gen/f32-vadd-minmax-scalar-u2.c", |
| "src/f32-vbinary/gen/f32-vadd-minmax-scalar-u4.c", |
| "src/f32-vbinary/gen/f32-vadd-minmax-scalar-u8.c", |
| "src/f32-vbinary/gen/f32-vadd-relu-scalar-u1.c", |
| "src/f32-vbinary/gen/f32-vadd-relu-scalar-u2.c", |
| "src/f32-vbinary/gen/f32-vadd-relu-scalar-u4.c", |
| "src/f32-vbinary/gen/f32-vadd-relu-scalar-u8.c", |
| "src/f32-vbinary/gen/f32-vadd-scalar-u1.c", |
| "src/f32-vbinary/gen/f32-vadd-scalar-u2.c", |
| "src/f32-vbinary/gen/f32-vadd-scalar-u4.c", |
| "src/f32-vbinary/gen/f32-vadd-scalar-u8.c", |
| "src/f32-vbinary/gen/f32-vaddc-minmax-scalar-u1.c", |
| "src/f32-vbinary/gen/f32-vaddc-minmax-scalar-u2.c", |
| "src/f32-vbinary/gen/f32-vaddc-minmax-scalar-u4.c", |
| "src/f32-vbinary/gen/f32-vaddc-minmax-scalar-u8.c", |
| "src/f32-vbinary/gen/f32-vaddc-relu-scalar-u1.c", |
| "src/f32-vbinary/gen/f32-vaddc-relu-scalar-u2.c", |
| "src/f32-vbinary/gen/f32-vaddc-relu-scalar-u4.c", |
| "src/f32-vbinary/gen/f32-vaddc-relu-scalar-u8.c", |
| "src/f32-vbinary/gen/f32-vaddc-scalar-u1.c", |
| "src/f32-vbinary/gen/f32-vaddc-scalar-u2.c", |
| "src/f32-vbinary/gen/f32-vaddc-scalar-u4.c", |
| "src/f32-vbinary/gen/f32-vaddc-scalar-u8.c", |
| "src/f32-vbinary/gen/f32-vdiv-minmax-scalar-u1.c", |
| "src/f32-vbinary/gen/f32-vdiv-minmax-scalar-u2.c", |
| "src/f32-vbinary/gen/f32-vdiv-minmax-scalar-u4.c", |
| "src/f32-vbinary/gen/f32-vdiv-minmax-scalar-u8.c", |
| "src/f32-vbinary/gen/f32-vdiv-relu-scalar-u1.c", |
| "src/f32-vbinary/gen/f32-vdiv-relu-scalar-u2.c", |
| "src/f32-vbinary/gen/f32-vdiv-relu-scalar-u4.c", |
| "src/f32-vbinary/gen/f32-vdiv-relu-scalar-u8.c", |
| "src/f32-vbinary/gen/f32-vdiv-scalar-u1.c", |
| "src/f32-vbinary/gen/f32-vdiv-scalar-u2.c", |
| "src/f32-vbinary/gen/f32-vdiv-scalar-u4.c", |
| "src/f32-vbinary/gen/f32-vdiv-scalar-u8.c", |
| "src/f32-vbinary/gen/f32-vdivc-minmax-scalar-u1.c", |
| "src/f32-vbinary/gen/f32-vdivc-minmax-scalar-u2.c", |
| "src/f32-vbinary/gen/f32-vdivc-minmax-scalar-u4.c", |
| "src/f32-vbinary/gen/f32-vdivc-minmax-scalar-u8.c", |
| "src/f32-vbinary/gen/f32-vdivc-relu-scalar-u1.c", |
| "src/f32-vbinary/gen/f32-vdivc-relu-scalar-u2.c", |
| "src/f32-vbinary/gen/f32-vdivc-relu-scalar-u4.c", |
| "src/f32-vbinary/gen/f32-vdivc-relu-scalar-u8.c", |
| "src/f32-vbinary/gen/f32-vdivc-scalar-u1.c", |
| "src/f32-vbinary/gen/f32-vdivc-scalar-u2.c", |
| "src/f32-vbinary/gen/f32-vdivc-scalar-u4.c", |
| "src/f32-vbinary/gen/f32-vdivc-scalar-u8.c", |
| "src/f32-vbinary/gen/f32-vmax-scalar-u1.c", |
| "src/f32-vbinary/gen/f32-vmax-scalar-u2.c", |
| "src/f32-vbinary/gen/f32-vmax-scalar-u4.c", |
| "src/f32-vbinary/gen/f32-vmax-scalar-u8.c", |
| "src/f32-vbinary/gen/f32-vmaxc-scalar-u1.c", |
| "src/f32-vbinary/gen/f32-vmaxc-scalar-u2.c", |
| "src/f32-vbinary/gen/f32-vmaxc-scalar-u4.c", |
| "src/f32-vbinary/gen/f32-vmaxc-scalar-u8.c", |
| "src/f32-vbinary/gen/f32-vmin-scalar-u1.c", |
| "src/f32-vbinary/gen/f32-vmin-scalar-u2.c", |
| "src/f32-vbinary/gen/f32-vmin-scalar-u4.c", |
| "src/f32-vbinary/gen/f32-vmin-scalar-u8.c", |
| "src/f32-vbinary/gen/f32-vminc-scalar-u1.c", |
| "src/f32-vbinary/gen/f32-vminc-scalar-u2.c", |
| "src/f32-vbinary/gen/f32-vminc-scalar-u4.c", |
| "src/f32-vbinary/gen/f32-vminc-scalar-u8.c", |
| "src/f32-vbinary/gen/f32-vmul-minmax-scalar-u1.c", |
| "src/f32-vbinary/gen/f32-vmul-minmax-scalar-u2.c", |
| "src/f32-vbinary/gen/f32-vmul-minmax-scalar-u4.c", |
| "src/f32-vbinary/gen/f32-vmul-minmax-scalar-u8.c", |
| "src/f32-vbinary/gen/f32-vmul-relu-scalar-u1.c", |
| "src/f32-vbinary/gen/f32-vmul-relu-scalar-u2.c", |
| "src/f32-vbinary/gen/f32-vmul-relu-scalar-u4.c", |
| "src/f32-vbinary/gen/f32-vmul-relu-scalar-u8.c", |
| "src/f32-vbinary/gen/f32-vmul-scalar-u1.c", |
| "src/f32-vbinary/gen/f32-vmul-scalar-u2.c", |
| "src/f32-vbinary/gen/f32-vmul-scalar-u4.c", |
| "src/f32-vbinary/gen/f32-vmul-scalar-u8.c", |
| "src/f32-vbinary/gen/f32-vmulc-minmax-scalar-u1.c", |
| "src/f32-vbinary/gen/f32-vmulc-minmax-scalar-u2.c", |
| "src/f32-vbinary/gen/f32-vmulc-minmax-scalar-u4.c", |
| "src/f32-vbinary/gen/f32-vmulc-minmax-scalar-u8.c", |
| "src/f32-vbinary/gen/f32-vmulc-relu-scalar-u1.c", |
| "src/f32-vbinary/gen/f32-vmulc-relu-scalar-u2.c", |
| "src/f32-vbinary/gen/f32-vmulc-relu-scalar-u4.c", |
| "src/f32-vbinary/gen/f32-vmulc-relu-scalar-u8.c", |
| "src/f32-vbinary/gen/f32-vmulc-scalar-u1.c", |
| "src/f32-vbinary/gen/f32-vmulc-scalar-u2.c", |
| "src/f32-vbinary/gen/f32-vmulc-scalar-u4.c", |
| "src/f32-vbinary/gen/f32-vmulc-scalar-u8.c", |
| "src/f32-vbinary/gen/f32-vrdivc-minmax-scalar-u1.c", |
| "src/f32-vbinary/gen/f32-vrdivc-minmax-scalar-u2.c", |
| "src/f32-vbinary/gen/f32-vrdivc-minmax-scalar-u4.c", |
| "src/f32-vbinary/gen/f32-vrdivc-minmax-scalar-u8.c", |
| "src/f32-vbinary/gen/f32-vrdivc-relu-scalar-u1.c", |
| "src/f32-vbinary/gen/f32-vrdivc-relu-scalar-u2.c", |
| "src/f32-vbinary/gen/f32-vrdivc-relu-scalar-u4.c", |
| "src/f32-vbinary/gen/f32-vrdivc-relu-scalar-u8.c", |
| "src/f32-vbinary/gen/f32-vrdivc-scalar-u1.c", |
| "src/f32-vbinary/gen/f32-vrdivc-scalar-u2.c", |
| "src/f32-vbinary/gen/f32-vrdivc-scalar-u4.c", |
| "src/f32-vbinary/gen/f32-vrdivc-scalar-u8.c", |
| "src/f32-vbinary/gen/f32-vrsubc-minmax-scalar-u1.c", |
| "src/f32-vbinary/gen/f32-vrsubc-minmax-scalar-u2.c", |
| "src/f32-vbinary/gen/f32-vrsubc-minmax-scalar-u4.c", |
| "src/f32-vbinary/gen/f32-vrsubc-minmax-scalar-u8.c", |
| "src/f32-vbinary/gen/f32-vrsubc-relu-scalar-u1.c", |
| "src/f32-vbinary/gen/f32-vrsubc-relu-scalar-u2.c", |
| "src/f32-vbinary/gen/f32-vrsubc-relu-scalar-u4.c", |
| "src/f32-vbinary/gen/f32-vrsubc-relu-scalar-u8.c", |
| "src/f32-vbinary/gen/f32-vrsubc-scalar-u1.c", |
| "src/f32-vbinary/gen/f32-vrsubc-scalar-u2.c", |
| "src/f32-vbinary/gen/f32-vrsubc-scalar-u4.c", |
| "src/f32-vbinary/gen/f32-vrsubc-scalar-u8.c", |
| "src/f32-vbinary/gen/f32-vsqrdiff-scalar-u1.c", |
| "src/f32-vbinary/gen/f32-vsqrdiff-scalar-u2.c", |
| "src/f32-vbinary/gen/f32-vsqrdiff-scalar-u4.c", |
| "src/f32-vbinary/gen/f32-vsqrdiff-scalar-u8.c", |
| "src/f32-vbinary/gen/f32-vsqrdiffc-scalar-u1.c", |
| "src/f32-vbinary/gen/f32-vsqrdiffc-scalar-u2.c", |
| "src/f32-vbinary/gen/f32-vsqrdiffc-scalar-u4.c", |
| "src/f32-vbinary/gen/f32-vsqrdiffc-scalar-u8.c", |
| "src/f32-vbinary/gen/f32-vsub-minmax-scalar-u1.c", |
| "src/f32-vbinary/gen/f32-vsub-minmax-scalar-u2.c", |
| "src/f32-vbinary/gen/f32-vsub-minmax-scalar-u4.c", |
| "src/f32-vbinary/gen/f32-vsub-minmax-scalar-u8.c", |
| "src/f32-vbinary/gen/f32-vsub-relu-scalar-u1.c", |
| "src/f32-vbinary/gen/f32-vsub-relu-scalar-u2.c", |
| "src/f32-vbinary/gen/f32-vsub-relu-scalar-u4.c", |
| "src/f32-vbinary/gen/f32-vsub-relu-scalar-u8.c", |
| "src/f32-vbinary/gen/f32-vsub-scalar-u1.c", |
| "src/f32-vbinary/gen/f32-vsub-scalar-u2.c", |
| "src/f32-vbinary/gen/f32-vsub-scalar-u4.c", |
| "src/f32-vbinary/gen/f32-vsub-scalar-u8.c", |
| "src/f32-vbinary/gen/f32-vsubc-minmax-scalar-u1.c", |
| "src/f32-vbinary/gen/f32-vsubc-minmax-scalar-u2.c", |
| "src/f32-vbinary/gen/f32-vsubc-minmax-scalar-u4.c", |
| "src/f32-vbinary/gen/f32-vsubc-minmax-scalar-u8.c", |
| "src/f32-vbinary/gen/f32-vsubc-relu-scalar-u1.c", |
| "src/f32-vbinary/gen/f32-vsubc-relu-scalar-u2.c", |
| "src/f32-vbinary/gen/f32-vsubc-relu-scalar-u4.c", |
| "src/f32-vbinary/gen/f32-vsubc-relu-scalar-u8.c", |
| "src/f32-vbinary/gen/f32-vsubc-scalar-u1.c", |
| "src/f32-vbinary/gen/f32-vsubc-scalar-u2.c", |
| "src/f32-vbinary/gen/f32-vsubc-scalar-u4.c", |
| "src/f32-vbinary/gen/f32-vsubc-scalar-u8.c", |
| "src/f32-vclamp/gen/f32-vclamp-scalar-u1.c", |
| "src/f32-vclamp/gen/f32-vclamp-scalar-u2.c", |
| "src/f32-vclamp/gen/f32-vclamp-scalar-u4.c", |
| "src/f32-vcmul/gen/f32-vcmul-scalar-u1.c", |
| "src/f32-vcmul/gen/f32-vcmul-scalar-u2.c", |
| "src/f32-vcmul/gen/f32-vcmul-scalar-u4.c", |
| "src/f32-vcmul/gen/f32-vcmul-scalar-u8.c", |
| "src/f32-velu/gen/f32-velu-scalar-rr2-lut16-p3-u1.c", |
| "src/f32-velu/gen/f32-velu-scalar-rr2-lut16-p3-u2.c", |
| "src/f32-velu/gen/f32-velu-scalar-rr2-lut16-p3-u3.c", |
| "src/f32-velu/gen/f32-velu-scalar-rr2-lut16-p3-u4.c", |
| "src/f32-velu/gen/f32-velu-scalar-rr2-lut16-p3-u5.c", |
| "src/f32-velu/gen/f32-velu-scalar-rr2-lut16-p3-u6.c", |
| "src/f32-velu/gen/f32-velu-scalar-rr2-p6-u1.c", |
| "src/f32-velu/gen/f32-velu-scalar-rr2-p6-u2.c", |
| "src/f32-velu/gen/f32-velu-scalar-rr2-p6-u3.c", |
| "src/f32-velu/gen/f32-velu-scalar-rr2-p6-u4.c", |
| "src/f32-velu/gen/f32-velu-scalar-rr2-p6-u5.c", |
| "src/f32-velu/gen/f32-velu-scalar-rr2-p6-u6.c", |
| "src/f32-vhswish/gen/f32-vhswish-scalar-u1.c", |
| "src/f32-vhswish/gen/f32-vhswish-scalar-u2.c", |
| "src/f32-vhswish/gen/f32-vhswish-scalar-u4.c", |
| "src/f32-vlrelu/gen/f32-vlrelu-scalar-u1.c", |
| "src/f32-vlrelu/gen/f32-vlrelu-scalar-u2.c", |
| "src/f32-vlrelu/gen/f32-vlrelu-scalar-u4.c", |
| "src/f32-vmulcaddc/gen/f32-vmulcaddc-c1-minmax-scalar-2x.c", |
| "src/f32-vmulcaddc/gen/f32-vmulcaddc-c2-minmax-scalar-2x.c", |
| "src/f32-vmulcaddc/gen/f32-vmulcaddc-c4-minmax-scalar-2x.c", |
| "src/f32-vrelu/gen/f32-vrelu-scalar-u1.c", |
| "src/f32-vrelu/gen/f32-vrelu-scalar-u2.c", |
| "src/f32-vrelu/gen/f32-vrelu-scalar-u4.c", |
| "src/f32-vrelu/gen/f32-vrelu-scalar-u8.c", |
| "src/f32-vrnd/gen/f32-vrndd-scalar-libm-u1.c", |
| "src/f32-vrnd/gen/f32-vrndd-scalar-libm-u2.c", |
| "src/f32-vrnd/gen/f32-vrndd-scalar-libm-u4.c", |
| "src/f32-vrnd/gen/f32-vrndne-scalar-libm-u1.c", |
| "src/f32-vrnd/gen/f32-vrndne-scalar-libm-u2.c", |
| "src/f32-vrnd/gen/f32-vrndne-scalar-libm-u4.c", |
| "src/f32-vrnd/gen/f32-vrndu-scalar-libm-u1.c", |
| "src/f32-vrnd/gen/f32-vrndu-scalar-libm-u2.c", |
| "src/f32-vrnd/gen/f32-vrndu-scalar-libm-u4.c", |
| "src/f32-vrnd/gen/f32-vrndz-scalar-libm-u1.c", |
| "src/f32-vrnd/gen/f32-vrndz-scalar-libm-u2.c", |
| "src/f32-vrnd/gen/f32-vrndz-scalar-libm-u4.c", |
| "src/f32-vsigmoid/gen/f32-vsigmoid-scalar-rr2-lut64-p2-div-u1.c", |
| "src/f32-vsigmoid/gen/f32-vsigmoid-scalar-rr2-lut64-p2-div-u2.c", |
| "src/f32-vsigmoid/gen/f32-vsigmoid-scalar-rr2-lut64-p2-div-u4.c", |
| "src/f32-vsigmoid/gen/f32-vsigmoid-scalar-rr2-lut2048-p1-div-u1.c", |
| "src/f32-vsigmoid/gen/f32-vsigmoid-scalar-rr2-lut2048-p1-div-u2.c", |
| "src/f32-vsigmoid/gen/f32-vsigmoid-scalar-rr2-lut2048-p1-div-u4.c", |
| "src/f32-vsigmoid/gen/f32-vsigmoid-scalar-rr2-p5-div-u1.c", |
| "src/f32-vsigmoid/gen/f32-vsigmoid-scalar-rr2-p5-div-u2.c", |
| "src/f32-vsigmoid/gen/f32-vsigmoid-scalar-rr2-p5-div-u4.c", |
| "src/f32-vsqrt/gen/f32-vsqrt-scalar-sqrt-u1.c", |
| "src/f32-vsqrt/gen/f32-vsqrt-scalar-sqrt-u2.c", |
| "src/f32-vsqrt/gen/f32-vsqrt-scalar-sqrt-u4.c", |
| "src/f32-vtanh/gen/f32-vtanh-scalar-expm1minus-rr1-lut8-p4h3ts-div-u1.c", |
| "src/f32-vtanh/gen/f32-vtanh-scalar-expm1minus-rr1-lut8-p4h3ts-div-u2.c", |
| "src/f32-vtanh/gen/f32-vtanh-scalar-expm1minus-rr1-lut8-p4h3ts-div-u4.c", |
| "src/f32-vtanh/gen/f32-vtanh-scalar-expm1minus-rr1-p6h5ts-div-u1.c", |
| "src/f32-vtanh/gen/f32-vtanh-scalar-expm1minus-rr1-p6h5ts-div-u2.c", |
| "src/f32-vtanh/gen/f32-vtanh-scalar-expm1minus-rr1-p6h5ts-div-u4.c", |
| "src/f32-vunary/gen/f32-vabs-scalar-u1.c", |
| "src/f32-vunary/gen/f32-vabs-scalar-u2.c", |
| "src/f32-vunary/gen/f32-vabs-scalar-u4.c", |
| "src/f32-vunary/gen/f32-vneg-scalar-u1.c", |
| "src/f32-vunary/gen/f32-vneg-scalar-u2.c", |
| "src/f32-vunary/gen/f32-vneg-scalar-u4.c", |
| "src/f32-vunary/gen/f32-vsqr-scalar-u1.c", |
| "src/f32-vunary/gen/f32-vsqr-scalar-u2.c", |
| "src/f32-vunary/gen/f32-vsqr-scalar-u4.c", |
| "src/i16-vlshift/gen/i16-vlshift-scalar-u1.c", |
| "src/i16-vlshift/gen/i16-vlshift-scalar-u2.c", |
| "src/i16-vlshift/gen/i16-vlshift-scalar-u3.c", |
| "src/i16-vlshift/gen/i16-vlshift-scalar-u4.c", |
| "src/math/f32-expm1minus-scalar-rr2-lut4-p4.c", |
| "src/math/f32-expm1minus-scalar-rr2-lut8-p3.c", |
| "src/math/f32-expm1minus-scalar-rr2-lut8-p4.c", |
| "src/math/f32-expm1minus-scalar-rr2-lut16-p3.c", |
| "src/math/f32-expm1minus-scalar-rr2-lut16-p4.c", |
| "src/math/f32-expm1minus-scalar-rr2-p5.c", |
| "src/math/f32-expm1minus-scalar-rr2-p6.c", |
| "src/math/f32-expminus-scalar-rr2-lut64-p2.c", |
| "src/math/f32-expminus-scalar-rr2-lut2048-p1.c", |
| "src/math/f32-expminus-scalar-rr2-p5.c", |
| "src/math/f32-f16-cvt-scalar-bitcast.c", |
| "src/math/f32-f16-cvt-scalar-fabsf.c", |
| "src/math/f32-roundd-scalar-addsub.c", |
| "src/math/f32-roundd-scalar-cvt.c", |
| "src/math/f32-roundd-scalar-floor.c", |
| "src/math/f32-roundne-scalar-addsub.c", |
| "src/math/f32-roundne-scalar-nearbyint.c", |
| "src/math/f32-roundne-scalar-rint.c", |
| "src/math/f32-roundu-scalar-addsub.c", |
| "src/math/f32-roundu-scalar-ceil.c", |
| "src/math/f32-roundu-scalar-cvt.c", |
| "src/math/f32-roundz-scalar-addsub.c", |
| "src/math/f32-roundz-scalar-cvt.c", |
| "src/math/f32-roundz-scalar-trunc.c", |
| "src/math/f32-sigmoid-scalar-rr2-lut64-p2-div.c", |
| "src/math/f32-sigmoid-scalar-rr2-lut2048-p1-div.c", |
| "src/math/f32-sigmoid-scalar-rr2-p5-div.c", |
| "src/math/gen/f32-tanh-scalar-expm1minus-rr1-lut4-p4h2ts-div.c", |
| "src/math/gen/f32-tanh-scalar-expm1minus-rr1-lut4-p4h2ts-rcp.c", |
| "src/math/gen/f32-tanh-scalar-expm1minus-rr1-lut4-p4h3ps-div.c", |
| "src/math/gen/f32-tanh-scalar-expm1minus-rr1-lut4-p4h3ts-div.c", |
| "src/math/gen/f32-tanh-scalar-expm1minus-rr1-lut8-p3h1ts-div.c", |
| "src/math/gen/f32-tanh-scalar-expm1minus-rr1-lut8-p4h2ts-div.c", |
| "src/math/gen/f32-tanh-scalar-expm1minus-rr1-lut8-p4h2ts-rcp.c", |
| "src/math/gen/f32-tanh-scalar-expm1minus-rr1-lut8-p4h3ps-div.c", |
| "src/math/gen/f32-tanh-scalar-expm1minus-rr1-lut8-p4h3ps-rcp.c", |
| "src/math/gen/f32-tanh-scalar-expm1minus-rr1-lut8-p4h3ts-div.c", |
| "src/math/gen/f32-tanh-scalar-expm1minus-rr1-lut8-p4h3ts-rcp.c", |
| "src/math/gen/f32-tanh-scalar-expm1minus-rr1-lut16-p3h1ts-div.c", |
| "src/math/gen/f32-tanh-scalar-expm1minus-rr1-lut16-p4h2ts-div.c", |
| "src/math/gen/f32-tanh-scalar-expm1minus-rr1-lut16-p4h2ts-rcp.c", |
| "src/math/gen/f32-tanh-scalar-expm1minus-rr1-lut16-p4h3ps-div.c", |
| "src/math/gen/f32-tanh-scalar-expm1minus-rr1-lut16-p4h3ts-div.c", |
| "src/math/gen/f32-tanh-scalar-expm1minus-rr1-lut32-p3h1ts-div.c", |
| "src/math/gen/f32-tanh-scalar-expm1minus-rr1-lut64-p3h1ts-div.c", |
| "src/math/gen/f32-tanh-scalar-expm1minus-rr1-p6h4ts-div.c", |
| "src/math/gen/f32-tanh-scalar-expm1minus-rr1-p6h5ps-div.c", |
| "src/math/gen/f32-tanh-scalar-expm1minus-rr1-p6h5ps-rcp.c", |
| "src/math/gen/f32-tanh-scalar-expm1minus-rr1-p6h5ts-div.c", |
| "src/math/gen/f32-tanh-scalar-expm1minus-rr1-p6h5ts-rcp.c", |
| "src/math/gen/f32-tanh-scalar-expm1minus-rr2-lut4-p4h2ts-div.c", |
| "src/math/gen/f32-tanh-scalar-expm1minus-rr2-lut4-p4h3ps-div.c", |
| "src/math/gen/f32-tanh-scalar-expm1minus-rr2-lut4-p4h3ts-div.c", |
| "src/math/gen/f32-tanh-scalar-expm1minus-rr2-lut8-p3h1ts-div.c", |
| "src/math/gen/f32-tanh-scalar-expm1minus-rr2-lut8-p4h2ts-div.c", |
| "src/math/gen/f32-tanh-scalar-expm1minus-rr2-lut8-p4h2ts-rcp.c", |
| "src/math/gen/f32-tanh-scalar-expm1minus-rr2-lut8-p4h3ps-div.c", |
| "src/math/gen/f32-tanh-scalar-expm1minus-rr2-lut8-p4h3ps-rcp.c", |
| "src/math/gen/f32-tanh-scalar-expm1minus-rr2-lut8-p4h3ts-div.c", |
| "src/math/gen/f32-tanh-scalar-expm1minus-rr2-lut8-p4h3ts-rcp.c", |
| "src/math/gen/f32-tanh-scalar-expm1minus-rr2-lut16-p3h1ts-div.c", |
| "src/math/gen/f32-tanh-scalar-expm1minus-rr2-lut16-p4h2ts-div.c", |
| "src/math/gen/f32-tanh-scalar-expm1minus-rr2-lut16-p4h3ps-div.c", |
| "src/math/gen/f32-tanh-scalar-expm1minus-rr2-lut16-p4h3ts-div.c", |
| "src/math/gen/f32-tanh-scalar-expm1minus-rr2-lut32-p3h1ts-div.c", |
| "src/math/gen/f32-tanh-scalar-expm1minus-rr2-lut64-p3h1ts-div.c", |
| "src/math/gen/f32-tanh-scalar-expm1minus-rr2-p6h4ts-div.c", |
| "src/math/gen/f32-tanh-scalar-expm1minus-rr2-p6h5ps-div.c", |
| "src/math/gen/f32-tanh-scalar-expm1minus-rr2-p6h5ts-div.c", |
| "src/math/gen/f32-tanh-scalar-expm1plus-rr1-lut4-p4h2ts-div.c", |
| "src/math/gen/f32-tanh-scalar-expm1plus-rr1-lut4-p4h3ps-div.c", |
| "src/math/gen/f32-tanh-scalar-expm1plus-rr1-lut4-p4h3ts-div.c", |
| "src/math/gen/f32-tanh-scalar-expm1plus-rr1-lut8-p3h1ts-div.c", |
| "src/math/gen/f32-tanh-scalar-expm1plus-rr1-lut8-p4h2ts-div.c", |
| "src/math/gen/f32-tanh-scalar-expm1plus-rr1-lut8-p4h3ps-div.c", |
| "src/math/gen/f32-tanh-scalar-expm1plus-rr1-lut8-p4h3ts-div.c", |
| "src/math/gen/f32-tanh-scalar-expm1plus-rr1-lut16-p3h1ts-div.c", |
| "src/math/gen/f32-tanh-scalar-expm1plus-rr1-lut16-p4h2ts-div.c", |
| "src/math/gen/f32-tanh-scalar-expm1plus-rr1-lut16-p4h3ps-div.c", |
| "src/math/gen/f32-tanh-scalar-expm1plus-rr1-lut16-p4h3ts-div.c", |
| "src/math/gen/f32-tanh-scalar-expm1plus-rr1-lut32-p3h1ts-div.c", |
| "src/math/gen/f32-tanh-scalar-expm1plus-rr1-lut64-p3h1ts-div.c", |
| "src/math/gen/f32-tanh-scalar-expm1plus-rr1-p6h4ts-div.c", |
| "src/math/gen/f32-tanh-scalar-expm1plus-rr1-p6h5ps-div.c", |
| "src/math/gen/f32-tanh-scalar-expm1plus-rr1-p6h5ts-div.c", |
| "src/math/gen/f32-tanh-scalar-expm1plus-rr2-lut4-p4h2ts-div.c", |
| "src/math/gen/f32-tanh-scalar-expm1plus-rr2-lut4-p4h3ps-div.c", |
| "src/math/gen/f32-tanh-scalar-expm1plus-rr2-lut4-p4h3ts-div.c", |
| "src/math/gen/f32-tanh-scalar-expm1plus-rr2-lut8-p3h1ts-div.c", |
| "src/math/gen/f32-tanh-scalar-expm1plus-rr2-lut8-p4h2ts-div.c", |
| "src/math/gen/f32-tanh-scalar-expm1plus-rr2-lut8-p4h3ps-div.c", |
| "src/math/gen/f32-tanh-scalar-expm1plus-rr2-lut8-p4h3ts-div.c", |
| "src/math/gen/f32-tanh-scalar-expm1plus-rr2-lut16-p3h1ts-div.c", |
| "src/math/gen/f32-tanh-scalar-expm1plus-rr2-lut16-p4h2ts-div.c", |
| "src/math/gen/f32-tanh-scalar-expm1plus-rr2-lut16-p4h3ps-div.c", |
| "src/math/gen/f32-tanh-scalar-expm1plus-rr2-lut16-p4h3ts-div.c", |
| "src/math/gen/f32-tanh-scalar-expm1plus-rr2-lut32-p3h1ts-div.c", |
| "src/math/gen/f32-tanh-scalar-expm1plus-rr2-lut64-p3h1ts-div.c", |
| "src/math/gen/f32-tanh-scalar-expm1plus-rr2-p6h4ts-div.c", |
| "src/math/gen/f32-tanh-scalar-expm1plus-rr2-p6h5ps-div.c", |
| "src/math/gen/f32-tanh-scalar-expm1plus-rr2-p6h5ts-div.c", |
| "src/math/u32-sqrt-scalar-bitmanip.c", |
| "src/math/u32-sqrt-scalar-clz-binsearch.c", |
| "src/math/u32-sqrt-scalar-clz-newton.c", |
| "src/math/u32-sqrt-scalar-cvti32-sqrt-lrint.c", |
| "src/math/u32-sqrt-scalar-cvti64-sqrt-lrint.c", |
| "src/math/u32-sqrt-scalar-cvti64-sqrtf-lrintf.c", |
| "src/math/u32-sqrt-scalar-cvtu32-sqrt-lrint.c", |
| "src/math/u32-sqrt-scalar-cvtu32-sqrtf-lrintf.c", |
| "src/math/u32-sqrt-scalar-hashemian.c", |
| "src/math/u32-sqrt-scalar-tflm.c", |
| "src/math/u64-sqrt-scalar-cvtu32-sqrt-cvtsatu32f64.c", |
| "src/math/u64-sqrt-scalar-cvtu32-sqrt-llrint.c", |
| "src/math/u64-sqrt-scalar-cvtu64-sqrt-llrint.c", |
| "src/qd8-f32-qc4w-gemm/gen/qd8-f32-qc4w-gemm-1x1-minmax-scalar.c", |
| "src/qd8-f32-qc4w-gemm/gen/qd8-f32-qc4w-gemm-1x2-minmax-scalar.c", |
| "src/qd8-f32-qc4w-gemm/gen/qd8-f32-qc4w-gemm-1x4-minmax-scalar.c", |
| "src/qd8-f32-qc4w-gemm/gen/qd8-f32-qc4w-gemm-1x8-minmax-scalar.c", |
| "src/qd8-f32-qc4w-gemm/gen/qd8-f32-qc4w-gemm-2x2-minmax-scalar.c", |
| "src/qd8-f32-qc4w-gemm/gen/qd8-f32-qc4w-gemm-2x4-minmax-scalar.c", |
| "src/qd8-f32-qc4w-gemm/gen/qd8-f32-qc4w-gemm-2x8-minmax-scalar.c", |
| "src/qd8-f32-qc4w-gemm/gen/qd8-f32-qc4w-gemm-4x4-minmax-scalar.c", |
| "src/qd8-f32-qc8w-gemm/gen/qd8-f32-qc8w-gemm-1x2-minmax-scalar.c", |
| "src/qd8-f32-qc8w-gemm/gen/qd8-f32-qc8w-gemm-1x4-minmax-scalar.c", |
| "src/qd8-f32-qc8w-gemm/gen/qd8-f32-qc8w-gemm-1x8-minmax-scalar.c", |
| "src/qd8-f32-qc8w-gemm/gen/qd8-f32-qc8w-gemm-2x2-minmax-scalar.c", |
| "src/qd8-f32-qc8w-gemm/gen/qd8-f32-qc8w-gemm-2x4-minmax-scalar.c", |
| "src/qd8-f32-qc8w-gemm/gen/qd8-f32-qc8w-gemm-2x8-minmax-scalar.c", |
| "src/qd8-f32-qc8w-gemm/gen/qd8-f32-qc8w-gemm-4x4-minmax-scalar.c", |
| "src/qs8-dwconv/gen/qs8-dwconv-5f5m5l1c1s1r-minmax-fp32-scalar-fmagic.c", |
| "src/qs8-dwconv/gen/qs8-dwconv-5f5m5l1c1s1r-minmax-fp32-scalar-imagic.c", |
| "src/qs8-dwconv/gen/qs8-dwconv-5f5m5l1c1s1r-minmax-fp32-scalar-lrintf.c", |
| "src/qs8-dwconv/gen/qs8-dwconv-5f5m5l2c1s1r-minmax-fp32-scalar-fmagic.c", |
| "src/qs8-dwconv/gen/qs8-dwconv-5f5m5l2c1s1r-minmax-fp32-scalar-imagic.c", |
| "src/qs8-dwconv/gen/qs8-dwconv-5f5m5l2c1s1r-minmax-fp32-scalar-lrintf.c", |
| "src/qs8-dwconv/gen/qs8-dwconv-5f5m5l4c1s1r-minmax-fp32-scalar-fmagic.c", |
| "src/qs8-dwconv/gen/qs8-dwconv-5f5m5l4c1s1r-minmax-fp32-scalar-imagic.c", |
| "src/qs8-dwconv/gen/qs8-dwconv-5f5m5l4c1s1r-minmax-fp32-scalar-lrintf.c", |
| "src/qs8-dwconv/gen/qs8-dwconv-6f6m7l1c1s1r-minmax-fp32-scalar-fmagic.c", |
| "src/qs8-dwconv/gen/qs8-dwconv-6f6m7l1c1s1r-minmax-fp32-scalar-imagic.c", |
| "src/qs8-dwconv/gen/qs8-dwconv-6f6m7l1c1s1r-minmax-fp32-scalar-lrintf.c", |
| "src/qs8-dwconv/gen/qs8-dwconv-6f6m7l2c1s1r-minmax-fp32-scalar-fmagic.c", |
| "src/qs8-dwconv/gen/qs8-dwconv-6f6m7l2c1s1r-minmax-fp32-scalar-imagic.c", |
| "src/qs8-dwconv/gen/qs8-dwconv-6f6m7l2c1s1r-minmax-fp32-scalar-lrintf.c", |
| "src/qs8-dwconv/gen/qs8-dwconv-6f6m7l4c1s1r-minmax-fp32-scalar-fmagic.c", |
| "src/qs8-dwconv/gen/qs8-dwconv-6f6m7l4c1s1r-minmax-fp32-scalar-imagic.c", |
| "src/qs8-dwconv/gen/qs8-dwconv-6f6m7l4c1s1r-minmax-fp32-scalar-lrintf.c", |
| "src/qs8-dwconv/gen/qs8-dwconv-8f8m9l1c1s1r-minmax-fp32-scalar-fmagic.c", |
| "src/qs8-dwconv/gen/qs8-dwconv-8f8m9l1c1s1r-minmax-fp32-scalar-imagic.c", |
| "src/qs8-dwconv/gen/qs8-dwconv-8f8m9l1c1s1r-minmax-fp32-scalar-lrintf.c", |
| "src/qs8-dwconv/gen/qs8-dwconv-8f8m9l2c1s1r-minmax-fp32-scalar-fmagic.c", |
| "src/qs8-dwconv/gen/qs8-dwconv-8f8m9l2c1s1r-minmax-fp32-scalar-imagic.c", |
| "src/qs8-dwconv/gen/qs8-dwconv-8f8m9l2c1s1r-minmax-fp32-scalar-lrintf.c", |
| "src/qs8-dwconv/gen/qs8-dwconv-8f8m9l4c1s1r-minmax-fp32-scalar-fmagic.c", |
| "src/qs8-dwconv/gen/qs8-dwconv-8f8m9l4c1s1r-minmax-fp32-scalar-imagic.c", |
| "src/qs8-dwconv/gen/qs8-dwconv-8f8m9l4c1s1r-minmax-fp32-scalar-lrintf.c", |
| "src/qs8-dwconv/gen/qs8-dwconv-9p1c-minmax-fp32-scalar-fmagic.c", |
| "src/qs8-dwconv/gen/qs8-dwconv-9p1c-minmax-fp32-scalar-imagic.c", |
| "src/qs8-dwconv/gen/qs8-dwconv-9p1c-minmax-fp32-scalar-lrintf.c", |
| "src/qs8-dwconv/gen/qs8-dwconv-9p1c-minmax-rndnu-scalar.c", |
| "src/qs8-dwconv/gen/qs8-dwconv-9p2c-minmax-fp32-scalar-fmagic.c", |
| "src/qs8-dwconv/gen/qs8-dwconv-9p2c-minmax-fp32-scalar-imagic.c", |
| "src/qs8-dwconv/gen/qs8-dwconv-9p2c-minmax-fp32-scalar-lrintf.c", |
| "src/qs8-dwconv/gen/qs8-dwconv-9p2c-minmax-rndnu-scalar.c", |
| "src/qs8-dwconv/gen/qs8-dwconv-9p4c-minmax-fp32-scalar-fmagic.c", |
| "src/qs8-dwconv/gen/qs8-dwconv-9p4c-minmax-fp32-scalar-imagic.c", |
| "src/qs8-dwconv/gen/qs8-dwconv-9p4c-minmax-fp32-scalar-lrintf.c", |
| "src/qs8-dwconv/gen/qs8-dwconv-9p4c-minmax-rndnu-scalar.c", |
| "src/qs8-dwconv/gen/qs8-dwconv-25p1c-minmax-fp32-scalar-fmagic.c", |
| "src/qs8-dwconv/gen/qs8-dwconv-25p1c-minmax-fp32-scalar-imagic.c", |
| "src/qs8-dwconv/gen/qs8-dwconv-25p1c-minmax-fp32-scalar-lrintf.c", |
| "src/qs8-dwconv/gen/qs8-dwconv-25p2c-minmax-fp32-scalar-fmagic.c", |
| "src/qs8-dwconv/gen/qs8-dwconv-25p2c-minmax-fp32-scalar-imagic.c", |
| "src/qs8-dwconv/gen/qs8-dwconv-25p2c-minmax-fp32-scalar-lrintf.c", |
| "src/qs8-dwconv/gen/qs8-dwconv-25p4c-minmax-fp32-scalar-fmagic.c", |
| "src/qs8-dwconv/gen/qs8-dwconv-25p4c-minmax-fp32-scalar-imagic.c", |
| "src/qs8-dwconv/gen/qs8-dwconv-25p4c-minmax-fp32-scalar-lrintf.c", |
| "src/qs8-f32-vcvt/gen/qs8-f32-vcvt-scalar-u1.c", |
| "src/qs8-f32-vcvt/gen/qs8-f32-vcvt-scalar-u2.c", |
| "src/qs8-f32-vcvt/gen/qs8-f32-vcvt-scalar-u3.c", |
| "src/qs8-f32-vcvt/gen/qs8-f32-vcvt-scalar-u4.c", |
| "src/qs8-gavgpool/gen/qs8-gavgpool-7p7x-minmax-fp32-scalar-fmagic-c1.c", |
| "src/qs8-gavgpool/gen/qs8-gavgpool-7p7x-minmax-fp32-scalar-fmagic-c2.c", |
| "src/qs8-gavgpool/gen/qs8-gavgpool-7p7x-minmax-fp32-scalar-fmagic-c4.c", |
| "src/qs8-gavgpool/gen/qs8-gavgpool-7p7x-minmax-fp32-scalar-imagic-c1.c", |
| "src/qs8-gavgpool/gen/qs8-gavgpool-7p7x-minmax-fp32-scalar-imagic-c2.c", |
| "src/qs8-gavgpool/gen/qs8-gavgpool-7p7x-minmax-fp32-scalar-imagic-c4.c", |
| "src/qs8-gavgpool/gen/qs8-gavgpool-7p7x-minmax-fp32-scalar-lrintf-c1.c", |
| "src/qs8-gavgpool/gen/qs8-gavgpool-7p7x-minmax-fp32-scalar-lrintf-c2.c", |
| "src/qs8-gavgpool/gen/qs8-gavgpool-7p7x-minmax-fp32-scalar-lrintf-c4.c", |
| "src/qs8-gavgpool/gen/qs8-gavgpool-7x-minmax-fp32-scalar-fmagic-c1.c", |
| "src/qs8-gavgpool/gen/qs8-gavgpool-7x-minmax-fp32-scalar-fmagic-c2.c", |
| "src/qs8-gavgpool/gen/qs8-gavgpool-7x-minmax-fp32-scalar-fmagic-c4.c", |
| "src/qs8-gavgpool/gen/qs8-gavgpool-7x-minmax-fp32-scalar-imagic-c1.c", |
| "src/qs8-gavgpool/gen/qs8-gavgpool-7x-minmax-fp32-scalar-imagic-c2.c", |
| "src/qs8-gavgpool/gen/qs8-gavgpool-7x-minmax-fp32-scalar-imagic-c4.c", |
| "src/qs8-gavgpool/gen/qs8-gavgpool-7x-minmax-fp32-scalar-lrintf-c1.c", |
| "src/qs8-gavgpool/gen/qs8-gavgpool-7x-minmax-fp32-scalar-lrintf-c2.c", |
| "src/qs8-gavgpool/gen/qs8-gavgpool-7x-minmax-fp32-scalar-lrintf-c4.c", |
| "src/qs8-gemm/gen/qs8-gemm-1x2-minmax-fp32-scalar-fmagic.c", |
| "src/qs8-gemm/gen/qs8-gemm-1x2-minmax-fp32-scalar-imagic.c", |
| "src/qs8-gemm/gen/qs8-gemm-1x2-minmax-fp32-scalar-lrintf.c", |
| "src/qs8-gemm/gen/qs8-gemm-1x2-minmax-rndnu-scalar.c", |
| "src/qs8-gemm/gen/qs8-gemm-1x4-minmax-fp32-scalar-fmagic.c", |
| "src/qs8-gemm/gen/qs8-gemm-1x4-minmax-fp32-scalar-imagic.c", |
| "src/qs8-gemm/gen/qs8-gemm-1x4-minmax-fp32-scalar-lrintf.c", |
| "src/qs8-gemm/gen/qs8-gemm-1x4-minmax-rndnu-scalar.c", |
| "src/qs8-gemm/gen/qs8-gemm-2x2-minmax-fp32-scalar-fmagic.c", |
| "src/qs8-gemm/gen/qs8-gemm-2x2-minmax-fp32-scalar-imagic.c", |
| "src/qs8-gemm/gen/qs8-gemm-2x2-minmax-fp32-scalar-lrintf.c", |
| "src/qs8-gemm/gen/qs8-gemm-2x2-minmax-rndnu-scalar.c", |
| "src/qs8-gemm/gen/qs8-gemm-2x4-minmax-fp32-scalar-fmagic.c", |
| "src/qs8-gemm/gen/qs8-gemm-2x4-minmax-fp32-scalar-imagic.c", |
| "src/qs8-gemm/gen/qs8-gemm-2x4-minmax-fp32-scalar-lrintf.c", |
| "src/qs8-gemm/gen/qs8-gemm-2x4-minmax-rndnu-scalar.c", |
| "src/qs8-gemm/gen/qs8-gemm-3x2-minmax-fp32-scalar-fmagic.c", |
| "src/qs8-gemm/gen/qs8-gemm-3x2-minmax-fp32-scalar-imagic.c", |
| "src/qs8-gemm/gen/qs8-gemm-3x2-minmax-fp32-scalar-lrintf.c", |
| "src/qs8-gemm/gen/qs8-gemm-3x2-minmax-rndnu-scalar.c", |
| "src/qs8-gemm/gen/qs8-gemm-3x4-minmax-fp32-scalar-fmagic.c", |
| "src/qs8-gemm/gen/qs8-gemm-3x4-minmax-fp32-scalar-imagic.c", |
| "src/qs8-gemm/gen/qs8-gemm-3x4-minmax-fp32-scalar-lrintf.c", |
| "src/qs8-gemm/gen/qs8-gemm-3x4-minmax-rndnu-scalar.c", |
| "src/qs8-gemm/gen/qs8-gemm-4x2-minmax-fp32-scalar-fmagic.c", |
| "src/qs8-gemm/gen/qs8-gemm-4x2-minmax-fp32-scalar-imagic.c", |
| "src/qs8-gemm/gen/qs8-gemm-4x2-minmax-fp32-scalar-lrintf.c", |
| "src/qs8-gemm/gen/qs8-gemm-4x2-minmax-rndnu-scalar.c", |
| "src/qs8-gemm/gen/qs8-gemm-4x4-minmax-fp32-scalar-fmagic.c", |
| "src/qs8-gemm/gen/qs8-gemm-4x4-minmax-fp32-scalar-imagic.c", |
| "src/qs8-gemm/gen/qs8-gemm-4x4-minmax-fp32-scalar-lrintf.c", |
| "src/qs8-gemm/gen/qs8-gemm-4x4-minmax-rndnu-scalar.c", |
| "src/qs8-igemm/gen/qs8-igemm-1x2-minmax-fp32-scalar-fmagic.c", |
| "src/qs8-igemm/gen/qs8-igemm-1x2-minmax-fp32-scalar-imagic.c", |
| "src/qs8-igemm/gen/qs8-igemm-1x2-minmax-fp32-scalar-lrintf.c", |
| "src/qs8-igemm/gen/qs8-igemm-1x2-minmax-rndnu-scalar.c", |
| "src/qs8-igemm/gen/qs8-igemm-1x4-minmax-fp32-scalar-fmagic.c", |
| "src/qs8-igemm/gen/qs8-igemm-1x4-minmax-fp32-scalar-imagic.c", |
| "src/qs8-igemm/gen/qs8-igemm-1x4-minmax-fp32-scalar-lrintf.c", |
| "src/qs8-igemm/gen/qs8-igemm-1x4-minmax-rndnu-scalar.c", |
| "src/qs8-igemm/gen/qs8-igemm-2x2-minmax-fp32-scalar-fmagic.c", |
| "src/qs8-igemm/gen/qs8-igemm-2x2-minmax-fp32-scalar-imagic.c", |
| "src/qs8-igemm/gen/qs8-igemm-2x2-minmax-fp32-scalar-lrintf.c", |
| "src/qs8-igemm/gen/qs8-igemm-2x2-minmax-rndnu-scalar.c", |
| "src/qs8-igemm/gen/qs8-igemm-2x4-minmax-fp32-scalar-fmagic.c", |
| "src/qs8-igemm/gen/qs8-igemm-2x4-minmax-fp32-scalar-imagic.c", |
| "src/qs8-igemm/gen/qs8-igemm-2x4-minmax-fp32-scalar-lrintf.c", |
| "src/qs8-igemm/gen/qs8-igemm-2x4-minmax-rndnu-scalar.c", |
| "src/qs8-igemm/gen/qs8-igemm-3x2-minmax-fp32-scalar-fmagic.c", |
| "src/qs8-igemm/gen/qs8-igemm-3x2-minmax-fp32-scalar-imagic.c", |
| "src/qs8-igemm/gen/qs8-igemm-3x2-minmax-fp32-scalar-lrintf.c", |
| "src/qs8-igemm/gen/qs8-igemm-3x2-minmax-rndnu-scalar.c", |
| "src/qs8-igemm/gen/qs8-igemm-3x4-minmax-fp32-scalar-fmagic.c", |
| "src/qs8-igemm/gen/qs8-igemm-3x4-minmax-fp32-scalar-imagic.c", |
| "src/qs8-igemm/gen/qs8-igemm-3x4-minmax-fp32-scalar-lrintf.c", |
| "src/qs8-igemm/gen/qs8-igemm-3x4-minmax-rndnu-scalar.c", |
| "src/qs8-igemm/gen/qs8-igemm-4x2-minmax-fp32-scalar-fmagic.c", |
| "src/qs8-igemm/gen/qs8-igemm-4x2-minmax-fp32-scalar-imagic.c", |
| "src/qs8-igemm/gen/qs8-igemm-4x2-minmax-fp32-scalar-lrintf.c", |
| "src/qs8-igemm/gen/qs8-igemm-4x2-minmax-rndnu-scalar.c", |
| "src/qs8-igemm/gen/qs8-igemm-4x4-minmax-fp32-scalar-fmagic.c", |
| "src/qs8-igemm/gen/qs8-igemm-4x4-minmax-fp32-scalar-imagic.c", |
| "src/qs8-igemm/gen/qs8-igemm-4x4-minmax-fp32-scalar-lrintf.c", |
| "src/qs8-igemm/gen/qs8-igemm-4x4-minmax-rndnu-scalar.c", |
| "src/qs8-qc8w-dwconv/gen/qs8-qc8w-dwconv-3p1c-minmax-fp32-scalar-fmagic.c", |
| "src/qs8-qc8w-dwconv/gen/qs8-qc8w-dwconv-3p2c-minmax-fp32-scalar-imagic.c", |
| "src/qs8-qc8w-dwconv/gen/qs8-qc8w-dwconv-3p2c-minmax-fp32-scalar-lrintf.c", |
| "src/qs8-qc8w-dwconv/gen/qs8-qc8w-dwconv-4p2c-minmax-fp32-scalar-imagic.c", |
| "src/qs8-qc8w-dwconv/gen/qs8-qc8w-dwconv-5f5m5l1c1s1r-minmax-fp32-scalar-fmagic.c", |
| "src/qs8-qc8w-dwconv/gen/qs8-qc8w-dwconv-5f5m5l1c1s1r-minmax-fp32-scalar-imagic.c", |
| "src/qs8-qc8w-dwconv/gen/qs8-qc8w-dwconv-5f5m5l1c1s1r-minmax-fp32-scalar-lrintf.c", |
| "src/qs8-qc8w-dwconv/gen/qs8-qc8w-dwconv-5f5m5l2c1s1r-minmax-fp32-scalar-fmagic.c", |
| "src/qs8-qc8w-dwconv/gen/qs8-qc8w-dwconv-5f5m5l2c1s1r-minmax-fp32-scalar-imagic.c", |
| "src/qs8-qc8w-dwconv/gen/qs8-qc8w-dwconv-5f5m5l2c1s1r-minmax-fp32-scalar-lrintf.c", |
| "src/qs8-qc8w-dwconv/gen/qs8-qc8w-dwconv-5f5m5l4c1s1r-minmax-fp32-scalar-fmagic.c", |
| "src/qs8-qc8w-dwconv/gen/qs8-qc8w-dwconv-5f5m5l4c1s1r-minmax-fp32-scalar-imagic.c", |
| "src/qs8-qc8w-dwconv/gen/qs8-qc8w-dwconv-5f5m5l4c1s1r-minmax-fp32-scalar-lrintf.c", |
| "src/qs8-qc8w-dwconv/gen/qs8-qc8w-dwconv-6f6m7l1c1s1r-minmax-fp32-scalar-fmagic.c", |
| "src/qs8-qc8w-dwconv/gen/qs8-qc8w-dwconv-6f6m7l1c1s1r-minmax-fp32-scalar-imagic.c", |
| "src/qs8-qc8w-dwconv/gen/qs8-qc8w-dwconv-6f6m7l1c1s1r-minmax-fp32-scalar-lrintf.c", |
| "src/qs8-qc8w-dwconv/gen/qs8-qc8w-dwconv-6f6m7l2c1s1r-minmax-fp32-scalar-fmagic.c", |
| "src/qs8-qc8w-dwconv/gen/qs8-qc8w-dwconv-6f6m7l2c1s1r-minmax-fp32-scalar-imagic.c", |
| "src/qs8-qc8w-dwconv/gen/qs8-qc8w-dwconv-6f6m7l2c1s1r-minmax-fp32-scalar-lrintf.c", |
| "src/qs8-qc8w-dwconv/gen/qs8-qc8w-dwconv-6f6m7l4c1s1r-minmax-fp32-scalar-fmagic.c", |
| "src/qs8-qc8w-dwconv/gen/qs8-qc8w-dwconv-6f6m7l4c1s1r-minmax-fp32-scalar-imagic.c", |
| "src/qs8-qc8w-dwconv/gen/qs8-qc8w-dwconv-6f6m7l4c1s1r-minmax-fp32-scalar-lrintf.c", |
| "src/qs8-qc8w-dwconv/gen/qs8-qc8w-dwconv-8f8m9l1c1s1r-minmax-fp32-scalar-fmagic.c", |
| "src/qs8-qc8w-dwconv/gen/qs8-qc8w-dwconv-8f8m9l1c1s1r-minmax-fp32-scalar-imagic.c", |
| "src/qs8-qc8w-dwconv/gen/qs8-qc8w-dwconv-8f8m9l1c1s1r-minmax-fp32-scalar-lrintf.c", |
| "src/qs8-qc8w-dwconv/gen/qs8-qc8w-dwconv-8f8m9l2c1s1r-minmax-fp32-scalar-fmagic.c", |
| "src/qs8-qc8w-dwconv/gen/qs8-qc8w-dwconv-8f8m9l2c1s1r-minmax-fp32-scalar-imagic.c", |
| "src/qs8-qc8w-dwconv/gen/qs8-qc8w-dwconv-8f8m9l2c1s1r-minmax-fp32-scalar-lrintf.c", |
| "src/qs8-qc8w-dwconv/gen/qs8-qc8w-dwconv-8f8m9l4c1s1r-minmax-fp32-scalar-fmagic.c", |
| "src/qs8-qc8w-dwconv/gen/qs8-qc8w-dwconv-8f8m9l4c1s1r-minmax-fp32-scalar-imagic.c", |
| "src/qs8-qc8w-dwconv/gen/qs8-qc8w-dwconv-8f8m9l4c1s1r-minmax-fp32-scalar-lrintf.c", |
| "src/qs8-qc8w-dwconv/gen/qs8-qc8w-dwconv-9p1c-minmax-fp32-scalar-fmagic.c", |
| "src/qs8-qc8w-dwconv/gen/qs8-qc8w-dwconv-9p1c-minmax-fp32-scalar-imagic.c", |
| "src/qs8-qc8w-dwconv/gen/qs8-qc8w-dwconv-9p1c-minmax-fp32-scalar-lrintf.c", |
| "src/qs8-qc8w-dwconv/gen/qs8-qc8w-dwconv-9p2c-minmax-fp32-scalar-fmagic.c", |
| "src/qs8-qc8w-dwconv/gen/qs8-qc8w-dwconv-9p2c-minmax-fp32-scalar-imagic.c", |
| "src/qs8-qc8w-dwconv/gen/qs8-qc8w-dwconv-9p2c-minmax-fp32-scalar-lrintf.c", |
| "src/qs8-qc8w-dwconv/gen/qs8-qc8w-dwconv-9p4c-minmax-fp32-scalar-fmagic.c", |
| "src/qs8-qc8w-dwconv/gen/qs8-qc8w-dwconv-9p4c-minmax-fp32-scalar-imagic.c", |
| "src/qs8-qc8w-dwconv/gen/qs8-qc8w-dwconv-9p4c-minmax-fp32-scalar-lrintf.c", |
| "src/qs8-qc8w-dwconv/gen/qs8-qc8w-dwconv-25p1c-minmax-fp32-scalar-fmagic.c", |
| "src/qs8-qc8w-dwconv/gen/qs8-qc8w-dwconv-25p1c-minmax-fp32-scalar-imagic.c", |
| "src/qs8-qc8w-dwconv/gen/qs8-qc8w-dwconv-25p1c-minmax-fp32-scalar-lrintf.c", |
| "src/qs8-qc8w-dwconv/gen/qs8-qc8w-dwconv-25p2c-minmax-fp32-scalar-fmagic.c", |
| "src/qs8-qc8w-dwconv/gen/qs8-qc8w-dwconv-25p2c-minmax-fp32-scalar-imagic.c", |
| "src/qs8-qc8w-dwconv/gen/qs8-qc8w-dwconv-25p2c-minmax-fp32-scalar-lrintf.c", |
| "src/qs8-qc8w-dwconv/gen/qs8-qc8w-dwconv-25p4c-minmax-fp32-scalar-fmagic.c", |
| "src/qs8-qc8w-dwconv/gen/qs8-qc8w-dwconv-25p4c-minmax-fp32-scalar-imagic.c", |
| "src/qs8-qc8w-dwconv/gen/qs8-qc8w-dwconv-25p4c-minmax-fp32-scalar-lrintf.c", |
| "src/qs8-qc8w-gemm/gen/qs8-qc8w-gemm-1x2-minmax-fp32-scalar-fmagic.c", |
| "src/qs8-qc8w-gemm/gen/qs8-qc8w-gemm-1x2-minmax-fp32-scalar-imagic.c", |
| "src/qs8-qc8w-gemm/gen/qs8-qc8w-gemm-1x2-minmax-fp32-scalar-lrintf.c", |
| "src/qs8-qc8w-gemm/gen/qs8-qc8w-gemm-1x4-minmax-fp32-scalar-fmagic.c", |
| "src/qs8-qc8w-gemm/gen/qs8-qc8w-gemm-1x4-minmax-fp32-scalar-imagic.c", |
| "src/qs8-qc8w-gemm/gen/qs8-qc8w-gemm-1x4-minmax-fp32-scalar-lrintf.c", |
| "src/qs8-qc8w-gemm/gen/qs8-qc8w-gemm-2x2-minmax-fp32-scalar-fmagic.c", |
| "src/qs8-qc8w-gemm/gen/qs8-qc8w-gemm-2x2-minmax-fp32-scalar-imagic.c", |
| "src/qs8-qc8w-gemm/gen/qs8-qc8w-gemm-2x2-minmax-fp32-scalar-lrintf.c", |
| "src/qs8-qc8w-gemm/gen/qs8-qc8w-gemm-2x4-minmax-fp32-scalar-fmagic.c", |
| "src/qs8-qc8w-gemm/gen/qs8-qc8w-gemm-2x4-minmax-fp32-scalar-imagic.c", |
| "src/qs8-qc8w-gemm/gen/qs8-qc8w-gemm-2x4-minmax-fp32-scalar-lrintf.c", |
| "src/qs8-qc8w-gemm/gen/qs8-qc8w-gemm-3x2-minmax-fp32-scalar-fmagic.c", |
| "src/qs8-qc8w-gemm/gen/qs8-qc8w-gemm-3x2-minmax-fp32-scalar-imagic.c", |
| "src/qs8-qc8w-gemm/gen/qs8-qc8w-gemm-3x2-minmax-fp32-scalar-lrintf.c", |
| "src/qs8-qc8w-gemm/gen/qs8-qc8w-gemm-3x4-minmax-fp32-scalar-fmagic.c", |
| "src/qs8-qc8w-gemm/gen/qs8-qc8w-gemm-3x4-minmax-fp32-scalar-imagic.c", |
| "src/qs8-qc8w-gemm/gen/qs8-qc8w-gemm-3x4-minmax-fp32-scalar-lrintf.c", |
| "src/qs8-qc8w-gemm/gen/qs8-qc8w-gemm-4x2-minmax-fp32-scalar-fmagic.c", |
| "src/qs8-qc8w-gemm/gen/qs8-qc8w-gemm-4x2-minmax-fp32-scalar-imagic.c", |
| "src/qs8-qc8w-gemm/gen/qs8-qc8w-gemm-4x2-minmax-fp32-scalar-lrintf.c", |
| "src/qs8-qc8w-gemm/gen/qs8-qc8w-gemm-4x4-minmax-fp32-scalar-fmagic.c", |
| "src/qs8-qc8w-gemm/gen/qs8-qc8w-gemm-4x4-minmax-fp32-scalar-imagic.c", |
| "src/qs8-qc8w-gemm/gen/qs8-qc8w-gemm-4x4-minmax-fp32-scalar-lrintf.c", |
| "src/qs8-qc8w-igemm/gen/qs8-qc8w-igemm-1x2-minmax-fp32-scalar-fmagic.c", |
| "src/qs8-qc8w-igemm/gen/qs8-qc8w-igemm-1x2-minmax-fp32-scalar-imagic.c", |
| "src/qs8-qc8w-igemm/gen/qs8-qc8w-igemm-1x2-minmax-fp32-scalar-lrintf.c", |
| "src/qs8-qc8w-igemm/gen/qs8-qc8w-igemm-1x4-minmax-fp32-scalar-fmagic.c", |
| "src/qs8-qc8w-igemm/gen/qs8-qc8w-igemm-1x4-minmax-fp32-scalar-imagic.c", |
| "src/qs8-qc8w-igemm/gen/qs8-qc8w-igemm-1x4-minmax-fp32-scalar-lrintf.c", |
| "src/qs8-qc8w-igemm/gen/qs8-qc8w-igemm-2x2-minmax-fp32-scalar-fmagic.c", |
| "src/qs8-qc8w-igemm/gen/qs8-qc8w-igemm-2x2-minmax-fp32-scalar-imagic.c", |
| "src/qs8-qc8w-igemm/gen/qs8-qc8w-igemm-2x2-minmax-fp32-scalar-lrintf.c", |
| "src/qs8-qc8w-igemm/gen/qs8-qc8w-igemm-2x4-minmax-fp32-scalar-fmagic.c", |
| "src/qs8-qc8w-igemm/gen/qs8-qc8w-igemm-2x4-minmax-fp32-scalar-imagic.c", |
| "src/qs8-qc8w-igemm/gen/qs8-qc8w-igemm-2x4-minmax-fp32-scalar-lrintf.c", |
| "src/qs8-qc8w-igemm/gen/qs8-qc8w-igemm-3x2-minmax-fp32-scalar-fmagic.c", |
| "src/qs8-qc8w-igemm/gen/qs8-qc8w-igemm-3x2-minmax-fp32-scalar-imagic.c", |
| "src/qs8-qc8w-igemm/gen/qs8-qc8w-igemm-3x2-minmax-fp32-scalar-lrintf.c", |
| "src/qs8-qc8w-igemm/gen/qs8-qc8w-igemm-3x4-minmax-fp32-scalar-fmagic.c", |
| "src/qs8-qc8w-igemm/gen/qs8-qc8w-igemm-3x4-minmax-fp32-scalar-imagic.c", |
| "src/qs8-qc8w-igemm/gen/qs8-qc8w-igemm-3x4-minmax-fp32-scalar-lrintf.c", |
| "src/qs8-qc8w-igemm/gen/qs8-qc8w-igemm-4x2-minmax-fp32-scalar-fmagic.c", |
| "src/qs8-qc8w-igemm/gen/qs8-qc8w-igemm-4x2-minmax-fp32-scalar-imagic.c", |
| "src/qs8-qc8w-igemm/gen/qs8-qc8w-igemm-4x2-minmax-fp32-scalar-lrintf.c", |
| "src/qs8-qc8w-igemm/gen/qs8-qc8w-igemm-4x4-minmax-fp32-scalar-fmagic.c", |
| "src/qs8-qc8w-igemm/gen/qs8-qc8w-igemm-4x4-minmax-fp32-scalar-imagic.c", |
| "src/qs8-qc8w-igemm/gen/qs8-qc8w-igemm-4x4-minmax-fp32-scalar-lrintf.c", |
| "src/qs8-requantization/qs8-requantization-fp32-scalar-fmagic.c", |
| "src/qs8-requantization/qs8-requantization-fp32-scalar-lrintf.c", |
| "src/qs8-requantization/qs8-requantization-gemmlowp-scalar.c", |
| "src/qs8-requantization/qs8-requantization-rndna-scalar-signed64.c", |
| "src/qs8-requantization/qs8-requantization-rndna-scalar-unsigned32.c", |
| "src/qs8-requantization/qs8-requantization-rndna-scalar-unsigned64.c", |
| "src/qs8-requantization/qs8-requantization-rndnu-scalar.c", |
| "src/qs8-vadd/gen/qs8-vadd-minmax-scalar-u1.c", |
| "src/qs8-vadd/gen/qs8-vadd-minmax-scalar-u2.c", |
| "src/qs8-vadd/gen/qs8-vadd-minmax-scalar-u4.c", |
| "src/qs8-vaddc/gen/qs8-vaddc-minmax-scalar-u1.c", |
| "src/qs8-vaddc/gen/qs8-vaddc-minmax-scalar-u2.c", |
| "src/qs8-vaddc/gen/qs8-vaddc-minmax-scalar-u4.c", |
| "src/qs8-vcvt/gen/qs8-vcvt-scalar-u1.c", |
| "src/qs8-vcvt/gen/qs8-vcvt-scalar-u2.c", |
| "src/qs8-vcvt/gen/qs8-vcvt-scalar-u4.c", |
| "src/qs8-vhswish/gen/qs8-vhswish-scalar-u1.c", |
| "src/qs8-vhswish/gen/qs8-vhswish-scalar-u2.c", |
| "src/qs8-vhswish/gen/qs8-vhswish-scalar-u4.c", |
| "src/qs8-vhswish/gen/qs8-vhswish-scalar-x1.c", |
| "src/qs8-vhswish/gen/qs8-vhswish-scalar-x2.c", |
| "src/qs8-vhswish/gen/qs8-vhswish-scalar-x4.c", |
| "src/qs8-vlrelu/gen/qs8-vlrelu-scalar-andxor-u1.c", |
| "src/qs8-vlrelu/gen/qs8-vlrelu-scalar-andxor-u2.c", |
| "src/qs8-vlrelu/gen/qs8-vlrelu-scalar-andxor-u4.c", |
| "src/qs8-vlrelu/gen/qs8-vlrelu-scalar-select-u1.c", |
| "src/qs8-vlrelu/gen/qs8-vlrelu-scalar-select-u2.c", |
| "src/qs8-vlrelu/gen/qs8-vlrelu-scalar-select-u4.c", |
| "src/qs8-vmul/gen/qs8-vmul-minmax-fp32-scalar-u1.c", |
| "src/qs8-vmul/gen/qs8-vmul-minmax-fp32-scalar-u2.c", |
| "src/qs8-vmul/gen/qs8-vmul-minmax-fp32-scalar-u4.c", |
| "src/qs8-vmulc/gen/qs8-vmulc-minmax-fp32-scalar-u1.c", |
| "src/qs8-vmulc/gen/qs8-vmulc-minmax-fp32-scalar-u2.c", |
| "src/qs8-vmulc/gen/qs8-vmulc-minmax-fp32-scalar-u4.c", |
| "src/qs16-qs8-vcvt/gen/qs16-qs8-vcvt-scalar-u1.c", |
| "src/qs16-qs8-vcvt/gen/qs16-qs8-vcvt-scalar-u2.c", |
| "src/qs16-qs8-vcvt/gen/qs16-qs8-vcvt-scalar-u4.c", |
| "src/qu8-avgpool/qu8-avgpool-9p8x-minmax-fp32-scalar-imagic-c1.c", |
| "src/qu8-avgpool/qu8-avgpool-9x-minmax-fp32-scalar-imagic-c1.c", |
| "src/qu8-dwconv/gen/qu8-dwconv-5f5m5l1c1s1r-minmax-fp32-scalar-fmagic.c", |
| "src/qu8-dwconv/gen/qu8-dwconv-5f5m5l1c1s1r-minmax-fp32-scalar-imagic.c", |
| "src/qu8-dwconv/gen/qu8-dwconv-5f5m5l1c1s1r-minmax-fp32-scalar-lrintf.c", |
| "src/qu8-dwconv/gen/qu8-dwconv-5f5m5l2c1s1r-minmax-fp32-scalar-fmagic.c", |
| "src/qu8-dwconv/gen/qu8-dwconv-5f5m5l2c1s1r-minmax-fp32-scalar-imagic.c", |
| "src/qu8-dwconv/gen/qu8-dwconv-5f5m5l2c1s1r-minmax-fp32-scalar-lrintf.c", |
| "src/qu8-dwconv/gen/qu8-dwconv-5f5m5l4c1s1r-minmax-fp32-scalar-fmagic.c", |
| "src/qu8-dwconv/gen/qu8-dwconv-5f5m5l4c1s1r-minmax-fp32-scalar-imagic.c", |
| "src/qu8-dwconv/gen/qu8-dwconv-5f5m5l4c1s1r-minmax-fp32-scalar-lrintf.c", |
| "src/qu8-dwconv/gen/qu8-dwconv-6f6m7l1c1s1r-minmax-fp32-scalar-fmagic.c", |
| "src/qu8-dwconv/gen/qu8-dwconv-6f6m7l1c1s1r-minmax-fp32-scalar-imagic.c", |
| "src/qu8-dwconv/gen/qu8-dwconv-6f6m7l1c1s1r-minmax-fp32-scalar-lrintf.c", |
| "src/qu8-dwconv/gen/qu8-dwconv-6f6m7l2c1s1r-minmax-fp32-scalar-fmagic.c", |
| "src/qu8-dwconv/gen/qu8-dwconv-6f6m7l2c1s1r-minmax-fp32-scalar-imagic.c", |
| "src/qu8-dwconv/gen/qu8-dwconv-6f6m7l2c1s1r-minmax-fp32-scalar-lrintf.c", |
| "src/qu8-dwconv/gen/qu8-dwconv-6f6m7l4c1s1r-minmax-fp32-scalar-fmagic.c", |
| "src/qu8-dwconv/gen/qu8-dwconv-6f6m7l4c1s1r-minmax-fp32-scalar-imagic.c", |
| "src/qu8-dwconv/gen/qu8-dwconv-6f6m7l4c1s1r-minmax-fp32-scalar-lrintf.c", |
| "src/qu8-dwconv/gen/qu8-dwconv-8f8m9l1c1s1r-minmax-fp32-scalar-fmagic.c", |
| "src/qu8-dwconv/gen/qu8-dwconv-8f8m9l1c1s1r-minmax-fp32-scalar-imagic.c", |
| "src/qu8-dwconv/gen/qu8-dwconv-8f8m9l1c1s1r-minmax-fp32-scalar-lrintf.c", |
| "src/qu8-dwconv/gen/qu8-dwconv-8f8m9l2c1s1r-minmax-fp32-scalar-fmagic.c", |
| "src/qu8-dwconv/gen/qu8-dwconv-8f8m9l2c1s1r-minmax-fp32-scalar-imagic.c", |
| "src/qu8-dwconv/gen/qu8-dwconv-8f8m9l2c1s1r-minmax-fp32-scalar-lrintf.c", |
| "src/qu8-dwconv/gen/qu8-dwconv-8f8m9l4c1s1r-minmax-fp32-scalar-fmagic.c", |
| "src/qu8-dwconv/gen/qu8-dwconv-8f8m9l4c1s1r-minmax-fp32-scalar-imagic.c", |
| "src/qu8-dwconv/gen/qu8-dwconv-8f8m9l4c1s1r-minmax-fp32-scalar-lrintf.c", |
| "src/qu8-dwconv/gen/qu8-dwconv-9p1c-minmax-fp32-scalar-fmagic.c", |
| "src/qu8-dwconv/gen/qu8-dwconv-9p1c-minmax-fp32-scalar-imagic.c", |
| "src/qu8-dwconv/gen/qu8-dwconv-9p1c-minmax-fp32-scalar-lrintf.c", |
| "src/qu8-dwconv/gen/qu8-dwconv-9p1c-minmax-rndnu-scalar.c", |
| "src/qu8-dwconv/gen/qu8-dwconv-9p2c-minmax-fp32-scalar-fmagic.c", |
| "src/qu8-dwconv/gen/qu8-dwconv-9p2c-minmax-fp32-scalar-imagic.c", |
| "src/qu8-dwconv/gen/qu8-dwconv-9p2c-minmax-fp32-scalar-lrintf.c", |
| "src/qu8-dwconv/gen/qu8-dwconv-9p2c-minmax-rndnu-scalar.c", |
| "src/qu8-dwconv/gen/qu8-dwconv-9p4c-minmax-fp32-scalar-fmagic.c", |
| "src/qu8-dwconv/gen/qu8-dwconv-9p4c-minmax-fp32-scalar-imagic.c", |
| "src/qu8-dwconv/gen/qu8-dwconv-9p4c-minmax-fp32-scalar-lrintf.c", |
| "src/qu8-dwconv/gen/qu8-dwconv-9p4c-minmax-rndnu-scalar.c", |
| "src/qu8-dwconv/gen/qu8-dwconv-25p1c-minmax-fp32-scalar-fmagic.c", |
| "src/qu8-dwconv/gen/qu8-dwconv-25p1c-minmax-fp32-scalar-imagic.c", |
| "src/qu8-dwconv/gen/qu8-dwconv-25p1c-minmax-fp32-scalar-lrintf.c", |
| "src/qu8-dwconv/gen/qu8-dwconv-25p2c-minmax-fp32-scalar-fmagic.c", |
| "src/qu8-dwconv/gen/qu8-dwconv-25p2c-minmax-fp32-scalar-imagic.c", |
| "src/qu8-dwconv/gen/qu8-dwconv-25p2c-minmax-fp32-scalar-lrintf.c", |
| "src/qu8-dwconv/gen/qu8-dwconv-25p4c-minmax-fp32-scalar-fmagic.c", |
| "src/qu8-dwconv/gen/qu8-dwconv-25p4c-minmax-fp32-scalar-imagic.c", |
| "src/qu8-dwconv/gen/qu8-dwconv-25p4c-minmax-fp32-scalar-lrintf.c", |
| "src/qu8-f32-vcvt/gen/qu8-f32-vcvt-scalar-u1.c", |
| "src/qu8-f32-vcvt/gen/qu8-f32-vcvt-scalar-u2.c", |
| "src/qu8-f32-vcvt/gen/qu8-f32-vcvt-scalar-u3.c", |
| "src/qu8-f32-vcvt/gen/qu8-f32-vcvt-scalar-u4.c", |
| "src/qu8-gavgpool/gen/qu8-gavgpool-7p7x-minmax-fp32-scalar-fmagic-c1.c", |
| "src/qu8-gavgpool/gen/qu8-gavgpool-7p7x-minmax-fp32-scalar-fmagic-c2.c", |
| "src/qu8-gavgpool/gen/qu8-gavgpool-7p7x-minmax-fp32-scalar-fmagic-c4.c", |
| "src/qu8-gavgpool/gen/qu8-gavgpool-7p7x-minmax-fp32-scalar-imagic-c1.c", |
| "src/qu8-gavgpool/gen/qu8-gavgpool-7p7x-minmax-fp32-scalar-imagic-c2.c", |
| "src/qu8-gavgpool/gen/qu8-gavgpool-7p7x-minmax-fp32-scalar-imagic-c4.c", |
| "src/qu8-gavgpool/gen/qu8-gavgpool-7p7x-minmax-fp32-scalar-lrintf-c1.c", |
| "src/qu8-gavgpool/gen/qu8-gavgpool-7p7x-minmax-fp32-scalar-lrintf-c2.c", |
| "src/qu8-gavgpool/gen/qu8-gavgpool-7p7x-minmax-fp32-scalar-lrintf-c4.c", |
| "src/qu8-gavgpool/gen/qu8-gavgpool-7x-minmax-fp32-scalar-fmagic-c1.c", |
| "src/qu8-gavgpool/gen/qu8-gavgpool-7x-minmax-fp32-scalar-fmagic-c2.c", |
| "src/qu8-gavgpool/gen/qu8-gavgpool-7x-minmax-fp32-scalar-fmagic-c4.c", |
| "src/qu8-gavgpool/gen/qu8-gavgpool-7x-minmax-fp32-scalar-imagic-c1.c", |
| "src/qu8-gavgpool/gen/qu8-gavgpool-7x-minmax-fp32-scalar-imagic-c2.c", |
| "src/qu8-gavgpool/gen/qu8-gavgpool-7x-minmax-fp32-scalar-imagic-c4.c", |
| "src/qu8-gavgpool/gen/qu8-gavgpool-7x-minmax-fp32-scalar-lrintf-c1.c", |
| "src/qu8-gavgpool/gen/qu8-gavgpool-7x-minmax-fp32-scalar-lrintf-c2.c", |
| "src/qu8-gavgpool/gen/qu8-gavgpool-7x-minmax-fp32-scalar-lrintf-c4.c", |
| "src/qu8-gemm/gen/qu8-gemm-1x2-minmax-fp32-scalar-fmagic.c", |
| "src/qu8-gemm/gen/qu8-gemm-1x2-minmax-fp32-scalar-imagic.c", |
| "src/qu8-gemm/gen/qu8-gemm-1x2-minmax-fp32-scalar-lrintf.c", |
| "src/qu8-gemm/gen/qu8-gemm-1x2-minmax-rndnu-scalar.c", |
| "src/qu8-gemm/gen/qu8-gemm-1x4-minmax-fp32-scalar-fmagic.c", |
| "src/qu8-gemm/gen/qu8-gemm-1x4-minmax-fp32-scalar-imagic.c", |
| "src/qu8-gemm/gen/qu8-gemm-1x4-minmax-fp32-scalar-lrintf.c", |
| "src/qu8-gemm/gen/qu8-gemm-1x4-minmax-rndnu-scalar.c", |
| "src/qu8-gemm/gen/qu8-gemm-2x2-minmax-fp32-scalar-fmagic.c", |
| "src/qu8-gemm/gen/qu8-gemm-2x2-minmax-fp32-scalar-imagic.c", |
| "src/qu8-gemm/gen/qu8-gemm-2x2-minmax-fp32-scalar-lrintf.c", |
| "src/qu8-gemm/gen/qu8-gemm-2x2-minmax-rndnu-scalar.c", |
| "src/qu8-gemm/gen/qu8-gemm-2x4-minmax-fp32-scalar-fmagic.c", |
| "src/qu8-gemm/gen/qu8-gemm-2x4-minmax-fp32-scalar-imagic.c", |
| "src/qu8-gemm/gen/qu8-gemm-2x4-minmax-fp32-scalar-lrintf.c", |
| "src/qu8-gemm/gen/qu8-gemm-2x4-minmax-rndnu-scalar.c", |
| "src/qu8-gemm/gen/qu8-gemm-3x2-minmax-fp32-scalar-fmagic.c", |
| "src/qu8-gemm/gen/qu8-gemm-3x2-minmax-fp32-scalar-imagic.c", |
| "src/qu8-gemm/gen/qu8-gemm-3x2-minmax-fp32-scalar-lrintf.c", |
| "src/qu8-gemm/gen/qu8-gemm-3x2-minmax-rndnu-scalar.c", |
| "src/qu8-gemm/gen/qu8-gemm-3x4-minmax-fp32-scalar-fmagic.c", |
| "src/qu8-gemm/gen/qu8-gemm-3x4-minmax-fp32-scalar-imagic.c", |
| "src/qu8-gemm/gen/qu8-gemm-3x4-minmax-fp32-scalar-lrintf.c", |
| "src/qu8-gemm/gen/qu8-gemm-3x4-minmax-rndnu-scalar.c", |
| "src/qu8-gemm/gen/qu8-gemm-4x2-minmax-fp32-scalar-fmagic.c", |
| "src/qu8-gemm/gen/qu8-gemm-4x2-minmax-fp32-scalar-imagic.c", |
| "src/qu8-gemm/gen/qu8-gemm-4x2-minmax-fp32-scalar-lrintf.c", |
| "src/qu8-gemm/gen/qu8-gemm-4x2-minmax-rndnu-scalar.c", |
| "src/qu8-gemm/gen/qu8-gemm-4x4-minmax-fp32-scalar-fmagic.c", |
| "src/qu8-gemm/gen/qu8-gemm-4x4-minmax-fp32-scalar-imagic.c", |
| "src/qu8-gemm/gen/qu8-gemm-4x4-minmax-fp32-scalar-lrintf.c", |
| "src/qu8-gemm/gen/qu8-gemm-4x4-minmax-rndnu-scalar.c", |
| "src/qu8-igemm/gen/qu8-igemm-1x2-minmax-fp32-scalar-fmagic.c", |
| "src/qu8-igemm/gen/qu8-igemm-1x2-minmax-fp32-scalar-imagic.c", |
| "src/qu8-igemm/gen/qu8-igemm-1x2-minmax-fp32-scalar-lrintf.c", |
| "src/qu8-igemm/gen/qu8-igemm-1x2-minmax-rndnu-scalar.c", |
| "src/qu8-igemm/gen/qu8-igemm-1x4-minmax-fp32-scalar-fmagic.c", |
| "src/qu8-igemm/gen/qu8-igemm-1x4-minmax-fp32-scalar-imagic.c", |
| "src/qu8-igemm/gen/qu8-igemm-1x4-minmax-fp32-scalar-lrintf.c", |
| "src/qu8-igemm/gen/qu8-igemm-1x4-minmax-rndnu-scalar.c", |
| "src/qu8-igemm/gen/qu8-igemm-2x2-minmax-fp32-scalar-fmagic.c", |
| "src/qu8-igemm/gen/qu8-igemm-2x2-minmax-fp32-scalar-imagic.c", |
| "src/qu8-igemm/gen/qu8-igemm-2x2-minmax-fp32-scalar-lrintf.c", |
| "src/qu8-igemm/gen/qu8-igemm-2x2-minmax-rndnu-scalar.c", |
| "src/qu8-igemm/gen/qu8-igemm-2x4-minmax-fp32-scalar-fmagic.c", |
| "src/qu8-igemm/gen/qu8-igemm-2x4-minmax-fp32-scalar-imagic.c", |
| "src/qu8-igemm/gen/qu8-igemm-2x4-minmax-fp32-scalar-lrintf.c", |
| "src/qu8-igemm/gen/qu8-igemm-2x4-minmax-rndnu-scalar.c", |
| "src/qu8-igemm/gen/qu8-igemm-3x2-minmax-fp32-scalar-fmagic.c", |
| "src/qu8-igemm/gen/qu8-igemm-3x2-minmax-fp32-scalar-imagic.c", |
| "src/qu8-igemm/gen/qu8-igemm-3x2-minmax-fp32-scalar-lrintf.c", |
| "src/qu8-igemm/gen/qu8-igemm-3x2-minmax-rndnu-scalar.c", |
| "src/qu8-igemm/gen/qu8-igemm-3x4-minmax-fp32-scalar-fmagic.c", |
| "src/qu8-igemm/gen/qu8-igemm-3x4-minmax-fp32-scalar-imagic.c", |
| "src/qu8-igemm/gen/qu8-igemm-3x4-minmax-fp32-scalar-lrintf.c", |
| "src/qu8-igemm/gen/qu8-igemm-3x4-minmax-rndnu-scalar.c", |
| "src/qu8-igemm/gen/qu8-igemm-4x2-minmax-fp32-scalar-fmagic.c", |
| "src/qu8-igemm/gen/qu8-igemm-4x2-minmax-fp32-scalar-imagic.c", |
| "src/qu8-igemm/gen/qu8-igemm-4x2-minmax-fp32-scalar-lrintf.c", |
| "src/qu8-igemm/gen/qu8-igemm-4x2-minmax-rndnu-scalar.c", |
| "src/qu8-igemm/gen/qu8-igemm-4x4-minmax-fp32-scalar-fmagic.c", |
| "src/qu8-igemm/gen/qu8-igemm-4x4-minmax-fp32-scalar-imagic.c", |
| "src/qu8-igemm/gen/qu8-igemm-4x4-minmax-fp32-scalar-lrintf.c", |
| "src/qu8-igemm/gen/qu8-igemm-4x4-minmax-rndnu-scalar.c", |
| "src/qu8-requantization/qu8-requantization-fp32-scalar-fmagic.c", |
| "src/qu8-requantization/qu8-requantization-fp32-scalar-lrintf.c", |
| "src/qu8-requantization/qu8-requantization-gemmlowp-scalar.c", |
| "src/qu8-requantization/qu8-requantization-rndna-scalar-signed64.c", |
| "src/qu8-requantization/qu8-requantization-rndna-scalar-unsigned32.c", |
| "src/qu8-requantization/qu8-requantization-rndna-scalar-unsigned64.c", |
| "src/qu8-vadd/gen/qu8-vadd-minmax-scalar-u1.c", |
| "src/qu8-vadd/gen/qu8-vadd-minmax-scalar-u2.c", |
| "src/qu8-vadd/gen/qu8-vadd-minmax-scalar-u4.c", |
| "src/qu8-vaddc/gen/qu8-vaddc-minmax-scalar-u1.c", |
| "src/qu8-vaddc/gen/qu8-vaddc-minmax-scalar-u2.c", |
| "src/qu8-vaddc/gen/qu8-vaddc-minmax-scalar-u4.c", |
| "src/qu8-vcvt/gen/qu8-vcvt-scalar-u1.c", |
| "src/qu8-vcvt/gen/qu8-vcvt-scalar-u2.c", |
| "src/qu8-vcvt/gen/qu8-vcvt-scalar-u4.c", |
| "src/qu8-vhswish/gen/qu8-vhswish-scalar-x1.c", |
| "src/qu8-vhswish/gen/qu8-vhswish-scalar-x2.c", |
| "src/qu8-vhswish/gen/qu8-vhswish-scalar-x4.c", |
| "src/qu8-vlrelu/gen/qu8-vlrelu-scalar-andxor-u1.c", |
| "src/qu8-vlrelu/gen/qu8-vlrelu-scalar-andxor-u2.c", |
| "src/qu8-vlrelu/gen/qu8-vlrelu-scalar-andxor-u4.c", |
| "src/qu8-vlrelu/gen/qu8-vlrelu-scalar-select-u1.c", |
| "src/qu8-vlrelu/gen/qu8-vlrelu-scalar-select-u2.c", |
| "src/qu8-vlrelu/gen/qu8-vlrelu-scalar-select-u4.c", |
| "src/qu8-vmul/gen/qu8-vmul-minmax-fp32-scalar-u1.c", |
| "src/qu8-vmul/gen/qu8-vmul-minmax-fp32-scalar-u2.c", |
| "src/qu8-vmul/gen/qu8-vmul-minmax-fp32-scalar-u4.c", |
| "src/qu8-vmulc/gen/qu8-vmulc-minmax-fp32-scalar-u1.c", |
| "src/qu8-vmulc/gen/qu8-vmulc-minmax-fp32-scalar-u2.c", |
| "src/qu8-vmulc/gen/qu8-vmulc-minmax-fp32-scalar-u4.c", |
| "src/s8-ibilinear/gen/s8-ibilinear-scalar-c1.c", |
| "src/s8-ibilinear/gen/s8-ibilinear-scalar-c2.c", |
| "src/s8-ibilinear/gen/s8-ibilinear-scalar-c4.c", |
| "src/s8-maxpool/s8-maxpool-9p8x-minmax-scalar-c1.c", |
| "src/s8-vclamp/s8-vclamp-scalar-u4.c", |
| "src/s16-rmaxabs/gen/s16-rmaxabs-scalar-x1.c", |
| "src/s16-rmaxabs/gen/s16-rmaxabs-scalar-x2.c", |
| "src/s16-rmaxabs/gen/s16-rmaxabs-scalar-x3.c", |
| "src/s16-rmaxabs/gen/s16-rmaxabs-scalar-x4.c", |
| "src/s16-window/gen/s16-window-scalar-u1.c", |
| "src/s16-window/gen/s16-window-scalar-u2.c", |
| "src/s16-window/gen/s16-window-scalar-u3.c", |
| "src/s16-window/gen/s16-window-scalar-u4.c", |
| "src/u8-ibilinear/gen/u8-ibilinear-scalar-c1.c", |
| "src/u8-ibilinear/gen/u8-ibilinear-scalar-c2.c", |
| "src/u8-ibilinear/gen/u8-ibilinear-scalar-c4.c", |
| "src/u8-lut32norm/u8-lut32norm-scalar.c", |
| "src/u8-maxpool/u8-maxpool-9p8x-minmax-scalar-c1.c", |
| "src/u8-rmax/u8-rmax-scalar.c", |
| "src/u8-vclamp/u8-vclamp-scalar-u4.c", |
| "src/u32-filterbank-accumulate/gen/u32-filterbank-accumulate-scalar-x1.c", |
| "src/u32-filterbank-subtract/u32-filterbank-subtract-scalar-x2.c", |
| "src/u32-vlog/gen/u32-vlog-scalar-x1.c", |
| "src/u32-vlog/gen/u32-vlog-scalar-x2.c", |
| "src/u32-vlog/gen/u32-vlog-scalar-x3.c", |
| "src/u32-vlog/gen/u32-vlog-scalar-x4.c", |
| "src/u64-u32-vsqrtshift/u64-u32-vsqrtshift-scalar-cvtu32-sqrt-cvtu32f64-u1.c", |
| "src/x8-lut/gen/x8-lut-scalar-u1.c", |
| "src/x8-lut/gen/x8-lut-scalar-u2.c", |
| "src/x8-lut/gen/x8-lut-scalar-u4.c", |
| "src/x8-lut/gen/x8-lut-scalar-u8.c", |
| "src/x8-lut/gen/x8-lut-scalar-u16.c", |
| "src/x8-packw/gen/x8-packw-x2-gemm-goi-scalar-int-u2.c", |
| "src/x8-packw/gen/x8-packw-x2-gemm-goi-scalar-int-u4.c", |
| "src/x8-packw/gen/x8-packw-x4-gemm-goi-scalar-int-u2.c", |
| "src/x8-packw/gen/x8-packw-x4-gemm-goi-scalar-int-u4.c", |
| "src/x8-packw/gen/x8-packw-x8-gemm-goi-scalar-int-u2.c", |
| "src/x8-packw/gen/x8-packw-x8-gemm-goi-scalar-int-u4.c", |
| "src/x8-packw/gen/x8-packw-x16-gemm-goi-scalar-int-u2.c", |
| "src/x8-packw/gen/x8-packw-x16-gemm-goi-scalar-int-u4.c", |
| "src/x8-packw/gen/x8-packw-x32-gemm-goi-scalar-int-u2.c", |
| "src/x8-packw/gen/x8-packw-x32-gemm-goi-scalar-int-u4.c", |
| "src/x8-transposec/gen/x8-transposec-1x2-scalar-int.c", |
| "src/x8-transposec/gen/x8-transposec-1x4-scalar-int.c", |
| "src/x8-transposec/gen/x8-transposec-2x1-scalar-int.c", |
| "src/x8-transposec/gen/x8-transposec-2x2-scalar-int.c", |
| "src/x8-transposec/gen/x8-transposec-2x4-scalar-int.c", |
| "src/x8-transposec/gen/x8-transposec-4x1-scalar-int.c", |
| "src/x8-transposec/gen/x8-transposec-4x2-scalar-int.c", |
| "src/x8-transposec/gen/x8-transposec-4x4-scalar-int.c", |
| "src/x8-zip/x8-zip-x2-scalar.c", |
| "src/x8-zip/x8-zip-x3-scalar.c", |
| "src/x8-zip/x8-zip-x4-scalar.c", |
| "src/x8-zip/x8-zip-xm-scalar.c", |
| "src/x16-packw/gen/x16-packw-x8-gemm-goi-scalar-int-u4.c", |
| "src/x16-packw/gen/x16-packw-x16-gemm-goi-scalar-int-u4.c", |
| "src/x16-transposec/gen/x16-transposec-1x2-scalar-int.c", |
| "src/x16-transposec/gen/x16-transposec-1x4-scalar-int.c", |
| "src/x16-transposec/gen/x16-transposec-2x1-scalar-int.c", |
| "src/x16-transposec/gen/x16-transposec-2x2-scalar-int.c", |
| "src/x16-transposec/gen/x16-transposec-2x4-scalar-int.c", |
| "src/x16-transposec/gen/x16-transposec-4x1-scalar-int.c", |
| "src/x16-transposec/gen/x16-transposec-4x2-scalar-int.c", |
| "src/x16-transposec/gen/x16-transposec-4x4-scalar-int.c", |
| "src/x24-transposec/gen/x24-transposec-1x2-scalar.c", |
| "src/x24-transposec/gen/x24-transposec-1x4-scalar.c", |
| "src/x24-transposec/gen/x24-transposec-2x1-scalar.c", |
| "src/x24-transposec/gen/x24-transposec-2x2-scalar.c", |
| "src/x24-transposec/gen/x24-transposec-2x4-scalar.c", |
| "src/x24-transposec/gen/x24-transposec-4x1-scalar.c", |
| "src/x24-transposec/gen/x24-transposec-4x2-scalar.c", |
| "src/x24-transposec/gen/x24-transposec-4x4-scalar.c", |
| "src/x32-packb/gen/x32-packb-2c1s1r-gemm-scalar-float.c", |
| "src/x32-packb/gen/x32-packb-2c1s1r-gemm-scalar-int.c", |
| "src/x32-packb/gen/x32-packb-2c2s1r-gemm-scalar-float.c", |
| "src/x32-packb/gen/x32-packb-2c2s1r-gemm-scalar-int.c", |
| "src/x32-packb/gen/x32-packb-4c1s1r-gemm-scalar-float.c", |
| "src/x32-packb/gen/x32-packb-4c1s1r-gemm-scalar-int.c", |
| "src/x32-packb/gen/x32-packb-4c4s1r-gemm-scalar-float.c", |
| "src/x32-packb/gen/x32-packb-4c4s1r-gemm-scalar-int.c", |
| "src/x32-packw/gen/x32-packw-x2-gemm-goi-scalar-float-u4.c", |
| "src/x32-packw/gen/x32-packw-x2-gemm-goi-scalar-int-u4.c", |
| "src/x32-packw/gen/x32-packw-x3-gemm-goi-scalar-float-u4.c", |
| "src/x32-packw/gen/x32-packw-x3-gemm-goi-scalar-int-u4.c", |
| "src/x32-packw/gen/x32-packw-x4-gemm-goi-scalar-float-u4.c", |
| "src/x32-packw/gen/x32-packw-x4-gemm-goi-scalar-int-u4.c", |
| "src/x32-packw/gen/x32-packw-x8-gemm-goi-scalar-float-u4.c", |
| "src/x32-packw/gen/x32-packw-x8-gemm-goi-scalar-int-u4.c", |
| "src/x32-packw/gen/x32-packw-x16-gemm-goi-scalar-float-u4.c", |
| "src/x32-packw/gen/x32-packw-x16-gemm-goi-scalar-int-u4.c", |
| "src/x32-packx/x32-packx-2x-scalar.c", |
| "src/x32-packx/x32-packx-3x-scalar.c", |
| "src/x32-packx/x32-packx-4x-scalar.c", |
| "src/x32-transposec/gen/x32-transposec-1x2-scalar-float.c", |
| "src/x32-transposec/gen/x32-transposec-1x2-scalar-int.c", |
| "src/x32-transposec/gen/x32-transposec-1x4-scalar-float.c", |
| "src/x32-transposec/gen/x32-transposec-1x4-scalar-int.c", |
| "src/x32-transposec/gen/x32-transposec-2x1-scalar-float.c", |
| "src/x32-transposec/gen/x32-transposec-2x1-scalar-int.c", |
| "src/x32-transposec/gen/x32-transposec-2x2-scalar-float.c", |
| "src/x32-transposec/gen/x32-transposec-2x2-scalar-int.c", |
| "src/x32-transposec/gen/x32-transposec-2x4-scalar-float.c", |
| "src/x32-transposec/gen/x32-transposec-2x4-scalar-int.c", |
| "src/x32-transposec/gen/x32-transposec-4x1-scalar-float.c", |
| "src/x32-transposec/gen/x32-transposec-4x1-scalar-int.c", |
| "src/x32-transposec/gen/x32-transposec-4x2-scalar-float.c", |
| "src/x32-transposec/gen/x32-transposec-4x2-scalar-int.c", |
| "src/x32-transposec/gen/x32-transposec-4x4-scalar-float.c", |
| "src/x32-transposec/gen/x32-transposec-4x4-scalar-int.c", |
| "src/x32-unpool/x32-unpool-scalar.c", |
| "src/x32-zerob/gen/x32-zerob-2c1s1r-gemm-scalar-float.c", |
| "src/x32-zerob/gen/x32-zerob-2c1s1r-gemm-scalar-int.c", |
| "src/x32-zerob/gen/x32-zerob-2c2s1r-gemm-scalar-float.c", |
| "src/x32-zerob/gen/x32-zerob-2c2s1r-gemm-scalar-int.c", |
| "src/x32-zerob/gen/x32-zerob-4c1s1r-gemm-scalar-float.c", |
| "src/x32-zerob/gen/x32-zerob-4c1s1r-gemm-scalar-int.c", |
| "src/x32-zerob/gen/x32-zerob-4c4s1r-gemm-scalar-float.c", |
| "src/x32-zerob/gen/x32-zerob-4c4s1r-gemm-scalar-int.c", |
| "src/x32-zip/x32-zip-x2-scalar.c", |
| "src/x32-zip/x32-zip-x3-scalar.c", |
| "src/x32-zip/x32-zip-x4-scalar.c", |
| "src/x32-zip/x32-zip-xm-scalar.c", |
| "src/x64-transposec/gen/x64-transposec-1x2-scalar-float.c", |
| "src/x64-transposec/gen/x64-transposec-1x2-scalar-int.c", |
| "src/x64-transposec/gen/x64-transposec-2x1-scalar-float.c", |
| "src/x64-transposec/gen/x64-transposec-2x1-scalar-int.c", |
| "src/x64-transposec/gen/x64-transposec-2x2-scalar-float.c", |
| "src/x64-transposec/gen/x64-transposec-2x2-scalar-int.c", |
| "src/x64-transposec/gen/x64-transposec-4x1-scalar-float.c", |
| "src/x64-transposec/gen/x64-transposec-4x1-scalar-int.c", |
| "src/x64-transposec/gen/x64-transposec-4x2-scalar-float.c", |
| "src/x64-transposec/gen/x64-transposec-4x2-scalar-int.c", |
| "src/xx-copy/xx-copy-scalar-memcpy.c", |
| "src/xx-fill/xx-fill-scalar-x16.c", |
| "src/xx-pad/xx-pad-scalar.c", |
| "src/xx-transposev/xx-transposev-1x1-scalar-memcpy.c", |
| ] |
| |
| ALL_SSE_MICROKERNEL_SRCS = [ |
| "src/f32-avgpool/f32-avgpool-9p8x-minmax-sse-c4.c", |
| "src/f32-avgpool/f32-avgpool-9x-minmax-sse-c4.c", |
| "src/f32-conv-hwc2chw/f32-conv-hwc2chw-3x3s2p1c3x4-sse-1x1.c", |
| "src/f32-conv-hwc2chw/f32-conv-hwc2chw-3x3s2p1c3x4-sse-2x2.c", |
| "src/f32-dwconv2d-chw/gen/f32-dwconv2d-chw-3x3p1-minmax-sse-1x4-acc2.c", |
| "src/f32-dwconv2d-chw/gen/f32-dwconv2d-chw-3x3p1-minmax-sse-1x4-acc3.c", |
| "src/f32-dwconv2d-chw/gen/f32-dwconv2d-chw-3x3p1-minmax-sse-1x4-acc4.c", |
| "src/f32-dwconv2d-chw/gen/f32-dwconv2d-chw-3x3p1-minmax-sse-1x4.c", |
| "src/f32-dwconv2d-chw/gen/f32-dwconv2d-chw-3x3p1-minmax-sse-2x4-acc2.c", |
| "src/f32-dwconv2d-chw/gen/f32-dwconv2d-chw-3x3p1-minmax-sse-2x4.c", |
| "src/f32-dwconv2d-chw/gen/f32-dwconv2d-chw-3x3p1-minmax-sse-3x4.c", |
| "src/f32-dwconv2d-chw/gen/f32-dwconv2d-chw-3x3p1-minmax-sse-4x4.c", |
| "src/f32-dwconv2d-chw/gen/f32-dwconv2d-chw-3x3p1-minmax-sse-5x4.c", |
| "src/f32-dwconv2d-chw/gen/f32-dwconv2d-chw-3x3p1-minmax-sse-6x4.c", |
| "src/f32-dwconv2d-chw/gen/f32-dwconv2d-chw-3x3s2p1-minmax-sse-1x4-acc2.c", |
| "src/f32-dwconv2d-chw/gen/f32-dwconv2d-chw-3x3s2p1-minmax-sse-1x4-acc3.c", |
| "src/f32-dwconv2d-chw/gen/f32-dwconv2d-chw-3x3s2p1-minmax-sse-1x4-acc4.c", |
| "src/f32-dwconv2d-chw/gen/f32-dwconv2d-chw-3x3s2p1-minmax-sse-1x4.c", |
| "src/f32-dwconv2d-chw/gen/f32-dwconv2d-chw-3x3s2p1-minmax-sse-2x4-acc2.c", |
| "src/f32-dwconv2d-chw/gen/f32-dwconv2d-chw-3x3s2p1-minmax-sse-2x4.c", |
| "src/f32-dwconv2d-chw/gen/f32-dwconv2d-chw-3x3s2p1-minmax-sse-3x4.c", |
| "src/f32-dwconv2d-chw/gen/f32-dwconv2d-chw-3x3s2p1-minmax-sse-4x4.c", |
| "src/f32-dwconv2d-chw/gen/f32-dwconv2d-chw-5x5p2-minmax-sse-1x4-acc2.c", |
| "src/f32-dwconv2d-chw/gen/f32-dwconv2d-chw-5x5p2-minmax-sse-1x4-acc3.c", |
| "src/f32-dwconv2d-chw/gen/f32-dwconv2d-chw-5x5p2-minmax-sse-1x4-acc4.c", |
| "src/f32-dwconv2d-chw/gen/f32-dwconv2d-chw-5x5p2-minmax-sse-1x4-acc5.c", |
| "src/f32-dwconv2d-chw/gen/f32-dwconv2d-chw-5x5p2-minmax-sse-1x4.c", |
| "src/f32-dwconv2d-chw/gen/f32-dwconv2d-chw-5x5p2-minmax-sse-2x4-acc2.c", |
| "src/f32-dwconv2d-chw/gen/f32-dwconv2d-chw-5x5p2-minmax-sse-2x4-acc3.c", |
| "src/f32-dwconv2d-chw/gen/f32-dwconv2d-chw-5x5p2-minmax-sse-2x4.c", |
| "src/f32-dwconv2d-chw/gen/f32-dwconv2d-chw-5x5p2-minmax-sse-3x4-acc2.c", |
| "src/f32-dwconv2d-chw/gen/f32-dwconv2d-chw-5x5p2-minmax-sse-3x4.c", |
| "src/f32-dwconv2d-chw/gen/f32-dwconv2d-chw-5x5p2-minmax-sse-4x4-acc2.c", |
| "src/f32-dwconv2d-chw/gen/f32-dwconv2d-chw-5x5p2-minmax-sse-4x4.c", |
| "src/f32-dwconv2d-chw/gen/f32-dwconv2d-chw-5x5p2-minmax-sse-5x4.c", |
| "src/f32-dwconv2d-chw/gen/f32-dwconv2d-chw-5x5s2p2-minmax-sse-1x4-acc2.c", |
| "src/f32-dwconv2d-chw/gen/f32-dwconv2d-chw-5x5s2p2-minmax-sse-1x4-acc3.c", |
| "src/f32-dwconv2d-chw/gen/f32-dwconv2d-chw-5x5s2p2-minmax-sse-1x4-acc4.c", |
| "src/f32-dwconv2d-chw/gen/f32-dwconv2d-chw-5x5s2p2-minmax-sse-1x4-acc5.c", |
| "src/f32-dwconv2d-chw/gen/f32-dwconv2d-chw-5x5s2p2-minmax-sse-1x4.c", |
| "src/f32-dwconv2d-chw/gen/f32-dwconv2d-chw-5x5s2p2-minmax-sse-2x4-acc2.c", |
| "src/f32-dwconv2d-chw/gen/f32-dwconv2d-chw-5x5s2p2-minmax-sse-2x4-acc3.c", |
| "src/f32-dwconv2d-chw/gen/f32-dwconv2d-chw-5x5s2p2-minmax-sse-2x4.c", |
| "src/f32-dwconv2d-chw/gen/f32-dwconv2d-chw-5x5s2p2-minmax-sse-3x4-acc2.c", |
| "src/f32-dwconv2d-chw/gen/f32-dwconv2d-chw-5x5s2p2-minmax-sse-3x4.c", |
| "src/f32-dwconv/gen/f32-dwconv-3p4c-minmax-sse-acc2.c", |
| "src/f32-dwconv/gen/f32-dwconv-3p4c-minmax-sse.c", |
| "src/f32-dwconv/gen/f32-dwconv-3p8c-minmax-sse-acc2.c", |
| "src/f32-dwconv/gen/f32-dwconv-3p8c-minmax-sse.c", |
| "src/f32-dwconv/gen/f32-dwconv-4p4c-minmax-sse-acc2.c", |
| "src/f32-dwconv/gen/f32-dwconv-4p4c-minmax-sse.c", |
| "src/f32-dwconv/gen/f32-dwconv-4p8c-minmax-sse-acc2.c", |
| "src/f32-dwconv/gen/f32-dwconv-4p8c-minmax-sse.c", |
| "src/f32-dwconv/gen/f32-dwconv-5f5m5l4c4s4r-minmax-sse-acc2.c", |
| "src/f32-dwconv/gen/f32-dwconv-5f5m5l4c4s4r-minmax-sse.c", |
| "src/f32-dwconv/gen/f32-dwconv-5f5m5l8c4s4r-minmax-sse-acc2.c", |
| "src/f32-dwconv/gen/f32-dwconv-5f5m5l8c4s4r-minmax-sse.c", |
| "src/f32-dwconv/gen/f32-dwconv-5f5m5l16c4s4r-minmax-sse-acc2.c", |
| "src/f32-dwconv/gen/f32-dwconv-5f5m5l16c4s4r-minmax-sse.c", |
| "src/f32-dwconv/gen/f32-dwconv-6f6m7l4c4s4r-minmax-sse-acc2.c", |
| "src/f32-dwconv/gen/f32-dwconv-6f6m7l4c4s4r-minmax-sse.c", |
| "src/f32-dwconv/gen/f32-dwconv-6f6m7l8c4s4r-minmax-sse-acc2.c", |
| "src/f32-dwconv/gen/f32-dwconv-6f6m7l8c4s4r-minmax-sse.c", |
| "src/f32-dwconv/gen/f32-dwconv-6f6m7l16c4s4r-minmax-sse-acc2.c", |
| "src/f32-dwconv/gen/f32-dwconv-6f6m7l16c4s4r-minmax-sse.c", |
| "src/f32-dwconv/gen/f32-dwconv-8f8m9l4c4s4r-minmax-sse-acc2.c", |
| "src/f32-dwconv/gen/f32-dwconv-8f8m9l4c4s4r-minmax-sse.c", |
| "src/f32-dwconv/gen/f32-dwconv-8f8m9l8c4s4r-minmax-sse-acc2.c", |
| "src/f32-dwconv/gen/f32-dwconv-8f8m9l8c4s4r-minmax-sse.c", |
| "src/f32-dwconv/gen/f32-dwconv-8f8m9l16c4s4r-minmax-sse-acc2.c", |
| "src/f32-dwconv/gen/f32-dwconv-8f8m9l16c4s4r-minmax-sse.c", |
| "src/f32-dwconv/gen/f32-dwconv-9p4c-minmax-sse-acc2.c", |
| "src/f32-dwconv/gen/f32-dwconv-9p4c-minmax-sse.c", |
| "src/f32-dwconv/gen/f32-dwconv-9p8c-minmax-sse-acc2.c", |
| "src/f32-dwconv/gen/f32-dwconv-9p8c-minmax-sse.c", |
| "src/f32-dwconv/gen/f32-dwconv-25p4c-minmax-sse-acc2.c", |
| "src/f32-dwconv/gen/f32-dwconv-25p4c-minmax-sse.c", |
| "src/f32-dwconv/gen/f32-dwconv-25p8c-minmax-sse-acc2.c", |
| "src/f32-dwconv/gen/f32-dwconv-25p8c-minmax-sse.c", |
| "src/f32-gavgpool-cw/f32-gavgpool-cw-sse-x4.c", |
| "src/f32-gavgpool/f32-gavgpool-7p7x-minmax-sse-c4.c", |
| "src/f32-gavgpool/f32-gavgpool-7x-minmax-sse-c4.c", |
| "src/f32-gemm/gen/f32-gemm-1x8-minmax-sse-dup.c", |
| "src/f32-gemm/gen/f32-gemm-1x8-minmax-sse-load1.c", |
| "src/f32-gemm/gen/f32-gemm-1x8s4-minmax-sse.c", |
| "src/f32-gemm/gen/f32-gemm-3x8-minmax-sse-dup.c", |
| "src/f32-gemm/gen/f32-gemm-3x8-minmax-sse-load1.c", |
| "src/f32-gemm/gen/f32-gemm-3x8s4-minmax-sse.c", |
| "src/f32-gemm/gen/f32-gemm-4x2c4-minmax-sse.c", |
| "src/f32-gemm/gen/f32-gemm-4x8-minmax-sse-dup.c", |
| "src/f32-gemm/gen/f32-gemm-4x8-minmax-sse-load1.c", |
| "src/f32-gemm/gen/f32-gemm-4x8s4-minmax-sse.c", |
| "src/f32-gemm/gen/f32-gemm-5x8-minmax-sse-dup.c", |
| "src/f32-gemm/gen/f32-gemm-5x8-minmax-sse-load1.c", |
| "src/f32-gemm/gen/f32-gemm-5x8s4-minmax-sse.c", |
| "src/f32-gemm/gen/f32-gemm-6x2c4-minmax-sse.c", |
| "src/f32-gemm/gen/f32-gemm-6x8-minmax-sse-dup.c", |
| "src/f32-gemm/gen/f32-gemm-6x8-minmax-sse-load1.c", |
| "src/f32-gemm/gen/f32-gemm-6x8s4-minmax-sse.c", |
| "src/f32-gemminc/gen/f32-gemminc-1x8-minmax-sse-dup.c", |
| "src/f32-gemminc/gen/f32-gemminc-1x8-minmax-sse-load1.c", |
| "src/f32-gemminc/gen/f32-gemminc-1x8s4-minmax-sse.c", |
| "src/f32-gemminc/gen/f32-gemminc-3x8-minmax-sse-dup.c", |
| "src/f32-gemminc/gen/f32-gemminc-3x8-minmax-sse-load1.c", |
| "src/f32-gemminc/gen/f32-gemminc-3x8s4-minmax-sse.c", |
| "src/f32-gemminc/gen/f32-gemminc-4x8-minmax-sse-dup.c", |
| "src/f32-gemminc/gen/f32-gemminc-4x8-minmax-sse-load1.c", |
| "src/f32-gemminc/gen/f32-gemminc-4x8s4-minmax-sse.c", |
| "src/f32-gemminc/gen/f32-gemminc-5x8-minmax-sse-dup.c", |
| "src/f32-gemminc/gen/f32-gemminc-5x8-minmax-sse-load1.c", |
| "src/f32-gemminc/gen/f32-gemminc-5x8s4-minmax-sse.c", |
| "src/f32-gemminc/gen/f32-gemminc-6x8-minmax-sse-dup.c", |
| "src/f32-gemminc/gen/f32-gemminc-6x8-minmax-sse-load1.c", |
| "src/f32-gemminc/gen/f32-gemminc-6x8s4-minmax-sse.c", |
| "src/f32-ibilinear-chw/gen/f32-ibilinear-chw-sse-p4.c", |
| "src/f32-ibilinear-chw/gen/f32-ibilinear-chw-sse-p8.c", |
| "src/f32-ibilinear/gen/f32-ibilinear-sse-c4.c", |
| "src/f32-ibilinear/gen/f32-ibilinear-sse-c8.c", |
| "src/f32-igemm/gen/f32-igemm-1x8-minmax-sse-dup.c", |
| "src/f32-igemm/gen/f32-igemm-1x8-minmax-sse-load1.c", |
| "src/f32-igemm/gen/f32-igemm-1x8s4-minmax-sse.c", |
| "src/f32-igemm/gen/f32-igemm-3x8-minmax-sse-dup.c", |
| "src/f32-igemm/gen/f32-igemm-3x8-minmax-sse-load1.c", |
| "src/f32-igemm/gen/f32-igemm-3x8s4-minmax-sse.c", |
| "src/f32-igemm/gen/f32-igemm-4x2c4-minmax-sse.c", |
| "src/f32-igemm/gen/f32-igemm-4x8-minmax-sse-dup.c", |
| "src/f32-igemm/gen/f32-igemm-4x8-minmax-sse-load1.c", |
| "src/f32-igemm/gen/f32-igemm-4x8s4-minmax-sse.c", |
| "src/f32-igemm/gen/f32-igemm-5x8-minmax-sse-dup.c", |
| "src/f32-igemm/gen/f32-igemm-5x8-minmax-sse-load1.c", |
| "src/f32-igemm/gen/f32-igemm-5x8s4-minmax-sse.c", |
| "src/f32-igemm/gen/f32-igemm-6x2c4-minmax-sse.c", |
| "src/f32-igemm/gen/f32-igemm-6x8-minmax-sse-dup.c", |
| "src/f32-igemm/gen/f32-igemm-6x8-minmax-sse-load1.c", |
| "src/f32-igemm/gen/f32-igemm-6x8s4-minmax-sse.c", |
| "src/f32-maxpool/f32-maxpool-9p8x-minmax-sse-c4.c", |
| "src/f32-pavgpool/f32-pavgpool-9p8x-minmax-sse-c4.c", |
| "src/f32-pavgpool/f32-pavgpool-9x-minmax-sse-c4.c", |
| "src/f32-ppmm/gen/f32-ppmm-4x8-minmax-sse.c", |
| "src/f32-prelu/gen/f32-prelu-sse-2x4.c", |
| "src/f32-prelu/gen/f32-prelu-sse-2x8.c", |
| "src/f32-rmax/f32-rmax-sse.c", |
| "src/f32-rminmax/gen/f32-rmax-sse-u4.c", |
| "src/f32-rminmax/gen/f32-rmax-sse-u8-acc2.c", |
| "src/f32-rminmax/gen/f32-rmax-sse-u12-acc3.c", |
| "src/f32-rminmax/gen/f32-rmax-sse-u16-acc2.c", |
| "src/f32-rminmax/gen/f32-rmax-sse-u16-acc4.c", |
| "src/f32-rminmax/gen/f32-rmin-sse-u4.c", |
| "src/f32-rminmax/gen/f32-rmin-sse-u8-acc2.c", |
| "src/f32-rminmax/gen/f32-rmin-sse-u12-acc3.c", |
| "src/f32-rminmax/gen/f32-rmin-sse-u16-acc2.c", |
| "src/f32-rminmax/gen/f32-rmin-sse-u16-acc4.c", |
| "src/f32-rminmax/gen/f32-rminmax-sse-u4.c", |
| "src/f32-rminmax/gen/f32-rminmax-sse-u8-acc2.c", |
| "src/f32-rminmax/gen/f32-rminmax-sse-u12-acc3.c", |
| "src/f32-rminmax/gen/f32-rminmax-sse-u16-acc2.c", |
| "src/f32-rminmax/gen/f32-rminmax-sse-u16-acc4.c", |
| "src/f32-rsum/gen/f32-rsum-sse-u4.c", |
| "src/f32-rsum/gen/f32-rsum-sse-u8-acc2.c", |
| "src/f32-rsum/gen/f32-rsum-sse-u12-acc3.c", |
| "src/f32-rsum/gen/f32-rsum-sse-u16-acc2.c", |
| "src/f32-rsum/gen/f32-rsum-sse-u16-acc4.c", |
| "src/f32-spmm/gen/f32-spmm-4x1-minmax-sse.c", |
| "src/f32-spmm/gen/f32-spmm-8x1-minmax-sse.c", |
| "src/f32-spmm/gen/f32-spmm-16x1-minmax-sse.c", |
| "src/f32-spmm/gen/f32-spmm-32x1-minmax-sse.c", |
| "src/f32-vbinary/gen/f32-vadd-minmax-sse-u4.c", |
| "src/f32-vbinary/gen/f32-vadd-minmax-sse-u8.c", |
| "src/f32-vbinary/gen/f32-vaddc-minmax-sse-u4.c", |
| "src/f32-vbinary/gen/f32-vaddc-minmax-sse-u8.c", |
| "src/f32-vbinary/gen/f32-vdiv-minmax-sse-u4.c", |
| "src/f32-vbinary/gen/f32-vdiv-minmax-sse-u8.c", |
| "src/f32-vbinary/gen/f32-vdivc-minmax-sse-u4.c", |
| "src/f32-vbinary/gen/f32-vdivc-minmax-sse-u8.c", |
| "src/f32-vbinary/gen/f32-vmax-sse-u4.c", |
| "src/f32-vbinary/gen/f32-vmax-sse-u8.c", |
| "src/f32-vbinary/gen/f32-vmaxc-sse-u4.c", |
| "src/f32-vbinary/gen/f32-vmaxc-sse-u8.c", |
| "src/f32-vbinary/gen/f32-vmin-sse-u4.c", |
| "src/f32-vbinary/gen/f32-vmin-sse-u8.c", |
| "src/f32-vbinary/gen/f32-vminc-sse-u4.c", |
| "src/f32-vbinary/gen/f32-vminc-sse-u8.c", |
| "src/f32-vbinary/gen/f32-vmul-minmax-sse-u4.c", |
| "src/f32-vbinary/gen/f32-vmul-minmax-sse-u8.c", |
| "src/f32-vbinary/gen/f32-vmulc-minmax-sse-u4.c", |
| "src/f32-vbinary/gen/f32-vmulc-minmax-sse-u8.c", |
| "src/f32-vbinary/gen/f32-vrdivc-minmax-sse-u4.c", |
| "src/f32-vbinary/gen/f32-vrdivc-minmax-sse-u8.c", |
| "src/f32-vbinary/gen/f32-vrsubc-minmax-sse-u4.c", |
| "src/f32-vbinary/gen/f32-vrsubc-minmax-sse-u8.c", |
| "src/f32-vbinary/gen/f32-vsqrdiff-sse-u4.c", |
| "src/f32-vbinary/gen/f32-vsqrdiff-sse-u8.c", |
| "src/f32-vbinary/gen/f32-vsqrdiffc-sse-u4.c", |
| "src/f32-vbinary/gen/f32-vsqrdiffc-sse-u8.c", |
| "src/f32-vbinary/gen/f32-vsub-minmax-sse-u4.c", |
| "src/f32-vbinary/gen/f32-vsub-minmax-sse-u8.c", |
| "src/f32-vbinary/gen/f32-vsubc-minmax-sse-u4.c", |
| "src/f32-vbinary/gen/f32-vsubc-minmax-sse-u8.c", |
| "src/f32-vclamp/gen/f32-vclamp-sse-u4.c", |
| "src/f32-vclamp/gen/f32-vclamp-sse-u8.c", |
| "src/f32-vcmul/gen/f32-vcmul-sse-u4.c", |
| "src/f32-vcmul/gen/f32-vcmul-sse-u8.c", |
| "src/f32-vcmul/gen/f32-vcmul-sse-u12.c", |
| "src/f32-vcmul/gen/f32-vcmul-sse-u16.c", |
| "src/f32-vhswish/gen/f32-vhswish-sse-u4.c", |
| "src/f32-vhswish/gen/f32-vhswish-sse-u8.c", |
| "src/f32-vlrelu/gen/f32-vlrelu-sse-u4.c", |
| "src/f32-vlrelu/gen/f32-vlrelu-sse-u8.c", |
| "src/f32-vmulcaddc/gen/f32-vmulcaddc-c4-minmax-sse-2x.c", |
| "src/f32-vmulcaddc/gen/f32-vmulcaddc-c8-minmax-sse-2x.c", |
| "src/f32-vrelu/gen/f32-vrelu-sse-u4.c", |
| "src/f32-vrelu/gen/f32-vrelu-sse-u8.c", |
| "src/f32-vsqrt/gen/f32-vsqrt-sse-sqrt-u4.c", |
| "src/f32-vsqrt/gen/f32-vsqrt-sse-sqrt-u8.c", |
| "src/f32-vunary/gen/f32-vabs-sse-u4.c", |
| "src/f32-vunary/gen/f32-vabs-sse-u8.c", |
| "src/f32-vunary/gen/f32-vneg-sse-u4.c", |
| "src/f32-vunary/gen/f32-vneg-sse-u8.c", |
| "src/f32-vunary/gen/f32-vsqr-sse-u4.c", |
| "src/f32-vunary/gen/f32-vsqr-sse-u8.c", |
| "src/math/f32-roundd-sse-addsub.c", |
| "src/math/f32-roundne-sse-addsub.c", |
| "src/math/f32-roundu-sse-addsub.c", |
| "src/math/f32-roundz-sse-addsub.c", |
| "src/math/f32-sqrt-sse-hh1mac.c", |
| "src/math/f32-sqrt-sse-nr1mac.c", |
| "src/math/f32-sqrt-sse-nr2mac.c", |
| "src/x32-packx/x32-packx-4x-sse.c", |
| "src/x32-transposec/x32-transposec-4x4-sse.c", |
| ] |
| |
| ALL_SSE2_MICROKERNEL_SRCS = [ |
| "src/f16-f32-vcvt/gen/f16-f32-vcvt-sse2-int16-u8.c", |
| "src/f16-f32-vcvt/gen/f16-f32-vcvt-sse2-int16-u16.c", |
| "src/f16-f32-vcvt/gen/f16-f32-vcvt-sse2-int16-u24.c", |
| "src/f16-f32-vcvt/gen/f16-f32-vcvt-sse2-int16-u32.c", |
| "src/f16-f32-vcvt/gen/f16-f32-vcvt-sse2-int32-u8.c", |
| "src/f16-f32-vcvt/gen/f16-f32-vcvt-sse2-int32-u16.c", |
| "src/f16-f32-vcvt/gen/f16-f32-vcvt-sse2-int32-u24.c", |
| "src/f16-f32-vcvt/gen/f16-f32-vcvt-sse2-int32-u32.c", |
| "src/f16-vunary/gen/f16-vabs-sse2-u8.c", |
| "src/f16-vunary/gen/f16-vabs-sse2-u16.c", |
| "src/f16-vunary/gen/f16-vneg-sse2-u8.c", |
| "src/f16-vunary/gen/f16-vneg-sse2-u16.c", |
| "src/f32-argmaxpool/f32-argmaxpool-4x-sse2-c4.c", |
| "src/f32-argmaxpool/f32-argmaxpool-9p8x-sse2-c4.c", |
| "src/f32-argmaxpool/f32-argmaxpool-9x-sse2-c4.c", |
| "src/f32-f16-vcvt/gen/f32-f16-vcvt-sse2-u8.c", |
| "src/f32-f16-vcvt/gen/f32-f16-vcvt-sse2-u16.c", |
| "src/f32-f16-vcvt/gen/f32-f16-vcvt-sse2-u24.c", |
| "src/f32-f16-vcvt/gen/f32-f16-vcvt-sse2-u32.c", |
| "src/f32-gemm/gen/f32-gemm-1x8-minmax-sse2-dup.c", |
| "src/f32-gemm/gen/f32-gemm-3x8-minmax-sse2-dup.c", |
| "src/f32-gemm/gen/f32-gemm-4x8-minmax-sse2-dup.c", |
| "src/f32-gemm/gen/f32-gemm-5x8-minmax-sse2-dup.c", |
| "src/f32-gemm/gen/f32-gemm-6x8-minmax-sse2-dup.c", |
| "src/f32-gemminc/gen/f32-gemminc-1x8-minmax-sse2-dup.c", |
| "src/f32-gemminc/gen/f32-gemminc-3x8-minmax-sse2-dup.c", |
| "src/f32-gemminc/gen/f32-gemminc-4x8-minmax-sse2-dup.c", |
| "src/f32-gemminc/gen/f32-gemminc-5x8-minmax-sse2-dup.c", |
| "src/f32-gemminc/gen/f32-gemminc-6x8-minmax-sse2-dup.c", |
| "src/f32-igemm/gen/f32-igemm-1x8-minmax-sse2-dup.c", |
| "src/f32-igemm/gen/f32-igemm-3x8-minmax-sse2-dup.c", |
| "src/f32-igemm/gen/f32-igemm-4x8-minmax-sse2-dup.c", |
| "src/f32-igemm/gen/f32-igemm-5x8-minmax-sse2-dup.c", |
| "src/f32-igemm/gen/f32-igemm-6x8-minmax-sse2-dup.c", |
| "src/f32-prelu/gen/f32-prelu-sse2-2x4.c", |
| "src/f32-prelu/gen/f32-prelu-sse2-2x8.c", |
| "src/f32-qc4w-gemm/gen/f32-qc4w-gemm-1x8-minmax-sse2-dup.c", |
| "src/f32-qc4w-gemm/gen/f32-qc4w-gemm-3x8-minmax-sse2-dup.c", |
| "src/f32-qc4w-gemm/gen/f32-qc4w-gemm-4x8-minmax-sse2-dup.c", |
| "src/f32-qc4w-gemm/gen/f32-qc4w-gemm-5x8-minmax-sse2-dup.c", |
| "src/f32-qc4w-gemm/gen/f32-qc4w-gemm-6x8-minmax-sse2-dup.c", |
| "src/f32-qc8w-gemm/gen/f32-qc8w-gemm-1x8-minmax-sse2-dup.c", |
| "src/f32-qc8w-gemm/gen/f32-qc8w-gemm-1x8-minmax-sse2-load1.c", |
| "src/f32-qc8w-gemm/gen/f32-qc8w-gemm-1x8s4-minmax-sse2.c", |
| "src/f32-qc8w-gemm/gen/f32-qc8w-gemm-3x8-minmax-sse2-dup.c", |
| "src/f32-qc8w-gemm/gen/f32-qc8w-gemm-3x8-minmax-sse2-load1.c", |
| "src/f32-qc8w-gemm/gen/f32-qc8w-gemm-3x8s4-minmax-sse2.c", |
| "src/f32-qc8w-gemm/gen/f32-qc8w-gemm-4x2c4-minmax-sse2.c", |
| "src/f32-qc8w-gemm/gen/f32-qc8w-gemm-4x8-minmax-sse2-dup.c", |
| "src/f32-qc8w-gemm/gen/f32-qc8w-gemm-4x8-minmax-sse2-load1.c", |
| "src/f32-qc8w-gemm/gen/f32-qc8w-gemm-4x8s4-minmax-sse2.c", |
| "src/f32-qc8w-gemm/gen/f32-qc8w-gemm-5x8-minmax-sse2-dup.c", |
| "src/f32-qc8w-gemm/gen/f32-qc8w-gemm-5x8-minmax-sse2-load1.c", |
| "src/f32-qc8w-gemm/gen/f32-qc8w-gemm-5x8s4-minmax-sse2.c", |
| "src/f32-qc8w-gemm/gen/f32-qc8w-gemm-6x8-minmax-sse2-dup.c", |
| "src/f32-qc8w-gemm/gen/f32-qc8w-gemm-6x8-minmax-sse2-load1.c", |
| "src/f32-qc8w-gemm/gen/f32-qc8w-gemm-6x8s4-minmax-sse2.c", |
| "src/f32-qs8-vcvt/gen/f32-qs8-vcvt-sse2-u8.c", |
| "src/f32-qs8-vcvt/gen/f32-qs8-vcvt-sse2-u16.c", |
| "src/f32-qs8-vcvt/gen/f32-qs8-vcvt-sse2-u24.c", |
| "src/f32-qs8-vcvt/gen/f32-qs8-vcvt-sse2-u32.c", |
| "src/f32-qu8-vcvt/gen/f32-qu8-vcvt-sse2-u8.c", |
| "src/f32-qu8-vcvt/gen/f32-qu8-vcvt-sse2-u16.c", |
| "src/f32-qu8-vcvt/gen/f32-qu8-vcvt-sse2-u24.c", |
| "src/f32-qu8-vcvt/gen/f32-qu8-vcvt-sse2-u32.c", |
| "src/f32-raddstoreexpminusmax/gen/f32-raddstoreexpminusmax-sse2-rr2-p5-u4.c", |
| "src/f32-raddstoreexpminusmax/gen/f32-raddstoreexpminusmax-sse2-rr2-p5-u8-acc2.c", |
| "src/f32-raddstoreexpminusmax/gen/f32-raddstoreexpminusmax-sse2-rr2-p5-u8.c", |
| "src/f32-raddstoreexpminusmax/gen/f32-raddstoreexpminusmax-sse2-rr2-p5-u12-acc2.c", |
| "src/f32-raddstoreexpminusmax/gen/f32-raddstoreexpminusmax-sse2-rr2-p5-u12-acc3.c", |
| "src/f32-raddstoreexpminusmax/gen/f32-raddstoreexpminusmax-sse2-rr2-p5-u12.c", |
| "src/f32-raddstoreexpminusmax/gen/f32-raddstoreexpminusmax-sse2-rr2-p5-u16-acc2.c", |
| "src/f32-raddstoreexpminusmax/gen/f32-raddstoreexpminusmax-sse2-rr2-p5-u16-acc4.c", |
| "src/f32-raddstoreexpminusmax/gen/f32-raddstoreexpminusmax-sse2-rr2-p5-u16.c", |
| "src/f32-raddstoreexpminusmax/gen/f32-raddstoreexpminusmax-sse2-rr2-p5-u20-acc2.c", |
| "src/f32-raddstoreexpminusmax/gen/f32-raddstoreexpminusmax-sse2-rr2-p5-u20-acc5.c", |
| "src/f32-raddstoreexpminusmax/gen/f32-raddstoreexpminusmax-sse2-rr2-p5-u20.c", |
| "src/f32-velu/gen/f32-velu-sse2-rr2-lut16-p3-u4.c", |
| "src/f32-velu/gen/f32-velu-sse2-rr2-lut16-p3-u8.c", |
| "src/f32-velu/gen/f32-velu-sse2-rr2-lut16-p3-u12.c", |
| "src/f32-velu/gen/f32-velu-sse2-rr2-lut16-p3-u16.c", |
| "src/f32-velu/gen/f32-velu-sse2-rr2-lut16-p3-u20.c", |
| "src/f32-velu/gen/f32-velu-sse2-rr2-lut16-p3-u24.c", |
| "src/f32-velu/gen/f32-velu-sse2-rr2-p6-u4.c", |
| "src/f32-velu/gen/f32-velu-sse2-rr2-p6-u8.c", |
| "src/f32-velu/gen/f32-velu-sse2-rr2-p6-u12.c", |
| "src/f32-velu/gen/f32-velu-sse2-rr2-p6-u16.c", |
| "src/f32-velu/gen/f32-velu-sse2-rr2-p6-u20.c", |
| "src/f32-velu/gen/f32-velu-sse2-rr2-p6-u24.c", |
| "src/f32-vlrelu/gen/f32-vlrelu-sse2-u4.c", |
| "src/f32-vlrelu/gen/f32-vlrelu-sse2-u8.c", |
| "src/f32-vrnd/gen/f32-vrndd-sse2-u4.c", |
| "src/f32-vrnd/gen/f32-vrndd-sse2-u8.c", |
| "src/f32-vrnd/gen/f32-vrndne-sse2-u4.c", |
| "src/f32-vrnd/gen/f32-vrndne-sse2-u8.c", |
| "src/f32-vrnd/gen/f32-vrndu-sse2-u4.c", |
| "src/f32-vrnd/gen/f32-vrndu-sse2-u8.c", |
| "src/f32-vrnd/gen/f32-vrndz-sse2-u4.c", |
| "src/f32-vrnd/gen/f32-vrndz-sse2-u8.c", |
| "src/f32-vsigmoid/gen/f32-vsigmoid-sse2-rr2-lut64-p2-div-u4.c", |
| "src/f32-vsigmoid/gen/f32-vsigmoid-sse2-rr2-lut64-p2-div-u8.c", |
| "src/f32-vsigmoid/gen/f32-vsigmoid-sse2-rr2-lut64-p2-div-u12.c", |
| "src/f32-vsigmoid/gen/f32-vsigmoid-sse2-rr2-lut64-p2-div-u16.c", |
| "src/f32-vsigmoid/gen/f32-vsigmoid-sse2-rr2-lut64-p2-div-u20.c", |
| "src/f32-vsigmoid/gen/f32-vsigmoid-sse2-rr2-lut64-p2-div-u24.c", |
| "src/f32-vsigmoid/gen/f32-vsigmoid-sse2-rr2-p5-div-u4.c", |
| "src/f32-vsigmoid/gen/f32-vsigmoid-sse2-rr2-p5-div-u8.c", |
| "src/f32-vsigmoid/gen/f32-vsigmoid-sse2-rr2-p5-div-u12.c", |
| "src/f32-vsigmoid/gen/f32-vsigmoid-sse2-rr2-p5-div-u16.c", |
| "src/f32-vsigmoid/gen/f32-vsigmoid-sse2-rr2-p5-div-u20.c", |
| "src/f32-vsigmoid/gen/f32-vsigmoid-sse2-rr2-p5-div-u24.c", |
| "src/f32-vtanh/gen/f32-vtanh-sse2-expm1minus-rr1-lut8-p4h3ts-div-u4.c", |
| "src/f32-vtanh/gen/f32-vtanh-sse2-expm1minus-rr1-lut8-p4h3ts-div-u8.c", |
| "src/f32-vtanh/gen/f32-vtanh-sse2-expm1minus-rr1-lut8-p4h3ts-div-u12.c", |
| "src/f32-vtanh/gen/f32-vtanh-sse2-expm1minus-rr1-lut8-p4h3ts-div-u16.c", |
| "src/f32-vtanh/gen/f32-vtanh-sse2-expm1minus-rr1-p6h5ts-div-u4.c", |
| "src/f32-vtanh/gen/f32-vtanh-sse2-expm1minus-rr1-p6h5ts-div-u8.c", |
| "src/f32-vtanh/gen/f32-vtanh-sse2-expm1minus-rr1-p6h5ts-div-u12.c", |
| "src/f32-vtanh/gen/f32-vtanh-sse2-expm1minus-rr1-p6h5ts-div-u16.c", |
| "src/f32-vtanh/gen/f32-vtanh-sse2-expm1minus-rr1-p6h5ts-nr1-u4.c", |
| "src/f32-vtanh/gen/f32-vtanh-sse2-expm1minus-rr1-p6h5ts-nr1-u8.c", |
| "src/f32-vtanh/gen/f32-vtanh-sse2-expm1minus-rr1-p6h5ts-nr1-u12.c", |
| "src/f32-vtanh/gen/f32-vtanh-sse2-expm1minus-rr1-p6h5ts-nr1-u16.c", |
| "src/f32-vtanh/gen/f32-vtanh-sse2-expm1minus-rr1-p6h5ts-nr2-u4.c", |
| "src/f32-vtanh/gen/f32-vtanh-sse2-expm1minus-rr1-p6h5ts-nr2-u8.c", |
| "src/f32-vtanh/gen/f32-vtanh-sse2-expm1minus-rr1-p6h5ts-nr2-u12.c", |
| "src/f32-vtanh/gen/f32-vtanh-sse2-expm1minus-rr1-p6h5ts-nr2-u16.c", |
| "src/math/f16-f32-cvt-sse2-int16.c", |
| "src/math/f16-f32-cvt-sse2-int32.c", |
| "src/math/f32-exp-sse2-rr2-lut64-p2.c", |
| "src/math/f32-exp-sse2-rr2-p5.c", |
| "src/math/f32-expm1minus-sse2-rr2-lut16-p3.c", |
| "src/math/f32-expm1minus-sse2-rr2-p6.c", |
| "src/math/f32-expminus-sse2-rr2-p5.c", |
| "src/math/f32-f16-cvt-sse2.c", |
| "src/math/f32-roundd-sse2-cvt.c", |
| "src/math/f32-roundne-sse2-cvt.c", |
| "src/math/f32-roundu-sse2-cvt.c", |
| "src/math/f32-roundz-sse2-cvt.c", |
| "src/math/f32-sigmoid-sse2-rr2-lut64-p2-div.c", |
| "src/math/f32-sigmoid-sse2-rr2-lut64-p2-nr1.c", |
| "src/math/f32-sigmoid-sse2-rr2-lut64-p2-nr2.c", |
| "src/math/f32-sigmoid-sse2-rr2-p5-div.c", |
| "src/math/f32-sigmoid-sse2-rr2-p5-nr1.c", |
| "src/math/f32-sigmoid-sse2-rr2-p5-nr2.c", |
| "src/math/gen/f32-tanh-sse2-expm1minus-rr1-lut8-p4h3ps-div.c", |
| "src/math/gen/f32-tanh-sse2-expm1minus-rr1-p6h5ts-div.c", |
| "src/math/gen/f32-tanh-sse2-expm1minus-rr1-p6h5ts-nr1.c", |
| "src/math/gen/f32-tanh-sse2-expm1minus-rr1-p6h5ts-nr2.c", |
| "src/math/gen/f32-tanh-sse2-expm1minus-rr2-lut8-p4h2ts-nr1.c", |
| "src/math/gen/f32-tanh-sse2-expm1minus-rr2-lut8-p4h2ts-nr2.c", |
| "src/math/gen/f32-tanh-sse2-expm1minus-rr2-lut8-p4h3ps-nr1.c", |
| "src/math/gen/f32-tanh-sse2-expm1minus-rr2-lut8-p4h3ps-nr2.c", |
| "src/math/gen/f32-tanh-sse2-expm1minus-rr2-lut8-p4h3ts-nr1.c", |
| "src/math/gen/f32-tanh-sse2-expm1minus-rr2-lut8-p4h3ts-nr2.c", |
| "src/qd8-f32-qc8w-gemm/gen/qd8-f32-qc8w-gemm-1x4c8-minmax-sse2-ld64.c", |
| "src/qd8-f32-qc8w-gemm/gen/qd8-f32-qc8w-gemm-1x4c8-minmax-sse2-ld128.c", |
| "src/qd8-f32-qc8w-gemm/gen/qd8-f32-qc8w-gemm-2x4c8-minmax-sse2-ld64.c", |
| "src/qd8-f32-qc8w-gemm/gen/qd8-f32-qc8w-gemm-2x4c8-minmax-sse2-ld128.c", |
| "src/qd8-f32-qc8w-gemm/gen/qd8-f32-qc8w-gemm-3x4c8-minmax-sse2-ld64.c", |
| "src/qd8-f32-qc8w-gemm/gen/qd8-f32-qc8w-gemm-3x4c8-minmax-sse2-ld128.c", |
| "src/qd8-f32-qc8w-gemm/gen/qd8-f32-qc8w-gemm-4x4c8-minmax-sse2-ld64.c", |
| "src/qd8-f32-qc8w-gemm/gen/qd8-f32-qc8w-gemm-4x4c8-minmax-sse2-ld128.c", |
| "src/qs8-dwconv/gen/qs8-dwconv-5f5m5l8c8s8r-minmax-fp32-sse2-mul16-add16.c", |
| "src/qs8-dwconv/gen/qs8-dwconv-5f5m5l8c8s8r-minmax-fp32-sse2-mul16.c", |
| "src/qs8-dwconv/gen/qs8-dwconv-5f5m5l16c8s8r-minmax-fp32-sse2-mul16-add16.c", |
| "src/qs8-dwconv/gen/qs8-dwconv-5f5m5l16c8s8r-minmax-fp32-sse2-mul16.c", |
| "src/qs8-dwconv/gen/qs8-dwconv-6f6m7l8c8s8r-minmax-fp32-sse2-mul16-add16.c", |
| "src/qs8-dwconv/gen/qs8-dwconv-6f6m7l8c8s8r-minmax-fp32-sse2-mul16.c", |
| "src/qs8-dwconv/gen/qs8-dwconv-6f6m7l16c8s8r-minmax-fp32-sse2-mul16-add16.c", |
| "src/qs8-dwconv/gen/qs8-dwconv-6f6m7l16c8s8r-minmax-fp32-sse2-mul16.c", |
| "src/qs8-dwconv/gen/qs8-dwconv-8f8m9l8c8s8r-minmax-fp32-sse2-mul16-add16.c", |
| "src/qs8-dwconv/gen/qs8-dwconv-8f8m9l8c8s8r-minmax-fp32-sse2-mul16.c", |
| "src/qs8-dwconv/gen/qs8-dwconv-8f8m9l16c8s8r-minmax-fp32-sse2-mul16-add16.c", |
| "src/qs8-dwconv/gen/qs8-dwconv-8f8m9l16c8s8r-minmax-fp32-sse2-mul16.c", |
| "src/qs8-dwconv/gen/qs8-dwconv-9p8c-minmax-fp32-sse2-mul16-add16.c", |
| "src/qs8-dwconv/gen/qs8-dwconv-9p8c-minmax-fp32-sse2-mul16.c", |
| "src/qs8-dwconv/gen/qs8-dwconv-9p16c-minmax-fp32-sse2-mul16-add16.c", |
| "src/qs8-dwconv/gen/qs8-dwconv-9p16c-minmax-fp32-sse2-mul16.c", |
| "src/qs8-dwconv/gen/qs8-dwconv-25p8c-minmax-fp32-sse2-mul16-add16.c", |
| "src/qs8-dwconv/gen/qs8-dwconv-25p8c-minmax-fp32-sse2-mul16.c", |
| "src/qs8-dwconv/gen/qs8-dwconv-25p16c-minmax-fp32-sse2-mul16-add16.c", |
| "src/qs8-dwconv/gen/qs8-dwconv-25p16c-minmax-fp32-sse2-mul16.c", |
| "src/qs8-f32-vcvt/gen/qs8-f32-vcvt-sse2-u8.c", |
| "src/qs8-f32-vcvt/gen/qs8-f32-vcvt-sse2-u16.c", |
| "src/qs8-f32-vcvt/gen/qs8-f32-vcvt-sse2-u24.c", |
| "src/qs8-f32-vcvt/gen/qs8-f32-vcvt-sse2-u32.c", |
| "src/qs8-gavgpool/gen/qs8-gavgpool-7p7x-minmax-fp32-sse2-c8.c", |
| "src/qs8-gavgpool/gen/qs8-gavgpool-7p7x-minmax-fp32-sse2-c16.c", |
| "src/qs8-gavgpool/gen/qs8-gavgpool-7p7x-minmax-fp32-sse2-c24.c", |
| "src/qs8-gavgpool/gen/qs8-gavgpool-7x-minmax-fp32-sse2-c8.c", |
| "src/qs8-gavgpool/gen/qs8-gavgpool-7x-minmax-fp32-sse2-c16.c", |
| "src/qs8-gavgpool/gen/qs8-gavgpool-7x-minmax-fp32-sse2-c24.c", |
| "src/qs8-gemm/gen/qs8-gemm-1x4c2-minmax-fp32-sse2-ld64.c", |
| "src/qs8-gemm/gen/qs8-gemm-1x4c2-minmax-fp32-sse2-ld128.c", |
| "src/qs8-gemm/gen/qs8-gemm-1x4c2-xw-minmax-fp32-sse2.c", |
| "src/qs8-gemm/gen/qs8-gemm-1x4c2s4-minmax-fp32-sse2-ld64.c", |
| "src/qs8-gemm/gen/qs8-gemm-1x4c2s4-minmax-fp32-sse2-ld128.c", |
| "src/qs8-gemm/gen/qs8-gemm-1x4c2s4-xw-minmax-fp32-sse2.c", |
| "src/qs8-gemm/gen/qs8-gemm-1x4c8-minmax-fp32-sse2-ld64.c", |
| "src/qs8-gemm/gen/qs8-gemm-1x4c8-minmax-fp32-sse2-ld128.c", |
| "src/qs8-gemm/gen/qs8-gemm-1x4c8-xw-minmax-fp32-sse2.c", |
| "src/qs8-gemm/gen/qs8-gemm-2x4c2-minmax-fp32-sse2-ld64.c", |
| "src/qs8-gemm/gen/qs8-gemm-2x4c2-minmax-fp32-sse2-ld128.c", |
| "src/qs8-gemm/gen/qs8-gemm-2x4c2-xw-minmax-fp32-sse2.c", |
| "src/qs8-gemm/gen/qs8-gemm-2x4c2s4-minmax-fp32-sse2-ld64.c", |
| "src/qs8-gemm/gen/qs8-gemm-2x4c2s4-minmax-fp32-sse2-ld128.c", |
| "src/qs8-gemm/gen/qs8-gemm-2x4c2s4-xw-minmax-fp32-sse2.c", |
| "src/qs8-gemm/gen/qs8-gemm-2x4c8-minmax-fp32-sse2-ld64.c", |
| "src/qs8-gemm/gen/qs8-gemm-2x4c8-minmax-fp32-sse2-ld128.c", |
| "src/qs8-gemm/gen/qs8-gemm-2x4c8-xw-minmax-fp32-sse2.c", |
| "src/qs8-gemm/gen/qs8-gemm-3x4c2-minmax-fp32-sse2-ld64.c", |
| "src/qs8-gemm/gen/qs8-gemm-3x4c2-minmax-fp32-sse2-ld128.c", |
| "src/qs8-gemm/gen/qs8-gemm-3x4c2-xw-minmax-fp32-sse2.c", |
| "src/qs8-gemm/gen/qs8-gemm-3x4c2s4-minmax-fp32-sse2-ld64.c", |
| "src/qs8-gemm/gen/qs8-gemm-3x4c2s4-minmax-fp32-sse2-ld128.c", |
| "src/qs8-gemm/gen/qs8-gemm-3x4c2s4-xw-minmax-fp32-sse2.c", |
| "src/qs8-gemm/gen/qs8-gemm-3x4c8-minmax-fp32-sse2-ld64.c", |
| "src/qs8-gemm/gen/qs8-gemm-3x4c8-minmax-fp32-sse2-ld128.c", |
| "src/qs8-gemm/gen/qs8-gemm-3x4c8-xw-minmax-fp32-sse2.c", |
| "src/qs8-gemm/gen/qs8-gemm-4x4c2-minmax-fp32-sse2-ld64.c", |
| "src/qs8-gemm/gen/qs8-gemm-4x4c2-minmax-fp32-sse2-ld128.c", |
| "src/qs8-gemm/gen/qs8-gemm-4x4c2-xw-minmax-fp32-sse2.c", |
| "src/qs8-gemm/gen/qs8-gemm-4x4c2s4-minmax-fp32-sse2-ld64.c", |
| "src/qs8-gemm/gen/qs8-gemm-4x4c2s4-minmax-fp32-sse2-ld128.c", |
| "src/qs8-gemm/gen/qs8-gemm-4x4c2s4-xw-minmax-fp32-sse2.c", |
| "src/qs8-igemm/gen/qs8-igemm-1x4c2-minmax-fp32-sse2-ld64.c", |
| "src/qs8-igemm/gen/qs8-igemm-1x4c2-minmax-fp32-sse2-ld128.c", |
| "src/qs8-igemm/gen/qs8-igemm-1x4c2s4-minmax-fp32-sse2-ld64.c", |
| "src/qs8-igemm/gen/qs8-igemm-1x4c2s4-minmax-fp32-sse2-ld128.c", |
| "src/qs8-igemm/gen/qs8-igemm-1x4c8-minmax-fp32-sse2-ld64.c", |
| "src/qs8-igemm/gen/qs8-igemm-1x4c8-minmax-fp32-sse2-ld128.c", |
| "src/qs8-igemm/gen/qs8-igemm-2x4c2-minmax-fp32-sse2-ld64.c", |
| "src/qs8-igemm/gen/qs8-igemm-2x4c2-minmax-fp32-sse2-ld128.c", |
| "src/qs8-igemm/gen/qs8-igemm-2x4c2s4-minmax-fp32-sse2-ld64.c", |
| "src/qs8-igemm/gen/qs8-igemm-2x4c2s4-minmax-fp32-sse2-ld128.c", |
| "src/qs8-igemm/gen/qs8-igemm-2x4c8-minmax-fp32-sse2-ld64.c", |
| "src/qs8-igemm/gen/qs8-igemm-2x4c8-minmax-fp32-sse2-ld128.c", |
| "src/qs8-igemm/gen/qs8-igemm-3x4c2-minmax-fp32-sse2-ld64.c", |
| "src/qs8-igemm/gen/qs8-igemm-3x4c2-minmax-fp32-sse2-ld128.c", |
| "src/qs8-igemm/gen/qs8-igemm-3x4c2s4-minmax-fp32-sse2-ld64.c", |
| "src/qs8-igemm/gen/qs8-igemm-3x4c2s4-minmax-fp32-sse2-ld128.c", |
| "src/qs8-igemm/gen/qs8-igemm-3x4c8-minmax-fp32-sse2-ld64.c", |
| "src/qs8-igemm/gen/qs8-igemm-3x4c8-minmax-fp32-sse2-ld128.c", |
| "src/qs8-igemm/gen/qs8-igemm-4x4c2-minmax-fp32-sse2-ld64.c", |
| "src/qs8-igemm/gen/qs8-igemm-4x4c2-minmax-fp32-sse2-ld128.c", |
| "src/qs8-igemm/gen/qs8-igemm-4x4c2s4-minmax-fp32-sse2-ld64.c", |
| "src/qs8-igemm/gen/qs8-igemm-4x4c2s4-minmax-fp32-sse2-ld128.c", |
| "src/qs8-qc8w-dwconv/gen/qs8-qc8w-dwconv-3p8c-minmax-fp32-sse2-mul16.c", |
| "src/qs8-qc8w-dwconv/gen/qs8-qc8w-dwconv-5f5m5l8c8s8r-minmax-fp32-sse2-mul16-add16.c", |
| "src/qs8-qc8w-dwconv/gen/qs8-qc8w-dwconv-5f5m5l8c8s8r-minmax-fp32-sse2-mul16.c", |
| "src/qs8-qc8w-dwconv/gen/qs8-qc8w-dwconv-5f5m5l16c8s8r-minmax-fp32-sse2-mul16-add16.c", |
| "src/qs8-qc8w-dwconv/gen/qs8-qc8w-dwconv-5f5m5l16c8s8r-minmax-fp32-sse2-mul16.c", |
| "src/qs8-qc8w-dwconv/gen/qs8-qc8w-dwconv-6f6m7l8c8s8r-minmax-fp32-sse2-mul16-add16.c", |
| "src/qs8-qc8w-dwconv/gen/qs8-qc8w-dwconv-6f6m7l8c8s8r-minmax-fp32-sse2-mul16.c", |
| "src/qs8-qc8w-dwconv/gen/qs8-qc8w-dwconv-6f6m7l16c8s8r-minmax-fp32-sse2-mul16-add16.c", |
| "src/qs8-qc8w-dwconv/gen/qs8-qc8w-dwconv-6f6m7l16c8s8r-minmax-fp32-sse2-mul16.c", |
| "src/qs8-qc8w-dwconv/gen/qs8-qc8w-dwconv-8f8m9l8c8s8r-minmax-fp32-sse2-mul16-add16.c", |
| "src/qs8-qc8w-dwconv/gen/qs8-qc8w-dwconv-8f8m9l8c8s8r-minmax-fp32-sse2-mul16.c", |
| "src/qs8-qc8w-dwconv/gen/qs8-qc8w-dwconv-8f8m9l16c8s8r-minmax-fp32-sse2-mul16-add16.c", |
| "src/qs8-qc8w-dwconv/gen/qs8-qc8w-dwconv-8f8m9l16c8s8r-minmax-fp32-sse2-mul16.c", |
| "src/qs8-qc8w-dwconv/gen/qs8-qc8w-dwconv-9p8c-minmax-fp32-sse2-mul16-add16.c", |
| "src/qs8-qc8w-dwconv/gen/qs8-qc8w-dwconv-9p8c-minmax-fp32-sse2-mul16.c", |
| "src/qs8-qc8w-dwconv/gen/qs8-qc8w-dwconv-9p16c-minmax-fp32-sse2-mul16-add16.c", |
| "src/qs8-qc8w-dwconv/gen/qs8-qc8w-dwconv-9p16c-minmax-fp32-sse2-mul16.c", |
| "src/qs8-qc8w-dwconv/gen/qs8-qc8w-dwconv-25p8c-minmax-fp32-sse2-mul16-add16.c", |
| "src/qs8-qc8w-dwconv/gen/qs8-qc8w-dwconv-25p8c-minmax-fp32-sse2-mul16.c", |
| "src/qs8-qc8w-dwconv/gen/qs8-qc8w-dwconv-25p16c-minmax-fp32-sse2-mul16-add16.c", |
| "src/qs8-qc8w-dwconv/gen/qs8-qc8w-dwconv-25p16c-minmax-fp32-sse2-mul16.c", |
| "src/qs8-qc8w-gemm/gen/qs8-qc8w-gemm-1x4c2-minmax-fp32-sse2-ld64.c", |
| "src/qs8-qc8w-gemm/gen/qs8-qc8w-gemm-1x4c2-minmax-fp32-sse2-ld128.c", |
| "src/qs8-qc8w-gemm/gen/qs8-qc8w-gemm-1x4c2s4-minmax-fp32-sse2-ld64.c", |
| "src/qs8-qc8w-gemm/gen/qs8-qc8w-gemm-1x4c2s4-minmax-fp32-sse2-ld128.c", |
| "src/qs8-qc8w-gemm/gen/qs8-qc8w-gemm-1x4c8-minmax-fp32-sse2-ld64.c", |
| "src/qs8-qc8w-gemm/gen/qs8-qc8w-gemm-1x4c8-minmax-fp32-sse2-ld128.c", |
| "src/qs8-qc8w-gemm/gen/qs8-qc8w-gemm-2x4c2-minmax-fp32-sse2-ld64.c", |
| "src/qs8-qc8w-gemm/gen/qs8-qc8w-gemm-2x4c2-minmax-fp32-sse2-ld128.c", |
| "src/qs8-qc8w-gemm/gen/qs8-qc8w-gemm-2x4c2s4-minmax-fp32-sse2-ld64.c", |
| "src/qs8-qc8w-gemm/gen/qs8-qc8w-gemm-2x4c2s4-minmax-fp32-sse2-ld128.c", |
| "src/qs8-qc8w-gemm/gen/qs8-qc8w-gemm-2x4c8-minmax-fp32-sse2-ld64.c", |
| "src/qs8-qc8w-gemm/gen/qs8-qc8w-gemm-2x4c8-minmax-fp32-sse2-ld128.c", |
| "src/qs8-qc8w-gemm/gen/qs8-qc8w-gemm-3x4c2-minmax-fp32-sse2-ld64.c", |
| "src/qs8-qc8w-gemm/gen/qs8-qc8w-gemm-3x4c2-minmax-fp32-sse2-ld128.c", |
| "src/qs8-qc8w-gemm/gen/qs8-qc8w-gemm-3x4c2s4-minmax-fp32-sse2-ld64.c", |
| "src/qs8-qc8w-gemm/gen/qs8-qc8w-gemm-3x4c2s4-minmax-fp32-sse2-ld128.c", |
| "src/qs8-qc8w-gemm/gen/qs8-qc8w-gemm-3x4c8-minmax-fp32-sse2-ld64.c", |
| "src/qs8-qc8w-gemm/gen/qs8-qc8w-gemm-3x4c8-minmax-fp32-sse2-ld128.c", |
| "src/qs8-qc8w-gemm/gen/qs8-qc8w-gemm-4x4c2-minmax-fp32-sse2-ld64.c", |
| "src/qs8-qc8w-gemm/gen/qs8-qc8w-gemm-4x4c2-minmax-fp32-sse2-ld128.c", |
| "src/qs8-qc8w-gemm/gen/qs8-qc8w-gemm-4x4c2s4-minmax-fp32-sse2-ld64.c", |
| "src/qs8-qc8w-gemm/gen/qs8-qc8w-gemm-4x4c2s4-minmax-fp32-sse2-ld128.c", |
| "src/qs8-qc8w-igemm/gen/qs8-qc8w-igemm-1x4c2-minmax-fp32-sse2-ld64.c", |
| "src/qs8-qc8w-igemm/gen/qs8-qc8w-igemm-1x4c2-minmax-fp32-sse2-ld128.c", |
| "src/qs8-qc8w-igemm/gen/qs8-qc8w-igemm-1x4c2s4-minmax-fp32-sse2-ld64.c", |
| "src/qs8-qc8w-igemm/gen/qs8-qc8w-igemm-1x4c2s4-minmax-fp32-sse2-ld128.c", |
| "src/qs8-qc8w-igemm/gen/qs8-qc8w-igemm-1x4c8-minmax-fp32-sse2-ld64.c", |
| "src/qs8-qc8w-igemm/gen/qs8-qc8w-igemm-1x4c8-minmax-fp32-sse2-ld128.c", |
| "src/qs8-qc8w-igemm/gen/qs8-qc8w-igemm-2x4c2-minmax-fp32-sse2-ld64.c", |
| "src/qs8-qc8w-igemm/gen/qs8-qc8w-igemm-2x4c2-minmax-fp32-sse2-ld128.c", |
| "src/qs8-qc8w-igemm/gen/qs8-qc8w-igemm-2x4c2s4-minmax-fp32-sse2-ld64.c", |
| "src/qs8-qc8w-igemm/gen/qs8-qc8w-igemm-2x4c2s4-minmax-fp32-sse2-ld128.c", |
| "src/qs8-qc8w-igemm/gen/qs8-qc8w-igemm-2x4c8-minmax-fp32-sse2-ld64.c", |
| "src/qs8-qc8w-igemm/gen/qs8-qc8w-igemm-2x4c8-minmax-fp32-sse2-ld128.c", |
| "src/qs8-qc8w-igemm/gen/qs8-qc8w-igemm-3x4c2-minmax-fp32-sse2-ld64.c", |
| "src/qs8-qc8w-igemm/gen/qs8-qc8w-igemm-3x4c2-minmax-fp32-sse2-ld128.c", |
| "src/qs8-qc8w-igemm/gen/qs8-qc8w-igemm-3x4c2s4-minmax-fp32-sse2-ld64.c", |
| "src/qs8-qc8w-igemm/gen/qs8-qc8w-igemm-3x4c2s4-minmax-fp32-sse2-ld128.c", |
| "src/qs8-qc8w-igemm/gen/qs8-qc8w-igemm-3x4c8-minmax-fp32-sse2-ld64.c", |
| "src/qs8-qc8w-igemm/gen/qs8-qc8w-igemm-3x4c8-minmax-fp32-sse2-ld128.c", |
| "src/qs8-qc8w-igemm/gen/qs8-qc8w-igemm-4x4c2-minmax-fp32-sse2-ld64.c", |
| "src/qs8-qc8w-igemm/gen/qs8-qc8w-igemm-4x4c2-minmax-fp32-sse2-ld128.c", |
| "src/qs8-qc8w-igemm/gen/qs8-qc8w-igemm-4x4c2s4-minmax-fp32-sse2-ld64.c", |
| "src/qs8-qc8w-igemm/gen/qs8-qc8w-igemm-4x4c2s4-minmax-fp32-sse2-ld128.c", |
| "src/qs8-requantization/qs8-requantization-fp32-sse2.c", |
| "src/qs8-requantization/qs8-requantization-gemmlowp-sse2.c", |
| "src/qs8-requantization/qs8-requantization-rndna-sse2.c", |
| "src/qs8-vadd/gen/qs8-vadd-minmax-sse2-mul16-ld64-u8.c", |
| "src/qs8-vadd/gen/qs8-vadd-minmax-sse2-mul16-ld64-u16.c", |
| "src/qs8-vadd/gen/qs8-vadd-minmax-sse2-mul16-ld64-u24.c", |
| "src/qs8-vadd/gen/qs8-vadd-minmax-sse2-mul16-ld64-u32.c", |
| "src/qs8-vaddc/gen/qs8-vaddc-minmax-sse2-mul16-ld64-u8.c", |
| "src/qs8-vaddc/gen/qs8-vaddc-minmax-sse2-mul16-ld64-u16.c", |
| "src/qs8-vaddc/gen/qs8-vaddc-minmax-sse2-mul16-ld64-u24.c", |
| "src/qs8-vaddc/gen/qs8-vaddc-minmax-sse2-mul16-ld64-u32.c", |
| "src/qs8-vcvt/gen/qs8-vcvt-sse2-u16.c", |
| "src/qs8-vcvt/gen/qs8-vcvt-sse2-u32.c", |
| "src/qs8-vlrelu/gen/qs8-vlrelu-sse2-u16.c", |
| "src/qs8-vlrelu/gen/qs8-vlrelu-sse2-u32.c", |
| "src/qs8-vmul/gen/qs8-vmul-minmax-fp32-sse2-mul16-ld64-u8.c", |
| "src/qs8-vmul/gen/qs8-vmul-minmax-fp32-sse2-mul16-ld64-u16.c", |
| "src/qs8-vmulc/gen/qs8-vmulc-minmax-fp32-sse2-mul16-ld64-u8.c", |
| "src/qs8-vmulc/gen/qs8-vmulc-minmax-fp32-sse2-mul16-ld64-u16.c", |
| "src/qs16-qs8-vcvt/gen/qs16-qs8-vcvt-sse2-u4.c", |
| "src/qs16-qs8-vcvt/gen/qs16-qs8-vcvt-sse2-u8.c", |
| "src/qs16-qs8-vcvt/gen/qs16-qs8-vcvt-sse2-u16.c", |
| "src/qu8-avgpool/qu8-avgpool-9p8x-minmax-fp32-sse2-c8.c", |
| "src/qu8-avgpool/qu8-avgpool-9x-minmax-fp32-sse2-c8.c", |
| "src/qu8-dwconv/gen/qu8-dwconv-5f5m5l8c8s8r-minmax-fp32-sse2-mul16.c", |
| "src/qu8-dwconv/gen/qu8-dwconv-5f5m5l16c8s8r-minmax-fp32-sse2-mul16.c", |
| "src/qu8-dwconv/gen/qu8-dwconv-6f6m7l8c8s8r-minmax-fp32-sse2-mul16.c", |
| "src/qu8-dwconv/gen/qu8-dwconv-6f6m7l16c8s8r-minmax-fp32-sse2-mul16.c", |
| "src/qu8-dwconv/gen/qu8-dwconv-8f8m9l8c8s8r-minmax-fp32-sse2-mul16.c", |
| "src/qu8-dwconv/gen/qu8-dwconv-8f8m9l16c8s8r-minmax-fp32-sse2-mul16.c", |
| "src/qu8-dwconv/gen/qu8-dwconv-9p8c-minmax-fp32-sse2-mul16.c", |
| "src/qu8-dwconv/gen/qu8-dwconv-9p16c-minmax-fp32-sse2-mul16.c", |
| "src/qu8-dwconv/gen/qu8-dwconv-25p8c-minmax-fp32-sse2-mul16.c", |
| "src/qu8-dwconv/gen/qu8-dwconv-25p16c-minmax-fp32-sse2-mul16.c", |
| "src/qu8-f32-vcvt/gen/qu8-f32-vcvt-sse2-u8.c", |
| "src/qu8-f32-vcvt/gen/qu8-f32-vcvt-sse2-u16.c", |
| "src/qu8-f32-vcvt/gen/qu8-f32-vcvt-sse2-u24.c", |
| "src/qu8-f32-vcvt/gen/qu8-f32-vcvt-sse2-u32.c", |
| "src/qu8-gavgpool/gen/qu8-gavgpool-7p7x-minmax-fp32-sse2-c8.c", |
| "src/qu8-gavgpool/gen/qu8-gavgpool-7p7x-minmax-fp32-sse2-c16.c", |
| "src/qu8-gavgpool/gen/qu8-gavgpool-7p7x-minmax-fp32-sse2-c24.c", |
| "src/qu8-gavgpool/gen/qu8-gavgpool-7x-minmax-fp32-sse2-c8.c", |
| "src/qu8-gavgpool/gen/qu8-gavgpool-7x-minmax-fp32-sse2-c16.c", |
| "src/qu8-gavgpool/gen/qu8-gavgpool-7x-minmax-fp32-sse2-c24.c", |
| "src/qu8-gemm/gen/qu8-gemm-1x4c2-minmax-fp32-sse2-ld64.c", |
| "src/qu8-gemm/gen/qu8-gemm-1x4c2-minmax-fp32-sse2-ld128.c", |
| "src/qu8-gemm/gen/qu8-gemm-1x4c2s4-minmax-fp32-sse2-ld64.c", |
| "src/qu8-gemm/gen/qu8-gemm-1x4c2s4-minmax-fp32-sse2-ld128.c", |
| "src/qu8-gemm/gen/qu8-gemm-1x4c8-minmax-fp32-sse2-ld64.c", |
| "src/qu8-gemm/gen/qu8-gemm-1x4c8-minmax-fp32-sse2-ld128.c", |
| "src/qu8-gemm/gen/qu8-gemm-2x4c2-minmax-fp32-sse2-ld64.c", |
| "src/qu8-gemm/gen/qu8-gemm-2x4c2-minmax-fp32-sse2-ld128.c", |
| "src/qu8-gemm/gen/qu8-gemm-2x4c2s4-minmax-fp32-sse2-ld64.c", |
| "src/qu8-gemm/gen/qu8-gemm-2x4c2s4-minmax-fp32-sse2-ld128.c", |
| "src/qu8-gemm/gen/qu8-gemm-2x4c8-minmax-fp32-sse2-ld64.c", |
| "src/qu8-gemm/gen/qu8-gemm-2x4c8-minmax-fp32-sse2-ld128.c", |
| "src/qu8-gemm/gen/qu8-gemm-3x4c2-minmax-fp32-sse2-ld64.c", |
| "src/qu8-gemm/gen/qu8-gemm-3x4c2-minmax-fp32-sse2-ld128.c", |
| "src/qu8-gemm/gen/qu8-gemm-3x4c2s4-minmax-fp32-sse2-ld64.c", |
| "src/qu8-gemm/gen/qu8-gemm-3x4c2s4-minmax-fp32-sse2-ld128.c", |
| "src/qu8-gemm/gen/qu8-gemm-3x4c8-minmax-fp32-sse2-ld64.c", |
| "src/qu8-gemm/gen/qu8-gemm-3x4c8-minmax-fp32-sse2-ld128.c", |
| "src/qu8-gemm/gen/qu8-gemm-4x4c2-minmax-fp32-sse2-ld64.c", |
| "src/qu8-gemm/gen/qu8-gemm-4x4c2-minmax-fp32-sse2-ld128.c", |
| "src/qu8-gemm/gen/qu8-gemm-4x4c2s4-minmax-fp32-sse2-ld64.c", |
| "src/qu8-gemm/gen/qu8-gemm-4x4c2s4-minmax-fp32-sse2-ld128.c", |
| "src/qu8-igemm/gen/qu8-igemm-1x4c2-minmax-fp32-sse2-ld64.c", |
| "src/qu8-igemm/gen/qu8-igemm-1x4c2-minmax-fp32-sse2-ld128.c", |
| "src/qu8-igemm/gen/qu8-igemm-1x4c2s4-minmax-fp32-sse2-ld64.c", |
| "src/qu8-igemm/gen/qu8-igemm-1x4c2s4-minmax-fp32-sse2-ld128.c", |
| "src/qu8-igemm/gen/qu8-igemm-1x4c8-minmax-fp32-sse2-ld64.c", |
| "src/qu8-igemm/gen/qu8-igemm-1x4c8-minmax-fp32-sse2-ld128.c", |
| "src/qu8-igemm/gen/qu8-igemm-2x4c2-minmax-fp32-sse2-ld64.c", |
| "src/qu8-igemm/gen/qu8-igemm-2x4c2-minmax-fp32-sse2-ld128.c", |
| "src/qu8-igemm/gen/qu8-igemm-2x4c2s4-minmax-fp32-sse2-ld64.c", |
| "src/qu8-igemm/gen/qu8-igemm-2x4c2s4-minmax-fp32-sse2-ld128.c", |
| "src/qu8-igemm/gen/qu8-igemm-2x4c8-minmax-fp32-sse2-ld64.c", |
| "src/qu8-igemm/gen/qu8-igemm-2x4c8-minmax-fp32-sse2-ld128.c", |
| "src/qu8-igemm/gen/qu8-igemm-3x4c2-minmax-fp32-sse2-ld64.c", |
| "src/qu8-igemm/gen/qu8-igemm-3x4c2-minmax-fp32-sse2-ld128.c", |
| "src/qu8-igemm/gen/qu8-igemm-3x4c2s4-minmax-fp32-sse2-ld64.c", |
| "src/qu8-igemm/gen/qu8-igemm-3x4c2s4-minmax-fp32-sse2-ld128.c", |
| "src/qu8-igemm/gen/qu8-igemm-3x4c8-minmax-fp32-sse2-ld64.c", |
| "src/qu8-igemm/gen/qu8-igemm-3x4c8-minmax-fp32-sse2-ld128.c", |
| "src/qu8-igemm/gen/qu8-igemm-4x4c2-minmax-fp32-sse2-ld64.c", |
| "src/qu8-igemm/gen/qu8-igemm-4x4c2-minmax-fp32-sse2-ld128.c", |
| "src/qu8-igemm/gen/qu8-igemm-4x4c2s4-minmax-fp32-sse2-ld64.c", |
| "src/qu8-igemm/gen/qu8-igemm-4x4c2s4-minmax-fp32-sse2-ld128.c", |
| "src/qu8-requantization/qu8-requantization-fp32-sse2.c", |
| "src/qu8-requantization/qu8-requantization-gemmlowp-sse2.c", |
| "src/qu8-requantization/qu8-requantization-rndna-sse2.c", |
| "src/qu8-vadd/gen/qu8-vadd-minmax-sse2-mul16-ld64-u8.c", |
| "src/qu8-vadd/gen/qu8-vadd-minmax-sse2-mul16-ld64-u16.c", |
| "src/qu8-vaddc/gen/qu8-vaddc-minmax-sse2-mul16-ld64-u8.c", |
| "src/qu8-vaddc/gen/qu8-vaddc-minmax-sse2-mul16-ld64-u16.c", |
| "src/qu8-vcvt/gen/qu8-vcvt-sse2-u16.c", |
| "src/qu8-vcvt/gen/qu8-vcvt-sse2-u32.c", |
| "src/qu8-vlrelu/gen/qu8-vlrelu-sse2-u16.c", |
| "src/qu8-vlrelu/gen/qu8-vlrelu-sse2-u32.c", |
| "src/qu8-vmul/gen/qu8-vmul-minmax-fp32-sse2-mul16-ld64-u8.c", |
| "src/qu8-vmul/gen/qu8-vmul-minmax-fp32-sse2-mul16-ld64-u16.c", |
| "src/qu8-vmul/gen/qu8-vmul-minmax-fp32-sse2-mul16-ld64-x16.c", |
| "src/qu8-vmulc/gen/qu8-vmulc-minmax-fp32-sse2-mul16-ld64-u8.c", |
| "src/qu8-vmulc/gen/qu8-vmulc-minmax-fp32-sse2-mul16-ld64-u16.c", |
| "src/s8-ibilinear/gen/s8-ibilinear-sse2-c8.c", |
| "src/s8-ibilinear/gen/s8-ibilinear-sse2-c16.c", |
| "src/s8-maxpool/s8-maxpool-9p8x-minmax-sse2-c16.c", |
| "src/s8-vclamp/s8-vclamp-sse2-u64.c", |
| "src/u8-ibilinear/gen/u8-ibilinear-sse2-c8.c", |
| "src/u8-ibilinear/gen/u8-ibilinear-sse2-c16.c", |
| "src/u8-maxpool/u8-maxpool-9p8x-minmax-sse2-c16.c", |
| "src/u8-rmax/u8-rmax-sse2.c", |
| "src/u8-vclamp/u8-vclamp-sse2-u64.c", |
| "src/x8-transposec/gen/x8-transposec-16x16-reuse-mov-sse2.c", |
| "src/x8-transposec/gen/x8-transposec-16x16-reuse-switch-sse2.c", |
| "src/x8-zip/x8-zip-x2-sse2.c", |
| "src/x8-zip/x8-zip-x3-sse2.c", |
| "src/x8-zip/x8-zip-x4-sse2.c", |
| "src/x8-zip/x8-zip-xm-sse2.c", |
| "src/x16-transposec/gen/x16-transposec-8x8-multi-mov-sse2.c", |
| "src/x16-transposec/gen/x16-transposec-8x8-multi-switch-sse2.c", |
| "src/x16-transposec/gen/x16-transposec-8x8-reuse-mov-sse2.c", |
| "src/x16-transposec/gen/x16-transposec-8x8-reuse-multi-sse2.c", |
| "src/x16-transposec/gen/x16-transposec-8x8-reuse-switch-sse2.c", |
| "src/x16-transposec/x16-transposec-4x8-sse2.c", |
| "src/x32-packw/gen/x32-packw-x2c4-gemm-goi-sse2-u4-prfm.c", |
| "src/x32-packw/gen/x32-packw-x2c4-gemm-goi-sse2-u4.c", |
| "src/x32-packw/gen/x32-packw-x8-gemm-goi-sse2-u4-prfm.c", |
| "src/x32-packw/gen/x32-packw-x8-gemm-goi-sse2-u4.c", |
| "src/x32-packw/gen/x32-packw-x8-gemm-goi-sse2-u8-prfm.c", |
| "src/x32-packw/gen/x32-packw-x8-gemm-goi-sse2-u8.c", |
| "src/x32-packw/gen/x32-packw-x8s4-gemm-goi-sse2-u4-prfm.c", |
| "src/x32-packw/gen/x32-packw-x8s4-gemm-goi-sse2-u4.c", |
| "src/x32-packw/gen/x32-packw-x8s4-gemm-goi-sse2-u8-prfm.c", |
| "src/x32-packw/gen/x32-packw-x8s4-gemm-goi-sse2-u8.c", |
| "src/x32-packw/gen/x32-packw-x16-gemm-goi-sse2-u4-prfm.c", |
| "src/x32-packw/gen/x32-packw-x16-gemm-goi-sse2-u4.c", |
| "src/x32-packw/gen/x32-packw-x16-gemm-goi-sse2-u8-prfm.c", |
| "src/x32-packw/gen/x32-packw-x16-gemm-goi-sse2-u8.c", |
| "src/x32-packw/gen/x32-packw-x16s4-gemm-goi-sse2-u4-prfm.c", |
| "src/x32-packw/gen/x32-packw-x16s4-gemm-goi-sse2-u4.c", |
| "src/x32-packw/gen/x32-packw-x16s4-gemm-goi-sse2-u8-prfm.c", |
| "src/x32-packw/gen/x32-packw-x16s4-gemm-goi-sse2-u8.c", |
| "src/x32-transposec/gen/x32-transposec-4x4-multi-mov-sse2.c", |
| "src/x32-transposec/gen/x32-transposec-4x4-multi-multi-sse2.c", |
| "src/x32-transposec/gen/x32-transposec-4x4-multi-switch-sse2.c", |
| "src/x32-transposec/gen/x32-transposec-4x4-reuse-mov-sse2.c", |
| "src/x32-transposec/gen/x32-transposec-4x4-reuse-multi-sse2.c", |
| "src/x32-transposec/gen/x32-transposec-4x4-reuse-switch-sse2.c", |
| "src/x32-unpool/x32-unpool-sse2.c", |
| "src/x32-zip/x32-zip-x2-sse2.c", |
| "src/x32-zip/x32-zip-x3-sse2.c", |
| "src/x32-zip/x32-zip-x4-sse2.c", |
| "src/x32-zip/x32-zip-xm-sse2.c", |
| "src/x64-transposec/gen/x64-transposec-2x2-multi-mov-sse2.c", |
| "src/x64-transposec/gen/x64-transposec-2x2-multi-multi-sse2.c", |
| "src/x64-transposec/gen/x64-transposec-2x2-multi-switch-sse2.c", |
| "src/x64-transposec/gen/x64-transposec-2x2-reuse-mov-sse2.c", |
| "src/x64-transposec/gen/x64-transposec-2x2-reuse-multi-sse2.c", |
| "src/x64-transposec/gen/x64-transposec-2x2-reuse-switch-sse2.c", |
| "src/xx-fill/xx-fill-sse2-x64.c", |
| "src/xx-pad/xx-pad-sse2.c", |
| ] |
| |
| ALL_SSE41_MICROKERNEL_SRCS = [ |
| "src/f16-f32-vcvt/gen/f16-f32-vcvt-sse41-int16-u8.c", |
| "src/f16-f32-vcvt/gen/f16-f32-vcvt-sse41-int16-u16.c", |
| "src/f16-f32-vcvt/gen/f16-f32-vcvt-sse41-int16-u24.c", |
| "src/f16-f32-vcvt/gen/f16-f32-vcvt-sse41-int16-u32.c", |
| "src/f16-f32-vcvt/gen/f16-f32-vcvt-sse41-int32-u8.c", |
| "src/f16-f32-vcvt/gen/f16-f32-vcvt-sse41-int32-u16.c", |
| "src/f16-f32-vcvt/gen/f16-f32-vcvt-sse41-int32-u24.c", |
| "src/f16-f32-vcvt/gen/f16-f32-vcvt-sse41-int32-u32.c", |
| "src/f32-f16-vcvt/gen/f32-f16-vcvt-sse41-u8.c", |
| "src/f32-f16-vcvt/gen/f32-f16-vcvt-sse41-u16.c", |
| "src/f32-f16-vcvt/gen/f32-f16-vcvt-sse41-u24.c", |
| "src/f32-f16-vcvt/gen/f32-f16-vcvt-sse41-u32.c", |
| "src/f32-prelu/gen/f32-prelu-sse41-2x4.c", |
| "src/f32-prelu/gen/f32-prelu-sse41-2x8.c", |
| "src/f32-qc4w-gemm/gen/f32-qc4w-gemm-1x8-minmax-sse41-dup.c", |
| "src/f32-qc4w-gemm/gen/f32-qc4w-gemm-3x8-minmax-sse41-dup.c", |
| "src/f32-qc4w-gemm/gen/f32-qc4w-gemm-4x8-minmax-sse41-dup.c", |
| "src/f32-qc4w-gemm/gen/f32-qc4w-gemm-5x8-minmax-sse41-dup.c", |
| "src/f32-qc4w-gemm/gen/f32-qc4w-gemm-6x8-minmax-sse41-dup.c", |
| "src/f32-qc8w-gemm/gen/f32-qc8w-gemm-1x8-minmax-sse41-dup.c", |
| "src/f32-qc8w-gemm/gen/f32-qc8w-gemm-1x8-minmax-sse41-load1.c", |
| "src/f32-qc8w-gemm/gen/f32-qc8w-gemm-1x8s4-minmax-sse41.c", |
| "src/f32-qc8w-gemm/gen/f32-qc8w-gemm-3x8-minmax-sse41-dup.c", |
| "src/f32-qc8w-gemm/gen/f32-qc8w-gemm-3x8-minmax-sse41-load1.c", |
| "src/f32-qc8w-gemm/gen/f32-qc8w-gemm-3x8s4-minmax-sse41.c", |
| "src/f32-qc8w-gemm/gen/f32-qc8w-gemm-4x2c4-minmax-sse41.c", |
| "src/f32-qc8w-gemm/gen/f32-qc8w-gemm-4x8-minmax-sse41-dup.c", |
| "src/f32-qc8w-gemm/gen/f32-qc8w-gemm-4x8-minmax-sse41-load1.c", |
| "src/f32-qc8w-gemm/gen/f32-qc8w-gemm-4x8s4-minmax-sse41.c", |
| "src/f32-qc8w-gemm/gen/f32-qc8w-gemm-5x8-minmax-sse41-dup.c", |
| "src/f32-qc8w-gemm/gen/f32-qc8w-gemm-5x8-minmax-sse41-load1.c", |
| "src/f32-qc8w-gemm/gen/f32-qc8w-gemm-5x8s4-minmax-sse41.c", |
| "src/f32-qc8w-gemm/gen/f32-qc8w-gemm-6x2c4-minmax-sse41.c", |
| "src/f32-qc8w-gemm/gen/f32-qc8w-gemm-6x8-minmax-sse41-dup.c", |
| "src/f32-qc8w-gemm/gen/f32-qc8w-gemm-6x8-minmax-sse41-load1.c", |
| "src/f32-qc8w-gemm/gen/f32-qc8w-gemm-6x8s4-minmax-sse41.c", |
| "src/f32-qs8-vcvt/gen/f32-qs8-vcvt-sse41-u8.c", |
| "src/f32-qs8-vcvt/gen/f32-qs8-vcvt-sse41-u16.c", |
| "src/f32-qs8-vcvt/gen/f32-qs8-vcvt-sse41-u24.c", |
| "src/f32-qs8-vcvt/gen/f32-qs8-vcvt-sse41-u32.c", |
| "src/f32-velu/gen/f32-velu-sse41-rr2-lut16-p3-u4.c", |
| "src/f32-velu/gen/f32-velu-sse41-rr2-lut16-p3-u8.c", |
| "src/f32-velu/gen/f32-velu-sse41-rr2-lut16-p3-u12.c", |
| "src/f32-velu/gen/f32-velu-sse41-rr2-lut16-p3-u16.c", |
| "src/f32-velu/gen/f32-velu-sse41-rr2-lut16-p3-u20.c", |
| "src/f32-velu/gen/f32-velu-sse41-rr2-lut16-p3-u24.c", |
| "src/f32-velu/gen/f32-velu-sse41-rr2-p6-u4.c", |
| "src/f32-velu/gen/f32-velu-sse41-rr2-p6-u8.c", |
| "src/f32-velu/gen/f32-velu-sse41-rr2-p6-u12.c", |
| "src/f32-velu/gen/f32-velu-sse41-rr2-p6-u16.c", |
| "src/f32-velu/gen/f32-velu-sse41-rr2-p6-u20.c", |
| "src/f32-velu/gen/f32-velu-sse41-rr2-p6-u24.c", |
| "src/f32-vlrelu/gen/f32-vlrelu-sse41-u4.c", |
| "src/f32-vlrelu/gen/f32-vlrelu-sse41-u8.c", |
| "src/f32-vrnd/gen/f32-vrndd-sse41-u4.c", |
| "src/f32-vrnd/gen/f32-vrndd-sse41-u8.c", |
| "src/f32-vrnd/gen/f32-vrndne-sse41-u4.c", |
| "src/f32-vrnd/gen/f32-vrndne-sse41-u8.c", |
| "src/f32-vrnd/gen/f32-vrndu-sse41-u4.c", |
| "src/f32-vrnd/gen/f32-vrndu-sse41-u8.c", |
| "src/f32-vrnd/gen/f32-vrndz-sse41-u4.c", |
| "src/f32-vrnd/gen/f32-vrndz-sse41-u8.c", |
| "src/f32-vsigmoid/gen/f32-vsigmoid-sse41-rr2-lut64-p2-div-u4.c", |
| "src/f32-vsigmoid/gen/f32-vsigmoid-sse41-rr2-lut64-p2-div-u8.c", |
| "src/f32-vsigmoid/gen/f32-vsigmoid-sse41-rr2-lut64-p2-div-u12.c", |
| "src/f32-vsigmoid/gen/f32-vsigmoid-sse41-rr2-lut64-p2-div-u16.c", |
| "src/f32-vsigmoid/gen/f32-vsigmoid-sse41-rr2-lut64-p2-div-u20.c", |
| "src/f32-vsigmoid/gen/f32-vsigmoid-sse41-rr2-lut64-p2-div-u24.c", |
| "src/f32-vsigmoid/gen/f32-vsigmoid-sse41-rr2-p5-div-u4.c", |
| "src/f32-vsigmoid/gen/f32-vsigmoid-sse41-rr2-p5-div-u8.c", |
| "src/f32-vsigmoid/gen/f32-vsigmoid-sse41-rr2-p5-div-u12.c", |
| "src/f32-vsigmoid/gen/f32-vsigmoid-sse41-rr2-p5-div-u16.c", |
| "src/f32-vsigmoid/gen/f32-vsigmoid-sse41-rr2-p5-div-u20.c", |
| "src/f32-vsigmoid/gen/f32-vsigmoid-sse41-rr2-p5-div-u24.c", |
| "src/f32-vtanh/gen/f32-vtanh-sse41-expm1minus-rr1-lut8-p4h3ts-div-u4.c", |
| "src/f32-vtanh/gen/f32-vtanh-sse41-expm1minus-rr1-lut8-p4h3ts-div-u8.c", |
| "src/f32-vtanh/gen/f32-vtanh-sse41-expm1minus-rr1-lut8-p4h3ts-div-u12.c", |
| "src/f32-vtanh/gen/f32-vtanh-sse41-expm1minus-rr1-lut8-p4h3ts-div-u16.c", |
| "src/f32-vtanh/gen/f32-vtanh-sse41-expm1minus-rr1-lut8-p4h3ts-div-u20.c", |
| "src/f32-vtanh/gen/f32-vtanh-sse41-expm1minus-rr1-lut8-p4h3ts-div-u24.c", |
| "src/f32-vtanh/gen/f32-vtanh-sse41-expm1minus-rr1-p6h5ts-div-u4.c", |
| "src/f32-vtanh/gen/f32-vtanh-sse41-expm1minus-rr1-p6h5ts-div-u8.c", |
| "src/f32-vtanh/gen/f32-vtanh-sse41-expm1minus-rr1-p6h5ts-div-u12.c", |
| "src/f32-vtanh/gen/f32-vtanh-sse41-expm1minus-rr1-p6h5ts-div-u16.c", |
| "src/f32-vtanh/gen/f32-vtanh-sse41-expm1minus-rr1-p6h5ts-div-u20.c", |
| "src/f32-vtanh/gen/f32-vtanh-sse41-expm1minus-rr1-p6h5ts-div-u24.c", |
| "src/f32-vtanh/gen/f32-vtanh-sse41-expm1minus-rr1-p6h5ts-nr1-u4.c", |
| "src/f32-vtanh/gen/f32-vtanh-sse41-expm1minus-rr1-p6h5ts-nr1-u8.c", |
| "src/f32-vtanh/gen/f32-vtanh-sse41-expm1minus-rr1-p6h5ts-nr1-u12.c", |
| "src/f32-vtanh/gen/f32-vtanh-sse41-expm1minus-rr1-p6h5ts-nr1-u16.c", |
| "src/f32-vtanh/gen/f32-vtanh-sse41-expm1minus-rr1-p6h5ts-nr1-u20.c", |
| "src/f32-vtanh/gen/f32-vtanh-sse41-expm1minus-rr1-p6h5ts-nr1-u24.c", |
| "src/f32-vtanh/gen/f32-vtanh-sse41-expm1minus-rr1-p6h5ts-nr2-u4.c", |
| "src/f32-vtanh/gen/f32-vtanh-sse41-expm1minus-rr1-p6h5ts-nr2-u8.c", |
| "src/f32-vtanh/gen/f32-vtanh-sse41-expm1minus-rr1-p6h5ts-nr2-u12.c", |
| "src/f32-vtanh/gen/f32-vtanh-sse41-expm1minus-rr1-p6h5ts-nr2-u16.c", |
| "src/f32-vtanh/gen/f32-vtanh-sse41-expm1minus-rr1-p6h5ts-nr2-u20.c", |
| "src/f32-vtanh/gen/f32-vtanh-sse41-expm1minus-rr1-p6h5ts-nr2-u24.c", |
| "src/math/f16-f32-cvt-sse41-int16.c", |
| "src/math/f16-f32-cvt-sse41-int32.c", |
| "src/math/f32-f16-cvt-sse41.c", |
| "src/math/f32-roundd-sse41.c", |
| "src/math/f32-roundne-sse41.c", |
| "src/math/f32-roundu-sse41.c", |
| "src/math/f32-roundz-sse41.c", |
| "src/qd8-f32-qc8w-gemm/gen/qd8-f32-qc8w-gemm-1x4c8-minmax-sse41-ld64.c", |
| "src/qd8-f32-qc8w-gemm/gen/qd8-f32-qc8w-gemm-1x4c8-minmax-sse41-ld128.c", |
| "src/qd8-f32-qc8w-gemm/gen/qd8-f32-qc8w-gemm-2x4c8-minmax-sse41-ld64.c", |
| "src/qd8-f32-qc8w-gemm/gen/qd8-f32-qc8w-gemm-2x4c8-minmax-sse41-ld128.c", |
| "src/qd8-f32-qc8w-gemm/gen/qd8-f32-qc8w-gemm-3x4c8-minmax-sse41-ld64.c", |
| "src/qd8-f32-qc8w-gemm/gen/qd8-f32-qc8w-gemm-3x4c8-minmax-sse41-ld128.c", |
| "src/qd8-f32-qc8w-gemm/gen/qd8-f32-qc8w-gemm-4x4c8-minmax-sse41-ld64.c", |
| "src/qd8-f32-qc8w-gemm/gen/qd8-f32-qc8w-gemm-4x4c8-minmax-sse41-ld128.c", |
| "src/qs8-dwconv/gen/qs8-dwconv-5f5m5l8c4s4r-minmax-fp32-sse41-mul32.c", |
| "src/qs8-dwconv/gen/qs8-dwconv-5f5m5l8c8s8r-minmax-fp32-sse41-mul16-add16.c", |
| "src/qs8-dwconv/gen/qs8-dwconv-5f5m5l8c8s8r-minmax-fp32-sse41-mul16.c", |
| "src/qs8-dwconv/gen/qs8-dwconv-5f5m5l16c4s4r-minmax-fp32-sse41-mul32.c", |
| "src/qs8-dwconv/gen/qs8-dwconv-5f5m5l16c8s8r-minmax-fp32-sse41-mul16-add16.c", |
| "src/qs8-dwconv/gen/qs8-dwconv-5f5m5l16c8s8r-minmax-fp32-sse41-mul16.c", |
| "src/qs8-dwconv/gen/qs8-dwconv-6f6m7l8c4s4r-minmax-fp32-sse41-mul32.c", |
| "src/qs8-dwconv/gen/qs8-dwconv-6f6m7l8c8s8r-minmax-fp32-sse41-mul16-add16.c", |
| "src/qs8-dwconv/gen/qs8-dwconv-6f6m7l8c8s8r-minmax-fp32-sse41-mul16.c", |
| "src/qs8-dwconv/gen/qs8-dwconv-6f6m7l16c4s4r-minmax-fp32-sse41-mul32.c", |
| "src/qs8-dwconv/gen/qs8-dwconv-6f6m7l16c8s8r-minmax-fp32-sse41-mul16-add16.c", |
| "src/qs8-dwconv/gen/qs8-dwconv-6f6m7l16c8s8r-minmax-fp32-sse41-mul16.c", |
| "src/qs8-dwconv/gen/qs8-dwconv-8f8m9l8c4s4r-minmax-fp32-sse41-mul32.c", |
| "src/qs8-dwconv/gen/qs8-dwconv-8f8m9l8c8s8r-minmax-fp32-sse41-mul16-add16.c", |
| "src/qs8-dwconv/gen/qs8-dwconv-8f8m9l8c8s8r-minmax-fp32-sse41-mul16.c", |
| "src/qs8-dwconv/gen/qs8-dwconv-8f8m9l16c4s4r-minmax-fp32-sse41-mul32.c", |
| "src/qs8-dwconv/gen/qs8-dwconv-8f8m9l16c8s8r-minmax-fp32-sse41-mul16-add16.c", |
| "src/qs8-dwconv/gen/qs8-dwconv-8f8m9l16c8s8r-minmax-fp32-sse41-mul16.c", |
| "src/qs8-dwconv/gen/qs8-dwconv-9p8c-minmax-fp32-sse41-mul16-add16.c", |
| "src/qs8-dwconv/gen/qs8-dwconv-9p8c-minmax-fp32-sse41-mul16.c", |
| "src/qs8-dwconv/gen/qs8-dwconv-9p8c-minmax-fp32-sse41-mul32.c", |
| "src/qs8-dwconv/gen/qs8-dwconv-9p16c-minmax-fp32-sse41-mul16-add16.c", |
| "src/qs8-dwconv/gen/qs8-dwconv-9p16c-minmax-fp32-sse41-mul16.c", |
| "src/qs8-dwconv/gen/qs8-dwconv-9p16c-minmax-fp32-sse41-mul32.c", |
| "src/qs8-dwconv/gen/qs8-dwconv-25p8c-minmax-fp32-sse41-mul16-add16.c", |
| "src/qs8-dwconv/gen/qs8-dwconv-25p8c-minmax-fp32-sse41-mul16.c", |
| "src/qs8-dwconv/gen/qs8-dwconv-25p8c-minmax-fp32-sse41-mul32.c", |
| "src/qs8-dwconv/gen/qs8-dwconv-25p16c-minmax-fp32-sse41-mul16-add16.c", |
| "src/qs8-dwconv/gen/qs8-dwconv-25p16c-minmax-fp32-sse41-mul16.c", |
| "src/qs8-dwconv/gen/qs8-dwconv-25p16c-minmax-fp32-sse41-mul32.c", |
| "src/qs8-f32-vcvt/gen/qs8-f32-vcvt-sse41-u8.c", |
| "src/qs8-f32-vcvt/gen/qs8-f32-vcvt-sse41-u16.c", |
| "src/qs8-f32-vcvt/gen/qs8-f32-vcvt-sse41-u24.c", |
| "src/qs8-f32-vcvt/gen/qs8-f32-vcvt-sse41-u32.c", |
| "src/qs8-gavgpool/gen/qs8-gavgpool-7p7x-minmax-fp32-sse41-c8.c", |
| "src/qs8-gavgpool/gen/qs8-gavgpool-7p7x-minmax-fp32-sse41-c16.c", |
| "src/qs8-gavgpool/gen/qs8-gavgpool-7p7x-minmax-fp32-sse41-c24.c", |
| "src/qs8-gavgpool/gen/qs8-gavgpool-7x-minmax-fp32-sse41-c8.c", |
| "src/qs8-gavgpool/gen/qs8-gavgpool-7x-minmax-fp32-sse41-c16.c", |
| "src/qs8-gavgpool/gen/qs8-gavgpool-7x-minmax-fp32-sse41-c24.c", |
| "src/qs8-gemm/gen/qs8-gemm-1x4c2-minmax-fp32-sse41-ld64.c", |
| "src/qs8-gemm/gen/qs8-gemm-1x4c2-minmax-fp32-sse41-ld128.c", |
| "src/qs8-gemm/gen/qs8-gemm-1x4c2-xw-minmax-fp32-sse41.c", |
| "src/qs8-gemm/gen/qs8-gemm-1x4c2s4-minmax-fp32-sse41-ld64.c", |
| "src/qs8-gemm/gen/qs8-gemm-1x4c2s4-minmax-fp32-sse41-ld128.c", |
| "src/qs8-gemm/gen/qs8-gemm-1x4c2s4-xw-minmax-fp32-sse41.c", |
| "src/qs8-gemm/gen/qs8-gemm-1x4c8-minmax-fp32-sse41-ld64.c", |
| "src/qs8-gemm/gen/qs8-gemm-1x4c8-minmax-fp32-sse41-ld128.c", |
| "src/qs8-gemm/gen/qs8-gemm-1x4c8-xw-minmax-fp32-sse41.c", |
| "src/qs8-gemm/gen/qs8-gemm-2x4c2-minmax-fp32-sse41-ld64.c", |
| "src/qs8-gemm/gen/qs8-gemm-2x4c2-minmax-fp32-sse41-ld128.c", |
| "src/qs8-gemm/gen/qs8-gemm-2x4c2-xw-minmax-fp32-sse41.c", |
| "src/qs8-gemm/gen/qs8-gemm-2x4c2s4-minmax-fp32-sse41-ld64.c", |
| "src/qs8-gemm/gen/qs8-gemm-2x4c2s4-minmax-fp32-sse41-ld128.c", |
| "src/qs8-gemm/gen/qs8-gemm-2x4c2s4-xw-minmax-fp32-sse41.c", |
| "src/qs8-gemm/gen/qs8-gemm-2x4c8-minmax-fp32-sse41-ld64.c", |
| "src/qs8-gemm/gen/qs8-gemm-2x4c8-minmax-fp32-sse41-ld128.c", |
| "src/qs8-gemm/gen/qs8-gemm-2x4c8-xw-minmax-fp32-sse41.c", |
| "src/qs8-gemm/gen/qs8-gemm-3x4c2-minmax-fp32-sse41-ld64.c", |
| "src/qs8-gemm/gen/qs8-gemm-3x4c2-minmax-fp32-sse41-ld128.c", |
| "src/qs8-gemm/gen/qs8-gemm-3x4c2-xw-minmax-fp32-sse41.c", |
| "src/qs8-gemm/gen/qs8-gemm-3x4c2s4-minmax-fp32-sse41-ld64.c", |
| "src/qs8-gemm/gen/qs8-gemm-3x4c2s4-minmax-fp32-sse41-ld128.c", |
| "src/qs8-gemm/gen/qs8-gemm-3x4c2s4-xw-minmax-fp32-sse41.c", |
| "src/qs8-gemm/gen/qs8-gemm-3x4c8-minmax-fp32-sse41-ld64.c", |
| "src/qs8-gemm/gen/qs8-gemm-3x4c8-minmax-fp32-sse41-ld128.c", |
| "src/qs8-gemm/gen/qs8-gemm-3x4c8-xw-minmax-fp32-sse41.c", |
| "src/qs8-gemm/gen/qs8-gemm-4x4c2-minmax-fp32-sse41-ld64.c", |
| "src/qs8-gemm/gen/qs8-gemm-4x4c2-minmax-fp32-sse41-ld128.c", |
| "src/qs8-gemm/gen/qs8-gemm-4x4c2-xw-minmax-fp32-sse41.c", |
| "src/qs8-gemm/gen/qs8-gemm-4x4c2s4-minmax-fp32-sse41-ld64.c", |
| "src/qs8-gemm/gen/qs8-gemm-4x4c2s4-minmax-fp32-sse41-ld128.c", |
| "src/qs8-gemm/gen/qs8-gemm-4x4c2s4-xw-minmax-fp32-sse41.c", |
| "src/qs8-igemm/gen/qs8-igemm-1x4c2-minmax-fp32-sse41-ld64.c", |
| "src/qs8-igemm/gen/qs8-igemm-1x4c2-minmax-fp32-sse41-ld128.c", |
| "src/qs8-igemm/gen/qs8-igemm-1x4c2s4-minmax-fp32-sse41-ld64.c", |
| "src/qs8-igemm/gen/qs8-igemm-1x4c2s4-minmax-fp32-sse41-ld128.c", |
| "src/qs8-igemm/gen/qs8-igemm-1x4c8-minmax-fp32-sse41-ld64.c", |
| "src/qs8-igemm/gen/qs8-igemm-1x4c8-minmax-fp32-sse41-ld128.c", |
| "src/qs8-igemm/gen/qs8-igemm-2x4c2-minmax-fp32-sse41-ld64.c", |
| "src/qs8-igemm/gen/qs8-igemm-2x4c2-minmax-fp32-sse41-ld128.c", |
| "src/qs8-igemm/gen/qs8-igemm-2x4c2s4-minmax-fp32-sse41-ld64.c", |
| "src/qs8-igemm/gen/qs8-igemm-2x4c2s4-minmax-fp32-sse41-ld128.c", |
| "src/qs8-igemm/gen/qs8-igemm-2x4c8-minmax-fp32-sse41-ld64.c", |
| "src/qs8-igemm/gen/qs8-igemm-2x4c8-minmax-fp32-sse41-ld128.c", |
| "src/qs8-igemm/gen/qs8-igemm-3x4c2-minmax-fp32-sse41-ld64.c", |
| "src/qs8-igemm/gen/qs8-igemm-3x4c2-minmax-fp32-sse41-ld128.c", |
| "src/qs8-igemm/gen/qs8-igemm-3x4c2s4-minmax-fp32-sse41-ld64.c", |
| "src/qs8-igemm/gen/qs8-igemm-3x4c2s4-minmax-fp32-sse41-ld128.c", |
| "src/qs8-igemm/gen/qs8-igemm-3x4c8-minmax-fp32-sse41-ld64.c", |
| "src/qs8-igemm/gen/qs8-igemm-3x4c8-minmax-fp32-sse41-ld128.c", |
| "src/qs8-igemm/gen/qs8-igemm-4x4c2-minmax-fp32-sse41-ld64.c", |
| "src/qs8-igemm/gen/qs8-igemm-4x4c2-minmax-fp32-sse41-ld128.c", |
| "src/qs8-igemm/gen/qs8-igemm-4x4c2s4-minmax-fp32-sse41-ld64.c", |
| "src/qs8-igemm/gen/qs8-igemm-4x4c2s4-minmax-fp32-sse41-ld128.c", |
| "src/qs8-qc8w-dwconv/gen/qs8-qc8w-dwconv-3p8c-minmax-fp32-sse41-mul16.c", |
| "src/qs8-qc8w-dwconv/gen/qs8-qc8w-dwconv-5f5m5l8c4s4r-minmax-fp32-sse41-mul32.c", |
| "src/qs8-qc8w-dwconv/gen/qs8-qc8w-dwconv-5f5m5l8c8s8r-minmax-fp32-sse41-mul16-add16.c", |
| "src/qs8-qc8w-dwconv/gen/qs8-qc8w-dwconv-5f5m5l8c8s8r-minmax-fp32-sse41-mul16.c", |
| "src/qs8-qc8w-dwconv/gen/qs8-qc8w-dwconv-5f5m5l16c4s4r-minmax-fp32-sse41-mul32.c", |
| "src/qs8-qc8w-dwconv/gen/qs8-qc8w-dwconv-5f5m5l16c8s8r-minmax-fp32-sse41-mul16-add16.c", |
| "src/qs8-qc8w-dwconv/gen/qs8-qc8w-dwconv-5f5m5l16c8s8r-minmax-fp32-sse41-mul16.c", |
| "src/qs8-qc8w-dwconv/gen/qs8-qc8w-dwconv-6f6m7l8c4s4r-minmax-fp32-sse41-mul32.c", |
| "src/qs8-qc8w-dwconv/gen/qs8-qc8w-dwconv-6f6m7l8c8s8r-minmax-fp32-sse41-mul16-add16.c", |
| "src/qs8-qc8w-dwconv/gen/qs8-qc8w-dwconv-6f6m7l8c8s8r-minmax-fp32-sse41-mul16.c", |
| "src/qs8-qc8w-dwconv/gen/qs8-qc8w-dwconv-6f6m7l16c4s4r-minmax-fp32-sse41-mul32.c", |
| "src/qs8-qc8w-dwconv/gen/qs8-qc8w-dwconv-6f6m7l16c8s8r-minmax-fp32-sse41-mul16-add16.c", |
| "src/qs8-qc8w-dwconv/gen/qs8-qc8w-dwconv-6f6m7l16c8s8r-minmax-fp32-sse41-mul16.c", |
| "src/qs8-qc8w-dwconv/gen/qs8-qc8w-dwconv-8f8m9l8c4s4r-minmax-fp32-sse41-mul32.c", |
| "src/qs8-qc8w-dwconv/gen/qs8-qc8w-dwconv-8f8m9l8c8s8r-minmax-fp32-sse41-mul16-add16.c", |
| "src/qs8-qc8w-dwconv/gen/qs8-qc8w-dwconv-8f8m9l8c8s8r-minmax-fp32-sse41-mul16.c", |
| "src/qs8-qc8w-dwconv/gen/qs8-qc8w-dwconv-8f8m9l16c4s4r-minmax-fp32-sse41-mul32.c", |
| "src/qs8-qc8w-dwconv/gen/qs8-qc8w-dwconv-8f8m9l16c8s8r-minmax-fp32-sse41-mul16-add16.c", |
| "src/qs8-qc8w-dwconv/gen/qs8-qc8w-dwconv-8f8m9l16c8s8r-minmax-fp32-sse41-mul16.c", |
| "src/qs8-qc8w-dwconv/gen/qs8-qc8w-dwconv-9p8c-minmax-fp32-sse41-mul16-add16.c", |
| "src/qs8-qc8w-dwconv/gen/qs8-qc8w-dwconv-9p8c-minmax-fp32-sse41-mul16.c", |
| "src/qs8-qc8w-dwconv/gen/qs8-qc8w-dwconv-9p8c-minmax-fp32-sse41-mul32.c", |
| "src/qs8-qc8w-dwconv/gen/qs8-qc8w-dwconv-9p16c-minmax-fp32-sse41-mul16-add16.c", |
| "src/qs8-qc8w-dwconv/gen/qs8-qc8w-dwconv-9p16c-minmax-fp32-sse41-mul16.c", |
| "src/qs8-qc8w-dwconv/gen/qs8-qc8w-dwconv-9p16c-minmax-fp32-sse41-mul32.c", |
| "src/qs8-qc8w-dwconv/gen/qs8-qc8w-dwconv-25p8c-minmax-fp32-sse41-mul16-add16.c", |
| "src/qs8-qc8w-dwconv/gen/qs8-qc8w-dwconv-25p8c-minmax-fp32-sse41-mul16.c", |
| "src/qs8-qc8w-dwconv/gen/qs8-qc8w-dwconv-25p8c-minmax-fp32-sse41-mul32.c", |
| "src/qs8-qc8w-dwconv/gen/qs8-qc8w-dwconv-25p16c-minmax-fp32-sse41-mul16-add16.c", |
| "src/qs8-qc8w-dwconv/gen/qs8-qc8w-dwconv-25p16c-minmax-fp32-sse41-mul16.c", |
| "src/qs8-qc8w-dwconv/gen/qs8-qc8w-dwconv-25p16c-minmax-fp32-sse41-mul32.c", |
| "src/qs8-qc8w-gemm/gen/qs8-qc8w-gemm-1x4c2-minmax-fp32-sse41-ld64.c", |
| "src/qs8-qc8w-gemm/gen/qs8-qc8w-gemm-1x4c2-minmax-fp32-sse41-ld128.c", |
| "src/qs8-qc8w-gemm/gen/qs8-qc8w-gemm-1x4c2s4-minmax-fp32-sse41-ld64.c", |
| "src/qs8-qc8w-gemm/gen/qs8-qc8w-gemm-1x4c2s4-minmax-fp32-sse41-ld128.c", |
| "src/qs8-qc8w-gemm/gen/qs8-qc8w-gemm-1x4c8-minmax-fp32-sse41-ld64.c", |
| "src/qs8-qc8w-gemm/gen/qs8-qc8w-gemm-1x4c8-minmax-fp32-sse41-ld128.c", |
| "src/qs8-qc8w-gemm/gen/qs8-qc8w-gemm-2x4c2-minmax-fp32-sse41-ld64.c", |
| "src/qs8-qc8w-gemm/gen/qs8-qc8w-gemm-2x4c2-minmax-fp32-sse41-ld128.c", |
| "src/qs8-qc8w-gemm/gen/qs8-qc8w-gemm-2x4c2s4-minmax-fp32-sse41-ld64.c", |
| "src/qs8-qc8w-gemm/gen/qs8-qc8w-gemm-2x4c2s4-minmax-fp32-sse41-ld128.c", |
| "src/qs8-qc8w-gemm/gen/qs8-qc8w-gemm-2x4c8-minmax-fp32-sse41-ld64.c", |
| "src/qs8-qc8w-gemm/gen/qs8-qc8w-gemm-2x4c8-minmax-fp32-sse41-ld128.c", |
| "src/qs8-qc8w-gemm/gen/qs8-qc8w-gemm-3x4c2-minmax-fp32-sse41-ld64.c", |
| "src/qs8-qc8w-gemm/gen/qs8-qc8w-gemm-3x4c2-minmax-fp32-sse41-ld128.c", |
| "src/qs8-qc8w-gemm/gen/qs8-qc8w-gemm-3x4c2s4-minmax-fp32-sse41-ld64.c", |
| "src/qs8-qc8w-gemm/gen/qs8-qc8w-gemm-3x4c2s4-minmax-fp32-sse41-ld128.c", |
| "src/qs8-qc8w-gemm/gen/qs8-qc8w-gemm-3x4c8-minmax-fp32-sse41-ld64.c", |
| "src/qs8-qc8w-gemm/gen/qs8-qc8w-gemm-3x4c8-minmax-fp32-sse41-ld128.c", |
| "src/qs8-qc8w-gemm/gen/qs8-qc8w-gemm-4x4c2-minmax-fp32-sse41-ld64.c", |
| "src/qs8-qc8w-gemm/gen/qs8-qc8w-gemm-4x4c2-minmax-fp32-sse41-ld128.c", |
| "src/qs8-qc8w-gemm/gen/qs8-qc8w-gemm-4x4c2s4-minmax-fp32-sse41-ld64.c", |
| "src/qs8-qc8w-gemm/gen/qs8-qc8w-gemm-4x4c2s4-minmax-fp32-sse41-ld128.c", |
| "src/qs8-qc8w-igemm/gen/qs8-qc8w-igemm-1x4c2-minmax-fp32-sse41-ld64.c", |
| "src/qs8-qc8w-igemm/gen/qs8-qc8w-igemm-1x4c2-minmax-fp32-sse41-ld128.c", |
| "src/qs8-qc8w-igemm/gen/qs8-qc8w-igemm-1x4c2s4-minmax-fp32-sse41-ld64.c", |
| "src/qs8-qc8w-igemm/gen/qs8-qc8w-igemm-1x4c2s4-minmax-fp32-sse41-ld128.c", |
| "src/qs8-qc8w-igemm/gen/qs8-qc8w-igemm-1x4c8-minmax-fp32-sse41-ld64.c", |
| "src/qs8-qc8w-igemm/gen/qs8-qc8w-igemm-1x4c8-minmax-fp32-sse41-ld128.c", |
| "src/qs8-qc8w-igemm/gen/qs8-qc8w-igemm-2x4c2-minmax-fp32-sse41-ld64.c", |
| "src/qs8-qc8w-igemm/gen/qs8-qc8w-igemm-2x4c2-minmax-fp32-sse41-ld128.c", |
| "src/qs8-qc8w-igemm/gen/qs8-qc8w-igemm-2x4c2s4-minmax-fp32-sse41-ld64.c", |
| "src/qs8-qc8w-igemm/gen/qs8-qc8w-igemm-2x4c2s4-minmax-fp32-sse41-ld128.c", |
| "src/qs8-qc8w-igemm/gen/qs8-qc8w-igemm-2x4c8-minmax-fp32-sse41-ld64.c", |
| "src/qs8-qc8w-igemm/gen/qs8-qc8w-igemm-2x4c8-minmax-fp32-sse41-ld128.c", |
| "src/qs8-qc8w-igemm/gen/qs8-qc8w-igemm-3x4c2-minmax-fp32-sse41-ld64.c", |
| "src/qs8-qc8w-igemm/gen/qs8-qc8w-igemm-3x4c2-minmax-fp32-sse41-ld128.c", |
| "src/qs8-qc8w-igemm/gen/qs8-qc8w-igemm-3x4c2s4-minmax-fp32-sse41-ld64.c", |
| "src/qs8-qc8w-igemm/gen/qs8-qc8w-igemm-3x4c2s4-minmax-fp32-sse41-ld128.c", |
| "src/qs8-qc8w-igemm/gen/qs8-qc8w-igemm-3x4c8-minmax-fp32-sse41-ld64.c", |
| "src/qs8-qc8w-igemm/gen/qs8-qc8w-igemm-3x4c8-minmax-fp32-sse41-ld128.c", |
| "src/qs8-qc8w-igemm/gen/qs8-qc8w-igemm-4x4c2-minmax-fp32-sse41-ld64.c", |
| "src/qs8-qc8w-igemm/gen/qs8-qc8w-igemm-4x4c2-minmax-fp32-sse41-ld128.c", |
| "src/qs8-qc8w-igemm/gen/qs8-qc8w-igemm-4x4c2s4-minmax-fp32-sse41-ld64.c", |
| "src/qs8-qc8w-igemm/gen/qs8-qc8w-igemm-4x4c2s4-minmax-fp32-sse41-ld128.c", |
| "src/qs8-requantization/qs8-requantization-fp32-sse41.c", |
| "src/qs8-requantization/qs8-requantization-gemmlowp-sse41.c", |
| "src/qs8-requantization/qs8-requantization-rndna-sse41.c", |
| "src/qs8-requantization/qs8-requantization-rndnu-sse41-sra.c", |
| "src/qs8-requantization/qs8-requantization-rndnu-sse41-srl.c", |
| "src/qs8-vadd/gen/qs8-vadd-minmax-sse41-mul16-ld64-u8.c", |
| "src/qs8-vadd/gen/qs8-vadd-minmax-sse41-mul16-ld64-u16.c", |
| "src/qs8-vadd/gen/qs8-vadd-minmax-sse41-mul16-ld64-u24.c", |
| "src/qs8-vadd/gen/qs8-vadd-minmax-sse41-mul16-ld64-u32.c", |
| "src/qs8-vadd/gen/qs8-vadd-minmax-sse41-mul32-ld32-u8.c", |
| "src/qs8-vadd/gen/qs8-vadd-minmax-sse41-mul32-ld32-u16.c", |
| "src/qs8-vadd/gen/qs8-vadd-minmax-sse41-mul32-ld32-u24.c", |
| "src/qs8-vadd/gen/qs8-vadd-minmax-sse41-mul32-ld32-u32.c", |
| "src/qs8-vaddc/gen/qs8-vaddc-minmax-sse41-mul16-ld64-u8.c", |
| "src/qs8-vaddc/gen/qs8-vaddc-minmax-sse41-mul16-ld64-u16.c", |
| "src/qs8-vaddc/gen/qs8-vaddc-minmax-sse41-mul16-ld64-u24.c", |
| "src/qs8-vaddc/gen/qs8-vaddc-minmax-sse41-mul16-ld64-u32.c", |
| "src/qs8-vaddc/gen/qs8-vaddc-minmax-sse41-mul32-ld32-u8.c", |
| "src/qs8-vaddc/gen/qs8-vaddc-minmax-sse41-mul32-ld32-u16.c", |
| "src/qs8-vaddc/gen/qs8-vaddc-minmax-sse41-mul32-ld32-u24.c", |
| "src/qs8-vaddc/gen/qs8-vaddc-minmax-sse41-mul32-ld32-u32.c", |
| "src/qs8-vcvt/gen/qs8-vcvt-sse41-u8.c", |
| "src/qs8-vcvt/gen/qs8-vcvt-sse41-u16.c", |
| "src/qs8-vcvt/gen/qs8-vcvt-sse41-u32.c", |
| "src/qs8-vlrelu/gen/qs8-vlrelu-sse41-u8.c", |
| "src/qs8-vlrelu/gen/qs8-vlrelu-sse41-u16.c", |
| "src/qs8-vlrelu/gen/qs8-vlrelu-sse41-u32.c", |
| "src/qs8-vmul/gen/qs8-vmul-minmax-fp32-sse41-mul16-ld64-u8.c", |
| "src/qs8-vmul/gen/qs8-vmul-minmax-fp32-sse41-mul16-ld64-u16.c", |
| "src/qs8-vmulc/gen/qs8-vmulc-minmax-fp32-sse41-mul16-ld64-u8.c", |
| "src/qs8-vmulc/gen/qs8-vmulc-minmax-fp32-sse41-mul16-ld64-u16.c", |
| "src/qs16-qs8-vcvt/gen/qs16-qs8-vcvt-sse41-u4.c", |
| "src/qs16-qs8-vcvt/gen/qs16-qs8-vcvt-sse41-u8.c", |
| "src/qs16-qs8-vcvt/gen/qs16-qs8-vcvt-sse41-u16.c", |
| "src/qu8-dwconv/gen/qu8-dwconv-5f5m5l8c4s4r-minmax-fp32-sse41-mul32.c", |
| "src/qu8-dwconv/gen/qu8-dwconv-5f5m5l8c8s8r-minmax-fp32-sse41-mul16.c", |
| "src/qu8-dwconv/gen/qu8-dwconv-5f5m5l16c4s4r-minmax-fp32-sse41-mul32.c", |
| "src/qu8-dwconv/gen/qu8-dwconv-5f5m5l16c8s8r-minmax-fp32-sse41-mul16.c", |
| "src/qu8-dwconv/gen/qu8-dwconv-6f6m7l8c4s4r-minmax-fp32-sse41-mul32.c", |
| "src/qu8-dwconv/gen/qu8-dwconv-6f6m7l8c8s8r-minmax-fp32-sse41-mul16.c", |
| "src/qu8-dwconv/gen/qu8-dwconv-6f6m7l16c4s4r-minmax-fp32-sse41-mul32.c", |
| "src/qu8-dwconv/gen/qu8-dwconv-6f6m7l16c8s8r-minmax-fp32-sse41-mul16.c", |
| "src/qu8-dwconv/gen/qu8-dwconv-8f8m9l8c4s4r-minmax-fp32-sse41-mul32.c", |
| "src/qu8-dwconv/gen/qu8-dwconv-8f8m9l8c8s8r-minmax-fp32-sse41-mul16.c", |
| "src/qu8-dwconv/gen/qu8-dwconv-8f8m9l16c4s4r-minmax-fp32-sse41-mul32.c", |
| "src/qu8-dwconv/gen/qu8-dwconv-8f8m9l16c8s8r-minmax-fp32-sse41-mul16.c", |
| "src/qu8-dwconv/gen/qu8-dwconv-9p8c-minmax-fp32-sse41-mul16.c", |
| "src/qu8-dwconv/gen/qu8-dwconv-9p8c-minmax-fp32-sse41-mul32.c", |
| "src/qu8-dwconv/gen/qu8-dwconv-9p16c-minmax-fp32-sse41-mul16.c", |
| "src/qu8-dwconv/gen/qu8-dwconv-9p16c-minmax-fp32-sse41-mul32.c", |
| "src/qu8-dwconv/gen/qu8-dwconv-25p8c-minmax-fp32-sse41-mul16.c", |
| "src/qu8-dwconv/gen/qu8-dwconv-25p8c-minmax-fp32-sse41-mul32.c", |
| "src/qu8-dwconv/gen/qu8-dwconv-25p16c-minmax-fp32-sse41-mul16.c", |
| "src/qu8-dwconv/gen/qu8-dwconv-25p16c-minmax-fp32-sse41-mul32.c", |
| "src/qu8-f32-vcvt/gen/qu8-f32-vcvt-sse41-u8.c", |
| "src/qu8-f32-vcvt/gen/qu8-f32-vcvt-sse41-u16.c", |
| "src/qu8-f32-vcvt/gen/qu8-f32-vcvt-sse41-u24.c", |
| "src/qu8-f32-vcvt/gen/qu8-f32-vcvt-sse41-u32.c", |
| "src/qu8-gavgpool/gen/qu8-gavgpool-7p7x-minmax-fp32-sse41-c8.c", |
| "src/qu8-gavgpool/gen/qu8-gavgpool-7p7x-minmax-fp32-sse41-c16.c", |
| "src/qu8-gavgpool/gen/qu8-gavgpool-7p7x-minmax-fp32-sse41-c24.c", |
| "src/qu8-gavgpool/gen/qu8-gavgpool-7x-minmax-fp32-sse41-c8.c", |
| "src/qu8-gavgpool/gen/qu8-gavgpool-7x-minmax-fp32-sse41-c16.c", |
| "src/qu8-gavgpool/gen/qu8-gavgpool-7x-minmax-fp32-sse41-c24.c", |
| "src/qu8-gemm/gen/qu8-gemm-1x4c2-minmax-fp32-sse41-ld64.c", |
| "src/qu8-gemm/gen/qu8-gemm-1x4c2-minmax-fp32-sse41-ld128.c", |
| "src/qu8-gemm/gen/qu8-gemm-1x4c2s4-minmax-fp32-sse41-ld64.c", |
| "src/qu8-gemm/gen/qu8-gemm-1x4c2s4-minmax-fp32-sse41-ld128.c", |
| "src/qu8-gemm/gen/qu8-gemm-1x4c8-minmax-fp32-sse41-ld64.c", |
| "src/qu8-gemm/gen/qu8-gemm-1x4c8-minmax-fp32-sse41-ld128.c", |
| "src/qu8-gemm/gen/qu8-gemm-2x4c2-minmax-fp32-sse41-ld64.c", |
| "src/qu8-gemm/gen/qu8-gemm-2x4c2-minmax-fp32-sse41-ld128.c", |
| "src/qu8-gemm/gen/qu8-gemm-2x4c2s4-minmax-fp32-sse41-ld64.c", |
| "src/qu8-gemm/gen/qu8-gemm-2x4c2s4-minmax-fp32-sse41-ld128.c", |
| "src/qu8-gemm/gen/qu8-gemm-2x4c8-minmax-fp32-sse41-ld64.c", |
| "src/qu8-gemm/gen/qu8-gemm-2x4c8-minmax-fp32-sse41-ld128.c", |
| "src/qu8-gemm/gen/qu8-gemm-3x4c2-minmax-fp32-sse41-ld64.c", |
| "src/qu8-gemm/gen/qu8-gemm-3x4c2-minmax-fp32-sse41-ld128.c", |
| "src/qu8-gemm/gen/qu8-gemm-3x4c2s4-minmax-fp32-sse41-ld64.c", |
| "src/qu8-gemm/gen/qu8-gemm-3x4c2s4-minmax-fp32-sse41-ld128.c", |
| "src/qu8-gemm/gen/qu8-gemm-3x4c8-minmax-fp32-sse41-ld64.c", |
| "src/qu8-gemm/gen/qu8-gemm-3x4c8-minmax-fp32-sse41-ld128.c", |
| "src/qu8-gemm/gen/qu8-gemm-4x4c2-minmax-fp32-sse41-ld64.c", |
| "src/qu8-gemm/gen/qu8-gemm-4x4c2-minmax-fp32-sse41-ld128.c", |
| "src/qu8-gemm/gen/qu8-gemm-4x4c2s4-minmax-fp32-sse41-ld64.c", |
| "src/qu8-gemm/gen/qu8-gemm-4x4c2s4-minmax-fp32-sse41-ld128.c", |
| "src/qu8-igemm/gen/qu8-igemm-1x4c2-minmax-fp32-sse41-ld64.c", |
| "src/qu8-igemm/gen/qu8-igemm-1x4c2-minmax-fp32-sse41-ld128.c", |
| "src/qu8-igemm/gen/qu8-igemm-1x4c2s4-minmax-fp32-sse41-ld64.c", |
| "src/qu8-igemm/gen/qu8-igemm-1x4c2s4-minmax-fp32-sse41-ld128.c", |
| "src/qu8-igemm/gen/qu8-igemm-1x4c8-minmax-fp32-sse41-ld64.c", |
| "src/qu8-igemm/gen/qu8-igemm-1x4c8-minmax-fp32-sse41-ld128.c", |
| "src/qu8-igemm/gen/qu8-igemm-2x4c2-minmax-fp32-sse41-ld64.c", |
| "src/qu8-igemm/gen/qu8-igemm-2x4c2-minmax-fp32-sse41-ld128.c", |
| "src/qu8-igemm/gen/qu8-igemm-2x4c2s4-minmax-fp32-sse41-ld64.c", |
| "src/qu8-igemm/gen/qu8-igemm-2x4c2s4-minmax-fp32-sse41-ld128.c", |
| "src/qu8-igemm/gen/qu8-igemm-2x4c8-minmax-fp32-sse41-ld64.c", |
| "src/qu8-igemm/gen/qu8-igemm-2x4c8-minmax-fp32-sse41-ld128.c", |
| "src/qu8-igemm/gen/qu8-igemm-3x4c2-minmax-fp32-sse41-ld64.c", |
| "src/qu8-igemm/gen/qu8-igemm-3x4c2-minmax-fp32-sse41-ld128.c", |
| "src/qu8-igemm/gen/qu8-igemm-3x4c2s4-minmax-fp32-sse41-ld64.c", |
| "src/qu8-igemm/gen/qu8-igemm-3x4c2s4-minmax-fp32-sse41-ld128.c", |
| "src/qu8-igemm/gen/qu8-igemm-3x4c8-minmax-fp32-sse41-ld64.c", |
| "src/qu8-igemm/gen/qu8-igemm-3x4c8-minmax-fp32-sse41-ld128.c", |
| "src/qu8-igemm/gen/qu8-igemm-4x4c2-minmax-fp32-sse41-ld64.c", |
| "src/qu8-igemm/gen/qu8-igemm-4x4c2-minmax-fp32-sse41-ld128.c", |
| "src/qu8-igemm/gen/qu8-igemm-4x4c2s4-minmax-fp32-sse41-ld64.c", |
| "src/qu8-igemm/gen/qu8-igemm-4x4c2s4-minmax-fp32-sse41-ld128.c", |
| "src/qu8-requantization/qu8-requantization-gemmlowp-sse41.c", |
| "src/qu8-requantization/qu8-requantization-rndna-sse41.c", |
| "src/qu8-vadd/gen/qu8-vadd-minmax-sse41-mul16-ld64-u8.c", |
| "src/qu8-vadd/gen/qu8-vadd-minmax-sse41-mul16-ld64-u16.c", |
| "src/qu8-vadd/gen/qu8-vadd-minmax-sse41-mul32-ld32-u8.c", |
| "src/qu8-vadd/gen/qu8-vadd-minmax-sse41-mul32-ld32-u16.c", |
| "src/qu8-vaddc/gen/qu8-vaddc-minmax-sse41-mul16-ld64-u8.c", |
| "src/qu8-vaddc/gen/qu8-vaddc-minmax-sse41-mul16-ld64-u16.c", |
| "src/qu8-vaddc/gen/qu8-vaddc-minmax-sse41-mul32-ld32-u8.c", |
| "src/qu8-vaddc/gen/qu8-vaddc-minmax-sse41-mul32-ld32-u16.c", |
| "src/qu8-vcvt/gen/qu8-vcvt-sse41-u8.c", |
| "src/qu8-vcvt/gen/qu8-vcvt-sse41-u16.c", |
| "src/qu8-vcvt/gen/qu8-vcvt-sse41-u32.c", |
| "src/qu8-vlrelu/gen/qu8-vlrelu-sse41-u8.c", |
| "src/qu8-vlrelu/gen/qu8-vlrelu-sse41-u16.c", |
| "src/qu8-vlrelu/gen/qu8-vlrelu-sse41-u32.c", |
| "src/qu8-vmul/gen/qu8-vmul-minmax-fp32-sse41-mul16-ld64-u8.c", |
| "src/qu8-vmul/gen/qu8-vmul-minmax-fp32-sse41-mul16-ld64-u16.c", |
| "src/qu8-vmulc/gen/qu8-vmulc-minmax-fp32-sse41-mul16-ld64-u8.c", |
| "src/qu8-vmulc/gen/qu8-vmulc-minmax-fp32-sse41-mul16-ld64-u16.c", |
| "src/s8-ibilinear/gen/s8-ibilinear-sse41-c8.c", |
| "src/s8-ibilinear/gen/s8-ibilinear-sse41-c16.c", |
| "src/s8-maxpool/s8-maxpool-9p8x-minmax-sse41-c16.c", |
| "src/s8-vclamp/s8-vclamp-sse41-u64.c", |
| "src/u8-ibilinear/gen/u8-ibilinear-sse41-c8.c", |
| "src/u8-ibilinear/gen/u8-ibilinear-sse41-c16.c", |
| ] |
| |
| ALL_SSSE3_MICROKERNEL_SRCS = [ |
| "src/f32-dwconv2d-chw/gen/f32-dwconv2d-chw-3x3p1-minmax-ssse3-1x4-acc2.c", |
| "src/f32-dwconv2d-chw/gen/f32-dwconv2d-chw-3x3p1-minmax-ssse3-1x4-acc3.c", |
| "src/f32-dwconv2d-chw/gen/f32-dwconv2d-chw-3x3p1-minmax-ssse3-1x4-acc4.c", |
| "src/f32-dwconv2d-chw/gen/f32-dwconv2d-chw-3x3p1-minmax-ssse3-1x4.c", |
| "src/f32-dwconv2d-chw/gen/f32-dwconv2d-chw-3x3p1-minmax-ssse3-2x4-acc2.c", |
| "src/f32-dwconv2d-chw/gen/f32-dwconv2d-chw-3x3p1-minmax-ssse3-2x4.c", |
| "src/f32-dwconv2d-chw/gen/f32-dwconv2d-chw-3x3p1-minmax-ssse3-3x4.c", |
| "src/f32-dwconv2d-chw/gen/f32-dwconv2d-chw-3x3p1-minmax-ssse3-4x4.c", |
| "src/f32-dwconv2d-chw/gen/f32-dwconv2d-chw-3x3p1-minmax-ssse3-5x4.c", |
| "src/f32-dwconv2d-chw/gen/f32-dwconv2d-chw-3x3p1-minmax-ssse3-6x4.c", |
| "src/qs8-gemm/gen/qs8-gemm-1x4c8-minmax-fp32-ssse3-ld64.c", |
| "src/qs8-gemm/gen/qs8-gemm-1x4c8-minmax-fp32-ssse3-ld128.c", |
| "src/qs8-gemm/gen/qs8-gemm-1x4c8-xw-minmax-fp32-ssse3.c", |
| "src/qs8-gemm/gen/qs8-gemm-2x4c8-minmax-fp32-ssse3-ld64.c", |
| "src/qs8-gemm/gen/qs8-gemm-2x4c8-minmax-fp32-ssse3-ld128.c", |
| "src/qs8-gemm/gen/qs8-gemm-2x4c8-xw-minmax-fp32-ssse3.c", |
| "src/qs8-gemm/gen/qs8-gemm-3x4c8-minmax-fp32-ssse3-ld64.c", |
| "src/qs8-gemm/gen/qs8-gemm-3x4c8-minmax-fp32-ssse3-ld128.c", |
| "src/qs8-gemm/gen/qs8-gemm-3x4c8-xw-minmax-fp32-ssse3.c", |
| "src/qs8-igemm/gen/qs8-igemm-1x4c8-minmax-fp32-ssse3-ld64.c", |
| "src/qs8-igemm/gen/qs8-igemm-1x4c8-minmax-fp32-ssse3-ld128.c", |
| "src/qs8-igemm/gen/qs8-igemm-2x4c8-minmax-fp32-ssse3-ld64.c", |
| "src/qs8-igemm/gen/qs8-igemm-2x4c8-minmax-fp32-ssse3-ld128.c", |
| "src/qs8-igemm/gen/qs8-igemm-3x4c8-minmax-fp32-ssse3-ld64.c", |
| "src/qs8-igemm/gen/qs8-igemm-3x4c8-minmax-fp32-ssse3-ld128.c", |
| "src/qs8-requantization/qs8-requantization-gemmlowp-ssse3.c", |
| "src/qs8-requantization/qs8-requantization-rndna-ssse3.c", |
| "src/qs8-vcvt/gen/qs8-vcvt-ssse3-u16.c", |
| "src/qs8-vcvt/gen/qs8-vcvt-ssse3-u32.c", |
| "src/qs8-vlrelu/gen/qs8-vlrelu-ssse3-u16.c", |
| "src/qs8-vlrelu/gen/qs8-vlrelu-ssse3-u32.c", |
| "src/qs16-qs8-vcvt/gen/qs16-qs8-vcvt-ssse3-u4.c", |
| "src/qs16-qs8-vcvt/gen/qs16-qs8-vcvt-ssse3-u8.c", |
| "src/qs16-qs8-vcvt/gen/qs16-qs8-vcvt-ssse3-u16.c", |
| "src/qu8-requantization/qu8-requantization-gemmlowp-ssse3.c", |
| "src/qu8-requantization/qu8-requantization-rndna-ssse3.c", |
| "src/qu8-vcvt/gen/qu8-vcvt-ssse3-u16.c", |
| "src/qu8-vcvt/gen/qu8-vcvt-ssse3-u32.c", |
| "src/qu8-vlrelu/gen/qu8-vlrelu-ssse3-u16.c", |
| "src/qu8-vlrelu/gen/qu8-vlrelu-ssse3-u32.c", |
| "src/x8-lut/gen/x8-lut-ssse3-u16.c", |
| "src/x8-lut/gen/x8-lut-ssse3-u32.c", |
| "src/x24-transposec/x24-transposec-4x4-ssse3.c", |
| ] |
| |
| ALL_WASM_MICROKERNEL_SRCS = [ |
| "src/f32-avgpool/f32-avgpool-9p8x-minmax-wasm-c1.c", |
| "src/f32-avgpool/f32-avgpool-9x-minmax-wasm-c1.c", |
| "src/f32-dwconv/gen/f32-dwconv-3f3m3l1c1s1r-minmax-wasm-acc2.c", |
| "src/f32-dwconv/gen/f32-dwconv-3f3m3l1c1s1r-minmax-wasm.c", |
| "src/f32-dwconv/gen/f32-dwconv-3p1c-minmax-wasm-acc2.c", |
| "src/f32-dwconv/gen/f32-dwconv-3p1c-minmax-wasm.c", |
| "src/f32-dwconv/gen/f32-dwconv-3p2c-minmax-wasm-acc2.c", |
| "src/f32-dwconv/gen/f32-dwconv-3p2c-minmax-wasm.c", |
| "src/f32-dwconv/gen/f32-dwconv-4p1c-minmax-wasm-acc2.c", |
| "src/f32-dwconv/gen/f32-dwconv-4p1c-minmax-wasm.c", |
| "src/f32-dwconv/gen/f32-dwconv-4p2c-minmax-wasm-acc2.c", |
| "src/f32-dwconv/gen/f32-dwconv-4p2c-minmax-wasm.c", |
| "src/f32-dwconv/gen/f32-dwconv-5f5m5l1c1s1r-minmax-wasm-acc2.c", |
| "src/f32-dwconv/gen/f32-dwconv-5f5m5l1c1s1r-minmax-wasm.c", |
| "src/f32-dwconv/gen/f32-dwconv-6f6m7l1c1s1r-minmax-wasm-acc2.c", |
| "src/f32-dwconv/gen/f32-dwconv-6f6m7l1c1s1r-minmax-wasm.c", |
| "src/f32-dwconv/gen/f32-dwconv-8f8m9l1c1s1r-minmax-wasm-acc2.c", |
| "src/f32-dwconv/gen/f32-dwconv-8f8m9l1c1s1r-minmax-wasm.c", |
| "src/f32-dwconv/gen/f32-dwconv-9p1c-minmax-wasm-acc2.c", |
| "src/f32-dwconv/gen/f32-dwconv-9p1c-minmax-wasm.c", |
| "src/f32-dwconv/gen/f32-dwconv-9p2c-minmax-wasm-acc2.c", |
| "src/f32-dwconv/gen/f32-dwconv-9p2c-minmax-wasm.c", |
| "src/f32-dwconv/gen/f32-dwconv-25p1c-minmax-wasm-acc2.c", |
| "src/f32-dwconv/gen/f32-dwconv-25p1c-minmax-wasm.c", |
| "src/f32-dwconv/gen/f32-dwconv-25p2c-minmax-wasm-acc2.c", |
| "src/f32-dwconv/gen/f32-dwconv-25p2c-minmax-wasm.c", |
| "src/f32-gavgpool/f32-gavgpool-7p7x-minmax-wasm-c1.c", |
| "src/f32-gavgpool/f32-gavgpool-7x-minmax-wasm-c1.c", |
| "src/f32-gemm/gen/f32-gemm-1x4-minmax-wasm.c", |
| "src/f32-gemm/gen/f32-gemm-1x4-relu-wasm.c", |
| "src/f32-gemm/gen/f32-gemm-2x4-minmax-wasm.c", |
| "src/f32-gemm/gen/f32-gemm-2x4-relu-wasm.c", |
| "src/f32-gemm/gen/f32-gemm-4x2-minmax-wasm.c", |
| "src/f32-gemm/gen/f32-gemm-4x2-relu-wasm.c", |
| "src/f32-gemm/gen/f32-gemm-4x4-minmax-wasm.c", |
| "src/f32-gemm/gen/f32-gemm-4x4-relu-wasm.c", |
| "src/f32-gemminc/gen/f32-gemminc-1x4-minmax-wasm.c", |
| "src/f32-gemminc/gen/f32-gemminc-2x4-minmax-wasm.c", |
| "src/f32-gemminc/gen/f32-gemminc-4x4-minmax-wasm.c", |
| "src/f32-igemm/gen/f32-igemm-1x4-minmax-wasm.c", |
| "src/f32-igemm/gen/f32-igemm-1x4-relu-wasm.c", |
| "src/f32-igemm/gen/f32-igemm-2x4-minmax-wasm.c", |
| "src/f32-igemm/gen/f32-igemm-2x4-relu-wasm.c", |
| "src/f32-igemm/gen/f32-igemm-4x2-minmax-wasm.c", |
| "src/f32-igemm/gen/f32-igemm-4x2-relu-wasm.c", |
| "src/f32-igemm/gen/f32-igemm-4x4-minmax-wasm.c", |
| "src/f32-igemm/gen/f32-igemm-4x4-relu-wasm.c", |
| "src/f32-maxpool/f32-maxpool-9p8x-minmax-wasm-c1.c", |
| "src/f32-pavgpool/f32-pavgpool-9p8x-minmax-wasm-c1.c", |
| "src/f32-pavgpool/f32-pavgpool-9x-minmax-wasm-c1.c", |
| "src/f32-prelu/gen/f32-prelu-wasm-2x1.c", |
| "src/f32-prelu/gen/f32-prelu-wasm-2x4.c", |
| "src/f32-qc4w-gemm/gen/f32-qc4w-gemm-1x4-minmax-wasm.c", |
| "src/f32-qc4w-gemm/gen/f32-qc4w-gemm-2x4-minmax-wasm.c", |
| "src/f32-qc4w-gemm/gen/f32-qc4w-gemm-4x2-minmax-wasm.c", |
| "src/f32-qc4w-gemm/gen/f32-qc4w-gemm-4x4-minmax-wasm.c", |
| "src/f32-qc8w-gemm/gen/f32-qc8w-gemm-1x4-minmax-wasm.c", |
| "src/f32-qc8w-gemm/gen/f32-qc8w-gemm-1x4-relu-wasm.c", |
| "src/f32-qc8w-gemm/gen/f32-qc8w-gemm-2x4-minmax-wasm.c", |
| "src/f32-qc8w-gemm/gen/f32-qc8w-gemm-2x4-relu-wasm.c", |
| "src/f32-qc8w-gemm/gen/f32-qc8w-gemm-4x2-minmax-wasm.c", |
| "src/f32-qc8w-gemm/gen/f32-qc8w-gemm-4x2-relu-wasm.c", |
| "src/f32-qc8w-gemm/gen/f32-qc8w-gemm-4x4-minmax-wasm.c", |
| "src/f32-qc8w-gemm/gen/f32-qc8w-gemm-4x4-relu-wasm.c", |
| "src/f32-qs8-vcvt/gen/f32-qs8-vcvt-wasm-fmagic-u1.c", |
| "src/f32-qs8-vcvt/gen/f32-qs8-vcvt-wasm-fmagic-u2.c", |
| "src/f32-qs8-vcvt/gen/f32-qs8-vcvt-wasm-fmagic-u3.c", |
| "src/f32-qs8-vcvt/gen/f32-qs8-vcvt-wasm-fmagic-u4.c", |
| "src/f32-qu8-vcvt/gen/f32-qu8-vcvt-wasm-fmagic-u1.c", |
| "src/f32-qu8-vcvt/gen/f32-qu8-vcvt-wasm-fmagic-u2.c", |
| "src/f32-qu8-vcvt/gen/f32-qu8-vcvt-wasm-fmagic-u3.c", |
| "src/f32-qu8-vcvt/gen/f32-qu8-vcvt-wasm-fmagic-u4.c", |
| "src/f32-rminmax/gen/f32-rmax-wasm-u1.c", |
| "src/f32-rminmax/gen/f32-rmax-wasm-u2-acc2.c", |
| "src/f32-rminmax/gen/f32-rmax-wasm-u3-acc3.c", |
| "src/f32-rminmax/gen/f32-rmax-wasm-u4-acc2.c", |
| "src/f32-rminmax/gen/f32-rmax-wasm-u4-acc4.c", |
| "src/f32-rminmax/gen/f32-rmin-wasm-u1.c", |
| "src/f32-rminmax/gen/f32-rmin-wasm-u2-acc2.c", |
| "src/f32-rminmax/gen/f32-rmin-wasm-u3-acc3.c", |
| "src/f32-rminmax/gen/f32-rmin-wasm-u4-acc2.c", |
| "src/f32-rminmax/gen/f32-rmin-wasm-u4-acc4.c", |
| "src/f32-rminmax/gen/f32-rminmax-wasm-u1.c", |
| "src/f32-rminmax/gen/f32-rminmax-wasm-u2-acc2.c", |
| "src/f32-rminmax/gen/f32-rminmax-wasm-u3-acc3.c", |
| "src/f32-rminmax/gen/f32-rminmax-wasm-u4-acc2.c", |
| "src/f32-rminmax/gen/f32-rminmax-wasm-u4-acc4.c", |
| "src/f32-vbinary/gen/f32-vadd-minmax-wasm-u1.c", |
| "src/f32-vbinary/gen/f32-vadd-minmax-wasm-u2.c", |
| "src/f32-vbinary/gen/f32-vadd-minmax-wasm-u4.c", |
| "src/f32-vbinary/gen/f32-vadd-minmax-wasm-u8.c", |
| "src/f32-vbinary/gen/f32-vadd-relu-wasm-u1.c", |
| "src/f32-vbinary/gen/f32-vadd-relu-wasm-u2.c", |
| "src/f32-vbinary/gen/f32-vadd-relu-wasm-u4.c", |
| "src/f32-vbinary/gen/f32-vadd-relu-wasm-u8.c", |
| "src/f32-vbinary/gen/f32-vaddc-minmax-wasm-u1.c", |
| "src/f32-vbinary/gen/f32-vaddc-minmax-wasm-u2.c", |
| "src/f32-vbinary/gen/f32-vaddc-minmax-wasm-u4.c", |
| "src/f32-vbinary/gen/f32-vaddc-minmax-wasm-u8.c", |
| "src/f32-vbinary/gen/f32-vaddc-relu-wasm-u1.c", |
| "src/f32-vbinary/gen/f32-vaddc-relu-wasm-u2.c", |
| "src/f32-vbinary/gen/f32-vaddc-relu-wasm-u4.c", |
| "src/f32-vbinary/gen/f32-vaddc-relu-wasm-u8.c", |
| "src/f32-vbinary/gen/f32-vdiv-minmax-wasm-u1.c", |
| "src/f32-vbinary/gen/f32-vdiv-minmax-wasm-u2.c", |
| "src/f32-vbinary/gen/f32-vdiv-minmax-wasm-u4.c", |
| "src/f32-vbinary/gen/f32-vdiv-minmax-wasm-u8.c", |
| "src/f32-vbinary/gen/f32-vdiv-relu-wasm-u1.c", |
| "src/f32-vbinary/gen/f32-vdiv-relu-wasm-u2.c", |
| "src/f32-vbinary/gen/f32-vdiv-relu-wasm-u4.c", |
| "src/f32-vbinary/gen/f32-vdiv-relu-wasm-u8.c", |
| "src/f32-vbinary/gen/f32-vdivc-minmax-wasm-u1.c", |
| "src/f32-vbinary/gen/f32-vdivc-minmax-wasm-u2.c", |
| "src/f32-vbinary/gen/f32-vdivc-minmax-wasm-u4.c", |
| "src/f32-vbinary/gen/f32-vdivc-minmax-wasm-u8.c", |
| "src/f32-vbinary/gen/f32-vdivc-relu-wasm-u1.c", |
| "src/f32-vbinary/gen/f32-vdivc-relu-wasm-u2.c", |
| "src/f32-vbinary/gen/f32-vdivc-relu-wasm-u4.c", |
| "src/f32-vbinary/gen/f32-vdivc-relu-wasm-u8.c", |
| "src/f32-vbinary/gen/f32-vmax-wasm-u1.c", |
| "src/f32-vbinary/gen/f32-vmax-wasm-u2.c", |
| "src/f32-vbinary/gen/f32-vmax-wasm-u4.c", |
| "src/f32-vbinary/gen/f32-vmax-wasm-u8.c", |
| "src/f32-vbinary/gen/f32-vmaxc-wasm-u1.c", |
| "src/f32-vbinary/gen/f32-vmaxc-wasm-u2.c", |
| "src/f32-vbinary/gen/f32-vmaxc-wasm-u4.c", |
| "src/f32-vbinary/gen/f32-vmaxc-wasm-u8.c", |
| "src/f32-vbinary/gen/f32-vmin-wasm-u1.c", |
| "src/f32-vbinary/gen/f32-vmin-wasm-u2.c", |
| "src/f32-vbinary/gen/f32-vmin-wasm-u4.c", |
| "src/f32-vbinary/gen/f32-vmin-wasm-u8.c", |
| "src/f32-vbinary/gen/f32-vminc-wasm-u1.c", |
| "src/f32-vbinary/gen/f32-vminc-wasm-u2.c", |
| "src/f32-vbinary/gen/f32-vminc-wasm-u4.c", |
| "src/f32-vbinary/gen/f32-vminc-wasm-u8.c", |
| "src/f32-vbinary/gen/f32-vmul-minmax-wasm-u1.c", |
| "src/f32-vbinary/gen/f32-vmul-minmax-wasm-u2.c", |
| "src/f32-vbinary/gen/f32-vmul-minmax-wasm-u4.c", |
| "src/f32-vbinary/gen/f32-vmul-minmax-wasm-u8.c", |
| "src/f32-vbinary/gen/f32-vmul-relu-wasm-u1.c", |
| "src/f32-vbinary/gen/f32-vmul-relu-wasm-u2.c", |
| "src/f32-vbinary/gen/f32-vmul-relu-wasm-u4.c", |
| "src/f32-vbinary/gen/f32-vmul-relu-wasm-u8.c", |
| "src/f32-vbinary/gen/f32-vmulc-minmax-wasm-u1.c", |
| "src/f32-vbinary/gen/f32-vmulc-minmax-wasm-u2.c", |
| "src/f32-vbinary/gen/f32-vmulc-minmax-wasm-u4.c", |
| "src/f32-vbinary/gen/f32-vmulc-minmax-wasm-u8.c", |
| "src/f32-vbinary/gen/f32-vmulc-relu-wasm-u1.c", |
| "src/f32-vbinary/gen/f32-vmulc-relu-wasm-u2.c", |
| "src/f32-vbinary/gen/f32-vmulc-relu-wasm-u4.c", |
| "src/f32-vbinary/gen/f32-vmulc-relu-wasm-u8.c", |
| "src/f32-vbinary/gen/f32-vrdivc-minmax-wasm-u1.c", |
| "src/f32-vbinary/gen/f32-vrdivc-minmax-wasm-u2.c", |
| "src/f32-vbinary/gen/f32-vrdivc-minmax-wasm-u4.c", |
| "src/f32-vbinary/gen/f32-vrdivc-minmax-wasm-u8.c", |
| "src/f32-vbinary/gen/f32-vrdivc-relu-wasm-u1.c", |
| "src/f32-vbinary/gen/f32-vrdivc-relu-wasm-u2.c", |
| "src/f32-vbinary/gen/f32-vrdivc-relu-wasm-u4.c", |
| "src/f32-vbinary/gen/f32-vrdivc-relu-wasm-u8.c", |
| "src/f32-vbinary/gen/f32-vrsubc-minmax-wasm-u1.c", |
| "src/f32-vbinary/gen/f32-vrsubc-minmax-wasm-u2.c", |
| "src/f32-vbinary/gen/f32-vrsubc-minmax-wasm-u4.c", |
| "src/f32-vbinary/gen/f32-vrsubc-minmax-wasm-u8.c", |
| "src/f32-vbinary/gen/f32-vrsubc-relu-wasm-u1.c", |
| "src/f32-vbinary/gen/f32-vrsubc-relu-wasm-u2.c", |
| "src/f32-vbinary/gen/f32-vrsubc-relu-wasm-u4.c", |
| "src/f32-vbinary/gen/f32-vrsubc-relu-wasm-u8.c", |
| "src/f32-vbinary/gen/f32-vsub-minmax-wasm-u1.c", |
| "src/f32-vbinary/gen/f32-vsub-minmax-wasm-u2.c", |
| "src/f32-vbinary/gen/f32-vsub-minmax-wasm-u4.c", |
| "src/f32-vbinary/gen/f32-vsub-minmax-wasm-u8.c", |
| "src/f32-vbinary/gen/f32-vsub-relu-wasm-u1.c", |
| "src/f32-vbinary/gen/f32-vsub-relu-wasm-u2.c", |
| "src/f32-vbinary/gen/f32-vsub-relu-wasm-u4.c", |
| "src/f32-vbinary/gen/f32-vsub-relu-wasm-u8.c", |
| "src/f32-vbinary/gen/f32-vsubc-minmax-wasm-u1.c", |
| "src/f32-vbinary/gen/f32-vsubc-minmax-wasm-u2.c", |
| "src/f32-vbinary/gen/f32-vsubc-minmax-wasm-u4.c", |
| "src/f32-vbinary/gen/f32-vsubc-minmax-wasm-u8.c", |
| "src/f32-vbinary/gen/f32-vsubc-relu-wasm-u1.c", |
| "src/f32-vbinary/gen/f32-vsubc-relu-wasm-u2.c", |
| "src/f32-vbinary/gen/f32-vsubc-relu-wasm-u4.c", |
| "src/f32-vbinary/gen/f32-vsubc-relu-wasm-u8.c", |
| "src/f32-vclamp/gen/f32-vclamp-wasm-u1.c", |
| "src/f32-vclamp/gen/f32-vclamp-wasm-u2.c", |
| "src/f32-vclamp/gen/f32-vclamp-wasm-u4.c", |
| "src/f32-velu/gen/f32-velu-wasm-rr2-lut16-p3-u1.c", |
| "src/f32-velu/gen/f32-velu-wasm-rr2-lut16-p3-u2.c", |
| "src/f32-velu/gen/f32-velu-wasm-rr2-lut16-p3-u3.c", |
| "src/f32-velu/gen/f32-velu-wasm-rr2-lut16-p3-u4.c", |
| "src/f32-velu/gen/f32-velu-wasm-rr2-lut16-p3-u5.c", |
| "src/f32-velu/gen/f32-velu-wasm-rr2-lut16-p3-u6.c", |
| "src/f32-velu/gen/f32-velu-wasm-rr2-p6-u1.c", |
| "src/f32-velu/gen/f32-velu-wasm-rr2-p6-u2.c", |
| "src/f32-velu/gen/f32-velu-wasm-rr2-p6-u3.c", |
| "src/f32-velu/gen/f32-velu-wasm-rr2-p6-u4.c", |
| "src/f32-velu/gen/f32-velu-wasm-rr2-p6-u5.c", |
| "src/f32-velu/gen/f32-velu-wasm-rr2-p6-u6.c", |
| "src/f32-vhswish/gen/f32-vhswish-wasm-u1.c", |
| "src/f32-vhswish/gen/f32-vhswish-wasm-u2.c", |
| "src/f32-vhswish/gen/f32-vhswish-wasm-u4.c", |
| "src/f32-vlrelu/gen/f32-vlrelu-wasm-u1.c", |
| "src/f32-vlrelu/gen/f32-vlrelu-wasm-u2.c", |
| "src/f32-vlrelu/gen/f32-vlrelu-wasm-u4.c", |
| "src/f32-vmulcaddc/gen/f32-vmulcaddc-c1-minmax-wasm-2x.c", |
| "src/f32-vmulcaddc/gen/f32-vmulcaddc-c2-minmax-wasm-2x.c", |
| "src/f32-vmulcaddc/gen/f32-vmulcaddc-c4-minmax-wasm-2x.c", |
| "src/f32-vrelu/gen/f32-vrelu-wasm-u1.c", |
| "src/f32-vrelu/gen/f32-vrelu-wasm-u2.c", |
| "src/f32-vrelu/gen/f32-vrelu-wasm-u4.c", |
| "src/f32-vrelu/gen/f32-vrelu-wasm-u8.c", |
| "src/f32-vtanh/gen/f32-vtanh-wasm-expm1minus-rr1-lut8-p4h3ts-div-u1.c", |
| "src/f32-vtanh/gen/f32-vtanh-wasm-expm1minus-rr1-lut8-p4h3ts-div-u2.c", |
| "src/f32-vtanh/gen/f32-vtanh-wasm-expm1minus-rr1-lut8-p4h3ts-div-u4.c", |
| "src/f32-vtanh/gen/f32-vtanh-wasm-expm1minus-rr1-p6h5ts-div-u1.c", |
| "src/f32-vtanh/gen/f32-vtanh-wasm-expm1minus-rr1-p6h5ts-div-u2.c", |
| "src/f32-vtanh/gen/f32-vtanh-wasm-expm1minus-rr1-p6h5ts-div-u4.c", |
| "src/math/gen/f32-tanh-wasm-expm1minus-rr1-lut8-p4h3ps-div.c", |
| "src/math/gen/f32-tanh-wasm-expm1minus-rr1-p6h5ts-div.c", |
| "src/qd8-f32-qc4w-gemm/gen/qd8-f32-qc4w-gemm-1x2-minmax-wasm.c", |
| "src/qd8-f32-qc4w-gemm/gen/qd8-f32-qc4w-gemm-1x4-minmax-wasm.c", |
| "src/qd8-f32-qc4w-gemm/gen/qd8-f32-qc4w-gemm-1x8-minmax-wasm.c", |
| "src/qd8-f32-qc4w-gemm/gen/qd8-f32-qc4w-gemm-2x2-minmax-wasm.c", |
| "src/qd8-f32-qc4w-gemm/gen/qd8-f32-qc4w-gemm-2x4-minmax-wasm.c", |
| "src/qd8-f32-qc4w-gemm/gen/qd8-f32-qc4w-gemm-2x8-minmax-wasm.c", |
| "src/qd8-f32-qc4w-gemm/gen/qd8-f32-qc4w-gemm-4x4-minmax-wasm.c", |
| "src/qd8-f32-qc8w-gemm/gen/qd8-f32-qc8w-gemm-1x2-minmax-wasm.c", |
| "src/qd8-f32-qc8w-gemm/gen/qd8-f32-qc8w-gemm-1x4-minmax-wasm.c", |
| "src/qd8-f32-qc8w-gemm/gen/qd8-f32-qc8w-gemm-1x8-minmax-wasm.c", |
| "src/qd8-f32-qc8w-gemm/gen/qd8-f32-qc8w-gemm-2x2-minmax-wasm.c", |
| "src/qd8-f32-qc8w-gemm/gen/qd8-f32-qc8w-gemm-2x4-minmax-wasm.c", |
| "src/qd8-f32-qc8w-gemm/gen/qd8-f32-qc8w-gemm-2x8-minmax-wasm.c", |
| "src/qd8-f32-qc8w-gemm/gen/qd8-f32-qc8w-gemm-4x4-minmax-wasm.c", |
| "src/qs8-dwconv/gen/qs8-dwconv-5f5m5l1c1s1r-minmax-fp32-wasm-fmagic.c", |
| "src/qs8-dwconv/gen/qs8-dwconv-5f5m5l2c1s1r-minmax-fp32-wasm-fmagic.c", |
| "src/qs8-dwconv/gen/qs8-dwconv-5f5m5l4c1s1r-minmax-fp32-wasm-fmagic.c", |
| "src/qs8-dwconv/gen/qs8-dwconv-6f6m7l1c1s1r-minmax-fp32-wasm-fmagic.c", |
| "src/qs8-dwconv/gen/qs8-dwconv-6f6m7l2c1s1r-minmax-fp32-wasm-fmagic.c", |
| "src/qs8-dwconv/gen/qs8-dwconv-6f6m7l4c1s1r-minmax-fp32-wasm-fmagic.c", |
| "src/qs8-dwconv/gen/qs8-dwconv-8f8m9l1c1s1r-minmax-fp32-wasm-fmagic.c", |
| "src/qs8-dwconv/gen/qs8-dwconv-8f8m9l2c1s1r-minmax-fp32-wasm-fmagic.c", |
| "src/qs8-dwconv/gen/qs8-dwconv-8f8m9l4c1s1r-minmax-fp32-wasm-fmagic.c", |
| "src/qs8-dwconv/gen/qs8-dwconv-9p1c-minmax-fp32-wasm-fmagic.c", |
| "src/qs8-dwconv/gen/qs8-dwconv-9p2c-minmax-fp32-wasm-fmagic.c", |
| "src/qs8-dwconv/gen/qs8-dwconv-9p4c-minmax-fp32-wasm-fmagic.c", |
| "src/qs8-dwconv/gen/qs8-dwconv-25p1c-minmax-fp32-wasm-fmagic.c", |
| "src/qs8-dwconv/gen/qs8-dwconv-25p2c-minmax-fp32-wasm-fmagic.c", |
| "src/qs8-dwconv/gen/qs8-dwconv-25p4c-minmax-fp32-wasm-fmagic.c", |
| "src/qs8-gemm/gen/qs8-gemm-1x2-minmax-fp32-wasm-fmagic.c", |
| "src/qs8-gemm/gen/qs8-gemm-1x4-minmax-fp32-wasm-fmagic.c", |
| "src/qs8-gemm/gen/qs8-gemm-2x2-minmax-fp32-wasm-fmagic.c", |
| "src/qs8-gemm/gen/qs8-gemm-2x4-minmax-fp32-wasm-fmagic.c", |
| "src/qs8-gemm/gen/qs8-gemm-3x2-minmax-fp32-wasm-fmagic.c", |
| "src/qs8-gemm/gen/qs8-gemm-3x4-minmax-fp32-wasm-fmagic.c", |
| "src/qs8-gemm/gen/qs8-gemm-4x2-minmax-fp32-wasm-fmagic.c", |
| "src/qs8-gemm/gen/qs8-gemm-4x4-minmax-fp32-wasm-fmagic.c", |
| "src/qs8-igemm/gen/qs8-igemm-1x2-minmax-fp32-wasm-fmagic.c", |
| "src/qs8-igemm/gen/qs8-igemm-1x4-minmax-fp32-wasm-fmagic.c", |
| "src/qs8-igemm/gen/qs8-igemm-2x2-minmax-fp32-wasm-fmagic.c", |
| "src/qs8-igemm/gen/qs8-igemm-2x4-minmax-fp32-wasm-fmagic.c", |
| "src/qs8-igemm/gen/qs8-igemm-3x2-minmax-fp32-wasm-fmagic.c", |
| "src/qs8-igemm/gen/qs8-igemm-3x4-minmax-fp32-wasm-fmagic.c", |
| "src/qs8-igemm/gen/qs8-igemm-4x2-minmax-fp32-wasm-fmagic.c", |
| "src/qs8-igemm/gen/qs8-igemm-4x4-minmax-fp32-wasm-fmagic.c", |
| "src/qs8-qc8w-dwconv/gen/qs8-qc8w-dwconv-3p2c-minmax-fp32-wasm-fmagic.c", |
| "src/qs8-qc8w-dwconv/gen/qs8-qc8w-dwconv-5f5m5l1c1s1r-minmax-fp32-wasm-fmagic.c", |
| "src/qs8-qc8w-dwconv/gen/qs8-qc8w-dwconv-5f5m5l2c1s1r-minmax-fp32-wasm-fmagic.c", |
| "src/qs8-qc8w-dwconv/gen/qs8-qc8w-dwconv-5f5m5l4c1s1r-minmax-fp32-wasm-fmagic.c", |
| "src/qs8-qc8w-dwconv/gen/qs8-qc8w-dwconv-6f6m7l1c1s1r-minmax-fp32-wasm-fmagic.c", |
| "src/qs8-qc8w-dwconv/gen/qs8-qc8w-dwconv-6f6m7l2c1s1r-minmax-fp32-wasm-fmagic.c", |
| "src/qs8-qc8w-dwconv/gen/qs8-qc8w-dwconv-6f6m7l4c1s1r-minmax-fp32-wasm-fmagic.c", |
| "src/qs8-qc8w-dwconv/gen/qs8-qc8w-dwconv-8f8m9l1c1s1r-minmax-fp32-wasm-fmagic.c", |
| "src/qs8-qc8w-dwconv/gen/qs8-qc8w-dwconv-8f8m9l2c1s1r-minmax-fp32-wasm-fmagic.c", |
| "src/qs8-qc8w-dwconv/gen/qs8-qc8w-dwconv-8f8m9l4c1s1r-minmax-fp32-wasm-fmagic.c", |
| "src/qs8-qc8w-dwconv/gen/qs8-qc8w-dwconv-9p1c-minmax-fp32-wasm-fmagic.c", |
| "src/qs8-qc8w-dwconv/gen/qs8-qc8w-dwconv-9p2c-minmax-fp32-wasm-fmagic.c", |
| "src/qs8-qc8w-dwconv/gen/qs8-qc8w-dwconv-9p4c-minmax-fp32-wasm-fmagic.c", |
| "src/qs8-qc8w-dwconv/gen/qs8-qc8w-dwconv-25p1c-minmax-fp32-wasm-fmagic.c", |
| "src/qs8-qc8w-dwconv/gen/qs8-qc8w-dwconv-25p2c-minmax-fp32-wasm-fmagic.c", |
| "src/qs8-qc8w-dwconv/gen/qs8-qc8w-dwconv-25p4c-minmax-fp32-wasm-fmagic.c", |
| "src/qs8-qc8w-gemm/gen/qs8-qc8w-gemm-1x2-minmax-fp32-wasm-fmagic.c", |
| "src/qs8-qc8w-gemm/gen/qs8-qc8w-gemm-1x4-minmax-fp32-wasm-fmagic.c", |
| "src/qs8-qc8w-gemm/gen/qs8-qc8w-gemm-2x2-minmax-fp32-wasm-fmagic.c", |
| "src/qs8-qc8w-gemm/gen/qs8-qc8w-gemm-2x4-minmax-fp32-wasm-fmagic.c", |
| "src/qs8-qc8w-gemm/gen/qs8-qc8w-gemm-3x2-minmax-fp32-wasm-fmagic.c", |
| "src/qs8-qc8w-gemm/gen/qs8-qc8w-gemm-3x4-minmax-fp32-wasm-fmagic.c", |
| "src/qs8-qc8w-gemm/gen/qs8-qc8w-gemm-4x2-minmax-fp32-wasm-fmagic.c", |
| "src/qs8-qc8w-gemm/gen/qs8-qc8w-gemm-4x4-minmax-fp32-wasm-fmagic.c", |
| "src/qs8-qc8w-igemm/gen/qs8-qc8w-igemm-1x2-minmax-fp32-wasm-fmagic.c", |
| "src/qs8-qc8w-igemm/gen/qs8-qc8w-igemm-1x4-minmax-fp32-wasm-fmagic.c", |
| "src/qs8-qc8w-igemm/gen/qs8-qc8w-igemm-2x2-minmax-fp32-wasm-fmagic.c", |
| "src/qs8-qc8w-igemm/gen/qs8-qc8w-igemm-2x4-minmax-fp32-wasm-fmagic.c", |
| "src/qs8-qc8w-igemm/gen/qs8-qc8w-igemm-3x2-minmax-fp32-wasm-fmagic.c", |
| "src/qs8-qc8w-igemm/gen/qs8-qc8w-igemm-3x4-minmax-fp32-wasm-fmagic.c", |
| "src/qs8-qc8w-igemm/gen/qs8-qc8w-igemm-4x2-minmax-fp32-wasm-fmagic.c", |
| "src/qs8-qc8w-igemm/gen/qs8-qc8w-igemm-4x4-minmax-fp32-wasm-fmagic.c", |
| "src/qu8-dwconv/gen/qu8-dwconv-5f5m5l1c1s1r-minmax-fp32-wasm-fmagic.c", |
| "src/qu8-dwconv/gen/qu8-dwconv-5f5m5l2c1s1r-minmax-fp32-wasm-fmagic.c", |
| "src/qu8-dwconv/gen/qu8-dwconv-5f5m5l4c1s1r-minmax-fp32-wasm-fmagic.c", |
| "src/qu8-dwconv/gen/qu8-dwconv-6f6m7l1c1s1r-minmax-fp32-wasm-fmagic.c", |
| "src/qu8-dwconv/gen/qu8-dwconv-6f6m7l2c1s1r-minmax-fp32-wasm-fmagic.c", |
| "src/qu8-dwconv/gen/qu8-dwconv-6f6m7l4c1s1r-minmax-fp32-wasm-fmagic.c", |
| "src/qu8-dwconv/gen/qu8-dwconv-8f8m9l1c1s1r-minmax-fp32-wasm-fmagic.c", |
| "src/qu8-dwconv/gen/qu8-dwconv-8f8m9l2c1s1r-minmax-fp32-wasm-fmagic.c", |
| "src/qu8-dwconv/gen/qu8-dwconv-8f8m9l4c1s1r-minmax-fp32-wasm-fmagic.c", |
| "src/qu8-dwconv/gen/qu8-dwconv-9p1c-minmax-fp32-wasm-fmagic.c", |
| "src/qu8-dwconv/gen/qu8-dwconv-9p2c-minmax-fp32-wasm-fmagic.c", |
| "src/qu8-dwconv/gen/qu8-dwconv-9p4c-minmax-fp32-wasm-fmagic.c", |
| "src/qu8-dwconv/gen/qu8-dwconv-25p1c-minmax-fp32-wasm-fmagic.c", |
| "src/qu8-dwconv/gen/qu8-dwconv-25p2c-minmax-fp32-wasm-fmagic.c", |
| "src/qu8-dwconv/gen/qu8-dwconv-25p4c-minmax-fp32-wasm-fmagic.c", |
| "src/qu8-gemm/gen/qu8-gemm-1x2-minmax-fp32-wasm-fmagic.c", |
| "src/qu8-gemm/gen/qu8-gemm-1x4-minmax-fp32-wasm-fmagic.c", |
| "src/qu8-gemm/gen/qu8-gemm-2x2-minmax-fp32-wasm-fmagic.c", |
| "src/qu8-gemm/gen/qu8-gemm-2x4-minmax-fp32-wasm-fmagic.c", |
| "src/qu8-gemm/gen/qu8-gemm-3x2-minmax-fp32-wasm-fmagic.c", |
| "src/qu8-gemm/gen/qu8-gemm-3x4-minmax-fp32-wasm-fmagic.c", |
| "src/qu8-gemm/gen/qu8-gemm-4x2-minmax-fp32-wasm-fmagic.c", |
| "src/qu8-gemm/gen/qu8-gemm-4x4-minmax-fp32-wasm-fmagic.c", |
| "src/qu8-igemm/gen/qu8-igemm-1x2-minmax-fp32-wasm-fmagic.c", |
| "src/qu8-igemm/gen/qu8-igemm-1x4-minmax-fp32-wasm-fmagic.c", |
| "src/qu8-igemm/gen/qu8-igemm-2x2-minmax-fp32-wasm-fmagic.c", |
| "src/qu8-igemm/gen/qu8-igemm-2x4-minmax-fp32-wasm-fmagic.c", |
| "src/qu8-igemm/gen/qu8-igemm-3x2-minmax-fp32-wasm-fmagic.c", |
| "src/qu8-igemm/gen/qu8-igemm-3x4-minmax-fp32-wasm-fmagic.c", |
| "src/qu8-igemm/gen/qu8-igemm-4x2-minmax-fp32-wasm-fmagic.c", |
| "src/qu8-igemm/gen/qu8-igemm-4x4-minmax-fp32-wasm-fmagic.c", |
| ] |
| |
| ALL_WASMRELAXEDSIMD_MICROKERNEL_SRCS = [ |
| "src/f16-f32-vcvt/gen/f16-f32-vcvt-wasmrelaxedsimd-int16-u8.c", |
| "src/f16-f32-vcvt/gen/f16-f32-vcvt-wasmrelaxedsimd-int16-u16.c", |
| "src/f16-f32-vcvt/gen/f16-f32-vcvt-wasmrelaxedsimd-int16-u24.c", |
| "src/f16-f32-vcvt/gen/f16-f32-vcvt-wasmrelaxedsimd-int16-u32.c", |
| "src/f16-f32-vcvt/gen/f16-f32-vcvt-wasmrelaxedsimd-int32-u8.c", |
| "src/f16-f32-vcvt/gen/f16-f32-vcvt-wasmrelaxedsimd-int32-u16.c", |
| "src/f16-f32-vcvt/gen/f16-f32-vcvt-wasmrelaxedsimd-int32-u24.c", |
| "src/f16-f32-vcvt/gen/f16-f32-vcvt-wasmrelaxedsimd-int32-u32.c", |
| "src/f32-dwconv/gen/f32-dwconv-3p4c-minmax-wasmrelaxedsimd-acc2.c", |
| "src/f32-dwconv/gen/f32-dwconv-3p4c-minmax-wasmrelaxedsimd-fma-acc2.c", |
| "src/f32-dwconv/gen/f32-dwconv-3p4c-minmax-wasmrelaxedsimd-fma.c", |
| "src/f32-dwconv/gen/f32-dwconv-3p4c-minmax-wasmrelaxedsimd.c", |
| "src/f32-dwconv/gen/f32-dwconv-3p4c-wasmrelaxedsimd-fma.c", |
| "src/f32-dwconv/gen/f32-dwconv-3p8c-minmax-wasmrelaxedsimd-acc2.c", |
| "src/f32-dwconv/gen/f32-dwconv-3p8c-minmax-wasmrelaxedsimd-fma-acc2.c", |
| "src/f32-dwconv/gen/f32-dwconv-3p8c-minmax-wasmrelaxedsimd-fma.c", |
| "src/f32-dwconv/gen/f32-dwconv-3p8c-minmax-wasmrelaxedsimd.c", |
| "src/f32-dwconv/gen/f32-dwconv-3p8c-wasmrelaxedsimd-fma.c", |
| "src/f32-dwconv/gen/f32-dwconv-4p4c-minmax-wasmrelaxedsimd-acc2.c", |
| "src/f32-dwconv/gen/f32-dwconv-4p4c-minmax-wasmrelaxedsimd-fma-acc2.c", |
| "src/f32-dwconv/gen/f32-dwconv-4p4c-minmax-wasmrelaxedsimd-fma.c", |
| "src/f32-dwconv/gen/f32-dwconv-4p4c-minmax-wasmrelaxedsimd.c", |
| "src/f32-dwconv/gen/f32-dwconv-4p4c-wasmrelaxedsimd-fma.c", |
| "src/f32-dwconv/gen/f32-dwconv-4p8c-minmax-wasmrelaxedsimd-acc2.c", |
| "src/f32-dwconv/gen/f32-dwconv-4p8c-minmax-wasmrelaxedsimd-fma-acc2.c", |
| "src/f32-dwconv/gen/f32-dwconv-4p8c-minmax-wasmrelaxedsimd-fma.c", |
| "src/f32-dwconv/gen/f32-dwconv-4p8c-minmax-wasmrelaxedsimd.c", |
| "src/f32-dwconv/gen/f32-dwconv-4p8c-wasmrelaxedsimd-fma.c", |
| "src/f32-dwconv/gen/f32-dwconv-5f5m5l4c4s4r-minmax-wasmrelaxedsimd-acc2.c", |
| "src/f32-dwconv/gen/f32-dwconv-5f5m5l4c4s4r-minmax-wasmrelaxedsimd-fma-acc2.c", |
| "src/f32-dwconv/gen/f32-dwconv-5f5m5l4c4s4r-minmax-wasmrelaxedsimd-fma.c", |
| "src/f32-dwconv/gen/f32-dwconv-5f5m5l4c4s4r-minmax-wasmrelaxedsimd.c", |
| "src/f32-dwconv/gen/f32-dwconv-5f5m5l4c4s4r-wasmrelaxedsimd-fma-acc2.c", |
| "src/f32-dwconv/gen/f32-dwconv-5f5m5l4c4s4r-wasmrelaxedsimd-fma.c", |
| "src/f32-dwconv/gen/f32-dwconv-9p4c-minmax-wasmrelaxedsimd-acc2.c", |
| "src/f32-dwconv/gen/f32-dwconv-9p4c-minmax-wasmrelaxedsimd-fma-acc2.c", |
| "src/f32-dwconv/gen/f32-dwconv-9p4c-minmax-wasmrelaxedsimd-fma.c", |
| "src/f32-dwconv/gen/f32-dwconv-9p4c-minmax-wasmrelaxedsimd.c", |
| "src/f32-dwconv/gen/f32-dwconv-9p4c-wasmrelaxedsimd-fma.c", |
| "src/f32-dwconv/gen/f32-dwconv-9p8c-minmax-wasmrelaxedsimd-acc2.c", |
| "src/f32-dwconv/gen/f32-dwconv-9p8c-minmax-wasmrelaxedsimd-fma-acc2.c", |
| "src/f32-dwconv/gen/f32-dwconv-9p8c-minmax-wasmrelaxedsimd-fma.c", |
| "src/f32-dwconv/gen/f32-dwconv-9p8c-minmax-wasmrelaxedsimd.c", |
| "src/f32-dwconv/gen/f32-dwconv-9p8c-wasmrelaxedsimd-fma.c", |
| "src/f32-dwconv/gen/f32-dwconv-25p4c-minmax-wasmrelaxedsimd-acc2.c", |
| "src/f32-dwconv/gen/f32-dwconv-25p4c-minmax-wasmrelaxedsimd-fma-acc2.c", |
| "src/f32-dwconv/gen/f32-dwconv-25p4c-minmax-wasmrelaxedsimd-fma.c", |
| "src/f32-dwconv/gen/f32-dwconv-25p4c-minmax-wasmrelaxedsimd.c", |
| "src/f32-dwconv/gen/f32-dwconv-25p4c-wasmrelaxedsimd-fma.c", |
| "src/f32-dwconv/gen/f32-dwconv-25p8c-minmax-wasmrelaxedsimd-acc2.c", |
| "src/f32-dwconv/gen/f32-dwconv-25p8c-minmax-wasmrelaxedsimd-fma-acc2.c", |
| "src/f32-dwconv/gen/f32-dwconv-25p8c-minmax-wasmrelaxedsimd-fma.c", |
| "src/f32-dwconv/gen/f32-dwconv-25p8c-minmax-wasmrelaxedsimd.c", |
| "src/f32-dwconv/gen/f32-dwconv-25p8c-wasmrelaxedsimd-fma.c", |
| "src/f32-f16-vcvt/gen/f32-f16-vcvt-wasmrelaxedsimd-u8.c", |
| "src/f32-f16-vcvt/gen/f32-f16-vcvt-wasmrelaxedsimd-u16.c", |
| "src/f32-f16-vcvt/gen/f32-f16-vcvt-wasmrelaxedsimd-u24.c", |
| "src/f32-f16-vcvt/gen/f32-f16-vcvt-wasmrelaxedsimd-u32.c", |
| "src/f32-gemm/gen/f32-gemm-1x8-minmax-wasmrelaxedsimd-fma-loadsplat.c", |
| "src/f32-gemm/gen/f32-gemm-1x8-minmax-wasmrelaxedsimd-fma-splat.c", |
| "src/f32-gemm/gen/f32-gemm-1x8-minmax-wasmrelaxedsimd-loadsplat.c", |
| "src/f32-gemm/gen/f32-gemm-1x8-minmax-wasmrelaxedsimd-splat.c", |
| "src/f32-gemm/gen/f32-gemm-1x8-relu-wasmrelaxedsimd-fma-loadsplat.c", |
| "src/f32-gemm/gen/f32-gemm-1x8-relu-wasmrelaxedsimd-fma-splat.c", |
| "src/f32-gemm/gen/f32-gemm-1x8-wasmrelaxedsimd-fma-loadsplat.c", |
| "src/f32-gemm/gen/f32-gemm-1x8-wasmrelaxedsimd-fma-splat.c", |
| "src/f32-gemm/gen/f32-gemm-1x8s4-minmax-wasmrelaxedsimd-fma.c", |
| "src/f32-gemm/gen/f32-gemm-1x8s4-minmax-wasmrelaxedsimd.c", |
| "src/f32-gemm/gen/f32-gemm-1x8s4-relu-wasmrelaxedsimd-fma.c", |
| "src/f32-gemm/gen/f32-gemm-1x8s4-wasmrelaxedsimd-fma.c", |
| "src/f32-gemm/gen/f32-gemm-3x8-minmax-wasmrelaxedsimd-fma-loadsplat.c", |
| "src/f32-gemm/gen/f32-gemm-3x8-minmax-wasmrelaxedsimd-fma-splat.c", |
| "src/f32-gemm/gen/f32-gemm-3x8-minmax-wasmrelaxedsimd-loadsplat.c", |
| "src/f32-gemm/gen/f32-gemm-3x8-minmax-wasmrelaxedsimd-splat.c", |
| "src/f32-gemm/gen/f32-gemm-3x8-relu-wasmrelaxedsimd-fma-loadsplat.c", |
| "src/f32-gemm/gen/f32-gemm-3x8-relu-wasmrelaxedsimd-fma-splat.c", |
| "src/f32-gemm/gen/f32-gemm-3x8-wasmrelaxedsimd-fma-loadsplat.c", |
| "src/f32-gemm/gen/f32-gemm-3x8-wasmrelaxedsimd-fma-splat.c", |
| "src/f32-gemm/gen/f32-gemm-3x8s4-minmax-wasmrelaxedsimd-fma.c", |
| "src/f32-gemm/gen/f32-gemm-3x8s4-minmax-wasmrelaxedsimd.c", |
| "src/f32-gemm/gen/f32-gemm-3x8s4-relu-wasmrelaxedsimd-fma.c", |
| "src/f32-gemm/gen/f32-gemm-3x8s4-wasmrelaxedsimd-fma.c", |
| "src/f32-gemm/gen/f32-gemm-4x2c4-minmax-wasmrelaxedsimd-fma.c", |
| "src/f32-gemm/gen/f32-gemm-4x2c4-minmax-wasmrelaxedsimd.c", |
| "src/f32-gemm/gen/f32-gemm-4x2c4-relu-wasmrelaxedsimd-fma.c", |
| "src/f32-gemm/gen/f32-gemm-4x2c4-wasmrelaxedsimd-fma.c", |
| "src/f32-gemm/gen/f32-gemm-4x8-minmax-wasmrelaxedsimd-fma-loadsplat.c", |
| "src/f32-gemm/gen/f32-gemm-4x8-minmax-wasmrelaxedsimd-fma-splat.c", |
| "src/f32-gemm/gen/f32-gemm-4x8-minmax-wasmrelaxedsimd-loadsplat.c", |
| "src/f32-gemm/gen/f32-gemm-4x8-minmax-wasmrelaxedsimd-splat.c", |
| "src/f32-gemm/gen/f32-gemm-4x8-relu-wasmrelaxedsimd-fma-loadsplat.c", |
| "src/f32-gemm/gen/f32-gemm-4x8-relu-wasmrelaxedsimd-fma-splat.c", |
| "src/f32-gemm/gen/f32-gemm-4x8-wasmrelaxedsimd-fma-loadsplat.c", |
| "src/f32-gemm/gen/f32-gemm-4x8-wasmrelaxedsimd-fma-splat.c", |
| "src/f32-gemm/gen/f32-gemm-4x8s4-minmax-wasmrelaxedsimd-fma.c", |
| "src/f32-gemm/gen/f32-gemm-4x8s4-minmax-wasmrelaxedsimd.c", |
| "src/f32-gemm/gen/f32-gemm-4x8s4-relu-wasmrelaxedsimd-fma.c", |
| "src/f32-gemm/gen/f32-gemm-4x8s4-wasmrelaxedsimd-fma.c", |
| "src/f32-gemm/gen/f32-gemm-5x8-minmax-wasmrelaxedsimd-fma-loadsplat.c", |
| "src/f32-gemm/gen/f32-gemm-5x8-minmax-wasmrelaxedsimd-fma-splat.c", |
| "src/f32-gemm/gen/f32-gemm-5x8-minmax-wasmrelaxedsimd-loadsplat.c", |
| "src/f32-gemm/gen/f32-gemm-5x8-minmax-wasmrelaxedsimd-splat.c", |
| "src/f32-gemm/gen/f32-gemm-5x8-relu-wasmrelaxedsimd-fma-loadsplat.c", |
| "src/f32-gemm/gen/f32-gemm-5x8-relu-wasmrelaxedsimd-fma-splat.c", |
| "src/f32-gemm/gen/f32-gemm-5x8-wasmrelaxedsimd-fma-loadsplat.c", |
| "src/f32-gemm/gen/f32-gemm-5x8-wasmrelaxedsimd-fma-splat.c", |
| "src/f32-gemm/gen/f32-gemm-5x8s4-minmax-wasmrelaxedsimd-fma.c", |
| "src/f32-gemm/gen/f32-gemm-5x8s4-minmax-wasmrelaxedsimd.c", |
| "src/f32-gemm/gen/f32-gemm-5x8s4-relu-wasmrelaxedsimd-fma.c", |
| "src/f32-gemm/gen/f32-gemm-5x8s4-wasmrelaxedsimd-fma.c", |
| "src/f32-gemm/gen/f32-gemm-6x8-minmax-wasmrelaxedsimd-fma-loadsplat.c", |
| "src/f32-gemm/gen/f32-gemm-6x8-minmax-wasmrelaxedsimd-fma-splat.c", |
| "src/f32-gemm/gen/f32-gemm-6x8-minmax-wasmrelaxedsimd-loadsplat.c", |
| "src/f32-gemm/gen/f32-gemm-6x8-minmax-wasmrelaxedsimd-splat.c", |
| "src/f32-gemm/gen/f32-gemm-6x8-relu-wasmrelaxedsimd-fma-loadsplat.c", |
| "src/f32-gemm/gen/f32-gemm-6x8-relu-wasmrelaxedsimd-fma-splat.c", |
| "src/f32-gemm/gen/f32-gemm-6x8-wasmrelaxedsimd-fma-loadsplat.c", |
| "src/f32-gemm/gen/f32-gemm-6x8-wasmrelaxedsimd-fma-splat.c", |
| "src/f32-gemm/gen/f32-gemm-6x8s4-minmax-wasmrelaxedsimd-fma.c", |
| "src/f32-gemm/gen/f32-gemm-6x8s4-minmax-wasmrelaxedsimd.c", |
| "src/f32-gemm/gen/f32-gemm-6x8s4-relu-wasmrelaxedsimd-fma.c", |
| "src/f32-gemm/gen/f32-gemm-6x8s4-wasmrelaxedsimd-fma.c", |
| "src/f32-gemminc/gen/f32-gemminc-1x8-minmax-wasmrelaxedsimd-fma-loadsplat.c", |
| "src/f32-gemminc/gen/f32-gemminc-1x8-minmax-wasmrelaxedsimd-fma-splat.c", |
| "src/f32-gemminc/gen/f32-gemminc-1x8-minmax-wasmrelaxedsimd-loadsplat.c", |
| "src/f32-gemminc/gen/f32-gemminc-1x8-minmax-wasmrelaxedsimd-splat.c", |
| "src/f32-gemminc/gen/f32-gemminc-1x8s4-minmax-wasmrelaxedsimd-fma.c", |
| "src/f32-gemminc/gen/f32-gemminc-1x8s4-minmax-wasmrelaxedsimd.c", |
| "src/f32-gemminc/gen/f32-gemminc-3x8-minmax-wasmrelaxedsimd-fma-loadsplat.c", |
| "src/f32-gemminc/gen/f32-gemminc-3x8-minmax-wasmrelaxedsimd-fma-splat.c", |
| "src/f32-gemminc/gen/f32-gemminc-3x8-minmax-wasmrelaxedsimd-loadsplat.c", |
| "src/f32-gemminc/gen/f32-gemminc-3x8-minmax-wasmrelaxedsimd-splat.c", |
| "src/f32-gemminc/gen/f32-gemminc-3x8s4-minmax-wasmrelaxedsimd-fma.c", |
| "src/f32-gemminc/gen/f32-gemminc-3x8s4-minmax-wasmrelaxedsimd.c", |
| "src/f32-gemminc/gen/f32-gemminc-4x8-minmax-wasmrelaxedsimd-fma-loadsplat.c", |
| "src/f32-gemminc/gen/f32-gemminc-4x8-minmax-wasmrelaxedsimd-fma-splat.c", |
| "src/f32-gemminc/gen/f32-gemminc-4x8-minmax-wasmrelaxedsimd-loadsplat.c", |
| "src/f32-gemminc/gen/f32-gemminc-4x8-minmax-wasmrelaxedsimd-splat.c", |
| "src/f32-gemminc/gen/f32-gemminc-4x8s4-minmax-wasmrelaxedsimd-fma.c", |
| "src/f32-gemminc/gen/f32-gemminc-4x8s4-minmax-wasmrelaxedsimd.c", |
| "src/f32-gemminc/gen/f32-gemminc-5x8-minmax-wasmrelaxedsimd-fma-loadsplat.c", |
| "src/f32-gemminc/gen/f32-gemminc-5x8-minmax-wasmrelaxedsimd-fma-splat.c", |
| "src/f32-gemminc/gen/f32-gemminc-5x8-minmax-wasmrelaxedsimd-loadsplat.c", |
| "src/f32-gemminc/gen/f32-gemminc-5x8-minmax-wasmrelaxedsimd-splat.c", |
| "src/f32-gemminc/gen/f32-gemminc-5x8s4-minmax-wasmrelaxedsimd-fma.c", |
| "src/f32-gemminc/gen/f32-gemminc-5x8s4-minmax-wasmrelaxedsimd.c", |
| "src/f32-gemminc/gen/f32-gemminc-6x8-minmax-wasmrelaxedsimd-fma-loadsplat.c", |
| "src/f32-gemminc/gen/f32-gemminc-6x8-minmax-wasmrelaxedsimd-fma-splat.c", |
| "src/f32-gemminc/gen/f32-gemminc-6x8-minmax-wasmrelaxedsimd-loadsplat.c", |
| "src/f32-gemminc/gen/f32-gemminc-6x8-minmax-wasmrelaxedsimd-splat.c", |
| "src/f32-gemminc/gen/f32-gemminc-6x8s4-minmax-wasmrelaxedsimd-fma.c", |
| "src/f32-gemminc/gen/f32-gemminc-6x8s4-minmax-wasmrelaxedsimd.c", |
| "src/f32-ibilinear/gen/f32-ibilinear-wasmrelaxedsimd-c4.c", |
| "src/f32-ibilinear/gen/f32-ibilinear-wasmrelaxedsimd-c8.c", |
| "src/f32-igemm/gen/f32-igemm-1x8-minmax-wasmrelaxedsimd-fma-loadsplat.c", |
| "src/f32-igemm/gen/f32-igemm-1x8-minmax-wasmrelaxedsimd-fma-splat.c", |
| "src/f32-igemm/gen/f32-igemm-1x8-minmax-wasmrelaxedsimd-loadsplat.c", |
| "src/f32-igemm/gen/f32-igemm-1x8-minmax-wasmrelaxedsimd-splat.c", |
| "src/f32-igemm/gen/f32-igemm-1x8-relu-wasmrelaxedsimd-fma-loadsplat.c", |
| "src/f32-igemm/gen/f32-igemm-1x8-relu-wasmrelaxedsimd-fma-splat.c", |
| "src/f32-igemm/gen/f32-igemm-1x8-wasmrelaxedsimd-fma-loadsplat.c", |
| "src/f32-igemm/gen/f32-igemm-1x8-wasmrelaxedsimd-fma-splat.c", |
| "src/f32-igemm/gen/f32-igemm-1x8s4-minmax-wasmrelaxedsimd-fma.c", |
| "src/f32-igemm/gen/f32-igemm-1x8s4-minmax-wasmrelaxedsimd.c", |
| "src/f32-igemm/gen/f32-igemm-1x8s4-relu-wasmrelaxedsimd-fma.c", |
| "src/f32-igemm/gen/f32-igemm-1x8s4-wasmrelaxedsimd-fma.c", |
| "src/f32-igemm/gen/f32-igemm-3x8-minmax-wasmrelaxedsimd-fma-loadsplat.c", |
| "src/f32-igemm/gen/f32-igemm-3x8-minmax-wasmrelaxedsimd-fma-splat.c", |
| "src/f32-igemm/gen/f32-igemm-3x8-minmax-wasmrelaxedsimd-loadsplat.c", |
| "src/f32-igemm/gen/f32-igemm-3x8-minmax-wasmrelaxedsimd-splat.c", |
| "src/f32-igemm/gen/f32-igemm-3x8-relu-wasmrelaxedsimd-fma-loadsplat.c", |
| "src/f32-igemm/gen/f32-igemm-3x8-relu-wasmrelaxedsimd-fma-splat.c", |
| "src/f32-igemm/gen/f32-igemm-3x8-wasmrelaxedsimd-fma-loadsplat.c", |
| "src/f32-igemm/gen/f32-igemm-3x8-wasmrelaxedsimd-fma-splat.c", |
| "src/f32-igemm/gen/f32-igemm-3x8s4-minmax-wasmrelaxedsimd-fma.c", |
| "src/f32-igemm/gen/f32-igemm-3x8s4-minmax-wasmrelaxedsimd.c", |
| "src/f32-igemm/gen/f32-igemm-3x8s4-relu-wasmrelaxedsimd-fma.c", |
| "src/f32-igemm/gen/f32-igemm-3x8s4-wasmrelaxedsimd-fma.c", |
| "src/f32-igemm/gen/f32-igemm-4x2c4-minmax-wasmrelaxedsimd-fma.c", |
| "src/f32-igemm/gen/f32-igemm-4x2c4-minmax-wasmrelaxedsimd.c", |
| "src/f32-igemm/gen/f32-igemm-4x2c4-relu-wasmrelaxedsimd-fma.c", |
| "src/f32-igemm/gen/f32-igemm-4x2c4-wasmrelaxedsimd-fma.c", |
| "src/f32-igemm/gen/f32-igemm-4x8-minmax-wasmrelaxedsimd-fma-loadsplat.c", |
| "src/f32-igemm/gen/f32-igemm-4x8-minmax-wasmrelaxedsimd-fma-splat.c", |
| "src/f32-igemm/gen/f32-igemm-4x8-minmax-wasmrelaxedsimd-loadsplat.c", |
| "src/f32-igemm/gen/f32-igemm-4x8-minmax-wasmrelaxedsimd-splat.c", |
| "src/f32-igemm/gen/f32-igemm-4x8-relu-wasmrelaxedsimd-fma-loadsplat.c", |
| "src/f32-igemm/gen/f32-igemm-4x8-relu-wasmrelaxedsimd-fma-splat.c", |
| "src/f32-igemm/gen/f32-igemm-4x8-wasmrelaxedsimd-fma-loadsplat.c", |
| "src/f32-igemm/gen/f32-igemm-4x8-wasmrelaxedsimd-fma-splat.c", |
| "src/f32-igemm/gen/f32-igemm-4x8s4-minmax-wasmrelaxedsimd-fma.c", |
| "src/f32-igemm/gen/f32-igemm-4x8s4-minmax-wasmrelaxedsimd.c", |
| "src/f32-igemm/gen/f32-igemm-4x8s4-relu-wasmrelaxedsimd-fma.c", |
| "src/f32-igemm/gen/f32-igemm-4x8s4-wasmrelaxedsimd-fma.c", |
| "src/f32-igemm/gen/f32-igemm-5x8-minmax-wasmrelaxedsimd-fma-loadsplat.c", |
| "src/f32-igemm/gen/f32-igemm-5x8-minmax-wasmrelaxedsimd-fma-splat.c", |
| "src/f32-igemm/gen/f32-igemm-5x8-minmax-wasmrelaxedsimd-loadsplat.c", |
| "src/f32-igemm/gen/f32-igemm-5x8-minmax-wasmrelaxedsimd-splat.c", |
| "src/f32-igemm/gen/f32-igemm-5x8-relu-wasmrelaxedsimd-fma-loadsplat.c", |
| "src/f32-igemm/gen/f32-igemm-5x8-relu-wasmrelaxedsimd-fma-splat.c", |
| "src/f32-igemm/gen/f32-igemm-5x8-wasmrelaxedsimd-fma-loadsplat.c", |
| "src/f32-igemm/gen/f32-igemm-5x8-wasmrelaxedsimd-fma-splat.c", |
| "src/f32-igemm/gen/f32-igemm-5x8s4-minmax-wasmrelaxedsimd-fma.c", |
| "src/f32-igemm/gen/f32-igemm-5x8s4-minmax-wasmrelaxedsimd.c", |
| "src/f32-igemm/gen/f32-igemm-5x8s4-relu-wasmrelaxedsimd-fma.c", |
| "src/f32-igemm/gen/f32-igemm-5x8s4-wasmrelaxedsimd-fma.c", |
| "src/f32-igemm/gen/f32-igemm-6x8-minmax-wasmrelaxedsimd-fma-loadsplat.c", |
| "src/f32-igemm/gen/f32-igemm-6x8-minmax-wasmrelaxedsimd-fma-splat.c", |
| "src/f32-igemm/gen/f32-igemm-6x8-minmax-wasmrelaxedsimd-loadsplat.c", |
| "src/f32-igemm/gen/f32-igemm-6x8-minmax-wasmrelaxedsimd-splat.c", |
| "src/f32-igemm/gen/f32-igemm-6x8-relu-wasmrelaxedsimd-fma-loadsplat.c", |
| "src/f32-igemm/gen/f32-igemm-6x8-relu-wasmrelaxedsimd-fma-splat.c", |
| "src/f32-igemm/gen/f32-igemm-6x8-wasmrelaxedsimd-fma-loadsplat.c", |
| "src/f32-igemm/gen/f32-igemm-6x8-wasmrelaxedsimd-fma-splat.c", |
| "src/f32-igemm/gen/f32-igemm-6x8s4-minmax-wasmrelaxedsimd-fma.c", |
| "src/f32-igemm/gen/f32-igemm-6x8s4-minmax-wasmrelaxedsimd.c", |
| "src/f32-igemm/gen/f32-igemm-6x8s4-relu-wasmrelaxedsimd-fma.c", |
| "src/f32-igemm/gen/f32-igemm-6x8s4-wasmrelaxedsimd-fma.c", |
| "src/f32-prelu/gen/f32-prelu-wasmrelaxedsimd-iminmax-1x4.c", |
| "src/f32-prelu/gen/f32-prelu-wasmrelaxedsimd-iminmax-1x8.c", |
| "src/f32-prelu/gen/f32-prelu-wasmrelaxedsimd-iminmax-1x16.c", |
| "src/f32-prelu/gen/f32-prelu-wasmrelaxedsimd-iminmax-2x4.c", |
| "src/f32-prelu/gen/f32-prelu-wasmrelaxedsimd-iminmax-2x8.c", |
| "src/f32-prelu/gen/f32-prelu-wasmrelaxedsimd-iminmax-2x16.c", |
| "src/f32-prelu/gen/f32-prelu-wasmrelaxedsimd-iminmax-4x4.c", |
| "src/f32-prelu/gen/f32-prelu-wasmrelaxedsimd-iminmax-4x8.c", |
| "src/f32-prelu/gen/f32-prelu-wasmrelaxedsimd-iminmax-4x16.c", |
| "src/f32-prelu/gen/f32-prelu-wasmrelaxedsimd-laneselect-1x4.c", |
| "src/f32-prelu/gen/f32-prelu-wasmrelaxedsimd-laneselect-1x8.c", |
| "src/f32-prelu/gen/f32-prelu-wasmrelaxedsimd-laneselect-1x16.c", |
| "src/f32-prelu/gen/f32-prelu-wasmrelaxedsimd-laneselect-2x4.c", |
| "src/f32-prelu/gen/f32-prelu-wasmrelaxedsimd-laneselect-2x8.c", |
| "src/f32-prelu/gen/f32-prelu-wasmrelaxedsimd-laneselect-2x16.c", |
| "src/f32-prelu/gen/f32-prelu-wasmrelaxedsimd-laneselect-4x4.c", |
| "src/f32-prelu/gen/f32-prelu-wasmrelaxedsimd-laneselect-4x8.c", |
| "src/f32-prelu/gen/f32-prelu-wasmrelaxedsimd-laneselect-4x16.c", |
| "src/f32-qc8w-gemm/gen/f32-qc8w-gemm-1x8-minmax-wasmrelaxedsimd-fma-loadsplat.c", |
| "src/f32-qc8w-gemm/gen/f32-qc8w-gemm-1x8-minmax-wasmrelaxedsimd-fma-splat.c", |
| "src/f32-qc8w-gemm/gen/f32-qc8w-gemm-1x8-minmax-wasmrelaxedsimd-loadsplat.c", |
| "src/f32-qc8w-gemm/gen/f32-qc8w-gemm-1x8-minmax-wasmrelaxedsimd-splat.c", |
| "src/f32-qc8w-gemm/gen/f32-qc8w-gemm-1x8-relu-wasmrelaxedsimd-fma-loadsplat.c", |
| "src/f32-qc8w-gemm/gen/f32-qc8w-gemm-1x8-relu-wasmrelaxedsimd-fma-splat.c", |
| "src/f32-qc8w-gemm/gen/f32-qc8w-gemm-1x8-wasmrelaxedsimd-fma-loadsplat.c", |
| "src/f32-qc8w-gemm/gen/f32-qc8w-gemm-1x8-wasmrelaxedsimd-fma-splat.c", |
| "src/f32-qc8w-gemm/gen/f32-qc8w-gemm-1x8s4-minmax-wasmrelaxedsimd-fma.c", |
| "src/f32-qc8w-gemm/gen/f32-qc8w-gemm-1x8s4-minmax-wasmrelaxedsimd.c", |
| "src/f32-qc8w-gemm/gen/f32-qc8w-gemm-1x8s4-relu-wasmrelaxedsimd-fma.c", |
| "src/f32-qc8w-gemm/gen/f32-qc8w-gemm-1x8s4-wasmrelaxedsimd-fma.c", |
| "src/f32-qc8w-gemm/gen/f32-qc8w-gemm-3x8-minmax-wasmrelaxedsimd-fma-loadsplat.c", |
| "src/f32-qc8w-gemm/gen/f32-qc8w-gemm-3x8-minmax-wasmrelaxedsimd-fma-splat.c", |
| "src/f32-qc8w-gemm/gen/f32-qc8w-gemm-3x8-minmax-wasmrelaxedsimd-loadsplat.c", |
| "src/f32-qc8w-gemm/gen/f32-qc8w-gemm-3x8-minmax-wasmrelaxedsimd-splat.c", |
| "src/f32-qc8w-gemm/gen/f32-qc8w-gemm-3x8-relu-wasmrelaxedsimd-fma-loadsplat.c", |
| "src/f32-qc8w-gemm/gen/f32-qc8w-gemm-3x8-relu-wasmrelaxedsimd-fma-splat.c", |
| "src/f32-qc8w-gemm/gen/f32-qc8w-gemm-3x8-wasmrelaxedsimd-fma-loadsplat.c", |
| "src/f32-qc8w-gemm/gen/f32-qc8w-gemm-3x8-wasmrelaxedsimd-fma-splat.c", |
| "src/f32-qc8w-gemm/gen/f32-qc8w-gemm-3x8s4-minmax-wasmrelaxedsimd-fma.c", |
| "src/f32-qc8w-gemm/gen/f32-qc8w-gemm-3x8s4-minmax-wasmrelaxedsimd.c", |
| "src/f32-qc8w-gemm/gen/f32-qc8w-gemm-3x8s4-relu-wasmrelaxedsimd-fma.c", |
| "src/f32-qc8w-gemm/gen/f32-qc8w-gemm-3x8s4-wasmrelaxedsimd-fma.c", |
| "src/f32-qc8w-gemm/gen/f32-qc8w-gemm-4x2c4-minmax-wasmrelaxedsimd-fma.c", |
| "src/f32-qc8w-gemm/gen/f32-qc8w-gemm-4x2c4-minmax-wasmrelaxedsimd.c", |
| "src/f32-qc8w-gemm/gen/f32-qc8w-gemm-4x2c4-relu-wasmrelaxedsimd-fma.c", |
| "src/f32-qc8w-gemm/gen/f32-qc8w-gemm-4x2c4-wasmrelaxedsimd-fma.c", |
| "src/f32-qc8w-gemm/gen/f32-qc8w-gemm-4x8-minmax-wasmrelaxedsimd-fma-loadsplat.c", |
| "src/f32-qc8w-gemm/gen/f32-qc8w-gemm-4x8-minmax-wasmrelaxedsimd-fma-splat.c", |
| "src/f32-qc8w-gemm/gen/f32-qc8w-gemm-4x8-minmax-wasmrelaxedsimd-loadsplat.c", |
| "src/f32-qc8w-gemm/gen/f32-qc8w-gemm-4x8-minmax-wasmrelaxedsimd-splat.c", |
| "src/f32-qc8w-gemm/gen/f32-qc8w-gemm-4x8-relu-wasmrelaxedsimd-fma-loadsplat.c", |
| "src/f32-qc8w-gemm/gen/f32-qc8w-gemm-4x8-relu-wasmrelaxedsimd-fma-splat.c", |
| "src/f32-qc8w-gemm/gen/f32-qc8w-gemm-4x8-wasmrelaxedsimd-fma-loadsplat.c", |
| "src/f32-qc8w-gemm/gen/f32-qc8w-gemm-4x8-wasmrelaxedsimd-fma-splat.c", |
| "src/f32-qc8w-gemm/gen/f32-qc8w-gemm-4x8s4-minmax-wasmrelaxedsimd-fma.c", |
| "src/f32-qc8w-gemm/gen/f32-qc8w-gemm-4x8s4-minmax-wasmrelaxedsimd.c", |
| "src/f32-qc8w-gemm/gen/f32-qc8w-gemm-4x8s4-relu-wasmrelaxedsimd-fma.c", |
| "src/f32-qc8w-gemm/gen/f32-qc8w-gemm-4x8s4-wasmrelaxedsimd-fma.c", |
| "src/f32-qc8w-gemm/gen/f32-qc8w-gemm-5x8-minmax-wasmrelaxedsimd-fma-loadsplat.c", |
| "src/f32-qc8w-gemm/gen/f32-qc8w-gemm-5x8-minmax-wasmrelaxedsimd-fma-splat.c", |
| "src/f32-qc8w-gemm/gen/f32-qc8w-gemm-5x8-minmax-wasmrelaxedsimd-loadsplat.c", |
| "src/f32-qc8w-gemm/gen/f32-qc8w-gemm-5x8-minmax-wasmrelaxedsimd-splat.c", |
| "src/f32-qc8w-gemm/gen/f32-qc8w-gemm-5x8-relu-wasmrelaxedsimd-fma-loadsplat.c", |
| "src/f32-qc8w-gemm/gen/f32-qc8w-gemm-5x8-relu-wasmrelaxedsimd-fma-splat.c", |
| "src/f32-qc8w-gemm/gen/f32-qc8w-gemm-5x8-wasmrelaxedsimd-fma-loadsplat.c", |
| "src/f32-qc8w-gemm/gen/f32-qc8w-gemm-5x8-wasmrelaxedsimd-fma-splat.c", |
| "src/f32-qc8w-gemm/gen/f32-qc8w-gemm-5x8s4-minmax-wasmrelaxedsimd-fma.c", |
| "src/f32-qc8w-gemm/gen/f32-qc8w-gemm-5x8s4-minmax-wasmrelaxedsimd.c", |
| "src/f32-qc8w-gemm/gen/f32-qc8w-gemm-5x8s4-relu-wasmrelaxedsimd-fma.c", |
| "src/f32-qc8w-gemm/gen/f32-qc8w-gemm-5x8s4-wasmrelaxedsimd-fma.c", |
| "src/f32-qc8w-gemm/gen/f32-qc8w-gemm-6x8-minmax-wasmrelaxedsimd-fma-loadsplat.c", |
| "src/f32-qc8w-gemm/gen/f32-qc8w-gemm-6x8-minmax-wasmrelaxedsimd-fma-splat.c", |
| "src/f32-qc8w-gemm/gen/f32-qc8w-gemm-6x8-minmax-wasmrelaxedsimd-loadsplat.c", |
| "src/f32-qc8w-gemm/gen/f32-qc8w-gemm-6x8-minmax-wasmrelaxedsimd-splat.c", |
| "src/f32-qc8w-gemm/gen/f32-qc8w-gemm-6x8-relu-wasmrelaxedsimd-fma-loadsplat.c", |
| "src/f32-qc8w-gemm/gen/f32-qc8w-gemm-6x8-relu-wasmrelaxedsimd-fma-splat.c", |
| "src/f32-qc8w-gemm/gen/f32-qc8w-gemm-6x8-wasmrelaxedsimd-fma-loadsplat.c", |
| "src/f32-qc8w-gemm/gen/f32-qc8w-gemm-6x8-wasmrelaxedsimd-fma-splat.c", |
| "src/f32-qc8w-gemm/gen/f32-qc8w-gemm-6x8s4-minmax-wasmrelaxedsimd-fma.c", |
| "src/f32-qc8w-gemm/gen/f32-qc8w-gemm-6x8s4-minmax-wasmrelaxedsimd.c", |
| "src/f32-qc8w-gemm/gen/f32-qc8w-gemm-6x8s4-relu-wasmrelaxedsimd-fma.c", |
| "src/f32-qc8w-gemm/gen/f32-qc8w-gemm-6x8s4-wasmrelaxedsimd-fma.c", |
| "src/f32-raddstoreexpminusmax/gen/f32-raddstoreexpminusmax-wasmrelaxedsimd-rr2-p5-u4.c", |
| "src/f32-raddstoreexpminusmax/gen/f32-raddstoreexpminusmax-wasmrelaxedsimd-rr2-p5-u8-acc2.c", |
| "src/f32-raddstoreexpminusmax/gen/f32-raddstoreexpminusmax-wasmrelaxedsimd-rr2-p5-u8.c", |
| "src/f32-raddstoreexpminusmax/gen/f32-raddstoreexpminusmax-wasmrelaxedsimd-rr2-p5-u12-acc2.c", |
| "src/f32-raddstoreexpminusmax/gen/f32-raddstoreexpminusmax-wasmrelaxedsimd-rr2-p5-u12-acc3.c", |
| "src/f32-raddstoreexpminusmax/gen/f32-raddstoreexpminusmax-wasmrelaxedsimd-rr2-p5-u12.c", |
| "src/f32-raddstoreexpminusmax/gen/f32-raddstoreexpminusmax-wasmrelaxedsimd-rr2-p5-u16-acc2.c", |
| "src/f32-raddstoreexpminusmax/gen/f32-raddstoreexpminusmax-wasmrelaxedsimd-rr2-p5-u16-acc4.c", |
| "src/f32-raddstoreexpminusmax/gen/f32-raddstoreexpminusmax-wasmrelaxedsimd-rr2-p5-u16.c", |
| "src/f32-raddstoreexpminusmax/gen/f32-raddstoreexpminusmax-wasmrelaxedsimd-rr2-p5-u20-acc2.c", |
| "src/f32-raddstoreexpminusmax/gen/f32-raddstoreexpminusmax-wasmrelaxedsimd-rr2-p5-u20-acc5.c", |
| "src/f32-raddstoreexpminusmax/gen/f32-raddstoreexpminusmax-wasmrelaxedsimd-rr2-p5-u20.c", |
| "src/f32-velu/gen/f32-velu-wasmrelaxedsimd-fma-rr2-lut16-p3-u4.c", |
| "src/f32-velu/gen/f32-velu-wasmrelaxedsimd-fma-rr2-lut16-p3-u8.c", |
| "src/f32-velu/gen/f32-velu-wasmrelaxedsimd-fma-rr2-lut16-p3-u12.c", |
| "src/f32-velu/gen/f32-velu-wasmrelaxedsimd-fma-rr2-lut16-p3-u16.c", |
| "src/f32-velu/gen/f32-velu-wasmrelaxedsimd-fma-rr2-lut16-p3-u20.c", |
| "src/f32-velu/gen/f32-velu-wasmrelaxedsimd-fma-rr2-lut16-p3-u24.c", |
| "src/f32-velu/gen/f32-velu-wasmrelaxedsimd-fma-rr2-p6-u4.c", |
| "src/f32-velu/gen/f32-velu-wasmrelaxedsimd-fma-rr2-p6-u8.c", |
| "src/f32-velu/gen/f32-velu-wasmrelaxedsimd-fma-rr2-p6-u12.c", |
| "src/f32-velu/gen/f32-velu-wasmrelaxedsimd-fma-rr2-p6-u16.c", |
| "src/f32-velu/gen/f32-velu-wasmrelaxedsimd-fma-rr2-p6-u20.c", |
| "src/f32-velu/gen/f32-velu-wasmrelaxedsimd-fma-rr2-p6-u24.c", |
| "src/f32-velu/gen/f32-velu-wasmrelaxedsimd-rr2-lut16-p3-u4.c", |
| "src/f32-velu/gen/f32-velu-wasmrelaxedsimd-rr2-lut16-p3-u8.c", |
| "src/f32-velu/gen/f32-velu-wasmrelaxedsimd-rr2-lut16-p3-u12.c", |
| "src/f32-velu/gen/f32-velu-wasmrelaxedsimd-rr2-lut16-p3-u16.c", |
| "src/f32-velu/gen/f32-velu-wasmrelaxedsimd-rr2-lut16-p3-u20.c", |
| "src/f32-velu/gen/f32-velu-wasmrelaxedsimd-rr2-lut16-p3-u24.c", |
| "src/f32-velu/gen/f32-velu-wasmrelaxedsimd-rr2-p6-u4.c", |
| "src/f32-velu/gen/f32-velu-wasmrelaxedsimd-rr2-p6-u8.c", |
| "src/f32-velu/gen/f32-velu-wasmrelaxedsimd-rr2-p6-u12.c", |
| "src/f32-velu/gen/f32-velu-wasmrelaxedsimd-rr2-p6-u16.c", |
| "src/f32-velu/gen/f32-velu-wasmrelaxedsimd-rr2-p6-u20.c", |
| "src/f32-velu/gen/f32-velu-wasmrelaxedsimd-rr2-p6-u24.c", |
| "src/f32-vlrelu/gen/f32-vlrelu-wasmrelaxedsimd-iminmax-u4.c", |
| "src/f32-vlrelu/gen/f32-vlrelu-wasmrelaxedsimd-iminmax-u8.c", |
| "src/f32-vlrelu/gen/f32-vlrelu-wasmrelaxedsimd-laneselect-u4.c", |
| "src/f32-vlrelu/gen/f32-vlrelu-wasmrelaxedsimd-laneselect-u8.c", |
| "src/f32-vmulcaddc/gen/f32-vmulcaddc-c4-minmax-wasmrelaxedsimd-2x.c", |
| "src/f32-vmulcaddc/gen/f32-vmulcaddc-c4-minmax-wasmrelaxedsimd-fma-2x.c", |
| "src/f32-vmulcaddc/gen/f32-vmulcaddc-c8-minmax-wasmrelaxedsimd-2x.c", |
| "src/f32-vmulcaddc/gen/f32-vmulcaddc-c8-minmax-wasmrelaxedsimd-fma-2x.c", |
| "src/f32-vsigmoid/gen/f32-vsigmoid-wasmblendvps-fma-rr2-p5-div-u4.c", |
| "src/f32-vsigmoid/gen/f32-vsigmoid-wasmblendvps-fma-rr2-p5-div-u8.c", |
| "src/f32-vsigmoid/gen/f32-vsigmoid-wasmblendvps-fma-rr2-p5-div-u12.c", |
| "src/f32-vsigmoid/gen/f32-vsigmoid-wasmblendvps-fma-rr2-p5-div-u16.c", |
| "src/f32-vsigmoid/gen/f32-vsigmoid-wasmblendvps-fma-rr2-p5-div-u20.c", |
| "src/f32-vsigmoid/gen/f32-vsigmoid-wasmblendvps-fma-rr2-p5-div-u24.c", |
| "src/f32-vsigmoid/gen/f32-vsigmoid-wasmblendvps-rr2-p5-div-u4.c", |
| "src/f32-vsigmoid/gen/f32-vsigmoid-wasmblendvps-rr2-p5-div-u8.c", |
| "src/f32-vsigmoid/gen/f32-vsigmoid-wasmblendvps-rr2-p5-div-u12.c", |
| "src/f32-vsigmoid/gen/f32-vsigmoid-wasmblendvps-rr2-p5-div-u16.c", |
| "src/f32-vsigmoid/gen/f32-vsigmoid-wasmblendvps-rr2-p5-div-u20.c", |
| "src/f32-vsigmoid/gen/f32-vsigmoid-wasmblendvps-rr2-p5-div-u24.c", |
| "src/f32-vsigmoid/gen/f32-vsigmoid-wasmrelaxedsimd-fma-rr2-lut64-p2-div-u4.c", |
| "src/f32-vsigmoid/gen/f32-vsigmoid-wasmrelaxedsimd-fma-rr2-lut64-p2-div-u8.c", |
| "src/f32-vsigmoid/gen/f32-vsigmoid-wasmrelaxedsimd-fma-rr2-lut64-p2-div-u12.c", |
| "src/f32-vsigmoid/gen/f32-vsigmoid-wasmrelaxedsimd-fma-rr2-lut64-p2-div-u16.c", |
| "src/f32-vsigmoid/gen/f32-vsigmoid-wasmrelaxedsimd-fma-rr2-lut64-p2-div-u20.c", |
| "src/f32-vsigmoid/gen/f32-vsigmoid-wasmrelaxedsimd-fma-rr2-lut64-p2-div-u24.c", |
| "src/f32-vsigmoid/gen/f32-vsigmoid-wasmrelaxedsimd-fma-rr2-p5-div-u4.c", |
| "src/f32-vsigmoid/gen/f32-vsigmoid-wasmrelaxedsimd-fma-rr2-p5-div-u8.c", |
| "src/f32-vsigmoid/gen/f32-vsigmoid-wasmrelaxedsimd-fma-rr2-p5-div-u12.c", |
| "src/f32-vsigmoid/gen/f32-vsigmoid-wasmrelaxedsimd-fma-rr2-p5-div-u16.c", |
| "src/f32-vsigmoid/gen/f32-vsigmoid-wasmrelaxedsimd-fma-rr2-p5-div-u20.c", |
| "src/f32-vsigmoid/gen/f32-vsigmoid-wasmrelaxedsimd-fma-rr2-p5-div-u24.c", |
| "src/f32-vsigmoid/gen/f32-vsigmoid-wasmrelaxedsimd-rr2-lut64-p2-div-u4.c", |
| "src/f32-vsigmoid/gen/f32-vsigmoid-wasmrelaxedsimd-rr2-lut64-p2-div-u8.c", |
| "src/f32-vsigmoid/gen/f32-vsigmoid-wasmrelaxedsimd-rr2-lut64-p2-div-u12.c", |
| "src/f32-vsigmoid/gen/f32-vsigmoid-wasmrelaxedsimd-rr2-lut64-p2-div-u16.c", |
| "src/f32-vsigmoid/gen/f32-vsigmoid-wasmrelaxedsimd-rr2-lut64-p2-div-u20.c", |
| "src/f32-vsigmoid/gen/f32-vsigmoid-wasmrelaxedsimd-rr2-lut64-p2-div-u24.c", |
| "src/f32-vsigmoid/gen/f32-vsigmoid-wasmrelaxedsimd-rr2-p5-div-u4.c", |
| "src/f32-vsigmoid/gen/f32-vsigmoid-wasmrelaxedsimd-rr2-p5-div-u8.c", |
| "src/f32-vsigmoid/gen/f32-vsigmoid-wasmrelaxedsimd-rr2-p5-div-u12.c", |
| "src/f32-vsigmoid/gen/f32-vsigmoid-wasmrelaxedsimd-rr2-p5-div-u16.c", |
| "src/f32-vsigmoid/gen/f32-vsigmoid-wasmrelaxedsimd-rr2-p5-div-u20.c", |
| "src/f32-vsigmoid/gen/f32-vsigmoid-wasmrelaxedsimd-rr2-p5-div-u24.c", |
| "src/qd8-f32-qc8w-gemm/gen/qd8-f32-qc8w-gemm-1x4c16-minmax-wasmsdot.c", |
| "src/qd8-f32-qc8w-gemm/gen/qd8-f32-qc8w-gemm-2x4c16-minmax-wasmsdot.c", |
| "src/qd8-f32-qc8w-gemm/gen/qd8-f32-qc8w-gemm-3x4c16-minmax-wasmsdot.c", |
| "src/qd8-f32-qc8w-gemm/gen/qd8-f32-qc8w-gemm-4x4c16-minmax-wasmsdot.c", |
| "src/qs8-gemm/gen/qs8-gemm-1x4c16-minmax-fp32-wasmsdot.c", |
| "src/qs8-gemm/gen/qs8-gemm-2x4c16-minmax-fp32-wasmsdot.c", |
| "src/qs8-gemm/gen/qs8-gemm-3x4c16-minmax-fp32-wasmsdot.c", |
| "src/qs8-gemm/gen/qs8-gemm-4x4c16-minmax-fp32-wasmsdot.c", |
| "src/qs8-igemm/gen/qs8-igemm-1x4c16-minmax-fp32-wasmsdot.c", |
| "src/qs8-igemm/gen/qs8-igemm-2x4c16-minmax-fp32-wasmsdot.c", |
| "src/qs8-igemm/gen/qs8-igemm-3x4c16-minmax-fp32-wasmsdot.c", |
| "src/qs8-igemm/gen/qs8-igemm-4x4c16-minmax-fp32-wasmsdot.c", |
| "src/qs8-qc8w-gemm/gen/qs8-qc8w-gemm-1x4c16-minmax-fp32-wasmsdot.c", |
| "src/qs8-qc8w-gemm/gen/qs8-qc8w-gemm-2x4c16-minmax-fp32-wasmsdot.c", |
| "src/qs8-qc8w-gemm/gen/qs8-qc8w-gemm-3x4c16-minmax-fp32-wasmsdot.c", |
| "src/qs8-qc8w-gemm/gen/qs8-qc8w-gemm-4x4c16-minmax-fp32-wasmsdot.c", |
| "src/qs8-qc8w-igemm/gen/qs8-qc8w-igemm-1x4c16-minmax-fp32-wasmsdot.c", |
| "src/qs8-qc8w-igemm/gen/qs8-qc8w-igemm-2x4c16-minmax-fp32-wasmsdot.c", |
| "src/qs8-qc8w-igemm/gen/qs8-qc8w-igemm-3x4c16-minmax-fp32-wasmsdot.c", |
| "src/qs8-qc8w-igemm/gen/qs8-qc8w-igemm-4x4c16-minmax-fp32-wasmsdot.c", |
| "src/qs8-vcvt/gen/qs8-vcvt-wasmrelaxedsimd-u8.c", |
| "src/qs8-vcvt/gen/qs8-vcvt-wasmrelaxedsimd-u16.c", |
| "src/qs8-vcvt/gen/qs8-vcvt-wasmrelaxedsimd-u32.c", |
| "src/qs8-vlrelu/gen/qs8-vlrelu-wasmrelaxedsimd-arm-u16.c", |
| "src/qs8-vlrelu/gen/qs8-vlrelu-wasmrelaxedsimd-arm-u32.c", |
| "src/qs8-vlrelu/gen/qs8-vlrelu-wasmrelaxedsimd-x86-u8.c", |
| "src/qs8-vlrelu/gen/qs8-vlrelu-wasmrelaxedsimd-x86-u16.c", |
| "src/qs8-vlrelu/gen/qs8-vlrelu-wasmrelaxedsimd-x86-u32.c", |
| "src/qu8-vcvt/gen/qu8-vcvt-wasmrelaxedsimd-u8.c", |
| "src/qu8-vcvt/gen/qu8-vcvt-wasmrelaxedsimd-u16.c", |
| "src/qu8-vcvt/gen/qu8-vcvt-wasmrelaxedsimd-u32.c", |
| "src/qu8-vlrelu/gen/qu8-vlrelu-wasmrelaxedsimd-arm-u16.c", |
| "src/qu8-vlrelu/gen/qu8-vlrelu-wasmrelaxedsimd-arm-u32.c", |
| "src/qu8-vlrelu/gen/qu8-vlrelu-wasmrelaxedsimd-x86-u8.c", |
| "src/qu8-vlrelu/gen/qu8-vlrelu-wasmrelaxedsimd-x86-u16.c", |
| "src/qu8-vlrelu/gen/qu8-vlrelu-wasmrelaxedsimd-x86-u32.c", |
| "src/x8-lut/gen/x8-lut-wasmpshufb-u16.c", |
| "src/x8-lut/gen/x8-lut-wasmpshufb-u32.c", |
| "src/x8-lut/gen/x8-lut-wasmpshufb-u48.c", |
| "src/x8-lut/gen/x8-lut-wasmpshufb-u64.c", |
| ] |
| |
| ALL_WASMSIMD_MICROKERNEL_SRCS = [ |
| "src/f16-f32-vcvt/gen/f16-f32-vcvt-wasmsimd-int16-u8.c", |
| "src/f16-f32-vcvt/gen/f16-f32-vcvt-wasmsimd-int16-u16.c", |
| "src/f16-f32-vcvt/gen/f16-f32-vcvt-wasmsimd-int16-u24.c", |
| "src/f16-f32-vcvt/gen/f16-f32-vcvt-wasmsimd-int16-u32.c", |
| "src/f16-f32-vcvt/gen/f16-f32-vcvt-wasmsimd-int32-u8.c", |
| "src/f16-f32-vcvt/gen/f16-f32-vcvt-wasmsimd-int32-u16.c", |
| "src/f16-f32-vcvt/gen/f16-f32-vcvt-wasmsimd-int32-u24.c", |
| "src/f16-f32-vcvt/gen/f16-f32-vcvt-wasmsimd-int32-u32.c", |
| "src/f32-argmaxpool/f32-argmaxpool-4x-wasmsimd-c4.c", |
| "src/f32-argmaxpool/f32-argmaxpool-9p8x-wasmsimd-c4.c", |
| "src/f32-argmaxpool/f32-argmaxpool-9x-wasmsimd-c4.c", |
| "src/f32-avgpool/f32-avgpool-9p8x-minmax-wasmsimd-arm-c4.c", |
| "src/f32-avgpool/f32-avgpool-9p8x-minmax-wasmsimd-x86-c4.c", |
| "src/f32-avgpool/f32-avgpool-9x-minmax-wasmsimd-arm-c4.c", |
| "src/f32-avgpool/f32-avgpool-9x-minmax-wasmsimd-x86-c4.c", |
| "src/f32-conv-hwc2chw/f32-conv-hwc2chw-3x3s2p1c3x4-wasmsimd-2x2.c", |
| "src/f32-dwconv2d-chw/gen/f32-dwconv2d-chw-3x3p1-minmax-wasmsimd-arm-loadsplat-1x4-acc2.c", |
| "src/f32-dwconv2d-chw/gen/f32-dwconv2d-chw-3x3p1-minmax-wasmsimd-arm-loadsplat-1x4-acc3.c", |
| "src/f32-dwconv2d-chw/gen/f32-dwconv2d-chw-3x3p1-minmax-wasmsimd-arm-loadsplat-1x4-acc4.c", |
| "src/f32-dwconv2d-chw/gen/f32-dwconv2d-chw-3x3p1-minmax-wasmsimd-arm-loadsplat-1x4.c", |
| "src/f32-dwconv2d-chw/gen/f32-dwconv2d-chw-3x3p1-minmax-wasmsimd-arm-loadsplat-2x4-acc2.c", |
| "src/f32-dwconv2d-chw/gen/f32-dwconv2d-chw-3x3p1-minmax-wasmsimd-arm-loadsplat-2x4.c", |
| "src/f32-dwconv2d-chw/gen/f32-dwconv2d-chw-3x3p1-minmax-wasmsimd-arm-loadsplat-3x4.c", |
| "src/f32-dwconv2d-chw/gen/f32-dwconv2d-chw-3x3p1-minmax-wasmsimd-arm-loadsplat-4x4.c", |
| "src/f32-dwconv2d-chw/gen/f32-dwconv2d-chw-3x3p1-minmax-wasmsimd-arm-loadsplat-5x4.c", |
| "src/f32-dwconv2d-chw/gen/f32-dwconv2d-chw-3x3p1-minmax-wasmsimd-arm-loadsplat-6x4.c", |
| "src/f32-dwconv2d-chw/gen/f32-dwconv2d-chw-3x3p1-minmax-wasmsimd-arm-splat-1x4-acc2.c", |
| "src/f32-dwconv2d-chw/gen/f32-dwconv2d-chw-3x3p1-minmax-wasmsimd-arm-splat-1x4-acc3.c", |
| "src/f32-dwconv2d-chw/gen/f32-dwconv2d-chw-3x3p1-minmax-wasmsimd-arm-splat-1x4-acc4.c", |
| "src/f32-dwconv2d-chw/gen/f32-dwconv2d-chw-3x3p1-minmax-wasmsimd-arm-splat-1x4.c", |
| "src/f32-dwconv2d-chw/gen/f32-dwconv2d-chw-3x3p1-minmax-wasmsimd-arm-splat-2x4-acc2.c", |
| "src/f32-dwconv2d-chw/gen/f32-dwconv2d-chw-3x3p1-minmax-wasmsimd-arm-splat-2x4.c", |
| "src/f32-dwconv2d-chw/gen/f32-dwconv2d-chw-3x3p1-minmax-wasmsimd-arm-splat-3x4.c", |
| "src/f32-dwconv2d-chw/gen/f32-dwconv2d-chw-3x3p1-minmax-wasmsimd-arm-splat-4x4.c", |
| "src/f32-dwconv2d-chw/gen/f32-dwconv2d-chw-3x3p1-minmax-wasmsimd-arm-splat-5x4.c", |
| "src/f32-dwconv2d-chw/gen/f32-dwconv2d-chw-3x3p1-minmax-wasmsimd-arm-splat-6x4.c", |
| "src/f32-dwconv2d-chw/gen/f32-dwconv2d-chw-3x3p1-minmax-wasmsimd-x86-loadsplat-1x4-acc2.c", |
| "src/f32-dwconv2d-chw/gen/f32-dwconv2d-chw-3x3p1-minmax-wasmsimd-x86-loadsplat-1x4-acc3.c", |
| "src/f32-dwconv2d-chw/gen/f32-dwconv2d-chw-3x3p1-minmax-wasmsimd-x86-loadsplat-1x4-acc4.c", |
| "src/f32-dwconv2d-chw/gen/f32-dwconv2d-chw-3x3p1-minmax-wasmsimd-x86-loadsplat-1x4.c", |
| "src/f32-dwconv2d-chw/gen/f32-dwconv2d-chw-3x3p1-minmax-wasmsimd-x86-loadsplat-2x4-acc2.c", |
| "src/f32-dwconv2d-chw/gen/f32-dwconv2d-chw-3x3p1-minmax-wasmsimd-x86-loadsplat-2x4.c", |
| "src/f32-dwconv2d-chw/gen/f32-dwconv2d-chw-3x3p1-minmax-wasmsimd-x86-loadsplat-3x4.c", |
| "src/f32-dwconv2d-chw/gen/f32-dwconv2d-chw-3x3p1-minmax-wasmsimd-x86-loadsplat-4x4.c", |
| "src/f32-dwconv2d-chw/gen/f32-dwconv2d-chw-3x3p1-minmax-wasmsimd-x86-loadsplat-5x4.c", |
| "src/f32-dwconv2d-chw/gen/f32-dwconv2d-chw-3x3p1-minmax-wasmsimd-x86-loadsplat-6x4.c", |
| "src/f32-dwconv2d-chw/gen/f32-dwconv2d-chw-3x3p1-minmax-wasmsimd-x86-splat-1x4-acc2.c", |
| "src/f32-dwconv2d-chw/gen/f32-dwconv2d-chw-3x3p1-minmax-wasmsimd-x86-splat-1x4-acc3.c", |
| "src/f32-dwconv2d-chw/gen/f32-dwconv2d-chw-3x3p1-minmax-wasmsimd-x86-splat-1x4-acc4.c", |
| "src/f32-dwconv2d-chw/gen/f32-dwconv2d-chw-3x3p1-minmax-wasmsimd-x86-splat-1x4.c", |
| "src/f32-dwconv2d-chw/gen/f32-dwconv2d-chw-3x3p1-minmax-wasmsimd-x86-splat-2x4-acc2.c", |
| "src/f32-dwconv2d-chw/gen/f32-dwconv2d-chw-3x3p1-minmax-wasmsimd-x86-splat-2x4.c", |
| "src/f32-dwconv2d-chw/gen/f32-dwconv2d-chw-3x3p1-minmax-wasmsimd-x86-splat-3x4.c", |
| "src/f32-dwconv2d-chw/gen/f32-dwconv2d-chw-3x3p1-minmax-wasmsimd-x86-splat-4x4.c", |
| "src/f32-dwconv2d-chw/gen/f32-dwconv2d-chw-3x3p1-minmax-wasmsimd-x86-splat-5x4.c", |
| "src/f32-dwconv2d-chw/gen/f32-dwconv2d-chw-3x3p1-minmax-wasmsimd-x86-splat-6x4.c", |
| "src/f32-dwconv2d-chw/gen/f32-dwconv2d-chw-3x3s2p1-minmax-wasmsimd-arm-loadsplat-1x4-acc2.c", |
| "src/f32-dwconv2d-chw/gen/f32-dwconv2d-chw-3x3s2p1-minmax-wasmsimd-arm-loadsplat-1x4-acc3.c", |
| "src/f32-dwconv2d-chw/gen/f32-dwconv2d-chw-3x3s2p1-minmax-wasmsimd-arm-loadsplat-1x4-acc4.c", |
| "src/f32-dwconv2d-chw/gen/f32-dwconv2d-chw-3x3s2p1-minmax-wasmsimd-arm-loadsplat-1x4.c", |
| "src/f32-dwconv2d-chw/gen/f32-dwconv2d-chw-3x3s2p1-minmax-wasmsimd-arm-loadsplat-2x4-acc2.c", |
| "src/f32-dwconv2d-chw/gen/f32-dwconv2d-chw-3x3s2p1-minmax-wasmsimd-arm-loadsplat-2x4.c", |
| "src/f32-dwconv2d-chw/gen/f32-dwconv2d-chw-3x3s2p1-minmax-wasmsimd-arm-loadsplat-3x4.c", |
| "src/f32-dwconv2d-chw/gen/f32-dwconv2d-chw-3x3s2p1-minmax-wasmsimd-arm-loadsplat-4x4.c", |
| "src/f32-dwconv2d-chw/gen/f32-dwconv2d-chw-3x3s2p1-minmax-wasmsimd-arm-splat-1x4-acc2.c", |
| "src/f32-dwconv2d-chw/gen/f32-dwconv2d-chw-3x3s2p1-minmax-wasmsimd-arm-splat-1x4-acc3.c", |
| "src/f32-dwconv2d-chw/gen/f32-dwconv2d-chw-3x3s2p1-minmax-wasmsimd-arm-splat-1x4-acc4.c", |
| "src/f32-dwconv2d-chw/gen/f32-dwconv2d-chw-3x3s2p1-minmax-wasmsimd-arm-splat-1x4.c", |
| "src/f32-dwconv2d-chw/gen/f32-dwconv2d-chw-3x3s2p1-minmax-wasmsimd-arm-splat-2x4-acc2.c", |
| "src/f32-dwconv2d-chw/gen/f32-dwconv2d-chw-3x3s2p1-minmax-wasmsimd-arm-splat-2x4.c", |
| "src/f32-dwconv2d-chw/gen/f32-dwconv2d-chw-3x3s2p1-minmax-wasmsimd-arm-splat-3x4.c", |
| "src/f32-dwconv2d-chw/gen/f32-dwconv2d-chw-3x3s2p1-minmax-wasmsimd-arm-splat-4x4.c", |
| "src/f32-dwconv2d-chw/gen/f32-dwconv2d-chw-3x3s2p1-minmax-wasmsimd-x86-loadsplat-1x4-acc2.c", |
| "src/f32-dwconv2d-chw/gen/f32-dwconv2d-chw-3x3s2p1-minmax-wasmsimd-x86-loadsplat-1x4-acc3.c", |
| "src/f32-dwconv2d-chw/gen/f32-dwconv2d-chw-3x3s2p1-minmax-wasmsimd-x86-loadsplat-1x4-acc4.c", |
| "src/f32-dwconv2d-chw/gen/f32-dwconv2d-chw-3x3s2p1-minmax-wasmsimd-x86-loadsplat-1x4.c", |
| "src/f32-dwconv2d-chw/gen/f32-dwconv2d-chw-3x3s2p1-minmax-wasmsimd-x86-loadsplat-2x4-acc2.c", |
| "src/f32-dwconv2d-chw/gen/f32-dwconv2d-chw-3x3s2p1-minmax-wasmsimd-x86-loadsplat-2x4.c", |
| "src/f32-dwconv2d-chw/gen/f32-dwconv2d-chw-3x3s2p1-minmax-wasmsimd-x86-loadsplat-3x4.c", |
| "src/f32-dwconv2d-chw/gen/f32-dwconv2d-chw-3x3s2p1-minmax-wasmsimd-x86-loadsplat-4x4.c", |
| "src/f32-dwconv2d-chw/gen/f32-dwconv2d-chw-3x3s2p1-minmax-wasmsimd-x86-splat-1x4-acc2.c", |
| "src/f32-dwconv2d-chw/gen/f32-dwconv2d-chw-3x3s2p1-minmax-wasmsimd-x86-splat-1x4-acc3.c", |
| "src/f32-dwconv2d-chw/gen/f32-dwconv2d-chw-3x3s2p1-minmax-wasmsimd-x86-splat-1x4-acc4.c", |
| "src/f32-dwconv2d-chw/gen/f32-dwconv2d-chw-3x3s2p1-minmax-wasmsimd-x86-splat-1x4.c", |
| "src/f32-dwconv2d-chw/gen/f32-dwconv2d-chw-3x3s2p1-minmax-wasmsimd-x86-splat-2x4-acc2.c", |
| "src/f32-dwconv2d-chw/gen/f32-dwconv2d-chw-3x3s2p1-minmax-wasmsimd-x86-splat-2x4.c", |
| "src/f32-dwconv2d-chw/gen/f32-dwconv2d-chw-3x3s2p1-minmax-wasmsimd-x86-splat-3x4.c", |
| "src/f32-dwconv2d-chw/gen/f32-dwconv2d-chw-3x3s2p1-minmax-wasmsimd-x86-splat-4x4.c", |
| "src/f32-dwconv2d-chw/gen/f32-dwconv2d-chw-5x5p2-minmax-wasmsimd-arm-loadsplat-1x4-acc2.c", |
| "src/f32-dwconv2d-chw/gen/f32-dwconv2d-chw-5x5p2-minmax-wasmsimd-arm-loadsplat-1x4-acc3.c", |
| "src/f32-dwconv2d-chw/gen/f32-dwconv2d-chw-5x5p2-minmax-wasmsimd-arm-loadsplat-1x4-acc4.c", |
| "src/f32-dwconv2d-chw/gen/f32-dwconv2d-chw-5x5p2-minmax-wasmsimd-arm-loadsplat-1x4-acc5.c", |
| "src/f32-dwconv2d-chw/gen/f32-dwconv2d-chw-5x5p2-minmax-wasmsimd-arm-loadsplat-1x4.c", |
| "src/f32-dwconv2d-chw/gen/f32-dwconv2d-chw-5x5p2-minmax-wasmsimd-arm-loadsplat-2x4-acc2.c", |
| "src/f32-dwconv2d-chw/gen/f32-dwconv2d-chw-5x5p2-minmax-wasmsimd-arm-loadsplat-2x4-acc3.c", |
| "src/f32-dwconv2d-chw/gen/f32-dwconv2d-chw-5x5p2-minmax-wasmsimd-arm-loadsplat-2x4.c", |
| "src/f32-dwconv2d-chw/gen/f32-dwconv2d-chw-5x5p2-minmax-wasmsimd-arm-loadsplat-3x4-acc2.c", |
| "src/f32-dwconv2d-chw/gen/f32-dwconv2d-chw-5x5p2-minmax-wasmsimd-arm-loadsplat-3x4.c", |
| "src/f32-dwconv2d-chw/gen/f32-dwconv2d-chw-5x5p2-minmax-wasmsimd-arm-loadsplat-4x4-acc2.c", |
| "src/f32-dwconv2d-chw/gen/f32-dwconv2d-chw-5x5p2-minmax-wasmsimd-arm-loadsplat-4x4.c", |
| "src/f32-dwconv2d-chw/gen/f32-dwconv2d-chw-5x5p2-minmax-wasmsimd-arm-loadsplat-5x4.c", |
| "src/f32-dwconv2d-chw/gen/f32-dwconv2d-chw-5x5p2-minmax-wasmsimd-arm-splat-1x4-acc2.c", |
| "src/f32-dwconv2d-chw/gen/f32-dwconv2d-chw-5x5p2-minmax-wasmsimd-arm-splat-1x4-acc3.c", |
| "src/f32-dwconv2d-chw/gen/f32-dwconv2d-chw-5x5p2-minmax-wasmsimd-arm-splat-1x4-acc4.c", |
| "src/f32-dwconv2d-chw/gen/f32-dwconv2d-chw-5x5p2-minmax-wasmsimd-arm-splat-1x4-acc5.c", |
| "src/f32-dwconv2d-chw/gen/f32-dwconv2d-chw-5x5p2-minmax-wasmsimd-arm-splat-1x4.c", |
| "src/f32-dwconv2d-chw/gen/f32-dwconv2d-chw-5x5p2-minmax-wasmsimd-arm-splat-2x4-acc2.c", |
| "src/f32-dwconv2d-chw/gen/f32-dwconv2d-chw-5x5p2-minmax-wasmsimd-arm-splat-2x4-acc3.c", |
| "src/f32-dwconv2d-chw/gen/f32-dwconv2d-chw-5x5p2-minmax-wasmsimd-arm-splat-2x4.c", |
| "src/f32-dwconv2d-chw/gen/f32-dwconv2d-chw-5x5p2-minmax-wasmsimd-arm-splat-3x4-acc2.c", |
| "src/f32-dwconv2d-chw/gen/f32-dwconv2d-chw-5x5p2-minmax-wasmsimd-arm-splat-3x4.c", |
| "src/f32-dwconv2d-chw/gen/f32-dwconv2d-chw-5x5p2-minmax-wasmsimd-arm-splat-4x4-acc2.c", |
| "src/f32-dwconv2d-chw/gen/f32-dwconv2d-chw-5x5p2-minmax-wasmsimd-arm-splat-4x4.c", |
| "src/f32-dwconv2d-chw/gen/f32-dwconv2d-chw-5x5p2-minmax-wasmsimd-arm-splat-5x4.c", |
| "src/f32-dwconv2d-chw/gen/f32-dwconv2d-chw-5x5p2-minmax-wasmsimd-x86-loadsplat-1x4-acc2.c", |
| "src/f32-dwconv2d-chw/gen/f32-dwconv2d-chw-5x5p2-minmax-wasmsimd-x86-loadsplat-1x4-acc3.c", |
| "src/f32-dwconv2d-chw/gen/f32-dwconv2d-chw-5x5p2-minmax-wasmsimd-x86-loadsplat-1x4-acc4.c", |
| "src/f32-dwconv2d-chw/gen/f32-dwconv2d-chw-5x5p2-minmax-wasmsimd-x86-loadsplat-1x4-acc5.c", |
| "src/f32-dwconv2d-chw/gen/f32-dwconv2d-chw-5x5p2-minmax-wasmsimd-x86-loadsplat-1x4.c", |
| "src/f32-dwconv2d-chw/gen/f32-dwconv2d-chw-5x5p2-minmax-wasmsimd-x86-loadsplat-2x4-acc2.c", |
| "src/f32-dwconv2d-chw/gen/f32-dwconv2d-chw-5x5p2-minmax-wasmsimd-x86-loadsplat-2x4-acc3.c", |
| "src/f32-dwconv2d-chw/gen/f32-dwconv2d-chw-5x5p2-minmax-wasmsimd-x86-loadsplat-2x4.c", |
| "src/f32-dwconv2d-chw/gen/f32-dwconv2d-chw-5x5p2-minmax-wasmsimd-x86-loadsplat-3x4-acc2.c", |
| "src/f32-dwconv2d-chw/gen/f32-dwconv2d-chw-5x5p2-minmax-wasmsimd-x86-loadsplat-3x4.c", |
| "src/f32-dwconv2d-chw/gen/f32-dwconv2d-chw-5x5p2-minmax-wasmsimd-x86-loadsplat-4x4-acc2.c", |
| "src/f32-dwconv2d-chw/gen/f32-dwconv2d-chw-5x5p2-minmax-wasmsimd-x86-loadsplat-4x4.c", |
| "src/f32-dwconv2d-chw/gen/f32-dwconv2d-chw-5x5p2-minmax-wasmsimd-x86-loadsplat-5x4.c", |
| "src/f32-dwconv2d-chw/gen/f32-dwconv2d-chw-5x5p2-minmax-wasmsimd-x86-splat-1x4-acc2.c", |
| "src/f32-dwconv2d-chw/gen/f32-dwconv2d-chw-5x5p2-minmax-wasmsimd-x86-splat-1x4-acc3.c", |
| "src/f32-dwconv2d-chw/gen/f32-dwconv2d-chw-5x5p2-minmax-wasmsimd-x86-splat-1x4-acc4.c", |
| "src/f32-dwconv2d-chw/gen/f32-dwconv2d-chw-5x5p2-minmax-wasmsimd-x86-splat-1x4-acc5.c", |
| "src/f32-dwconv2d-chw/gen/f32-dwconv2d-chw-5x5p2-minmax-wasmsimd-x86-splat-1x4.c", |
| "src/f32-dwconv2d-chw/gen/f32-dwconv2d-chw-5x5p2-minmax-wasmsimd-x86-splat-2x4-acc2.c", |
| "src/f32-dwconv2d-chw/gen/f32-dwconv2d-chw-5x5p2-minmax-wasmsimd-x86-splat-2x4-acc3.c", |
| "src/f32-dwconv2d-chw/gen/f32-dwconv2d-chw-5x5p2-minmax-wasmsimd-x86-splat-2x4.c", |
| "src/f32-dwconv2d-chw/gen/f32-dwconv2d-chw-5x5p2-minmax-wasmsimd-x86-splat-3x4-acc2.c", |
| "src/f32-dwconv2d-chw/gen/f32-dwconv2d-chw-5x5p2-minmax-wasmsimd-x86-splat-3x4.c", |
| "src/f32-dwconv2d-chw/gen/f32-dwconv2d-chw-5x5p2-minmax-wasmsimd-x86-splat-4x4-acc2.c", |
| "src/f32-dwconv2d-chw/gen/f32-dwconv2d-chw-5x5p2-minmax-wasmsimd-x86-splat-4x4.c", |
| "src/f32-dwconv2d-chw/gen/f32-dwconv2d-chw-5x5p2-minmax-wasmsimd-x86-splat-5x4.c", |
| "src/f32-dwconv2d-chw/gen/f32-dwconv2d-chw-5x5s2p2-minmax-wasmsimd-arm-loadsplat-1x4-acc2.c", |
| "src/f32-dwconv2d-chw/gen/f32-dwconv2d-chw-5x5s2p2-minmax-wasmsimd-arm-loadsplat-1x4-acc3.c", |
| "src/f32-dwconv2d-chw/gen/f32-dwconv2d-chw-5x5s2p2-minmax-wasmsimd-arm-loadsplat-1x4-acc4.c", |
| "src/f32-dwconv2d-chw/gen/f32-dwconv2d-chw-5x5s2p2-minmax-wasmsimd-arm-loadsplat-1x4-acc5.c", |
| "src/f32-dwconv2d-chw/gen/f32-dwconv2d-chw-5x5s2p2-minmax-wasmsimd-arm-loadsplat-1x4.c", |
| "src/f32-dwconv2d-chw/gen/f32-dwconv2d-chw-5x5s2p2-minmax-wasmsimd-arm-loadsplat-2x4-acc2.c", |
| "src/f32-dwconv2d-chw/gen/f32-dwconv2d-chw-5x5s2p2-minmax-wasmsimd-arm-loadsplat-2x4-acc3.c", |
| "src/f32-dwconv2d-chw/gen/f32-dwconv2d-chw-5x5s2p2-minmax-wasmsimd-arm-loadsplat-2x4.c", |
| "src/f32-dwconv2d-chw/gen/f32-dwconv2d-chw-5x5s2p2-minmax-wasmsimd-arm-loadsplat-3x4-acc2.c", |
| "src/f32-dwconv2d-chw/gen/f32-dwconv2d-chw-5x5s2p2-minmax-wasmsimd-arm-loadsplat-3x4.c", |
| "src/f32-dwconv2d-chw/gen/f32-dwconv2d-chw-5x5s2p2-minmax-wasmsimd-arm-splat-1x4-acc2.c", |
| "src/f32-dwconv2d-chw/gen/f32-dwconv2d-chw-5x5s2p2-minmax-wasmsimd-arm-splat-1x4-acc3.c", |
| "src/f32-dwconv2d-chw/gen/f32-dwconv2d-chw-5x5s2p2-minmax-wasmsimd-arm-splat-1x4-acc4.c", |
| "src/f32-dwconv2d-chw/gen/f32-dwconv2d-chw-5x5s2p2-minmax-wasmsimd-arm-splat-1x4-acc5.c", |
| "src/f32-dwconv2d-chw/gen/f32-dwconv2d-chw-5x5s2p2-minmax-wasmsimd-arm-splat-1x4.c", |
| "src/f32-dwconv2d-chw/gen/f32-dwconv2d-chw-5x5s2p2-minmax-wasmsimd-arm-splat-2x4-acc2.c", |
| "src/f32-dwconv2d-chw/gen/f32-dwconv2d-chw-5x5s2p2-minmax-wasmsimd-arm-splat-2x4-acc3.c", |
| "src/f32-dwconv2d-chw/gen/f32-dwconv2d-chw-5x5s2p2-minmax-wasmsimd-arm-splat-2x4.c", |
| "src/f32-dwconv2d-chw/gen/f32-dwconv2d-chw-5x5s2p2-minmax-wasmsimd-arm-splat-3x4-acc2.c", |
| "src/f32-dwconv2d-chw/gen/f32-dwconv2d-chw-5x5s2p2-minmax-wasmsimd-arm-splat-3x4.c", |
| "src/f32-dwconv2d-chw/gen/f32-dwconv2d-chw-5x5s2p2-minmax-wasmsimd-x86-loadsplat-1x4-acc2.c", |
| "src/f32-dwconv2d-chw/gen/f32-dwconv2d-chw-5x5s2p2-minmax-wasmsimd-x86-loadsplat-1x4-acc3.c", |
| "src/f32-dwconv2d-chw/gen/f32-dwconv2d-chw-5x5s2p2-minmax-wasmsimd-x86-loadsplat-1x4-acc4.c", |
| "src/f32-dwconv2d-chw/gen/f32-dwconv2d-chw-5x5s2p2-minmax-wasmsimd-x86-loadsplat-1x4-acc5.c", |
| "src/f32-dwconv2d-chw/gen/f32-dwconv2d-chw-5x5s2p2-minmax-wasmsimd-x86-loadsplat-1x4.c", |
| "src/f32-dwconv2d-chw/gen/f32-dwconv2d-chw-5x5s2p2-minmax-wasmsimd-x86-loadsplat-2x4-acc2.c", |
| "src/f32-dwconv2d-chw/gen/f32-dwconv2d-chw-5x5s2p2-minmax-wasmsimd-x86-loadsplat-2x4-acc3.c", |
| "src/f32-dwconv2d-chw/gen/f32-dwconv2d-chw-5x5s2p2-minmax-wasmsimd-x86-loadsplat-2x4.c", |
| "src/f32-dwconv2d-chw/gen/f32-dwconv2d-chw-5x5s2p2-minmax-wasmsimd-x86-loadsplat-3x4-acc2.c", |
| "src/f32-dwconv2d-chw/gen/f32-dwconv2d-chw-5x5s2p2-minmax-wasmsimd-x86-loadsplat-3x4.c", |
| "src/f32-dwconv2d-chw/gen/f32-dwconv2d-chw-5x5s2p2-minmax-wasmsimd-x86-splat-1x4-acc2.c", |
| "src/f32-dwconv2d-chw/gen/f32-dwconv2d-chw-5x5s2p2-minmax-wasmsimd-x86-splat-1x4-acc3.c", |
| "src/f32-dwconv2d-chw/gen/f32-dwconv2d-chw-5x5s2p2-minmax-wasmsimd-x86-splat-1x4-acc4.c", |
| "src/f32-dwconv2d-chw/gen/f32-dwconv2d-chw-5x5s2p2-minmax-wasmsimd-x86-splat-1x4-acc5.c", |
| "src/f32-dwconv2d-chw/gen/f32-dwconv2d-chw-5x5s2p2-minmax-wasmsimd-x86-splat-1x4.c", |
| "src/f32-dwconv2d-chw/gen/f32-dwconv2d-chw-5x5s2p2-minmax-wasmsimd-x86-splat-2x4-acc2.c", |
| "src/f32-dwconv2d-chw/gen/f32-dwconv2d-chw-5x5s2p2-minmax-wasmsimd-x86-splat-2x4-acc3.c", |
| "src/f32-dwconv2d-chw/gen/f32-dwconv2d-chw-5x5s2p2-minmax-wasmsimd-x86-splat-2x4.c", |
| "src/f32-dwconv2d-chw/gen/f32-dwconv2d-chw-5x5s2p2-minmax-wasmsimd-x86-splat-3x4-acc2.c", |
| "src/f32-dwconv2d-chw/gen/f32-dwconv2d-chw-5x5s2p2-minmax-wasmsimd-x86-splat-3x4.c", |
| "src/f32-dwconv/gen/f32-dwconv-3f3m3l4c4s4r-minmax-wasmsimd-arm-acc2.c", |
| "src/f32-dwconv/gen/f32-dwconv-3f3m3l4c4s4r-minmax-wasmsimd-arm.c", |
| "src/f32-dwconv/gen/f32-dwconv-3f3m3l4c4s4r-minmax-wasmsimd-x86-acc2.c", |
| "src/f32-dwconv/gen/f32-dwconv-3f3m3l4c4s4r-minmax-wasmsimd-x86.c", |
| "src/f32-dwconv/gen/f32-dwconv-3f3m3l4c4s4r-wasmsimd-acc2.c", |
| "src/f32-dwconv/gen/f32-dwconv-3f3m3l4c4s4r-wasmsimd.c", |
| "src/f32-dwconv/gen/f32-dwconv-3f3m3l8c4s4r-minmax-wasmsimd-arm-acc2.c", |
| "src/f32-dwconv/gen/f32-dwconv-3f3m3l8c4s4r-minmax-wasmsimd-arm.c", |
| "src/f32-dwconv/gen/f32-dwconv-3f3m3l8c4s4r-minmax-wasmsimd-x86-acc2.c", |
| "src/f32-dwconv/gen/f32-dwconv-3f3m3l8c4s4r-minmax-wasmsimd-x86.c", |
| "src/f32-dwconv/gen/f32-dwconv-3f3m3l8c4s4r-wasmsimd-acc2.c", |
| "src/f32-dwconv/gen/f32-dwconv-3f3m3l8c4s4r-wasmsimd.c", |
| "src/f32-dwconv/gen/f32-dwconv-3p4c-minmax-wasmsimd-arm-acc2.c", |
| "src/f32-dwconv/gen/f32-dwconv-3p4c-minmax-wasmsimd-arm.c", |
| "src/f32-dwconv/gen/f32-dwconv-3p4c-minmax-wasmsimd-x86-acc2.c", |
| "src/f32-dwconv/gen/f32-dwconv-3p4c-minmax-wasmsimd-x86.c", |
| "src/f32-dwconv/gen/f32-dwconv-3p4c-wasmsimd.c", |
| "src/f32-dwconv/gen/f32-dwconv-3p8c-minmax-wasmsimd-arm-acc2.c", |
| "src/f32-dwconv/gen/f32-dwconv-3p8c-minmax-wasmsimd-arm.c", |
| "src/f32-dwconv/gen/f32-dwconv-3p8c-minmax-wasmsimd-x86-acc2.c", |
| "src/f32-dwconv/gen/f32-dwconv-3p8c-minmax-wasmsimd-x86.c", |
| "src/f32-dwconv/gen/f32-dwconv-3p8c-wasmsimd.c", |
| "src/f32-dwconv/gen/f32-dwconv-4p4c-minmax-wasmsimd-arm-acc2.c", |
| "src/f32-dwconv/gen/f32-dwconv-4p4c-minmax-wasmsimd-arm.c", |
| "src/f32-dwconv/gen/f32-dwconv-4p4c-minmax-wasmsimd-x86-acc2.c", |
| "src/f32-dwconv/gen/f32-dwconv-4p4c-minmax-wasmsimd-x86.c", |
| "src/f32-dwconv/gen/f32-dwconv-4p4c-wasmsimd.c", |
| "src/f32-dwconv/gen/f32-dwconv-4p8c-minmax-wasmsimd-arm-acc2.c", |
| "src/f32-dwconv/gen/f32-dwconv-4p8c-minmax-wasmsimd-arm.c", |
| "src/f32-dwconv/gen/f32-dwconv-4p8c-minmax-wasmsimd-x86-acc2.c", |
| "src/f32-dwconv/gen/f32-dwconv-4p8c-minmax-wasmsimd-x86.c", |
| "src/f32-dwconv/gen/f32-dwconv-4p8c-wasmsimd.c", |
| "src/f32-dwconv/gen/f32-dwconv-5f5m5l4c4s4r-minmax-wasmsimd-arm-acc2.c", |
| "src/f32-dwconv/gen/f32-dwconv-5f5m5l4c4s4r-minmax-wasmsimd-arm.c", |
| "src/f32-dwconv/gen/f32-dwconv-5f5m5l4c4s4r-minmax-wasmsimd-x86-acc2.c", |
| "src/f32-dwconv/gen/f32-dwconv-5f5m5l4c4s4r-minmax-wasmsimd-x86.c", |
| "src/f32-dwconv/gen/f32-dwconv-5f5m5l4c4s4r-wasmsimd-acc2.c", |
| "src/f32-dwconv/gen/f32-dwconv-5f5m5l4c4s4r-wasmsimd.c", |
| "src/f32-dwconv/gen/f32-dwconv-9p4c-minmax-wasmsimd-arm-acc2.c", |
| "src/f32-dwconv/gen/f32-dwconv-9p4c-minmax-wasmsimd-arm.c", |
| "src/f32-dwconv/gen/f32-dwconv-9p4c-minmax-wasmsimd-x86-acc2.c", |
| "src/f32-dwconv/gen/f32-dwconv-9p4c-minmax-wasmsimd-x86.c", |
| "src/f32-dwconv/gen/f32-dwconv-9p4c-wasmsimd-acc2.c", |
| "src/f32-dwconv/gen/f32-dwconv-9p4c-wasmsimd.c", |
| "src/f32-dwconv/gen/f32-dwconv-9p8c-minmax-wasmsimd-arm-acc2.c", |
| "src/f32-dwconv/gen/f32-dwconv-9p8c-minmax-wasmsimd-arm.c", |
| "src/f32-dwconv/gen/f32-dwconv-9p8c-minmax-wasmsimd-x86-acc2.c", |
| "src/f32-dwconv/gen/f32-dwconv-9p8c-minmax-wasmsimd-x86.c", |
| "src/f32-dwconv/gen/f32-dwconv-9p8c-wasmsimd-acc2.c", |
| "src/f32-dwconv/gen/f32-dwconv-9p8c-wasmsimd.c", |
| "src/f32-dwconv/gen/f32-dwconv-25p4c-minmax-wasmsimd-arm-acc2.c", |
| "src/f32-dwconv/gen/f32-dwconv-25p4c-minmax-wasmsimd-arm.c", |
| "src/f32-dwconv/gen/f32-dwconv-25p4c-minmax-wasmsimd-x86-acc2.c", |
| "src/f32-dwconv/gen/f32-dwconv-25p4c-minmax-wasmsimd-x86.c", |
| "src/f32-dwconv/gen/f32-dwconv-25p4c-wasmsimd.c", |
| "src/f32-dwconv/gen/f32-dwconv-25p8c-minmax-wasmsimd-arm-acc2.c", |
| "src/f32-dwconv/gen/f32-dwconv-25p8c-minmax-wasmsimd-arm.c", |
| "src/f32-dwconv/gen/f32-dwconv-25p8c-minmax-wasmsimd-x86-acc2.c", |
| "src/f32-dwconv/gen/f32-dwconv-25p8c-minmax-wasmsimd-x86.c", |
| "src/f32-dwconv/gen/f32-dwconv-25p8c-wasmsimd.c", |
| "src/f32-f16-vcvt/gen/f32-f16-vcvt-wasmsimd-u8.c", |
| "src/f32-f16-vcvt/gen/f32-f16-vcvt-wasmsimd-u16.c", |
| "src/f32-f16-vcvt/gen/f32-f16-vcvt-wasmsimd-u24.c", |
| "src/f32-f16-vcvt/gen/f32-f16-vcvt-wasmsimd-u32.c", |
| "src/f32-gavgpool-cw/f32-gavgpool-cw-wasmsimd-arm-x4.c", |
| "src/f32-gavgpool-cw/f32-gavgpool-cw-wasmsimd-x86-x4.c", |
| "src/f32-gavgpool/f32-gavgpool-7p7x-minmax-wasmsimd-arm-c4.c", |
| "src/f32-gavgpool/f32-gavgpool-7p7x-minmax-wasmsimd-x86-c4.c", |
| "src/f32-gavgpool/f32-gavgpool-7x-minmax-wasmsimd-arm-c4.c", |
| "src/f32-gavgpool/f32-gavgpool-7x-minmax-wasmsimd-x86-c4.c", |
| "src/f32-gemm/gen/f32-gemm-1x8-minmax-wasmsimd-arm-loadsplat.c", |
| "src/f32-gemm/gen/f32-gemm-1x8-minmax-wasmsimd-arm-splat.c", |
| "src/f32-gemm/gen/f32-gemm-1x8-minmax-wasmsimd-x86-loadsplat.c", |
| "src/f32-gemm/gen/f32-gemm-1x8-minmax-wasmsimd-x86-splat.c", |
| "src/f32-gemm/gen/f32-gemm-1x8-relu-wasmsimd-loadsplat.c", |
| "src/f32-gemm/gen/f32-gemm-1x8-relu-wasmsimd-splat.c", |
| "src/f32-gemm/gen/f32-gemm-1x8-wasmsimd-loadsplat.c", |
| "src/f32-gemm/gen/f32-gemm-1x8-wasmsimd-splat.c", |
| "src/f32-gemm/gen/f32-gemm-1x8s4-minmax-wasmsimd-arm.c", |
| "src/f32-gemm/gen/f32-gemm-1x8s4-minmax-wasmsimd-x86.c", |
| "src/f32-gemm/gen/f32-gemm-1x8s4-relu-wasmsimd.c", |
| "src/f32-gemm/gen/f32-gemm-1x8s4-wasmsimd.c", |
| "src/f32-gemm/gen/f32-gemm-3x8-minmax-wasmsimd-arm-loadsplat.c", |
| "src/f32-gemm/gen/f32-gemm-3x8-minmax-wasmsimd-arm-splat.c", |
| "src/f32-gemm/gen/f32-gemm-3x8-minmax-wasmsimd-x86-loadsplat.c", |
| "src/f32-gemm/gen/f32-gemm-3x8-minmax-wasmsimd-x86-splat.c", |
| "src/f32-gemm/gen/f32-gemm-3x8-relu-wasmsimd-loadsplat.c", |
| "src/f32-gemm/gen/f32-gemm-3x8-relu-wasmsimd-splat.c", |
| "src/f32-gemm/gen/f32-gemm-3x8-wasmsimd-loadsplat.c", |
| "src/f32-gemm/gen/f32-gemm-3x8-wasmsimd-splat.c", |
| "src/f32-gemm/gen/f32-gemm-3x8s4-minmax-wasmsimd-arm.c", |
| "src/f32-gemm/gen/f32-gemm-3x8s4-minmax-wasmsimd-x86.c", |
| "src/f32-gemm/gen/f32-gemm-3x8s4-relu-wasmsimd.c", |
| "src/f32-gemm/gen/f32-gemm-3x8s4-wasmsimd.c", |
| "src/f32-gemm/gen/f32-gemm-4x2c4-minmax-wasmsimd-arm.c", |
| "src/f32-gemm/gen/f32-gemm-4x2c4-minmax-wasmsimd-x86.c", |
| "src/f32-gemm/gen/f32-gemm-4x2c4-relu-wasmsimd.c", |
| "src/f32-gemm/gen/f32-gemm-4x2c4-wasmsimd.c", |
| "src/f32-gemm/gen/f32-gemm-4x8-minmax-wasmsimd-arm-loadsplat.c", |
| "src/f32-gemm/gen/f32-gemm-4x8-minmax-wasmsimd-arm-splat.c", |
| "src/f32-gemm/gen/f32-gemm-4x8-minmax-wasmsimd-x86-loadsplat.c", |
| "src/f32-gemm/gen/f32-gemm-4x8-minmax-wasmsimd-x86-splat.c", |
| "src/f32-gemm/gen/f32-gemm-4x8-relu-wasmsimd-loadsplat.c", |
| "src/f32-gemm/gen/f32-gemm-4x8-relu-wasmsimd-splat.c", |
| "src/f32-gemm/gen/f32-gemm-4x8-wasmsimd-loadsplat.c", |
| "src/f32-gemm/gen/f32-gemm-4x8-wasmsimd-splat.c", |
| "src/f32-gemm/gen/f32-gemm-4x8s4-minmax-wasmsimd-arm.c", |
| "src/f32-gemm/gen/f32-gemm-4x8s4-minmax-wasmsimd-x86.c", |
| "src/f32-gemm/gen/f32-gemm-4x8s4-relu-wasmsimd.c", |
| "src/f32-gemm/gen/f32-gemm-4x8s4-wasmsimd.c", |
| "src/f32-gemm/gen/f32-gemm-5x8-minmax-wasmsimd-arm-loadsplat.c", |
| "src/f32-gemm/gen/f32-gemm-5x8-minmax-wasmsimd-arm-splat.c", |
| "src/f32-gemm/gen/f32-gemm-5x8-minmax-wasmsimd-x86-loadsplat.c", |
| "src/f32-gemm/gen/f32-gemm-5x8-minmax-wasmsimd-x86-splat.c", |
| "src/f32-gemm/gen/f32-gemm-5x8-relu-wasmsimd-loadsplat.c", |
| "src/f32-gemm/gen/f32-gemm-5x8-relu-wasmsimd-splat.c", |
| "src/f32-gemm/gen/f32-gemm-5x8-wasmsimd-loadsplat.c", |
| "src/f32-gemm/gen/f32-gemm-5x8-wasmsimd-splat.c", |
| "src/f32-gemm/gen/f32-gemm-5x8s4-minmax-wasmsimd-arm.c", |
| "src/f32-gemm/gen/f32-gemm-5x8s4-minmax-wasmsimd-x86.c", |
| "src/f32-gemm/gen/f32-gemm-5x8s4-relu-wasmsimd.c", |
| "src/f32-gemm/gen/f32-gemm-5x8s4-wasmsimd.c", |
| "src/f32-gemm/gen/f32-gemm-6x8-minmax-wasmsimd-arm-loadsplat.c", |
| "src/f32-gemm/gen/f32-gemm-6x8-minmax-wasmsimd-arm-splat.c", |
| "src/f32-gemm/gen/f32-gemm-6x8-minmax-wasmsimd-x86-loadsplat.c", |
| "src/f32-gemm/gen/f32-gemm-6x8-minmax-wasmsimd-x86-splat.c", |
| "src/f32-gemm/gen/f32-gemm-6x8-relu-wasmsimd-loadsplat.c", |
| "src/f32-gemm/gen/f32-gemm-6x8-relu-wasmsimd-splat.c", |
| "src/f32-gemm/gen/f32-gemm-6x8-wasmsimd-loadsplat.c", |
| "src/f32-gemm/gen/f32-gemm-6x8-wasmsimd-splat.c", |
| "src/f32-gemm/gen/f32-gemm-6x8s4-minmax-wasmsimd-arm.c", |
| "src/f32-gemm/gen/f32-gemm-6x8s4-minmax-wasmsimd-x86.c", |
| "src/f32-gemm/gen/f32-gemm-6x8s4-relu-wasmsimd.c", |
| "src/f32-gemm/gen/f32-gemm-6x8s4-wasmsimd.c", |
| "src/f32-gemminc/gen/f32-gemminc-1x8-minmax-wasmsimd-arm-loadsplat.c", |
| "src/f32-gemminc/gen/f32-gemminc-1x8-minmax-wasmsimd-arm-splat.c", |
| "src/f32-gemminc/gen/f32-gemminc-1x8-minmax-wasmsimd-x86-loadsplat.c", |
| "src/f32-gemminc/gen/f32-gemminc-1x8-minmax-wasmsimd-x86-splat.c", |
| "src/f32-gemminc/gen/f32-gemminc-1x8s4-minmax-wasmsimd-arm.c", |
| "src/f32-gemminc/gen/f32-gemminc-1x8s4-minmax-wasmsimd-x86.c", |
| "src/f32-gemminc/gen/f32-gemminc-3x8-minmax-wasmsimd-arm-loadsplat.c", |
| "src/f32-gemminc/gen/f32-gemminc-3x8-minmax-wasmsimd-arm-splat.c", |
| "src/f32-gemminc/gen/f32-gemminc-3x8-minmax-wasmsimd-x86-loadsplat.c", |
| "src/f32-gemminc/gen/f32-gemminc-3x8-minmax-wasmsimd-x86-splat.c", |
| "src/f32-gemminc/gen/f32-gemminc-3x8s4-minmax-wasmsimd-arm.c", |
| "src/f32-gemminc/gen/f32-gemminc-3x8s4-minmax-wasmsimd-x86.c", |
| "src/f32-gemminc/gen/f32-gemminc-4x8-minmax-wasmsimd-arm-loadsplat.c", |
| "src/f32-gemminc/gen/f32-gemminc-4x8-minmax-wasmsimd-arm-splat.c", |
| "src/f32-gemminc/gen/f32-gemminc-4x8-minmax-wasmsimd-x86-loadsplat.c", |
| "src/f32-gemminc/gen/f32-gemminc-4x8-minmax-wasmsimd-x86-splat.c", |
| "src/f32-gemminc/gen/f32-gemminc-4x8s4-minmax-wasmsimd-arm.c", |
| "src/f32-gemminc/gen/f32-gemminc-4x8s4-minmax-wasmsimd-x86.c", |
| "src/f32-gemminc/gen/f32-gemminc-5x8-minmax-wasmsimd-arm-loadsplat.c", |
| "src/f32-gemminc/gen/f32-gemminc-5x8-minmax-wasmsimd-arm-splat.c", |
| "src/f32-gemminc/gen/f32-gemminc-5x8-minmax-wasmsimd-x86-loadsplat.c", |
| "src/f32-gemminc/gen/f32-gemminc-5x8-minmax-wasmsimd-x86-splat.c", |
| "src/f32-gemminc/gen/f32-gemminc-5x8s4-minmax-wasmsimd-arm.c", |
| "src/f32-gemminc/gen/f32-gemminc-5x8s4-minmax-wasmsimd-x86.c", |
| "src/f32-gemminc/gen/f32-gemminc-6x8-minmax-wasmsimd-arm-loadsplat.c", |
| "src/f32-gemminc/gen/f32-gemminc-6x8-minmax-wasmsimd-arm-splat.c", |
| "src/f32-gemminc/gen/f32-gemminc-6x8-minmax-wasmsimd-x86-loadsplat.c", |
| "src/f32-gemminc/gen/f32-gemminc-6x8-minmax-wasmsimd-x86-splat.c", |
| "src/f32-gemminc/gen/f32-gemminc-6x8s4-minmax-wasmsimd-arm.c", |
| "src/f32-gemminc/gen/f32-gemminc-6x8s4-minmax-wasmsimd-x86.c", |
| "src/f32-ibilinear-chw/gen/f32-ibilinear-chw-wasmsimd-p4.c", |
| "src/f32-ibilinear-chw/gen/f32-ibilinear-chw-wasmsimd-p8.c", |
| "src/f32-ibilinear/gen/f32-ibilinear-wasmsimd-c4.c", |
| "src/f32-ibilinear/gen/f32-ibilinear-wasmsimd-c8.c", |
| "src/f32-igemm/gen/f32-igemm-1x8-minmax-wasmsimd-arm-loadsplat.c", |
| "src/f32-igemm/gen/f32-igemm-1x8-minmax-wasmsimd-arm-splat.c", |
| "src/f32-igemm/gen/f32-igemm-1x8-minmax-wasmsimd-x86-loadsplat.c", |
| "src/f32-igemm/gen/f32-igemm-1x8-minmax-wasmsimd-x86-splat.c", |
| "src/f32-igemm/gen/f32-igemm-1x8-relu-wasmsimd-loadsplat.c", |
| "src/f32-igemm/gen/f32-igemm-1x8-relu-wasmsimd-splat.c", |
| "src/f32-igemm/gen/f32-igemm-1x8-wasmsimd-loadsplat.c", |
| "src/f32-igemm/gen/f32-igemm-1x8-wasmsimd-splat.c", |
| "src/f32-igemm/gen/f32-igemm-1x8s4-minmax-wasmsimd-arm.c", |
| "src/f32-igemm/gen/f32-igemm-1x8s4-minmax-wasmsimd-x86.c", |
| "src/f32-igemm/gen/f32-igemm-1x8s4-relu-wasmsimd.c", |
| "src/f32-igemm/gen/f32-igemm-1x8s4-wasmsimd.c", |
| "src/f32-igemm/gen/f32-igemm-3x8-minmax-wasmsimd-arm-loadsplat.c", |
| "src/f32-igemm/gen/f32-igemm-3x8-minmax-wasmsimd-arm-splat.c", |
| "src/f32-igemm/gen/f32-igemm-3x8-minmax-wasmsimd-x86-loadsplat.c", |
| "src/f32-igemm/gen/f32-igemm-3x8-minmax-wasmsimd-x86-splat.c", |
| "src/f32-igemm/gen/f32-igemm-3x8-relu-wasmsimd-loadsplat.c", |
| "src/f32-igemm/gen/f32-igemm-3x8-relu-wasmsimd-splat.c", |
| "src/f32-igemm/gen/f32-igemm-3x8-wasmsimd-loadsplat.c", |
| "src/f32-igemm/gen/f32-igemm-3x8-wasmsimd-splat.c", |
| "src/f32-igemm/gen/f32-igemm-3x8s4-minmax-wasmsimd-arm.c", |
| "src/f32-igemm/gen/f32-igemm-3x8s4-minmax-wasmsimd-x86.c", |
| "src/f32-igemm/gen/f32-igemm-3x8s4-relu-wasmsimd.c", |
| "src/f32-igemm/gen/f32-igemm-3x8s4-wasmsimd.c", |
| "src/f32-igemm/gen/f32-igemm-4x2c4-minmax-wasmsimd-arm.c", |
| "src/f32-igemm/gen/f32-igemm-4x2c4-minmax-wasmsimd-x86.c", |
| "src/f32-igemm/gen/f32-igemm-4x2c4-relu-wasmsimd.c", |
| "src/f32-igemm/gen/f32-igemm-4x2c4-wasmsimd.c", |
| "src/f32-igemm/gen/f32-igemm-4x8-minmax-wasmsimd-arm-loadsplat.c", |
| "src/f32-igemm/gen/f32-igemm-4x8-minmax-wasmsimd-arm-splat.c", |
| "src/f32-igemm/gen/f32-igemm-4x8-minmax-wasmsimd-x86-loadsplat.c", |
| "src/f32-igemm/gen/f32-igemm-4x8-minmax-wasmsimd-x86-splat.c", |
| "src/f32-igemm/gen/f32-igemm-4x8-relu-wasmsimd-loadsplat.c", |
| "src/f32-igemm/gen/f32-igemm-4x8-relu-wasmsimd-splat.c", |
| "src/f32-igemm/gen/f32-igemm-4x8-wasmsimd-loadsplat.c", |
| "src/f32-igemm/gen/f32-igemm-4x8-wasmsimd-splat.c", |
| "src/f32-igemm/gen/f32-igemm-4x8s4-minmax-wasmsimd-arm.c", |
| "src/f32-igemm/gen/f32-igemm-4x8s4-minmax-wasmsimd-x86.c", |
| "src/f32-igemm/gen/f32-igemm-4x8s4-relu-wasmsimd.c", |
| "src/f32-igemm/gen/f32-igemm-4x8s4-wasmsimd.c", |
| "src/f32-igemm/gen/f32-igemm-5x8-minmax-wasmsimd-arm-loadsplat.c", |
| "src/f32-igemm/gen/f32-igemm-5x8-minmax-wasmsimd-arm-splat.c", |
| "src/f32-igemm/gen/f32-igemm-5x8-minmax-wasmsimd-x86-loadsplat.c", |
| "src/f32-igemm/gen/f32-igemm-5x8-minmax-wasmsimd-x86-splat.c", |
| "src/f32-igemm/gen/f32-igemm-5x8-relu-wasmsimd-loadsplat.c", |
| "src/f32-igemm/gen/f32-igemm-5x8-relu-wasmsimd-splat.c", |
| "src/f32-igemm/gen/f32-igemm-5x8-wasmsimd-loadsplat.c", |
| "src/f32-igemm/gen/f32-igemm-5x8-wasmsimd-splat.c", |
| "src/f32-igemm/gen/f32-igemm-5x8s4-minmax-wasmsimd-arm.c", |
| "src/f32-igemm/gen/f32-igemm-5x8s4-minmax-wasmsimd-x86.c", |
| "src/f32-igemm/gen/f32-igemm-5x8s4-relu-wasmsimd.c", |
| "src/f32-igemm/gen/f32-igemm-5x8s4-wasmsimd.c", |
| "src/f32-igemm/gen/f32-igemm-6x8-minmax-wasmsimd-arm-loadsplat.c", |
| "src/f32-igemm/gen/f32-igemm-6x8-minmax-wasmsimd-arm-splat.c", |
| "src/f32-igemm/gen/f32-igemm-6x8-minmax-wasmsimd-x86-loadsplat.c", |
| "src/f32-igemm/gen/f32-igemm-6x8-minmax-wasmsimd-x86-splat.c", |
| "src/f32-igemm/gen/f32-igemm-6x8-relu-wasmsimd-loadsplat.c", |
| "src/f32-igemm/gen/f32-igemm-6x8-relu-wasmsimd-splat.c", |
| "src/f32-igemm/gen/f32-igemm-6x8-wasmsimd-loadsplat.c", |
| "src/f32-igemm/gen/f32-igemm-6x8-wasmsimd-splat.c", |
| "src/f32-igemm/gen/f32-igemm-6x8s4-minmax-wasmsimd-arm.c", |
| "src/f32-igemm/gen/f32-igemm-6x8s4-minmax-wasmsimd-x86.c", |
| "src/f32-igemm/gen/f32-igemm-6x8s4-relu-wasmsimd.c", |
| "src/f32-igemm/gen/f32-igemm-6x8s4-wasmsimd.c", |
| "src/f32-maxpool/f32-maxpool-9p8x-minmax-wasmsimd-arm-c4.c", |
| "src/f32-maxpool/f32-maxpool-9p8x-minmax-wasmsimd-x86-c4.c", |
| "src/f32-pavgpool/f32-pavgpool-9p8x-minmax-wasmsimd-arm-c4.c", |
| "src/f32-pavgpool/f32-pavgpool-9p8x-minmax-wasmsimd-x86-c4.c", |
| "src/f32-pavgpool/f32-pavgpool-9x-minmax-wasmsimd-arm-c4.c", |
| "src/f32-pavgpool/f32-pavgpool-9x-minmax-wasmsimd-x86-c4.c", |
| "src/f32-ppmm/gen/f32-ppmm-4x8-minmax-wasmsimd-arm-splat.c", |
| "src/f32-ppmm/gen/f32-ppmm-4x8-minmax-wasmsimd-x86-splat.c", |
| "src/f32-prelu/gen/f32-prelu-wasmsimd-iminmax-1x4.c", |
| "src/f32-prelu/gen/f32-prelu-wasmsimd-iminmax-1x8.c", |
| "src/f32-prelu/gen/f32-prelu-wasmsimd-iminmax-1x16.c", |
| "src/f32-prelu/gen/f32-prelu-wasmsimd-iminmax-2x4.c", |
| "src/f32-prelu/gen/f32-prelu-wasmsimd-iminmax-2x8.c", |
| "src/f32-prelu/gen/f32-prelu-wasmsimd-iminmax-2x16.c", |
| "src/f32-prelu/gen/f32-prelu-wasmsimd-iminmax-4x4.c", |
| "src/f32-prelu/gen/f32-prelu-wasmsimd-iminmax-4x8.c", |
| "src/f32-prelu/gen/f32-prelu-wasmsimd-iminmax-4x16.c", |
| "src/f32-prelu/gen/f32-prelu-wasmsimd-laneselect-1x4.c", |
| "src/f32-prelu/gen/f32-prelu-wasmsimd-laneselect-1x8.c", |
| "src/f32-prelu/gen/f32-prelu-wasmsimd-laneselect-1x16.c", |
| "src/f32-prelu/gen/f32-prelu-wasmsimd-laneselect-2x4.c", |
| "src/f32-prelu/gen/f32-prelu-wasmsimd-laneselect-2x8.c", |
| "src/f32-prelu/gen/f32-prelu-wasmsimd-laneselect-2x16.c", |
| "src/f32-prelu/gen/f32-prelu-wasmsimd-laneselect-4x4.c", |
| "src/f32-prelu/gen/f32-prelu-wasmsimd-laneselect-4x8.c", |
| "src/f32-prelu/gen/f32-prelu-wasmsimd-laneselect-4x16.c", |
| "src/f32-qc8w-gemm/gen/f32-qc8w-gemm-1x8-minmax-wasmsimd-arm-loadsplat.c", |
| "src/f32-qc8w-gemm/gen/f32-qc8w-gemm-1x8-minmax-wasmsimd-arm-splat.c", |
| "src/f32-qc8w-gemm/gen/f32-qc8w-gemm-1x8-minmax-wasmsimd-x86-loadsplat.c", |
| "src/f32-qc8w-gemm/gen/f32-qc8w-gemm-1x8-minmax-wasmsimd-x86-splat.c", |
| "src/f32-qc8w-gemm/gen/f32-qc8w-gemm-1x8-relu-wasmsimd-loadsplat.c", |
| "src/f32-qc8w-gemm/gen/f32-qc8w-gemm-1x8-relu-wasmsimd-splat.c", |
| "src/f32-qc8w-gemm/gen/f32-qc8w-gemm-1x8-wasmsimd-loadsplat.c", |
| "src/f32-qc8w-gemm/gen/f32-qc8w-gemm-1x8-wasmsimd-splat.c", |
| "src/f32-qc8w-gemm/gen/f32-qc8w-gemm-1x8s4-minmax-wasmsimd-arm.c", |
| "src/f32-qc8w-gemm/gen/f32-qc8w-gemm-1x8s4-minmax-wasmsimd-x86.c", |
| "src/f32-qc8w-gemm/gen/f32-qc8w-gemm-1x8s4-relu-wasmsimd.c", |
| "src/f32-qc8w-gemm/gen/f32-qc8w-gemm-1x8s4-wasmsimd.c", |
| "src/f32-qc8w-gemm/gen/f32-qc8w-gemm-3x8-minmax-wasmsimd-arm-loadsplat.c", |
| "src/f32-qc8w-gemm/gen/f32-qc8w-gemm-3x8-minmax-wasmsimd-arm-splat.c", |
| "src/f32-qc8w-gemm/gen/f32-qc8w-gemm-3x8-minmax-wasmsimd-x86-loadsplat.c", |
| "src/f32-qc8w-gemm/gen/f32-qc8w-gemm-3x8-minmax-wasmsimd-x86-splat.c", |
| "src/f32-qc8w-gemm/gen/f32-qc8w-gemm-3x8-relu-wasmsimd-loadsplat.c", |
| "src/f32-qc8w-gemm/gen/f32-qc8w-gemm-3x8-relu-wasmsimd-splat.c", |
| "src/f32-qc8w-gemm/gen/f32-qc8w-gemm-3x8-wasmsimd-loadsplat.c", |
| "src/f32-qc8w-gemm/gen/f32-qc8w-gemm-3x8-wasmsimd-splat.c", |
| "src/f32-qc8w-gemm/gen/f32-qc8w-gemm-3x8s4-minmax-wasmsimd-arm.c", |
| "src/f32-qc8w-gemm/gen/f32-qc8w-gemm-3x8s4-minmax-wasmsimd-x86.c", |
| "src/f32-qc8w-gemm/gen/f32-qc8w-gemm-3x8s4-relu-wasmsimd.c", |
| "src/f32-qc8w-gemm/gen/f32-qc8w-gemm-3x8s4-wasmsimd.c", |
| "src/f32-qc8w-gemm/gen/f32-qc8w-gemm-4x2c4-minmax-wasmsimd-arm.c", |
| "src/f32-qc8w-gemm/gen/f32-qc8w-gemm-4x2c4-minmax-wasmsimd-x86.c", |
| "src/f32-qc8w-gemm/gen/f32-qc8w-gemm-4x2c4-relu-wasmsimd.c", |
| "src/f32-qc8w-gemm/gen/f32-qc8w-gemm-4x2c4-wasmsimd.c", |
| "src/f32-qc8w-gemm/gen/f32-qc8w-gemm-4x8-minmax-wasmsimd-arm-loadsplat.c", |
| "src/f32-qc8w-gemm/gen/f32-qc8w-gemm-4x8-minmax-wasmsimd-arm-splat.c", |
| "src/f32-qc8w-gemm/gen/f32-qc8w-gemm-4x8-minmax-wasmsimd-x86-loadsplat.c", |
| "src/f32-qc8w-gemm/gen/f32-qc8w-gemm-4x8-minmax-wasmsimd-x86-splat.c", |
| "src/f32-qc8w-gemm/gen/f32-qc8w-gemm-4x8-relu-wasmsimd-loadsplat.c", |
| "src/f32-qc8w-gemm/gen/f32-qc8w-gemm-4x8-relu-wasmsimd-splat.c", |
| "src/f32-qc8w-gemm/gen/f32-qc8w-gemm-4x8-wasmsimd-loadsplat.c", |
| "src/f32-qc8w-gemm/gen/f32-qc8w-gemm-4x8-wasmsimd-splat.c", |
| "src/f32-qc8w-gemm/gen/f32-qc8w-gemm-4x8s4-minmax-wasmsimd-arm.c", |
| "src/f32-qc8w-gemm/gen/f32-qc8w-gemm-4x8s4-minmax-wasmsimd-x86.c", |
| "src/f32-qc8w-gemm/gen/f32-qc8w-gemm-4x8s4-relu-wasmsimd.c", |
| "src/f32-qc8w-gemm/gen/f32-qc8w-gemm-4x8s4-wasmsimd.c", |
| "src/f32-qc8w-gemm/gen/f32-qc8w-gemm-5x8-minmax-wasmsimd-arm-loadsplat.c", |
| "src/f32-qc8w-gemm/gen/f32-qc8w-gemm-5x8-minmax-wasmsimd-arm-splat.c", |
| "src/f32-qc8w-gemm/gen/f32-qc8w-gemm-5x8-minmax-wasmsimd-x86-loadsplat.c", |
| "src/f32-qc8w-gemm/gen/f32-qc8w-gemm-5x8-minmax-wasmsimd-x86-splat.c", |
| "src/f32-qc8w-gemm/gen/f32-qc8w-gemm-5x8-relu-wasmsimd-loadsplat.c", |
| "src/f32-qc8w-gemm/gen/f32-qc8w-gemm-5x8-relu-wasmsimd-splat.c", |
| "src/f32-qc8w-gemm/gen/f32-qc8w-gemm-5x8-wasmsimd-loadsplat.c", |
| "src/f32-qc8w-gemm/gen/f32-qc8w-gemm-5x8-wasmsimd-splat.c", |
| "src/f32-qc8w-gemm/gen/f32-qc8w-gemm-5x8s4-minmax-wasmsimd-arm.c", |
| "src/f32-qc8w-gemm/gen/f32-qc8w-gemm-5x8s4-minmax-wasmsimd-x86.c", |
| "src/f32-qc8w-gemm/gen/f32-qc8w-gemm-5x8s4-relu-wasmsimd.c", |
| "src/f32-qc8w-gemm/gen/f32-qc8w-gemm-5x8s4-wasmsimd.c", |
| "src/f32-qc8w-gemm/gen/f32-qc8w-gemm-6x8-minmax-wasmsimd-arm-loadsplat.c", |
| "src/f32-qc8w-gemm/gen/f32-qc8w-gemm-6x8-minmax-wasmsimd-arm-splat.c", |
| "src/f32-qc8w-gemm/gen/f32-qc8w-gemm-6x8-minmax-wasmsimd-x86-loadsplat.c", |
| "src/f32-qc8w-gemm/gen/f32-qc8w-gemm-6x8-minmax-wasmsimd-x86-splat.c", |
| "src/f32-qc8w-gemm/gen/f32-qc8w-gemm-6x8-relu-wasmsimd-loadsplat.c", |
| "src/f32-qc8w-gemm/gen/f32-qc8w-gemm-6x8-relu-wasmsimd-splat.c", |
| "src/f32-qc8w-gemm/gen/f32-qc8w-gemm-6x8-wasmsimd-loadsplat.c", |
| "src/f32-qc8w-gemm/gen/f32-qc8w-gemm-6x8-wasmsimd-splat.c", |
| "src/f32-qc8w-gemm/gen/f32-qc8w-gemm-6x8s4-minmax-wasmsimd-arm.c", |
| "src/f32-qc8w-gemm/gen/f32-qc8w-gemm-6x8s4-minmax-wasmsimd-x86.c", |
| "src/f32-qc8w-gemm/gen/f32-qc8w-gemm-6x8s4-relu-wasmsimd.c", |
| "src/f32-qc8w-gemm/gen/f32-qc8w-gemm-6x8s4-wasmsimd.c", |
| "src/f32-qs8-vcvt/gen/f32-qs8-vcvt-wasmsimd-cvt-u8.c", |
| "src/f32-qs8-vcvt/gen/f32-qs8-vcvt-wasmsimd-cvt-u16.c", |
| "src/f32-qs8-vcvt/gen/f32-qs8-vcvt-wasmsimd-cvt-u24.c", |
| "src/f32-qs8-vcvt/gen/f32-qs8-vcvt-wasmsimd-cvt-u32.c", |
| "src/f32-qs8-vcvt/gen/f32-qs8-vcvt-wasmsimd-magic-u8.c", |
| "src/f32-qs8-vcvt/gen/f32-qs8-vcvt-wasmsimd-magic-u16.c", |
| "src/f32-qs8-vcvt/gen/f32-qs8-vcvt-wasmsimd-magic-u24.c", |
| "src/f32-qs8-vcvt/gen/f32-qs8-vcvt-wasmsimd-magic-u32.c", |
| "src/f32-qu8-vcvt/gen/f32-qu8-vcvt-wasmsimd-cvt-u8.c", |
| "src/f32-qu8-vcvt/gen/f32-qu8-vcvt-wasmsimd-cvt-u16.c", |
| "src/f32-qu8-vcvt/gen/f32-qu8-vcvt-wasmsimd-cvt-u24.c", |
| "src/f32-qu8-vcvt/gen/f32-qu8-vcvt-wasmsimd-cvt-u32.c", |
| "src/f32-qu8-vcvt/gen/f32-qu8-vcvt-wasmsimd-magic-u8.c", |
| "src/f32-qu8-vcvt/gen/f32-qu8-vcvt-wasmsimd-magic-u16.c", |
| "src/f32-qu8-vcvt/gen/f32-qu8-vcvt-wasmsimd-magic-u24.c", |
| "src/f32-qu8-vcvt/gen/f32-qu8-vcvt-wasmsimd-magic-u32.c", |
| "src/f32-raddstoreexpminusmax/gen/f32-raddstoreexpminusmax-wasmsimd-rr2-p5-u4.c", |
| "src/f32-raddstoreexpminusmax/gen/f32-raddstoreexpminusmax-wasmsimd-rr2-p5-u8-acc2.c", |
| "src/f32-raddstoreexpminusmax/gen/f32-raddstoreexpminusmax-wasmsimd-rr2-p5-u8.c", |
| "src/f32-raddstoreexpminusmax/gen/f32-raddstoreexpminusmax-wasmsimd-rr2-p5-u12-acc2.c", |
| "src/f32-raddstoreexpminusmax/gen/f32-raddstoreexpminusmax-wasmsimd-rr2-p5-u12-acc3.c", |
| "src/f32-raddstoreexpminusmax/gen/f32-raddstoreexpminusmax-wasmsimd-rr2-p5-u12.c", |
| "src/f32-raddstoreexpminusmax/gen/f32-raddstoreexpminusmax-wasmsimd-rr2-p5-u16-acc2.c", |
| "src/f32-raddstoreexpminusmax/gen/f32-raddstoreexpminusmax-wasmsimd-rr2-p5-u16-acc4.c", |
| "src/f32-raddstoreexpminusmax/gen/f32-raddstoreexpminusmax-wasmsimd-rr2-p5-u16.c", |
| "src/f32-raddstoreexpminusmax/gen/f32-raddstoreexpminusmax-wasmsimd-rr2-p5-u20-acc2.c", |
| "src/f32-raddstoreexpminusmax/gen/f32-raddstoreexpminusmax-wasmsimd-rr2-p5-u20-acc5.c", |
| "src/f32-raddstoreexpminusmax/gen/f32-raddstoreexpminusmax-wasmsimd-rr2-p5-u20.c", |
| "src/f32-rmax/f32-rmax-wasmsimd-arm.c", |
| "src/f32-rmax/f32-rmax-wasmsimd-x86.c", |
| "src/f32-rminmax/gen/f32-rmax-wasmsimd-minmax-u4.c", |
| "src/f32-rminmax/gen/f32-rmax-wasmsimd-minmax-u8-acc2.c", |
| "src/f32-rminmax/gen/f32-rmax-wasmsimd-minmax-u12-acc3.c", |
| "src/f32-rminmax/gen/f32-rmax-wasmsimd-minmax-u16-acc2.c", |
| "src/f32-rminmax/gen/f32-rmax-wasmsimd-minmax-u16-acc4.c", |
| "src/f32-rminmax/gen/f32-rmax-wasmsimd-pminmax-u4.c", |
| "src/f32-rminmax/gen/f32-rmax-wasmsimd-pminmax-u8-acc2.c", |
| "src/f32-rminmax/gen/f32-rmax-wasmsimd-pminmax-u12-acc3.c", |
| "src/f32-rminmax/gen/f32-rmax-wasmsimd-pminmax-u16-acc2.c", |
| "src/f32-rminmax/gen/f32-rmax-wasmsimd-pminmax-u16-acc4.c", |
| "src/f32-rminmax/gen/f32-rmin-wasmsimd-minmax-u4.c", |
| "src/f32-rminmax/gen/f32-rmin-wasmsimd-minmax-u8-acc2.c", |
| "src/f32-rminmax/gen/f32-rmin-wasmsimd-minmax-u12-acc3.c", |
| "src/f32-rminmax/gen/f32-rmin-wasmsimd-minmax-u16-acc2.c", |
| "src/f32-rminmax/gen/f32-rmin-wasmsimd-minmax-u16-acc4.c", |
| "src/f32-rminmax/gen/f32-rmin-wasmsimd-pminmax-u4.c", |
| "src/f32-rminmax/gen/f32-rmin-wasmsimd-pminmax-u8-acc2.c", |
| "src/f32-rminmax/gen/f32-rmin-wasmsimd-pminmax-u12-acc3.c", |
| "src/f32-rminmax/gen/f32-rmin-wasmsimd-pminmax-u16-acc2.c", |
| "src/f32-rminmax/gen/f32-rmin-wasmsimd-pminmax-u16-acc4.c", |
| "src/f32-rminmax/gen/f32-rminmax-wasmsimd-minmax-u4.c", |
| "src/f32-rminmax/gen/f32-rminmax-wasmsimd-minmax-u8-acc2.c", |
| "src/f32-rminmax/gen/f32-rminmax-wasmsimd-minmax-u12-acc3.c", |
| "src/f32-rminmax/gen/f32-rminmax-wasmsimd-minmax-u16-acc2.c", |
| "src/f32-rminmax/gen/f32-rminmax-wasmsimd-minmax-u16-acc4.c", |
| "src/f32-rminmax/gen/f32-rminmax-wasmsimd-pminmax-u4.c", |
| "src/f32-rminmax/gen/f32-rminmax-wasmsimd-pminmax-u8-acc2.c", |
| "src/f32-rminmax/gen/f32-rminmax-wasmsimd-pminmax-u12-acc3.c", |
| "src/f32-rminmax/gen/f32-rminmax-wasmsimd-pminmax-u16-acc2.c", |
| "src/f32-rminmax/gen/f32-rminmax-wasmsimd-pminmax-u16-acc4.c", |
| "src/f32-rsum/gen/f32-rsum-wasmsimd-u4.c", |
| "src/f32-rsum/gen/f32-rsum-wasmsimd-u8-acc2.c", |
| "src/f32-rsum/gen/f32-rsum-wasmsimd-u12-acc3.c", |
| "src/f32-rsum/gen/f32-rsum-wasmsimd-u16-acc2.c", |
| "src/f32-rsum/gen/f32-rsum-wasmsimd-u16-acc4.c", |
| "src/f32-spmm/gen/f32-spmm-4x1-minmax-wasmsimd-arm-pipelined-x2.c", |
| "src/f32-spmm/gen/f32-spmm-4x1-minmax-wasmsimd-arm-pipelined.c", |
| "src/f32-spmm/gen/f32-spmm-4x1-minmax-wasmsimd-arm-x2.c", |
| "src/f32-spmm/gen/f32-spmm-4x1-minmax-wasmsimd-arm-x4.c", |
| "src/f32-spmm/gen/f32-spmm-4x1-minmax-wasmsimd-arm.c", |
| "src/f32-spmm/gen/f32-spmm-4x1-minmax-wasmsimd-x86-pipelined-x2.c", |
| "src/f32-spmm/gen/f32-spmm-4x1-minmax-wasmsimd-x86-pipelined.c", |
| "src/f32-spmm/gen/f32-spmm-4x1-minmax-wasmsimd-x86-x2.c", |
| "src/f32-spmm/gen/f32-spmm-4x1-minmax-wasmsimd-x86-x4.c", |
| "src/f32-spmm/gen/f32-spmm-4x1-minmax-wasmsimd-x86.c", |
| "src/f32-spmm/gen/f32-spmm-8x1-minmax-wasmsimd-arm-pipelined-x2.c", |
| "src/f32-spmm/gen/f32-spmm-8x1-minmax-wasmsimd-arm-pipelined.c", |
| "src/f32-spmm/gen/f32-spmm-8x1-minmax-wasmsimd-arm-x2.c", |
| "src/f32-spmm/gen/f32-spmm-8x1-minmax-wasmsimd-arm-x4.c", |
| "src/f32-spmm/gen/f32-spmm-8x1-minmax-wasmsimd-arm.c", |
| "src/f32-spmm/gen/f32-spmm-8x1-minmax-wasmsimd-x86-pipelined-x2.c", |
| "src/f32-spmm/gen/f32-spmm-8x1-minmax-wasmsimd-x86-pipelined.c", |
| "src/f32-spmm/gen/f32-spmm-8x1-minmax-wasmsimd-x86-x2.c", |
| "src/f32-spmm/gen/f32-spmm-8x1-minmax-wasmsimd-x86-x4.c", |
| "src/f32-spmm/gen/f32-spmm-8x1-minmax-wasmsimd-x86.c", |
| "src/f32-spmm/gen/f32-spmm-16x1-minmax-wasmsimd-arm-pipelined-x2.c", |
| "src/f32-spmm/gen/f32-spmm-16x1-minmax-wasmsimd-arm-pipelined.c", |
| "src/f32-spmm/gen/f32-spmm-16x1-minmax-wasmsimd-arm-x2.c", |
| "src/f32-spmm/gen/f32-spmm-16x1-minmax-wasmsimd-arm-x4.c", |
| "src/f32-spmm/gen/f32-spmm-16x1-minmax-wasmsimd-arm.c", |
| "src/f32-spmm/gen/f32-spmm-16x1-minmax-wasmsimd-x86-pipelined-x2.c", |
| "src/f32-spmm/gen/f32-spmm-16x1-minmax-wasmsimd-x86-pipelined.c", |
| "src/f32-spmm/gen/f32-spmm-16x1-minmax-wasmsimd-x86-x2.c", |
| "src/f32-spmm/gen/f32-spmm-16x1-minmax-wasmsimd-x86-x4.c", |
| "src/f32-spmm/gen/f32-spmm-16x1-minmax-wasmsimd-x86.c", |
| "src/f32-spmm/gen/f32-spmm-32x1-minmax-wasmsimd-arm-pipelined-x2.c", |
| "src/f32-spmm/gen/f32-spmm-32x1-minmax-wasmsimd-arm-pipelined.c", |
| "src/f32-spmm/gen/f32-spmm-32x1-minmax-wasmsimd-arm-x2.c", |
| "src/f32-spmm/gen/f32-spmm-32x1-minmax-wasmsimd-arm-x4.c", |
| "src/f32-spmm/gen/f32-spmm-32x1-minmax-wasmsimd-arm.c", |
| "src/f32-spmm/gen/f32-spmm-32x1-minmax-wasmsimd-x86-pipelined-x2.c", |
| "src/f32-spmm/gen/f32-spmm-32x1-minmax-wasmsimd-x86-pipelined.c", |
| "src/f32-spmm/gen/f32-spmm-32x1-minmax-wasmsimd-x86-x2.c", |
| "src/f32-spmm/gen/f32-spmm-32x1-minmax-wasmsimd-x86-x4.c", |
| "src/f32-spmm/gen/f32-spmm-32x1-minmax-wasmsimd-x86.c", |
| "src/f32-vbinary/gen/f32-vadd-minmax-wasmsimd-arm-u4.c", |
| "src/f32-vbinary/gen/f32-vadd-minmax-wasmsimd-arm-u8.c", |
| "src/f32-vbinary/gen/f32-vadd-minmax-wasmsimd-arm-u16.c", |
| "src/f32-vbinary/gen/f32-vadd-minmax-wasmsimd-x86-u4.c", |
| "src/f32-vbinary/gen/f32-vadd-minmax-wasmsimd-x86-u8.c", |
| "src/f32-vbinary/gen/f32-vadd-minmax-wasmsimd-x86-u16.c", |
| "src/f32-vbinary/gen/f32-vadd-relu-wasmsimd-u4.c", |
| "src/f32-vbinary/gen/f32-vadd-relu-wasmsimd-u8.c", |
| "src/f32-vbinary/gen/f32-vadd-relu-wasmsimd-u16.c", |
| "src/f32-vbinary/gen/f32-vadd-wasmsimd-u4.c", |
| "src/f32-vbinary/gen/f32-vadd-wasmsimd-u8.c", |
| "src/f32-vbinary/gen/f32-vadd-wasmsimd-u16.c", |
| "src/f32-vbinary/gen/f32-vaddc-minmax-wasmsimd-arm-u4.c", |
| "src/f32-vbinary/gen/f32-vaddc-minmax-wasmsimd-arm-u8.c", |
| "src/f32-vbinary/gen/f32-vaddc-minmax-wasmsimd-arm-u16.c", |
| "src/f32-vbinary/gen/f32-vaddc-minmax-wasmsimd-x86-u4.c", |
| "src/f32-vbinary/gen/f32-vaddc-minmax-wasmsimd-x86-u8.c", |
| "src/f32-vbinary/gen/f32-vaddc-minmax-wasmsimd-x86-u16.c", |
| "src/f32-vbinary/gen/f32-vaddc-relu-wasmsimd-u4.c", |
| "src/f32-vbinary/gen/f32-vaddc-relu-wasmsimd-u8.c", |
| "src/f32-vbinary/gen/f32-vaddc-relu-wasmsimd-u16.c", |
| "src/f32-vbinary/gen/f32-vaddc-wasmsimd-u4.c", |
| "src/f32-vbinary/gen/f32-vaddc-wasmsimd-u8.c", |
| "src/f32-vbinary/gen/f32-vaddc-wasmsimd-u16.c", |
| "src/f32-vbinary/gen/f32-vdiv-minmax-wasmsimd-arm-u4.c", |
| "src/f32-vbinary/gen/f32-vdiv-minmax-wasmsimd-arm-u8.c", |
| "src/f32-vbinary/gen/f32-vdiv-minmax-wasmsimd-arm-u16.c", |
| "src/f32-vbinary/gen/f32-vdiv-minmax-wasmsimd-x86-u4.c", |
| "src/f32-vbinary/gen/f32-vdiv-minmax-wasmsimd-x86-u8.c", |
| "src/f32-vbinary/gen/f32-vdiv-minmax-wasmsimd-x86-u16.c", |
| "src/f32-vbinary/gen/f32-vdiv-relu-wasmsimd-u4.c", |
| "src/f32-vbinary/gen/f32-vdiv-relu-wasmsimd-u8.c", |
| "src/f32-vbinary/gen/f32-vdiv-relu-wasmsimd-u16.c", |
| "src/f32-vbinary/gen/f32-vdiv-wasmsimd-u4.c", |
| "src/f32-vbinary/gen/f32-vdiv-wasmsimd-u8.c", |
| "src/f32-vbinary/gen/f32-vdiv-wasmsimd-u16.c", |
| "src/f32-vbinary/gen/f32-vdivc-minmax-wasmsimd-arm-u4.c", |
| "src/f32-vbinary/gen/f32-vdivc-minmax-wasmsimd-arm-u8.c", |
| "src/f32-vbinary/gen/f32-vdivc-minmax-wasmsimd-arm-u16.c", |
| "src/f32-vbinary/gen/f32-vdivc-minmax-wasmsimd-x86-u4.c", |
| "src/f32-vbinary/gen/f32-vdivc-minmax-wasmsimd-x86-u8.c", |
| "src/f32-vbinary/gen/f32-vdivc-minmax-wasmsimd-x86-u16.c", |
| "src/f32-vbinary/gen/f32-vdivc-relu-wasmsimd-u4.c", |
| "src/f32-vbinary/gen/f32-vdivc-relu-wasmsimd-u8.c", |
| "src/f32-vbinary/gen/f32-vdivc-relu-wasmsimd-u16.c", |
| "src/f32-vbinary/gen/f32-vdivc-wasmsimd-u4.c", |
| "src/f32-vbinary/gen/f32-vdivc-wasmsimd-u8.c", |
| "src/f32-vbinary/gen/f32-vdivc-wasmsimd-u16.c", |
| "src/f32-vbinary/gen/f32-vmax-wasmsimd-arm-u4.c", |
| "src/f32-vbinary/gen/f32-vmax-wasmsimd-arm-u8.c", |
| "src/f32-vbinary/gen/f32-vmax-wasmsimd-arm-u16.c", |
| "src/f32-vbinary/gen/f32-vmax-wasmsimd-x86-u4.c", |
| "src/f32-vbinary/gen/f32-vmax-wasmsimd-x86-u8.c", |
| "src/f32-vbinary/gen/f32-vmax-wasmsimd-x86-u16.c", |
| "src/f32-vbinary/gen/f32-vmaxc-wasmsimd-arm-u4.c", |
| "src/f32-vbinary/gen/f32-vmaxc-wasmsimd-arm-u8.c", |
| "src/f32-vbinary/gen/f32-vmaxc-wasmsimd-arm-u16.c", |
| "src/f32-vbinary/gen/f32-vmaxc-wasmsimd-x86-u4.c", |
| "src/f32-vbinary/gen/f32-vmaxc-wasmsimd-x86-u8.c", |
| "src/f32-vbinary/gen/f32-vmaxc-wasmsimd-x86-u16.c", |
| "src/f32-vbinary/gen/f32-vmin-wasmsimd-arm-u4.c", |
| "src/f32-vbinary/gen/f32-vmin-wasmsimd-arm-u8.c", |
| "src/f32-vbinary/gen/f32-vmin-wasmsimd-arm-u16.c", |
| "src/f32-vbinary/gen/f32-vmin-wasmsimd-x86-u4.c", |
| "src/f32-vbinary/gen/f32-vmin-wasmsimd-x86-u8.c", |
| "src/f32-vbinary/gen/f32-vmin-wasmsimd-x86-u16.c", |
| "src/f32-vbinary/gen/f32-vminc-wasmsimd-arm-u4.c", |
| "src/f32-vbinary/gen/f32-vminc-wasmsimd-arm-u8.c", |
| "src/f32-vbinary/gen/f32-vminc-wasmsimd-arm-u16.c", |
| "src/f32-vbinary/gen/f32-vminc-wasmsimd-x86-u4.c", |
| "src/f32-vbinary/gen/f32-vminc-wasmsimd-x86-u8.c", |
| "src/f32-vbinary/gen/f32-vminc-wasmsimd-x86-u16.c", |
| "src/f32-vbinary/gen/f32-vmul-minmax-wasmsimd-arm-u4.c", |
| "src/f32-vbinary/gen/f32-vmul-minmax-wasmsimd-arm-u8.c", |
| "src/f32-vbinary/gen/f32-vmul-minmax-wasmsimd-arm-u16.c", |
| "src/f32-vbinary/gen/f32-vmul-minmax-wasmsimd-x86-u4.c", |
| "src/f32-vbinary/gen/f32-vmul-minmax-wasmsimd-x86-u8.c", |
| "src/f32-vbinary/gen/f32-vmul-minmax-wasmsimd-x86-u16.c", |
| "src/f32-vbinary/gen/f32-vmul-relu-wasmsimd-u4.c", |
| "src/f32-vbinary/gen/f32-vmul-relu-wasmsimd-u8.c", |
| "src/f32-vbinary/gen/f32-vmul-relu-wasmsimd-u16.c", |
| "src/f32-vbinary/gen/f32-vmul-wasmsimd-u4.c", |
| "src/f32-vbinary/gen/f32-vmul-wasmsimd-u8.c", |
| "src/f32-vbinary/gen/f32-vmul-wasmsimd-u16.c", |
| "src/f32-vbinary/gen/f32-vmulc-minmax-wasmsimd-arm-u4.c", |
| "src/f32-vbinary/gen/f32-vmulc-minmax-wasmsimd-arm-u8.c", |
| "src/f32-vbinary/gen/f32-vmulc-minmax-wasmsimd-arm-u16.c", |
| "src/f32-vbinary/gen/f32-vmulc-minmax-wasmsimd-x86-u4.c", |
| "src/f32-vbinary/gen/f32-vmulc-minmax-wasmsimd-x86-u8.c", |
| "src/f32-vbinary/gen/f32-vmulc-minmax-wasmsimd-x86-u16.c", |
| "src/f32-vbinary/gen/f32-vmulc-relu-wasmsimd-u4.c", |
| "src/f32-vbinary/gen/f32-vmulc-relu-wasmsimd-u8.c", |
| "src/f32-vbinary/gen/f32-vmulc-relu-wasmsimd-u16.c", |
| "src/f32-vbinary/gen/f32-vmulc-wasmsimd-u4.c", |
| "src/f32-vbinary/gen/f32-vmulc-wasmsimd-u8.c", |
| "src/f32-vbinary/gen/f32-vmulc-wasmsimd-u16.c", |
| "src/f32-vbinary/gen/f32-vrdivc-minmax-wasmsimd-arm-u4.c", |
| "src/f32-vbinary/gen/f32-vrdivc-minmax-wasmsimd-arm-u8.c", |
| "src/f32-vbinary/gen/f32-vrdivc-minmax-wasmsimd-arm-u16.c", |
| "src/f32-vbinary/gen/f32-vrdivc-minmax-wasmsimd-x86-u4.c", |
| "src/f32-vbinary/gen/f32-vrdivc-minmax-wasmsimd-x86-u8.c", |
| "src/f32-vbinary/gen/f32-vrdivc-minmax-wasmsimd-x86-u16.c", |
| "src/f32-vbinary/gen/f32-vrdivc-relu-wasmsimd-u4.c", |
| "src/f32-vbinary/gen/f32-vrdivc-relu-wasmsimd-u8.c", |
| "src/f32-vbinary/gen/f32-vrdivc-relu-wasmsimd-u16.c", |
| "src/f32-vbinary/gen/f32-vrdivc-wasmsimd-u4.c", |
| "src/f32-vbinary/gen/f32-vrdivc-wasmsimd-u8.c", |
| "src/f32-vbinary/gen/f32-vrdivc-wasmsimd-u16.c", |
| "src/f32-vbinary/gen/f32-vrsubc-minmax-wasmsimd-arm-u4.c", |
| "src/f32-vbinary/gen/f32-vrsubc-minmax-wasmsimd-arm-u8.c", |
| "src/f32-vbinary/gen/f32-vrsubc-minmax-wasmsimd-arm-u16.c", |
| "src/f32-vbinary/gen/f32-vrsubc-minmax-wasmsimd-x86-u4.c", |
| "src/f32-vbinary/gen/f32-vrsubc-minmax-wasmsimd-x86-u8.c", |
| "src/f32-vbinary/gen/f32-vrsubc-minmax-wasmsimd-x86-u16.c", |
| "src/f32-vbinary/gen/f32-vrsubc-relu-wasmsimd-u4.c", |
| "src/f32-vbinary/gen/f32-vrsubc-relu-wasmsimd-u8.c", |
| "src/f32-vbinary/gen/f32-vrsubc-relu-wasmsimd-u16.c", |
| "src/f32-vbinary/gen/f32-vrsubc-wasmsimd-u4.c", |
| "src/f32-vbinary/gen/f32-vrsubc-wasmsimd-u8.c", |
| "src/f32-vbinary/gen/f32-vrsubc-wasmsimd-u16.c", |
| "src/f32-vbinary/gen/f32-vsqrdiff-wasmsimd-u4.c", |
| "src/f32-vbinary/gen/f32-vsqrdiff-wasmsimd-u8.c", |
| "src/f32-vbinary/gen/f32-vsqrdiff-wasmsimd-u16.c", |
| "src/f32-vbinary/gen/f32-vsqrdiffc-wasmsimd-u4.c", |
| "src/f32-vbinary/gen/f32-vsqrdiffc-wasmsimd-u8.c", |
| "src/f32-vbinary/gen/f32-vsqrdiffc-wasmsimd-u16.c", |
| "src/f32-vbinary/gen/f32-vsub-minmax-wasmsimd-arm-u4.c", |
| "src/f32-vbinary/gen/f32-vsub-minmax-wasmsimd-arm-u8.c", |
| "src/f32-vbinary/gen/f32-vsub-minmax-wasmsimd-arm-u16.c", |
| "src/f32-vbinary/gen/f32-vsub-minmax-wasmsimd-x86-u4.c", |
| "src/f32-vbinary/gen/f32-vsub-minmax-wasmsimd-x86-u8.c", |
| "src/f32-vbinary/gen/f32-vsub-minmax-wasmsimd-x86-u16.c", |
| "src/f32-vbinary/gen/f32-vsub-relu-wasmsimd-u4.c", |
| "src/f32-vbinary/gen/f32-vsub-relu-wasmsimd-u8.c", |
| "src/f32-vbinary/gen/f32-vsub-relu-wasmsimd-u16.c", |
| "src/f32-vbinary/gen/f32-vsub-wasmsimd-u4.c", |
| "src/f32-vbinary/gen/f32-vsub-wasmsimd-u8.c", |
| "src/f32-vbinary/gen/f32-vsub-wasmsimd-u16.c", |
| "src/f32-vbinary/gen/f32-vsubc-minmax-wasmsimd-arm-u4.c", |
| "src/f32-vbinary/gen/f32-vsubc-minmax-wasmsimd-arm-u8.c", |
| "src/f32-vbinary/gen/f32-vsubc-minmax-wasmsimd-arm-u16.c", |
| "src/f32-vbinary/gen/f32-vsubc-minmax-wasmsimd-x86-u4.c", |
| "src/f32-vbinary/gen/f32-vsubc-minmax-wasmsimd-x86-u8.c", |
| "src/f32-vbinary/gen/f32-vsubc-minmax-wasmsimd-x86-u16.c", |
| "src/f32-vbinary/gen/f32-vsubc-relu-wasmsimd-u4.c", |
| "src/f32-vbinary/gen/f32-vsubc-relu-wasmsimd-u8.c", |
| "src/f32-vbinary/gen/f32-vsubc-relu-wasmsimd-u16.c", |
| "src/f32-vbinary/gen/f32-vsubc-wasmsimd-u4.c", |
| "src/f32-vbinary/gen/f32-vsubc-wasmsimd-u8.c", |
| "src/f32-vbinary/gen/f32-vsubc-wasmsimd-u16.c", |
| "src/f32-vclamp/gen/f32-vclamp-wasmsimd-arm-u4.c", |
| "src/f32-vclamp/gen/f32-vclamp-wasmsimd-arm-u8.c", |
| "src/f32-vclamp/gen/f32-vclamp-wasmsimd-x86-u4.c", |
| "src/f32-vclamp/gen/f32-vclamp-wasmsimd-x86-u8.c", |
| "src/f32-vcmul/gen/f32-vcmul-wasmsimd-u4.c", |
| "src/f32-vcmul/gen/f32-vcmul-wasmsimd-u8.c", |
| "src/f32-vcmul/gen/f32-vcmul-wasmsimd-u12.c", |
| "src/f32-vcmul/gen/f32-vcmul-wasmsimd-u16.c", |
| "src/f32-velu/gen/f32-velu-wasmsimd-arm-rr2-lut16-p3-u4.c", |
| "src/f32-velu/gen/f32-velu-wasmsimd-arm-rr2-lut16-p3-u8.c", |
| "src/f32-velu/gen/f32-velu-wasmsimd-arm-rr2-lut16-p3-u12.c", |
| "src/f32-velu/gen/f32-velu-wasmsimd-arm-rr2-lut16-p3-u16.c", |
| "src/f32-velu/gen/f32-velu-wasmsimd-arm-rr2-lut16-p3-u20.c", |
| "src/f32-velu/gen/f32-velu-wasmsimd-arm-rr2-lut16-p3-u24.c", |
| "src/f32-velu/gen/f32-velu-wasmsimd-arm-rr2-p6-u4.c", |
| "src/f32-velu/gen/f32-velu-wasmsimd-arm-rr2-p6-u8.c", |
| "src/f32-velu/gen/f32-velu-wasmsimd-arm-rr2-p6-u12.c", |
| "src/f32-velu/gen/f32-velu-wasmsimd-arm-rr2-p6-u16.c", |
| "src/f32-velu/gen/f32-velu-wasmsimd-arm-rr2-p6-u20.c", |
| "src/f32-velu/gen/f32-velu-wasmsimd-arm-rr2-p6-u24.c", |
| "src/f32-velu/gen/f32-velu-wasmsimd-x86-rr2-lut16-p3-u4.c", |
| "src/f32-velu/gen/f32-velu-wasmsimd-x86-rr2-lut16-p3-u8.c", |
| "src/f32-velu/gen/f32-velu-wasmsimd-x86-rr2-lut16-p3-u12.c", |
| "src/f32-velu/gen/f32-velu-wasmsimd-x86-rr2-lut16-p3-u16.c", |
| "src/f32-velu/gen/f32-velu-wasmsimd-x86-rr2-lut16-p3-u20.c", |
| "src/f32-velu/gen/f32-velu-wasmsimd-x86-rr2-lut16-p3-u24.c", |
| "src/f32-velu/gen/f32-velu-wasmsimd-x86-rr2-p6-u4.c", |
| "src/f32-velu/gen/f32-velu-wasmsimd-x86-rr2-p6-u8.c", |
| "src/f32-velu/gen/f32-velu-wasmsimd-x86-rr2-p6-u12.c", |
| "src/f32-velu/gen/f32-velu-wasmsimd-x86-rr2-p6-u16.c", |
| "src/f32-velu/gen/f32-velu-wasmsimd-x86-rr2-p6-u20.c", |
| "src/f32-velu/gen/f32-velu-wasmsimd-x86-rr2-p6-u24.c", |
| "src/f32-vhswish/gen/f32-vhswish-wasmsimd-u4.c", |
| "src/f32-vhswish/gen/f32-vhswish-wasmsimd-u8.c", |
| "src/f32-vhswish/gen/f32-vhswish-wasmsimd-u16.c", |
| "src/f32-vlrelu/gen/f32-vlrelu-wasmsimd-iminmax-u4.c", |
| "src/f32-vlrelu/gen/f32-vlrelu-wasmsimd-iminmax-u8.c", |
| "src/f32-vlrelu/gen/f32-vlrelu-wasmsimd-laneselect-u4.c", |
| "src/f32-vlrelu/gen/f32-vlrelu-wasmsimd-laneselect-u8.c", |
| "src/f32-vmulcaddc/gen/f32-vmulcaddc-c4-minmax-wasmsimd-arm-2x.c", |
| "src/f32-vmulcaddc/gen/f32-vmulcaddc-c4-minmax-wasmsimd-x86-2x.c", |
| "src/f32-vmulcaddc/gen/f32-vmulcaddc-c8-minmax-wasmsimd-arm-2x.c", |
| "src/f32-vmulcaddc/gen/f32-vmulcaddc-c8-minmax-wasmsimd-x86-2x.c", |
| "src/f32-vrelu/gen/f32-vrelu-wasmsimd-u4.c", |
| "src/f32-vrelu/gen/f32-vrelu-wasmsimd-u8.c", |
| "src/f32-vrelu/gen/f32-vrelu-wasmsimd-u16.c", |
| "src/f32-vrnd/gen/f32-vrndd-wasmsimd-u4.c", |
| "src/f32-vrnd/gen/f32-vrndd-wasmsimd-u8.c", |
| "src/f32-vrnd/gen/f32-vrndne-wasmsimd-u4.c", |
| "src/f32-vrnd/gen/f32-vrndne-wasmsimd-u8.c", |
| "src/f32-vrnd/gen/f32-vrndu-wasmsimd-u4.c", |
| "src/f32-vrnd/gen/f32-vrndu-wasmsimd-u8.c", |
| "src/f32-vrnd/gen/f32-vrndz-wasmsimd-u4.c", |
| "src/f32-vrnd/gen/f32-vrndz-wasmsimd-u8.c", |
| "src/f32-vsigmoid/gen/f32-vsigmoid-wasmsimd-rr2-lut64-p2-div-u4.c", |
| "src/f32-vsigmoid/gen/f32-vsigmoid-wasmsimd-rr2-lut64-p2-div-u8.c", |
| "src/f32-vsigmoid/gen/f32-vsigmoid-wasmsimd-rr2-lut64-p2-div-u12.c", |
| "src/f32-vsigmoid/gen/f32-vsigmoid-wasmsimd-rr2-lut64-p2-div-u16.c", |
| "src/f32-vsigmoid/gen/f32-vsigmoid-wasmsimd-rr2-lut64-p2-div-u20.c", |
| "src/f32-vsigmoid/gen/f32-vsigmoid-wasmsimd-rr2-lut64-p2-div-u24.c", |
| "src/f32-vsigmoid/gen/f32-vsigmoid-wasmsimd-rr2-p5-div-u4.c", |
| "src/f32-vsigmoid/gen/f32-vsigmoid-wasmsimd-rr2-p5-div-u8.c", |
| "src/f32-vsigmoid/gen/f32-vsigmoid-wasmsimd-rr2-p5-div-u12.c", |
| "src/f32-vsigmoid/gen/f32-vsigmoid-wasmsimd-rr2-p5-div-u16.c", |
| "src/f32-vsigmoid/gen/f32-vsigmoid-wasmsimd-rr2-p5-div-u20.c", |
| "src/f32-vsigmoid/gen/f32-vsigmoid-wasmsimd-rr2-p5-div-u24.c", |
| "src/f32-vsqrt/gen/f32-vsqrt-wasmsimd-sqrt-u4.c", |
| "src/f32-vsqrt/gen/f32-vsqrt-wasmsimd-sqrt-u8.c", |
| "src/f32-vtanh/gen/f32-vtanh-wasmsimd-expm1minus-rr1-lut8-p4h3ts-div-abs-min-u4.c", |
| "src/f32-vtanh/gen/f32-vtanh-wasmsimd-expm1minus-rr1-lut8-p4h3ts-div-abs-min-u8.c", |
| "src/f32-vtanh/gen/f32-vtanh-wasmsimd-expm1minus-rr1-lut8-p4h3ts-div-abs-min-u12.c", |
| "src/f32-vtanh/gen/f32-vtanh-wasmsimd-expm1minus-rr1-lut8-p4h3ts-div-abs-min-u16.c", |
| "src/f32-vtanh/gen/f32-vtanh-wasmsimd-expm1minus-rr1-lut8-p4h3ts-div-abs-pmin-u4.c", |
| "src/f32-vtanh/gen/f32-vtanh-wasmsimd-expm1minus-rr1-lut8-p4h3ts-div-abs-pmin-u8.c", |
| "src/f32-vtanh/gen/f32-vtanh-wasmsimd-expm1minus-rr1-lut8-p4h3ts-div-abs-pmin-u12.c", |
| "src/f32-vtanh/gen/f32-vtanh-wasmsimd-expm1minus-rr1-lut8-p4h3ts-div-abs-pmin-u16.c", |
| "src/f32-vtanh/gen/f32-vtanh-wasmsimd-expm1minus-rr1-lut8-p4h3ts-div-nabs-max-u4.c", |
| "src/f32-vtanh/gen/f32-vtanh-wasmsimd-expm1minus-rr1-lut8-p4h3ts-div-nabs-max-u8.c", |
| "src/f32-vtanh/gen/f32-vtanh-wasmsimd-expm1minus-rr1-lut8-p4h3ts-div-nabs-max-u12.c", |
| "src/f32-vtanh/gen/f32-vtanh-wasmsimd-expm1minus-rr1-lut8-p4h3ts-div-nabs-max-u16.c", |
| "src/f32-vtanh/gen/f32-vtanh-wasmsimd-expm1minus-rr1-lut8-p4h3ts-div-nabs-pmax-u4.c", |
| "src/f32-vtanh/gen/f32-vtanh-wasmsimd-expm1minus-rr1-lut8-p4h3ts-div-nabs-pmax-u8.c", |
| "src/f32-vtanh/gen/f32-vtanh-wasmsimd-expm1minus-rr1-lut8-p4h3ts-div-nabs-pmax-u12.c", |
| "src/f32-vtanh/gen/f32-vtanh-wasmsimd-expm1minus-rr1-lut8-p4h3ts-div-nabs-pmax-u16.c", |
| "src/f32-vtanh/gen/f32-vtanh-wasmsimd-expm1minus-rr1-p6h5ts-div-abs-min-u4.c", |
| "src/f32-vtanh/gen/f32-vtanh-wasmsimd-expm1minus-rr1-p6h5ts-div-abs-min-u8.c", |
| "src/f32-vtanh/gen/f32-vtanh-wasmsimd-expm1minus-rr1-p6h5ts-div-abs-min-u12.c", |
| "src/f32-vtanh/gen/f32-vtanh-wasmsimd-expm1minus-rr1-p6h5ts-div-abs-min-u16.c", |
| "src/f32-vtanh/gen/f32-vtanh-wasmsimd-expm1minus-rr1-p6h5ts-div-abs-pmin-u4.c", |
| "src/f32-vtanh/gen/f32-vtanh-wasmsimd-expm1minus-rr1-p6h5ts-div-abs-pmin-u8.c", |
| "src/f32-vtanh/gen/f32-vtanh-wasmsimd-expm1minus-rr1-p6h5ts-div-abs-pmin-u12.c", |
| "src/f32-vtanh/gen/f32-vtanh-wasmsimd-expm1minus-rr1-p6h5ts-div-abs-pmin-u16.c", |
| "src/f32-vtanh/gen/f32-vtanh-wasmsimd-expm1minus-rr1-p6h5ts-div-nabs-max-u4.c", |
| "src/f32-vtanh/gen/f32-vtanh-wasmsimd-expm1minus-rr1-p6h5ts-div-nabs-max-u8.c", |
| "src/f32-vtanh/gen/f32-vtanh-wasmsimd-expm1minus-rr1-p6h5ts-div-nabs-max-u12.c", |
| "src/f32-vtanh/gen/f32-vtanh-wasmsimd-expm1minus-rr1-p6h5ts-div-nabs-max-u16.c", |
| "src/f32-vtanh/gen/f32-vtanh-wasmsimd-expm1minus-rr1-p6h5ts-div-nabs-pmax-u4.c", |
| "src/f32-vtanh/gen/f32-vtanh-wasmsimd-expm1minus-rr1-p6h5ts-div-nabs-pmax-u8.c", |
| "src/f32-vtanh/gen/f32-vtanh-wasmsimd-expm1minus-rr1-p6h5ts-div-nabs-pmax-u12.c", |
| "src/f32-vtanh/gen/f32-vtanh-wasmsimd-expm1minus-rr1-p6h5ts-div-nabs-pmax-u16.c", |
| "src/f32-vunary/gen/f32-vabs-wasmsimd-u4.c", |
| "src/f32-vunary/gen/f32-vabs-wasmsimd-u8.c", |
| "src/f32-vunary/gen/f32-vneg-wasmsimd-u4.c", |
| "src/f32-vunary/gen/f32-vneg-wasmsimd-u8.c", |
| "src/f32-vunary/gen/f32-vsqr-wasmsimd-u4.c", |
| "src/f32-vunary/gen/f32-vsqr-wasmsimd-u8.c", |
| "src/math/f16-f32-cvt-wasmsimd-int16.c", |
| "src/math/f16-f32-cvt-wasmsimd-int32.c", |
| "src/math/f32-expm1minus-wasmsimd-rr2-lut16-p3-andnot.c", |
| "src/math/f32-expm1minus-wasmsimd-rr2-lut16-p3-max.c", |
| "src/math/f32-expm1minus-wasmsimd-rr2-p6-andnot.c", |
| "src/math/f32-expm1minus-wasmsimd-rr2-p6-max.c", |
| "src/math/f32-f16-cvt-wasmsimd.c", |
| "src/math/f32-qs8-cvt-wasmsimd.c", |
| "src/math/f32-qu8-cvt-wasmsimd.c", |
| "src/math/f32-roundd-wasmsimd-addsub.c", |
| "src/math/f32-roundd-wasmsimd-cvt.c", |
| "src/math/f32-roundd-wasmsimd-native.c", |
| "src/math/f32-roundne-wasmsimd-addsub.c", |
| "src/math/f32-roundne-wasmsimd-native.c", |
| "src/math/f32-roundu-wasmsimd-addsub.c", |
| "src/math/f32-roundu-wasmsimd-cvt.c", |
| "src/math/f32-roundu-wasmsimd-native.c", |
| "src/math/f32-roundz-wasmsimd-addsub.c", |
| "src/math/f32-roundz-wasmsimd-cvt.c", |
| "src/math/f32-roundz-wasmsimd-native.c", |
| "src/math/f32-sigmoid-wasmsimd-rr2-lut64-p2-div.c", |
| "src/math/f32-sigmoid-wasmsimd-rr2-p5-div.c", |
| "src/math/gen/f32-tanh-wasmsimd-expm1minus-rr1-lut8-p4h3ps-div-abs-min.c", |
| "src/math/gen/f32-tanh-wasmsimd-expm1minus-rr1-lut8-p4h3ps-div-abs-pmin.c", |
| "src/math/gen/f32-tanh-wasmsimd-expm1minus-rr1-lut8-p4h3ps-div-nabs-max.c", |
| "src/math/gen/f32-tanh-wasmsimd-expm1minus-rr1-lut8-p4h3ps-div-nabs-pmax.c", |
| "src/math/gen/f32-tanh-wasmsimd-expm1minus-rr1-p6h5ts-div-abs-min.c", |
| "src/math/gen/f32-tanh-wasmsimd-expm1minus-rr1-p6h5ts-div-abs-pmin.c", |
| "src/math/gen/f32-tanh-wasmsimd-expm1minus-rr1-p6h5ts-div-nabs-max.c", |
| "src/math/gen/f32-tanh-wasmsimd-expm1minus-rr1-p6h5ts-div-nabs-pmax.c", |
| "src/qd8-f32-qc8w-gemm/gen/qd8-f32-qc8w-gemm-1x4c2-minmax-wasmsimd-dot16x2-ld64.c", |
| "src/qd8-f32-qc8w-gemm/gen/qd8-f32-qc8w-gemm-1x4c2-minmax-wasmsimd-dot16x2-ld128.c", |
| "src/qd8-f32-qc8w-gemm/gen/qd8-f32-qc8w-gemm-1x4c2s4-minmax-wasmsimd-dot16x2-ld64.c", |
| "src/qd8-f32-qc8w-gemm/gen/qd8-f32-qc8w-gemm-1x4c2s4-minmax-wasmsimd-dot16x2-ld128.c", |
| "src/qd8-f32-qc8w-gemm/gen/qd8-f32-qc8w-gemm-1x4c8-minmax-wasmsimd-dot16x2-ld64.c", |
| "src/qd8-f32-qc8w-gemm/gen/qd8-f32-qc8w-gemm-1x4c8-minmax-wasmsimd-dot16x2-ld128.c", |
| "src/qd8-f32-qc8w-gemm/gen/qd8-f32-qc8w-gemm-2x4c2-minmax-wasmsimd-dot16x2-ld64.c", |
| "src/qd8-f32-qc8w-gemm/gen/qd8-f32-qc8w-gemm-2x4c2-minmax-wasmsimd-dot16x2-ld128.c", |
| "src/qd8-f32-qc8w-gemm/gen/qd8-f32-qc8w-gemm-2x4c2s4-minmax-wasmsimd-dot16x2-ld64.c", |
| "src/qd8-f32-qc8w-gemm/gen/qd8-f32-qc8w-gemm-2x4c2s4-minmax-wasmsimd-dot16x2-ld128.c", |
| "src/qd8-f32-qc8w-gemm/gen/qd8-f32-qc8w-gemm-2x4c8-minmax-wasmsimd-dot16x2-ld64.c", |
| "src/qd8-f32-qc8w-gemm/gen/qd8-f32-qc8w-gemm-2x4c8-minmax-wasmsimd-dot16x2-ld128.c", |
| "src/qd8-f32-qc8w-gemm/gen/qd8-f32-qc8w-gemm-3x4c2-minmax-wasmsimd-dot16x2-ld64.c", |
| "src/qd8-f32-qc8w-gemm/gen/qd8-f32-qc8w-gemm-3x4c2-minmax-wasmsimd-dot16x2-ld128.c", |
| "src/qd8-f32-qc8w-gemm/gen/qd8-f32-qc8w-gemm-3x4c2s4-minmax-wasmsimd-dot16x2-ld64.c", |
| "src/qd8-f32-qc8w-gemm/gen/qd8-f32-qc8w-gemm-3x4c2s4-minmax-wasmsimd-dot16x2-ld128.c", |
| "src/qd8-f32-qc8w-gemm/gen/qd8-f32-qc8w-gemm-3x4c8-minmax-wasmsimd-dot16x2-ld64.c", |
| "src/qd8-f32-qc8w-gemm/gen/qd8-f32-qc8w-gemm-3x4c8-minmax-wasmsimd-dot16x2-ld128.c", |
| "src/qd8-f32-qc8w-gemm/gen/qd8-f32-qc8w-gemm-4x4c2-minmax-wasmsimd-dot16x2-ld64.c", |
| "src/qd8-f32-qc8w-gemm/gen/qd8-f32-qc8w-gemm-4x4c2-minmax-wasmsimd-dot16x2-ld128.c", |
| "src/qd8-f32-qc8w-gemm/gen/qd8-f32-qc8w-gemm-4x4c2s4-minmax-wasmsimd-dot16x2-ld64.c", |
| "src/qd8-f32-qc8w-gemm/gen/qd8-f32-qc8w-gemm-4x4c2s4-minmax-wasmsimd-dot16x2-ld128.c", |
| "src/qd8-f32-qc8w-gemm/gen/qd8-f32-qc8w-gemm-4x4c8-minmax-wasmsimd-dot16x2-ld64.c", |
| "src/qd8-f32-qc8w-gemm/gen/qd8-f32-qc8w-gemm-4x4c8-minmax-wasmsimd-dot16x2-ld128.c", |
| "src/qs8-dwconv/gen/qs8-dwconv-5f5m5l8c8s8r-minmax-fp32-wasmsimd-mul16-add16.c", |
| "src/qs8-dwconv/gen/qs8-dwconv-5f5m5l8c8s8r-minmax-fp32-wasmsimd-mul16.c", |
| "src/qs8-dwconv/gen/qs8-dwconv-5f5m5l16c8s8r-minmax-fp32-wasmsimd-mul16-add16.c", |
| "src/qs8-dwconv/gen/qs8-dwconv-5f5m5l16c8s8r-minmax-fp32-wasmsimd-mul16.c", |
| "src/qs8-dwconv/gen/qs8-dwconv-6f6m7l8c8s8r-minmax-fp32-wasmsimd-mul16-add16.c", |
| "src/qs8-dwconv/gen/qs8-dwconv-6f6m7l8c8s8r-minmax-fp32-wasmsimd-mul16.c", |
| "src/qs8-dwconv/gen/qs8-dwconv-6f6m7l16c8s8r-minmax-fp32-wasmsimd-mul16-add16.c", |
| "src/qs8-dwconv/gen/qs8-dwconv-6f6m7l16c8s8r-minmax-fp32-wasmsimd-mul16.c", |
| "src/qs8-dwconv/gen/qs8-dwconv-8f8m9l8c8s8r-minmax-fp32-wasmsimd-mul16-add16.c", |
| "src/qs8-dwconv/gen/qs8-dwconv-8f8m9l8c8s8r-minmax-fp32-wasmsimd-mul16.c", |
| "src/qs8-dwconv/gen/qs8-dwconv-8f8m9l16c8s8r-minmax-fp32-wasmsimd-mul16-add16.c", |
| "src/qs8-dwconv/gen/qs8-dwconv-8f8m9l16c8s8r-minmax-fp32-wasmsimd-mul16.c", |
| "src/qs8-dwconv/gen/qs8-dwconv-9p8c-minmax-fp32-wasmsimd-mul16-add16.c", |
| "src/qs8-dwconv/gen/qs8-dwconv-9p8c-minmax-fp32-wasmsimd-mul16.c", |
| "src/qs8-dwconv/gen/qs8-dwconv-9p16c-minmax-fp32-wasmsimd-mul16-add16.c", |
| "src/qs8-dwconv/gen/qs8-dwconv-9p16c-minmax-fp32-wasmsimd-mul16.c", |
| "src/qs8-dwconv/gen/qs8-dwconv-25p8c-minmax-fp32-wasmsimd-mul16-add16.c", |
| "src/qs8-dwconv/gen/qs8-dwconv-25p8c-minmax-fp32-wasmsimd-mul16.c", |
| "src/qs8-dwconv/gen/qs8-dwconv-25p16c-minmax-fp32-wasmsimd-mul16-add16.c", |
| "src/qs8-dwconv/gen/qs8-dwconv-25p16c-minmax-fp32-wasmsimd-mul16.c", |
| "src/qs8-f32-vcvt/gen/qs8-f32-vcvt-wasmsimd-u8.c", |
| "src/qs8-f32-vcvt/gen/qs8-f32-vcvt-wasmsimd-u16.c", |
| "src/qs8-f32-vcvt/gen/qs8-f32-vcvt-wasmsimd-u24.c", |
| "src/qs8-f32-vcvt/gen/qs8-f32-vcvt-wasmsimd-u32.c", |
| "src/qs8-gavgpool/gen/qs8-gavgpool-7p7x-minmax-fp32-wasmsimd-c8.c", |
| "src/qs8-gavgpool/gen/qs8-gavgpool-7p7x-minmax-fp32-wasmsimd-c16.c", |
| "src/qs8-gavgpool/gen/qs8-gavgpool-7p7x-minmax-fp32-wasmsimd-c24.c", |
| "src/qs8-gavgpool/gen/qs8-gavgpool-7p7x-minmax-fp32-wasmsimd-c32.c", |
| "src/qs8-gavgpool/gen/qs8-gavgpool-7x-minmax-fp32-wasmsimd-c8.c", |
| "src/qs8-gavgpool/gen/qs8-gavgpool-7x-minmax-fp32-wasmsimd-c16.c", |
| "src/qs8-gavgpool/gen/qs8-gavgpool-7x-minmax-fp32-wasmsimd-c24.c", |
| "src/qs8-gavgpool/gen/qs8-gavgpool-7x-minmax-fp32-wasmsimd-c32.c", |
| "src/qs8-gemm/gen/qs8-gemm-1x4c2-minmax-fp32-wasmsimd-dot16x2-ld64.c", |
| "src/qs8-gemm/gen/qs8-gemm-1x4c2-minmax-fp32-wasmsimd-dot16x2-ld128.c", |
| "src/qs8-gemm/gen/qs8-gemm-1x4c2-xw-minmax-fp32-wasmsimd-dot16x2.c", |
| "src/qs8-gemm/gen/qs8-gemm-1x4c2s4-minmax-fp32-wasmsimd-dot16x2-ld64.c", |
| "src/qs8-gemm/gen/qs8-gemm-1x4c2s4-minmax-fp32-wasmsimd-dot16x2-ld128.c", |
| "src/qs8-gemm/gen/qs8-gemm-1x4c8-minmax-fp32-wasmsimd-dot16x2-ld64.c", |
| "src/qs8-gemm/gen/qs8-gemm-1x4c8-minmax-fp32-wasmsimd-dot16x2-ld128.c", |
| "src/qs8-gemm/gen/qs8-gemm-1x4c8-xw-minmax-fp32-wasmsimd-dot16x2.c", |
| "src/qs8-gemm/gen/qs8-gemm-2x4c2-minmax-fp32-wasmsimd-dot16x2-ld64.c", |
| "src/qs8-gemm/gen/qs8-gemm-2x4c2-minmax-fp32-wasmsimd-dot16x2-ld128.c", |
| "src/qs8-gemm/gen/qs8-gemm-2x4c2-xw-minmax-fp32-wasmsimd-dot16x2.c", |
| "src/qs8-gemm/gen/qs8-gemm-2x4c2s4-minmax-fp32-wasmsimd-dot16x2-ld64.c", |
| "src/qs8-gemm/gen/qs8-gemm-2x4c2s4-minmax-fp32-wasmsimd-dot16x2-ld128.c", |
| "src/qs8-gemm/gen/qs8-gemm-2x4c8-minmax-fp32-wasmsimd-dot16x2-ld64.c", |
| "src/qs8-gemm/gen/qs8-gemm-2x4c8-minmax-fp32-wasmsimd-dot16x2-ld128.c", |
| "src/qs8-gemm/gen/qs8-gemm-2x4c8-xw-minmax-fp32-wasmsimd-dot16x2.c", |
| "src/qs8-gemm/gen/qs8-gemm-3x4c2-minmax-fp32-wasmsimd-dot16x2-ld64.c", |
| "src/qs8-gemm/gen/qs8-gemm-3x4c2-minmax-fp32-wasmsimd-dot16x2-ld128.c", |
| "src/qs8-gemm/gen/qs8-gemm-3x4c2-xw-minmax-fp32-wasmsimd-dot16x2.c", |
| "src/qs8-gemm/gen/qs8-gemm-3x4c2s4-minmax-fp32-wasmsimd-dot16x2-ld64.c", |
| "src/qs8-gemm/gen/qs8-gemm-3x4c2s4-minmax-fp32-wasmsimd-dot16x2-ld128.c", |
| "src/qs8-gemm/gen/qs8-gemm-3x4c8-minmax-fp32-wasmsimd-dot16x2-ld64.c", |
| "src/qs8-gemm/gen/qs8-gemm-3x4c8-minmax-fp32-wasmsimd-dot16x2-ld128.c", |
| "src/qs8-gemm/gen/qs8-gemm-3x4c8-xw-minmax-fp32-wasmsimd-dot16x2.c", |
| "src/qs8-gemm/gen/qs8-gemm-4x4c2-minmax-fp32-wasmsimd-dot16x2-ld64.c", |
| "src/qs8-gemm/gen/qs8-gemm-4x4c2-minmax-fp32-wasmsimd-dot16x2-ld128.c", |
| "src/qs8-gemm/gen/qs8-gemm-4x4c2-xw-minmax-fp32-wasmsimd-dot16x2.c", |
| "src/qs8-gemm/gen/qs8-gemm-4x4c2s4-minmax-fp32-wasmsimd-dot16x2-ld64.c", |
| "src/qs8-gemm/gen/qs8-gemm-4x4c2s4-minmax-fp32-wasmsimd-dot16x2-ld128.c", |
| "src/qs8-gemm/gen/qs8-gemm-4x4c8-minmax-fp32-wasmsimd-dot16x2-ld64.c", |
| "src/qs8-gemm/gen/qs8-gemm-4x4c8-minmax-fp32-wasmsimd-dot16x2-ld128.c", |
| "src/qs8-gemm/gen/qs8-gemm-4x4c8-xw-minmax-fp32-wasmsimd-dot16x2.c", |
| "src/qs8-igemm/gen/qs8-igemm-1x4c2-minmax-fp32-wasmsimd-dot16x2-ld64.c", |
| "src/qs8-igemm/gen/qs8-igemm-1x4c2-minmax-fp32-wasmsimd-dot16x2-ld128.c", |
| "src/qs8-igemm/gen/qs8-igemm-1x4c2s4-minmax-fp32-wasmsimd-dot16x2-ld64.c", |
| "src/qs8-igemm/gen/qs8-igemm-1x4c2s4-minmax-fp32-wasmsimd-dot16x2-ld128.c", |
| "src/qs8-igemm/gen/qs8-igemm-1x4c8-minmax-fp32-wasmsimd-dot16x2-ld64.c", |
| "src/qs8-igemm/gen/qs8-igemm-1x4c8-minmax-fp32-wasmsimd-dot16x2-ld128.c", |
| "src/qs8-igemm/gen/qs8-igemm-2x4c2-minmax-fp32-wasmsimd-dot16x2-ld64.c", |
| "src/qs8-igemm/gen/qs8-igemm-2x4c2-minmax-fp32-wasmsimd-dot16x2-ld128.c", |
| "src/qs8-igemm/gen/qs8-igemm-2x4c2s4-minmax-fp32-wasmsimd-dot16x2-ld64.c", |
| "src/qs8-igemm/gen/qs8-igemm-2x4c2s4-minmax-fp32-wasmsimd-dot16x2-ld128.c", |
| "src/qs8-igemm/gen/qs8-igemm-2x4c8-minmax-fp32-wasmsimd-dot16x2-ld64.c", |
| "src/qs8-igemm/gen/qs8-igemm-2x4c8-minmax-fp32-wasmsimd-dot16x2-ld128.c", |
| "src/qs8-igemm/gen/qs8-igemm-3x4c2-minmax-fp32-wasmsimd-dot16x2-ld64.c", |
| "src/qs8-igemm/gen/qs8-igemm-3x4c2-minmax-fp32-wasmsimd-dot16x2-ld128.c", |
| "src/qs8-igemm/gen/qs8-igemm-3x4c2s4-minmax-fp32-wasmsimd-dot16x2-ld64.c", |
| "src/qs8-igemm/gen/qs8-igemm-3x4c2s4-minmax-fp32-wasmsimd-dot16x2-ld128.c", |
| "src/qs8-igemm/gen/qs8-igemm-3x4c8-minmax-fp32-wasmsimd-dot16x2-ld64.c", |
| "src/qs8-igemm/gen/qs8-igemm-3x4c8-minmax-fp32-wasmsimd-dot16x2-ld128.c", |
| "src/qs8-igemm/gen/qs8-igemm-4x4c2-minmax-fp32-wasmsimd-dot16x2-ld64.c", |
| "src/qs8-igemm/gen/qs8-igemm-4x4c2-minmax-fp32-wasmsimd-dot16x2-ld128.c", |
| "src/qs8-igemm/gen/qs8-igemm-4x4c2s4-minmax-fp32-wasmsimd-dot16x2-ld64.c", |
| "src/qs8-igemm/gen/qs8-igemm-4x4c2s4-minmax-fp32-wasmsimd-dot16x2-ld128.c", |
| "src/qs8-igemm/gen/qs8-igemm-4x4c8-minmax-fp32-wasmsimd-dot16x2-ld64.c", |
| "src/qs8-igemm/gen/qs8-igemm-4x4c8-minmax-fp32-wasmsimd-dot16x2-ld128.c", |
| "src/qs8-qc8w-dwconv/gen/qs8-qc8w-dwconv-3p16c-minmax-fp32-wasmsimd-mul16-add16.c", |
| "src/qs8-qc8w-dwconv/gen/qs8-qc8w-dwconv-5f5m5l8c8s8r-minmax-fp32-wasmsimd-mul16-add16.c", |
| "src/qs8-qc8w-dwconv/gen/qs8-qc8w-dwconv-5f5m5l8c8s8r-minmax-fp32-wasmsimd-mul16.c", |
| "src/qs8-qc8w-dwconv/gen/qs8-qc8w-dwconv-5f5m5l16c8s8r-minmax-fp32-wasmsimd-mul16-add16.c", |
| "src/qs8-qc8w-dwconv/gen/qs8-qc8w-dwconv-5f5m5l16c8s8r-minmax-fp32-wasmsimd-mul16.c", |
| "src/qs8-qc8w-dwconv/gen/qs8-qc8w-dwconv-6f6m7l8c8s8r-minmax-fp32-wasmsimd-mul16-add16.c", |
| "src/qs8-qc8w-dwconv/gen/qs8-qc8w-dwconv-6f6m7l8c8s8r-minmax-fp32-wasmsimd-mul16.c", |
| "src/qs8-qc8w-dwconv/gen/qs8-qc8w-dwconv-6f6m7l16c8s8r-minmax-fp32-wasmsimd-mul16-add16.c", |
| "src/qs8-qc8w-dwconv/gen/qs8-qc8w-dwconv-6f6m7l16c8s8r-minmax-fp32-wasmsimd-mul16.c", |
| "src/qs8-qc8w-dwconv/gen/qs8-qc8w-dwconv-8f8m9l8c8s8r-minmax-fp32-wasmsimd-mul16-add16.c", |
| "src/qs8-qc8w-dwconv/gen/qs8-qc8w-dwconv-8f8m9l8c8s8r-minmax-fp32-wasmsimd-mul16.c", |
| "src/qs8-qc8w-dwconv/gen/qs8-qc8w-dwconv-8f8m9l16c8s8r-minmax-fp32-wasmsimd-mul16-add16.c", |
| "src/qs8-qc8w-dwconv/gen/qs8-qc8w-dwconv-8f8m9l16c8s8r-minmax-fp32-wasmsimd-mul16.c", |
| "src/qs8-qc8w-dwconv/gen/qs8-qc8w-dwconv-9p8c-minmax-fp32-wasmsimd-mul16-add16.c", |
| "src/qs8-qc8w-dwconv/gen/qs8-qc8w-dwconv-9p8c-minmax-fp32-wasmsimd-mul16.c", |
| "src/qs8-qc8w-dwconv/gen/qs8-qc8w-dwconv-9p16c-minmax-fp32-wasmsimd-mul16-add16.c", |
| "src/qs8-qc8w-dwconv/gen/qs8-qc8w-dwconv-9p16c-minmax-fp32-wasmsimd-mul16.c", |
| "src/qs8-qc8w-dwconv/gen/qs8-qc8w-dwconv-25p8c-minmax-fp32-wasmsimd-mul16-add16.c", |
| "src/qs8-qc8w-dwconv/gen/qs8-qc8w-dwconv-25p8c-minmax-fp32-wasmsimd-mul16.c", |
| "src/qs8-qc8w-dwconv/gen/qs8-qc8w-dwconv-25p16c-minmax-fp32-wasmsimd-mul16-add16.c", |
| "src/qs8-qc8w-dwconv/gen/qs8-qc8w-dwconv-25p16c-minmax-fp32-wasmsimd-mul16.c", |
| "src/qs8-qc8w-gemm/gen/qs8-qc8w-gemm-1x4c2-minmax-fp32-wasmsimd-dot16x2-ld64.c", |
| "src/qs8-qc8w-gemm/gen/qs8-qc8w-gemm-1x4c2-minmax-fp32-wasmsimd-dot16x2-ld128.c", |
| "src/qs8-qc8w-gemm/gen/qs8-qc8w-gemm-1x4c2s4-minmax-fp32-wasmsimd-dot16x2-ld64.c", |
| "src/qs8-qc8w-gemm/gen/qs8-qc8w-gemm-1x4c2s4-minmax-fp32-wasmsimd-dot16x2-ld128.c", |
| "src/qs8-qc8w-gemm/gen/qs8-qc8w-gemm-1x4c8-minmax-fp32-wasmsimd-dot16x2-ld64.c", |
| "src/qs8-qc8w-gemm/gen/qs8-qc8w-gemm-1x4c8-minmax-fp32-wasmsimd-dot16x2-ld128.c", |
| "src/qs8-qc8w-gemm/gen/qs8-qc8w-gemm-2x4c2-minmax-fp32-wasmsimd-dot16x2-ld64.c", |
| "src/qs8-qc8w-gemm/gen/qs8-qc8w-gemm-2x4c2-minmax-fp32-wasmsimd-dot16x2-ld128.c", |
| "src/qs8-qc8w-gemm/gen/qs8-qc8w-gemm-2x4c2s4-minmax-fp32-wasmsimd-dot16x2-ld64.c", |
| "src/qs8-qc8w-gemm/gen/qs8-qc8w-gemm-2x4c2s4-minmax-fp32-wasmsimd-dot16x2-ld128.c", |
| "src/qs8-qc8w-gemm/gen/qs8-qc8w-gemm-2x4c8-minmax-fp32-wasmsimd-dot16x2-ld64.c", |
| "src/qs8-qc8w-gemm/gen/qs8-qc8w-gemm-2x4c8-minmax-fp32-wasmsimd-dot16x2-ld128.c", |
| "src/qs8-qc8w-gemm/gen/qs8-qc8w-gemm-3x4c2-minmax-fp32-wasmsimd-dot16x2-ld64.c", |
| "src/qs8-qc8w-gemm/gen/qs8-qc8w-gemm-3x4c2-minmax-fp32-wasmsimd-dot16x2-ld128.c", |
| "src/qs8-qc8w-gemm/gen/qs8-qc8w-gemm-3x4c2s4-minmax-fp32-wasmsimd-dot16x2-ld64.c", |
| "src/qs8-qc8w-gemm/gen/qs8-qc8w-gemm-3x4c2s4-minmax-fp32-wasmsimd-dot16x2-ld128.c", |
| "src/qs8-qc8w-gemm/gen/qs8-qc8w-gemm-3x4c8-minmax-fp32-wasmsimd-dot16x2-ld64.c", |
| "src/qs8-qc8w-gemm/gen/qs8-qc8w-gemm-3x4c8-minmax-fp32-wasmsimd-dot16x2-ld128.c", |
| "src/qs8-qc8w-gemm/gen/qs8-qc8w-gemm-4x4c2-minmax-fp32-wasmsimd-dot16x2-ld64.c", |
| "src/qs8-qc8w-gemm/gen/qs8-qc8w-gemm-4x4c2-minmax-fp32-wasmsimd-dot16x2-ld128.c", |
| "src/qs8-qc8w-gemm/gen/qs8-qc8w-gemm-4x4c2s4-minmax-fp32-wasmsimd-dot16x2-ld64.c", |
| "src/qs8-qc8w-gemm/gen/qs8-qc8w-gemm-4x4c2s4-minmax-fp32-wasmsimd-dot16x2-ld128.c", |
| "src/qs8-qc8w-gemm/gen/qs8-qc8w-gemm-4x4c8-minmax-fp32-wasmsimd-dot16x2-ld64.c", |
| "src/qs8-qc8w-gemm/gen/qs8-qc8w-gemm-4x4c8-minmax-fp32-wasmsimd-dot16x2-ld128.c", |
| "src/qs8-qc8w-igemm/gen/qs8-qc8w-igemm-1x4c2-minmax-fp32-wasmsimd-dot16x2-ld64.c", |
| "src/qs8-qc8w-igemm/gen/qs8-qc8w-igemm-1x4c2-minmax-fp32-wasmsimd-dot16x2-ld128.c", |
| "src/qs8-qc8w-igemm/gen/qs8-qc8w-igemm-1x4c2s4-minmax-fp32-wasmsimd-dot16x2-ld64.c", |
| "src/qs8-qc8w-igemm/gen/qs8-qc8w-igemm-1x4c2s4-minmax-fp32-wasmsimd-dot16x2-ld128.c", |
| "src/qs8-qc8w-igemm/gen/qs8-qc8w-igemm-1x4c8-minmax-fp32-wasmsimd-dot16x2-ld64.c", |
| "src/qs8-qc8w-igemm/gen/qs8-qc8w-igemm-1x4c8-minmax-fp32-wasmsimd-dot16x2-ld128.c", |
| "src/qs8-qc8w-igemm/gen/qs8-qc8w-igemm-2x4c2-minmax-fp32-wasmsimd-dot16x2-ld64.c", |
| "src/qs8-qc8w-igemm/gen/qs8-qc8w-igemm-2x4c2-minmax-fp32-wasmsimd-dot16x2-ld128.c", |
| "src/qs8-qc8w-igemm/gen/qs8-qc8w-igemm-2x4c2s4-minmax-fp32-wasmsimd-dot16x2-ld64.c", |
| "src/qs8-qc8w-igemm/gen/qs8-qc8w-igemm-2x4c2s4-minmax-fp32-wasmsimd-dot16x2-ld128.c", |
| "src/qs8-qc8w-igemm/gen/qs8-qc8w-igemm-2x4c8-minmax-fp32-wasmsimd-dot16x2-ld64.c", |
| "src/qs8-qc8w-igemm/gen/qs8-qc8w-igemm-2x4c8-minmax-fp32-wasmsimd-dot16x2-ld128.c", |
| "src/qs8-qc8w-igemm/gen/qs8-qc8w-igemm-3x4c2-minmax-fp32-wasmsimd-dot16x2-ld64.c", |
| "src/qs8-qc8w-igemm/gen/qs8-qc8w-igemm-3x4c2-minmax-fp32-wasmsimd-dot16x2-ld128.c", |
| "src/qs8-qc8w-igemm/gen/qs8-qc8w-igemm-3x4c2s4-minmax-fp32-wasmsimd-dot16x2-ld64.c", |
| "src/qs8-qc8w-igemm/gen/qs8-qc8w-igemm-3x4c2s4-minmax-fp32-wasmsimd-dot16x2-ld128.c", |
| "src/qs8-qc8w-igemm/gen/qs8-qc8w-igemm-3x4c8-minmax-fp32-wasmsimd-dot16x2-ld64.c", |
| "src/qs8-qc8w-igemm/gen/qs8-qc8w-igemm-3x4c8-minmax-fp32-wasmsimd-dot16x2-ld128.c", |
| "src/qs8-qc8w-igemm/gen/qs8-qc8w-igemm-4x4c2-minmax-fp32-wasmsimd-dot16x2-ld64.c", |
| "src/qs8-qc8w-igemm/gen/qs8-qc8w-igemm-4x4c2-minmax-fp32-wasmsimd-dot16x2-ld128.c", |
| "src/qs8-qc8w-igemm/gen/qs8-qc8w-igemm-4x4c2s4-minmax-fp32-wasmsimd-dot16x2-ld64.c", |
| "src/qs8-qc8w-igemm/gen/qs8-qc8w-igemm-4x4c2s4-minmax-fp32-wasmsimd-dot16x2-ld128.c", |
| "src/qs8-qc8w-igemm/gen/qs8-qc8w-igemm-4x4c8-minmax-fp32-wasmsimd-dot16x2-ld64.c", |
| "src/qs8-qc8w-igemm/gen/qs8-qc8w-igemm-4x4c8-minmax-fp32-wasmsimd-dot16x2-ld128.c", |
| "src/qs8-requantization/qs8-requantization-fp32-wasmsimd.c", |
| "src/qs8-requantization/qs8-requantization-gemmlowp-wasmsimd.c", |
| "src/qs8-vadd/gen/qs8-vadd-minmax-wasmsimd-u8.c", |
| "src/qs8-vadd/gen/qs8-vadd-minmax-wasmsimd-u16.c", |
| "src/qs8-vadd/gen/qs8-vadd-minmax-wasmsimd-u24.c", |
| "src/qs8-vadd/gen/qs8-vadd-minmax-wasmsimd-u32.c", |
| "src/qs8-vaddc/gen/qs8-vaddc-minmax-wasmsimd-u8.c", |
| "src/qs8-vaddc/gen/qs8-vaddc-minmax-wasmsimd-u16.c", |
| "src/qs8-vaddc/gen/qs8-vaddc-minmax-wasmsimd-u24.c", |
| "src/qs8-vaddc/gen/qs8-vaddc-minmax-wasmsimd-u32.c", |
| "src/qs8-vcvt/gen/qs8-vcvt-wasmsimd-u8.c", |
| "src/qs8-vcvt/gen/qs8-vcvt-wasmsimd-u16.c", |
| "src/qs8-vcvt/gen/qs8-vcvt-wasmsimd-u32.c", |
| "src/qs8-vlrelu/gen/qs8-vlrelu-wasmsimd-arm-u16.c", |
| "src/qs8-vlrelu/gen/qs8-vlrelu-wasmsimd-arm-u32.c", |
| "src/qs8-vlrelu/gen/qs8-vlrelu-wasmsimd-x86-u8.c", |
| "src/qs8-vlrelu/gen/qs8-vlrelu-wasmsimd-x86-u16.c", |
| "src/qs8-vlrelu/gen/qs8-vlrelu-wasmsimd-x86-u32.c", |
| "src/qs8-vmul/gen/qs8-vmul-minmax-fp32-wasmsimd-mul32-ld64-u8.c", |
| "src/qs8-vmul/gen/qs8-vmul-minmax-fp32-wasmsimd-mul32-ld64-u16.c", |
| "src/qs8-vmulc/gen/qs8-vmulc-minmax-fp32-wasmsimd-mul32-ld64-u8.c", |
| "src/qs8-vmulc/gen/qs8-vmulc-minmax-fp32-wasmsimd-mul32-ld64-u16.c", |
| "src/qs16-qs8-vcvt/gen/qs16-qs8-vcvt-wasmsimd-u8.c", |
| "src/qs16-qs8-vcvt/gen/qs16-qs8-vcvt-wasmsimd-u16.c", |
| "src/qs16-qs8-vcvt/gen/qs16-qs8-vcvt-wasmsimd-u32.c", |
| "src/qu8-dwconv/gen/qu8-dwconv-5f5m5l8c8s8r-minmax-fp32-wasmsimd-mul16.c", |
| "src/qu8-dwconv/gen/qu8-dwconv-5f5m5l16c8s8r-minmax-fp32-wasmsimd-mul16.c", |
| "src/qu8-dwconv/gen/qu8-dwconv-6f6m7l8c8s8r-minmax-fp32-wasmsimd-mul16.c", |
| "src/qu8-dwconv/gen/qu8-dwconv-6f6m7l16c8s8r-minmax-fp32-wasmsimd-mul16.c", |
| "src/qu8-dwconv/gen/qu8-dwconv-8f8m9l8c8s8r-minmax-fp32-wasmsimd-mul16.c", |
| "src/qu8-dwconv/gen/qu8-dwconv-8f8m9l16c8s8r-minmax-fp32-wasmsimd-mul16.c", |
| "src/qu8-dwconv/gen/qu8-dwconv-9p8c-minmax-fp32-wasmsimd-mul16.c", |
| "src/qu8-dwconv/gen/qu8-dwconv-9p16c-minmax-fp32-wasmsimd-mul16.c", |
| "src/qu8-dwconv/gen/qu8-dwconv-25p8c-minmax-fp32-wasmsimd-mul16.c", |
| "src/qu8-dwconv/gen/qu8-dwconv-25p16c-minmax-fp32-wasmsimd-mul16.c", |
| "src/qu8-f32-vcvt/gen/qu8-f32-vcvt-wasmsimd-u8.c", |
| "src/qu8-f32-vcvt/gen/qu8-f32-vcvt-wasmsimd-u16.c", |
| "src/qu8-f32-vcvt/gen/qu8-f32-vcvt-wasmsimd-u24.c", |
| "src/qu8-f32-vcvt/gen/qu8-f32-vcvt-wasmsimd-u32.c", |
| "src/qu8-gavgpool/gen/qu8-gavgpool-7p7x-minmax-fp32-wasmsimd-c8.c", |
| "src/qu8-gavgpool/gen/qu8-gavgpool-7p7x-minmax-fp32-wasmsimd-c16.c", |
| "src/qu8-gavgpool/gen/qu8-gavgpool-7p7x-minmax-fp32-wasmsimd-c24.c", |
| "src/qu8-gavgpool/gen/qu8-gavgpool-7p7x-minmax-fp32-wasmsimd-c32.c", |
| "src/qu8-gavgpool/gen/qu8-gavgpool-7x-minmax-fp32-wasmsimd-c8.c", |
| "src/qu8-gavgpool/gen/qu8-gavgpool-7x-minmax-fp32-wasmsimd-c16.c", |
| "src/qu8-gavgpool/gen/qu8-gavgpool-7x-minmax-fp32-wasmsimd-c24.c", |
| "src/qu8-gavgpool/gen/qu8-gavgpool-7x-minmax-fp32-wasmsimd-c32.c", |
| "src/qu8-gemm/gen/qu8-gemm-1x4c2-minmax-fp32-wasmsimd-dot16x2-ld64.c", |
| "src/qu8-gemm/gen/qu8-gemm-1x4c2-minmax-fp32-wasmsimd-dot16x2-ld128.c", |
| "src/qu8-gemm/gen/qu8-gemm-1x4c2s4-minmax-fp32-wasmsimd-dot16x2-ld64.c", |
| "src/qu8-gemm/gen/qu8-gemm-1x4c2s4-minmax-fp32-wasmsimd-dot16x2-ld128.c", |
| "src/qu8-gemm/gen/qu8-gemm-1x4c8-minmax-fp32-wasmsimd-dot16x2-ld64.c", |
| "src/qu8-gemm/gen/qu8-gemm-1x4c8-minmax-fp32-wasmsimd-dot16x2-ld128.c", |
| "src/qu8-gemm/gen/qu8-gemm-2x4c2-minmax-fp32-wasmsimd-dot16x2-ld64.c", |
| "src/qu8-gemm/gen/qu8-gemm-2x4c2-minmax-fp32-wasmsimd-dot16x2-ld128.c", |
| "src/qu8-gemm/gen/qu8-gemm-2x4c2s4-minmax-fp32-wasmsimd-dot16x2-ld64.c", |
| "src/qu8-gemm/gen/qu8-gemm-2x4c2s4-minmax-fp32-wasmsimd-dot16x2-ld128.c", |
| "src/qu8-gemm/gen/qu8-gemm-2x4c8-minmax-fp32-wasmsimd-dot16x2-ld64.c", |
| "src/qu8-gemm/gen/qu8-gemm-2x4c8-minmax-fp32-wasmsimd-dot16x2-ld128.c", |
| "src/qu8-gemm/gen/qu8-gemm-3x4c2-minmax-fp32-wasmsimd-dot16x2-ld64.c", |
| "src/qu8-gemm/gen/qu8-gemm-3x4c2-minmax-fp32-wasmsimd-dot16x2-ld128.c", |
| "src/qu8-gemm/gen/qu8-gemm-3x4c2s4-minmax-fp32-wasmsimd-dot16x2-ld64.c", |
| "src/qu8-gemm/gen/qu8-gemm-3x4c2s4-minmax-fp32-wasmsimd-dot16x2-ld128.c", |
| "src/qu8-gemm/gen/qu8-gemm-3x4c8-minmax-fp32-wasmsimd-dot16x2-ld64.c", |
| "src/qu8-gemm/gen/qu8-gemm-3x4c8-minmax-fp32-wasmsimd-dot16x2-ld128.c", |
| "src/qu8-gemm/gen/qu8-gemm-4x4c2-minmax-fp32-wasmsimd-dot16x2-ld64.c", |
| "src/qu8-gemm/gen/qu8-gemm-4x4c2-minmax-fp32-wasmsimd-dot16x2-ld128.c", |
| "src/qu8-gemm/gen/qu8-gemm-4x4c2s4-minmax-fp32-wasmsimd-dot16x2-ld64.c", |
| "src/qu8-gemm/gen/qu8-gemm-4x4c2s4-minmax-fp32-wasmsimd-dot16x2-ld128.c", |
| "src/qu8-gemm/gen/qu8-gemm-4x4c8-minmax-fp32-wasmsimd-dot16x2-ld64.c", |
| "src/qu8-gemm/gen/qu8-gemm-4x4c8-minmax-fp32-wasmsimd-dot16x2-ld128.c", |
| "src/qu8-igemm/gen/qu8-igemm-1x4c2-minmax-fp32-wasmsimd-dot16x2-ld64.c", |
| "src/qu8-igemm/gen/qu8-igemm-1x4c2-minmax-fp32-wasmsimd-dot16x2-ld128.c", |
| "src/qu8-igemm/gen/qu8-igemm-1x4c2s4-minmax-fp32-wasmsimd-dot16x2-ld64.c", |
| "src/qu8-igemm/gen/qu8-igemm-1x4c2s4-minmax-fp32-wasmsimd-dot16x2-ld128.c", |
| "src/qu8-igemm/gen/qu8-igemm-1x4c8-minmax-fp32-wasmsimd-dot16x2-ld64.c", |
| "src/qu8-igemm/gen/qu8-igemm-1x4c8-minmax-fp32-wasmsimd-dot16x2-ld128.c", |
| "src/qu8-igemm/gen/qu8-igemm-2x4c2-minmax-fp32-wasmsimd-dot16x2-ld64.c", |
| "src/qu8-igemm/gen/qu8-igemm-2x4c2-minmax-fp32-wasmsimd-dot16x2-ld128.c", |
| "src/qu8-igemm/gen/qu8-igemm-2x4c2s4-minmax-fp32-wasmsimd-dot16x2-ld64.c", |
| "src/qu8-igemm/gen/qu8-igemm-2x4c2s4-minmax-fp32-wasmsimd-dot16x2-ld128.c", |
| "src/qu8-igemm/gen/qu8-igemm-2x4c8-minmax-fp32-wasmsimd-dot16x2-ld64.c", |
| "src/qu8-igemm/gen/qu8-igemm-2x4c8-minmax-fp32-wasmsimd-dot16x2-ld128.c", |
| "src/qu8-igemm/gen/qu8-igemm-3x4c2-minmax-fp32-wasmsimd-dot16x2-ld64.c", |
| "src/qu8-igemm/gen/qu8-igemm-3x4c2-minmax-fp32-wasmsimd-dot16x2-ld128.c", |
| "src/qu8-igemm/gen/qu8-igemm-3x4c2s4-minmax-fp32-wasmsimd-dot16x2-ld64.c", |
| "src/qu8-igemm/gen/qu8-igemm-3x4c2s4-minmax-fp32-wasmsimd-dot16x2-ld128.c", |
| "src/qu8-igemm/gen/qu8-igemm-3x4c8-minmax-fp32-wasmsimd-dot16x2-ld64.c", |
| "src/qu8-igemm/gen/qu8-igemm-3x4c8-minmax-fp32-wasmsimd-dot16x2-ld128.c", |
| "src/qu8-igemm/gen/qu8-igemm-4x4c2-minmax-fp32-wasmsimd-dot16x2-ld64.c", |
| "src/qu8-igemm/gen/qu8-igemm-4x4c2-minmax-fp32-wasmsimd-dot16x2-ld128.c", |
| "src/qu8-igemm/gen/qu8-igemm-4x4c2s4-minmax-fp32-wasmsimd-dot16x2-ld64.c", |
| "src/qu8-igemm/gen/qu8-igemm-4x4c2s4-minmax-fp32-wasmsimd-dot16x2-ld128.c", |
| "src/qu8-igemm/gen/qu8-igemm-4x4c8-minmax-fp32-wasmsimd-dot16x2-ld64.c", |
| "src/qu8-igemm/gen/qu8-igemm-4x4c8-minmax-fp32-wasmsimd-dot16x2-ld128.c", |
| "src/qu8-requantization/qu8-requantization-fp32-wasmsimd.c", |
| "src/qu8-requantization/qu8-requantization-gemmlowp-wasmsimd.c", |
| "src/qu8-vadd/gen/qu8-vadd-minmax-wasmsimd-u8.c", |
| "src/qu8-vadd/gen/qu8-vadd-minmax-wasmsimd-u16.c", |
| "src/qu8-vadd/gen/qu8-vadd-minmax-wasmsimd-u32.c", |
| "src/qu8-vaddc/gen/qu8-vaddc-minmax-wasmsimd-u8.c", |
| "src/qu8-vaddc/gen/qu8-vaddc-minmax-wasmsimd-u16.c", |
| "src/qu8-vaddc/gen/qu8-vaddc-minmax-wasmsimd-u32.c", |
| "src/qu8-vcvt/gen/qu8-vcvt-wasmsimd-u8.c", |
| "src/qu8-vcvt/gen/qu8-vcvt-wasmsimd-u16.c", |
| "src/qu8-vcvt/gen/qu8-vcvt-wasmsimd-u32.c", |
| "src/qu8-vlrelu/gen/qu8-vlrelu-wasmsimd-arm-u16.c", |
| "src/qu8-vlrelu/gen/qu8-vlrelu-wasmsimd-arm-u32.c", |
| "src/qu8-vlrelu/gen/qu8-vlrelu-wasmsimd-x86-u8.c", |
| "src/qu8-vlrelu/gen/qu8-vlrelu-wasmsimd-x86-u16.c", |
| "src/qu8-vlrelu/gen/qu8-vlrelu-wasmsimd-x86-u32.c", |
| "src/qu8-vmul/gen/qu8-vmul-minmax-fp32-wasmsimd-mul32-ld64-u8.c", |
| "src/qu8-vmul/gen/qu8-vmul-minmax-fp32-wasmsimd-mul32-ld64-u16.c", |
| "src/qu8-vmulc/gen/qu8-vmulc-minmax-fp32-wasmsimd-mul32-ld64-u8.c", |
| "src/qu8-vmulc/gen/qu8-vmulc-minmax-fp32-wasmsimd-mul32-ld64-u16.c", |
| "src/s8-ibilinear/gen/s8-ibilinear-wasmsimd-dot16x2-c8.c", |
| "src/s8-ibilinear/gen/s8-ibilinear-wasmsimd-dot16x2-c16.c", |
| "src/s8-ibilinear/gen/s8-ibilinear-wasmsimd-mul32-c8.c", |
| "src/s8-ibilinear/gen/s8-ibilinear-wasmsimd-mul32-c16.c", |
| "src/s8-maxpool/s8-maxpool-9p8x-minmax-wasmsimd-c16.c", |
| "src/s8-vclamp/s8-vclamp-wasmsimd-u64.c", |
| "src/u8-ibilinear/gen/u8-ibilinear-wasmsimd-dot16x2-c8.c", |
| "src/u8-ibilinear/gen/u8-ibilinear-wasmsimd-dot16x2-c16.c", |
| "src/u8-ibilinear/gen/u8-ibilinear-wasmsimd-mul32-c8.c", |
| "src/u8-ibilinear/gen/u8-ibilinear-wasmsimd-mul32-c16.c", |
| "src/u8-maxpool/u8-maxpool-9p8x-minmax-wasmsimd-c16.c", |
| "src/u8-vclamp/u8-vclamp-wasmsimd-u64.c", |
| "src/x8-lut/gen/x8-lut-wasmsimd-u16.c", |
| "src/x8-lut/gen/x8-lut-wasmsimd-u32.c", |
| "src/x8-lut/gen/x8-lut-wasmsimd-u48.c", |
| "src/x8-lut/gen/x8-lut-wasmsimd-u64.c", |
| "src/x8-transposec/gen/x8-transposec-16x16-reuse-mov-wasmsimd.c", |
| "src/x8-transposec/gen/x8-transposec-16x16-reuse-switch-wasmsimd.c", |
| "src/x16-transposec/gen/x16-transposec-8x8-multi-mov-wasmsimd.c", |
| "src/x16-transposec/gen/x16-transposec-8x8-multi-switch-wasmsimd.c", |
| "src/x16-transposec/gen/x16-transposec-8x8-reuse-mov-wasmsimd.c", |
| "src/x16-transposec/gen/x16-transposec-8x8-reuse-multi-wasmsimd.c", |
| "src/x16-transposec/gen/x16-transposec-8x8-reuse-switch-wasmsimd.c", |
| "src/x32-packw/gen/x32-packw-x2c4-gemm-goi-wasmsimd-u4.c", |
| "src/x32-packw/gen/x32-packw-x8-gemm-goi-wasmsimd-u4.c", |
| "src/x32-packw/gen/x32-packw-x8s4-gemm-goi-wasmsimd-u4.c", |
| "src/x32-packx/x32-packx-4x-wasmsimd.c", |
| "src/x32-transposec/gen/x32-transposec-4x4-multi-mov-wasmsimd.c", |
| "src/x32-transposec/gen/x32-transposec-4x4-multi-multi-wasmsimd.c", |
| "src/x32-transposec/gen/x32-transposec-4x4-multi-switch-wasmsimd.c", |
| "src/x32-transposec/gen/x32-transposec-4x4-reuse-mov-wasmsimd.c", |
| "src/x32-transposec/gen/x32-transposec-4x4-reuse-multi-wasmsimd.c", |
| "src/x32-transposec/gen/x32-transposec-4x4-reuse-switch-wasmsimd.c", |
| "src/x32-unpool/x32-unpool-wasmsimd.c", |
| "src/x32-zip/x32-zip-x2-wasmsimd.c", |
| "src/x32-zip/x32-zip-x3-wasmsimd.c", |
| "src/x32-zip/x32-zip-x4-wasmsimd.c", |
| "src/x32-zip/x32-zip-xm-wasmsimd.c", |
| "src/xx-fill/xx-fill-wasmsimd-x64.c", |
| "src/xx-pad/xx-pad-wasmsimd.c", |
| ] |
| |
| ALL_XOP_MICROKERNEL_SRCS = [ |
| "src/qd8-f32-qc8w-gemm/gen/qd8-f32-qc8w-gemm-1x4c8-minmax-xop-ld64.c", |
| "src/qd8-f32-qc8w-gemm/gen/qd8-f32-qc8w-gemm-1x4c8-minmax-xop-ld128.c", |
| "src/qd8-f32-qc8w-gemm/gen/qd8-f32-qc8w-gemm-2x4c8-minmax-xop-ld64.c", |
| "src/qd8-f32-qc8w-gemm/gen/qd8-f32-qc8w-gemm-2x4c8-minmax-xop-ld128.c", |
| "src/qd8-f32-qc8w-gemm/gen/qd8-f32-qc8w-gemm-3x4c8-minmax-xop-ld64.c", |
| "src/qd8-f32-qc8w-gemm/gen/qd8-f32-qc8w-gemm-3x4c8-minmax-xop-ld128.c", |
| "src/qd8-f32-qc8w-gemm/gen/qd8-f32-qc8w-gemm-4x4c8-minmax-xop-ld64.c", |
| "src/qd8-f32-qc8w-gemm/gen/qd8-f32-qc8w-gemm-4x4c8-minmax-xop-ld128.c", |
| "src/qs8-dwconv/gen/qs8-dwconv-5f5m5l8c4s4r-minmax-fp32-xop-mul32.c", |
| "src/qs8-dwconv/gen/qs8-dwconv-5f5m5l16c4s4r-minmax-fp32-xop-mul32.c", |
| "src/qs8-dwconv/gen/qs8-dwconv-6f6m7l8c4s4r-minmax-fp32-xop-mul32.c", |
| "src/qs8-dwconv/gen/qs8-dwconv-6f6m7l16c4s4r-minmax-fp32-xop-mul32.c", |
| "src/qs8-dwconv/gen/qs8-dwconv-8f8m9l8c4s4r-minmax-fp32-xop-mul32.c", |
| "src/qs8-dwconv/gen/qs8-dwconv-8f8m9l16c4s4r-minmax-fp32-xop-mul32.c", |
| "src/qs8-dwconv/gen/qs8-dwconv-9p8c-minmax-fp32-xop-mul16-add16.c", |
| "src/qs8-dwconv/gen/qs8-dwconv-9p8c-minmax-fp32-xop-mul32.c", |
| "src/qs8-dwconv/gen/qs8-dwconv-9p16c-minmax-fp32-xop-mul16-add16.c", |
| "src/qs8-dwconv/gen/qs8-dwconv-9p16c-minmax-fp32-xop-mul32.c", |
| "src/qs8-dwconv/gen/qs8-dwconv-25p8c-minmax-fp32-xop-mul16-add16.c", |
| "src/qs8-dwconv/gen/qs8-dwconv-25p8c-minmax-fp32-xop-mul32.c", |
| "src/qs8-dwconv/gen/qs8-dwconv-25p16c-minmax-fp32-xop-mul16-add16.c", |
| "src/qs8-dwconv/gen/qs8-dwconv-25p16c-minmax-fp32-xop-mul32.c", |
| "src/qs8-gemm/gen/qs8-gemm-1x4c2-minmax-fp32-xop-ld64.c", |
| "src/qs8-gemm/gen/qs8-gemm-1x4c2-minmax-fp32-xop-ld128.c", |
| "src/qs8-gemm/gen/qs8-gemm-1x4c2-xw-minmax-fp32-xop.c", |
| "src/qs8-gemm/gen/qs8-gemm-1x4c2s4-minmax-fp32-xop-ld64.c", |
| "src/qs8-gemm/gen/qs8-gemm-1x4c2s4-minmax-fp32-xop-ld128.c", |
| "src/qs8-gemm/gen/qs8-gemm-1x4c2s4-xw-minmax-fp32-xop.c", |
| "src/qs8-gemm/gen/qs8-gemm-1x4c8-minmax-fp32-xop-ld64.c", |
| "src/qs8-gemm/gen/qs8-gemm-1x4c8-minmax-fp32-xop-ld128.c", |
| "src/qs8-gemm/gen/qs8-gemm-1x4c8-xw-minmax-fp32-xop.c", |
| "src/qs8-gemm/gen/qs8-gemm-2x4c2-minmax-fp32-xop-ld64.c", |
| "src/qs8-gemm/gen/qs8-gemm-2x4c2-minmax-fp32-xop-ld128.c", |
| "src/qs8-gemm/gen/qs8-gemm-2x4c2-xw-minmax-fp32-xop.c", |
| "src/qs8-gemm/gen/qs8-gemm-2x4c2s4-minmax-fp32-xop-ld64.c", |
| "src/qs8-gemm/gen/qs8-gemm-2x4c2s4-minmax-fp32-xop-ld128.c", |
| "src/qs8-gemm/gen/qs8-gemm-2x4c2s4-xw-minmax-fp32-xop.c", |
| "src/qs8-gemm/gen/qs8-gemm-2x4c8-minmax-fp32-xop-ld64.c", |
| "src/qs8-gemm/gen/qs8-gemm-2x4c8-minmax-fp32-xop-ld128.c", |
| "src/qs8-gemm/gen/qs8-gemm-2x4c8-xw-minmax-fp32-xop.c", |
| "src/qs8-gemm/gen/qs8-gemm-3x4c2-minmax-fp32-xop-ld64.c", |
| "src/qs8-gemm/gen/qs8-gemm-3x4c2-minmax-fp32-xop-ld128.c", |
| "src/qs8-gemm/gen/qs8-gemm-3x4c2-xw-minmax-fp32-xop.c", |
| "src/qs8-gemm/gen/qs8-gemm-3x4c2s4-minmax-fp32-xop-ld64.c", |
| "src/qs8-gemm/gen/qs8-gemm-3x4c2s4-minmax-fp32-xop-ld128.c", |
| "src/qs8-gemm/gen/qs8-gemm-3x4c2s4-xw-minmax-fp32-xop.c", |
| "src/qs8-gemm/gen/qs8-gemm-3x4c8-minmax-fp32-xop-ld64.c", |
| "src/qs8-gemm/gen/qs8-gemm-3x4c8-minmax-fp32-xop-ld128.c", |
| "src/qs8-gemm/gen/qs8-gemm-3x4c8-xw-minmax-fp32-xop.c", |
| "src/qs8-gemm/gen/qs8-gemm-4x4c2-minmax-fp32-xop-ld64.c", |
| "src/qs8-gemm/gen/qs8-gemm-4x4c2-minmax-fp32-xop-ld128.c", |
| "src/qs8-gemm/gen/qs8-gemm-4x4c2-xw-minmax-fp32-xop.c", |
| "src/qs8-gemm/gen/qs8-gemm-4x4c2s4-minmax-fp32-xop-ld64.c", |
| "src/qs8-gemm/gen/qs8-gemm-4x4c2s4-minmax-fp32-xop-ld128.c", |
| "src/qs8-gemm/gen/qs8-gemm-4x4c2s4-xw-minmax-fp32-xop.c", |
| "src/qs8-igemm/gen/qs8-igemm-1x4c2-minmax-fp32-xop-ld64.c", |
| "src/qs8-igemm/gen/qs8-igemm-1x4c2-minmax-fp32-xop-ld128.c", |
| "src/qs8-igemm/gen/qs8-igemm-1x4c2s4-minmax-fp32-xop-ld64.c", |
| "src/qs8-igemm/gen/qs8-igemm-1x4c2s4-minmax-fp32-xop-ld128.c", |
| "src/qs8-igemm/gen/qs8-igemm-1x4c8-minmax-fp32-xop-ld64.c", |
| "src/qs8-igemm/gen/qs8-igemm-1x4c8-minmax-fp32-xop-ld128.c", |
| "src/qs8-igemm/gen/qs8-igemm-2x4c2-minmax-fp32-xop-ld64.c", |
| "src/qs8-igemm/gen/qs8-igemm-2x4c2-minmax-fp32-xop-ld128.c", |
| "src/qs8-igemm/gen/qs8-igemm-2x4c2s4-minmax-fp32-xop-ld64.c", |
| "src/qs8-igemm/gen/qs8-igemm-2x4c2s4-minmax-fp32-xop-ld128.c", |
| "src/qs8-igemm/gen/qs8-igemm-2x4c8-minmax-fp32-xop-ld64.c", |
| "src/qs8-igemm/gen/qs8-igemm-2x4c8-minmax-fp32-xop-ld128.c", |
| "src/qs8-igemm/gen/qs8-igemm-3x4c2-minmax-fp32-xop-ld64.c", |
| "src/qs8-igemm/gen/qs8-igemm-3x4c2-minmax-fp32-xop-ld128.c", |
| "src/qs8-igemm/gen/qs8-igemm-3x4c2s4-minmax-fp32-xop-ld64.c", |
| "src/qs8-igemm/gen/qs8-igemm-3x4c2s4-minmax-fp32-xop-ld128.c", |
| "src/qs8-igemm/gen/qs8-igemm-3x4c8-minmax-fp32-xop-ld64.c", |
| "src/qs8-igemm/gen/qs8-igemm-3x4c8-minmax-fp32-xop-ld128.c", |
| "src/qs8-igemm/gen/qs8-igemm-4x4c2-minmax-fp32-xop-ld64.c", |
| "src/qs8-igemm/gen/qs8-igemm-4x4c2-minmax-fp32-xop-ld128.c", |
| "src/qs8-igemm/gen/qs8-igemm-4x4c2s4-minmax-fp32-xop-ld64.c", |
| "src/qs8-igemm/gen/qs8-igemm-4x4c2s4-minmax-fp32-xop-ld128.c", |
| "src/qs8-qc8w-dwconv/gen/qs8-qc8w-dwconv-3p16c-minmax-fp32-xop-mul16-add16.c", |
| "src/qs8-qc8w-dwconv/gen/qs8-qc8w-dwconv-5f5m5l8c4s4r-minmax-fp32-xop-mul32.c", |
| "src/qs8-qc8w-dwconv/gen/qs8-qc8w-dwconv-5f5m5l16c4s4r-minmax-fp32-xop-mul32.c", |
| "src/qs8-qc8w-dwconv/gen/qs8-qc8w-dwconv-6f6m7l8c4s4r-minmax-fp32-xop-mul32.c", |
| "src/qs8-qc8w-dwconv/gen/qs8-qc8w-dwconv-6f6m7l16c4s4r-minmax-fp32-xop-mul32.c", |
| "src/qs8-qc8w-dwconv/gen/qs8-qc8w-dwconv-8f8m9l8c4s4r-minmax-fp32-xop-mul32.c", |
| "src/qs8-qc8w-dwconv/gen/qs8-qc8w-dwconv-8f8m9l16c4s4r-minmax-fp32-xop-mul32.c", |
| "src/qs8-qc8w-dwconv/gen/qs8-qc8w-dwconv-9p8c-minmax-fp32-xop-mul16-add16.c", |
| "src/qs8-qc8w-dwconv/gen/qs8-qc8w-dwconv-9p8c-minmax-fp32-xop-mul32.c", |
| "src/qs8-qc8w-dwconv/gen/qs8-qc8w-dwconv-9p16c-minmax-fp32-xop-mul16-add16.c", |
| "src/qs8-qc8w-dwconv/gen/qs8-qc8w-dwconv-9p16c-minmax-fp32-xop-mul32.c", |
| "src/qs8-qc8w-dwconv/gen/qs8-qc8w-dwconv-25p8c-minmax-fp32-xop-mul16-add16.c", |
| "src/qs8-qc8w-dwconv/gen/qs8-qc8w-dwconv-25p8c-minmax-fp32-xop-mul32.c", |
| "src/qs8-qc8w-dwconv/gen/qs8-qc8w-dwconv-25p16c-minmax-fp32-xop-mul16-add16.c", |
| "src/qs8-qc8w-dwconv/gen/qs8-qc8w-dwconv-25p16c-minmax-fp32-xop-mul32.c", |
| "src/qs8-qc8w-gemm/gen/qs8-qc8w-gemm-1x4c2-minmax-fp32-xop-ld64.c", |
| "src/qs8-qc8w-gemm/gen/qs8-qc8w-gemm-1x4c2-minmax-fp32-xop-ld128.c", |
| "src/qs8-qc8w-gemm/gen/qs8-qc8w-gemm-1x4c2s4-minmax-fp32-xop-ld64.c", |
| "src/qs8-qc8w-gemm/gen/qs8-qc8w-gemm-1x4c2s4-minmax-fp32-xop-ld128.c", |
| "src/qs8-qc8w-gemm/gen/qs8-qc8w-gemm-1x4c8-minmax-fp32-xop-ld64.c", |
| "src/qs8-qc8w-gemm/gen/qs8-qc8w-gemm-1x4c8-minmax-fp32-xop-ld128.c", |
| "src/qs8-qc8w-gemm/gen/qs8-qc8w-gemm-2x4c2-minmax-fp32-xop-ld64.c", |
| "src/qs8-qc8w-gemm/gen/qs8-qc8w-gemm-2x4c2-minmax-fp32-xop-ld128.c", |
| "src/qs8-qc8w-gemm/gen/qs8-qc8w-gemm-2x4c2s4-minmax-fp32-xop-ld64.c", |
| "src/qs8-qc8w-gemm/gen/qs8-qc8w-gemm-2x4c2s4-minmax-fp32-xop-ld128.c", |
| "src/qs8-qc8w-gemm/gen/qs8-qc8w-gemm-2x4c8-minmax-fp32-xop-ld64.c", |
| "src/qs8-qc8w-gemm/gen/qs8-qc8w-gemm-2x4c8-minmax-fp32-xop-ld128.c", |
| "src/qs8-qc8w-gemm/gen/qs8-qc8w-gemm-3x4c2-minmax-fp32-xop-ld64.c", |
| "src/qs8-qc8w-gemm/gen/qs8-qc8w-gemm-3x4c2-minmax-fp32-xop-ld128.c", |
| "src/qs8-qc8w-gemm/gen/qs8-qc8w-gemm-3x4c2s4-minmax-fp32-xop-ld64.c", |
| "src/qs8-qc8w-gemm/gen/qs8-qc8w-gemm-3x4c2s4-minmax-fp32-xop-ld128.c", |
| "src/qs8-qc8w-gemm/gen/qs8-qc8w-gemm-3x4c8-minmax-fp32-xop-ld64.c", |
| "src/qs8-qc8w-gemm/gen/qs8-qc8w-gemm-3x4c8-minmax-fp32-xop-ld128.c", |
| "src/qs8-qc8w-gemm/gen/qs8-qc8w-gemm-4x4c2-minmax-fp32-xop-ld64.c", |
| "src/qs8-qc8w-gemm/gen/qs8-qc8w-gemm-4x4c2-minmax-fp32-xop-ld128.c", |
| "src/qs8-qc8w-gemm/gen/qs8-qc8w-gemm-4x4c2s4-minmax-fp32-xop-ld64.c", |
| "src/qs8-qc8w-gemm/gen/qs8-qc8w-gemm-4x4c2s4-minmax-fp32-xop-ld128.c", |
| "src/qs8-qc8w-igemm/gen/qs8-qc8w-igemm-1x4c2-minmax-fp32-xop-ld64.c", |
| "src/qs8-qc8w-igemm/gen/qs8-qc8w-igemm-1x4c2-minmax-fp32-xop-ld128.c", |
| "src/qs8-qc8w-igemm/gen/qs8-qc8w-igemm-1x4c2s4-minmax-fp32-xop-ld64.c", |
| "src/qs8-qc8w-igemm/gen/qs8-qc8w-igemm-1x4c2s4-minmax-fp32-xop-ld128.c", |
| "src/qs8-qc8w-igemm/gen/qs8-qc8w-igemm-1x4c8-minmax-fp32-xop-ld64.c", |
| "src/qs8-qc8w-igemm/gen/qs8-qc8w-igemm-1x4c8-minmax-fp32-xop-ld128.c", |
| "src/qs8-qc8w-igemm/gen/qs8-qc8w-igemm-2x4c2-minmax-fp32-xop-ld64.c", |
| "src/qs8-qc8w-igemm/gen/qs8-qc8w-igemm-2x4c2-minmax-fp32-xop-ld128.c", |
| "src/qs8-qc8w-igemm/gen/qs8-qc8w-igemm-2x4c2s4-minmax-fp32-xop-ld64.c", |
| "src/qs8-qc8w-igemm/gen/qs8-qc8w-igemm-2x4c2s4-minmax-fp32-xop-ld128.c", |
| "src/qs8-qc8w-igemm/gen/qs8-qc8w-igemm-2x4c8-minmax-fp32-xop-ld64.c", |
| "src/qs8-qc8w-igemm/gen/qs8-qc8w-igemm-2x4c8-minmax-fp32-xop-ld128.c", |
| "src/qs8-qc8w-igemm/gen/qs8-qc8w-igemm-3x4c2-minmax-fp32-xop-ld64.c", |
| "src/qs8-qc8w-igemm/gen/qs8-qc8w-igemm-3x4c2-minmax-fp32-xop-ld128.c", |
| "src/qs8-qc8w-igemm/gen/qs8-qc8w-igemm-3x4c2s4-minmax-fp32-xop-ld64.c", |
| "src/qs8-qc8w-igemm/gen/qs8-qc8w-igemm-3x4c2s4-minmax-fp32-xop-ld128.c", |
| "src/qs8-qc8w-igemm/gen/qs8-qc8w-igemm-3x4c8-minmax-fp32-xop-ld64.c", |
| "src/qs8-qc8w-igemm/gen/qs8-qc8w-igemm-3x4c8-minmax-fp32-xop-ld128.c", |
| "src/qs8-qc8w-igemm/gen/qs8-qc8w-igemm-4x4c2-minmax-fp32-xop-ld64.c", |
| "src/qs8-qc8w-igemm/gen/qs8-qc8w-igemm-4x4c2-minmax-fp32-xop-ld128.c", |
| "src/qs8-qc8w-igemm/gen/qs8-qc8w-igemm-4x4c2s4-minmax-fp32-xop-ld64.c", |
| "src/qs8-qc8w-igemm/gen/qs8-qc8w-igemm-4x4c2s4-minmax-fp32-xop-ld128.c", |
| "src/qs8-vadd/gen/qs8-vadd-minmax-xop-mul32-ld32-u8.c", |
| "src/qs8-vadd/gen/qs8-vadd-minmax-xop-mul32-ld32-u16.c", |
| "src/qs8-vadd/gen/qs8-vadd-minmax-xop-mul32-ld32-u24.c", |
| "src/qs8-vadd/gen/qs8-vadd-minmax-xop-mul32-ld32-u32.c", |
| "src/qs8-vaddc/gen/qs8-vaddc-minmax-xop-mul32-ld32-u8.c", |
| "src/qs8-vaddc/gen/qs8-vaddc-minmax-xop-mul32-ld32-u16.c", |
| "src/qs8-vaddc/gen/qs8-vaddc-minmax-xop-mul32-ld32-u24.c", |
| "src/qs8-vaddc/gen/qs8-vaddc-minmax-xop-mul32-ld32-u32.c", |
| "src/qu8-dwconv/gen/qu8-dwconv-5f5m5l8c4s4r-minmax-fp32-xop-mul32.c", |
| "src/qu8-dwconv/gen/qu8-dwconv-5f5m5l16c4s4r-minmax-fp32-xop-mul32.c", |
| "src/qu8-dwconv/gen/qu8-dwconv-6f6m7l8c4s4r-minmax-fp32-xop-mul32.c", |
| "src/qu8-dwconv/gen/qu8-dwconv-6f6m7l16c4s4r-minmax-fp32-xop-mul32.c", |
| "src/qu8-dwconv/gen/qu8-dwconv-8f8m9l8c4s4r-minmax-fp32-xop-mul32.c", |
| "src/qu8-dwconv/gen/qu8-dwconv-8f8m9l16c4s4r-minmax-fp32-xop-mul32.c", |
| "src/qu8-dwconv/gen/qu8-dwconv-9p8c-minmax-fp32-xop-mul32.c", |
| "src/qu8-dwconv/gen/qu8-dwconv-9p16c-minmax-fp32-xop-mul32.c", |
| "src/qu8-dwconv/gen/qu8-dwconv-25p8c-minmax-fp32-xop-mul32.c", |
| "src/qu8-dwconv/gen/qu8-dwconv-25p16c-minmax-fp32-xop-mul32.c", |
| "src/qu8-gemm/gen/qu8-gemm-1x4c2-minmax-fp32-xop-ld64.c", |
| "src/qu8-gemm/gen/qu8-gemm-1x4c2-minmax-fp32-xop-ld128.c", |
| "src/qu8-gemm/gen/qu8-gemm-1x4c2s4-minmax-fp32-xop-ld64.c", |
| "src/qu8-gemm/gen/qu8-gemm-1x4c2s4-minmax-fp32-xop-ld128.c", |
| "src/qu8-gemm/gen/qu8-gemm-1x4c8-minmax-fp32-xop-ld64.c", |
| "src/qu8-gemm/gen/qu8-gemm-1x4c8-minmax-fp32-xop-ld128.c", |
| "src/qu8-gemm/gen/qu8-gemm-2x4c2-minmax-fp32-xop-ld64.c", |
| "src/qu8-gemm/gen/qu8-gemm-2x4c2-minmax-fp32-xop-ld128.c", |
| "src/qu8-gemm/gen/qu8-gemm-2x4c2s4-minmax-fp32-xop-ld64.c", |
| "src/qu8-gemm/gen/qu8-gemm-2x4c2s4-minmax-fp32-xop-ld128.c", |
| "src/qu8-gemm/gen/qu8-gemm-2x4c8-minmax-fp32-xop-ld64.c", |
| "src/qu8-gemm/gen/qu8-gemm-2x4c8-minmax-fp32-xop-ld128.c", |
| "src/qu8-gemm/gen/qu8-gemm-3x4c2-minmax-fp32-xop-ld64.c", |
| "src/qu8-gemm/gen/qu8-gemm-3x4c2-minmax-fp32-xop-ld128.c", |
| "src/qu8-gemm/gen/qu8-gemm-3x4c2s4-minmax-fp32-xop-ld64.c", |
| "src/qu8-gemm/gen/qu8-gemm-3x4c2s4-minmax-fp32-xop-ld128.c", |
| "src/qu8-gemm/gen/qu8-gemm-3x4c8-minmax-fp32-xop-ld64.c", |
| "src/qu8-gemm/gen/qu8-gemm-3x4c8-minmax-fp32-xop-ld128.c", |
| "src/qu8-gemm/gen/qu8-gemm-4x4c2-minmax-fp32-xop-ld64.c", |
| "src/qu8-gemm/gen/qu8-gemm-4x4c2-minmax-fp32-xop-ld128.c", |
| "src/qu8-gemm/gen/qu8-gemm-4x4c2s4-minmax-fp32-xop-ld64.c", |
| "src/qu8-gemm/gen/qu8-gemm-4x4c2s4-minmax-fp32-xop-ld128.c", |
| "src/qu8-igemm/gen/qu8-igemm-1x4c2-minmax-fp32-xop-ld64.c", |
| "src/qu8-igemm/gen/qu8-igemm-1x4c2-minmax-fp32-xop-ld128.c", |
| "src/qu8-igemm/gen/qu8-igemm-1x4c2s4-minmax-fp32-xop-ld64.c", |
| "src/qu8-igemm/gen/qu8-igemm-1x4c2s4-minmax-fp32-xop-ld128.c", |
| "src/qu8-igemm/gen/qu8-igemm-1x4c8-minmax-fp32-xop-ld64.c", |
| "src/qu8-igemm/gen/qu8-igemm-1x4c8-minmax-fp32-xop-ld128.c", |
| "src/qu8-igemm/gen/qu8-igemm-2x4c2-minmax-fp32-xop-ld64.c", |
| "src/qu8-igemm/gen/qu8-igemm-2x4c2-minmax-fp32-xop-ld128.c", |
| "src/qu8-igemm/gen/qu8-igemm-2x4c2s4-minmax-fp32-xop-ld64.c", |
| "src/qu8-igemm/gen/qu8-igemm-2x4c2s4-minmax-fp32-xop-ld128.c", |
| "src/qu8-igemm/gen/qu8-igemm-2x4c8-minmax-fp32-xop-ld64.c", |
| "src/qu8-igemm/gen/qu8-igemm-2x4c8-minmax-fp32-xop-ld128.c", |
| "src/qu8-igemm/gen/qu8-igemm-3x4c2-minmax-fp32-xop-ld64.c", |
| "src/qu8-igemm/gen/qu8-igemm-3x4c2-minmax-fp32-xop-ld128.c", |
| "src/qu8-igemm/gen/qu8-igemm-3x4c2s4-minmax-fp32-xop-ld64.c", |
| "src/qu8-igemm/gen/qu8-igemm-3x4c2s4-minmax-fp32-xop-ld128.c", |
| "src/qu8-igemm/gen/qu8-igemm-3x4c8-minmax-fp32-xop-ld64.c", |
| "src/qu8-igemm/gen/qu8-igemm-3x4c8-minmax-fp32-xop-ld128.c", |
| "src/qu8-igemm/gen/qu8-igemm-4x4c2-minmax-fp32-xop-ld64.c", |
| "src/qu8-igemm/gen/qu8-igemm-4x4c2-minmax-fp32-xop-ld128.c", |
| "src/qu8-igemm/gen/qu8-igemm-4x4c2s4-minmax-fp32-xop-ld64.c", |
| "src/qu8-igemm/gen/qu8-igemm-4x4c2s4-minmax-fp32-xop-ld128.c", |
| "src/qu8-vadd/gen/qu8-vadd-minmax-xop-mul32-ld32-u8.c", |
| "src/qu8-vadd/gen/qu8-vadd-minmax-xop-mul32-ld32-u16.c", |
| "src/qu8-vaddc/gen/qu8-vaddc-minmax-xop-mul32-ld32-u8.c", |
| "src/qu8-vaddc/gen/qu8-vaddc-minmax-xop-mul32-ld32-u16.c", |
| ] |
| |
| AARCH32_ASM_MICROKERNEL_SRCS = [ |
| "src/cs16-bfly4/cs16-bfly4-samples1-asm-aarch32-neon-x1.S", |
| "src/cs16-bfly4/cs16-bfly4-samples1-asm-aarch32-neon-x2.S", |
| "src/cs16-bfly4/cs16-bfly4-samples1-asm-aarch32-neon-x4.S", |
| "src/cs16-fftr/cs16-fftr-asm-aarch32-neon-x1.S", |
| "src/cs16-fftr/cs16-fftr-asm-aarch32-neon-x4.S", |
| "src/f32-gemm/gen/f32-gemm-1x8-minmax-asm-aarch32-neon-cortex-a53-prfm.S", |
| "src/f32-gemm/gen/f32-gemm-1x8-minmax-asm-aarch32-neon-cortex-a53.S", |
| "src/f32-gemm/gen/f32-gemm-4x4-asm-aarch32-vfp-ld64.S", |
| "src/f32-gemm/gen/f32-gemm-4x4-minmax-asm-aarch32-vfp-ld64.S", |
| "src/f32-gemm/gen/f32-gemm-4x8-minmax-asm-aarch32-neon-cortex-a7.S", |
| "src/f32-gemm/gen/f32-gemm-4x8-minmax-asm-aarch32-neon-cortex-a53-prfm.S", |
| "src/f32-gemm/gen/f32-gemm-4x8-minmax-asm-aarch32-neon-cortex-a53.S", |
| "src/f32-gemm/gen/f32-gemm-4x8-minmax-asm-aarch32-neon-cortex-a55.S", |
| "src/f32-gemm/gen/f32-gemm-4x8-minmax-asm-aarch32-neon-cortex-a75-prfm.S", |
| "src/f32-gemm/gen/f32-gemm-4x8-minmax-asm-aarch32-neon-cortex-a75.S", |
| "src/f32-gemm/gen/f32-gemm-4x8-minmax-asm-aarch32-neon-ld64.S", |
| "src/f32-igemm/f32-igemm-4x8-minmax-asm-aarch32-neon-cortex-a55.S", |
| "src/f32-igemm/gen/f32-igemm-1x8-minmax-asm-aarch32-neon-cortex-a53-prfm.S", |
| "src/f32-igemm/gen/f32-igemm-1x8-minmax-asm-aarch32-neon-cortex-a53.S", |
| "src/f32-igemm/gen/f32-igemm-4x8-minmax-asm-aarch32-neon-cortex-a7.S", |
| "src/f32-igemm/gen/f32-igemm-4x8-minmax-asm-aarch32-neon-cortex-a53-prfm.S", |
| "src/f32-igemm/gen/f32-igemm-4x8-minmax-asm-aarch32-neon-cortex-a53.S", |
| "src/f32-igemm/gen/f32-igemm-4x8-minmax-asm-aarch32-neon-cortex-a75-prfm.S", |
| "src/f32-igemm/gen/f32-igemm-4x8-minmax-asm-aarch32-neon-cortex-a75.S", |
| "src/f32-igemm/gen/f32-igemm-4x8-minmax-asm-aarch32-neon-ld64.S", |
| "src/qd8-f32-qc8w-gemm/gen/qd8-f32-qc8w-gemm-4x8c4-minmax-asm-aarch32-neondot-cortex-a55.S", |
| "src/qs8-gemm/gen/qs8-gemm-1x8-minmax-rndnu-asm-aarch32-neon-mlal-lane-cortex-a7-prfm.S", |
| "src/qs8-gemm/gen/qs8-gemm-1x8-minmax-rndnu-asm-aarch32-neon-mlal-lane-cortex-a7.S", |
| "src/qs8-gemm/gen/qs8-gemm-4x8-minmax-rndnu-asm-aarch32-neon-mlal-lane-cortex-a7-prfm.S", |
| "src/qs8-gemm/gen/qs8-gemm-4x8-minmax-rndnu-asm-aarch32-neon-mlal-lane-cortex-a7.S", |
| "src/qs8-gemm/gen/qs8-gemm-4x8-minmax-rndnu-asm-aarch32-neon-mlal-lane-cortex-a53-prfm.S", |
| "src/qs8-gemm/gen/qs8-gemm-4x8-minmax-rndnu-asm-aarch32-neon-mlal-lane-cortex-a53.S", |
| "src/qs8-gemm/gen/qs8-gemm-4x8-minmax-rndnu-asm-aarch32-neon-mlal-lane-ld64-prfm.S", |
| "src/qs8-gemm/gen/qs8-gemm-4x8-minmax-rndnu-asm-aarch32-neon-mlal-lane-ld64.S", |
| "src/qs8-gemm/gen/qs8-gemm-4x8c4-minmax-rndnu-asm-aarch32-neondot-cortex-a55.S", |
| "src/qs8-gemm/gen/qs8-gemm-4x8c4-minmax-rndnu-asm-aarch32-neondot-ld64.S", |
| "src/qs8-igemm/gen/qs8-igemm-1x8-minmax-rndnu-asm-aarch32-neon-mlal-lane-cortex-a7-prfm.S", |
| "src/qs8-igemm/gen/qs8-igemm-1x8-minmax-rndnu-asm-aarch32-neon-mlal-lane-cortex-a7.S", |
| "src/qs8-igemm/gen/qs8-igemm-4x8-minmax-rndnu-asm-aarch32-neon-mlal-lane-cortex-a7-prfm.S", |
| "src/qs8-igemm/gen/qs8-igemm-4x8-minmax-rndnu-asm-aarch32-neon-mlal-lane-cortex-a7.S", |
| "src/qs8-igemm/gen/qs8-igemm-4x8-minmax-rndnu-asm-aarch32-neon-mlal-lane-cortex-a53-prfm.S", |
| "src/qs8-igemm/gen/qs8-igemm-4x8-minmax-rndnu-asm-aarch32-neon-mlal-lane-cortex-a53.S", |
| "src/qs8-igemm/gen/qs8-igemm-4x8-minmax-rndnu-asm-aarch32-neon-mlal-lane-ld64-prfm.S", |
| "src/qs8-igemm/gen/qs8-igemm-4x8-minmax-rndnu-asm-aarch32-neon-mlal-lane-ld64.S", |
| "src/qs8-igemm/gen/qs8-igemm-4x8c4-minmax-rndnu-asm-aarch32-neondot-cortex-a55.S", |
| "src/qs8-igemm/gen/qs8-igemm-4x8c4-minmax-rndnu-asm-aarch32-neondot-ld64.S", |
| "src/qs8-qc8w-dwconv/qs8-qc8w-dwconv-3p8c-minmax-fp32-asm-aarch32-neonv8-mla8-cortex-a35.S", |
| "src/qs8-qc8w-dwconv/qs8-qc8w-dwconv-3p16c-minmax-fp32-asm-aarch32-neonv8-mla8-cortex-a35.S", |
| "src/qs8-qc8w-gemm/gen/qs8-qc8w-gemm-1x8-minmax-fp32-asm-aarch32-neon-mlal-lane-cortex-a7-prfm.S", |
| "src/qs8-qc8w-gemm/gen/qs8-qc8w-gemm-1x8-minmax-fp32-asm-aarch32-neon-mlal-lane-cortex-a7.S", |
| "src/qs8-qc8w-gemm/gen/qs8-qc8w-gemm-1x8-minmax-fp32-asm-aarch32-neonv8-mlal-lane-cortex-a35-prfm.S", |
| "src/qs8-qc8w-gemm/gen/qs8-qc8w-gemm-1x8-minmax-fp32-asm-aarch32-neonv8-mlal-lane-cortex-a35.S", |
| "src/qs8-qc8w-gemm/gen/qs8-qc8w-gemm-4x8-minmax-fp32-asm-aarch32-neon-mlal-lane-cortex-a7-prfm.S", |
| "src/qs8-qc8w-gemm/gen/qs8-qc8w-gemm-4x8-minmax-fp32-asm-aarch32-neon-mlal-lane-cortex-a7.S", |
| "src/qs8-qc8w-gemm/gen/qs8-qc8w-gemm-4x8-minmax-fp32-asm-aarch32-neon-mlal-lane-cortex-a53-prfm.S", |
| "src/qs8-qc8w-gemm/gen/qs8-qc8w-gemm-4x8-minmax-fp32-asm-aarch32-neon-mlal-lane-cortex-a53.S", |
| "src/qs8-qc8w-gemm/gen/qs8-qc8w-gemm-4x8-minmax-fp32-asm-aarch32-neon-mlal-lane-ld64-prfm.S", |
| "src/qs8-qc8w-gemm/gen/qs8-qc8w-gemm-4x8-minmax-fp32-asm-aarch32-neon-mlal-lane-ld64.S", |
| "src/qs8-qc8w-gemm/gen/qs8-qc8w-gemm-4x8-minmax-fp32-asm-aarch32-neonv8-mlal-lane-cortex-a35-prfm.S", |
| "src/qs8-qc8w-gemm/gen/qs8-qc8w-gemm-4x8-minmax-fp32-asm-aarch32-neonv8-mlal-lane-cortex-a35.S", |
| "src/qs8-qc8w-gemm/gen/qs8-qc8w-gemm-4x8-minmax-fp32-asm-aarch32-neonv8-mlal-lane-cortex-a53-prfm.S", |
| "src/qs8-qc8w-gemm/gen/qs8-qc8w-gemm-4x8-minmax-fp32-asm-aarch32-neonv8-mlal-lane-cortex-a53.S", |
| "src/qs8-qc8w-gemm/gen/qs8-qc8w-gemm-4x8-minmax-fp32-asm-aarch32-neonv8-mlal-lane-ld64-prfm.S", |
| "src/qs8-qc8w-gemm/gen/qs8-qc8w-gemm-4x8-minmax-fp32-asm-aarch32-neonv8-mlal-lane-ld64.S", |
| "src/qs8-qc8w-gemm/gen/qs8-qc8w-gemm-4x8c4-minmax-fp32-asm-aarch32-neondot-cortex-a55.S", |
| "src/qs8-qc8w-gemm/gen/qs8-qc8w-gemm-4x8c4-minmax-fp32-asm-aarch32-neondot-ld64.S", |
| "src/qs8-qc8w-igemm/gen/qs8-qc8w-igemm-1x8-minmax-fp32-asm-aarch32-neon-mlal-lane-cortex-a7-prfm.S", |
| "src/qs8-qc8w-igemm/gen/qs8-qc8w-igemm-1x8-minmax-fp32-asm-aarch32-neon-mlal-lane-cortex-a7.S", |
| "src/qs8-qc8w-igemm/gen/qs8-qc8w-igemm-1x8-minmax-fp32-asm-aarch32-neonv8-mlal-lane-cortex-a35-prfm.S", |
| "src/qs8-qc8w-igemm/gen/qs8-qc8w-igemm-1x8-minmax-fp32-asm-aarch32-neonv8-mlal-lane-cortex-a35.S", |
| "src/qs8-qc8w-igemm/gen/qs8-qc8w-igemm-4x8-minmax-fp32-asm-aarch32-neon-mlal-lane-cortex-a7-prfm.S", |
| "src/qs8-qc8w-igemm/gen/qs8-qc8w-igemm-4x8-minmax-fp32-asm-aarch32-neon-mlal-lane-cortex-a7.S", |
| "src/qs8-qc8w-igemm/gen/qs8-qc8w-igemm-4x8-minmax-fp32-asm-aarch32-neon-mlal-lane-cortex-a53-prfm.S", |
| "src/qs8-qc8w-igemm/gen/qs8-qc8w-igemm-4x8-minmax-fp32-asm-aarch32-neon-mlal-lane-cortex-a53.S", |
| "src/qs8-qc8w-igemm/gen/qs8-qc8w-igemm-4x8-minmax-fp32-asm-aarch32-neon-mlal-lane-ld64-prfm.S", |
| "src/qs8-qc8w-igemm/gen/qs8-qc8w-igemm-4x8-minmax-fp32-asm-aarch32-neon-mlal-lane-ld64.S", |
| "src/qs8-qc8w-igemm/gen/qs8-qc8w-igemm-4x8-minmax-fp32-asm-aarch32-neonv8-mlal-lane-cortex-a35-prfm.S", |
| "src/qs8-qc8w-igemm/gen/qs8-qc8w-igemm-4x8-minmax-fp32-asm-aarch32-neonv8-mlal-lane-cortex-a35.S", |
| "src/qs8-qc8w-igemm/gen/qs8-qc8w-igemm-4x8-minmax-fp32-asm-aarch32-neonv8-mlal-lane-cortex-a53-prfm.S", |
| "src/qs8-qc8w-igemm/gen/qs8-qc8w-igemm-4x8-minmax-fp32-asm-aarch32-neonv8-mlal-lane-cortex-a53.S", |
| "src/qs8-qc8w-igemm/gen/qs8-qc8w-igemm-4x8-minmax-fp32-asm-aarch32-neonv8-mlal-lane-ld64-prfm.S", |
| "src/qs8-qc8w-igemm/gen/qs8-qc8w-igemm-4x8-minmax-fp32-asm-aarch32-neonv8-mlal-lane-ld64.S", |
| "src/qs8-qc8w-igemm/gen/qs8-qc8w-igemm-4x8c4-minmax-fp32-asm-aarch32-neondot-cortex-a55.S", |
| "src/qs8-qc8w-igemm/gen/qs8-qc8w-igemm-4x8c4-minmax-fp32-asm-aarch32-neondot-ld64.S", |
| "src/qs16-qs8-vcvt/qs16-qs8-vcvt-asm-aarch32-neon-u16.S", |
| "src/qu8-gemm/gen/qu8-gemm-1x8-minmax-rndnu-asm-aarch32-neon-mlal-lane-cortex-a7-prfm.S", |
| "src/qu8-gemm/gen/qu8-gemm-1x8-minmax-rndnu-asm-aarch32-neon-mlal-lane-cortex-a7.S", |
| "src/qu8-gemm/gen/qu8-gemm-4x8-minmax-rndnu-asm-aarch32-neon-mlal-lane-cortex-a7-prfm.S", |
| "src/qu8-gemm/gen/qu8-gemm-4x8-minmax-rndnu-asm-aarch32-neon-mlal-lane-cortex-a7.S", |
| "src/qu8-gemm/gen/qu8-gemm-4x8-minmax-rndnu-asm-aarch32-neon-mlal-lane-cortex-a53-prfm.S", |
| "src/qu8-gemm/gen/qu8-gemm-4x8-minmax-rndnu-asm-aarch32-neon-mlal-lane-cortex-a53.S", |
| "src/qu8-gemm/gen/qu8-gemm-4x8-minmax-rndnu-asm-aarch32-neon-mlal-lane-ld64-prfm.S", |
| "src/qu8-gemm/gen/qu8-gemm-4x8-minmax-rndnu-asm-aarch32-neon-mlal-lane-ld64.S", |
| "src/qu8-igemm/gen/qu8-igemm-1x8-minmax-rndnu-asm-aarch32-neon-mlal-lane-cortex-a7-prfm.S", |
| "src/qu8-igemm/gen/qu8-igemm-1x8-minmax-rndnu-asm-aarch32-neon-mlal-lane-cortex-a7.S", |
| "src/qu8-igemm/gen/qu8-igemm-4x8-minmax-rndnu-asm-aarch32-neon-mlal-lane-cortex-a7-prfm.S", |
| "src/qu8-igemm/gen/qu8-igemm-4x8-minmax-rndnu-asm-aarch32-neon-mlal-lane-cortex-a7.S", |
| "src/qu8-igemm/gen/qu8-igemm-4x8-minmax-rndnu-asm-aarch32-neon-mlal-lane-cortex-a53-prfm.S", |
| "src/qu8-igemm/gen/qu8-igemm-4x8-minmax-rndnu-asm-aarch32-neon-mlal-lane-cortex-a53.S", |
| "src/qu8-igemm/gen/qu8-igemm-4x8-minmax-rndnu-asm-aarch32-neon-mlal-lane-ld64-prfm.S", |
| "src/qu8-igemm/gen/qu8-igemm-4x8-minmax-rndnu-asm-aarch32-neon-mlal-lane-ld64.S", |
| "src/u32-filterbank-accumulate/u32-filterbank-accumulate-asm-aarch32-arm-x1.S", |
| "src/u32-filterbank-accumulate/u32-filterbank-accumulate-asm-aarch32-neon-x1.S", |
| "src/u32-filterbank-accumulate/u32-filterbank-accumulate-asm-aarch32-neon-x2.S", |
| ] |
| |
| AARCH64_ASM_MICROKERNEL_SRCS = [ |
| "src/f16-gemm/gen/f16-gemm-1x8-minmax-asm-aarch64-neonfp16arith-ld64.S", |
| "src/f16-gemm/gen/f16-gemm-1x16-minmax-asm-aarch64-neonfp16arith-ld32.S", |
| "src/f16-gemm/gen/f16-gemm-1x16-minmax-asm-aarch64-neonfp16arith-ld64.S", |
| "src/f16-gemm/gen/f16-gemm-4x8-minmax-asm-aarch64-neonfp16arith-ld64.S", |
| "src/f16-gemm/gen/f16-gemm-4x16-minmax-asm-aarch64-neonfp16arith-ld32.S", |
| "src/f16-gemm/gen/f16-gemm-4x16-minmax-asm-aarch64-neonfp16arith-ld64.S", |
| "src/f16-gemm/gen/f16-gemm-6x8-minmax-asm-aarch64-neonfp16arith-ld64.S", |
| "src/f16-gemm/gen/f16-gemm-6x16-minmax-asm-aarch64-neonfp16arith-cortex-a55.S", |
| "src/f16-gemm/gen/f16-gemm-6x16-minmax-asm-aarch64-neonfp16arith-cortex-a55r0.S", |
| "src/f16-gemm/gen/f16-gemm-6x16-minmax-asm-aarch64-neonfp16arith-cortex-a75.S", |
| "src/f16-gemm/gen/f16-gemm-6x16-minmax-asm-aarch64-neonfp16arith-ld32.S", |
| "src/f16-gemm/gen/f16-gemm-6x16-minmax-asm-aarch64-neonfp16arith-ld64.S", |
| "src/f16-gemm/gen/f16-gemm-8x8-minmax-asm-aarch64-neonfp16arith-ld64.S", |
| "src/f16-gemm/gen/f16-gemminc-1x8-minmax-asm-aarch64-neonfp16arith-ld64.S", |
| "src/f16-gemm/gen/f16-gemminc-1x16-minmax-asm-aarch64-neonfp16arith-ld32.S", |
| "src/f16-gemm/gen/f16-gemminc-4x8-minmax-asm-aarch64-neonfp16arith-ld64.S", |
| "src/f16-gemm/gen/f16-gemminc-4x16-minmax-asm-aarch64-neonfp16arith-ld32.S", |
| "src/f16-gemm/gen/f16-gemminc-6x8-minmax-asm-aarch64-neonfp16arith-ld64.S", |
| "src/f16-gemm/gen/f16-gemminc-6x16-minmax-asm-aarch64-neonfp16arith-cortex-a55.S", |
| "src/f16-gemm/gen/f16-gemminc-6x16-minmax-asm-aarch64-neonfp16arith-cortex-a75.S", |
| "src/f16-gemm/gen/f16-gemminc-6x16-minmax-asm-aarch64-neonfp16arith-ld32.S", |
| "src/f16-gemm/gen/f16-gemminc-8x8-minmax-asm-aarch64-neonfp16arith-ld64.S", |
| "src/f16-igemm/f16-igemm-1x16-minmax-asm-aarch64-neonfp16arith-ld32.S", |
| "src/f16-igemm/f16-igemm-1x16-minmax-asm-aarch64-neonfp16arith-ld64.S", |
| "src/f16-igemm/f16-igemm-4x16-minmax-asm-aarch64-neonfp16arith-ld32.S", |
| "src/f16-igemm/f16-igemm-4x16-minmax-asm-aarch64-neonfp16arith-ld64.S", |
| "src/f16-igemm/f16-igemm-6x16-minmax-asm-aarch64-neonfp16arith-cortex-a55.S", |
| "src/f16-igemm/f16-igemm-6x16-minmax-asm-aarch64-neonfp16arith-cortex-a55r0.S", |
| "src/f16-igemm/f16-igemm-6x16-minmax-asm-aarch64-neonfp16arith-cortex-a75.S", |
| "src/f16-igemm/f16-igemm-6x16-minmax-asm-aarch64-neonfp16arith-ld32.S", |
| "src/f16-igemm/f16-igemm-6x16-minmax-asm-aarch64-neonfp16arith-ld64.S", |
| "src/f32-dwconv/f32-dwconv-9p4c-minmax-asm-aarch64-neonfma-cortex-a55.S", |
| "src/f32-dwconv/f32-dwconv-9p4c-minmax-asm-aarch64-neonfma.S", |
| "src/f32-gemm/gen/f32-gemm-1x8-minmax-asm-aarch64-neon-ld128-acc2-prfm.S", |
| "src/f32-gemm/gen/f32-gemm-1x8-minmax-asm-aarch64-neon-ld128-acc2.S", |
| "src/f32-gemm/gen/f32-gemm-1x8-minmax-asm-aarch64-neonfma-cortex-a53-prfm.S", |
| "src/f32-gemm/gen/f32-gemm-1x8-minmax-asm-aarch64-neonfma-cortex-a53.S", |
| "src/f32-gemm/gen/f32-gemm-1x8-minmax-asm-aarch64-neonfma-cortex-a75-prfm.S", |
| "src/f32-gemm/gen/f32-gemm-1x8-minmax-asm-aarch64-neonfma-cortex-a75.S", |
| "src/f32-gemm/gen/f32-gemm-1x8-minmax-asm-aarch64-neonfma-ld64-acc2-prfm.S", |
| "src/f32-gemm/gen/f32-gemm-1x8-minmax-asm-aarch64-neonfma-ld64-acc2.S", |
| "src/f32-gemm/gen/f32-gemm-1x8-minmax-asm-aarch64-neonfma-ld64-acc4-prfm.S", |
| "src/f32-gemm/gen/f32-gemm-1x8-minmax-asm-aarch64-neonfma-ld64-acc4.S", |
| "src/f32-gemm/gen/f32-gemm-1x8-minmax-asm-aarch64-neonfma-ld64-prfm.S", |
| "src/f32-gemm/gen/f32-gemm-1x8-minmax-asm-aarch64-neonfma-ld64.S", |
| "src/f32-gemm/gen/f32-gemm-1x8-minmax-asm-aarch64-neonfma-ld128-acc2-prfm.S", |
| "src/f32-gemm/gen/f32-gemm-1x8-minmax-asm-aarch64-neonfma-ld128-acc2.S", |
| "src/f32-gemm/gen/f32-gemm-1x8-minmax-asm-aarch64-neonfma-ld128-acc4-prfm.S", |
| "src/f32-gemm/gen/f32-gemm-1x8-minmax-asm-aarch64-neonfma-ld128-acc4.S", |
| "src/f32-gemm/gen/f32-gemm-1x8-minmax-asm-aarch64-neonfma-ld128-prfm.S", |
| "src/f32-gemm/gen/f32-gemm-1x8-minmax-asm-aarch64-neonfma-ld128.S", |
| "src/f32-gemm/gen/f32-gemm-1x12-minmax-asm-aarch64-neonfma-cortex-a53.S", |
| "src/f32-gemm/gen/f32-gemm-4x1-minmax-asm-aarch64-neonfma-ld64.S", |
| "src/f32-gemm/gen/f32-gemm-4x1-minmax-asm-aarch64-neonfma-ld128.S", |
| "src/f32-gemm/gen/f32-gemm-4x2-minmax-asm-aarch64-neonfma-cortex-a75-prfm.S", |
| "src/f32-gemm/gen/f32-gemm-4x2-minmax-asm-aarch64-neonfma-cortex-a75.S", |
| "src/f32-gemm/gen/f32-gemm-4x2-minmax-asm-aarch64-neonfma-ld64.S", |
| "src/f32-gemm/gen/f32-gemm-4x2-minmax-asm-aarch64-neonfma-ld128.S", |
| "src/f32-gemm/gen/f32-gemm-4x8-minmax-asm-aarch64-neonfma-cortex-a53-prfm.S", |
| "src/f32-gemm/gen/f32-gemm-4x8-minmax-asm-aarch64-neonfma-cortex-a53.S", |
| "src/f32-gemm/gen/f32-gemm-4x8-minmax-asm-aarch64-neonfma-cortex-a55.S", |
| "src/f32-gemm/gen/f32-gemm-4x8-minmax-asm-aarch64-neonfma-cortex-a75-prfm.S", |
| "src/f32-gemm/gen/f32-gemm-4x8-minmax-asm-aarch64-neonfma-cortex-a75.S", |
| "src/f32-gemm/gen/f32-gemm-4x8-minmax-asm-aarch64-neonfma-ld64.S", |
| "src/f32-gemm/gen/f32-gemm-4x8-minmax-asm-aarch64-neonfma-ld128.S", |
| "src/f32-gemm/gen/f32-gemm-4x12-minmax-asm-aarch64-neonfma-cortex-a53.S", |
| "src/f32-gemm/gen/f32-gemm-5x8-minmax-asm-aarch64-neonfma-cortex-a75-prfm.S", |
| "src/f32-gemm/gen/f32-gemm-5x8-minmax-asm-aarch64-neonfma-cortex-a75.S", |
| "src/f32-gemm/gen/f32-gemm-6x8-minmax-asm-aarch64-neonfma-cortex-a53-prfm.S", |
| "src/f32-gemm/gen/f32-gemm-6x8-minmax-asm-aarch64-neonfma-cortex-a53.S", |
| "src/f32-gemm/gen/f32-gemm-6x8-minmax-asm-aarch64-neonfma-cortex-a55.S", |
| "src/f32-gemm/gen/f32-gemm-6x8-minmax-asm-aarch64-neonfma-cortex-a73.S", |
| "src/f32-gemm/gen/f32-gemm-6x8-minmax-asm-aarch64-neonfma-cortex-a75-prfm.S", |
| "src/f32-gemm/gen/f32-gemm-6x8-minmax-asm-aarch64-neonfma-cortex-a75.S", |
| "src/f32-gemm/gen/f32-gemm-6x8-minmax-asm-aarch64-neonfma-ld64.S", |
| "src/f32-gemm/gen/f32-gemm-6x8-minmax-asm-aarch64-neonfma-ld128.S", |
| "src/f32-gemm/gen/f32-gemm-goi-1x8-minmax-asm-aarch64-neonfma-ld128-prfm.S", |
| "src/f32-gemm/gen/f32-gemm-goi-1x8-minmax-asm-aarch64-neonfma-ld128.S", |
| "src/f32-gemm/gen/f32-gemm-goi-4x8-minmax-asm-aarch64-neonfma-ld128.S", |
| "src/f32-gemminc/gen/f32-gemminc-1x8-minmax-asm-aarch64-neonfma-cortex-a53.S", |
| "src/f32-gemminc/gen/f32-gemminc-1x8-minmax-asm-aarch64-neonfma-cortex-a75-prfm.S", |
| "src/f32-gemminc/gen/f32-gemminc-1x8-minmax-asm-aarch64-neonfma-cortex-a75.S", |
| "src/f32-gemminc/gen/f32-gemminc-1x8-minmax-asm-aarch64-neonfma-ld64.S", |
| "src/f32-gemminc/gen/f32-gemminc-1x12-minmax-asm-aarch64-neonfma-cortex-a53.S", |
| "src/f32-gemminc/gen/f32-gemminc-4x8-minmax-asm-aarch64-neonfma-cortex-a53.S", |
| "src/f32-gemminc/gen/f32-gemminc-4x8-minmax-asm-aarch64-neonfma-cortex-a55.S", |
| "src/f32-gemminc/gen/f32-gemminc-4x8-minmax-asm-aarch64-neonfma-cortex-a75-prfm.S", |
| "src/f32-gemminc/gen/f32-gemminc-4x8-minmax-asm-aarch64-neonfma-cortex-a75.S", |
| "src/f32-gemminc/gen/f32-gemminc-4x8-minmax-asm-aarch64-neonfma-ld64.S", |
| "src/f32-gemminc/gen/f32-gemminc-4x8-minmax-asm-aarch64-neonfma-ld128.S", |
| "src/f32-gemminc/gen/f32-gemminc-4x12-minmax-asm-aarch64-neonfma-cortex-a53.S", |
| "src/f32-gemminc/gen/f32-gemminc-5x8-minmax-asm-aarch64-neonfma-cortex-a75-prfm.S", |
| "src/f32-gemminc/gen/f32-gemminc-5x8-minmax-asm-aarch64-neonfma-cortex-a75.S", |
| "src/f32-gemminc/gen/f32-gemminc-6x8-minmax-asm-aarch64-neonfma-cortex-a53.S", |
| "src/f32-gemminc/gen/f32-gemminc-6x8-minmax-asm-aarch64-neonfma-cortex-a55.S", |
| "src/f32-gemminc/gen/f32-gemminc-6x8-minmax-asm-aarch64-neonfma-cortex-a73.S", |
| "src/f32-gemminc/gen/f32-gemminc-6x8-minmax-asm-aarch64-neonfma-cortex-a75-prfm.S", |
| "src/f32-gemminc/gen/f32-gemminc-6x8-minmax-asm-aarch64-neonfma-cortex-a75.S", |
| "src/f32-gemminc/gen/f32-gemminc-6x8-minmax-asm-aarch64-neonfma-ld64.S", |
| "src/f32-gemminc/gen/f32-gemminc-6x8-minmax-asm-aarch64-neonfma-ld128.S", |
| "src/f32-igemm/f32-igemm-1x12-minmax-asm-aarch64-neonfma-cortex-a53.S", |
| "src/f32-igemm/f32-igemm-4x8-minmax-asm-aarch64-neonfma-cortex-a55.S", |
| "src/f32-igemm/f32-igemm-4x12-minmax-asm-aarch64-neonfma-cortex-a53.S", |
| "src/f32-igemm/f32-igemm-6x8-minmax-asm-aarch64-neonfma-cortex-a55.S", |
| "src/f32-igemm/f32-igemm-6x8-minmax-asm-aarch64-neonfma-cortex-a73.S", |
| "src/f32-igemm/gen/f32-igemm-1x8-minmax-asm-aarch64-neonfma-cortex-a53-prfm.S", |
| "src/f32-igemm/gen/f32-igemm-1x8-minmax-asm-aarch64-neonfma-cortex-a53.S", |
| "src/f32-igemm/gen/f32-igemm-1x8-minmax-asm-aarch64-neonfma-cortex-a75-prfm.S", |
| "src/f32-igemm/gen/f32-igemm-1x8-minmax-asm-aarch64-neonfma-cortex-a75.S", |
| "src/f32-igemm/gen/f32-igemm-1x8-minmax-asm-aarch64-neonfma-ld64-prfm.S", |
| "src/f32-igemm/gen/f32-igemm-1x8-minmax-asm-aarch64-neonfma-ld64.S", |
| "src/f32-igemm/gen/f32-igemm-4x2-minmax-asm-aarch64-neonfma-cortex-a75-prfm.S", |
| "src/f32-igemm/gen/f32-igemm-4x2-minmax-asm-aarch64-neonfma-cortex-a75.S", |
| "src/f32-igemm/gen/f32-igemm-4x2-minmax-asm-aarch64-neonfma-ld64.S", |
| "src/f32-igemm/gen/f32-igemm-4x8-minmax-asm-aarch64-neonfma-cortex-a53-prfm.S", |
| "src/f32-igemm/gen/f32-igemm-4x8-minmax-asm-aarch64-neonfma-cortex-a53.S", |
| "src/f32-igemm/gen/f32-igemm-4x8-minmax-asm-aarch64-neonfma-cortex-a75-prfm.S", |
| "src/f32-igemm/gen/f32-igemm-4x8-minmax-asm-aarch64-neonfma-cortex-a75.S", |
| "src/f32-igemm/gen/f32-igemm-4x8-minmax-asm-aarch64-neonfma-ld64.S", |
| "src/f32-igemm/gen/f32-igemm-4x8-minmax-asm-aarch64-neonfma-ld128.S", |
| "src/f32-igemm/gen/f32-igemm-5x8-minmax-asm-aarch64-neonfma-cortex-a75-prfm.S", |
| "src/f32-igemm/gen/f32-igemm-5x8-minmax-asm-aarch64-neonfma-cortex-a75.S", |
| "src/f32-igemm/gen/f32-igemm-6x8-minmax-asm-aarch64-neonfma-cortex-a53-prfm.S", |
| "src/f32-igemm/gen/f32-igemm-6x8-minmax-asm-aarch64-neonfma-cortex-a53.S", |
| "src/f32-igemm/gen/f32-igemm-6x8-minmax-asm-aarch64-neonfma-cortex-a75-prfm.S", |
| "src/f32-igemm/gen/f32-igemm-6x8-minmax-asm-aarch64-neonfma-cortex-a75.S", |
| "src/f32-igemm/gen/f32-igemm-6x8-minmax-asm-aarch64-neonfma-ld64.S", |
| "src/f32-igemm/gen/f32-igemm-6x8-minmax-asm-aarch64-neonfma-ld128.S", |
| "src/f32-ppmm/gen/f32-ppmm-4x8-minmax-asm-aarch64-neonfma-cortex-a75-prfm.S", |
| "src/f32-ppmm/gen/f32-ppmm-4x8-minmax-asm-aarch64-neonfma-cortex-a75.S", |
| "src/f32-ppmm/gen/f32-ppmm-4x8-minmax-asm-aarch64-neonfma-ld128-prfm.S", |
| "src/f32-ppmm/gen/f32-ppmm-4x8-minmax-asm-aarch64-neonfma-ld128.S", |
| "src/f32-ppmm/gen/f32-ppmm-8x8-minmax-asm-aarch64-neonfma-cortex-a75-prfm.S", |
| "src/f32-ppmm/gen/f32-ppmm-8x8-minmax-asm-aarch64-neonfma-cortex-a75.S", |
| "src/f32-ppmm/gen/f32-ppmm-8x8-minmax-asm-aarch64-neonfma-ld128-prfm.S", |
| "src/f32-ppmm/gen/f32-ppmm-8x8-minmax-asm-aarch64-neonfma-ld128.S", |
| "src/f32-qc4w-gemm/gen/f32-qc4w-gemm-1x8-minmax-asm-aarch64-neon-ld128-acc2-prfm.S", |
| "src/f32-qc4w-gemm/gen/f32-qc4w-gemm-1x8-minmax-asm-aarch64-neon-ld128-acc2.S", |
| "src/f32-qc4w-gemm/gen/f32-qc4w-gemm-1x8-minmax-asm-aarch64-neonfma-ld64-acc2-prfm.S", |
| "src/f32-qc4w-gemm/gen/f32-qc4w-gemm-1x8-minmax-asm-aarch64-neonfma-ld64-acc2.S", |
| "src/f32-qc4w-gemm/gen/f32-qc4w-gemm-1x8-minmax-asm-aarch64-neonfma-ld64-acc4-prfm.S", |
| "src/f32-qc4w-gemm/gen/f32-qc4w-gemm-1x8-minmax-asm-aarch64-neonfma-ld64-acc4.S", |
| "src/f32-qc4w-gemm/gen/f32-qc4w-gemm-1x8-minmax-asm-aarch64-neonfma-ld64-prfm.S", |
| "src/f32-qc4w-gemm/gen/f32-qc4w-gemm-1x8-minmax-asm-aarch64-neonfma-ld64.S", |
| "src/f32-qc4w-gemm/gen/f32-qc4w-gemm-1x8-minmax-asm-aarch64-neonfma-ld128-acc2-prfm.S", |
| "src/f32-qc4w-gemm/gen/f32-qc4w-gemm-1x8-minmax-asm-aarch64-neonfma-ld128-acc2.S", |
| "src/f32-qc4w-gemm/gen/f32-qc4w-gemm-1x8-minmax-asm-aarch64-neonfma-ld128-acc4-prfm.S", |
| "src/f32-qc4w-gemm/gen/f32-qc4w-gemm-1x8-minmax-asm-aarch64-neonfma-ld128-acc4.S", |
| "src/f32-qc4w-gemm/gen/f32-qc4w-gemm-1x8-minmax-asm-aarch64-neonfma-ld128-prfm.S", |
| "src/f32-qc4w-gemm/gen/f32-qc4w-gemm-1x8-minmax-asm-aarch64-neonfma-ld128.S", |
| "src/f32-qc4w-gemm/gen/f32-qc4w-gemm-4x1-minmax-asm-aarch64-neonfma-ld64.S", |
| "src/f32-qc4w-gemm/gen/f32-qc4w-gemm-4x1-minmax-asm-aarch64-neonfma-ld128.S", |
| "src/f32-qc4w-gemm/gen/f32-qc4w-gemm-4x2-minmax-asm-aarch64-neonfma-ld64.S", |
| "src/f32-qc4w-gemm/gen/f32-qc4w-gemm-4x2-minmax-asm-aarch64-neonfma-ld128.S", |
| "src/f32-qc4w-gemm/gen/f32-qc4w-gemm-4x8-minmax-asm-aarch64-neonfma-ld64.S", |
| "src/f32-qc4w-gemm/gen/f32-qc4w-gemm-4x8-minmax-asm-aarch64-neonfma-ld128.S", |
| "src/f32-qc4w-gemm/gen/f32-qc4w-gemm-6x8-minmax-asm-aarch64-neonfma-ld64.S", |
| "src/f32-qc4w-gemm/gen/f32-qc4w-gemm-6x8-minmax-asm-aarch64-neonfma-ld128.S", |
| "src/f32-qc8w-gemm/gen/f32-qc8w-gemm-1x8-minmax-asm-aarch64-neon-ld128-acc2-prfm.S", |
| "src/f32-qc8w-gemm/gen/f32-qc8w-gemm-1x8-minmax-asm-aarch64-neon-ld128-acc2.S", |
| "src/f32-qc8w-gemm/gen/f32-qc8w-gemm-1x8-minmax-asm-aarch64-neonfma-ld64-acc2-prfm.S", |
| "src/f32-qc8w-gemm/gen/f32-qc8w-gemm-1x8-minmax-asm-aarch64-neonfma-ld64-acc2.S", |
| "src/f32-qc8w-gemm/gen/f32-qc8w-gemm-1x8-minmax-asm-aarch64-neonfma-ld64-acc4-prfm.S", |
| "src/f32-qc8w-gemm/gen/f32-qc8w-gemm-1x8-minmax-asm-aarch64-neonfma-ld64-acc4.S", |
| "src/f32-qc8w-gemm/gen/f32-qc8w-gemm-1x8-minmax-asm-aarch64-neonfma-ld64-prfm.S", |
| "src/f32-qc8w-gemm/gen/f32-qc8w-gemm-1x8-minmax-asm-aarch64-neonfma-ld64.S", |
| "src/f32-qc8w-gemm/gen/f32-qc8w-gemm-1x8-minmax-asm-aarch64-neonfma-ld128-acc2-prfm.S", |
| "src/f32-qc8w-gemm/gen/f32-qc8w-gemm-1x8-minmax-asm-aarch64-neonfma-ld128-acc2.S", |
| "src/f32-qc8w-gemm/gen/f32-qc8w-gemm-1x8-minmax-asm-aarch64-neonfma-ld128-acc4-prfm.S", |
| "src/f32-qc8w-gemm/gen/f32-qc8w-gemm-1x8-minmax-asm-aarch64-neonfma-ld128-acc4.S", |
| "src/f32-qc8w-gemm/gen/f32-qc8w-gemm-1x8-minmax-asm-aarch64-neonfma-ld128-prfm.S", |
| "src/f32-qc8w-gemm/gen/f32-qc8w-gemm-1x8-minmax-asm-aarch64-neonfma-ld128.S", |
| "src/f32-qc8w-gemm/gen/f32-qc8w-gemm-4x1-minmax-asm-aarch64-neonfma-ld64.S", |
| "src/f32-qc8w-gemm/gen/f32-qc8w-gemm-4x1-minmax-asm-aarch64-neonfma-ld128.S", |
| "src/f32-qc8w-gemm/gen/f32-qc8w-gemm-4x2-minmax-asm-aarch64-neonfma-ld64.S", |
| "src/f32-qc8w-gemm/gen/f32-qc8w-gemm-4x2-minmax-asm-aarch64-neonfma-ld128.S", |
| "src/f32-qc8w-gemm/gen/f32-qc8w-gemm-4x8-minmax-asm-aarch64-neonfma-ld64.S", |
| "src/f32-qc8w-gemm/gen/f32-qc8w-gemm-4x8-minmax-asm-aarch64-neonfma-ld128.S", |
| "src/f32-qc8w-gemm/gen/f32-qc8w-gemm-6x8-minmax-asm-aarch64-neonfma-ld64.S", |
| "src/f32-qc8w-gemm/gen/f32-qc8w-gemm-6x8-minmax-asm-aarch64-neonfma-ld128.S", |
| "src/qd8-f32-qc8w-gemm/gen/qd8-f32-qc8w-gemm-4x16c4-minmax-asm-aarch64-neondot-cortex-a55.S", |
| "src/qd8-f32-qc8w-gemm/gen/qd8-f32-qc8w-gemm-4x16c4-minmax-asm-aarch64-neondot-ld64.S", |
| "src/qd8-f32-qc8w-gemm/gen/qd8-f32-qc8w-gemm-4x16c4-minmax-asm-aarch64-neondot-ld128.S", |
| "src/qs8-gemm/gen/qs8-gemm-1x8c8-minmax-fp32-asm-aarch64-neon-mlal-cortex-a53-prfm.S", |
| "src/qs8-gemm/gen/qs8-gemm-1x8c8-minmax-fp32-asm-aarch64-neon-mlal-cortex-a53.S", |
| "src/qs8-gemm/gen/qs8-gemm-1x8c8-minmax-fp32-asm-aarch64-neon-mlal-prfm.S", |
| "src/qs8-gemm/gen/qs8-gemm-1x8c8-minmax-fp32-asm-aarch64-neon-mlal.S", |
| "src/qs8-gemm/gen/qs8-gemm-1x8c8-minmax-rndnu-asm-aarch64-neon-mlal-cortex-a53-prfm.S", |
| "src/qs8-gemm/gen/qs8-gemm-1x8c8-minmax-rndnu-asm-aarch64-neon-mlal-cortex-a53.S", |
| "src/qs8-gemm/gen/qs8-gemm-1x8c8-minmax-rndnu-asm-aarch64-neon-mlal-prfm.S", |
| "src/qs8-gemm/gen/qs8-gemm-1x8c8-minmax-rndnu-asm-aarch64-neon-mlal.S", |
| "src/qs8-gemm/gen/qs8-gemm-1x16c4-minmax-fp32-asm-aarch64-neondot-ld32.S", |
| "src/qs8-gemm/gen/qs8-gemm-1x16c4-minmax-fp32-asm-aarch64-neondot-ld64.S", |
| "src/qs8-gemm/gen/qs8-gemm-1x16c4-minmax-rndnu-asm-aarch64-neondot-ld32.S", |
| "src/qs8-gemm/gen/qs8-gemm-1x16c4-minmax-rndnu-asm-aarch64-neondot-ld64.S", |
| "src/qs8-gemm/gen/qs8-gemm-2x8c8-minmax-fp32-asm-aarch64-neon-mlal-cortex-a53-prfm.S", |
| "src/qs8-gemm/gen/qs8-gemm-2x8c8-minmax-fp32-asm-aarch64-neon-mlal-cortex-a53.S", |
| "src/qs8-gemm/gen/qs8-gemm-2x8c8-minmax-fp32-asm-aarch64-neon-mlal-prfm.S", |
| "src/qs8-gemm/gen/qs8-gemm-2x8c8-minmax-fp32-asm-aarch64-neon-mlal.S", |
| "src/qs8-gemm/gen/qs8-gemm-2x8c8-minmax-fp32-asm-aarch64-neon-mull.S", |
| "src/qs8-gemm/gen/qs8-gemm-2x8c8-minmax-rndnu-asm-aarch64-neon-mlal-cortex-a53-prfm.S", |
| "src/qs8-gemm/gen/qs8-gemm-2x8c8-minmax-rndnu-asm-aarch64-neon-mlal-cortex-a53.S", |
| "src/qs8-gemm/gen/qs8-gemm-2x8c8-minmax-rndnu-asm-aarch64-neon-mlal-prfm.S", |
| "src/qs8-gemm/gen/qs8-gemm-2x8c8-minmax-rndnu-asm-aarch64-neon-mlal.S", |
| "src/qs8-gemm/gen/qs8-gemm-2x8c8-minmax-rndnu-asm-aarch64-neon-mull.S", |
| "src/qs8-gemm/gen/qs8-gemm-2x8c16-minmax-fp32-asm-aarch64-neon-mlal.S", |
| "src/qs8-gemm/gen/qs8-gemm-2x8c16-minmax-rndnu-asm-aarch64-neon-mlal.S", |
| "src/qs8-gemm/gen/qs8-gemm-4x8-minmax-rndnu-asm-aarch64-neon-mlal-lane-ld64-prfm.S", |
| "src/qs8-gemm/gen/qs8-gemm-4x8-minmax-rndnu-asm-aarch64-neon-mlal-lane-ld64.S", |
| "src/qs8-gemm/gen/qs8-gemm-4x16-minmax-fp32-asm-aarch64-neon-mlal-lane-cortex-a53-prfm.S", |
| "src/qs8-gemm/gen/qs8-gemm-4x16-minmax-fp32-asm-aarch64-neon-mlal-lane-cortex-a53.S", |
| "src/qs8-gemm/gen/qs8-gemm-4x16-minmax-fp32-asm-aarch64-neon-mlal-lane-ld64-prfm.S", |
| "src/qs8-gemm/gen/qs8-gemm-4x16-minmax-fp32-asm-aarch64-neon-mlal-lane-ld64.S", |
| "src/qs8-gemm/gen/qs8-gemm-4x16-minmax-rndnu-asm-aarch64-neon-mlal-lane-cortex-a53-prfm.S", |
| "src/qs8-gemm/gen/qs8-gemm-4x16-minmax-rndnu-asm-aarch64-neon-mlal-lane-cortex-a53.S", |
| "src/qs8-gemm/gen/qs8-gemm-4x16-minmax-rndnu-asm-aarch64-neon-mlal-lane-ld64-prfm.S", |
| "src/qs8-gemm/gen/qs8-gemm-4x16-minmax-rndnu-asm-aarch64-neon-mlal-lane-ld64.S", |
| "src/qs8-gemm/gen/qs8-gemm-4x16c4-minmax-fp32-asm-aarch64-neondot-cortex-a55.S", |
| "src/qs8-gemm/gen/qs8-gemm-4x16c4-minmax-fp32-asm-aarch64-neondot-ld32.S", |
| "src/qs8-gemm/gen/qs8-gemm-4x16c4-minmax-fp32-asm-aarch64-neondot-ld64.S", |
| "src/qs8-gemm/gen/qs8-gemm-4x16c4-minmax-fp32-asm-aarch64-neondot-ld128.S", |
| "src/qs8-gemm/gen/qs8-gemm-4x16c4-minmax-rndnu-asm-aarch64-neondot-cortex-a55.S", |
| "src/qs8-gemm/gen/qs8-gemm-4x16c4-minmax-rndnu-asm-aarch64-neondot-ld32.S", |
| "src/qs8-gemm/gen/qs8-gemm-4x16c4-minmax-rndnu-asm-aarch64-neondot-ld64.S", |
| "src/qs8-gemm/gen/qs8-gemm-4x16c4-minmax-rndnu-asm-aarch64-neondot-ld128.S", |
| "src/qs8-igemm/gen/qs8-igemm-1x8c8-minmax-fp32-asm-aarch64-neon-mlal-cortex-a53-prfm.S", |
| "src/qs8-igemm/gen/qs8-igemm-1x8c8-minmax-fp32-asm-aarch64-neon-mlal-cortex-a53.S", |
| "src/qs8-igemm/gen/qs8-igemm-1x8c8-minmax-fp32-asm-aarch64-neon-mlal-prfm.S", |
| "src/qs8-igemm/gen/qs8-igemm-1x8c8-minmax-fp32-asm-aarch64-neon-mlal.S", |
| "src/qs8-igemm/gen/qs8-igemm-1x8c8-minmax-rndnu-asm-aarch64-neon-mlal-cortex-a53-prfm.S", |
| "src/qs8-igemm/gen/qs8-igemm-1x8c8-minmax-rndnu-asm-aarch64-neon-mlal-cortex-a53.S", |
| "src/qs8-igemm/gen/qs8-igemm-1x8c8-minmax-rndnu-asm-aarch64-neon-mlal-prfm.S", |
| "src/qs8-igemm/gen/qs8-igemm-1x8c8-minmax-rndnu-asm-aarch64-neon-mlal.S", |
| "src/qs8-igemm/gen/qs8-igemm-2x8c8-minmax-fp32-asm-aarch64-neon-mlal-cortex-a53-prfm.S", |
| "src/qs8-igemm/gen/qs8-igemm-2x8c8-minmax-fp32-asm-aarch64-neon-mlal-cortex-a53.S", |
| "src/qs8-igemm/gen/qs8-igemm-2x8c8-minmax-fp32-asm-aarch64-neon-mlal-prfm.S", |
| "src/qs8-igemm/gen/qs8-igemm-2x8c8-minmax-fp32-asm-aarch64-neon-mlal.S", |
| "src/qs8-igemm/gen/qs8-igemm-2x8c8-minmax-rndnu-asm-aarch64-neon-mlal-cortex-a53-prfm.S", |
| "src/qs8-igemm/gen/qs8-igemm-2x8c8-minmax-rndnu-asm-aarch64-neon-mlal-cortex-a53.S", |
| "src/qs8-igemm/gen/qs8-igemm-2x8c8-minmax-rndnu-asm-aarch64-neon-mlal-prfm.S", |
| "src/qs8-igemm/gen/qs8-igemm-2x8c8-minmax-rndnu-asm-aarch64-neon-mlal.S", |
| "src/qs8-igemm/gen/qs8-igemm-2x8c16-minmax-fp32-asm-aarch64-neon-mlal.S", |
| "src/qs8-igemm/gen/qs8-igemm-2x8c16-minmax-rndnu-asm-aarch64-neon-mlal.S", |
| "src/qs8-igemm/gen/qs8-igemm-4x8-minmax-rndnu-asm-aarch64-neon-mlal-lane-ld64-prfm.S", |
| "src/qs8-igemm/gen/qs8-igemm-4x8-minmax-rndnu-asm-aarch64-neon-mlal-lane-ld64.S", |
| "src/qs8-igemm/gen/qs8-igemm-4x16-minmax-fp32-asm-aarch64-neon-mlal-lane-cortex-a53-prfm.S", |
| "src/qs8-igemm/gen/qs8-igemm-4x16-minmax-fp32-asm-aarch64-neon-mlal-lane-cortex-a53.S", |
| "src/qs8-igemm/gen/qs8-igemm-4x16-minmax-fp32-asm-aarch64-neon-mlal-lane-ld64-prfm.S", |
| "src/qs8-igemm/gen/qs8-igemm-4x16-minmax-fp32-asm-aarch64-neon-mlal-lane-ld64.S", |
| "src/qs8-igemm/gen/qs8-igemm-4x16-minmax-rndnu-asm-aarch64-neon-mlal-lane-cortex-a53-prfm.S", |
| "src/qs8-igemm/gen/qs8-igemm-4x16-minmax-rndnu-asm-aarch64-neon-mlal-lane-cortex-a53.S", |
| "src/qs8-igemm/gen/qs8-igemm-4x16-minmax-rndnu-asm-aarch64-neon-mlal-lane-ld64-prfm.S", |
| "src/qs8-igemm/gen/qs8-igemm-4x16-minmax-rndnu-asm-aarch64-neon-mlal-lane-ld64.S", |
| "src/qs8-igemm/gen/qs8-igemm-4x16c4-minmax-fp32-asm-aarch64-neondot-cortex-a55.S", |
| "src/qs8-igemm/gen/qs8-igemm-4x16c4-minmax-fp32-asm-aarch64-neondot-ld64.S", |
| "src/qs8-igemm/gen/qs8-igemm-4x16c4-minmax-fp32-asm-aarch64-neondot-ld128.S", |
| "src/qs8-igemm/gen/qs8-igemm-4x16c4-minmax-rndnu-asm-aarch64-neondot-cortex-a55.S", |
| "src/qs8-igemm/gen/qs8-igemm-4x16c4-minmax-rndnu-asm-aarch64-neondot-ld64.S", |
| "src/qs8-igemm/gen/qs8-igemm-4x16c4-minmax-rndnu-asm-aarch64-neondot-ld128.S", |
| "src/qs8-qc8w-gemm/gen/qs8-qc8w-gemm-1x8c8-minmax-fp32-asm-aarch64-neon-mlal-cortex-a53-prfm.S", |
| "src/qs8-qc8w-gemm/gen/qs8-qc8w-gemm-1x8c8-minmax-fp32-asm-aarch64-neon-mlal-cortex-a53.S", |
| "src/qs8-qc8w-gemm/gen/qs8-qc8w-gemm-1x8c8-minmax-fp32-asm-aarch64-neon-mlal-prfm.S", |
| "src/qs8-qc8w-gemm/gen/qs8-qc8w-gemm-1x8c8-minmax-fp32-asm-aarch64-neon-mlal.S", |
| "src/qs8-qc8w-gemm/gen/qs8-qc8w-gemm-1x16c4-minmax-fp32-asm-aarch64-neondot-ld32.S", |
| "src/qs8-qc8w-gemm/gen/qs8-qc8w-gemm-1x16c4-minmax-fp32-asm-aarch64-neondot-ld64.S", |
| "src/qs8-qc8w-gemm/gen/qs8-qc8w-gemm-2x8c8-minmax-fp32-asm-aarch64-neon-mlal-cortex-a53-prfm.S", |
| "src/qs8-qc8w-gemm/gen/qs8-qc8w-gemm-2x8c8-minmax-fp32-asm-aarch64-neon-mlal-cortex-a53.S", |
| "src/qs8-qc8w-gemm/gen/qs8-qc8w-gemm-2x8c8-minmax-fp32-asm-aarch64-neon-mlal-prfm.S", |
| "src/qs8-qc8w-gemm/gen/qs8-qc8w-gemm-2x8c8-minmax-fp32-asm-aarch64-neon-mlal.S", |
| "src/qs8-qc8w-gemm/gen/qs8-qc8w-gemm-2x8c8-minmax-fp32-asm-aarch64-neon-mull.S", |
| "src/qs8-qc8w-gemm/gen/qs8-qc8w-gemm-2x8c16-minmax-fp32-asm-aarch64-neon-mlal.S", |
| "src/qs8-qc8w-gemm/gen/qs8-qc8w-gemm-4x16-minmax-fp32-asm-aarch64-neon-mlal-lane-cortex-a53-prfm.S", |
| "src/qs8-qc8w-gemm/gen/qs8-qc8w-gemm-4x16-minmax-fp32-asm-aarch64-neon-mlal-lane-cortex-a53.S", |
| "src/qs8-qc8w-gemm/gen/qs8-qc8w-gemm-4x16-minmax-fp32-asm-aarch64-neon-mlal-lane-ld64-prfm.S", |
| "src/qs8-qc8w-gemm/gen/qs8-qc8w-gemm-4x16-minmax-fp32-asm-aarch64-neon-mlal-lane-ld64.S", |
| "src/qs8-qc8w-gemm/gen/qs8-qc8w-gemm-4x16c4-minmax-fp32-asm-aarch64-neondot-cortex-a55.S", |
| "src/qs8-qc8w-gemm/gen/qs8-qc8w-gemm-4x16c4-minmax-fp32-asm-aarch64-neondot-ld32.S", |
| "src/qs8-qc8w-gemm/gen/qs8-qc8w-gemm-4x16c4-minmax-fp32-asm-aarch64-neondot-ld64.S", |
| "src/qs8-qc8w-gemm/gen/qs8-qc8w-gemm-4x16c4-minmax-fp32-asm-aarch64-neondot-ld128.S", |
| "src/qs8-qc8w-igemm/gen/qs8-qc8w-igemm-1x8c8-minmax-fp32-asm-aarch64-neon-mlal-cortex-a53-prfm.S", |
| "src/qs8-qc8w-igemm/gen/qs8-qc8w-igemm-1x8c8-minmax-fp32-asm-aarch64-neon-mlal-cortex-a53.S", |
| "src/qs8-qc8w-igemm/gen/qs8-qc8w-igemm-1x8c8-minmax-fp32-asm-aarch64-neon-mlal-prfm.S", |
| "src/qs8-qc8w-igemm/gen/qs8-qc8w-igemm-1x8c8-minmax-fp32-asm-aarch64-neon-mlal.S", |
| "src/qs8-qc8w-igemm/gen/qs8-qc8w-igemm-2x8c8-minmax-fp32-asm-aarch64-neon-mlal-cortex-a53-prfm.S", |
| "src/qs8-qc8w-igemm/gen/qs8-qc8w-igemm-2x8c8-minmax-fp32-asm-aarch64-neon-mlal-cortex-a53.S", |
| "src/qs8-qc8w-igemm/gen/qs8-qc8w-igemm-2x8c8-minmax-fp32-asm-aarch64-neon-mlal-prfm.S", |
| "src/qs8-qc8w-igemm/gen/qs8-qc8w-igemm-2x8c8-minmax-fp32-asm-aarch64-neon-mlal.S", |
| "src/qs8-qc8w-igemm/gen/qs8-qc8w-igemm-2x8c16-minmax-fp32-asm-aarch64-neon-mlal.S", |
| "src/qs8-qc8w-igemm/gen/qs8-qc8w-igemm-4x16-minmax-fp32-asm-aarch64-neon-mlal-lane-cortex-a53-prfm.S", |
| "src/qs8-qc8w-igemm/gen/qs8-qc8w-igemm-4x16-minmax-fp32-asm-aarch64-neon-mlal-lane-cortex-a53.S", |
| "src/qs8-qc8w-igemm/gen/qs8-qc8w-igemm-4x16-minmax-fp32-asm-aarch64-neon-mlal-lane-ld64-prfm.S", |
| "src/qs8-qc8w-igemm/gen/qs8-qc8w-igemm-4x16-minmax-fp32-asm-aarch64-neon-mlal-lane-ld64.S", |
| "src/qs8-qc8w-igemm/gen/qs8-qc8w-igemm-4x16c4-minmax-fp32-asm-aarch64-neondot-cortex-a55.S", |
| "src/qs8-qc8w-igemm/gen/qs8-qc8w-igemm-4x16c4-minmax-fp32-asm-aarch64-neondot-ld64.S", |
| "src/qs8-qc8w-igemm/gen/qs8-qc8w-igemm-4x16c4-minmax-fp32-asm-aarch64-neondot-ld128.S", |
| "src/qu8-gemm/gen/qu8-gemm-4x8c4-minmax-rndnu-asm-aarch64-neondot-cortex-a55.S", |
| "src/qu8-gemm/gen/qu8-gemm-4x8c4-minmax-rndnu-asm-aarch64-neondot-ld128.S", |
| "src/qu8-gemm/gen/qu8-gemm-4x16-minmax-rndnu-asm-aarch64-neon-mlal-lane-cortex-a53-prfm.S", |
| "src/qu8-gemm/gen/qu8-gemm-4x16-minmax-rndnu-asm-aarch64-neon-mlal-lane-cortex-a53.S", |
| "src/qu8-gemm/gen/qu8-gemm-4x16-minmax-rndnu-asm-aarch64-neon-mlal-lane-cortex-a75-prfm.S", |
| "src/qu8-gemm/gen/qu8-gemm-4x16-minmax-rndnu-asm-aarch64-neon-mlal-lane-cortex-a75.S", |
| "src/qu8-gemm/gen/qu8-gemm-4x16-minmax-rndnu-asm-aarch64-neon-mlal-lane-ld64-prfm.S", |
| "src/qu8-gemm/gen/qu8-gemm-4x16-minmax-rndnu-asm-aarch64-neon-mlal-lane-ld64.S", |
| "src/qu8-gemm/gen/qu8-gemm-4x16c4-minmax-fp32-asm-aarch64-neondot-cortex-a55.S", |
| "src/qu8-gemm/gen/qu8-gemm-4x16c4-minmax-fp32-asm-aarch64-neondot-ld128.S", |
| "src/qu8-gemm/gen/qu8-gemm-4x16c4-minmax-rndnu-asm-aarch64-neondot-cortex-a55.S", |
| "src/qu8-gemm/gen/qu8-gemm-4x16c4-minmax-rndnu-asm-aarch64-neondot-ld128.S", |
| "src/qu8-igemm/gen/qu8-igemm-4x8c4-minmax-rndnu-asm-aarch64-neondot-cortex-a55.S", |
| "src/qu8-igemm/gen/qu8-igemm-4x8c4-minmax-rndnu-asm-aarch64-neondot-ld128.S", |
| "src/qu8-igemm/gen/qu8-igemm-4x16-minmax-rndnu-asm-aarch64-neon-mlal-lane-cortex-a53-prfm.S", |
| "src/qu8-igemm/gen/qu8-igemm-4x16-minmax-rndnu-asm-aarch64-neon-mlal-lane-cortex-a53.S", |
| "src/qu8-igemm/gen/qu8-igemm-4x16-minmax-rndnu-asm-aarch64-neon-mlal-lane-cortex-a75-prfm.S", |
| "src/qu8-igemm/gen/qu8-igemm-4x16-minmax-rndnu-asm-aarch64-neon-mlal-lane-cortex-a75.S", |
| "src/qu8-igemm/gen/qu8-igemm-4x16-minmax-rndnu-asm-aarch64-neon-mlal-lane-ld64-prfm.S", |
| "src/qu8-igemm/gen/qu8-igemm-4x16-minmax-rndnu-asm-aarch64-neon-mlal-lane-ld64.S", |
| "src/qu8-igemm/gen/qu8-igemm-4x16c4-minmax-fp32-asm-aarch64-neondot-cortex-a55.S", |
| "src/qu8-igemm/gen/qu8-igemm-4x16c4-minmax-fp32-asm-aarch64-neondot-ld128.S", |
| "src/qu8-igemm/gen/qu8-igemm-4x16c4-minmax-rndnu-asm-aarch64-neondot-cortex-a55.S", |
| "src/qu8-igemm/gen/qu8-igemm-4x16c4-minmax-rndnu-asm-aarch64-neondot-ld128.S", |
| ] |
| |
| WASM32_ASM_MICROKERNEL_SRCS = [ |
| "src/f32-vrelu/f32-vrelu-asm-wasm32-shr-u1.S", |
| "src/f32-vrelu/f32-vrelu-asm-wasm32-shr-u2.S", |
| "src/f32-vrelu/f32-vrelu-asm-wasm32-shr-u4.S", |
| ] |
| |
| WASMRELAXEDSIMD32_ASM_MICROKERNEL_SRCS = [ |
| ] |
| |
| WASMSIMD32_ASM_MICROKERNEL_SRCS = [ |
| ] |
| |
| AARCH32_JIT_MICROKERNEL_SRCS = [ |
| "src/f32-gemm/gen/f32-gemm-1x8-aarch32-neon-cortex-a53.cc", |
| "src/f32-gemm/gen/f32-gemm-4x8-aarch32-neon-cortex-a7.cc", |
| "src/f32-gemm/gen/f32-gemm-4x8-aarch32-neon-cortex-a53.cc", |
| "src/f32-gemm/gen/f32-gemm-4x8-aarch32-neon-cortex-a55.cc", |
| "src/f32-gemm/gen/f32-gemm-4x8-aarch32-neon-cortex-a75.cc", |
| "src/f32-gemm/gen/f32-gemm-4x8-aarch32-neon-ld64.cc", |
| "src/f32-igemm/gen/f32-igemm-1x8-aarch32-neon-cortex-a53.cc", |
| "src/f32-igemm/gen/f32-igemm-4x8-aarch32-neon-cortex-a7.cc", |
| "src/f32-igemm/gen/f32-igemm-4x8-aarch32-neon-cortex-a53.cc", |
| "src/f32-igemm/gen/f32-igemm-4x8-aarch32-neon-cortex-a55.cc", |
| "src/f32-igemm/gen/f32-igemm-4x8-aarch32-neon-cortex-a75.cc", |
| "src/f32-igemm/gen/f32-igemm-4x8-aarch32-neon-ld64.cc", |
| "src/qs8-gemm/gen/qs8-gemm-4x8-rndnu-aarch32-neon-mlal-lane-ld64.cc", |
| "src/qs8-gemm/gen/qs8-gemm-4x8c4-rndnu-aarch32-neondot-ld64.cc", |
| "src/qs8-igemm/gen/qs8-igemm-4x8-rndnu-aarch32-neon-mlal-lane-ld64.cc", |
| "src/qs8-igemm/gen/qs8-igemm-4x8c4-rndnu-aarch32-neondot-ld64.cc", |
| "src/qs8-qc8w-gemm/gen/qs8-qc8w-gemm-4x8-fp32-aarch32-neonv8-mlal-lane-ld64.cc", |
| "src/qs8-qc8w-gemm/gen/qs8-qc8w-gemm-4x8c4-fp32-aarch32-neondot-ld64.cc", |
| "src/qs8-qc8w-igemm/gen/qs8-qc8w-igemm-4x8-fp32-aarch32-neonv8-mlal-lane-ld64.cc", |
| "src/qs8-qc8w-igemm/gen/qs8-qc8w-igemm-4x8c4-fp32-aarch32-neondot-ld64.cc", |
| ] |
| |
| AARCH64_JIT_MICROKERNEL_SRCS = [ |
| "src/f16-gemm/gen/f16-gemm-1x16-aarch64-neonfp16arith-ld64.cc", |
| "src/f16-gemm/gen/f16-gemm-4x16-aarch64-neonfp16arith-ld64.cc", |
| "src/f16-gemm/gen/f16-gemm-6x16-aarch64-neonfp16arith-cortex-a55.cc", |
| "src/f16-gemm/gen/f16-gemm-6x16-aarch64-neonfp16arith-cortex-a55r0.cc", |
| "src/f16-gemm/gen/f16-gemm-6x16-aarch64-neonfp16arith-cortex-a75.cc", |
| "src/f16-gemm/gen/f16-gemm-6x16-aarch64-neonfp16arith-ld64.cc", |
| "src/f16-igemm/gen/f16-igemm-1x16-aarch64-neonfp16arith-ld64.cc", |
| "src/f16-igemm/gen/f16-igemm-4x16-aarch64-neonfp16arith-ld64.cc", |
| "src/f16-igemm/gen/f16-igemm-6x16-aarch64-neonfp16arith-cortex-a55.cc", |
| "src/f16-igemm/gen/f16-igemm-6x16-aarch64-neonfp16arith-cortex-a55r0.cc", |
| "src/f16-igemm/gen/f16-igemm-6x16-aarch64-neonfp16arith-cortex-a75.cc", |
| "src/f16-igemm/gen/f16-igemm-6x16-aarch64-neonfp16arith-ld64.cc", |
| "src/f32-gemm/gen/f32-gemm-1x8-aarch64-neonfma-cortex-a53.cc", |
| "src/f32-gemm/gen/f32-gemm-1x8-aarch64-neonfma-cortex-a75.cc", |
| "src/f32-gemm/gen/f32-gemm-1x8-aarch64-neonfma-ld64.cc", |
| "src/f32-gemm/gen/f32-gemm-4x8-aarch64-neonfma-cortex-a53.cc", |
| "src/f32-gemm/gen/f32-gemm-4x8-aarch64-neonfma-cortex-a55.cc", |
| "src/f32-gemm/gen/f32-gemm-4x8-aarch64-neonfma-cortex-a75.cc", |
| "src/f32-gemm/gen/f32-gemm-4x8-aarch64-neonfma-ld128.cc", |
| "src/f32-gemm/gen/f32-gemm-6x8-aarch64-neonfma-cortex-a53.cc", |
| "src/f32-gemm/gen/f32-gemm-6x8-aarch64-neonfma-cortex-a55.cc", |
| "src/f32-gemm/gen/f32-gemm-6x8-aarch64-neonfma-cortex-a75.cc", |
| "src/f32-gemm/gen/f32-gemm-6x8-aarch64-neonfma-ld128.cc", |
| "src/f32-igemm/gen/f32-igemm-1x8-aarch64-neonfma-cortex-a53.cc", |
| "src/f32-igemm/gen/f32-igemm-1x8-aarch64-neonfma-cortex-a75.cc", |
| "src/f32-igemm/gen/f32-igemm-4x8-aarch64-neonfma-cortex-a53.cc", |
| "src/f32-igemm/gen/f32-igemm-4x8-aarch64-neonfma-cortex-a55.cc", |
| "src/f32-igemm/gen/f32-igemm-4x8-aarch64-neonfma-cortex-a75.cc", |
| "src/f32-igemm/gen/f32-igemm-4x8-aarch64-neonfma-ld128.cc", |
| "src/f32-igemm/gen/f32-igemm-6x8-aarch64-neonfma-cortex-a53.cc", |
| "src/f32-igemm/gen/f32-igemm-6x8-aarch64-neonfma-cortex-a55.cc", |
| "src/f32-igemm/gen/f32-igemm-6x8-aarch64-neonfma-cortex-a75.cc", |
| "src/f32-igemm/gen/f32-igemm-6x8-aarch64-neonfma-ld128.cc", |
| ] |
| |
| WASM32_JIT_MICROKERNEL_SRCS = [ |
| ] |
| |
| WASMRELAXEDSIMD32_JIT_MICROKERNEL_SRCS = [ |
| ] |
| |
| WASMSIMD32_JIT_MICROKERNEL_SRCS = [ |
| "src/f32-gemm/MRx8-wasmsimd32-x86-loadsplat.cc", |
| "src/f32-gemm/MRx8-wasmsimd32-x86-splat.cc", |
| "src/f32-gemm/MRx8s4-wasmsimd32-x86.cc", |
| "src/f32-igemm/MRx8-wasmsimd32-x86-loadsplat.cc", |
| "src/f32-igemm/MRx8-wasmsimd32-x86-splat.cc", |
| "src/f32-igemm/MRx8s4-wasmsimd32-x86.cc", |
| ] |
