commit d9bb7b69abe266ab8d3ba54186604af9cc8750ad
author Cullen Rhodes <cullen.rhodes@arm.com> Fri May 24 08:45:37 2019
committer Cullen Rhodes <cullen.rhodes@arm.com> Fri May 24 08:45:37 2019
tree c45874c8eec14898980dbf76491b67da4143a80d
parent 3b2157aeed845b0cf70f38cf7d3b29da50291cf8

[AArch64][SVE2] Asm: fix overlapping bit

Summary:
Bit 20 in sve2_int_arith_pred TableGen class was overlapping. The
encodings are not affected as bit 20 is defined by the opc bits
and this was overwriting the earlier error of setting bit 20 to 0.

Raised by Momchil: https://reviews.llvm.org/D62130

Reviewed By: chill

Differential Revision: https://reviews.llvm.org/D62292

llvm-svn: 361609

llvm/lib/Target/AArch64/SVEInstrFormats.td

diff --git a/llvm/lib/Target/AArch64/SVEInstrFormats.td b/llvm/lib/Target/AArch64/SVEInstrFormats.td
index 79f2dab..ac4d800 100644
--- a/llvm/lib/Target/AArch64/SVEInstrFormats.td
+++ b/llvm/lib/Target/AArch64/SVEInstrFormats.td
@@ -2070,7 +2070,7 @@
   bits<5> Zdn;
   let Inst{31-24} = 0b01000100;
   let Inst{23-22} = sz;
-  let Inst{21-20} = 0b01;
+  let Inst{21}    = 0b0;
   let Inst{20-16} = opc{5-1};
   let Inst{15-14} = 0b10;
   let Inst{13}    = opc{0};