Use x86_64_general_operand in a bunch more SI mode insn patterns
The x86_64_general_operand predicate applies some important constraints,
such as that a symbol_ref cannot be an immediate operand under -fPIC.
With the ILP32 model, these constraints matter for SI mode instructions
(rather than just DI mode) too, since address values are SI mode.
Previously the x86_64_general_operand predicate was used inconsistently,
e.g. on add patterns but not on sub and mul patterns. This fix changes
all the relevant patterns to use x86_64_general_operand in place of
vanilla general_operand. This is consistent with how the -mx32 support
handles this issue in the upstream trunk code.
BUG= https://code.google.com/p/nativeclient/issues/detail?id=3549
TEST= toolchain trybots
R=khim@chromium.org
Review URL: https://codereview.chromium.org/20820002
diff --git a/gcc/config/i386/i386.md b/gcc/config/i386/i386.md
index 7da4cfc..a260bad 100644
--- a/gcc/config/i386/i386.md
+++ b/gcc/config/i386/i386.md
@@ -776,7 +776,7 @@
(define_expand "cmpsi"
[(set (reg:CC FLAGS_REG)
(compare:CC (match_operand:SI 0 "cmpsi_operand" "")
- (match_operand:SI 1 "general_operand" "")))]
+ (match_operand:SI 1 "x86_64_general_operand" "")))]
""
{
if (MEM_P (operands[0]) && MEM_P (operands[1]))
@@ -866,7 +866,7 @@
(define_insn "*cmpsi_minus_1"
[(set (reg FLAGS_REG)
(compare (minus:SI (match_operand:SI 0 "nonimmediate_operand" "rm,r")
- (match_operand:SI 1 "general_operand" "re,mr"))
+ (match_operand:SI 1 "x86_64_general_operand" "re,mr"))
(const_int 0)))]
"ix86_match_ccmode (insn, CCGOCmode)"
"cmp{l}\t{%1, %0|%0, %1}"
@@ -876,14 +876,14 @@
(define_expand "cmpsi_1"
[(set (reg:CC FLAGS_REG)
(compare:CC (match_operand:SI 0 "nonimmediate_operand" "")
- (match_operand:SI 1 "general_operand" "")))]
+ (match_operand:SI 1 "x86_64_general_operand" "")))]
""
"")
(define_insn "*cmpsi_1_insn"
[(set (reg FLAGS_REG)
(compare (match_operand:SI 0 "nonimmediate_operand" "rm,r")
- (match_operand:SI 1 "general_operand" "re,mr")))]
+ (match_operand:SI 1 "x86_64_general_operand" "re,mr")))]
"!(MEM_P (operands[0]) && MEM_P (operands[1]))
&& ix86_match_ccmode (insn, CCmode)"
"cmp{l}\t{%1, %0|%0, %1}"
@@ -5891,7 +5891,7 @@
[(set (reg:CCC FLAGS_REG)
(compare:CCC
(plusminus:SI (match_operand:SI 1 "nonimmediate_operand" "<comm>0")
- (match_operand:SI 2 "general_operand" "g"))
+ (match_operand:SI 2 "x86_64_general_operand" "g"))
(match_dup 1)))
(set (match_operand:DI 0 "register_operand" "=r")
(zero_extend:DI (plusminus:SI (match_dup 1) (match_dup 2))))]
@@ -7757,7 +7757,7 @@
[(set (match_operand:SI 0 "nonimmediate_operand" "=rm,r")
(minus:SI (match_operand:SI 1 "nonimmediate_operand" "0,0")
(plus:SI (match_operand:SI 3 "ix86_carry_flag_operator" "")
- (match_operand:SI 2 "general_operand" "ri,rm"))))
+ (match_operand:SI 2 "x86_64_general_operand" "ri,rm"))))
(clobber (reg:CC FLAGS_REG))]
"ix86_binary_operator_ok (MINUS, SImode, operands)"
"sbb{l}\t{%2, %0|%0, %2}"
@@ -7770,7 +7770,7 @@
(zero_extend:DI
(minus:SI (match_operand:SI 1 "register_operand" "0")
(plus:SI (match_operand:SI 3 "ix86_carry_flag_operator" "")
- (match_operand:SI 2 "general_operand" "g")))))
+ (match_operand:SI 2 "x86_64_general_operand" "g")))))
(clobber (reg:CC FLAGS_REG))]
"TARGET_64BIT && ix86_binary_operator_ok (MINUS, SImode, operands)"
"sbb{l}\t{%2, %k0|%k0, %2}"
@@ -7781,14 +7781,14 @@
(define_expand "subsi3"
[(set (match_operand:SI 0 "nonimmediate_operand" "")
(minus:SI (match_operand:SI 1 "nonimmediate_operand" "")
- (match_operand:SI 2 "general_operand" "")))]
+ (match_operand:SI 2 "x86_64_general_operand" "")))]
""
"ix86_expand_binary_operator (MINUS, SImode, operands); DONE;")
(define_insn "*subsi_1"
[(set (match_operand:SI 0 "nonimmediate_operand" "=rm,r")
(minus:SI (match_operand:SI 1 "nonimmediate_operand" "0,0")
- (match_operand:SI 2 "general_operand" "re,rm")))
+ (match_operand:SI 2 "x86_64_general_operand" "re,rm")))
(clobber (reg:CC FLAGS_REG))]
"ix86_binary_operator_ok (MINUS, SImode, operands)"
"sub{l}\t{%2, %0|%0, %2}"
@@ -7799,7 +7799,7 @@
[(set (match_operand:DI 0 "register_operand" "=r")
(zero_extend:DI
(minus:SI (match_operand:SI 1 "register_operand" "0")
- (match_operand:SI 2 "general_operand" "g"))))
+ (match_operand:SI 2 "x86_64_general_operand" "g"))))
(clobber (reg:CC FLAGS_REG))]
"TARGET_64BIT && ix86_binary_operator_ok (MINUS, SImode, operands)"
"sub{l}\t{%2, %k0|%k0, %2}"
@@ -7810,7 +7810,7 @@
[(set (reg FLAGS_REG)
(compare
(minus:SI (match_operand:SI 1 "nonimmediate_operand" "0,0")
- (match_operand:SI 2 "general_operand" "ri,rm"))
+ (match_operand:SI 2 "x86_64_general_operand" "ri,rm"))
(const_int 0)))
(set (match_operand:SI 0 "nonimmediate_operand" "=rm,r")
(minus:SI (match_dup 1) (match_dup 2)))]
@@ -7824,7 +7824,7 @@
[(set (reg FLAGS_REG)
(compare
(minus:SI (match_operand:SI 1 "register_operand" "0")
- (match_operand:SI 2 "general_operand" "g"))
+ (match_operand:SI 2 "x86_64_general_operand" "g"))
(const_int 0)))
(set (match_operand:DI 0 "register_operand" "=r")
(zero_extend:DI
@@ -7839,7 +7839,7 @@
(define_insn "*subsi_3"
[(set (reg FLAGS_REG)
(compare (match_operand:SI 1 "nonimmediate_operand" "0,0")
- (match_operand:SI 2 "general_operand" "ri,rm")))
+ (match_operand:SI 2 "x86_64_general_operand" "ri,rm")))
(set (match_operand:SI 0 "nonimmediate_operand" "=rm,r")
(minus:SI (match_dup 1) (match_dup 2)))]
"ix86_match_ccmode (insn, CCmode)
@@ -7851,7 +7851,7 @@
(define_insn "*subsi_3_zext"
[(set (reg FLAGS_REG)
(compare (match_operand:SI 1 "register_operand" "0")
- (match_operand:SI 2 "general_operand" "g")))
+ (match_operand:SI 2 "x86_64_general_operand" "g")))
(set (match_operand:DI 0 "register_operand" "=r")
(zero_extend:DI
(minus:SI (match_dup 1)
@@ -8025,7 +8025,7 @@
(define_expand "mulsi3"
[(parallel [(set (match_operand:SI 0 "register_operand" "")
(mult:SI (match_operand:SI 1 "register_operand" "")
- (match_operand:SI 2 "general_operand" "")))
+ (match_operand:SI 2 "x86_64_general_operand" "")))
(clobber (reg:CC FLAGS_REG))])]
""
"")
@@ -8041,7 +8041,7 @@
(define_insn "*mulsi3_1"
[(set (match_operand:SI 0 "register_operand" "=r,r,r")
(mult:SI (match_operand:SI 1 "nonimmediate_operand" "%rm,rm,0")
- (match_operand:SI 2 "general_operand" "K,i,mr")))
+ (match_operand:SI 2 "x86_64_general_operand" "K,i,mr")))
(clobber (reg:CC FLAGS_REG))]
"!(MEM_P (operands[1]) && MEM_P (operands[2]))"
"@
@@ -8070,7 +8070,7 @@
[(set (match_operand:DI 0 "register_operand" "=r,r,r")
(zero_extend:DI
(mult:SI (match_operand:SI 1 "nonimmediate_operand" "%rm,rm,0")
- (match_operand:SI 2 "general_operand" "K,i,mr"))))
+ (match_operand:SI 2 "x86_64_general_operand" "K,i,mr"))))
(clobber (reg:CC FLAGS_REG))]
"TARGET_64BIT
&& !(MEM_P (operands[1]) && MEM_P (operands[2]))"
@@ -8925,7 +8925,7 @@
[(set (reg FLAGS_REG)
(compare
(and:SI (match_operand:SI 0 "nonimmediate_operand" "%!*a,r,rm")
- (match_operand:SI 1 "general_operand" "i,i,ri"))
+ (match_operand:SI 1 "x86_64_general_operand" "i,i,ri"))
(const_int 0)))]
"ix86_match_ccmode (insn, CCNOmode)
&& !(MEM_P (operands[0]) && MEM_P (operands[1]))"
@@ -8939,7 +8939,7 @@
[(set (reg:CCNO FLAGS_REG)
(compare:CCNO
(and:SI (match_operand:SI 0 "nonimmediate_operand" "")
- (match_operand:SI 1 "nonmemory_operand" ""))
+ (match_operand:SI 1 "x86_64_nonmemory_operand" ""))
(const_int 0)))]
""
"")
@@ -9747,14 +9747,14 @@
(define_expand "iorsi3"
[(set (match_operand:SI 0 "nonimmediate_operand" "")
(ior:SI (match_operand:SI 1 "nonimmediate_operand" "")
- (match_operand:SI 2 "general_operand" "")))]
+ (match_operand:SI 2 "x86_64_general_operand" "")))]
""
"ix86_expand_binary_operator (IOR, SImode, operands); DONE;")
(define_insn "*iorsi_1"
[(set (match_operand:SI 0 "nonimmediate_operand" "=rm,r")
(ior:SI (match_operand:SI 1 "nonimmediate_operand" "%0,0")
- (match_operand:SI 2 "general_operand" "ri,g")))
+ (match_operand:SI 2 "x86_64_general_operand" "ri,g")))
(clobber (reg:CC FLAGS_REG))]
"ix86_binary_operator_ok (IOR, SImode, operands)"
"or{l}\t{%2, %0|%0, %2}"
@@ -9766,7 +9766,7 @@
[(set (match_operand:DI 0 "register_operand" "=r")
(zero_extend:DI
(ior:SI (match_operand:SI 1 "nonimmediate_operand" "%0")
- (match_operand:SI 2 "general_operand" "g"))))
+ (match_operand:SI 2 "x86_64_general_operand" "g"))))
(clobber (reg:CC FLAGS_REG))]
"TARGET_64BIT && ix86_binary_operator_ok (IOR, SImode, operands)"
"or{l}\t{%2, %k0|%k0, %2}"
@@ -9786,7 +9786,7 @@
(define_insn "*iorsi_2"
[(set (reg FLAGS_REG)
(compare (ior:SI (match_operand:SI 1 "nonimmediate_operand" "%0,0")
- (match_operand:SI 2 "general_operand" "g,ri"))
+ (match_operand:SI 2 "x86_64_general_operand" "g,ri"))
(const_int 0)))
(set (match_operand:SI 0 "nonimmediate_operand" "=r,rm")
(ior:SI (match_dup 1) (match_dup 2)))]
@@ -9801,7 +9801,7 @@
(define_insn "*iorsi_2_zext"
[(set (reg FLAGS_REG)
(compare (ior:SI (match_operand:SI 1 "nonimmediate_operand" "%0")
- (match_operand:SI 2 "general_operand" "g"))
+ (match_operand:SI 2 "x86_64_general_operand" "g"))
(const_int 0)))
(set (match_operand:DI 0 "register_operand" "=r")
(zero_extend:DI (ior:SI (match_dup 1) (match_dup 2))))]
@@ -10130,7 +10130,7 @@
(define_insn "*iorsi_3"
[(set (reg FLAGS_REG)
(compare (ior:SI (match_operand:SI 1 "nonimmediate_operand" "%0")
- (match_operand:SI 2 "general_operand" "g"))
+ (match_operand:SI 2 "x86_64_general_operand" "g"))
(const_int 0)))
(clobber (match_scratch:SI 0 "=r"))]
"ix86_match_ccmode (insn, CCNOmode)
@@ -10418,14 +10418,14 @@
(define_expand "xorsi3"
[(set (match_operand:SI 0 "nonimmediate_operand" "")
(xor:SI (match_operand:SI 1 "nonimmediate_operand" "")
- (match_operand:SI 2 "general_operand" "")))]
+ (match_operand:SI 2 "x86_64_general_operand" "")))]
""
"ix86_expand_binary_operator (XOR, SImode, operands); DONE;")
(define_insn "*xorsi_1"
[(set (match_operand:SI 0 "nonimmediate_operand" "=rm,r")
(xor:SI (match_operand:SI 1 "nonimmediate_operand" "%0,0")
- (match_operand:SI 2 "general_operand" "ri,rm")))
+ (match_operand:SI 2 "x86_64_general_operand" "ri,rm")))
(clobber (reg:CC FLAGS_REG))]
"ix86_binary_operator_ok (XOR, SImode, operands)"
"xor{l}\t{%2, %0|%0, %2}"
@@ -10438,7 +10438,7 @@
[(set (match_operand:DI 0 "register_operand" "=r")
(zero_extend:DI
(xor:SI (match_operand:SI 1 "nonimmediate_operand" "%0")
- (match_operand:SI 2 "general_operand" "g"))))
+ (match_operand:SI 2 "x86_64_general_operand" "g"))))
(clobber (reg:CC FLAGS_REG))]
"TARGET_64BIT && ix86_binary_operator_ok (XOR, SImode, operands)"
"xor{l}\t{%2, %k0|%k0, %2}"
@@ -10458,7 +10458,7 @@
(define_insn "*xorsi_2"
[(set (reg FLAGS_REG)
(compare (xor:SI (match_operand:SI 1 "nonimmediate_operand" "%0,0")
- (match_operand:SI 2 "general_operand" "g,ri"))
+ (match_operand:SI 2 "x86_64_general_operand" "g,ri"))
(const_int 0)))
(set (match_operand:SI 0 "nonimmediate_operand" "=r,rm")
(xor:SI (match_dup 1) (match_dup 2)))]
@@ -10473,7 +10473,7 @@
(define_insn "*xorsi_2_zext"
[(set (reg FLAGS_REG)
(compare (xor:SI (match_operand:SI 1 "nonimmediate_operand" "%0")
- (match_operand:SI 2 "general_operand" "g"))
+ (match_operand:SI 2 "x86_64_general_operand" "g"))
(const_int 0)))
(set (match_operand:DI 0 "register_operand" "=r")
(zero_extend:DI (xor:SI (match_dup 1) (match_dup 2))))]
@@ -10499,7 +10499,7 @@
(define_insn "*xorsi_3"
[(set (reg FLAGS_REG)
(compare (xor:SI (match_operand:SI 1 "nonimmediate_operand" "%0")
- (match_operand:SI 2 "general_operand" "g"))
+ (match_operand:SI 2 "x86_64_general_operand" "g"))
(const_int 0)))
(clobber (match_scratch:SI 0 "=r"))]
"ix86_match_ccmode (insn, CCNOmode)
@@ -15342,7 +15342,7 @@
operands[0] = expand_simple_binop (Pmode, code, op0, op1, NULL_RTX, 0,
OPTAB_DIRECT);
}
-
+
/* For NativeClient, force address into register and wrap it into UNSPEC. */
if (TARGET_NACL)
{
@@ -15633,7 +15633,7 @@
/* In order to give reg-stack an easier job in validating two
coprocessor registers as containing a possible return value,
simply pretend the untyped call returns a complex long double
- value.
+ value.
We can't use SSE_REGPARM_MAX here since callee is unprototyped
and should have the default ABI. */
@@ -20558,8 +20558,8 @@
(define_expand "movsicc"
[(set (match_operand:SI 0 "register_operand" "")
(if_then_else:SI (match_operand 1 "comparison_operator" "")
- (match_operand:SI 2 "general_operand" "")
- (match_operand:SI 3 "general_operand" "")))]
+ (match_operand:SI 2 "x86_64_general_operand" "")
+ (match_operand:SI 3 "x86_64_general_operand" "")))]
""
"if (ix86_expand_int_movcc (operands)) DONE; else FAIL;")
@@ -21613,7 +21613,7 @@
[(match_dup 0)
(match_operand 2 "memory_operand" "")]))]
"REGNO (operands[0]) != REGNO (operands[1])
- && ((MMX_REG_P (operands[0]) && MMX_REG_P (operands[1]))
+ && ((MMX_REG_P (operands[0]) && MMX_REG_P (operands[1]))
|| (SSE_REG_P (operands[0]) && SSE_REG_P (operands[1])))"
[(set (match_dup 0) (match_dup 2))
(set (match_dup 0)
