commit bc8a494beaa6e47877905cfd9dc485ff99c77af0
author Fabian Sommer <fabiansommer@chromium.org> Thu Mar 02 12:03:38 2023
committer Fabian Sommer <fabiansommer@chromium.org> Mon Apr 03 11:50:50 2023
tree 849e1b1f344f08864b4b8a82c4a73da95f150f90
parent 0c5ca942a02346a92d21d9d4a7e5a26b0cb3cde0

Fix compile errors after rebase

Use llvm/TargetParser/Triple.h instead of llvm/ADT/Triple.h
Use getX86SubSuperRegister instead of getX86SubSuperRegisterOrZero

llvm/lib/MC/MCNaCl.cpp

diff --git a/llvm/lib/MC/MCNaCl.cpp b/llvm/lib/MC/MCNaCl.cpp
index d9249c7..3ef7e37 100644
--- a/llvm/lib/MC/MCNaCl.cpp
+++ b/llvm/lib/MC/MCNaCl.cpp
@@ -9,7 +9,6 @@
 //===----------------------------------------------------------------------===//
 
 #include "llvm/MC/MCNaCl.h"
-#include "llvm/ADT/Triple.h"
 #include "llvm/BinaryFormat/ELF.h"
 #include "llvm/MC/MCContext.h"
 #include "llvm/MC/MCNaClExpander.h"
@@ -18,6 +17,7 @@
 #include "llvm/MC/TargetRegistry.h"
 #include "llvm/Support/Alignment.h"
 #include "llvm/Support/CommandLine.h"
+#include "llvm/TargetParser/Triple.h"
 
 static const char NoteNamespace[] = "NaCl";
 

llvm/lib/Target/X86/MCTargetDesc/X86MCNaClExpander.cpp

diff --git a/llvm/lib/Target/X86/MCTargetDesc/X86MCNaClExpander.cpp b/llvm/lib/Target/X86/MCTargetDesc/X86MCNaClExpander.cpp
index cb5ff2e..5b6cd8c 100644
--- a/llvm/lib/Target/X86/MCTargetDesc/X86MCNaClExpander.cpp
+++ b/llvm/lib/Target/X86/MCTargetDesc/X86MCNaClExpander.cpp
@@ -51,7 +51,7 @@
 MCRegister getReg32(MCRegister Reg) {
   switch (Reg) {
   default:
-    return getX86SubSuperRegisterOrZero(Reg, 32, false);
+    return getX86SubSuperRegister(Reg, 32, false);
   case X86::IP:
   case X86::EIP:
     return X86::EIP;
@@ -63,7 +63,7 @@
 MCRegister getReg64(MCRegister Reg) {
   switch (Reg) {
   default:
-    return getX86SubSuperRegisterOrZero(Reg, 64, false);
+    return getX86SubSuperRegister(Reg, 64, false);
   case X86::IP:
   case X86::EIP:
   case X86::RIP:
@@ -620,7 +620,7 @@
     RotateRegister = SandboxedInst.getOperand(0).getReg();
     SandboxedInst.setOpcode(X86::MOV8rm);
     SandboxedInst.getOperand(0).setReg(
-        getX86SubSuperRegisterOrZero(RotateRegister, 8, /*High=*/false));
+        getX86SubSuperRegister(RotateRegister, 8, /*High=*/false));
   } else if (InstNeedsSandboxing &&
              (SandboxedInst.getOpcode() == X86::MOV8mr_NOREX ||
               SandboxedInst.getOpcode() == X86::MOV8mr) &&
@@ -628,7 +628,7 @@
     RotateRegister = SandboxedInst.getOperand(5).getReg();
     SandboxedInst.setOpcode(X86::MOV8mr);
     SandboxedInst.getOperand(5).setReg(
-        getX86SubSuperRegisterOrZero(RotateRegister, 8, /*High=*/false));
+        getX86SubSuperRegister(RotateRegister, 8, /*High=*/false));
   }
 
   if (RotateRegister != X86::NoRegister) {