src/assembler-arm-inl.h

// Copyright 2007-2008 Google Inc. All Rights Reserved.
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// modification, are permitted provided that the following conditions are
// met:
//
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//     * Redistributions in binary form must reproduce the above
//       copyright notice, this list of conditions and the following
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#ifndef V8_ASSEMBLER_ARM_INL_H_
#define V8_ASSEMBLER_ARM_INL_H_

#include "assembler-arm.h"
#include "cpu.h"


namespace v8 { namespace internal {

Condition NegateCondition(Condition cc) {
  ASSERT(cc != al);
  return static_cast<Condition>(cc ^ ne);
}


void RelocInfo::apply(int delta) {
  // We do not use pc relative addressing on ARM, so there is nothing to do.
}


Address RelocInfo::target_address() {
  ASSERT(is_code_target(rmode_));
  return Assembler::target_address_at(pc_);
}


void RelocInfo::set_target_address(Address target) {
  ASSERT(is_code_target(rmode_));
  Assembler::set_target_address_at(pc_, target);
}


Object* RelocInfo::target_object() {
  ASSERT(is_code_target(rmode_) || rmode_ == embedded_object);
  return reinterpret_cast<Object*>(Assembler::target_address_at(pc_));
}


Object** RelocInfo::target_object_address() {
  ASSERT(is_code_target(rmode_) || rmode_ == embedded_object);
  return reinterpret_cast<Object**>(Assembler::target_address_address_at(pc_));
}


void RelocInfo::set_target_object(Object* target) {
  ASSERT(is_code_target(rmode_) || rmode_ == embedded_object);
  Assembler::set_target_address_at(pc_, reinterpret_cast<Address>(target));
}


Address* RelocInfo::target_reference_address() {
  ASSERT(rmode_ == external_reference);
  return reinterpret_cast<Address*>(pc_);
}


Address RelocInfo::call_address() {
  ASSERT(is_call_instruction());
  UNIMPLEMENTED();
  return NULL;
}


void RelocInfo::set_call_address(Address target) {
  ASSERT(is_call_instruction());
  UNIMPLEMENTED();
}


Object* RelocInfo::call_object() {
  ASSERT(is_call_instruction());
  UNIMPLEMENTED();
  return NULL;
}


Object** RelocInfo::call_object_address() {
  ASSERT(is_call_instruction());
  UNIMPLEMENTED();
  return NULL;
}


void RelocInfo::set_call_object(Object* target) {
  ASSERT(is_call_instruction());
  UNIMPLEMENTED();
}


bool RelocInfo::is_call_instruction() {
  UNIMPLEMENTED();
  return false;
}


Operand::Operand(int32_t immediate, RelocMode rmode)  {
  rm_ = no_reg;
  imm32_ = immediate;
  rmode_ = rmode;
}


Operand::Operand(const char* s) {
  rm_ = no_reg;
  imm32_ = reinterpret_cast<int32_t>(s);
  rmode_ = embedded_string;
}


Operand::Operand(const ExternalReference& f)  {
  rm_ = no_reg;
  imm32_ = reinterpret_cast<int32_t>(f.address());
  rmode_ = external_reference;
}


Operand::Operand(Object** opp) {
  rm_ = no_reg;
  imm32_ = reinterpret_cast<int32_t>(opp);
  rmode_ = no_reloc;
}


Operand::Operand(Context** cpp) {
  rm_ = no_reg;
  imm32_ = reinterpret_cast<int32_t>(cpp);
  rmode_ = no_reloc;
}


Operand::Operand(Smi* value) {
  rm_ = no_reg;
  imm32_ =  reinterpret_cast<intptr_t>(value);
  rmode_ = no_reloc;
}


Operand::Operand(Register rm) {
  rm_ = rm;
  rs_ = no_reg;
  shift_op_ = LSL;
  shift_imm_ = 0;
}


void Assembler::CheckBuffer() {
  if (buffer_space() <= kGap) {
    GrowBuffer();
  }
  if (pc_offset() > next_buffer_check_) {
    CheckConstPool(false, true);
  }
}


void Assembler::emit(Instr x) {
  CheckBuffer();
  *reinterpret_cast<Instr*>(pc_) = x;
  pc_ += kInstrSize;
}


Address Assembler::target_address_address_at(Address pc) {
  Instr instr = Memory::int32_at(pc);
  // Verify that the instruction at pc is a ldr<cond> <Rd>, [pc +/- offset_12].
  ASSERT((instr & 0x0f7f0000) == 0x051f0000);
  int offset = instr & 0xfff;  // offset_12 is unsigned
  if ((instr & (1 << 23)) == 0) offset = -offset;  // U bit defines offset sign
  // Verify that the constant pool comes after the instruction referencing it.
  ASSERT(offset >= -4);
  return pc + offset + 8;
}


Address Assembler::target_address_at(Address pc) {
  return Memory::Address_at(target_address_address_at(pc));
}


void Assembler::set_target_address_at(Address pc, Address target) {
  Memory::Address_at(target_address_address_at(pc)) = target;
  // Intuitively, we would think it is necessary to flush the instruction cache
  // after patching a target address in the code as follows:
  //   CPU::FlushICache(pc, sizeof(target));
  // However, on ARM, no instruction was actually patched by the assignment
  // above; the target address is not part of an instruction, it is patched in
  // the constant pool and is read via a data access; the instruction accessing
  // this address in the constant pool remains unchanged.
}

} }  // namespace v8::internal

#endif  // V8_ASSEMBLER_ARM_INL_H_