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| <pending_commit branch="chromeos-3.18" change_id="I5cd8df904a75780310dbe876181077e5f7613f3d" commit="d5c5c280a64346c1598a78c4310554a2cd333630" commit_message="UPSTREAM: mmc: sdhci: Simplify use of tuning timer The tuning timer is always used if the tuning mode is 1 and there is a tuning count, irrespective of whether this is the first call, or any subsequent call. Consequently the logic to start the timer can be simplified. Signed-off-by: Adrian Hunter <adrian.hunter@intel.com> Reviewed-by: Aaron Lu <aaron.lu@intel.com> Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org> (cherry picked from commit 38e40bf5db9d5b8cbaeca9a78ee17f38473dd78d) Signed-off-by: Marc Herbert <marc.herbert@intel.com> Conflicts: drivers/mmc/host/sdhci.c (minor text conflict with CHROMIUM: sdhci: tegra: tuning iterations based on speed) BUG=chrome-os-partner:40410 TEST=With this whole HS400 series applied: TEST=on a system with HS400 controller(s), it/they initialize with the following log message: INFO kernel: [ 103.601747] mmc0: new HS400 MMC card at address 0001 TEST=run SD/eMMC test plan: higher eMMC throughput after change, and no other change. TEST=same on another system with no HS400: no observable change at all. Change-Id: I5cd8df904a75780310dbe876181077e5f7613f3d Reviewed-on: https://chromium-review.googlesource.com/276392 Commit-Ready: Marc Herbert <marc.herbert@intel.com> Tested-by: Philip Hanson <philip.hanson@intel.com> Reviewed-by: Derek Basehore <dbasehore@chromium.org> " fail_count="0" gerrit_number="276392" owner_email="marc.herbert@intel.com" pass_count="0" patch_number="5" project="chromiumos/third_party/kernel" project_url="https://chromium-review.googlesource.com/chromiumos/third_party/kernel" ref="refs/changes/92/276392/5" remote="cros" total_fail_count="0"/><pending_commit branch="chromeos-3.18" change_id="I0a26f0aedc04d6e4f1a516e8a7ea9769dcf4ff9d" commit="f3e83f8a442bb1180989a4aa3731ee4b4af170ee" commit_message="UPSTREAM: mmc: sdhci: Disable re-tuning for HS400 Re-tuning for HS400 mode must be done in HS200 mode. Currently there is no support for that. That needs to be reflected in the code. Specifically, if tuning is executed in HS400 mode then return an error, and do not start the tuning timer if HS200 tuning is being done prior to switching to HS400. Note that periodic re-tuning is not expected to be needed for HS400 but re-tuning is still needed after the host controller has lost power. In the case of suspend/resume that is not necessary because the card is fully re-initialised. That just leaves runtime suspend/resume with no support for HS400 re-tuning. Signed-off-by: Adrian Hunter <adrian.hunter@intel.com> Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org> (cherry picked from commit b5540ce1512eede3bed68ab1e9949df9ad556091) Signed-off-by: Marc Herbert <marc.herbert@intel.com> BUG=chrome-os-partner:40410 TEST=With this whole HS400 series applied: TEST=on a system with HS400 controller(s), it/they initialize with the following log message: INFO kernel: [ 103.601747] mmc0: new HS400 MMC card at address 0001 TEST=run SD/eMMC test plan: higher eMMC throughput after change, and no other change. TEST=same on another system with no HS400: no observable change at all. Change-Id: I0a26f0aedc04d6e4f1a516e8a7ea9769dcf4ff9d Reviewed-on: https://chromium-review.googlesource.com/276393 Commit-Ready: Marc Herbert <marc.herbert@intel.com> Tested-by: Philip Hanson <philip.hanson@intel.com> Reviewed-by: Derek Basehore <dbasehore@chromium.org> " fail_count="2" gerrit_number="276393" owner_email="marc.herbert@intel.com" pass_count="0" patch_number="5" project="chromiumos/third_party/kernel" project_url="https://chromium-review.googlesource.com/chromiumos/third_party/kernel" ref="refs/changes/93/276393/5" remote="cros" total_fail_count="5"/><pending_commit branch="chromeos-3.18" change_id="I6f02578327cf31589fdb441769404802a289226a" commit="88d8c75897a8740c8be18458a70db6d4477da7b9" commit_message="UPSTREAM: mmc: core: consistent handling of initial values mmc_do_hw_reset(), mmc_power_up() and mmc_power_off() all set similar initial values for bus_mode, bus_width, chip_select and timing. Let's make this handling simpler and more consistent by sticking them together in a common function. This will introduce small changes in behavior in the following places: mmc_power_off(): For SPI hosts, explicitly set bus_mode = MMC_BUSMODE_PUSHPULL and chip_select = MMC_CS_HIGH, before we left them as they were. For non-SPI hosts, set bus_mode = MMC_BUSMODE_PUSHPULL instead of MMC_BUSMODE_OPENDRAIN as before. These two changes should not be a problem since the device will be powered off anyway. mmc_do_hw_reset(): Always set bus_mode = MMC_BUSMODE_PUSHPULL, as required by SD/SDIO cards. MMC cards require MMC_BUSMODE_OPENDRAIN, but this is taken care of by mmc_init_card() and mmc_attach_mmc(). Signed-off-by: Johan Rudholm <johanru@axis.com> Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org> (cherry picked from commit 2d079c43bc5ade7b41610b356bf117e14037a584) Signed-off-by: Marc Herbert <marc.herbert@intel.com> BUG=chrome-os-partner:40410 TEST=With this whole HS400 series applied: TEST=on a system with HS400 controller(s), it/they initialize with the following log message: INFO kernel: [ 103.601747] mmc0: new HS400 MMC card at address 0001 TEST=run SD/eMMC test plan: higher eMMC throughput after change, and no other change. TEST=same on another system with no HS400: no observable change at all. Change-Id: I6f02578327cf31589fdb441769404802a289226a Reviewed-on: https://chromium-review.googlesource.com/276394 Commit-Ready: Marc Herbert <marc.herbert@intel.com> Tested-by: Philip Hanson <philip.hanson@intel.com> Reviewed-by: Derek Basehore <dbasehore@chromium.org> " fail_count="2" gerrit_number="276394" owner_email="marc.herbert@intel.com" pass_count="0" patch_number="5" project="chromiumos/third_party/kernel" project_url="https://chromium-review.googlesource.com/chromiumos/third_party/kernel" ref="refs/changes/94/276394/5" remote="cros" total_fail_count="2"/><pending_commit branch="chromeos-3.18" change_id="I39a4a7862b3974f64d5eb472da39330d0c8a4492" commit="8a8cde1066b6b813c2e49c2a41ad1f88265e6894" commit_message="UPSTREAM: mmc: core: Simplify by adding mmc_execute_tuning() For each MMC, SD and SDIO there is code that holds the clock, calls ops->execute_tuning, and releases the clock. Simplify the code a bit by providing a separate function to do that. Signed-off-by: Adrian Hunter <adrian.hunter@intel.com> Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org> (cherry picked from commit 63e415c64003fd62a302a1dc19f082e2c6f1b7cc) Signed-off-by: Marc Herbert <marc.herbert@intel.com> BUG=chrome-os-partner:40410 TEST=With this whole HS400 series applied: TEST=on a system with HS400 controller(s), it/they initialize with the following log message: INFO kernel: [ 103.601747] mmc0: new HS400 MMC card at address 0001 TEST=run SD/eMMC test plan: higher eMMC throughput after change, and no other change. TEST=same on another system with no HS400: no observable change at all. Change-Id: I39a4a7862b3974f64d5eb472da39330d0c8a4492 Reviewed-on: https://chromium-review.googlesource.com/276395 Commit-Ready: Marc Herbert <marc.herbert@intel.com> Tested-by: Philip Hanson <philip.hanson@intel.com> Reviewed-by: Derek Basehore <dbasehore@chromium.org> " fail_count="2" gerrit_number="276395" owner_email="marc.herbert@intel.com" pass_count="0" patch_number="5" project="chromiumos/third_party/kernel" project_url="https://chromium-review.googlesource.com/chromiumos/third_party/kernel" ref="refs/changes/95/276395/5" remote="cros" total_fail_count="2"/><pending_commit branch="chromeos-3.18" change_id="Icbee2716ecdaafb190051fa7bc7feef18ebddef1" commit="0868aec106fc14c65203ac21d91212752fdc1eac" commit_message="UPSTREAM: mmc: core: Move mmc_card_removed() into mmc_start_request() Both callers of mmc_start_request() call mmc_card_removed() so move that call into mmc_start_request(). This patch is preparation for adding re-tuning support. Signed-off-by: Adrian Hunter <adrian.hunter@intel.com> Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org> (cherry picked from commit f100c1c2b55b08d419b7cd3985cc144b41ce9a1f) Signed-off-by: Marc Herbert <marc.herbert@intel.com> BUG=chrome-os-partner:40410 TEST=With this whole HS400 series applied: TEST=on a system with HS400 controller(s), it/they initialize with the following log message: INFO kernel: [ 103.601747] mmc0: new HS400 MMC card at address 0001 TEST=run SD/eMMC test plan: higher eMMC throughput after change, and no other change. TEST=same on another system with no HS400: no observable change at all. Change-Id: Icbee2716ecdaafb190051fa7bc7feef18ebddef1 Reviewed-on: https://chromium-review.googlesource.com/276396 Commit-Ready: Marc Herbert <marc.herbert@intel.com> Tested-by: Philip Hanson <philip.hanson@intel.com> Reviewed-by: Derek Basehore <dbasehore@chromium.org> " fail_count="2" gerrit_number="276396" owner_email="marc.herbert@intel.com" pass_count="0" patch_number="5" project="chromiumos/third_party/kernel" project_url="https://chromium-review.googlesource.com/chromiumos/third_party/kernel" ref="refs/changes/96/276396/5" remote="cros" total_fail_count="2"/><pending_commit branch="chromeos-3.18" change_id="I5b33e78f81f4e5419edb3579064f37924c5b15b8" commit="625dc8c640343033da9b8c87f75b9419c610400f" commit_message="UPSTREAM: mmc: sdhci: Always init buf_ready_int There is no point making the initialization of buf_ready_int conditional on host version. Simplify by just doing it always. Note that the other conditional initializations will be removed when the new way of doing re-tuning is taken into use. Signed-off-by: Adrian Hunter <adrian.hunter@intel.com> Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org> (cherry picked from commit 250fb7b45031fd56f5f54da27ffc6fe05abea98e) Signed-off-by: Marc Herbert <marc.herbert@intel.com> BUG=chrome-os-partner:40410 TEST=With this whole HS400 series applied: TEST=on a system with HS400 controller(s), it/they initialize with the following log message: INFO kernel: [ 103.601747] mmc0: new HS400 MMC card at address 0001 TEST=run SD/eMMC test plan: higher eMMC throughput after change, and no other change. TEST=same on another system with no HS400: no observable change at all. Change-Id: I5b33e78f81f4e5419edb3579064f37924c5b15b8 Reviewed-on: https://chromium-review.googlesource.com/276397 Commit-Ready: Marc Herbert <marc.herbert@intel.com> Tested-by: Philip Hanson <philip.hanson@intel.com> Reviewed-by: Derek Basehore <dbasehore@chromium.org> " fail_count="2" gerrit_number="276397" owner_email="marc.herbert@intel.com" pass_count="0" patch_number="5" project="chromiumos/third_party/kernel" project_url="https://chromium-review.googlesource.com/chromiumos/third_party/kernel" ref="refs/changes/97/276397/5" remote="cros" total_fail_count="5"/><pending_commit branch="chromeos-3.18" change_id="I712d58df02a84c7c97051cad3b66a023d59155e6" commit="9d6052ba893934dfb8775149c968bc95e8b7d748" commit_message="BACKPORT: mmc: sdhci: Remove the sdhci exported header file Since there no users of the struct sdhci_host, but the shdci host drivers themselves, let's move the definition of it to the local sdhci header. The exported sdhci header then becomes empty, so let's remove it. Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org> (cherry picked from commit 83f13cc9af9822cacc6644ee3c63c81f3930ddad) Signed-off-by: Marc Herbert <marc.herbert@intel.com> Conflicts: include/linux/mmc/sdhci.h (pure code move with zero change: re-created the move. Moved CHROMIUM quirks2 to the end of the bit range to minimize future conflicts) BUG=chrome-os-partner:40410 TEST=With this whole HS400 series applied: TEST=on a system with HS400 controller(s), it/they initialize with the following log message: INFO kernel: [ 103.601747] mmc0: new HS400 MMC card at address 0001 TEST=run SD/eMMC test plan: higher eMMC throughput after change, and no other change. TEST=same on another system with no HS400: no observable change at all. Change-Id: I712d58df02a84c7c97051cad3b66a023d59155e6 Reviewed-on: https://chromium-review.googlesource.com/276398 Commit-Ready: Marc Herbert <marc.herbert@intel.com> Tested-by: Philip Hanson <philip.hanson@intel.com> Reviewed-by: Derek Basehore <dbasehore@chromium.org> " fail_count="0" gerrit_number="276398" owner_email="marc.herbert@intel.com" pass_count="0" patch_number="5" project="chromiumos/third_party/kernel" project_url="https://chromium-review.googlesource.com/chromiumos/third_party/kernel" ref="refs/changes/98/276398/5" remote="cros" total_fail_count="3"/><pending_commit branch="chromeos-3.18" change_id="I70ae79347fa0d2c484f6c2808899d3be6f969445" commit="dd0af0d13af80f786a1f87f16bc72e31320b3db2" commit_message="UPSTREAM: mmc: host: Add facility to support re-tuning Currently, there is core support for tuning during initialization. There can also be a need to re-tune periodically (e.g. sdhci) or to re-tune after the host controller is powered off (e.g. after PM runtime suspend / resume) or to re-tune in response to CRC errors. The main requirements for re-tuning are: - ability to enable / disable re-tuning - ability to flag that re-tuning is needed - ability to re-tune before any request - ability to hold off re-tuning if the card is busy - ability to hold off re-tuning if re-tuning is in progress - ability to run a re-tuning timer To support those requirements 7 members are added to struct mmc_host: unsigned int can_retune:1; /* re-tuning can be used */ unsigned int doing_retune:1; /* re-tuning in progress */ unsigned int retune_now:1; /* do re-tuning at next req */ int need_retune; /* re-tuning is needed */ int hold_retune; /* hold off re-tuning */ unsigned int retune_period; /* re-tuning period in secs */ struct timer_list retune_timer; /* for periodic re-tuning */ need_retune is an integer so it can be set without needing synchronization. hold_retune is a integer to allow nesting. Various simple functions are provided to set / clear those variables. Subsequent patches take those functions into use. Signed-off-by: Adrian Hunter <adrian.hunter@intel.com> Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org> (cherry picked from commit dfa13ebbe3340e538b988f5608efd9ff2ca7fc35) Signed-off-by: Marc Herbert <marc.herbert@intel.com> BUG=chrome-os-partner:40410 TEST=With this whole HS400 series applied: TEST=on a system with HS400 controller(s), it/they initialize with the following log message: INFO kernel: [ 103.601747] mmc0: new HS400 MMC card at address 0001 TEST=run SD/eMMC test plan: higher eMMC throughput after change, and no other change. TEST=same on another system with no HS400: no observable change at all. Change-Id: I70ae79347fa0d2c484f6c2808899d3be6f969445 Reviewed-on: https://chromium-review.googlesource.com/276399 Commit-Ready: Marc Herbert <marc.herbert@intel.com> Tested-by: Philip Hanson <philip.hanson@intel.com> Reviewed-by: Derek Basehore <dbasehore@chromium.org> " fail_count="2" gerrit_number="276399" owner_email="marc.herbert@intel.com" pass_count="0" patch_number="5" project="chromiumos/third_party/kernel" project_url="https://chromium-review.googlesource.com/chromiumos/third_party/kernel" ref="refs/changes/99/276399/5" remote="cros" total_fail_count="2"/><pending_commit branch="chromeos-3.18" change_id="I8e95c2c8604a7002fa79164a5160c7cbd6fbc82d" commit="e950c7b1ccaa57535a8ac6e9ecebcb14c3ca9ed7" commit_message="UPSTREAM: mmc: core: Enable / disable re-tuning Enable re-tuning when tuning is executed and disable re-tuning when card is no longer initialized. In the case of SDIO suspend, the card can keep power. In that case, re-tuning need not be disabled, but, if a re-tuning timer is being used, ensure it is disabled and assume that re-tuning will be needed upon resume since it is not known how long the suspend will last. Signed-off-by: Adrian Hunter <adrian.hunter@intel.com> Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org> (cherry picked from commit 79d5a65aeea43920bf3ff60791f317570dd6f54f) Signed-off-by: Marc Herbert <marc.herbert@intel.com> BUG=chrome-os-partner:40410 TEST=With this whole HS400 series applied: TEST=on a system with HS400 controller(s), it/they initialize with the following log message: INFO kernel: [ 103.601747] mmc0: new HS400 MMC card at address 0001 TEST=run SD/eMMC test plan: higher eMMC throughput after change, and no other change. TEST=same on another system with no HS400: no observable change at all. Change-Id: I8e95c2c8604a7002fa79164a5160c7cbd6fbc82d Reviewed-on: https://chromium-review.googlesource.com/276400 Commit-Ready: Marc Herbert <marc.herbert@intel.com> Tested-by: Philip Hanson <philip.hanson@intel.com> Reviewed-by: Derek Basehore <dbasehore@chromium.org> " fail_count="2" gerrit_number="276400" owner_email="marc.herbert@intel.com" pass_count="0" patch_number="5" project="chromiumos/third_party/kernel" project_url="https://chromium-review.googlesource.com/chromiumos/third_party/kernel" ref="refs/changes/00/276400/5" remote="cros" total_fail_count="5"/><pending_commit branch="chromeos-3.18" change_id="Iaef1f1ef8277d754997d2602da05701e8f29fa07" commit="d626e507d4eeb920fc853a006bfb88979685194e" commit_message="UPSTREAM: mmc: core: Add support for re-tuning before each request At the start of each request, re-tune if needed and then hold off re-tuning again until the request is done. Note that though there is one function that starts requests (mmc_start_request) there are two that wait for the request to be done (mmc_wait_for_req_done and mmc_wait_for_data_req_done). Also note that mmc_wait_for_data_req_done can return even when the request is not done (which allows the block driver to prepare a newly arrived request while still waiting for the previous request). This patch ensures re-tuning is held for the duration of a request. Subsequent patches will also hold re-tuning at other times when it might cause a conflict. In addition, possibly a command is failing because re-tuning is needed. Use mmc_retune_recheck() to check re-tuning. At that point re-tuning is held, at least by the request, so mmc_retune_recheck() flags host->retune_now if the hold count is 1. Signed-off-by: Adrian Hunter <adrian.hunter@intel.com> Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org> (cherry picked from commit 90a81489b0a9d7b56df2dcf68498fd3a03deb354) Signed-off-by: Marc Herbert <marc.herbert@intel.com> BUG=chrome-os-partner:40410 TEST=With this whole HS400 series applied: TEST=on a system with HS400 controller(s), it/they initialize with the following log message: INFO kernel: [ 103.601747] mmc0: new HS400 MMC card at address 0001 TEST=run SD/eMMC test plan: higher eMMC throughput after change, and no other change. TEST=same on another system with no HS400: no observable change at all. Change-Id: Iaef1f1ef8277d754997d2602da05701e8f29fa07 Reviewed-on: https://chromium-review.googlesource.com/276401 Commit-Ready: Marc Herbert <marc.herbert@intel.com> Tested-by: Philip Hanson <philip.hanson@intel.com> Reviewed-by: Derek Basehore <dbasehore@chromium.org> " fail_count="2" gerrit_number="276401" owner_email="marc.herbert@intel.com" pass_count="0" patch_number="5" project="chromiumos/third_party/kernel" project_url="https://chromium-review.googlesource.com/chromiumos/third_party/kernel" ref="refs/changes/01/276401/5" remote="cros" total_fail_count="5"/><pending_commit branch="chromeos-3.18" change_id="Ie6ef4e651fc142c8b367f13dbaeab7ed15453a6c" commit="f1138b3cf264e9de587f966003e51e7239110219" commit_message="UPSTREAM: mmc: core: Hold re-tuning during switch commands Hold re-tuning during switch commands to prevent it from conflicting with the busy state or the CMD13 verification. Signed-off-by: Adrian Hunter <adrian.hunter@intel.com> Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org> (cherry picked from commit c6dbab9cb58f5519c65867c4b371e1ee730a8451) Signed-off-by: Marc Herbert <marc.herbert@intel.com> BUG=chrome-os-partner:40410 TEST=With this whole HS400 series applied: TEST=on a system with HS400 controller(s), it/they initialize with the following log message: INFO kernel: [ 103.601747] mmc0: new HS400 MMC card at address 0001 TEST=run SD/eMMC test plan: higher eMMC throughput after change, and no other change. TEST=same on another system with no HS400: no observable change at all. Change-Id: Ie6ef4e651fc142c8b367f13dbaeab7ed15453a6c Reviewed-on: https://chromium-review.googlesource.com/276402 Commit-Ready: Marc Herbert <marc.herbert@intel.com> Tested-by: Philip Hanson <philip.hanson@intel.com> Reviewed-by: Derek Basehore <dbasehore@chromium.org> " fail_count="2" gerrit_number="276402" owner_email="marc.herbert@intel.com" pass_count="0" patch_number="5" project="chromiumos/third_party/kernel" project_url="https://chromium-review.googlesource.com/chromiumos/third_party/kernel" ref="refs/changes/02/276402/5" remote="cros" total_fail_count="5"/><pending_commit branch="chromeos-3.18" change_id="I9cc6d74aa52e9328ae8e7d894c3bbd0a9d0e79bd" commit="f11da8d0dad47bb6772bc29a94b2a147c1df95e8" commit_message="BACKPORT: mmc: core: Hold re-tuning during erase commands Hold re-tuning during erase commands to prevent it from conflicting with the sequence of commands. Signed-off-by: Adrian Hunter <adrian.hunter@intel.com> Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org> (cherry picked from commit 8f11d1064e01e1c8bf33ffef86072c2cb0c05b8c) Signed-off-by: Marc Herbert <marc.herbert@intel.com> Conflicts: drivers/mmc/core/core.c (Context conflict with ChromeOS tracepoints: put tuning inside tracepoints) BUG=chrome-os-partner:40410 TEST=With this whole HS400 series applied: TEST=on a system with HS400 controller(s), it/they initialize with the following log message: INFO kernel: [ 103.601747] mmc0: new HS400 MMC card at address 0001 TEST=run SD/eMMC test plan: higher eMMC throughput after change, and no other change. TEST=same on another system with no HS400: no observable change at all. Change-Id: I9cc6d74aa52e9328ae8e7d894c3bbd0a9d0e79bd Reviewed-on: https://chromium-review.googlesource.com/276403 Commit-Ready: Marc Herbert <marc.herbert@intel.com> Tested-by: Philip Hanson <philip.hanson@intel.com> Reviewed-by: Derek Basehore <dbasehore@chromium.org> " fail_count="2" gerrit_number="276403" owner_email="marc.herbert@intel.com" pass_count="0" patch_number="5" project="chromiumos/third_party/kernel" project_url="https://chromium-review.googlesource.com/chromiumos/third_party/kernel" ref="refs/changes/03/276403/5" remote="cros" total_fail_count="2"/><pending_commit branch="chromeos-3.18" change_id="I030ad335569098b1ada7b4aa27612cc8a0ddb8cb" commit="11f9f4a471a655a05f6ce30f1570b78562122d3e" commit_message="UPSTREAM: mmc: core: Hold re-tuning while bkops ongoing Hold re-tuning during bkops to prevent it from conflicting with the busy state. Signed-off-by: Adrian Hunter <adrian.hunter@intel.com> Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org> (cherry picked from commit 66073d8671c41fb0bc8c6e36531b4eafb70c990e) Signed-off-by: Marc Herbert <marc.herbert@intel.com> BUG=chrome-os-partner:40410 TEST=With this whole HS400 series applied: TEST=on a system with HS400 controller(s), it/they initialize with the following log message: INFO kernel: [ 103.601747] mmc0: new HS400 MMC card at address 0001 TEST=run SD/eMMC test plan: higher eMMC throughput after change, and no other change. TEST=same on another system with no HS400: no observable change at all. Change-Id: I030ad335569098b1ada7b4aa27612cc8a0ddb8cb Reviewed-on: https://chromium-review.googlesource.com/276404 Commit-Ready: Marc Herbert <marc.herbert@intel.com> Tested-by: Philip Hanson <philip.hanson@intel.com> Reviewed-by: Derek Basehore <dbasehore@chromium.org> " fail_count="2" gerrit_number="276404" owner_email="marc.herbert@intel.com" pass_count="0" patch_number="5" project="chromiumos/third_party/kernel" project_url="https://chromium-review.googlesource.com/chromiumos/third_party/kernel" ref="refs/changes/04/276404/5" remote="cros" total_fail_count="2"/><pending_commit branch="chromeos-3.18" change_id="I490865cb865c8cb0e3f0766905dd88e9d06a52cf" commit="0ad5c4d65b43035c93da52fb94a79485f248410d" commit_message="UPSTREAM: mmc: mmc: Hold re-tuning in mmc_sleep() The sleep command is issued after deselecting the card, but re-tuning won't work on a deselected card so re-tuning must be held. Signed-off-by: Adrian Hunter <adrian.hunter@intel.com> Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org> (cherry picked from commit 436f8daa6f5a2943a20df8f3447da250b46f0d87) Signed-off-by: Marc Herbert <marc.herbert@intel.com> BUG=chrome-os-partner:40410 TEST=With this whole HS400 series applied: TEST=on a system with HS400 controller(s), it/they initialize with the following log message: INFO kernel: [ 103.601747] mmc0: new HS400 MMC card at address 0001 TEST=run SD/eMMC test plan: higher eMMC throughput after change, and no other change. TEST=same on another system with no HS400: no observable change at all. Change-Id: I490865cb865c8cb0e3f0766905dd88e9d06a52cf Reviewed-on: https://chromium-review.googlesource.com/276405 Commit-Ready: Marc Herbert <marc.herbert@intel.com> Tested-by: Philip Hanson <philip.hanson@intel.com> Reviewed-by: Derek Basehore <dbasehore@chromium.org> " fail_count="2" gerrit_number="276405" owner_email="marc.herbert@intel.com" pass_count="0" patch_number="5" project="chromiumos/third_party/kernel" project_url="https://chromium-review.googlesource.com/chromiumos/third_party/kernel" ref="refs/changes/05/276405/5" remote="cros" total_fail_count="2"/><pending_commit branch="chromeos-3.18" change_id="I8ad688b432e384ceb071f54ec743f97155ed6eef" commit="53d0ea1d8a32e25390f1598e89fe1b524a99d1af" commit_message="UPSTREAM: mmc: core: Separate out the mmc_switch status check so it can be re-used Make a separate function to do the mmc_switch status check so it can be re-used. This is preparation for adding support for HS400 re-tuning. Signed-off-by: Adrian Hunter <adrian.hunter@intel.com> Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org> (cherry picked from commit ed16f58dc00d47439c201ab18ca4d981210bcafd) Signed-off-by: Marc Herbert <marc.herbert@intel.com> BUG=chrome-os-partner:40410 TEST=With this whole HS400 series applied: TEST=on a system with HS400 controller(s), it/they initialize with the following log message: INFO kernel: [ 103.601747] mmc0: new HS400 MMC card at address 0001 TEST=run SD/eMMC test plan: higher eMMC throughput after change, and no other change. TEST=same on another system with no HS400: no observable change at all. Change-Id: I8ad688b432e384ceb071f54ec743f97155ed6eef Reviewed-on: https://chromium-review.googlesource.com/276406 Commit-Ready: Marc Herbert <marc.herbert@intel.com> Tested-by: Philip Hanson <philip.hanson@intel.com> Reviewed-by: Derek Basehore <dbasehore@chromium.org> " fail_count="2" gerrit_number="276406" owner_email="marc.herbert@intel.com" pass_count="0" patch_number="5" project="chromiumos/third_party/kernel" project_url="https://chromium-review.googlesource.com/chromiumos/third_party/kernel" ref="refs/changes/06/276406/5" remote="cros" total_fail_count="5"/><pending_commit branch="chromeos-3.18" change_id="I5ba763c7c226bc835fd231f741315b10d4d27f3d" commit="f6ddefe271a8081159bccdf46ea97387fcf8d2d0" commit_message="UPSTREAM: mmc: core: Add support for HS400 re-tuning HS400 re-tuning must be done in HS200 mode. Add the ability to switch from HS400 mode to HS200 mode before re-tuning and switch back to HS400 after re-tuning. Signed-off-by: Adrian Hunter <adrian.hunter@intel.com> Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org> (cherry picked from commit 6376f69d20a6905c1d83be451065f70200490b98) Signed-off-by: Marc Herbert <marc.herbert@intel.com> BUG=chrome-os-partner:40410 TEST=With this whole HS400 series applied: TEST=on a system with HS400 controller(s), it/they initialize with the following log message: INFO kernel: [ 103.601747] mmc0: new HS400 MMC card at address 0001 TEST=run SD/eMMC test plan: higher eMMC throughput after change, and no other change. TEST=same on another system with no HS400: no observable change at all. Change-Id: I5ba763c7c226bc835fd231f741315b10d4d27f3d Reviewed-on: https://chromium-review.googlesource.com/276407 Commit-Ready: Marc Herbert <marc.herbert@intel.com> Tested-by: Philip Hanson <philip.hanson@intel.com> Reviewed-by: Derek Basehore <dbasehore@chromium.org> " fail_count="2" gerrit_number="276407" owner_email="marc.herbert@intel.com" pass_count="0" patch_number="5" project="chromiumos/third_party/kernel" project_url="https://chromium-review.googlesource.com/chromiumos/third_party/kernel" ref="refs/changes/07/276407/5" remote="cros" total_fail_count="2"/><pending_commit branch="chromeos-3.18" change_id="I9caf801abc919807d2751b3ba27db72e7f6450e1" commit="2c825b9875bce535ca04de5a75392028bf552866" commit_message="UPSTREAM: mmc: sdhci: Change to new way of doing re-tuning Make use of mmc core support for re-tuning instead of doing it all in the sdhci driver. This patch also changes to flag the need for re-tuning always after runtime suspend when tuning has been used at initialization. Previously it was only done if the re-tuning timer was in use. Signed-off-by: Adrian Hunter <adrian.hunter@intel.com> Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org> (cherry picked from commit 66c39dfc92f9d35ed9f713833156547842086891) Signed-off-by: Marc Herbert <marc.herbert@intel.com> BUG=chrome-os-partner:40410 TEST=With this whole HS400 series applied: TEST=on a system with HS400 controller(s), it/they initialize with the following log message: INFO kernel: [ 103.601747] mmc0: new HS400 MMC card at address 0001 TEST=run SD/eMMC test plan: higher eMMC throughput after change, and no other change. TEST=same on another system with no HS400: no observable change at all. Change-Id: I9caf801abc919807d2751b3ba27db72e7f6450e1 Reviewed-on: https://chromium-review.googlesource.com/276408 Commit-Ready: Marc Herbert <marc.herbert@intel.com> Tested-by: Philip Hanson <philip.hanson@intel.com> Reviewed-by: Derek Basehore <dbasehore@chromium.org> " fail_count="2" gerrit_number="276408" owner_email="marc.herbert@intel.com" pass_count="0" patch_number="5" project="chromiumos/third_party/kernel" project_url="https://chromium-review.googlesource.com/chromiumos/third_party/kernel" ref="refs/changes/08/276408/5" remote="cros" total_fail_count="5"/><pending_commit branch="chromeos-3.18" change_id="Ifc7ed13fdc7afc902529f4e324ef18e2d929f734" commit="24541825d8496c21123aa20581d64350f9fc8356" commit_message="UPSTREAM: mmc: core: Flag re-tuning is needed on CRC errors CRC errors could possibly be alleviated by re-tuning so flag re-tuning needed in those cases. Note this has no effect if re-tuning has not been enabled. Signed-off-by: Adrian Hunter <adrian.hunter@intel.com> Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org> (cherry picked from commit bd11e8bd03cae9e0499c34f67c55408566f6a089) Signed-off-by: Marc Herbert <marc.herbert@intel.com> BUG=chrome-os-partner:40410 TEST=With this whole HS400 series applied: TEST=on a system with HS400 controller(s), it/they initialize with the following log message: INFO kernel: [ 103.601747] mmc0: new HS400 MMC card at address 0001 TEST=run SD/eMMC test plan: higher eMMC throughput after change, and no other change. TEST=same on another system with no HS400: no observable change at all. Change-Id: Ifc7ed13fdc7afc902529f4e324ef18e2d929f734 Reviewed-on: https://chromium-review.googlesource.com/276409 Commit-Ready: Marc Herbert <marc.herbert@intel.com> Tested-by: Philip Hanson <philip.hanson@intel.com> Reviewed-by: Derek Basehore <dbasehore@chromium.org> " fail_count="2" gerrit_number="276409" owner_email="marc.herbert@intel.com" pass_count="0" patch_number="5" project="chromiumos/third_party/kernel" project_url="https://chromium-review.googlesource.com/chromiumos/third_party/kernel" ref="refs/changes/09/276409/5" remote="cros" total_fail_count="5"/><pending_commit branch="chromeos-3.18" change_id="Ia53f2e0088d9a1b10ed7a440d77d566e5161b236" commit="ab09d44175f7697c2835f27d35328c84ec112596" commit_message="UPSTREAM: mmc: block: Check re-tuning in the recovery path If re-tuning is needed, do it in the recovery path to give recovery commands a better chance of success. Signed-off-by: Adrian Hunter <adrian.hunter@intel.com> Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org> (cherry picked from commit 6f398ad2075d9af4158d37442e9ca22e528f06c1) Signed-off-by: Marc Herbert <marc.herbert@intel.com> BUG=chrome-os-partner:40410 TEST=With this whole HS400 series applied: TEST=on a system with HS400 controller(s), it/they initialize with the following log message: INFO kernel: [ 103.601747] mmc0: new HS400 MMC card at address 0001 TEST=run SD/eMMC test plan: higher eMMC throughput after change, and no other change. TEST=same on another system with no HS400: no observable change at all. Change-Id: Ia53f2e0088d9a1b10ed7a440d77d566e5161b236 Reviewed-on: https://chromium-review.googlesource.com/276410 Commit-Ready: Marc Herbert <marc.herbert@intel.com> Tested-by: Philip Hanson <philip.hanson@intel.com> Reviewed-by: Derek Basehore <dbasehore@chromium.org> " fail_count="2" gerrit_number="276410" owner_email="marc.herbert@intel.com" pass_count="0" patch_number="5" project="chromiumos/third_party/kernel" project_url="https://chromium-review.googlesource.com/chromiumos/third_party/kernel" ref="refs/changes/10/276410/5" remote="cros" total_fail_count="2"/><pending_commit branch="chromeos-3.18" change_id="I13f7d28ac2393a818b41b5e8af7c73df57ab07e8" commit="be369192811ef3e87ab33d646fbe7f26eb74657f" commit_message="UPSTREAM: mmc: block: Retry errored data requests when re-tuning is needed Retry errored data requests when re-tuning is needed and add a flag to struct mmc_blk_request so that the retry is only done once. Signed-off-by: Adrian Hunter <adrian.hunter@intel.com> Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org> (cherry picked from commit b8360a4945c49c07568892b5958c08e01bf7d6d2) Signed-off-by: Marc Herbert <marc.herbert@intel.com> BUG=chrome-os-partner:40410 TEST=With this whole HS400 series applied: TEST=on a system with HS400 controller(s), it/they initialize with the following log message: INFO kernel: [ 103.601747] mmc0: new HS400 MMC card at address 0001 TEST=run SD/eMMC test plan: higher eMMC throughput after change, and no other change. TEST=same on another system with no HS400: no observable change at all. Change-Id: I13f7d28ac2393a818b41b5e8af7c73df57ab07e8 Reviewed-on: https://chromium-review.googlesource.com/276411 Commit-Ready: Marc Herbert <marc.herbert@intel.com> Tested-by: Philip Hanson <philip.hanson@intel.com> Reviewed-by: Derek Basehore <dbasehore@chromium.org> " fail_count="2" gerrit_number="276411" owner_email="marc.herbert@intel.com" pass_count="0" patch_number="5" project="chromiumos/third_party/kernel" project_url="https://chromium-review.googlesource.com/chromiumos/third_party/kernel" ref="refs/changes/11/276411/5" remote="cros" total_fail_count="5"/><pending_commit branch="chromeos-3.18" change_id="Ie9b545e118c841eb9d1d46c284dd3add47aace8a" commit="49d83b52dc61a174476fecd9f3fd3db719c38d7f" commit_message="UPSTREAM: mmc: core: Reset driver type to default IO state variable drv_type could be set during card initialization. Consequently, it must be reset to the default value when setting the initial state. Signed-off-by: Adrian Hunter <adrian.hunter@intel.com> Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org> (cherry picked from commit 75e8a2288c4fabd6c2f752e8fd3bf7f60be7d3a4) Signed-off-by: Marc Herbert <marc.herbert@intel.com> BUG=chrome-os-partner:40410 TEST=With this whole HS400 series applied: TEST=on a system with HS400 controller(s), it/they initialize with the following log message: INFO kernel: [ 103.601747] mmc0: new HS400 MMC card at address 0001 TEST=run SD/eMMC test plan: higher eMMC throughput after change, and no other change. TEST=same on another system with no HS400: no observable change at all. Change-Id: Ie9b545e118c841eb9d1d46c284dd3add47aace8a Reviewed-on: https://chromium-review.googlesource.com/276412 Commit-Ready: Marc Herbert <marc.herbert@intel.com> Tested-by: Philip Hanson <philip.hanson@intel.com> Reviewed-by: Derek Basehore <dbasehore@chromium.org> " fail_count="2" gerrit_number="276412" owner_email="marc.herbert@intel.com" pass_count="0" patch_number="5" project="chromiumos/third_party/kernel" project_url="https://chromium-review.googlesource.com/chromiumos/third_party/kernel" ref="refs/changes/12/276412/5" remote="cros" total_fail_count="2"/><pending_commit branch="chromeos-3.18" change_id="I4a33ed4a8c100684e64389583f1f82d828fb4540" commit="eb78268b8ee7691add77181a341c0ebd67b150ce" commit_message="UPSTREAM: mmc: core: Allow card drive strength to be different to host Initialization of UHS-I modes for SD and SDIO cards employs a callback to allow the host driver to choose a drive strength value. Currently that assumes the card drive strength and host driver type must be the same value. Change to let the callback make that decision and return both the card drive strength and host driver type. Signed-off-by: Adrian Hunter <adrian.hunter@intel.com> Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org> (cherry picked from commit b4f30a174e1fda8118eda038b5d8d5260db36ad5) Signed-off-by: Marc Herbert <marc.herbert@intel.com> BUG=chrome-os-partner:40410 TEST=With this whole HS400 series applied: TEST=on a system with HS400 controller(s), it/they initialize with the following log message: INFO kernel: [ 103.601747] mmc0: new HS400 MMC card at address 0001 TEST=run SD/eMMC test plan: higher eMMC throughput after change, and no other change. TEST=same on another system with no HS400: no observable change at all. Change-Id: I4a33ed4a8c100684e64389583f1f82d828fb4540 Reviewed-on: https://chromium-review.googlesource.com/276413 Commit-Ready: Marc Herbert <marc.herbert@intel.com> Tested-by: Philip Hanson <philip.hanson@intel.com> Reviewed-by: Derek Basehore <dbasehore@chromium.org> " fail_count="2" gerrit_number="276413" owner_email="marc.herbert@intel.com" pass_count="0" patch_number="5" project="chromiumos/third_party/kernel" project_url="https://chromium-review.googlesource.com/chromiumos/third_party/kernel" ref="refs/changes/13/276413/5" remote="cros" total_fail_count="5"/><pending_commit branch="chromeos-3.18" change_id="Ib5cfbc6744b1a15a900a80c4a0ec9ff464adb863" commit="112e6a617d8b55456942542ee30b5d1d43387ffe" commit_message="UPSTREAM: mmc: core: Simplify card drive strength mask Card drive strength selection uses a callback to which a mask of supported drive strengths is passed. Currently, the bits are checked against the values in the SD specifications. That is not necessary because the callback will anyway match the mask against a valid value. Simplify by taking the mask as is but still ensuring that the default mandatory value (type B) is always supported. Signed-off-by: Adrian Hunter <adrian.hunter@intel.com> Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org> (cherry picked from commit fa021cef1af64cb4ba11c3c0910ef45085c58016) Signed-off-by: Marc Herbert <marc.herbert@intel.com> BUG=chrome-os-partner:40410 TEST=With this whole HS400 series applied: TEST=on a system with HS400 controller(s), it/they initialize with the following log message: INFO kernel: [ 103.601747] mmc0: new HS400 MMC card at address 0001 TEST=run SD/eMMC test plan: higher eMMC throughput after change, and no other change. TEST=same on another system with no HS400: no observable change at all. Change-Id: Ib5cfbc6744b1a15a900a80c4a0ec9ff464adb863 Reviewed-on: https://chromium-review.googlesource.com/276414 Commit-Ready: Marc Herbert <marc.herbert@intel.com> Tested-by: Philip Hanson <philip.hanson@intel.com> Reviewed-by: Derek Basehore <dbasehore@chromium.org> " fail_count="2" gerrit_number="276414" owner_email="marc.herbert@intel.com" pass_count="0" patch_number="5" project="chromiumos/third_party/kernel" project_url="https://chromium-review.googlesource.com/chromiumos/third_party/kernel" ref="refs/changes/14/276414/5" remote="cros" total_fail_count="2"/><pending_commit branch="chromeos-3.18" change_id="Ieb858e9e0491b9ed78eeb6c03b0ccd739f721e84" commit="6b481eb5b3f5be86354bc0c591e8e9eedf4009ad" commit_message="UPSTREAM: mmc: core: Add 'card' to drive strength selection callback In preparation for supporting also eMMC drive strength, add the 'card' as a parameter so that the callback can distinguish different types of cards if necessary. Signed-off-by: Adrian Hunter <adrian.hunter@intel.com> Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org> (cherry picked from commit f168359efbb99d6f8591bb666d6510bb78df2d07) Signed-off-by: Marc Herbert <marc.herbert@intel.com> BUG=chrome-os-partner:40410 TEST=With this whole HS400 series applied: TEST=on a system with HS400 controller(s), it/they initialize with the following log message: INFO kernel: [ 103.601747] mmc0: new HS400 MMC card at address 0001 TEST=run SD/eMMC test plan: higher eMMC throughput after change, and no other change. TEST=same on another system with no HS400: no observable change at all. Change-Id: Ieb858e9e0491b9ed78eeb6c03b0ccd739f721e84 Reviewed-on: https://chromium-review.googlesource.com/276415 Commit-Ready: Marc Herbert <marc.herbert@intel.com> Tested-by: Philip Hanson <philip.hanson@intel.com> Reviewed-by: Derek Basehore <dbasehore@chromium.org> " fail_count="2" gerrit_number="276415" owner_email="marc.herbert@intel.com" pass_count="0" patch_number="5" project="chromiumos/third_party/kernel" project_url="https://chromium-review.googlesource.com/chromiumos/third_party/kernel" ref="refs/changes/15/276415/5" remote="cros" total_fail_count="2"/><pending_commit branch="chromeos-3.18" change_id="I73baaf4d032458250696915f7af91556919276ed" commit="4ddd79d0b3e7432314cefe619c911b168f51e8f2" commit_message="UPSTREAM: mmc: core: Factor out common code in drive strength selection Make a new function out of common code used for drive strength selection. Signed-off-by: Adrian Hunter <adrian.hunter@intel.com> Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org> (cherry picked from commit e23350b35deb77ef8e33c35dbb0ed1dab9e8ab86) Signed-off-by: Marc Herbert <marc.herbert@intel.com> BUG=chrome-os-partner:40410 TEST=With this whole HS400 series applied: TEST=on a system with HS400 controller(s), it/they initialize with the following log message: INFO kernel: [ 103.601747] mmc0: new HS400 MMC card at address 0001 TEST=run SD/eMMC test plan: higher eMMC throughput after change, and no other change. TEST=same on another system with no HS400: no observable change at all. Change-Id: I73baaf4d032458250696915f7af91556919276ed Reviewed-on: https://chromium-review.googlesource.com/276416 Commit-Ready: Marc Herbert <marc.herbert@intel.com> Tested-by: Philip Hanson <philip.hanson@intel.com> Reviewed-by: Derek Basehore <dbasehore@chromium.org> " fail_count="2" gerrit_number="276416" owner_email="marc.herbert@intel.com" pass_count="0" patch_number="5" project="chromiumos/third_party/kernel" project_url="https://chromium-review.googlesource.com/chromiumos/third_party/kernel" ref="refs/changes/16/276416/5" remote="cros" total_fail_count="2"/><pending_commit branch="chromeos-3.18" change_id="Ie4ed0155b73e32dd8e3ef2d2e56c49602b25181d" commit="275421b80de3c48e79ce03f544b7932b17316056" commit_message="UPSTREAM: mmc: core: Record card drive strength In preparation for adding drive strength support for eMMC, add drive_strength to struct mmc_card to record the card drive strength for UHS-I modes and HS200 / HS400. For eMMC this will be needed when switching between HS200 and HS400. Signed-off-by: Adrian Hunter <adrian.hunter@intel.com> Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org> (cherry picked from commit 3853a042325e8f497c199020979c4fc824528c6e) Signed-off-by: Marc Herbert <marc.herbert@intel.com> BUG=chrome-os-partner:40410 TEST=With this whole HS400 series applied: TEST=on a system with HS400 controller(s), it/they initialize with the following log message: INFO kernel: [ 103.601747] mmc0: new HS400 MMC card at address 0001 TEST=run SD/eMMC test plan: higher eMMC throughput after change, and no other change. TEST=same on another system with no HS400: no observable change at all. Change-Id: Ie4ed0155b73e32dd8e3ef2d2e56c49602b25181d Reviewed-on: https://chromium-review.googlesource.com/276417 Commit-Ready: Marc Herbert <marc.herbert@intel.com> Tested-by: Philip Hanson <philip.hanson@intel.com> Reviewed-by: Derek Basehore <dbasehore@chromium.org> " fail_count="2" gerrit_number="276417" owner_email="marc.herbert@intel.com" pass_count="0" patch_number="5" project="chromiumos/third_party/kernel" project_url="https://chromium-review.googlesource.com/chromiumos/third_party/kernel" ref="refs/changes/17/276417/5" remote="cros" total_fail_count="2"/><pending_commit branch="chromeos-3.18" change_id="I193b73b2b5dbb4f9dc484b1342adef217d44fc5b" commit="d57df876db0b96570e100dc87c63939265ba9d1a" commit_message="UPSTREAM: mmc: mmc: Read card's valid driver strength mask In preparation for supporing drive strength selection for eMMC, read the card's valid driver strengths. Note that though the SD spec uses the term "drive strength", the JEDEC eMMC spec uses the term "driver strength". Signed-off-by: Adrian Hunter <adrian.hunter@intel.com> Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org> (cherry picked from commit b097e07f57930eda774c83aa46e8e401686d01dc) Signed-off-by: Marc Herbert <marc.herbert@intel.com> BUG=chrome-os-partner:40410 TEST=With this whole HS400 series applied: TEST=on a system with HS400 controller(s), it/they initialize with the following log message: INFO kernel: [ 103.601747] mmc0: new HS400 MMC card at address 0001 TEST=run SD/eMMC test plan: higher eMMC throughput after change, and no other change. TEST=same on another system with no HS400: no observable change at all. Change-Id: I193b73b2b5dbb4f9dc484b1342adef217d44fc5b Reviewed-on: https://chromium-review.googlesource.com/276418 Commit-Ready: Marc Herbert <marc.herbert@intel.com> Tested-by: Philip Hanson <philip.hanson@intel.com> Reviewed-by: Derek Basehore <dbasehore@chromium.org> " fail_count="2" gerrit_number="276418" owner_email="marc.herbert@intel.com" pass_count="0" patch_number="5" project="chromiumos/third_party/kernel" project_url="https://chromium-review.googlesource.com/chromiumos/third_party/kernel" ref="refs/changes/18/276418/5" remote="cros" total_fail_count="2"/><pending_commit branch="chromeos-3.18" change_id="I700e901e1b5fc22853996b6617080d8e168af4f6" commit="4fec1251c449099572c0a4b04d0b178a4c3679c2" commit_message="UPSTREAM: mmc: mmc: Add driver strength selection Add the ability to set eMMC driver strength for HS200 and HS400. Signed-off-by: Adrian Hunter <adrian.hunter@intel.com> Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org> (cherry picked from commit cc4f414c885cd04f7227ad9bcd6b18fd78d718d9) Signed-off-by: Marc Herbert <marc.herbert@intel.com> BUG=chrome-os-partner:40410 TEST=With this whole HS400 series applied: TEST=on a system with HS400 controller(s), it/they initialize with the following log message: INFO kernel: [ 103.601747] mmc0: new HS400 MMC card at address 0001 TEST=run SD/eMMC test plan: higher eMMC throughput after change, and no other change. TEST=same on another system with no HS400: no observable change at all. Change-Id: I700e901e1b5fc22853996b6617080d8e168af4f6 Reviewed-on: https://chromium-review.googlesource.com/276419 Commit-Ready: Marc Herbert <marc.herbert@intel.com> Tested-by: Philip Hanson <philip.hanson@intel.com> Reviewed-by: Derek Basehore <dbasehore@chromium.org> " fail_count="2" gerrit_number="276419" owner_email="marc.herbert@intel.com" pass_count="0" patch_number="5" project="chromiumos/third_party/kernel" project_url="https://chromium-review.googlesource.com/chromiumos/third_party/kernel" ref="refs/changes/19/276419/5" remote="cros" total_fail_count="2"/><pending_commit branch="chromeos-3.18" change_id="If256a081262fb3f59eb89beea8733961bea4e868" commit="c79eda62881c03a9e55513fc361ab8a303c0d658" commit_message="UPSTREAM: mmc: sdhci: Add a callback to select drive strength Add a callbak to let host drivers select drive strength. Signed-off-by: Adrian Hunter <adrian.hunter@intel.com> Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org> (cherry picked from commit cb8496482e8886bbd6bd79462d8062db572b0473) Signed-off-by: Marc Herbert <marc.herbert@intel.com> Conflicts: drivers/mmc/host/sdhci.h (minor contextual conflict: we have no voltage_switch() callback) BUG=chrome-os-partner:40410 TEST=With this whole HS400 series applied: TEST=on a system with HS400 controller(s), it/they initialize with the following log message: INFO kernel: [ 103.601747] mmc0: new HS400 MMC card at address 0001 TEST=run SD/eMMC test plan: higher eMMC throughput after change, and no other change. TEST=same on another system with no HS400: no observable change at all. Change-Id: If256a081262fb3f59eb89beea8733961bea4e868 Reviewed-on: https://chromium-review.googlesource.com/276420 Commit-Ready: Marc Herbert <marc.herbert@intel.com> Tested-by: Philip Hanson <philip.hanson@intel.com> Reviewed-by: Derek Basehore <dbasehore@chromium.org> " fail_count="0" gerrit_number="276420" owner_email="marc.herbert@intel.com" pass_count="0" patch_number="5" project="chromiumos/third_party/kernel" project_url="https://chromium-review.googlesource.com/chromiumos/third_party/kernel" ref="refs/changes/20/276420/5" remote="cros" total_fail_count="3"/><pending_commit branch="chromeos-3.18" change_id="I5b0ac1c85725130fa92867fbd00dc62eaa6535e0" commit="d10d85832522fac86001cd3c6c0eec1b2ddd74c6" commit_message="UPSTREAM: mmc: sdhci-pci: Add support for drive strength selection for SPT Implement the select_drive_strength callback to provide drive strength selection for Intel SPT. Signed-off-by: Adrian Hunter <adrian.hunter@intel.com> Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org> (cherry picked from commit e1bfad6d936d7149a83423e2a7244dd5771f27e7) Signed-off-by: Marc Herbert <marc.herbert@intel.com> BUG=chrome-os-partner:40410 TEST=With this whole HS400 series applied: TEST=on a system with HS400 controller(s), it/they initialize with the following log message: INFO kernel: [ 103.601747] mmc0: new HS400 MMC card at address 0001 TEST=run SD/eMMC test plan: higher eMMC throughput after change, and no other change. TEST=same on another system with no HS400: no observable change at all. Change-Id: I5b0ac1c85725130fa92867fbd00dc62eaa6535e0 Reviewed-on: https://chromium-review.googlesource.com/276421 Commit-Ready: Marc Herbert <marc.herbert@intel.com> Tested-by: Philip Hanson <philip.hanson@intel.com> Reviewed-by: Derek Basehore <dbasehore@chromium.org> " fail_count="2" gerrit_number="276421" owner_email="marc.herbert@intel.com" pass_count="0" patch_number="5" project="chromiumos/third_party/kernel" project_url="https://chromium-review.googlesource.com/chromiumos/third_party/kernel" ref="refs/changes/21/276421/5" remote="cros" total_fail_count="5"/><pending_commit branch="chromeos-3.18" change_id="Iee0cde41093f79ba09c84318bc40760fbe6b1cae" commit="27b2c2e65d79697d66e9979fe67fcb3202c5b0de" commit_message="UPSTREAM: mmc: sdhci-pxav3: Respect MMC_DDR52 timing on uhs signaling commit bb8175a8aa42d731a840cd474e348ac3367eb5a0 ("mmc: sdhci: clarify DDR timing mode between SD-UHS and eMMC") added MMC_DDR52 as eMMC's DDR mode to be distinguished from SD-UHS. While the differentation may be useful, pxav3 SDHCI controller lacks a corresponding check in its custom .set_uhs_signaling callback for MMC_DDR52. This patch adds a new switch case for MMC_TIMING_MMC_DDR52 to MMC_TIMING_UHS_DDR50 case. Signed-off-by: Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com> Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org> (cherry picked from commit 668e84b20f7a76c7aacfc907906400b844561276) BUG=chrome-os-partner:43600 TEST=TBD Change-Id: Iee0cde41093f79ba09c84318bc40760fbe6b1cae Signed-off-by: Grant Grundler <grundler@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/305282 Reviewed-by: Andrew Bresticker <abrestic@chromium.org> " fail_count="0" gerrit_number="305282" owner_email="grundler@chromium.org" pass_count="0" patch_number="2" project="chromiumos/third_party/kernel" project_url="https://chromium-review.googlesource.com/chromiumos/third_party/kernel" ref="refs/changes/82/305282/2" remote="cros" total_fail_count="0"/><pending_commit branch="chromeos-3.18" change_id="I539c2490a535019d39319767b73cf241a047eb73" commit="6c92ddaed808fcb4c782c1fe41794645ea663db2" commit_message="UPSTREAM: mmc: sdhci-pxav3: Move private driver data to driver source struct sdhci_pxa is only used in sdhci_pxa driver itself, so move it there. Signed-off-by: Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com> Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org> (cherry picked from commit cc9571e85808dfc121e4fda5c75c9a3c3c75e514) BUG=chrome-os-partner:43600 TEST=TBD Change-Id: I539c2490a535019d39319767b73cf241a047eb73 Signed-off-by: Grant Grundler <grundler@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/300466 Reviewed-by: Andrew Bresticker <abrestic@chromium.org> " fail_count="0" gerrit_number="300466" owner_email="nadavh@marvell.com" pass_count="0" patch_number="4" project="chromiumos/third_party/kernel" project_url="https://chromium-review.googlesource.com/chromiumos/third_party/kernel" ref="refs/changes/66/300466/4" remote="cros" total_fail_count="0"/><pending_commit branch="chromeos-3.18" change_id="I6838e09d94c944887313715b13a56c77bc867ee6" commit="b508cdc15194a527475292acff63e9b4e06d4bb4" commit_message="UPSTREAM: mmc: sdhci-pxav3: Remove unused clk_enable from sdhci_pxa clk_enable from struct sdhci_pxa is unused, remove it from the private driver data. Signed-off-by: Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com> Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org> (cherry picked from commit ff8878fd64c0e578d979816a675c8ecb937888bd) BUG=chrome-os-partner:43600 TEST=TBD Change-Id: I6838e09d94c944887313715b13a56c77bc867ee6 Signed-off-by: Grant Grundler <grundler@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/305283 Reviewed-by: Andrew Bresticker <abrestic@chromium.org> " fail_count="0" gerrit_number="305283" owner_email="grundler@chromium.org" pass_count="0" patch_number="2" project="chromiumos/third_party/kernel" project_url="https://chromium-review.googlesource.com/chromiumos/third_party/kernel" ref="refs/changes/83/305283/2" remote="cros" total_fail_count="0"/><pending_commit branch="chromeos-3.18" change_id="I855f68093a51c804b8221a84ff04495d6732d8f7" commit="bf10a1389e7988a363fc6f288af1887e96c3da92" commit_message="UPSTREAM: mmc: sdhci-pxav3: Remove checks for mandatory host clock NULL-checking a struct clk it not only wrong but also not required as for PXAv3 driver the corresponding clock is mandatory. Remove the checks from sdhci_pxav3_runtime_{suspend,resume}. Signed-off-by: Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com> Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org> (cherry picked from commit 20d5a70344e526f51efe50861be10f6d743b7706) BUG=chrome-os-partner:43600 TEST=TBD Change-Id: I855f68093a51c804b8221a84ff04495d6732d8f7 Signed-off-by: Grant Grundler <grundler@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/305284 Reviewed-by: Andrew Bresticker <abrestic@chromium.org> " fail_count="0" gerrit_number="305284" owner_email="grundler@chromium.org" pass_count="0" patch_number="2" project="chromiumos/third_party/kernel" project_url="https://chromium-review.googlesource.com/chromiumos/third_party/kernel" ref="refs/changes/84/305284/2" remote="cros" total_fail_count="0"/><pending_commit branch="chromeos-3.18" change_id="Ic09c3cc3a9d2a6d9a44e5ba9701da117f0627ad1" commit="4e4dc25e6b4f3309f04486005fedc496c58c8ab2" commit_message="UPSTREAM: mmc: sdhci-pxav3: Move I/O clock to private data As we are using references to the I/O clock throughout the driver, move it to the private data. Also, in preparation for core clock, rename it to clk_io. Signed-off-by: Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com> Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org> (cherry picked from commit 8c96a7a3310a21a4a3f827b9c42636aa04a47f9e) BUG=chrome-os-partner:43600 TEST=TBD Change-Id: Ic09c3cc3a9d2a6d9a44e5ba9701da117f0627ad1 Signed-off-by: Grant Grundler <grundler@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/305285 Reviewed-by: Andrew Bresticker <abrestic@chromium.org> " fail_count="0" gerrit_number="305285" owner_email="grundler@chromium.org" pass_count="0" patch_number="2" project="chromiumos/third_party/kernel" project_url="https://chromium-review.googlesource.com/chromiumos/third_party/kernel" ref="refs/changes/85/305285/2" remote="cros" total_fail_count="0"/><pending_commit branch="chromeos-3.18" change_id="Ie45a6382e6fd315dea56494fc853ba91a65b3c10" commit="c59851679610737f267d0fbd31a03463f353fdc2" commit_message="UPSTREAM: mmc: sdhci-pxav3: Try to get named I/O clock first With support for more than one clock, we'll need to distinguish between the clock by name. Change clock probing to first try to get "io" clock before falling back to unnamed clock. Signed-off-by: Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com> Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org> (cherry picked from commit 01ae1070cbb5fbb3bffa0df44e422521df2b4ab1) BUG=chrome-os-partner:43600 TEST=TBD Change-Id: Ie45a6382e6fd315dea56494fc853ba91a65b3c10 Signed-off-by: Grant Grundler <grundler@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/305286 Reviewed-by: Andrew Bresticker <abrestic@chromium.org> " fail_count="0" gerrit_number="305286" owner_email="grundler@chromium.org" pass_count="0" patch_number="2" project="chromiumos/third_party/kernel" project_url="https://chromium-review.googlesource.com/chromiumos/third_party/kernel" ref="refs/changes/86/305286/2" remote="cros" total_fail_count="0"/><pending_commit branch="chromeos-3.18" change_id="I62d8eebb2323fd9c41089e50beb1c81ab153782b" commit="a87de6f89265596de6dfd29cf0603e6ce82797f7" commit_message="UPSTREAM: mmc: sdhci-pxav3: Get optional core clock Besides the I/O clock, some PXAv3 SDHCI IP also requires a core clock to be enabled. Add an optional core clock to the corresponding driver. Signed-off-by: Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com> Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org> (cherry picked from commit 8afdc9cca27fc299ffe7b535b299adc03efab851) BUG=chrome-os-partner:43600 TEST=TBD Change-Id: I62d8eebb2323fd9c41089e50beb1c81ab153782b Signed-off-by: Grant Grundler <grundler@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/305287 Reviewed-by: Andrew Bresticker <abrestic@chromium.org> " fail_count="0" gerrit_number="305287" owner_email="grundler@chromium.org" pass_count="0" patch_number="2" project="chromiumos/third_party/kernel" project_url="https://chromium-review.googlesource.com/chromiumos/third_party/kernel" ref="refs/changes/87/305287/2" remote="cros" total_fail_count="0"/><pending_commit branch="chromeos-3.18" change_id="Ica81249539d0789123ebd86fdb86037df88d18dd" commit="549f7174a4801a1ca9fbc453d7e9e63a04126cfb" commit_message="UPSTREAM: PM: Kconfig: Set PM_RUNTIME if PM_SLEEP is selected The number of and dependencies between high-level power management Kconfig options make life much harder than necessary. Several conbinations of them have to be tested and supported, even though some of those combinations are very rarely used in practice (if they are used in practice at all). Moreover, the fact that we have separate independent Kconfig options for runtime PM and system suspend is a serious obstacle for integration between the two frameworks. To overcome these difficulties, always select PM_RUNTIME if PM_SLEEP is set. Among other things, this will allow system suspend callbacks provided by bus types and device drivers to rely on the runtime PM framework regardless of the kernel configuration. Enthusiastically-acked-by: Kevin Hilman <khilman@linaro.org> Tested-by: Geert Uytterhoeven <geert+renesas@glider.be> Signed-off-by: Rafael J. Wysocki <rafael.j.wysocki@intel.com> (cherry picked from commit b2b49ccbdd547135c69371ed066cffa44912060a) BUG=chrome-os-partner:43600 TEST=TBD Change-Id: Ica81249539d0789123ebd86fdb86037df88d18dd Signed-off-by: Grant Grundler <grundler@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/305243 Reviewed-by: Andrew Bresticker <abrestic@chromium.org> " fail_count="0" gerrit_number="305243" owner_email="grundler@chromium.org" pass_count="0" patch_number="1" project="chromiumos/third_party/kernel" project_url="https://chromium-review.googlesource.com/chromiumos/third_party/kernel" ref="refs/changes/43/305243/1" remote="cros" total_fail_count="0"/><pending_commit branch="chromeos-3.18" change_id="I413c1b19e45394d9b928b34e80aabbde62da05aa" commit="f89fa9295c69f12249eba9310103c4e2f9d5d8bc" commit_message="UPSTREAM: MMC / PM: Replace CONFIG_PM_RUNTIME with CONFIG_PM After commit b2b49ccbdd54 (PM: Kconfig: Set PM_RUNTIME if PM_SLEEP is selected) PM_RUNTIME is always set if PM is set, so #ifdef blocks depending on CONFIG_PM_RUNTIME may now be changed to depend on CONFIG_PM. Replace CONFIG_PM_RUNTIME with CONFIG_PM everywhere under drivers/mmc/. Signed-off-by: Rafael J. Wysocki <rafael.j.wysocki@intel.com> Acked-by: Ulf Hansson <ulf.hansson@linaro.org> (cherry picked from commit 162d6f98005fce408efc5af73956c434ae08ef73) BUG=chrome-os-partner:43600 TEST=TBD Change-Id: I413c1b19e45394d9b928b34e80aabbde62da05aa Signed-off-by: Grant Grundler <grundler@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/305288 Reviewed-by: Andrew Bresticker <abrestic@chromium.org> " fail_count="0" gerrit_number="305288" owner_email="grundler@chromium.org" pass_count="0" patch_number="2" project="chromiumos/third_party/kernel" project_url="https://chromium-review.googlesource.com/chromiumos/third_party/kernel" ref="refs/changes/88/305288/2" remote="cros" total_fail_count="0"/><pending_commit branch="chromeos-3.18" change_id="If2c45dc4198bbc734db5fb0cc566ac1f2d0803c8" commit="45f1acbde3a6474b5937a400a3d9a5b99dd0514e" commit_message="UPSTREAM: mmc: sdhci-pxav3: do the mbus window configuration after enabling clocks In commit 5491ce3f79ee ("mmc: sdhci-pxav3: add support for the Armada 38x SDHCI controller"), the sdhci-pxav3 driver was extended to include support for the SDHCI controller found in the Armada 38x processor. This mainly involved adding some MBus window related configuration. However, this configuration is currently done too early in ->probe(): it is done before clocks are enabled, while this configuration involves touching the registers of the controller, which will hang the SoC if the clock is disabled. It wasn't noticed until now because the bootloader typically leaves gatable clocks enabled, but in situations where we have a deferred probe (due to a CD GPIO that cannot be taken, for example), then the probe will be re-tried later, after a clock disable has been done in the exit path of the failed probe attempt of the device. This second probe() will hang the system due to the clock being disabled. This can for example be produced on Armada 385 GP, which has a CD GPIO connected to an I2C PCA9555. If the driver for the PCA9555 is not compiled into the kernel, then we will have the following sequence of events: 1. The SDHCI probes 2. It does the MBus configuration (which works, because the clock is left enabled by the bootloader) 3. It enables the clock 4. It tries to get the CD GPIO, which fails due to the driver being missing, so -EPROBE_DEFER is returned. 5. Before returning -EPROBE_DEFER, the driver cleans up what was done, which includes disabling the clock. 6. Later on, the SDHCI probe is tried again. 7. It does the MBus configuration, which hangs because the clock is no longer enabled. This commit does the obvious fix of doing the MBus configuration after the clock has been enabled by the driver. Fixes: 5491ce3f79ee ("mmc: sdhci-pxav3: add support for the Armada 38x SDHCI controller") Cc: <stable@vger.kernel.org> # v3.15+ Signed-off-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com> Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org> (cherry picked from commit aa8165f914420f143476305a01894b017d3abe6b) BUG=chrome-os-partner:43600 TEST=TBD Change-Id: If2c45dc4198bbc734db5fb0cc566ac1f2d0803c8 Signed-off-by: Grant Grundler <grundler@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/300465 Reviewed-by: Andrew Bresticker <abrestic@chromium.org> " fail_count="0" gerrit_number="300465" owner_email="nadavh@marvell.com" pass_count="0" patch_number="4" project="chromiumos/third_party/kernel" project_url="https://chromium-review.googlesource.com/chromiumos/third_party/kernel" ref="refs/changes/65/300465/4" remote="cros" total_fail_count="0"/><pending_commit branch="chromeos-3.18" change_id="I480c5d7f2549966cdbab51b8639af77d11063c95" commit="0684f7a00935ba01c75c3ce2df6785a6f6452ea6" commit_message="UPSTREAM: mmc: sdhci-pxav3: fix unbalanced clock issues during probe Commit 0dcaa2499b7d ("sdhci-pxav3: Fix runtime PM initialization") tries to fix one hang issue caused by calling sdhci_add_host() on a suspended device. The fix enables the clock twice, once by clk_prepare_enable() and another by pm_runtime_get_sync(), meaning that the clock will never be gated at runtime PM suspend. I observed the power consumption regression on Marvell BG2Q SoCs. In fact, the fix is not correct. There still be a very small window during which a runtime suspend might somehow occur after pm_runtime_enable() but before pm_runtime_get_sync(). This patch fixes all of the two problems by just incrementing the usage counter before pm_runtime_enable(). It also adjust the order of disabling runtime pm and storing the usage count in the error path to handle clock gating properly. Signed-off-by: Jisheng Zhang <jszhang@marvell.com> Cc: <stable@vger.kernel.org> # v3.11+ Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org> (cherry picked from commit 62cf983ad84275f8580c807e5e596216c46773cf) BUG=chrome-os-partner:43600 TEST=TBD Change-Id: I480c5d7f2549966cdbab51b8639af77d11063c95 Signed-off-by: Grant Grundler <grundler@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/300461 Reviewed-by: Andrew Bresticker <abrestic@chromium.org> " fail_count="0" gerrit_number="300461" owner_email="nadavh@marvell.com" pass_count="0" patch_number="4" project="chromiumos/third_party/kernel" project_url="https://chromium-review.googlesource.com/chromiumos/third_party/kernel" ref="refs/changes/61/300461/4" remote="cros" total_fail_count="0"/><pending_commit branch="chromeos-3.18" change_id="I6fbc038c7195e5934fc1e5db136b5ecef04387b5" commit="d64c5fb029b5d282249b8b013206a18d22944594" commit_message="UPSTREAM: mmc: sdhci-pxav3: fix pm unbalanced issue in -> remove() This patch calls pm_runtime_put_noidle() to restore the device's usage counter in the ->remove() implementation. Signed-off-by: Jisheng Zhang <jszhang@marvell.com> Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org> (cherry picked from commit 20f1f2d7d4a497ce6c51866e23ce5f452e3aeb99) BUG=chrome-os-partner:43600 TEST=TBD Change-Id: I6fbc038c7195e5934fc1e5db136b5ecef04387b5 Signed-off-by: Grant Grundler <grundler@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/305289 Reviewed-by: Andrew Bresticker <abrestic@chromium.org> " fail_count="0" gerrit_number="305289" owner_email="grundler@chromium.org" pass_count="0" patch_number="2" project="chromiumos/third_party/kernel" project_url="https://chromium-review.googlesource.com/chromiumos/third_party/kernel" ref="refs/changes/89/305289/2" remote="cros" total_fail_count="0"/><pending_commit branch="chromeos-3.18" change_id="Ife38e58c79a8bc034c8b4b0f7e602b3cce23b925" commit="fbcded3bedd626119c36458bf40c34cea830ef94" commit_message="UPSTREAM: mmc: sdhci-pxav3: Remove checks for optional core clock in error/remove path Commit 63589e92c2d9 ("clk: Ignore error and NULL pointers passed to clk_{unprepare, disable}()") allows NULL or error pointer to be passed unconditionally. This patch is to simplify probe error and remove code paths. However, we reserve the core clock checks in runtime suspend/resume code because we want a little smaller latency. Signed-off-by: Jisheng Zhang <jszhang@marvell.com> Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org> (cherry picked from commit c25d9e1bda2316aa0d2bb61640ab4fbe01feb590) BUG=chrome-os-partner:43600 TEST=TBD Change-Id: Ife38e58c79a8bc034c8b4b0f7e602b3cce23b925 Signed-off-by: Grant Grundler <grundler@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/305320 Reviewed-by: Andrew Bresticker <abrestic@chromium.org> " fail_count="0" gerrit_number="305320" owner_email="grundler@chromium.org" pass_count="0" patch_number="2" project="chromiumos/third_party/kernel" project_url="https://chromium-review.googlesource.com/chromiumos/third_party/kernel" ref="refs/changes/20/305320/2" remote="cros" total_fail_count="0"/><pending_commit branch="chromeos-3.18" change_id="I0e374f69c79065cd24fc6a0eefee3462694df9a1" commit="d766c752979cca13a562beea5ece62e8defc3205" commit_message="UPSTREAM: mmc: sdhci-pxav3: fix race between runtime pm and irq This patch is to fix a race condition that may cause an unhandled irq, which results in big sdhci interrupt numbers and endless "mmc1: got irq while runtime suspended" msgs before v3.15. Consider following scenario: CPU0 CPU1 sdhci_pxav3_runtime_suspend() spin_lock_irqsave(&host->lock, flags); sdhci_irq() spining on the &host->lock host->runtime_suspended = true; spin_unlock_irqrestore(&host->lock, flags); get the &host->lock runtime_suspended is true now return IRQ_NONE; Fix this race by using the core sdhci.c supplied sdhci_runtime_suspend_host() in runtime suspend hook which will disable card interrupts. We also use the sdhci_runtime_resume_host() in the runtime resume hook accordingly. Signed-off-by: Jisheng Zhang <jszhang@marvell.com> Cc: <stable@vger.kernel.org> # v3.9+ Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org> (cherry picked from commit 3bb10f60933e84abfe2be69f60b3486f9b96348b) BUG=chrome-os-partner:43600 TEST=TBD Change-Id: I0e374f69c79065cd24fc6a0eefee3462694df9a1 Signed-off-by: Grant Grundler <grundler@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/305321 Reviewed-by: Andrew Bresticker <abrestic@chromium.org> " fail_count="0" gerrit_number="305321" owner_email="grundler@chromium.org" pass_count="0" patch_number="2" project="chromiumos/third_party/kernel" project_url="https://chromium-review.googlesource.com/chromiumos/third_party/kernel" ref="refs/changes/21/305321/2" remote="cros" total_fail_count="0"/><pending_commit branch="chromeos-3.18" change_id="Ibe7f5b53935bd98e0461120c9caf003e622a1aca" commit="25ed0c37e77e30068771a075e2c58368be86c4d1" commit_message="UPSTREAM: mmc: sdhci-pxav3: fix setting of pdata->clk_delay_cycles Current code checks "clk_delay_cycles > 0" to know whether the optional "mrvl,clk_delay_cycles" is set or not. But of_property_read_u32() doesn't touch clk_delay_cycles if the property is not set. And type of clk_delay_cycles is u32, so we may always set pdata->clk_delay_cycles as a random value. This patch fix this problem by check the return value of of_property_read_u32() to know whether the optional clk-delay-cycles is set or not. Signed-off-by: Jisheng Zhang <jszhang@marvell.com> Cc: <stable@vger.kernel.org> # v3.6+ Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org> (cherry picked from commit 14460dbaf7a5a0488963fdb8232ad5c8a8cca7b7) BUG=chrome-os-partner:43600 TEST=TBD Change-Id: Ibe7f5b53935bd98e0461120c9caf003e622a1aca Signed-off-by: Grant Grundler <grundler@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/300462 Reviewed-by: Andrew Bresticker <abrestic@chromium.org> " fail_count="0" gerrit_number="300462" owner_email="nadavh@marvell.com" pass_count="0" patch_number="4" project="chromiumos/third_party/kernel" project_url="https://chromium-review.googlesource.com/chromiumos/third_party/kernel" ref="refs/changes/62/300462/4" remote="cros" total_fail_count="0"/><pending_commit branch="chromeos-3.8" change_id="Idc22c547fbccdd6952958485a1d940b77414f0df" commit="f97fa36ddba53dbcb1520681374369bcc911cbf1" commit_message="dts: exynos542x: Add IOMMU support for JPEG Adds IOMMU support for JPEG and JPEG_2. BUG=chrome-os-partner:40139 TEST=Run the jpeg test with userpointer and see that it generates the decoded output. Change-Id: Idc22c547fbccdd6952958485a1d940b77414f0df Signed-off-by: Tony K Nadackal <tony.kn@samsung.com> Reviewed-on: https://chromium-review.googlesource.com/274791 Commit-Ready: Heng-ruey Hsu <henryhsu@chromium.org> Tested-by: Heng-ruey Hsu <henryhsu@chromium.org> Reviewed-by: Heng-ruey Hsu <henryhsu@chromium.org> " fail_count="0" gerrit_number="274791" owner_email="a.kesavan@samsung.com" pass_count="0" patch_number="4" project="chromiumos/third_party/kernel" project_url="https://chromium-review.googlesource.com/chromiumos/third_party/kernel" ref="refs/changes/91/274791/4" remote="cros" total_fail_count="0"/><lkgm version="7541.0.0-rc2"/></manifest> |
