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| <pending_commit branch="master" change_id="Ic1378c49a7a750f1a7ff884056952f355b03851e" commit="4b74710a5396b0e71df3baecf73b7b094eb16f8f" commit_message="mtk_mmc: fix response CRC error in 50Mhz clock frequency when clock frequency was 50Mhz, use falling edge to sample response is more stable BUG=chrome-os-partner:50512 BRANCH=None TEST=cbmem -c and confirm 'mmc: ERROR: cmd: 13 crc error!' is gone. Change-Id: Ic1378c49a7a750f1a7ff884056952f355b03851e Signed-off-by: Chaotian Jing <chaotian.jing@mediatek.com> Reviewed-on: https://chromium-review.googlesource.com/329089 Commit-Ready: Yidi Lin <yidi.lin@mediatek.com> Tested-by: Yidi Lin <yidi.lin@mediatek.com> Reviewed-by: Julius Werner <jwerner@chromium.org> " fail_count="0" gerrit_number="329089" owner_email="yidi.lin@mediatek.com" pass_count="0" patch_number="2" project="chromiumos/platform/depthcharge" project_url="https://chromium-review.googlesource.com/chromiumos/platform/depthcharge" ref="refs/changes/89/329089/2" remote="cros" total_fail_count="0"/><pending_commit branch="master" change_id="I1e16a52f35ef2d3195f7c7f344d4e032bf409640" commit="47b1d36f8b023d0dcd6dcc600a874406b8a3324d" commit_message="oak: enable CONFIG_DRIVER_EC_CROS_PASSTHRU Enable the config to make sure cros_ec_probe_passthru() won't return 0 value. And then we will get right value of passthru_param_size instead of a negative number. BRANCH=none BUG=chrome-os-partner:50530 TEST=build and verify on rev5 "ectool --name=cros_pd version" and pd is in RW stage. Change-Id: I1e16a52f35ef2d3195f7c7f344d4e032bf409640 Signed-off-by: YH Huang <yh.huang@mediatek.com> Reviewed-on: https://chromium-review.googlesource.com/329850 Commit-Ready: Yidi Lin <yidi.lin@mediatek.com> Tested-by: Yidi Lin <yidi.lin@mediatek.com> Reviewed-by: Julius Werner <jwerner@chromium.org> " fail_count="0" gerrit_number="329850" owner_email="yidi.lin@mediatek.com" pass_count="0" patch_number="1" project="chromiumos/platform/depthcharge" project_url="https://chromium-review.googlesource.com/chromiumos/platform/depthcharge" ref="refs/changes/50/329850/1" remote="cros" total_fail_count="0"/><pending_commit branch="chromeos-2015.07" change_id="I7cac60fb0144e090b8decb05d948b2d8d2f8deac" commit="036816788c511efc49fb63f6abdaa0381065bd5c" commit_message="mainboard/skylakes: Configuring gpio PADRSTCFG to PLTRST With gpio PADRSTCFG set to DEEP & GPIROUTIOXAPIC=1 & PADRSTCFG, causes IRQ storm after S3 resume. GPIOs that fire IRQs via IOAPIC need to get their logic reset over pltrst and hence configuring PADRSTCFG to PLTRST to prevent IRQ strom after S3 resume. BRANCH=glados BUG=chrome-os-partner:50536 TEST=Build for kunimitsu and Boot on FAB4, no irq storm observed after S3 resume. Change-Id: I7cac60fb0144e090b8decb05d948b2d8d2f8deac Signed-off-by: Naresh G Solanki <naresh.solanki@intel.com> Reviewed-on: https://chromium-review.googlesource.com/329453 Commit-Ready: Naresh Solanki <naresh.solanki@intel.com> Tested-by: Naresh Solanki <naresh.solanki@intel.com> Reviewed-by: Duncan Laurie <dlaurie@chromium.org> " fail_count="0" gerrit_number="329453" owner_email="naresh.solanki@intel.com" pass_count="0" patch_number="2" project="chromiumos/third_party/coreboot" project_url="https://chromium-review.googlesource.com/chromiumos/third_party/coreboot" ref="refs/changes/53/329453/2" remote="cros" total_fail_count="0"/><pending_commit branch="master" change_id="I874b58f3f160021bc51dd2201998741e19aa24fa" commit="9e280292c81f324f92fae4ed4a2949e1f0299024" commit_message="Chameleon: Increase the retry number and timeout value for mirroring Have to increase these values for the dongle connection, e.g. Link needs timeout value at least 3; One Spring needs the retry number 4 but another is fine to use 2. Change these values to larger to reduce noise. BUG=chromium:582489 TEST=Ran the display_SwitchMode.fast_switch test on Link and Spring. Change-Id: I874b58f3f160021bc51dd2201998741e19aa24fa Reviewed-on: https://chromium-review.googlesource.com/329946 Commit-Ready: Wai-Hong Tam <waihong@chromium.org> Tested-by: Wai-Hong Tam <waihong@chromium.org> Reviewed-by: Kalin Stoyanov <kalin@chromium.org> " fail_count="0" gerrit_number="329946" owner_email="waihong@chromium.org" pass_count="0" patch_number="1" project="chromiumos/third_party/autotest" project_url="https://chromium-review.googlesource.com/chromiumos/third_party/autotest" ref="refs/changes/46/329946/1" remote="cros" total_fail_count="0"/><pending_commit branch="master" change_id="Ic16189cb69eb29c0f1376b1ae369e0b20ba58c19" commit="783628a218d3b2c1e96fc1d98454d537d1f676a2" commit_message="[Chameleon] gpio/button/led controller For Cyclone V HPS usage, HPS buttons and leds are GPIOs and we can monitor and control them by Linux GPIO sysfs interface. Before using, it is necessary to update the fpga_tio image to enable the correspondent pins as GPIO in SocKit IO pinmux setting. Since those button GPIOs are not configured as interrupt input, we monitor the change of value periodically as polling the button event. We use a queue to transmit the button event to LCM display module. BUG=chromium:569733 TEST=manual test. Push code onto chameleon and test. chameleon> cd /usr/lib/python2.7/site-packages/chameleond chameleon> python 1. Test LEDs (HPS_LED0~3: gpio 478~481) >>> from utils import gpio >>> a = gpio.Led(478) >>> a.On() --> HPS_LED0 turns on >>> a.Off() --> HPS_LED0 turns off >>> a.Blink() --> HPS_LED0 blinks 2. Test buttons (HPS_KEY0~3: gpio 448~451) >>> from utils import gpio >>> a = gpio.Gpio(451, 2) # 2: EDGE_RISING trigger >>> a.Poll() (Press HPS_KEY3 and a.Poll() escapes) Change-Id: Ic16189cb69eb29c0f1376b1ae369e0b20ba58c19 Reviewed-on: https://chromium-review.googlesource.com/327365 Commit-Ready: Pin-chih Lin <johnylin@chromium.org> Tested-by: Pin-chih Lin <johnylin@chromium.org> Reviewed-by: Wai-Hong Tam <waihong@chromium.org> " fail_count="0" gerrit_number="327365" owner_email="johnylin@chromium.org" pass_count="0" patch_number="4" project="chromiumos/platform/chameleon" project_url="https://chromium-review.googlesource.com/chromiumos/platform/chameleon" ref="refs/changes/65/327365/4" remote="cros" total_fail_count="0"/><pending_commit branch="master" change_id="I7e07e411961eb3aecea8948de1a7c522b1cf9788" commit="5085b07cb310986e9b72795b1a000b44b08ed3c9" commit_message="oak: Build PD firmware for bundling in BIOS This is needed for full BIOS builds to work. BUG=chrome-os-partner:50530 TEST=emerge-oak chromeos-bootimage and verify on rev5 "ectool --name=cros_pd version" and pd is in RW stage. Change-Id: I7e07e411961eb3aecea8948de1a7c522b1cf9788 Signed-off-by: YH Huang <yh.huang@mediatek.com> Reviewed-on: https://chromium-review.googlesource.com/329486 Commit-Ready: Yidi Lin <yidi.lin@mediatek.com> Tested-by: Yidi Lin <yidi.lin@mediatek.com> Reviewed-by: Daniel Kurtz <djkurtz@chromium.org> " fail_count="0" gerrit_number="329486" owner_email="yidi.lin@mediatek.com" pass_count="0" patch_number="2" project="chromiumos/overlays/board-overlays" project_url="https://chromium-review.googlesource.com/chromiumos/overlays/board-overlays" ref="refs/changes/86/329486/2" remote="cros" total_fail_count="0"/><pending_commit branch="master" change_id="Iecdf02e3ee79061a97182d0e1a55eca827dfb78b" commit="7a3db0f266982853ef331df1442f6e41f520d3aa" commit_message="toybox: upgraded package to upstream Upgraded sys-apps/toybox to version 0.7.0 on amd64, x86 BUG=chromium:584542 TEST=Launch tryjob, no more error in BuildPackages Change-Id: Iecdf02e3ee79061a97182d0e1a55eca827dfb78b Reviewed-on: https://chromium-review.googlesource.com/329921 Commit-Ready: Nicolas Boichat <drinkcat@chromium.org> Tested-by: Nicolas Boichat <drinkcat@chromium.org> Reviewed-by: Hung-Te Lin <hungte@chromium.org> Reviewed-by: Mike Frysinger <vapier@chromium.org> " fail_count="0" gerrit_number="329921" owner_email="drinkcat@chromium.org" pass_count="0" patch_number="1" project="chromiumos/overlays/portage-stable" project_url="https://chromium-review.googlesource.com/chromiumos/overlays/portage-stable" ref="refs/changes/21/329921/1" remote="cros" total_fail_count="0"/><pending_commit branch="chromeos-2015.07" change_id="I16f4f98df8c70fd25986a8b3644334c7209fd083" commit="f852ea1be81833f8f7be3a24724f14021c32c6fe" commit_message="skylake: Do not log wake source on reset Skip logging a wake source when just resetting without coming from S3 or S5 state. This will prevent the occasional spurious event like PCI PME from showing up in the event log. BUG=chrome-os-partner:40635 BRANCH=glados TEST=run warm reboot teset on chell and ensure no wake source is logged Change-Id: I16f4f98df8c70fd25986a8b3644334c7209fd083 Signed-off-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/329846 Reviewed-by: Aaron Durbin <adurbin@chromium.org> " fail_count="0" gerrit_number="329846" owner_email="dlaurie@chromium.org" pass_count="0" patch_number="1" project="chromiumos/third_party/coreboot" project_url="https://chromium-review.googlesource.com/chromiumos/third_party/coreboot" ref="refs/changes/46/329846/1" remote="cros" total_fail_count="0"/><lkgm version="7996.0.0-rc1"/></manifest> |
