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| <pending_commit branch="chromeos-2016.02" change_id="Icbf5804b66b9517f9ceb352bed86978dcf92228f" commit="81a04edcbcd1ca199d5fc21d3c0775e7e1eba405" commit_message="UPSTREAM: arch/x86: Rename bootblock.S to bootblock_romcc.S bootblock.S was used strictly for setting up the system so that the assembly generated by ROMCC could be executed. Since the infrastructure now exists to run a bootblock wihtout ROMCC, rename this file accordingly. this is done to prevent any future confusion. BUG=chrome-os-partner:51844 BRANCH=none TEST=none yet, the full stack of patches boots to payload on APLK Change-Id: Icbf5804b66b9517f9ceb352bed86978dcf92228f Signed-off-by: Alexandru Gagniuc <mr.nuke.me@gmail.com> Reviewed-on: https://review.coreboot.org/11784 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/335960 Commit-Ready: Aaron Durbin <adurbin@chromium.org> Tested-by: Andrey Petrov <andrey.petrov@intel.com> Reviewed-by: Furquan Shaikh <furquan@chromium.org> " fail_count="1" gerrit_number="335960" owner_email="andrey.petrov@intel.com" pass_count="0" patch_number="3" project="chromiumos/third_party/coreboot" project_url="https://chromium-review.googlesource.com/chromiumos/third_party/coreboot" ref="refs/changes/60/335960/3" remote="cros" total_fail_count="1"/><pending_commit branch="chromeos-2016.02" change_id="I009b42b9a707cf11a74493bd4d8c189dc09b8ace" commit="8fdaed96de1fe3a2002e4b5051948f8d16edfb97" commit_message="UPSTREAM: arch/x86: Implement minimal bootblock for C_ENVIRONMENT_BOTOBLOCK Some newer x86 systems can boot from non-memory-mapped boot media (e.g. EMMC). The bootblock may be backed by small amounts of SRAM, or other memory, similar to how most ARM chipsets work. In such cases, we may not have enough code space for romstage very early on. This means that CAR setup and early boot media (e.g. SPI, EMMC) drivers need to be implemented within the limited amount memory of storage available. Since the reset vector has to be contained in this early code memory, the bootblock is the best place to implement loading of other stages. Implement a bootblock which does the minimal initialization, up to, and including switch to protected mode. This then transfers control to platform-specific code. No stack is needed, and control is transferred via a "jmp" such that no stack operations are involved. BUG=chrome-os-partner:51844 BRANCH=none TEST=none yet, the full stack of patches boots to payload on APLK Change-Id: I009b42b9a707cf11a74493bd4d8c189dc09b8ace Signed-off-by: Alexandru Gagniuc <mr.nuke.me@gmail.com> Reviewed-on: https://review.coreboot.org/13485 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/335961 Commit-Ready: Aaron Durbin <adurbin@chromium.org> Tested-by: Andrey Petrov <andrey.petrov@intel.com> Reviewed-by: Furquan Shaikh <furquan@chromium.org> " fail_count="1" gerrit_number="335961" owner_email="andrey.petrov@intel.com" pass_count="0" patch_number="3" project="chromiumos/third_party/coreboot" project_url="https://chromium-review.googlesource.com/chromiumos/third_party/coreboot" ref="refs/changes/61/335961/3" remote="cros" total_fail_count="1"/><pending_commit branch="chromeos-2016.02" change_id="I7f9e5f564181071591a4640019f59f91a4c456c6" commit="5188ba15f6f16cc1a8104d54f09580d98857307f" commit_message="UPSTREAM: soc/intel: Add skeleton infrastructure for Apollolake SOC This is the very very minimum needed to compile the code. BUG=chrome-os-partner:51844 BRANCH=none TEST=none yet, the full stack of patches boots to payload on APLK Change-Id: I7f9e5f564181071591a4640019f59f91a4c456c6 Signed-off-by: Alexandru Gagniuc <alexandrux.gagniuc@intel.com> Reviewed-on: https://review.coreboot.org/13297 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/335962 Commit-Ready: Aaron Durbin <adurbin@chromium.org> Tested-by: Andrey Petrov <andrey.petrov@intel.com> Reviewed-by: Furquan Shaikh <furquan@chromium.org> " fail_count="1" gerrit_number="335962" owner_email="andrey.petrov@intel.com" pass_count="0" patch_number="3" project="chromiumos/third_party/coreboot" project_url="https://chromium-review.googlesource.com/chromiumos/third_party/coreboot" ref="refs/changes/62/335962/3" remote="cros" total_fail_count="1"/><pending_commit branch="chromeos-2016.02" change_id="If2fea66d4b054be4555f5f172ea5945620648325" commit="b6cd2ccb5fcd188290780a9a92ccde7c68dc780f" commit_message="UPSTREAM: soc/intel/common: Use SoC specific routine to read/write MTRRs The registers associated with the MTRRs for Quark are referenced through a port on the host bridge. Support the standard configurations by providing a weak routines which just do a rdmsr/wrmsr. Testing: * Edit the src/mainboard/intel/galileo/Makefile.inc file * Add "select DISPLAY_MTRRS" * Add "select HAVE_FSP_PDAT_FILE" * Add "select HAVE_FSP_RAW_BIN" * Add "select HAVE_RMU_FILE" * Place the FSP.bin file in the location specified by CONFIG_FSP_FILE * Place the pdat.bin files in the location specified by CONFIG_FSP_PDAT_FILE * Place the rmu.bin file in the location specified by CONFIG_RMU_FILE * Testing is successful if: * The MTRRs are displayed and * The message "FspTempRamExit returned successfully" is displayed TEST=Build and run on Galileo BUG=chrome-os-partner:51844 BRANCH=none TEST=none yet, the full stack of patches boots to payload on APLK Change-Id: If2fea66d4b054be4555f5f172ea5945620648325 Signed-off-by: Lee Leahy <leroy.p.leahy@intel.com> Reviewed-on: https://review.coreboot.org/13529 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins) Reviewed-on: https://chromium-review.googlesource.com/335963 Commit-Ready: Aaron Durbin <adurbin@chromium.org> Tested-by: Andrey Petrov <andrey.petrov@intel.com> " fail_count="1" gerrit_number="335963" owner_email="andrey.petrov@intel.com" pass_count="0" patch_number="3" project="chromiumos/third_party/coreboot" project_url="https://chromium-review.googlesource.com/chromiumos/third_party/coreboot" ref="refs/changes/63/335963/3" remote="cros" total_fail_count="1"/><pending_commit branch="chromeos-2016.02" change_id="I8dec768cf8763dbe235f0ba1339079ebc49cbd9a" commit="84406e57c2ed9cbae6a98fb83d27d15c452f0246" commit_message="UPSTREAM: arch/x86: Reserve space for stack in CAR layout Some platforms may want to use C code in bootblock so they need writable memory and CAR can be used for it. This change reserves memory in CAR that can be used by bootblock and other CAR stages. BUG=chrome-os-partner:51844 BRANCH=none TEST=none yet, the full stack of patches boots to payload on APLK Change-Id: I8dec768cf8763dbe235f0ba1339079ebc49cbd9a Signed-off-by: Andrey Petrov <andrey.petrov@intel.com> Reviewed-on: https://review.coreboot.org/13640 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins) Reviewed-on: https://chromium-review.googlesource.com/335964 Commit-Ready: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Furquan Shaikh <furquan@chromium.org> " fail_count="1" gerrit_number="335964" owner_email="andrey.petrov@intel.com" pass_count="0" patch_number="3" project="chromiumos/third_party/coreboot" project_url="https://chromium-review.googlesource.com/chromiumos/third_party/coreboot" ref="refs/changes/64/335964/3" remote="cros" total_fail_count="1"/><pending_commit branch="chromeos-2016.02" change_id="Ifc705016290807c49dc8c49b581864cac2ad3f80" commit="4df2b1bc38400a41ac7cabfa95dffeb972eeb80f" commit_message="UPSTREAM: arch/x86: Allow bootblock code to use CAR_GLOBAL variables Since cbmem is not initialized in bootblock, CAR_GLOBAL variables can only be accessed directly similar to verstage. BUG=chrome-os-partner:51844 BRANCH=none TEST=none yet, the full stack of patches boots to payload on APLK Change-Id: Ifc705016290807c49dc8c49b581864cac2ad3f80 Signed-off-by: Andrey Petrov <andrey.petrov@intel.com> Reviewed-on: https://review.coreboot.org/13641 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins) Reviewed-on: https://chromium-review.googlesource.com/335965 Commit-Ready: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Furquan Shaikh <furquan@chromium.org> " fail_count="1" gerrit_number="335965" owner_email="andrey.petrov@intel.com" pass_count="0" patch_number="3" project="chromiumos/third_party/coreboot" project_url="https://chromium-review.googlesource.com/chromiumos/third_party/coreboot" ref="refs/changes/65/335965/3" remote="cros" total_fail_count="1"/><pending_commit branch="chromeos-2016.02" change_id="I218f3b4044175b89697790c82c384b0f85a27ade" commit="45d7d243599e6d2419ba707c1c8abaaaf159481b" commit_message="UPSTREAM: arch/x86: Change how BOOTBLOCK_CUSTOM is selected by default Currently x86s select BOOTBLOCK_CUSTOM by default. With this change BOOTBLOCK_CUSTOM is selected only if C bootblock isn't. BUG=chrome-os-partner:51844 BRANCH=none TEST=none yet, the full stack of patches boots to payload on APLK Change-Id: I218f3b4044175b89697790c82c384b0f85a27ade Signed-off-by: Andrey Petrov <andrey.petrov@intel.com> Reviewed-on: https://review.coreboot.org/13642 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins) Reviewed-on: https://chromium-review.googlesource.com/335966 Commit-Ready: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Furquan Shaikh <furquan@chromium.org> " fail_count="1" gerrit_number="335966" owner_email="andrey.petrov@intel.com" pass_count="0" patch_number="3" project="chromiumos/third_party/coreboot" project_url="https://chromium-review.googlesource.com/chromiumos/third_party/coreboot" ref="refs/changes/66/335966/3" remote="cros" total_fail_count="1"/><pending_commit branch="chromeos-2016.02" change_id="I7da6a060a91b83f3b32c5c5d269c102ce7ae3b8a" commit="aee87f1695f4b727b5d441f21e05002caef533f0" commit_message="UPSTREAM: cpu/x86/tsc: Compile delay_tsc.c for the bootblock as well This is needed in a follow-on patch to enable udelay() handling on apollolake, which is a dependency for the console code. BUG=chrome-os-partner:51844 BRANCH=none TEST=none yet, the full stack of patches boots to payload on APLK Change-Id: I7da6a060a91b83f3b32c5c5d269c102ce7ae3b8a Signed-off-by: Alexandru Gagniuc <alexandrux.gagniuc@intel.com> Reviewed-on: https://review.coreboot.org/13302 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/335967 Commit-Ready: Aaron Durbin <adurbin@chromium.org> Tested-by: Andrey Petrov <andrey.petrov@intel.com> Reviewed-by: Furquan Shaikh <furquan@chromium.org> " fail_count="1" gerrit_number="335967" owner_email="andrey.petrov@intel.com" pass_count="0" patch_number="3" project="chromiumos/third_party/coreboot" project_url="https://chromium-review.googlesource.com/chromiumos/third_party/coreboot" ref="refs/changes/67/335967/3" remote="cros" total_fail_count="1"/><pending_commit branch="chromeos-2016.02" change_id="I65c51f972580609d2c1f03dfe2a86bc5d45d1e46" commit="130c03b85a1658b57db1701f2b1ab403e9fa3ece" commit_message="UPSTREAM: soc/apollolake: Add initial cache-as-ram setup for bootblock This is the minimum setup needed to both get cache-as-ram setup and a C environment working. On apollolake, we only get 32 KiB of data loaded into an SRAM that is readonly to the main CPU. Due to this restriction we have to set CAR and a C environment very early on. BUG=chrome-os-partner:51844 BRANCH=none TEST=none yet, the full stack of patches boots to payload on APLK Change-Id: I65c51f972580609d2c1f03dfe2a86bc5d45d1e46 Signed-off-by: Alexandru Gagniuc <alexandrux.gagniuc@intel.com> Signed-off-by: Andrey Petrov <andrey.petrov@intel.com> Reviewed-on: https://review.coreboot.org/13301 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins) Reviewed-on: https://chromium-review.googlesource.com/335968 Commit-Ready: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Furquan Shaikh <furquan@chromium.org> " fail_count="1" gerrit_number="335968" owner_email="andrey.petrov@intel.com" pass_count="0" patch_number="3" project="chromiumos/third_party/coreboot" project_url="https://chromium-review.googlesource.com/chromiumos/third_party/coreboot" ref="refs/changes/68/335968/3" remote="cros" total_fail_count="1"/><pending_commit branch="chromeos-2016.02" change_id="I3e47c157c49ad55ff1ba824672ac2630a64a6037" commit="9c98f2a26375710ca15897e7dac333d6d2101e4b" commit_message="UPSTREAM: mainboard/intel: Add skeleton for Apollolake RVP board family RVP1 board comes with DDR3 SODIMMs and discrete VRs. RVP2 board uses LPDDR3 and PMIC. BUG=chrome-os-partner:51844 BRANCH=none TEST=none yet, the full stack of patches boots to payload on APLK Change-Id: I3e47c157c49ad55ff1ba824672ac2630a64a6037 Signed-off-by: Alexandru Gagniuc <alexandrux.gagniuc@intel.com> Signed-off-by: Andrey Petrov <andrey.petrov@intel.com> Reviewed-on: https://review.coreboot.org/13298 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins) Reviewed-on: https://chromium-review.googlesource.com/335969 Commit-Ready: Aaron Durbin <adurbin@chromium.org> " fail_count="1" gerrit_number="335969" owner_email="andrey.petrov@intel.com" pass_count="0" patch_number="3" project="chromiumos/third_party/coreboot" project_url="https://chromium-review.googlesource.com/chromiumos/third_party/coreboot" ref="refs/changes/69/335969/3" remote="cros" total_fail_count="1"/><pending_commit branch="chromeos-2016.02" change_id="I2e2268eee2b8c822b42a48a95604b0fab86c9833" commit="77eb485871495ec2d7481a8df0dd2c347d1d3180" commit_message="UPSTREAM: soc/apollolake: Add minimal GPIO driver This adds the minimal functionality needed to configure SoC pads. BUG=chrome-os-partner:51844 BRANCH=none TEST=none yet, the full stack of patches boots to payload on APLK Change-Id: I2e2268eee2b8c822b42a48a95604b0fab86c9833 Signed-off-by: Andrey Petrov <andrey.petrov@intel.com> Reviewed-on: https://review.coreboot.org/13676 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Tested-by: build bot (Jenkins) Reviewed-on: https://chromium-review.googlesource.com/335970 Commit-Ready: Aaron Durbin <adurbin@chromium.org> " fail_count="1" gerrit_number="335970" owner_email="andrey.petrov@intel.com" pass_count="0" patch_number="3" project="chromiumos/third_party/coreboot" project_url="https://chromium-review.googlesource.com/chromiumos/third_party/coreboot" ref="refs/changes/70/335970/3" remote="cros" total_fail_count="1"/><pending_commit branch="chromeos-2016.02" change_id="I15520d566f107797e68d618885d4379e73d0fa45" commit="09eb08f159298e1e38723b21a25325d1f0da1ce4" commit_message="UPSTREAM: soc/apollolake: Add early serial driver for BOOTBLOCK_CONSOLE Early UART driver is for bootblock and romstage. It is supposed to be used when BOOTBLOCK_CONSOLE is enabled. This also adds few configuration bits in bootblock requiered for serial to be set up. BUG=chrome-os-partner:51844 BRANCH=none TEST=none yet, the full stack of patches boots to payload on APLK Change-Id: I15520d566f107797e68d618885d4379e73d0fa45 Signed-off-by: Andrey Petrov <andrey.petrov@intel.com> Reviewed-on: https://review.coreboot.org/13677 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/335971 Commit-Ready: Aaron Durbin <adurbin@chromium.org> " fail_count="1" gerrit_number="335971" owner_email="andrey.petrov@intel.com" pass_count="0" patch_number="3" project="chromiumos/third_party/coreboot" project_url="https://chromium-review.googlesource.com/chromiumos/third_party/coreboot" ref="refs/changes/71/335971/3" remote="cros" total_fail_count="1"/><pending_commit branch="chromeos-2016.02" change_id="I0f90a74291c8a2ef7a1e1027d2d2182f896050fb" commit="188c37c8493528970f040643dcee3eec2a5b7979" commit_message="UPSTREAM: include/device: Move inline functions from pci_def.h to pci.h pci_def.h is supposed to only contain definitions, such that it may be included in assembly files. Declaration of functions in said file prevents that. BUG=chrome-os-partner:51844 BRANCH=none TEST=none yet, the full stack of patches boots to payload on APLK Change-Id: I0f90a74291c8a2ef7a1e1027d2d2182f896050fb Signed-off-by: Alexandru Gagniuc <mr.nuke.me@gmail.com> Reviewed-on: https://review.coreboot.org/13300 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/335972 Commit-Ready: Aaron Durbin <adurbin@chromium.org> Tested-by: Andrey Petrov <andrey.petrov@intel.com> " fail_count="1" gerrit_number="335972" owner_email="andrey.petrov@intel.com" pass_count="0" patch_number="3" project="chromiumos/third_party/coreboot" project_url="https://chromium-review.googlesource.com/chromiumos/third_party/coreboot" ref="refs/changes/72/335972/3" remote="cros" total_fail_count="1"/><pending_commit branch="master" change_id="Iacc02beba05ef3e80ffa59aa7fc5718c12bae20c" commit="ae3e12bd15cd2fc3cb1c49564f4dee213e734c65" commit_message="kevin: GPIO changes for new proto build BUG=chrome-os-partner:52171 TEST=Verify old kevin boards still boot + power sequence. BRANCH=None Change-Id: Iacc02beba05ef3e80ffa59aa7fc5718c12bae20c Signed-off-by: Shawn Nematbakhsh <shawnn@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/338043 Commit-Ready: Shawn N <shawnn@chromium.org> Tested-by: Shawn N <shawnn@chromium.org> Reviewed-by: Shawn N <shawnn@chromium.org> " fail_count="0" gerrit_number="338043" owner_email="shawnn@chromium.org" pass_count="0" patch_number="7" project="chromiumos/platform/ec" project_url="https://chromium-review.googlesource.com/chromiumos/platform/ec" ref="refs/changes/43/338043/7" remote="cros" total_fail_count="0"/><pending_commit branch="master" change_id="Ifdbdd2e975e463ab45d81ee6eaa4ba017a2f29c0" commit="3b0a9d20a1078ccab5043ab21978acf8c9719e49" commit_message="kevin: Decode board version Decode board version from analog voltage on BOARD_ID. BUG=chrome-os-partner:52642 BRANCH=None TEST=Verify 'ver' shows "Board: 0" on proto 1 board. Signed-off-by: Shawn Nematbakhsh <shawnn@chromium.org> Change-Id: Ifdbdd2e975e463ab45d81ee6eaa4ba017a2f29c0 Reviewed-on: https://chromium-review.googlesource.com/340241 Commit-Ready: Shawn N <shawnn@chromium.org> Tested-by: Shawn N <shawnn@chromium.org> Reviewed-by: Mary Ruthven <mruthven@chromium.org> " fail_count="0" gerrit_number="340241" owner_email="shawnn@chromium.org" pass_count="0" patch_number="8" project="chromiumos/platform/ec" project_url="https://chromium-review.googlesource.com/chromiumos/platform/ec" ref="refs/changes/41/340241/8" remote="cros" total_fail_count="0"/><pending_commit branch="master" change_id="I3e34b602595a03d888a9dfac9f74a77509b59399" commit="46ddd71d2ad2155cf367a1f6c385feaf0e8bcbac" commit_message="cros-disks: Add support for running without a session manager. BUG=chromium:605225 TEST=DeviceEventModeratorTest Change-Id: I3e34b602595a03d888a9dfac9f74a77509b59399 Reviewed-on: https://chromium-review.googlesource.com/339578 Commit-Ready: Mathieu Perreault <mathp@chromium.org> Tested-by: Mathieu Perreault <mathp@chromium.org> Reviewed-by: Andrew de los Reyes <adlr@chromium.org> Reviewed-by: Ben Chan <benchan@chromium.org> " fail_count="1" gerrit_number="339578" owner_email="mathp@chromium.org" pass_count="0" patch_number="8" project="chromiumos/platform2" project_url="https://chromium-review.googlesource.com/chromiumos/platform2" ref="refs/changes/78/339578/8" remote="cros" total_fail_count="1"/><pending_commit branch="master" change_id="I75ff069f7f9cf94cdb3adfa0a5f4574f912cad9f" commit="4363f36a3d6562ced16aba9d8bdf193ee9b6b436" commit_message="mmc-utils: Add blockprotect command set This patch adds a group of commands that allow controlling an eMMC's user partition write-protect features, which allow temporary, permanent or until-next-power-on write-protection of a write-protect block (which is a device-dependent multiple of an erase block). BUG=None TEST=Manual enabling, disabling and writing of a bunch of blocks on my Minnie. Change-Id: I75ff069f7f9cf94cdb3adfa0a5f4574f912cad9f Signed-off-by: Julius Werner <jwerner@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/340252 Reviewed-by: Gwendal Grignou <gwendal@google.com> " fail_count="0" gerrit_number="340252" owner_email="jwerner@chromium.org" pass_count="0" patch_number="5" project="chromiumos/third_party/mmc-utils" project_url="https://chromium-review.googlesource.com/chromiumos/third_party/mmc-utils" ref="refs/changes/52/340252/5" remote="cros" total_fail_count="0"/><lkgm version="8258.0.0-rc1"/></manifest> |
