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| <pending_commit branch="chromeos-4.4" change_id="I385927100a3fb55373dd284c5df2657a0bc4095f" commit="81a2fc6144e48b3262dda5611ff72be752930152" commit_message="FROMLIST: ARM64: dts: rockchip: make rk3399's grf a "simple-mfd" Per the examples in Documentation/devicetree/bindings/phy/rockchip-emmc-phy.txt, we need the grf node to be a simple-mfd in order to properly enumerate child devices like our eMMC PHY. Signed-off-by: Brian Norris <briannorris@chromium.org> (am from https://patchwork.kernel.org/patch/9093841/) BUG=chrome-os-partner:52691 TEST=boot to eMMC on kevin Change-Id: I385927100a3fb55373dd284c5df2657a0bc4095f Signed-off-by: Brian Norris <briannorris@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/344698 Reviewed-by: Douglas Anderson <dianders@chromium.org> " fail_count="0" gerrit_number="344698" owner_email="briannorris@chromium.org" pass_count="0" patch_number="1" project="chromiumos/third_party/kernel" project_url="https://chromium-review.googlesource.com/chromiumos/third_party/kernel" ref="refs/changes/98/344698/1" remote="cros" total_fail_count="0"/><pending_commit branch="chromeos-4.4" change_id="Id9c4fb119f606bdddb95d9a64e43a120616e6407" commit="e47224ebb0d3a65bd5cbf6c7e833dc620ca38113" commit_message="FROMLIST: ARM64: dts: rockchip: add sdhci/emmc for rk3399 Add description for the SDHCI v5.1 eMMC controller on rk3399. Fix it to 200 MHz, to support all supported timing modes. Note that 'rockchip,rk3399-sdhci-5.1' is not documented; we presumably have a compliant Arasan controller, but let's have a rockchip property as the canonical backup/precautionary measure. Per Heiko's previous suggestion, let's not clutter the arasan doc with it. Signed-off-by: Brian Norris <briannorris@chromium.org> (am from https://patchwork.kernel.org/patch/9093821/) BUG=chrome-os-partner:52691 TEST=boot to eMMC on kevin Change-Id: Id9c4fb119f606bdddb95d9a64e43a120616e6407 Signed-off-by: Brian Norris <briannorris@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/344348 Reviewed-by: Douglas Anderson <dianders@chromium.org> " fail_count="0" gerrit_number="344348" owner_email="briannorris@chromium.org" pass_count="0" patch_number="2" project="chromiumos/third_party/kernel" project_url="https://chromium-review.googlesource.com/chromiumos/third_party/kernel" ref="refs/changes/48/344348/2" remote="cros" total_fail_count="0"/><pending_commit branch="chromeos-4.4" change_id="I0122a664aeacc758de7dda4e99df0d21a09d3b93" commit="2ecc970f357593f021cb8f7490a1ba4d8ea2d23b" commit_message="FROMLIST: ARM64: dts: rockchip: enable eMMC for rk3399 EVB Rockchip's rk3399 evaluation board has eMMC. Let's enable the newly-added nodes. Signed-off-by: Brian Norris <briannorris@chromium.org> (am from https://patchwork.kernel.org/patch/9093861/) BUG=chrome-os-partner:52691 TEST=boot to eMMC on kevin Change-Id: I0122a664aeacc758de7dda4e99df0d21a09d3b93 Signed-off-by: Brian Norris <briannorris@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/344349 Reviewed-by: Douglas Anderson <dianders@chromium.org> " fail_count="0" gerrit_number="344349" owner_email="briannorris@chromium.org" pass_count="0" patch_number="2" project="chromiumos/third_party/kernel" project_url="https://chromium-review.googlesource.com/chromiumos/third_party/kernel" ref="refs/changes/49/344349/2" remote="cros" total_fail_count="0"/><pending_commit branch="chromeos-4.4" change_id="I35a6c8e62ac5085f43970de1ef63008b5e3ac5ee" commit="f5e71e53bc69e597a68d1a8c4bbf8e3de50db22c" commit_message="Revert "CHROMIUM: HACK: ARM64: dts: rockchip: disable 'mmc0' alias temporarily" This reverts commit 37972e78a54f1c84c31caeb9a4bbf980e2eb76da. We now have an sdhci node. BUG=none TEST=build; boot kevin and see eMMC as mmcblk0 Change-Id: I35a6c8e62ac5085f43970de1ef63008b5e3ac5ee Signed-off-by: Brian Norris <briannorris@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/344650 Reviewed-by: Douglas Anderson <dianders@chromium.org> " fail_count="0" gerrit_number="344650" owner_email="briannorris@chromium.org" pass_count="0" patch_number="2" project="chromiumos/third_party/kernel" project_url="https://chromium-review.googlesource.com/chromiumos/third_party/kernel" ref="refs/changes/50/344650/2" remote="cros" total_fail_count="0"/><pending_commit branch="chromeos-4.4" change_id="I91e677ebd37560d13d6269fbe6bfd855dc1b8daa" commit="9370be2a0884c79e28e6ae1d9874b7fa8376eb13" commit_message="FROMLIST: phy: rockchip-emmc: give DLL some extra time to be ready According to the databook, 10.2us is the max time for dll to be ready to work. However in testing, some chips need 20us for dll to be ready. This patch adds some extra margin for dllrdy to be ready, fixing our -ETIMEDOUT issues. Signed-off-by: Shawn Lin <shawn.lin@rock-chips.com> Signed-off-by: Brian Norris <briannorris@chromium.org> (am from https://patchwork.kernel.org/patch/9086501/) BUG=chrome-os-partner:52691 TEST=boot to eMMC on kevin Change-Id: I91e677ebd37560d13d6269fbe6bfd855dc1b8daa Signed-off-by: Brian Norris <briannorris@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/344651 Reviewed-by: Douglas Anderson <dianders@chromium.org> " fail_count="0" gerrit_number="344651" owner_email="briannorris@chromium.org" pass_count="0" patch_number="2" project="chromiumos/third_party/kernel" project_url="https://chromium-review.googlesource.com/chromiumos/third_party/kernel" ref="refs/changes/51/344651/2" remote="cros" total_fail_count="0"/><pending_commit branch="chromeos-4.4" change_id="I63b991ff9165c326d1df30eae2f4b15214d6e3e0" commit="d9476592a41c787fcec430c33c02edd257a4a505" commit_message="FROMLIST: phy: rockchip-emmc: configure frequency range and drive impedance Signal integrity analysis has suggested we set these values. Do this in power_on(), so that they get reconfigured after suspend/resume. Signed-off-by: Shawn Lin <shawn.lin@rock-chips.com> Signed-off-by: Brian Norris <briannorris@chromium.org> (am from https://patchwork.kernel.org/patch/9093681/) BUG=chrome-os-partner:52691 TEST=boot to eMMC on kevin Change-Id: I63b991ff9165c326d1df30eae2f4b15214d6e3e0 Signed-off-by: Brian Norris <briannorris@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/344652 Reviewed-by: Douglas Anderson <dianders@chromium.org> " fail_count="0" gerrit_number="344652" owner_email="briannorris@chromium.org" pass_count="0" patch_number="3" project="chromiumos/third_party/kernel" project_url="https://chromium-review.googlesource.com/chromiumos/third_party/kernel" ref="refs/changes/52/344652/3" remote="cros" total_fail_count="0"/><pending_commit branch="chromeos-4.4" change_id="Iec0261856450f73c3e0f2f4654141efed430756d" commit="ee6c1e60ccbcb710d297dd7d2e8a72327d362e1c" commit_message="FROMLIST: phy: rockchip-emmc: configure default output tap delay The output tap delay controls helps maintain the hold requirements for eMMC. The exact value is dependent on the SoC and other factors, though it isn't really an exact science. But the default of 0 is not very good, as it doesn't give the eMMC much hold time, so let's bump up to 4 (approx 90 degree phase?). If we need to configure this any further (e.g., based on board or speed factors), we may need to consider a device tree representation. Suggested-by: Shawn Lin <shawn.lin@rock-chips.com> Signed-off-by: Brian Norris <briannorris@chromium.org> (am from https://patchwork.kernel.org/patch/9086511/) BUG=chrome-os-partner:52691 TEST=boot to eMMC on kevin Change-Id: Iec0261856450f73c3e0f2f4654141efed430756d Signed-off-by: Brian Norris <briannorris@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/344653 Reviewed-by: Douglas Anderson <dianders@chromium.org> " fail_count="0" gerrit_number="344653" owner_email="briannorris@chromium.org" pass_count="0" patch_number="3" project="chromiumos/third_party/kernel" project_url="https://chromium-review.googlesource.com/chromiumos/third_party/kernel" ref="refs/changes/53/344653/3" remote="cros" total_fail_count="0"/><pending_commit branch="chromeos-4.4" change_id="Iccf3975af2cc61395cec061468cf4a025f4d92e0" commit="cc48e4889dd49e1f53b90a3bfed908642f02e660" commit_message="FROMLIST: phy: rockchip-emmc: reindent the register definitions Some of the spacing was wrong (spaces instead of tabs), and due to longer entries added later, the columns weren't aligned. Let's get everything consistent. Signed-off-by: Brian Norris <briannorris@chromium.org> (am from https://patchwork.kernel.org/patch/9086531/) BUG=chrome-os-partner:52691 TEST=boot to eMMC on kevin Change-Id: Iccf3975af2cc61395cec061468cf4a025f4d92e0 Signed-off-by: Brian Norris <briannorris@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/344654 Reviewed-by: Douglas Anderson <dianders@chromium.org> " fail_count="0" gerrit_number="344654" owner_email="briannorris@chromium.org" pass_count="0" patch_number="3" project="chromiumos/third_party/kernel" project_url="https://chromium-review.googlesource.com/chromiumos/third_party/kernel" ref="refs/changes/54/344654/3" remote="cros" total_fail_count="0"/><pending_commit branch="chromeos-3.18" change_id="Id77ac565b17e37a31996ceb972936298b224ad91" commit="671d7269eba22f177817b5a5510f46aad1463b87" commit_message="CHROMIUM: config: Enable MESH in the default config Default kernel configuration for Gale should have the Mesh enabled by default BUG=chrome-os-partner:49260 TEST=build validated Change-Id: Id77ac565b17e37a31996ceb972936298b224ad91 Signed-off-by: Sreedhar Sambangi <ssambang@codeaurora.org> Reviewed-on: https://chromium-review.googlesource.com/344424 Reviewed-by: Kan Yan <kyan@google.com> Reviewed-by: Suresh Rajashekara <sureshraj@chromium.org> " fail_count="0" gerrit_number="344424" owner_email="ssambang@codeaurora.org" pass_count="0" patch_number="4" project="chromiumos/third_party/kernel" project_url="https://chromium-review.googlesource.com/chromiumos/third_party/kernel" ref="refs/changes/24/344424/4" remote="cros" total_fail_count="0"/><pending_commit branch="chromeos-3.18" change_id="I18a4a9880a0c000d6af49eae9e6a55bf82c292d8" commit="414c78431b2427076a872990fe1325c1a766b704" commit_message="CHROMIUM: clk: ipq4019: add mux and div ops Adding support for mux select and mux divide on IPQ4019. BUG=chrome-os-partner:49262 TEST=clock changes needed for i2s / audio Change-Id: I18a4a9880a0c000d6af49eae9e6a55bf82c292d8 Signed-off-by: Pradeep Banavathi <pradeepb@codeaurora.org> Signed-off-by: Senthilkumar N L <snlakshm@codeaurora.org> Signed-off-by: Sreedhar Sambangi <ssambang@codeaurora.org> Signed-off-by: Varadarajan Narayanan <varada@codeaurora.org> Reviewed-on: https://chromium-review.googlesource.com/342781 Commit-Ready: Grant Grundler <grundler@chromium.org> Tested-by: Grant Grundler <grundler@chromium.org> Reviewed-by: Dmitry Torokhov <dtor@chromium.org> Reviewed-by: Grant Grundler <grundler@chromium.org> " fail_count="0" gerrit_number="342781" owner_email="ssambang@codeaurora.org" pass_count="0" patch_number="12" project="chromiumos/third_party/kernel" project_url="https://chromium-review.googlesource.com/chromiumos/third_party/kernel" ref="refs/changes/81/342781/12" remote="cros" total_fail_count="0"/><pending_commit branch="chromeos-3.18" change_id="Ibcfc4159b55e0a5fd82d3c382b88bd4f1b8985c4" commit="219a23f2786097ccd341e991dfd3c4bc308b784f" commit_message="CHROMIUM: qcom: ipq4019: fixup clock sources for apps_clk_src - Remove unused DDRPLLAPSS - Add new frequency plans to hit 710Mhz for Dakota - Base apss_clk_src of clk_cdiv_rcg2 - Include additional blocks after GCC_CLK_CTL_REG in regmap (GCC_DDRC_DAKOTA_DDRC_GLB_CSR, GCC_FEPLL_FEPLL_REG) BUG=chrome-os-partner:49255 TEST=CPUfreq goes to 710Mhz now Change-Id: Ibcfc4159b55e0a5fd82d3c382b88bd4f1b8985c4 Signed-off-by: Matthew McClintock <mmcclint@codeaurora.org> Reviewed-on: https://chromium-review.googlesource.com/343524 Commit-Ready: Grant Grundler <grundler@chromium.org> Tested-by: Grant Grundler <grundler@chromium.org> Reviewed-by: Grant Grundler <grundler@chromium.org> " fail_count="0" gerrit_number="343524" owner_email="mmcclint@qca.qualcomm.com" pass_count="0" patch_number="8" project="chromiumos/third_party/kernel" project_url="https://chromium-review.googlesource.com/chromiumos/third_party/kernel" ref="refs/changes/24/343524/8" remote="cros" total_fail_count="1"/><pending_commit branch="chromeos-3.18" change_id="I27e3d89c1576456c3ec6e5db68fed9e9f560a8b7" commit="bb2b227aa70697cbc279ca20421b2229bbd4a149" commit_message="CHROMIUM: qcom: ipq4019: add 710Mhz option for cpu speed This will let the CPU scale up to 710Mhz via the cpu freq driver BUG=chrome-os-partner:49255 TEST=CPUfreq goes to 710Mhz now Change-Id: I27e3d89c1576456c3ec6e5db68fed9e9f560a8b7 Signed-off-by: Matthew McClintock <mmcclint@codeaurora.org> Reviewed-on: https://chromium-review.googlesource.com/343525 Commit-Ready: Grant Grundler <grundler@chromium.org> Tested-by: Grant Grundler <grundler@chromium.org> Reviewed-by: Grant Grundler <grundler@chromium.org> " fail_count="0" gerrit_number="343525" owner_email="mmcclint@qca.qualcomm.com" pass_count="0" patch_number="8" project="chromiumos/third_party/kernel" project_url="https://chromium-review.googlesource.com/chromiumos/third_party/kernel" ref="refs/changes/25/343525/8" remote="cros" total_fail_count="3"/><pending_commit branch="chromeos-3.18" change_id="Ia509fcf71ceaf2fd7ec2e7842f98c16fa5c83f54" commit="86ba06a13d6e896bb69ca4380fb83200f746c377" commit_message="CHROMIUM: config: add cpu freq driver to gale defconfig This is required for CPU frequency scaling to work properly BUG=chrome-os-partner:49255 TEST=CPUfreq goes to 710Mhz now Change-Id: Ia509fcf71ceaf2fd7ec2e7842f98c16fa5c83f54 Signed-off-by: Matthew McClintock <mmcclint@codeaurora.org> Reviewed-on: https://chromium-review.googlesource.com/343526 Commit-Ready: Grant Grundler <grundler@chromium.org> Tested-by: Grant Grundler <grundler@chromium.org> Reviewed-by: Kan Yan <kyan@google.com> Reviewed-by: Grant Grundler <grundler@chromium.org> " fail_count="0" gerrit_number="343526" owner_email="mmcclint@qca.qualcomm.com" pass_count="0" patch_number="7" project="chromiumos/third_party/kernel" project_url="https://chromium-review.googlesource.com/chromiumos/third_party/kernel" ref="refs/changes/26/343526/7" remote="cros" total_fail_count="3"/><pending_commit branch="chromeos-4.4" change_id="Iaedeed1f2a4879ae65b8afb0cc3a5126e633f2d2" commit="db8c1c7c64e45d8ebaea22cb033fa79b9ee45ad1" commit_message="FROMLIST: clk: rockchip: mark rk3399 GIC clocks as critical We never want to kill the GIC. Noticed when making other clock fixups, and seeing the newly-constructed clock tree try to disable cpll, where we had this parent structure: aclk_gic <------\ |--- aclk_gic_pre <-- cpll <-- pll_cpll aclk_gic_noc <--/ Signed-off-by: Brian Norris <briannorris@chromium.org> (am from https://patchwork.kernel.org/patch/9092901/) BUG=chrome-os-partner:52691 TEST=boot to eMMC on kevin Change-Id: Iaedeed1f2a4879ae65b8afb0cc3a5126e633f2d2 Signed-off-by: Brian Norris <briannorris@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/344730 Reviewed-by: Douglas Anderson <dianders@chromium.org> " fail_count="0" gerrit_number="344730" owner_email="briannorris@chromium.org" pass_count="0" patch_number="1" project="chromiumos/third_party/kernel" project_url="https://chromium-review.googlesource.com/chromiumos/third_party/kernel" ref="refs/changes/30/344730/1" remote="cros" total_fail_count="0"/><pending_commit branch="chromeos-4.4" change_id="I3692f829b480fe3bfa0f3b34f6933b8b59a88b6e" commit="7f73c3e9300b7882353c29ccfbaabc3aee91c674" commit_message="FROMLIST: ARM64: dts: rockchip: assign default rates for core rk3399 clocks These clocks are all core clocks used by many blocks/peripherals, many of whose drivers don't set their clock rates at all. Let's assign reasonable default clock rates for these core clocks, so that these peripherals get something reasonable by default, and also so that if child devices want to select a clock rate themselves, their muxes have some reasonable parent clock rates to branch off of (rather than just the boot-time defaults). This helps the eMMC PHY, for one, to get a reasonable ACLK rate. Signed-off-by: Xing Zheng <zhengxing@rock-chips.com> Signed-off-by: Brian Norris <briannorris@chromium.org> (am from https://patchwork.kernel.org/patch/9093481/) BUG=chrome-os-partner:52691 TEST=boot to eMMC on kevin Change-Id: I3692f829b480fe3bfa0f3b34f6933b8b59a88b6e Signed-off-by: Brian Norris <briannorris@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/344731 Reviewed-by: Douglas Anderson <dianders@chromium.org> " fail_count="0" gerrit_number="344731" owner_email="briannorris@chromium.org" pass_count="0" patch_number="1" project="chromiumos/third_party/kernel" project_url="https://chromium-review.googlesource.com/chromiumos/third_party/kernel" ref="refs/changes/31/344731/1" remote="cros" total_fail_count="0"/><pending_commit branch="chromeos-4.4" change_id="I46cd77541b28ad0f6d1a8bfe62bd90d438d8bc3d" commit="9096d2f05bf7886eeba71eccbf3afa3f795a19ce" commit_message="FROMLIST: clk: rockchip: fix incorrect parent for rk3399's {c, g}pll_aclk_perihp_src There was a typo, swapping 'c' <--> 'g'. Signed-off-by: Xing Zheng <zhengxing@rock-chips.com> Signed-off-by: Brian Norris <briannorris@chromium.org> (am from https://patchwork.kernel.org/patch/9092891/) BUG=chrome-os-partner:52691 TEST=boot to eMMC on kevin Change-Id: I46cd77541b28ad0f6d1a8bfe62bd90d438d8bc3d Signed-off-by: Brian Norris <briannorris@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/344732 Reviewed-by: Douglas Anderson <dianders@chromium.org> " fail_count="0" gerrit_number="344732" owner_email="briannorris@chromium.org" pass_count="0" patch_number="1" project="chromiumos/third_party/kernel" project_url="https://chromium-review.googlesource.com/chromiumos/third_party/kernel" ref="refs/changes/32/344732/1" remote="cros" total_fail_count="0"/><pending_commit branch="master" change_id="I3d54c866c44d66120fffdf93cdfb750670e25fb0" commit="c5aa582a82cda562a01bdbc8edee4fed079fc47b" commit_message="eclass: Add golang-* eclasses from gentoo upstream These are used by some of the new packages like app-emulation/containerd and app-emulation/runc etc. Taken at upstream commit d9abb73c24f7bd9fb93fff5664e01ad2c7b4b4f1. BUG=None TEST=trybots Change-Id: I3d54c866c44d66120fffdf93cdfb750670e25fb0 Reviewed-on: https://chromium-review.googlesource.com/344643 Commit-Ready: Aditya Kali <adityakali@google.com> Tested-by: Aditya Kali <adityakali@google.com> Reviewed-by: Mike Frysinger <vapier@chromium.org> " fail_count="0" gerrit_number="344643" owner_email="adityakali@google.com" pass_count="0" patch_number="1" project="chromiumos/overlays/portage-stable" project_url="https://chromium-review.googlesource.com/chromiumos/overlays/portage-stable" ref="refs/changes/43/344643/1" remote="cros" total_fail_count="0"/><lkgm version="8320.0.0-rc1"/></manifest> |
