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| <pending_commit branch="chromeos-4.4" change_id="Ic5ffb713bd1b16fc60b3d03da153100efb200ccb" commit="5ead36de022df89f72426d8d8ab6e06dc142cf12" commit_message="UPSTREAM: drm/i915: Dump pfit PGM_RATIOS as hex pgm_ratios in stored as a register value in pipe config, so let's dump this one as hex as well. Signed-off-by: Ville Syrjl <ville.syrjala@linux.intel.com> Link: http://patchwork.freedesktop.org/patch/msgid/1458052809-23426-15-git-send-email-ville.syrjala@linux.intel.com Reviewed-by: Jani Nikula <jani.nikula@intel.com> (cherry picked from commit 7f7d8dd62cb8d7697c58a5b0266b11446d97e12d from drm-intel-next-2016-04-25) Signed-off-by: Tarun Vyas <tarun.vyas@intel.com> BUG=chrome-os-partner:52640 TEST=Image builds, boots and is browse-able Change-Id: Ic5ffb713bd1b16fc60b3d03da153100efb200ccb Reviewed-on: https://chromium-review.googlesource.com/345244 Commit-Ready: Wayne Boyer <wayne.boyer@intel.com> Tested-by: Russ Sage <russ.sage@intel.com> Reviewed-by: Stéphane Marchesin <marcheu@chromium.org> " fail_count="2" gerrit_number="345244" owner_email="tarun.vyas@intel.com" pass_count="0" patch_number="1" project="chromiumos/third_party/kernel" project_url="https://chromium-review.googlesource.com/chromiumos/third_party/kernel" ref="refs/changes/44/345244/1" remote="cros" total_fail_count="2"/><pending_commit branch="chromeos-4.4" change_id="I2106b9d21531351e456f69febd5c57c062a4e973" commit="34ef592b2d8e8ff372fdc547742db6ecde485f59" commit_message="UPSTREAM: drm/i915: Don't read out port_clock on CHV when DPLL is disabled Check whether the DPLL is even enabled before readoing out the dividers and trying to derive port_clock on CHV. We already did this on VLV. Also remove the comment "MIPI" comment from the VLV code since we call this function whenever the pipe is enabled. Signed-off-by: Ville Syrjl <ville.syrjala@linux.intel.com> Link: http://patchwork.freedesktop.org/patch/msgid/1458052809-23426-9-git-send-email-ville.syrjala@linux.intel.com Reviewed-by: Jani Nikula <jani.nikula@intel.com> (cherry picked from commit b521973b45efe496ef7482a1ef98a2986c57839e from drm-intel-next-2016-04-25) Signed-off-by: Tarun Vyas <tarun.vyas@intel.com> BUG=chrome-os-partner:52640 TEST=Image builds, boots and is browse-able Change-Id: I2106b9d21531351e456f69febd5c57c062a4e973 Reviewed-on: https://chromium-review.googlesource.com/345245 Commit-Ready: Wayne Boyer <wayne.boyer@intel.com> Tested-by: Russ Sage <russ.sage@intel.com> Reviewed-by: Stéphane Marchesin <marcheu@chromium.org> " fail_count="2" gerrit_number="345245" owner_email="tarun.vyas@intel.com" pass_count="0" patch_number="1" project="chromiumos/third_party/kernel" project_url="https://chromium-review.googlesource.com/chromiumos/third_party/kernel" ref="refs/changes/45/345245/1" remote="cros" total_fail_count="2"/><pending_commit branch="chromeos-4.4" change_id="Iaf1968e00c6ceaf6e7d974781ee49649c3dc3789" commit="9af344068d9950cfb98d0c141e4d2100ccb99082" commit_message="UPSTREAM: drm/i915: Split execlists hardware status page initialisation from setup Split the hardware status page into setup and initialisation, where setup means setting up the driver state to support the engine, and initialization means programming the hardware with the before set up state. This way the design matches the design of the engine setup/init code which is split in the same fashion and it enables the stages to be used in a balanced fashion (engine setup - hws setup, engine init - hws init). This will enable the upcoming improvements to slot in without any kludges on the GPU reset path. Signed-off-by: Tvrtko Ursulin <tvrtko.ursulin@intel.com> Suggested-by: Chris Wilson <chris@chris-wilson.co.uk> Cc: Chris Wilson <chris@chris-wilson.co.uk> Reviewed-by: Chris Wilson <chris@chris-wilson.co.uk> (cherry picked from commit 04794adbdde0008215748414e63a5c3734e1f9fc from drm-intel-next-2016-04-25) Signed-off-by: Tarun Vyas <tarun.vyas@intel.com> BUG=chrome-os-partner:52640 TEST=Image builds, boots and is browse-able Change-Id: Iaf1968e00c6ceaf6e7d974781ee49649c3dc3789 Reviewed-on: https://chromium-review.googlesource.com/345246 Commit-Ready: Wayne Boyer <wayne.boyer@intel.com> Tested-by: Russ Sage <russ.sage@intel.com> Reviewed-by: Stéphane Marchesin <marcheu@chromium.org> " fail_count="2" gerrit_number="345246" owner_email="tarun.vyas@intel.com" pass_count="0" patch_number="1" project="chromiumos/third_party/kernel" project_url="https://chromium-review.googlesource.com/chromiumos/third_party/kernel" ref="refs/changes/46/345246/1" remote="cros" total_fail_count="2"/><pending_commit branch="chromeos-4.4" change_id="I265251b3e9b6e19582db692782875daf46dc8820" commit="6f108189600cee1f0f237d8b9247527cf19b8c0c" commit_message="UPSTREAM: drm/i915: Use new i915_gem_object_pin_map for LRC We can use the new pin/lazy unpin API for simplicity and more performance in the execlist submission paths. v2: * Fix error handling and convert more users. * Compact some names for readability. v3: * intel_lr_context_free was not unpinning. * Special case for GPU reset which otherwise unbalances the HWS object pages pin count by running the engine initialization only (not destructors). v4: * Rebased on top of hws setup/init split. Signed-off-by: Tvrtko Ursulin <tvrtko.ursulin@intel.com> Cc: Chris Wilson <chris@chris-wilson.co.uk> Link: http://patchwork.freedesktop.org/patch/msgid/1460472042-1998-1-git-send-email-tvrtko.ursulin@linux.intel.com [tursulin: renames: s/hwd/hws/, s/obj_addr/vaddr/] Reviewed-by: Chris Wilson <chris@chris-wilson.co.uk> (cherry picked from commit 7d774cacf0b5d9fc4abac00fd25df09d019619f9 from drm-intel-next-2016-04-25) Signed-off-by: Tarun Vyas <tarun.vyas@intel.com> BUG=chrome-os-partner:52640 TEST=Image builds, boots and is browse-able Change-Id: I265251b3e9b6e19582db692782875daf46dc8820 Reviewed-on: https://chromium-review.googlesource.com/345247 Commit-Ready: Wayne Boyer <wayne.boyer@intel.com> Tested-by: Russ Sage <russ.sage@intel.com> Reviewed-by: Stéphane Marchesin <marcheu@chromium.org> " fail_count="2" gerrit_number="345247" owner_email="tarun.vyas@intel.com" pass_count="0" patch_number="1" project="chromiumos/third_party/kernel" project_url="https://chromium-review.googlesource.com/chromiumos/third_party/kernel" ref="refs/changes/47/345247/1" remote="cros" total_fail_count="2"/><pending_commit branch="chromeos-4.4" change_id="I1479da175ec582db29c173e630285ea28f9754fe" commit="7dee45d8afd7e32674f80c400a68b1a7c23210e9" commit_message="UPSTREAM: drm/i915: add INTEL_GEN() helper shorthand for INTEL_INFO()->gen Sudden realization: $ grep -ho "INTEL_INFO([^)]*)->[a-zA-Z0-9_]*" *.[ch] | sed 's/.*->//' |\ sort | uniq -c | sort -rn | head -5 446 gen 24 num_pipes 10 ring_mask 9 color 4 subslice_per_slice Acked-by: Chris Wilson <chris@chris-wilson.co.uk> Signed-off-by: Jani Nikula <jani.nikula@intel.com> Link: http://patchwork.freedesktop.org/patch/msgid/1460022497-29304-1-git-send-email-jani.nikula@intel.com (cherry picked from commit 3f10e82fe10d87d2fd558ef51c34abaf2ee538d2 from drm-intel-next-2016-04-25) Signed-off-by: Tarun Vyas <tarun.vyas@intel.com> BUG=chrome-os-partner:52640 TEST=Image builds, boots and is browse-able Change-Id: I1479da175ec582db29c173e630285ea28f9754fe Reviewed-on: https://chromium-review.googlesource.com/345248 Commit-Ready: Wayne Boyer <wayne.boyer@intel.com> Tested-by: Russ Sage <russ.sage@intel.com> Reviewed-by: Stéphane Marchesin <marcheu@chromium.org> " fail_count="2" gerrit_number="345248" owner_email="tarun.vyas@intel.com" pass_count="0" patch_number="1" project="chromiumos/third_party/kernel" project_url="https://chromium-review.googlesource.com/chromiumos/third_party/kernel" ref="refs/changes/48/345248/1" remote="cros" total_fail_count="2"/><pending_commit branch="chromeos-4.4" change_id="I83fb499cda45c768ac42ab52cfb179b649edd360" commit="90507d0a5465f31abec9bcb0a1dc3dde1066907e" commit_message="UPSTREAM: drm/i915/skl: Fix rc6 based gpu/system hang For all gt3 and gt4 skylake variants, extend the usage of WaRsDisableCoarsePowerGating for all revisions. Without this gt3 and gt4 skylakes up to atleast rev 0xa can gpu hang or system hang. Cc: Abdiel Janulgue <abdiel.janulgue@linux.intel.com> Cc: Ben Widawsky <benjamin.widawsky@intel.com> Cc: Timo Aaltonen <tjaalton@ubuntu.com> Cc: <stable@vger.kernel.org> Reported-by: Mikael Djurfeldt <mikael@djurfeldt.com> References: https://bugs.freedesktop.org/show_bug.cgi?id=94161 Signed-off-by: Mika Kuoppala <mika.kuoppala@intel.com> Reviewed-by: Ben Widawsky <benjamin.widawsky@intel.com> Tested-by: Timo Aaltonen <tjaalton@ubuntu.com> Link: http://patchwork.freedesktop.org/patch/msgid/1459860977-27751-1-git-send-email-mika.kuoppala@intel.com (cherry picked from commit 185c66e57ce725afeb58a3cfa48547706af3a7af from drm-intel-next-2016-04-25) Signed-off-by: Tarun Vyas <tarun.vyas@intel.com> BUG=chrome-os-partner:52640 TEST=Image builds, boots and is browse-able Change-Id: I83fb499cda45c768ac42ab52cfb179b649edd360 Reviewed-on: https://chromium-review.googlesource.com/345249 Commit-Ready: Wayne Boyer <wayne.boyer@intel.com> Tested-by: Russ Sage <russ.sage@intel.com> Reviewed-by: Stéphane Marchesin <marcheu@chromium.org> " fail_count="2" gerrit_number="345249" owner_email="tarun.vyas@intel.com" pass_count="0" patch_number="1" project="chromiumos/third_party/kernel" project_url="https://chromium-review.googlesource.com/chromiumos/third_party/kernel" ref="refs/changes/49/345249/1" remote="cros" total_fail_count="2"/><pending_commit branch="chromeos-4.4" change_id="Ida9eba50b51e08e59be6860e17c16e3491cb1d87" commit="2a10b8b44b4abffd8f59a7f10024280739f066a6" commit_message="UPSTREAM: drm/i915/skl: Fix spurious gpu hang with gt3/gt4 revs Experiments with heaven 4.0 benchmark and skylake gt3e (rev 0xa) suggest that WaForceContextSaveRestoreNonCoherent is needed for all revs. Extending this to all revs cures a gpu hang with rev 0xa when running heaven4.0 gpu benchmark. We have been here before, with problems enabling gt4e and extending up to revision F0 instead of false claims of bspec of E0 only. See commit <e238659ddd88> ("drm/i915/skl: Default to noncoherent access up to F0"). In retrospect we should have covered this with this big blanket back then already, as E0 vs F0 discrepancy was suspicious enough. Previously the WaForceEnableNonCoherent has been tied to context non-coherence, atleast in relevant hsds. So keep this tie and extended this alongside. Cc: Abdiel Janulgue <abdiel.janulgue@linux.intel.com> Cc: Ben Widawsky <benjamin.widawsky@intel.com> Cc: Timo Aaltonen <tjaalton@ubuntu.com> Cc: stable@vger.kernel.org Reported-by: Mike Lothian <mike@fireburn.co.uk> References: https://bugs.freedesktop.org/show_bug.cgi?id=93491 Signed-off-by: Mika Kuoppala <mika.kuoppala@intel.com> Reviewed-by: Ben Widawsky <benjamin.widawsky@intel.com> Tested-by: Timo Aaltonen <tjaalton@ubuntu.com> Link: http://patchwork.freedesktop.org/patch/msgid/1459860977-27751-2-git-send-email-mika.kuoppala@intel.com (cherry picked from commit 97ea6be161c55dec896b65c95157d953c330ae05 from drm-intel-next-2016-04-25) Signed-off-by: Tarun Vyas <tarun.vyas@intel.com> BUG=chrome-os-partner:52640 TEST=Image builds, boots and is browse-able Change-Id: Ida9eba50b51e08e59be6860e17c16e3491cb1d87 Reviewed-on: https://chromium-review.googlesource.com/345250 Commit-Ready: Wayne Boyer <wayne.boyer@intel.com> Tested-by: Russ Sage <russ.sage@intel.com> Reviewed-by: Stéphane Marchesin <marcheu@chromium.org> " fail_count="2" gerrit_number="345250" owner_email="tarun.vyas@intel.com" pass_count="0" patch_number="1" project="chromiumos/third_party/kernel" project_url="https://chromium-review.googlesource.com/chromiumos/third_party/kernel" ref="refs/changes/50/345250/1" remote="cros" total_fail_count="2"/><pending_commit branch="chromeos-4.4" change_id="Ic774442658c5130e579ae9167ec4f412debe16f9" commit="3a8366fcbea3b7620fabe26e84b90dadf76cff95" commit_message="UPSTREAM: drm/i915: Adjust size of PIPE_CONTROL used for gen8 render seqno write We started to use PIPE_CONTROL to write render ring seqno in order to combat seqno write vs interrupt generation problems. This was introduced by commit 7c17d377374d ("drm/i915: Use ordered seqno write interrupt generation on gen8+ execlists"). On gen8+ size of PIPE_CONTROL with Post Sync Operation should be 6 dwords. When we're using older 5-dword variant it's possible to observe inconsistent values written by PIPE_CONTROL with Post Sync Operation from user batches, resulting in rendering corruptions. v2: Fix BAT failures v3: Comments on alignment and thrashing high dword of seqno (Chris) v4: Updated commit msg (Mika) Testcase: igt/gem_pipe_control_store_loop/*-qword-write Issue: VIZ-7393 Cc: stable@vger.kernel.org Cc: Chris Wilson <chris@chris-wilson.co.uk> Cc: Mika Kuoppala <mika.kuoppala@intel.com> Cc: Abdiel Janulgue <abdiel.janulgue@linux.intel.com> Signed-off-by: Micha Winiarski <michal.winiarski@intel.com> Reviewed-by: Mika Kuoppala <mika.kuoppala@intel.com> Reviewed-by: Chris Wilson <chris@chris-wilson.co.uk> Tested-by: Abdiel Janulgue <abdiel.janulgue@linux.intel.com> Signed-off-by: Mika Kuoppala <mika.kuoppala@intel.com> Link: http://patchwork.freedesktop.org/patch/msgid/1460469115-26002-1-git-send-email-michal.winiarski@intel.com (cherry picked from commit ce81a65c79d6012a384563caf76d47e28947a347 from drm-intel-next-2016-04-25) Signed-off-by: Tarun Vyas <tarun.vyas@intel.com> BUG=chrome-os-partner:52640 TEST=Image builds, boots and is browse-able Change-Id: Ic774442658c5130e579ae9167ec4f412debe16f9 Reviewed-on: https://chromium-review.googlesource.com/345251 Commit-Ready: Wayne Boyer <wayne.boyer@intel.com> Tested-by: Russ Sage <russ.sage@intel.com> Reviewed-by: Stéphane Marchesin <marcheu@chromium.org> " fail_count="2" gerrit_number="345251" owner_email="tarun.vyas@intel.com" pass_count="0" patch_number="1" project="chromiumos/third_party/kernel" project_url="https://chromium-review.googlesource.com/chromiumos/third_party/kernel" ref="refs/changes/51/345251/1" remote="cros" total_fail_count="2"/><pending_commit branch="chromeos-4.4" change_id="Idef5ff96ebe47bb43a13de139c9930a4193eb978" commit="eefb6b52197c9961a7303048101805b0e4c9e930" commit_message="UPSTREAM: drm/i915/opregion: remove unnecessary ifdefs on CONFIG_ACPI The whole file is ignored on CONFIG_ACPI=n. Reviewed-by: Ander Conselvan de Oliveira <conselvan2@gmail.com> Signed-off-by: Jani Nikula <jani.nikula@intel.com> Link: http://patchwork.freedesktop.org/patch/msgid/1460127589-8357-1-git-send-email-jani.nikula@intel.com (cherry picked from commit 3cb26e26edd12b11b98bbe2b8c89c3a0da79e390 from drm-intel-next-2016-04-25) Signed-off-by: Tarun Vyas <tarun.vyas@intel.com> BUG=chrome-os-partner:52640 TEST=Image builds, boots and is browse-able Change-Id: Idef5ff96ebe47bb43a13de139c9930a4193eb978 Reviewed-on: https://chromium-review.googlesource.com/345252 Commit-Ready: Wayne Boyer <wayne.boyer@intel.com> Tested-by: Russ Sage <russ.sage@intel.com> Reviewed-by: Stéphane Marchesin <marcheu@chromium.org> " fail_count="2" gerrit_number="345252" owner_email="tarun.vyas@intel.com" pass_count="0" patch_number="1" project="chromiumos/third_party/kernel" project_url="https://chromium-review.googlesource.com/chromiumos/third_party/kernel" ref="refs/changes/52/345252/1" remote="cros" total_fail_count="2"/><pending_commit branch="chromeos-4.4" change_id="Idfb2d250caecad098d158526f8892ef3574b97c3" commit="577fe7737852affc62c024271ee54ab5e6873af7" commit_message="UPSTREAM: drm/i915: Don't program eLLC IDI hash mask for gen9+ For gen9 onwards, eDRAM is a true memory side cache. So there is no need to program idi hash mask as it is for eLLC only. v2: INTEL_GEN (Chris), s/has/hash (Matthew) Signed-off-by: Mika Kuoppala <mika.kuoppala@intel.com> Reviewed-by: Matthew Auld <matthew.auld@intel.com> (cherry picked from commit 666fbcf5c21d8d8654b00b9c2e21a3caf070e9f8 from drm-intel-next-2016-04-25) Signed-off-by: Tarun Vyas <tarun.vyas@intel.com> BUG=chrome-os-partner:52640 TEST=Image builds, boots and is browse-able Change-Id: Idfb2d250caecad098d158526f8892ef3574b97c3 Reviewed-on: https://chromium-review.googlesource.com/345253 Commit-Ready: Wayne Boyer <wayne.boyer@intel.com> Tested-by: Russ Sage <russ.sage@intel.com> Reviewed-by: Stéphane Marchesin <marcheu@chromium.org> " fail_count="2" gerrit_number="345253" owner_email="tarun.vyas@intel.com" pass_count="0" patch_number="1" project="chromiumos/third_party/kernel" project_url="https://chromium-review.googlesource.com/chromiumos/third_party/kernel" ref="refs/changes/53/345253/1" remote="cros" total_fail_count="2"/><pending_commit branch="chromeos-4.4" change_id="Ib61ad002cc5c60115fed831b4cc747c6b032d21f" commit="ef8028ff5d602c1bda0e3df335247ec9923d7561" commit_message="UPSTREAM: drm/i915: Store and use edram capabilities Store the edram capabilities instead of only the size of edram. This is preparatory patch to allow edram size calculation based on edram capability bits for gen9+. With gen9 the edram is behind llc and is a separate entity. With hsw/bdw it was more of a victim cache for LLC so the name 'eLLC' might be warranted. Regardless, rename all mentions of eLLC to EDRAM to clear the confusion. v2: return bytes for edram size (Chris) s/eLLC/eDRAM in output if we are gen > 8 v3: rebase, INTEL_GEN (Chris) Signed-off-by: Mika Kuoppala <mika.kuoppala@intel.com> Reviewed-by: Chris Wilson <chris@chris-wilson.co.uk> (cherry picked from commit 3accaf7e734d691dd8494548da009a646426655c from drm-intel-next-2016-04-25) Signed-off-by: Tarun Vyas <tarun.vyas@intel.com> BUG=chrome-os-partner:52640 TEST=Image builds, boots and is browse-able Change-Id: Ib61ad002cc5c60115fed831b4cc747c6b032d21f Reviewed-on: https://chromium-review.googlesource.com/345254 Commit-Ready: Wayne Boyer <wayne.boyer@intel.com> Tested-by: Russ Sage <russ.sage@intel.com> Reviewed-by: Stéphane Marchesin <marcheu@chromium.org> " fail_count="2" gerrit_number="345254" owner_email="tarun.vyas@intel.com" pass_count="0" patch_number="1" project="chromiumos/third_party/kernel" project_url="https://chromium-review.googlesource.com/chromiumos/third_party/kernel" ref="refs/changes/54/345254/1" remote="cros" total_fail_count="2"/><pending_commit branch="chromeos-4.4" change_id="I0d5399b48212a305ceea1deec5ec3ae524031c59" commit="a9398b7f1a2ede86468be50893de676d098f3ee1" commit_message="UPSTREAM: drm/i915: Calculate edram size With gen9+ the edram capabilities are defined so that we can calculate the edram (ellc) size accordingly. Note that there are undefined combinations for some subset of edram capability bits. Return the closest size for undefined indexes. Even if we get it wrong with beginning of future gen enabling, the size information is currently only used for boot message and in debugfs entry. v2: Use function instead of hard to read macro (Daniel) v3: s/INTEL_INFO/INTEL_GEN (Matthew) Signed-off-by: Mika Kuoppala <mika.kuoppala@intel.com> Reviewed-by: Matthew Auld <matthew.auld@intel.com> Link: http://patchwork.freedesktop.org/patch/msgid/1460557604-7126-2-git-send-email-mika.kuoppala@intel.com (cherry picked from commit c02e85a06e191f9888f3d561a39b1dc55e934b3b from drm-intel-next-2016-04-25) Signed-off-by: Tarun Vyas <tarun.vyas@intel.com> BUG=chrome-os-partner:52640 TEST=Image builds, boots and is browse-able Change-Id: I0d5399b48212a305ceea1deec5ec3ae524031c59 Reviewed-on: https://chromium-review.googlesource.com/345255 Commit-Ready: Wayne Boyer <wayne.boyer@intel.com> Tested-by: Russ Sage <russ.sage@intel.com> Reviewed-by: Stéphane Marchesin <marcheu@chromium.org> " fail_count="2" gerrit_number="345255" owner_email="tarun.vyas@intel.com" pass_count="0" patch_number="1" project="chromiumos/third_party/kernel" project_url="https://chromium-review.googlesource.com/chromiumos/third_party/kernel" ref="refs/changes/55/345255/1" remote="cros" total_fail_count="2"/><pending_commit branch="master" change_id="I9a08b312be9392882472090dc8ed6cc3f85ea2e8" commit="f456acc4ac9cf9912c3b23a1aad458c3fd9c2641" commit_message="dome: add skeleton code for RESTful API of bundle management BUG=chromium:617496 TEST=None Change-Id: I9a08b312be9392882472090dc8ed6cc3f85ea2e8 Reviewed-on: https://chromium-review.googlesource.com/349860 Commit-Ready: Mao Huang <littlecvr@chromium.org> Tested-by: Mao Huang <littlecvr@chromium.org> Reviewed-by: Hung-Te Lin <hungte@chromium.org> " fail_count="0" gerrit_number="349860" owner_email="littlecvr@chromium.org" pass_count="0" patch_number="5" project="chromiumos/platform/factory" project_url="https://chromium-review.googlesource.com/chromiumos/platform/factory" ref="refs/changes/60/349860/5" remote="cros" total_fail_count="0"/><pending_commit branch="master" change_id="Ie27890a906a31d17ddd59082bfb266fc41283812" commit="a60c2c01472f2457d7fdb88bea28c09464438b26" commit_message="login: Bump auto-enrollment constants. This increases the auto-enrollment constants to start with a larger initial bucket size and also bumps the limits to allow for future growth. BUG=chromium:617930 TEST=Verified that auto-enrollment checks in Chrome still work with the new contants for good measure. Change-Id: Ie27890a906a31d17ddd59082bfb266fc41283812 Reviewed-on: https://chromium-review.googlesource.com/350310 Commit-Ready: Igor Covganet <igorcov@chromium.org> Tested-by: Igor Covganet <igorcov@chromium.org> Reviewed-by: Dan Erat <derat@chromium.org> Reviewed-by: Thiemo Nagel <tnagel@chromium.org> " fail_count="2" gerrit_number="350310" owner_email="igorcov@chromium.org" pass_count="0" patch_number="1" project="chromiumos/platform2" project_url="https://chromium-review.googlesource.com/chromiumos/platform2" ref="refs/changes/10/350310/1" remote="cros" total_fail_count="2"/><lkgm version="8447.0.0-rc3"/></manifest> |
