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| <pending_commit branch="chromeos-2016.05" change_id="Ie1269a4357e2fbd608ad8b7b8262275914730f6e" commit="2136b69eb780cd591b9ee1ee4d36c1794d12d793" commit_message="UPSTREAM: ec/lenovo/h8: Add USB Always On USB AO is the internal name for the dedicated charging port on ThinkPads when in S3 or lower. AOEN (bit 0) is internal name for enabling this feature while AOCF (bits 2 and 3) is the configuration field. According to Peter Stuge, AOCF can be configured in this way: 00 => AC S3 S4 S4 USB on, battery S3 USB on, battery S4 S5 off 11 => AC S3 S4 S4 USB on, battery S3 S4 S5 USB off 10, 01 => equivalent to 00 This commit also adds a new configuration field in the CMOS of the X220 and the X201 to activate this feature. It probably can be also added to all the ThinkPads that support this functionality. With this functionality USB devices are able to negotiate full power from the dedicated port (usually the yellow one) even in S3. Tested on a X201 and X220 with an Android smartphone: with this feature enabled it shows "Charging" when connected during S3, without it it shows "Charging slowly" (or it doesn't charge at all on the X201). For some reasons the "AC only" mode doesn't work, so it has been disabled. BUG=None BRANCH=None TEST=None Signed-off-by: Nicola Corna <nicola@corna.info> Reviewed-on: https://review.coreboot.org/17252 Tested-by: build bot (Jenkins) Reviewed-by: Nico Huber <nico.h@gmx.de> Change-Id: Ie1269a4357e2fbd608ad8b7b8262275914730f6e Reviewed-on: https://chromium-review.googlesource.com/413055 Commit-Ready: Furquan Shaikh <furquan@chromium.org> Tested-by: Furquan Shaikh <furquan@chromium.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org> " fail_count="0" gerrit_number="413055" owner_email="furquan@chromium.org" pass_count="0" patch_number="1" project="chromiumos/third_party/coreboot" project_url="https://chromium-review.googlesource.com/chromiumos/third_party/coreboot" ref="refs/changes/55/413055/1" remote="cros" total_fail_count="0"/><pending_commit branch="chromeos-2016.05" change_id="If825701450c78289cb8cca731d589e12aafced11" commit="db3657a2aeb535a292174ef2a32193ba2bea576a" commit_message="UPSTREAM: Makefile.inc: export VARIANT_DIR as top-level variable export VARIANT_DIR at the top level, rather than doing so multiple times at the SoC / board level BUG=None BRANCH=None TEST=None Signed-off-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-on: https://review.coreboot.org/17451 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com> Change-Id: If825701450c78289cb8cca731d589e12aafced11 Reviewed-on: https://chromium-review.googlesource.com/413056 Commit-Ready: Furquan Shaikh <furquan@chromium.org> Tested-by: Furquan Shaikh <furquan@chromium.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org> " fail_count="0" gerrit_number="413056" owner_email="furquan@chromium.org" pass_count="0" patch_number="1" project="chromiumos/third_party/coreboot" project_url="https://chromium-review.googlesource.com/chromiumos/third_party/coreboot" ref="refs/changes/56/413056/1" remote="cros" total_fail_count="0"/><pending_commit branch="chromeos-2016.05" change_id="I597ba3a03bd42c64d03137b10a3758d86b129029" commit="28b346a7fe9a24ba9bfab8f562a067a51cdc9c68" commit_message="UPSTREAM: sio/it8772f: add GPIO blink definition needed by google/tricky BUG=None BRANCH=None TEST=None Signed-off-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-on: https://review.coreboot.org/17452 Reviewed-by: Kysti Mlkki <kyosti.malkki@gmail.com> Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Change-Id: I597ba3a03bd42c64d03137b10a3758d86b129029 Reviewed-on: https://chromium-review.googlesource.com/413057 Commit-Ready: Furquan Shaikh <furquan@chromium.org> Tested-by: Furquan Shaikh <furquan@chromium.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org> " fail_count="0" gerrit_number="413057" owner_email="furquan@chromium.org" pass_count="0" patch_number="1" project="chromiumos/third_party/coreboot" project_url="https://chromium-review.googlesource.com/chromiumos/third_party/coreboot" ref="refs/changes/57/413057/1" remote="cros" total_fail_count="0"/><pending_commit branch="chromeos-2016.05" change_id="Ie2d0cf573876694fe87edf2f6915a5cc26238940" commit="05ba8c94727a4c1b89459649a78ed15e983719fe" commit_message="UPSTREAM: sb/lynxpoint: use hda_verb.c from VARIANT_DIR if applicable BUG=None BRANCH=None TEST=None Signed-off-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-on: https://review.coreboot.org/17453 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Martin Roth <martinroth@google.com> Change-Id: Ie2d0cf573876694fe87edf2f6915a5cc26238940 Reviewed-on: https://chromium-review.googlesource.com/413058 Commit-Ready: Furquan Shaikh <furquan@chromium.org> Tested-by: Furquan Shaikh <furquan@chromium.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org> " fail_count="0" gerrit_number="413058" owner_email="furquan@chromium.org" pass_count="0" patch_number="1" project="chromiumos/third_party/coreboot" project_url="https://chromium-review.googlesource.com/chromiumos/third_party/coreboot" ref="refs/changes/58/413058/1" remote="cros" total_fail_count="0"/><pending_commit branch="chromeos-2016.05" change_id="I5bbd100eeb673417da205a2c2c3410fef1af61f0" commit="b386d1956960409fc7745453e33019b3db0a1b26" commit_message="UPSTREAM: intel post-car: Increase stacktop alignment Align top of stack to 8 bytes, value documented as FSP1.1 requirement. Also fix some cases of uintptr_t casted to unsigned long. BUG=None BRANCH=None TEST=None Signed-off-by: Kysti Mlkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/17461 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Change-Id: I5bbd100eeb673417da205a2c2c3410fef1af61f0 Reviewed-on: https://chromium-review.googlesource.com/413059 Commit-Ready: Furquan Shaikh <furquan@chromium.org> Tested-by: Furquan Shaikh <furquan@chromium.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org> " fail_count="0" gerrit_number="413059" owner_email="furquan@chromium.org" pass_count="0" patch_number="1" project="chromiumos/third_party/coreboot" project_url="https://chromium-review.googlesource.com/chromiumos/third_party/coreboot" ref="refs/changes/59/413059/1" remote="cros" total_fail_count="0"/><pending_commit branch="chromeos-2016.05" change_id="I2afee3662e73e8e629188258b2f4119e02d60305" commit="5e7ef053d9216fa6ddb225b6c3ae4ec40a15a36e" commit_message="UPSTREAM: intel/sandybridge post-car: Redo MTRR settings and stack selection Adapt implementation from haswell to prepare for removal of HIGH_MEMORY_SAVE and moving on to RELOCATABLE_RAMSTAGE. With the change, CBMEM and SMM regions are set to WRBACK with MTRRs and romstage ram stack is moved to CBMEM. Also fixes regression of slower S3 resume path after commit 9b99152 intel/sandybridge: Use common ACPI S3 recovery Skipping low memory backup and using stage cache for ramstage decreases time spent on S3 resume path by 50 ms on samsung/lumpy. BUG=None BRANCH=None TEST=None Signed-off-by: Kysti Mlkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/15790 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins) Change-Id: I2afee3662e73e8e629188258b2f4119e02d60305 Reviewed-on: https://chromium-review.googlesource.com/413240 Commit-Ready: Furquan Shaikh <furquan@chromium.org> Tested-by: Furquan Shaikh <furquan@chromium.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org> " fail_count="0" gerrit_number="413240" owner_email="furquan@chromium.org" pass_count="0" patch_number="1" project="chromiumos/third_party/coreboot" project_url="https://chromium-review.googlesource.com/chromiumos/third_party/coreboot" ref="refs/changes/40/413240/1" remote="cros" total_fail_count="0"/><pending_commit branch="chromeos-2016.05" change_id="I5b218ce3046493b92952e47610c41b07efa4d1de" commit="b55a7af5b54bfea478452f9eeeedcda0446df2aa" commit_message="UPSTREAM: intel/sandybridge: Use romstage_handoff for S3 Don't use scratchpad registers when we have romstage_handoff to pass S3 resume flag. Also fixes console log from reporting early in ramstage "Normal boot" while on S3 resume path. BUG=None BRANCH=None TEST=None Signed-off-by: Kysti Mlkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/17455 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org> Change-Id: I5b218ce3046493b92952e47610c41b07efa4d1de Reviewed-on: https://chromium-review.googlesource.com/413241 Commit-Ready: Furquan Shaikh <furquan@chromium.org> Tested-by: Furquan Shaikh <furquan@chromium.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org> " fail_count="0" gerrit_number="413241" owner_email="furquan@chromium.org" pass_count="0" patch_number="1" project="chromiumos/third_party/coreboot" project_url="https://chromium-review.googlesource.com/chromiumos/third_party/coreboot" ref="refs/changes/41/413241/1" remote="cros" total_fail_count="0"/><pending_commit branch="chromeos-2016.05" change_id="I5021ad8c1581d1935b39875ffa3aa00b594c537a" commit="206fc052dde095f383a517d2b97fe8ec637d9bf9" commit_message="UPSTREAM: soc/intel/common/lpss_i2c: fix NULL dereference in error path If the SoC clock speed is not supported there is supposed to be an error printed. However, the value printed was wrong which was dereferencing a NULL struct. Fix that. BUG=None BRANCH=None TEST=None Found-by: Coverity Scan #1365977 Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: https://review.coreboot.org/17468 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Furquan Shaikh <furquan@google.com> Change-Id: I5021ad8c1581d1935b39875ffa3aa00b594c537a Reviewed-on: https://chromium-review.googlesource.com/413242 Commit-Ready: Furquan Shaikh <furquan@chromium.org> Tested-by: Furquan Shaikh <furquan@chromium.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org> " fail_count="0" gerrit_number="413242" owner_email="furquan@chromium.org" pass_count="0" patch_number="1" project="chromiumos/third_party/coreboot" project_url="https://chromium-review.googlesource.com/chromiumos/third_party/coreboot" ref="refs/changes/42/413242/1" remote="cros" total_fail_count="0"/><pending_commit branch="chromeos-2016.05" change_id="I6c92ede3d95590d95a42b40422bab88ea9ae72a1" commit="6387046e01bdd2da5d5018b6b1853bb963a5dbea" commit_message="UPSTREAM: soc/intel/common/lpss_i2c: correct bus speed error The wrong value was used for reporting an error when a requested bus speed was made that isn't supported. Use the requested value. BUG=None BRANCH=None TEST=None Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: https://review.coreboot.org/17474 Tested-by: build bot (Jenkins) Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Change-Id: I6c92ede3d95590d95a42b40422bab88ea9ae72a1 Reviewed-on: https://chromium-review.googlesource.com/413243 Commit-Ready: Furquan Shaikh <furquan@chromium.org> Tested-by: Furquan Shaikh <furquan@chromium.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org> " fail_count="0" gerrit_number="413243" owner_email="furquan@chromium.org" pass_count="0" patch_number="1" project="chromiumos/third_party/coreboot" project_url="https://chromium-review.googlesource.com/chromiumos/third_party/coreboot" ref="refs/changes/43/413243/1" remote="cros" total_fail_count="0"/><pending_commit branch="chromeos-2016.05" change_id="I038fda68b1cd05fa2e66135158e5e2d18567563a" commit="a113ac995361bb62b49601f203598e90c714e078" commit_message="UPSTREAM: commonlib/include: remove NEED_VB20_INTERNALS vboot_handoff.c is the only place that needs the vb2 internals. Provide it in the one place it is actually required instead of pulling in the headers unnecessarily in common code. There is, however, still a need to get the vb2 hashing types for a function declaration. BUG=None BRANCH=None TEST=None Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: https://review.coreboot.org/17475 Tested-by: build bot (Jenkins) Reviewed-by: Furquan Shaikh <furquan@google.com> Change-Id: I038fda68b1cd05fa2e66135158e5e2d18567563a Reviewed-on: https://chromium-review.googlesource.com/413244 Commit-Ready: Furquan Shaikh <furquan@chromium.org> Tested-by: Furquan Shaikh <furquan@chromium.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org> " fail_count="0" gerrit_number="413244" owner_email="furquan@chromium.org" pass_count="0" patch_number="1" project="chromiumos/third_party/coreboot" project_url="https://chromium-review.googlesource.com/chromiumos/third_party/coreboot" ref="refs/changes/44/413244/1" remote="cros" total_fail_count="0"/><pending_commit branch="chromeos-2016.05" change_id="I24fff6228bc5207750a3c4bf8cf34e91cf35e716" commit="a9575ff868055c52c4ce902c0a76abbdd3672ce1" commit_message="UPSTREAM: intel car: Move pre-ram stack guard lower SPD data alone consumes 0x400 of pre-ram stack, so the guard was initially set too high, printing spurious "smashed stack detected" messages at end of romstage. Use the same stack size as haswell. BUG=None BRANCH=None TEST=None Signed-off-by: Kysti Mlkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/17501 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org> Change-Id: I24fff6228bc5207750a3c4bf8cf34e91cf35e716 Reviewed-on: https://chromium-review.googlesource.com/413245 Commit-Ready: Furquan Shaikh <furquan@chromium.org> Tested-by: Furquan Shaikh <furquan@chromium.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org> " fail_count="0" gerrit_number="413245" owner_email="furquan@chromium.org" pass_count="0" patch_number="1" project="chromiumos/third_party/coreboot" project_url="https://chromium-review.googlesource.com/chromiumos/third_party/coreboot" ref="refs/changes/45/413245/1" remote="cros" total_fail_count="0"/><pending_commit branch="chromeos-2016.05" change_id="Ic91c5389cf4d47d28a6c54db152c18541c413bc1" commit="5b1b013c79a417b74aca2729a89ef833c8e27644" commit_message="UPSTREAM: arch/x86 GDT: Fix orphan debug output On S3 resume path, CBMEM_ID_GDT already exists but we only printed the final "ok" string. Always tell GDT is about to be moved. BUG=None BRANCH=None TEST=None Signed-off-by: Kysti Mlkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/17500 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org> Change-Id: Ic91c5389cf4d47d28a6c54db152c18541c413bc1 Reviewed-on: https://chromium-review.googlesource.com/413246 Commit-Ready: Furquan Shaikh <furquan@chromium.org> Tested-by: Furquan Shaikh <furquan@chromium.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org> " fail_count="0" gerrit_number="413246" owner_email="furquan@chromium.org" pass_count="0" patch_number="1" project="chromiumos/third_party/coreboot" project_url="https://chromium-review.googlesource.com/chromiumos/third_party/coreboot" ref="refs/changes/46/413246/1" remote="cros" total_fail_count="0"/><pending_commit branch="chromeos-2016.05" change_id="Ib90b5de872a219cf80b4976b6dfae6bc02e298f4" commit="0954b99d11427be9c3d9f8145f263b40101d8c3b" commit_message="UPSTREAM: nb/intel/sandybridge/raminit: Fix CAS Write Latency As documented in DDR3 spec for MR2 the CWL is based on DDR frequency. There's no to little difference for most memory modules operating at DDR3-1333. It might fix problems for memory modules that operate at a higher frequency and memory modules with low CL values should work even better. Tested on Lenovo T420 with DDR3-1333 CL9 and DDR3-1600 CL11. No regressions found. BUG=None BRANCH=None TEST=None Signed-off-by: Patrick Rudolph <siro@das-labor.org> Reviewed-on: https://review.coreboot.org/17389 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Martin Roth <martinroth@google.com> Reviewed-by: Kysti Mlkki <kyosti.malkki@gmail.com> Change-Id: Ib90b5de872a219cf80b4976b6dfae6bc02e298f4 Reviewed-on: https://chromium-review.googlesource.com/413247 Commit-Ready: Furquan Shaikh <furquan@chromium.org> Tested-by: Furquan Shaikh <furquan@chromium.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org> " fail_count="0" gerrit_number="413247" owner_email="furquan@chromium.org" pass_count="0" patch_number="1" project="chromiumos/third_party/coreboot" project_url="https://chromium-review.googlesource.com/chromiumos/third_party/coreboot" ref="refs/changes/47/413247/1" remote="cros" total_fail_count="0"/><pending_commit branch="chromeos-2016.05" change_id="Iccb54fa7d7357a22182dd26bd5b49c4073c04dc9" commit="23f5afc944be05c60231bf6cd4d1d6ae62be430e" commit_message="UPSTREAM: nb/intel/sandybridge/raminit: Get rid of fallback attempts Locking the PLL again once it's locked doesn't work. The MRC doesn't do this, for some reason. Remove fallback attempts of lowering DDR frequency. BUG=None BRANCH=None TEST=None Signed-off-by: Patrick Rudolph <siro@das-labor.org> Reviewed-on: https://review.coreboot.org/17399 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com> Change-Id: Iccb54fa7d7357a22182dd26bd5b49c4073c04dc9 Reviewed-on: https://chromium-review.googlesource.com/413248 Commit-Ready: Furquan Shaikh <furquan@chromium.org> Tested-by: Furquan Shaikh <furquan@chromium.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org> " fail_count="0" gerrit_number="413248" owner_email="furquan@chromium.org" pass_count="0" patch_number="1" project="chromiumos/third_party/coreboot" project_url="https://chromium-review.googlesource.com/chromiumos/third_party/coreboot" ref="refs/changes/48/413248/1" remote="cros" total_fail_count="0"/><pending_commit branch="chromeos-2016.05" change_id="Ibaede39a24e8df1c4d42cb27986ab66174b7d45b" commit="1281f835dde0f318b3ea6cbdfc4650fb50919ee2" commit_message="UPSTREAM: nb/intel/sandybridge/raminit: Define registers Use register names found on forums.corsair.com. No functionality changed. BUG=None BRANCH=None TEST=None Signed-off-by: Patrick Rudolph <siro@das-labor.org> Reviewed-on: https://review.coreboot.org/17400 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Martin Roth <martinroth@google.com> Reviewed-by: Kysti Mlkki <kyosti.malkki@gmail.com> Change-Id: Ibaede39a24e8df1c4d42cb27986ab66174b7d45b Reviewed-on: https://chromium-review.googlesource.com/413249 Commit-Ready: Furquan Shaikh <furquan@chromium.org> Tested-by: Furquan Shaikh <furquan@chromium.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org> " fail_count="0" gerrit_number="413249" owner_email="furquan@chromium.org" pass_count="0" patch_number="1" project="chromiumos/third_party/coreboot" project_url="https://chromium-review.googlesource.com/chromiumos/third_party/coreboot" ref="refs/changes/49/413249/1" remote="cros" total_fail_count="0"/><pending_commit branch="chromeos-2016.05" change_id="I7036275ae89335dd3549ec392fa64824355b3cbf" commit="65afc32fded76697554f108ed318f6637b435b2d" commit_message="UPSTREAM: nb/intel/sandybridge/raminit: Find CMD rate per channel No need to find the same CMD rate for all channels. Allow different CMD rates for every channel. Tested on Lenovo T420 with different modules on each channel. No regressions found. BUG=None BRANCH=None TEST=None Signed-off-by: Patrick Rudolph <siro@das-labor.org> Reviewed-on: https://review.coreboot.org/17472 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Change-Id: I7036275ae89335dd3549ec392fa64824355b3cbf Reviewed-on: https://chromium-review.googlesource.com/413250 Commit-Ready: Furquan Shaikh <furquan@chromium.org> Tested-by: Furquan Shaikh <furquan@chromium.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org> " fail_count="0" gerrit_number="413250" owner_email="furquan@chromium.org" pass_count="0" patch_number="1" project="chromiumos/third_party/coreboot" project_url="https://chromium-review.googlesource.com/chromiumos/third_party/coreboot" ref="refs/changes/50/413250/1" remote="cros" total_fail_count="0"/><pending_commit branch="chromeos-2016.05" change_id="I659e5bc2a6cbadd9539931ee00ddea0a5253295f" commit="1766b92575766271e9a2bc5c1445083223fb1b44" commit_message="UPSTREAM: nb/intel/sandybridge/raminit: Fix disable_channel Also memset info.dimm as it contains decoded SPD timings used to calculate common timings. Tested manually on Lenovo T420. BUG=None BRANCH=None TEST=None Signed-off-by: Patrick Rudolph <siro@das-labor.org> Reviewed-on: https://review.coreboot.org/17473 Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com> Change-Id: I659e5bc2a6cbadd9539931ee00ddea0a5253295f Reviewed-on: https://chromium-review.googlesource.com/413251 Commit-Ready: Furquan Shaikh <furquan@chromium.org> Tested-by: Furquan Shaikh <furquan@chromium.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org> " fail_count="0" gerrit_number="413251" owner_email="furquan@chromium.org" pass_count="0" patch_number="1" project="chromiumos/third_party/coreboot" project_url="https://chromium-review.googlesource.com/chromiumos/third_party/coreboot" ref="refs/changes/51/413251/1" remote="cros" total_fail_count="0"/><pending_commit branch="chromeos-2016.05" change_id="I7a701812cb45f51828a3cbb3343e03817645110e" commit="efb7a12429c3c80ee3797c3574de052f79005b76" commit_message="UPSTREAM: mainboard/google/reef: Update DPTF parameters provided from thermal team Update the DPTF parameters based on thermal test result. 1. Update DPTF CPU/TSR0/TSR1/TSR2 passive/critial trigger points. CPU passive point:61 TSR0 passive point:120, critial point:125 TSR1 passive point:46, critial point:75 TSR2 passive point:100, critial point:125 2. Update PL1/PL2 Min Power Limit/Max Power Limit Set PL1 min to 3W, and max to 6W Set PL2 min to 8W 3. Change thermal relationship table (TRT) setting. Change CPU Throttle Effect on CPU sample rate to 80secs Change CPU Effect on Temp Sensor 0 sample rate to 120secs The TRT of TCHG is TSR1, but real sensor is TSR2. Change Charger Effect on Temp Sensor 2 sample rate to 120secs Change CPU Effect on Temp Sensor 2 sample rate to 120secs BUG=chrome-os-partner:60038 BRANCH=master TEST=build and boot on electro dut Signed-off-by: Tim Chen <Tim-Chen@quantatw.com> Reviewed-on: https://review.coreboot.org/17466 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org> Change-Id: I7a701812cb45f51828a3cbb3343e03817645110e Reviewed-on: https://chromium-review.googlesource.com/413252 Commit-Ready: Furquan Shaikh <furquan@chromium.org> Tested-by: Furquan Shaikh <furquan@chromium.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org> " fail_count="0" gerrit_number="413252" owner_email="furquan@chromium.org" pass_count="0" patch_number="1" project="chromiumos/third_party/coreboot" project_url="https://chromium-review.googlesource.com/chromiumos/third_party/coreboot" ref="refs/changes/52/413252/1" remote="cros" total_fail_count="0"/><pending_commit branch="chromeos-2016.05" change_id="I5c4cbf581fc845150f207087c1527338ca364f60" commit="924203aa97fc3cd715bdbffa063c039912079884" commit_message="UPSTREAM: intel sandy/ivy: Increase XIP cache with USE_NATIVE_RAMINIT Compiled romstage is over 64kiB and exceeded XIP_ROM_SIZE, so it was not entirely set WRPROT cacheable. Reduces first boot raminit (including training) time by 400ms. BUG=None BRANCH=None TEST=None Signed-off-by: Kysti Mlkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/17488 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Patrick Rudolph <siro@das-labor.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Change-Id: I5c4cbf581fc845150f207087c1527338ca364f60 Reviewed-on: https://chromium-review.googlesource.com/413253 Commit-Ready: Furquan Shaikh <furquan@chromium.org> Tested-by: Furquan Shaikh <furquan@chromium.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org> " fail_count="0" gerrit_number="413253" owner_email="furquan@chromium.org" pass_count="0" patch_number="1" project="chromiumos/third_party/coreboot" project_url="https://chromium-review.googlesource.com/chromiumos/third_party/coreboot" ref="refs/changes/53/413253/1" remote="cros" total_fail_count="0"/><pending_commit branch="chromeos-2016.05" change_id="I8e830018b15c344d9f72f921ab84893f633f7654" commit="587aaf451af00a68575a0d4c1b5b6191ccca54c5" commit_message="UPSTREAM: device/dram/ddr3: Calculate CRC16 of SPD unique identifier Specification allows for the unique identifier bytes 117..125 to be excluded of CRC calculation. For such SPD, the CRC would not identify replacement between two identical DIMM parts, while memory training needs to be redone. BUG=None BRANCH=None TEST=None Signed-off-by: Kysti Mlkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/17486 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Rudolph <siro@das-labor.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Change-Id: I8e830018b15c344d9f72f921ab84893f633f7654 Reviewed-on: https://chromium-review.googlesource.com/413254 Commit-Ready: Furquan Shaikh <furquan@chromium.org> Tested-by: Furquan Shaikh <furquan@chromium.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org> " fail_count="0" gerrit_number="413254" owner_email="furquan@chromium.org" pass_count="0" patch_number="1" project="chromiumos/third_party/coreboot" project_url="https://chromium-review.googlesource.com/chromiumos/third_party/coreboot" ref="refs/changes/54/413254/1" remote="cros" total_fail_count="0"/><pending_commit branch="chromeos-2016.05" change_id="If4b43183f99f5f911ae6c311b43c29a72b9922e2" commit="efcfd4c31f9e4e0beeaaad9919c400191575407c" commit_message="UPSTREAM: intel sandy/ivy: Change CRC used to detect DIMM replacement Switch to use CRC of unique identifier section SPD[117..127], remaining area of SPD data is ignored. BUG=None BRANCH=None TEST=None Signed-off-by: Kysti Mlkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/17487 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Patrick Rudolph <siro@das-labor.org> Change-Id: If4b43183f99f5f911ae6c311b43c29a72b9922e2 Reviewed-on: https://chromium-review.googlesource.com/413255 Commit-Ready: Furquan Shaikh <furquan@chromium.org> Tested-by: Furquan Shaikh <furquan@chromium.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org> " fail_count="0" gerrit_number="413255" owner_email="furquan@chromium.org" pass_count="0" patch_number="1" project="chromiumos/third_party/coreboot" project_url="https://chromium-review.googlesource.com/chromiumos/third_party/coreboot" ref="refs/changes/55/413255/1" remote="cros" total_fail_count="0"/><pending_commit branch="chromeos-2016.05" change_id="I50b5a9d02d2caf4c63e1a4025544131a085b8fb6" commit="5553a52adf264559f82aae73dd7d163ca3e2ecd3" commit_message="UPSTREAM: intel sandy/ivy: Move SPD loading after TS_BEFORE_INITRAM Take the timestamp before SPD loading takes place, for easier comparison against MRC blob performance and followup changes will optimize some of the slow SPD/SMBus operations. BUG=None BRANCH=None TEST=None Signed-off-by: Kysti Mlkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/17489 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Patrick Rudolph <siro@das-labor.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Change-Id: I50b5a9d02d2caf4c63e1a4025544131a085b8fb6 Reviewed-on: https://chromium-review.googlesource.com/413256 Commit-Ready: Furquan Shaikh <furquan@chromium.org> Tested-by: Furquan Shaikh <furquan@chromium.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org> " fail_count="0" gerrit_number="413256" owner_email="furquan@chromium.org" pass_count="0" patch_number="1" project="chromiumos/third_party/coreboot" project_url="https://chromium-review.googlesource.com/chromiumos/third_party/coreboot" ref="refs/changes/56/413256/1" remote="cros" total_fail_count="0"/><pending_commit branch="chromeos-2016.05" change_id="I4f2838c05f172d3cb351b027c9b8dd6543ab5944" commit="957880611df8a4a7328e1854b82650da9435d26c" commit_message="UPSTREAM: intel sandy/ivy: Skip SPD loading on S3 resume path For S3 resume path SPD is only used for DIMM replacement detection. As this detection already fails in the case of removal/insertion of same DIMM, we can rely on cbmem_recovery() failure alone to force system reset in case someone accidentally does DIMM replacements while system is suspend-to-ram stage. Skipping DIMM replacement detection allows skipping slow SPD loading, thus reducing S3 resume path time by 80ms for every installed DIMM. BUG=None BRANCH=None TEST=None Signed-off-by: Kysti Mlkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/17490 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Patrick Rudolph <siro@das-labor.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Change-Id: I4f2838c05f172d3cb351b027c9b8dd6543ab5944 Reviewed-on: https://chromium-review.googlesource.com/413257 Commit-Ready: Furquan Shaikh <furquan@chromium.org> Tested-by: Furquan Shaikh <furquan@chromium.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org> " fail_count="0" gerrit_number="413257" owner_email="furquan@chromium.org" pass_count="0" patch_number="1" project="chromiumos/third_party/coreboot" project_url="https://chromium-review.googlesource.com/chromiumos/third_party/coreboot" ref="refs/changes/57/413257/1" remote="cros" total_fail_count="0"/><pending_commit branch="chromeos-2016.05" change_id="I294a56e7b7562c3dea322c644b21a15abb033870" commit="89c03898f32f775c11aaca3aa05f2169521b16d3" commit_message="UPSTREAM: intel sandy/ivy: Improve DIMM replacement detection When MRC cache is available, first read only the SPD unique identifier bytes required to detect possible DIMM replacement. As this is 11 vs 256 bytes with slow SMBus operations, we save about 70ms for every installed DIMM on normal boot path. In the DIMM replacement case this adds some 10ms per installed DIMM as some SPD gets read twice, but we are on slow RAM training boot path anyways. BUG=None BRANCH=None TEST=None Signed-off-by: Kysti Mlkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/17491 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Patrick Rudolph <siro@das-labor.org> Change-Id: I294a56e7b7562c3dea322c644b21a15abb033870 Reviewed-on: https://chromium-review.googlesource.com/413258 Commit-Ready: Furquan Shaikh <furquan@chromium.org> Tested-by: Furquan Shaikh <furquan@chromium.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org> " fail_count="0" gerrit_number="413258" owner_email="furquan@chromium.org" pass_count="0" patch_number="1" project="chromiumos/third_party/coreboot" project_url="https://chromium-review.googlesource.com/chromiumos/third_party/coreboot" ref="refs/changes/58/413258/1" remote="cros" total_fail_count="0"/><pending_commit branch="chromeos-2016.05" change_id="I77b151720001bddad5563b0f8e1279abcea056fa" commit="904d1c6bc19b02201ee9cf29803ebb0044c912cc" commit_message="UPSTREAM: riscv: map first 4GiB of physical address space o The first 4G of physical address space is now mapped at 0. o The first 4G of physical address space is now mapped at 1 << 38. o The first 2G of DRAM (2 - 4 GiB of physical address space) is now mapped at the top of memory save for the last 4K i.e. at 0xffffffff80000000, with SBI page at the very top. Of these, we hope to remove the *most* of the last one once the gcc toolchain can handle linking programs that can run at "top 33 bits of address not all ones (but bit 63 set)". The 4K mapping of the top of the 64 bit address space will always remain, however, for SBI calls. BUG=None BRANCH=None TEST=None Reviewed-on: https://review.coreboot.org/17403 Tested-by: build bot (Jenkins) Reviewed-by: Jonathan Neuschfer <j.neuschaefer@gmx.net> Change-Id: I77b151720001bddad5563b0f8e1279abcea056fa Reviewed-on: https://chromium-review.googlesource.com/413259 Commit-Ready: Furquan Shaikh <furquan@chromium.org> Tested-by: Furquan Shaikh <furquan@chromium.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org> " fail_count="0" gerrit_number="413259" owner_email="furquan@chromium.org" pass_count="0" patch_number="1" project="chromiumos/third_party/coreboot" project_url="https://chromium-review.googlesource.com/chromiumos/third_party/coreboot" ref="refs/changes/59/413259/1" remote="cros" total_fail_count="0"/><pending_commit branch="chromeos-2016.05" change_id="I9699ee2ead5b99c7f46f6f4682235aae3125cca6" commit="eb3efbe73b574df28c02c598156442d7eb0d8310" commit_message="UPSTREAM: device/dram/ddr3: Fix calculation CRC16 of SPD Fix regression with commit: 7dc4b84 device/dram/ddr3: Calculate CRC16 of SPD unique identifier Misplaced parenthesis causes CRC check failure, potentially rendering some platform unbootable. BUG=None BRANCH=None TEST=None Signed-off-by: Kysti Mlkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/17550 Tested-by: build bot (Jenkins) Reviewed-by: David Hendricks <dhendrix@chromium.org> Change-Id: I9699ee2ead5b99c7f46f6f4682235aae3125cca6 Reviewed-on: https://chromium-review.googlesource.com/413260 Commit-Ready: Furquan Shaikh <furquan@chromium.org> Tested-by: Furquan Shaikh <furquan@chromium.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org> " fail_count="0" gerrit_number="413260" owner_email="furquan@chromium.org" pass_count="0" patch_number="1" project="chromiumos/third_party/coreboot" project_url="https://chromium-review.googlesource.com/chromiumos/third_party/coreboot" ref="refs/changes/60/413260/1" remote="cros" total_fail_count="0"/><pending_commit branch="chromeos-2016.05" change_id="Ie39aa0170882ff5b4512f0349f6f86d3f0b86421" commit="91d7049acf104023a9ebac954a166fa94cba593d" commit_message="UPSTREAM: drivers/usb: Add option for baudrate of FT232H UART The maximum supported rate is 12MHz. Only tested with 4MHz though, since I couldn't set anything higher on my Linux receiver. But that works fine with another FT*232H as receiver, whoosh. BUG=None BRANCH=None TEST=None Signed-off-by: Nico Huber <nico.h@gmx.de> Reviewed-on: https://review.coreboot.org/17477 Tested-by: build bot (Jenkins) Reviewed-by: Kysti Mlkki <kyosti.malkki@gmail.com> Change-Id: Ie39aa0170882ff5b4512f0349f6f86d3f0b86421 Reviewed-on: https://chromium-review.googlesource.com/413261 Commit-Ready: Furquan Shaikh <furquan@chromium.org> Tested-by: Furquan Shaikh <furquan@chromium.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org> " fail_count="0" gerrit_number="413261" owner_email="furquan@chromium.org" pass_count="0" patch_number="1" project="chromiumos/third_party/coreboot" project_url="https://chromium-review.googlesource.com/chromiumos/third_party/coreboot" ref="refs/changes/61/413261/1" remote="cros" total_fail_count="0"/><pending_commit branch="chromeos-2016.05" change_id="I153d831fcea8a3132c7bd1927ff3b445d9a8e92c" commit="37a2c3062ae220f0da7863a13b471acaedc7083f" commit_message="UPSTREAM: ec/roda/it8518: Add another embedded controller The embedded-controller interface of Roda's Ivy Bridge notebooks is supposedly programmed by AMI. BUG=None BRANCH=None TEST=None Signed-off-by: Dennis Wassenberg <dennis.wassenberg@secunet.com> Signed-off-by: Nico Huber <nico.huber@secunet.com> Reviewed-on: https://review.coreboot.org/17288 Tested-by: build bot (Jenkins) Reviewed-by: Edward O'Callaghan <edward.ocallaghan@koparo.com> Change-Id: I153d831fcea8a3132c7bd1927ff3b445d9a8e92c Reviewed-on: https://chromium-review.googlesource.com/413262 Commit-Ready: Furquan Shaikh <furquan@chromium.org> Tested-by: Furquan Shaikh <furquan@chromium.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org> " fail_count="0" gerrit_number="413262" owner_email="furquan@chromium.org" pass_count="0" patch_number="1" project="chromiumos/third_party/coreboot" project_url="https://chromium-review.googlesource.com/chromiumos/third_party/coreboot" ref="refs/changes/62/413262/1" remote="cros" total_fail_count="0"/><pending_commit branch="chromeos-2016.05" change_id="I1aa6d75bd5aa153c7b11a6b74564272eaa7cc523" commit="5f114277ec808a8ddc07d77f68077c26edf89f56" commit_message="UPSTREAM: mb/siemens/sitemp_g1p1/cmos.layout: Re-add cmos_defaults_loaded I guess it was dropped because its concept was misunderstood. The idea is to always have it set to `Yes` in the cmos.default. Users can then ack the loading of the defaults by setting it to `No`. If the defaults ever get loaded again, they'll be notified by the default `Yes`. BUG=None BRANCH=None TEST=None Signed-off-by: Nico Huber <nico.huber@secunet.com> Reviewed-on: https://review.coreboot.org/17355 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Martin Roth <martinroth@google.com> Change-Id: I1aa6d75bd5aa153c7b11a6b74564272eaa7cc523 Reviewed-on: https://chromium-review.googlesource.com/413263 Commit-Ready: Furquan Shaikh <furquan@chromium.org> Tested-by: Furquan Shaikh <furquan@chromium.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org> " fail_count="0" gerrit_number="413263" owner_email="furquan@chromium.org" pass_count="0" patch_number="1" project="chromiumos/third_party/coreboot" project_url="https://chromium-review.googlesource.com/chromiumos/third_party/coreboot" ref="refs/changes/63/413263/1" remote="cros" total_fail_count="0"/><pending_commit branch="master" change_id="Idda631017d979de7f6a6e8bf52664db3b95efdf5" commit="d4ab7a8e147ea9f90e8a3ca4e45437f57f16cbf8" commit_message="gcc: add a USE flag "gcc_repo" to specify branch. Some times we need to get gcc from a different repository other than AOSP. This CL adds a USE flag to enable us to do it. BUG=none TEST=The use flag is added. Change-Id: Idda631017d979de7f6a6e8bf52664db3b95efdf5 Reviewed-on: https://chromium-review.googlesource.com/411949 Commit-Ready: Yunlian Jiang <yunlian@chromium.org> Tested-by: Yunlian Jiang <yunlian@chromium.org> Reviewed-by: Caroline Tice <cmtice@chromium.org> " fail_count="0" gerrit_number="411949" owner_email="yunlian@chromium.org" pass_count="0" patch_number="4" project="chromiumos/overlays/chromiumos-overlay" project_url="https://chromium-review.googlesource.com/chromiumos/overlays/chromiumos-overlay" ref="refs/changes/49/411949/4" remote="cros" total_fail_count="0"/><pending_commit branch="master" change_id="I21fd35d1c53014c8e4521e5d296b845d961ac2c4" commit="af1b0a1b4eaca3d31ece348d6ab8bd10c5617e48" commit_message="[cbuildbot] Add 'next_gcc' use flag to toolchain gcc builders. BUG=chromium:666938 TEST=./run_tests CQ-DEPEND=CL:411949 Change-Id: I21fd35d1c53014c8e4521e5d296b845d961ac2c4 Reviewed-on: https://chromium-review.googlesource.com/413004 Commit-Ready: Caroline Tice <cmtice@chromium.org> Tested-by: Caroline Tice <cmtice@chromium.org> Reviewed-by: Yunlian Jiang <yunlian@chromium.org> " fail_count="2" gerrit_number="413004" owner_email="cmtice@chromium.org" pass_count="0" patch_number="1" project="chromiumos/chromite" project_url="https://chromium-review.googlesource.com/chromiumos/chromite" ref="refs/changes/04/413004/1" remote="cros" total_fail_count="2"/><pending_commit branch="master" change_id="I2a4ee4e47cc5cf735f98b770a319ab04cab5f580" commit="8e81a3b6a23e2d6bfb3c29cc1de7ce8b17eb82ee" commit_message="pty_driver: Freeze terminals when using regexp. The pty driver has the ability to have regular expressions to check the output after running some command. However, if a user has a serial terminal open, the command will fail because the serial console output will go to the user's terminal instead of being caught by the pty_driver functions. This commit attempts to freeze any terminals that are in use when a regexp is set. The TerminalFreezer class has been moved here from it's former home in chromite. BUG=chromium:647109 BRANCH=None TEST=Open minicom for the EC console on kevin and cyan. Verify that `dut-control power_state:rec` succeeds without having to close minicom. TEST=Verify servod starts successfully on a servo v3. Change-Id: I2a4ee4e47cc5cf735f98b770a319ab04cab5f580 Signed-off-by: Aseda Aboagye <aaboagye@google.com> Reviewed-on: https://chromium-review.googlesource.com/401529 Commit-Ready: Aseda Aboagye <aaboagye@chromium.org> Tested-by: Aseda Aboagye <aaboagye@chromium.org> Reviewed-by: Julius Werner <jwerner@chromium.org> Reviewed-by: Mike Frysinger <vapier@chromium.org> " fail_count="1" gerrit_number="401529" owner_email="aaboagye@chromium.org" pass_count="0" patch_number="8" project="chromiumos/third_party/hdctools" project_url="https://chromium-review.googlesource.com/chromiumos/third_party/hdctools" ref="refs/changes/29/401529/8" remote="cros" total_fail_count="2"/><pending_commit branch="master" change_id="I904b6e6c24acbcec263fdf211e9ed2be24dd40f3" commit="47814b0b726f4f49abfcd751c466c994e558da12" commit_message="servo: Use new connections for each servod RPC. It seems that httplib is not threadsafe. For certain FAFT tests such as firmware_ECWakeSource, certain test cases would fail fairly reliably. It turns out that there was some contention of the HTTPConnection to servod between some of the wake methods and the mode_aware_reboot() common method. The wake methods have a "delay" decorator that delays for a certain time period and spawns a new thread to issue RPCs to servod. This would cause "CannotSendRequest" exceptions thrown by the httplib because a request was already in place. This commit changes the behaviour to have each RPC to servod acquire a new ServerProxy connection. This way, the threads can't fight for the same HTTPConnection. BUG=chrome-os-partner:59753 BRANCH=None TEST=run firmware_ECWakeSource against cave 4 times, and verify it passes each time. Change-Id: I904b6e6c24acbcec263fdf211e9ed2be24dd40f3 Signed-off-by: Aseda Aboagye <aaboagye@google.com> Reviewed-on: https://chromium-review.googlesource.com/411992 Commit-Ready: Aseda Aboagye <aaboagye@chromium.org> Tested-by: Aseda Aboagye <aaboagye@chromium.org> Reviewed-by: Wai-Hong Tam <waihong@google.com> " fail_count="1" gerrit_number="411992" owner_email="aaboagye@chromium.org" pass_count="0" patch_number="1" project="chromiumos/third_party/autotest" project_url="https://chromium-review.googlesource.com/chromiumos/third_party/autotest" ref="refs/changes/92/411992/1" remote="cros" total_fail_count="1"/><pending_commit branch="master" change_id="I322ed7a0cf09ace8bffaaf67250d13a39bc21f22" commit="e1727e4a68f664e46b28ec90fe3f792ecd43caf4" commit_message="HACK: power_LoadTest: disable google play audio. Since the play.google.com audio does not auto-play content and the javascript and associated python code to press 'play' is fragile lets disable the player for now and revisit moving back once we've either a) found equivalent auto-play mechanism b) made identifying page load success and button press less fragil c) added a mechanism to confirm audio is streaming successfully after the load. BUG=none TEST=power_LoadTest.1hour see & hear the BBC page. Change-Id: I322ed7a0cf09ace8bffaaf67250d13a39bc21f22 Reviewed-on: https://chromium-review.googlesource.com/412321 Commit-Ready: Todd Broch <tbroch@chromium.org> Tested-by: Todd Broch <tbroch@chromium.org> Reviewed-by: Ravi Chandra Sadineni <ravisadineni@chromium.org> " fail_count="1" gerrit_number="412321" owner_email="tbroch@chromium.org" pass_count="0" patch_number="1" project="chromiumos/third_party/autotest" project_url="https://chromium-review.googlesource.com/chromiumos/third_party/autotest" ref="refs/changes/21/412321/1" remote="cros" total_fail_count="1"/><pending_commit branch="master" change_id="I0a91e338a211ff76e23f9e2080ab9c62deeb3225" commit="88e127c1d81654d2c3d79372106b453d4b6b4c65" commit_message="login: Request for state keys done only after the time sync completed. This prevents the state keys to be generated using a wrong timestamp. Because we can't get a notification from tlsdated when the time gets updated (crbug/661205), this implementation is making requests for LastTimeSyncInfo in loops until a response that time sync was done is received. BUG=chromium:649422 TEST=manually tested on a reks device. Change-Id: I0a91e338a211ff76e23f9e2080ab9c62deeb3225 Reviewed-on: https://chromium-review.googlesource.com/406948 Commit-Ready: Igor <igorcov@chromium.org> Tested-by: Igor <igorcov@chromium.org> Reviewed-by: Dan Erat <derat@chromium.org> " fail_count="0" gerrit_number="406948" owner_email="igorcov@chromium.org" pass_count="0" patch_number="16" project="chromiumos/platform2" project_url="https://chromium-review.googlesource.com/chromiumos/platform2" ref="refs/changes/48/406948/16" remote="cros" total_fail_count="0"/><pending_commit branch="master" change_id="I908d409cd1860b523c8eff6aa9bb73ae3a941737" commit="2e3fbe5c239fc9ab02da78546512b5677b581ad4" commit_message="servo_interfaces: cleanup jtag & spi re-purpose to uart. BUG=chrome-os-partner:58999 TEST=sudo emerge hdctools Change-Id: I908d409cd1860b523c8eff6aa9bb73ae3a941737 Reviewed-on: https://chromium-review.googlesource.com/403208 Commit-Ready: Todd Broch <tbroch@chromium.org> Tested-by: Todd Broch <tbroch@chromium.org> Reviewed-by: Wai-Hong Tam <waihong@google.com> " fail_count="1" gerrit_number="403208" owner_email="tbroch@chromium.org" pass_count="0" patch_number="1" project="chromiumos/third_party/hdctools" project_url="https://chromium-review.googlesource.com/chromiumos/third_party/hdctools" ref="refs/changes/08/403208/1" remote="cros" total_fail_count="1"/><pending_commit branch="master" change_id="Ibdbb19597d25e75ab99119fa6b9f81296446d6d7" commit="e607e154c6c9c0cf7a1f059a6cac5776b8e9974a" commit_message="minigbm: rockchip: remove assert.h We don't use it anywhere. BUG=None TEST=None CQ-DEPEND=CL:406485 Change-Id: Ibdbb19597d25e75ab99119fa6b9f81296446d6d7 Reviewed-on: https://chromium-review.googlesource.com/413048 Commit-Ready: Gurchetan Singh <gurchetansingh@chromium.org> Tested-by: Gurchetan Singh <gurchetansingh@chromium.org> Reviewed-by: Stéphane Marchesin <marcheu@chromium.org> " fail_count="1" gerrit_number="413048" owner_email="gurchetansingh@chromium.org" pass_count="0" patch_number="1" project="chromiumos/platform/minigbm" project_url="https://chromium-review.googlesource.com/chromiumos/platform/minigbm" ref="refs/changes/48/413048/1" remote="cros" total_fail_count="1"/><pending_commit branch="master" change_id="I37383518dbbbba88552ceac38ff9ea0e150a1355" commit="43947127e604d6355a294725193aca7f8293c6cd" commit_message="authpolicy: Implement samba interface Last missing link for the authpolicy daemon. Implements a couple of samba calls for AD domain joining, user authentication and user/ device policy fetching. The methods are called by the authpolicy dbus interface. The samba interface assumes that certain samba command line tools are installed and accessible. BUG=chromium:653509 TEST=Emerges. Tested daemon with custom test code, works as intended. Change-Id: I37383518dbbbba88552ceac38ff9ea0e150a1355 Reviewed-on: https://chromium-review.googlesource.com/405427 Commit-Ready: Roman Sorokin <rsorokin@chromium.org> Tested-by: Roman Sorokin <rsorokin@chromium.org> Reviewed-by: Roman Sorokin <rsorokin@chromium.org> " fail_count="0" gerrit_number="405427" owner_email="ljusten@chromium.org" pass_count="0" patch_number="18" project="chromiumos/platform2" project_url="https://chromium-review.googlesource.com/chromiumos/platform2" ref="refs/changes/27/405427/18" remote="cros" total_fail_count="0"/><pending_commit branch="master" change_id="I3222f9513657c73014272402b203a347c73797f4" commit="3f5d6416387a20755be96ff776cedb7afb3cbf88" commit_message="autotest: Make power_AudioDetector not use powerd's logs. Make powerd_AudioDetector use dbus-monitor to check whether the system suspended rather than searching for a hardcoded message in powerd's log file. BUG=chromium:658769 TEST=test passes normally. after hacking it up to not actually play audio, it failed with "System suspended while audio was playing." Change-Id: I3222f9513657c73014272402b203a347c73797f4 Reviewed-on: https://chromium-review.googlesource.com/412929 Commit-Ready: Dan Erat <derat@chromium.org> Tested-by: Dan Erat <derat@chromium.org> Reviewed-by: Cheng-Yi Chiang <cychiang@chromium.org> Reviewed-by: Chinyue Chen <chinyue@chromium.org> " fail_count="0" gerrit_number="412929" owner_email="derat@chromium.org" pass_count="0" patch_number="1" project="chromiumos/third_party/autotest" project_url="https://chromium-review.googlesource.com/chromiumos/third_party/autotest" ref="refs/changes/29/412929/1" remote="cros" total_fail_count="0"/><pending_commit branch="master" change_id="I87b383683984ed091d9e247567747abe4580e881" commit="e3582fc1c275e72f4338036fa883914fb12c92ff" commit_message="Add a static license mapping for mit-krb5. In the process of upreving this library the latest ebuild contains a license string that the license parser cannot parse (infix || operator). BUG=chromium:654842 TEST=license checker does not fail. Change-Id: I87b383683984ed091d9e247567747abe4580e881 Reviewed-on: https://chromium-review.googlesource.com/412268 Commit-Ready: Zentaro Kavanagh <zentaro@google.com> Tested-by: Zentaro Kavanagh <zentaro@google.com> Tested-by: Don Garrett <dgarrett@chromium.org> Reviewed-by: Don Garrett <dgarrett@chromium.org> " fail_count="1" gerrit_number="412268" owner_email="zentaro@google.com" pass_count="0" patch_number="1" project="chromiumos/chromite" project_url="https://chromium-review.googlesource.com/chromiumos/chromite" ref="refs/changes/68/412268/1" remote="cros" total_fail_count="1"/><lkgm version="9010.0.0-rc2"/></manifest> |
