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| <pending_commit branch="chromeos-3.18" change_id="Icf3efd97613eeca3a0268d555a6eabb4e0a4cbd8" commit="952fe5b76848d9811ea45695887bee038030f8ec" commit_message="UPSTREAM: perf: Add cycles to branch_info Intel Skylake supports reporting the time in cycles a branch in the LBR took, to give a rough indication of the basic block performance. Export the cycle information in the branch_info structure. This can be done by just reusing some currently zero padding. This is just the generic header change. The architecture still needs to fill it in. There's no attempt to convert to real time, as we really want cycles here. Signed-off-by: Andi Kleen <ak@linux.intel.com> Signed-off-by: Peter Zijlstra (Intel) <peterz@infradead.org> Cc: Linus Torvalds <torvalds@linux-foundation.org> Cc: Peter Zijlstra <peterz@infradead.org> Cc: Thomas Gleixner <tglx@linutronix.de> Cc: eranian@google.com Link: http://lkml.kernel.org/r/1431285767-27027-5-git-send-email-andi@firstfloor.org Signed-off-by: Ingo Molnar <mingo@kernel.org> (cherry picked from commit 71ef3c6b9d4665ee7afbbe4c208a98917dcfc32f) Signed-off-by: Gabriel Marin <gmx@chromium.org> BUG=b:33115527 TEST=Verified that it compiles Change-Id: Icf3efd97613eeca3a0268d555a6eabb4e0a4cbd8 Reviewed-on: https://chromium-review.googlesource.com/417607 Commit-Ready: Gabriel Marin <gmx@chromium.org> Tested-by: Gabriel Marin <gmx@chromium.org> Reviewed-by: Sonny Rao <sonnyrao@chromium.org> " fail_count="1" gerrit_number="417607" owner_email="gmx@chromium.org" pass_count="0" patch_number="2" project="chromiumos/third_party/kernel" project_url="https://chromium-review.googlesource.com/chromiumos/third_party/kernel" ref="refs/changes/07/417607/2" remote="cros" total_fail_count="1"/><pending_commit branch="chromeos-3.18" change_id="Iacd9cfe62d0ccd1b4a85686b911335fd7437911a" commit="f979866040f95e9c402c6ff94b829cb3a73d922b" commit_message="UPSTREAM: perf/x86/intel/lbr: Add support for LBRv5 Add support for the new LBRv5 format used on Intel Skylake CPUs. The flags for mispredict, abort, in_tx etc. moved to range of separate LBR_INFO_* MSRs. Teach the LBR code to read those. The original LBR registers stay the same, except they have full sign extension now. LBR_INFO also reports a cycle count to the last branch. Report the cycle information using the new "cycles" branch_info output field. In addition we have to context switch and clear the new INFO MSRs to avoid any information leaks. Signed-off-by: Andi Kleen <ak@linux.intel.com> Signed-off-by: Peter Zijlstra (Intel) <peterz@infradead.org> Cc: Linus Torvalds <torvalds@linux-foundation.org> Cc: Peter Zijlstra <peterz@infradead.org> Cc: Thomas Gleixner <tglx@linutronix.de> Cc: eranian@google.com Link: http://lkml.kernel.org/r/1431285767-27027-6-git-send-email-andi@firstfloor.org Signed-off-by: Ingo Molnar <mingo@kernel.org> (cherry picked from commit 50eab8f6ecd77ae4f9742f8e21ea50705ce0f830) Signed-off-by: Gabriel Marin <gmx@chromium.org> BUG=b:33115527 TEST=Verified that it compiles Change-Id: Iacd9cfe62d0ccd1b4a85686b911335fd7437911a Reviewed-on: https://chromium-review.googlesource.com/417608 Commit-Ready: Gabriel Marin <gmx@chromium.org> Tested-by: Gabriel Marin <gmx@chromium.org> Reviewed-by: Sonny Rao <sonnyrao@chromium.org> " fail_count="1" gerrit_number="417608" owner_email="gmx@chromium.org" pass_count="0" patch_number="2" project="chromiumos/third_party/kernel" project_url="https://chromium-review.googlesource.com/chromiumos/third_party/kernel" ref="refs/changes/08/417608/2" remote="cros" total_fail_count="1"/><pending_commit branch="chromeos-3.18" change_id="I76a0f04cb2bcf0699d75618a37d71694d637b90f" commit="cc708b55753572d85ffba78210ca6b194c2f6835" commit_message="UPSTREAM: perf/x86/intel: Handle new arch perfmon v4 status bits ArchPerfmon v4 has some new status bits in GLOBAL_STATUS. These need to be ignored when deciding whether a NMI was an NMI, to avoid eating all NMIs when they stay set, see: b292d7a10487 ("perf/x86/intel: ignore CondChgd bit to avoid false NMI handling") This patch ignores the new ASIF bit, which indicates that SGX interfered with the PMU, and also the new LBR freezing bits, which are set when the LBRs get frozen, plus the existing CondChange (set by JTAG debuggers and some buggy BIOSes) Signed-off-by: Andi Kleen <ak@linux.intel.com> Signed-off-by: Peter Zijlstra (Intel) <peterz@infradead.org> Cc: Linus Torvalds <torvalds@linux-foundation.org> Cc: Peter Zijlstra <peterz@infradead.org> Cc: Thomas Gleixner <tglx@linutronix.de> Cc: eranian@google.com Link: http://lkml.kernel.org/r/1431285767-27027-8-git-send-email-andi@firstfloor.org Signed-off-by: Ingo Molnar <mingo@kernel.org> (cherry picked from commit d8020bee1d0caa90e7b9d6f39ac1fdfaaee7f67f) Signed-off-by: Gabriel Marin <gmx@chromium.org> BUG=b:33115527 TEST=Verified that it compiles Change-Id: I76a0f04cb2bcf0699d75618a37d71694d637b90f Reviewed-on: https://chromium-review.googlesource.com/417609 Commit-Ready: Gabriel Marin <gmx@chromium.org> Tested-by: Gabriel Marin <gmx@chromium.org> Reviewed-by: Sonny Rao <sonnyrao@chromium.org> " fail_count="1" gerrit_number="417609" owner_email="gmx@chromium.org" pass_count="0" patch_number="2" project="chromiumos/third_party/kernel" project_url="https://chromium-review.googlesource.com/chromiumos/third_party/kernel" ref="refs/changes/09/417609/2" remote="cros" total_fail_count="1"/><pending_commit branch="chromeos-3.18" change_id="Iaad2ebe3bde733379a010905db82390d96f4e758" commit="d0750541852c8a71e8360c19f116d1da81ceda32" commit_message="UPSTREAM: perf/x86/intel: Move PMU ACK to after LBR read With Arch Perfmon v4 the PMU ack unfreezes the LBRs. So we need to do the PMU ack after the LBR reading, otherwise the LBRs would be polluted by the PMI handler. This is a minimal change. In principle the ACK could be moved much later. Signed-off-by: Andi Kleen <ak@linux.intel.com> Signed-off-by: Peter Zijlstra (Intel) <peterz@infradead.org> Cc: Linus Torvalds <torvalds@linux-foundation.org> Cc: Peter Zijlstra <peterz@infradead.org> Cc: Thomas Gleixner <tglx@linutronix.de> Cc: eranian@google.com Link: http://lkml.kernel.org/r/1431285767-27027-10-git-send-email-andi@firstfloor.org Signed-off-by: Ingo Molnar <mingo@kernel.org> (cherry picked from commit 0f29e573dd32bb8598e74271454e97c962da5e05) Signed-off-by: Gabriel Marin <gmx@chromium.org> BUG=b:33115527 TEST=Verified that it compiles Change-Id: Iaad2ebe3bde733379a010905db82390d96f4e758 Reviewed-on: https://chromium-review.googlesource.com/417610 Commit-Ready: Gabriel Marin <gmx@chromium.org> Tested-by: Gabriel Marin <gmx@chromium.org> Reviewed-by: Sonny Rao <sonnyrao@chromium.org> " fail_count="1" gerrit_number="417610" owner_email="gmx@chromium.org" pass_count="0" patch_number="2" project="chromiumos/third_party/kernel" project_url="https://chromium-review.googlesource.com/chromiumos/third_party/kernel" ref="refs/changes/10/417610/2" remote="cros" total_fail_count="1"/><pending_commit branch="chromeos-3.18" change_id="Ifa82f028dfe7ed1b240b83135199354207d5dd05" commit="d31a7b2e2ebb718503850eb67a4ff1754eee2f72" commit_message="UPSTREAM: perf/x86/intel: Reset more state in PMU reset The PMU reset code didn't quite keep up with newer PMU features. Improve it a bit to really reset a modern PMU: - Clear all overflow status - Clear LBRs and freezing state - Disable fixed counters too Signed-off-by: Andi Kleen <ak@linux.intel.com> Signed-off-by: Peter Zijlstra (Intel) <peterz@infradead.org> Cc: eranian@google.com Link: http://lkml.kernel.org/r/1425059312-18217-2-git-send-email-andi@firstfloor.org Signed-off-by: Ingo Molnar <mingo@kernel.org> (cherry picked from commit 8882edf735738c949aba4b65d3ec3453066bab12) Signed-off-by: Gabriel Marin <gmx@chromium.org> BUG=b:33115527 TEST=Verified that it compiles Change-Id: Ifa82f028dfe7ed1b240b83135199354207d5dd05 Reviewed-on: https://chromium-review.googlesource.com/417611 Commit-Ready: Gabriel Marin <gmx@chromium.org> Tested-by: Gabriel Marin <gmx@chromium.org> Reviewed-by: Sonny Rao <sonnyrao@chromium.org> " fail_count="1" gerrit_number="417611" owner_email="gmx@chromium.org" pass_count="0" patch_number="2" project="chromiumos/third_party/kernel" project_url="https://chromium-review.googlesource.com/chromiumos/third_party/kernel" ref="refs/changes/11/417611/2" remote="cros" total_fail_count="1"/><pending_commit branch="chromeos-3.18" change_id="I6e4c00c25e526354d8fad79f298829728aef7b40" commit="1c8e0fedc8f761cf8618f49232cf1fb1b90531c1" commit_message="UPSTREAM: perf/x86: Dump DEBUGCTL in PMU dump LBRs and LBR freezing are controlled through the DEBUGCTL MSR. So dump the state of DEBUGCTL too when dumping the PMU state. Signed-off-by: Andi Kleen <ak@linux.intel.com> Signed-off-by: Peter Zijlstra (Intel) <peterz@infradead.org> Cc: eranian@google.com Link: http://lkml.kernel.org/r/1425059312-18217-3-git-send-email-andi@firstfloor.org Signed-off-by: Ingo Molnar <mingo@kernel.org> (cherry picked from commit da3e606d885a17525eb18afd423f5c438860b833) Signed-off-by: Gabriel Marin <gmx@chromium.org> BUG=b:33115527 TEST=Verified that it compiles Change-Id: I6e4c00c25e526354d8fad79f298829728aef7b40 Reviewed-on: https://chromium-review.googlesource.com/417612 Commit-Ready: Gabriel Marin <gmx@chromium.org> Tested-by: Gabriel Marin <gmx@chromium.org> Reviewed-by: Sonny Rao <sonnyrao@chromium.org> " fail_count="1" gerrit_number="417612" owner_email="gmx@chromium.org" pass_count="0" patch_number="2" project="chromiumos/third_party/kernel" project_url="https://chromium-review.googlesource.com/chromiumos/third_party/kernel" ref="refs/changes/12/417612/2" remote="cros" total_fail_count="1"/><pending_commit branch="chromeos-3.18" change_id="I58cf66ca609be11edca84179c24e923115dbf7bb" commit="193ec2644cb64b8ffea3d10d3725b2ab461f5e34" commit_message="UPSTREAM: perf/x86: Only dump PEBS register when PEBS has been detected Technically PEBS_ENABLED is only guaranteed to exist when we detected PEBS. So add a check for this to the PMU dump function. I don't think it can happen on a real CPU, but could in a VM. Signed-off-by: Andi Kleen <ak@linux.intel.com> Signed-off-by: Peter Zijlstra (Intel) <peterz@infradead.org> Cc: eranian@google.com Link: http://lkml.kernel.org/r/1425059312-18217-4-git-send-email-andi@firstfloor.org Signed-off-by: Ingo Molnar <mingo@kernel.org> (cherry picked from commit 15fde1101a1aed11958e0d86bc360f01866a74b1) Signed-off-by: Gabriel Marin <gmx@chromium.org> BUG=b:33115527 TEST=Verified that it compiles Change-Id: I58cf66ca609be11edca84179c24e923115dbf7bb Reviewed-on: https://chromium-review.googlesource.com/417613 Commit-Ready: Gabriel Marin <gmx@chromium.org> Tested-by: Gabriel Marin <gmx@chromium.org> Reviewed-by: Sonny Rao <sonnyrao@chromium.org> " fail_count="1" gerrit_number="417613" owner_email="gmx@chromium.org" pass_count="0" patch_number="2" project="chromiumos/third_party/kernel" project_url="https://chromium-review.googlesource.com/chromiumos/third_party/kernel" ref="refs/changes/13/417613/2" remote="cros" total_fail_count="1"/><pending_commit branch="chromeos-3.18" change_id="I98cceee0690fd28aa37c7444fd4a4cb37fb35c8b" commit="e6880bbfa4439eb7f0843f2fb5276b9278d2e57e" commit_message="UPSTREAM: perf/x86/intel: Streamline LBR MSR handling in PMI The perf PMI currently does unnecessary MSR accesses when LBRs are enabled. We use LBR freezing, or when in callstack mode force the LBRs to only filter on ring 3. So there is no need to disable the LBRs explicitely in the PMI handler. Also we always unnecessarily rewrite LBR_SELECT in the LBR handler, even though it can never change. 5) | /* write_msr: MSR_LBR_SELECT(1c8), value 0 */ 5) | /* read_msr: MSR_IA32_DEBUGCTLMSR(1d9), value 1801 */ 5) | /* write_msr: MSR_IA32_DEBUGCTLMSR(1d9), value 1801 */ 5) | /* write_msr: MSR_CORE_PERF_GLOBAL_CTRL(38f), value 70000000f */ 5) | /* write_msr: MSR_CORE_PERF_GLOBAL_CTRL(38f), value 0 */ 5) | /* write_msr: MSR_LBR_SELECT(1c8), value 0 */ 5) | /* read_msr: MSR_IA32_DEBUGCTLMSR(1d9), value 1801 */ 5) | /* write_msr: MSR_IA32_DEBUGCTLMSR(1d9), value 1801 */ This patch: - Avoids disabling already frozen LBRs unnecessarily in the PMI - Avoids changing LBR_SELECT in the PMI Signed-off-by: Andi Kleen <ak@linux.intel.com> Signed-off-by: Peter Zijlstra (Intel) <peterz@infradead.org> Cc: eranian@google.com Link: http://lkml.kernel.org/r/1426871484-21285-1-git-send-email-andi@firstfloor.org Signed-off-by: Ingo Molnar <mingo@kernel.org> (cherry picked from commit 1a78d93750bb5f61abdc59a91fc3bd06a214542a) Signed-off-by: Gabriel Marin <gmx@chromium.org> BUG=b:33115527 TEST=Verified that it compiles Change-Id: I98cceee0690fd28aa37c7444fd4a4cb37fb35c8b Reviewed-on: https://chromium-review.googlesource.com/417614 Commit-Ready: Gabriel Marin <gmx@chromium.org> Tested-by: Gabriel Marin <gmx@chromium.org> Reviewed-by: Sonny Rao <sonnyrao@chromium.org> " fail_count="1" gerrit_number="417614" owner_email="gmx@chromium.org" pass_count="0" patch_number="2" project="chromiumos/third_party/kernel" project_url="https://chromium-review.googlesource.com/chromiumos/third_party/kernel" ref="refs/changes/14/417614/2" remote="cros" total_fail_count="1"/><pending_commit branch="chromeos-3.18" change_id="I22a13f6510f6b645178135bd2da59fbc3c084929" commit="42a800b713e32feb1891f1517139b288caec2eb5" commit_message="UPSTREAM: perf/x86/intel: Avoid rewriting DEBUGCTL with the same value for LBRs perf with LBRs on has a tendency to rewrite the DEBUGCTL MSR with the same value. Add a little optimization to skip the unnecessary write. Signed-off-by: Andi Kleen <ak@linux.intel.com> Signed-off-by: Peter Zijlstra (Intel) <peterz@infradead.org> Cc: eranian@google.com Link: http://lkml.kernel.org/r/1426871484-21285-2-git-send-email-andi@firstfloor.org Signed-off-by: Ingo Molnar <mingo@kernel.org> (cherry picked from commit cd1f11de69226cc7ce7e7f22bdab9010103ddaa6) Signed-off-by: Gabriel Marin <gmx@chromium.org> BUG=b:33115527 TEST=Verified that it compiles Change-Id: I22a13f6510f6b645178135bd2da59fbc3c084929 Reviewed-on: https://chromium-review.googlesource.com/417615 Commit-Ready: Gabriel Marin <gmx@chromium.org> Tested-by: Gabriel Marin <gmx@chromium.org> Reviewed-by: Sonny Rao <sonnyrao@chromium.org> " fail_count="1" gerrit_number="417615" owner_email="gmx@chromium.org" pass_count="0" patch_number="2" project="chromiumos/third_party/kernel" project_url="https://chromium-review.googlesource.com/chromiumos/third_party/kernel" ref="refs/changes/15/417615/2" remote="cros" total_fail_count="1"/><pending_commit branch="chromeos-3.18" change_id="I07bc40f874f8c5031ee0a6c266db02e6fa7b2182" commit="b9e126c527f707a86f4d1181ed445a612f60e3aa" commit_message="UPSTREAM: perf/x86/intel/lbr: Optimize v4 LBR unfreezing In Arch perfmon v4 the GLOBAL_STATUS reset automatically unfreezes LBRs. So no need to do it manually in the LBR code. Add a check to skip it. v2: Move test up to beginning of function. Signed-off-by: Andi Kleen <ak@linux.intel.com> Signed-off-by: Peter Zijlstra (Intel) <peterz@infradead.org> Cc: Linus Torvalds <torvalds@linux-foundation.org> Cc: Peter Zijlstra <peterz@infradead.org> Cc: Thomas Gleixner <tglx@linutronix.de> Cc: eranian@google.com Link: http://lkml.kernel.org/r/1431285767-27027-9-git-send-email-andi@firstfloor.org Signed-off-by: Ingo Molnar <mingo@kernel.org> (cherry picked from commit 425507fa5f321bb5ce1b5eb57a9586e0cf0b9802) Signed-off-by: Gabriel Marin <gmx@chromium.org> BUG=b:33115527 TEST=Verified that it compiles Change-Id: I07bc40f874f8c5031ee0a6c266db02e6fa7b2182 Reviewed-on: https://chromium-review.googlesource.com/417616 Commit-Ready: Gabriel Marin <gmx@chromium.org> Tested-by: Gabriel Marin <gmx@chromium.org> Reviewed-by: Sonny Rao <sonnyrao@chromium.org> " fail_count="1" gerrit_number="417616" owner_email="gmx@chromium.org" pass_count="0" patch_number="2" project="chromiumos/third_party/kernel" project_url="https://chromium-review.googlesource.com/chromiumos/third_party/kernel" ref="refs/changes/16/417616/2" remote="cros" total_fail_count="1"/><pending_commit branch="chromeos-3.18" change_id="I6e0413d5420b4dcfa726ba6d91c8797bfdac8710" commit="03489177337f32713e26a89ed1619e51bc08a2ce" commit_message="BACKPORT: perf/x86/intel: Add Intel Skylake PMU support Add perf core PMU support for future Intel Skylake CPU cores. The code is based on Haswell/Broadwell. There is a new cache event list, based on the updated Haswell event list. Skylake has removed most counter constraints on basic events, so the basic constraints table now only has a single entry (plus the fixed counters). TSX support and various other setups are all shared with Haswell. Skylake has 32 LBR entries. Add a new LBR init function to set this up. The filters are all the same as Haswell. It also has a new LBR format with a separate LBR_INFO_* MSR, but that has been already added earlier. Signed-off-by: Andi Kleen <ak@linux.intel.com> Signed-off-by: Peter Zijlstra (Intel) <peterz@infradead.org> Cc: Linus Torvalds <torvalds@linux-foundation.org> Cc: Peter Zijlstra <peterz@infradead.org> Cc: Thomas Gleixner <tglx@linutronix.de> Cc: eranian@google.com Link: http://lkml.kernel.org/r/1431285767-27027-7-git-send-email-andi@firstfloor.org Signed-off-by: Ingo Molnar <mingo@kernel.org> (cherry picked from commit 9a92e16fd7b4ccd9aabcbc4d42a3fb5f9a3cf4a1) Signed-off-by: Gabriel Marin <gmx@chromium.org> Fixes: In file perf_event_intel.c - replaced uses of x86_pmu.flags with x86_pmu.er_flags; - replaced uses of PMU_FL_* with ERF_*; BUG=b:33115527 TEST=Verified that the kernel compiles. Tested that perf record / report / top / stat works on a Skylake based chromebook. Verified that perf list shows a set of hardware and hardware cache events. Change-Id: I6e0413d5420b4dcfa726ba6d91c8797bfdac8710 Reviewed-on: https://chromium-review.googlesource.com/414624 Commit-Ready: Gabriel Marin <gmx@chromium.org> Tested-by: Gabriel Marin <gmx@chromium.org> Reviewed-by: Sonny Rao <sonnyrao@chromium.org> " fail_count="1" gerrit_number="414624" owner_email="gmx@chromium.org" pass_count="0" patch_number="3" project="chromiumos/third_party/kernel" project_url="https://chromium-review.googlesource.com/chromiumos/third_party/kernel" ref="refs/changes/24/414624/3" remote="cros" total_fail_count="1"/><pending_commit branch="chromeos-3.18" change_id="Ic74ea2fcd3538f68cdef9e8ceb95170d982e6a59" commit="5bcaf09ab50fed8f90676eef89ea5165bf19b0e4" commit_message="UPSTREAM: perf/x86/intel/lbr: Use correct index to save/restore LBR_INFO with call stack Use the correct index to save/restore the LBR_INFO_x MSR in callstack mode. This is more a cleanup, as even with the wrong index the register was correctly saved/restored, and also LBR callgraph mode in perf tools do not really need anything in LBR_INFO. But still better to use the right index. Signed-off-by: Andi Kleen <ak@linux.intel.com> Signed-off-by: Peter Zijlstra (Intel) <peterz@infradead.org> Cc: Linus Torvalds <torvalds@linux-foundation.org> Cc: Peter Zijlstra <peterz@infradead.org> Cc: Thomas Gleixner <tglx@linutronix.de> Cc: acme@kernel.org Cc: eranian@google.com Cc: jolsa@redhat.com Link: http://lkml.kernel.org/r/1432786398-23861-5-git-send-email-andi@firstfloor.org Signed-off-by: Ingo Molnar <mingo@kernel.org> (cherry picked from commit e0573364b8c5b17401569ef581f1625803210f4d) Signed-off-by: Gabriel Marin <gmx@chromium.org> BUG=b:33115527 TEST=Verified that it compiles Change-Id: Ic74ea2fcd3538f68cdef9e8ceb95170d982e6a59 Reviewed-on: https://chromium-review.googlesource.com/417617 Commit-Ready: Gabriel Marin <gmx@chromium.org> Tested-by: Gabriel Marin <gmx@chromium.org> Reviewed-by: Sonny Rao <sonnyrao@chromium.org> " fail_count="1" gerrit_number="417617" owner_email="gmx@chromium.org" pass_count="0" patch_number="2" project="chromiumos/third_party/kernel" project_url="https://chromium-review.googlesource.com/chromiumos/third_party/kernel" ref="refs/changes/17/417617/2" remote="cros" total_fail_count="1"/><pending_commit branch="chromeos-3.18" change_id="I6bbe449b734b624e78bcd22a6af2eb8b566e7d7e" commit="c58a3285f7b27b22c1e57af6074c3cf3a14ad270" commit_message="UPSTREAM: perf/x86/intel/lbr: Limit LBR accesses to TOS in callstack mode In callstack mode the LBR is not a ring buffer, but a stack that grows up and down. This means in this case we don't need to access all LBRs, only the ones up to TOS. Do this optimization for the normal LBR read, and the context switch save/restore code. For save/restore it can be done unconditionally, as it only runs when call stack mode is active. This recovers some of the cost of going to 32 LBRs on Skylake. Signed-off-by: Andi Kleen <ak@linux.intel.com> Signed-off-by: Peter Zijlstra (Intel) <peterz@infradead.org> Cc: Linus Torvalds <torvalds@linux-foundation.org> Cc: Peter Zijlstra <peterz@infradead.org> Cc: Thomas Gleixner <tglx@linutronix.de> Cc: acme@kernel.org Cc: eranian@google.com Cc: jolsa@redhat.com Link: http://lkml.kernel.org/r/1432786398-23861-6-git-send-email-andi@firstfloor.org Signed-off-by: Ingo Molnar <mingo@kernel.org> (cherry picked from commit 90405aa02247c1a6313c33e2253f9fd2299ae60b) Signed-off-by: Gabriel Marin <gmx@chromium.org> BUG=b:33115527 TEST=Verified that it compiles Change-Id: I6bbe449b734b624e78bcd22a6af2eb8b566e7d7e Reviewed-on: https://chromium-review.googlesource.com/417618 Commit-Ready: Gabriel Marin <gmx@chromium.org> Tested-by: Gabriel Marin <gmx@chromium.org> Reviewed-by: Sonny Rao <sonnyrao@chromium.org> " fail_count="1" gerrit_number="417618" owner_email="gmx@chromium.org" pass_count="0" patch_number="2" project="chromiumos/third_party/kernel" project_url="https://chromium-review.googlesource.com/chromiumos/third_party/kernel" ref="refs/changes/18/417618/2" remote="cros" total_fail_count="1"/><pending_commit branch="chromeos-3.18" change_id="Id187a4f6cd4fd7764cd3c6432a35d09ef1a38bff" commit="38c7e40eed198f638a281b82daaacc561e83ee4a" commit_message="UPSTREAM: perf/x86: Make merge_attr() global to use from perf_event_intel merge_attr() allows to merge two sysfs attribute tables. Export it to be usable by other files too. Next patch is going to use that to extend the sysfs format attributes for a CPU. Signed-off-by: Andi Kleen <ak@linux.intel.com> Signed-off-by: Peter Zijlstra (Intel) <peterz@infradead.org> Cc: Linus Torvalds <torvalds@linux-foundation.org> Cc: Peter Zijlstra <peterz@infradead.org> Cc: Thomas Gleixner <tglx@linutronix.de> Cc: eranian@google.com Link: http://lkml.kernel.org/r/1435612935-24425-1-git-send-email-andi@firstfloor.org Signed-off-by: Ingo Molnar <mingo@kernel.org> (cherry picked from commit 47732d886385af769449022a02c7cf0ce45d8a5c) Signed-off-by: Gabriel Marin <gmx@chromium.org> BUG=b:33115527 TEST=Verified that it compiles Change-Id: Id187a4f6cd4fd7764cd3c6432a35d09ef1a38bff Reviewed-on: https://chromium-review.googlesource.com/414626 Commit-Ready: Gabriel Marin <gmx@chromium.org> Tested-by: Gabriel Marin <gmx@chromium.org> Reviewed-by: Sonny Rao <sonnyrao@chromium.org> " fail_count="1" gerrit_number="414626" owner_email="gmx@chromium.org" pass_count="0" patch_number="3" project="chromiumos/third_party/kernel" project_url="https://chromium-review.googlesource.com/chromiumos/third_party/kernel" ref="refs/changes/26/414626/3" remote="cros" total_fail_count="1"/><pending_commit branch="chromeos-3.18" change_id="I669a2eeabf0ad319af967f8fae5f51cecdb9da04" commit="109ab490ede29938b77fca50cdf25ce6cf1c702b" commit_message="BACKPORT: perf/x86/intel/pebs: Add PEBS frontend profiling for Skylake Skylake has a new FRONTEND_LATENCY PEBS event to accurately profile frontend problems (like ITLB or decoding issues). The new event is configured through a separate MSR, which selects a range of sub events. Define the extra MSR as a extra reg and export support for it through sysfs. To avoid duplicating the existing tables use a new function to add new entries to existing tables. Signed-off-by: Andi Kleen <ak@linux.intel.com> Signed-off-by: Peter Zijlstra (Intel) <peterz@infradead.org> Acked-by: Thomas Gleixner <tglx@linutronix.de> Cc: Linus Torvalds <torvalds@linux-foundation.org> Cc: Peter Zijlstra <peterz@infradead.org> Link: http://lkml.kernel.org/r/1435707205-6676-4-git-send-email-andi@firstfloor.org Signed-off-by: Ingo Molnar <mingo@kernel.org> (cherry picked from commit d0dc8494cd6904f8ad035d9ad97f313948f35d0c) Signed-off-by: Gabriel Marin <gmx@chromium.org> Conflicts: arch/x86/include/asm/msr-index.h Added MSR bits definition to file arch/x86/include/uapi/asm/msr-index.h. File arch/x86/include/asm/msr-index.h doesn't exist in kernel 3.18. BUG=b:33115527 TEST=Verified that it compiles Change-Id: I669a2eeabf0ad319af967f8fae5f51cecdb9da04 Reviewed-on: https://chromium-review.googlesource.com/414627 Commit-Ready: Gabriel Marin <gmx@chromium.org> Tested-by: Gabriel Marin <gmx@chromium.org> Reviewed-by: Sonny Rao <sonnyrao@chromium.org> " fail_count="1" gerrit_number="414627" owner_email="gmx@chromium.org" pass_count="0" patch_number="3" project="chromiumos/third_party/kernel" project_url="https://chromium-review.googlesource.com/chromiumos/third_party/kernel" ref="refs/changes/27/414627/3" remote="cros" total_fail_count="1"/><pending_commit branch="chromeos-3.18" change_id="I56f8ca702f1917378258a34745de56782fab975e" commit="f7de132fd56001f844d9153a7fd6c56d3d3c97de" commit_message="UPSTREAM: perf/x86/intel: Fix Skylake FRONTEND MSR extrareg mask Stephane pointed out that the extrareg mask was one bit too short. The bubble width field was truncated by one bit. Fix that here. Also add some extra comments on the reserved bits inside the event select code. Reported-by: Stephane Eranian <eranian@google.com> Signed-off-by: Andi Kleen <ak@linux.intel.com> Signed-off-by: Peter Zijlstra (Intel) <peterz@infradead.org> Acked-by: Thomas Gleixner <tglx@linutronix.de> Cc: Linus Torvalds <torvalds@linux-foundation.org> Cc: Peter Zijlstra <peterz@infradead.org> Link: http://lkml.kernel.org/r/1441835640-21347-3-git-send-email-andi@firstfloor.org Signed-off-by: Ingo Molnar <mingo@kernel.org> (cherry picked from commit dfe1f3cb312624928052413928d88b0ee3492216) Signed-off-by: Gabriel Marin <gmx@chromium.org> BUG=b:33115527 TEST=Verified that it compiles Change-Id: I56f8ca702f1917378258a34745de56782fab975e Reviewed-on: https://chromium-review.googlesource.com/417619 Commit-Ready: Gabriel Marin <gmx@chromium.org> Tested-by: Gabriel Marin <gmx@chromium.org> Reviewed-by: Sonny Rao <sonnyrao@chromium.org> " fail_count="1" gerrit_number="417619" owner_email="gmx@chromium.org" pass_count="0" patch_number="2" project="chromiumos/third_party/kernel" project_url="https://chromium-review.googlesource.com/chromiumos/third_party/kernel" ref="refs/changes/19/417619/2" remote="cros" total_fail_count="1"/><pending_commit branch="chromeos-2016.05" change_id="I63ef5dde8dddd9afeae91e396c157a1a37d47c80" commit="5d2b2b4600b1e60145ff2b99aaaed8389a758d8c" commit_message="UPSTREAM: tpm2: handle failures more gracefully When trying to bring up a device with a malfunctioning TPM2 chip, the driver currently gets stuck waiting for SPI flow control, causing bricked devices. This patch puts a 100 ms cap on the waiting time - this should be enough even for a longest NVRAM save operation which could be under way on the TPM device. BRANCH=gru BUG=chrome-os-partner:59807 TEST=with a matching change in depthcharge, now a gru with corrupted SPI TPM comes up to the recovery screen (it was not showing signs of life before this change). Change-Id: I63ef5dde8dddd9afeae91e396c157a1a37d47c80 Original-Signed-off-by: Vadim Bendebury <vbendeb@chromium.org> Original-Reviewed-on: https://review.coreboot.org/17898 Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> Original-Tested-by: build bot (Jenkins) Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/421209 Reviewed-by: Vadim Bendebury <vbendeb@chromium.org> " fail_count="0" gerrit_number="421209" owner_email="adurbin@chromium.org" pass_count="0" patch_number="1" project="chromiumos/third_party/coreboot" project_url="https://chromium-review.googlesource.com/chromiumos/third_party/coreboot" ref="refs/changes/09/421209/1" remote="cros" total_fail_count="0"/><pending_commit branch="chromeos-2016.05" change_id="I7fc6f9da83b1abbae6dd069f759b220d59153d1c" commit="e0fa09bd9840f16c563e4d975b3746ee9679bb3d" commit_message="UPSTREAM: google/eve: Enable touch devices Enable the actual touch devices to be probed by the kernel and remove the placeholder devices that I put in before and were used for initial bringup. BUG=chrome-os-partner:58666 TEST=tested on eve Change-Id: I7fc6f9da83b1abbae6dd069f759b220d59153d1c Original-Signed-off-by: Duncan Laurie <dlaurie@chromium.org> Original-Reviewed-on: https://review.coreboot.org/17896 Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> Original-Tested-by: build bot (Jenkins) Original-Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/421210 Reviewed-by: Patrick Georgi <pgeorgi@chromium.org> " fail_count="0" gerrit_number="421210" owner_email="adurbin@chromium.org" pass_count="0" patch_number="1" project="chromiumos/third_party/coreboot" project_url="https://chromium-review.googlesource.com/chromiumos/third_party/coreboot" ref="refs/changes/10/421210/1" remote="cros" total_fail_count="0"/><pending_commit branch="chromeos-2016.05" change_id="I5193c6a9f08398b881c971c7175654ba5775b34a" commit="f718bf2790b2aded8d4226bc2e7e72413194d71b" commit_message="UPSTREAM: util/broadcom: close file on error Change-Id: I5193c6a9f08398b881c971c7175654ba5775b34a Original-Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Found-by: Coverity Scan #1323509 Original-Reviewed-on: https://review.coreboot.org/17876 Original-Tested-by: build bot (Jenkins) Original-Reviewed-by: Martin Roth <martinroth@google.com> Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/421211 Reviewed-by: Patrick Georgi <pgeorgi@chromium.org> " fail_count="0" gerrit_number="421211" owner_email="adurbin@chromium.org" pass_count="0" patch_number="1" project="chromiumos/third_party/coreboot" project_url="https://chromium-review.googlesource.com/chromiumos/third_party/coreboot" ref="refs/changes/11/421211/1" remote="cros" total_fail_count="0"/><pending_commit branch="chromeos-2016.05" change_id="I078aa39906394be64023424731fe0c7ae2019899" commit="788dd1f752dd3af860aa1b71471f80aaacef3ede" commit_message="UPSTREAM: util/broadcom: Terminate string filebuffer is treated like a string, so it should be zero-terminated like a string. Change-Id: I078aa39906394be64023424731fe0c7ae2019899 Original-Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Found-by: Coverity Scan #1323473 Original-Reviewed-on: https://review.coreboot.org/17878 Original-Tested-by: build bot (Jenkins) Original-Reviewed-by: Martin Roth <martinroth@google.com> Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/421212 Reviewed-by: Patrick Georgi <pgeorgi@chromium.org> " fail_count="0" gerrit_number="421212" owner_email="adurbin@chromium.org" pass_count="0" patch_number="1" project="chromiumos/third_party/coreboot" project_url="https://chromium-review.googlesource.com/chromiumos/third_party/coreboot" ref="refs/changes/12/421212/1" remote="cros" total_fail_count="0"/><pending_commit branch="chromeos-2016.05" change_id="Ieea7ac7fbc618cd12f843f1606f9ebab37cae67e" commit="42f9aa476bdf2a4a2e33c9a4b719bec9a63de347" commit_message="UPSTREAM: util/broadcom: Close file after use Change-Id: Ieea7ac7fbc618cd12f843f1606f9ebab37cae67e Original-Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Found-by: Coverity Scan #1323508 Original-Reviewed-on: https://review.coreboot.org/17879 Original-Tested-by: build bot (Jenkins) Original-Reviewed-by: Martin Roth <martinroth@google.com> Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/421213 Reviewed-by: Patrick Georgi <pgeorgi@chromium.org> " fail_count="0" gerrit_number="421213" owner_email="adurbin@chromium.org" pass_count="0" patch_number="1" project="chromiumos/third_party/coreboot" project_url="https://chromium-review.googlesource.com/chromiumos/third_party/coreboot" ref="refs/changes/13/421213/1" remote="cros" total_fail_count="0"/><pending_commit branch="chromeos-2016.05" change_id="Iadee1af224507a6dd39956306f3eafa687895176" commit="85d23ad0d5bd520a5c1c0c692c29d0da94eadb39" commit_message="UPSTREAM: util/broadcom: Initialize variable It's later tested for NULL, but never initialized to make that test work reliably. Change-Id: Iadee1af224507a6dd39956306f3eafa687895176 Original-Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Found-by: Coverity Scan #1323515 Original-Reviewed-on: https://review.coreboot.org/17880 Original-Tested-by: build bot (Jenkins) Original-Reviewed-by: Martin Roth <martinroth@google.com> Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/421214 Reviewed-by: Patrick Georgi <pgeorgi@chromium.org> " fail_count="0" gerrit_number="421214" owner_email="adurbin@chromium.org" pass_count="0" patch_number="1" project="chromiumos/third_party/coreboot" project_url="https://chromium-review.googlesource.com/chromiumos/third_party/coreboot" ref="refs/changes/14/421214/1" remote="cros" total_fail_count="0"/><pending_commit branch="chromeos-2016.05" change_id="Ib53408e8b186c07aa8e42c67131d39c4add05983" commit="09794ce9a54e703399c844c9f0b64bbec609abb0" commit_message="UPSTREAM: util/broadcom: Check return value of stat() Change-Id: Ib53408e8b186c07aa8e42c67131d39c4add05983 Original-Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Found-by: Coverity Scan #1323515 Original-Reviewed-on: https://review.coreboot.org/17881 Original-Tested-by: build bot (Jenkins) Original-Reviewed-by: Martin Roth <martinroth@google.com> Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/421215 Reviewed-by: Patrick Georgi <pgeorgi@chromium.org> " fail_count="0" gerrit_number="421215" owner_email="adurbin@chromium.org" pass_count="0" patch_number="1" project="chromiumos/third_party/coreboot" project_url="https://chromium-review.googlesource.com/chromiumos/third_party/coreboot" ref="refs/changes/15/421215/1" remote="cros" total_fail_count="0"/><pending_commit branch="chromeos-2016.05" change_id="I088730fd87dd39fa2c36a06c5770fad05a5808b0" commit="77e70340a520ccdf3813957629db88dfbfc68700" commit_message="UPSTREAM: util/broadcom: Add two more NULL checks Change-Id: I088730fd87dd39fa2c36a06c5770fad05a5808b0 Original-Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Found-by: Coverity Scan #1323511, #1323512 Original-Reviewed-on: https://review.coreboot.org/17882 Original-Tested-by: build bot (Jenkins) Original-Reviewed-by: Martin Roth <martinroth@google.com> Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/421216 Reviewed-by: Patrick Georgi <pgeorgi@chromium.org> " fail_count="0" gerrit_number="421216" owner_email="adurbin@chromium.org" pass_count="0" patch_number="1" project="chromiumos/third_party/coreboot" project_url="https://chromium-review.googlesource.com/chromiumos/third_party/coreboot" ref="refs/changes/16/421216/1" remote="cros" total_fail_count="0"/><pending_commit branch="chromeos-2016.05" change_id="I0d260254bab714ec939fc199b3a133b0fc05b10d" commit="b1b89f6b5def5b2044b749a320f36f03d6effe47" commit_message="UPSTREAM: util/romcc: Fix resource leak Change-Id: I0d260254bab714ec939fc199b3a133b0fc05b10d Original-Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Found-by: Coverity Scan #1129112 Original-Reviewed-on: https://review.coreboot.org/17883 Original-Tested-by: build bot (Jenkins) Original-Reviewed-by: Martin Roth <martinroth@google.com> Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/421217 Reviewed-by: Patrick Georgi <pgeorgi@chromium.org> " fail_count="0" gerrit_number="421217" owner_email="adurbin@chromium.org" pass_count="0" patch_number="1" project="chromiumos/third_party/coreboot" project_url="https://chromium-review.googlesource.com/chromiumos/third_party/coreboot" ref="refs/changes/17/421217/1" remote="cros" total_fail_count="0"/><pending_commit branch="chromeos-2016.05" change_id="I7f9c38fd6e75b32fe1ed8a60c7054f4dd1fcd5c0" commit="324936d7df46769cb5bdbbab7a6e3071f3d93223" commit_message="UPSTREAM: util/romcc: Move access after NULL-check Change-Id: I7f9c38fd6e75b32fe1ed8a60c7054f4dd1fcd5c0 Original-Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Found-by: Coverity Scan #1129104 Original-Reviewed-on: https://review.coreboot.org/17884 Original-Tested-by: build bot (Jenkins) Original-Reviewed-by: Martin Roth <martinroth@google.com> Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/421218 Reviewed-by: Patrick Georgi <pgeorgi@chromium.org> " fail_count="0" gerrit_number="421218" owner_email="adurbin@chromium.org" pass_count="0" patch_number="1" project="chromiumos/third_party/coreboot" project_url="https://chromium-review.googlesource.com/chromiumos/third_party/coreboot" ref="refs/changes/18/421218/1" remote="cros" total_fail_count="0"/><pending_commit branch="chromeos-2016.05" change_id="I0f78b55b28011cdefc90665bca2a7ea17647e955" commit="03d04a78993d1767a8539c8868fc2740d695e72d" commit_message="UPSTREAM: util/romcc: remove self-assignment Change-Id: I0f78b55b28011cdefc90665bca2a7ea17647e955 Original-Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Found-by: Coverity Scan #1129127 Original-Reviewed-on: https://review.coreboot.org/17885 Original-Tested-by: build bot (Jenkins) Original-Reviewed-by: Martin Roth <martinroth@google.com> Original-Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/421219 Reviewed-by: Patrick Georgi <pgeorgi@chromium.org> " fail_count="0" gerrit_number="421219" owner_email="adurbin@chromium.org" pass_count="0" patch_number="1" project="chromiumos/third_party/coreboot" project_url="https://chromium-review.googlesource.com/chromiumos/third_party/coreboot" ref="refs/changes/19/421219/1" remote="cros" total_fail_count="0"/><pending_commit branch="chromeos-2016.05" change_id="I126fe86422900bbae2c3ca16052be27985cfed53" commit="467777dd58c98d123faaf9e487c7d6a42235f742" commit_message="UPSTREAM: samsung/exynos5420: Fix test for src < 0 It was unsigned, not a good place to be for testing < 0. Change-Id: I126fe86422900bbae2c3ca16052be27985cfed53 Original-Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Found-by: Coverity Scan #1241911 Original-Reviewed-on: https://review.coreboot.org/17888 Original-Reviewed-by: Nico Huber <nico.h@gmx.de> Original-Tested-by: build bot (Jenkins) Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/421220 Reviewed-by: Patrick Georgi <pgeorgi@chromium.org> " fail_count="0" gerrit_number="421220" owner_email="adurbin@chromium.org" pass_count="0" patch_number="1" project="chromiumos/third_party/coreboot" project_url="https://chromium-review.googlesource.com/chromiumos/third_party/coreboot" ref="refs/changes/20/421220/1" remote="cros" total_fail_count="0"/><pending_commit branch="master" change_id="I79691bb57083fd925f9c4be06de706f676a1d043" commit="87c7e4dca654bd99d66c2dac165d735321161247" commit_message="make i2c_handle_sda_irq() static to fix GCC 5.3 warning GCC 5.3 and 6.2 complain about the the i2c_irqs array being defined as static because it's used by a non-static inline function. Since i2c_handle_sda_irq is only used in the i2c.c file, it makes sense to make it static. Additionally, remove the inline keyword for i2c_handle_sda_irq since it's a huge function, if it were used more than once, we wouldn't want it to be inlined. chip/npcx/i2c.c:462:22: error: 'i2c_irqs' is static but used in inline function 'i2c_handle_sda_irq' which is not static [-Werror] task_disable_irq(i2c_irqs[controller]); npcx_evb/RW/ec.RW and npcx_evb_arm/RW/ec.RW.flat each shrank by 20 bytes. npcx_evb/RO/ec.RO and npcx_evb_arm/RO/ec.RO.flat each shrank by 64 bytes BUG=none BRANCH=none TEST=make buildall passes under GCC 4.9.2, 5.3 and 6.2 Change-Id: I79691bb57083fd925f9c4be06de706f676a1d043 Signed-off-by: Martin Roth <martinroth@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/403502 Reviewed-by: Shawn N <shawnn@chromium.org> " fail_count="0" gerrit_number="403502" owner_email="martinroth@chromium.org" pass_count="0" patch_number="4" project="chromiumos/platform/ec" project_url="https://chromium-review.googlesource.com/chromiumos/platform/ec" ref="refs/changes/02/403502/4" remote="cros" total_fail_count="1"/><pending_commit branch="master" change_id="Iaf8641b3d252c494ad13fbeb8ad8ece3cdfe6e76" commit="f97e5dccafc9b7b2d557611b555a34f51153ca68" commit_message="i2cs.c: Initialize variable to fix GCC warnings word_in_value shouldn't be able to be used without being initialized, so just initialize it to make GCC 5.3 happy. It's configured separately in the (last_write_pointer & 3) and (!(last_write_pointer & 3)) paths, so it can't actually slip through uninitialized. There is probably a way to rwrite this that won't confuse GCC as much, but I haven't found it yet. The solutions I did try generally ended up increasing the binary size, so I'm falling back to just initializing the variable. chip/g/i2cs.c: In function '_i2cs_write_complete_int': chip/g/i2cs.c:178:19: error: 'word_in_value' may be used uninitialized in this function [-Werror=maybe-uninitialized] This does not change the size of any ec.*.flat file. BRANCH=none BUG=none TEST=build succeeds under GCC 4.9.2, 5.3 and 6.2 Change-Id: Iaf8641b3d252c494ad13fbeb8ad8ece3cdfe6e76 Signed-off-by: Martin Roth <martinroth@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/403504 Reviewed-by: Shawn N <shawnn@chromium.org> " fail_count="0" gerrit_number="403504" owner_email="martinroth@chromium.org" pass_count="0" patch_number="2" project="chromiumos/platform/ec" project_url="https://chromium-review.googlesource.com/chromiumos/platform/ec" ref="refs/changes/04/403504/2" remote="cros" total_fail_count="0"/><pending_commit branch="master" change_id="I6bbe73b4acf3dcbbaa03d9cbf1dcdfeb883c0a6d" commit="973b9f620b222bb110e983dd63e0e47333099387" commit_message="spi_nor.c: Initialize variables to fix GCC warnings Looking at these warnings, none of these are real issues, so just initialize the variables to make GCC happy. There might be a way to rewrite the functions to make GCC be less confused, but I haven't figured it out yet, and the solutions I tried generally ended up increasing the binary size. The function spi_nor_read_jedec_id() will initialize the variables or return an error, so there isn't a path where they would be used without initialization. common/spi_nor.c: In function 'command_spi_nor_info': common/spi_nor.c:771:3: error: 'mfn_id' may be used uninitialized in this function [-Werror=maybe-uninitialized] common/spi_nor.c:771:3: error: 'mfn_bank' may be used uninitialized in this function [-Werror=maybe-uninitialized] The function spi_nor_device_discover_sfdp_page_size() will either set these variables or return an error, so these should never actually be uninitialized when they get used. common/spi_nor.c: In function 'spi_nor_init': common/spi_nor.c:449:30: error: 'capacity' may be used uninitialized in this function [-Werror=maybe-uninitialized] common/spi_nor.c:450:31: error: 'page_size' may be used uninitialized in this function [-Werror=maybe-uninitialized] This does not change the size of any ec.*.flat file. BRANCH=none BUG=none TEST=build succeeds under GCC 4.9.2, 5.3, and 6.2 Change-Id: I6bbe73b4acf3dcbbaa03d9cbf1dcdfeb883c0a6d Signed-off-by: Martin Roth <martinroth@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/403503 Reviewed-by: Shawn N <shawnn@chromium.org> " fail_count="0" gerrit_number="403503" owner_email="martinroth@chromium.org" pass_count="0" patch_number="2" project="chromiumos/platform/ec" project_url="https://chromium-review.googlesource.com/chromiumos/platform/ec" ref="refs/changes/03/403503/2" remote="cros" total_fail_count="0"/><pending_commit branch="master" change_id="I1e21a13e3d7f9dc296296db6465ec975187a1cc0" commit="caa4673bd908006d47cbed90d00564c30e0cc469" commit_message="cr50: Initialize variable where it's used The previous code split the initialization of digest_len out into a separate area than were it was used. This confused gcc into thinking that the variable might be uninitialized when it was used later. By putting it all in one area, we save a couple of bytes and make things more plain for the compiler. This does not change the size of any ec.*.flat file. BRANCH=none BUG=none TEST=build succeeds under GCC 4.9.2, 5.3 and 6.2 Change-Id: I1e21a13e3d7f9dc296296db6465ec975187a1cc0 Signed-off-by: Martin Roth <martinroth@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/411407 Reviewed-by: Nagendra Modadugu <ngm@google.com> Reviewed-by: Shawn N <shawnn@chromium.org> " fail_count="0" gerrit_number="411407" owner_email="martinroth@chromium.org" pass_count="0" patch_number="1" project="chromiumos/platform/ec" project_url="https://chromium-review.googlesource.com/chromiumos/platform/ec" ref="refs/changes/07/411407/1" remote="cros" total_fail_count="0"/><pending_commit branch="chromeos-3.10" change_id="Id10b3d6ac0767385a2e5534c459f54ba6bf2216c" commit="5efa1bbf9589cae6e252ed8c7815f37ee251ab18" commit_message="Revert "FROMLIST: timers: Fix usleep_range() in the context of wake_up_process()" This reverts commit f5f520d79ec610cc9c7faf8d6aa73cb5ecbac792 as it is broken (does busy-wait in case task is woken up early) and we'll pick up fixed version from upstream. BUG=chromium:658801 TEST=See CL:Ib2eaa31e272c15a9a7a17796a4b22fe954f332bf Change-Id: Id10b3d6ac0767385a2e5534c459f54ba6bf2216c Reviewed-on: https://chromium-review.googlesource.com/418877 Commit-Ready: Dmitry Torokhov <dtor@chromium.org> Tested-by: Dmitry Torokhov <dtor@chromium.org> Reviewed-by: Sonny Rao <sonnyrao@chromium.org> (cherry picked from commit 7c9ac25fa67c209666536392ca873cce4ae658e8) Conflicts: kernel/time/timer.c ... because it is in kernel/timer.c in older kernels. Reviewed-on: https://chromium-review.googlesource.com/419639 Reviewed-by: Douglas Anderson <dianders@chromium.org> " fail_count="3" gerrit_number="419639" owner_email="dtor@chromium.org" pass_count="0" patch_number="1" project="chromiumos/third_party/kernel" project_url="https://chromium-review.googlesource.com/chromiumos/third_party/kernel" ref="refs/changes/39/419639/1" remote="cros" total_fail_count="3"/><pending_commit branch="chromeos-3.10" change_id="I69566b3de45c83fbbe52d2b23f2942cb0231f55d" commit="680360b42f84898d97ad5e0ee7170e7f3ae2166b" commit_message="UPSTREAM: timers: Fix usleep_range() in the context of wake_up_process() Users of usleep_range() expect that it will _never_ return in less time than the minimum passed parameter. However, nothing in the code ensures this, when the sleeping task is woken by wake_up_process() or any other mechanism which can wake a task from uninterruptible state. Neither usleep_range() nor schedule_hrtimeout_range*() have any protection against wakeups. schedule_hrtimeout_range*() is designed this way despite the fact that the API documentation does not mention it. msleep() already has code to handle this case since it will loop as long as there was still time left. usleep_range() has no such loop, add it. Presumably this problem was not detected before because usleep_range() is only used in a few places and the function is mostly used in contexts which are not exposed to wakeups of any form. An effort was made to look for users relying on the old behavior by looking for usleep_range() in the same file as wake_up_process(). No problems were found by this search, though it is conceivable that someone could have put the sleep and wakeup in two different files. An effort was made to ask several upstream maintainers if they were aware of people relying on wake_up_process() to wake up usleep_range(). No maintainers were aware of that but they were aware of many people relying on usleep_range() never returning before the minimum. Reported-by: Tao Huang <huangtao@rock-chips.com> Signed-off-by: Douglas Anderson <dianders@chromium.org> Cc: heiko@sntech.de Cc: broonie@kernel.org Cc: briannorris@chromium.org Cc: Andreas Mohr <andi@lisas.de> Cc: linux-rockchip@lists.infradead.org Cc: tony.xie@rock-chips.com Cc: John Stultz <john.stultz@linaro.org> Cc: djkurtz@chromium.org Cc: linux@roeck-us.net Cc: tskd08@gmail.com Link: http://lkml.kernel.org/r/1477065531-30342-1-git-send-email-dianders@chromium.org Signed-off-by: Thomas Gleixner <tglx@linutronix.de> BUG=chromium:658801 TEST=See CL:Ib2eaa31e272c15a9a7a17796a4b22fe954f332bf (cherry picked from git://git.kernel.org/pub/scm/linux/kernel/git/tip/tip.git commit 6c5e9059692567740a4ee51530dffe51a4b9584d) Signed-off-by: Dmitry Torokhov <dtor@chromium.org> Change-Id: I69566b3de45c83fbbe52d2b23f2942cb0231f55d Reviewed-on: https://chromium-review.googlesource.com/418878 Reviewed-by: Sonny Rao <sonnyrao@chromium.org> (cherry picked from commit 8c5a40400217ed0d1546ccc644d7f78fb6396613) Conflicts: kernel/time/timer.c ... because it is in kernel/timer.c in older kernels. ... also keeping delta as unsigned long. Reviewed-on: https://chromium-review.googlesource.com/419640 Reviewed-by: Douglas Anderson <dianders@chromium.org> " fail_count="2" gerrit_number="419640" owner_email="dtor@chromium.org" pass_count="0" patch_number="2" project="chromiumos/third_party/kernel" project_url="https://chromium-review.googlesource.com/chromiumos/third_party/kernel" ref="refs/changes/40/419640/2" remote="cros" total_fail_count="2"/><pending_commit branch="master" change_id="I234e61f6f8cbbdfdbb427ed6668967fb8bd0346a" commit="07bdce47915d1030784f552df75b6b74a0a9c5a0" commit_message="trunks: set Decrypt attribute for sign keys If a padding-only signing scheme is not supported on TPM, set Decrypt attribute for the generated keys to allow using raw RSA operations for it. A raw RSA is required to support PKCS#11 CKM_RSA_PKCS (and other, like CKM_MD5_RSA_PKCS, not supported directly by TPM) mechanisms for signing. BUG=chrome-os-partner:60880 BUG=chrome-os-partner:60844 TEST=1) On a unowned machine with TPM2: corp enroll, login, install a network certificate (gECC or GMC), then: a) retrieve the public key from the installed certificate LIBCHAPS=`ls /usr/lib**/libchaps.so` CERTID=`pkcs11-tool --module=$LIBCHAPS --slot=1 --type=cert \ -O | grep "ID:" | awk '{print $2}'` pkcs11-tool --module=$LIBCHAPS --slot=1 --id=$CERTID \ --type=cert -r > /tmp/cert openssl x509 -inform der -pubkey -noout -in /tmp/cert > /tmp/pub.key b) sign a sample text using the private key for the certificate and MD5-RSA-PKCS mechanism, not supported by TPM2_Sign command: echo "ABCDEF" > /tmp/1.txt pkcs11-tool --module=$LIBCHAPS --slot=1 --id=$CERTID --sign \ -i /tmp/1.txt -o /tmp/1.sig -m MD5-RSA-PKCS c) verify signature: openssl dgst -md5 -verify /tmp/pub.key -signature /tmp/1.sig /tmp/1.txt Step (b) should succeed and step (c) should return "Verified OK". 2) Unit tests. Change-Id: I234e61f6f8cbbdfdbb427ed6668967fb8bd0346a Reviewed-on: https://chromium-review.googlesource.com/420349 Commit-Ready: Andrey Pronin <apronin@chromium.org> Tested-by: Andrey Pronin <apronin@chromium.org> Reviewed-by: Darren Krahn <dkrahn@chromium.org> " fail_count="0" gerrit_number="420349" owner_email="apronin@chromium.org" pass_count="0" patch_number="4" project="aosp/platform/system/tpm" project_url="https://chromium-review.googlesource.com/aosp/platform/system/tpm" ref="refs/changes/49/420349/4" remote="cros" total_fail_count="0"/><pending_commit branch="master" change_id="I000f6dc5c40a0ffb0ecc45bbd3bac560dbc32dc9" commit="3e528d75dab751984c2dbbc4254ee12a4c4d5f85" commit_message="trunks: allow NULL hashing algorithm for RSASSA TPMs can support padding-only scheme for RSASSA (CL:420486, CL:420811, CL:420854) - it is indicated by passing TPM_ALG_NULL as a hashing algorithm to TPM2_Sign. This patch removes setting the default SHA256 hashing algorithm if NULL hash_alg was passed to TpmUtilityImpl::Sign for RSASSA. BUG=chrome-os-partner:60967 TEST=On a unowned machine with TPM2: corp enroll, login, install a network certificate (gECC or GMC), then: a) retrieve the public key from the installed certificate LIBCHAPS=`ls /usr/lib**/libchaps.so` CERTID=`pkcs11-tool --module=$LIBCHAPS --slot=1 --type=cert \ -O | grep "ID:" | awk '{print $2}'` pkcs11-tool --module=$LIBCHAPS --slot=1 --id=$CERTID \ --type=cert -r > /tmp/cert openssl x509 -inform der -pubkey -noout -in /tmp/cert > /tmp/pub.key b) sign a sample text using the private key for the certificate and MD5-RSA-PKCS mechanism, not supported by TPM2_Sign command: echo "ABCDEF" > /tmp/1.txt pkcs11-tool --module=$LIBCHAPS --slot=1 --id=$CERTID --sign \ -i /tmp/1.txt -o /tmp/1.sig -m MD5-RSA-PKCS c) verify signature: openssl dgst -md5 -verify /tmp/pub.key \ -signature /tmp/1.sig /tmp/1.txt Step (b) should succeed and step (c) should return "Verified OK" Change-Id: I000f6dc5c40a0ffb0ecc45bbd3bac560dbc32dc9 Reviewed-on: https://chromium-review.googlesource.com/421010 Commit-Ready: Andrey Pronin <apronin@chromium.org> Tested-by: Andrey Pronin <apronin@chromium.org> Reviewed-by: Darren Krahn <dkrahn@chromium.org> " fail_count="0" gerrit_number="421010" owner_email="apronin@chromium.org" pass_count="0" patch_number="3" project="aosp/platform/system/tpm" project_url="https://chromium-review.googlesource.com/aosp/platform/system/tpm" ref="refs/changes/10/421010/3" remote="cros" total_fail_count="0"/><pending_commit branch="master" change_id="I0a37d60268fec2480d5d847f512dfe9c378b3fb9" commit="07645b469beef9aaffe45ed05411449ecf7c5c13" commit_message="autotest: Remove autotest_stats from autoserv BUG=chromium:667171 TEST=Run jobs on moblab. Change-Id: I0a37d60268fec2480d5d847f512dfe9c378b3fb9 Reviewed-on: https://chromium-review.googlesource.com/414446 Commit-Ready: Prathmesh Prabhu <pprabhu@chromium.org> Tested-by: Prathmesh Prabhu <pprabhu@chromium.org> Reviewed-by: Prathmesh Prabhu <pprabhu@chromium.org> " fail_count="1" gerrit_number="414446" owner_email="pprabhu@chromium.org" pass_count="0" patch_number="5" project="chromiumos/third_party/autotest" project_url="https://chromium-review.googlesource.com/chromiumos/third_party/autotest" ref="refs/changes/46/414446/5" remote="cros" total_fail_count="3"/><pending_commit branch="master" change_id="Ieefffae38469327b1df664b3eec8f17f702591b1" commit="e1ff0a55a6b10a5b0d12a217f7c3fb8235288c11" commit_message="autotest: Drop old feature to time individual tests. This is an old experimental feature that we aren't actively using. By removing this feature, we remove an unnecessary stat, and also reduce a call from autoserv to AFE. The feature was originally introduced for crbug.com/237811 BUG=chromium:667171 TEST=Run job on moblab. Change-Id: Ieefffae38469327b1df664b3eec8f17f702591b1 Reviewed-on: https://chromium-review.googlesource.com/414307 Commit-Ready: Prathmesh Prabhu <pprabhu@chromium.org> Tested-by: Prathmesh Prabhu <pprabhu@chromium.org> Reviewed-by: Prathmesh Prabhu <pprabhu@chromium.org> Reviewed-by: Aviv Keshet <akeshet@chromium.org> " fail_count="1" gerrit_number="414307" owner_email="pprabhu@chromium.org" pass_count="0" patch_number="5" project="chromiumos/third_party/autotest" project_url="https://chromium-review.googlesource.com/chromiumos/third_party/autotest" ref="refs/changes/07/414307/5" remote="cros" total_fail_count="2"/><pending_commit branch="master" change_id="I8d39db04c4ca3194f99e17840365429ed2d39390" commit="a5d18b5141aa60f1cf72cfb80ab4769638874808" commit_message="common/i2c.c: Check that i2c port is always 0 or greater Previously, an assert was checking the port value after the port value had been converted to the controller. Instead, verify that the value is not negative, and return if it is. The if sequence generates much less code than the ASSERT, and protects both paths. Fixes coverity warning 141748: Negative array index read 42 files changed. Total size change: -1248 bytes. Average size change: -29 bytes. These platforms increased in size: lucid/RO/ec.RO.flat grew by 4 bytes: (64404 to 64408) lucid/RW/ec.RW.flat grew by 20 bytes: (63996 to 64016) pyro/RO/ec.RO.flat grew by 120 bytes: (131212 to 131332) pyro/RW/ec.RW.flat grew by 144 bytes: (130764 to 130908) TEST=Build BUG=None BRANCH=None Change-Id: I8d39db04c4ca3194f99e17840365429ed2d39390 Signed-off-by: Martin Roth <martinroth@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/371401 Reviewed-by: Randall Spangler <rspangler@chromium.org> " fail_count="0" gerrit_number="371401" owner_email="martinroth@chromium.org" pass_count="0" patch_number="2" project="chromiumos/platform/ec" project_url="https://chromium-review.googlesource.com/chromiumos/platform/ec" ref="refs/changes/01/371401/2" remote="cros" total_fail_count="0"/><pending_commit branch="master" change_id="Ifb6f9e04b42ef21e3e667f420dbcdf77049fc533" commit="c4b9193b7019abca55a1c519f0e73204f346cc46" commit_message="power: Make WakeupController handle tablet mode. Make powerd's policy::WakeupController inhibit and configure S3 wakeup for input devices while in tablet mode. It previously had code for handling the mode, but was never wired up to be notified about tablet switch events. It's possible/likely that the udev tags around tablet mode will need to be updated, as this code has never been exercised. BUG=chromium:661368 TEST=added unit tests; also checked powerd log after switching in and out of tablet mode and saw that devices were inhibited and configured for wakeup as expected Change-Id: Ifb6f9e04b42ef21e3e667f420dbcdf77049fc533 Reviewed-on: https://chromium-review.googlesource.com/416373 Commit-Ready: Dan Erat <derat@chromium.org> Tested-by: Dan Erat <derat@chromium.org> Reviewed-by: Benson Leung <bleung@google.com> " fail_count="4" gerrit_number="416373" owner_email="derat@chromium.org" pass_count="0" patch_number="3" project="chromiumos/platform2" project_url="https://chromium-review.googlesource.com/chromiumos/platform2" ref="refs/changes/73/416373/3" remote="cros" total_fail_count="4"/><pending_commit branch="master" change_id="Ibcc499de860982261e5c59728a2fee5ee5bf8178" commit="d2d769b5a4d4debf6845a0736a70f6396cc9c54c" commit_message="fides: Nuke obsolete project. We no longer intend to ship fides in its current form on any hardware, so remove the code. There's always the option to bring it back should it become relevant in the future. BUG=none TEST=none Change-Id: Ibcc499de860982261e5c59728a2fee5ee5bf8178 Reviewed-on: https://chromium-review.googlesource.com/416429 Commit-Ready: Mattias Nissler <mnissler@chromium.org> Tested-by: Mattias Nissler <mnissler@chromium.org> Reviewed-by: Mattias Nissler <mnissler@chromium.org> Reviewed-by: Christoph Schütte <cschuet@chromium.org> " fail_count="0" gerrit_number="416429" owner_email="mnissler@chromium.org" pass_count="0" patch_number="1" project="chromiumos/platform2" project_url="https://chromium-review.googlesource.com/chromiumos/platform2" ref="refs/changes/29/416429/1" remote="cros" total_fail_count="0"/><pending_commit branch="master" change_id="Ib3bbbaf63ac7f787aa06133275ebbf6064c002f6" commit="6299b78f6e13e0e27232d51455d593b3fb0a8669" commit_message="autotest: unify email metrics to single metric BUG=None TEST=None Change-Id: Ib3bbbaf63ac7f787aa06133275ebbf6064c002f6 Reviewed-on: https://chromium-review.googlesource.com/418711 Commit-Ready: Aviv Keshet <akeshet@chromium.org> Tested-by: Aviv Keshet <akeshet@chromium.org> Reviewed-by: Prathmesh Prabhu <pprabhu@chromium.org> " fail_count="2" gerrit_number="418711" owner_email="akeshet@chromium.org" pass_count="0" patch_number="1" project="chromiumos/third_party/autotest" project_url="https://chromium-review.googlesource.com/chromiumos/third_party/autotest" ref="refs/changes/11/418711/1" remote="cros" total_fail_count="2"/><pending_commit branch="master" change_id="Ief7b584989cc456fc674dd06ff8fb388f8b91758" commit="5898d904366a2e832c553990c13b8da85519a0c2" commit_message="autotest: do not rebase before running automated_deploy The instructions on our internal website already tell you to make sure you are at ToT before running automated deploy. The `git pull --rebase` command failed for me (because I was not on a tracking branch) and caused the automated_deploy script to fail. Either we should make the script not crash when that fails, or we can just get rid of that git pull. BUG=None TEST=Ran automated_deploy locally to do a deployment. Change-Id: Ief7b584989cc456fc674dd06ff8fb388f8b91758 Reviewed-on: https://chromium-review.googlesource.com/419176 Commit-Ready: Aviv Keshet <akeshet@chromium.org> Tested-by: Aviv Keshet <akeshet@chromium.org> Reviewed-by: Shuqian Zhao <shuqianz@chromium.org> " fail_count="3" gerrit_number="419176" owner_email="akeshet@chromium.org" pass_count="0" patch_number="1" project="chromiumos/third_party/autotest" project_url="https://chromium-review.googlesource.com/chromiumos/third_party/autotest" ref="refs/changes/76/419176/1" remote="cros" total_fail_count="3"/><pending_commit branch="master" change_id="Iacfde8063914472b540661f1cd29faabc4905047" commit="991bd598f56af573a6ca56a5e5236f6dadd58ba8" commit_message="Change the depenency of system-locales. The system-locales requires exactly the same version as glibc. However, we could not upgrade glibc and system-locales in the same time. This is because the glibc is built by the sdk bot, but the system-locales is built for the target. If we upgrade these two package at the same time, in the commit queue buildbot, the buildbot will try to build glibc for target and it will fail. So glibc and system-locales can fall out of sync during an upgrade. BUG=chromium:674336 TEST=cbuildbot. Change-Id: Iacfde8063914472b540661f1cd29faabc4905047 Reviewed-on: https://chromium-review.googlesource.com/419696 Commit-Ready: Yunlian Jiang <yunlian@chromium.org> Tested-by: Yunlian Jiang <yunlian@chromium.org> Reviewed-by: Mike Frysinger <vapier@chromium.org> " fail_count="1" gerrit_number="419696" owner_email="yunlian@chromium.org" pass_count="0" patch_number="2" project="chromiumos/overlays/chromiumos-overlay" project_url="https://chromium-review.googlesource.com/chromiumos/overlays/chromiumos-overlay" ref="refs/changes/96/419696/2" remote="cros" total_fail_count="1"/><pending_commit branch="master" change_id="I210ca71bc98c56758b179cf292a90e89c8a757cb" commit="d8969b50c85dfd4907e66412a75d8332f9dab827" commit_message="Revert "Add authpolicy dependency to target-chromium-os ebuild" This reverts 63da1a3f6b03bb80835b878cebf8b6cbf8e6b363 (except for target-chromium-os-1-r59.ebuild, which is uprev'ed instead of reverted/downrev'ed). The above CL was temp. With CL:419436 the actual implementation has landed. BUG=chromium:667696 TEST=build_packages on x86-generic and amd64-generic Change-Id: I210ca71bc98c56758b179cf292a90e89c8a757cb Reviewed-on: https://chromium-review.googlesource.com/420986 Commit-Ready: Lutz Justen <ljusten@chromium.org> Tested-by: Lutz Justen <ljusten@chromium.org> Reviewed-by: Mike Frysinger <vapier@chromium.org> " fail_count="0" gerrit_number="420986" owner_email="ljusten@chromium.org" pass_count="0" patch_number="2" project="chromiumos/overlays/chromiumos-overlay" project_url="https://chromium-review.googlesource.com/chromiumos/overlays/chromiumos-overlay" ref="refs/changes/86/420986/2" remote="cros" total_fail_count="0"/><pending_commit branch="master" change_id="Ica583d9a95d78689ee1b21ccfa882fced2a414d9" commit="a1c7517c73c8d6b3da1261825c5691569eebb36c" commit_message="eve: Ignore VCC1_RST status bit when determining reset cause The EC on Eve has VCC1_RST connected to 3.3DSW which drops when resetting for recovery. Since I need this to work on current boards treat Eve the same as Wheatley and use the workaround that always reports reset-pin instead of power-on status. BUG=chrome-os-partner:61028 BRANCH=none TEST=successfully enter recovery mode on eve with the keyboard Change-Id: Ica583d9a95d78689ee1b21ccfa882fced2a414d9 Signed-off-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/421128 Reviewed-by: Shawn N <shawnn@chromium.org> " fail_count="0" gerrit_number="421128" owner_email="dlaurie@chromium.org" pass_count="0" patch_number="2" project="chromiumos/platform/ec" project_url="https://chromium-review.googlesource.com/chromiumos/platform/ec" ref="refs/changes/28/421128/2" remote="cros" total_fail_count="0"/><pending_commit branch="master" change_id="I2dccc78174acee79a836f9520d850f17cdf27b8c" commit="6fe52e39e440c149517bb97c285804c29eadcc52" commit_message="chromeos-bootimage: fix payload placement in netboot image As Julius noted in CL:418781, the payloads were put in the wrong regions in the netboot image. BUG=chromium:595715 BRANCH=none TEST=none Change-Id: I2dccc78174acee79a836f9520d850f17cdf27b8c Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/420724 Reviewed-by: Stefan Reinauer <reinauer@chromium.org> " fail_count="0" gerrit_number="420724" owner_email="pgeorgi@chromium.org" pass_count="0" patch_number="1" project="chromiumos/overlays/chromiumos-overlay" project_url="https://chromium-review.googlesource.com/chromiumos/overlays/chromiumos-overlay" ref="refs/changes/24/420724/1" remote="cros" total_fail_count="0"/><pending_commit branch="master" change_id="I9158d642ea9660714de786409cd54c8fb248e24e" commit="8fe2157a3e7558b4a1274abd1f8b7e62d1c631ef" commit_message="Add monarch metrics for Buildbucket cancel operation on pre-cq runs. BUG=chromium:672242 TEST=run_tests Change-Id: I9158d642ea9660714de786409cd54c8fb248e24e Reviewed-on: https://chromium-review.googlesource.com/419801 Commit-Ready: Ningning Xia <nxia@chromium.org> Tested-by: Ningning Xia <nxia@chromium.org> Reviewed-by: Ningning Xia <nxia@chromium.org> " fail_count="0" gerrit_number="419801" owner_email="nxia@chromium.org" pass_count="0" patch_number="2" project="chromiumos/chromite" project_url="https://chromium-review.googlesource.com/chromiumos/chromite" ref="refs/changes/01/419801/2" remote="cros" total_fail_count="1"/><pending_commit branch="master" change_id="Ibb0d4f0af1a842b82642fc5c4e8ca9f2e67f4c7a" commit="62d0166f8d68be2fe0377a0db6c6464ab753bf48" commit_message="Add platform_SuspendResumeTiming to ebuild BUG=chromium:653315 TEST=None Change-Id: Ibb0d4f0af1a842b82642fc5c4e8ca9f2e67f4c7a Reviewed-on: https://chromium-review.googlesource.com/420828 Commit-Ready: Kalin Stoyanov <kalin@chromium.org> Tested-by: Kalin Stoyanov <kalin@chromium.org> Reviewed-by: Ruchi Jahagirdar <rjahagir@chromium.org> " fail_count="1" gerrit_number="420828" owner_email="kalin@chromium.org" pass_count="0" patch_number="1" project="chromiumos/overlays/chromiumos-overlay" project_url="https://chromium-review.googlesource.com/chromiumos/overlays/chromiumos-overlay" ref="refs/changes/28/420828/1" remote="cros" total_fail_count="1"/><pending_commit branch="master" change_id="Idfcce1cf7b04501b105f78a1e132fd27de657480" commit="0c2d204b409044db0556c263b66384b779deb3c8" commit_message="Adding graphics_VTSwitch to telemetry ebuild. BUG=None TEST=None Change-Id: Idfcce1cf7b04501b105f78a1e132fd27de657480 Reviewed-on: https://chromium-review.googlesource.com/419819 Commit-Ready: Ruchi Jahagirdar <rjahagir@chromium.org> Tested-by: Ruchi Jahagirdar <rjahagir@chromium.org> Reviewed-by: Ruchi Jahagirdar <rjahagir@chromium.org> " fail_count="3" gerrit_number="419819" owner_email="rjahagir@chromium.org" pass_count="0" patch_number="2" project="chromiumos/overlays/chromiumos-overlay" project_url="https://chromium-review.googlesource.com/chromiumos/overlays/chromiumos-overlay" ref="refs/changes/19/419819/2" remote="cros" total_fail_count="3"/><pending_commit branch="master" change_id="I6fc73b2ac76ccb3bac01f52707f5016505713fca" commit="a4baf096a6d78a0312f5d3440e8605cb9983e50b" commit_message="tpm2: handle failures more gracefully When trying to bring up a device with a malfunctioning TPM2 chip, the driver currently gets stuck waiting for SPI flow control, causing bricked devices. This patch puts a 100 ms cap on the waiting time - this should be enough even for a longest NVRAM save operation which could be under way on the TPM device. BRANCH=gru BUG=chrome-os-partner:59807 TEST=with a matching change in coreboot, now a gru with corrupted SPI TPM comes up to the recovery screen (it was not showing signs of life before this change). Change-Id: I6fc73b2ac76ccb3bac01f52707f5016505713fca Signed-off-by: Vadim Bendebury <vbendeb@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/421174 Reviewed-by: Aaron Durbin <adurbin@chromium.org> " fail_count="0" gerrit_number="421174" owner_email="vbendeb@chromium.org" pass_count="0" patch_number="1" project="chromiumos/platform/depthcharge" project_url="https://chromium-review.googlesource.com/chromiumos/platform/depthcharge" ref="refs/changes/74/421174/1" remote="cros" total_fail_count="0"/><lkgm version="9092.0.0-rc3"/></manifest> |
