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| <pending_commit branch="chromeos-2016.05" change_id="Ib7336bc10123f2f50c464916b285ada6a691242b" commit="a2bf29ae759bf1d92b8b94a7bf2cce04eea60b91" commit_message="UPSTREAM: usbdebug: Fix init and add support for postcar It was originally designed such that if usbdebug_init() was called before cbmem_initialize(), it would fetch the already-initialized state from CBMEM. This changed when cbmem_find() behaviour changed to require cbmem_initialize() to be called first. As a result, ramstage had to reinitialize all of the EHCI controller and USB endpoints on entry. This was slow, specially with AMD hardware where one can scan USB ports to probe for the debug dongle. For postcar and ramstage, move usbdebug entry such that it is triggered from CBMEM_INIT_HOOK instead of console_init(). Side-effect of this is usbdebug console shows 'coreboot-xxx ... starting...' line only for romstage. Initialisation for usbdebug is never done in postcar. If you have USBDEBUG_IN_ROMSTAGE=n, postcar will not have console output on usb either. While at it, fix also some other __PRE_RAM__ cases to ENV_ROMSTAGE and alike. BUG=none BRANCH=none TEST=none Change-Id: Ib7336bc10123f2f50c464916b285ada6a691242b Signed-off-by: Patrick Georgi <pgeorgi@google.com> Original-Commit-Id: d07f377872d1d229a8a9cc1d4a2c66f535e95fe3 Original-Change-Id: If8ab973321a801abc5529f3ff68c5dccae9512ad Original-Signed-off-by: Kysti Mlkki <kyosti.malkki@gmail.com> Original-Reviewed-on: https://review.coreboot.org/21443 Original-Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/667180 Commit-Ready: Patrick Georgi <pgeorgi@chromium.org> Tested-by: Patrick Georgi <pgeorgi@chromium.org> Reviewed-by: Patrick Georgi <pgeorgi@chromium.org> " fail_count="0" gerrit_number="667180" owner_email="pgeorgi@chromium.org" pass_count="0" patch_number="1" project="chromiumos/third_party/coreboot" project_url="https://chromium-review.googlesource.com/chromiumos/third_party/coreboot" ref="refs/changes/80/667180/1" remote="cros" total_fail_count="0"/><pending_commit branch="chromeos-2016.05" change_id="I446e325cc863e4222e413531069b3461568d0cab" commit="1015abe65459daf6e5b639ff8aa667479c327e0a" commit_message="UPSTREAM: device: acpi_name() should take a const struct device There's no reason to mutate the struct device when determining the ACPI name for a device. Adjust the function pointer signature and the respective implementations to use const struct device. BUG=none BRANCH=none TEST=none Change-Id: I446e325cc863e4222e413531069b3461568d0cab Signed-off-by: Patrick Georgi <pgeorgi@google.com> Original-Commit-Id: aa090cb6ea696d9b6a2869e16c53bd8b14a0e7d1 Original-Change-Id: If5e1f4de36a53646616581b01f47c4e86822c42e Original-Signed-off-by: Aaron Durbin <adurbin@chromium.org> Original-Reviewed-on: https://review.coreboot.org/21527 Original-Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Original-Reviewed-by: Furquan Shaikh <furquan@google.com> Original-Reviewed-by: Subrata Banik <subrata.banik@intel.com> Original-Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-on: https://chromium-review.googlesource.com/667181 Commit-Ready: Patrick Georgi <pgeorgi@chromium.org> Tested-by: Patrick Georgi <pgeorgi@chromium.org> Reviewed-by: Patrick Georgi <pgeorgi@chromium.org> " fail_count="0" gerrit_number="667181" owner_email="pgeorgi@chromium.org" pass_count="0" patch_number="1" project="chromiumos/third_party/coreboot" project_url="https://chromium-review.googlesource.com/chromiumos/third_party/coreboot" ref="refs/changes/81/667181/1" remote="cros" total_fail_count="0"/><pending_commit branch="chromeos-2016.05" change_id="I038dc5242f3a99ff9819c64a7a7473e66ebbf317" commit="99e4e803ee5e4fde5cb366d3995f4b6d001e1589" commit_message="UPSTREAM: intel/common/systemagent: Add API to get SOC specific PRMRR base and mask Implement weak definition and SOC specific code would implement actual definition. BUG=none BRANCH=none TEST=none Change-Id: I038dc5242f3a99ff9819c64a7a7473e66ebbf317 Signed-off-by: Patrick Georgi <pgeorgi@google.com> Original-Commit-Id: 82cdfa73d5fbe8ded890f5bb4079a67f57449db1 Original-Change-Id: I5e787a2603aaa475cb5c61558cc31ec0afcb4a8b Original-Signed-off-by: Pratik Prajapati <pratikkumar.v.prajapati@intel.com> Original-Reviewed-on: https://review.coreboot.org/21243 Original-Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/667182 Commit-Ready: Patrick Georgi <pgeorgi@chromium.org> Tested-by: Patrick Georgi <pgeorgi@chromium.org> Reviewed-by: Patrick Georgi <pgeorgi@chromium.org> " fail_count="0" gerrit_number="667182" owner_email="pgeorgi@chromium.org" pass_count="0" patch_number="1" project="chromiumos/third_party/coreboot" project_url="https://chromium-review.googlesource.com/chromiumos/third_party/coreboot" ref="refs/changes/82/667182/1" remote="cros" total_fail_count="0"/><pending_commit branch="chromeos-2016.05" change_id="I5a91b3422cab41b1b8b134f702d17c3f5bb6a9aa" commit="e973e21bc8ce4ee48ed5e393082ab16edfb523c0" commit_message="UPSTREAM: soc/intel/apollolake: Implement UNCORE PRMRR get base and mask API Implement soc_get_uncore_prmmr_base_and_mask() API for APL/GLK BUG=none BRANCH=none TEST=none Change-Id: I5a91b3422cab41b1b8b134f702d17c3f5bb6a9aa Signed-off-by: Patrick Georgi <pgeorgi@google.com> Original-Commit-Id: 738414586d1b6eb0339e1e70534c68e0c2d36027 Original-Change-Id: I57df1f0e8ff984f32de4efdc6ebd68be501b4799 Original-Signed-off-by: Pratik Prajapati <pratikkumar.v.prajapati@intel.com> Original-Reviewed-on: https://review.coreboot.org/21244 Original-Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/667183 Commit-Ready: Patrick Georgi <pgeorgi@chromium.org> Tested-by: Patrick Georgi <pgeorgi@chromium.org> Reviewed-by: Patrick Georgi <pgeorgi@chromium.org> " fail_count="0" gerrit_number="667183" owner_email="pgeorgi@chromium.org" pass_count="0" patch_number="1" project="chromiumos/third_party/coreboot" project_url="https://chromium-review.googlesource.com/chromiumos/third_party/coreboot" ref="refs/changes/83/667183/1" remote="cros" total_fail_count="0"/><pending_commit branch="chromeos-2016.05" change_id="If35f20badcc1a16d9d65e90adc258c98f8f55fa2" commit="a9b4e4988cd09fc5e1e0e75ecfb2f0fd8358c35b" commit_message="UPSTREAM: soc/intel/skylake: Implement UNCORE PRMRR get base and mask API Implement soc_get_uncore_prmmr_base_and_mask() API for SKL/KBL BUG=none BRANCH=none TEST=none Change-Id: If35f20badcc1a16d9d65e90adc258c98f8f55fa2 Signed-off-by: Patrick Georgi <pgeorgi@google.com> Original-Commit-Id: 653f019d0d4de5e50281edae2f1d88af58e53388 Original-Change-Id: I880d3d88138809cdf030507877079cbea52a0d97 Original-Signed-off-by: Pratik Prajapati <pratikkumar.v.prajapati@intel.com> Original-Reviewed-on: https://review.coreboot.org/21245 Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> Original-Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-on: https://chromium-review.googlesource.com/667184 Commit-Ready: Patrick Georgi <pgeorgi@chromium.org> Tested-by: Patrick Georgi <pgeorgi@chromium.org> Reviewed-by: Patrick Georgi <pgeorgi@chromium.org> " fail_count="0" gerrit_number="667184" owner_email="pgeorgi@chromium.org" pass_count="0" patch_number="1" project="chromiumos/third_party/coreboot" project_url="https://chromium-review.googlesource.com/chromiumos/third_party/coreboot" ref="refs/changes/84/667184/1" remote="cros" total_fail_count="0"/><pending_commit branch="chromeos-2016.05" change_id="Ide535bb1c5078290ef5bb545a1a429e07db26b4f" commit="33545387012c2e538c9cfc0f9a4ea5f7030dd156" commit_message="UPSTREAM: timestamp: Add function to get time since boot Add a function to retrieve the elapsed time since boot. For that purpose use the base time in the timestamp table among with the current timestamp at call time of the function. So more precise the returned time is the elapsed time since the timestamp was initialized scaled in microseconds. This was chosen to get a reliable value even on platforms where the TSC might not be reset on software reset or warm start. BUG=none BRANCH=none TEST=none Change-Id: Ide535bb1c5078290ef5bb545a1a429e07db26b4f Signed-off-by: Patrick Georgi <pgeorgi@google.com> Original-Commit-Id: 35cceb861c90083ea5dd6ad084141280d905aa36 Original-Change-Id: Ib93ad89078645c0ebe256048cb48f9622c90451f Original-Signed-off-by: Werner Zeh <werner.zeh@siemens.com> Original-Reviewed-on: https://review.coreboot.org/21516 Original-Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Original-Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/667185 Commit-Ready: Patrick Georgi <pgeorgi@chromium.org> Tested-by: Patrick Georgi <pgeorgi@chromium.org> Reviewed-by: Patrick Georgi <pgeorgi@chromium.org> " fail_count="0" gerrit_number="667185" owner_email="pgeorgi@chromium.org" pass_count="0" patch_number="1" project="chromiumos/third_party/coreboot" project_url="https://chromium-review.googlesource.com/chromiumos/third_party/coreboot" ref="refs/changes/85/667185/1" remote="cros" total_fail_count="0"/><pending_commit branch="chromeos-2016.05" change_id="I2d3082463995144cc619303c643f8858074820dd" commit="649ca7da397afdfa984082c4e9931b6abcaadc98" commit_message="UPSTREAM: siemens/mc_apl1: Add delay to wait for legacy devices There are old legacy onboard devices which are too slow for a coreboot boot with log level BIOS_ERR. In this case coreboot is so fast that these devices do not have enough time to become visible on the PCI bus and this in turn leads to missing resource allocation for this devices. The most generic way to work around this problem on existing hardware is to introduce a delay right before the PCI enumeration starts. The needed delay time depends on the hardware and will therefore be get from hwinfo. BUG=none BRANCH=none TEST=none Change-Id: I2d3082463995144cc619303c643f8858074820dd Signed-off-by: Patrick Georgi <pgeorgi@google.com> Original-Commit-Id: efd0eb35af5e5620331d885d3140c734a6fc9098 Original-Change-Id: Ia91babc81e3a347bbc498c3def97b2ea70e10922 Original-Signed-off-by: Werner Zeh <werner.zeh@siemens.com> Original-Reviewed-on: https://review.coreboot.org/21518 Original-Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Original-Reviewed-by: Mario Scheithauer <mario.scheithauer@siemens.com> Reviewed-on: https://chromium-review.googlesource.com/667186 Commit-Ready: Patrick Georgi <pgeorgi@chromium.org> Tested-by: Patrick Georgi <pgeorgi@chromium.org> Reviewed-by: Patrick Georgi <pgeorgi@chromium.org> " fail_count="0" gerrit_number="667186" owner_email="pgeorgi@chromium.org" pass_count="0" patch_number="1" project="chromiumos/third_party/coreboot" project_url="https://chromium-review.googlesource.com/chromiumos/third_party/coreboot" ref="refs/changes/86/667186/1" remote="cros" total_fail_count="0"/><pending_commit branch="chromeos-2016.05" change_id="I04f51ed9b86cf4723fd299e9b1c994c8ec5e51ef" commit="fee3fa473e39555a45c86f4413ab35e85e295d23" commit_message="UPSTREAM: src/soc/intel/cannonlake: Define USB configuration params Define USB2, USB3 and Type-C configuration for CannonLake. BUG=none BRANCH=none TEST=none Change-Id: I04f51ed9b86cf4723fd299e9b1c994c8ec5e51ef Signed-off-by: Patrick Georgi <pgeorgi@google.com> Original-Commit-Id: c82e1fbcabe54b4c19d93f4252df93a606dfb075 Original-Change-Id: I42243950366d672e886158eb1934350f47b4ff1f Original-Signed-off-by: Pratik Prajapati <pratikkumar.v.prajapati@intel.com> Original-Reviewed-on: https://review.coreboot.org/21339 Original-Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/667187 Commit-Ready: Patrick Georgi <pgeorgi@chromium.org> Tested-by: Patrick Georgi <pgeorgi@chromium.org> Reviewed-by: Patrick Georgi <pgeorgi@chromium.org> " fail_count="0" gerrit_number="667187" owner_email="pgeorgi@chromium.org" pass_count="0" patch_number="1" project="chromiumos/third_party/coreboot" project_url="https://chromium-review.googlesource.com/chromiumos/third_party/coreboot" ref="refs/changes/87/667187/1" remote="cros" total_fail_count="0"/><pending_commit branch="chromeos-2016.05" change_id="I887dd1b23816a671bd4dfb39bb3bd595cdbccb90" commit="67b0442e6d0bf9b5cb9548ce4987bf9f6f1af9f9" commit_message="UPSTREAM: mainboard/intel/cannonlake_rvp-y: Configure USB ports Configure USB2, USB3 and Type-C ports for CannonLake-Y RVP BUG=none BRANCH=none TEST=none Change-Id: I887dd1b23816a671bd4dfb39bb3bd595cdbccb90 Signed-off-by: Patrick Georgi <pgeorgi@google.com> Original-Commit-Id: b2d6902086d6b7058d8d7a31959c1a16264e4092 Original-Change-Id: Ic3b6b481cb33bfefb267910a5e649877d900d109 Original-Signed-off-by: Pratik Prajapati <pratikkumar.v.prajapati@intel.com> Original-Reviewed-on: https://review.coreboot.org/21481 Original-Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/667188 Commit-Ready: Patrick Georgi <pgeorgi@chromium.org> Tested-by: Patrick Georgi <pgeorgi@chromium.org> Reviewed-by: Patrick Georgi <pgeorgi@chromium.org> " fail_count="0" gerrit_number="667188" owner_email="pgeorgi@chromium.org" pass_count="0" patch_number="1" project="chromiumos/third_party/coreboot" project_url="https://chromium-review.googlesource.com/chromiumos/third_party/coreboot" ref="refs/changes/88/667188/1" remote="cros" total_fail_count="0"/><pending_commit branch="chromeos-2016.05" change_id="I7114391ea8bb8b78f718f44886bebe1d19bff76e" commit="8d217c587afa2730d045efe44823b3ea83921a16" commit_message="UPSTREAM: mainboard/intel/cannonlake_rvp-u: Configure USB ports Configure USB2, USB3 and Type-C ports for CannonLake-U RVP BUG=none BRANCH=none TEST=none Change-Id: I7114391ea8bb8b78f718f44886bebe1d19bff76e Signed-off-by: Patrick Georgi <pgeorgi@google.com> Original-Commit-Id: 982688a41ae91218fbb2cfbdb8ff19005ffce0f9 Original-Change-Id: Id875063721ccb62ad4b5187c81f6abf44bf93f74 Original-Signed-off-by: Pratik Prajapati <pratikkumar.v.prajapati@intel.com> Original-Reviewed-on: https://review.coreboot.org/21482 Original-Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/667189 Commit-Ready: Patrick Georgi <pgeorgi@chromium.org> Tested-by: Patrick Georgi <pgeorgi@chromium.org> Reviewed-by: Patrick Georgi <pgeorgi@chromium.org> " fail_count="0" gerrit_number="667189" owner_email="pgeorgi@chromium.org" pass_count="0" patch_number="1" project="chromiumos/third_party/coreboot" project_url="https://chromium-review.googlesource.com/chromiumos/third_party/coreboot" ref="refs/changes/89/667189/1" remote="cros" total_fail_count="0"/><pending_commit branch="chromeos-2016.05" change_id="Ic9d5a7ecc08c72475a9ef597c0f7e2f8c5eb05ce" commit="9377dc6b65bfe7e26774d1f22416f27670d0ff65" commit_message="UPSTREAM: google/cyan: convert to variant configuration Setup cyan to be the baseboard for other Google Braswell boards, to be added in subsequent commits: - Keep code common to all Google Braswell boards in the baseboard, and separate out the board-specific bits into the new cyan variant. - Define the I2C ACPI devices such that they can be easily reused for other variants. - Switch the trackpad/touchscreen interrupts from edge to level, for better performance/compatibility, as was done with all previous Google boards. - Add code to the baseboard to allow optional variant-specific parameters to be used for both memory and silicon init. - Remove superfluous includes, replace some hardcoded values with variables, and correct typos/formatting errors. BUG=none BRANCH=none TEST=none Change-Id: Ic9d5a7ecc08c72475a9ef597c0f7e2f8c5eb05ce Signed-off-by: Patrick Georgi <pgeorgi@google.com> Original-Commit-Id: e69a9c75816dd3cd6a9af50a09eb090ea00cfed4 Original-Change-Id: Iabbbad16efa9cfa79338f4e94d0771779900d8d9 Original-Signed-off-by: Matt DeVillier <matt.devillier@gmail.com> Original-Reviewed-on: https://review.coreboot.org/21126 Original-Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/667190 Commit-Ready: Patrick Georgi <pgeorgi@chromium.org> Tested-by: Patrick Georgi <pgeorgi@chromium.org> Reviewed-by: Patrick Georgi <pgeorgi@chromium.org> " fail_count="0" gerrit_number="667190" owner_email="pgeorgi@chromium.org" pass_count="0" patch_number="1" project="chromiumos/third_party/coreboot" project_url="https://chromium-review.googlesource.com/chromiumos/third_party/coreboot" ref="refs/changes/90/667190/1" remote="cros" total_fail_count="0"/><pending_commit branch="chromeos-2016.05" change_id="I7d9cf9b0a4b679d865acacd8d11e44fd40618b92" commit="25422fb6a2fab4725e0a05148a82919c0f3b61d9" commit_message="UPSTREAM: MAINTAINERS: Add INTEL FSP DENVERTON-NS SOC & HARCUVAR CRB Add Intel FSP Atom C3000 SoC ("Denverton" and "Denverton-NS") and Harcuvar CRB to the list. BUG=none BRANCH=none TEST=none Change-Id: I7d9cf9b0a4b679d865acacd8d11e44fd40618b92 Signed-off-by: Patrick Georgi <pgeorgi@google.com> Original-Commit-Id: 025d819ee1d2f0e16af38d68fd7bb50c743b4960 Original-Change-Id: I1c4bfd0900e8d425b95b5ef6c541b1e988846667 Original-Signed-off-by: Mariusz Szafranski <mariuszx.szafranski@intel.com> Original-Reviewed-on: https://review.coreboot.org/21515 Original-Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Original-Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Original-Reviewed-by: FEI WANG <wangfei.jimei@gmail.com> Reviewed-on: https://chromium-review.googlesource.com/667191 Commit-Ready: Patrick Georgi <pgeorgi@chromium.org> Tested-by: Patrick Georgi <pgeorgi@chromium.org> Reviewed-by: Patrick Georgi <pgeorgi@chromium.org> " fail_count="0" gerrit_number="667191" owner_email="pgeorgi@chromium.org" pass_count="0" patch_number="1" project="chromiumos/third_party/coreboot" project_url="https://chromium-review.googlesource.com/chromiumos/third_party/coreboot" ref="refs/changes/91/667191/1" remote="cros" total_fail_count="0"/><pending_commit branch="chromeos-2016.05" change_id="I8f3a10844c3f9a19075e88a602520addea3520ab" commit="243c3536b15227bb462a6b2a8537c2707e2365e5" commit_message="UPSTREAM: MAINTAINERS: Add Julius as LZ4 maintainer I imported the LZ4 compression code and want to keep an eye on it to ensure that our sources stay in sync with upstream. BUG=none BRANCH=none TEST=none Change-Id: I8f3a10844c3f9a19075e88a602520addea3520ab Signed-off-by: Patrick Georgi <pgeorgi@google.com> Original-Commit-Id: 848f5db3459cb440e56df8f76ffabd2b9708fd09 Original-Change-Id: I249ce24f6630d66d451d993198cd267478e5743e Original-Signed-off-by: Julius Werner <jwerner@chromium.org> Original-Reviewed-on: https://review.coreboot.org/21488 Original-Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Original-Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Original-Reviewed-by: Martin Roth <martinroth@google.com> Reviewed-on: https://chromium-review.googlesource.com/667192 Commit-Ready: Patrick Georgi <pgeorgi@chromium.org> Tested-by: Patrick Georgi <pgeorgi@chromium.org> Reviewed-by: Patrick Georgi <pgeorgi@chromium.org> " fail_count="0" gerrit_number="667192" owner_email="pgeorgi@chromium.org" pass_count="0" patch_number="1" project="chromiumos/third_party/coreboot" project_url="https://chromium-review.googlesource.com/chromiumos/third_party/coreboot" ref="refs/changes/92/667192/1" remote="cros" total_fail_count="0"/><pending_commit branch="chromeos-2016.05" change_id="Ifc6bc73b55e412efaeeb844c46354caaa377c0f3" commit="b95a1576cf5e7038a07dce8ebc25e6d23df0e567" commit_message="UPSTREAM: MAINTAINERS: Remove extra unnecessary space Remove extra unnecessary space at end of line. BUG=none BRANCH=none TEST=none Change-Id: Ifc6bc73b55e412efaeeb844c46354caaa377c0f3 Signed-off-by: Patrick Georgi <pgeorgi@google.com> Original-Commit-Id: 1638a85b495fbf32680a3baf141ef959cb201257 Original-Change-Id: I27688c3b8df71b875f1dc1020465d838756362be Original-Signed-off-by: Sumeet Pawnikar <sumeet.r.pawnikar@intel.com> Original-Reviewed-on: https://review.coreboot.org/21521 Original-Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Original-Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Original-Reviewed-by: Philippe Mathieu-Daud <f4bug@amsat.org> Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/667193 Commit-Ready: Patrick Georgi <pgeorgi@chromium.org> Tested-by: Patrick Georgi <pgeorgi@chromium.org> Reviewed-by: Patrick Georgi <pgeorgi@chromium.org> " fail_count="0" gerrit_number="667193" owner_email="pgeorgi@chromium.org" pass_count="0" patch_number="1" project="chromiumos/third_party/coreboot" project_url="https://chromium-review.googlesource.com/chromiumos/third_party/coreboot" ref="refs/changes/93/667193/1" remote="cros" total_fail_count="0"/><pending_commit branch="master" change_id="I1f7419fa5d44dcf3eaee178f0a619cfd42689351" commit="6046849e35ed303b137c5544d1697bb24bf17e3b" commit_message="minigbm: cros_gralloc: fix mis-named variable BUG=none TEST=none Change-Id: I1f7419fa5d44dcf3eaee178f0a619cfd42689351 Reviewed-on: https://chromium-review.googlesource.com/668216 Commit-Ready: Gurchetan Singh <gurchetansingh@chromium.org> Tested-by: Gurchetan Singh <gurchetansingh@chromium.org> Reviewed-by: Gurchetan Singh <gurchetansingh@chromium.org> " fail_count="0" gerrit_number="668216" owner_email="gurchetansingh@chromium.org" pass_count="0" patch_number="1" project="chromiumos/platform/minigbm" project_url="https://chromium-review.googlesource.com/chromiumos/platform/minigbm" ref="refs/changes/16/668216/1" remote="cros" total_fail_count="0"/><pending_commit branch="master" change_id="I7839b5a348f95f38385a555a8fe3ab0982d3533f" commit="65cd59bdc9366c06950f8ee6ef5c099f91a4fd55" commit_message="minigbm: move tegra_bo_import to be above tegra_bo_map, and run clang-format IMO this looks nicer. BUG=chromium:764871 TEST=gbmtest on Tegra Change-Id: I7839b5a348f95f38385a555a8fe3ab0982d3533f Reviewed-on: https://chromium-review.googlesource.com/668217 Commit-Ready: Gurchetan Singh <gurchetansingh@chromium.org> Tested-by: Gurchetan Singh <gurchetansingh@chromium.org> Reviewed-by: Gurchetan Singh <gurchetansingh@chromium.org> " fail_count="0" gerrit_number="668217" owner_email="gurchetansingh@chromium.org" pass_count="0" patch_number="1" project="chromiumos/platform/minigbm" project_url="https://chromium-review.googlesource.com/chromiumos/platform/minigbm" ref="refs/changes/17/668217/1" remote="cros" total_fail_count="0"/><pending_commit branch="master" change_id="Ice7a4267e10f5ea1c6bf6aa6fbdd206a1500498b" commit="181c7b7460fbf2385af09bd82a5f60d74ce915c8" commit_message="Add Bluetooth LE Mouse support to Chameleon This patch implements the Chameleon-side changes that allow the kit to emulate a Bluetooth LE (HOG) mouse. BUG=chromium:752719 TEST=Run this code on the Chameleon board, with a Bluefruit attached: $ make && make remote-install CHAMELEON_HOST=$CHAMELEON_IP Execute the non-flaky non-stress tests that use this code, see that the tests pass: $ test_that --board ${BOARD} --args "chameleon_host=${CHAMELEON_IP}" \ ${DUT_IP} bluetooth_AdapterPairing.le.mouse \ bluetooth_AdapterPairing.le.mouse.pairing_twice \ bluetooth_AdapterHIDReports.le.mouse Change-Id: Ice7a4267e10f5ea1c6bf6aa6fbdd206a1500498b Reviewed-on: https://chromium-review.googlesource.com/664419 Commit-Ready: Alexander Lent <alent@google.com> Tested-by: Alexander Lent <alent@google.com> Reviewed-by: Shyh-In Hwang <josephsih@chromium.org> " fail_count="0" gerrit_number="664419" owner_email="alent@google.com" pass_count="0" patch_number="9" project="chromiumos/platform/chameleon" project_url="https://chromium-review.googlesource.com/chromiumos/platform/chameleon" ref="refs/changes/19/664419/9" remote="cros" total_fail_count="0"/><pending_commit branch="master" change_id="Ia0929b9e5cea1da92903f2b4fa0a378cf2a67898" commit="b745f0680010bf99aefd5d2ecea9b9c66cf3945b" commit_message="[autotest] Add Bluetooth LE support to HID tests Add control files to enable testing with a Bluetooth LE mouse, and make the changes necessary to support the API changes in Chameleon that made this possible. IMPORTANT: These tests will not run until the chameleon:bt_hog label exists in the lab, so track that in: http://crbug.com/765451 This involves modifying some of the successful/retry logic to allow certain falsy responses when reasonable. This depends on API changes in Chameleon to do feature detection, so we can work around tests that the Bluefruit LE Friend doesn't support. Also, let's change GetChipName -> GetAdvertisedName while we're changing things. Mouse movement support depends on that being implemented in Chameleon, which isn't done yet. You can watch it fail, though. BUG=chromium:752719 CQ-DEPEND=CL:658697,CL:664419 TEST=Execute the non-flaky non-stress tests that use this code, see that the tests pass: $ test_that --board ${BOARD} --args "chameleon_host=${CHAMELEON_IP}" \ ${DUT_IP} bluetooth_AdapterPairing.{,le.}mouse \ bluetooth_AdapterPairing.{,le.}mouse.pairing_twice \ bluetooth_AdapterHIDReports.{,le.}mouse Change-Id: Ia0929b9e5cea1da92903f2b4fa0a378cf2a67898 Reviewed-on: https://chromium-review.googlesource.com/639850 Commit-Ready: Alexander Lent <alent@google.com> Tested-by: Alexander Lent <alent@google.com> Reviewed-by: Shyh-In Hwang <josephsih@chromium.org> " fail_count="0" gerrit_number="639850" owner_email="alent@google.com" pass_count="0" patch_number="24" project="chromiumos/third_party/autotest" project_url="https://chromium-review.googlesource.com/chromiumos/third_party/autotest" ref="refs/changes/50/639850/24" remote="cros" total_fail_count="0"/><pending_commit branch="master" change_id="Ie347270aa9c00342de13489c9422e45e681b94c2" commit="973b20e17f6eb10e9607dc55a1e48b140da49fa9" commit_message="Makefile: Generate hashes for the touchpad FW Based on the passed TOUCHPAD_FW parameter to the make command, the build system generates hashes for the touchpad FW. To generate the hashes, gen_touchpad_hash splits the touchpad FW in blocks of CONFIG_UPDATE_PDU_SIZE, that are hashed individually (SHA-256), and then stored in the EC image. This will allow the USB updater code to verify the integrity of the touchpad firmware being flashed. When no FW is provided, zeros are output, which do not match any valid data. BRANCH=none BUG=b:63993173 TEST=make TOUCHPAD_FW=SA459C-1211_ForGoogleHammer_3.0.bin \ BOARD=hammer -j TEST=Using variations of make TOUCHPAD_FW=SA459C-1211_ForGoogleHammer_3.0.bin \ BOARD=hammer -j make TOUCHPAD_FW=SA459C-1211_ForGoogleHammer_4.0.bin \ BOARD=hammer -j make BOARD=hammer -j Check that TPHASH touchpad_fw_hash.h is only regenerated when the parameter changes. Change-Id: Ie347270aa9c00342de13489c9422e45e681b94c2 Signed-off-by: Nicolas Boichat <drinkcat@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/615321 Reviewed-by: Vincent Palatin <vpalatin@chromium.org> " fail_count="0" gerrit_number="615321" owner_email="drinkcat@chromium.org" pass_count="0" patch_number="13" project="chromiumos/platform/ec" project_url="https://chromium-review.googlesource.com/chromiumos/platform/ec" ref="refs/changes/21/615321/13" remote="cros" total_fail_count="0"/><pending_commit branch="master" change_id="If5d2be57b63e16ee81aa9acaf840c5084f9b92de" commit="aafcb4db1e59e1d42eba66265a9e50b04ddb55a7" commit_message="update_fw: Validate touchpad FW hashes before updating Make use of the generated touchpad firmware hashes to validate the blocks before writing them to the touchpad. BRANCH=none BUG=b:63993173 TEST=make TOUCHPAD_FW=SA459C-1211_ForGoogleHammer_3.0.bin \ BOARD=hammer -j TEST=./usb_updater2 -p SA459C-1211_ForGoogleHammer_3.0.bin works TEST=./usb_updater2 -p SA459C-1211_ForGoogleHammer_4.0.bin fails Change-Id: If5d2be57b63e16ee81aa9acaf840c5084f9b92de Signed-off-by: Nicolas Boichat <drinkcat@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/616371 Reviewed-by: Vincent Palatin <vpalatin@chromium.org> " fail_count="0" gerrit_number="616371" owner_email="drinkcat@chromium.org" pass_count="0" patch_number="12" project="chromiumos/platform/ec" project_url="https://chromium-review.googlesource.com/chromiumos/platform/ec" ref="refs/changes/71/616371/12" remote="cros" total_fail_count="0"/><pending_commit branch="master" change_id="If718d3f762718b05333610e0b18ce46ae11197f1" commit="4c4f8c0e05f7ad93201e5aea1e8543f1b6e15e0b" commit_message="intel: ipu3: Add error handling when poll SOF timeout [Issue] When resuming from S3 state, sometimes poll SOF timeout. [Root Cause] There is no error handling when polling timeout. [Changes] Poll SOF event again when polling timeout. BUG=b:62358788 TEST=Camera preview/capture/video recording work well Change-Id: If718d3f762718b05333610e0b18ce46ae11197f1 Signed-off-by: Qingwu Zhang <qingwu.zhang@intel.com> Reviewed-on: https://chromium-review.googlesource.com/665517 Commit-Ready: WeiX Meng <weix.meng@intel.com> Tested-by: WeiX Meng <weix.meng@intel.com> Reviewed-by: Ricky Liang <jcliang@chromium.org> " fail_count="0" gerrit_number="665517" owner_email="weix.meng@intel.com" pass_count="0" patch_number="1" project="chromiumos/platform/arc-camera" project_url="https://chromium-review.googlesource.com/chromiumos/platform/arc-camera" ref="refs/changes/17/665517/1" remote="cros" total_fail_count="0"/><pending_commit branch="master" change_id="I0583f084739c3c938543bb01bf6f45b6ffed3543" commit="ead1817c8fd371652af35196bf79a52d7f226ce3" commit_message="intel: ipu3: Get the bus address of element dynamically Acquire the bus addr when parsing xml file, which might be dynamically changed. BUG=b:65449138 TEST=Build and deploy package to poppy and camera works Change-Id: I0583f084739c3c938543bb01bf6f45b6ffed3543 Signed-off-by: caoxi <xi.cao@intel.com> Reviewed-on: https://chromium-review.googlesource.com/666151 Commit-Ready: WeiX Meng <weix.meng@intel.com> Tested-by: WeiX Meng <weix.meng@intel.com> Reviewed-by: Ricky Liang <jcliang@chromium.org> " fail_count="0" gerrit_number="666151" owner_email="weix.meng@intel.com" pass_count="0" patch_number="1" project="chromiumos/platform/arc-camera" project_url="https://chromium-review.googlesource.com/chromiumos/platform/arc-camera" ref="refs/changes/51/666151/1" remote="cros" total_fail_count="0"/><pending_commit branch="master" change_id="I0c70d0ded77f41c5cd51c723073620922958992d" commit="dba5b49bbf97d7bb27e974b928cb54ceca0de393" commit_message="update_chroot: get pkg list from cros_setup_toolchains Rather than hardcode the list of packages here, get the list from cros_setup_toolchains and its new config option. BUG=chromium:751852 TEST=precqs pass CQ-DEPEND=CL:664840 Change-Id: I0c70d0ded77f41c5cd51c723073620922958992d Reviewed-on: https://chromium-review.googlesource.com/665058 Commit-Ready: Mike Frysinger <vapier@chromium.org> Tested-by: Mike Frysinger <vapier@chromium.org> Reviewed-by: Manoj Gupta <manojgupta@chromium.org> " fail_count="1" gerrit_number="665058" owner_email="vapier@chromium.org" pass_count="0" patch_number="2" project="chromiumos/platform/crosutils" project_url="https://chromium-review.googlesource.com/chromiumos/platform/crosutils" ref="refs/changes/58/665058/2" remote="cros" total_fail_count="1"/><pending_commit branch="master" change_id="I016044ce8ca3d16b4f9419808c1c5d9c0e4b6859" commit="925eb003fa7ca0821c32500c1327c2a52e259f3d" commit_message="chromeos-base/vpd: Prevent putting static 'vpd' to release images. The `vpd` program is also producing both dynamic and static (vpd_s) version, and the static version should be only needed by auto update and firmware updater, not release images. BUG=None TEST=emerge-reef vpd Change-Id: I016044ce8ca3d16b4f9419808c1c5d9c0e4b6859 Reviewed-on: https://chromium-review.googlesource.com/668269 Commit-Ready: Hung-Te Lin <hungte@chromium.org> Tested-by: Hung-Te Lin <hungte@chromium.org> Reviewed-by: Mike Frysinger <vapier@chromium.org> " fail_count="0" gerrit_number="668269" owner_email="hungte@chromium.org" pass_count="0" patch_number="1" project="chromiumos/overlays/chromiumos-overlay" project_url="https://chromium-review.googlesource.com/chromiumos/overlays/chromiumos-overlay" ref="refs/changes/69/668269/1" remote="cros" total_fail_count="0"/><pending_commit branch="master" change_id="I108e8c6bb9eb727c41f3e1c607f0919fa1192d5a" commit="2bd35c81446f1a10f89f400241ccef9890053daf" commit_message="g: fix short packets on USB control endpoint In the USB 2.0 specification, the "8.5.3 Control Transfers" chapter says that "When all of the data structure is returned to the host, the function should indicate that the Data stage is ended by returning a packet that is shorter than the MaxPacketSize for the pipe. If the data structure is an exact multiple of wMaxPacketSize for the pipe, the function will return a zero-length packet to indicate the end of the Data stage." When doing a 'Control Read' transfer and the returned data (in IN packets) was a multiple of MaxPacketSize, we were omitting the zero-length packet and so the host was blocked waiting for a successful IN transaction. This corner-case was a regression introduced by the re-writing of the control transfer handling done by CL 318864. So the STM32 USB code which is similar to the former code is dealing properly with this case. Signed-off-by: Vincent Palatin <vpalatin@chromium.org> BRANCH=cr50 BUG=none TEST=manual, extend the configuration descriptor to be exactly 64 bytes, and see the enumeration is no longer failing. Change-Id: I108e8c6bb9eb727c41f3e1c607f0919fa1192d5a Reviewed-on: https://chromium-review.googlesource.com/664814 Commit-Ready: Vincent Palatin <vpalatin@chromium.org> Tested-by: Vincent Palatin <vpalatin@chromium.org> Reviewed-by: Marius Schilder <mschilder@chromium.org> Reviewed-by: Vadim Bendebury <vbendeb@chromium.org> Reviewed-by: Shawn N <shawnn@chromium.org> " fail_count="0" gerrit_number="664814" owner_email="vpalatin@chromium.org" pass_count="0" patch_number="2" project="chromiumos/platform/ec" project_url="https://chromium-review.googlesource.com/chromiumos/platform/ec" ref="refs/changes/14/664814/2" remote="cros" total_fail_count="0"/><pending_commit branch="master" change_id="I884a3c354dc3324c2b2b927ad1628d490705a403" commit="3d61e397a3597843194a7f1d79f7899114e074c9" commit_message="camera3-usb-hal: fix buffer overflow Fix metadata handler's buffer overflow. BUG=b:65565460 TEST='USE="asan -cros-debug" FEATURES='nostrip noclean' emerge-reef arc-camera3-test' 'arc-camera3-test Change-Id: I884a3c354dc3324c2b2b927ad1628d490705a403 Reviewed-on: https://chromium-review.googlesource.com/662005 Commit-Ready: Hsincheng Hou <dihimono@google.com> Tested-by: Hsincheng Hou <dihimono@google.com> Reviewed-by: Heng-ruey Hsu <henryhsu@chromium.org> " fail_count="0" gerrit_number="662005" owner_email="dihimono@google.com" pass_count="0" patch_number="1" project="chromiumos/platform/arc-camera" project_url="https://chromium-review.googlesource.com/chromiumos/platform/arc-camera" ref="refs/changes/05/662005/1" remote="cros" total_fail_count="0"/><pending_commit branch="master" change_id="Ia54472b80efd8c3fa7695d42df10027e1470105f" commit="0f9e14b2f537217ddb30004359e8abc545e20512" commit_message="setup_board: automatically include sdk toolchain packages in host boards Rather than requiring the list of toolchain packages that we are managing by hand be listed in the virtual/target-sdk tree, pull in the list when we are creating a new host board from scratch. This shouldn't currently be functionally different, but should smooth over future changes since there will be only one place to maintain this list. BUG=chromium:751852 TEST=precqs pass CQ-DEPEND=CL:664840 Change-Id: Ia54472b80efd8c3fa7695d42df10027e1470105f Reviewed-on: https://chromium-review.googlesource.com/666297 Commit-Ready: Mike Frysinger <vapier@chromium.org> Tested-by: Mike Frysinger <vapier@chromium.org> Reviewed-by: Manoj Gupta <manojgupta@chromium.org> " fail_count="3" gerrit_number="666297" owner_email="vapier@chromium.org" pass_count="0" patch_number="1" project="chromiumos/platform/crosutils" project_url="https://chromium-review.googlesource.com/chromiumos/platform/crosutils" ref="refs/changes/97/666297/1" remote="cros" total_fail_count="3"/><lkgm version="9943.0.0-rc2"/></manifest> |
