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| <pending_commit branch="chromeos-2016.05" change_id="Iec5e654e55fa0644f384de13a291aa094be157f5" commit="8969436ee50ad1e818352ad38e2be0074bd0891b" commit_message="UPSTREAM: mb/google/poppy/variants/nami: Use GPP_B4 as Touchscreen Power Enable Touchscreen power enable for Nami has moved from GBB_C22 to GPP_B4 in the latest schematics. BUG=b:74347464 BRANCH=None TEST=./util/abuild/abuild -p none -t google/poppy -x -a Change-Id: Iec5e654e55fa0644f384de13a291aa094be157f5 Signed-off-by: Furquan Shaikh <furquan@google.com> Original-Commit-Id: 6a0eafefc41602c98ab7607a8684709c23062a02 Original-Change-Id: I3b1794d44f25c0d42d082d63b9e3ec3dfcef7528 Original-Signed-off-by: Shelley Chen <shchen@chromium.org> Original-Reviewed-on: https://review.coreboot.org/25154 Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> Original-Reviewed-by: Furquan Shaikh <furquan@google.com> Original-Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-on: https://chromium-review.googlesource.com/967874 Commit-Ready: Furquan Shaikh <furquan@chromium.org> Tested-by: Furquan Shaikh <furquan@chromium.org> Reviewed-by: Furquan Shaikh <furquan@chromium.org> " fail_count="0" gerrit_number="967874" owner_email="furquan@chromium.org" pass_count="0" patch_number="1" project="chromiumos/third_party/coreboot" project_url="https://chromium-review.googlesource.com/chromiumos/third_party/coreboot" ref="refs/changes/74/967874/1" remote="cros" total_fail_count="0"/><pending_commit branch="chromeos-2016.05" change_id="Ib7a519073dce330ffebe86c16ac750aaee93e925" commit="58c6b8c3bc6b58736643ea8671c3a96730921f2d" commit_message="UPSTREAM: mb/google/poppy/variants/nami: Add gpio-keys ACPI node for PENH Use gpio_keys driver to add ACPI node for pen eject event. Also setting gpio wake pin for wake events. BUG=b:73121017 BRANCH=None TEST=./util/abuild/abuild -p none -t google/poppy -x -a Change-Id: Ib7a519073dce330ffebe86c16ac750aaee93e925 Signed-off-by: Furquan Shaikh <furquan@google.com> Original-Commit-Id: 4e0b47a5ed4c305ff158e8264a60e78e1775ea56 Original-Change-Id: I5d87d938ac3a4e52e676850b9d8b80e83726275d Original-Signed-off-by: Shelley Chen <shchen@chromium.org> Original-Reviewed-on: https://review.coreboot.org/25162 Original-Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Original-Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-on: https://chromium-review.googlesource.com/967875 Commit-Ready: Furquan Shaikh <furquan@chromium.org> Tested-by: Furquan Shaikh <furquan@chromium.org> Reviewed-by: Furquan Shaikh <furquan@chromium.org> " fail_count="0" gerrit_number="967875" owner_email="furquan@chromium.org" pass_count="0" patch_number="1" project="chromiumos/third_party/coreboot" project_url="https://chromium-review.googlesource.com/chromiumos/third_party/coreboot" ref="refs/changes/75/967875/1" remote="cros" total_fail_count="0"/><pending_commit branch="chromeos-2016.05" change_id="Iba2a49564b46c937b7a2f1107f02b8bbb57c6c40" commit="68fbb615dd6a4a6f2c1283b385b04a3a2bdcbc61" commit_message="UPSTREAM: soc/intel/apollolake and mainboards: Use pcie_rp_clkreq_pin array This change uses an array pcie_rp_clkreq_pin for accepting CLKREQ# from mainboards instead of defining a separate property for each root port. This allows us to use memcpy to copy the entire array into FSP params as well as new properties for PCIe root ports can be added as arrays in future CLs. BUG=b:74633273 BRANCH=reef,coral Change-Id: Iba2a49564b46c937b7a2f1107f02b8bbb57c6c40 Signed-off-by: Furquan Shaikh <furquan@google.com> Original-Commit-Id: 6d5e10c05d99c475e63bbe95012066f9c585cfb3 Original-Change-Id: Ifa05f1e38fcfd95063ec327712e472cdbd12dbb7 Original-Signed-off-by: Furquan Shaikh <furquan@google.com> Original-Reviewed-on: https://review.coreboot.org/25186 Original-Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/967876 Commit-Ready: Furquan Shaikh <furquan@chromium.org> Tested-by: Furquan Shaikh <furquan@chromium.org> Reviewed-by: Furquan Shaikh <furquan@chromium.org> " fail_count="0" gerrit_number="967876" owner_email="furquan@chromium.org" pass_count="0" patch_number="1" project="chromiumos/third_party/coreboot" project_url="https://chromium-review.googlesource.com/chromiumos/third_party/coreboot" ref="refs/changes/76/967876/1" remote="cros" total_fail_count="0"/><pending_commit branch="chromeos-2016.05" change_id="I2fd6159fc697792daa82f16fab0d7865b2a49043" commit="c22ef61df87923a255a0bbd813926dce49125a9b" commit_message="UPSTREAM: soc/intel/apollolake: Add config option for enabling hotplug PcieRpHotPlug in apollolake UPD is default enabled. This change adds a config option to enable hotplug only if explicitly requested by mainboard. This changes the default behavior on all apollolake boards to have hotplug disabled. BUG=b:74633273 BRANCH=reef,coral Change-Id: I2fd6159fc697792daa82f16fab0d7865b2a49043 Signed-off-by: Furquan Shaikh <furquan@google.com> Original-Commit-Id: 2cfc862a3e4769ea94c23a109f1ca82dfbc47f1b Original-Change-Id: I572c054d31aaf5d43a79c4b1773ec9356da48d9d Original-Signed-off-by: Furquan Shaikh <furquan@google.com> Original-Reviewed-on: https://review.coreboot.org/25187 Original-Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/967877 Commit-Ready: Furquan Shaikh <furquan@chromium.org> Tested-by: Furquan Shaikh <furquan@chromium.org> Reviewed-by: Furquan Shaikh <furquan@chromium.org> " fail_count="0" gerrit_number="967877" owner_email="furquan@chromium.org" pass_count="0" patch_number="1" project="chromiumos/third_party/coreboot" project_url="https://chromium-review.googlesource.com/chromiumos/third_party/coreboot" ref="refs/changes/77/967877/1" remote="cros" total_fail_count="0"/><pending_commit branch="chromeos-2016.05" change_id="I83eda0635977609f2a1fb11f46febecfbf41118c" commit="41245fc03aa1913f8966b02c8f5fbea522bee134" commit_message="UPSTREAM: soc/intel/apollolake: handle different memory profiles for apl and glk glk has different memory profile values than apl. Therefore, a translation is required to correctly set the proper profile value depending on what SoC (and therefore FSP) is being used. Based on SOC_INTEL_GLK Kconfig value use different profiles. BUG=b:74932341 Change-Id: I83eda0635977609f2a1fb11f46febecfbf41118c Signed-off-by: Furquan Shaikh <furquan@google.com> Original-Commit-Id: fd228e979c37b66111ba1405875b08182c8d993d Original-Change-Id: I6ea84d3339caf666aea5034ab8f0287bd1915e06 Original-Signed-off-by: Aaron Durbin <adurbin@chromium.org> Original-Reviewed-on: https://review.coreboot.org/25249 Original-Reviewed-by: Justin TerAvest <teravest@chromium.org> Original-Reviewed-by: Furquan Shaikh <furquan@google.com> Original-Reviewed-by: Sumeet R Pawnikar <sumeet.r.pawnikar@intel.com> Original-Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-on: https://chromium-review.googlesource.com/967878 Commit-Ready: Furquan Shaikh <furquan@chromium.org> Tested-by: Furquan Shaikh <furquan@chromium.org> Reviewed-by: Furquan Shaikh <furquan@chromium.org> " fail_count="0" gerrit_number="967878" owner_email="furquan@chromium.org" pass_count="0" patch_number="1" project="chromiumos/third_party/coreboot" project_url="https://chromium-review.googlesource.com/chromiumos/third_party/coreboot" ref="refs/changes/78/967878/1" remote="cros" total_fail_count="0"/><pending_commit branch="chromeos-2016.05" change_id="I59d1c7675045d5c8d583afb5b38bc9543c4846f6" commit="fa2813d6faef5e41d67456939a864f469adaf853" commit_message="UPSTREAM: mb/google/octopus: Do not configure GPIO_149 as GPO GPIO_149 is used as ESPI clock feedback and configuring it as a GPO results in EC communication failure. This change removes the configuration of GPIO_149 as GPO in ramstage so that it remains configured for ESPI (as it was when AP came out of reset). BUG=b:75348718 Change-Id: I59d1c7675045d5c8d583afb5b38bc9543c4846f6 Signed-off-by: Furquan Shaikh <furquan@google.com> Original-Commit-Id: 6bff3bf4be7fd94e6ffd080e498bbe75c75418d9 Original-Change-Id: Ie4f21b12fae027cdba54ce147e6d1a88ee854792 Original-Signed-off-by: Furquan Shaikh <furquan@google.com> Original-Reviewed-on: https://review.coreboot.org/25259 Original-Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Original-Reviewed-by: Justin TerAvest <teravest@chromium.org> Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/967879 Commit-Ready: Furquan Shaikh <furquan@chromium.org> Tested-by: Furquan Shaikh <furquan@chromium.org> Reviewed-by: Furquan Shaikh <furquan@chromium.org> " fail_count="0" gerrit_number="967879" owner_email="furquan@chromium.org" pass_count="0" patch_number="1" project="chromiumos/third_party/coreboot" project_url="https://chromium-review.googlesource.com/chromiumos/third_party/coreboot" ref="refs/changes/79/967879/1" remote="cros" total_fail_count="0"/><pending_commit branch="master" change_id="I9c9d6af93bf5b4b565ca34b68b963225b137a55b" commit="a50ba824e22c4d44b943447f232aae0a294e0bc0" commit_message="cryptohome: Add README for LE Credentials BUG=chromium:794010 TEST=None Change-Id: I9c9d6af93bf5b4b565ca34b68b963225b137a55b Reviewed-on: https://chromium-review.googlesource.com/961723 Commit-Ready: Prashant Malani <pmalani@google.com> Tested-by: Prashant Malani <pmalani@google.com> Reviewed-by: Andrey Pronin <apronin@chromium.org> " fail_count="0" gerrit_number="961723" owner_email="pmalani@google.com" pass_count="0" patch_number="7" project="chromiumos/platform2" project_url="https://chromium-review.googlesource.com/chromiumos/platform2" ref="refs/changes/23/961723/7" remote="cros" total_fail_count="0"/><lkgm version="10498.0.0-rc1"/></manifest> |
