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| <pending_commit branch="chromeos-2016.05" change_id="Ie93e91f8c477cefdb4dc5dd11e45361fd71ec76c" commit="bec51cd0210d3bb37273a9eff810c046b98195b6" commit_message="UPSTREAM: libpayload: Add UNKNOWN_SPEED to usb_speed enum xhci_rh_port_speed return -1 if the port is disabled. The usb_speed enum is unsigned so this results in a positive value which implies success. Adding a -1 to the enum will make it signed so the >= 0 check will work correctly. BUG=b:76831439 TEST=verified on grunt that -1 is returned when port is disabled. Change-Id: Ie93e91f8c477cefdb4dc5dd11e45361fd71ec76c Signed-off-by: Patrick Georgi <pgeorgi@google.com> Original-Commit-Id: c534a066d8808e97eee9ccd2ac2bc936961a129b Original-Change-Id: I98a373717d52dfb6ca4dcc53a00dc1b4c240a919 Original-Signed-off-by: Raul E Rangel <rrangel@chromium.org> Original-Reviewed-on: https://review.coreboot.org/27476 Original-Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Original-Reviewed-by: Julius Werner <jwerner@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/1143194 Commit-Ready: Patrick Georgi <pgeorgi@chromium.org> Tested-by: Patrick Georgi <pgeorgi@chromium.org> Reviewed-by: Patrick Georgi <pgeorgi@chromium.org> " fail_count="1" gerrit_number="1143194" owner_email="pgeorgi@chromium.org" pass_count="0" patch_number="1" project="chromiumos/third_party/coreboot" project_url="https://chromium-review.googlesource.com/chromiumos/third_party/coreboot" ref="refs/changes/94/1143194/1" remote="cros" total_fail_count="1"/><pending_commit branch="chromeos-2016.05" change_id="Idf3cfcc1db3cc5b8f4968fcb26fd820e08c9b844" commit="bf80d25813a438b33a5a376dd18179445e057e93" commit_message="UPSTREAM: libpayload/xhci: Check noop return code when debugging Make it obvious that the command has failed. BUG=b:76831439 TEST=Verified on grunt Change-Id: Idf3cfcc1db3cc5b8f4968fcb26fd820e08c9b844 Signed-off-by: Patrick Georgi <pgeorgi@google.com> Original-Commit-Id: d29c81d51314806f17e0b49cb57f0d620bde783c Original-Change-Id: Ifa0b2fb087f5f0a36ba017a774fc98b33ab035a4 Original-Signed-off-by: Raul E Rangel <rrangel@chromium.org> Original-Reviewed-on: https://review.coreboot.org/27478 Original-Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Original-Reviewed-by: Julius Werner <jwerner@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/1143195 Commit-Ready: Patrick Georgi <pgeorgi@chromium.org> Tested-by: Patrick Georgi <pgeorgi@chromium.org> Reviewed-by: Patrick Georgi <pgeorgi@chromium.org> " fail_count="1" gerrit_number="1143195" owner_email="pgeorgi@chromium.org" pass_count="0" patch_number="1" project="chromiumos/third_party/coreboot" project_url="https://chromium-review.googlesource.com/chromiumos/third_party/coreboot" ref="refs/changes/95/1143195/1" remote="cros" total_fail_count="1"/><pending_commit branch="chromeos-2016.05" change_id="Ifb5b1d6379c017527e0222dfc7373176bccf4ba1" commit="afef30e0da92294cf27d3e46ea0e291be4e0a05b" commit_message="UPSTREAM: security/vboot: Add interface for FSP 2.0 mrc caching * Move vboot/tpm specific implementation to vboot. * Only call functions if CONFIG_FSP2_0_USES_TPM_MRC_HASH is set. * Preparation for software hash function support, no logic changed. BUG=none BRANCH=none TEST=none Change-Id: Ifb5b1d6379c017527e0222dfc7373176bccf4ba1 Signed-off-by: Patrick Georgi <pgeorgi@google.com> Original-Commit-Id: 80961af4b6888ff31aacaae0753969db4a8fb734 Original-Change-Id: I41a458186c7981adaf3fea8974adec2ca8668f14 Original-Signed-off-by: Philipp Deppenwiese <zaolin@das-labor.org> Original-Reviewed-on: https://review.coreboot.org/24904 Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> Original-Reviewed-by: Philipp Deppenwiese <zaolin.daisuki@gmail.com> Original-Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-on: https://chromium-review.googlesource.com/1143196 Commit-Ready: Patrick Georgi <pgeorgi@chromium.org> Tested-by: Patrick Georgi <pgeorgi@chromium.org> Reviewed-by: Patrick Georgi <pgeorgi@chromium.org> " fail_count="1" gerrit_number="1143196" owner_email="pgeorgi@chromium.org" pass_count="0" patch_number="1" project="chromiumos/third_party/coreboot" project_url="https://chromium-review.googlesource.com/chromiumos/third_party/coreboot" ref="refs/changes/96/1143196/1" remote="cros" total_fail_count="1"/><pending_commit branch="chromeos-2016.05" change_id="I47aa07a95b37853f4d3a3d8268c535ed8aeb2dc9" commit="15cbe6094549b229cc6ffa133c69c7dee7148966" commit_message="UPSTREAM: soc/amd/stoneyridge: Update ACPI external processor name update external processor name to match declaration in SSDT. in SSDT: Processor (\_PR.P000, 0x00, 0x00000410, 0x06) {} Processor (\_PR.P001, 0x01, 0x00000000, 0x00) {} in DSDT: External (_PR_.CP00, UnknownObj) External (_PR_.CP01, UnknownObj) After fix this, ACPI _PSL (Passive List) now can return correct list of processor objects for thermal passive cooling. BUG=b:111478152 BRANCH=master TEST=emerge-grunt coreboot Change-Id: I47aa07a95b37853f4d3a3d8268c535ed8aeb2dc9 Signed-off-by: Patrick Georgi <pgeorgi@google.com> Original-Commit-Id: f17a0df112ec3351a9ea344408a39dc895bf1788 Original-Change-Id: I78c838608c78eb7b5e3f8d5c67589e082c756201 Original-Signed-off-by: Kevin Chiu <Kevin.Chiu@quantatw.com> Original-Reviewed-on: https://review.coreboot.org/27495 Original-Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com> Original-Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Original-Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-on: https://chromium-review.googlesource.com/1143197 Commit-Ready: Patrick Georgi <pgeorgi@chromium.org> Tested-by: Patrick Georgi <pgeorgi@chromium.org> Reviewed-by: Patrick Georgi <pgeorgi@chromium.org> " fail_count="1" gerrit_number="1143197" owner_email="pgeorgi@chromium.org" pass_count="0" patch_number="1" project="chromiumos/third_party/coreboot" project_url="https://chromium-review.googlesource.com/chromiumos/third_party/coreboot" ref="refs/changes/97/1143197/1" remote="cros" total_fail_count="1"/><pending_commit branch="chromeos-2016.05" change_id="I482b49faea46b0bfb03c5f20e59234787e7d0636" commit="86db4dcf33bad007890de99f887364aa2e4306f9" commit_message="UPSTREAM: pnp_device: improve readability Add comments on the ops handling in pnp_enable_devices function and the pnp_info struct. Also remove the negation in the check if an LDN-specific override is used. This patch doesn't change the logic though. BUG=none BRANCH=none TEST=none Change-Id: I482b49faea46b0bfb03c5f20e59234787e7d0636 Signed-off-by: Patrick Georgi <pgeorgi@google.com> Original-Commit-Id: 745e58a5ee50373276924349524a2594599e8bb5 Original-Change-Id: I3e80dbce1f29ee3e95e3b1d71c9b8479561d5c1a Original-Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Original-Reviewed-on: https://review.coreboot.org/27384 Original-Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Original-Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Original-Reviewed-by: Patrick Rudolph <siro@das-labor.org> Reviewed-on: https://chromium-review.googlesource.com/1143198 Commit-Ready: Patrick Georgi <pgeorgi@chromium.org> Tested-by: Patrick Georgi <pgeorgi@chromium.org> Reviewed-by: Patrick Georgi <pgeorgi@chromium.org> " fail_count="1" gerrit_number="1143198" owner_email="pgeorgi@chromium.org" pass_count="0" patch_number="1" project="chromiumos/third_party/coreboot" project_url="https://chromium-review.googlesource.com/chromiumos/third_party/coreboot" ref="refs/changes/98/1143198/1" remote="cros" total_fail_count="1"/><pending_commit branch="chromeos-2016.05" change_id="I54bd82b3f40f2d7885e61b58f8cdf49f51648fea" commit="2bdddd989cc742606dc90e4843143d7ad5f08b25" commit_message="UPSTREAM: riscv: add support for modifying compiler options Each HART of a SoC like fu540 supports a different ISA. In order for the coreboot's code can run on each core, need to modify the compile options. So add this code. BUG=none BRANCH=none TEST=none Change-Id: I54bd82b3f40f2d7885e61b58f8cdf49f51648fea Signed-off-by: Patrick Georgi <pgeorgi@google.com> Original-Commit-Id: 5fed693a52ed9746900ce58ec12a2b245f08202e Original-Change-Id: Ie33edc175e612846d4a74f3cbf7520d4145cb68b Original-Signed-off-by: Xiang Wang <wxjstz@126.com> Original-Reviewed-on: https://review.coreboot.org/27442 Original-Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Original-Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Original-Reviewed-by: Jonathan Neuschfer <j.neuschaefer@gmx.net> Original-Reviewed-by: Philipp Hug <philipp@hug.cx> Reviewed-on: https://chromium-review.googlesource.com/1143199 Commit-Ready: Patrick Georgi <pgeorgi@chromium.org> Tested-by: Patrick Georgi <pgeorgi@chromium.org> Reviewed-by: Patrick Georgi <pgeorgi@chromium.org> " fail_count="1" gerrit_number="1143199" owner_email="pgeorgi@chromium.org" pass_count="0" patch_number="1" project="chromiumos/third_party/coreboot" project_url="https://chromium-review.googlesource.com/chromiumos/third_party/coreboot" ref="refs/changes/99/1143199/1" remote="cros" total_fail_count="1"/><pending_commit branch="chromeos-2016.05" change_id="I7879c65477e21c4ae1c5a2a91b1083b3c4b7b255" commit="b07800a9fe2e754aa7b8ef89cd09e5958d6a99c3" commit_message="UPSTREAM: libpayload/generic_hub: Detect port disconnect after reset If a port disconnects after a reset we should abort any initialization on the port. This might mean the device has re-enumerated as a 3.0 device so the hub should be scanned again. BUG=b:76831439 TEST=Verified USB-C devices that get detected correctly in depthcharge. Change-Id: I7879c65477e21c4ae1c5a2a91b1083b3c4b7b255 Signed-off-by: Patrick Georgi <pgeorgi@google.com> Original-Commit-Id: 1b43ad7149ebae684b0cbd08d293117a7304249d Original-Change-Id: Iad899544684312df1bef08d69b5c7f41eac3a21c Original-Signed-off-by: Raul E Rangel <rrangel@chromium.org> Original-Reviewed-on: https://review.coreboot.org/27477 Original-Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Original-Reviewed-by: Julius Werner <jwerner@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/1143200 Commit-Ready: Patrick Georgi <pgeorgi@chromium.org> Tested-by: Patrick Georgi <pgeorgi@chromium.org> Reviewed-by: Patrick Georgi <pgeorgi@chromium.org> " fail_count="1" gerrit_number="1143200" owner_email="pgeorgi@chromium.org" pass_count="0" patch_number="1" project="chromiumos/third_party/coreboot" project_url="https://chromium-review.googlesource.com/chromiumos/third_party/coreboot" ref="refs/changes/00/1143200/1" remote="cros" total_fail_count="1"/><pending_commit branch="chromeos-2016.05" change_id="Ib3d067145552ebcd4f0f9120d50e31d102bf2760" commit="01115fcd9a6d511de6632a517e106aa2a31ade42" commit_message="UPSTREAM: sifive/fu540: add empty sdram init and size functions BUG=none BRANCH=none TEST=none Change-Id: Ib3d067145552ebcd4f0f9120d50e31d102bf2760 Signed-off-by: Patrick Georgi <pgeorgi@google.com> Original-Commit-Id: 52a022f680e9f59fbb4991109c2435f017c4f6c9 Original-Change-Id: I65f900a3277bc8a4a83ebc8883d4a325bd690bf8 Original-Signed-off-by: Philipp Hug <philipp@hug.cx> Original-Reviewed-on: https://review.coreboot.org/27438 Original-Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Original-Reviewed-by: Ronald G. Minnich <rminnich@gmail.com> Reviewed-on: https://chromium-review.googlesource.com/1143201 Commit-Ready: Patrick Georgi <pgeorgi@chromium.org> Tested-by: Patrick Georgi <pgeorgi@chromium.org> Reviewed-by: Patrick Georgi <pgeorgi@chromium.org> " fail_count="1" gerrit_number="1143201" owner_email="pgeorgi@chromium.org" pass_count="0" patch_number="1" project="chromiumos/third_party/coreboot" project_url="https://chromium-review.googlesource.com/chromiumos/third_party/coreboot" ref="refs/changes/01/1143201/1" remote="cros" total_fail_count="1"/><pending_commit branch="chromeos-2016.05" change_id="I30d35c10f439b64ccf6c10dd7fb62a0f5379e115" commit="a510a7bf634510af57bfaa22d18a2c545bbc50b0" commit_message="UPSTREAM: soc/intel/common/block: Add WhiskeyLake W0 CPUID TEST=Boot up with W0 stepping processor. Change-Id: I30d35c10f439b64ccf6c10dd7fb62a0f5379e115 Signed-off-by: Patrick Georgi <pgeorgi@google.com> Original-Commit-Id: cdeb41482a160606dd314e5628a3bae9e1d644b1 Original-Change-Id: Ia7bcfd5235e57c70aa3f15d0042da8b16cf7e186 Original-Signed-off-by: Krzysztof Sywula <krzysztof.m.sywula@intel.com> Original-Reviewed-on: https://review.coreboot.org/27500 Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> Original-Reviewed-by: Lijian Zhao <lijian.zhao@intel.com> Original-Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-on: https://chromium-review.googlesource.com/1143202 Commit-Ready: Patrick Georgi <pgeorgi@chromium.org> Tested-by: Patrick Georgi <pgeorgi@chromium.org> Reviewed-by: Patrick Georgi <pgeorgi@chromium.org> " fail_count="1" gerrit_number="1143202" owner_email="pgeorgi@chromium.org" pass_count="0" patch_number="1" project="chromiumos/third_party/coreboot" project_url="https://chromium-review.googlesource.com/chromiumos/third_party/coreboot" ref="refs/changes/02/1143202/1" remote="cros" total_fail_count="1"/><pending_commit branch="chromeos-2016.05" change_id="I3902bdc46c6a45e8f79a3b8e1a3fabc8ec1361db" commit="eef7a5b46a5d11a2bbcc7aeb027af44b797f5838" commit_message="UPSTREAM: mb/lenovo/x201: Add data.vbt file Extracted from live running Thinkpad X201 with vendor firmware. BUG=none BRANCH=none TEST=none Change-Id: I3902bdc46c6a45e8f79a3b8e1a3fabc8ec1361db Signed-off-by: Patrick Georgi <pgeorgi@google.com> Original-Commit-Id: ad417c9c7b20529d20a72c81b225c29953439acc Original-Change-Id: Ia33b4c1a2af6f7d460375cc8ea4e404963a72244 Original-Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Original-Reviewed-on: https://review.coreboot.org/27502 Original-Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Original-Reviewed-by: Patrick Rudolph <siro@das-labor.org> Original-Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-on: https://chromium-review.googlesource.com/1143203 Commit-Ready: Patrick Georgi <pgeorgi@chromium.org> Tested-by: Patrick Georgi <pgeorgi@chromium.org> Reviewed-by: Patrick Georgi <pgeorgi@chromium.org> " fail_count="1" gerrit_number="1143203" owner_email="pgeorgi@chromium.org" pass_count="0" patch_number="1" project="chromiumos/third_party/coreboot" project_url="https://chromium-review.googlesource.com/chromiumos/third_party/coreboot" ref="refs/changes/03/1143203/1" remote="cros" total_fail_count="1"/><pending_commit branch="chromeos-2016.05" change_id="Id342c7434a6c91ceac3d8a364b3cbd21fee85f57" commit="17fd545878c8f8df2b77eaeba93da1f8877481ee" commit_message="UPSTREAM: superio/nuvoton: remove LDN-specific ops overrides The pnp ops struct is already passed to the pnp_enable_devices function and it is used if no override is supplied in the elements of the pnp_info struct array BUG=none BRANCH=none TEST=none Change-Id: Id342c7434a6c91ceac3d8a364b3cbd21fee85f57 Signed-off-by: Patrick Georgi <pgeorgi@google.com> Original-Commit-Id: 9911d64b9edb8c055b37b0635e97b4c585aa4ae1 Original-Change-Id: I18345d7cc50a7d46cb15584dfb54df28e8534f81 Original-Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Original-Reviewed-on: https://review.coreboot.org/27386 Original-Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Original-Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Original-Reviewed-by: Patrick Rudolph <siro@das-labor.org> Reviewed-on: https://chromium-review.googlesource.com/1143244 Commit-Ready: Patrick Georgi <pgeorgi@chromium.org> Tested-by: Patrick Georgi <pgeorgi@chromium.org> Reviewed-by: Patrick Georgi <pgeorgi@chromium.org> " fail_count="1" gerrit_number="1143244" owner_email="pgeorgi@chromium.org" pass_count="0" patch_number="1" project="chromiumos/third_party/coreboot" project_url="https://chromium-review.googlesource.com/chromiumos/third_party/coreboot" ref="refs/changes/44/1143244/1" remote="cros" total_fail_count="1"/><pending_commit branch="chromeos-2016.05" change_id="I0fd8874f740f8b1cfdc96c7ef1c1a417fa5c98f7" commit="c8ce21060295331e99a4201c25c1e81311583a9f" commit_message="UPSTREAM: what-jenkins-does: Pass V=1 through to abuild Even though we were setting V=1 in the build, this wasn't getting passed to abuild, so the builds there didn't have additional debug information. That made it difficult to debug issues on the builder. This sets the verbose flag for abuild if V=1 is set. BUG=none BRANCH=none TEST=none Change-Id: I0fd8874f740f8b1cfdc96c7ef1c1a417fa5c98f7 Signed-off-by: Patrick Georgi <pgeorgi@google.com> Original-Commit-Id: 6d4a060bba907ca29b2c69fda9a4ae3e3c73fc44 Original-Change-Id: Id9ec50add9693a6c36ffdb5c78d148d0fc012549 Original-Signed-off-by: Martin Roth <gaumless@gmail.com> Original-Reviewed-on: https://review.coreboot.org/27492 Original-Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Original-Reviewed-by: Patrick Georgi <pgeorgi@google.com> Reviewed-on: https://chromium-review.googlesource.com/1143245 Commit-Ready: Patrick Georgi <pgeorgi@chromium.org> Tested-by: Patrick Georgi <pgeorgi@chromium.org> Reviewed-by: Patrick Georgi <pgeorgi@chromium.org> " fail_count="1" gerrit_number="1143245" owner_email="pgeorgi@chromium.org" pass_count="0" patch_number="1" project="chromiumos/third_party/coreboot" project_url="https://chromium-review.googlesource.com/chromiumos/third_party/coreboot" ref="refs/changes/45/1143245/1" remote="cros" total_fail_count="1"/><pending_commit branch="chromeos-2016.05" change_id="I22d3b9e01b7f5a72c3511bc392a2cb3269c1f18c" commit="ae5ea42cf9e1246f822dcbff322d07a9953eb962" commit_message="UPSTREAM: security/vboot: fix typo BUG=none TEST=none Change-Id: I22d3b9e01b7f5a72c3511bc392a2cb3269c1f18c Signed-off-by: Patrick Georgi <pgeorgi@google.com> Original-Commit-Id: 3a59174cf02c8c0afd8eb547f5325788cd3537ea Original-Change-Id: I7027abee66ccdf9b2d37df60ca7f4dbbbae2f9e4 Original-Signed-off-by: Raul E Rangel <rrangel@chromium.org> Original-Reviewed-on: https://review.coreboot.org/27517 Original-Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Original-Reviewed-by: Furquan Shaikh <furquan@google.com> Original-Reviewed-by: Martin Roth <martinroth@google.com> Original-Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-on: https://chromium-review.googlesource.com/1143246 Commit-Ready: Patrick Georgi <pgeorgi@chromium.org> Tested-by: Patrick Georgi <pgeorgi@chromium.org> Reviewed-by: Patrick Georgi <pgeorgi@chromium.org> " fail_count="1" gerrit_number="1143246" owner_email="pgeorgi@chromium.org" pass_count="0" patch_number="1" project="chromiumos/third_party/coreboot" project_url="https://chromium-review.googlesource.com/chromiumos/third_party/coreboot" ref="refs/changes/46/1143246/1" remote="cros" total_fail_count="1"/><pending_commit branch="chromeos-2016.05" change_id="Ibe2e8c957e547e3cd24784b8fb0e49d8f04311eb" commit="68371b2b43d6ff4f4aaf8ec872c66515a98f047e" commit_message="UPSTREAM: superio/ite: pass the chip-specific ops struct to pnp_enable_devices Pass the address of the chip-specific ops struct instead of the one of the generic pnp_ops struct to the PNP device enable function. This allows the removal of the LDN-specific ops overrides which is also done in this patch. BUG=none BRANCH=none TEST=none Change-Id: Ibe2e8c957e547e3cd24784b8fb0e49d8f04311eb Signed-off-by: Patrick Georgi <pgeorgi@google.com> Original-Commit-Id: c40275bce0efb8b79792c7a6f846204b4c317124 Original-Change-Id: I5f03a4064778c419f4b9c50e70db1296addf6c9e Original-Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Original-Reviewed-on: https://review.coreboot.org/23006 Original-Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Original-Reviewed-by: Martin Roth <martinroth@google.com> Reviewed-on: https://chromium-review.googlesource.com/1143247 Commit-Ready: Patrick Georgi <pgeorgi@chromium.org> Tested-by: Patrick Georgi <pgeorgi@chromium.org> Reviewed-by: Patrick Georgi <pgeorgi@chromium.org> " fail_count="1" gerrit_number="1143247" owner_email="pgeorgi@chromium.org" pass_count="0" patch_number="1" project="chromiumos/third_party/coreboot" project_url="https://chromium-review.googlesource.com/chromiumos/third_party/coreboot" ref="refs/changes/47/1143247/1" remote="cros" total_fail_count="1"/><pending_commit branch="chromeos-2016.05" change_id="I1bc7f701f42871cc8002e89521089b4ab575fdfa" commit="d47fc80e9fe5a383e679dacf470cd74716e4be95" commit_message="UPSTREAM: superio/smsc: pass the chip-specific ops struct to pnp_enable_devices Pass the address of the chip-specific ops struct instead of the one of the generic pnp_ops struct to the PNP device enable function. This allows the removal of the LDN-specific ops overrides which is also done in this patch. BUG=none BRANCH=none TEST=none Change-Id: I1bc7f701f42871cc8002e89521089b4ab575fdfa Signed-off-by: Patrick Georgi <pgeorgi@google.com> Original-Commit-Id: b0d868e8fe3f9a13f9be109fc3b73dfa949bec15 Original-Change-Id: I16e485494e448ae02e0a7b9e21b90ddbb1a53a4b Original-Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Original-Reviewed-on: https://review.coreboot.org/23007 Original-Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Original-Reviewed-by: Martin Roth <martinroth@google.com> Reviewed-on: https://chromium-review.googlesource.com/1143248 Commit-Ready: Patrick Georgi <pgeorgi@chromium.org> Tested-by: Patrick Georgi <pgeorgi@chromium.org> Reviewed-by: Patrick Georgi <pgeorgi@chromium.org> " fail_count="1" gerrit_number="1143248" owner_email="pgeorgi@chromium.org" pass_count="0" patch_number="1" project="chromiumos/third_party/coreboot" project_url="https://chromium-review.googlesource.com/chromiumos/third_party/coreboot" ref="refs/changes/48/1143248/1" remote="cros" total_fail_count="1"/><pending_commit branch="chromeos-2016.05" change_id="I8f85af67818b37b11a9a58c347977e3fec5b8af7" commit="13313391d16e5a7cc33264bf393ce51817cf33cb" commit_message="UPSTREAM: superio/nsc: pass the chip-specific ops struct to pnp_enable_devices Pass the address of the chip-specific ops struct instead of the one of the generic pnp_ops struct to the PNP device enable function. This allows the removal of the LDN-specific ops overrides which is also done in this patch. BUG=none BRANCH=none TEST=none Change-Id: I8f85af67818b37b11a9a58c347977e3fec5b8af7 Signed-off-by: Patrick Georgi <pgeorgi@google.com> Original-Commit-Id: faca0bc2fa5a347a98fc3ee8dd1a5dd9c9763459 Original-Change-Id: I0c820254e97e3f80470d148552af06940e147b74 Original-Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Original-Reviewed-on: https://review.coreboot.org/23008 Original-Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Original-Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://chromium-review.googlesource.com/1143249 Commit-Ready: Patrick Georgi <pgeorgi@chromium.org> Tested-by: Patrick Georgi <pgeorgi@chromium.org> Reviewed-by: Patrick Georgi <pgeorgi@chromium.org> " fail_count="1" gerrit_number="1143249" owner_email="pgeorgi@chromium.org" pass_count="0" patch_number="1" project="chromiumos/third_party/coreboot" project_url="https://chromium-review.googlesource.com/chromiumos/third_party/coreboot" ref="refs/changes/49/1143249/1" remote="cros" total_fail_count="1"/><pending_commit branch="chromeos-2016.05" change_id="Icdc2123678b4e68fe316358546bf763f98049521" commit="86c5a079446f2ecdfc68c8883df4ff7ac159efab" commit_message="UPSTREAM: riscv: add CAR interface Add an interface to support cache as ram. Initialize stack pointer for each hart. BUG=none BRANCH=none TEST=none Change-Id: Icdc2123678b4e68fe316358546bf763f98049521 Signed-off-by: Patrick Georgi <pgeorgi@google.com> Original-Commit-Id: 35da319b725805482e4d57571d92cccf65384d63 Original-Change-Id: Ic3920e01dd1a7f047a53de57250589000a111409 Original-Signed-off-by: Xiang Wang <wxjstz@126.com> Original-Reviewed-on: https://review.coreboot.org/27430 Original-Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Original-Reviewed-by: Ronald G. Minnich <rminnich@gmail.com> Reviewed-on: https://chromium-review.googlesource.com/1143251 Commit-Ready: Patrick Georgi <pgeorgi@chromium.org> Tested-by: Patrick Georgi <pgeorgi@chromium.org> Reviewed-by: Patrick Georgi <pgeorgi@chromium.org> " fail_count="1" gerrit_number="1143251" owner_email="pgeorgi@chromium.org" pass_count="0" patch_number="2" project="chromiumos/third_party/coreboot" project_url="https://chromium-review.googlesource.com/chromiumos/third_party/coreboot" ref="refs/changes/51/1143251/2" remote="cros" total_fail_count="1"/><pending_commit branch="chromeos-2016.05" change_id="I5cc0b210982b6c8dcca92c917253933711803b07" commit="182c748535638a52766bb3a7e2fa011bdd7ff020" commit_message="UPSTREAM: mainboard/google/kahlee: Enable ASPM on PCI express We should use active-state power management where possible to reduce power consumption during normal operation. Enable these options. Linux does not seem to enable this for AMD, and the Intel code in coreboot does enable these options. PCIEXP_COMMON_CLOCK is enabled also, to follow how Intel does it. BUG=b:110041917 TEST=boot on grunt, see that WiFi and eMMC still run OK Change-Id: I5cc0b210982b6c8dcca92c917253933711803b07 Signed-off-by: Patrick Georgi <pgeorgi@google.com> Original-Commit-Id: 82eb80cc8c08d2f676e7cb20b3b9bdf45b91d214 Original-Change-Id: Ia7c711304ffe460a9fb0d4f654a51485958239ea Original-Signed-off-by: Simon Glass <sjg@chromium.org> Original-Reviewed-on: https://review.coreboot.org/27464 Original-Reviewed-by: Martin Roth <martinroth@google.com> Original-Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-on: https://chromium-review.googlesource.com/1143252 Commit-Ready: Patrick Georgi <pgeorgi@chromium.org> Tested-by: Patrick Georgi <pgeorgi@chromium.org> Reviewed-by: Patrick Georgi <pgeorgi@chromium.org> " fail_count="1" gerrit_number="1143252" owner_email="pgeorgi@chromium.org" pass_count="0" patch_number="2" project="chromiumos/third_party/coreboot" project_url="https://chromium-review.googlesource.com/chromiumos/third_party/coreboot" ref="refs/changes/52/1143252/2" remote="cros" total_fail_count="1"/><pending_commit branch="chromeos-2016.05" change_id="Ib0bb6d8b6d60f3019fc889c28ebc56efbcffe6fb" commit="2097961c8e6c0bb0a471b62eeda564552dd3f095" commit_message="UPSTREAM: mainboard/google/Kahlee: Select low-power mode for WiFi Put the PCIe clock pins in power-saving mode for the WiFi module to save power. Note: This currently does not appear to have any effect on grunt. BUG=b:110041917 BRANCH=none TEST=boot without this patch: $ iotools mem_read32 0xfed80e00 0x0046f3ff With this patch: $ iotools mem_read32 0xfed80e00 0x0046f3f1 Change-Id: Ib0bb6d8b6d60f3019fc889c28ebc56efbcffe6fb Signed-off-by: Patrick Georgi <pgeorgi@google.com> Original-Commit-Id: e577168ae3163768bc76d23e4e121a57b436abd6 Original-Change-Id: I389815bc36b8610a30b0cbb9d73262ad392e0181 Original-Signed-off-by: Simon Glass <sjg@chromium.org> Original-Reviewed-on: https://review.coreboot.org/27465 Original-Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> Original-Reviewed-by: Martin Roth <martinroth@google.com> Original-Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-on: https://chromium-review.googlesource.com/1143253 Commit-Ready: Patrick Georgi <pgeorgi@chromium.org> Tested-by: Patrick Georgi <pgeorgi@chromium.org> Reviewed-by: Patrick Georgi <pgeorgi@chromium.org> " fail_count="1" gerrit_number="1143253" owner_email="pgeorgi@chromium.org" pass_count="0" patch_number="2" project="chromiumos/third_party/coreboot" project_url="https://chromium-review.googlesource.com/chromiumos/third_party/coreboot" ref="refs/changes/53/1143253/2" remote="cros" total_fail_count="1"/><pending_commit branch="chromeos-2016.05" change_id="I3f8e1b8d2f9359857ada1b9d7390071b103c8422" commit="348bab5b48529fcaf152332391b55d8d921a1bef" commit_message="UPSTREAM: linux_trampoline: use trampoline RAM for the GDT The linux trampoline was modifying the existing GDT to add the 0x10 and 0x18 descriptors for Linux. This will not work when the existing GDT is in ROM. Change the code to set up a new GDT in what we know to be RAM. Tested by booting a linux payload. The main reason this works is that Linux almost immediately loads its own GDT and then segment registers. This GDT is a very temporary bridge. Note that none of this change used to be necessary; the coreboot GDT was originally compatible with Linux (ca 2000); then Linux changed. BUG=none BRANCH=none TEST=none Change-Id: I3f8e1b8d2f9359857ada1b9d7390071b103c8422 Signed-off-by: Patrick Georgi <pgeorgi@google.com> Original-Commit-Id: eeb83b6b53fc72fda60dea31fc7e0cf155ccdecf Original-Change-Id: I13990052fbfd6a500adab8a2db8f7aead1d24fa6 Original-Signed-off-by: Ronald G. Minnich <rminnich@gmail.com> Original-Reviewed-on: https://review.coreboot.org/27529 Original-Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Original-Reviewed-by: Patrick Georgi <pgeorgi@google.com> Reviewed-on: https://chromium-review.googlesource.com/1143255 Commit-Ready: Patrick Georgi <pgeorgi@chromium.org> Tested-by: Patrick Georgi <pgeorgi@chromium.org> Reviewed-by: Patrick Georgi <pgeorgi@chromium.org> " fail_count="1" gerrit_number="1143255" owner_email="pgeorgi@chromium.org" pass_count="0" patch_number="2" project="chromiumos/third_party/coreboot" project_url="https://chromium-review.googlesource.com/chromiumos/third_party/coreboot" ref="refs/changes/55/1143255/2" remote="cros" total_fail_count="1"/><pending_commit branch="chromeos-2016.05" change_id="Ia130d62fabe286536750204ce848027edaa513c2" commit="b39c56eb292809c0e27939f4d88f9d582a81e632" commit_message="UPSTREAM: arch/riscv: Fix makefile to only set flags for riscv This was updating flags for ALL architectures, not just riscv. That was bad, and gave us errors, although they weren't fatal for some reason: i386-elf-gcc: error: missing argument to '-mcmodel=' i386-elf-gcc: error: missing argument to '-march=' i386-elf-gcc: error: missing argument to '-mabi=' This issue started from commit 5fed693a (riscv: add support for modifying compiler options) Add comments to the other 'endif' statements since they're now surrounded by a global ifeq BUG=none BRANCH=none TEST=none Change-Id: Ia130d62fabe286536750204ce848027edaa513c2 Signed-off-by: Patrick Georgi <pgeorgi@google.com> Original-Commit-Id: 202e7d4f3c50bfac53d06eaf0b0b1247f4c95be8 Original-Change-Id: Ifa12ad98b04a5ac36148609ccdf46ca427fc5a27 Original-Signed-off-by: Martin Roth <martin@coreboot.org> Original-Reviewed-on: https://review.coreboot.org/27535 Original-Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Original-Reviewed-by: Patrick Georgi <pgeorgi@google.com> Reviewed-on: https://chromium-review.googlesource.com/1143256 Commit-Ready: Patrick Georgi <pgeorgi@chromium.org> Tested-by: Patrick Georgi <pgeorgi@chromium.org> Reviewed-by: Patrick Georgi <pgeorgi@chromium.org> " fail_count="1" gerrit_number="1143256" owner_email="pgeorgi@chromium.org" pass_count="0" patch_number="2" project="chromiumos/third_party/coreboot" project_url="https://chromium-review.googlesource.com/chromiumos/third_party/coreboot" ref="refs/changes/56/1143256/2" remote="cros" total_fail_count="1"/><pending_commit branch="chromeos-2016.05" change_id="Id04badac639cd7b7f3027405d4881271c954f887" commit="bd282d8836189db6b4ba18c4ddf3c8dc314e6f03" commit_message="UPSTREAM: Kconfig: Add config for creating a second bootblock Intel PCH/Southbridges have feature that it is possible to have the southbridge/PCH look for the bootblock at a 64K or 128K/256K/512K/1MB (in case of newer SoCs) offset instead of the usual top of flash. Add configs to create a second bootblock and configure its size. BUG=none BRANCH=none TEST=none Change-Id: Id04badac639cd7b7f3027405d4881271c954f887 Signed-off-by: Patrick Georgi <pgeorgi@google.com> Original-Commit-Id: b082670234819108a15da6239e481f5c9d8b30ec Original-Change-Id: I4bbd19c35871891b762a0673f840858d972e129e Original-Signed-off-by: Rizwan Qureshi <rizwan.qureshi@intel.com> Original-Signed-off-by: Aamir Bohra <aamir.bohra@intel.com> Original-Reviewed-on: https://review.coreboot.org/22533 Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> Original-Reviewed-by: Furquan Shaikh <furquan@google.com> Original-Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-on: https://chromium-review.googlesource.com/1143258 Commit-Ready: Patrick Georgi <pgeorgi@chromium.org> Tested-by: Patrick Georgi <pgeorgi@chromium.org> Reviewed-by: Patrick Georgi <pgeorgi@chromium.org> " fail_count="1" gerrit_number="1143258" owner_email="pgeorgi@chromium.org" pass_count="0" patch_number="2" project="chromiumos/third_party/coreboot" project_url="https://chromium-review.googlesource.com/chromiumos/third_party/coreboot" ref="refs/changes/58/1143258/2" remote="cros" total_fail_count="1"/><pending_commit branch="chromeos-2016.05" change_id="I85d05eb90d857028700a4b0d7921190d4a2392db" commit="46b890c70832af0490016cfa5c9bd275e41165e1" commit_message="UPSTREAM: Kconfig: Add config to insert ucode address in second FIT This config is used to provide the name of a region where a microcode is located. The address of this will be added as the first entry in the FIT of the topswap bootblock. This adds a capability to associate two microcodes for each of the two bootblocks, this allows for the CPU to boot with different microcodes with 2 separate bootblocks. BUG=none BRANCH=none TEST=none Change-Id: I85d05eb90d857028700a4b0d7921190d4a2392db Signed-off-by: Patrick Georgi <pgeorgi@google.com> Original-Commit-Id: 53485124513a76ebe85a80f59e8dff9915f518bd Original-Change-Id: I4ee41d90bae34862aa68c9b8bd69288de1335585 Original-Signed-off-by: Rizwan Qureshi <rizwan.qureshi@intel.com> Original-Reviewed-on: https://review.coreboot.org/27151 Original-Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Original-Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-on: https://chromium-review.googlesource.com/1143259 Commit-Ready: Patrick Georgi <pgeorgi@chromium.org> Tested-by: Patrick Georgi <pgeorgi@chromium.org> Reviewed-by: Patrick Georgi <pgeorgi@chromium.org> " fail_count="1" gerrit_number="1143259" owner_email="pgeorgi@chromium.org" pass_count="0" patch_number="2" project="chromiumos/third_party/coreboot" project_url="https://chromium-review.googlesource.com/chromiumos/third_party/coreboot" ref="refs/changes/59/1143259/2" remote="cros" total_fail_count="1"/><pending_commit branch="chromeos-4.14" change_id="Id5f351dc47e4c8a10d28c76038b79af5b60ff3d1" commit="c746c7864293833a39ecae780780f96f30629a38" commit_message="CHROMIUM: arch: x86: configs: enable IPVLAN The last CL enabled the dependencies for IPVLAN, but not the config itself. So enable CONFIG_IPVLAN. BUG=chromium:860874 TEST=emerge-tatl chromeos-kernel-4_14 TBR=dgreid Signed-off-by: Stephen Barber <smbarber@chromium.org> Change-Id: Id5f351dc47e4c8a10d28c76038b79af5b60ff3d1 Reviewed-on: https://chromium-review.googlesource.com/1144785 Commit-Ready: ChromeOS CL Exonerator Bot <chromiumos-cl-exonerator@appspot.gserviceaccount.com> Tested-by: Stephen Barber <smbarber@chromium.org> Reviewed-by: Stephen Barber <smbarber@chromium.org> " fail_count="0" gerrit_number="1144785" owner_email="smbarber@chromium.org" pass_count="0" patch_number="2" project="chromiumos/third_party/kernel" project_url="https://chromium-review.googlesource.com/chromiumos/third_party/kernel" ref="refs/changes/85/1144785/2" remote="cros" total_fail_count="0"/><pending_commit branch="master" change_id="I081183a5dfebb3a5031d801b21c85a45dc385cf7" commit="1f66b0ab9b4deba84e4044838d99e586a6032929" commit_message="Makefile: Get private overlay resource when resource/ does not exist. The factory makefile ignores private overlay resources when the directory `chromeos-base/factory-board/files/resources/` does not exist. The CL changes the makefile to always find resource files even if the directory does not exist. BUG=chromium:865866 TEST=Find an overlay with py/config/cutoff.json and without resource/; `emerge-<board> chromeos-base/factory`; `emerge-<board> chromeos-base/factory_installer`; `script/build_image --board=<board> factory_install`; Mount factory shim, see cutoff.json in /usr/share/cutoff/ Change-Id: I081183a5dfebb3a5031d801b21c85a45dc385cf7 Reviewed-on: https://chromium-review.googlesource.com/1144815 Commit-Ready: Cheng-Han Yang <chenghan@chromium.org> Tested-by: Cheng-Han Yang <chenghan@chromium.org> Reviewed-by: Hung-Te Lin <hungte@chromium.org> " fail_count="0" gerrit_number="1144815" owner_email="chenghan@chromium.org" pass_count="0" patch_number="2" project="chromiumos/platform/factory" project_url="https://chromium-review.googlesource.com/chromiumos/platform/factory" ref="refs/changes/15/1144815/2" remote="cros" total_fail_count="0"/><pending_commit branch="master" change_id="Iccc9aad211fec47ecc80f9e591097303f30f5d90" commit="bde700e0b45238096dcc66cd58802da4f64591f2" commit_message="Instalog: BufferEventStream doesn't time out in time when filtering Instalog has flow policy to filter events in buffer. If a output plugin doesn't accept a event, the BufferEventStream will ignore it automatically. However, if buffer has lots of event which is not for the output plugin, the BufferEventStream won't time out in time. BUG=b:109905899 TEST=manually test in local device Change-Id: Iccc9aad211fec47ecc80f9e591097303f30f5d90 Reviewed-on: https://chromium-review.googlesource.com/1141547 Commit-Ready: Chun-Tsen Kuo <chuntsen@chromium.org> Tested-by: Chun-Tsen Kuo <chuntsen@chromium.org> Reviewed-by: Ting Shen <phoenixshen@chromium.org> " fail_count="0" gerrit_number="1141547" owner_email="chuntsen@chromium.org" pass_count="0" patch_number="6" project="chromiumos/platform/factory" project_url="https://chromium-review.googlesource.com/chromiumos/platform/factory" ref="refs/changes/47/1141547/6" remote="cros" total_fail_count="0"/><pending_commit branch="master" change_id="I27c20a2113f13811d36be8eaafc6c16f95f187d4" commit="c318ff968c34a6ee21a03d14e36f936472400308" commit_message="valid_hwid_db_unittest: Blacklist KENCH temporarily. According to the conclusion in b/110759697, we should deprecate the invalid region encoding from the KENCH HWID DB. This is a temporary solution to make unittest happy before we are having a better way to handle deprecated region. TEST=make test BUG=b:110596222 Change-Id: I27c20a2113f13811d36be8eaafc6c16f95f187d4 Signed-off-by: Yilun Lin <yllin@google.com> Reviewed-on: https://chromium-review.googlesource.com/1144590 Commit-Ready: Yilun Lin <yllin@chromium.org> Tested-by: Yilun Lin <yllin@chromium.org> Reviewed-by: Yong Hong <yhong@google.com> " fail_count="0" gerrit_number="1144590" owner_email="yllin@chromium.org" pass_count="0" patch_number="2" project="chromiumos/platform/factory" project_url="https://chromium-review.googlesource.com/chromiumos/platform/factory" ref="refs/changes/90/1144590/2" remote="cros" total_fail_count="0"/><pending_commit branch="chromeos-4.14" change_id="I4c6af7cf88e7a6a0237f7eb01ddda3226cc9711d" commit="e4d506b7e7100e99e77761f185f6156f06b43ed2" commit_message="CHROMIUM: arch: arm64: configs: enable IPVLAN The last CL enabled the dependencies for IPVLAN, but not the config itself. So enable CONFIG_IPVLAN. BUG=chromium:860874 TEST=emerge-tael chromeos-kernel-4_14 TBR=dgreid Change-Id: I4c6af7cf88e7a6a0237f7eb01ddda3226cc9711d Signed-off-by: Stephen Barber <smbarber@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/1144786 " fail_count="0" gerrit_number="1144786" owner_email="smbarber@chromium.org" pass_count="0" patch_number="2" project="chromiumos/third_party/kernel" project_url="https://chromium-review.googlesource.com/chromiumos/third_party/kernel" ref="refs/changes/86/1144786/2" remote="cros" total_fail_count="0"/><pending_commit branch="chromeos-4.14" change_id="Ia6ffd3b4eb4c38f669fd3223fd7fd199ada6d8eb" commit="f233b47cd9cf173860df44591eea3cd29f35979d" commit_message="CHROMIUM: Merge 'v4.14.56' into chromeos-4.14 Merge of v4.14.56 into chromeos-4.14 Changelog: ---------------------------------------------------------------- Chris Wilson (1): ALSA: hda - Handle pm failure during hotplug Christian Borntraeger (1): mm: do not drop unused pages when userfaultd is running Christian Brauner (2): devpts: hoist out check for DEVPTS_SUPER_MAGIC devpts: resolve devpts bind-mounts Christoph Hellwig (1): genirq/affinity: assign vectors to all possible CPUs Damien Le Moal (2): ata: Fix ZBC_OUT command block check ata: Fix ZBC_OUT all bit handling Dan Carpenter (2): USB: serial: ch341: fix type promotion bug in ch341_control_in() xhci: xhci-mem: off by one in xhci_stream_id_to_ring() Eric Biggers (1): crypto: x86/salsa20 - remove x86 salsa20 implementations Eric Dumazet (1): netfilter: nf_queue: augment nfqa_cfg_policy Florian Westphal (1): netfilter: x_tables: initialise match/target check parameter struct Greg Kroah-Hartman (1): Linux 4.14.56 Guenter Roeck (1): Merge remote-tracking branch 'origin/linux/v4.14.56' into merge/chromeos-4.14-v4.14.56 Hans de Goede (1): ahci: Disable LPM on Lenovo 50 series laptops with a too old BIOS Hui Wang (1): ALSA: hda/realtek - two more lenovo models need fixup of MIC_LOCATION Jaegeuk Kim (1): f2fs: give message and set need_fsck given broken node id Jann Horn (2): ibmasm: don't write out of bounds in read handler USB: yurex: fix out-of-bounds uaccess in read handler Joel Fernandes (Google) (1): tracing: Reorder display of TGID to be after PID Johan Hovold (2): USB: serial: keyspan_pda: fix modem-status error handling USB: serial: mos7840: fix status-register error handling Jon Hunter (1): i2c: tegra: Fix NACK error handling Juergen Gross (1): xen: setup pv irq ops vector earlier Kai Chieh Chuang (1): ASoC: mediatek: preallocate pages use platform device Keith Busch (1): nvme-pci: Remap CMB SQ entries on every controller reset Leon Romanovsky (1): RDMA/ucm: Mark UCM interface as BROKEN Linus Torvalds (1): Fix up non-directory creation in SGID directories Michael J. Ruhl (1): IB/hfi1: Fix incorrect mixing of ERR_PTR and NULL return values Michal Hocko (1): mm: do not bug_on on incorrect length in __mm_populate() Ming Lei (1): scsi: megaraid_sas: fix selection of reply queue Murray McAllister (1): staging: rtl8723bs: Prevent an underflow in rtw_check_beacon_data(). Nadav Amit (1): vmw_balloon: fix inflation with batching Nico Sneck (1): usb: quirks: add delay quirks for Corsair Strafe Oleg Nesterov (1): uprobes/x86: Remove incorrect WARN_ON() in uprobe_init_insn() Olli Salonen (1): USB: serial: cp210x: add another USB ID for Qivicon ZigBee stick Oscar Salvador (1): fs, elf: make sure to page align bss in load_elf_library Paul Burton (3): MIPS: Call dump_stack() from show_regs() MIPS: Use async IPIs for arch_trigger_cpumask_backtrace() MIPS: Fix ioremap() RAM check Paul Menzel (1): tools build: fix # escaping in .cmd files for future Make Ping-Ke Shih (1): staging: r8822be: Fix RTL8822be can't find any wireless AP Randy Dunlap (1): kbuild: delete INSTALL_FW_PATH from kbuild documentation Sean Young (1): media: rc: mce_kbd decoder: fix stuck keys Shivasharan S (4): scsi: megaraid_sas: use adapter_type for all gen controllers scsi: megaraid_sas: replace instance->ctrl_context checks with instance->adapter_type scsi: megaraid_sas: replace is_ventura with adapter_type checks scsi: megaraid_sas: Create separate functions to allocate ctrl memory Stefan Agner (1): mmc: sdhci-esdhc-imx: allow 1.8V modes without 100/200MHz pinctrl states Steve Wise (1): iw_cxgb4: correctly enforce the max reg_mr depth Tetsuo Handa (2): PM / hibernate: Fix oops at snapshot_write() loop: remember whether sysfs_create_group() was done Theodore Ts'o (1): loop: add recursion validation to LOOP_CHANGE_FD Vlastimil Babka (1): fs/proc/task_mmu.c: fix Locked field in /proc/pid/smaps* Yandong Zhao (1): arm64: neon: Fix function may_use_simd() return error status x00270170 (1): mmc: dw_mmc: fix card threshold control configuration Documentation/kbuild/kbuild.txt | 9 - Makefile | 2 +- arch/arm64/include/asm/simd.h | 19 +- arch/mips/kernel/process.c | 43 +- arch/mips/kernel/traps.c | 1 + arch/mips/mm/ioremap.c | 37 +- arch/x86/crypto/Makefile | 4 - arch/x86/crypto/salsa20-i586-asm_32.S | 1114 -------------------- arch/x86/crypto/salsa20-x86_64-asm_64.S | 919 ---------------- arch/x86/crypto/salsa20_glue.c | 116 -- arch/x86/kernel/uprobes.c | 2 +- arch/x86/xen/enlighten_pv.c | 24 +- arch/x86/xen/irq.c | 4 +- crypto/Kconfig | 26 - drivers/ata/ahci.c | 59 ++ drivers/ata/libata-core.c | 3 + drivers/ata/libata-scsi.c | 18 +- drivers/block/loop.c | 79 +- drivers/block/loop.h | 1 + drivers/i2c/busses/i2c-tegra.c | 17 +- drivers/infiniband/Kconfig | 12 + drivers/infiniband/core/Makefile | 4 +- drivers/infiniband/hw/cxgb4/mem.c | 2 +- drivers/infiniband/hw/hfi1/rc.c | 2 +- drivers/infiniband/hw/hfi1/uc.c | 4 +- drivers/infiniband/hw/hfi1/ud.c | 4 +- drivers/infiniband/hw/hfi1/verbs_txreq.c | 4 +- drivers/infiniband/hw/hfi1/verbs_txreq.h | 4 +- drivers/media/rc/ir-mce_kbd-decoder.c | 2 + drivers/misc/ibmasm/ibmasmfs.c | 27 +- drivers/misc/vmw_balloon.c | 4 +- drivers/mmc/host/dw_mmc.c | 7 +- drivers/mmc/host/sdhci-esdhc-imx.c | 21 +- drivers/nvme/host/pci.c | 27 +- drivers/scsi/megaraid/megaraid_sas.h | 10 +- drivers/scsi/megaraid/megaraid_sas_base.c | 296 ++++-- drivers/scsi/megaraid/megaraid_sas_fp.c | 20 +- drivers/scsi/megaraid/megaraid_sas_fusion.c | 54 +- drivers/scsi/megaraid/megaraid_sas_fusion.h | 7 - drivers/staging/rtl8723bs/core/rtw_ap.c | 2 +- drivers/staging/rtlwifi/rtl8822be/hw.c | 2 +- drivers/staging/rtlwifi/wifi.h | 1 + drivers/usb/core/quirks.c | 4 + drivers/usb/host/xhci-mem.c | 2 +- drivers/usb/misc/yurex.c | 23 +- drivers/usb/serial/ch341.c | 2 +- drivers/usb/serial/cp210x.c | 1 + drivers/usb/serial/keyspan_pda.c | 4 +- drivers/usb/serial/mos7840.c | 3 + fs/binfmt_elf.c | 5 +- fs/devpts/inode.c | 48 +- fs/f2fs/f2fs.h | 13 +- fs/f2fs/inode.c | 13 +- fs/f2fs/node.c | 21 +- fs/inode.c | 6 + fs/proc/task_mmu.c | 2 +- include/linux/libata.h | 1 + kernel/irq/affinity.c | 30 +- kernel/power/user.c | 5 + kernel/trace/trace.c | 8 +- kernel/trace/trace_output.c | 5 +- mm/gup.c | 2 - mm/mmap.c | 29 +- mm/rmap.c | 8 +- net/bridge/netfilter/ebtables.c | 2 + net/ipv4/netfilter/ip_tables.c | 1 + net/ipv6/netfilter/ip6_tables.c | 1 + net/netfilter/nfnetlink_queue.c | 3 + sound/pci/hda/patch_hdmi.c | 19 +- sound/pci/hda/patch_realtek.c | 6 +- .../soc/mediatek/common/mtk-afe-platform-driver.c | 4 +- tools/build/Build.include | 4 +- 72 files changed, 664 insertions(+), 2624 deletions(-) delete mode 100644 arch/x86/crypto/salsa20-i586-asm_32.S delete mode 100644 arch/x86/crypto/salsa20-x86_64-asm_64.S delete mode 100644 arch/x86/crypto/salsa20_glue.c BUG=chromium:864507 TEST=Build and test on various affected systems Change-Id: Ia6ffd3b4eb4c38f669fd3223fd7fd199ada6d8eb Signed-off-by: Guenter Roeck <groeck@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/1140354 " fail_count="0" gerrit_number="1140354" owner_email="groeck@chromium.org" pass_count="0" patch_number="1" project="chromiumos/third_party/kernel" project_url="https://chromium-review.googlesource.com/chromiumos/third_party/kernel" ref="refs/changes/54/1140354/1" remote="cros" total_fail_count="0"/><pending_commit branch="chromeos-4.4" change_id="Ib6ea2b89e4a056df2de9ede48e7a6e2dc2a67bc1" commit="0e1047110f8b12017c07fc5d259221d3d71f63c2" commit_message="CHROMIUM: Merge 'v4.4.141' into chromeos-4.4 Merge of v4.4.141 into chromeos-4.4 Conflicts: arch/x86/include/asm/thread_info.h Changelog: ---------------------------------------------------------------- Alexander Kuleshov (1): x86/boot: Simplify kernel load address alignment check Andi Kleen (1): x86/headers: Don't include asm/processor.h in asm/atomic.h Borislav Petkov (11): x86/cpufeature: Move some of the scattered feature bits to x86_capability x86/cpufeature: Cleanup get_cpu_cap() x86/cpu: Provide a config option to disable static_cpu_has x86/fpu: Add an XSTATE_OP() macro x86/fpu: Get rid of xstate_fault() x86/cpufeature: Carve out X86_FEATURE_* x86/cpufeature: Replace the old static_cpu_has() with safe variant x86/cpufeature: Get rid of the non-asm goto variant x86/alternatives: Add an auxilary section x86/vdso: Use static_cpu_has() x86/cpufeature: Speed up cpu_feature_enabled() Brian Gerst (1): x86/alternatives: Discard dynamic check after init Dan Carpenter (2): USB: serial: ch341: fix type promotion bug in ch341_control_in() xhci: xhci-mem: off by one in xhci_stream_id_to_ring() Dave Hansen (6): x86/cpufeature, x86/mm/pkeys: Add protection keys related CPUID definitions x86/mm/pkeys: Fix mismerge of protection keys CPUID bits x86/cpufeature, x86/mm/pkeys: Fix broken compile-time disabling of pkeys x86/cpufeature: Update cpufeaure macros x86/cpufeature: Make sure DISABLED/REQUIRED macros are updated x86/cpufeature: Add helper macro for mask check macros Eric Dumazet (1): netfilter: nf_queue: augment nfqa_cfg_policy Florian Westphal (1): netfilter: x_tables: initialise match/target check parameter struct Greg Kroah-Hartman (1): Linux 4.4.141 Guenter Roeck (1): Merge remote-tracking branch 'origin/linux/v4.4.141' into merge/chromeos-4.4-v4.4.141 Hans de Goede (1): ahci: Disable LPM on Lenovo 50 series laptops with a too old BIOS Jann Horn (2): ibmasm: don't write out of bounds in read handler USB: yurex: fix out-of-bounds uaccess in read handler Johan Hovold (2): USB: serial: keyspan_pda: fix modem-status error handling USB: serial: mos7840: fix status-register error handling Leon Romanovsky (1): RDMA/ucm: Mark UCM interface as BROKEN Linus Torvalds (1): Fix up non-directory creation in SGID directories Nadav Amit (1): vmw_balloon: fix inflation with batching Nico Sneck (1): usb: quirks: add delay quirks for Corsair Strafe Oleg Nesterov (1): uprobes/x86: Remove incorrect WARN_ON() in uprobe_init_insn() Olli Salonen (1): USB: serial: cp210x: add another USB ID for Qivicon ZigBee stick Paul Burton (1): MIPS: Fix ioremap() RAM check Paul Menzel (1): tools build: fix # escaping in .cmd files for future Make Steve Wise (1): iw_cxgb4: correctly enforce the max reg_mr depth Tetsuo Handa (2): PM / hibernate: Fix oops at snapshot_write() loop: remember whether sysfs_create_group() was done Theodore Ts'o (1): loop: add recursion validation to LOOP_CHANGE_FD Tomasz Kramkowski (1): HID: usbhid: add quirk for innomedia INNEX GENESIS/ATARI adapter Yazen Ghannam (1): x86/cpu: Add detection of AMD RAS Capabilities Documentation/kernel-parameters.txt | 2 +- Makefile | 2 +- arch/mips/mm/ioremap.c | 37 ++- arch/x86/Kconfig | 11 + arch/x86/Kconfig.debug | 10 - arch/x86/boot/cpuflags.h | 2 +- arch/x86/boot/mkcpustr.c | 2 +- arch/x86/crypto/crc32-pclmul_glue.c | 2 +- arch/x86/crypto/crc32c-intel_glue.c | 2 +- arch/x86/crypto/crct10dif-pclmul_glue.c | 2 +- arch/x86/entry/common.c | 1 + arch/x86/entry/entry_32.S | 2 +- arch/x86/entry/vdso/vdso32-setup.c | 1 - arch/x86/entry/vdso/vdso32/system_call.S | 2 +- arch/x86/entry/vdso/vma.c | 3 +- arch/x86/include/asm/alternative.h | 6 - arch/x86/include/asm/apic.h | 1 - arch/x86/include/asm/arch_hweight.h | 2 + arch/x86/include/asm/atomic.h | 1 - arch/x86/include/asm/atomic64_32.h | 1 - arch/x86/include/asm/cmpxchg.h | 1 + arch/x86/include/asm/cpufeature.h | 546 ++++++------------------------- arch/x86/include/asm/cpufeatures.h | 306 +++++++++++++++++ arch/x86/include/asm/disabled-features.h | 17 + arch/x86/include/asm/fpu/internal.h | 182 +++++------ arch/x86/include/asm/irq_work.h | 2 +- arch/x86/include/asm/mwait.h | 2 + arch/x86/include/asm/nospec-branch.h | 2 +- arch/x86/include/asm/processor.h | 3 +- arch/x86/include/asm/required-features.h | 9 + arch/x86/include/asm/smap.h | 2 +- arch/x86/include/asm/smp.h | 1 - arch/x86/include/asm/thread_info.h | 2 +- arch/x86/include/asm/tlbflush.h | 1 + arch/x86/include/asm/uaccess_64.h | 2 +- arch/x86/kernel/apic/apic_numachip.c | 4 +- arch/x86/kernel/cpu/Makefile | 2 +- arch/x86/kernel/cpu/centaur.c | 4 +- arch/x86/kernel/cpu/common.c | 71 ++-- arch/x86/kernel/cpu/cyrix.c | 1 + arch/x86/kernel/cpu/intel.c | 2 +- arch/x86/kernel/cpu/intel_cacheinfo.c | 2 +- arch/x86/kernel/cpu/match.c | 2 +- arch/x86/kernel/cpu/mkcapflags.sh | 6 +- arch/x86/kernel/cpu/mtrr/main.c | 2 +- arch/x86/kernel/cpu/scattered.c | 20 -- arch/x86/kernel/cpu/transmeta.c | 6 +- arch/x86/kernel/e820.c | 1 + arch/x86/kernel/head_32.S | 2 +- arch/x86/kernel/head_64.S | 4 +- arch/x86/kernel/hpet.c | 1 + arch/x86/kernel/msr.c | 2 +- arch/x86/kernel/uprobes.c | 2 +- arch/x86/kernel/verify_cpu.S | 2 +- arch/x86/kernel/vm86_32.c | 2 +- arch/x86/kernel/vmlinux.lds.S | 11 + arch/x86/lib/clear_page_64.S | 2 +- arch/x86/lib/copy_page_64.S | 2 +- arch/x86/lib/copy_user_64.S | 2 +- arch/x86/lib/memcpy_64.S | 2 +- arch/x86/lib/memmove_64.S | 2 +- arch/x86/lib/memset_64.S | 2 +- arch/x86/lib/retpoline.S | 2 +- arch/x86/mm/setup_nx.c | 1 + arch/x86/oprofile/op_model_amd.c | 1 - arch/x86/um/asm/barrier.h | 2 +- drivers/ata/ahci.c | 59 ++++ drivers/ata/libata-core.c | 3 + drivers/block/loop.c | 79 +++-- drivers/block/loop.h | 1 + drivers/hid/hid-ids.h | 3 + drivers/hid/usbhid/hid-quirks.c | 1 + drivers/infiniband/Kconfig | 12 + drivers/infiniband/core/Makefile | 4 +- drivers/infiniband/hw/cxgb4/mem.c | 2 +- drivers/misc/ibmasm/ibmasmfs.c | 27 +- drivers/misc/vmw_balloon.c | 4 +- drivers/usb/core/quirks.c | 4 + drivers/usb/host/xhci-mem.c | 2 +- drivers/usb/misc/yurex.c | 23 +- drivers/usb/serial/ch341.c | 2 +- drivers/usb/serial/cp210x.c | 1 + drivers/usb/serial/keyspan_pda.c | 4 +- drivers/usb/serial/mos7840.c | 3 + fs/btrfs/disk-io.c | 2 +- fs/inode.c | 6 + include/linux/libata.h | 1 + kernel/power/user.c | 5 + lib/atomic64_test.c | 4 + net/bridge/netfilter/ebtables.c | 2 + net/ipv4/netfilter/ip_tables.c | 1 + net/ipv6/netfilter/ip6_tables.c | 1 + net/netfilter/nfnetlink_queue.c | 3 + tools/build/Build.include | 4 +- 94 files changed, 830 insertions(+), 770 deletions(-) create mode 100644 arch/x86/include/asm/cpufeatures.h BUG=chromium:864505 TEST=Build and test on various affected systems Change-Id: Ib6ea2b89e4a056df2de9ede48e7a6e2dc2a67bc1 Signed-off-by: Guenter Roeck <groeck@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/1140357 " fail_count="0" gerrit_number="1140357" owner_email="groeck@chromium.org" pass_count="0" patch_number="1" project="chromiumos/third_party/kernel" project_url="https://chromium-review.googlesource.com/chromiumos/third_party/kernel" ref="refs/changes/57/1140357/1" remote="cros" total_fail_count="0"/><lkgm version="10894.0.0-rc3"/></manifest> |
