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https://chromium-review.googlesource.com/1340627 Commit-Ready: Patrick Georgi <pgeorgi@chromium.org> Tested-by: Patrick Georgi <pgeorgi@chromium.org> Reviewed-by: Patrick Georgi <pgeorgi@chromium.org> " fail_count="0" gerrit_number="1340627" owner_email="pgeorgi@chromium.org" pass_count="0" patch_number="1" project="chromiumos/third_party/coreboot" project_url="https://chromium-review.googlesource.com/chromiumos/third_party/coreboot" ref="refs/changes/27/1340627/1" remote="cros" total_fail_count="0"/><pending_commit branch="chromeos-2016.05" change_id="I1076e1e0e22e5894c1e135eea2baeba5992b608b" commit="cd364e59827df21211b089b4dfc566a99e32738e" commit_message="UPSTREAM: soc/intel/icelake: Allow coreboot to reserve stack for fsp BUG=none BRANCH=none TEST=none Change-Id: I1076e1e0e22e5894c1e135eea2baeba5992b608b Signed-off-by: Patrick Georgi <pgeorgi@google.com> Original-Commit-Id: 23012a0dff9810c9055369fb5f21e8ef5f074f7b Original-Change-Id: I5f2d9548b8e2c7b1d154b7bad126ec7b1052231a Original-Signed-off-by: Subrata Banik <subrata.banik@intel.com> Original-Signed-off-by: Aamir Bohra <aamir.bohra@intel.com> Original-Reviewed-on: https://review.coreboot.org/29317 Original-Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Original-Reviewed-by: Shelley Chen <shchen@google.com> Reviewed-on: https://chromium-review.googlesource.com/1340628 Commit-Ready: Patrick Georgi <pgeorgi@chromium.org> Tested-by: Patrick Georgi <pgeorgi@chromium.org> Reviewed-by: Patrick Georgi <pgeorgi@chromium.org> " fail_count="0" gerrit_number="1340628" owner_email="pgeorgi@chromium.org" pass_count="0" patch_number="1" project="chromiumos/third_party/coreboot" project_url="https://chromium-review.googlesource.com/chromiumos/third_party/coreboot" ref="refs/changes/28/1340628/1" remote="cros" total_fail_count="0"/><pending_commit branch="chromeos-2016.05" change_id="I11691eb39723d461332959d2b8cab9f71970ee87" commit="2f4741fd18f2c49bab33fe106117228291abdcbf" commit_message="UPSTREAM: soc/intel/icelake: Add PID based on Icelake EDS BUG=none BRANCH=none TEST=none Change-Id: I11691eb39723d461332959d2b8cab9f71970ee87 Signed-off-by: Patrick Georgi <pgeorgi@google.com> Original-Commit-Id: c7267631e23ec113de898bf07b5f6f212acc3629 Original-Change-Id: I2d9e06f06a39dc76a3c1351d7976505d7bd92d10 Original-Signed-off-by: Subrata Banik <subrata.banik@intel.com> Original-Signed-off-by: Aamir Bohra <aamir.bohra@intel.com> Original-Reviewed-on: https://review.coreboot.org/29436 Original-Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Original-Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-on: https://chromium-review.googlesource.com/1340629 Commit-Ready: Patrick Georgi <pgeorgi@chromium.org> Tested-by: Patrick Georgi <pgeorgi@chromium.org> Reviewed-by: Patrick Georgi <pgeorgi@chromium.org> " fail_count="0" gerrit_number="1340629" owner_email="pgeorgi@chromium.org" pass_count="0" patch_number="1" project="chromiumos/third_party/coreboot" project_url="https://chromium-review.googlesource.com/chromiumos/third_party/coreboot" ref="refs/changes/29/1340629/1" remote="cros" total_fail_count="0"/><pending_commit branch="chromeos-2016.05" change_id="I482fe9791534a3e12c914ef964d00142d6861cfd" commit="5362ddb8497c094ac67d4a13fc2222cc1c1399c2" commit_message="UPSTREAM: src: Remove unneeded include <arch/ioapic.h> BUG=none BRANCH=none TEST=none Change-Id: I482fe9791534a3e12c914ef964d00142d6861cfd Signed-off-by: Patrick Georgi <pgeorgi@google.com> Original-Commit-Id: 3b6624b88ec433b4546584c0a9d82cda365d10dd Original-Change-Id: Ic08b191ee4dbcc56eb482601aa268394545936ba Original-Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Original-Reviewed-on: https://review.coreboot.org/29292 Original-Reviewed-by: Patrick Georgi <pgeorgi@google.com> Original-Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-on: https://chromium-review.googlesource.com/1340630 Commit-Ready: Patrick Georgi <pgeorgi@chromium.org> Tested-by: Patrick Georgi <pgeorgi@chromium.org> Reviewed-by: Patrick Georgi <pgeorgi@chromium.org> " fail_count="0" gerrit_number="1340630" owner_email="pgeorgi@chromium.org" pass_count="0" patch_number="1" project="chromiumos/third_party/coreboot" project_url="https://chromium-review.googlesource.com/chromiumos/third_party/coreboot" ref="refs/changes/30/1340630/1" remote="cros" total_fail_count="0"/><pending_commit branch="chromeos-2016.05" change_id="Ia483058cfff6edc8373f52cafb0fab491a4ae417" commit="fb9d2066fc2cb8652e29f9bfc133baeb64e9e969" commit_message="UPSTREAM: drivers/intel/fsp2_0: Run SplitFspBin with python2 It's not Python 3 compatible. BUG=none BRANCH=none TEST=none Change-Id: Ia483058cfff6edc8373f52cafb0fab491a4ae417 Signed-off-by: Patrick Georgi <pgeorgi@google.com> Original-Commit-Id: e0af8aa34fb4c2ea8d97a3572d99f15cafe740da Original-Change-Id: Ibaad2c31bb6494652ce650ab7c1064728ec5fe80 Original-Signed-off-by: Nico Huber <nico.h@gmx.de> Original-Reviewed-on: https://review.coreboot.org/29519 Original-Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Original-Reviewed-by: Philipp Deppenwiese <zaolin.daisuki@gmail.com> Reviewed-on: https://chromium-review.googlesource.com/1340631 Commit-Ready: Patrick Georgi <pgeorgi@chromium.org> Tested-by: Patrick Georgi <pgeorgi@chromium.org> Reviewed-by: Patrick Georgi <pgeorgi@chromium.org> " fail_count="0" gerrit_number="1340631" owner_email="pgeorgi@chromium.org" pass_count="0" patch_number="1" project="chromiumos/third_party/coreboot" project_url="https://chromium-review.googlesource.com/chromiumos/third_party/coreboot" ref="refs/changes/31/1340631/1" remote="cros" total_fail_count="0"/><pending_commit branch="chromeos-2016.05" change_id="I4528718e360c6a4d99d895280b8bf2233448857c" commit="f08abb4cd86c786d6b442548ec62d9b8e27d013c" commit_message="UPSTREAM: soc/intel/common: Include Icelake device IDs Add Icelake specific CPU, System Agent, PCH, IGD device IDs. BUG=none BRANCH=none TEST=none Change-Id: I4528718e360c6a4d99d895280b8bf2233448857c Signed-off-by: Patrick Georgi <pgeorgi@google.com> Original-Commit-Id: 9eac039f592f44dc3580682597b794c27684d70f Original-Change-Id: I2c398957ffbc9bb0e5b363740d99433075ca66a3 Original-Signed-off-by: Subrata Banik <subrata.banik@intel.com> Original-Signed-off-by: Aamir Bohra <aamir.bohra@intel.com> Original-Reviewed-on: https://review.coreboot.org/29435 Original-Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Original-Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-on: https://chromium-review.googlesource.com/1340632 Commit-Ready: Patrick Georgi <pgeorgi@chromium.org> Tested-by: Patrick Georgi <pgeorgi@chromium.org> Reviewed-by: Patrick Georgi <pgeorgi@chromium.org> " fail_count="0" gerrit_number="1340632" owner_email="pgeorgi@chromium.org" pass_count="0" patch_number="1" project="chromiumos/third_party/coreboot" project_url="https://chromium-review.googlesource.com/chromiumos/third_party/coreboot" ref="refs/changes/32/1340632/1" remote="cros" total_fail_count="0"/><pending_commit branch="chromeos-2016.05" change_id="I20832546e911e8cc289b1d7b40a1ce4fec9df759" commit="bf877ac2e78ba4b2b3c2bd342d968c484b129bbe" commit_message="UPSTREAM: mb/intel/icelake_rvp: Move CNVi ASL entry from static DSDT to dynamic SSDT generation This changes uses drivers/intel/wifi chip for CNVi device to ensure that: 1. Correct device name shows in ACPI name space 2. Correct wake up shows in cat /proc/acpi/wakeup 3. Remove cnvi.asl from soc/intel/icelake BUG=none BRANCH=none TEST=none Change-Id: I20832546e911e8cc289b1d7b40a1ce4fec9df759 Signed-off-by: Patrick Georgi <pgeorgi@google.com> Original-Commit-Id: 2df5abc53bf670786a472c9c315adfc4e988cf2a Original-Change-Id: I21d3818ac9e384b0dbaa330d231022bdb8b8a547 Original-Signed-off-by: Subrata Banik <subrata.banik@intel.com> Original-Reviewed-on: https://review.coreboot.org/29507 Original-Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Original-Reviewed-by: Shelley Chen <shchen@google.com> Original-Reviewed-by: Furquan Shaikh <furquan@google.com> Original-Reviewed-by: Aamir Bohra <aamir.bohra@intel.com> Reviewed-on: https://chromium-review.googlesource.com/1340633 Commit-Ready: Patrick Georgi <pgeorgi@chromium.org> Tested-by: Patrick Georgi <pgeorgi@chromium.org> Reviewed-by: Patrick Georgi <pgeorgi@chromium.org> " fail_count="0" gerrit_number="1340633" owner_email="pgeorgi@chromium.org" pass_count="0" patch_number="1" project="chromiumos/third_party/coreboot" project_url="https://chromium-review.googlesource.com/chromiumos/third_party/coreboot" ref="refs/changes/33/1340633/1" remote="cros" total_fail_count="0"/><pending_commit branch="chromeos-2016.05" change_id="I1d5d489ad5e6a21fe73ce797d113df459e32065e" commit="287310408dcd8d5028e4e845d4722a8d4b3877c8" commit_message="UPSTREAM: mb/google/kahlee: Tune eDP panel initialization time 1. Add two parameters for panel initialization timing. > lvds_poseq_varybl_to_blon > lvds_poseq_blon_to_varybl 2. The BL_PWM is controlled by APU_EDP_BKLTEN_L/APU_DP_VARY_BL/ EDP_BKLTEN_L, so move APU_EDP_BKLTEN_L to early init stage, and be enabled depends on SKU, thus we can control the delay time by config APU_DP_VARY_BL. BUG=b:118011567 TEST=emerge-grunt coreboot. Change-Id: I1d5d489ad5e6a21fe73ce797d113df459e32065e Signed-off-by: Patrick Georgi <pgeorgi@google.com> Original-Commit-Id: 50c11607a1afaa373d381575c5056e4185a014c4 Original-Change-Id: Ib20c48813b208d697b950b2f02a70a690e483fdb Original-Signed-off-by: Chris Wang <chris.wang@amd.corp-partner.google.com> Original-Reviewed-on: https://review.coreboot.org/29469 Original-Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Original-Reviewed-by: Martin Roth <martinroth@google.com> Reviewed-on: https://chromium-review.googlesource.com/1340634 Commit-Ready: Patrick Georgi <pgeorgi@chromium.org> Tested-by: Patrick Georgi <pgeorgi@chromium.org> Reviewed-by: Patrick Georgi <pgeorgi@chromium.org> " fail_count="0" gerrit_number="1340634" owner_email="pgeorgi@chromium.org" pass_count="0" patch_number="1" project="chromiumos/third_party/coreboot" project_url="https://chromium-review.googlesource.com/chromiumos/third_party/coreboot" ref="refs/changes/34/1340634/1" remote="cros" total_fail_count="0"/><pending_commit branch="chromeos-2016.05" change_id="Ie782a97cb4ef525be0cf327150366803fc2cd8aa" commit="1ffaf2094317f86c5f2be6618b9d4512d54f3591" commit_message="UPSTREAM: mb/google/kahlee/variants/liara: Decrease eDP adjust time to 20 ms Add 20ms adjust timing for edp panel in devicetree. BUG=b:118011567 TEST=verify panel sequences by ODM. Change-Id: Ie782a97cb4ef525be0cf327150366803fc2cd8aa Signed-off-by: Patrick Georgi <pgeorgi@google.com> Original-Commit-Id: 05b7cab1d7042d82e98387d6fc5849ff2d4df9db Original-Change-Id: Iab46f6fc653047a1ec6e8528eefa0999d7019690 Original-Signed-off-by: Chris Wang <chris.wang@amd.corp-partner.google.com> Original-Reviewed-on: https://review.coreboot.org/29473 Original-Reviewed-by: Martin Roth <martinroth@google.com> Original-Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-on: https://chromium-review.googlesource.com/1340635 Commit-Ready: Patrick Georgi <pgeorgi@chromium.org> Tested-by: Patrick Georgi <pgeorgi@chromium.org> Reviewed-by: Patrick Georgi <pgeorgi@chromium.org> " fail_count="0" gerrit_number="1340635" owner_email="pgeorgi@chromium.org" pass_count="0" patch_number="1" project="chromiumos/third_party/coreboot" project_url="https://chromium-review.googlesource.com/chromiumos/third_party/coreboot" ref="refs/changes/35/1340635/1" remote="cros" total_fail_count="0"/><pending_commit branch="chromeos-2016.05" change_id="I150dfa7e4be4127d337ae188edb216fbb7630a24" commit="be6b1b24b2fe54ec971eb04d62759a6b05534ec7" commit_message="UPSTREAM: intel/i945: add timestamps in romstage It is able to do so if timestamps are initialized. BUG=none BRANCH=none TEST=none Change-Id: I150dfa7e4be4127d337ae188edb216fbb7630a24 Signed-off-by: Patrick Georgi <pgeorgi@google.com> Original-Commit-Id: 771328f7dff554fe06a2dc931097b0e129e2113f Original-Change-Id: Ic95313a19646b66dc1633fb680e54bfc61ec90be Original-Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Reviewed-on: https://review.coreboot.org/27330 Original-Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Original-Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org> Reviewed-on: https://chromium-review.googlesource.com/1340636 Commit-Ready: Patrick Georgi <pgeorgi@chromium.org> Tested-by: Patrick Georgi <pgeorgi@chromium.org> Reviewed-by: Patrick Georgi <pgeorgi@chromium.org> " fail_count="0" gerrit_number="1340636" owner_email="pgeorgi@chromium.org" pass_count="0" patch_number="1" project="chromiumos/third_party/coreboot" project_url="https://chromium-review.googlesource.com/chromiumos/third_party/coreboot" ref="refs/changes/36/1340636/1" remote="cros" total_fail_count="0"/><pending_commit branch="chromeos-2016.05" change_id="I6e5a386b0978c638ac16c5ba1cce2495b90b8305" commit="cf463f3dadc526be66dde75fea7d3bec1532e2ff" commit_message="UPSTREAM: include/program_loading: Add POSTCAR prog type Now postcar is a standalone stage give it a proper type. BUG=none BRANCH=none TEST=none Change-Id: I6e5a386b0978c638ac16c5ba1cce2495b90b8305 Signed-off-by: Patrick Georgi <pgeorgi@google.com> Original-Commit-Id: 01797b1737a687807a5a6076ec3bcf45a6bdc621 Original-Change-Id: Ifa6af9cf20aad27ca87a86817e6ad0a0d1de17c8 Original-Signed-off-by: Philipp Deppenwiese <zaolin.daisuki@gmail.com> Original-Reviewed-on: https://review.coreboot.org/29545 Original-Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Original-Reviewed-by: Werner Zeh <werner.zeh@siemens.com> Reviewed-on: https://chromium-review.googlesource.com/1340637 Commit-Ready: Patrick Georgi <pgeorgi@chromium.org> Tested-by: Patrick Georgi <pgeorgi@chromium.org> Reviewed-by: Patrick Georgi <pgeorgi@chromium.org> " fail_count="0" gerrit_number="1340637" owner_email="pgeorgi@chromium.org" pass_count="0" patch_number="1" project="chromiumos/third_party/coreboot" project_url="https://chromium-review.googlesource.com/chromiumos/third_party/coreboot" ref="refs/changes/37/1340637/1" remote="cros" total_fail_count="0"/><pending_commit branch="chromeos-2016.05" change_id="I97bb29fcf18e73e0a5ef9dbfee474fef1868e72f" commit="bfff8f4638f08e21d89acdb364668f4a5a3421fb" commit_message="UPSTREAM: drivers/*/tpm: Add postcar target Now postcar is a standalone stage, add it as target to all TPM bus drivers. This is a required for a measured boot. BUG=none BRANCH=none TEST=none Change-Id: I97bb29fcf18e73e0a5ef9dbfee474fef1868e72f Signed-off-by: Patrick Georgi <pgeorgi@google.com> Original-Commit-Id: 97fda101e3c996d52e8f1081eae13673941e0c80 Original-Change-Id: I758185daf3941a29883c2256b900360e112275e1 Original-Signed-off-by: Philipp Deppenwiese <zaolin.daisuki@gmail.com> Original-Reviewed-on: https://review.coreboot.org/29546 Original-Reviewed-by: Werner Zeh <werner.zeh@siemens.com> Original-Reviewed-by: Patrick Georgi <pgeorgi@google.com> Original-Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-on: https://chromium-review.googlesource.com/1340638 Commit-Ready: Patrick Georgi <pgeorgi@chromium.org> Tested-by: Patrick Georgi <pgeorgi@chromium.org> Reviewed-by: Patrick Georgi <pgeorgi@chromium.org> " fail_count="0" gerrit_number="1340638" owner_email="pgeorgi@chromium.org" pass_count="0" patch_number="1" project="chromiumos/third_party/coreboot" project_url="https://chromium-review.googlesource.com/chromiumos/third_party/coreboot" ref="refs/changes/38/1340638/1" remote="cros" total_fail_count="0"/><pending_commit branch="chromeos-2016.05" change_id="I4fe9ec350501e9bb83815b741e0bc8b575ec2b5e" commit="474d8c89f7f289d8e76af17fe33a909ea296f0f3" commit_message="UPSTREAM: mb/lenovo/t400: Improve docking code * Remove dead code * Add support for types 2504 and 2505 * Print dock info at romstage entry * Improve dock disconnect for type 2505 * Move defines into dock.h for future ACPI code * Reduce timeouts according to spec to decrease boot time on error * Fix no docking detection (reduces boot time by 1 second) * Configure GPIO LDN before reading GPIOs * Use Kconfig values instead of fixed defines * Add documentation Tested on Lenovo T500 with docking 2504 and 2505. BUG=none BRANCH=none TEST=none Change-Id: I4fe9ec350501e9bb83815b741e0bc8b575ec2b5e Signed-off-by: Patrick Georgi <pgeorgi@google.com> Original-Commit-Id: c0a1625df13ac9e95ca4de849ac52bb3af29c7b6 Original-Change-Id: Ic4510ffadc67da95961cecd51a6d8ed856b3ac99 Original-Signed-off-by: Patrick Rudolph <siro@das-labor.org> Original-Reviewed-on: https://review.coreboot.org/29418 Original-Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Original-Reviewed-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-on: https://chromium-review.googlesource.com/1341299 Commit-Ready: Patrick Georgi <pgeorgi@chromium.org> Tested-by: Patrick Georgi <pgeorgi@chromium.org> Reviewed-by: Patrick Georgi <pgeorgi@chromium.org> " fail_count="0" gerrit_number="1341299" owner_email="pgeorgi@chromium.org" pass_count="0" patch_number="1" project="chromiumos/third_party/coreboot" project_url="https://chromium-review.googlesource.com/chromiumos/third_party/coreboot" ref="refs/changes/99/1341299/1" remote="cros" total_fail_count="0"/><pending_commit branch="chromeos-2016.05" change_id="I9e3d967eca391ccc4135f5eeabf37c0422dd266f" commit="10509abf79fed4b1cd5969475d24fa2b27c3610c" commit_message="UPSTREAM: mb/emulation/qemu-i440fx|q35: Link memory.c Link memory.c instead of including it. BUG=none BRANCH=none TEST=none Change-Id: I9e3d967eca391ccc4135f5eeabf37c0422dd266f Signed-off-by: Patrick Georgi <pgeorgi@google.com> Original-Commit-Id: 69d5ef9d143afbd9904507dd02d32148c40c6474 Original-Change-Id: I2bc461b13332ec5885c33c87828a5fd023f8e730 Original-Signed-off-by: Patrick Rudolph <siro@das-labor.org> Original-Reviewed-on: https://review.coreboot.org/29574 Original-Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Original-Reviewed-by: Felix Held <felix-coreboot@felixheld.de> Original-Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://chromium-review.googlesource.com/1341300 Commit-Ready: Patrick Georgi <pgeorgi@chromium.org> Tested-by: Patrick Georgi <pgeorgi@chromium.org> Reviewed-by: Patrick Georgi <pgeorgi@chromium.org> " fail_count="0" gerrit_number="1341300" owner_email="pgeorgi@chromium.org" pass_count="0" patch_number="1" project="chromiumos/third_party/coreboot" project_url="https://chromium-review.googlesource.com/chromiumos/third_party/coreboot" ref="refs/changes/00/1341300/1" remote="cros" total_fail_count="0"/><pending_commit branch="chromeos-2016.05" change_id="I14c443c58fee268c859190f458eb1e77ce1d8685" commit="e0b6b877c6aa9159ff7df1637090e12515df2b5d" commit_message="UPSTREAM: siemens/mc_apl3: Adjust Legacy IRQ routing for PCI devices On this mainboard there is a legacy PCI device, which is connected to the PCIe root port via a PCIe-2-PCI bridge. This device only supports legacy interrupt routing. For this reason we have to adjust the PIR6 register (0x314c) which is responsible for PCIe device 13h and 14h. This means that the interrupt routing will also be the same for both PCIe devices. The bridge is connected to PCIe root port 2 and 3 over two lanes (Device 13.0 and 13.1). The following routing is required: INTA#->PIRQD#, INTB#->PIRQA#, INTC#->PIRQB#, INTD#->PIRQC# BUG=none BRANCH=none TEST=none Change-Id: I14c443c58fee268c859190f458eb1e77ce1d8685 Signed-off-by: Patrick Georgi <pgeorgi@google.com> Original-Commit-Id: 98689df18f7431c69cc0b53a53d083ab3cef28ce Original-Change-Id: I5028c26769a2122b1c609ad7789c9949e3cb7a87 Original-Signed-off-by: Mario Scheithauer <mario.scheithauer@siemens.com> Original-Reviewed-on: https://review.coreboot.org/29513 Original-Reviewed-by: Werner Zeh <werner.zeh@siemens.com> Original-Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-on: https://chromium-review.googlesource.com/1341301 Commit-Ready: Patrick Georgi <pgeorgi@chromium.org> Tested-by: Patrick Georgi <pgeorgi@chromium.org> Reviewed-by: Patrick Georgi <pgeorgi@chromium.org> " fail_count="0" gerrit_number="1341301" owner_email="pgeorgi@chromium.org" pass_count="0" patch_number="1" project="chromiumos/third_party/coreboot" project_url="https://chromium-review.googlesource.com/chromiumos/third_party/coreboot" ref="refs/changes/01/1341301/1" remote="cros" total_fail_count="0"/><pending_commit branch="chromeos-2016.05" change_id="I800c3cb2c656804399c99c024f3460229a6f7061" commit="0346e568f8615d473d29336031aae8aa9e8bb76c" commit_message="UPSTREAM: siemens/mc_apl3: Remove the correction of the Tx signal for SATA For this mainboard the correction of transmit voltage swing from SATA interface is not necessary. BUG=none BRANCH=none TEST=none Change-Id: I800c3cb2c656804399c99c024f3460229a6f7061 Signed-off-by: Patrick Georgi <pgeorgi@google.com> Original-Commit-Id: bcbcecd38ff6273bb9e8bf45da8e5f1578a72728 Original-Change-Id: I900d0d44b88585c223182d85c78cf3ff1e3e9159 Original-Signed-off-by: Mario Scheithauer <mario.scheithauer@siemens.com> Original-Reviewed-on: https://review.coreboot.org/29527 Original-Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Original-Reviewed-by: Werner Zeh <werner.zeh@siemens.com> Reviewed-on: https://chromium-review.googlesource.com/1341302 Commit-Ready: Patrick Georgi <pgeorgi@chromium.org> Tested-by: Patrick Georgi <pgeorgi@chromium.org> Reviewed-by: Patrick Georgi <pgeorgi@chromium.org> " fail_count="0" gerrit_number="1341302" owner_email="pgeorgi@chromium.org" pass_count="0" patch_number="1" project="chromiumos/third_party/coreboot" project_url="https://chromium-review.googlesource.com/chromiumos/third_party/coreboot" ref="refs/changes/02/1341302/1" remote="cros" total_fail_count="0"/><pending_commit branch="chromeos-2016.05" change_id="Id0de132c436bd7a7ec47fa53cb1e288dc51d36ac" commit="1f4f29202e2594cb34b240c7c2d26d69eb54885a" commit_message="UPSTREAM: siemens/mc_apl3: Set bus master bit for on-board PCI device There is an on-board PCI device where bus master has to be enabled in PCI configuration space. As there is no need for a complete PCI driver for this device just set the bus master bit in mainboard_final(). BUG=none BRANCH=none TEST=none Change-Id: Id0de132c436bd7a7ec47fa53cb1e288dc51d36ac Signed-off-by: Patrick Georgi <pgeorgi@google.com> Original-Commit-Id: d985cdc7638967889e586447fb58a9c14bf72c63 Original-Change-Id: I1ef4a7774d4ca75c230063debbc63d03486fed6f Original-Signed-off-by: Mario Scheithauer <mario.scheithauer@siemens.com> Original-Reviewed-on: https://review.coreboot.org/29528 Original-Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Original-Reviewed-by: Werner Zeh <werner.zeh@siemens.com> Reviewed-on: https://chromium-review.googlesource.com/1341303 Commit-Ready: Patrick Georgi <pgeorgi@chromium.org> Tested-by: Patrick Georgi <pgeorgi@chromium.org> Reviewed-by: Patrick Georgi <pgeorgi@chromium.org> " fail_count="0" gerrit_number="1341303" owner_email="pgeorgi@chromium.org" pass_count="0" patch_number="1" project="chromiumos/third_party/coreboot" project_url="https://chromium-review.googlesource.com/chromiumos/third_party/coreboot" ref="refs/changes/03/1341303/1" remote="cros" total_fail_count="0"/><pending_commit branch="chromeos-2016.05" change_id="I5fc6ecb07a09288e229a13406b9073a818306bfa" commit="c85f85c13d43c9e6a064f4f80c6f32dc69b6ca15" commit_message="UPSTREAM: siemens/mc_apl3: Set Full Reset Bit into Reset Control Register This mainboard provides customer hardware reset button. A feature of this button is that it holds the APL in reset state as long as the reset button is pressed. After releasing the reset button the APL should restart again without the need for a power cycle. When Bit 3 in Reset Control Register (I/O port CF9h) is set to 1 and then the reset button is pressed the PCH will drive SLP_S3 active (low). BUG=none BRANCH=none TEST=none Change-Id: I5fc6ecb07a09288e229a13406b9073a818306bfa Signed-off-by: Patrick Georgi <pgeorgi@google.com> Original-Commit-Id: 04ea73ee78bceb680a2565777c4c7774c2ad1a8e Original-Change-Id: Ib842f15b6ba14851d7f9b1b97c83389adc61f50b Original-Signed-off-by: Mario Scheithauer <mario.scheithauer@siemens.com> Original-Reviewed-on: https://review.coreboot.org/29530 Original-Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Original-Reviewed-by: Werner Zeh <werner.zeh@siemens.com> Reviewed-on: https://chromium-review.googlesource.com/1341304 Commit-Ready: Patrick Georgi <pgeorgi@chromium.org> Tested-by: Patrick Georgi <pgeorgi@chromium.org> Reviewed-by: Patrick Georgi <pgeorgi@chromium.org> " fail_count="0" gerrit_number="1341304" owner_email="pgeorgi@chromium.org" pass_count="0" patch_number="1" project="chromiumos/third_party/coreboot" project_url="https://chromium-review.googlesource.com/chromiumos/third_party/coreboot" ref="refs/changes/04/1341304/1" remote="cros" total_fail_count="0"/><pending_commit branch="chromeos-2016.05" change_id="I9f69695f44b623947c9651e47a0b8c7c4b7ced18" commit="2e394d774bdd897b51ee1cc37f33d5ed41b2480c" commit_message="UPSTREAM: siemens/mc_apl3: Disable PCI clock outputs on XIO bridges On this mainboard there are legacy PCI device, which are connected to different PCIe root ports via PCIe-2-PCI bridges. This patch disables the unused PCI clock outputs on the XIO2001 PCI Express to PCI Bridges. BUG=none BRANCH=none TEST=none Change-Id: I9f69695f44b623947c9651e47a0b8c7c4b7ced18 Signed-off-by: Patrick Georgi <pgeorgi@google.com> Original-Commit-Id: 4946804f0b6536df3e7a46654c0dbbc3172b1de8 Original-Change-Id: I2212c1080b72a656b5c8e68b040108a7adbec608 Original-Signed-off-by: Mario Scheithauer <mario.scheithauer@siemens.com> Original-Reviewed-on: https://review.coreboot.org/29549 Original-Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Original-Reviewed-by: Werner Zeh <werner.zeh@siemens.com> Reviewed-on: https://chromium-review.googlesource.com/1341305 Commit-Ready: Patrick Georgi <pgeorgi@chromium.org> Tested-by: Patrick Georgi <pgeorgi@chromium.org> Reviewed-by: Patrick Georgi <pgeorgi@chromium.org> " fail_count="0" gerrit_number="1341305" owner_email="pgeorgi@chromium.org" pass_count="0" patch_number="1" project="chromiumos/third_party/coreboot" project_url="https://chromium-review.googlesource.com/chromiumos/third_party/coreboot" ref="refs/changes/05/1341305/1" remote="cros" total_fail_count="0"/><pending_commit branch="chromeos-2016.05" change_id="I47ae7f168ff7ea3514b1a88f98b7ca634a7689bb" commit="23113a6e8a383e4aa1d07b9be9a0d87184998634" commit_message="UPSTREAM: siemens/mc_apl4: Disable CLKREQ of PCIe root ports All PCIe root ports of this mainboard do not have an associated CLKREQ signal. Therefore the ports are marked with "CLKREQ_DISABLED". BUG=none BRANCH=none TEST=none Change-Id: I47ae7f168ff7ea3514b1a88f98b7ca634a7689bb Signed-off-by: Patrick Georgi <pgeorgi@google.com> Original-Commit-Id: c27ce827dc788e2c34d72fcc43097d8e858e2f9f Original-Change-Id: I834b3b0c77223d81c950e27ccfff8e9aeece2aa4 Original-Signed-off-by: Mario Scheithauer <mario.scheithauer@siemens.com> Original-Reviewed-on: https://review.coreboot.org/29556 Original-Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Original-Reviewed-by: Werner Zeh <werner.zeh@siemens.com> Reviewed-on: https://chromium-review.googlesource.com/1341306 Commit-Ready: Patrick Georgi <pgeorgi@chromium.org> Tested-by: Patrick Georgi <pgeorgi@chromium.org> Reviewed-by: Patrick Georgi <pgeorgi@chromium.org> " fail_count="0" gerrit_number="1341306" owner_email="pgeorgi@chromium.org" pass_count="0" patch_number="1" project="chromiumos/third_party/coreboot" project_url="https://chromium-review.googlesource.com/chromiumos/third_party/coreboot" ref="refs/changes/06/1341306/1" remote="cros" total_fail_count="0"/><pending_commit branch="chromeos-2016.05" change_id="Ife7eb3421c35f794de1e92a4555493863b5f2eab" commit="a5db027184120eed3c0a8206ab1663669d5c0484" commit_message="UPSTREAM: siemens/mc_apl4: Remove reduced clock rate for I2C0 There is no device on I2C0 which requires a lower clock rate. BUG=none BRANCH=none TEST=none Change-Id: Ife7eb3421c35f794de1e92a4555493863b5f2eab Signed-off-by: Patrick Georgi <pgeorgi@google.com> Original-Commit-Id: fe7367801c3f6f0f876c6258aa924c085e19ed89 Original-Change-Id: Ib7c4e3251545b2d32368dd56206e3b4844a24800 Original-Signed-off-by: Mario Scheithauer <mario.scheithauer@siemens.com> Original-Reviewed-on: https://review.coreboot.org/29558 Original-Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Original-Reviewed-by: Werner Zeh <werner.zeh@siemens.com> Reviewed-on: https://chromium-review.googlesource.com/1341307 Commit-Ready: Patrick Georgi <pgeorgi@chromium.org> Tested-by: Patrick Georgi <pgeorgi@chromium.org> Reviewed-by: Patrick Georgi <pgeorgi@chromium.org> " fail_count="0" gerrit_number="1341307" owner_email="pgeorgi@chromium.org" pass_count="0" patch_number="1" project="chromiumos/third_party/coreboot" project_url="https://chromium-review.googlesource.com/chromiumos/third_party/coreboot" ref="refs/changes/07/1341307/1" remote="cros" total_fail_count="0"/><pending_commit branch="chromeos-2016.05" change_id="I45d1f9633eb3f604572d8a2b1cd00b7616a45be3" commit="46c30fd1a175b239ecad138fab65b9e912a13241" commit_message="UPSTREAM: siemens/mc_apl4: Enable all PCIe root ports Enable all PCIe root ports for this mainboard. BUG=none BRANCH=none TEST=none Change-Id: I45d1f9633eb3f604572d8a2b1cd00b7616a45be3 Signed-off-by: Patrick Georgi <pgeorgi@google.com> Original-Commit-Id: 3a499725f0fded9cba9b76816f469138149e00f8 Original-Change-Id: I7f6feb2f0d4c45f32d9454838e67e1a244b2712b Original-Signed-off-by: Mario Scheithauer <mario.scheithauer@siemens.com> Original-Reviewed-on: https://review.coreboot.org/29559 Original-Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Original-Reviewed-by: Werner Zeh <werner.zeh@siemens.com> Reviewed-on: https://chromium-review.googlesource.com/1341308 Commit-Ready: Patrick Georgi <pgeorgi@chromium.org> Tested-by: Patrick Georgi <pgeorgi@chromium.org> Reviewed-by: Patrick Georgi <pgeorgi@chromium.org> " fail_count="0" gerrit_number="1341308" owner_email="pgeorgi@chromium.org" pass_count="0" patch_number="1" project="chromiumos/third_party/coreboot" project_url="https://chromium-review.googlesource.com/chromiumos/third_party/coreboot" ref="refs/changes/08/1341308/1" remote="cros" total_fail_count="0"/><pending_commit branch="chromeos-2016.05" change_id="I54651829bad19dd721fcf32288fe88f04ede28a7" commit="6b2ee184e66979cff6a5e0e8bb6423286abbdf5c" commit_message="UPSTREAM: siemens/mc_apl4: Remove external RTC from I2C0 This mainboard also has an external RTC chip, but not on this bus. The topic is currently in clarification and will be published with a later patch. In a first step we enable all I2C busses. BUG=none BRANCH=none TEST=none Change-Id: I54651829bad19dd721fcf32288fe88f04ede28a7 Signed-off-by: Patrick Georgi <pgeorgi@google.com> Original-Commit-Id: adc7d8e6ec2f48eef026ac88a576d75e3b2f4df2 Original-Change-Id: I9ec9631ed15ab30cc6a4594531521f4a1419ad00 Original-Signed-off-by: Mario Scheithauer <mario.scheithauer@siemens.com> Original-Reviewed-on: https://review.coreboot.org/29560 Original-Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Original-Reviewed-by: Werner Zeh <werner.zeh@siemens.com> Reviewed-on: https://chromium-review.googlesource.com/1341309 Commit-Ready: Patrick Georgi <pgeorgi@chromium.org> Tested-by: Patrick Georgi <pgeorgi@chromium.org> Reviewed-by: Patrick Georgi <pgeorgi@chromium.org> " fail_count="0" gerrit_number="1341309" owner_email="pgeorgi@chromium.org" pass_count="0" patch_number="1" project="chromiumos/third_party/coreboot" project_url="https://chromium-review.googlesource.com/chromiumos/third_party/coreboot" ref="refs/changes/09/1341309/1" remote="cros" total_fail_count="0"/><pending_commit branch="chromeos-2016.05" change_id="I36d577d79c28256bd34443dde3cb69f8091dfbf1" commit="858bbcf206d01fca1435cb53a6bc1712059bd8d4" commit_message="UPSTREAM: siemens/mc_apl4: Enable SDCARD This mainboard also has a SD slot. BUG=none BRANCH=none TEST=none Change-Id: I36d577d79c28256bd34443dde3cb69f8091dfbf1 Signed-off-by: Patrick Georgi <pgeorgi@google.com> Original-Commit-Id: 5d6929772c956be36cc423a185652eb6486ba683 Original-Change-Id: Id56bc1be60ec8c2be0e5543d1d8851610b7248e0 Original-Signed-off-by: Mario Scheithauer <mario.scheithauer@siemens.com> Original-Reviewed-on: https://review.coreboot.org/29561 Original-Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Original-Reviewed-by: Werner Zeh <werner.zeh@siemens.com> Reviewed-on: https://chromium-review.googlesource.com/1341310 Commit-Ready: Patrick Georgi <pgeorgi@chromium.org> Tested-by: Patrick Georgi <pgeorgi@chromium.org> Reviewed-by: Patrick Georgi <pgeorgi@chromium.org> " fail_count="0" gerrit_number="1341310" owner_email="pgeorgi@chromium.org" pass_count="0" patch_number="1" project="chromiumos/third_party/coreboot" project_url="https://chromium-review.googlesource.com/chromiumos/third_party/coreboot" ref="refs/changes/10/1341310/1" remote="cros" total_fail_count="0"/><pending_commit branch="chromeos-2016.05" change_id="Ia74bcece2d272582b1c3ca294c8df3bf65716932" commit="1487b3188eda67f7f51be10b6087e42618dfe6d5" commit_message="UPSTREAM: mb/emulation/qemu-i440fx/Makefile.inc: Fix "No newline at end of file" BUG=none BRANCH=none TEST=none Change-Id: Ia74bcece2d272582b1c3ca294c8df3bf65716932 Signed-off-by: Patrick Georgi <pgeorgi@google.com> Original-Commit-Id: a9a1913d4d3f27f681b6ef980f064b57da8c1a68 Original-Change-Id: I79e9b95059f16c53767c89cfaef1e89182be9c62 Original-Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Original-Reviewed-on: https://review.coreboot.org/29583 Original-Reviewed-by: Patrick Georgi <pgeorgi@google.com> Original-Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-on: https://chromium-review.googlesource.com/1341311 Commit-Ready: Patrick Georgi <pgeorgi@chromium.org> Tested-by: Patrick Georgi <pgeorgi@chromium.org> Reviewed-by: Patrick Georgi <pgeorgi@chromium.org> " fail_count="0" gerrit_number="1341311" owner_email="pgeorgi@chromium.org" pass_count="0" patch_number="1" project="chromiumos/third_party/coreboot" project_url="https://chromium-review.googlesource.com/chromiumos/third_party/coreboot" ref="refs/changes/11/1341311/1" remote="cros" total_fail_count="0"/><pending_commit branch="chromeos-2016.05" change_id="If76cef48d7bb5037b0a5ef66f1dee9ebe38fc29a" commit="ccbb28373a9cc02884e5e0cb6d568dae68ab4ce0" commit_message="UPSTREAM: src: Remove unneeded include "{arch,cpu}/cpu.h" BUG=none BRANCH=none TEST=none Change-Id: If76cef48d7bb5037b0a5ef66f1dee9ebe38fc29a Signed-off-by: Patrick Georgi <pgeorgi@google.com> Original-Commit-Id: d2b9ec13622d34714b4ecf8b9daf53b32665d3d7 Original-Change-Id: I17c4fc4e3e2eeef7c720c6a020b37d8f7a0f57a4 Original-Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Original-Reviewed-on: https://review.coreboot.org/29300 Original-Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Original-Reviewed-by: Patrick Georgi <pgeorgi@google.com> Reviewed-on: https://chromium-review.googlesource.com/1341312 Commit-Ready: Patrick Georgi <pgeorgi@chromium.org> Tested-by: Patrick Georgi <pgeorgi@chromium.org> Reviewed-by: Patrick Georgi <pgeorgi@chromium.org> " fail_count="0" gerrit_number="1341312" owner_email="pgeorgi@chromium.org" pass_count="0" patch_number="1" project="chromiumos/third_party/coreboot" project_url="https://chromium-review.googlesource.com/chromiumos/third_party/coreboot" ref="refs/changes/12/1341312/1" remote="cros" total_fail_count="0"/><pending_commit branch="chromeos-2016.05" change_id="Ie7d9c49b06fa996de7b9855a41967cf244888619" commit="b046666a6e1c8539af587a381750610eb697b3bb" commit_message="UPSTREAM: intel/i945: Factor out ram init time stamps Instead of having the code for the RAM init time stamps in each mainboards `romstage.c`, factor it out to the northbridge code, done in commit 771328f7 (intel/i945: add timestamps in romstage). BUG=none BRANCH=none TEST=none Change-Id: Ie7d9c49b06fa996de7b9855a41967cf244888619 Signed-off-by: Patrick Georgi <pgeorgi@google.com> Original-Commit-Id: 81dd52b7eb663c6098de5d8c7c56ed572c91b539 Original-Change-Id: Ibb699a1fea2f0b1f3c6564d401542d2fb3249f5a Original-Signed-off-by: Paul Menzel <paulepanter@users.sourceforge.net> Original-Reviewed-on: https://review.coreboot.org/17994 Original-Reviewed-by: Elyes HAOUAS <ehaouas@noos.fr> Original-Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-on: https://chromium-review.googlesource.com/1341313 Commit-Ready: Patrick Georgi <pgeorgi@chromium.org> Tested-by: Patrick Georgi <pgeorgi@chromium.org> Reviewed-by: Patrick Georgi <pgeorgi@chromium.org> " fail_count="0" gerrit_number="1341313" owner_email="pgeorgi@chromium.org" pass_count="0" patch_number="1" project="chromiumos/third_party/coreboot" project_url="https://chromium-review.googlesource.com/chromiumos/third_party/coreboot" ref="refs/changes/13/1341313/1" remote="cros" total_fail_count="0"/><pending_commit branch="chromeos-2016.05" change_id="I34d77c904a6ef990599a967ca98111a6cd317b9b" commit="d954ee1bb3a9d8cdb497959e2124138b9b95eb34" commit_message="UPSTREAM: mb/*/*: Harmonise FD and devicetree on boards featuring ICH7 On some boards the devicetree and Function Disable register did not match. In this case the FD values are put in the devicetree as these were the values that were actually used in practice. A complete devicetree will make it easier to automatically disable devices in ramstage. BUG=none BRANCH=none TEST=none Change-Id: I34d77c904a6ef990599a967ca98111a6cd317b9b Signed-off-by: Patrick Georgi <pgeorgi@google.com> Original-Commit-Id: b9d2589ca40026b543ecb5b008ce0d1bc346bf53 Original-Change-Id: I1692ca5f490ea84e2fc520d3f66044ad7514f76e Original-Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Original-Reviewed-on: https://review.coreboot.org/27122 Original-Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Original-Reviewed-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-on: https://chromium-review.googlesource.com/1341314 Commit-Ready: Patrick Georgi <pgeorgi@chromium.org> Tested-by: Patrick Georgi <pgeorgi@chromium.org> Reviewed-by: Patrick Georgi <pgeorgi@chromium.org> " fail_count="0" gerrit_number="1341314" owner_email="pgeorgi@chromium.org" pass_count="0" patch_number="1" project="chromiumos/third_party/coreboot" project_url="https://chromium-review.googlesource.com/chromiumos/third_party/coreboot" ref="refs/changes/14/1341314/1" remote="cros" total_fail_count="0"/><pending_commit branch="chromeos-2016.05" change_id="Ifa37841531cf4a2bb3addbb8e7335b089827da38" commit="69a86c48225a491bd6d03d1d14dea3de1acf2bd8" commit_message="UPSTREAM: mb/emulation/qemu-i440fx|q35: Get rid of unused headers BUG=none BRANCH=none TEST=none Change-Id: Ifa37841531cf4a2bb3addbb8e7335b089827da38 Signed-off-by: Patrick Georgi <pgeorgi@google.com> Original-Commit-Id: 7665aefb0ad216ee76307193b849834eac7b1f88 Original-Change-Id: I3cf0e4ef5b090d15ad823747fcf9219644e130fc Original-Signed-off-by: Patrick Rudolph <siro@das-labor.org> Original-Reviewed-on: https://review.coreboot.org/29577 Original-Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Original-Reviewed-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-on: https://chromium-review.googlesource.com/1341315 Commit-Ready: Patrick Georgi <pgeorgi@chromium.org> Tested-by: Patrick Georgi <pgeorgi@chromium.org> Reviewed-by: Patrick Georgi <pgeorgi@chromium.org> " fail_count="0" gerrit_number="1341315" owner_email="pgeorgi@chromium.org" pass_count="0" patch_number="1" project="chromiumos/third_party/coreboot" project_url="https://chromium-review.googlesource.com/chromiumos/third_party/coreboot" ref="refs/changes/15/1341315/1" remote="cros" total_fail_count="0"/><pending_commit branch="chromeos-2016.05" change_id="Ifd41bfacb71f123582a55491821f56d4d2d59e4d" commit="ed4a1c91ce6317020e557ccf7fab9fd7ccf7fd0f" commit_message="UPSTREAM: mb/emulation/qemu-i440fx|q35: Switch to C_ENVIRONMENT_BOOTBLOCK Useful for testing stuff in C_ENVIRONMENT_BOOTBLOCK, like VBOOT with separate verstage. Changes: * Use symbols to set up CAR and STACK * Zero CAR area * Move BIST failure checking to cpu folder * Rename functions where necessary Tested: * qemu-2.11.2 machine pc * qemu-2.11.2 machine q35 Test result: * BIST error reporting is still working. * Console starts in bootblock * SeaBios 1.11.2 as payload is still working BUG=none BRANCH=none TEST=none Change-Id: Ifd41bfacb71f123582a55491821f56d4d2d59e4d Signed-off-by: Patrick Georgi <pgeorgi@google.com> Original-Commit-Id: 1af89237094246216c6f60d77d74690a39907999 Original-Change-Id: Ibf341002c36d868b9b44c8b37381fa78ae5c4381 Original-Signed-off-by: Patrick Rudolph <siro@das-labor.org> Original-Reviewed-on: https://review.coreboot.org/29578 Original-Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Original-Reviewed-by: Patrick Georgi <pgeorgi@google.com> Reviewed-on: https://chromium-review.googlesource.com/1341316 Commit-Ready: Patrick Georgi <pgeorgi@chromium.org> Tested-by: Patrick Georgi <pgeorgi@chromium.org> Reviewed-by: Patrick Georgi <pgeorgi@chromium.org> " fail_count="0" gerrit_number="1341316" owner_email="pgeorgi@chromium.org" pass_count="0" patch_number="1" project="chromiumos/third_party/coreboot" project_url="https://chromium-review.googlesource.com/chromiumos/third_party/coreboot" ref="refs/changes/16/1341316/1" remote="cros" total_fail_count="0"/><pending_commit branch="chromeos-2016.05" change_id="Id84fbee258d18c8d002c7e013a26078838282064" commit="c5454a36edcfb095848296668f1829f369aaddeb" commit_message="UPSTREAM: util/intelvbttool: Cleanup and fixes * Clear remalloced memory * Fix check for invalid VBT offset in header * Fix VBIOS checksum generation * Fix VBIOS size field * Align VBIOS size to multiple of 512 * Reassign pointers after use of remalloc * Don't leak on error path Current version is enough to allow the proprietary Windows Intel GMA driver to find the VBT in the legacy VBIOS area and it doesn't BSOD any more. The LVDS screen remains black, due to an unknown issue with the proprietary driver, while the VGA works. Tested with libgfxinit and native graphics init. BUG=none BRANCH=none TEST=none Change-Id: Id84fbee258d18c8d002c7e013a26078838282064 Signed-off-by: Patrick Georgi <pgeorgi@google.com> Original-Commit-Id: aece006b38d7ee166f35b8affca4c2f02fd501f9 Original-Change-Id: If07b1bb51d8fb3499d13102f70fedb36c020fb72 Original-Signed-off-by: Patrick Rudolph <siro@das-labor.org> Original-Reviewed-on: https://review.coreboot.org/29099 Original-Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Original-Reviewed-by: Patrick Georgi <pgeorgi@google.com> Reviewed-on: https://chromium-review.googlesource.com/1341317 Commit-Ready: Patrick Georgi <pgeorgi@chromium.org> Tested-by: Patrick Georgi <pgeorgi@chromium.org> Reviewed-by: Patrick Georgi <pgeorgi@chromium.org> " fail_count="0" gerrit_number="1341317" owner_email="pgeorgi@chromium.org" pass_count="0" patch_number="1" project="chromiumos/third_party/coreboot" project_url="https://chromium-review.googlesource.com/chromiumos/third_party/coreboot" ref="refs/changes/17/1341317/1" remote="cros" total_fail_count="0"/><pending_commit branch="chromeos-2016.05" change_id="I7af5ddce955095128bbf6a847a7a8dba8e3a721f" commit="bbb41f558f9391cdd4279288064717070a9e3607" commit_message="UPSTREAM: mb/google/octopus/var/bobba: Configure EC_SYNC IRQ as level-triggered This change updates the configuration of EC_SYNC IRQ to be level triggered to match the EC behavior. BUG=none BRANCH=none TEST=none Change-Id: I7af5ddce955095128bbf6a847a7a8dba8e3a721f Signed-off-by: Patrick Georgi <pgeorgi@google.com> Original-Commit-Id: 670cd7016460e98627014e011cee34a92a8b4c5d Original-Change-Id: I8e3cb2ae8016ea183d9067697aa5d4b9caa2d07e Original-Signed-off-by: Furquan Shaikh <furquan@google.com> Original-Reviewed-on: https://review.coreboot.org/29576 Original-Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Original-Reviewed-by: Duncan Laurie <dlaurie@chromium.org> Original-Reviewed-by: Karthik Ramasubramanian <kramasub@google.com> Reviewed-on: https://chromium-review.googlesource.com/1341318 Commit-Ready: Patrick Georgi <pgeorgi@chromium.org> Tested-by: Patrick Georgi <pgeorgi@chromium.org> Reviewed-by: Patrick Georgi <pgeorgi@chromium.org> " fail_count="0" gerrit_number="1341318" owner_email="pgeorgi@chromium.org" pass_count="0" patch_number="1" project="chromiumos/third_party/coreboot" project_url="https://chromium-review.googlesource.com/chromiumos/third_party/coreboot" ref="refs/changes/18/1341318/1" remote="cros" total_fail_count="0"/><pending_commit branch="chromeos-2016.05" change_id="I1e23d42c61c47148d8e182db5f7f7a1bad098479" commit="5accfb451ea86c36ef76c58d5bf28f69998b0f35" commit_message="UPSTREAM: util/scripts/maintainers.go: Stub support for website tag ME Cleaner's component has an entry specifying its website, which this parser didn't know how to handle. Avoid the resulting warning. While at it, de-C the switch statement and make it work go-style. This also fixes "R" statements being ignored. BUG=none BRANCH=none TEST=none Change-Id: I1e23d42c61c47148d8e182db5f7f7a1bad098479 Signed-off-by: Patrick Georgi <pgeorgi@google.com> Original-Commit-Id: 92332635bf6b36c0db771aa9bc775e338507702b Original-Change-Id: Ifc23e28daba9d85bf690557a80134accea8bed21 Original-Signed-off-by: Patrick Georgi <pgeorgi@google.com> Original-Reviewed-on: https://review.coreboot.org/29601 Original-Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Original-Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org> Original-Reviewed-by: Philipp Deppenwiese <zaolin.daisuki@gmail.com> Reviewed-on: https://chromium-review.googlesource.com/1341319 Commit-Ready: Patrick Georgi <pgeorgi@chromium.org> Tested-by: Patrick Georgi <pgeorgi@chromium.org> Reviewed-by: Patrick Georgi <pgeorgi@chromium.org> " fail_count="0" gerrit_number="1341319" owner_email="pgeorgi@chromium.org" pass_count="0" patch_number="1" project="chromiumos/third_party/coreboot" project_url="https://chromium-review.googlesource.com/chromiumos/third_party/coreboot" ref="refs/changes/19/1341319/1" remote="cros" total_fail_count="0"/><pending_commit branch="chromeos-2016.05" change_id="I7ff225d972f7dadb8e1dcbb939849ee0c3668fb3" commit="1a88f822238fb568fad594f0b6b3c7bf0ba41d74" commit_message="UPSTREAM: soc/intel/common: Add option to call EC _PTS/_WAK methods Some embedded controllers expect to be sent a command when the OS calls the ACPI \_PTS and \_WAK methods. For example see the code in ec/google/wilco/acpi/platform.asl that tells the EC when the methods have been executed by the OS. Not all ECs may define these methods so this change requires also setting a Kconfig option to enable it. BUG=none BRANCH=none TEST=none Change-Id: I7ff225d972f7dadb8e1dcbb939849ee0c3668fb3 Signed-off-by: Patrick Georgi <pgeorgi@google.com> Original-Commit-Id: 0dd913510af40d4f230130722cf0f6a755e955d8 Original-Change-Id: I6bf83509423c0fb07c4890986a189cf54afaed10 Original-Signed-off-by: Duncan Laurie <dlaurie@google.com> Original-Reviewed-on: https://review.coreboot.org/29487 Original-Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Original-Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-on: https://chromium-review.googlesource.com/1341320 Commit-Ready: Patrick Georgi <pgeorgi@chromium.org> Tested-by: Patrick Georgi <pgeorgi@chromium.org> Reviewed-by: Patrick Georgi <pgeorgi@chromium.org> " fail_count="0" gerrit_number="1341320" owner_email="pgeorgi@chromium.org" pass_count="0" patch_number="1" project="chromiumos/third_party/coreboot" project_url="https://chromium-review.googlesource.com/chromiumos/third_party/coreboot" ref="refs/changes/20/1341320/1" remote="cros" total_fail_count="0"/><pending_commit branch="chromeos-2016.05" change_id="I4512f50807e138332f37d0e160c63b7bce319955" commit="aaa75c19a5765d0efcf2e1277da3e9384f864ec7" commit_message="UPSTREAM: mb/opencellular/rotundu: Remove unused CACHE_ROM_SIZE_OVERRIDE BUG=none BRANCH=none TEST=none Change-Id: I4512f50807e138332f37d0e160c63b7bce319955 Signed-off-by: Patrick Georgi <pgeorgi@google.com> Original-Commit-Id: d913d490b50b583d3c86bc532a17c042ae2bef81 Original-Change-Id: If77c23fc5d440fe9181e4aae72ffff8ddaa716b6 Original-Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Original-Reviewed-on: https://review.coreboot.org/29588 Original-Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Original-Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://chromium-review.googlesource.com/1341321 Commit-Ready: Patrick Georgi <pgeorgi@chromium.org> Tested-by: Patrick Georgi <pgeorgi@chromium.org> Reviewed-by: Patrick Georgi <pgeorgi@chromium.org> " fail_count="0" gerrit_number="1341321" owner_email="pgeorgi@chromium.org" pass_count="0" patch_number="1" project="chromiumos/third_party/coreboot" project_url="https://chromium-review.googlesource.com/chromiumos/third_party/coreboot" ref="refs/changes/21/1341321/1" remote="cros" total_fail_count="0"/><pending_commit branch="chromeos-2016.05" change_id="I2b9653d2c9f341572adfc8c7c1ac48d2b9280880" commit="cc854f0b69741e205f45a4aaf08cb9d5dac46ed5" commit_message="UPSTREAM: soc/intel/icelake: Update GPIOs for Icelake SOC This implementation updates the GPIO pins, communities and group mapping. Change details: 1. Update 5 GPIO community includes 11 GPIO groups GPIO COM 0 GPP_G, GPP_B, GPP_A GPIO COM 1 GPP_H, GPP_D, GPP_F GPIO COM 2 GPD GPIO COM 4 GPP_C, GPP_E GPIO COM 5 GPP_R, GPP_S 2. Update GPIO IRQ routing. 3. Add GPIO configuration for iclrvp board. BUG=none BRANCH=none TEST=none Change-Id: I2b9653d2c9f341572adfc8c7c1ac48d2b9280880 Signed-off-by: Patrick Georgi <pgeorgi@google.com> Original-Commit-Id: 6efa5c38460b28d650231429ae4fc9a0be7fddba Original-Change-Id: I223abacc18f78631a42f340952f13d45fa9a4703 Original-Signed-off-by: Subrata Banik <subrata.banik@intel.com> Original-Signed-off-by: Aamir Bohra <aamir.bohra@intel.com> Original-Reviewed-on: https://review.coreboot.org/29495 Original-Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Original-Reviewed-by: Shelley Chen <shchen@google.com> Reviewed-on: https://chromium-review.googlesource.com/1341322 Commit-Ready: Patrick Georgi <pgeorgi@chromium.org> Tested-by: Patrick Georgi <pgeorgi@chromium.org> Reviewed-by: Patrick Georgi <pgeorgi@chromium.org> " fail_count="0" gerrit_number="1341322" owner_email="pgeorgi@chromium.org" pass_count="0" patch_number="1" project="chromiumos/third_party/coreboot" project_url="https://chromium-review.googlesource.com/chromiumos/third_party/coreboot" ref="refs/changes/22/1341322/1" remote="cros" total_fail_count="0"/><pending_commit branch="chromeos-2016.05" change_id="If7b573c4b330e19534321aa899262cae17f3d088" commit="e15b58016273f15fc022a84916572a599e860e5e" commit_message="UPSTREAM: mb/cannonlake: Remove SmbusEnable from devicetree Remove the SmbusEnable parameter from all Cannon Lake mainboards. Instead this will be determined by the enable state of the SMBUS PCI device. BUG=none BRANCH=none TEST=none Change-Id: If7b573c4b330e19534321aa899262cae17f3d088 Signed-off-by: Patrick Georgi <pgeorgi@google.com> Original-Commit-Id: 98456f4ee6e1d7df2863e2fafe8e505522a48da8 Original-Change-Id: I7ece6768da4c517747af12a07012583575816ae1 Original-Signed-off-by: Duncan Laurie <dlaurie@google.com> Original-Reviewed-on: https://review.coreboot.org/29551 Original-Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Original-Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-on: https://chromium-review.googlesource.com/1341323 Commit-Ready: Patrick Georgi <pgeorgi@chromium.org> Tested-by: Patrick Georgi <pgeorgi@chromium.org> Reviewed-by: Patrick Georgi <pgeorgi@chromium.org> " fail_count="0" gerrit_number="1341323" owner_email="pgeorgi@chromium.org" pass_count="0" patch_number="1" project="chromiumos/third_party/coreboot" project_url="https://chromium-review.googlesource.com/chromiumos/third_party/coreboot" ref="refs/changes/23/1341323/1" remote="cros" total_fail_count="0"/><pending_commit branch="chromeos-2016.05" change_id="Ife227a2ee293ef286f1544f0e0ecfeff6b298199" commit="cb84d816609bf2474b27ada90a49a1527272460a" commit_message="UPSTREAM: soc/intel/cannonlake: Remove SmbusEnable Remove the SmbusEnable config option from devicetree and instead use the state of the PCI device to determine if it should be enabled or disabled. BUG=none BRANCH=none TEST=none Change-Id: Ife227a2ee293ef286f1544f0e0ecfeff6b298199 Signed-off-by: Patrick Georgi <pgeorgi@google.com> Original-Commit-Id: 25b387a50b25ceaaca29cf94eb02582a0d0e390a Original-Change-Id: Id362009e4c8e91699d1ca9bb3c2614e21cfc462a Original-Signed-off-by: Duncan Laurie <dlaurie@google.com> Original-Reviewed-on: https://review.coreboot.org/29552 Original-Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Original-Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-on: https://chromium-review.googlesource.com/1341324 Commit-Ready: Patrick Georgi <pgeorgi@chromium.org> Tested-by: Patrick Georgi <pgeorgi@chromium.org> Reviewed-by: Patrick Georgi <pgeorgi@chromium.org> " fail_count="0" gerrit_number="1341324" owner_email="pgeorgi@chromium.org" pass_count="0" patch_number="1" project="chromiumos/third_party/coreboot" project_url="https://chromium-review.googlesource.com/chromiumos/third_party/coreboot" ref="refs/changes/24/1341324/1" remote="cros" total_fail_count="0"/><pending_commit branch="chromeos-2016.05" change_id="I7af6929cf0e0b2c1251d2dbe758f5afe5a462dc0" commit="6fc29f9d95a4e0251aa1f70f0d3222a4c7ee6eb9" commit_message="UPSTREAM: drivers/elog: Group event log state information Group event log state information together to manage them better during different stages of coreboot. BUG=b:117884485 BRANCH=None TEST=Add an event log from romstage, boot to ChromeOS Change-Id: I7af6929cf0e0b2c1251d2dbe758f5afe5a462dc0 Signed-off-by: Patrick Georgi <pgeorgi@google.com> Original-Commit-Id: 07bc08c2995b535b554a54e48673c144650fb234 Original-Change-Id: I62792c0f5063c89ad11b512f1777c7ab8a2c13e5 Original-Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com> Original-Reviewed-on: https://review.coreboot.org/29541 Original-Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Original-Reviewed-by: Furquan Shaikh <furquan@google.com> Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/1341325 Commit-Ready: Patrick Georgi <pgeorgi@chromium.org> Tested-by: Patrick Georgi <pgeorgi@chromium.org> Reviewed-by: Patrick Georgi <pgeorgi@chromium.org> " fail_count="0" gerrit_number="1341325" owner_email="pgeorgi@chromium.org" pass_count="0" patch_number="1" project="chromiumos/third_party/coreboot" project_url="https://chromium-review.googlesource.com/chromiumos/third_party/coreboot" ref="refs/changes/25/1341325/1" remote="cros" total_fail_count="0"/><pending_commit branch="chromeos-2016.05" change_id="I2f9f62426fb2fe1bdbce30e40f93eea2749352f9" commit="83bdf195a66c19448906d859e7a47d4df427142c" commit_message="UPSTREAM: drivers/elog: Add Ramstage helper to add boot count Add a helper function specific to ramstage to add the boot count information into event log at ramstage. BUG=b:117884485 BRANCH=None TEST=Add an event log from romstage, boot to ChromeOS Change-Id: I2f9f62426fb2fe1bdbce30e40f93eea2749352f9 Signed-off-by: Patrick Georgi <pgeorgi@google.com> Original-Commit-Id: cca1f371d2c1f775fce69e526a20bd424a4aecb8 Original-Change-Id: Ic79f1a702548d8a2cd5c13175a9b2d718527953f Original-Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com> Original-Reviewed-on: https://review.coreboot.org/29542 Original-Reviewed-by: Furquan Shaikh <furquan@google.com> Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> Original-Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-on: https://chromium-review.googlesource.com/1341326 Commit-Ready: Patrick Georgi <pgeorgi@chromium.org> Tested-by: Patrick Georgi <pgeorgi@chromium.org> Reviewed-by: Patrick Georgi <pgeorgi@chromium.org> " fail_count="0" gerrit_number="1341326" owner_email="pgeorgi@chromium.org" pass_count="0" patch_number="1" project="chromiumos/third_party/coreboot" project_url="https://chromium-review.googlesource.com/chromiumos/third_party/coreboot" ref="refs/changes/26/1341326/1" remote="cros" total_fail_count="0"/><pending_commit branch="chromeos-2016.05" change_id="Ie3701c47c2de95d596b467d24e53c502d594fdc7" commit="43212886a18fb743adcb218fc497e027d126ace3" commit_message="UPSTREAM: util/scrips/maintainers.go: Allow file to appear in multiple components Without this change, the tool only reports the first hit. We want to see all of them. BUG=none BRANCH=none TEST=none Change-Id: Ie3701c47c2de95d596b467d24e53c502d594fdc7 Signed-off-by: Patrick Georgi <pgeorgi@google.com> Original-Commit-Id: 2e5d6a8153756fe036c9eba54fbd7a6c87b157b8 Original-Change-Id: Ib59b13c50b61c48e3cb200bf57e28c9453590819 Original-Signed-off-by: Patrick Georgi <pgeorgi@google.com> Original-Reviewed-on: https://review.coreboot.org/29602 Original-Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Original-Reviewed-by: Philipp Deppenwiese <zaolin.daisuki@gmail.com> Reviewed-on: https://chromium-review.googlesource.com/1341327 Commit-Ready: Patrick Georgi <pgeorgi@chromium.org> Tested-by: Patrick Georgi <pgeorgi@chromium.org> Reviewed-by: Patrick Georgi <pgeorgi@chromium.org> " fail_count="0" gerrit_number="1341327" owner_email="pgeorgi@chromium.org" pass_count="0" patch_number="1" project="chromiumos/third_party/coreboot" project_url="https://chromium-review.googlesource.com/chromiumos/third_party/coreboot" ref="refs/changes/27/1341327/1" remote="cros" total_fail_count="0"/><pending_commit branch="chromeos-2016.05" change_id="If9d5b20f448acc8806dd4ebe0fc4c05129a1ed0e" commit="af1da6a5d264c00736e310ce9eb108cac2d91cab" commit_message="UPSTREAM: util/scripts/maintainers.go: Use a full glob parser Instead of checking only for three cases, just use a glob parser (that translates the glob to regex). After that, maintainers src/arch/x86/memlayout.h emits: src/arch/x86/memlayout.h is in subsystem X86 ARCHITECTURE Maintainers: [] src/arch/x86/memlayout.h is in subsystem MEMLAYOUT Maintainers: [Julius Werner <jwerner@chromium.org>] The latter entry was invisible to the maintainers tool because its path description wasn't in one of the supported formats. BUG=none BRANCH=none TEST=none Change-Id: If9d5b20f448acc8806dd4ebe0fc4c05129a1ed0e Signed-off-by: Patrick Georgi <pgeorgi@google.com> Original-Commit-Id: 0cadafaac964fd602060658fda5724156f6c64f7 Original-Change-Id: I7e5cf4269415269552e35f2c73952ce3dff487e1 Original-Signed-off-by: Patrick Georgi <pgeorgi@google.com> Original-Reviewed-on: https://review.coreboot.org/29603 Original-Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Original-Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org> Reviewed-on: https://chromium-review.googlesource.com/1341328 Commit-Ready: Patrick Georgi <pgeorgi@chromium.org> Tested-by: Patrick Georgi <pgeorgi@chromium.org> Reviewed-by: Patrick Georgi <pgeorgi@chromium.org> " fail_count="0" gerrit_number="1341328" owner_email="pgeorgi@chromium.org" pass_count="0" patch_number="1" project="chromiumos/third_party/coreboot" project_url="https://chromium-review.googlesource.com/chromiumos/third_party/coreboot" ref="refs/changes/28/1341328/1" remote="cros" total_fail_count="0"/><pending_commit branch="chromeos-2016.05" change_id="I7d7ef612d4e3e1b2884928d60a42b75e589b5671" commit="a3dae449ce52ae6d80db126a093c96f7919395ea" commit_message="UPSTREAM: util/scripts/maintainers.go: Provide delimiters between maintainers Help automated tools make sense of the output. Instead of "[name 1 <email> name 2 <email>]", it now prints "name 1 <email>, name 2 <email>". As long as there are no commas in the maintainer names, they can be split easily. BUG=none BRANCH=none TEST=none Change-Id: I7d7ef612d4e3e1b2884928d60a42b75e589b5671 Signed-off-by: Patrick Georgi <pgeorgi@google.com> Original-Commit-Id: 89bd4892b3f0dc2039bf1d02eabce5c7f1825585 Original-Change-Id: I4a254f566404b081a08923bc7ceb49f02039aa2a Original-Signed-off-by: Patrick Georgi <pgeorgi@google.com> Original-Reviewed-on: https://review.coreboot.org/29604 Original-Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org> Original-Reviewed-by: Ronald G. Minnich <rminnich@gmail.com> Original-Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-on: https://chromium-review.googlesource.com/1341329 Commit-Ready: Patrick Georgi <pgeorgi@chromium.org> Tested-by: Patrick Georgi <pgeorgi@chromium.org> Reviewed-by: Patrick Georgi <pgeorgi@chromium.org> " fail_count="0" gerrit_number="1341329" owner_email="pgeorgi@chromium.org" pass_count="0" patch_number="1" project="chromiumos/third_party/coreboot" project_url="https://chromium-review.googlesource.com/chromiumos/third_party/coreboot" ref="refs/changes/29/1341329/1" remote="cros" total_fail_count="0"/><pending_commit branch="chromeos-2016.05" change_id="I359186daeede86cceb957d29c87d2697895a8065" commit="1682089dc5926dfcbb7f9f3ed5a5b07a245a76ed" commit_message="UPSTREAM: util/scripts/maintainers.go: Introduce command line argument handling First new option is -debug. BUG=none BRANCH=none TEST=none Change-Id: I359186daeede86cceb957d29c87d2697895a8065 Signed-off-by: Patrick Georgi <pgeorgi@google.com> Original-Commit-Id: 62a27385fdf770113972793bfffa8514d602144d Original-Change-Id: Ia6e9b3675449a0b1e6f5d7526ee999f925eaadb2 Original-Signed-off-by: Patrick Georgi <pgeorgi@google.com> Original-Reviewed-on: https://review.coreboot.org/29606 Original-Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Original-Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org> Reviewed-on: https://chromium-review.googlesource.com/1341330 Commit-Ready: Patrick Georgi <pgeorgi@chromium.org> Tested-by: Patrick Georgi <pgeorgi@chromium.org> Reviewed-by: Patrick Georgi <pgeorgi@chromium.org> " fail_count="0" gerrit_number="1341330" owner_email="pgeorgi@chromium.org" pass_count="0" patch_number="1" project="chromiumos/third_party/coreboot" project_url="https://chromium-review.googlesource.com/chromiumos/third_party/coreboot" ref="refs/changes/30/1341330/1" remote="cros" total_fail_count="0"/><pending_commit branch="chromeos-2016.05" change_id="Ia503aa158fc99e8502f4321f2173a269804a73db" commit="04ae5e59d24f1a768485b2fb0b3f0521b34819eb" commit_message="UPSTREAM: util/scripts/maintainers.go: Add Gerrit reviewers config emitter The gerrit reviewers plugin has a certain configuration format. Teach maintainers to emit it when called with -print-gerrit-rules. BUG=none BRANCH=none TEST=none Change-Id: Ia503aa158fc99e8502f4321f2173a269804a73db Signed-off-by: Patrick Georgi <pgeorgi@google.com> Original-Commit-Id: e874df9e0be1c61dceede3084f18ac7d49655cfc Original-Change-Id: I92cfc905e0c1b03b7cf793a4324c392140a22060 Original-Signed-off-by: Patrick Georgi <pgeorgi@google.com> Original-Reviewed-on: https://review.coreboot.org/29607 Original-Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Original-Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org> Reviewed-on: https://chromium-review.googlesource.com/1341331 Commit-Ready: Patrick Georgi <pgeorgi@chromium.org> Tested-by: Patrick Georgi <pgeorgi@chromium.org> Reviewed-by: Patrick Georgi <pgeorgi@chromium.org> " fail_count="0" gerrit_number="1341331" owner_email="pgeorgi@chromium.org" pass_count="0" patch_number="1" project="chromiumos/third_party/coreboot" project_url="https://chromium-review.googlesource.com/chromiumos/third_party/coreboot" ref="refs/changes/31/1341331/1" remote="cros" total_fail_count="0"/><pending_commit branch="chromeos-2016.05" change_id="Ie0019a10bc522387e0b7adc0350f467b2a652fc8" commit="70dcd2c09e7f0211872dc127f30ee82b3830cce7" commit_message="UPSTREAM: mb/google/sarien: Enable EC _PTS/_WAK methods Enable the option to have the system level _PTS/_WAK methods call the EC provided methods when they are invoked by the OS. Verified on sarien board by inspecting dsdt.dsl: Method (_PTS, 1, NotSerialized) // _PTS: Prepare To Sleep { DBG0 = 0x96 \_SB.PCI0.LPCB.EC0.PTS (Arg0) } Method (_WAK, 1, NotSerialized) // _WAK: Wake { DBG0 = 0x97 \_SB.PCI0.LPCB.EC0.WAK (Arg0) Return (Package (0x02) { Zero, Zero }) } BUG=none BRANCH=none TEST=none Change-Id: Ie0019a10bc522387e0b7adc0350f467b2a652fc8 Signed-off-by: Patrick Georgi <pgeorgi@google.com> Original-Commit-Id: c62b477b6e24d78a7072e0f87e7062b87f9396fe Original-Change-Id: I52be1c1cd7adae9ad317a51868735eb87a410549 Original-Signed-off-by: Duncan Laurie <dlaurie@google.com> Original-Reviewed-on: https://review.coreboot.org/29614 Original-Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Original-Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-on: https://chromium-review.googlesource.com/1341332 Commit-Ready: Patrick Georgi <pgeorgi@chromium.org> Tested-by: Patrick Georgi <pgeorgi@chromium.org> Reviewed-by: Patrick Georgi <pgeorgi@chromium.org> " fail_count="0" gerrit_number="1341332" owner_email="pgeorgi@chromium.org" pass_count="0" patch_number="1" project="chromiumos/third_party/coreboot" project_url="https://chromium-review.googlesource.com/chromiumos/third_party/coreboot" ref="refs/changes/32/1341332/1" remote="cros" total_fail_count="0"/><pending_commit branch="chromeos-2016.05" change_id="Iec78f6a7e41498f4252edcf409b4cd59a6ff34c2" commit="b79f15d4a707359de29ef5cc93291915d04ca674" commit_message="UPSTREAM: google/grunt/aleena: Update H1/TP/TS i2c timings After adjustment on aleena EVT Audio: 390.0 KHz H1: 390.0 KHz TP: 399.8 KHz TS: 399.8 kHz BUG=b:116306959 BRANCH=master TEST=emerge-grunt coreboot, scope measuring. Change-Id: Iec78f6a7e41498f4252edcf409b4cd59a6ff34c2 Signed-off-by: Patrick Georgi <pgeorgi@google.com> Original-Commit-Id: 19651a20e2fec2620f5614c3e7a197e725d60417 Original-Change-Id: I6f621508ce2dbb1b9dcdf529ac35afc80d485f53 Original-Signed-off-by: Lucas Chen <lucas.chen@quanta.corp-partner.google.com> Original-Reviewed-on: https://review.coreboot.org/29548 Original-Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Original-Reviewed-by: Martin Roth <martinroth@google.com> Reviewed-on: https://chromium-review.googlesource.com/1341333 Commit-Ready: Patrick Georgi <pgeorgi@chromium.org> Tested-by: Patrick Georgi <pgeorgi@chromium.org> Reviewed-by: Patrick Georgi <pgeorgi@chromium.org> " fail_count="0" gerrit_number="1341333" owner_email="pgeorgi@chromium.org" pass_count="0" patch_number="1" project="chromiumos/third_party/coreboot" project_url="https://chromium-review.googlesource.com/chromiumos/third_party/coreboot" ref="refs/changes/33/1341333/1" remote="cros" total_fail_count="0"/><pending_commit branch="master" change_id="Ie202596eca55b29025f8b6252427f25ad997cff5" commit="5fdc588427eb78faa44c6bd79a9731643c0d8ff4" commit_message="eclass: cros-firmware: Add local updaters back. This reverts commit db84ad2ca28e21fcd8c3cb8858b3168d3901f05c (CL:1310153). In current flow of early engineering builds, the factory still needs a package for imaging before the firmware images are really selected by an explicit firmware updater package. The `updater.sh` is needed until we can come out a better way of maintaining firmware packages. BUG=b:119290803 TEST=emerge-octopus chromeos-firmware-octopus # unibuild with local emerge-eve chromeos-firmware-eve # non-unibuild with local # remove IMAGE from eve and build again, see local updater emerge-kukui chromeos-firmware-null # empty image Change-Id: Ie202596eca55b29025f8b6252427f25ad997cff5 Reviewed-on: https://chromium-review.googlesource.com/1333106 Commit-Ready: Hung-Te Lin <hungte@chromium.org> Tested-by: Hung-Te Lin <hungte@chromium.org> Reviewed-by: Hung-Te Lin <hungte@chromium.org> " fail_count="0" gerrit_number="1333106" owner_email="hungte@chromium.org" pass_count="0" patch_number="11" project="chromiumos/overlays/chromiumos-overlay" project_url="https://chromium-review.googlesource.com/chromiumos/overlays/chromiumos-overlay" ref="refs/changes/06/1333106/11" remote="cros" total_fail_count="4"/><pending_commit branch="master" change_id="Ibf96366f01ec36a50978f47d135770cbc6024bc5" commit="7e518bd8e307e0bed870d7b3fae73d33c94e3159" commit_message="Install libvpx to test image By this change, libvpx.so is put in /usr/local/lib, and vpxdec and vpxenc are installed in /usr/local/bin. BUG=chromium:901221 TEST=./build_package && ./build_image CQ-DEPEND=CL:1319355 Change-Id: Ibf96366f01ec36a50978f47d135770cbc6024bc5 Reviewed-on: https://chromium-review.googlesource.com/1314082 Commit-Ready: Hirokazu Honda <hiroh@chromium.org> Tested-by: Hirokazu Honda <hiroh@chromium.org> Reviewed-by: Hirokazu Honda <hiroh@chromium.org> " fail_count="12" gerrit_number="1314082" owner_email="hiroh@chromium.org" pass_count="0" patch_number="4" project="chromiumos/overlays/chromiumos-overlay" project_url="https://chromium-review.googlesource.com/chromiumos/overlays/chromiumos-overlay" ref="refs/changes/82/1314082/4" remote="cros" total_fail_count="12"/><pending_commit branch="chromeos-3.18" change_id="Ie9e23b4d9ff9a05f6d733893a582f696a439fa19" commit="5882ca9e32f0a2f64c81a3d642530364fc885f0f" commit_message="CHROMIUM: add openat to altsyscall test list glibc 2.27 uses 'openat' system call when calling 'open()', we need to add this to system call whitelist accordingly. Signed-off-by: Yunlian Jiang <yunlian@chromium.org> BUG=chromium:897951 TEST=security_AltSyscall passes on kevin with glibc 2.27 Change-Id: Ie9e23b4d9ff9a05f6d733893a582f696a439fa19 Reviewed-on: https://chromium-review.googlesource.com/1296815 Commit-Ready: ChromeOS CL Exonerator Bot <chromiumos-cl-exonerator@appspot.gserviceaccount.com> Tested-by: Yunlian Jiang <yunlian@chromium.org> Reviewed-by: Luis Lozano <llozano@chromium.org> Reviewed-by: Mike Frysinger <vapier@chromium.org> (cherry picked from commit e061643ece564a23d2ff6376719ccdddb7d143e1) Reviewed-on: https://chromium-review.googlesource.com/1340503 Commit-Ready: Manoj Gupta <manojgupta@chromium.org> Tested-by: Manoj Gupta <manojgupta@chromium.org> Reviewed-by: Manoj Gupta <manojgupta@chromium.org> Reviewed-by: Micah Morton <mortonm@chromium.org> " fail_count="1" gerrit_number="1340503" owner_email="manojgupta@chromium.org" pass_count="0" patch_number="1" project="chromiumos/third_party/kernel" project_url="https://chromium-review.googlesource.com/chromiumos/third_party/kernel" ref="refs/changes/03/1340503/1" remote="cros" total_fail_count="1"/><pending_commit branch="chromeos-4.19" change_id="Ie9e23b4d9ff9a05f6d733893a582f696a439fa19" commit="d2728a5bef6347f92d93fbfc144240bc47b614c9" commit_message="CHROMIUM: add openat to altsyscall test list glibc 2.27 uses 'openat' system call when calling 'open()', we need to add this to system call whitelist accordingly. Signed-off-by: Yunlian Jiang <yunlian@chromium.org> BUG=chromium:897951 TEST=security_AltSyscall passes on kevin with glibc 2.27 Change-Id: Ie9e23b4d9ff9a05f6d733893a582f696a439fa19 Reviewed-on: https://chromium-review.googlesource.com/1296815 Commit-Ready: ChromeOS CL Exonerator Bot <chromiumos-cl-exonerator@appspot.gserviceaccount.com> Tested-by: Yunlian Jiang <yunlian@chromium.org> Reviewed-by: Luis Lozano <llozano@chromium.org> Reviewed-by: Mike Frysinger <vapier@chromium.org> (cherry picked from commit e061643ece564a23d2ff6376719ccdddb7d143e1) Reviewed-on: https://chromium-review.googlesource.com/1340529 Commit-Ready: Manoj Gupta <manojgupta@chromium.org> Tested-by: Manoj Gupta <manojgupta@chromium.org> Reviewed-by: Manoj Gupta <manojgupta@chromium.org> " fail_count="1" gerrit_number="1340529" owner_email="manojgupta@chromium.org" pass_count="0" patch_number="1" project="chromiumos/third_party/kernel" project_url="https://chromium-review.googlesource.com/chromiumos/third_party/kernel" ref="refs/changes/29/1340529/1" remote="cros" total_fail_count="1"/><pending_commit branch="master" change_id="Id54236a4441e6441bd8500a81f83c00e2fa405d8" commit="e2ea18ac2b08b589e5cf04ec65699db133fefbf6" commit_message="amdgpu: Don't use AMDGPU_GEM_CREATE_EXPLICIT_SYNC flag. some of the android.media.cts.EncodeDecodeTest in media test are failing when enabled. Bug=b:115585732 TEST=run android.media.cts.EncodeDecodeTest tests Change-Id: Id54236a4441e6441bd8500a81f83c00e2fa405d8 Signed-off-by: Deepak Sharma <Deepak.Sharma@amd.com> Reviewed-on: https://chromium-review.googlesource.com/1329993 Commit-Ready: Deepak Sharma <deepak.sharma@amd.com> Tested-by: Deepak Sharma <deepak.sharma@amd.com> Reviewed-by: Bas Nieuwenhuizen <basni@chromium.org> Reviewed-by: Gurchetan Singh <gurchetansingh@chromium.org> " fail_count="1" gerrit_number="1329993" owner_email="deepak.sharma@amd.com" pass_count="0" patch_number="4" project="chromiumos/platform/minigbm" project_url="https://chromium-review.googlesource.com/chromiumos/platform/minigbm" ref="refs/changes/93/1329993/4" remote="cros" total_fail_count="1"/><lkgm version="11271.0.0-rc4"/></manifest> |
