platform/ec/include: Change PD_T_CC_DEBOUNCE from 130ms to 140ms
Change PD_T_CC_DEBOUNCE from 130ms to 140ms so that obtained time
difference is within 150ms to 425ms for Pujjoga and Anraggar.
BUG=b:432428219 & b:442733768
TEST=Pass TD.4.6.4
Change-Id: Ife1cafac96e9facfb0682b497466965c91748880
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/6905043
Commit-Queue: Pranava Y N <pranavayn@google.com>
Auto-Submit: Smit Patel <smit.patel@7rays.corp-partner.google.com>
Reviewed-by: Pranava Y N <pranavayn@google.com>
Reviewed-by: Abe Levkoy <alevkoy@chromium.org>
Code-Coverage: Zoss <zoss-cl-coverage@prod.google.com>
Tested-by: Smit Patel <smit.patel@7rays.corp-partner.google.com>
diff --git a/include/usb_pd.h b/include/usb_pd.h
index c254dff..96b13f4 100644
--- a/include/usb_pd.h
+++ b/include/usb_pd.h
@@ -283,7 +283,7 @@
#define PD_T_PS_SOURCE_OFF (835 * MSEC) /* between 750ms and 920ms */
#define PD_T_PS_HARD_RESET (25 * MSEC) /* between 25ms and 35ms */
#define PD_T_ERROR_RECOVERY (240 * MSEC) /* min 240ms if sourcing VConn */
-#define PD_T_CC_DEBOUNCE (130 * MSEC) /* between 100ms and 200ms */
+#define PD_T_CC_DEBOUNCE (140 * MSEC) /* between 100ms and 200ms */
/* DRP_SNK + DRP_SRC must be between 50ms and 100ms with 30%-70% duty cycle */
#define PD_T_DRP_SNK (40 * MSEC) /* toggle time for sink DRP */
#define PD_T_DRP_SRC (30 * MSEC) /* toggle time for source DRP */
