Strip the rest of the repo down
Only these two files are needed left:
- firmware_builder.py
- import-sdk.py
May find a new home for them in the coming weeks but obviously much
less important to move as they change infrequently.
Left the OWNERS file just in case.
BUG=b:177003034
TEST=CQ
Change-Id: I8843057fbab803e0364871a91daff499e10bfcdf
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/zephyr-chrome/+/2634349
Tested-by: Jack Rosenthal <jrosenth@chromium.org>
Auto-Submit: Jack Rosenthal <jrosenth@chromium.org>
Commit-Queue: Paul Fagerburg <pfagerburg@chromium.org>
Reviewed-by: Paul Fagerburg <pfagerburg@chromium.org>
diff --git a/.checkpatch.conf b/.checkpatch.conf
deleted file mode 100644
index 9e44b05..0000000
--- a/.checkpatch.conf
+++ /dev/null
@@ -1,20 +0,0 @@
-# Not the Linux source tree.
---no-tree
-
-# Zephyr printk isn't the same as Linux printk
---ignore PRINTK_WITHOUT_KERN_LEVEL
-
-# We don't use Signed-off-by in this repo.
---ignore MISSING_SIGN_OFF
-
-# While we use SPDX license identifiers for files which may end up
-# upstreamed, files which will never be upstreamed can have the
-# sandard Chrome OS license headers instead.
---ignore SPDX_LICENSE_TAG
-
-# Disable some options which are too nit-picky.
---ignore SPLIT_STRING
---ignore C99_COMMENT_TOLERANCE
-
-# Ignore added braces for single-line code blocks
---ignore BRACES
diff --git a/.clang-format b/.clang-format
deleted file mode 100644
index 39f5403..0000000
--- a/.clang-format
+++ /dev/null
@@ -1,119 +0,0 @@
-# SPDX-License-Identifier: GPL-2.0
-#
-# clang-format configuration file. Intended for clang-format >= 9.
-#
-# For more information, see:
-#
-# Documentation/process/clang-format.rst
-# https://clang.llvm.org/docs/ClangFormat.html
-# https://clang.llvm.org/docs/ClangFormatStyleOptions.html
-#
-# Note: imported from Kernel .clang-format, uncommented options that
-# require clang-format-4.0 or clang-format-5.0, and removed
-# kernel-specific macros.
----
-AccessModifierOffset: -4
-AlignAfterOpenBracket: Align
-AlignConsecutiveAssignments: false
-AlignConsecutiveDeclarations: false
-AlignEscapedNewlines: Left
-AlignOperands: true
-AlignTrailingComments: false
-AllowAllParametersOfDeclarationOnNextLine: false
-AllowShortBlocksOnASingleLine: false
-AllowShortCaseLabelsOnASingleLine: false
-AllowShortFunctionsOnASingleLine: None
-AllowShortIfStatementsOnASingleLine: false
-AllowShortLoopsOnASingleLine: false
-AlwaysBreakAfterDefinitionReturnType: None
-AlwaysBreakAfterReturnType: None
-AlwaysBreakBeforeMultilineStrings: false
-AlwaysBreakTemplateDeclarations: false
-BinPackArguments: true
-BinPackParameters: true
-BraceWrapping:
- AfterClass: false
- AfterControlStatement: false
- AfterEnum: false
- AfterFunction: true
- AfterNamespace: true
- AfterObjCDeclaration: false
- AfterStruct: false
- AfterUnion: false
- AfterExternBlock: false
- BeforeCatch: false
- BeforeElse: false
- IndentBraces: false
- SplitEmptyFunction: true
- SplitEmptyRecord: true
- SplitEmptyNamespace: true
-BreakBeforeBinaryOperators: None
-BreakBeforeBraces: Custom
-BreakBeforeInheritanceComma: false
-BreakBeforeTernaryOperators: false
-BreakConstructorInitializersBeforeComma: false
-BreakConstructorInitializers: BeforeComma
-BreakAfterJavaFieldAnnotations: false
-BreakStringLiterals: false
-ColumnLimit: 80
-CommentPragmas: '^ IWYU pragma:'
-CompactNamespaces: false
-ConstructorInitializerAllOnOneLineOrOnePerLine: false
-ConstructorInitializerIndentWidth: 8
-ContinuationIndentWidth: 8
-Cpp11BracedListStyle: false
-DerivePointerAlignment: false
-DisableFormat: false
-ExperimentalAutoDetectBinPacking: false
-FixNamespaceComments: false
-IncludeBlocks: Preserve
-IncludeCategories:
- - Regex: '.*'
- Priority: 1
-IncludeIsMainRegex: '(Test)?$'
-IndentCaseLabels: false
-IndentPPDirectives: None
-IndentWidth: 8
-IndentWrappedFunctionNames: false
-JavaScriptQuotes: Leave
-JavaScriptWrapImports: true
-KeepEmptyLinesAtTheStartOfBlocks: false
-MacroBlockBegin: ''
-MacroBlockEnd: ''
-MaxEmptyLinesToKeep: 1
-NamespaceIndentation: Inner
-ObjCBinPackProtocolList: Auto
-ObjCBlockIndentWidth: 8
-ObjCSpaceAfterProperty: true
-ObjCSpaceBeforeProtocolList: true
-
-# Taken from git's rules
-PenaltyBreakAssignment: 10
-PenaltyBreakBeforeFirstCallParameter: 30
-PenaltyBreakComment: 10
-PenaltyBreakFirstLessLess: 0
-PenaltyBreakString: 10
-PenaltyExcessCharacter: 100
-PenaltyReturnTypeOnItsOwnLine: 60
-
-PointerAlignment: Right
-ReflowComments: false
-SortIncludes: false
-SortUsingDeclarations: false
-SpaceAfterCStyleCast: false
-SpaceAfterTemplateKeyword: true
-SpaceBeforeAssignmentOperators: true
-SpaceBeforeCtorInitializerColon: true
-SpaceBeforeInheritanceColon: true
-SpaceBeforeParens: ControlStatements
-SpaceBeforeRangeBasedForLoopColon: true
-SpaceInEmptyParentheses: false
-SpacesBeforeTrailingComments: 1
-SpacesInAngles: false
-SpacesInContainerLiterals: false
-SpacesInCStyleCastParentheses: false
-SpacesInParentheses: false
-SpacesInSquareBrackets: false
-Standard: Cpp03
-TabWidth: 8
-UseTab: Always
diff --git a/.dir-locals.el b/.dir-locals.el
deleted file mode 100644
index 8f3931f..0000000
--- a/.dir-locals.el
+++ /dev/null
@@ -1,4 +0,0 @@
-((c-mode . ((c-file-style . "linux")
- (c-basic-offset . 8)
- (tab-width . 8)
- (indent-tabs-mode . t))))
diff --git a/.gitignore b/.gitignore
deleted file mode 100644
index dcdbd68..0000000
--- a/.gitignore
+++ /dev/null
@@ -1,3 +0,0 @@
-__pycache__
-*.pyc
-*.egg-info
\ No newline at end of file
diff --git a/CMakeLists.txt b/CMakeLists.txt
deleted file mode 100644
index d6d2597..0000000
--- a/CMakeLists.txt
+++ /dev/null
@@ -1,14 +0,0 @@
-# Copyright 2020 The Chromium OS Authors. All rights reserved.
-# Use of this source code is governed by a BSD-style license that can be
-# found in the LICENSE file.
-
-# Build the EC's expected ec_version.h file.
-set(ec_version_file "${CMAKE_BINARY_DIR}/zephyr/include/generated/ec_version.h")
-execute_process(COMMAND sh ${PLATFORM_EC}/util/getversion.sh BOARD=${BOARD} > ${ec_version_file})
-
-# Set ${ZEPHYR_CHROME} as a convenience variable to the root path of
-# this module.
-set(ZEPHYR_CHROME "${ZEPHYR_CURRENT_MODULE_DIR}" CACHE PATH
- "Path to the zephyr-chrome repository.")
-
-add_subdirectory("drivers")
diff --git a/Kconfig b/Kconfig
deleted file mode 100644
index b451340..0000000
--- a/Kconfig
+++ /dev/null
@@ -1,9 +0,0 @@
-# Copyright 2020 The Chromium OS Authors. All rights reserved.
-# Use of this source code is governed by a BSD-style license that can be
-# found in the LICENSE file.
-
-if PLATFORM_EC
-
-rsource "drivers/Kconfig"
-
-endif
diff --git a/PRESUBMIT.cfg b/PRESUBMIT.cfg
deleted file mode 100644
index 2514a0e..0000000
--- a/PRESUBMIT.cfg
+++ /dev/null
@@ -1,9 +0,0 @@
-[Hook Overrides]
-# Zephyr uses SPDX license identifiers.
-cros_license_check: false
-
-# Zephyr uses Linux Kernel Code Style.
-checkpatch_check: true
-tab_check: false
-stray_whitespace_check: true
-long_line_check: true
diff --git a/drivers/CMakeLists.txt b/drivers/CMakeLists.txt
deleted file mode 100644
index 61aebb5..0000000
--- a/drivers/CMakeLists.txt
+++ /dev/null
@@ -1,4 +0,0 @@
-# SPDX-License-Identifier: Apache-2.0
-
-add_subdirectory(cros_kb_raw)
-add_subdirectory(cros_flash)
diff --git a/drivers/Kconfig b/drivers/Kconfig
deleted file mode 100644
index 87237d0..0000000
--- a/drivers/Kconfig
+++ /dev/null
@@ -1,5 +0,0 @@
-# Copyright 2020 Google LLC
-# SPDX-License-Identifier: Apache-2.0
-
-rsource "cros_kb_raw/Kconfig"
-rsource "cros_flash/Kconfig"
diff --git a/drivers/cros_flash/CMakeLists.txt b/drivers/cros_flash/CMakeLists.txt
deleted file mode 100644
index a5d333b..0000000
--- a/drivers/cros_flash/CMakeLists.txt
+++ /dev/null
@@ -1,3 +0,0 @@
-# SPDX-License-Identifier: Apache-2.0
-
-zephyr_library_sources_ifdef(CONFIG_CROS_FLASH_NPCX cros_flash_npcx.c)
diff --git a/drivers/cros_flash/Kconfig b/drivers/cros_flash/Kconfig
deleted file mode 100644
index 9dd83a5..0000000
--- a/drivers/cros_flash/Kconfig
+++ /dev/null
@@ -1,13 +0,0 @@
-
-# Copyright 2020 Google LLC
-# SPDX-License-Identifier: Apache-2.0
-
-# TODO(b/176828988): enable by default once the code can compile
-menuconfig CROS_FLASH_NPCX
- bool "Nuvoton NPCX flash driver for the Zephyr shim"
- depends on SOC_FAMILY_NPCX
- help
- This option enables a flash unit interface (FIU) driver for the NPCX
- chip. This is used instead of the flash memory interface so we can
- continue to use most of the existing flash memory processing code in
- ECOS.
diff --git a/drivers/cros_flash/cros_flash_npcx.c b/drivers/cros_flash/cros_flash_npcx.c
deleted file mode 100644
index 3fd8f4e..0000000
--- a/drivers/cros_flash/cros_flash_npcx.c
+++ /dev/null
@@ -1,525 +0,0 @@
-/*
- * Copyright 2020 Google LLC
- *
- * SPDX-License-Identifier: Apache-2.0
- */
-
-#define DT_DRV_COMPAT nuvoton_npcx_cros_flash
-
-#include <dt-bindings/clock/npcx_clock.h>
-#include <drivers/cros_flash.h>
-#include <drivers/clock_control.h>
-#include <drivers/gpio.h>
-#include <kernel.h>
-#include <logging/log.h>
-#include <soc.h>
-#include <soc/nuvoton_npcx/reg_def_cros.h>
-#include <sys/__assert.h>
-#include "ec_tasks.h"
-#include "soc_miwu.h"
-#include "task.h"
-#include "../drivers/flash/spi_nor.h"
-
-LOG_MODULE_REGISTER(cros_flash, LOG_LEVEL_ERR);
-
-/* Device config */
-struct cros_flash_npcx_config {
- /* flash interface unit base address */
- uintptr_t base;
- /* clock configuration */
- struct npcx_clk_cfg clk_cfg;
- /* Flash size (Unit:bytes) */
- int size;
- /* pinmux configuration */
- const uint8_t alts_size;
- const struct npcx_alt *alts_list;
-};
-
-/* Device data */
-struct cros_flash_npcx_data {
- /* flag of flash write protection */
- bool write_protectied;
- /* mutex of flash interface controller */
- struct k_sem lock_sem;
-};
-
-/* TODO: Should we replace them with Kconfig variables */
-#define CONFIG_FLASH_WRITE_SIZE 0x1 /* minimum write size */
-#define CONFIG_FLASH_WRITE_IDEAL_SIZE 256 /* one page size for write */
-
-/* TODO: It should be defined in the spi_nor.h in the zephyr repository */
-#define SPI_NOR_CMD_FAST_READ 0x0B
-
-/* Driver convenience defines */
-#define DRV_CONFIG(dev) ((const struct cros_flash_npcx_config *)(dev)->config)
-#define DRV_DATA(dev) ((struct cros_flash_npcx_data *)(dev)->data)
-#define HAL_INSTANCE(dev) (struct fiu_reg *)(DRV_CONFIG(dev)->base)
-
-/* cros ec flash local inline functions */
-static inline void cros_flash_npcx_mutex_lock(const struct device *dev)
-{
- struct cros_flash_npcx_data *data = DRV_DATA(dev);
-
- k_sem_take(&data->lock_sem, K_FOREVER);
-}
-
-static inline void cros_flash_npcx_mutex_unlock(const struct device *dev)
-{
- struct cros_flash_npcx_data *data = DRV_DATA(dev);
-
- k_sem_give(&data->lock_sem);
-}
-
-static inline void cros_flash_npcx_set_address(const struct device *dev,
- uint32_t qspi_addr)
-{
- struct fiu_reg *const inst = HAL_INSTANCE(dev);
- uint8_t *addr = (uint8_t *)&qspi_addr;
-
- /* Write 3 bytes address to UMA registers */
- inst->UMA_AB2 = addr[2];
- inst->UMA_AB1 = addr[1];
- inst->UMA_AB0 = addr[0];
-}
-
-static inline void cros_flash_npcx_cs_level(const struct device *dev, int level)
-{
- struct fiu_reg *const inst = HAL_INSTANCE(dev);
-
- /* Set chip select to high/low level */
- if (level == 0)
- inst->UMA_ECTS &= ~BIT(NPCX_UMA_ECTS_SW_CS1);
- else
- inst->UMA_ECTS |= BIT(NPCX_UMA_ECTS_SW_CS1);
-}
-
-static inline void cros_flash_npcx_exec_cmd(const struct device *dev,
- uint8_t code, uint8_t cts)
-{
- struct fiu_reg *const inst = HAL_INSTANCE(dev);
-
-#ifdef CONFIG_ASSERT
- struct cros_flash_npcx_data *data = DRV_DATA(dev);
-
- /* Flash mutex must be held while executing UMA commands */
- __ASSERT((k_sem_count_get(&data->lock_sem) == 0), "UMA is not locked");
-#endif
-
- /* set UMA_CODE */
- inst->UMA_CODE = code;
- /* execute UMA flash transaction */
- inst->UMA_CTS = cts;
- while (IS_BIT_SET(inst->UMA_CTS, NPCX_UMA_CTS_EXEC_DONE))
- ;
-}
-
-static inline void cros_flash_npcx_burst_read(const struct device *dev,
- char *dst_data, int dst_size)
-{
- struct fiu_reg *const inst = HAL_INSTANCE(dev);
-
- /* Burst read transaction */
- for (int idx = 0; idx < dst_size; idx++) {
- /* 1101 0101 - EXEC, RD, NO CMD, NO ADDR, 4 bytes */
- inst->UMA_CTS = UMA_CODE_RD_BYTE(1);
- /* wait for UMA to complete */
- while (IS_BIT_SET(inst->UMA_CTS, NPCX_UMA_CTS_EXEC_DONE))
- ;
- /* Get read transaction results*/
- dst_data[idx] = inst->UMA_DB0;
- }
-}
-
-static inline int cros_flash_npcx_wait_busy_bit_clear(const struct device *dev)
-{
- struct fiu_reg *const inst = HAL_INSTANCE(dev);
- int wait_period = 10; /* 10 us period t0 check status register */
- int timeout = (10 * USEC_PER_SEC) / wait_period; /* 10 seconds */
-
- do {
- /* Read status register */
- inst->UMA_CTS = UMA_CODE_RD_BYTE(1);
- while (IS_BIT_SET(inst->UMA_CTS, NPCX_UMA_CTS_EXEC_DONE))
- ;
- /* Status bit is clear */
- if ((inst->UMA_DB0 & SPI_NOR_WIP_BIT) == 0)
- break;
- k_usleep(wait_period);
- } while (--timeout); /* Wait for busy bit clear */
-
- if (timeout) {
- return 0;
- } else {
- return -ETIMEDOUT;
- }
-}
-
-/* cros ec flash local functions */
-static int cros_flash_npcx_wait_ready(const struct device *dev)
-{
- int ret = 0;
-
- /* Drive CS to low */
- cros_flash_npcx_cs_level(dev, 0);
-
- /* Command for Read status register of flash */
- cros_flash_npcx_exec_cmd(dev, SPI_NOR_CMD_RDSR, UMA_CODE_CMD_ONLY);
- /* Wait busy bit is clear */
- ret = cros_flash_npcx_wait_busy_bit_clear(dev);
- /* Drive CS to low */
- cros_flash_npcx_cs_level(dev, 1);
-
- return ret;
-}
-
-static int cros_flash_npcx_set_write_enable(const struct device *dev)
-{
- struct fiu_reg *const inst = HAL_INSTANCE(dev);
- int ret;
-
- /* Wait for previous operation to complete */
- ret = cros_flash_npcx_wait_ready(dev);
- if (ret != 0)
- return ret;
-
- /* Write enable command */
- cros_flash_npcx_exec_cmd(dev, SPI_NOR_CMD_WREN, UMA_CODE_CMD_ONLY);
-
- /* Wait for flash is not busy */
- ret = cros_flash_npcx_wait_ready(dev);
- if (ret != 0)
- return ret;
-
- if ((inst->UMA_DB0 & SPI_NOR_WEL_BIT) != 0)
- return 0;
- else
- return -EINVAL;
-}
-
-static void cros_flash_npcx_burst_write(const struct device *dev,
- unsigned int dest_addr,
- unsigned int bytes,
- const char *src_data)
-{
- /* Chip Select down */
- cros_flash_npcx_cs_level(dev, 0);
-
- /* Set write address */
- cros_flash_npcx_set_address(dev, dest_addr);
- /* Start programming */
- cros_flash_npcx_exec_cmd(dev, SPI_NOR_CMD_PP, UMA_CODE_CMD_WR_ADR);
- for (int i = 0; i < bytes; i++) {
- cros_flash_npcx_exec_cmd(dev, *src_data, UMA_CODE_CMD_WR_ONLY);
- src_data++;
- }
-
- /* Chip Select up */
- cros_flash_npcx_cs_level(dev, 1);
-}
-
-static int cros_flash_npcx_program_bytes(const struct device *dev,
- uint32_t offset, uint32_t bytes,
- const uint8_t *src_data)
-{
- int write_size;
- int ret = 0;
-
- while (bytes > 0) {
- /* Write length can not go beyond the end of the flash page */
- write_size = MIN(bytes,
- CONFIG_FLASH_WRITE_IDEAL_SIZE -
- (offset &
- (CONFIG_FLASH_WRITE_IDEAL_SIZE - 1)));
-
- /* Enable write */
- ret = cros_flash_npcx_set_write_enable(dev);
- if (ret != 0)
- return ret;
-
- /* Executr UMA burst write transaction */
- cros_flash_npcx_burst_write(dev, offset, write_size, src_data);
-
- /* Wait write completed */
- ret = cros_flash_npcx_wait_ready(dev);
- if (ret != 0)
- return ret;
-
- src_data += write_size;
- offset += write_size;
- bytes -= write_size;
- }
-
- return ret;
-}
-
-/* cros ec flash api functions */
-static int cros_flash_npcx_init(const struct device *dev)
-{
- const struct cros_flash_npcx_config *const config = DRV_CONFIG(dev);
- struct cros_flash_npcx_data *data = DRV_DATA(dev);
-
- /* initialize mutux for flash interface controller */
- k_sem_init(&data->lock_sem, 1, 1);
-
- /* Configure pin-mux for FIU device */
- npcx_pinctrl_mux_configure(config->alts_list, config->alts_size, 1);
-
- return 0;
-}
-
-static int cros_flash_npcx_read(const struct device *dev, int offset, int size,
- char *dst_data)
-{
- int ret = 0;
-
- /* Unlock flash interface device during reading flash */
- cros_flash_npcx_mutex_lock(dev);
-
- /* Chip Select down */
- cros_flash_npcx_cs_level(dev, 0);
-
- /* Set read address */
- cros_flash_npcx_set_address(dev, offset);
- /* Start with fast read command (skip one dummy byte) */
- cros_flash_npcx_exec_cmd(dev, SPI_NOR_CMD_FAST_READ,
- UMA_CODE_CMD_ADR_WR_BYTE(1));
- /* Execute burst read */
- cros_flash_npcx_burst_read(dev, dst_data, size);
-
- /* Chip Select up */
- cros_flash_npcx_cs_level(dev, 1);
-
- /* Unlock flash interface device */
- cros_flash_npcx_mutex_unlock(dev);
-
- return ret;
-}
-
-static int cros_flash_npcx_write(const struct device *dev, int offset, int size,
- const char *src_data)
-{
- struct cros_flash_npcx_data *const data = DRV_DATA(dev);
- int ret = 0;
-
- /* Is write protection enabled? */
- if (data->write_protectied) {
- return -EACCES;
- }
-
- /* Invalid data pointer? */
- if (src_data == 0) {
- return -EINVAL;
- }
-
- /* Unlock flash interface device during writing flash */
- cros_flash_npcx_mutex_lock(dev);
-
- while (size > 0) {
- /* First write multiples of 256, then (size % 256) last */
- int write_len =
- ((size % CONFIG_FLASH_WRITE_IDEAL_SIZE) == size) ?
- size :
- CONFIG_FLASH_WRITE_IDEAL_SIZE;
-
- ret = cros_flash_npcx_program_bytes(dev, offset, write_len,
- src_data);
- if (ret != 0)
- break;
-
- src_data += write_len;
- offset += write_len;
- size -= write_len;
- }
-
- /* Unlock flash interface device */
- cros_flash_npcx_mutex_unlock(dev);
-
- return ret;
-}
-
-static int cros_flash_npcx_erase(const struct device *dev, int offset, int size)
-{
- const struct cros_flash_npcx_config *const config = DRV_CONFIG(dev);
- struct cros_flash_npcx_data *const data = DRV_DATA(dev);
- int ret = 0;
-
- /* Is write protection enabled? */
- if (data->write_protectied) {
- return -EACCES;
- }
- /* affected region should be within device */
- if (offset < 0 || (offset + size) > config->size) {
- LOG_ERR("Flash erase address or size exceeds expected values. "
- "Addr: 0x%lx size %zu",
- (long)offset, size);
- return -EINVAL;
- }
-
- /* address must be aligned to erase size */
- if ((offset % CONFIG_FLASH_ERASE_SIZE) != 0) {
- return -EINVAL;
- }
-
- /* Erase size must be a non-zero multiple of sectors */
- if ((size == 0) || (size % CONFIG_FLASH_ERASE_SIZE) != 0) {
- return -EINVAL;
- }
-
- /* Unlock flash interface device during erasing flash */
- cros_flash_npcx_mutex_lock(dev);
-
- /* Alignment has been checked in upper layer */
- for (; size > 0; size -= CONFIG_FLASH_ERASE_SIZE,
- offset += CONFIG_FLASH_ERASE_SIZE) {
-
- /* Enable write */
- ret = cros_flash_npcx_set_write_enable(dev);
- if (ret != 0)
- break;
-
- /* Set erase address */
- cros_flash_npcx_set_address(dev, offset);
- /* Start erasing */
- cros_flash_npcx_exec_cmd(dev, SPI_NOR_CMD_SE, UMA_CODE_CMD_ADR);
-
- /* Wait erase completed */
- ret = cros_flash_npcx_wait_ready(dev);
- if (ret != 0) {
- break;
- }
- }
-
- /* Unlock flash interface device */
- cros_flash_npcx_mutex_unlock(dev);
-
- return ret;
-}
-
-static int cros_flash_npcx_get_status_reg(const struct device *dev,
- char cmd_code, char *data)
-{
- int ret = 0;
- struct fiu_reg *const inst = HAL_INSTANCE(dev);
-
- if (data == 0) {
- return -EINVAL;
- }
-
- /* Lock flash interface device during reading status register */
- cros_flash_npcx_mutex_lock(dev);
-
- cros_flash_npcx_exec_cmd(dev, cmd_code, UMA_CODE_CMD_RD_BYTE(1));
- *data = inst->UMA_DB0;
- /* Unlock flash interface device */
- cros_flash_npcx_mutex_unlock(dev);
-
- return ret;
-}
-
-static int cros_flash_npcx_set_status_reg(const struct device *dev, char *data)
-{
- int ret = 0;
- struct fiu_reg *const inst = HAL_INSTANCE(dev);
-
- /* Lock flash interface device */
- cros_flash_npcx_mutex_lock(dev);
- /* Enable write */
- ret = cros_flash_npcx_set_write_enable(dev);
- if (ret != 0)
- return ret;
-
- inst->UMA_DB0 = data[0];
- inst->UMA_DB1 = data[1];
- /* Write status register 1/2 */
- cros_flash_npcx_exec_cmd(dev, SPI_NOR_CMD_WRSR,
- UMA_CODE_CMD_WR_BYTE(2));
- /* Unlock flash interface device */
- cros_flash_npcx_mutex_unlock(dev);
-
- return ret;
-}
-
-static int cros_flash_npcx_write_protection_set(const struct device *dev,
- bool enable)
-{
- int ret = 0;
-
- /* Write protection can be cleared only by core domain reset */
- if (!enable) {
- LOG_ERR("WP can be disabled only via core domain reset ");
- return -ENOTSUP;
- }
- /* Lock flash interface device */
- cros_flash_npcx_mutex_lock(dev);
- ret = npcx_pinctrl_flash_write_protect_set();
- /* Unlock flash interface device */
- cros_flash_npcx_mutex_unlock(dev);
-
- return ret;
-}
-
-static int cros_flash_npcx_write_protection_is_set(const struct device *dev)
-{
- return npcx_pinctrl_flash_write_protect_is_set();
-}
-
-static int cros_flash_npcx_uma_lock(const struct device *dev, bool enable)
-{
- struct fiu_reg *const inst = HAL_INSTANCE(dev);
-
- if (enable) {
- inst->UMA_ECTS |= BIT(NPCX_UMA_ECTS_UMA_LOCK);
- } else {
- inst->UMA_ECTS &= ~BIT(NPCX_UMA_ECTS_UMA_LOCK);
- }
-
- return 0;
-}
-
-/* cros ec flash driver registration */
-static const struct cros_flash_driver_api cros_flash_npcx_driver_api = {
- .init = cros_flash_npcx_init,
- .physical_read = cros_flash_npcx_read,
- .physical_write = cros_flash_npcx_write,
- .physical_erase = cros_flash_npcx_erase,
- .write_protection = cros_flash_npcx_write_protection_set,
- .write_protection_is_set = cros_flash_npcx_write_protection_is_set,
- .get_status_reg = cros_flash_npcx_get_status_reg,
- .set_status_reg = cros_flash_npcx_set_status_reg,
- .uma_lock = cros_flash_npcx_uma_lock,
-};
-
-static int flash_npcx_init(const struct device *dev)
-{
- const struct cros_flash_npcx_config *const config = DRV_CONFIG(dev);
- const struct device *const clk_dev =
- device_get_binding(NPCX_CLK_CTRL_NAME);
-
- int ret;
-
- /* Turn on device clock first and get source clock freq. */
- ret = clock_control_on(clk_dev,
- (clock_control_subsys_t *)&config->clk_cfg);
- if (ret < 0) {
- LOG_ERR("Turn on FIU clock fail %d", ret);
- return ret;
- }
-
- return ret;
-}
-
-static const struct npcx_alt cros_flash_alts[] = NPCX_DT_ALT_ITEMS_LIST(0);
-static const struct cros_flash_npcx_config cros_flash_cfg = {
- .base = DT_INST_REG_ADDR(0),
- .clk_cfg = NPCX_DT_CLK_CFG_ITEM(0),
- .size = DT_INST_PROP(0, size),
- .alts_size = ARRAY_SIZE(cros_flash_alts),
- .alts_list = cros_flash_alts,
-};
-
-static struct cros_flash_npcx_data cros_flash_data;
-
-DEVICE_AND_API_INIT(cros_flash_npcx_0, DT_INST_LABEL(0), flash_npcx_init,
- &cros_flash_data, &cros_flash_cfg, PRE_KERNEL_1,
- CONFIG_KERNEL_INIT_PRIORITY_DEFAULT,
- &cros_flash_npcx_driver_api);
diff --git a/drivers/cros_kb_raw/CMakeLists.txt b/drivers/cros_kb_raw/CMakeLists.txt
deleted file mode 100644
index 54b8c63..0000000
--- a/drivers/cros_kb_raw/CMakeLists.txt
+++ /dev/null
@@ -1,3 +0,0 @@
-# SPDX-License-Identifier: Apache-2.0
-
-zephyr_library_sources_ifdef(CONFIG_CROS_KB_RAW_NPCX cros_kb_raw_npcx.c)
diff --git a/drivers/cros_kb_raw/Kconfig b/drivers/cros_kb_raw/Kconfig
deleted file mode 100644
index fb52526..0000000
--- a/drivers/cros_kb_raw/Kconfig
+++ /dev/null
@@ -1,13 +0,0 @@
-
-# Copyright 2020 Google LLC
-# SPDX-License-Identifier: Apache-2.0
-
-menuconfig CROS_KB_RAW_NPCX
- bool "Nuvoton NPCX raw-keyboard-scan driver for the Zephyr shim"
- depends on SOC_FAMILY_NPCX
- default y
- help
- This option enables a driver for providing raw access to the
- keyboard-scan peripheral in the chip. This is used instead of the
- kscan interface so we can continue to use most of the existing
- keyboard-scanning code in ECOS.
diff --git a/drivers/cros_kb_raw/cros_kb_raw_npcx.c b/drivers/cros_kb_raw/cros_kb_raw_npcx.c
deleted file mode 100644
index 91e8c84..0000000
--- a/drivers/cros_kb_raw/cros_kb_raw_npcx.c
+++ /dev/null
@@ -1,242 +0,0 @@
-/*
- * Copyright 2020 Google LLC
- *
- * SPDX-License-Identifier: Apache-2.0
- */
-
-#define DT_DRV_COMPAT nuvoton_npcx_cros_kb_raw
-
-#include <assert.h>
-#include <dt-bindings/clock/npcx_clock.h>
-#include <drivers/cros_kb_raw.h>
-#include <drivers/clock_control.h>
-#include <drivers/gpio.h>
-#include <kernel.h>
-#include <soc.h>
-#include <soc/nuvoton_npcx/reg_def_cros.h>
-
-#include "ec_tasks.h"
-#include "keyboard_raw.h"
-#include "soc_miwu.h"
-#include "task.h"
-
-#include <logging/log.h>
-LOG_MODULE_REGISTER(cros_kb_raw, LOG_LEVEL_ERR);
-
-#define NPCX_MAX_KEY_COLS 18 /* Maximum rows of keyboard matrix */
-#define NPCX_MAX_KEY_ROWS 8 /* Maximum columns of keyboard matrix */
-#define NPCX_KB_ROW_MASK (BIT(NPCX_MAX_KEY_ROWS) - 1)
-
-/* Device config */
-struct cros_kb_raw_npcx_config {
- /* keyboard scan controller base address */
- uintptr_t base;
- /* clock configuration */
- struct npcx_clk_cfg clk_cfg;
- /* pinmux configuration */
- const uint8_t alts_size;
- const struct npcx_alt *alts_list;
- /* Keyboard scan input (KSI) wake-up irq */
- int irq;
- /* Size of keyboard inputs-wui mapping array */
- int wui_size;
- /* Mapping table between keyboard inputs and wui */
- struct npcx_wui wui_maps[];
-};
-
-/* Driver convenience defines */
-#define DRV_CONFIG(dev) ((const struct cros_kb_raw_npcx_config *)(dev)->config)
-#define HAL_INSTANCE(dev) (struct kbs_reg *)(DRV_CONFIG(dev)->base)
-
-/* Keyboard Scan local functions */
-static struct miwu_dev_callback ksi_callback[NPCX_MAX_KEY_ROWS];
-
-static void kb_raw_npcx_init_ksi_wui_callback(
- const struct device *dev, struct miwu_dev_callback *callback,
- const struct npcx_wui *wui, miwu_dev_callback_handler_t handler)
-{
- /* KSI signal which has no wake-up input source */
- if (wui->table == NPCX_MIWU_TABLE_NONE)
- return;
-
- /* Install callback function */
- npcx_miwu_init_dev_callback(callback, wui, handler, dev);
- npcx_miwu_manage_dev_callback(callback, 1);
-
- /* Configure MIWU setting and enable its interrupt */
- npcx_miwu_interrupt_configure(wui, NPCX_MIWU_MODE_EDGE,
- NPCX_MIWU_TRIG_BOTH);
- npcx_miwu_irq_enable(wui);
-}
-
-static int kb_raw_npcx_init(const struct device *dev)
-{
- const struct cros_kb_raw_npcx_config *const config = DRV_CONFIG(dev);
- const struct device *const clk_dev =
- device_get_binding(NPCX_CLK_CTRL_NAME);
- int ret;
-
- /* Turn on device clock first and get source clock freq. */
- ret = clock_control_on(clk_dev,
- (clock_control_subsys_t *)&config->clk_cfg);
- if (ret < 0) {
- LOG_ERR("Turn on KSCAN clock fail %d", ret);
- return ret;
- }
-
- return 0;
-}
-
-/* Cros ec keyboard raw api functions */
-static int cros_kb_raw_npcx_enable_interrupt(const struct device *dev,
- int enable)
-{
- const struct cros_kb_raw_npcx_config *const config = DRV_CONFIG(dev);
-
- if (enable)
- irq_enable(config->irq);
- else
- irq_disable(config->irq);
-
- return 0;
-}
-
-static int cros_kb_raw_npcx_read_row(const struct device *dev)
-{
- struct kbs_reg *const inst = HAL_INSTANCE(dev);
- int val;
-
- val = inst->KBSIN;
- LOG_DBG("rows raw %02x", val);
-
- /* 1 means key pressed, otherwise means key released. */
- return (~val & NPCX_KB_ROW_MASK);
-}
-
-static int cros_kb_raw_npcx_drive_column(const struct device *dev, int col)
-{
- struct kbs_reg *const inst = HAL_INSTANCE(dev);
-
- /*
- * Nuvoton 'Keyboard Scan' module supports 18x8 matrix
- * It also support automatic scan functionality.
- */
- uint32_t mask, col_out;
-
- /* Add support for CONFIG_KEYBOARD_KSO_BASE shifting */
- col_out = col + CONFIG_KEYBOARD_KSO_BASE;
-
- /* Drive all lines to high. ie. Key detection is disabled. */
- if (col == KEYBOARD_COLUMN_NONE) {
- mask = ~0;
- if (IS_ENABLED(CONFIG_PLATFORM_EC_KEYBOARD_COL2_INVERTED)) {
- gpio_set_level(GPIO_KBD_KSO2, 0);
- }
- }
- /* Drive all lines to low for detection any key press */
- else if (col == KEYBOARD_COLUMN_ALL) {
- mask = ~(BIT(keyboard_cols) - 1);
- if (IS_ENABLED(CONFIG_PLATFORM_EC_KEYBOARD_COL2_INVERTED)) {
- gpio_set_level(GPIO_KBD_KSO2, 1);
- }
- }
- /* Drive one line to low for determining which key's state changed. */
- else {
- if (IS_ENABLED(CONFIG_PLATFORM_EC_KEYBOARD_COL2_INVERTED)) {
- if (col == 2)
- gpio_set_level(GPIO_KBD_KSO2, 1);
- else
- gpio_set_level(GPIO_KBD_KSO2, 0);
- }
- mask = ~BIT(col_out);
- }
-
- /* Set KBSOUT */
- inst->KBSOUT0 = (mask & 0xFFFF);
- inst->KBSOUT1 = ((mask >> 16) & 0x03);
-
- return 0;
-}
-
-static void cros_kb_raw_npcx_ksi_isr(const struct device *dev,
- struct npcx_wui *wui)
-{
- ARG_UNUSED(dev);
- ARG_UNUSED(wui);
-
- LOG_DBG("%s: KSI%d is changed", __func__, wui->bit);
- /* Wake-up keyboard scan task */
- task_wake(TASK_ID_KEYSCAN);
-}
-
-static int cros_kb_raw_npcx_init(const struct device *dev)
-{
- const struct cros_kb_raw_npcx_config *const config = DRV_CONFIG(dev);
- struct kbs_reg *const inst = HAL_INSTANCE(dev);
-
- /* Pull-up KBSIN0-7 internally */
- inst->KBSINPU = 0xFF;
-
- /*
- * Keyboard Scan Control Register
- *
- * [6:7] - KBHDRV KBSOUTn signals output buffers are open-drain.
- * [3] - KBSINC Auto-increment of Buffer Data register is disabled
- * [2] - KBSIEN Interrupt of Auto-Scan is disabled
- * [1] - KBSMODE Key detection mechanism is implemented by firmware
- * [0] - START Write 0 to this field is not affected
- */
- inst->KBSCTL = 0x00;
-
- /*
- * Select quasi-bidirectional buffers for KSO pins. It reduces the
- * low-to-high transition time. This feature only supports in npcx7.
- */
- if (IS_ENABLED(CONFIG_KEYBOARD_KSO_HIGH_DRIVE)) {
- SET_FIELD(inst->KBSCTL, NPCX_KBSCTL_KBHDRV_FIELD, 0x01);
- }
-
- /* Configure pin-mux for kscan device */
- npcx_pinctrl_mux_configure(config->alts_list, config->alts_size, 1);
-
- /* Drive all column lines to low for detection any key press */
- cros_kb_raw_npcx_drive_column(dev, KEYBOARD_COLUMN_ALL);
-
- /* Configure wake-up input and callback for keyboard input signal */
- for (int i = 0; i < ARRAY_SIZE(ksi_callback); i++)
- kb_raw_npcx_init_ksi_wui_callback(dev, &ksi_callback[i],
- &config->wui_maps[i],
- cros_kb_raw_npcx_ksi_isr);
-
- return 0;
-}
-
-static const struct cros_kb_raw_driver_api cros_kb_raw_npcx_driver_api = {
- .init = cros_kb_raw_npcx_init,
- .drive_colum = cros_kb_raw_npcx_drive_column,
- .read_rows = cros_kb_raw_npcx_read_row,
- .enable_interrupt = cros_kb_raw_npcx_enable_interrupt,
-};
-
-static const struct npcx_alt cros_kb_raw_alts[] = NPCX_DT_ALT_ITEMS_LIST(0);
-
-static const struct cros_kb_raw_npcx_config cros_kb_raw_cfg = {
- .base = DT_INST_REG_ADDR(0),
- .alts_size = ARRAY_SIZE(cros_kb_raw_alts),
- .alts_list = cros_kb_raw_alts,
- .clk_cfg = NPCX_DT_CLK_CFG_ITEM(0),
- .irq = DT_INST_IRQN(0),
- .wui_size = NPCX_DT_WUI_ITEMS_LEN(0),
- .wui_maps = NPCX_DT_WUI_ITEMS_LIST(0),
-};
-
-DEVICE_AND_API_INIT(cros_kb_raw_npcx_0, DT_INST_LABEL(0), kb_raw_npcx_init,
- NULL, &cros_kb_raw_cfg, PRE_KERNEL_1,
- CONFIG_KERNEL_INIT_PRIORITY_DEFAULT,
- &cros_kb_raw_npcx_driver_api);
-
-/* KBS register structure check */
-NPCX_REG_SIZE_CHECK(kbs_reg, 0x010);
-NPCX_REG_OFFSET_CHECK(kbs_reg, KBSIN, 0x004);
-NPCX_REG_OFFSET_CHECK(kbs_reg, KBSOUT0, 0x006);
-NPCX_REG_OFFSET_CHECK(kbs_reg, KBS_BUF_INDX, 0x00a);
diff --git a/tests/.gitignore b/tests/.gitignore
deleted file mode 100644
index 378eac2..0000000
--- a/tests/.gitignore
+++ /dev/null
@@ -1 +0,0 @@
-build
diff --git a/zephyr/module.yml b/zephyr/module.yml
deleted file mode 100644
index 883e994..0000000
--- a/zephyr/module.yml
+++ /dev/null
@@ -1,7 +0,0 @@
-# Copyright 2020 The Chromium OS Authors. All rights reserved.
-# Use of this source code is governed by a BSD-style license that can be
-# found in the LICENSE file.
-
-build:
- cmake: .
- kconfig: Kconfig
