test/CodeGen/Mips/GlobalISel/instruction-select/load.mir

# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
# RUN: llc -O0 -mtriple=mipsel-linux-gnu -run-pass=instruction-select -verify-machineinstrs %s -o - | FileCheck %s -check-prefixes=MIPS32FP32
# RUN: llc -O0 -mtriple=mipsel-linux-gnu -mattr=+fp64,+mips32r2 -run-pass=instruction-select -verify-machineinstrs %s -o - | FileCheck %s -check-prefixes=MIPS32FP64
--- |

  define void @load_i32(i32* %ptr) {entry: ret void}
  define void @load_float(float* %ptr) {entry: ret void}
  define void @load_double(double* %ptr) {entry: ret void}

...
---
name:            load_i32
alignment:       4
legalized:       true
regBankSelected: true
tracksRegLiveness: true
body:             |
  bb.1.entry:
    liveins: $a0

    ; MIPS32FP32-LABEL: name: load_i32
    ; MIPS32FP32: liveins: $a0
    ; MIPS32FP32: [[COPY:%[0-9]+]]:gpr32 = COPY $a0
    ; MIPS32FP32: [[LW:%[0-9]+]]:gpr32 = LW [[COPY]], 0 :: (load 4 from %ir.ptr)
    ; MIPS32FP32: $v0 = COPY [[LW]]
    ; MIPS32FP32: RetRA implicit $v0
    ; MIPS32FP64-LABEL: name: load_i32
    ; MIPS32FP64: liveins: $a0
    ; MIPS32FP64: [[COPY:%[0-9]+]]:gpr32 = COPY $a0
    ; MIPS32FP64: [[LW:%[0-9]+]]:gpr32 = LW [[COPY]], 0 :: (load 4 from %ir.ptr)
    ; MIPS32FP64: $v0 = COPY [[LW]]
    ; MIPS32FP64: RetRA implicit $v0
    %0:gprb(p0) = COPY $a0
    %1:gprb(s32) = G_LOAD %0(p0) :: (load 4 from %ir.ptr)
    $v0 = COPY %1(s32)
    RetRA implicit $v0

...
---
name:            load_float
alignment:       4
legalized:       true
regBankSelected: true
tracksRegLiveness: true
body:             |
  bb.1.entry:
    liveins: $a0

    ; MIPS32FP32-LABEL: name: load_float
    ; MIPS32FP32: liveins: $a0
    ; MIPS32FP32: [[COPY:%[0-9]+]]:gpr32 = COPY $a0
    ; MIPS32FP32: [[LWC1_:%[0-9]+]]:fgr32 = LWC1 [[COPY]], 0 :: (load 4 from %ir.ptr)
    ; MIPS32FP32: $f0 = COPY [[LWC1_]]
    ; MIPS32FP32: RetRA implicit $f0
    ; MIPS32FP64-LABEL: name: load_float
    ; MIPS32FP64: liveins: $a0
    ; MIPS32FP64: [[COPY:%[0-9]+]]:gpr32 = COPY $a0
    ; MIPS32FP64: [[LWC1_:%[0-9]+]]:fgr32 = LWC1 [[COPY]], 0 :: (load 4 from %ir.ptr)
    ; MIPS32FP64: $f0 = COPY [[LWC1_]]
    ; MIPS32FP64: RetRA implicit $f0
    %0:gprb(p0) = COPY $a0
    %1:fprb(s32) = G_LOAD %0(p0) :: (load 4 from %ir.ptr)
    $f0 = COPY %1(s32)
    RetRA implicit $f0

...
---
name:            load_double
alignment:       4
legalized:       true
regBankSelected: true
tracksRegLiveness: true
body:             |
  bb.1.entry:
    liveins: $a0

    ; MIPS32FP32-LABEL: name: load_double
    ; MIPS32FP32: liveins: $a0
    ; MIPS32FP32: [[COPY:%[0-9]+]]:gpr32 = COPY $a0
    ; MIPS32FP32: [[LDC1_:%[0-9]+]]:afgr64 = LDC1 [[COPY]], 0 :: (load 8 from %ir.ptr)
    ; MIPS32FP32: $d0 = COPY [[LDC1_]]
    ; MIPS32FP32: RetRA implicit $d0
    ; MIPS32FP64-LABEL: name: load_double
    ; MIPS32FP64: liveins: $a0
    ; MIPS32FP64: [[COPY:%[0-9]+]]:gpr32 = COPY $a0
    ; MIPS32FP64: [[LDC164_:%[0-9]+]]:fgr64 = LDC164 [[COPY]], 0 :: (load 8 from %ir.ptr)
    ; MIPS32FP64: $d0 = COPY [[LDC164_]]
    ; MIPS32FP64: RetRA implicit $d0
    %0:gprb(p0) = COPY $a0
    %1:fprb(s64) = G_LOAD %0(p0) :: (load 8 from %ir.ptr)
    $d0 = COPY %1(s64)
    RetRA implicit $d0

...