test/CodeGen/Mips/GlobalISel/instruction-select/load_store_fold.mir

# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
# RUN: llc -O0 -mtriple=mipsel-linux-gnu -run-pass=instruction-select -verify-machineinstrs %s -o - | FileCheck %s -check-prefixes=MIPS32
--- |

  define void @_16_bit_positive_offset() {entry: ret void}
  define void @_16_bit_negative_offset() {entry: ret void}
  define void @_large_positive_offset() {entry: ret void}
  define void @_large_negative_offset() {entry: ret void}
  define void @fold_f32_load() {entry: ret void}
  define void @fold_f64_store() {entry: ret void}
  define void @fold_i16_load() {entry: ret void}
  define void @fold_i32_store() {entry: ret void}

...
---
name:            _16_bit_positive_offset
alignment:       4
legalized:       true
regBankSelected: true
tracksRegLiveness: true
body:             |
  bb.1.entry:
    liveins: $a0

    ; MIPS32-LABEL: name: _16_bit_positive_offset
    ; MIPS32: liveins: $a0
    ; MIPS32: [[COPY:%[0-9]+]]:gpr32 = COPY $a0
    ; MIPS32: [[LBu:%[0-9]+]]:gpr32 = LBu [[COPY]], 32767 :: (load 1)
    ; MIPS32: $v0 = COPY [[LBu]]
    ; MIPS32: RetRA implicit $v0
    %0:gprb(p0) = COPY $a0
    %1:gprb(s32) = G_CONSTANT i32 32767
    %2:gprb(p0) = G_GEP %0, %1(s32)
    %4:gprb(s32) = G_ZEXTLOAD %2(p0) :: (load 1)
    $v0 = COPY %4(s32)
    RetRA implicit $v0

...
---
name:            _16_bit_negative_offset
alignment:       4
legalized:       true
regBankSelected: true
tracksRegLiveness: true
body:             |
  bb.1.entry:
    liveins: $a0, $a1

    ; MIPS32-LABEL: name: _16_bit_negative_offset
    ; MIPS32: liveins: $a0, $a1
    ; MIPS32: [[COPY:%[0-9]+]]:gpr32 = COPY $a0
    ; MIPS32: [[COPY1:%[0-9]+]]:gpr32 = COPY $a1
    ; MIPS32: SB [[COPY]], [[COPY1]], -32768 :: (store 1)
    ; MIPS32: RetRA
    %2:gprb(s32) = COPY $a0
    %1:gprb(p0) = COPY $a1
    %3:gprb(s32) = G_CONSTANT i32 -32768
    %4:gprb(p0) = G_GEP %1, %3(s32)
    %5:gprb(s32) = COPY %2(s32)
    G_STORE %5(s32), %4(p0) :: (store 1)
    RetRA

...
---
name:            _large_positive_offset
alignment:       4
legalized:       true
regBankSelected: true
tracksRegLiveness: true
body:             |
  bb.1.entry:
    liveins: $a0, $a1

    ; MIPS32-LABEL: name: _large_positive_offset
    ; MIPS32: liveins: $a0, $a1
    ; MIPS32: [[COPY:%[0-9]+]]:gpr32 = COPY $a0
    ; MIPS32: [[COPY1:%[0-9]+]]:gpr32 = COPY $a1
    ; MIPS32: [[ORi:%[0-9]+]]:gpr32 = ORi $zero, 32768
    ; MIPS32: [[ADDu:%[0-9]+]]:gpr32 = ADDu [[COPY1]], [[ORi]]
    ; MIPS32: SB [[COPY]], [[ADDu]], 0 :: (store 1)
    ; MIPS32: RetRA
    %2:gprb(s32) = COPY $a0
    %1:gprb(p0) = COPY $a1
    %3:gprb(s32) = G_CONSTANT i32 32768
    %4:gprb(p0) = G_GEP %1, %3(s32)
    %5:gprb(s32) = COPY %2(s32)
    G_STORE %5(s32), %4(p0) :: (store 1)
    RetRA

...
---
name:            _large_negative_offset
alignment:       4
legalized:       true
regBankSelected: true
tracksRegLiveness: true
body:             |
  bb.1.entry:
    liveins: $a0

    ; MIPS32-LABEL: name: _large_negative_offset
    ; MIPS32: liveins: $a0
    ; MIPS32: [[COPY:%[0-9]+]]:gpr32 = COPY $a0
    ; MIPS32: [[LUi:%[0-9]+]]:gpr32 = LUi 65535
    ; MIPS32: [[ORi:%[0-9]+]]:gpr32 = ORi [[LUi]], 32767
    ; MIPS32: [[ADDu:%[0-9]+]]:gpr32 = ADDu [[COPY]], [[ORi]]
    ; MIPS32: [[LB:%[0-9]+]]:gpr32 = LB [[ADDu]], 0 :: (load 1)
    ; MIPS32: $v0 = COPY [[LB]]
    ; MIPS32: RetRA implicit $v0
    %0:gprb(p0) = COPY $a0
    %1:gprb(s32) = G_CONSTANT i32 -32769
    %2:gprb(p0) = G_GEP %0, %1(s32)
    %4:gprb(s32) = G_SEXTLOAD %2(p0) :: (load 1)
    $v0 = COPY %4(s32)
    RetRA implicit $v0

...
---
name:            fold_f32_load
alignment:       4
legalized:       true
regBankSelected: true
tracksRegLiveness: true
body:             |
  bb.1.entry:
    liveins: $a0

    ; MIPS32-LABEL: name: fold_f32_load
    ; MIPS32: liveins: $a0
    ; MIPS32: [[COPY:%[0-9]+]]:gpr32 = COPY $a0
    ; MIPS32: [[LWC1_:%[0-9]+]]:fgr32 = LWC1 [[COPY]], 40 :: (load 4)
    ; MIPS32: $f0 = COPY [[LWC1_]]
    ; MIPS32: RetRA implicit $f0
    %0:gprb(p0) = COPY $a0
    %1:gprb(s32) = G_CONSTANT i32 40
    %2:gprb(p0) = G_GEP %0, %1(s32)
    %3:fprb(s32) = G_LOAD %2(p0) :: (load 4)
    $f0 = COPY %3(s32)
    RetRA implicit $f0

...
---
name:            fold_f64_store
alignment:       4
legalized:       true
regBankSelected: true
tracksRegLiveness: true
body:             |
  bb.1.entry:
    liveins: $a2, $d6

    ; MIPS32-LABEL: name: fold_f64_store
    ; MIPS32: liveins: $a2, $d6
    ; MIPS32: [[COPY:%[0-9]+]]:afgr64 = COPY $d6
    ; MIPS32: [[COPY1:%[0-9]+]]:gpr32 = COPY $a2
    ; MIPS32: SDC1 [[COPY]], [[COPY1]], -80 :: (store 8)
    ; MIPS32: RetRA
    %0:fprb(s64) = COPY $d6
    %1:gprb(p0) = COPY $a2
    %2:gprb(s32) = G_CONSTANT i32 -80
    %3:gprb(p0) = G_GEP %1, %2(s32)
    G_STORE %0(s64), %3(p0) :: (store 8)
    RetRA

...
---
name:            fold_i16_load
alignment:       4
legalized:       true
regBankSelected: true
tracksRegLiveness: true
body:             |
  bb.1.entry:
    liveins: $a0

    ; MIPS32-LABEL: name: fold_i16_load
    ; MIPS32: liveins: $a0
    ; MIPS32: [[COPY:%[0-9]+]]:gpr32 = COPY $a0
    ; MIPS32: [[LHu:%[0-9]+]]:gpr32 = LHu [[COPY]], -20 :: (load 2)
    ; MIPS32: $v0 = COPY [[LHu]]
    ; MIPS32: RetRA implicit $v0
    %0:gprb(p0) = COPY $a0
    %1:gprb(s32) = G_CONSTANT i32 -20
    %2:gprb(p0) = G_GEP %0, %1(s32)
    %4:gprb(s32) = G_LOAD %2(p0) :: (load 2)
    $v0 = COPY %4(s32)
    RetRA implicit $v0

...
---
name:            fold_i32_store
alignment:       4
legalized:       true
regBankSelected: true
tracksRegLiveness: true
body:             |
  bb.1.entry:
    liveins: $a0, $a1

    ; MIPS32-LABEL: name: fold_i32_store
    ; MIPS32: liveins: $a0, $a1
    ; MIPS32: [[COPY:%[0-9]+]]:gpr32 = COPY $a0
    ; MIPS32: [[COPY1:%[0-9]+]]:gpr32 = COPY $a1
    ; MIPS32: SW [[COPY]], [[COPY1]], 40 :: (store 4)
    ; MIPS32: RetRA
    %0:gprb(s32) = COPY $a0
    %1:gprb(p0) = COPY $a1
    %2:gprb(s32) = G_CONSTANT i32 40
    %3:gprb(p0) = G_GEP %1, %2(s32)
    G_STORE %0(s32), %3(p0) :: (store 4)
    RetRA

...