test/CodeGen/Mips/GlobalISel/instruction-select/store.mir

# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
# RUN: llc -O0 -mtriple=mipsel-linux-gnu -run-pass=instruction-select -verify-machineinstrs %s -o - | FileCheck %s -check-prefixes=MIPS32FP32
# RUN: llc -O0 -mtriple=mipsel-linux-gnu -mattr=+fp64,+mips32r2 -run-pass=instruction-select -verify-machineinstrs %s -o - | FileCheck %s -check-prefixes=MIPS32FP64
--- |

  define void @store_i32(i32* %ptr) { entry: ret void }
  define void @store_float(float* %ptr) { entry: ret void }
  define void @store_double(double* %ptr) { entry: ret void }

...
---
name:            store_i32
alignment:       4
legalized:       true
regBankSelected: true
tracksRegLiveness: true
body:             |
  bb.1.entry:
    liveins: $a0, $a1

    ; MIPS32FP32-LABEL: name: store_i32
    ; MIPS32FP32: liveins: $a0, $a1
    ; MIPS32FP32: [[COPY:%[0-9]+]]:gpr32 = COPY $a0
    ; MIPS32FP32: [[COPY1:%[0-9]+]]:gpr32 = COPY $a1
    ; MIPS32FP32: SW [[COPY]], [[COPY1]], 0 :: (store 4 into %ir.ptr)
    ; MIPS32FP32: RetRA
    ; MIPS32FP64-LABEL: name: store_i32
    ; MIPS32FP64: liveins: $a0, $a1
    ; MIPS32FP64: [[COPY:%[0-9]+]]:gpr32 = COPY $a0
    ; MIPS32FP64: [[COPY1:%[0-9]+]]:gpr32 = COPY $a1
    ; MIPS32FP64: SW [[COPY]], [[COPY1]], 0 :: (store 4 into %ir.ptr)
    ; MIPS32FP64: RetRA
    %0:gprb(s32) = COPY $a0
    %1:gprb(p0) = COPY $a1
    G_STORE %0(s32), %1(p0) :: (store 4 into %ir.ptr)
    RetRA

...
---
name:            store_float
alignment:       4
legalized:       true
regBankSelected: true
tracksRegLiveness: true
body:             |
  bb.1.entry:
    liveins: $a1, $f12

    ; MIPS32FP32-LABEL: name: store_float
    ; MIPS32FP32: liveins: $a1, $f12
    ; MIPS32FP32: [[COPY:%[0-9]+]]:fgr32 = COPY $f12
    ; MIPS32FP32: [[COPY1:%[0-9]+]]:gpr32 = COPY $a1
    ; MIPS32FP32: SWC1 [[COPY]], [[COPY1]], 0 :: (store 4 into %ir.ptr)
    ; MIPS32FP32: RetRA
    ; MIPS32FP64-LABEL: name: store_float
    ; MIPS32FP64: liveins: $a1, $f12
    ; MIPS32FP64: [[COPY:%[0-9]+]]:fgr32 = COPY $f12
    ; MIPS32FP64: [[COPY1:%[0-9]+]]:gpr32 = COPY $a1
    ; MIPS32FP64: SWC1 [[COPY]], [[COPY1]], 0 :: (store 4 into %ir.ptr)
    ; MIPS32FP64: RetRA
    %0:fprb(s32) = COPY $f12
    %1:gprb(p0) = COPY $a1
    G_STORE %0(s32), %1(p0) :: (store 4 into %ir.ptr)
    RetRA

...
---
name:            store_double
alignment:       4
legalized:       true
regBankSelected: true
tracksRegLiveness: true
body:             |
  bb.1.entry:
    liveins: $a2, $d6

    ; MIPS32FP32-LABEL: name: store_double
    ; MIPS32FP32: liveins: $a2, $d6
    ; MIPS32FP32: [[COPY:%[0-9]+]]:afgr64 = COPY $d6
    ; MIPS32FP32: [[COPY1:%[0-9]+]]:gpr32 = COPY $a2
    ; MIPS32FP32: SDC1 [[COPY]], [[COPY1]], 0 :: (store 8 into %ir.ptr)
    ; MIPS32FP32: RetRA
    ; MIPS32FP64-LABEL: name: store_double
    ; MIPS32FP64: liveins: $a2, $d6
    ; MIPS32FP64: [[COPY:%[0-9]+]]:fgr64 = COPY $d6
    ; MIPS32FP64: [[COPY1:%[0-9]+]]:gpr32 = COPY $a2
    ; MIPS32FP64: SDC164 [[COPY]], [[COPY1]], 0 :: (store 8 into %ir.ptr)
    ; MIPS32FP64: RetRA
    %0:fprb(s64) = COPY $d6
    %1:gprb(p0) = COPY $a2
    G_STORE %0(s64), %1(p0) :: (store 8 into %ir.ptr)
    RetRA

...