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| <pending_commit branch="chromeos-3.18" change_id="Icf3efd97613eeca3a0268d555a6eabb4e0a4cbd8" commit="952fe5b76848d9811ea45695887bee038030f8ec" commit_message="UPSTREAM: perf: Add cycles to branch_info Intel Skylake supports reporting the time in cycles a branch in the LBR took, to give a rough indication of the basic block performance. Export the cycle information in the branch_info structure. This can be done by just reusing some currently zero padding. This is just the generic header change. The architecture still needs to fill it in. There's no attempt to convert to real time, as we really want cycles here. Signed-off-by: Andi Kleen <ak@linux.intel.com> Signed-off-by: Peter Zijlstra (Intel) <peterz@infradead.org> Cc: Linus Torvalds <torvalds@linux-foundation.org> Cc: Peter Zijlstra <peterz@infradead.org> Cc: Thomas Gleixner <tglx@linutronix.de> Cc: eranian@google.com Link: http://lkml.kernel.org/r/1431285767-27027-5-git-send-email-andi@firstfloor.org Signed-off-by: Ingo Molnar <mingo@kernel.org> (cherry picked from commit 71ef3c6b9d4665ee7afbbe4c208a98917dcfc32f) Signed-off-by: Gabriel Marin <gmx@chromium.org> BUG=b:33115527 TEST=Verified that it compiles Change-Id: Icf3efd97613eeca3a0268d555a6eabb4e0a4cbd8 Reviewed-on: https://chromium-review.googlesource.com/417607 Commit-Ready: Gabriel Marin <gmx@chromium.org> Tested-by: Gabriel Marin <gmx@chromium.org> Reviewed-by: Sonny Rao <sonnyrao@chromium.org> " fail_count="1" gerrit_number="417607" owner_email="gmx@chromium.org" pass_count="0" patch_number="2" project="chromiumos/third_party/kernel" project_url="https://chromium-review.googlesource.com/chromiumos/third_party/kernel" ref="refs/changes/07/417607/2" remote="cros" total_fail_count="1"/><pending_commit branch="chromeos-3.18" change_id="Iacd9cfe62d0ccd1b4a85686b911335fd7437911a" commit="f979866040f95e9c402c6ff94b829cb3a73d922b" commit_message="UPSTREAM: perf/x86/intel/lbr: Add support for LBRv5 Add support for the new LBRv5 format used on Intel Skylake CPUs. The flags for mispredict, abort, in_tx etc. moved to range of separate LBR_INFO_* MSRs. Teach the LBR code to read those. The original LBR registers stay the same, except they have full sign extension now. LBR_INFO also reports a cycle count to the last branch. Report the cycle information using the new "cycles" branch_info output field. In addition we have to context switch and clear the new INFO MSRs to avoid any information leaks. Signed-off-by: Andi Kleen <ak@linux.intel.com> Signed-off-by: Peter Zijlstra (Intel) <peterz@infradead.org> Cc: Linus Torvalds <torvalds@linux-foundation.org> Cc: Peter Zijlstra <peterz@infradead.org> Cc: Thomas Gleixner <tglx@linutronix.de> Cc: eranian@google.com Link: http://lkml.kernel.org/r/1431285767-27027-6-git-send-email-andi@firstfloor.org Signed-off-by: Ingo Molnar <mingo@kernel.org> (cherry picked from commit 50eab8f6ecd77ae4f9742f8e21ea50705ce0f830) Signed-off-by: Gabriel Marin <gmx@chromium.org> BUG=b:33115527 TEST=Verified that it compiles Change-Id: Iacd9cfe62d0ccd1b4a85686b911335fd7437911a Reviewed-on: https://chromium-review.googlesource.com/417608 Commit-Ready: Gabriel Marin <gmx@chromium.org> Tested-by: Gabriel Marin <gmx@chromium.org> Reviewed-by: Sonny Rao <sonnyrao@chromium.org> " fail_count="1" gerrit_number="417608" owner_email="gmx@chromium.org" pass_count="0" patch_number="2" project="chromiumos/third_party/kernel" project_url="https://chromium-review.googlesource.com/chromiumos/third_party/kernel" ref="refs/changes/08/417608/2" remote="cros" total_fail_count="1"/><pending_commit branch="chromeos-3.18" change_id="I76a0f04cb2bcf0699d75618a37d71694d637b90f" commit="cc708b55753572d85ffba78210ca6b194c2f6835" commit_message="UPSTREAM: perf/x86/intel: Handle new arch perfmon v4 status bits ArchPerfmon v4 has some new status bits in GLOBAL_STATUS. These need to be ignored when deciding whether a NMI was an NMI, to avoid eating all NMIs when they stay set, see: b292d7a10487 ("perf/x86/intel: ignore CondChgd bit to avoid false NMI handling") This patch ignores the new ASIF bit, which indicates that SGX interfered with the PMU, and also the new LBR freezing bits, which are set when the LBRs get frozen, plus the existing CondChange (set by JTAG debuggers and some buggy BIOSes) Signed-off-by: Andi Kleen <ak@linux.intel.com> Signed-off-by: Peter Zijlstra (Intel) <peterz@infradead.org> Cc: Linus Torvalds <torvalds@linux-foundation.org> Cc: Peter Zijlstra <peterz@infradead.org> Cc: Thomas Gleixner <tglx@linutronix.de> Cc: eranian@google.com Link: http://lkml.kernel.org/r/1431285767-27027-8-git-send-email-andi@firstfloor.org Signed-off-by: Ingo Molnar <mingo@kernel.org> (cherry picked from commit d8020bee1d0caa90e7b9d6f39ac1fdfaaee7f67f) Signed-off-by: Gabriel Marin <gmx@chromium.org> BUG=b:33115527 TEST=Verified that it compiles Change-Id: I76a0f04cb2bcf0699d75618a37d71694d637b90f Reviewed-on: https://chromium-review.googlesource.com/417609 Commit-Ready: Gabriel Marin <gmx@chromium.org> Tested-by: Gabriel Marin <gmx@chromium.org> Reviewed-by: Sonny Rao <sonnyrao@chromium.org> " fail_count="1" gerrit_number="417609" owner_email="gmx@chromium.org" pass_count="0" patch_number="2" project="chromiumos/third_party/kernel" project_url="https://chromium-review.googlesource.com/chromiumos/third_party/kernel" ref="refs/changes/09/417609/2" remote="cros" total_fail_count="1"/><pending_commit branch="chromeos-3.18" change_id="Iaad2ebe3bde733379a010905db82390d96f4e758" commit="d0750541852c8a71e8360c19f116d1da81ceda32" commit_message="UPSTREAM: perf/x86/intel: Move PMU ACK to after LBR read With Arch Perfmon v4 the PMU ack unfreezes the LBRs. So we need to do the PMU ack after the LBR reading, otherwise the LBRs would be polluted by the PMI handler. This is a minimal change. In principle the ACK could be moved much later. Signed-off-by: Andi Kleen <ak@linux.intel.com> Signed-off-by: Peter Zijlstra (Intel) <peterz@infradead.org> Cc: Linus Torvalds <torvalds@linux-foundation.org> Cc: Peter Zijlstra <peterz@infradead.org> Cc: Thomas Gleixner <tglx@linutronix.de> Cc: eranian@google.com Link: http://lkml.kernel.org/r/1431285767-27027-10-git-send-email-andi@firstfloor.org Signed-off-by: Ingo Molnar <mingo@kernel.org> (cherry picked from commit 0f29e573dd32bb8598e74271454e97c962da5e05) Signed-off-by: Gabriel Marin <gmx@chromium.org> BUG=b:33115527 TEST=Verified that it compiles Change-Id: Iaad2ebe3bde733379a010905db82390d96f4e758 Reviewed-on: https://chromium-review.googlesource.com/417610 Commit-Ready: Gabriel Marin <gmx@chromium.org> Tested-by: Gabriel Marin <gmx@chromium.org> Reviewed-by: Sonny Rao <sonnyrao@chromium.org> " fail_count="1" gerrit_number="417610" owner_email="gmx@chromium.org" pass_count="0" patch_number="2" project="chromiumos/third_party/kernel" project_url="https://chromium-review.googlesource.com/chromiumos/third_party/kernel" ref="refs/changes/10/417610/2" remote="cros" total_fail_count="1"/><pending_commit branch="chromeos-3.18" change_id="Ifa82f028dfe7ed1b240b83135199354207d5dd05" commit="d31a7b2e2ebb718503850eb67a4ff1754eee2f72" commit_message="UPSTREAM: perf/x86/intel: Reset more state in PMU reset The PMU reset code didn't quite keep up with newer PMU features. Improve it a bit to really reset a modern PMU: - Clear all overflow status - Clear LBRs and freezing state - Disable fixed counters too Signed-off-by: Andi Kleen <ak@linux.intel.com> Signed-off-by: Peter Zijlstra (Intel) <peterz@infradead.org> Cc: eranian@google.com Link: http://lkml.kernel.org/r/1425059312-18217-2-git-send-email-andi@firstfloor.org Signed-off-by: Ingo Molnar <mingo@kernel.org> (cherry picked from commit 8882edf735738c949aba4b65d3ec3453066bab12) Signed-off-by: Gabriel Marin <gmx@chromium.org> BUG=b:33115527 TEST=Verified that it compiles Change-Id: Ifa82f028dfe7ed1b240b83135199354207d5dd05 Reviewed-on: https://chromium-review.googlesource.com/417611 Commit-Ready: Gabriel Marin <gmx@chromium.org> Tested-by: Gabriel Marin <gmx@chromium.org> Reviewed-by: Sonny Rao <sonnyrao@chromium.org> " fail_count="1" gerrit_number="417611" owner_email="gmx@chromium.org" pass_count="0" patch_number="2" project="chromiumos/third_party/kernel" project_url="https://chromium-review.googlesource.com/chromiumos/third_party/kernel" ref="refs/changes/11/417611/2" remote="cros" total_fail_count="1"/><pending_commit branch="chromeos-3.18" change_id="I6e4c00c25e526354d8fad79f298829728aef7b40" commit="1c8e0fedc8f761cf8618f49232cf1fb1b90531c1" commit_message="UPSTREAM: perf/x86: Dump DEBUGCTL in PMU dump LBRs and LBR freezing are controlled through the DEBUGCTL MSR. So dump the state of DEBUGCTL too when dumping the PMU state. Signed-off-by: Andi Kleen <ak@linux.intel.com> Signed-off-by: Peter Zijlstra (Intel) <peterz@infradead.org> Cc: eranian@google.com Link: http://lkml.kernel.org/r/1425059312-18217-3-git-send-email-andi@firstfloor.org Signed-off-by: Ingo Molnar <mingo@kernel.org> (cherry picked from commit da3e606d885a17525eb18afd423f5c438860b833) Signed-off-by: Gabriel Marin <gmx@chromium.org> BUG=b:33115527 TEST=Verified that it compiles Change-Id: I6e4c00c25e526354d8fad79f298829728aef7b40 Reviewed-on: https://chromium-review.googlesource.com/417612 Commit-Ready: Gabriel Marin <gmx@chromium.org> Tested-by: Gabriel Marin <gmx@chromium.org> Reviewed-by: Sonny Rao <sonnyrao@chromium.org> " fail_count="1" gerrit_number="417612" owner_email="gmx@chromium.org" pass_count="0" patch_number="2" project="chromiumos/third_party/kernel" project_url="https://chromium-review.googlesource.com/chromiumos/third_party/kernel" ref="refs/changes/12/417612/2" remote="cros" total_fail_count="1"/><pending_commit branch="chromeos-3.18" change_id="I58cf66ca609be11edca84179c24e923115dbf7bb" commit="193ec2644cb64b8ffea3d10d3725b2ab461f5e34" commit_message="UPSTREAM: perf/x86: Only dump PEBS register when PEBS has been detected Technically PEBS_ENABLED is only guaranteed to exist when we detected PEBS. So add a check for this to the PMU dump function. I don't think it can happen on a real CPU, but could in a VM. Signed-off-by: Andi Kleen <ak@linux.intel.com> Signed-off-by: Peter Zijlstra (Intel) <peterz@infradead.org> Cc: eranian@google.com Link: http://lkml.kernel.org/r/1425059312-18217-4-git-send-email-andi@firstfloor.org Signed-off-by: Ingo Molnar <mingo@kernel.org> (cherry picked from commit 15fde1101a1aed11958e0d86bc360f01866a74b1) Signed-off-by: Gabriel Marin <gmx@chromium.org> BUG=b:33115527 TEST=Verified that it compiles Change-Id: I58cf66ca609be11edca84179c24e923115dbf7bb Reviewed-on: https://chromium-review.googlesource.com/417613 Commit-Ready: Gabriel Marin <gmx@chromium.org> Tested-by: Gabriel Marin <gmx@chromium.org> Reviewed-by: Sonny Rao <sonnyrao@chromium.org> " fail_count="1" gerrit_number="417613" owner_email="gmx@chromium.org" pass_count="0" patch_number="2" project="chromiumos/third_party/kernel" project_url="https://chromium-review.googlesource.com/chromiumos/third_party/kernel" ref="refs/changes/13/417613/2" remote="cros" total_fail_count="1"/><pending_commit branch="chromeos-3.18" change_id="I98cceee0690fd28aa37c7444fd4a4cb37fb35c8b" commit="e6880bbfa4439eb7f0843f2fb5276b9278d2e57e" commit_message="UPSTREAM: perf/x86/intel: Streamline LBR MSR handling in PMI The perf PMI currently does unnecessary MSR accesses when LBRs are enabled. We use LBR freezing, or when in callstack mode force the LBRs to only filter on ring 3. So there is no need to disable the LBRs explicitely in the PMI handler. Also we always unnecessarily rewrite LBR_SELECT in the LBR handler, even though it can never change. 5) | /* write_msr: MSR_LBR_SELECT(1c8), value 0 */ 5) | /* read_msr: MSR_IA32_DEBUGCTLMSR(1d9), value 1801 */ 5) | /* write_msr: MSR_IA32_DEBUGCTLMSR(1d9), value 1801 */ 5) | /* write_msr: MSR_CORE_PERF_GLOBAL_CTRL(38f), value 70000000f */ 5) | /* write_msr: MSR_CORE_PERF_GLOBAL_CTRL(38f), value 0 */ 5) | /* write_msr: MSR_LBR_SELECT(1c8), value 0 */ 5) | /* read_msr: MSR_IA32_DEBUGCTLMSR(1d9), value 1801 */ 5) | /* write_msr: MSR_IA32_DEBUGCTLMSR(1d9), value 1801 */ This patch: - Avoids disabling already frozen LBRs unnecessarily in the PMI - Avoids changing LBR_SELECT in the PMI Signed-off-by: Andi Kleen <ak@linux.intel.com> Signed-off-by: Peter Zijlstra (Intel) <peterz@infradead.org> Cc: eranian@google.com Link: http://lkml.kernel.org/r/1426871484-21285-1-git-send-email-andi@firstfloor.org Signed-off-by: Ingo Molnar <mingo@kernel.org> (cherry picked from commit 1a78d93750bb5f61abdc59a91fc3bd06a214542a) Signed-off-by: Gabriel Marin <gmx@chromium.org> BUG=b:33115527 TEST=Verified that it compiles Change-Id: I98cceee0690fd28aa37c7444fd4a4cb37fb35c8b Reviewed-on: https://chromium-review.googlesource.com/417614 Commit-Ready: Gabriel Marin <gmx@chromium.org> Tested-by: Gabriel Marin <gmx@chromium.org> Reviewed-by: Sonny Rao <sonnyrao@chromium.org> " fail_count="1" gerrit_number="417614" owner_email="gmx@chromium.org" pass_count="0" patch_number="2" project="chromiumos/third_party/kernel" project_url="https://chromium-review.googlesource.com/chromiumos/third_party/kernel" ref="refs/changes/14/417614/2" remote="cros" total_fail_count="1"/><pending_commit branch="chromeos-3.18" change_id="I22a13f6510f6b645178135bd2da59fbc3c084929" commit="42a800b713e32feb1891f1517139b288caec2eb5" commit_message="UPSTREAM: perf/x86/intel: Avoid rewriting DEBUGCTL with the same value for LBRs perf with LBRs on has a tendency to rewrite the DEBUGCTL MSR with the same value. Add a little optimization to skip the unnecessary write. Signed-off-by: Andi Kleen <ak@linux.intel.com> Signed-off-by: Peter Zijlstra (Intel) <peterz@infradead.org> Cc: eranian@google.com Link: http://lkml.kernel.org/r/1426871484-21285-2-git-send-email-andi@firstfloor.org Signed-off-by: Ingo Molnar <mingo@kernel.org> (cherry picked from commit cd1f11de69226cc7ce7e7f22bdab9010103ddaa6) Signed-off-by: Gabriel Marin <gmx@chromium.org> BUG=b:33115527 TEST=Verified that it compiles Change-Id: I22a13f6510f6b645178135bd2da59fbc3c084929 Reviewed-on: https://chromium-review.googlesource.com/417615 Commit-Ready: Gabriel Marin <gmx@chromium.org> Tested-by: Gabriel Marin <gmx@chromium.org> Reviewed-by: Sonny Rao <sonnyrao@chromium.org> " fail_count="1" gerrit_number="417615" owner_email="gmx@chromium.org" pass_count="0" patch_number="2" project="chromiumos/third_party/kernel" project_url="https://chromium-review.googlesource.com/chromiumos/third_party/kernel" ref="refs/changes/15/417615/2" remote="cros" total_fail_count="1"/><pending_commit branch="chromeos-3.18" change_id="I07bc40f874f8c5031ee0a6c266db02e6fa7b2182" commit="b9e126c527f707a86f4d1181ed445a612f60e3aa" commit_message="UPSTREAM: perf/x86/intel/lbr: Optimize v4 LBR unfreezing In Arch perfmon v4 the GLOBAL_STATUS reset automatically unfreezes LBRs. So no need to do it manually in the LBR code. Add a check to skip it. v2: Move test up to beginning of function. Signed-off-by: Andi Kleen <ak@linux.intel.com> Signed-off-by: Peter Zijlstra (Intel) <peterz@infradead.org> Cc: Linus Torvalds <torvalds@linux-foundation.org> Cc: Peter Zijlstra <peterz@infradead.org> Cc: Thomas Gleixner <tglx@linutronix.de> Cc: eranian@google.com Link: http://lkml.kernel.org/r/1431285767-27027-9-git-send-email-andi@firstfloor.org Signed-off-by: Ingo Molnar <mingo@kernel.org> (cherry picked from commit 425507fa5f321bb5ce1b5eb57a9586e0cf0b9802) Signed-off-by: Gabriel Marin <gmx@chromium.org> BUG=b:33115527 TEST=Verified that it compiles Change-Id: I07bc40f874f8c5031ee0a6c266db02e6fa7b2182 Reviewed-on: https://chromium-review.googlesource.com/417616 Commit-Ready: Gabriel Marin <gmx@chromium.org> Tested-by: Gabriel Marin <gmx@chromium.org> Reviewed-by: Sonny Rao <sonnyrao@chromium.org> " fail_count="1" gerrit_number="417616" owner_email="gmx@chromium.org" pass_count="0" patch_number="2" project="chromiumos/third_party/kernel" project_url="https://chromium-review.googlesource.com/chromiumos/third_party/kernel" ref="refs/changes/16/417616/2" remote="cros" total_fail_count="1"/><pending_commit branch="chromeos-3.18" change_id="I6e0413d5420b4dcfa726ba6d91c8797bfdac8710" commit="03489177337f32713e26a89ed1619e51bc08a2ce" commit_message="BACKPORT: perf/x86/intel: Add Intel Skylake PMU support Add perf core PMU support for future Intel Skylake CPU cores. The code is based on Haswell/Broadwell. There is a new cache event list, based on the updated Haswell event list. Skylake has removed most counter constraints on basic events, so the basic constraints table now only has a single entry (plus the fixed counters). TSX support and various other setups are all shared with Haswell. Skylake has 32 LBR entries. Add a new LBR init function to set this up. The filters are all the same as Haswell. It also has a new LBR format with a separate LBR_INFO_* MSR, but that has been already added earlier. Signed-off-by: Andi Kleen <ak@linux.intel.com> Signed-off-by: Peter Zijlstra (Intel) <peterz@infradead.org> Cc: Linus Torvalds <torvalds@linux-foundation.org> Cc: Peter Zijlstra <peterz@infradead.org> Cc: Thomas Gleixner <tglx@linutronix.de> Cc: eranian@google.com Link: http://lkml.kernel.org/r/1431285767-27027-7-git-send-email-andi@firstfloor.org Signed-off-by: Ingo Molnar <mingo@kernel.org> (cherry picked from commit 9a92e16fd7b4ccd9aabcbc4d42a3fb5f9a3cf4a1) Signed-off-by: Gabriel Marin <gmx@chromium.org> Fixes: In file perf_event_intel.c - replaced uses of x86_pmu.flags with x86_pmu.er_flags; - replaced uses of PMU_FL_* with ERF_*; BUG=b:33115527 TEST=Verified that the kernel compiles. Tested that perf record / report / top / stat works on a Skylake based chromebook. Verified that perf list shows a set of hardware and hardware cache events. Change-Id: I6e0413d5420b4dcfa726ba6d91c8797bfdac8710 Reviewed-on: https://chromium-review.googlesource.com/414624 Commit-Ready: Gabriel Marin <gmx@chromium.org> Tested-by: Gabriel Marin <gmx@chromium.org> Reviewed-by: Sonny Rao <sonnyrao@chromium.org> " fail_count="1" gerrit_number="414624" owner_email="gmx@chromium.org" pass_count="0" patch_number="3" project="chromiumos/third_party/kernel" project_url="https://chromium-review.googlesource.com/chromiumos/third_party/kernel" ref="refs/changes/24/414624/3" remote="cros" total_fail_count="1"/><pending_commit branch="chromeos-3.18" change_id="Ic74ea2fcd3538f68cdef9e8ceb95170d982e6a59" commit="5bcaf09ab50fed8f90676eef89ea5165bf19b0e4" commit_message="UPSTREAM: perf/x86/intel/lbr: Use correct index to save/restore LBR_INFO with call stack Use the correct index to save/restore the LBR_INFO_x MSR in callstack mode. This is more a cleanup, as even with the wrong index the register was correctly saved/restored, and also LBR callgraph mode in perf tools do not really need anything in LBR_INFO. But still better to use the right index. Signed-off-by: Andi Kleen <ak@linux.intel.com> Signed-off-by: Peter Zijlstra (Intel) <peterz@infradead.org> Cc: Linus Torvalds <torvalds@linux-foundation.org> Cc: Peter Zijlstra <peterz@infradead.org> Cc: Thomas Gleixner <tglx@linutronix.de> Cc: acme@kernel.org Cc: eranian@google.com Cc: jolsa@redhat.com Link: http://lkml.kernel.org/r/1432786398-23861-5-git-send-email-andi@firstfloor.org Signed-off-by: Ingo Molnar <mingo@kernel.org> (cherry picked from commit e0573364b8c5b17401569ef581f1625803210f4d) Signed-off-by: Gabriel Marin <gmx@chromium.org> BUG=b:33115527 TEST=Verified that it compiles Change-Id: Ic74ea2fcd3538f68cdef9e8ceb95170d982e6a59 Reviewed-on: https://chromium-review.googlesource.com/417617 Commit-Ready: Gabriel Marin <gmx@chromium.org> Tested-by: Gabriel Marin <gmx@chromium.org> Reviewed-by: Sonny Rao <sonnyrao@chromium.org> " fail_count="1" gerrit_number="417617" owner_email="gmx@chromium.org" pass_count="0" patch_number="2" project="chromiumos/third_party/kernel" project_url="https://chromium-review.googlesource.com/chromiumos/third_party/kernel" ref="refs/changes/17/417617/2" remote="cros" total_fail_count="1"/><pending_commit branch="chromeos-3.18" change_id="I6bbe449b734b624e78bcd22a6af2eb8b566e7d7e" commit="c58a3285f7b27b22c1e57af6074c3cf3a14ad270" commit_message="UPSTREAM: perf/x86/intel/lbr: Limit LBR accesses to TOS in callstack mode In callstack mode the LBR is not a ring buffer, but a stack that grows up and down. This means in this case we don't need to access all LBRs, only the ones up to TOS. Do this optimization for the normal LBR read, and the context switch save/restore code. For save/restore it can be done unconditionally, as it only runs when call stack mode is active. This recovers some of the cost of going to 32 LBRs on Skylake. Signed-off-by: Andi Kleen <ak@linux.intel.com> Signed-off-by: Peter Zijlstra (Intel) <peterz@infradead.org> Cc: Linus Torvalds <torvalds@linux-foundation.org> Cc: Peter Zijlstra <peterz@infradead.org> Cc: Thomas Gleixner <tglx@linutronix.de> Cc: acme@kernel.org Cc: eranian@google.com Cc: jolsa@redhat.com Link: http://lkml.kernel.org/r/1432786398-23861-6-git-send-email-andi@firstfloor.org Signed-off-by: Ingo Molnar <mingo@kernel.org> (cherry picked from commit 90405aa02247c1a6313c33e2253f9fd2299ae60b) Signed-off-by: Gabriel Marin <gmx@chromium.org> BUG=b:33115527 TEST=Verified that it compiles Change-Id: I6bbe449b734b624e78bcd22a6af2eb8b566e7d7e Reviewed-on: https://chromium-review.googlesource.com/417618 Commit-Ready: Gabriel Marin <gmx@chromium.org> Tested-by: Gabriel Marin <gmx@chromium.org> Reviewed-by: Sonny Rao <sonnyrao@chromium.org> " fail_count="1" gerrit_number="417618" owner_email="gmx@chromium.org" pass_count="0" patch_number="2" project="chromiumos/third_party/kernel" project_url="https://chromium-review.googlesource.com/chromiumos/third_party/kernel" ref="refs/changes/18/417618/2" remote="cros" total_fail_count="1"/><pending_commit branch="chromeos-3.18" change_id="Id187a4f6cd4fd7764cd3c6432a35d09ef1a38bff" commit="38c7e40eed198f638a281b82daaacc561e83ee4a" commit_message="UPSTREAM: perf/x86: Make merge_attr() global to use from perf_event_intel merge_attr() allows to merge two sysfs attribute tables. Export it to be usable by other files too. Next patch is going to use that to extend the sysfs format attributes for a CPU. Signed-off-by: Andi Kleen <ak@linux.intel.com> Signed-off-by: Peter Zijlstra (Intel) <peterz@infradead.org> Cc: Linus Torvalds <torvalds@linux-foundation.org> Cc: Peter Zijlstra <peterz@infradead.org> Cc: Thomas Gleixner <tglx@linutronix.de> Cc: eranian@google.com Link: http://lkml.kernel.org/r/1435612935-24425-1-git-send-email-andi@firstfloor.org Signed-off-by: Ingo Molnar <mingo@kernel.org> (cherry picked from commit 47732d886385af769449022a02c7cf0ce45d8a5c) Signed-off-by: Gabriel Marin <gmx@chromium.org> BUG=b:33115527 TEST=Verified that it compiles Change-Id: Id187a4f6cd4fd7764cd3c6432a35d09ef1a38bff Reviewed-on: https://chromium-review.googlesource.com/414626 Commit-Ready: Gabriel Marin <gmx@chromium.org> Tested-by: Gabriel Marin <gmx@chromium.org> Reviewed-by: Sonny Rao <sonnyrao@chromium.org> " fail_count="1" gerrit_number="414626" owner_email="gmx@chromium.org" pass_count="0" patch_number="3" project="chromiumos/third_party/kernel" project_url="https://chromium-review.googlesource.com/chromiumos/third_party/kernel" ref="refs/changes/26/414626/3" remote="cros" total_fail_count="1"/><pending_commit branch="master" change_id="I797b3fd9e23837f5fc9e5bf9d3aa4523b0ea0b9a" commit="e48bf25ddb9006eb160b1ccaa501d3944f4fb3db" commit_message="Add an ebuild for the chromeos-config library and tools We need to provide a C++ library to access the master configuration, as well as a command-line tool for scripts. As a starting point, create an ebuild for the croscfg library. BUG=chromium:671391 TEST=FEATURES=test emerge-reef chromeos-config-tools Change-Id: I797b3fd9e23837f5fc9e5bf9d3aa4523b0ea0b9a Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/417479 Reviewed-by: Mike Frysinger <vapier@chromium.org> " fail_count="0" gerrit_number="417479" owner_email="sjg@chromium.org" pass_count="0" patch_number="9" project="chromiumos/overlays/chromiumos-overlay" project_url="https://chromium-review.googlesource.com/chromiumos/overlays/chromiumos-overlay" ref="refs/changes/79/417479/9" remote="cros" total_fail_count="0"/><pending_commit branch="master" change_id="Ibcc499de860982261e5c59728a2fee5ee5bf8178" commit="d2d769b5a4d4debf6845a0736a70f6396cc9c54c" commit_message="fides: Nuke obsolete project. We no longer intend to ship fides in its current form on any hardware, so remove the code. There's always the option to bring it back should it become relevant in the future. BUG=none TEST=none Change-Id: Ibcc499de860982261e5c59728a2fee5ee5bf8178 Reviewed-on: https://chromium-review.googlesource.com/416429 Commit-Ready: Mattias Nissler <mnissler@chromium.org> Tested-by: Mattias Nissler <mnissler@chromium.org> Reviewed-by: Mattias Nissler <mnissler@chromium.org> Reviewed-by: Christoph Schütte <cschuet@chromium.org> " fail_count="0" gerrit_number="416429" owner_email="mnissler@chromium.org" pass_count="0" patch_number="1" project="chromiumos/platform2" project_url="https://chromium-review.googlesource.com/chromiumos/platform2" ref="refs/changes/29/416429/1" remote="cros" total_fail_count="0"/><pending_commit branch="master" change_id="Ifb6f9e04b42ef21e3e667f420dbcdf77049fc533" commit="c4b9193b7019abca55a1c519f0e73204f346cc46" commit_message="power: Make WakeupController handle tablet mode. Make powerd's policy::WakeupController inhibit and configure S3 wakeup for input devices while in tablet mode. It previously had code for handling the mode, but was never wired up to be notified about tablet switch events. It's possible/likely that the udev tags around tablet mode will need to be updated, as this code has never been exercised. BUG=chromium:661368 TEST=added unit tests; also checked powerd log after switching in and out of tablet mode and saw that devices were inhibited and configured for wakeup as expected Change-Id: Ifb6f9e04b42ef21e3e667f420dbcdf77049fc533 Reviewed-on: https://chromium-review.googlesource.com/416373 Commit-Ready: Dan Erat <derat@chromium.org> Tested-by: Dan Erat <derat@chromium.org> Reviewed-by: Benson Leung <bleung@google.com> " fail_count="4" gerrit_number="416373" owner_email="derat@chromium.org" pass_count="0" patch_number="3" project="chromiumos/platform2" project_url="https://chromium-review.googlesource.com/chromiumos/platform2" ref="refs/changes/73/416373/3" remote="cros" total_fail_count="4"/><lkgm version="9092.0.0-rc1"/></manifest> |
