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| <pending_commit branch="chromeos-2016.05" change_id="Ice984c4d814a1e75ab25dcd3748115f6306d5375" commit="d6d7af984f528fb2e158819c7e60c89c34cd1da8" commit_message="UPSTREAM: soc/intel/broadwell: add support for Intel GMA OpRegion Add global/ACPI nvs variables required for IGD OpRegion. Add functions necessary to generate ACPI OpRegion, save the table address in ASLB, and restore table address upon S3 resume. Implementation largely based on existing Haswell/Lynxpoint code. Test: boot Windows 10 on google/lulu with Tianocore payload and GOP display init, observe display driver loaded and functional, display not black screen when resuming from S3 suspend. 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Change-Id: I5890e17192be9d24418fe25d8afced899777f1aa Signed-off-by: Patrick Georgi <pgeorgi@google.com> Original-Commit-Id: e7513e0d5c418d8f43621c1fb3818c435fa6daa5 Original-Change-Id: I8cf329e5cd2002b225742fefa5c1ddd2598de674 Original-Signed-off-by: Garrett Kirkendall <garrett.kirkendall@amd.corp-partner.google.com> Original-Reviewed-on: https://review.coreboot.org/25161 Original-Reviewed-by: Richard Spiegel <richard.spiegel@silverbackltd.com> Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> Original-Reviewed-by: Martin Roth <martinroth@google.com> Original-Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-on: https://chromium-review.googlesource.com/968443 Commit-Ready: Patrick Georgi <pgeorgi@chromium.org> Tested-by: Patrick Georgi <pgeorgi@chromium.org> Reviewed-by: Patrick Georgi <pgeorgi@chromium.org> " fail_count="0" gerrit_number="968443" owner_email="pgeorgi@chromium.org" pass_count="0" patch_number="1" project="chromiumos/third_party/coreboot" project_url="https://chromium-review.googlesource.com/chromiumos/third_party/coreboot" ref="refs/changes/43/968443/1" remote="cros" total_fail_count="0"/><pending_commit branch="chromeos-2016.05" change_id="I10ba99fb75c942b42dc7480923038550cda06057" commit="d52572bd6001f8e8cead3e868954b921439b05db" commit_message="UPSTREAM: security/tpm: Fix TPM software stack vulnerability * Fix tlcl_read() for TPM 1.2 * https://github.com/nccgroup/TPMGenie BUG=none BRANCH=none TEST=none Change-Id: I10ba99fb75c942b42dc7480923038550cda06057 Signed-off-by: Patrick Georgi <pgeorgi@google.com> Original-Commit-Id: 1356d6288bc85ae8784daef8d663acef9593d19a Original-Change-Id: I1618b2cc579d189bccca7a781e2bed0976a8b471 Original-Signed-off-by: zaolin <zaolin@das-labor.org> Original-Reviewed-on: https://review.coreboot.org/25184 Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> Original-Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-on: https://chromium-review.googlesource.com/968444 Commit-Ready: Patrick Georgi <pgeorgi@chromium.org> Tested-by: Patrick Georgi <pgeorgi@chromium.org> Reviewed-by: Patrick Georgi <pgeorgi@chromium.org> " fail_count="0" gerrit_number="968444" owner_email="pgeorgi@chromium.org" pass_count="0" patch_number="1" project="chromiumos/third_party/coreboot" project_url="https://chromium-review.googlesource.com/chromiumos/third_party/coreboot" ref="refs/changes/44/968444/1" remote="cros" total_fail_count="0"/><pending_commit branch="chromeos-2016.05" change_id="If157750e4c11e042f44fa05c2c8db8b919317647" commit="55f537fda6be6274ec3b1403a298bb3aa336a617" commit_message="UPSTREAM: mb/google/eve: Update DPTF parameters 1) Set the critical temperature threshold to 100C to match changes on other boards. This is intended to reduce DPTF-initiated thermal shutdowns before it has had a chance to react. 2) Reduce the CPU passive threshold sample rate from 5 seconds to 1 second so DPTF will react faster to rapid temperature increases. BUG=b:67459049 BRANCH=eve TEST=manual performance/power testing on Eve hardware Change-Id: If157750e4c11e042f44fa05c2c8db8b919317647 Signed-off-by: Patrick Georgi <pgeorgi@google.com> Original-Commit-Id: 211bb97c67ce704fb40abb6dd9971790652237e3 Original-Change-Id: Ib660dcb25422fea0aa692fac5ba65b49808965ba Original-Signed-off-by: Duncan Laurie <dlaurie@chromium.org> Original-Reviewed-on: https://review.coreboot.org/25153 Original-Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Original-Reviewed-by: Furquan Shaikh <furquan@google.com> Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> Original-Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-on: https://chromium-review.googlesource.com/968445 Commit-Ready: Patrick Georgi <pgeorgi@chromium.org> Tested-by: Patrick Georgi <pgeorgi@chromium.org> Reviewed-by: Patrick Georgi <pgeorgi@chromium.org> " fail_count="0" gerrit_number="968445" owner_email="pgeorgi@chromium.org" pass_count="0" patch_number="1" project="chromiumos/third_party/coreboot" project_url="https://chromium-review.googlesource.com/chromiumos/third_party/coreboot" ref="refs/changes/45/968445/1" remote="cros" total_fail_count="0"/><pending_commit branch="chromeos-2016.05" change_id="I7c93328d333f4a8557a60eab7661547d0f600005" commit="b8e21107fcdf7a7685a48061f97410620d9796ec" commit_message="UPSTREAM: soc/amd/stoneyridge/southbridge.c: Create AOAC initialization code Devices that need to have their AOAC register enabled do have a delay before they become available. Currently each device has their own wait loop. Create a procedure that initializes all AOAC devices in a table and wait for all AOAC to become alive, then call this new procedure before the call to initialize the UART. Then change all procedures that initialize some AOAC by moving the devices to the table and removing AOAC initialization code. BUG=b:74416098 TEST=Build and boot kahlee checking that UART is sending debug messages out. Change-Id: I7c93328d333f4a8557a60eab7661547d0f600005 Signed-off-by: Patrick Georgi <pgeorgi@google.com> Original-Commit-Id: 0e0e93cce1a4707f169154d01478ac6faa1be771 Original-Change-Id: I359791c2a332629aa991f2f17a67e94726a21eb5 Original-Signed-off-by: Richard Spiegel <richard.spiegel@silverbackltd.com> Original-Reviewed-on: https://review.coreboot.org/25142 Original-Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> Original-Reviewed-by: Martin Roth <martinroth@google.com> Reviewed-on: https://chromium-review.googlesource.com/968446 Commit-Ready: Patrick Georgi <pgeorgi@chromium.org> Tested-by: Patrick Georgi <pgeorgi@chromium.org> Reviewed-by: Patrick Georgi <pgeorgi@chromium.org> " fail_count="0" gerrit_number="968446" owner_email="pgeorgi@chromium.org" pass_count="0" patch_number="1" project="chromiumos/third_party/coreboot" project_url="https://chromium-review.googlesource.com/chromiumos/third_party/coreboot" ref="refs/changes/46/968446/1" remote="cros" total_fail_count="0"/><pending_commit branch="chromeos-2016.05" change_id="If7975e1e5648443f4cb8a1b04daf46cd769c8f97" commit="4713631b04be3ce7c427216011e3c697e1ae5ecb" commit_message="UPSTREAM: stoneyridge: Update AGESA binary and AGESA.h AGESA.bin was updated in the binary repo, so update the submodule pointer. Among other changes, this added a callback "AGESA_HALT_THIS_AP", which requires updated header files. BUG=b:70338633 TEST=build kahlee. Change-Id: If7975e1e5648443f4cb8a1b04daf46cd769c8f97 Signed-off-by: Patrick Georgi <pgeorgi@google.com> Original-Commit-Id: 013f1024c3f96ff9a59b70ae6a83ea3d7e9071dc Original-Change-Id: I5a07f1c539d00aed34cfe45d6d7ef60c1dc56566 Original-Signed-off-by: Richard Spiegel <richard.spiegel@silverbackltd.com> Original-Reviewed-on: https://review.coreboot.org/25183 Original-Reviewed-by: Martin Roth <martinroth@google.com> Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> Original-Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-on: https://chromium-review.googlesource.com/968447 Commit-Ready: Patrick Georgi <pgeorgi@chromium.org> Tested-by: Patrick Georgi <pgeorgi@chromium.org> Reviewed-by: Patrick Georgi <pgeorgi@chromium.org> " fail_count="0" gerrit_number="968447" owner_email="pgeorgi@chromium.org" pass_count="0" patch_number="1" project="chromiumos/third_party/coreboot" project_url="https://chromium-review.googlesource.com/chromiumos/third_party/coreboot" ref="refs/changes/47/968447/1" remote="cros" total_fail_count="0"/><pending_commit branch="chromeos-2016.05" change_id="I9a9efd43fa109a1e950b4147566bdebd8f68d781" commit="6eb5717095147107f9abc55684693adf29e1133b" commit_message="UPSTREAM: soc/amd/stoneyridge: Create a HALT_THIS_AP callout It was required for all cores use the same CAR teardown function (exit_car.S and gcccar.inc). AGESA has already been modified to do the AP to do the call out. Create assembly code to call chipset_teardown_car and then enter an endless loop with halt instruction. Then create the call out that will call this new assembly code. BUG=b:70338633 AGESA COMMIT=3313d277 TEST=Created a debug version of AGESA that would print the returned status of HALT_THIS_AP. Build code without the fix, see the return. Build code with the fix, see that there's no return. Change-Id: I9a9efd43fa109a1e950b4147566bdebd8f68d781 Signed-off-by: Patrick Georgi <pgeorgi@google.com> Original-Commit-Id: a9f49366c09f8902a13221185449a1d0870af1c6 Original-Change-Id: I05ee405812211d93dfdbdc5ee7d9978c2eb585e1 Original-Signed-off-by: Richard Spiegel <richard.spiegel@silverbackltd.com> Original-Reviewed-on: https://review.coreboot.org/24999 Original-Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Original-Reviewed-by: Martin Roth <martinroth@google.com> Reviewed-on: https://chromium-review.googlesource.com/968448 Commit-Ready: Patrick Georgi <pgeorgi@chromium.org> Tested-by: Patrick Georgi <pgeorgi@chromium.org> Reviewed-by: Patrick Georgi <pgeorgi@chromium.org> " fail_count="0" gerrit_number="968448" owner_email="pgeorgi@chromium.org" pass_count="0" patch_number="1" project="chromiumos/third_party/coreboot" project_url="https://chromium-review.googlesource.com/chromiumos/third_party/coreboot" ref="refs/changes/48/968448/1" remote="cros" total_fail_count="0"/><pending_commit branch="chromeos-2016.05" change_id="I1f4992f1bc68d26a34aaa06ce8714d1a7485c926" commit="d13ddee3729e9d912fab6759fa41b61af89967a0" commit_message="UPSTREAM: soc/amd/stoneyridge: Call sb_spibase() early Call sb_spibase() early so that it will set up the SPI base address. This is another step to moving AGESA calls out of the bootblock. BUG=b:74427893 BRANCH=master TEST=Build and boot Grunt. Change-Id: I1f4992f1bc68d26a34aaa06ce8714d1a7485c926 Signed-off-by: Patrick Georgi <pgeorgi@google.com> Original-Commit-Id: 64294eb5e241afe9d93b37b31d8a6310ec8d9279 Original-Change-Id: I665d32f3acb0046eb6abbd363735561f0372f2a0 Original-Signed-off-by: Garrett Kirkendall <garrett.kirkendall@amd.corp-partner.google.com> Original-Reviewed-on: https://review.coreboot.org/25246 Original-Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> Original-Reviewed-by: Richard Spiegel <richard.spiegel@silverbackltd.com> Original-Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-on: https://chromium-review.googlesource.com/968449 Commit-Ready: Patrick Georgi <pgeorgi@chromium.org> Tested-by: Patrick Georgi <pgeorgi@chromium.org> Reviewed-by: Patrick Georgi <pgeorgi@chromium.org> " fail_count="0" gerrit_number="968449" owner_email="pgeorgi@chromium.org" pass_count="0" patch_number="1" project="chromiumos/third_party/coreboot" project_url="https://chromium-review.googlesource.com/chromiumos/third_party/coreboot" ref="refs/changes/49/968449/1" remote="cros" total_fail_count="0"/><pending_commit branch="master" change_id="I60d8574c827c1102f0968766b1e6c4a50f56071a" commit="b7f7c37a9870908cc03703df1a0a68dfafdd1400" commit_message="poppy: Increase task stack sizes, add stack analysis annotations On cros/firmware-poppy-10431.B, plus the patches on this branch: make BOARD=soraka SECTION=RO analyzestack | grep Task Task: HOOKS, Max size: 776 (552 + 224), Allocated size: 800 Task: USB_CHG_P0, Max size: 696 (472 + 224), Allocated size: 800 Task: USB_CHG_P1, Max size: 696 (472 + 224), Allocated size: 800 Task: CHARGER, Max size: 776 (552 + 224), Allocated size: 800 Task: MOTIONSENSE, Max size: 664 (440 + 224), Allocated size: 768 Task: CHIPSET, Max size: 760 (536 + 224), Allocated size: 800 Task: PDCMD, Max size: 784 (560 + 224), Allocated size: 880 Task: HOSTCMD, Max size: 808 (584 + 224), Allocated size: 840 Task: CONSOLE, Max size: 856 (632 + 224), Allocated size: 960 Task: POWERBTN, Max size: 728 (504 + 224), Allocated size: 800 Task: PD_C0, Max size: 912 (688 + 224), Allocated size: 1000 Task: PD_C1, Max size: 912 (688 + 224), Allocated size: 1000 (RW returns identical values) All tasks have a good amount of slack (some have even more, as poppy board requires even more stack size than soraka). Shared_mem_buf at: 200c7400 D __shared_mem_buf (so there is still 3072 bytes of available RAM) BRANCH=none BUG=b:75234824 TEST=See line above, EC software sync still works Change-Id: I60d8574c827c1102f0968766b1e6c4a50f56071a Signed-off-by: Nicolas Boichat <drinkcat@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/966044 Reviewed-by: Vincent Palatin <vpalatin@chromium.org> " fail_count="0" gerrit_number="966044" owner_email="drinkcat@chromium.org" pass_count="0" patch_number="5" project="chromiumos/platform/ec" project_url="https://chromium-review.googlesource.com/chromiumos/platform/ec" ref="refs/changes/44/966044/5" remote="cros" total_fail_count="0"/><pending_commit branch="master" change_id="Ia98b27a924d0023a5fb3bfef5280e9365e6ddf4b" commit="5c537a11ce04897673a013e272eacc7f86971ddb" commit_message="nautilus: Increase task stack sizes, add stack analysis annotations On cros/firmware-poppy-10431.B, plus the patches on this branch: make BOARD=nautilus SECTION=RW analyzestack | grep Task Task: HOOKS, Max size: 728 (504 + 224), Allocated size: 800 Task: USB_CHG_P0, Max size: 672 (448 + 224), Allocated size: 720 Task: USB_CHG_P1, Max size: 672 (448 + 224), Allocated size: 720 Task: CHARGER, Max size: 712 (488 + 224), Allocated size: 800 Task: MOTIONSENSE, Max size: 720 (496 + 224), Allocated size: 768 Task: CHIPSET, Max size: 744 (520 + 224), Allocated size: 800 Task: KEYPROTO, Max size: 516 (292 + 224), Allocated size: 600 Task: PDCMD, Max size: 776 (552 + 224), Allocated size: 800 Task: HOSTCMD, Max size: 792 (568 + 224), Allocated size: 840 Task: CONSOLE, Max size: 840 (616 + 224), Allocated size: 880 Task: POWERBTN, Max size: 696 (472 + 224), Allocated size: 800 Task: KEYSCAN, Max size: 584 (360 + 224), Allocated size: 600 Task: PD_C0, Max size: 896 (672 + 224), Allocated size: 1000 Task: PD_C1, Max size: 896 (672 + 224), Allocated size: 1000 RO is identical 200c7720 D __shared_mem_buf There is still 2272 bytes of shared memory. BRANCH=poppy BUG=b:75234825 TEST=See above, software sync still works Change-Id: Ia98b27a924d0023a5fb3bfef5280e9365e6ddf4b Signed-off-by: Nicolas Boichat <drinkcat@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/965706 Reviewed-by: Vincent Palatin <vpalatin@chromium.org> " fail_count="0" gerrit_number="965706" owner_email="drinkcat@chromium.org" pass_count="0" patch_number="5" project="chromiumos/platform/ec" project_url="https://chromium-review.googlesource.com/chromiumos/platform/ec" ref="refs/changes/06/965706/5" remote="cros" total_fail_count="0"/><lkgm version="10501.0.0-rc1"/></manifest> |
