| /* SPDX-License-Identifier: BSD-3-Clause |
| * |
| * Copyright (c) 2020 The Chromium OS Authors |
| */ |
| |
| /dts-v1/; |
| #include <st/f1/stm32f103Xg.dtsi> |
| #include <st/f1/stm32f103z(f-g)hx-pinctrl.dtsi> |
| #include "gpio_defines.h" |
| |
| / { |
| model = "Google Chameleon"; |
| compatible = "st,stm32f103zg", "st,stm32f103"; |
| |
| chosen { |
| zephyr,console = &usart1; |
| zephyr,shell-uart = &usart1; |
| zephyr,sram = &sram0; |
| zephyr,flash = &flash0; |
| }; |
| |
| leds { |
| compatible = "gpio-leds"; |
| power_good_led { |
| gpios = <&gpiob 14 GPIO_OUTPUT_HIGH>; |
| label = "POWER_GOOD"; |
| }; |
| }; |
| |
| sd-mux { |
| compatible = "gpio-keys"; |
| |
| sd_mux_sel { |
| gpios = <&gpioe 0 GPIO_OUTPUT_LOW>; |
| label = "SD_MUX_SEL"; |
| }; |
| |
| sd_mux_en_l { |
| gpios = <&gpioe 1 GPIO_OUTPUT_HIGH>; |
| label = "SD_MUX_EN_L"; |
| }; |
| |
| usd_pwr_sel { |
| gpios = <&gpiob 13 GPIO_OUTPUT_LOW>; |
| label = "USD_PWR_SEL"; |
| }; |
| |
| usd_pwr_en { |
| gpios = <&gpioe 4 GPIO_OUTPUT_LOW>; |
| label = "USD_PWR_EN"; |
| }; |
| |
| usd_cd_det { |
| gpios = <&gpioe 2 GPIO_INPUT_PULL_UP>; |
| label = "USD_CD_DET"; |
| }; |
| }; |
| |
| sysmon { |
| compatible = "gpio-keys"; |
| |
| sysmon_sel { |
| gpios = <&gpioc 6 GPIO_OUTPUT_HIGH>; |
| label = "SYSMON_SEL"; |
| }; |
| }; |
| |
| fpga { |
| compatible = "gpio-keys"; |
| |
| pwr_en { |
| gpios = <&gpioc 7 GPIO_OUTPUT_LOW>; |
| label = "SOM_PWR_EN"; |
| }; |
| |
| pwr_good { |
| gpios = <&gpioc 8 GPIO_INPUT_PULL_UP>; |
| label = "SOM_PWR_GOOD"; |
| }; |
| |
| boot_mode1 { |
| gpios = <&gpiod 1 GPIO_OUTPUT_HIGH>; |
| label = "SOM_BOOT_MODE1"; |
| }; |
| |
| boot_mode0 { |
| gpios = <&gpiod 0 GPIO_OUTPUT_HIGH>; |
| label = "SOM_BOOT_MODE0"; |
| }; |
| |
| por_l_load_l { |
| gpios = <&gpiob 1 GPIO_OUTPUT_LOW>; |
| label = "SOM_POR_L_LOAD_L"; |
| }; |
| |
| fpga_done { |
| gpios = <&gpiob 0 GPIO_INPUT_PULL_UP>; |
| label = "SOM_FPGA_DONE"; |
| }; |
| }; |
| |
| misc { |
| compatible = "gpio-keys"; |
| |
| tp126 { |
| gpios = <&u78 11 GPIO_OUTPUT_LOW>; |
| label = "TP126"; |
| }; |
| |
| tp125 { |
| gpios = <&u78 12 GPIO_OUTPUT_LOW>; |
| label = "TP125"; |
| }; |
| |
| board_version_2 { |
| gpios = <&u78 13 GPIO_INPUT>; |
| label = "BOARD_VERSION_2"; |
| }; |
| |
| board_version_1 { |
| gpios = <&u78 14 GPIO_INPUT>; |
| label = "BOARD_VERSION_1"; |
| }; |
| |
| board_version_0 { |
| gpios = <&u78 15 GPIO_INPUT>; |
| label = "BOARD_VERSION_0"; |
| }; |
| }; |
| |
| i2c-switch { |
| compatible = "gpio-keys"; |
| |
| exp_reset { |
| gpios = <&gpiob 8 GPIO_OUTPUT_HIGH>; |
| label = "I2C1_EXP_RESET_L"; |
| }; |
| |
| exp_irq { |
| gpios = <&gpiob 5 GPIO_INPUT_PULL_UP>; |
| label = "I2C1_SMBA"; |
| }; |
| }; |
| |
| videomux { |
| compatible = "gpio-keys"; |
| |
| /* |
| * I/Os are initially set to connect HDMI signals to the FPGA |
| * MGTs and DisplayPort signals through the DP->HDMI converter |
| * to the HDMI Receiver. |
| */ |
| gp213_it68051p1_ch_sel { |
| /* GPU_SEL on U18 */ |
| gpios = <&gpiog 1 GPIO_OUTPUT_LOW>; |
| label = "GP213_IT68051P1_CH_SEL"; |
| }; |
| |
| dp1_ps8468_sw { |
| /* SW on U3 */ |
| gpios = <&gpiog 12 GPIO_OUTPUT_LOW>; |
| label = "DP1_PS8468_SW"; |
| }; |
| |
| hdmi1_gp213_ch_sel { |
| /* GPU_SEL on U10 */ |
| gpios = <&gpiog 0 GPIO_OUTPUT_HIGH>; |
| label = "HDMI1_GP213_CH_SEL"; |
| }; |
| |
| somp1_mode_sel { |
| /* GPU_SEL on U11 */ |
| gpios = <&gpiog 4 GPIO_OUTPUT_HIGH>; |
| label = "SOMP1_MODE_SEL"; |
| }; |
| |
| /* |
| * Note that all of the channels are designated 1&2 except for |
| * the IT68051, which has ports 1 (channel 1 on the other |
| * switches) and 0 (channel 2 on the other switches). |
| */ |
| gp213_it68051p0_ch_sel { |
| /* GPU_SEL on U31 */ |
| gpios = <&gpiog 3 GPIO_OUTPUT_LOW>; |
| label = "GP213_IT68051P0_CH_SEL"; |
| }; |
| |
| dp2_ps8468_sw { |
| /* SW on U22 */ |
| gpios = <&gpiog 13 GPIO_OUTPUT_LOW>; |
| label = "DP2_PS8468_SW"; |
| }; |
| |
| hdmi2_gp213_ch_sel { |
| /* GPU_SEL on U29 */ |
| gpios = <&gpiog 2 GPIO_OUTPUT_HIGH>; |
| label = "HDMI2_GP213_CH_SEL"; |
| }; |
| |
| somp2_mode_sel { |
| /* GPU_SEL on U14 */ |
| gpios = <&gpiog 5 GPIO_OUTPUT_HIGH>; |
| label = "SOMP2_MODE_SEL"; |
| }; |
| |
| /* |
| * Reset lines for the PS8468 demuxes. All of the other |
| * mux/demux chips do not have reset lines. |
| */ |
| dp1_ps8468_rst_l { |
| /* RESETN on U3 */ |
| gpios = <&gpiof 5 GPIO_OUTPUT_HIGH>; |
| label = "DP1_PS8468_RST_L"; |
| }; |
| |
| dp2_ps8468_rst_l { |
| /* RESETN on U22 */ |
| gpios = <&gpiof 11 GPIO_OUTPUT_HIGH>; |
| label = "DP2_PS8468_RST_L"; |
| }; |
| |
| /* |
| * Reset lines for the MCDP2900 DP->HDMI converters. |
| */ |
| dp1_hdmi_rst_l { |
| /* EX_RESETN on U17 */ |
| gpios = <&gpiog 10 GPIO_OUTPUT_HIGH>; |
| label = "DP1_HDMI_RST_L"; |
| }; |
| |
| dp2_hdmi_rst_l { |
| /* EX_RESETN on U30 */ |
| gpios = <&gpiog 11 GPIO_OUTPUT_HIGH>; |
| label = "DP2_HDMI_RST_L"; |
| }; |
| }; |
| |
| it68051 { |
| compatible = "gpio-keys"; |
| |
| it68051p0_pwr_det { |
| gpios = <&gpiof 0 GPIO_OUTPUT_HIGH>; |
| label = "IT68051P0_PWR_DET"; |
| }; |
| |
| it68051p1_pwr_det { |
| gpios = <&gpiof 1 GPIO_OUTPUT_HIGH>; |
| label = "IT68051P1_PWR_DET"; |
| }; |
| |
| it68051_rst_l { |
| gpios = <&gpiof 2 GPIO_OUTPUT_LOW>; |
| label = "IT68051_RST_L"; |
| }; |
| |
| it68051p0_ddc_bp_l { |
| gpios = <&gpiod 6 GPIO_OUTPUT_LOW>; |
| label = "IT68051P0_DDC_BP_L"; |
| }; |
| |
| it68051p1_ddc_bp_l { |
| gpios = <&gpiod 11 GPIO_OUTPUT_LOW>; |
| label = "IT68051P1_DDC_BP_L"; |
| }; |
| |
| gp213_it68051p1_hpd { |
| gpios = <&gpioe 15 GPIO_OUTPUT_LOW>; |
| label = "GP213_IT68051P1_HPD"; |
| }; |
| |
| /* |
| * I2C signals for STM32 to provide the EDID (future use) |
| * Right now, set them input/pull-up so they don't interfere with |
| * the IT68051's I2C bus. |
| */ |
| gp213_it68051p0_ddc_scl { |
| gpios = <&gpiod 7 GPIO_INPUT_PULL_UP>; |
| label = "GP213_IT68051P0_DDC_SCL"; |
| }; |
| |
| gp213_it68051p0_ddc_sda { |
| gpios = <&gpiod 8 GPIO_INPUT_PULL_UP>; |
| label = "GP213_IT68051P0_DDC_SDA"; |
| }; |
| |
| stm32_it68051p0_ddc_scl { |
| gpios = <&gpiod 9 GPIO_INPUT_PULL_UP>; |
| label = "STM32_IT68051P0_DDC_SCL"; |
| }; |
| |
| stm32_it68051p0_ddc_sda { |
| gpios = <&gpiod 10 GPIO_INPUT_PULL_UP>; |
| label = "STM32_IT68051P0_DDC_SDA"; |
| }; |
| |
| gp213_it68051p1_ddc_scl { |
| gpios = <&gpiod 12 GPIO_INPUT_PULL_UP>; |
| label = "GP213_IT68051P1_DDC_SCL"; |
| }; |
| |
| gp213_it68051p1_ddc_sda { |
| gpios = <&gpiod 13 GPIO_INPUT_PULL_UP>; |
| label = "GP213_IT68051P1_DDC_SDA"; |
| }; |
| |
| stm32_it68051p1_ddc_scl { |
| gpios = <&gpiod 14 GPIO_INPUT_PULL_UP>; |
| label = "STM32_IT68051P1_DDC_SCL"; |
| }; |
| |
| stm32_it68051p1_ddc_sda { |
| gpios = <&gpiod 15 GPIO_INPUT_PULL_UP>; |
| label = "STM32_IT68051P1_DDC_SDA"; |
| }; |
| }; |
| |
| hotplug { |
| compatible = "gpio-keys"; |
| |
| dp1_auxp_det { |
| gpios = <&gpioe 5 GPIO_INPUT>; |
| label = "DP1_AUXP_DET"; |
| }; |
| |
| dp1_auxn_det { |
| gpios = <&gpioe 6 GPIO_INPUT>; |
| label = "DP1_AUXN_DET"; |
| }; |
| |
| dp2_auxp_det { |
| gpios = <&gpioe 7 GPIO_INPUT>; |
| label = "DP2_AUXP_DET"; |
| }; |
| |
| dp2_auxn_det { |
| gpios = <&gpioe 8 GPIO_INPUT>; |
| label = "DP2_AUXN_DET"; |
| }; |
| |
| hdmi1_pp3300 { |
| gpios = <&gpioe 9 GPIO_INPUT_PULL_DOWN>; |
| label = "HDMI1_PP3300"; |
| }; |
| |
| hdmi2_pp3300 { |
| gpios = <&gpioe 10 GPIO_INPUT_PULL_DOWN>; |
| label = "HDMI2_PP3300"; |
| }; |
| |
| /* |
| * DP1 and DP2 HPD can be controlled by PE11 and PE12, or by |
| * the HPD_SRC signal on the PS8468 demux/redriver, depending |
| * on which of two optional-load resistors is stuffed. The |
| * Proto 0 boards have R20 and R141 stuffed, while R22 and |
| * R143 are not stuffed, so the HPD signals for the DisplayPort |
| * connecters are controlled by the PS8468 and anything the |
| * STM32 does will have no effect. |
| */ |
| dp1_mcu_hpd { |
| gpios = <&gpioe 11 GPIO_OUTPUT_LOW>; |
| label = "DP1_MCU_HPD"; |
| }; |
| |
| dp2_mcu_hpd { |
| gpios = <&gpioe 12 GPIO_OUTPUT_LOW>; |
| label = "DP2_MCU_HPD"; |
| }; |
| |
| /* |
| * HDMI1 and HDMI2 HPD can be controlled by PE13 and PE14, |
| * or by the HDMI1_RP_HPD/HDMI2_RP_HPD signals on the |
| * EP91A6SQ redriver, depending on which of two optional-load |
| * resistors is stuffed. The Proto 0 boards have R41 and R164 |
| * stuffed, while R42 and R164 are not stuffed, so the HPD |
| * signals for the HDMI connecters are controlled by the |
| * EP91A6SQ and anything the STM32 does will have no effect. |
| */ |
| hdmi1_mcu_hpd { |
| gpios = <&gpioe 13 GPIO_OUTPUT_LOW>; |
| label = "HDMI1_MCU_HPD"; |
| }; |
| |
| hdmi2_mcu_hpd { |
| gpios = <&gpioe 14 GPIO_OUTPUT_LOW>; |
| label = "HDMI2_MCU_HPD"; |
| }; |
| |
| dp_in_pwr_en { |
| gpios = <&u79 15 GPIO_OUTPUT_HIGH>; |
| label = "DP_IN_PWR_EN"; |
| }; |
| }; |
| dp_cfg { |
| compatible = "gpio-keys"; |
| |
| /* |
| * Most of these are GPIO_INPUT to allow the pull-up/pull-down |
| * resistors to apply the desired level. We only want to actively |
| * drive the MODE pins to select manual mux control by the SW pin. |
| */ |
| dp1_ps8468_mode { |
| gpios = <&u77 0 GPIO_OUTPUT_LOW>; |
| label = "DP1_PS8468_MODE"; |
| }; |
| |
| dp1_ps8468_cfg0 { |
| gpios = <&u77 1 GPIO_INPUT>; |
| label = "DP1_PS8468_CFG0"; |
| }; |
| |
| dp1_ps8468_cfg1 { |
| gpios = <&u77 2 GPIO_INPUT>; |
| label = "DP1_PS8468_CFG1"; |
| }; |
| |
| dp1_ps8468_cfg2 { |
| gpios = <&u77 3 GPIO_INPUT>; |
| label = "DP1_PS8468_CFG2"; |
| }; |
| |
| dp1_ps8468_cfg3 { |
| gpios = <&u77 4 GPIO_INPUT>; |
| label = "DP1_PS8468_CFG3"; |
| }; |
| |
| dp1_ps8468_cfg4 { |
| gpios = <&u77 5 GPIO_INPUT>; |
| label = "DP1_PS8468_CFG4"; |
| }; |
| |
| dp1_ps8468_eq0 { |
| gpios = <&u77 6 GPIO_INPUT>; |
| label = "DP1_PS8468_EQ0"; |
| }; |
| |
| dp1_ps8468_eq1 { |
| gpios = <&u77 7 GPIO_INPUT>; |
| label = "DP1_PS8468_EQ1"; |
| }; |
| |
| dp2_ps8468_mode { |
| gpios = <&u77 8 GPIO_OUTPUT_LOW>; |
| label = "DP2_PS8468_MODE"; |
| }; |
| |
| dp2_ps8468_cfg0 { |
| gpios = <&u77 9 GPIO_INPUT>; |
| label = "DP2_PS8468_CFG0"; |
| }; |
| |
| dp2_ps8468_cfg1 { |
| gpios = <&u77 10 GPIO_INPUT>; |
| label = "DP2_PS8468_CFG1"; |
| }; |
| |
| dp2_ps8468_cfg2 { |
| gpios = <&u77 11 GPIO_INPUT>; |
| label = "DP2_PS8468_CFG2"; |
| }; |
| |
| dp2_ps8468_cfg3 { |
| gpios = <&u77 12 GPIO_INPUT>; |
| label = "DP2_PS8468_CFG3"; |
| }; |
| |
| dp2_ps8468_cfg4 { |
| gpios = <&u77 13 GPIO_INPUT>; |
| label = "DP2_PS8468_CFG4"; |
| }; |
| |
| dp2_ps8468_eq0 { |
| gpios = <&u77 14 GPIO_INPUT>; |
| label = "DP2_PS8468_EQ0"; |
| }; |
| |
| dp2_ps8468_eq1 { |
| gpios = <&u77 15 GPIO_INPUT>; |
| label = "DP2_PS8468_EQ1"; |
| }; |
| }; |
| }; |
| |
| &usart1 { |
| pinctrl-0 = <&usart1_tx_pa9 &usart1_rx_pa10>; |
| current-speed = <115200>; |
| status = "okay"; |
| }; |
| |
| &usart2 { |
| pinctrl-0 = <&usart2_tx_pa2 &usart2_rx_pa3>; |
| current-speed = <115200>; |
| status = "okay"; |
| }; |
| |
| &uart4 { |
| pinctrl-0 = <&uart4_tx_pc10 &uart4_rx_pc11>; |
| current-speed = <115200>; |
| status = "okay"; |
| }; |
| |
| &uart5 { |
| pinctrl-0 = <&uart5_tx_pc12 &uart5_rx_pd2>; |
| current-speed = <115200>; |
| status = "okay"; |
| }; |
| |
| &spi1 { |
| pinctrl-0 = <&spi1_nss_master_pa4 &spi1_sck_master_pa5 |
| &spi1_miso_master_pa6 &spi1_mosi_master_pa7>; |
| status = "okay"; |
| }; |
| |
| &i2c1 { |
| pinctrl-0 = <&i2c1_scl_pb6 &i2c1_sda_pb7>; |
| status = "okay"; |
| }; |
| |
| &i2c2 { |
| pinctrl-0 = <&i2c2_scl_pb10 &i2c2_sda_pb11>; |
| status = "okay"; |
| |
| /* U77 I/O expander, config signals for PS8468 */ |
| u77: pca95xx@20 { |
| compatible = "nxp,pca95xx"; |
| label = "U77 - PCA95XX"; |
| reg = <0x20>; |
| #gpio-cells = <2>; |
| gpio-controller; |
| }; |
| |
| /* U78 I/O expander, DP1 OUT config signals, plus misc I/O */ |
| u78: pca95xx@21 { |
| compatible = "nxp,pca95xx"; |
| label = "U78 - PCA95XX"; |
| reg = <0x21>; |
| #gpio-cells = <2>; |
| gpio-controller; |
| }; |
| |
| /* U79 I/O expander DP2 OUT config, HDMI input reset, DP IN power */ |
| u79: pca95xx@23 { |
| compatible = "nxp,pca95xx"; |
| label = "U79 - PCA95XX"; |
| reg = <0x23>; |
| #gpio-cells = <2>; |
| gpio-controller; |
| }; |
| }; |
| |
| &adc1 { |
| pinctrl-0 = <&adc1_in10_pc0 &adc1_in11_pc1 &adc1_in12_pc2 |
| &adc1_in13_pc3 &adc1_in14_pc4 &adc1_in15_pc5>; |
| status = "okay"; |
| }; |
| |
| &adc3 { |
| /* These ADC inputs are only available on ADC3 */ |
| pinctrl-0 = <&adc3_in4_pf6 &adc3_in5_pf7 &adc3_in6_pf8 |
| &adc3_in7_pf9 &adc3_in8_pf10>; |
| status = "okay"; |
| }; |
| |
| &usb { |
| pinctrl-0 = <&usb_dm_pa11 &usb_dp_pa12>; |
| status = "okay"; |
| }; |
| |
| &timers1 { |
| status = "okay"; |
| }; |
| |
| &systick { |
| status = "okay"; |
| }; |