Gandof: Initial Depthcharge commit
Cloned entirely from Auron_paine, with only string changes.
BUG=chrome-os-partner:38462
TEST=None
BRANCH=None
Signed-off-by: Pan Sheng-Liang <Sheng-Liang.Pan@quantatw.com>
Change-Id: I1dd00bf128917bed1099b69c186d49775e1ba588
Reviewed-on: https://chromium-review.googlesource.com/264913
Reviewed-by: Mike M Hsieh <mike.m.hsieh@intel.com>
Commit-Queue: Mike M Hsieh <mike.m.hsieh@intel.com>
Tested-by: Mike M Hsieh <mike.m.hsieh@intel.com>
Reviewed-by: Ryan Lin <ryan.lin@intel.com>
Reviewed-by: Shawn N <shawnn@chromium.org>
diff --git a/board/gandof/defconfig b/board/gandof/defconfig
new file mode 100644
index 0000000..e024207
--- /dev/null
+++ b/board/gandof/defconfig
@@ -0,0 +1,32 @@
+# Arch
+CONFIG_ARCH_X86=y
+
+# Board
+CONFIG_BOARD="gandof"
+
+# Image
+CONFIG_FMAP_OFFSET=0x610000
+
+# Vboot
+CONFIG_EC_SOFTWARE_SYNC=y
+CONFIG_OPROM_MATTERS=y
+CONFIG_RO_NORMAL_SUPPORT=y
+CONFIG_VIRTUAL_DEV_SWITCH=y
+
+CONFIG_CROSSYSTEM_ACPI=y
+CONFIG_NV_STORAGE_CMOS=y
+
+# Kernel format
+CONFIG_KERNEL_ZIMAGE=y
+
+# Drivers
+CONFIG_DRIVER_AHCI=y
+CONFIG_DRIVER_EC_CROS=y
+CONFIG_DRIVER_EC_CROS_LPC=y
+CONFIG_DRIVER_FLASH_MEMMAPPED=y
+CONFIG_DRIVER_GPIO_LYNXPOINT_LP=y
+CONFIG_DRIVER_INPUT_PS2=y
+CONFIG_DRIVER_INPUT_USB=y
+CONFIG_DRIVER_POWER_PCH=y
+CONFIG_DRIVER_SOUND_HDA=y
+CONFIG_DRIVER_TPM_LPC=y
diff --git a/board/gandof/fmap.dts b/board/gandof/fmap.dts
new file mode 100644
index 0000000..0aafe78
--- /dev/null
+++ b/board/gandof/fmap.dts
@@ -0,0 +1,314 @@
+/dts-v1/;
+
+/ {
+ model = "Google Gandof";
+ config {
+ hwid = "GANDOF TEST A-A 6718";
+ };
+ chromeos-config {
+ /* Enable factory-friendly features. */
+ gbb-flag-dev-screen-short-delay;
+ gbb-flag-force-dev-switch-on;
+ gbb-flag-force-dev-boot-usb;
+ gbb-flag-disable-fw-rollback-check;
+ };
+ flash@ff800000 {
+ #address-cells = <1>;
+ #size-cells = <1>;
+ compatible = "chromeos,flashmap";
+ reg = <0xff800000 0x00800000>;
+
+ /*
+ * Non-BIOS section of the Intel Firmware Descriptor image.
+ * This section covers the all the parts that are not shown
+ * to the CPU right below 4G.
+ */
+ si-all {
+ label = "si-all";
+ reg = <0x00000000 0x00200000>;
+ type = "ifd";
+ };
+
+ /*
+ * Firmware Descriptor section of the Intel Firmware Descriptor
+ * image.
+ */
+ si-desc {
+ label = "si-desc";
+ reg = <0x00000000 0x00001000>;
+ };
+
+ /*
+ * Intel Management Engine section of the Intel Firmware
+ * Descriptor image.
+ */
+ si-me {
+ label = "si-me";
+ reg = <0x00001000 0x001ff000>;
+ };
+
+ /*
+ * "BIOS" section of the Intel Firmware Descriptor image.
+ * This section covers the complete image as shown to the
+ * CPU right below 4G.
+ */
+ si-bios {
+ label ="si-bios";
+ reg = <0x00200000 0x00600000>;
+ };
+
+ /* ---- Section: Rewritable slot A ---- */
+ rw-a {
+ label = "rw-section-a";
+ /* Alignment: 4k (for updating) */
+ reg = <0x00200000 0x000f0000>;
+ };
+ rw-a-vblock {
+ label = "vblock-a";
+ /*
+ * Alignment: 4k (for updating) and must be in start of
+ * each RW_SECTION.
+ */
+ reg = <0x00200000 0x00010000>;
+ type = "keyblock boot,ecrwhash,ramstage,refcode";
+ with_index;
+ keyblock = "firmware.keyblock";
+ signprivate = "firmware_data_key.vbprivk";
+ version = <1>;
+ kernelkey = "kernel_subkey.vbpubk";
+ preamble-flags = <0>;
+ };
+ rw-a-boot {
+ /* Alignment: no requirement (yet). */
+ label = "fw-main-a";
+ reg = <0x00210000 0x000c0000>;
+ type = "blob boot,ecrwhash,ramstage,refcode";
+ with_index;
+ };
+ rw-a-ec-boot {
+ label = "ec-main-a";
+ type = "blob ecbin";
+ reg = <0x002d0000 0x0001ffc0>;
+ with_index;
+ };
+ rw-a-firmware-id {
+ /* Alignment: no requirement. */
+ label = "rw-fwid-a";
+ reg = <0x002effc0 0x00000040>;
+ read-only;
+ type = "blobstring fwid";
+ };
+
+ /* ---- Section: Rewritable slot B ---- */
+ rw-b {
+ label = "rw-section-b";
+ /* Alignment: 4k (for updating) */
+ reg = <0x002f0000 0x000f0000>;
+ };
+ rw-b-vblock {
+ label = "vblock-b";
+ /*
+ * Alignment: 4k (for updating) and must be in start of
+ * each RW_SECTION.
+ */
+ reg = <0x002f0000 0x00010000>;
+ type = "keyblock boot,ecrwhash,ramstage,refcode";
+ with_index;
+ keyblock = "firmware.keyblock";
+ signprivate = "firmware_data_key.vbprivk";
+ version = <1>;
+ kernelkey = "kernel_subkey.vbpubk";
+ preamble-flags = <0>;
+ };
+ rw-b-boot {
+ label = "fw-main-b";
+ /* Alignment: no requirement (yet). */
+ reg = <0x00300000 0x000c0000>;
+ type = "blob boot,ecrwhash,ramstage,refcode";
+ with_index;
+ };
+ rw-b-ec-boot {
+ label = "ec-main-b";
+ type = "blob ecbin";
+ reg = <0x003c0000 0x0001ffc0>;
+ with_index;
+ };
+ rw-b-firmware-id {
+ label = "rw-fwid-b";
+ /* Alignment: no requirement. */
+ reg = <0x003dffc0 0x00000040>;
+ read-only;
+ type = "blobstring fwid";
+ };
+
+ /* ---- Section: Rewritable MRC cache 64KB ---- */
+ rw-mrc-cache {
+ label = "rw-mrc-cache";
+ /* Alignment: 4k (for updating) */
+ reg = <0x003e0000 0x00010000>;
+ type = "wiped";
+ wipe-value = [ff];
+ };
+
+ /* ---- Section: Rewritable Event Log 16KB ---- */
+ rw-elog {
+ label = "rw-elog";
+ /* Alignment: 4k (for updating) */
+ reg = <0x003f0000 0x00004000>;
+ type = "wiped";
+ wipe-value = [ff];
+ };
+
+ /* ---- Section: Rewritable shared 16 KB---- */
+ shared-section {
+ /*
+ * Alignment: 4k (for updating).
+ * Anything in this range may be updated in recovery.
+ */
+ label = "rw-shared";
+ reg = <0x003f4000 0x00004000>;
+ };
+ shared-data {
+ label = "shared-data";
+ /*
+ * Alignment: 4k (for random read/write).
+ * RW firmware can put calibration data here.
+ */
+ reg = <0x003f4000 0x00002000>;
+ type = "wiped";
+ wipe-value = [00];
+ };
+
+ rw-vblock-dev {
+ label = "vblock-dev";
+ /*
+ * Alignment: 4k (for random read/write).
+ * Reserve space for an optional user-installed
+ * vblock to validate dev-mode kernels.
+ * See crosbug.com/p/11216.
+ */
+ reg = <0x003f6000 0x00002000>;
+ type = "wiped";
+ wipe-value = [ff];
+ };
+
+ /* ---- Section: Rewritable private 16 KB---- */
+
+ /* ---- Section: Rewritable VPD 8 KB ---- */
+ rw-vpd {
+ label = "rw-vpd";
+ /* Alignment: 4k (for updating) */
+ reg = <0x003f8000 0x00002000>;
+ type = "wiped";
+ wipe-value = [ff];
+ };
+
+ /*
+ * This space is currently unused and reserved for future
+ * extensions. cros_bundle_firmware dislikes holes in the
+ * FMAP, so we cover all empty space here.
+ */
+ rw-unused {
+ label = "rw-unused";
+ reg = <0x003fa000 0x00006000>;
+ type = "wiped";
+ wipe-value = [ff];
+ };
+
+ rw-legacy {
+ label = "rw-legacy";
+ reg = <0x00400000 0x00200000>;
+ type = "blob legacy";
+ read-only;
+ };
+
+ /*
+ * This describes the portion of the image that will be
+ * write-protected in the factory.
+ */
+ wp-ro {
+ label = "wp-ro";
+ reg = <0x00600000 0x00200000>;
+ read-only;
+ };
+
+ /* ---- Section: Vital-product data (VPD) ---- */
+ ro-vpd {
+ label = "ro-vpd";
+
+ /* VPD offset must be aligned to 4K bytes */
+ reg = <0x00600000 0x00004000>;
+ read-only;
+ type = "wiped";
+ wipe-value = [ff];
+ };
+
+ /*
+ * This space is currently unused and reserved for future
+ * extensions. cros_bundle_firmware dislikes holes in the
+ * FMAP, so we cover all empty space here.
+ */
+ ro-unused {
+ label = "ro-unused";
+ reg = <0x00604000 0x0000c000>;
+ type = "wiped";
+ wipe-value = [ff];
+ };
+
+ /* ---- Section: Read-only ---- */
+ ro-section {
+ label = "ro-section";
+ reg = <0x00610000 0x001f0000>;
+ read-only;
+ };
+ ro-fmap {
+ label = "fmap";
+
+ /*
+ * We encourage to align FMAP partition in as large
+ * block as possible so that flashrom can find it soon.
+ * For example, aligning to 512KB is better than to
+ * 256KB.
+ */
+
+ reg = <0x00610000 0x00000800>;
+ read-only;
+ type = "fmap";
+ ver-major = <1>;
+ ver-minor = <0>;
+ };
+ ro-firmware-id {
+ label = "ro-frid";
+ reg = <0x00610800 0x00000040>;
+ read-only;
+ type = "blobstring fwid";
+ };
+
+ /*
+ * Padding after FRID so the next section is 4K aligned. This
+ * is only needed to avoid gaps in the FMAP and to keep the
+ * next section aligned; FRID itself doesn't care.
+ */
+ ro-firmware-id-pad {
+ label = "ro-frid-pad";
+ reg = <0x00610840 0x000007c0>;
+ type = "wiped";
+ wipe-value = [ff];
+ };
+ ro-gbb {
+ label = "gbb";
+
+ /* GBB offset must be aligned to 4K bytes */
+ reg = <0x00611000 0x000ef000>;
+ read-only;
+ type = "blob gbb";
+ };
+ ro-boot {
+ label = "boot-stub";
+ reg = <0x00700000 0x00100000>; /* 1 MB */
+ read-only;
+ type = "blob coreboot";
+ required;
+ };
+ };
+};
diff --git a/src/board/Kconfig b/src/board/Kconfig
index 0bfbb8d..d14d323 100644
--- a/src/board/Kconfig
+++ b/src/board/Kconfig
@@ -49,6 +49,9 @@
if BOARD = "fox_wtm2"
source src/board/fox_wtm2/Kconfig
endif
+if BOARD = "gandof"
+source src/board/gandof/Kconfig
+endif
if BOARD = "gizmo"
source src/board/gizmo/Kconfig
endif
diff --git a/src/board/gandof/Kconfig b/src/board/gandof/Kconfig
new file mode 100644
index 0000000..f64c238
--- /dev/null
+++ b/src/board/gandof/Kconfig
@@ -0,0 +1,16 @@
+##
+## Copyright 2015 Google Inc. All rights reserved.
+##
+## This program is free software; you can redistribute it and/or modify
+## it under the terms of the GNU General Public License as published by
+## the Free Software Foundation; version 2 of the License.
+##
+## This program is distributed in the hope that it will be useful,
+## but WITHOUT ANY WARRANTY; without even the implied warranty of
+## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+## GNU General Public License for more details.
+##
+## You should have received a copy of the GNU General Public License
+## along with this program; if not, write to the Free Software
+## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+
diff --git a/src/board/gandof/Makefile.inc b/src/board/gandof/Makefile.inc
new file mode 100644
index 0000000..eacc1ab
--- /dev/null
+++ b/src/board/gandof/Makefile.inc
@@ -0,0 +1,18 @@
+##
+## Copyright 2015 Google Inc.
+##
+## This program is free software; you can redistribute it and/or modify
+## it under the terms of the GNU General Public License as published by
+## the Free Software Foundation; version 2 of the License.
+##
+## This program is distributed in the hope that it will be useful,
+## but WITHOUT ANY WARRANTY; without even the implied warranty of
+## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+## GNU General Public License for more details.
+##
+## You should have received a copy of the GNU General Public License
+## along with this program; if not, write to the Free Software
+## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+##
+
+depthcharge-y += board.c
diff --git a/src/board/gandof/board.c b/src/board/gandof/board.c
new file mode 100644
index 0000000..29e0ddf
--- /dev/null
+++ b/src/board/gandof/board.c
@@ -0,0 +1,69 @@
+/*
+ * Copyright 2015 Google Inc.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but without any warranty; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <pci.h>
+
+#include "base/init_funcs.h"
+#include "base/list.h"
+#include "drivers/ec/cros/lpc.h"
+#include "drivers/flash/flash.h"
+#include "drivers/flash/memmapped.h"
+#include "drivers/gpio/lynxpoint_lp.h"
+#include "drivers/gpio/sysinfo.h"
+#include "drivers/power/pch.h"
+#include "drivers/sound/hda_codec.h"
+#include "drivers/sound/sound.h"
+#include "drivers/storage/ahci.h"
+#include "drivers/storage/blockdev.h"
+#include "drivers/tpm/lpc.h"
+#include "drivers/tpm/tpm.h"
+#include "vboot/util/flag.h"
+
+static int board_setup(void)
+{
+ sysinfo_install_flags();
+
+ LpPchGpio *ec_in_rw = new_lp_pch_gpio_input(14);
+ flag_install(FLAG_ECINRW, &ec_in_rw->ops);
+
+ CrosEcLpcBus *cros_ec_lpc_bus = new_cros_ec_lpc_bus();
+ cros_ec_set_bus(&cros_ec_lpc_bus->ops);
+
+ flash_set_ops(&new_mem_mapped_flash(0xff800000, 0x800000)->ops);
+
+ HdaCodec *codec = new_hda_codec();
+ sound_set_ops(&codec->ops);
+
+ // The realtek codec doesn't report its beep_nid (NID 1)
+ set_hda_beep_nid_override(codec, 1);
+
+ AhciCtrlr *ahci = new_ahci_ctrlr(PCI_DEV(0, 31, 2));
+ list_insert_after(&ahci->ctrlr.list_node, &fixed_block_dev_controllers);
+
+ power_set_ops(&pch_power_ops);
+
+ tpm_set_ops(&new_lpc_tpm((void *)(uintptr_t)0xfed40000)->ops);
+
+ return 0;
+}
+
+INIT_FUNC(board_setup);
