| /* Copyright 2021 The ChromiumOS Authors |
| * Use of this source code is governed by a BSD-style license that can be |
| * found in the LICENSE file. |
| */ |
| |
| / { |
| aliases { |
| gpio-wp = &gpio_wp; |
| gpio-cbi-wp = &gpio_cbi_wp; |
| gpio-kbd-kso2 = &gpio_ec_kso_02_inv; |
| }; |
| |
| /* GPIOs shared by all boards */ |
| named-gpios { |
| compatible = "named-gpios"; |
| |
| ccd_mode_odl { |
| gpios = <&gpioc 6 GPIO_ODR_HIGH>; |
| }; |
| ec_gsc_packet_mode { |
| gpios = <&gpiob 1 GPIO_OUTPUT_LOW>; |
| enum-name = "GPIO_PACKET_MODE_EN"; |
| }; |
| gpio_mech_pwr_btn_odl: mech_pwr_btn_odl { |
| gpios = <&gpiod 2 GPIO_INPUT>; |
| enum-name = "GPIO_POWER_BUTTON_L"; |
| }; |
| gpio_slp_s3_l: slp_s3_l { |
| gpios = <&gpio6 1 GPIO_INPUT>; |
| enum-name = "GPIO_PCH_SLP_S3_L"; |
| alias = "GPIO_PCH_SLP_S0_L"; |
| }; |
| gpio_slp_s5_l: slp_s5_l { |
| gpios = <&gpio7 2 GPIO_INPUT>; |
| enum-name = "GPIO_PCH_SLP_S5_L"; |
| }; |
| gpio_pg_pwr_s5: pg_pwr_s5 { |
| gpios = <&gpioc 0 GPIO_INPUT>; |
| enum-name = "GPIO_S5_PGOOD"; |
| }; |
| gpio_s0_pgood: pg_pcore_s0_r_od { |
| gpios = <&gpiob 6 GPIO_INPUT>; |
| enum-name = "GPIO_S0_PGOOD"; |
| }; |
| gpio_acok_od: acok_od { |
| gpios = <&gpio0 0 GPIO_INPUT>; |
| enum-name = "GPIO_AC_PRESENT"; |
| }; |
| gpio_en_pwr_s5: en_pwr_s5 { |
| gpios = <&gpiob 7 GPIO_OUTPUT_LOW>; |
| enum-name = "GPIO_EN_PWR_A"; |
| }; |
| gpio_en_pwr_s0_r: en_pwr_s0_r { |
| gpios = <&gpiof 1 GPIO_OUTPUT_LOW>; |
| }; |
| gpio_en_pwr_pcore_s0_r: en_pwr_pcore_s0_r { |
| gpios = <&gpioe 1 GPIO_OUTPUT_LOW>; |
| }; |
| ec_sys_rst_l { |
| gpios = <&gpio7 6 GPIO_ODR_HIGH>; |
| enum-name = "GPIO_SYS_RESET_L"; |
| }; |
| gpio_ec_soc_rsmrst_l: ec_soc_rsmrst_l { |
| gpios = <&gpioc 5 GPIO_OUTPUT_LOW>; |
| enum-name = "GPIO_PCH_RSMRST_L"; |
| }; |
| gpio_ec_pch_wake_odl: ec_soc_wake_l { |
| gpios = <&gpio0 3 GPIO_OUTPUT_HIGH>; |
| }; |
| gpio_prochot_odl: prochot_odl { |
| gpios = <&gpiod 5 GPIO_ODR_HIGH>; |
| enum-name = "GPIO_CPU_PROCHOT"; |
| }; |
| soc_alert_ec_l { |
| gpios = <&gpioe 2 GPIO_INPUT>; |
| }; |
| gpio_usb_c0_tcpc_int_odl: usb_c0_tcpc_int_odl { |
| gpios = <&gpioe 0 (GPIO_INPUT | GPIO_ACTIVE_LOW)>; |
| enum-name = "GPIO_USB_C0_TCPC_INT_ODL"; |
| }; |
| gpio_usb_c1_tcpc_int_odl: usb_c1_tcpc_int_odl { |
| gpios = <&gpioc 7 (GPIO_INPUT | GPIO_ACTIVE_LOW)>; |
| enum-name = "GPIO_USB_C1_TCPC_INT_ODL"; |
| }; |
| gpio_usb_c0_ppc_int_odl: usb_c0_ppc_int_odl { |
| gpios = <&gpio7 5 (GPIO_INPUT | GPIO_ACTIVE_LOW)>; |
| enum-name = "GPIO_USB_C0_PPC_INT_ODL"; |
| }; |
| gpio_usb_c1_ppc_int_odl: usb_c1_ppc_int_odl { |
| gpios = <&gpiod 4 (GPIO_INPUT | GPIO_ACTIVE_LOW)>; |
| enum-name = "GPIO_USB_C1_PPC_INT_ODL"; |
| }; |
| gpio_usb_c0_bc12_int_odl: usb_c0_bc12_int_odl { |
| gpios = <&gpioa 4 GPIO_INPUT_PULL_UP>; |
| enum-name = "GPIO_USB_C0_BC12_INT_ODL"; |
| }; |
| gpio_usb_c1_bc12_int_odl: usb_c1_bc12_int_odl { |
| gpios = <&gpio9 6 GPIO_INPUT_PULL_UP>; |
| enum-name = "GPIO_USB_C1_BC12_INT_ODL"; |
| }; |
| gpio_usb_c0_tcpc_rst_l: usb_c0_tcpc_rst_l { |
| gpios = <&gpio3 4 (GPIO_OUTPUT_HIGH | GPIO_ACTIVE_LOW)>; |
| enum-name = "GPIO_USB_C0_TCPC_RST_L"; |
| }; |
| gpio_usb_c1_tcpc_rst_l: usb_c1_tcpc_rst_l { |
| gpios = <&gpio3 7 (GPIO_OUTPUT_HIGH | GPIO_ACTIVE_LOW)>; |
| enum-name = "GPIO_USB_C1_TCPC_RST_L"; |
| }; |
| usb_c0_hpd { |
| gpios = <&gpiof 5 GPIO_OUTPUT_LOW>; |
| enum-name = "GPIO_USB_C0_DP_HPD"; |
| }; |
| usb_c1_hpd { |
| gpios = <&gpiof 4 GPIO_OUTPUT_LOW>; |
| enum-name = "GPIO_USB_C1_DP_HPD"; |
| }; |
| gpio_lid_open: lid_open { |
| gpios = <&gpio0 2 GPIO_INPUT>; |
| enum-name = "GPIO_LID_OPEN"; |
| }; |
| gpio_ec_batt_pres_odl: ec_batt_pres_odl { |
| gpios = <&gpio9 4 GPIO_INPUT>; |
| enum-name = "GPIO_BATT_PRES_ODL"; |
| }; |
| gpio_ec_disable_disp_bl: ec_disable_disp_bl { |
| gpios = <&gpioa 6 GPIO_OUTPUT_HIGH>; |
| enum-name = "GPIO_ENABLE_BACKLIGHT_L"; |
| }; |
| gpio_usb_fault_odl: usb_fault_odl { |
| gpios = <&gpio5 0 (GPIO_ODR_HIGH | GPIO_VOLTAGE_1P8)>; |
| }; |
| gpio_en_pwr_s3: en_pwr_s3 { |
| gpios = <&gpio7 4 GPIO_OUTPUT_LOW>; |
| }; |
| gpio_pg_groupc_s0_od: pg_groupc_s0_od { |
| gpios = <&gpiof 0 GPIO_INPUT>; |
| }; |
| gpio_ec_i2c_usbc_pd_int: ec_i2c_usbc_pd_int { |
| gpios = <&gpioa 3 GPIO_INPUT>; |
| }; |
| gpio_soc_thermtrip_odl: soc_thermtrip_odl { |
| gpios = <&gpio9 5 GPIO_INPUT>; |
| }; |
| gpio_hub_rst: hub_rst { |
| gpios = <&gpio6 6 GPIO_OUTPUT_HIGH>; |
| }; |
| ec_soc_int_l { |
| gpios = <&gpioa 1 GPIO_OUTPUT_HIGH>; |
| enum-name = "GPIO_EC_INT_L"; |
| }; |
| gpio_ec_soc_pwr_good: ec_soc_pwr_good { |
| gpios = <&gpiod 3 GPIO_OUTPUT_LOW>; |
| }; |
| gpio_pcore_ocp_r_l: pcore_ocp_r_l { |
| gpios = <&gpioa 5 GPIO_INPUT>; |
| }; |
| gpio_usb_hub_fault_q_odl: usb_hub_fault_q_odl { |
| gpios = <&gpioe 5 GPIO_INPUT_PULL_UP>; |
| }; |
| gpio_pg_lpddr5_s3_od: pg_lpddr5_s3_od { |
| gpios = <&gpio7 3 GPIO_INPUT>; |
| }; |
| gpio_lid_accel_int_l: 3axis_int_l { |
| gpios = <&gpioa 2 GPIO_INPUT_PULL_UP>; |
| }; |
| gpio_ec_soc_pwr_btn_l: ec_soc_pwr_btn_l { |
| gpios = <&gpioa 7 GPIO_OUTPUT_HIGH>; |
| enum-name = "GPIO_PCH_PWRBTN_L"; |
| }; |
| gpio_volup_btn_odl: volup_btn_odl { |
| gpios = <&gpio6 7 GPIO_INPUT_PULL_UP>; |
| enum-name = "GPIO_VOLUME_UP_L"; |
| }; |
| gpio_voldn_btn_odl: voldn_btn_odl { |
| gpios = <&gpio7 0 GPIO_INPUT_PULL_UP>; |
| enum-name = "GPIO_VOLUME_DOWN_L"; |
| }; |
| ec_sc_rst { |
| gpios = <&gpiob 0 GPIO_OUTPUT_LOW>; |
| }; |
| gpio_cbi_wp: ec_cbi_wp { |
| gpios = <&gpio8 1 GPIO_OUTPUT_LOW>; |
| }; |
| gpio_wp: ec_wp_l { |
| gpios = <&gpiod 7 (GPIO_INPUT | GPIO_ACTIVE_LOW)>; |
| }; |
| gpio_pg_lpddr5_s0_od: pg_lpddr5_s0_od { |
| gpios = <&gpio6 0 GPIO_INPUT>; |
| }; |
| ec_espi_rst_l { |
| gpios = <&gpio5 4 GPIO_PULL_DOWN>; |
| }; |
| gpio_accel_gyro_int_l: accel_gyro_int_l { |
| gpios = <&gpioa 0 GPIO_INPUT>; |
| }; |
| /* unimplemented GPIOs */ |
| entering-rw { |
| enum-name = "GPIO_ENTERING_RW"; |
| }; |
| pch-sys-prwok { |
| enum-name = "GPIO_PCH_SYS_PWROK"; |
| }; |
| ec_i2c_usb_a0_c0_scl { |
| gpios = <&gpiob 5 GPIO_INPUT>; |
| }; |
| ec_i2c_usb_a0_c0_sda { |
| gpios = <&gpiob 4 GPIO_INPUT>; |
| }; |
| ec_i2c_usb_a1_c1_scl { |
| gpios = <&gpio9 0 GPIO_INPUT>; |
| }; |
| ec_i2c_usb_a1_c1_sda { |
| gpios = <&gpio8 7 GPIO_INPUT>; |
| }; |
| ec_i2c_batt_scl { |
| gpios = <&gpio9 2 (GPIO_INPUT | GPIO_VOLTAGE_1P8)>; |
| }; |
| ec_i2c_batt_sda { |
| gpios = <&gpio9 1 (GPIO_INPUT | GPIO_VOLTAGE_1P8)>; |
| }; |
| ec_i2c_usbc_mux_scl { |
| gpios = <&gpiod 1 GPIO_INPUT>; |
| }; |
| ec_i2c_usbc_mux_sda { |
| gpios = <&gpiod 0 GPIO_INPUT>; |
| }; |
| ec_i2c_power_scl { |
| gpios = <&gpiof 3 GPIO_INPUT>; |
| }; |
| ec_i2c_power_sda { |
| gpios = <&gpiof 2 GPIO_INPUT>; |
| }; |
| ec_i2c_cbi_scl { |
| gpios = <&gpio3 3 GPIO_INPUT>; |
| }; |
| ec_i2c_cbi_sda { |
| gpios = <&gpio3 6 GPIO_INPUT>; |
| }; |
| ec_i2c_sensor_scl { |
| gpios = <&gpioe 4 (GPIO_INPUT | GPIO_VOLTAGE_1P8)>; |
| }; |
| ec_i2c_sensor_sda { |
| gpios = <&gpioe 3 (GPIO_INPUT | GPIO_VOLTAGE_1P8)>; |
| }; |
| ec_i2c_soc_sic { |
| gpios = <&gpiob 3 (GPIO_INPUT | GPIO_VOLTAGE_1P8)>; |
| }; |
| ec_i2c_soc_sid { |
| gpios = <&gpiob 2 (GPIO_INPUT | GPIO_VOLTAGE_1P8)>; |
| }; |
| en_kb_bl { |
| gpios = <&gpio9 7 GPIO_OUTPUT_HIGH>; |
| enum-name = "GPIO_EN_KEYBOARD_BACKLIGHT"; |
| }; |
| gpio_ec_kso_02_inv: ec_kso_02_inv { |
| gpios = <&gpio1 7 (GPIO_OUTPUT | GPIO_ACTIVE_HIGH)>; |
| }; |
| tablet_mode_l { |
| gpios = <&gpioc 1 GPIO_INPUT>; |
| enum-name = "GPIO_TABLET_MODE_L"; |
| }; |
| ec_flprg2 { |
| gpios = <&gpio8 6 GPIO_INPUT_PULL_UP>; |
| }; |
| |
| usb_c0_tcpc_fastsw_ctl_en { |
| gpios = <&ioex_c0_port0 4 GPIO_OUTPUT_LOW>; |
| enum-name = "IOEX_USB_C0_TCPC_FASTSW_CTL_EN"; |
| }; |
| usb_c0_ppc_en_l { |
| gpios = <&ioex_c0_port1 0 GPIO_OUTPUT_LOW>; |
| }; |
| ioex_usb_c0_ilim_3a_en: usb_c0_ppc_ilim_3a_en { |
| gpios = <&ioex_c0_port1 1 GPIO_OUTPUT_LOW>; |
| enum-name = "IOEX_USB_C0_PPC_ILIM_3A_EN"; |
| }; |
| ioex_usb_c0_sbu_fault_odl: usb_c0_sbu_fault_odl { |
| gpios = <&ioex_c0_port1 2 GPIO_INPUT>; |
| }; |
| ioex_en_pp5000_usb_a0_vbus: en_pp5000_usb_a0_vbus { |
| gpios = <&ioex_c0_port1 5 GPIO_OUTPUT_LOW>; |
| }; |
| ioex_usb_a0_fault_odl: usb_a0_fault_odl { |
| gpios = <&ioex_c0_port1 6 GPIO_INPUT>; |
| }; |
| ioex_usb_c0_sbu_flip: usb_c0_sbu_flip { |
| gpios = <&ioex_c0_port1 7 GPIO_OUTPUT_LOW>; |
| enum-name = "IOEX_USB_C0_SBU_FLIP"; |
| }; |
| |
| usb_a1_retimer_en { |
| gpios = <&ioex_c1_port0 0 GPIO_OUTPUT_LOW>; |
| enum-name = "IOEX_USB_A1_RETIMER_EN"; |
| }; |
| usb_a1_retimer_rst { |
| gpios = <&ioex_c1_port0 1 GPIO_OUTPUT_LOW>; |
| }; |
| usb_c1_in_hpd { |
| gpios = <&ioex_c1_port0 3 GPIO_OUTPUT_LOW>; |
| enum-name = "IOEX_USB_C1_HPD_IN_DB"; |
| }; |
| usb_c1_tcpc_fastsw_ctl_en { |
| gpios = <&ioex_c1_port0 4 GPIO_OUTPUT_LOW>; |
| enum-name = "IOEX_USB_C1_TCPC_FASTSW_CTL_EN"; |
| }; |
| usb_c1_ppc_en_l { |
| gpios = <&ioex_c1_port1 0 GPIO_OUTPUT_LOW>; |
| }; |
| usb_c1_ppc_ilim_3a_en { |
| gpios = <&ioex_c1_port1 1 GPIO_OUTPUT_LOW>; |
| enum-name = "IOEX_USB_C1_PPC_ILIM_3A_EN"; |
| }; |
| ioex_usb_c1_sbu_fault_odl: usb_c1_sbu_fault_odl { |
| gpios = <&ioex_c1_port1 2 GPIO_INPUT>; |
| enum-name = "IOEX_USB_C1_FAULT_ODL"; |
| }; |
| ioex_en_pp5000_usb_a1_vbus: en_pp5000_usb_a1_vbus { |
| gpios = <&ioex_c1_port1 5 GPIO_OUTPUT_LOW>; |
| }; |
| ioex_usb_a1_fault_db_odl: usb_a1_fault_db_odl { |
| gpios = <&ioex_c1_port1 6 GPIO_INPUT>; |
| }; |
| ioex_usb_c1_sbu_flip: usb_c1_sbu_flip { |
| gpios = <&ioex_c1_port1 7 GPIO_OUTPUT_LOW>; |
| enum-name = "IOEX_USB_C1_SBU_FLIP"; |
| }; |
| |
| /* STB dumping GPIOs */ |
| gpio_ec_sfh_int_h: ec_sfh_int_h { |
| gpios = <&gpio9 3 GPIO_OUTPUT_LOW>; |
| }; |
| gpio_sfh_ec_int_h: sfh_ec_int_h { |
| gpios = <&gpio5 6 GPIO_INPUT>; |
| }; |
| }; |
| |
| usba-port-enable-list { |
| compatible = "cros-ec,usba-port-enable-pins"; |
| enable-pins = <&ioex_en_pp5000_usb_a0_vbus |
| &ioex_en_pp5000_usb_a1_vbus>; |
| }; |
| }; |
| |
| /* PSL input pads*/ |
| &psl_in1_gpd2 { |
| /* MECH_PWR_BTN_ODL */ |
| psl-in-mode = "edge"; |
| psl-in-pol = "low-falling"; |
| }; |
| |
| &psl_in2_gp00 { |
| /* ACOK_OD */ |
| psl-in-mode = "edge"; |
| psl-in-pol = "high-rising"; |
| }; |
| |
| &psl_in4_gp02 { |
| /* LID_OPEN */ |
| psl-in-mode = "edge"; |
| psl-in-pol = "high-rising"; |
| }; |
| |
| /* Power domain device controlled by PSL (Power Switch Logic) IO pads */ |
| &power_ctrl_psl { |
| status = "okay"; |
| pinctrl-names = "sleep"; |
| pinctrl-0 = <&psl_in1_gpd2 &psl_in2_gp00 &psl_in4_gp02>; |
| }; |
| |
| /* host interface */ |
| &espi0 { |
| status = "okay"; |
| pinctrl-0 = <&espi_lpc_gp46_47_51_52_53_54_55_57>; |
| pinctrl-names = "default"; |
| }; |
