minigbm: align first plane to 64 bytes
The chroma stride of Android YV12 buffers is required to be
aligned to 16 bytes (see <system/graphics.h>).
Additionally, the size of the ARM L1 cache line is 64-bytes
(see chrome-os-partner:45777).
Let's always align the first plane to 64 bytes. The chroma strides
will be aligned to 32 bytes in that case.
BUG=chromium:616275
TEST=
ImageReaderDecoderTest#testGoogH264ImageReader
passes on veyron_minnie-cheets.
Change-Id: I87a309ce0612bf8c5be8f8e47dad3da10d61a081
Reviewed-on: https://chromium-review.googlesource.com/441912
Commit-Ready: Gurchetan Singh <gurchetansingh@chromium.org>
Tested-by: Gurchetan Singh <gurchetansingh@chromium.org>
Reviewed-by: Stéphane Marchesin <marcheu@chromium.org>
Reviewed-by: Tomasz Figa <tfiga@chromium.org>
diff --git a/mediatek.c b/mediatek.c
index 7e85f63..a1db9db 100644
--- a/mediatek.c
+++ b/mediatek.c
@@ -49,7 +49,13 @@
int ret;
size_t plane;
struct drm_mtk_gem_create gem_create;
+ uint32_t bytes_per_pixel = drv_stride_from_format(format, 1, 0);
+ /*
+ * Since the ARM L1 cache line size is 64 bytes, align to that as a
+ * performance optimization.
+ */
+ width = ALIGN(width, DIV_ROUND_UP(64, bytes_per_pixel));
drv_bo_from_format(bo, width, height, format);
memset(&gem_create, 0, sizeof(gem_create));
diff --git a/rockchip.c b/rockchip.c
index 30b6822..140ec93 100644
--- a/rockchip.c
+++ b/rockchip.c
@@ -142,6 +142,13 @@
fprintf(stderr, "no usable modifier found\n");
return -1;
}
+
+ /*
+ * Since the ARM L1 cache line size is 64 bytes, align to that
+ * as a performance optimization.
+ */
+ uint32_t bytes_per_pixel = drv_stride_from_format(format, 1, 0);
+ width = ALIGN(width, DIV_ROUND_UP(64, bytes_per_pixel));
drv_bo_from_format(bo, width, height, format);
}
