Hana: Update memory supporting list
Update new DRAM: hynix_lpddr3_h9ccnnnbjtalar_nud, micron_mt52l256m32d1pf &
micron_mt52l512m32d2pf
BUG=chrome-os-partner:60341
TEST=Manually test
1. cros_workon-hana start mosys
2. emerge-hana mosys
3. cros deploy ${DUT_IP} mosys
3. mosys memory spd print all
Change-Id: I6c952a118fabfc12219a04f9ed554c60fd28ec6d
Signed-off-by: Milton Chiang <milton.chiang@mediatek.com>
Reviewed-on: https://chromium-review.googlesource.com/414693
Reviewed-by: Philip Chen <philipchen@chromium.org>
diff --git a/include/lib/nonspd.h b/include/lib/nonspd.h
index 2945558..0ae2200 100644
--- a/include/lib/nonspd.h
+++ b/include/lib/nonspd.h
@@ -110,11 +110,14 @@
extern const struct nonspd_mem_info hynix_ddr3l_h5tc4g63afr_pba;
extern const struct nonspd_mem_info hynix_ddr3l_h5tc4g63cfr_pba;
extern const struct nonspd_mem_info hynix_lpddr3_h9ccnnn8gtmlar_nud;
+extern const struct nonspd_mem_info hynix_lpddr3_h9ccnnnbjtalar_nud;
extern const struct nonspd_mem_info hynix_lpddr3_h9ccnnnbjtmlar_nud;
extern const struct nonspd_mem_info hynix_ddr3l_h5tc8g63amr_pba;
extern const struct nonspd_mem_info hynix_lpddr3_h9ccnnnbptblbr_nud;
extern const struct nonspd_mem_info hynix_lpddr3_h9ccnnnbltblar_nud;
extern const struct nonspd_mem_info micron_mt41k256m16ha;
+extern const struct nonspd_mem_info micron_mt52l256m32d1pf;
+extern const struct nonspd_mem_info micron_mt52l512m32d2pf;
extern const struct nonspd_mem_info nanya_ddr3l_nt5cc256m16dp_di;
extern const struct nonspd_mem_info samsung_k4b4g1646d;
extern const struct nonspd_mem_info samsung_k4b4g1646e;
diff --git a/lib/spd/nonspd_modules.c b/lib/spd/nonspd_modules.c
index 647be07..4b7036a 100644
--- a/lib/spd/nonspd_modules.c
+++ b/lib/spd/nonspd_modules.c
@@ -135,6 +135,23 @@
'A', 'R', '-', 'N', 'U', 'D',},
};
+const struct nonspd_mem_info hynix_lpddr3_h9ccnnnbjtalar_nud = {
+ .dram_type = SPD_DRAM_TYPE_LPDDR3,
+ .module_type.ddr3_type = DDR3_MODULE_TYPE_SO_DIMM,
+
+ .module_size_mbits = 16384,
+ .num_ranks = 2,
+ .device_width = 32,
+ .ddr_freq = { DDR_333, DDR_400, DDR_533, DDR_667, DDR_800 },
+
+ .module_mfg_id = { .msb = 0xad, .lsb = 0x80 },
+ .dram_mfg_id = { .msb = 0xad, .lsb = 0x80 },
+
+ .part_num =
+ { 'H', '9', 'C', 'C', 'N', 'N', 'N', 'B', 'J', 'T', 'A', 'L',
+ 'A', 'R', '-', 'N', 'U', 'D',},
+};
+
const struct nonspd_mem_info hynix_lpddr3_h9ccnnnbjtmlar_nud = {
.dram_type = SPD_DRAM_TYPE_LPDDR3,
.module_type.ddr3_type = DDR3_MODULE_TYPE_SO_DIMM,
@@ -252,6 +269,42 @@
'1', '6', 'H', 'A', '-', '1', '2', '5' },
};
+const struct nonspd_mem_info micron_mt52l256m32d1pf = {
+ .dram_type = SPD_DRAM_TYPE_DDR3,
+ .module_type.ddr3_type = DDR3_MODULE_TYPE_UNDEFINED,
+
+ .module_size_mbits = 8192,
+ .num_ranks = 1,
+ .device_width = 32,
+ .ddr_freq = { DDR_800, DDR_933, DDR_1067 },
+
+ .module_mfg_id = { .msb = 0x2c, .lsb = 0x00 },
+ .dram_mfg_id = { .msb = 0x2c, .lsb = 0x00 },
+
+ .serial_num = { 0, 0, 0, 0 },
+ .part_num = { 'M', 'T', '5', '2', 'L', '2', '5', '6', 'M',
+ '3', '2', 'D', '1', 'P', 'F', '-', '0', '9',
+ '3', 'W', 'T', ':', 'B' },
+};
+
+const struct nonspd_mem_info micron_mt52l512m32d2pf = {
+ .dram_type = SPD_DRAM_TYPE_DDR3,
+ .module_type.ddr3_type = DDR3_MODULE_TYPE_UNDEFINED,
+
+ .module_size_mbits = 16384,
+ .num_ranks = 2,
+ .device_width = 32,
+ .ddr_freq = { DDR_800, DDR_933, DDR_1067 },
+
+ .module_mfg_id = { .msb = 0x2c, .lsb = 0x00 },
+ .dram_mfg_id = { .msb = 0x2c, .lsb = 0x00 },
+
+ .serial_num = { 0, 0, 0, 0 },
+ .part_num = { 'M', 'T', '5', '2', 'L', '5', '1', '2', 'M',
+ '3', '2', 'D', '2', 'P', 'F', '-', '0', '9',
+ '3', 'W', 'T', ':', 'B' },
+};
+
const struct nonspd_mem_info nanya_ddr3l_nt5cc256m16dp_di = {
.dram_type = SPD_DRAM_TYPE_DDR3,
.module_type.ddr3_type = DDR3_MODULE_TYPE_UNDEFINED,
@@ -565,6 +618,7 @@
&hynix_ddr3l_h5tc4g63afr_pba,
&hynix_ddr3l_h5tc4g63cfr_pba,
&hynix_lpddr3_h9ccnnn8gtmlar_nud,
+ &hynix_lpddr3_h9ccnnnbjtalar_nud,
&hynix_lpddr3_h9ccnnnbjtmlar_nud,
&hynix_ddr3l_h5tc8g63amr_pba,
&hynix_lpddr3_h9ccnnnbptblbr_nud,
@@ -574,6 +628,8 @@
µn_lpddr4_mt53b256m32d1np,
µn_lpddr4_mt53b512m32d2np,
µn_mt41k256m16ha,
+ µn_mt52l256m32d1pf,
+ µn_mt52l512m32d2pf,
&nanya_ddr3l_nt5cc256m16dp_di,
&samsung_k4b4g1646d,
&samsung_k4b4g1646e,
diff --git a/platform/google/oak/memory.c b/platform/google/oak/memory.c
index 5d4eaf5..57dd1b4 100644
--- a/platform/google/oak/memory.c
+++ b/platform/google/oak/memory.c
@@ -41,10 +41,14 @@
enum oak_memory_config {
HYNIX_DDR3_H9CCNNN8GTMLAR_NUD_1G,
+ HYNIX_DDR3_H9CCNNNBJTALAR_NUD_2G,
HYNIX_DDR3_H9CCNNNBLTBLAR_NUD_2G,
- SAMSUNG_DDR3_K4E8E304EE_EGCE_1G,
- SAMSUNG_DDR3_K4E6E304EE_EGCE_2G,
+ MICRON_DDR3_MT52L256M32D1PF_107WTB_1G,
+ MICRON_DDR3_MT52L512M32D2PF_107WTB_2G,
SAMSUNG_DDR3_K4E6E304EB_EGCF_2G,
+ SAMSUNG_DDR3_K4E6E304EE_EGCE_2G,
+ SAMSUNG_DDR3_K4E8E304EE_EGCE_1G,
+ SAMSUNG_DDR3_K4E8E324EB_EGCF_1G,
MEM_UNKNOWN,
};
@@ -68,6 +72,15 @@
return HYNIX_DDR3_H9CCNNNBLTBLAR_NUD_2G;
case 4:
return SAMSUNG_DDR3_K4E6E304EB_EGCF_2G;
+ case 5:
+ return SAMSUNG_DDR3_K4E8E324EB_EGCF_1G;
+ case 6:
+ return MICRON_DDR3_MT52L512M32D2PF_107WTB_2G;
+ case 7:
+ return HYNIX_DDR3_H9CCNNNBJTALAR_NUD_2G;
+ case 8:
+ return MICRON_DDR3_MT52L256M32D1PF_107WTB_1G;
+
default:
lprintf(LOG_ERR, "Unable to determine memory configuration\n");
}
@@ -95,17 +108,29 @@
case HYNIX_DDR3_H9CCNNN8GTMLAR_NUD_1G:
*info = &hynix_lpddr3_h9ccnnn8gtmlar_nud;
break;
+ case HYNIX_DDR3_H9CCNNNBJTALAR_NUD_2G:
+ *info = &hynix_lpddr3_h9ccnnnbjtalar_nud;
+ break;
case HYNIX_DDR3_H9CCNNNBLTBLAR_NUD_2G:
*info = &hynix_lpddr3_h9ccnnnbltblar_nud;
break;
- case SAMSUNG_DDR3_K4E8E304EE_EGCE_1G:
- *info = &samsung_lpddr3_k4e8e304ee_egce;
+ case MICRON_DDR3_MT52L256M32D1PF_107WTB_1G:
+ *info = µn_mt52l256m32d1pf;
+ break;
+ case MICRON_DDR3_MT52L512M32D2PF_107WTB_2G:
+ *info = µn_mt52l512m32d2pf;
+ break;
+ case SAMSUNG_DDR3_K4E6E304EB_EGCF_2G:
+ *info = &samsung_lpddr3_k4e6e304eb_egcf;
break;
case SAMSUNG_DDR3_K4E6E304EE_EGCE_2G:
*info = &samsung_lpddr3_k4e6e304ee_egce;
break;
- case SAMSUNG_DDR3_K4E6E304EB_EGCF_2G:
- *info = &samsung_lpddr3_k4e6e304eb_egcf;
+ case SAMSUNG_DDR3_K4E8E304EE_EGCE_1G:
+ *info = &samsung_lpddr3_k4e8e304ee_egce;
+ break;
+ case SAMSUNG_DDR3_K4E8E324EB_EGCF_1G:
+ *info = &samsung_lpddr3_k4e8e324eb_egcf;
break;
default:
return -1;
